From 12326f5ff08904a4cb172c66f4aa2b511c631ab0 Mon Sep 17 00:00:00 2001 From: Michael Maitland Date: Thu, 30 Nov 2023 12:15:35 -0500 Subject: [PATCH 001/699] [RISCV][GISEL] lowerFormalArguments for variadic arguments (#73064) This is based of the varargs coe in RISCVTargetLowering::LowerFormalArguments. --- .../Target/RISCV/GISel/RISCVCallLowering.cpp | 90 ++++- .../Target/RISCV/GISel/RISCVCallLowering.h | 5 + .../irtranslator/lower-args-vararg.ll | 365 ++++++++++++++++++ 3 files changed, 452 insertions(+), 8 deletions(-) create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/lower-args-vararg.ll diff --git a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp index 3108ce983789..bd602635dd5f 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp @@ -423,18 +423,84 @@ bool RISCVCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, return true; } +static const MCPhysReg ArgGPRs[] = {RISCV::X10, RISCV::X11, RISCV::X12, + RISCV::X13, RISCV::X14, RISCV::X15, + RISCV::X16, RISCV::X17}; + +/// If there are varargs that were passed in a0-a7, the data in those registers +/// must be copied to the varargs save area on the stack. +void RISCVCallLowering::saveVarArgRegisters( + MachineIRBuilder &MIRBuilder, CallLowering::IncomingValueHandler &Handler, + IncomingValueAssigner &Assigner, CCState &CCInfo) const { + MachineFunction &MF = MIRBuilder.getMF(); + const RISCVSubtarget &Subtarget = MF.getSubtarget(); + unsigned XLenInBytes = Subtarget.getXLen() / 8; + ArrayRef ArgRegs(ArgGPRs); + unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); + + // Offset of the first variable argument from stack pointer, and size of + // the vararg save area. For now, the varargs save area is either zero or + // large enough to hold a0-a7. + int VaArgOffset, VarArgsSaveSize; + // If all registers are allocated, then all varargs must be passed on the + // stack and we don't need to save any argregs. + if (ArgRegs.size() == Idx) { + VaArgOffset = Assigner.StackSize; + VarArgsSaveSize = 0; + } else { + VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx); + VaArgOffset = -VarArgsSaveSize; + } + + // Record the frame index of the first variable argument which is a value + // necessary to G_VASTART. + MachineFrameInfo &MFI = MF.getFrameInfo(); + int FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true); + RISCVMachineFunctionInfo *RVFI = MF.getInfo(); + RVFI->setVarArgsFrameIndex(FI); + + // If saving an odd number of registers then create an extra stack slot to + // ensure that the frame pointer is 2*XLEN-aligned, which in turn ensures + // offsets to even-numbered registered remain 2*XLEN-aligned. + if (Idx % 2) { + MFI.CreateFixedObject(XLenInBytes, VaArgOffset - (int)XLenInBytes, true); + VarArgsSaveSize += XLenInBytes; + } + RVFI->setVarArgsSaveSize(VarArgsSaveSize); + + // Copy the integer registers that may have been used for passing varargs + // to the vararg save area. + const LLT p0 = LLT::pointer(MF.getDataLayout().getAllocaAddrSpace(), + Subtarget.getXLen()); + const LLT sXLen = LLT::scalar(Subtarget.getXLen()); + const MVT XLenVT = Subtarget.getXLenVT(); + MachineRegisterInfo &MRI = MF.getRegInfo(); + for (unsigned I = Idx; I < ArgRegs.size(); ++I, VaArgOffset += XLenInBytes) { + const Register VReg = MRI.createGenericVirtualRegister(sXLen); + Handler.assignValueToReg( + VReg, ArgRegs[I], + CCValAssign::getReg(I + MF.getFunction().getNumOperands(), XLenVT, + ArgRegs[I], XLenVT, CCValAssign::Full)); + FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true); + auto FIN = MIRBuilder.buildFrameIndex(p0, FI); + auto MPO = MachinePointerInfo::getFixedStack(MF, FI); + auto Store = + MIRBuilder.buildStore(VReg, FIN, MPO, inferAlignFromPtrInfo(MF, MPO)); + // This was taken from SelectionDAG, but we are not sure why it exists. + // It is being investigated in github.com/llvm/llvm-project/issues/73735. + Store->memoperands()[0]->setValue((Value *)nullptr); + } +} + bool RISCVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef> VRegs, FunctionLoweringInfo &FLI) const { - // Early exit if there are no arguments. - if (F.arg_empty()) + // Early exit if there are no arguments. varargs are not part of F.args() but + // must be lowered. + if (F.arg_empty() && !F.isVarArg()) return true; - // TODO: Support vararg functions. - if (F.isVarArg()) - return false; - const RISCVSubtarget &Subtarget = MIRBuilder.getMF().getSubtarget(); for (auto &Arg : F.args()) { @@ -467,8 +533,16 @@ bool RISCVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, /*IsRet=*/false); RISCVFormalArgHandler Handler(MIRBuilder, MF.getRegInfo()); - return determineAndHandleAssignments(Handler, Assigner, SplitArgInfos, - MIRBuilder, CC, F.isVarArg()); + SmallVector ArgLocs; + CCState CCInfo(CC, F.isVarArg(), MIRBuilder.getMF(), ArgLocs, F.getContext()); + if (!determineAssignments(Assigner, SplitArgInfos, CCInfo) || + !handleAssignments(Handler, SplitArgInfos, CCInfo, ArgLocs, MIRBuilder)) + return false; + + if (F.isVarArg()) + saveVarArgRegisters(MIRBuilder, Handler, Assigner, CCInfo); + + return true; } bool RISCVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, diff --git a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.h b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.h index d80a666f3489..abe704b4a645 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.h +++ b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.h @@ -42,6 +42,11 @@ public: private: bool lowerReturnVal(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef VRegs, MachineInstrBuilder &Ret) const; + + void saveVarArgRegisters(MachineIRBuilder &MIRBuilder, + CallLowering::IncomingValueHandler &Handler, + IncomingValueAssigner &Assigner, + CCState &CCInfo) const; }; } // end namespace llvm diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/lower-args-vararg.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/lower-args-vararg.ll new file mode 100644 index 000000000000..ecfccc48bb34 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/lower-args-vararg.ll @@ -0,0 +1,365 @@ +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=RV32 %s +; RUN: llc -mtriple=riscv64 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=RV64 %s + +define void @va1arg(ptr %a, ...) { + ; RV32-LABEL: name: va1arg + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6 + ; RV32-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32)) + ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; RV32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5 + ; RV32-NEXT: G_STORE [[COPY2]](s32), [[FRAME_INDEX1]](p0) :: (store (s32), align 8) + ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 + ; RV32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4 + ; RV32-NEXT: G_STORE [[COPY3]](s32), [[FRAME_INDEX2]](p0) :: (store (s32)) + ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14 + ; RV32-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3 + ; RV32-NEXT: G_STORE [[COPY4]](s32), [[FRAME_INDEX3]](p0) :: (store (s32), align 16) + ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15 + ; RV32-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 + ; RV32-NEXT: G_STORE [[COPY5]](s32), [[FRAME_INDEX4]](p0) :: (store (s32)) + ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16 + ; RV32-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; RV32-NEXT: G_STORE [[COPY6]](s32), [[FRAME_INDEX5]](p0) :: (store (s32), align 8) + ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17 + ; RV32-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; RV32-NEXT: G_STORE [[COPY7]](s32), [[FRAME_INDEX6]](p0) :: (store (s32)) + ; RV32-NEXT: PseudoRET + ; + ; RV64-LABEL: name: va1arg + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6 + ; RV64-NEXT: G_STORE [[COPY1]](s64), [[FRAME_INDEX]](p0) :: (store (s64)) + ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; RV64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5 + ; RV64-NEXT: G_STORE [[COPY2]](s64), [[FRAME_INDEX1]](p0) :: (store (s64), align 16) + ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13 + ; RV64-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4 + ; RV64-NEXT: G_STORE [[COPY3]](s64), [[FRAME_INDEX2]](p0) :: (store (s64)) + ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14 + ; RV64-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3 + ; RV64-NEXT: G_STORE [[COPY4]](s64), [[FRAME_INDEX3]](p0) :: (store (s64), align 16) + ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15 + ; RV64-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 + ; RV64-NEXT: G_STORE [[COPY5]](s64), [[FRAME_INDEX4]](p0) :: (store (s64)) + ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16 + ; RV64-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; RV64-NEXT: G_STORE [[COPY6]](s64), [[FRAME_INDEX5]](p0) :: (store (s64), align 16) + ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17 + ; RV64-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; RV64-NEXT: G_STORE [[COPY7]](s64), [[FRAME_INDEX6]](p0) :: (store (s64)) + ; RV64-NEXT: PseudoRET + ret void +} + +define void @va2arg(ptr %a, ptr %b, ...) { + ; RV32-LABEL: name: va2arg + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5 + ; RV32-NEXT: G_STORE [[COPY2]](s32), [[FRAME_INDEX]](p0) :: (store (s32), align 8) + ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 + ; RV32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4 + ; RV32-NEXT: G_STORE [[COPY3]](s32), [[FRAME_INDEX1]](p0) :: (store (s32)) + ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14 + ; RV32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3 + ; RV32-NEXT: G_STORE [[COPY4]](s32), [[FRAME_INDEX2]](p0) :: (store (s32), align 16) + ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15 + ; RV32-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 + ; RV32-NEXT: G_STORE [[COPY5]](s32), [[FRAME_INDEX3]](p0) :: (store (s32)) + ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16 + ; RV32-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; RV32-NEXT: G_STORE [[COPY6]](s32), [[FRAME_INDEX4]](p0) :: (store (s32), align 8) + ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17 + ; RV32-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; RV32-NEXT: G_STORE [[COPY7]](s32), [[FRAME_INDEX5]](p0) :: (store (s32)) + ; RV32-NEXT: PseudoRET + ; + ; RV64-LABEL: name: va2arg + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5 + ; RV64-NEXT: G_STORE [[COPY2]](s64), [[FRAME_INDEX]](p0) :: (store (s64), align 16) + ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13 + ; RV64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4 + ; RV64-NEXT: G_STORE [[COPY3]](s64), [[FRAME_INDEX1]](p0) :: (store (s64)) + ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14 + ; RV64-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3 + ; RV64-NEXT: G_STORE [[COPY4]](s64), [[FRAME_INDEX2]](p0) :: (store (s64), align 16) + ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15 + ; RV64-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 + ; RV64-NEXT: G_STORE [[COPY5]](s64), [[FRAME_INDEX3]](p0) :: (store (s64)) + ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16 + ; RV64-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; RV64-NEXT: G_STORE [[COPY6]](s64), [[FRAME_INDEX4]](p0) :: (store (s64), align 16) + ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17 + ; RV64-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; RV64-NEXT: G_STORE [[COPY7]](s64), [[FRAME_INDEX5]](p0) :: (store (s64)) + ; RV64-NEXT: PseudoRET + ret void +} + +define void @va3arg(ptr %a, ptr %b, ptr %c, ...) { + ; RV32-LABEL: name: va3arg + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x12 + ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 + ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4 + ; RV32-NEXT: G_STORE [[COPY3]](s32), [[FRAME_INDEX]](p0) :: (store (s32)) + ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14 + ; RV32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3 + ; RV32-NEXT: G_STORE [[COPY4]](s32), [[FRAME_INDEX1]](p0) :: (store (s32), align 16) + ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15 + ; RV32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 + ; RV32-NEXT: G_STORE [[COPY5]](s32), [[FRAME_INDEX2]](p0) :: (store (s32)) + ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16 + ; RV32-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; RV32-NEXT: G_STORE [[COPY6]](s32), [[FRAME_INDEX3]](p0) :: (store (s32), align 8) + ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17 + ; RV32-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; RV32-NEXT: G_STORE [[COPY7]](s32), [[FRAME_INDEX4]](p0) :: (store (s32)) + ; RV32-NEXT: PseudoRET + ; + ; RV64-LABEL: name: va3arg + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x12 + ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13 + ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4 + ; RV64-NEXT: G_STORE [[COPY3]](s64), [[FRAME_INDEX]](p0) :: (store (s64)) + ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14 + ; RV64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3 + ; RV64-NEXT: G_STORE [[COPY4]](s64), [[FRAME_INDEX1]](p0) :: (store (s64), align 16) + ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15 + ; RV64-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 + ; RV64-NEXT: G_STORE [[COPY5]](s64), [[FRAME_INDEX2]](p0) :: (store (s64)) + ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16 + ; RV64-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; RV64-NEXT: G_STORE [[COPY6]](s64), [[FRAME_INDEX3]](p0) :: (store (s64), align 16) + ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17 + ; RV64-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; RV64-NEXT: G_STORE [[COPY7]](s64), [[FRAME_INDEX4]](p0) :: (store (s64)) + ; RV64-NEXT: PseudoRET + ret void +} + +define void @va4arg(ptr %a, ptr %b, ptr %c, ptr %d, ...) { + ; RV32-LABEL: name: va4arg + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x12 + ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x13 + ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14 + ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3 + ; RV32-NEXT: G_STORE [[COPY4]](s32), [[FRAME_INDEX]](p0) :: (store (s32), align 16) + ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15 + ; RV32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 + ; RV32-NEXT: G_STORE [[COPY5]](s32), [[FRAME_INDEX1]](p0) :: (store (s32)) + ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16 + ; RV32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; RV32-NEXT: G_STORE [[COPY6]](s32), [[FRAME_INDEX2]](p0) :: (store (s32), align 8) + ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17 + ; RV32-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; RV32-NEXT: G_STORE [[COPY7]](s32), [[FRAME_INDEX3]](p0) :: (store (s32)) + ; RV32-NEXT: PseudoRET + ; + ; RV64-LABEL: name: va4arg + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x12 + ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x13 + ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14 + ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3 + ; RV64-NEXT: G_STORE [[COPY4]](s64), [[FRAME_INDEX]](p0) :: (store (s64), align 16) + ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15 + ; RV64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 + ; RV64-NEXT: G_STORE [[COPY5]](s64), [[FRAME_INDEX1]](p0) :: (store (s64)) + ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16 + ; RV64-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; RV64-NEXT: G_STORE [[COPY6]](s64), [[FRAME_INDEX2]](p0) :: (store (s64), align 16) + ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17 + ; RV64-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; RV64-NEXT: G_STORE [[COPY7]](s64), [[FRAME_INDEX3]](p0) :: (store (s64)) + ; RV64-NEXT: PseudoRET + ret void +} + +define void @va5arg(ptr %a, ptr %b, ptr %c, ptr %d, ptr %e, ...) { + ; RV32-LABEL: name: va5arg + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x12 + ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x13 + ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $x14 + ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15 + ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 + ; RV32-NEXT: G_STORE [[COPY5]](s32), [[FRAME_INDEX]](p0) :: (store (s32)) + ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16 + ; RV32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; RV32-NEXT: G_STORE [[COPY6]](s32), [[FRAME_INDEX1]](p0) :: (store (s32), align 8) + ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17 + ; RV32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; RV32-NEXT: G_STORE [[COPY7]](s32), [[FRAME_INDEX2]](p0) :: (store (s32)) + ; RV32-NEXT: PseudoRET + ; + ; RV64-LABEL: name: va5arg + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x12 + ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x13 + ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $x14 + ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15 + ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 + ; RV64-NEXT: G_STORE [[COPY5]](s64), [[FRAME_INDEX]](p0) :: (store (s64)) + ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16 + ; RV64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; RV64-NEXT: G_STORE [[COPY6]](s64), [[FRAME_INDEX1]](p0) :: (store (s64), align 16) + ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17 + ; RV64-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; RV64-NEXT: G_STORE [[COPY7]](s64), [[FRAME_INDEX2]](p0) :: (store (s64)) + ; RV64-NEXT: PseudoRET + ret void +} + +define void @va6arg(ptr %a, ptr %b, ptr %c, ptr %d, ptr %e, ptr %f, ...) { + ; RV32-LABEL: name: va6arg + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x12 + ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x13 + ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $x14 + ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(p0) = COPY $x15 + ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16 + ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; RV32-NEXT: G_STORE [[COPY6]](s32), [[FRAME_INDEX]](p0) :: (store (s32), align 8) + ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17 + ; RV32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; RV32-NEXT: G_STORE [[COPY7]](s32), [[FRAME_INDEX1]](p0) :: (store (s32)) + ; RV32-NEXT: PseudoRET + ; + ; RV64-LABEL: name: va6arg + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x12 + ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x13 + ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $x14 + ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(p0) = COPY $x15 + ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16 + ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; RV64-NEXT: G_STORE [[COPY6]](s64), [[FRAME_INDEX]](p0) :: (store (s64), align 16) + ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17 + ; RV64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; RV64-NEXT: G_STORE [[COPY7]](s64), [[FRAME_INDEX1]](p0) :: (store (s64)) + ; RV64-NEXT: PseudoRET + ret void +} + +define void @va7arg(ptr %a, ptr %b, ptr %c, ptr %d, ptr %e, ptr %f, ptr %g, ...) { + ; RV32-LABEL: name: va7arg + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x12 + ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x13 + ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $x14 + ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(p0) = COPY $x15 + ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(p0) = COPY $x16 + ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17 + ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; RV32-NEXT: G_STORE [[COPY7]](s32), [[FRAME_INDEX]](p0) :: (store (s32)) + ; RV32-NEXT: PseudoRET + ; + ; RV64-LABEL: name: va7arg + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x12 + ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x13 + ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $x14 + ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(p0) = COPY $x15 + ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(p0) = COPY $x16 + ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17 + ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; RV64-NEXT: G_STORE [[COPY7]](s64), [[FRAME_INDEX]](p0) :: (store (s64)) + ; RV64-NEXT: PseudoRET + ret void +} + +define void @va8arg(ptr %a, ptr %b, ptr %c, ptr %d, ptr %e, ptr %f, ptr %g, ptr %h, ...) { + ; RV32-LABEL: name: va8arg + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x12 + ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x13 + ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $x14 + ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(p0) = COPY $x15 + ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(p0) = COPY $x16 + ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(p0) = COPY $x17 + ; RV32-NEXT: PseudoRET + ; + ; RV64-LABEL: name: va8arg + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x12 + ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x13 + ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $x14 + ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(p0) = COPY $x15 + ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(p0) = COPY $x16 + ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(p0) = COPY $x17 + ; RV64-NEXT: PseudoRET + ret void +} -- GitLab From ea5b1ef016d020c37f903d6c7d4f623be975dab8 Mon Sep 17 00:00:00 2001 From: Vlad Serebrennikov Date: Thu, 30 Nov 2023 21:16:33 +0400 Subject: [PATCH 002/699] [clang][NFC] Refactor expected directives in C++ DRs 1-99 (#73879) This patch converts (almost) every expected directive in `test/CXX/drs/dr0xx.cpp` into either `@-1` form (when directive immediately follow the line diagnostic is pointing out to), or `@#` form (when directive is placed away from the line diagnostic is pointing out to). It also converts directive to match exactly one diagnostic, as opposed to matching multiple. Error messages are expanded to exactly match compiler output. `#if __cplusplus` guarding directives are replaced with respective prefixes (e.g. `since-cxx17`). All aforementioned changes serve a purpose of making it easier to reconstruct expected compiler output, which should also make it a bit easier to grasp the gist of those already non-trivial tests due to their nature of testing corner cases of the language. --- clang/test/CXX/drs/dr0xx.cpp | 788 ++++++++++++++++++++++------------- 1 file changed, 496 insertions(+), 292 deletions(-) diff --git a/clang/test/CXX/drs/dr0xx.cpp b/clang/test/CXX/drs/dr0xx.cpp index 0d60d55326c8..e79ce6daf265 100644 --- a/clang/test/CXX/drs/dr0xx.cpp +++ b/clang/test/CXX/drs/dr0xx.cpp @@ -1,9 +1,9 @@ -// RUN: %clang_cc1 -std=c++98 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -Wno-bind-to-temporary-copy -// RUN: %clang_cc1 -std=c++11 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -triple %itanium_abi_triple -// RUN: %clang_cc1 -std=c++14 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -triple %itanium_abi_triple -// RUN: %clang_cc1 -std=c++17 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -triple %itanium_abi_triple -// RUN: %clang_cc1 -std=c++20 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -triple %itanium_abi_triple -// RUN: %clang_cc1 -std=c++23 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -triple %itanium_abi_triple +// RUN: %clang_cc1 -std=c++98 %s -verify=expected,cxx98,cxx98-14 -fexceptions -fcxx-exceptions -pedantic-errors -Wno-bind-to-temporary-copy +// RUN: %clang_cc1 -std=c++11 %s -verify=expected,since-cxx11,cxx98-14,cxx11-14 -fexceptions -fcxx-exceptions -pedantic-errors -triple %itanium_abi_triple +// RUN: %clang_cc1 -std=c++14 %s -verify=expected,since-cxx11,cxx98-14,cxx11-14 -fexceptions -fcxx-exceptions -pedantic-errors -triple %itanium_abi_triple +// RUN: %clang_cc1 -std=c++17 %s -verify=expected,since-cxx11,since-cxx17 -fexceptions -fcxx-exceptions -pedantic-errors -triple %itanium_abi_triple +// RUN: %clang_cc1 -std=c++20 %s -verify=expected,since-cxx11,since-cxx17 -fexceptions -fcxx-exceptions -pedantic-errors -triple %itanium_abi_triple +// RUN: %clang_cc1 -std=c++23 %s -verify=expected,since-cxx11,since-cxx17 -fexceptions -fcxx-exceptions -pedantic-errors -triple %itanium_abi_triple namespace dr1 { // dr1: no namespace X { extern "C" void dr1_f(int a = 1); } @@ -26,9 +26,11 @@ namespace dr1 { // dr1: no namespace X { void z(int); } - void X::z(int = 1) {} // expected-note {{previous}} + void X::z(int = 1) {} // #dr1-z namespace X { - void z(int = 1); // expected-error {{redefinition of default argument}} + void z(int = 1); + // expected-error@-1 {{redefinition of default argument}} + // expected-note@#dr1-z {{previous definition is here}} } void i(int = 1); @@ -50,17 +52,21 @@ namespace dr1 { // dr1: no namespace dr3 { // dr3: yes template struct A {}; - template void f(T) { A a; } // expected-note {{implicit instantiation}} + template void f(T) { A a; } // #dr3-f-T template void f(int); - template<> struct A {}; // expected-error {{explicit specialization of 'dr3::A' after instantiation}} + template<> struct A {}; + // expected-error@-1 {{explicit specialization of 'dr3::A' after instantiation}} + // expected-note@#dr3-f-T {{implicit instantiation first required here}} } namespace dr4 { // dr4: yes extern "C" { static void dr4_f(int) {} static void dr4_f(float) {} - void dr4_g(int) {} // expected-note {{previous}} - void dr4_g(float) {} // expected-error {{conflicting types}} + void dr4_g(int) {} // #dr4-g-int + void dr4_g(float) {} + // expected-error@-1 {{conflicting types for 'dr4_g'}} + // expected-note@#dr4-g-int {{previous definition is here}} } } @@ -80,14 +86,21 @@ namespace dr5 { // dr5: 3.1 namespace dr7 { // dr7: 3.4 class A { public: ~A(); }; - class B : virtual private A {}; // expected-note 2 {{declared private here}} - class C : public B {} c; // expected-error 2 {{inherited virtual base class 'A' has private destructor}} \ - // expected-note {{implicit default constructor for 'dr7::C' first required here}} \ - // expected-note {{implicit destructor for 'dr7::C' first required here}} + class B : virtual private A {}; // #dr7-B + class C : public B {} c; // #dr7-C + // expected-error@#dr7-C {{inherited virtual base class 'A' has private destructor}} + // expected-note@#dr7-C {{in implicit default constructor for 'dr7::C' first required here}} + // expected-note@#dr7-B {{declared private here}} + + // expected-error@#dr7-C {{inherited virtual base class 'A' has private destructor}} + // expected-note@#dr7-C {{in implicit destructor for 'dr7::C' first required here}} + // expected-note@#dr7-B {{declared private here}} class VeryDerivedC : public B, virtual public A {} vdc; - class X { ~X(); }; // expected-note {{here}} - class Y : X { ~Y() {} }; // expected-error {{private destructor}} + class X { ~X(); }; // #dr7-X + class Y : X { ~Y() {} }; + // expected-error@-1 {{base class 'X' has private destructor}} + // expected-note@#dr7-X {{implicitly declared private here}} namespace PR16370 { // This regressed the first time DR7 was fixed. struct S1 { virtual ~S1(); }; @@ -117,13 +130,16 @@ namespace dr8 { // dr8: dup 45 namespace dr9 { // dr9: 2.8 struct B { protected: - int m; // expected-note {{here}} + int m; // #dr9-m friend int R1(); }; - struct N : protected B { // expected-note {{protected}} + struct N : protected B { // #dr9-N friend int R2(); } n; - int R1() { return n.m; } // expected-error {{protected member}} + int R1() { return n.m; } + // expected-error@-1 {{'m' is a protected member of 'dr9::B'}} + // expected-note@#dr9-N {{constrained by protected inheritance here}} + // expected-note@#dr9-m {{member is declared here}} int R2() { return n.m; } } @@ -142,7 +158,8 @@ namespace dr11 { // dr11: yes }; template struct B : T { using T::V; - V v; // expected-error {{unknown type name}} + V v; + // expected-error@-1 {{unknown type name 'V'}} }; struct X { typedef int U; }; A ax; @@ -190,27 +207,41 @@ namespace dr14 { // dr14: 3.4 extern "C" int dr14_f() { return c.k; } } - namespace X { typedef int T; typedef int U; } // expected-note {{candidate}} - namespace Y { typedef int T; typedef long U; } // expected-note {{candidate}} + namespace X { typedef int T; typedef int U; } // #dr14-X-U + namespace Y { typedef int T; typedef long U; } // #dr14-Y-U T t; // ok, same type both times - U u; // expected-error {{ambiguous}} + U u; + // expected-error@-1 {{reference to 'U' is ambiguous}} + // expected-note@#dr14-X-U {{candidate found by name lookup is 'dr14::X::U'}} + // expected-note@#dr14-Y-U {{candidate found by name lookup is 'dr14::Y::U'}} } namespace dr15 { // dr15: yes - template void f(int); // expected-note {{previous}} - template void f(int = 0); // expected-error {{default arguments cannot be added}} + template void f(int); // #dr15-f-decl-first + template void f(int = 0); + // expected-error@-1 {{default arguments cannot be added to a function template that has already been declared}} + // expected-note@#dr15-f-decl-first {{previous template declaration is here}} } namespace dr16 { // dr16: 2.8 - class A { // expected-note {{here}} - void f(); // expected-note {{here}} + class A { // #dr16-A + void f(); // #dr16-A-f-decl friend class C; }; - class B : A {}; // expected-note 3{{here}} + class B : A {}; // #dr16-B class C : B { void g() { - f(); // expected-error {{private member}} - A::f(); // expected-error {{private member}} expected-error {{private base}} + f(); + // expected-error@-1 {{'f' is a private member of 'dr16::A'}} + // expected-note@#dr16-B {{constrained by implicitly private inheritance here}} + // expected-note@#dr16-A-f-decl {{member is declared here}} + A::f(); // #dr16-A-f-call + // expected-error@#dr16-A-f-call {{'A' is a private member of 'dr16::A'}} + // expected-note@#dr16-B {{constrained by implicitly private inheritance here}} + // expected-note@#dr16-A {{member is declared here}} + + // expected-error@#dr16-A-f-call {{cannot cast 'dr16::C' to its private base class 'dr16::A'}} + // expected-note@#dr16-B {{implicitly declared private here}} } }; } @@ -232,13 +263,16 @@ namespace dr17 { // dr17: yes namespace dr19 { // dr19: 3.1 struct A { - int n; // expected-note {{here}} + int n; // #dr19-n }; - struct B : protected A { // expected-note {{here}} + struct B : protected A { // #dr19-B }; struct C : B {} c; struct D : B { - int get1() { return c.n; } // expected-error {{protected member}} + int get1() { return c.n; } + // expected-error@-1 {{'n' is a protected member of 'dr19::A'}} + // expected-note@#dr19-B {{constrained by protected inheritance here}} + // expected-note@#dr19-n {{member is declared here}} int get2() { return ((A&)c).n; } // ok, A is an accessible base of B from here }; } @@ -248,86 +282,94 @@ namespace dr20 { // dr20: 2.8 public: X(); private: - X(const X&); // expected-note {{here}} + X(const X&); // #dr20-X-ctor }; X &f(); - X x = f(); // expected-error {{private}} + X x = f(); + // expected-error@-1 {{calling a private constructor of class 'dr20::X'}} + // expected-note@#dr20-X-ctor {{declared private here}} } namespace dr21 { // dr21: 3.4 template struct A; struct X { - template friend struct A; // expected-error {{default template argument not permitted on a friend template}} - template friend struct B; // expected-error {{default template argument not permitted on a friend template}} + template friend struct A; + // expected-error@-1 {{default template argument not permitted on a friend template}} + template friend struct B; + // expected-error@-1 {{default template argument not permitted on a friend template}} }; } namespace dr22 { // dr22: sup 481 - template struct X; // expected-error {{unknown type name 'dr22_T'}} + template struct X; + // expected-error@-1 {{unknown type name 'dr22_T'}} typedef int T; template struct Y; } namespace dr23 { // dr23: yes - template void f(T, T); // expected-note {{candidate}} - template void f(T, int); // expected-note {{candidate}} - void g() { f(0, 0); } // expected-error {{ambiguous}} + template void f(T, T); // #dr23-f-T-T + template void f(T, int); // #dr23-f-T-int + void g() { f(0, 0); } + // expected-error@-1 {{call to 'f' is ambiguous}} + // expected-note@#dr23-f-T-T {{candidate function [with T = int]}} + // expected-note@#dr23-f-T-int {{candidate function [with T = int]}} } // dr24: na namespace dr25 { // dr25: yes struct A { - void f() throw(int); // expected-error 0-1{{ISO C++17 does not allow}} expected-note 0-1{{use 'noexcept}} + void f() throw(int); + // since-cxx17-error@-1 {{ISO C++17 does not allow dynamic exception specifications}} + // since-cxx17-note@-2 {{use 'noexcept(false)' instead}} }; - void (A::*f)() throw (int); // expected-error 0-1{{ISO C++17 does not allow}} expected-note 0-1{{use 'noexcept}} + void (A::*f)() throw (int); + // since-cxx17-error@-1 {{ISO C++17 does not allow dynamic exception specifications}} + // since-cxx17-note@-2 {{use 'noexcept(false)' instead}} void (A::*g)() throw () = f; -#if __cplusplus <= 201402L - // expected-error@-2 {{is not superset of source}} -#else - // expected-error@-4 {{different exception specifications}} -#endif + // cxx98-14-error@-1 {{target exception specification is not superset of source}} + // since-cxx17-error@-2 {{different exception specifications}} void (A::*g2)() throw () = 0; - void (A::*h)() throw (int, char) = f; // expected-error 0-1{{ISO C++17 does not allow}} expected-note 0-1{{use 'noexcept}} + void (A::*h)() throw (int, char) = f; + // since-cxx17-error@-1 {{ISO C++17 does not allow dynamic exception specifications}} + // since-cxx17-note@-2 {{use 'noexcept(false)' instead}} void (A::*i)() throw () = &A::f; -#if __cplusplus <= 201402L - // expected-error@-2 {{is not superset of source}} -#else - // expected-error@-4 {{different exception specifications}} -#endif + // cxx98-14-error@-1 {{target exception specification is not superset of source}} + // since-cxx17-error@-2 {{different exception specifications}} void (A::*i2)() throw () = 0; - void (A::*j)() throw (int, char) = &A::f; // expected-error 0-1{{ISO C++17 does not allow}} expected-note 0-1{{use 'noexcept}} + void (A::*j)() throw (int, char) = &A::f; + // since-cxx17-error@-1 {{ISO C++17 does not allow dynamic exception specifications}} + // since-cxx17-note@-2 {{use 'noexcept(false)' instead}} void x() { g2 = f; -#if __cplusplus <= 201402L - // expected-error@-2 {{is not superset of source}} -#else - // expected-error@-4 {{different exception specifications}} -#endif + // cxx98-14-error@-1 {{target exception specification is not superset of source}} + // since-cxx17-error@-2 {{different exception specifications}} h = f; i2 = &A::f; -#if __cplusplus <= 201402L - // expected-error@-2 {{is not superset of source}} -#else - // expected-error@-4 {{different exception specifications}} -#endif + // cxx98-14-error@-1 {{target exception specification is not superset of source}} + // since-cxx17-error@-2 {{different exception specifications}} j = &A::f; } } namespace dr26 { // dr26: yes - struct A { A(A, const A & = A()); }; // expected-error {{must pass its first argument by reference}} + struct A { A(A, const A & = A()); }; + // expected-error@-1 {{copy constructor must pass its first argument by reference}} struct B { B(); // FIXME: In C++98, we diagnose this twice. B(const B &, B = B()); -#if __cplusplus <= 201402L - // expected-error@-2 1+{{recursive evaluation of default argument}} expected-note@-2 1+{{used here}} -#endif + // cxx98-14-error@-1 {{recursive evaluation of default argument}} + // cxx98-14-note@-2 {{default argument used here}} + // cxx98-error@-3 {{recursive evaluation of default argument}} + // cxx98-note@-4 {{default argument used here}} }; struct C { static C &f(); - C(const C &, C = f()); // expected-error {{recursive evaluation of default argument}} expected-note {{used here}} + C(const C &, C = f()); + // expected-error@-1 {{recursive evaluation of default argument}} + // expected-note@-2 {{default argument used here}} }; } @@ -339,24 +381,34 @@ namespace dr27 { // dr27: yes // dr28: na lib namespace dr29 { // dr29: 3.4 - void dr29_f0(); // expected-note {{here}} + void dr29_f0(); // #dr29-f0 void g0() { void dr29_f0(); } extern "C++" void g0_cxx() { void dr29_f0(); } - extern "C" void g0_c() { void dr29_f0(); } // expected-error {{different language linkage}} + extern "C" void g0_c() { void dr29_f0(); } + // expected-error@-1 {{declaration of 'dr29_f0' has a different language linkage}} + // expected-note@#dr29-f0 {{previous declaration is here}} - extern "C" void dr29_f1(); // expected-note {{here}} + extern "C" void dr29_f1(); // #dr29-f1 void g1() { void dr29_f1(); } extern "C" void g1_c() { void dr29_f1(); } - extern "C++" void g1_cxx() { void dr29_f1(); } // expected-error {{different language linkage}} + extern "C++" void g1_cxx() { void dr29_f1(); } + // expected-error@-1 {{declaration of 'dr29_f1' has a different language linkage}} + // expected-note@#dr29-f1 {{previous declaration is here}} - void g2() { void dr29_f2(); } // expected-note {{here}} - extern "C" void dr29_f2(); // expected-error {{different language linkage}} + void g2() { void dr29_f2(); } // #dr29-f2 + extern "C" void dr29_f2(); + // expected-error@-1 {{declaration of 'dr29_f2' has a different language linkage}} + // expected-note@#dr29-f2 {{previous declaration is here}} - extern "C" void g3() { void dr29_f3(); } // expected-note {{here}} - extern "C++" void dr29_f3(); // expected-error {{different language linkage}} + extern "C" void g3() { void dr29_f3(); } // #dr29-f3 + extern "C++" void dr29_f3(); + // expected-error@-1 {{declaration of 'dr29_f3' has a different language linkage}} + // expected-note@#dr29-f3 {{previous declaration is here}} - extern "C++" void g4() { void dr29_f4(); } // expected-note {{here}} - extern "C" void dr29_f4(); // expected-error {{different language linkage}} + extern "C++" void g4() { void dr29_f4(); } // #dr29-f4 + extern "C" void dr29_f4(); + // expected-error@-1 {{declaration of 'dr29_f4' has a different language linkage}} + // expected-note@#dr29-f4 {{previous declaration is here}} extern "C" void g5(); extern "C++" void dr29_f5(); @@ -371,15 +423,19 @@ namespace dr29 { // dr29: 3.4 } extern "C" void g7(); - extern "C++" void dr29_f7(); // expected-note {{here}} + extern "C++" void dr29_f7(); // #dr29-f7 extern "C" void g7() { - void dr29_f7(); // expected-error {{different language linkage}} + void dr29_f7(); + // expected-error@-1 {{declaration of 'dr29_f7' has a different language linkage}} + // expected-note@#dr29-f7 {{previous declaration is here}} } extern "C++" void g8(); - extern "C" void dr29_f8(); // expected-note {{here}} + extern "C" void dr29_f8(); // #dr29-f8 extern "C++" void g8() { - void dr29_f8(); // expected-error {{different language linkage}} + void dr29_f8(); + // expected-error@-1 {{declaration of 'dr29_f8' has a different language linkage}} + // expected-note@#dr29-f8 {{previous declaration is here}} } } @@ -387,38 +443,42 @@ namespace dr30 { // dr30: sup 468 c++11 struct A { template static int f(); } a, *p = &a; + // FIXME: It's not clear whether DR468 applies to C++98 too. int x = A::template f<0>(); + // cxx98-error@-1 {{'template' keyword outside of a template}} int y = a.template f<0>(); + // cxx98-error@-1 {{'template' keyword outside of a template}} int z = p->template f<0>(); -#if __cplusplus < 201103L - // FIXME: It's not clear whether DR468 applies to C++98 too. - // expected-error@-5 {{'template' keyword outside of a template}} - // expected-error@-5 {{'template' keyword outside of a template}} - // expected-error@-5 {{'template' keyword outside of a template}} -#endif + // cxx98-error@-1 {{'template' keyword outside of a template}} } namespace dr31 { // dr31: 2.8 class X { private: - void operator delete(void*); // expected-note {{here}} + void operator delete(void*); // #dr31-delete }; // We would call X::operator delete if X() threw (even though it can't, // and even though we allocated the X using ::operator delete). - X *p = new X; // expected-error {{private}} + X *p = new X; + // expected-error@-1 {{'operator delete' is a private member of 'dr31::X'}} + // expected-note@#dr31-delete {{declared private here}} } // dr32: na namespace dr33 { // dr33: 9 - namespace X { struct S; void f(void (*)(S)); } // expected-note {{candidate}} - namespace Y { struct T; void f(void (*)(T)); } // expected-note {{candidate}} + namespace X { struct S; void f(void (*)(S)); } // #dr33-f-S + namespace Y { struct T; void f(void (*)(T)); } // #dr33-f-T void g(X::S); template Z g(Y::T); - void h() { f(&g); } // expected-error {{ambiguous}} + void h() { f(&g); } + // expected-error@-1 {{call to 'f' is ambiguous}} + // expected-note@#dr33-f-S {{candidate function}} + // expected-note@#dr33-f-T {{candidate function}} template void t(X::S); - template void u(X::S); // expected-error 0-1{{default template argument}} + template void u(X::S); + // expected-error@-1 0-1 {{default template arguments for a function template are a C++11 extension}} void templ() { f(t); f(u); } // Even though v cannot select the first overload, ADL considers it @@ -436,7 +496,8 @@ namespace dr33 { // dr33: 9 }; template void f(Y); - int use = X() + f; // expected-error {{invalid operands}} + int use = X() + f; + // expected-error@-1 {{invalid operands to binary expression ('X' and 'void (Y)')}} } namespace member { @@ -481,17 +542,25 @@ namespace example2 { struct D : virtual B, virtual C { - using B::i; // expected-note {{previous using declaration}} - using B::i; // expected-error {{redeclaration of using declaration}} - - using C::i; // expected-note {{previous using declaration}} - using C::i; // expected-error {{redeclaration of using declaration}} - - using B::j; // expected-note {{previous using declaration}} - using B::j; // expected-error {{redeclaration of using declaration}} - - using C::j; // expected-note {{previous using declaration}} - using C::j; // expected-error {{redeclaration of using declaration}} + using B::i; // #dr36-ex2-B-i-first + using B::i; + // expected-error@-1 {{redeclaration of using declaration}} + // expected-note@#dr36-ex2-B-i-first {{previous using declaration}} + + using C::i; // #dr36-ex2-C-i-first + using C::i; + // expected-error@-1 {{redeclaration of using declaration}} + // expected-note@#dr36-ex2-C-i-first {{previous using declaration}} + + using B::j; // #dr36-ex2-B-j-first + using B::j; + // expected-error@-1 {{redeclaration of using declaration}} + // expected-note@#dr36-ex2-B-j-first {{previous using declaration}} + + using C::j; // #dr36-ex2-C-j-first + using C::j; + // expected-error@-1 {{redeclaration of using declaration}} + // expected-note@#dr36-ex2-C-j-first {{previous using declaration}} }; } @@ -511,17 +580,25 @@ namespace example3 { template struct D : virtual B, virtual C { - using B::i; // expected-note {{previous using declaration}} - using B::i; // expected-error {{redeclaration of using declaration}} - - using C::i; // expected-note {{previous using declaration}} - using C::i; // expected-error {{redeclaration of using declaration}} - - using B::j; // expected-note {{previous using declaration}} - using B::j; // expected-error {{redeclaration of using declaration}} - - using C::j; // expected-note {{previous using declaration}} - using C::j; // expected-error {{redeclaration of using declaration}} + using B::i; // #dr36-ex3-B-i-first + using B::i; + // expected-error@-1 {{redeclaration of using declaration}} + // expected-note@#dr36-ex3-B-i-first {{previous using declaration}} + + using C::i; // #dr36-ex3-C-i-first + using C::i; + // expected-error@-1 {{redeclaration of using declaration}} + // expected-note@#dr36-ex3-C-i-first {{previous using declaration}} + + using B::j; // #dr36-ex3-B-j-first + using B::j; + // expected-error@-1 {{redeclaration of using declaration}} + // expected-note@#dr36-ex3-B-j-first {{previous using declaration}} + + using C::j; // #dr36-ex3-C-j-first + using C::j; + // expected-error@-1 {{redeclaration of using declaration}} + // expected-note@#dr36-ex3-C-j-first {{previous using declaration}} }; } namespace example4 { @@ -532,8 +609,10 @@ namespace example4 { template struct G : E { - using E::k; // expected-note {{previous using declaration}} - using E::k; // expected-error {{redeclaration of using declaration}} + using E::k; // #dr36-E-k-first + using E::k; + // expected-error@-1 {{redeclaration of using declaration}} + // expected-note@#dr36-E-k-first {{previous using declaration}} }; } } @@ -558,24 +637,35 @@ namespace dr39 { // dr39: no namespace example2 { struct A { - int &x(int); // expected-note {{found}} - static int &y(int); // expected-note {{found}} + int &x(int); // #dr39-A-x-decl + static int &y(int); // #dr39-A-y-decl }; struct V { int &z(int); }; struct B : A, virtual V { - using A::x; // expected-note {{found}} + using A::x; // #dr39-using-A-x float &x(float); - using A::y; // expected-note {{found}} + using A::y; // #dr39-using-A-y static float &y(float); using V::z; float &z(float); }; - struct C : A, B, virtual V {} c; // expected-warning {{direct base 'A' is inaccessible due to ambiguity:\n struct dr39::example2::C -> A\n struct dr39::example2::C -> B -> A}} - int &x = c.x(0); // expected-error {{found in multiple base classes}} + struct C : A, B, virtual V {} c; + /* expected-warning@-1 + {{direct base 'A' is inaccessible due to ambiguity: + struct dr39::example2::C -> A + struct dr39::example2::C -> B -> A}} */ + int &x = c.x(0); + // expected-error@-1 {{member 'x' found in multiple base classes of different types}} + // expected-note@#dr39-A-x-decl {{member found by ambiguous name lookup}} + // expected-note@#dr39-using-A-x {{member found by ambiguous name lookup}} + // FIXME: This is valid, because we find the same static data member either way. - int &y = c.y(0); // expected-error {{found in multiple base classes}} + int &y = c.y(0); + // expected-error@-1 {{member 'y' found in multiple base classes of different types}} + // expected-note@#dr39-A-y-decl {{member found by ambiguous name lookup}} + // expected-note@#dr39-using-A-y {{member found by ambiguous name lookup}} int &z = c.z(0); } @@ -588,21 +678,38 @@ namespace dr39 { // dr39: no } namespace example4 { - struct A { int n; }; // expected-note {{found}} + struct A { int n; }; // #dr39-ex4-A-n struct B : A {}; struct C : A {}; - struct D : B, C { int f() { return n; } }; // expected-error {{found in multiple base-class}} + struct D : B, C { int f() { return n; } }; + /* expected-error@-1 + {{non-static member 'n' found in multiple base-class subobjects of type 'A': + struct dr39::example4::D -> B -> A + struct dr39::example4::D -> C -> A}} */ + // expected-note@#dr39-ex4-A-n {{member found by ambiguous name lookup}} } namespace PR5916 { // FIXME: This is valid. - struct A { int n; }; // expected-note +{{found}} + struct A { int n; }; // #dr39-A-n struct B : A {}; struct C : A {}; struct D : B, C {}; - int k = sizeof(D::n); // expected-error {{found in multiple base}} expected-error {{unknown type name}} + int k = sizeof(D::n); // #dr39-sizeof + /* expected-error@#dr39-sizeof + {{non-static member 'n' found in multiple base-class subobjects of type 'A': + struct dr39::PR5916::D -> B -> A + struct dr39::PR5916::D -> C -> A}} */ + // expected-note@#dr39-A-n {{member found by ambiguous name lookup}} + + // expected-error@#dr39-sizeof {{unknown type name}} #if __cplusplus >= 201103L - decltype(D::n) n; // expected-error {{found in multiple base}} + decltype(D::n) n; + /* expected-error@-1 + {{non-static member 'n' found in multiple base-class subobjects of type 'A': + struct dr39::PR5916::D -> B -> A + struct dr39::PR5916::D -> C -> A}} */ + // expected-note@#dr39-A-n {{member found by ambiguous name lookup}} #endif } } @@ -637,15 +744,19 @@ namespace dr45 { // dr45: yes namespace dr46 { // dr46: yes template struct A { template struct B {}; }; - template template struct A::B; // expected-error {{expected unqualified-id}} + template template struct A::B; + // expected-error@-1 {{expected unqualified-id}} } namespace dr47 { // dr47: sup 329 template struct A { - friend void f() { T t; } // expected-error {{redefinition}} expected-note {{previous}} + friend void f() { T t; } // #dr47-f + // expected-error@-1 {{redefinition of 'f'}} + // expected-note@#dr47-b {{in instantiation of template class 'dr47::A' requested here}} + // expected-note@#dr47-f {{previous definition is here}} }; A a; - A b; // expected-note {{instantiation of}} + A b; // #dr47-b void f(); void g() { f(); } @@ -668,39 +779,44 @@ namespace dr48 { // dr48: yes } namespace dr49 { // dr49: 2.8 - template struct A {}; // expected-note 0-2{{here}} + template struct A {}; // #dr49-A int k; #if __has_feature(cxx_constexpr) constexpr #endif - int *const p = &k; // expected-note 0-2{{here}} + int *const p = &k; // #dr49-p A<&k> a; - A

b; -#if __cplusplus <= 201402L - // expected-error@-2 {{must have its address taken}} -#endif -#if __cplusplus < 201103L - // expected-error@-5 {{internal linkage}} -#endif - int *q = &k; - A c; -#if __cplusplus < 201103L - // expected-error@-2 {{must have its address taken}} -#else - // expected-error@-4 {{constant expression}} - // expected-note@-5 {{read of non-constexpr}} - // expected-note@-7 {{declared here}} -#endif + A

b; // #dr49-b + // cxx98-error@#dr49-b {{non-type template argument referring to object 'p' with internal linkage is a C++11 extension}} + // cxx98-note@#dr49-p {{non-type template argument refers to object here}} + + // cxx98-14-error@#dr49-b {{non-type template argument for template parameter of pointer type 'int *' must have its address taken}} + // cxx98-14-note@#dr49-A {{template parameter is declared here}} + int *q = &k; // #dr49-q + A c; // #dr49-c + // cxx98-error@#dr49-c {{non-type template argument for template parameter of pointer type 'int *' must have its address taken}} + // cxx98-note@#dr49-A {{template parameter is declared here}} + + // cxx11-14-error@#dr49-c {{non-type template argument of type 'int *' is not a constant expression}} + // cxx11-14-note@#dr49-c {{read of non-constexpr variable 'q' is not allowed in a constant expression}} + // cxx11-14-note@#dr49-q {{declared here}} + // cxx11-14-note@#dr49-A {{template parameter is declared here}} + + // since-cxx17-error@#dr49-c {{non-type template argument is not a constant expression}} + // since-cxx17-note@#dr49-c {{read of non-constexpr variable 'q' is not allowed in a constant expression}} + // since-cxx17-note@#dr49-q {{declared here}} } namespace dr50 { // dr50: yes - struct X; // expected-note {{forward}} + struct X; // #dr50-X extern X *p; X *q = (X*)p; X *r = static_cast(p); X *s = const_cast(p); X *t = reinterpret_cast(p); - X *u = dynamic_cast(p); // expected-error {{incomplete}} + X *u = dynamic_cast(p); + // expected-error@-1 {{'dr50::X' is an incomplete type}} + // expected-note@#dr50-X {{forward declaration of 'dr50::X'}} } namespace dr51 { // dr51: 2.8 @@ -714,11 +830,16 @@ namespace dr51 { // dr51: 2.8 } namespace dr52 { // dr52: 2.8 - struct A { int n; }; // expected-note {{here}} - struct B : private A {} b; // expected-note 2{{private}} + struct A { int n; }; // #dr52-A + struct B : private A {} b; // #dr52-B + int k = b.A::n; // #dr52-k // FIXME: This first diagnostic is very strangely worded, and seems to be bogus. - int k = b.A::n; // expected-error {{'A' is a private member of 'dr52::A'}} - // expected-error@-1 {{cannot cast 'struct B' to its private base}} + // expected-error@#dr52-k {{'A' is a private member of 'dr52::A'}} + // expected-note@#dr52-B {{constrained by private inheritance here}} + // expected-note@#dr52-A {{member is declared here}} + + // expected-error@#dr52-k {{cannot cast 'struct B' to its private base class 'dr52::A'}} + // expected-note@#dr52-B {{declared private here}} } namespace dr53 { // dr53: yes @@ -729,21 +850,37 @@ namespace dr53 { // dr53: yes namespace dr54 { // dr54: 2.8 struct A { int a; } a; struct V { int v; } v; - struct B : private A, virtual V { int b; } b; // expected-note 6{{private here}} - - A &sab = static_cast(b); // expected-error {{private base}} - A *spab = static_cast(&b); // expected-error {{private base}} - int A::*smab = static_cast(&B::b); // expected-error {{private base}} - B &sba = static_cast(a); // expected-error {{private base}} - B *spba = static_cast(&a); // expected-error {{private base}} - int B::*smba = static_cast(&A::a); // expected-error {{private base}} + struct B : private A, virtual V { int b; } b; // #dr54-B + + A &sab = static_cast(b); + // expected-error@-1 {{cannot cast 'struct B' to its private base class 'A'}} + // expected-note@#dr54-B {{declared private here}} + A *spab = static_cast(&b); + // expected-error@-1 {{cannot cast 'struct B' to its private base class 'A'}} + // expected-note@#dr54-B {{declared private here}} + int A::*smab = static_cast(&B::b); + // expected-error@-1 {{cannot cast 'dr54::B' to its private base class 'dr54::A'}} + // expected-note@#dr54-B {{declared private here}} + B &sba = static_cast(a); + // expected-error@-1 {{cannot cast private base class 'dr54::A' to 'dr54::B'}} + // expected-note@#dr54-B {{declared private here}} + B *spba = static_cast(&a); + // expected-error@-1 {{cannot cast private base class 'dr54::A' to 'dr54::B'}} + // expected-note@#dr54-B {{declared private here}} + int B::*smba = static_cast(&A::a); + // expected-error@-1 {{cannot cast private base class 'dr54::A' to 'dr54::B'}} + // expected-note@#dr54-B {{declared private here}} V &svb = static_cast(b); V *spvb = static_cast(&b); - int V::*smvb = static_cast(&B::b); // expected-error {{virtual base}} - B &sbv = static_cast(v); // expected-error {{virtual base}} - B *spbv = static_cast(&v); // expected-error {{virtual base}} - int B::*smbv = static_cast(&V::v); // expected-error {{virtual base}} + int V::*smvb = static_cast(&B::b); + // expected-error@-1 {{conversion from pointer to member of class 'dr54::B' to pointer to member of class 'dr54::V' via virtual base 'dr54::V' is not allowed}} + B &sbv = static_cast(v); + // expected-error@-1 {{cannot cast 'struct V' to 'B &' via virtual base 'dr54::V'}} + B *spbv = static_cast(&v); + // expected-error@-1 {{cannot cast 'dr54::V *' to 'B *' via virtual base 'dr54::V'}} + int B::*smbv = static_cast(&V::v); + // expected-error@-1 {{conversion from pointer to member of class 'dr54::V' to pointer to member of class 'dr54::B' via virtual base 'dr54::V' is not allowed}} A &cab = (A&)(b); A *cpab = (A*)(&b); @@ -754,10 +891,14 @@ namespace dr54 { // dr54: 2.8 V &cvb = (V&)(b); V *cpvb = (V*)(&b); - int V::*cmvb = (int V::*)(&B::b); // expected-error {{virtual base}} - B &cbv = (B&)(v); // expected-error {{virtual base}} - B *cpbv = (B*)(&v); // expected-error {{virtual base}} - int B::*cmbv = (int B::*)(&V::v); // expected-error {{virtual base}} + int V::*cmvb = (int V::*)(&B::b); + // expected-error@-1 {{conversion from pointer to member of class 'dr54::B' to pointer to member of class 'dr54::V' via virtual base 'dr54::V' is not allowed}} + B &cbv = (B&)(v); + // expected-error@-1 {{cannot cast 'struct V' to 'B &' via virtual base 'dr54::V'}} + B *cpbv = (B*)(&v); + // expected-error@-1 {{cannot cast 'dr54::V *' to 'B *' via virtual base 'dr54::V'}} + int B::*cmbv = (int B::*)(&V::v); + // expected-error@-1 {{conversion from pointer to member of class 'dr54::V' to pointer to member of class 'dr54::B' via virtual base 'dr54::V' is not allowed}} } namespace dr55 { // dr55: yes @@ -767,13 +908,17 @@ namespace dr55 { // dr55: yes namespace dr56 { // dr56: yes struct A { - typedef int T; // expected-note {{previous}} - typedef int T; // expected-error {{redefinition}} + typedef int T; // #dr56-typedef-int-T-first + typedef int T; + // expected-error@-1 {{redefinition of 'T'}} + // expected-note@#dr56-typedef-int-T-first {{previous definition is here}} }; struct B { struct X; - typedef X X; // expected-note {{previous}} - typedef X X; // expected-error {{redefinition}} + typedef X X; // #dr56-typedef-X-X-first + typedef X X; + // expected-error@-1 {{redefinition of 'X'}} + // expected-note@#dr56-typedef-X-X-first {{previous definition is here}} }; } @@ -792,32 +937,50 @@ namespace dr59 { // dr59: yes #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wdeprecated-volatile" template struct convert_to { operator T() const; }; - struct A {}; // expected-note 5+{{candidate}} - struct B : A {}; // expected-note 0+{{candidate}} + struct A {}; // #dr59-A + struct B : A {}; // #dr59-B A a1 = convert_to(); A a2 = convert_to(); A a3 = convert_to(); A a4 = convert_to(); -#if __cplusplus <= 201402L - // expected-error@-2 {{no viable}} -#endif - A a5 = convert_to(); // expected-error {{no viable}} + // cxx98-14-error@-1 {{no viable constructor copying variable of type 'const volatile dr59::A'}} + // cxx98-14-note@#dr59-A {{candidate constructor (the implicit copy constructor) not viable: 1st argument ('const volatile dr59::A') would lose volatile qualifier}} + // cxx11-14-note@#dr59-A {{candidate constructor (the implicit move constructor) not viable: 1st argument ('const volatile dr59::A') would lose const and volatile qualifiers}} + // cxx98-14-note@#dr59-A {{candidate constructor (the implicit default constructor) not viable: requires 0 arguments, but 1 was provided}} + A a5 = convert_to(); + // expected-error@-1 {{no viable constructor copying variable of type 'const volatile dr59::A'}} + // expected-note@#dr59-A {{candidate constructor (the implicit copy constructor) not viable: 1st argument ('const volatile dr59::A') would lose volatile qualifier}} + // since-cxx11-note@#dr59-A {{candidate constructor (the implicit move constructor) not viable: 1st argument ('const volatile dr59::A') would lose const and volatile qualifiers}} + // expected-note@#dr59-A {{candidate constructor (the implicit default constructor) not viable: requires 0 arguments, but 1 was provided}} B b1 = convert_to(); B b2 = convert_to(); B b3 = convert_to(); B b4 = convert_to(); -#if __cplusplus <= 201402L - // expected-error@-2 {{no viable}} -#endif - B b5 = convert_to(); // expected-error {{no viable}} + // cxx98-14-error@-1 {{no viable constructor copying variable of type 'const volatile dr59::B'}} + // cxx98-14-note@#dr59-B {{candidate constructor (the implicit copy constructor) not viable: 1st argument ('const volatile dr59::B') would lose volatile qualifier}} + // cxx11-14-note@#dr59-B {{candidate constructor (the implicit move constructor) not viable: 1st argument ('const volatile dr59::B') would lose const and volatile qualifiers}} + // cxx98-14-note@#dr59-B {{candidate constructor (the implicit default constructor) not viable: requires 0 arguments, but 1 was provided}} + B b5 = convert_to(); + // expected-error@-1 {{no viable constructor copying variable of type 'const volatile dr59::B'}} + // expected-note@#dr59-B {{candidate constructor (the implicit copy constructor) not viable: 1st argument ('const volatile dr59::B') would lose volatile qualifier}} + // since-cxx11-note@#dr59-B {{candidate constructor (the implicit move constructor) not viable: 1st argument ('const volatile dr59::B') would lose const and volatile qualifiers}} + // expected-note@#dr59-B {{candidate constructor (the implicit default constructor) not viable: requires 0 arguments, but 1 was provided}} A c1 = convert_to(); A c2 = convert_to(); A c3 = convert_to(); - A c4 = convert_to(); // expected-error {{no viable}} - A c5 = convert_to(); // expected-error {{no viable}} + A c4 = convert_to(); + // expected-error@-1 {{no viable constructor copying variable of type 'const volatile dr59::B'}} + // expected-note@#dr59-A {{candidate constructor (the implicit copy constructor) not viable: no known conversion from 'const volatile dr59::B' to 'const A &' for 1st argument}} + // since-cxx11-note@#dr59-A {{candidate constructor (the implicit move constructor) not viable: no known conversion from 'const volatile dr59::B' to 'A &&' for 1st argument}} + // expected-note@#dr59-A {{candidate constructor (the implicit default constructor) not viable: requires 0 arguments, but 1 was provided}} + A c5 = convert_to(); + // expected-error@-1 {{no viable constructor copying variable of type 'const volatile dr59::B'}} + // expected-note@#dr59-A {{candidate constructor (the implicit copy constructor) not viable: no known conversion from 'const volatile dr59::B' to 'const A &' for 1st argument}} + // since-cxx11-note@#dr59-A {{candidate constructor (the implicit move constructor) not viable: no known conversion from 'const volatile dr59::B' to 'A &&' for 1st argument}} + // expected-note@#dr59-A {{candidate constructor (the implicit default constructor) not viable: requires 0 arguments, but 1 was provided}} int n1 = convert_to(); int n2 = convert_to(); @@ -845,8 +1008,10 @@ namespace dr61 { // dr61: 3.4 // This is (presumably) valid, because x.f does not refer to an overloaded // function name. void (*p)() = &x.f; - void (*q)() = &y.f; // expected-error {{cannot create a non-constant pointer to member function}} - void (*r)() = y.f; // expected-error {{cannot create a non-constant pointer to member function}} + void (*q)() = &y.f; + // expected-error@-1 {{cannot create a non-constant pointer to member function}} + void (*r)() = y.f; + // expected-error@-1 {{cannot create a non-constant pointer to member function}} } namespace dr62 { // dr62: 2.9 @@ -860,10 +1025,7 @@ namespace dr62 { // dr62: 2.9 X x1; A a = get(); - typedef struct { } *NoNameForLinkagePtr; -#if __cplusplus < 201103L - // expected-note@-2 5{{here}} -#endif + typedef struct { } *NoNameForLinkagePtr; // #dr62-unnamed NoNameForLinkagePtr noNameForLinkagePtr; struct Danger { @@ -871,36 +1033,37 @@ namespace dr62 { // dr62: 2.9 }; X x2; + // cxx98-error@-1 {{template argument uses unnamed type}} + // cxx98-note@#dr62-unnamed {{unnamed type used in template argument was declared here}} X x3; + // cxx98-error@-1 {{template argument uses unnamed type}} + // cxx98-note@#dr62-unnamed {{unnamed type used in template argument was declared here}} NoNameForLinkagePtr p1 = get(); + // cxx98-error@-1 {{template argument uses unnamed type}} + // cxx98-note@#dr62-unnamed {{unnamed type used in template argument was declared here}} NoNameForLinkagePtr p2 = get(); + // cxx98-error@-1 {{template argument uses unnamed type}} + // cxx98-note@#dr62-unnamed {{unnamed type used in template argument was declared here}} int n1 = take(noNameForLinkagePtr); -#if __cplusplus < 201103L - // expected-error@-6 {{uses unnamed type}} - // expected-error@-6 {{uses unnamed type}} - // expected-error@-6 {{uses unnamed type}} - // expected-error@-6 {{uses unnamed type}} - // expected-error@-6 {{uses unnamed type}} -#endif + // cxx98-error@-1 {{template argument uses unnamed type}} + // cxx98-note@#dr62-unnamed {{unnamed type used in template argument was declared here}} X x4; void f() { struct NoLinkage {}; X a; + // cxx98-error@-1 {{template argument uses local type }} X b; + // cxx98-error@-1 {{template argument uses local type }} get(); + // cxx98-error@-1 {{template argument uses local type }} get(); + // cxx98-error@-1 {{template argument uses local type }} X c; + // cxx98-error@-1 {{template argument uses local type }} X d; -#if __cplusplus < 201103L - // expected-error@-7 {{uses local type}} - // expected-error@-7 {{uses local type}} - // expected-error@-7 {{uses local type}} - // expected-error@-7 {{uses local type}} - // expected-error@-7 {{uses local type}} - // expected-error@-7 {{uses local type}} -#endif + // cxx98-error@-1 {{template argument uses local type }} } } @@ -922,7 +1085,7 @@ namespace dr64 { // dr64: yes namespace dr66 { // dr66: no namespace X { - int f(int n); // expected-note 2{{candidate}} + int f(int n); // #dr66-f-first } using X::f; namespace X { @@ -930,9 +1093,13 @@ namespace dr66 { // dr66: no int f(int, int); } // FIXME: The first two calls here should be accepted. - int a = f(); // expected-error {{no matching function}} + int a = f(); + // expected-error@-1 {{no matching function for call to 'f'}} + // expected-note@#dr66-f-first {{candidate function not viable: requires single argument 'n', but no arguments were provided}} int b = f(1); - int c = f(1, 2); // expected-error {{no matching function}} + int c = f(1, 2); + // expected-error@-1 {{no matching function for call to 'f'}} + // expected-note@#dr66-f-first {{candidate function not viable: requires single argument 'n', but 2 arguments were provided}} } // dr67: na @@ -941,24 +1108,18 @@ namespace dr68 { // dr68: 2.8 template struct X {}; struct ::dr68::X x1; struct ::dr68::template X x2; -#if __cplusplus < 201103L - // expected-error@-2 {{'template' keyword outside of a template}} -#endif + // cxx98-error@-1 {{'template' keyword outside of a template}} struct Y { friend struct X; friend struct ::dr68::X; friend struct ::dr68::template X; -#if __cplusplus < 201103L - // expected-error@-2 {{'template' keyword outside of a template}} -#endif + // cxx98-error@-1 {{'template' keyword outside of a template}} }; template struct Z { friend struct ::dr68::template X; friend typename ::dr68::X; -#if __cplusplus < 201103L - // expected-error@-2 {{C++11 extension}} -#endif + // cxx98-error@-1 {{unelaborated friend declaration is a C++11 extension; specify 'struct' to befriend 'typename ::dr68::X'}} }; } @@ -966,15 +1127,13 @@ namespace dr69 { // dr69: 9 template static void f() {} // #dr69-f // FIXME: Should we warn here? inline void g() { f(); } - extern template void f(); // expected-error {{explicit instantiation declaration of 'f' with internal linkage}} -#if __cplusplus < 201103L - // expected-error@-2 {{C++11 extension}} -#endif + extern template void f(); + // cxx98-error@-1 {{extern templates are a C++11 extension}} + // expected-error@-2 {{explicit instantiation declaration of 'f' with internal linkage}} template struct Q {}; Q<&f > q; -#if __cplusplus < 201103L - // expected-error@-2 {{internal linkage}} expected-note@#dr69-f {{here}} -#endif + // cxx98-error@-1 {{non-type template argument referring to function 'f' with internal linkage is a C++11 extension}} + // cxx98-note@#dr69-f {{non-type template argument refers to function here}} } namespace dr70 { // dr70: yes @@ -990,8 +1149,9 @@ namespace dr70 { // dr70: yes #if __cplusplus >= 201103L namespace dr73 { // dr73: sup 1652 int a, b; - static_assert(&a + 1 != &b, ""); // expected-error {{not an integral constant expression}} - // expected-note@-1 {{comparison against pointer '&a + 1' that points past the end of a complete object}} + static_assert(&a + 1 != &b, ""); + // expected-error@-1 {{static assertion expression is not an integral constant expression}} + // expected-note@-2 {{comparison against pointer '&a + 1' that points past the end of a complete object has unspecified value}} } #endif @@ -1002,13 +1162,18 @@ namespace dr74 { // dr74: yes namespace dr75 { // dr75: yes struct S { - static int n = 0; // expected-error {{non-const}} + static int n = 0; + // expected-error@-1 {{non-const static data member must be initialized out of line}} }; } namespace dr76 { // dr76: yes const volatile int n = 1; - int arr[n]; // expected-error +{{variable length array}} expected-note {{read of volatile}} + int arr[n]; // #dr76-vla + // expected-error@#dr76-vla {{variable length arrays in C++ are a Clang extension}} + // expected-note@#dr76-vla {{read of volatile-qualified type 'const volatile int' is not allowed in a constant expression}} + + // expected-error@#dr76-vla {{variable length array declaration not allowed at file scope}} } namespace dr77 { // dr77: yes @@ -1021,7 +1186,8 @@ namespace dr77 { // dr77: yes namespace dr78 { // dr78: sup ???? // Under DR78, this is valid, because 'k' has static storage duration, so is // zero-initialized. - const int k; // expected-error {{default initialization of an object of const}} + const int k; + // expected-error@-1 {{default initialization of an object of const type 'const int'}} } // dr79: na @@ -1031,15 +1197,18 @@ namespace dr80 { // dr80: 2.9 int A; }; struct B { - static int B; // expected-error {{same name as its class}} + static int B; + // expected-error@-1 {{member 'B' has the same name as its class}} }; struct C { - int C; // expected-error {{same name as its class}} + int C; + // expected-error@-1 {{member 'C' has the same name as its class}} C(); }; struct D { D(); - int D; // expected-error {{same name as its class}} + int D; + // expected-error@-1 {{member 'D' has the same name as its class}} }; } @@ -1057,44 +1226,54 @@ namespace dr84 { // dr84: yes struct A { operator B() const; }; struct C {}; struct B { - B(B&); // expected-note 0-1{{candidate}} - B(C); // expected-note 0-1{{no known conversion from 'B' to 'C'}} + B(B&); // #dr84-copy-ctor + B(C); // #dr84-ctor-from-C operator C() const; }; A a; // Cannot use B(C) / operator C() pair to construct the B from the B temporary // here. In C++17, we initialize the B object directly using 'A::operator B()'. B b = a; -#if __cplusplus <= 201402L - // expected-error@-2 {{no viable}} -#endif + // cxx98-14-error@-1 {{no viable constructor copying variable of type 'B'}} + // cxx98-14-note@#dr84-copy-ctor {{candidate constructor not viable: expects an lvalue for 1st argument}} + // cxx98-14-note@#dr84-ctor-from-C {{candidate constructor not viable: no known conversion from 'B' to 'C' for 1st argument}} } namespace dr85 { // dr85: 3.4 struct A { struct B; - struct B {}; // expected-note{{previous declaration is here}} - struct B; // expected-error{{class member cannot be redeclared}} + struct B {}; // #dr85-B-def + struct B; + // expected-error@-1 {{class member cannot be redeclared}} + // expected-note@#dr85-B-def {{previous declaration is here}} union U; - union U {}; // expected-note{{previous declaration is here}} - union U; // expected-error{{class member cannot be redeclared}} + union U {}; // #dr85-U-def + union U; + // expected-error@-1 {{class member cannot be redeclared}} + // expected-note@#dr85-U-def {{previous declaration is here}} #if __cplusplus >= 201103L enum E1 : int; - enum E1 : int { e1 }; // expected-note{{previous declaration is here}} - enum E1 : int; // expected-error{{class member cannot be redeclared}} + enum E1 : int { e1 }; // #dr85-E1-def + enum E1 : int; + // expected-error@-1 {{class member cannot be redeclared}} + // expected-note@#dr85-E1-def {{previous declaration is here}} enum class E2; - enum class E2 { e2 }; // expected-note{{previous declaration is here}} - enum class E2; // expected-error{{class member cannot be redeclared}} + enum class E2 { e2 }; // #dr85-E2-def + enum class E2; + // expected-error@-1 {{class member cannot be redeclared}} + // expected-note@#dr85-E2-def {{previous declaration is here}} #endif }; template struct C { - struct B {}; // expected-note{{previous declaration is here}} - struct B; // expected-error{{class member cannot be redeclared}} + struct B {}; // #dr85-C-B-def + struct B; + // expected-error@-1 {{class member cannot be redeclared}} + // expected-note@#dr85-C-B-def {{previous declaration is here}} }; } @@ -1111,10 +1290,12 @@ namespace dr87 { // dr87: no namespace dr88 { // dr88: 2.8 template struct S { - static const int a = 1; // expected-note {{previous}} + static const int a = 1; // #dr88-a static const int b; }; - template<> const int S::a = 4; // expected-error {{already has an initializer}} + template<> const int S::a = 4; + // expected-error@-1 {{static data member 'a' already has an initializer}} + // expected-note@#dr88-a {{previous initialization is here}} template<> const int S::b = 4; } @@ -1135,17 +1316,22 @@ namespace dr90 { // dr90: yes void test() { dr90_f(A()); dr90_f(B()); - dr90_f(B::C()); // expected-error {{undeclared identifier}} - dr90_f(B::D()); // expected-error {{undeclared identifier}} + dr90_f(B::C()); + // expected-error@-1 {{use of undeclared identifier 'dr90_f'}} + dr90_f(B::D()); + // expected-error@-1 {{use of undeclared identifier 'dr90_f'}} dr90_f(E()); - dr90_f(F()); // expected-error {{undeclared identifier}} + dr90_f(F()); + // expected-error@-1 {{use of undeclared identifier 'dr90_f'}} - dr90_g(A()); // expected-error {{undeclared identifier}} + dr90_g(A()); + // expected-error@-1 {{use of undeclared identifier 'dr90_g'}} dr90_g(B()); dr90_g(B::C()); dr90_g(B::D()); dr90_g(E()); - dr90_g(F()); // expected-error {{undeclared identifier}} + dr90_g(F()); + // expected-error@-1 {{use of undeclared identifier 'dr90_g'}} } } @@ -1155,25 +1341,33 @@ namespace dr91 { // dr91: yes } namespace dr92 { // dr92: 4 c++17 - void f() throw(int, float); // expected-error 0-1{{ISO C++17 does not allow}} expected-note 0-1{{use 'noexcept}} - void (*p)() throw(int) = &f; // expected-error 0-1{{ISO C++17 does not allow}} expected-note 0-1{{use 'noexcept}} -#if __cplusplus <= 201402L - // expected-error@-2 {{target exception specification is not superset of source}} -#else - // expected-warning@-4 {{target exception specification is not superset of source}} -#endif - void (*q)() throw(int); // expected-error 0-1{{ISO C++17 does not allow}} expected-note 0-1{{use 'noexcept}} + void f() throw(int, float); + // since-cxx17-error@-1 {{ISO C++17 does not allow dynamic exception specifications}} + // since-cxx17-note@-2 {{use 'noexcept(false)' instead}} + void (*p)() throw(int) = &f; // #dr92-p + // since-cxx17-error@#dr92-p {{ISO C++17 does not allow dynamic exception specifications}} + // since-cxx17-note@#dr92-p {{use 'noexcept(false)' instead}} + + // cxx98-14-error@#dr92-p {{target exception specification is not superset of source}} + // since-cxx17-warning@#dr92-p {{target exception specification is not superset of source}} + void (*q)() throw(int); + // since-cxx17-error@-1 {{ISO C++17 does not allow dynamic exception specifications}} + // since-cxx17-note@-2 {{use 'noexcept(false)' instead}} void (**pp)() throw() = &q; -#if __cplusplus <= 201402L - // expected-error@-2 {{exception specifications are not allowed}} -#else - // expected-error@-4 {{cannot initialize}} -#endif + // cxx98-14-error@-1 {{exception specifications are not allowed beyond a single level of indirection}} + // since-cxx17-error@-2 {{cannot initialize a variable of type 'void (**)() throw()' with an rvalue of type 'void (**)() throw(int)'}} - void g(void() throw()); // expected-note 0-2 {{no known conversion}} expected-warning 0-1{{mangled name of 'g' will change in C++17}} + void g(void() throw()); // #dr92-g + // cxx98-14-warning@-1 {{mangled name of 'g' will change in C++17 due to non-throwing exception specification in function signature}} void h() throw() { - g(f); // expected-error-re {{{{is not superset|no matching function}}}} - g(q); // expected-error-re {{{{is not superset|no matching function}}}} + g(f); + // cxx98-14-error@-1 {{target exception specification is not superset of source}} + // since-cxx17-error@-2 {{no matching function for call to 'g'}} + // since-cxx17-note@#dr92-g {{candidate function not viable: no known conversion from 'void () throw(int, float)' to 'void (*)() throw()' for 1st argument}} + g(q); + // cxx98-14-error@-1 {{target exception specification is not superset of source}} + // since-cxx17-error@-2 {{no matching function for call to 'g'}} + // since-cxx17-note@#dr92-g {{candidate function not viable: no known conversion from 'void (*)() throw(int)' to 'void (*)() throw()' for 1st argument}} } // Prior to C++17, this is OK because the exception specification is not @@ -1182,11 +1376,11 @@ namespace dr92 { // dr92: 4 c++17 // is part of the type of the parameter, so this is invalid. template struct X {}; X<&f> xp; -#if __cplusplus > 201402L - // expected-error@-2 {{not implicitly convertible}} -#endif + // since-cxx17-error@-1 {{value of type 'void (*)() throw(int, float)' is not implicitly convertible to 'void (*)() throw()'}} - template struct Y {}; // expected-error 0-1{{ISO C++17 does not allow}} expected-note 0-1{{use 'noexcept}} + template struct Y {}; + // since-cxx17-error@-1 {{ISO C++17 does not allow dynamic exception specifications}} + // since-cxx17-note@-2 {{use 'noexcept(false)' instead}} Y<&h> yp; // ok } @@ -1204,12 +1398,14 @@ namespace dr95 { // dr95: 3.3 class C { friend struct A; friend struct B; - static void f(); // expected-note {{here}} + static void f(); // #dr95-C-f }; struct A *p; // dr95::A, not dr95::N::A. } A *q = N::p; // ok, same type - struct B { void f() { N::C::f(); } }; // expected-error {{private}} + struct B { void f() { N::C::f(); } }; + // expected-error@-1 {{'f' is a private member of 'dr95::N::C'}} + // expected-note@#dr95-C-f {{implicitly declared private here}} } namespace dr96 { // dr96: no @@ -1242,19 +1438,27 @@ namespace dr97 { // dr97: yes namespace dr98 { // dr98: yes void test(int n) { switch (n) { - try { // expected-note 2{{bypasses}} - case 0: // expected-error {{cannot jump}} + try { // #dr98-try + case 0: + // expected-error@-1 {{cannot jump from switch statement to this case label}} + // expected-note@#dr98-try {{jump bypasses initialization of try block}} x: throw n; - } catch (...) { // expected-note 2{{bypasses}} - case 1: // expected-error {{cannot jump}} + } catch (...) { // #dr98-catch + case 1: + // expected-error@-1 {{cannot jump from switch statement to this case label}} + // expected-note@#dr98-catch {{jump bypasses initialization of catch block}} y: throw n; } case 2: - goto x; // expected-error {{cannot jump}} + goto x; + // expected-error@-1 {{cannot jump from this goto statement to its label}} + // expected-note@#dr98-try {{jump bypasses initialization of try block}} case 3: - goto y; // expected-error {{cannot jump}} + goto y; + // expected-error@-1 {{cannot jump from this goto statement to its label}} + // expected-note@#dr98-catch {{jump bypasses initialization of catch block}} } } } -- GitLab From 5b729503946cd88b71264405f6a7c50014efff4f Mon Sep 17 00:00:00 2001 From: Aart Bik <39774503+aartbik@users.noreply.github.com> Date: Thu, 30 Nov 2023 09:40:39 -0800 Subject: [PATCH 003/699] [mlir][sparse] move all COO related methods into SparseTensorType (#73881) This centralizes all COO methods, and provides a cleaner API. Note that the "enc" only constructor is a temporary workaround the need for COO methods inside the "enc" only storage specifier. --- .../Dialect/SparseTensor/IR/SparseTensor.h | 13 --- .../SparseTensor/IR/SparseTensorType.h | 20 ++++- .../SparseTensor/IR/SparseTensorDialect.cpp | 80 +++++++++---------- .../SparseTensor/Transforms/LoopEmitter.cpp | 7 +- .../Transforms/SparseTensorCodegen.cpp | 9 +-- .../Transforms/SparseTensorDescriptor.cpp | 2 +- .../Transforms/SparseTensorDescriptor.h | 2 +- .../Transforms/SparseTensorRewriting.cpp | 4 +- 8 files changed, 65 insertions(+), 72 deletions(-) diff --git a/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h b/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h index 28dfdbdcf89b..5e523ec428ae 100644 --- a/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h +++ b/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h @@ -89,19 +89,6 @@ inline MemRefType getMemRefType(T &&t) { /// Returns null-attribute for any type without an encoding. SparseTensorEncodingAttr getSparseTensorEncoding(Type type); -/// Returns true iff the given sparse tensor encoding attribute has a trailing -/// COO region starting at the given level. -bool isCOOType(SparseTensorEncodingAttr enc, Level startLvl, bool isUnique); - -/// Returns true iff the given type is a COO type where the last level -/// is unique. -bool isUniqueCOOType(Type tp); - -/// Returns the starting level for a trailing COO region that spans -/// at least two levels. If no such COO region is found, then returns -/// the level-rank. -Level getCOOStart(SparseTensorEncodingAttr enc); - /// Returns true iff MLIR operand has any sparse operand. inline bool hasAnySparseOperand(Operation *op) { return llvm::any_of(op->getOperands().getTypes(), [](Type t) { diff --git a/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorType.h b/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorType.h index dc520e390de2..4c98129744bc 100644 --- a/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorType.h +++ b/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorType.h @@ -60,6 +60,12 @@ public: : SparseTensorType( RankedTensorType::get(stp.getShape(), stp.getElementType(), enc)) {} + // TODO: remove? + SparseTensorType(SparseTensorEncodingAttr enc) + : SparseTensorType(RankedTensorType::get( + SmallVector(enc.getDimRank(), ShapedType::kDynamic), + Float32Type::get(enc.getContext()), enc)) {} + SparseTensorType &operator=(const SparseTensorType &) = delete; SparseTensorType(const SparseTensorType &) = default; @@ -234,9 +240,9 @@ public: CrdTransDirectionKind::dim2lvl); } + /// Returns the type with an identity mapping. RankedTensorType getDemappedType() const { - auto lvlShape = getLvlShape(); - return RankedTensorType::get(lvlShape, rtp.getElementType(), + return RankedTensorType::get(getLvlShape(), getElementType(), enc.withoutDimToLvl()); } @@ -311,6 +317,16 @@ public: return IndexType::get(getContext()); } + /// Returns true iff this sparse tensor type has a trailing + /// COO region starting at the given level. By default, it + /// tests for a unique COO type at top level. + bool isCOOType(Level startLvl = 0, bool isUnique = true) const; + + /// Returns the starting level of this sparse tensor type for a + /// trailing COO region that spans **at least** two levels. If + /// no such COO region is found, then returns the level-rank. + Level getCOOStart() const; + /// Returns [un]ordered COO type for this sparse tensor type. RankedTensorType getCOOType(bool ordered) const; diff --git a/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp b/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp index d4f8afdd62f2..577dfe5ab2f3 100644 --- a/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp +++ b/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp @@ -66,7 +66,7 @@ void StorageLayout::foreachField( callback) const { const auto lvlTypes = enc.getLvlTypes(); const Level lvlRank = enc.getLvlRank(); - const Level cooStart = getCOOStart(enc); + const Level cooStart = SparseTensorType(enc).getCOOStart(); const Level end = cooStart == lvlRank ? cooStart : cooStart + 1; FieldIndex fieldIdx = kDataFieldStartingIdx; // Per-level storage. @@ -158,7 +158,7 @@ StorageLayout::getFieldIndexAndStride(SparseTensorFieldKind kind, unsigned stride = 1; if (kind == SparseTensorFieldKind::CrdMemRef) { assert(lvl.has_value()); - const Level cooStart = getCOOStart(enc); + const Level cooStart = SparseTensorType(enc).getCOOStart(); const Level lvlRank = enc.getLvlRank(); if (lvl.value() >= cooStart && lvl.value() < lvlRank) { lvl = cooStart; @@ -710,6 +710,29 @@ LogicalResult SparseTensorEncodingAttr::verifyEncoding( // SparseTensorType Methods. //===----------------------------------------------------------------------===// +bool mlir::sparse_tensor::SparseTensorType::isCOOType(Level startLvl, + bool isUnique) const { + if (!hasEncoding()) + return false; + if (!isCompressedLvl(startLvl) && !isLooseCompressedLvl(startLvl)) + return false; + for (Level l = startLvl + 1; l < lvlRank; ++l) + if (!isSingletonLvl(l)) + return false; + // If isUnique is true, then make sure that the last level is unique, + // that is, when lvlRank == 1, the only compressed level is unique, + // and when lvlRank > 1, the last singleton is unique. + return !isUnique || isUniqueLvl(lvlRank - 1); +} + +Level mlir::sparse_tensor::SparseTensorType::getCOOStart() const { + if (hasEncoding() && lvlRank > 1) + for (Level l = 0; l < lvlRank - 1; l++) + if (isCOOType(l, /*isUnique=*/false)) + return l; + return lvlRank; +} + RankedTensorType mlir::sparse_tensor::SparseTensorType::getCOOType(bool ordered) const { SmallVector lvlTypes; @@ -859,25 +882,6 @@ bool mlir::sparse_tensor::isBlockSparsity(AffineMap dimToLvl) { return !coeffientMap.empty(); } -bool mlir::sparse_tensor::isCOOType(SparseTensorEncodingAttr enc, - Level startLvl, bool isUnique) { - if (!enc || - !(enc.isCompressedLvl(startLvl) || enc.isLooseCompressedLvl(startLvl))) - return false; - const Level lvlRank = enc.getLvlRank(); - for (Level l = startLvl + 1; l < lvlRank; ++l) - if (!enc.isSingletonLvl(l)) - return false; - // If isUnique is true, then make sure that the last level is unique, - // that is, lvlRank == 1 (unique the only compressed) and lvlRank > 1 - // (unique on the last singleton). - return !isUnique || enc.isUniqueLvl(lvlRank - 1); -} - -bool mlir::sparse_tensor::isUniqueCOOType(Type tp) { - return isCOOType(getSparseTensorEncoding(tp), 0, /*isUnique=*/true); -} - bool mlir::sparse_tensor::hasAnyNonIdentityOperandsOrResults(Operation *op) { auto hasNonIdentityMap = [](Value v) { auto stt = tryGetSparseTensorType(v); @@ -888,17 +892,6 @@ bool mlir::sparse_tensor::hasAnyNonIdentityOperandsOrResults(Operation *op) { llvm::any_of(op->getResults(), hasNonIdentityMap); } -Level mlir::sparse_tensor::getCOOStart(SparseTensorEncodingAttr enc) { - // We only consider COO region with at least two levels for the purpose - // of AOS storage optimization. - const Level lvlRank = enc.getLvlRank(); - if (lvlRank > 1) - for (Level l = 0; l < lvlRank - 1; l++) - if (isCOOType(enc, l, /*isUnique=*/false)) - return l; - return lvlRank; -} - Dimension mlir::sparse_tensor::toDim(SparseTensorEncodingAttr enc, Level l) { if (enc) { assert(enc.isPermutation() && "Non permutation map not supported"); @@ -1013,7 +1006,7 @@ static LogicalResult verifyPackUnPack(Operation *op, bool requiresStaticShape, return op->emitError("the sparse-tensor must have the identity mapping"); // Verifies the trailing COO. - Level cooStartLvl = getCOOStart(stt.getEncoding()); + Level cooStartLvl = stt.getCOOStart(); if (cooStartLvl < stt.getLvlRank()) { // We only supports trailing COO for now, must be the last input. auto cooTp = llvm::cast(lvlTps.back()); @@ -1309,34 +1302,34 @@ OpFoldResult ReinterpretMapOp::fold(FoldAdaptor adaptor) { } LogicalResult ToPositionsOp::verify() { - auto e = getSparseTensorEncoding(getTensor().getType()); + auto stt = getSparseTensorType(getTensor()); if (failed(lvlIsInBounds(getLevel(), getTensor()))) return emitError("requested level is out of bounds"); - if (failed(isMatchingWidth(getResult(), e.getPosWidth()))) + if (failed(isMatchingWidth(getResult(), stt.getPosWidth()))) return emitError("unexpected type for positions"); return success(); } LogicalResult ToCoordinatesOp::verify() { - auto e = getSparseTensorEncoding(getTensor().getType()); + auto stt = getSparseTensorType(getTensor()); if (failed(lvlIsInBounds(getLevel(), getTensor()))) return emitError("requested level is out of bounds"); - if (failed(isMatchingWidth(getResult(), e.getCrdWidth()))) + if (failed(isMatchingWidth(getResult(), stt.getCrdWidth()))) return emitError("unexpected type for coordinates"); return success(); } LogicalResult ToCoordinatesBufferOp::verify() { - auto e = getSparseTensorEncoding(getTensor().getType()); - if (getCOOStart(e) >= e.getLvlRank()) + auto stt = getSparseTensorType(getTensor()); + if (stt.getCOOStart() >= stt.getLvlRank()) return emitError("expected sparse tensor with a COO region"); return success(); } LogicalResult ToValuesOp::verify() { - auto ttp = getRankedTensorType(getTensor()); + auto stt = getSparseTensorType(getTensor()); auto mtp = getMemRefType(getResult()); - if (ttp.getElementType() != mtp.getElementType()) + if (stt.getElementType() != mtp.getElementType()) return emitError("unexpected mismatch in element types"); return success(); } @@ -1660,9 +1653,8 @@ LogicalResult ReorderCOOOp::verify() { SparseTensorType srcStt = getSparseTensorType(getInputCoo()); SparseTensorType dstStt = getSparseTensorType(getResultCoo()); - if (!isCOOType(srcStt.getEncoding(), 0, /*isUnique=*/true) || - !isCOOType(dstStt.getEncoding(), 0, /*isUnique=*/true)) - emitError("Unexpected non-COO sparse tensors"); + if (!srcStt.isCOOType() || !dstStt.isCOOType()) + emitError("Expected COO sparse tensors only"); if (!srcStt.hasSameDimToLvl(dstStt)) emitError("Unmatched dim2lvl map between input and result COO"); diff --git a/mlir/lib/Dialect/SparseTensor/Transforms/LoopEmitter.cpp b/mlir/lib/Dialect/SparseTensor/Transforms/LoopEmitter.cpp index a245344755f0..26f015ce6ec6 100644 --- a/mlir/lib/Dialect/SparseTensor/Transforms/LoopEmitter.cpp +++ b/mlir/lib/Dialect/SparseTensor/Transforms/LoopEmitter.cpp @@ -412,8 +412,7 @@ void LoopEmitter::initializeLoopEmit( auto stt = getSparseTensorType(tensor); const Level lvlRank = stt.getLvlRank(); const auto shape = rtp.getShape(); - const auto enc = getSparseTensorEncoding(rtp); - const Level cooStart = enc ? getCOOStart(enc) : lvlRank; + const Level cooStart = stt.getCOOStart(); SmallVector lvlSzs; for (Level l = 0; l < stt.getLvlRank(); l++) { @@ -457,8 +456,8 @@ void LoopEmitter::initializeLoopEmit( // values. // Delegates extra output initialization to clients. bool isOutput = isOutputTensor(t); - Type elementType = rtp.getElementType(); - if (!enc) { + Type elementType = stt.getElementType(); + if (!stt.hasEncoding()) { // Non-annotated dense tensors. BaseMemRefType denseTp = MemRefType::get(shape, elementType); diff --git a/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorCodegen.cpp b/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorCodegen.cpp index e9062b49435f..18b2bb0819e2 100644 --- a/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorCodegen.cpp +++ b/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorCodegen.cpp @@ -194,7 +194,7 @@ static void createAllocFields(OpBuilder &builder, Location loc, valHeuristic = builder.create(loc, valHeuristic, lvlSizesValues[lvl]); } else if (sizeHint) { - if (getCOOStart(stt.getEncoding()) == 0) { + if (stt.getCOOStart() == 0) { posHeuristic = constantIndex(builder, loc, 2); crdHeuristic = builder.create( loc, constantIndex(builder, loc, lvlRank), sizeHint); // AOS @@ -657,8 +657,7 @@ struct SparseReorderCOOConverter : public OpConversionPattern { // Should have been verified. assert(dstStt.isAllOrdered() && !srcStt.isAllOrdered() && - isUniqueCOOType(srcStt.getRankedTensorType()) && - isUniqueCOOType(dstStt.getRankedTensorType())); + dstStt.isCOOType() && srcStt.isCOOType()); assert(dstStt.hasSameDimToLvl(srcStt)); // We don't need a mutable descriptor here as we perform sorting in-place. @@ -1317,7 +1316,7 @@ struct SparseAssembleOpConverter : public OpConversionPattern { Value posBack = c0; // index to the last value in the position array Value memSize = c1; // memory size for current array - Level trailCOOStart = getCOOStart(stt.getEncoding()); + Level trailCOOStart = stt.getCOOStart(); Level trailCOORank = stt.getLvlRank() - trailCOOStart; // Sets up SparseTensorSpecifier. for (Level lvl = 0, lvlRank = stt.getLvlRank(); lvl < lvlRank; lvl++) { @@ -1454,7 +1453,7 @@ struct SparseNewConverter : public OpConversionPattern { const auto dstTp = getSparseTensorType(op.getResult()); // Creating COO with NewOp is handled by direct IR codegen. All other cases // are handled by rewriting. - if (!dstTp.hasEncoding() || getCOOStart(dstTp.getEncoding()) != 0) + if (!dstTp.hasEncoding() || dstTp.getCOOStart() != 0) return failure(); // Implement as follows: diff --git a/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorDescriptor.cpp b/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorDescriptor.cpp index 1c6d7bebe37e..3ab4157475cd 100644 --- a/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorDescriptor.cpp +++ b/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorDescriptor.cpp @@ -103,7 +103,7 @@ void SparseTensorSpecifier::setSpecifierField(OpBuilder &builder, Location loc, Value sparse_tensor::SparseTensorDescriptor::getCrdMemRefOrView( OpBuilder &builder, Location loc, Level lvl) const { - const Level cooStart = getCOOStart(rType.getEncoding()); + const Level cooStart = rType.getCOOStart(); if (lvl < cooStart) return getMemRefField(SparseTensorFieldKind::CrdMemRef, lvl); diff --git a/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorDescriptor.h b/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorDescriptor.h index 4bd700eef522..5c7d8aa4c9d9 100644 --- a/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorDescriptor.h +++ b/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorDescriptor.h @@ -137,7 +137,7 @@ public: } Value getAOSMemRef() const { - const Level cooStart = getCOOStart(rType.getEncoding()); + const Level cooStart = rType.getCOOStart(); assert(cooStart < rType.getLvlRank()); return getMemRefField(SparseTensorFieldKind::CrdMemRef, cooStart); } diff --git a/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorRewriting.cpp b/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorRewriting.cpp index 2bd129b85ea5..4fc692f2fe9d 100644 --- a/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorRewriting.cpp +++ b/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorRewriting.cpp @@ -1180,8 +1180,7 @@ struct NewRewriter : public OpRewritePattern { PatternRewriter &rewriter) const override { Location loc = op.getLoc(); auto stt = getSparseTensorType(op.getResult()); - auto enc = stt.getEncoding(); - if (!stt.hasEncoding() || getCOOStart(enc) == 0) + if (!stt.hasEncoding() || stt.getCOOStart() == 0) return failure(); // Implement the NewOp as follows: @@ -1192,6 +1191,7 @@ struct NewRewriter : public OpRewritePattern { RankedTensorType cooTp = stt.getCOOType(/*ordered=*/true); Value cooTensor = rewriter.create(loc, cooTp, op.getSource()); Value convert = cooTensor; + auto enc = stt.getEncoding(); if (!stt.isPermutation()) { // demap coo, demap dstTp auto coo = getSparseTensorType(cooTensor).getEncoding().withoutDimToLvl(); convert = rewriter.create(loc, coo, convert); -- GitLab From 52be47b890d371c6033e84adabe03198a1cb9a38 Mon Sep 17 00:00:00 2001 From: Alexander Yermolovich <43973793+ayermolo@users.noreply.github.com> Date: Thu, 30 Nov 2023 09:41:01 -0800 Subject: [PATCH 004/699] [BOLT][DWARF] Add support to create path (#73884) When option --dwarf-output-path is specified, if the path does not exist BOLT will now create it. This is what also happens when --plugin-opt=dwo_dir= is specified to LLD. --- bolt/lib/Rewrite/DWARFRewriter.cpp | 2 ++ .../test/X86/dwarf5-df-output-dir-same-name.test | 16 ++++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/bolt/lib/Rewrite/DWARFRewriter.cpp b/bolt/lib/Rewrite/DWARFRewriter.cpp index 0beb865bd48c..5580d85e3fa7 100644 --- a/bolt/lib/Rewrite/DWARFRewriter.cpp +++ b/bolt/lib/Rewrite/DWARFRewriter.cpp @@ -679,6 +679,8 @@ void DWARFRewriter::updateDebugInfo() { assert(CompDirAttrInfo && "DW_AT_comp_dir is not in Skeleton CU."); if (!opts::DwarfOutputPath.empty()) { + if (!sys::fs::exists(opts::DwarfOutputPath)) + sys::fs::create_directory(opts::DwarfOutputPath); addStringHelper(DIEBldr, UnitDIE, Unit, CompDirAttrInfo, opts::DwarfOutputPath.c_str()); } diff --git a/bolt/test/X86/dwarf5-df-output-dir-same-name.test b/bolt/test/X86/dwarf5-df-output-dir-same-name.test index 4fd42e287a11..1f78da2022b8 100644 --- a/bolt/test/X86/dwarf5-df-output-dir-same-name.test +++ b/bolt/test/X86/dwarf5-df-output-dir-same-name.test @@ -21,3 +21,19 @@ ; BOLT: split.dwo1.dwo ; BOLT: DW_AT_dwo_name ("split.dwo0.dwo") ; BOLT: DW_AT_dwo_name ("split.dwo1.dwo") + +; Tests that when --dwarf-output-path is specified, but path do not exist BOLT creates it. + +; RUN: rm -rf dwo +; RUN: llvm-bolt main.exe -o main.exe.bolt --update-debug-sections --dwarf-output-path=%t/dwo +; RUN: ls -l %t/dwo > log +; RUN: llvm-dwarfdump --debug-info main.exe.bolt >> log +; RUN: cat log | FileCheck -check-prefix=BOLT1 %s + +; Tests that BOLT handles correctly writing out .dwo files to the same directory when input has input where part of path +; is in DW_AT_dwo_name and the .dwo file names are the same. + +; BOLT1: split.dwo0.dwo +; BOLT1: split.dwo1.dwo +; BOLT1: DW_AT_dwo_name ("split.dwo0.dwo") +; BOLT1: DW_AT_dwo_name ("split.dwo1.dwo") -- GitLab From cc944f502f1ee20d73ff88c2c86cc909f12caadb Mon Sep 17 00:00:00 2001 From: Momchil Velikov Date: Thu, 30 Nov 2023 17:41:51 +0000 Subject: [PATCH 005/699] [AArch64] Stack probing for function prologues (#66524) This adds code to AArch64 function prologues to protect against stack clash attacks by probing (writing to) the stack at regular enough intervals to ensure that the guard page cannot be skipped over. The patch depends on and maintains the following invariants: Upon function entry the caller guarantees that it has probed the stack (e.g. performed a store) at some address [sp, #N], where`0 <= N <= 1024`. This invariant comes from a requirement for compatibility with GCC. Any address range in the allocated stack, no smaller than stack-probe-size bytes contains at least one probe At any time the stack pointer is above or in the guard page Probes are performed in descreasing address order The stack-probe-size is a function attribute that can be set by a platform to correspond to the guard page size. By default, the stack probe size is 4KiB, which is a safe default as this is the smallest possible page size for AArch64. Linux uses a 64KiB guard for AArch64, so this can be overridden by the stack-probe-size function attribute. For small frames without a frame pointer (<= 240 bytes), no probes are needed. For larger frame sizes, LLVM always stores x29 to the stack. This serves as an implicit stack probe. Thus, while allocating stack objects the compiler assumes that the stack has been probed at [sp]. There are multiple probing sequences that can be emitted, depending on the size of the stack allocation: A straight-line sequence of subtracts and stores, used when the allocation size is smaller than 5 guard pages. A loop allocating and probing one page size per iteration, plus at most a single probe to deal with the remainder, used when the allocation size is larger but still known at compile time. A loop which moves the SP down to the target value held in a register (or a loop, moving a scratch register to the target value help in SP), used when the allocation size is not known at compile-time, such as when allocating space for SVE values, or when over-aligning the stack. This is emitted in AArch64InstrInfo because it will also be used for dynamic allocas in a future patch. A single probe where the amount of stack adjustment is unknown, but is known to be less than or equal to a page size. --------- Co-authored-by: Oliver Stannard --- .../Target/AArch64/AArch64FrameLowering.cpp | 336 +++++++- .../lib/Target/AArch64/AArch64FrameLowering.h | 17 +- .../Target/AArch64/AArch64ISelLowering.cpp | 6 + llvm/lib/Target/AArch64/AArch64ISelLowering.h | 10 + llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 91 ++- llvm/lib/Target/AArch64/AArch64InstrInfo.h | 7 + llvm/lib/Target/AArch64/AArch64InstrInfo.td | 25 +- .../AArch64/AArch64MachineFunctionInfo.cpp | 43 +- .../AArch64/AArch64MachineFunctionInfo.h | 6 + .../test/CodeGen/AArch64/stack-probing-64k.ll | 392 ++++++++++ .../AArch64/stack-probing-last-in-block.mir | 146 ++++ .../test/CodeGen/AArch64/stack-probing-sve.ll | 724 ++++++++++++++++++ llvm/test/CodeGen/AArch64/stack-probing.ll | 539 +++++++++++++ 13 files changed, 2302 insertions(+), 40 deletions(-) create mode 100644 llvm/test/CodeGen/AArch64/stack-probing-64k.ll create mode 100644 llvm/test/CodeGen/AArch64/stack-probing-last-in-block.mir create mode 100644 llvm/test/CodeGen/AArch64/stack-probing-sve.ll create mode 100644 llvm/test/CodeGen/AArch64/stack-probing.ll diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp index 95ac21214a5c..96702cb8b255 100644 --- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -689,10 +689,18 @@ void AArch64FrameLowering::emitCalleeSavedSVERestores( emitCalleeSavedRestores(MBB, MBBI, true); } +// Return the maximum possible number of bytes for `Size` due to the +// architectural limit on the size of a SVE register. +static int64_t upperBound(StackOffset Size) { + static const int64_t MAX_BYTES_PER_SCALABLE_BYTE = 16; + return Size.getScalable() * MAX_BYTES_PER_SCALABLE_BYTE + Size.getFixed(); +} + void AArch64FrameLowering::allocateStackSpace( MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, - bool NeedsRealignment, StackOffset AllocSize, bool NeedsWinCFI, - bool *HasWinCFI, bool EmitCFI, StackOffset InitialOffset) const { + int64_t RealignmentPadding, StackOffset AllocSize, bool NeedsWinCFI, + bool *HasWinCFI, bool EmitCFI, StackOffset InitialOffset, + bool FollowupAllocs) const { if (!AllocSize) return; @@ -704,27 +712,128 @@ void AArch64FrameLowering::allocateStackSpace( AArch64FunctionInfo &AFI = *MF.getInfo(); const MachineFrameInfo &MFI = MF.getFrameInfo(); - Register TargetReg = - NeedsRealignment ? findScratchNonCalleeSaveRegister(&MBB) : AArch64::SP; - // SUB Xd/SP, SP, AllocSize + const int64_t MaxAlign = MFI.getMaxAlign().value(); + const uint64_t AndMask = ~(MaxAlign - 1); + + if (!Subtarget.getTargetLowering()->hasInlineStackProbe(MF)) { + Register TargetReg = RealignmentPadding + ? findScratchNonCalleeSaveRegister(&MBB) + : AArch64::SP; + // SUB Xd/SP, SP, AllocSize + emitFrameOffset(MBB, MBBI, DL, TargetReg, AArch64::SP, -AllocSize, &TII, + MachineInstr::FrameSetup, false, NeedsWinCFI, HasWinCFI, + EmitCFI, InitialOffset); + + if (RealignmentPadding) { + // AND SP, X9, 0b11111...0000 + BuildMI(MBB, MBBI, DL, TII.get(AArch64::ANDXri), AArch64::SP) + .addReg(TargetReg, RegState::Kill) + .addImm(AArch64_AM::encodeLogicalImmediate(AndMask, 64)) + .setMIFlags(MachineInstr::FrameSetup); + AFI.setStackRealigned(true); + + // No need for SEH instructions here; if we're realigning the stack, + // we've set a frame pointer and already finished the SEH prologue. + assert(!NeedsWinCFI); + } + return; + } + + // + // Stack probing allocation. + // + + // Fixed length allocation. If we don't need to re-align the stack and don't + // have SVE objects, we can use a more efficient sequence for stack probing. + if (AllocSize.getScalable() == 0 && RealignmentPadding == 0) { + Register ScratchReg = findScratchNonCalleeSaveRegister(&MBB); + assert(ScratchReg != AArch64::NoRegister); + BuildMI(MBB, MBBI, DL, TII.get(AArch64::PROBED_STACKALLOC)) + .addDef(ScratchReg) + .addImm(AllocSize.getFixed()) + .addImm(InitialOffset.getFixed()) + .addImm(InitialOffset.getScalable()); + // The fixed allocation may leave unprobed bytes at the top of the + // stack. If we have subsequent alocation (e.g. if we have variable-sized + // objects), we need to issue an extra probe, so these allocations start in + // a known state. + if (FollowupAllocs) { + // STR XZR, [SP] + BuildMI(MBB, MBBI, DL, TII.get(AArch64::STRXui)) + .addReg(AArch64::XZR) + .addReg(AArch64::SP) + .addImm(0) + .setMIFlags(MachineInstr::FrameSetup); + } + + return; + } + + // Variable length allocation. + + // If the (unknown) allocation size cannot exceed the probe size, decrement + // the stack pointer right away. + int64_t ProbeSize = AFI.getStackProbeSize(); + if (upperBound(AllocSize) + RealignmentPadding <= ProbeSize) { + Register ScratchReg = RealignmentPadding + ? findScratchNonCalleeSaveRegister(&MBB) + : AArch64::SP; + assert(ScratchReg != AArch64::NoRegister); + // SUB Xd, SP, AllocSize + emitFrameOffset(MBB, MBBI, DL, ScratchReg, AArch64::SP, -AllocSize, &TII, + MachineInstr::FrameSetup, false, NeedsWinCFI, HasWinCFI, + EmitCFI, InitialOffset); + if (RealignmentPadding) { + // AND SP, Xn, 0b11111...0000 + BuildMI(MBB, MBBI, DL, TII.get(AArch64::ANDXri), AArch64::SP) + .addReg(ScratchReg, RegState::Kill) + .addImm(AArch64_AM::encodeLogicalImmediate(AndMask, 64)) + .setMIFlags(MachineInstr::FrameSetup); + AFI.setStackRealigned(true); + } + if (FollowupAllocs || upperBound(AllocSize) + RealignmentPadding > + AArch64::StackProbeMaxUnprobedStack) { + // STR XZR, [SP] + BuildMI(MBB, MBBI, DL, TII.get(AArch64::STRXui)) + .addReg(AArch64::XZR) + .addReg(AArch64::SP) + .addImm(0) + .setMIFlags(MachineInstr::FrameSetup); + } + return; + } + + // Emit a variable-length allocation probing loop. + // TODO: As an optimisation, the loop can be "unrolled" into a few parts, + // each of them guaranteed to adjust the stack by less than the probe size. + Register TargetReg = findScratchNonCalleeSaveRegister(&MBB); + assert(TargetReg != AArch64::NoRegister); + // SUB Xd, SP, AllocSize emitFrameOffset(MBB, MBBI, DL, TargetReg, AArch64::SP, -AllocSize, &TII, MachineInstr::FrameSetup, false, NeedsWinCFI, HasWinCFI, EmitCFI, InitialOffset); - - if (NeedsRealignment) { - const int64_t MaxAlign = MFI.getMaxAlign().value(); - const uint64_t AndMask = ~(MaxAlign - 1); - // AND SP, Xd, 0b11111...0000 - BuildMI(MBB, MBBI, DL, TII.get(AArch64::ANDXri), AArch64::SP) + if (RealignmentPadding) { + // AND Xn, Xn, 0b11111...0000 + BuildMI(MBB, MBBI, DL, TII.get(AArch64::ANDXri), TargetReg) .addReg(TargetReg, RegState::Kill) .addImm(AArch64_AM::encodeLogicalImmediate(AndMask, 64)) .setMIFlags(MachineInstr::FrameSetup); - AFI.setStackRealigned(true); + } - // No need for SEH instructions here; if we're realigning the stack, - // we've set a frame pointer and already finished the SEH prologue. - assert(!NeedsWinCFI); + BuildMI(MBB, MBBI, DL, TII.get(AArch64::PROBED_STACKALLOC_VAR)) + .addReg(TargetReg); + if (EmitCFI) { + // Set the CFA register back to SP. + unsigned Reg = + Subtarget.getRegisterInfo()->getDwarfRegNum(AArch64::SP, true); + unsigned CFIIndex = + MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, Reg)); + BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) + .addCFIIndex(CFIIndex) + .setMIFlags(MachineInstr::FrameSetup); } + if (RealignmentPadding) + AFI.setStackRealigned(true); } static MCRegister getRegisterOrZero(MCRegister Reg, bool HasSVE) { @@ -905,9 +1014,11 @@ bool AArch64FrameLowering::canUseAsPrologue( MachineBasicBlock *TmpMBB = const_cast(&MBB); const AArch64Subtarget &Subtarget = MF->getSubtarget(); const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); + const AArch64TargetLowering *TLI = Subtarget.getTargetLowering(); - // Don't need a scratch register if we're not going to re-align the stack. - if (!RegInfo->hasStackRealignment(*MF)) + // Don't need a scratch register if we're not going to re-align the stack or + // emit stack probes. + if (!RegInfo->hasStackRealignment(*MF) && TLI->hasInlineStackProbe(*MF)) return true; // Otherwise, we can use any block as long as it has a scratch register // available. @@ -917,15 +1028,11 @@ bool AArch64FrameLowering::canUseAsPrologue( static bool windowsRequiresStackProbe(MachineFunction &MF, uint64_t StackSizeInBytes) { const AArch64Subtarget &Subtarget = MF.getSubtarget(); - if (!Subtarget.isTargetWindows()) - return false; - const Function &F = MF.getFunction(); + const AArch64FunctionInfo &MFI = *MF.getInfo(); // TODO: When implementing stack protectors, take that into account // for the probe threshold. - unsigned StackProbeSize = - F.getFnAttributeAsParsedInteger("stack-probe-size", 4096); - return (StackSizeInBytes >= StackProbeSize) && - !F.hasFnAttribute("no-stack-arg-probe"); + return Subtarget.isTargetWindows() && MFI.hasStackProbing() && + StackSizeInBytes >= uint64_t(MFI.getStackProbeSize()); } static bool needsWinCFI(const MachineFunction &MF) { @@ -1730,7 +1837,7 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF, // Alignment is required for the parent frame, not the funclet const bool NeedsRealignment = NumBytes && !IsFunclet && RegInfo->hasStackRealignment(MF); - int64_t RealignmentPadding = + const int64_t RealignmentPadding = (NeedsRealignment && MFI.getMaxAlign() > Align(16)) ? MFI.getMaxAlign().value() - 16 : 0; @@ -1866,6 +1973,8 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF, // Process the SVE callee-saves to determine what space needs to be // allocated. if (int64_t CalleeSavedSize = AFI->getSVECalleeSavedStackSize()) { + LLVM_DEBUG(dbgs() << "SVECalleeSavedStackSize = " << CalleeSavedSize + << "\n"); // Find callee save instructions in frame. CalleeSavesBegin = MBBI; assert(IsSVECalleeSave(CalleeSavesBegin) && "Unexpected instruction"); @@ -1880,8 +1989,10 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF, // Allocate space for the callee saves (if any). StackOffset CFAOffset = StackOffset::getFixed((int64_t)MFI.getStackSize() - NumBytes); - allocateStackSpace(MBB, CalleeSavesBegin, false, SVECalleeSavesSize, false, - nullptr, EmitAsyncCFI && !HasFP, CFAOffset); + StackOffset LocalsSize = SVELocalsSize + StackOffset::getFixed(NumBytes); + allocateStackSpace(MBB, CalleeSavesBegin, 0, SVECalleeSavesSize, false, + nullptr, EmitAsyncCFI && !HasFP, CFAOffset, + MFI.hasVarSizedObjects() || LocalsSize); CFAOffset += SVECalleeSavesSize; if (EmitAsyncCFI) @@ -1895,10 +2006,10 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF, // FIXME: in the case of dynamic re-alignment, NumBytes doesn't have // the correct value here, as NumBytes also includes padding bytes, // which shouldn't be counted here. - allocateStackSpace(MBB, CalleeSavesEnd, NeedsRealignment, + allocateStackSpace(MBB, CalleeSavesEnd, RealignmentPadding, SVELocalsSize + StackOffset::getFixed(NumBytes), NeedsWinCFI, &HasWinCFI, EmitAsyncCFI && !HasFP, - CFAOffset); + CFAOffset, MFI.hasVarSizedObjects()); } // If we need a base pointer, set it up here. It's whatever the value of the @@ -4108,3 +4219,170 @@ void AArch64FrameLowering::orderFrameObjects( dbgs() << "\n"; }); } + +/// Emit a loop to decrement SP until it is equal to TargetReg, with probes at +/// least every ProbeSize bytes. Returns an iterator of the first instruction +/// after the loop. The difference between SP and TargetReg must be an exact +/// multiple of ProbeSize. +MachineBasicBlock::iterator +AArch64FrameLowering::inlineStackProbeLoopExactMultiple( + MachineBasicBlock::iterator MBBI, int64_t ProbeSize, + Register TargetReg) const { + MachineBasicBlock &MBB = *MBBI->getParent(); + MachineFunction &MF = *MBB.getParent(); + const AArch64InstrInfo *TII = + MF.getSubtarget().getInstrInfo(); + DebugLoc DL = MBB.findDebugLoc(MBBI); + + MachineFunction::iterator MBBInsertPoint = std::next(MBB.getIterator()); + MachineBasicBlock *LoopMBB = MF.CreateMachineBasicBlock(MBB.getBasicBlock()); + MF.insert(MBBInsertPoint, LoopMBB); + MachineBasicBlock *ExitMBB = MF.CreateMachineBasicBlock(MBB.getBasicBlock()); + MF.insert(MBBInsertPoint, ExitMBB); + + // SUB SP, SP, #ProbeSize (or equivalent if ProbeSize is not encodable + // in SUB). + emitFrameOffset(*LoopMBB, LoopMBB->end(), DL, AArch64::SP, AArch64::SP, + StackOffset::getFixed(-ProbeSize), TII, + MachineInstr::FrameSetup); + // STR XZR, [SP] + BuildMI(*LoopMBB, LoopMBB->end(), DL, TII->get(AArch64::STRXui)) + .addReg(AArch64::XZR) + .addReg(AArch64::SP) + .addImm(0) + .setMIFlags(MachineInstr::FrameSetup); + // CMP SP, TargetReg + BuildMI(*LoopMBB, LoopMBB->end(), DL, TII->get(AArch64::SUBSXrx64), + AArch64::XZR) + .addReg(AArch64::SP) + .addReg(TargetReg) + .addImm(AArch64_AM::getArithExtendImm(AArch64_AM::UXTX, 0)) + .setMIFlags(MachineInstr::FrameSetup); + // B.CC Loop + BuildMI(*LoopMBB, LoopMBB->end(), DL, TII->get(AArch64::Bcc)) + .addImm(AArch64CC::NE) + .addMBB(LoopMBB) + .setMIFlags(MachineInstr::FrameSetup); + + LoopMBB->addSuccessor(ExitMBB); + LoopMBB->addSuccessor(LoopMBB); + // Synthesize the exit MBB. + ExitMBB->splice(ExitMBB->end(), &MBB, MBBI, MBB.end()); + ExitMBB->transferSuccessorsAndUpdatePHIs(&MBB); + MBB.addSuccessor(LoopMBB); + // Update liveins. + recomputeLiveIns(*LoopMBB); + recomputeLiveIns(*ExitMBB); + + return ExitMBB->begin(); +} + +void AArch64FrameLowering::inlineStackProbeFixed( + MachineBasicBlock::iterator MBBI, Register ScratchReg, int64_t FrameSize, + StackOffset CFAOffset) const { + MachineBasicBlock *MBB = MBBI->getParent(); + MachineFunction &MF = *MBB->getParent(); + const AArch64InstrInfo *TII = + MF.getSubtarget().getInstrInfo(); + AArch64FunctionInfo *AFI = MF.getInfo(); + bool EmitAsyncCFI = AFI->needsAsyncDwarfUnwindInfo(MF); + bool HasFP = hasFP(MF); + + DebugLoc DL; + int64_t ProbeSize = MF.getInfo()->getStackProbeSize(); + int64_t NumBlocks = FrameSize / ProbeSize; + int64_t ResidualSize = FrameSize % ProbeSize; + + LLVM_DEBUG(dbgs() << "Stack probing: total " << FrameSize << " bytes, " + << NumBlocks << " blocks of " << ProbeSize + << " bytes, plus " << ResidualSize << " bytes\n"); + + // Decrement SP by NumBlock * ProbeSize bytes, with either unrolled or + // ordinary loop. + if (NumBlocks <= AArch64::StackProbeMaxLoopUnroll) { + for (int i = 0; i < NumBlocks; ++i) { + // SUB SP, SP, #ProbeSize (or equivalent if ProbeSize is not + // encodable in a SUB). + emitFrameOffset(*MBB, MBBI, DL, AArch64::SP, AArch64::SP, + StackOffset::getFixed(-ProbeSize), TII, + MachineInstr::FrameSetup, false, false, nullptr, + EmitAsyncCFI && !HasFP, CFAOffset); + CFAOffset += StackOffset::getFixed(ProbeSize); + // STR XZR, [SP] + BuildMI(*MBB, MBBI, DL, TII->get(AArch64::STRXui)) + .addReg(AArch64::XZR) + .addReg(AArch64::SP) + .addImm(0) + .setMIFlags(MachineInstr::FrameSetup); + } + } else if (NumBlocks != 0) { + // SUB ScratchReg, SP, #FrameSize (or equivalent if FrameSize is not + // encodable in ADD). ScrathReg may temporarily become the CFA register. + emitFrameOffset(*MBB, MBBI, DL, ScratchReg, AArch64::SP, + StackOffset::getFixed(-ProbeSize * NumBlocks), TII, + MachineInstr::FrameSetup, false, false, nullptr, + EmitAsyncCFI && !HasFP, CFAOffset); + CFAOffset += StackOffset::getFixed(ProbeSize * NumBlocks); + MBBI = inlineStackProbeLoopExactMultiple(MBBI, ProbeSize, ScratchReg); + MBB = MBBI->getParent(); + if (EmitAsyncCFI && !HasFP) { + // Set the CFA register back to SP. + const AArch64RegisterInfo &RegInfo = + *MF.getSubtarget().getRegisterInfo(); + unsigned Reg = RegInfo.getDwarfRegNum(AArch64::SP, true); + unsigned CFIIndex = + MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, Reg)); + BuildMI(*MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) + .addCFIIndex(CFIIndex) + .setMIFlags(MachineInstr::FrameSetup); + } + } + + if (ResidualSize != 0) { + // SUB SP, SP, #ResidualSize (or equivalent if ResidualSize is not encodable + // in SUB). + emitFrameOffset(*MBB, MBBI, DL, AArch64::SP, AArch64::SP, + StackOffset::getFixed(-ResidualSize), TII, + MachineInstr::FrameSetup, false, false, nullptr, + EmitAsyncCFI && !HasFP, CFAOffset); + if (ResidualSize > AArch64::StackProbeMaxUnprobedStack) { + // STR XZR, [SP] + BuildMI(*MBB, MBBI, DL, TII->get(AArch64::STRXui)) + .addReg(AArch64::XZR) + .addReg(AArch64::SP) + .addImm(0) + .setMIFlags(MachineInstr::FrameSetup); + } + } +} + +void AArch64FrameLowering::inlineStackProbe(MachineFunction &MF, + MachineBasicBlock &MBB) const { + // Get the instructions that need to be replaced. We emit at most two of + // these. Remember them in order to avoid complications coming from the need + // to traverse the block while potentially creating more blocks. + SmallVector ToReplace; + for (MachineInstr &MI : MBB) + if (MI.getOpcode() == AArch64::PROBED_STACKALLOC || + MI.getOpcode() == AArch64::PROBED_STACKALLOC_VAR) + ToReplace.push_back(&MI); + + for (MachineInstr *MI : ToReplace) { + if (MI->getOpcode() == AArch64::PROBED_STACKALLOC) { + Register ScratchReg = MI->getOperand(0).getReg(); + int64_t FrameSize = MI->getOperand(1).getImm(); + StackOffset CFAOffset = StackOffset::get(MI->getOperand(2).getImm(), + MI->getOperand(3).getImm()); + inlineStackProbeFixed(MI->getIterator(), ScratchReg, FrameSize, + CFAOffset); + } else { + assert(MI->getOpcode() == AArch64::PROBED_STACKALLOC_VAR && + "Stack probe pseudo-instruction expected"); + const AArch64InstrInfo *TII = + MI->getMF()->getSubtarget().getInstrInfo(); + Register TargetReg = MI->getOperand(0).getReg(); + (void)TII->probedStackAlloc(MI->getIterator(), TargetReg, true); + } + MI->eraseFromParent(); + } +} diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.h b/llvm/lib/Target/AArch64/AArch64FrameLowering.h index f3313f3b53ff..941af03a78b7 100644 --- a/llvm/lib/Target/AArch64/AArch64FrameLowering.h +++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.h @@ -152,13 +152,26 @@ private: MachineBasicBlock::iterator MBBI) const; void allocateStackSpace(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, - bool NeedsRealignment, StackOffset AllocSize, + int64_t RealignmentPadding, StackOffset AllocSize, bool NeedsWinCFI, bool *HasWinCFI, bool EmitCFI, - StackOffset InitialOffset) const; + StackOffset InitialOffset, bool FollowupAllocs) const; /// Emit target zero call-used regs. void emitZeroCallUsedRegs(BitVector RegsToZero, MachineBasicBlock &MBB) const override; + + /// Replace a StackProbe stub (if any) with the actual probe code inline + void inlineStackProbe(MachineFunction &MF, + MachineBasicBlock &PrologueMBB) const override; + + void inlineStackProbeFixed(MachineBasicBlock::iterator MBBI, + Register ScratchReg, int64_t FrameSize, + StackOffset CFAOffset) const; + + MachineBasicBlock::iterator + inlineStackProbeLoopExactMultiple(MachineBasicBlock::iterator MBBI, + int64_t NegProbeSize, + Register TargetReg) const; }; } // End llvm namespace diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 149a6d413d81..cb093a161311 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -26815,3 +26815,9 @@ unsigned AArch64TargetLowering::getVectorTypeBreakdownForCallingConv( return NumRegs; } + +bool AArch64TargetLowering::hasInlineStackProbe( + const MachineFunction &MF) const { + return !Subtarget->isTargetWindows() && + MF.getInfo()->hasStackProbing(); +} diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h index c67c7c5affdc..25d7cb6d212d 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h @@ -514,6 +514,13 @@ const unsigned RoundingBitsPos = 22; ArrayRef getGPRArgRegs(); ArrayRef getFPRArgRegs(); +/// Maximum allowed number of unprobed bytes above SP at an ABI +/// boundary. +const unsigned StackProbeMaxUnprobedStack = 1024; + +/// Maximum number of iterations to unroll for a constant size probing loop. +const unsigned StackProbeMaxLoopUnroll = 4; + } // namespace AArch64 class AArch64Subtarget; @@ -966,6 +973,9 @@ public: unsigned &NumIntermediates, MVT &RegisterVT) const override; + /// True if stack clash protection is enabled for this functions. + bool hasInlineStackProbe(const MachineFunction &MF) const override; + private: /// Keep a pointer to the AArch64Subtarget around so that we can /// make the right decision when generating code for different targets. diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index 55c21f1b7ddb..6f4c6f5ad073 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -10,8 +10,8 @@ // //===----------------------------------------------------------------------===// -#include "AArch64ExpandImm.h" #include "AArch64InstrInfo.h" +#include "AArch64ExpandImm.h" #include "AArch64FrameLowering.h" #include "AArch64MachineFunctionInfo.h" #include "AArch64PointerAuth.h" @@ -21,6 +21,7 @@ #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/CodeGen/LivePhysRegs.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineCombinerPattern.h" #include "llvm/CodeGen/MachineFrameInfo.h" @@ -9467,6 +9468,94 @@ bool AArch64InstrInfo::isReallyTriviallyReMaterializable( return TargetInstrInfo::isReallyTriviallyReMaterializable(MI); } +MachineBasicBlock::iterator +AArch64InstrInfo::probedStackAlloc(MachineBasicBlock::iterator MBBI, + Register TargetReg, bool FrameSetup) const { + assert(TargetReg != AArch64::SP && "New top of stack cannot aleady be in SP"); + + MachineBasicBlock &MBB = *MBBI->getParent(); + MachineFunction &MF = *MBB.getParent(); + const AArch64InstrInfo *TII = + MF.getSubtarget().getInstrInfo(); + int64_t ProbeSize = MF.getInfo()->getStackProbeSize(); + DebugLoc DL = MBB.findDebugLoc(MBBI); + + MachineFunction::iterator MBBInsertPoint = std::next(MBB.getIterator()); + MachineBasicBlock *LoopTestMBB = + MF.CreateMachineBasicBlock(MBB.getBasicBlock()); + MF.insert(MBBInsertPoint, LoopTestMBB); + MachineBasicBlock *LoopBodyMBB = + MF.CreateMachineBasicBlock(MBB.getBasicBlock()); + MF.insert(MBBInsertPoint, LoopBodyMBB); + MachineBasicBlock *ExitMBB = MF.CreateMachineBasicBlock(MBB.getBasicBlock()); + MF.insert(MBBInsertPoint, ExitMBB); + MachineInstr::MIFlag Flags = + FrameSetup ? MachineInstr::FrameSetup : MachineInstr::NoFlags; + + // LoopTest: + // SUB SP, SP, #ProbeSize + emitFrameOffset(*LoopTestMBB, LoopTestMBB->end(), DL, AArch64::SP, + AArch64::SP, StackOffset::getFixed(-ProbeSize), TII, Flags); + + // CMP SP, TargetReg + BuildMI(*LoopTestMBB, LoopTestMBB->end(), DL, TII->get(AArch64::SUBSXrx64), + AArch64::XZR) + .addReg(AArch64::SP) + .addReg(TargetReg) + .addImm(AArch64_AM::getArithExtendImm(AArch64_AM::UXTX, 0)) + .setMIFlags(Flags); + + // B. LoopExit + BuildMI(*LoopTestMBB, LoopTestMBB->end(), DL, TII->get(AArch64::Bcc)) + .addImm(AArch64CC::LE) + .addMBB(ExitMBB) + .setMIFlags(Flags); + + // STR XZR, [SP] + BuildMI(*LoopBodyMBB, LoopBodyMBB->end(), DL, TII->get(AArch64::STRXui)) + .addReg(AArch64::XZR) + .addReg(AArch64::SP) + .addImm(0) + .setMIFlags(Flags); + + // B loop + BuildMI(*LoopBodyMBB, LoopBodyMBB->end(), DL, TII->get(AArch64::B)) + .addMBB(LoopTestMBB) + .setMIFlags(Flags); + + // LoopExit: + // MOV SP, TargetReg + BuildMI(*ExitMBB, ExitMBB->end(), DL, TII->get(AArch64::ADDXri), AArch64::SP) + .addReg(TargetReg) + .addImm(0) + .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)) + .setMIFlags(Flags); + + // STR XZR, [SP] + BuildMI(*ExitMBB, ExitMBB->end(), DL, TII->get(AArch64::STRXui)) + .addReg(AArch64::XZR) + .addReg(AArch64::SP) + .addImm(0) + .setMIFlags(Flags); + + ExitMBB->splice(ExitMBB->end(), &MBB, std::next(MBBI), MBB.end()); + ExitMBB->transferSuccessorsAndUpdatePHIs(&MBB); + + LoopTestMBB->addSuccessor(ExitMBB); + LoopTestMBB->addSuccessor(LoopBodyMBB); + LoopBodyMBB->addSuccessor(LoopTestMBB); + MBB.addSuccessor(LoopTestMBB); + + // Update liveins. + if (MF.getRegInfo().reservedRegsFrozen()) { + recomputeLiveIns(*LoopTestMBB); + recomputeLiveIns(*LoopBodyMBB); + recomputeLiveIns(*ExitMBB); + } + + return ExitMBB->begin(); +} + #define GET_INSTRINFO_HELPERS #define GET_INSTRMAP_INFO #include "AArch64GenInstrInfo.inc" diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h index c63e856d46fb..b259efb9f2e7 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h @@ -383,6 +383,13 @@ public: bool isLegalAddressingMode(unsigned NumBytes, int64_t Offset, unsigned Scale) const; + // Decrement the SP, issuing probes along the way. `TargetReg` is the new top + // of the stack. `FrameSetup` is passed as true, if the allocation is a part + // of constructing the activation frame of a function. + MachineBasicBlock::iterator probedStackAlloc(MachineBasicBlock::iterator MBBI, + Register TargetReg, + bool FrameSetup) const; + #define GET_INSTRINFO_HELPER_DECLS #include "AArch64GenInstrInfo.inc" diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index b94bc101dc60..60cd94f4ff8e 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -936,7 +936,8 @@ include "SMEInstrFormats.td" // Miscellaneous instructions. //===----------------------------------------------------------------------===// -let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in { +let hasSideEffects = 1, isCodeGenOnly = 1 in { +let Defs = [SP], Uses = [SP] in { // We set Sched to empty list because we expect these instructions to simply get // removed in most cases. def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), @@ -945,7 +946,27 @@ def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), [(AArch64callseq_end timm:$amt1, timm:$amt2)]>, Sched<[]>; -} // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 + +} + +let Defs = [SP, NZCV], Uses = [SP] in { +// Probed stack allocation of a constant size, used in function prologues when +// stack-clash protection is enabled. +def PROBED_STACKALLOC : Pseudo<(outs GPR64:$scratch), + (ins i64imm:$stacksize, i64imm:$fixed_offset, + i64imm:$scalable_offset), + []>, + Sched<[]>; + +// Probed stack allocation of a variable size, used in function prologues when +// stack-clash protection is enabled. +def PROBED_STACKALLOC_VAR : Pseudo<(outs), + (ins GPR64sp:$target), + []>, + Sched<[]>; + +} // Defs = [SP, NZCV], Uses = [SP] in +} // hasSideEffects = 1, isCodeGenOnly = 1 let isReMaterializable = 1, isCodeGenOnly = 1 in { // FIXME: The following pseudo instructions are only needed because remat diff --git a/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp b/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp index 7bb5041b8ba9..f8b73ba6dda3 100644 --- a/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp @@ -97,14 +97,45 @@ AArch64FunctionInfo::AArch64FunctionInfo(const Function &F, if (const auto *BTE = mdconst::extract_or_null( F.getParent()->getModuleFlag("branch-target-enforcement"))) BranchTargetEnforcement = BTE->getZExtValue(); - return; + } else { + const StringRef BTIEnable = + F.getFnAttribute("branch-target-enforcement").getValueAsString(); + assert(BTIEnable.equals_insensitive("true") || + BTIEnable.equals_insensitive("false")); + BranchTargetEnforcement = BTIEnable.equals_insensitive("true"); } - const StringRef BTIEnable = - F.getFnAttribute("branch-target-enforcement").getValueAsString(); - assert(BTIEnable.equals_insensitive("true") || - BTIEnable.equals_insensitive("false")); - BranchTargetEnforcement = BTIEnable.equals_insensitive("true"); + // The default stack probe size is 4096 if the function has no + // stack-probe-size attribute. This is a safe default because it is the + // smallest possible guard page size. + uint64_t ProbeSize = 4096; + if (F.hasFnAttribute("stack-probe-size")) + ProbeSize = F.getFnAttributeAsParsedInteger("stack-probe-size"); + else if (const auto *PS = mdconst::extract_or_null( + F.getParent()->getModuleFlag("stack-probe-size"))) + ProbeSize = PS->getZExtValue(); + assert(int64_t(ProbeSize) > 0 && "Invalid stack probe size"); + + if (STI->isTargetWindows()) { + if (!F.hasFnAttribute("no-stack-arg-probe")) + StackProbeSize = ProbeSize; + } else { + // Round down to the stack alignment. + uint64_t StackAlign = + STI->getFrameLowering()->getTransientStackAlign().value(); + ProbeSize = std::max(StackAlign, ProbeSize & ~(StackAlign - 1U)); + StringRef ProbeKind; + if (F.hasFnAttribute("probe-stack")) + ProbeKind = F.getFnAttribute("probe-stack").getValueAsString(); + else if (const auto *PS = dyn_cast_or_null( + F.getParent()->getModuleFlag("probe-stack"))) + ProbeKind = PS->getString(); + if (ProbeKind.size()) { + if (ProbeKind != "inline-asm") + report_fatal_error("Unsupported stack probing method"); + StackProbeSize = ProbeSize; + } + } } MachineFunctionInfo *AArch64FunctionInfo::clone( diff --git a/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h b/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h index 0b8bfb04a572..219f83cfd32e 100644 --- a/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h +++ b/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h @@ -194,6 +194,8 @@ class AArch64FunctionInfo final : public MachineFunctionInfo { /// True if the function need asynchronous unwind information. mutable std::optional NeedsAsyncDwarfUnwindInfo; + int64_t StackProbeSize = 0; + public: AArch64FunctionInfo(const Function &F, const AArch64Subtarget *STI); @@ -456,6 +458,10 @@ public: HasStreamingModeChanges = HasChanges; } + bool hasStackProbing() const { return StackProbeSize != 0; } + + int64_t getStackProbeSize() const { return StackProbeSize; } + private: // Hold the lists of LOHs. MILOHContainer LOHContainerSet; diff --git a/llvm/test/CodeGen/AArch64/stack-probing-64k.ll b/llvm/test/CodeGen/AArch64/stack-probing-64k.ll new file mode 100644 index 000000000000..945c271d3750 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/stack-probing-64k.ll @@ -0,0 +1,392 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple aarch64-none-eabi < %s -verify-machineinstrs -enable-post-misched=false | FileCheck %s +; RUN: llc -mtriple aarch64-none-eabi < %s -verify-machineinstrs -enable-post-misched=false -global-isel | FileCheck %s + +; Tests for prolog sequences for stack probing, when using a 64KiB stack guard. + +; 64k bytes is the largest frame we can probe in one go. +define void @static_65536(ptr %out) #0 { +; CHECK-LABEL: static_65536: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: sub sp, sp, #16, lsl #12 // =65536 +; CHECK-NEXT: .cfi_def_cfa_offset 65552 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: str x8, [x0] +; CHECK-NEXT: add sp, sp, #16, lsl #12 // =65536 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %v = alloca i8, i64 65536, align 1 + store i8* %v, ptr %out, align 8 + ret void +} + +; 64k+16 bytes, still needs just one probe. +define void @static_65552(ptr %out) #0 { +; CHECK-LABEL: static_65552: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: sub sp, sp, #16, lsl #12 // =65536 +; CHECK-NEXT: .cfi_def_cfa_offset 65552 +; CHECK-NEXT: str xzr, [sp], #-16 +; CHECK-NEXT: .cfi_def_cfa_offset 65568 +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: str x8, [x0] +; CHECK-NEXT: add sp, sp, #16, lsl #12 // =65536 +; CHECK-NEXT: .cfi_def_cfa_offset 32 +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %v = alloca i8, i64 65552, align 1 + store i8* %v, ptr %out, align 8 + ret void +} + +; 64k+1024 bytes, the largest frame which needs just one probe. +define void @static_66560(ptr %out) #0 { +; CHECK-LABEL: static_66560: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: sub sp, sp, #16, lsl #12 // =65536 +; CHECK-NEXT: .cfi_def_cfa_offset 65552 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: sub sp, sp, #1024 +; CHECK-NEXT: .cfi_def_cfa_offset 66576 +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: str x8, [x0] +; CHECK-NEXT: add sp, sp, #16, lsl #12 // =65536 +; CHECK-NEXT: .cfi_def_cfa_offset 1040 +; CHECK-NEXT: add sp, sp, #1024 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %v = alloca i8, i64 66560, align 1 + store i8* %v, ptr %out, align 8 + ret void +} + +; 64k+1024+16 bytes, the smallest frame which needs two probes. +define void @static_66576(ptr %out) #0 { +; CHECK-LABEL: static_66576: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: sub sp, sp, #16, lsl #12 // =65536 +; CHECK-NEXT: .cfi_def_cfa_offset 65552 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: sub sp, sp, #1040 +; CHECK-NEXT: .cfi_def_cfa_offset 66592 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: str x8, [x0] +; CHECK-NEXT: add sp, sp, #16, lsl #12 // =65536 +; CHECK-NEXT: .cfi_def_cfa_offset 1056 +; CHECK-NEXT: add sp, sp, #1040 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %v = alloca i8, i64 66576, align 1 + store i8* %v, ptr %out, align 8 + ret void +} + +; 2*64k+1024, the largest frame needing two probes. +define void @static_132096(ptr %out) #0 { +; CHECK-LABEL: static_132096: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: sub sp, sp, #16, lsl #12 // =65536 +; CHECK-NEXT: .cfi_def_cfa_offset 65552 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: sub sp, sp, #16, lsl #12 // =65536 +; CHECK-NEXT: .cfi_def_cfa_offset 131088 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: sub sp, sp, #1024 +; CHECK-NEXT: .cfi_def_cfa_offset 132112 +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: str x8, [x0] +; CHECK-NEXT: add sp, sp, #32, lsl #12 // =131072 +; CHECK-NEXT: .cfi_def_cfa_offset 1040 +; CHECK-NEXT: add sp, sp, #1024 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %v = alloca i8, i64 132096, align 1 + store i8* %v, ptr %out, align 8 + ret void +} + +; 5*64k-16, the largest frame probed without a loop. +define void @static_327664(ptr %out) #0 { +; CHECK-LABEL: static_327664: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: sub sp, sp, #16, lsl #12 // =65536 +; CHECK-NEXT: .cfi_def_cfa_offset 65552 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: sub sp, sp, #16, lsl #12 // =65536 +; CHECK-NEXT: .cfi_def_cfa_offset 131088 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: sub sp, sp, #16, lsl #12 // =65536 +; CHECK-NEXT: .cfi_def_cfa_offset 196624 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: sub sp, sp, #16, lsl #12 // =65536 +; CHECK-NEXT: .cfi_def_cfa_offset 262160 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: sub sp, sp, #15, lsl #12 // =61440 +; CHECK-NEXT: .cfi_def_cfa_offset 323600 +; CHECK-NEXT: sub sp, sp, #4080 +; CHECK-NEXT: .cfi_def_cfa_offset 327680 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: str x8, [x0] +; CHECK-NEXT: add sp, sp, #79, lsl #12 // =323584 +; CHECK-NEXT: .cfi_def_cfa_offset 4096 +; CHECK-NEXT: add sp, sp, #4080 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %v = alloca i8, i64 327664, align 1 + store i8* %v, ptr %out, align 8 + ret void +} + +; 5*64k, smallest frame probed with a loop. +define void @static_327680(ptr %out) #0 { +; CHECK-LABEL: static_327680: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: sub x9, sp, #80, lsl #12 // =327680 +; CHECK-NEXT: .cfi_def_cfa w9, 327696 +; CHECK-NEXT: .LBB6_1: // %entry +; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: sub sp, sp, #16, lsl #12 // =65536 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: cmp sp, x9 +; CHECK-NEXT: b.ne .LBB6_1 +; CHECK-NEXT: // %bb.2: // %entry +; CHECK-NEXT: .cfi_def_cfa_register wsp +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: str x8, [x0] +; CHECK-NEXT: add sp, sp, #80, lsl #12 // =327680 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %v = alloca i8, i64 327680, align 1 + store i8* %v, ptr %out, align 8 + ret void +} + +; 5*64k+1024, large enough to use a loop, but not a multiple of 64KiB +; so has a reminder, but no extra probe. +define void @static_328704(ptr %out) #0 { +; CHECK-LABEL: static_328704: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: sub x9, sp, #80, lsl #12 // =327680 +; CHECK-NEXT: .cfi_def_cfa w9, 327696 +; CHECK-NEXT: .LBB7_1: // %entry +; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: sub sp, sp, #16, lsl #12 // =65536 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: cmp sp, x9 +; CHECK-NEXT: b.ne .LBB7_1 +; CHECK-NEXT: // %bb.2: // %entry +; CHECK-NEXT: .cfi_def_cfa_register wsp +; CHECK-NEXT: sub sp, sp, #1024 +; CHECK-NEXT: .cfi_def_cfa_offset 328720 +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: str x8, [x0] +; CHECK-NEXT: add sp, sp, #80, lsl #12 // =327680 +; CHECK-NEXT: .cfi_def_cfa_offset 1040 +; CHECK-NEXT: add sp, sp, #1024 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %v = alloca i8, i64 328704, align 1 + store i8* %v, ptr %out, align 8 + ret void +} + +; 5*64k+1040, large enough to use a loop, has a reminder and +; an extra probe. +define void @static_328720(ptr %out) #0 { +; CHECK-LABEL: static_328720: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: sub x9, sp, #80, lsl #12 // =327680 +; CHECK-NEXT: .cfi_def_cfa w9, 327696 +; CHECK-NEXT: .LBB8_1: // %entry +; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: sub sp, sp, #16, lsl #12 // =65536 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: cmp sp, x9 +; CHECK-NEXT: b.ne .LBB8_1 +; CHECK-NEXT: // %bb.2: // %entry +; CHECK-NEXT: .cfi_def_cfa_register wsp +; CHECK-NEXT: sub sp, sp, #1040 +; CHECK-NEXT: .cfi_def_cfa_offset 328736 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: str x8, [x0] +; CHECK-NEXT: add sp, sp, #80, lsl #12 // =327680 +; CHECK-NEXT: .cfi_def_cfa_offset 1056 +; CHECK-NEXT: add sp, sp, #1040 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %v = alloca i8, i64 328720, align 1 + store i8* %v, ptr %out, align 8 + ret void +} + +; A small allocation, but with a very large alignment requirement. We do this +; by moving SP far enough that a sufficiently-aligned block will exist +; somewhere in the stack frame, so must probe the whole of that larger SP move. +define void @static_16_align_131072(ptr %out) #0 { +; CHECK-LABEL: static_16_align_131072: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: mov x29, sp +; CHECK-NEXT: .cfi_def_cfa w29, 16 +; CHECK-NEXT: .cfi_offset w30, -8 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: sub x9, sp, #31, lsl #12 // =126976 +; CHECK-NEXT: sub x9, x9, #4080 +; CHECK-NEXT: and x9, x9, #0xfffffffffffe0000 +; CHECK-NEXT: .LBB9_1: // %entry +; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: sub sp, sp, #16, lsl #12 // =65536 +; CHECK-NEXT: cmp sp, x9 +; CHECK-NEXT: b.le .LBB9_3 +; CHECK-NEXT: // %bb.2: // %entry +; CHECK-NEXT: // in Loop: Header=BB9_1 Depth=1 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: b .LBB9_1 +; CHECK-NEXT: .LBB9_3: // %entry +; CHECK-NEXT: mov sp, x9 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: str x8, [x0] +; CHECK-NEXT: mov sp, x29 +; CHECK-NEXT: .cfi_def_cfa wsp, 16 +; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w30 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %v = alloca i8, i64 16, align 131072 + store i8* %v, ptr %out, align 8 + ret void +} + +; A small allocation, but with a very large alignment requirement which +; is nevertheless small enough as to not need a loop. +define void @static_16_align_8192(ptr %out) #0 { +; CHECK-LABEL: static_16_align_8192: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: mov x29, sp +; CHECK-NEXT: .cfi_def_cfa w29, 16 +; CHECK-NEXT: .cfi_offset w30, -8 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: sub x9, sp, #1, lsl #12 // =4096 +; CHECK-NEXT: sub x9, x9, #4080 +; CHECK-NEXT: and sp, x9, #0xffffffffffffe000 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: str x8, [x0] +; CHECK-NEXT: mov sp, x29 +; CHECK-NEXT: .cfi_def_cfa wsp, 16 +; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w30 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %v = alloca i8, i64 16, align 8192 + store i8* %v, ptr %out, align 8 + ret void +} + +; A large allocation with a very large alignment requirement which +; is nevertheless small enough as to not need a loop. +define void @static_32752_align_32k(ptr %out) #0 { +; CHECK-LABEL: static_32752_align_32k: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: mov x29, sp +; CHECK-NEXT: .cfi_def_cfa w29, 16 +; CHECK-NEXT: .cfi_offset w30, -8 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: sub x9, sp, #7, lsl #12 // =28672 +; CHECK-NEXT: sub x9, x9, #4080 +; CHECK-NEXT: and sp, x9, #0xffffffffffff8000 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: str x8, [x0] +; CHECK-NEXT: mov sp, x29 +; CHECK-NEXT: .cfi_def_cfa wsp, 16 +; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w30 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %v = alloca i8, i64 32752, align 32768 + store i8* %v, ptr %out, align 8 + ret void +} + +attributes #0 = { uwtable(async) "probe-stack"="inline-asm" "stack-probe-size"="65536" "frame-pointer"="none" } diff --git a/llvm/test/CodeGen/AArch64/stack-probing-last-in-block.mir b/llvm/test/CodeGen/AArch64/stack-probing-last-in-block.mir new file mode 100644 index 000000000000..6c8ec7e4c4fa --- /dev/null +++ b/llvm/test/CodeGen/AArch64/stack-probing-last-in-block.mir @@ -0,0 +1,146 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -run-pass=prologepilog %s -o - | FileCheck %s +# Regression test for a crash when the probing instruction +# to replace is last in the block. +--- | + source_filename = "tt.ll" + target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" + target triple = "aarch64-linux" + + declare i1 @g(ptr) + + define void @f(ptr %out) #0 { + entry: + %p = alloca i32, i32 50000, align 4 + br label %loop + + loop: ; preds = %loop, %entry + %c = call i1 @g(ptr %p) + br i1 %c, label %loop, label %exit + + exit: ; preds = %loop + ret void + } + + attributes #0 = { uwtable "frame-pointer"="none" "probe-stack"="inline-asm" "target-features"="+sve" } + +... +--- +name: f +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: true +registers: [] +liveins: [] +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 4 + adjustsStack: true + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 0 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 200000 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: p, type: default, offset: 0, size: 200000, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + local-offset: -200000, debug-info-variable: '', debug-info-expression: '', + debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + ; CHECK-LABEL: name: f + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: liveins: $lr, $fp + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: early-clobber $sp = frame-setup STPXpre killed $fp, killed $lr, $sp, -2 :: (store (s64) into %stack.2), (store (s64) into %stack.1) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $w30, -8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $w29, -16 + ; CHECK-NEXT: $x9 = frame-setup SUBXri $sp, 48, 12 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa $w9, 196624 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.entry: + ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000) + ; CHECK-NEXT: liveins: $x9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $sp = frame-setup SUBXri $sp, 1, 12 + ; CHECK-NEXT: frame-setup STRXui $xzr, $sp, 0 + ; CHECK-NEXT: $xzr = frame-setup SUBSXrx64 $sp, $x9, 24, implicit-def $nzcv + ; CHECK-NEXT: frame-setup Bcc 1, %bb.3, implicit $nzcv + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4.entry: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $wsp + ; CHECK-NEXT: $sp = frame-setup SUBXri $sp, 3392, 0 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 200016 + ; CHECK-NEXT: frame-setup STRXui $xzr, $sp, 0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.loop: + ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x0 = ADDXri $sp, 0, 0 + ; CHECK-NEXT: BL @g, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp, implicit-def $w0 + ; CHECK-NEXT: TBNZW killed renamable $w0, 0, %bb.1 + ; CHECK-NEXT: B %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.exit: + ; CHECK-NEXT: $sp = frame-destroy ADDXri $sp, 48, 12 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 3408 + ; CHECK-NEXT: $sp = frame-destroy ADDXri $sp, 3392, 0 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-NEXT: early-clobber $sp, $fp, $lr = frame-destroy LDPXpost $sp, 2 :: (load (s64) from %stack.2), (load (s64) from %stack.1) + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $w30 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $w29 + ; CHECK-NEXT: RET_ReallyLR + bb.0.entry: + successors: %bb.1(0x80000000) + + + bb.1.loop: + successors: %bb.1(0x7c000000), %bb.2(0x04000000) + + ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp + $x0 = ADDXri %stack.0.p, 0, 0 + BL @g, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp, implicit-def $w0 + ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp + TBNZW killed renamable $w0, 0, %bb.1 + B %bb.2 + + bb.2.exit: + RET_ReallyLR + +... diff --git a/llvm/test/CodeGen/AArch64/stack-probing-sve.ll b/llvm/test/CodeGen/AArch64/stack-probing-sve.ll new file mode 100644 index 000000000000..4dad104e66f2 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/stack-probing-sve.ll @@ -0,0 +1,724 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple aarch64-none-eabi < %s -verify-machineinstrs | FileCheck %s +; RUN: llc -mtriple aarch64-none-eabi < %s -verify-machineinstrs -global-isel -global-isel-abort=2 | FileCheck %s + +; Test prolog sequences for stack probing when SVE objects are involved. + +; The space for SVE objects needs probing in the general case, because +; the stack adjustment may happen to be too big (i.e. greater than the +; probe size) to allocate with a single `addvl`. +; When we do know that the stack adjustment cannot exceed the probe size +; we can avoid emitting a probe loop and emit a simple `addvl; str` +; sequence instead. + +define void @sve_1_vector(ptr %out) #0 { +; CHECK-LABEL: sve_1_vector: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: addvl sp, sp, #-1 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG +; CHECK-NEXT: addvl sp, sp, #1 +; CHECK-NEXT: .cfi_def_cfa wsp, 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %vec = alloca , align 16 + ret void +} + +; As above, but with 4 SVE vectors of stack space. +define void @sve_4_vector(ptr %out) #0 { +; CHECK-LABEL: sve_4_vector: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: addvl sp, sp, #-4 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 32 * VG +; CHECK-NEXT: addvl sp, sp, #4 +; CHECK-NEXT: .cfi_def_cfa wsp, 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %vec1 = alloca , align 16 + %vec2 = alloca , align 16 + %vec3 = alloca , align 16 + %vec4 = alloca , align 16 + ret void +} + +; As above, but with 16 SVE vectors of stack space. +; The stack adjustment is less than or equal to 16 x 256 = 4096, so +; we can allocate the locals at once. +define void @sve_16_vector(ptr %out) #0 { +; CHECK-LABEL: sve_16_vector: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: addvl sp, sp, #-16 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x80, 0x01, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 128 * VG +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: addvl sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa wsp, 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %vec1 = alloca , align 16 + %vec2 = alloca , align 16 + %vec3 = alloca , align 16 + %vec4 = alloca , align 16 + %vec5 = alloca , align 16 + %vec6 = alloca , align 16 + %vec7 = alloca , align 16 + %vec8 = alloca , align 16 + %vec9 = alloca , align 16 + %vec10 = alloca , align 16 + %vec11 = alloca , align 16 + %vec12 = alloca , align 16 + %vec13 = alloca , align 16 + %vec14 = alloca , align 16 + %vec15 = alloca , align 16 + %vec16 = alloca , align 16 + ret void +} + +; As above, but with 17 SVE vectors of stack space. Now we need +; a probing loops since stack adjustment may be greater than +; the probe size (17 x 256 = 4354 bytes) +; TODO: Allocating `k*16+r` SVE vectors can be unrolled into +; emiting the `k + r` sequences of `addvl sp, sp, #-N; str xzr, [sp]` +define void @sve_17_vector(ptr %out) #0 { +; CHECK-LABEL: sve_17_vector: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: addvl x9, sp, #-17 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x79, 0x00, 0x11, 0x10, 0x22, 0x11, 0x88, 0x01, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $x9 + 16 + 136 * VG +; CHECK-NEXT: .LBB3_1: // %entry +; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: sub sp, sp, #1, lsl #12 // =4096 +; CHECK-NEXT: cmp sp, x9 +; CHECK-NEXT: b.le .LBB3_3 +; CHECK-NEXT: // %bb.2: // %entry +; CHECK-NEXT: // in Loop: Header=BB3_1 Depth=1 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: b .LBB3_1 +; CHECK-NEXT: .LBB3_3: // %entry +; CHECK-NEXT: mov sp, x9 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: .cfi_def_cfa_register wsp +; CHECK-NEXT: addvl sp, sp, #17 +; CHECK-NEXT: .cfi_def_cfa wsp, 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %vec1 = alloca , align 16 + %vec2 = alloca , align 16 + %vec3 = alloca , align 16 + %vec4 = alloca , align 16 + %vec5 = alloca , align 16 + %vec6 = alloca , align 16 + %vec7 = alloca , align 16 + %vec8 = alloca , align 16 + %vec9 = alloca , align 16 + %vec10 = alloca , align 16 + %vec11 = alloca , align 16 + %vec12 = alloca , align 16 + %vec13 = alloca , align 16 + %vec14 = alloca , align 16 + %vec15 = alloca , align 16 + %vec16 = alloca , align 16 + %vec17 = alloca , align 16 + ret void +} + +; Space for callee-saved SVE register is allocated similarly to allocating +; space for SVE locals. When we know the stack adjustment cannot exceed the +; probe size we can skip the explict probe, since saving SVE registers serves +; as an implicit probe. +define void @sve_1v_csr( %a) #0 { +; CHECK-LABEL: sve_1v_csr: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: addvl sp, sp, #-1 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG +; CHECK-NEXT: str z8, [sp] // 16-byte Folded Spill +; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x78, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d8 @ cfa - 16 - 8 * VG +; CHECK-NEXT: //APP +; CHECK-NEXT: //NO_APP +; CHECK-NEXT: ldr z8, [sp] // 16-byte Folded Reload +; CHECK-NEXT: addvl sp, sp, #1 +; CHECK-NEXT: .cfi_def_cfa wsp, 16 +; CHECK-NEXT: .cfi_restore z8 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + call void asm sideeffect "", "~{z8}" () + ret void +} + +define void @sve_4v_csr( %a) #0 { +; CHECK-LABEL: sve_4v_csr: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: addvl sp, sp, #-4 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 32 * VG +; CHECK-NEXT: str z11, [sp] // 16-byte Folded Spill +; CHECK-NEXT: str z10, [sp, #1, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z9, [sp, #2, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z8, [sp, #3, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x78, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d8 @ cfa - 16 - 8 * VG +; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x70, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d9 @ cfa - 16 - 16 * VG +; CHECK-NEXT: .cfi_escape 0x10, 0x4a, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x68, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d10 @ cfa - 16 - 24 * VG +; CHECK-NEXT: .cfi_escape 0x10, 0x4b, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x60, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d11 @ cfa - 16 - 32 * VG +; CHECK-NEXT: //APP +; CHECK-NEXT: //NO_APP +; CHECK-NEXT: ldr z11, [sp] // 16-byte Folded Reload +; CHECK-NEXT: ldr z10, [sp, #1, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z9, [sp, #2, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z8, [sp, #3, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: addvl sp, sp, #4 +; CHECK-NEXT: .cfi_def_cfa wsp, 16 +; CHECK-NEXT: .cfi_restore z8 +; CHECK-NEXT: .cfi_restore z9 +; CHECK-NEXT: .cfi_restore z10 +; CHECK-NEXT: .cfi_restore z11 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + call void asm sideeffect "", "~{z8},~{z9},~{z10},~{z11}" () + ret void +} + +define void @sve_16v_csr( %a) #0 { +; CHECK-LABEL: sve_16v_csr: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: addvl sp, sp, #-16 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x80, 0x01, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 128 * VG +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: str z23, [sp] // 16-byte Folded Spill +; CHECK-NEXT: str z22, [sp, #1, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z21, [sp, #2, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z20, [sp, #3, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z19, [sp, #4, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z18, [sp, #5, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z17, [sp, #6, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z16, [sp, #7, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z15, [sp, #8, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z14, [sp, #9, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z13, [sp, #10, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z12, [sp, #11, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z11, [sp, #12, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z10, [sp, #13, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z9, [sp, #14, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z8, [sp, #15, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x78, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d8 @ cfa - 16 - 8 * VG +; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x70, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d9 @ cfa - 16 - 16 * VG +; CHECK-NEXT: .cfi_escape 0x10, 0x4a, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x68, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d10 @ cfa - 16 - 24 * VG +; CHECK-NEXT: .cfi_escape 0x10, 0x4b, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x60, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d11 @ cfa - 16 - 32 * VG +; CHECK-NEXT: .cfi_escape 0x10, 0x4c, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x58, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d12 @ cfa - 16 - 40 * VG +; CHECK-NEXT: .cfi_escape 0x10, 0x4d, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x50, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d13 @ cfa - 16 - 48 * VG +; CHECK-NEXT: .cfi_escape 0x10, 0x4e, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x48, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d14 @ cfa - 16 - 56 * VG +; CHECK-NEXT: .cfi_escape 0x10, 0x4f, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x40, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d15 @ cfa - 16 - 64 * VG +; CHECK-NEXT: //APP +; CHECK-NEXT: //NO_APP +; CHECK-NEXT: ldr z23, [sp] // 16-byte Folded Reload +; CHECK-NEXT: ldr z22, [sp, #1, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z21, [sp, #2, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z20, [sp, #3, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z19, [sp, #4, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z18, [sp, #5, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z17, [sp, #6, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z16, [sp, #7, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z15, [sp, #8, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z14, [sp, #9, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z13, [sp, #10, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z12, [sp, #11, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z11, [sp, #12, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z10, [sp, #13, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z9, [sp, #14, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z8, [sp, #15, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: addvl sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa wsp, 16 +; CHECK-NEXT: .cfi_restore z8 +; CHECK-NEXT: .cfi_restore z9 +; CHECK-NEXT: .cfi_restore z10 +; CHECK-NEXT: .cfi_restore z11 +; CHECK-NEXT: .cfi_restore z12 +; CHECK-NEXT: .cfi_restore z13 +; CHECK-NEXT: .cfi_restore z14 +; CHECK-NEXT: .cfi_restore z15 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + call void asm sideeffect "", "~{z8},~{z9},~{z10},~{z11},~{z12},~{z13},~{z14},~{z15},~{z16},~{z17},~{z18},~{z19},~{z20},~{z21},~{z22},~{z23}" () + ret void +} + +define void @sve_1p_csr( %a) #0 { +; CHECK-LABEL: sve_1p_csr: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: addvl sp, sp, #-1 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG +; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Folded Spill +; CHECK-NEXT: //APP +; CHECK-NEXT: //NO_APP +; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Folded Reload +; CHECK-NEXT: addvl sp, sp, #1 +; CHECK-NEXT: .cfi_def_cfa wsp, 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + call void asm sideeffect "", "~{p8}" () + ret void +} + +define void @sve_4p_csr( %a) #0 { +; CHECK-LABEL: sve_4p_csr: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: addvl sp, sp, #-1 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG +; CHECK-NEXT: str p11, [sp, #4, mul vl] // 2-byte Folded Spill +; CHECK-NEXT: str p10, [sp, #5, mul vl] // 2-byte Folded Spill +; CHECK-NEXT: str p9, [sp, #6, mul vl] // 2-byte Folded Spill +; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Folded Spill +; CHECK-NEXT: //APP +; CHECK-NEXT: //NO_APP +; CHECK-NEXT: ldr p11, [sp, #4, mul vl] // 2-byte Folded Reload +; CHECK-NEXT: ldr p10, [sp, #5, mul vl] // 2-byte Folded Reload +; CHECK-NEXT: ldr p9, [sp, #6, mul vl] // 2-byte Folded Reload +; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Folded Reload +; CHECK-NEXT: addvl sp, sp, #1 +; CHECK-NEXT: .cfi_def_cfa wsp, 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + call void asm sideeffect "", "~{p8},~{p9},~{p10},~{p11}" () + ret void +} + +define void @sve_16v_1p_csr( %a) #0 { +; CHECK-LABEL: sve_16v_1p_csr: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: addvl x9, sp, #-17 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x79, 0x00, 0x11, 0x10, 0x22, 0x11, 0x88, 0x01, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $x9 + 16 + 136 * VG +; CHECK-NEXT: .LBB9_1: // %entry +; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: sub sp, sp, #1, lsl #12 // =4096 +; CHECK-NEXT: cmp sp, x9 +; CHECK-NEXT: b.le .LBB9_3 +; CHECK-NEXT: // %bb.2: // %entry +; CHECK-NEXT: // in Loop: Header=BB9_1 Depth=1 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: b .LBB9_1 +; CHECK-NEXT: .LBB9_3: // %entry +; CHECK-NEXT: mov sp, x9 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: .cfi_def_cfa_register wsp +; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Folded Spill +; CHECK-NEXT: str z23, [sp, #1, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z22, [sp, #2, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z21, [sp, #3, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z20, [sp, #4, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z19, [sp, #5, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z18, [sp, #6, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z17, [sp, #7, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z16, [sp, #8, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z15, [sp, #9, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z14, [sp, #10, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z13, [sp, #11, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z12, [sp, #12, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z11, [sp, #13, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z10, [sp, #14, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z9, [sp, #15, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z8, [sp, #16, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x78, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d8 @ cfa - 16 - 8 * VG +; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x70, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d9 @ cfa - 16 - 16 * VG +; CHECK-NEXT: .cfi_escape 0x10, 0x4a, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x68, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d10 @ cfa - 16 - 24 * VG +; CHECK-NEXT: .cfi_escape 0x10, 0x4b, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x60, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d11 @ cfa - 16 - 32 * VG +; CHECK-NEXT: .cfi_escape 0x10, 0x4c, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x58, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d12 @ cfa - 16 - 40 * VG +; CHECK-NEXT: .cfi_escape 0x10, 0x4d, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x50, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d13 @ cfa - 16 - 48 * VG +; CHECK-NEXT: .cfi_escape 0x10, 0x4e, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x48, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d14 @ cfa - 16 - 56 * VG +; CHECK-NEXT: .cfi_escape 0x10, 0x4f, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x40, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d15 @ cfa - 16 - 64 * VG +; CHECK-NEXT: //APP +; CHECK-NEXT: //NO_APP +; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Folded Reload +; CHECK-NEXT: ldr z23, [sp, #1, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z22, [sp, #2, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z21, [sp, #3, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z20, [sp, #4, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z19, [sp, #5, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z18, [sp, #6, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z17, [sp, #7, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z16, [sp, #8, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z15, [sp, #9, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z14, [sp, #10, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z13, [sp, #11, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z12, [sp, #12, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z11, [sp, #13, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z10, [sp, #14, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z9, [sp, #15, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z8, [sp, #16, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: addvl sp, sp, #17 +; CHECK-NEXT: .cfi_def_cfa wsp, 16 +; CHECK-NEXT: .cfi_restore z8 +; CHECK-NEXT: .cfi_restore z9 +; CHECK-NEXT: .cfi_restore z10 +; CHECK-NEXT: .cfi_restore z11 +; CHECK-NEXT: .cfi_restore z12 +; CHECK-NEXT: .cfi_restore z13 +; CHECK-NEXT: .cfi_restore z14 +; CHECK-NEXT: .cfi_restore z15 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + call void asm sideeffect "", "~{p8},~{z8},~{z9},~{z10},~{z11},~{z12},~{z13},~{z14},~{z15},~{z16},~{z17},~{z18},~{z19},~{z20},~{z21},~{z22},~{z23}" () + ret void +} + +; A SVE vector and a 16-byte fixed size object. +define void @sve_1_vector_16_arr(ptr %out) #0 { +; CHECK-LABEL: sve_1_vector_16_arr: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 32 +; CHECK-NEXT: addvl sp, sp, #-1 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x20, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 32 + 8 * VG +; CHECK-NEXT: addvl sp, sp, #1 +; CHECK-NEXT: .cfi_def_cfa wsp, 32 +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %vec = alloca , align 16 + %arr = alloca i8, i64 16, align 1 + ret void +} + +; A large SVE stack object and a large stack slot, both of which need probing. +; TODO: This could be optimised by combining the fixed-size offset into the +; loop. +define void @sve_1_vector_4096_arr(ptr %out) #0 { +; CHECK-LABEL: sve_1_vector_4096_arr: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: sub x9, sp, #3, lsl #12 // =12288 +; CHECK-NEXT: .cfi_def_cfa w9, 12304 +; CHECK-NEXT: addvl x9, x9, #-32 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0f, 0x79, 0x00, 0x11, 0x90, 0xe0, 0x00, 0x22, 0x11, 0x80, 0x02, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $x9 + 12304 + 256 * VG +; CHECK-NEXT: addvl x9, x9, #-32 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0f, 0x79, 0x00, 0x11, 0x90, 0xe0, 0x00, 0x22, 0x11, 0x80, 0x04, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $x9 + 12304 + 512 * VG +; CHECK-NEXT: .LBB11_1: // %entry +; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: sub sp, sp, #1, lsl #12 // =4096 +; CHECK-NEXT: cmp sp, x9 +; CHECK-NEXT: b.le .LBB11_3 +; CHECK-NEXT: // %bb.2: // %entry +; CHECK-NEXT: // in Loop: Header=BB11_1 Depth=1 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: b .LBB11_1 +; CHECK-NEXT: .LBB11_3: // %entry +; CHECK-NEXT: mov sp, x9 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: .cfi_def_cfa_register wsp +; CHECK-NEXT: addvl sp, sp, #31 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0f, 0x8f, 0x00, 0x11, 0x90, 0xe0, 0x00, 0x22, 0x11, 0x88, 0x02, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 12304 + 264 * VG +; CHECK-NEXT: addvl sp, sp, #31 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0e, 0x8f, 0x00, 0x11, 0x90, 0xe0, 0x00, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 12304 + 16 * VG +; CHECK-NEXT: addvl sp, sp, #2 +; CHECK-NEXT: .cfi_def_cfa wsp, 12304 +; CHECK-NEXT: add sp, sp, #3, lsl #12 // =12288 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %vec = alloca , align 16 + %arr = alloca i8, i64 12288, align 1 + ret void +} + +; Not tested: SVE stack objects with alignment >16 bytes, which isn't currently +; supported even without stack-probing. + +; An SVE vector, and a 16-byte fixed size object, which +; has a large alignment requirement. +define void @sve_1_vector_16_arr_align_8192(ptr %out) #0 { +; CHECK-LABEL: sve_1_vector_16_arr_align_8192: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: mov x29, sp +; CHECK-NEXT: .cfi_def_cfa w29, 16 +; CHECK-NEXT: .cfi_offset w30, -8 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: sub x9, sp, #1, lsl #12 // =4096 +; CHECK-NEXT: sub x9, x9, #4080 +; CHECK-NEXT: addvl x9, x9, #-1 +; CHECK-NEXT: and x9, x9, #0xffffffffffffe000 +; CHECK-NEXT: .LBB12_1: // %entry +; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: sub sp, sp, #1, lsl #12 // =4096 +; CHECK-NEXT: cmp sp, x9 +; CHECK-NEXT: b.le .LBB12_3 +; CHECK-NEXT: // %bb.2: // %entry +; CHECK-NEXT: // in Loop: Header=BB12_1 Depth=1 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: b .LBB12_1 +; CHECK-NEXT: .LBB12_3: // %entry +; CHECK-NEXT: mov sp, x9 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: mov sp, x29 +; CHECK-NEXT: .cfi_def_cfa wsp, 16 +; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w30 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %vec = alloca , align 16 + %arr = alloca i8, i64 16, align 8192 + ret void +} + +; With 64k guard pages, we can allocate bigger SVE space without a probing loop. +define void @sve_1024_64k_guard(ptr %out) #0 "stack-probe-size"="65536" { +; CHECK-LABEL: sve_1024_64k_guard: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: addvl sp, sp, #-32 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x80, 0x02, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 256 * VG +; CHECK-NEXT: addvl sp, sp, #-32 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x80, 0x04, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 512 * VG +; CHECK-NEXT: addvl sp, sp, #-32 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x80, 0x06, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 768 * VG +; CHECK-NEXT: addvl sp, sp, #-32 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x80, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 1024 * VG +; CHECK-NEXT: addvl sp, sp, #-32 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x80, 0x0a, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 1280 * VG +; CHECK-NEXT: addvl sp, sp, #-32 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x80, 0x0c, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 1536 * VG +; CHECK-NEXT: addvl sp, sp, #-32 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x80, 0x0e, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 1792 * VG +; CHECK-NEXT: addvl sp, sp, #-32 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x80, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 2048 * VG +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: addvl sp, sp, #31 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x88, 0x0e, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 1800 * VG +; CHECK-NEXT: addvl sp, sp, #31 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x90, 0x0c, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 1552 * VG +; CHECK-NEXT: addvl sp, sp, #31 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x98, 0x0a, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 1304 * VG +; CHECK-NEXT: addvl sp, sp, #31 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0xa0, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 1056 * VG +; CHECK-NEXT: addvl sp, sp, #31 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0xa8, 0x06, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 808 * VG +; CHECK-NEXT: addvl sp, sp, #31 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0xb0, 0x04, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 560 * VG +; CHECK-NEXT: addvl sp, sp, #31 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0xb8, 0x02, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 312 * VG +; CHECK-NEXT: addvl sp, sp, #31 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0xc0, 0x00, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 64 * VG +; CHECK-NEXT: addvl sp, sp, #8 +; CHECK-NEXT: .cfi_def_cfa wsp, 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %vec = alloca , align 16 + ret void +} + +define void @sve_1028_64k_guard(ptr %out) #0 "stack-probe-size"="65536" { +; CHECK-LABEL: sve_1028_64k_guard: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: addvl x9, sp, #-32 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x79, 0x00, 0x11, 0x10, 0x22, 0x11, 0x80, 0x02, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $x9 + 16 + 256 * VG +; CHECK-NEXT: addvl x9, x9, #-32 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x79, 0x00, 0x11, 0x10, 0x22, 0x11, 0x80, 0x04, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $x9 + 16 + 512 * VG +; CHECK-NEXT: addvl x9, x9, #-32 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x79, 0x00, 0x11, 0x10, 0x22, 0x11, 0x80, 0x06, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $x9 + 16 + 768 * VG +; CHECK-NEXT: addvl x9, x9, #-32 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x79, 0x00, 0x11, 0x10, 0x22, 0x11, 0x80, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $x9 + 16 + 1024 * VG +; CHECK-NEXT: addvl x9, x9, #-32 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x79, 0x00, 0x11, 0x10, 0x22, 0x11, 0x80, 0x0a, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $x9 + 16 + 1280 * VG +; CHECK-NEXT: addvl x9, x9, #-32 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x79, 0x00, 0x11, 0x10, 0x22, 0x11, 0x80, 0x0c, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $x9 + 16 + 1536 * VG +; CHECK-NEXT: addvl x9, x9, #-32 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x79, 0x00, 0x11, 0x10, 0x22, 0x11, 0x80, 0x0e, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $x9 + 16 + 1792 * VG +; CHECK-NEXT: addvl x9, x9, #-32 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x79, 0x00, 0x11, 0x10, 0x22, 0x11, 0x80, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $x9 + 16 + 2048 * VG +; CHECK-NEXT: addvl x9, x9, #-1 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x79, 0x00, 0x11, 0x10, 0x22, 0x11, 0x88, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $x9 + 16 + 2056 * VG +; CHECK-NEXT: .LBB14_1: // %entry +; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: sub sp, sp, #16, lsl #12 // =65536 +; CHECK-NEXT: cmp sp, x9 +; CHECK-NEXT: b.le .LBB14_3 +; CHECK-NEXT: // %bb.2: // %entry +; CHECK-NEXT: // in Loop: Header=BB14_1 Depth=1 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: b .LBB14_1 +; CHECK-NEXT: .LBB14_3: // %entry +; CHECK-NEXT: mov sp, x9 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: .cfi_def_cfa_register wsp +; CHECK-NEXT: addvl sp, sp, #31 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x90, 0x0e, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 1808 * VG +; CHECK-NEXT: addvl sp, sp, #31 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x98, 0x0c, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 1560 * VG +; CHECK-NEXT: addvl sp, sp, #31 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0xa0, 0x0a, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 1312 * VG +; CHECK-NEXT: addvl sp, sp, #31 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0xa8, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 1064 * VG +; CHECK-NEXT: addvl sp, sp, #31 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0xb0, 0x06, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 816 * VG +; CHECK-NEXT: addvl sp, sp, #31 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0xb8, 0x04, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 568 * VG +; CHECK-NEXT: addvl sp, sp, #31 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0xc0, 0x02, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 320 * VG +; CHECK-NEXT: addvl sp, sp, #31 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0xc8, 0x00, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 72 * VG +; CHECK-NEXT: addvl sp, sp, #9 +; CHECK-NEXT: .cfi_def_cfa wsp, 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %vec = alloca , align 16 + %vec1 = alloca , align 16 + ret void +} + +; With 5 SVE vectors of stack space the unprobed area +; at the top of the stack can exceed 1024 bytes (5 x 256 == 1280), +; hence we need to issue a probe. +define void @sve_5_vector(ptr %out) #0 { +; CHECK-LABEL: sve_5_vector: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: addvl sp, sp, #-5 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 40 * VG +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: addvl sp, sp, #5 +; CHECK-NEXT: .cfi_def_cfa wsp, 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %vec1 = alloca , align 16 + %vec2 = alloca , align 16 + %vec3 = alloca , align 16 + %vec4 = alloca , align 16 + %vec5 = alloca , align 16 + ret void +} + +; Test with a 14 scalable bytes (so up to 14 * 16 = 224) of unprobed +; are bellow the save location of `p9`. +define void @sve_unprobed_area( %a, i32 %n) #0 { +; CHECK-LABEL: sve_unprobed_area: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: addvl sp, sp, #-4 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 32 * VG +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: str p9, [sp, #7, mul vl] // 2-byte Folded Spill +; CHECK-NEXT: str z10, [sp, #1, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z9, [sp, #2, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z8, [sp, #3, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x78, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d8 @ cfa - 16 - 8 * VG +; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x70, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d9 @ cfa - 16 - 16 * VG +; CHECK-NEXT: .cfi_escape 0x10, 0x4a, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x68, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d10 @ cfa - 16 - 24 * VG +; CHECK-NEXT: addvl sp, sp, #-4 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0xc0, 0x00, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 64 * VG +; CHECK-NEXT: //APP +; CHECK-NEXT: //NO_APP +; CHECK-NEXT: addvl sp, sp, #4 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 32 * VG +; CHECK-NEXT: ldr p9, [sp, #7, mul vl] // 2-byte Folded Reload +; CHECK-NEXT: ldr z10, [sp, #1, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z9, [sp, #2, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z8, [sp, #3, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: addvl sp, sp, #4 +; CHECK-NEXT: .cfi_def_cfa wsp, 16 +; CHECK-NEXT: .cfi_restore z8 +; CHECK-NEXT: .cfi_restore z9 +; CHECK-NEXT: .cfi_restore z10 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + call void asm sideeffect "", "~{z8},~{z9},~{z10},~{p9}" () + + %v0 = alloca , align 16 + %v1 = alloca , align 16 + %v2 = alloca , align 16 + %v3 = alloca , align 16 + + ret void +} + +attributes #0 = { uwtable(async) "probe-stack"="inline-asm" "frame-pointer"="none" "target-features"="+sve" } diff --git a/llvm/test/CodeGen/AArch64/stack-probing.ll b/llvm/test/CodeGen/AArch64/stack-probing.ll new file mode 100644 index 000000000000..5c5d9321a56e --- /dev/null +++ b/llvm/test/CodeGen/AArch64/stack-probing.ll @@ -0,0 +1,539 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple aarch64-none-eabi < %s -verify-machineinstrs -enable-post-misched=false | FileCheck %s +; RUN: llc -mtriple aarch64-none-eabi < %s -verify-machineinstrs -enable-post-misched=false -global-isel | FileCheck %s + +; Tests for prolog sequences for stack probing, when using a 4KiB stack guard. + +; The stack probing parameters in function attributes take precedence over +; ones in the module flags. + +; Small stack frame, no probing required. +define void @static_64(ptr %out) #0 { +; CHECK-LABEL: static_64: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: sub sp, sp, #64 +; CHECK-NEXT: .cfi_def_cfa_offset 64 +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: str x8, [x0] +; CHECK-NEXT: add sp, sp, #64 +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: ret +entry: + %v = alloca i8, i64 64, align 1 + store ptr %v, ptr %out, align 8 + ret void +} + +; At 256 bytes we start to always create a frame pointer. No frame smaller then +; this needs a probe, so we can use the saving of at least one CSR as a probe +; at the top of our frame. +define void @static_256(ptr %out) #0 { +; CHECK-LABEL: static_256: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: sub sp, sp, #272 +; CHECK-NEXT: .cfi_def_cfa_offset 272 +; CHECK-NEXT: str x29, [sp, #256] // 8-byte Folded Spill +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: str x8, [x0] +; CHECK-NEXT: add sp, sp, #272 +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %v = alloca i8, i64 256, align 1 + store ptr %v, ptr %out, align 8 + ret void +} + +; At 1024 bytes, this is the largest frame which doesn't need probing. +define void @static_1024(ptr %out) #0 { +; CHECK-LABEL: static_1024: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: sub sp, sp, #1024 +; CHECK-NEXT: .cfi_def_cfa_offset 1040 +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: str x8, [x0] +; CHECK-NEXT: add sp, sp, #1024 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %v = alloca i8, i64 1024, align 1 + store ptr %v, ptr %out, align 8 + ret void +} + +; At 1024+16 bytes, this is the smallest frame which needs probing. +define void @static_1040(ptr %out) #0 { +; CHECK-LABEL: static_1040: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: sub sp, sp, #1040 +; CHECK-NEXT: .cfi_def_cfa_offset 1056 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: str x8, [x0] +; CHECK-NEXT: add sp, sp, #1040 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %v = alloca i8, i64 1040, align 1 + store ptr %v, ptr %out, align 8 + ret void +} + +; 4k bytes is the largest frame we can probe in one go. +define void @static_4096(ptr %out) #0 { +; CHECK-LABEL: static_4096: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: sub sp, sp, #1, lsl #12 // =4096 +; CHECK-NEXT: .cfi_def_cfa_offset 4112 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: str x8, [x0] +; CHECK-NEXT: add sp, sp, #1, lsl #12 // =4096 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %v = alloca i8, i64 4096, align 1 + store ptr %v, ptr %out, align 8 + ret void +} + +; 4k+16 bytes, still needs just one probe. +define void @static_4112(ptr %out) #0 { +; CHECK-LABEL: static_4112: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: sub sp, sp, #1, lsl #12 // =4096 +; CHECK-NEXT: .cfi_def_cfa_offset 4112 +; CHECK-NEXT: str xzr, [sp], #-16 +; CHECK-NEXT: .cfi_def_cfa_offset 4128 +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: str x8, [x0] +; CHECK-NEXT: add sp, sp, #1, lsl #12 // =4096 +; CHECK-NEXT: .cfi_def_cfa_offset 32 +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %v = alloca i8, i64 4112, align 1 + store ptr %v, ptr %out, align 8 + ret void +} + +; 4k+1024 bytes, the largest frame which needs just one probe. +define void @static_5120(ptr %out) #0 { +; CHECK-LABEL: static_5120: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: sub sp, sp, #1, lsl #12 // =4096 +; CHECK-NEXT: .cfi_def_cfa_offset 4112 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: sub sp, sp, #1024 +; CHECK-NEXT: .cfi_def_cfa_offset 5136 +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: str x8, [x0] +; CHECK-NEXT: add sp, sp, #1, lsl #12 // =4096 +; CHECK-NEXT: .cfi_def_cfa_offset 1040 +; CHECK-NEXT: add sp, sp, #1024 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %v = alloca i8, i64 5120, align 1 + store ptr %v, ptr %out, align 8 + ret void +} + +; 4k+1024+16, the smallest frame which needs two probes. +define void @static_5136(ptr %out) #0 { +; CHECK-LABEL: static_5136: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: sub sp, sp, #1, lsl #12 // =4096 +; CHECK-NEXT: .cfi_def_cfa_offset 4112 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: sub sp, sp, #1040 +; CHECK-NEXT: .cfi_def_cfa_offset 5152 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: str x8, [x0] +; CHECK-NEXT: add sp, sp, #1, lsl #12 // =4096 +; CHECK-NEXT: .cfi_def_cfa_offset 1056 +; CHECK-NEXT: add sp, sp, #1040 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %v = alloca i8, i64 5136, align 1 + store ptr %v, ptr %out, align 8 + ret void +} + +; 2*4k+1024, the largest frame needing two probes +define void @static_9216(ptr %out) #0 { +; CHECK-LABEL: static_9216: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: sub sp, sp, #1, lsl #12 // =4096 +; CHECK-NEXT: .cfi_def_cfa_offset 4112 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: sub sp, sp, #1, lsl #12 // =4096 +; CHECK-NEXT: .cfi_def_cfa_offset 8208 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: sub sp, sp, #1024 +; CHECK-NEXT: .cfi_def_cfa_offset 9232 +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: str x8, [x0] +; CHECK-NEXT: add sp, sp, #2, lsl #12 // =8192 +; CHECK-NEXT: .cfi_def_cfa_offset 1040 +; CHECK-NEXT: add sp, sp, #1024 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %v = alloca i8, i64 9216, align 1 + store ptr %v, ptr %out, align 8 + ret void +} + +; 5*4k-16, the largest frame probed without a loop +define void @static_20464(ptr %out) #0 { +; CHECK-LABEL: static_20464: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: sub sp, sp, #1, lsl #12 // =4096 +; CHECK-NEXT: .cfi_def_cfa_offset 4112 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: sub sp, sp, #1, lsl #12 // =4096 +; CHECK-NEXT: .cfi_def_cfa_offset 8208 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: sub sp, sp, #1, lsl #12 // =4096 +; CHECK-NEXT: .cfi_def_cfa_offset 12304 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: sub sp, sp, #1, lsl #12 // =4096 +; CHECK-NEXT: .cfi_def_cfa_offset 16400 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: sub sp, sp, #4080 +; CHECK-NEXT: .cfi_def_cfa_offset 20480 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: str x8, [x0] +; CHECK-NEXT: add sp, sp, #4, lsl #12 // =16384 +; CHECK-NEXT: .cfi_def_cfa_offset 4096 +; CHECK-NEXT: add sp, sp, #4080 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %v = alloca i8, i64 20464, align 1 + store ptr %v, ptr %out, align 8 + ret void +} + +; 5*4k, the smallest frame probed with a loop +define void @static_20480(ptr %out) #0 { +; CHECK-LABEL: static_20480: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: sub x9, sp, #5, lsl #12 // =20480 +; CHECK-NEXT: .cfi_def_cfa w9, 20496 +; CHECK-NEXT: .LBB10_1: // %entry +; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: sub sp, sp, #1, lsl #12 // =4096 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: cmp sp, x9 +; CHECK-NEXT: b.ne .LBB10_1 +; CHECK-NEXT: // %bb.2: // %entry +; CHECK-NEXT: .cfi_def_cfa_register wsp +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: str x8, [x0] +; CHECK-NEXT: add sp, sp, #5, lsl #12 // =20480 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %v = alloca i8, i64 20480, align 1 + store ptr %v, ptr %out, align 8 + ret void +} + +; 5*4k + 1024, large enough to use a loop, but not a multiple of 4KiB +; so has a reminder, but no extra probe. +define void @static_21504(ptr %out) #0 { +; CHECK-LABEL: static_21504: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: sub x9, sp, #5, lsl #12 // =20480 +; CHECK-NEXT: .cfi_def_cfa w9, 20496 +; CHECK-NEXT: .LBB11_1: // %entry +; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: sub sp, sp, #1, lsl #12 // =4096 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: cmp sp, x9 +; CHECK-NEXT: b.ne .LBB11_1 +; CHECK-NEXT: // %bb.2: // %entry +; CHECK-NEXT: .cfi_def_cfa_register wsp +; CHECK-NEXT: sub sp, sp, #1024 +; CHECK-NEXT: .cfi_def_cfa_offset 21520 +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: str x8, [x0] +; CHECK-NEXT: add sp, sp, #5, lsl #12 // =20480 +; CHECK-NEXT: .cfi_def_cfa_offset 1040 +; CHECK-NEXT: add sp, sp, #1024 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %v = alloca i8, i64 21504, align 1 + store ptr %v, ptr %out, align 8 + ret void +} + +; 5*4k+1040, large enough to use a loop, has a reminder and +; an extra probe. +define void @static_21520(ptr %out) #0 { +; CHECK-LABEL: static_21520: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: sub x9, sp, #5, lsl #12 // =20480 +; CHECK-NEXT: .cfi_def_cfa w9, 20496 +; CHECK-NEXT: .LBB12_1: // %entry +; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: sub sp, sp, #1, lsl #12 // =4096 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: cmp sp, x9 +; CHECK-NEXT: b.ne .LBB12_1 +; CHECK-NEXT: // %bb.2: // %entry +; CHECK-NEXT: .cfi_def_cfa_register wsp +; CHECK-NEXT: sub sp, sp, #1040 +; CHECK-NEXT: .cfi_def_cfa_offset 21536 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: str x8, [x0] +; CHECK-NEXT: add sp, sp, #5, lsl #12 // =20480 +; CHECK-NEXT: .cfi_def_cfa_offset 1056 +; CHECK-NEXT: add sp, sp, #1040 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %v = alloca i8, i64 21520, align 1 + store ptr %v, ptr %out, align 8 + ret void +} + +; A small allocation, but with a very large alignment requirement. We do this +; by moving SP far enough that a sufficiently-aligned block will exist +; somewhere in the stack frame, so must probe the whole of that larger SP move. +define void @static_16_align_8192(ptr %out) #0 { +; CHECK-LABEL: static_16_align_8192: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: mov x29, sp +; CHECK-NEXT: .cfi_def_cfa w29, 16 +; CHECK-NEXT: .cfi_offset w30, -8 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: sub x9, sp, #1, lsl #12 // =4096 +; CHECK-NEXT: sub x9, x9, #4080 +; CHECK-NEXT: and x9, x9, #0xffffffffffffe000 +; CHECK-NEXT: .LBB13_1: // %entry +; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: sub sp, sp, #1, lsl #12 // =4096 +; CHECK-NEXT: cmp sp, x9 +; CHECK-NEXT: b.le .LBB13_3 +; CHECK-NEXT: // %bb.2: // %entry +; CHECK-NEXT: // in Loop: Header=BB13_1 Depth=1 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: b .LBB13_1 +; CHECK-NEXT: .LBB13_3: // %entry +; CHECK-NEXT: mov sp, x9 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: str x8, [x0] +; CHECK-NEXT: mov sp, x29 +; CHECK-NEXT: .cfi_def_cfa wsp, 16 +; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w30 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %v = alloca i8, i64 16, align 8192 + store ptr %v, ptr %out, align 8 + ret void +} + +; A small allocation with a very large alignment requirement, but +; nevertheless small enough as to not need a loop. +define void @static_16_align_2048(ptr %out) #0 { +; CHECK-LABEL: static_16_align_2048: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: mov x29, sp +; CHECK-NEXT: .cfi_def_cfa w29, 16 +; CHECK-NEXT: .cfi_offset w30, -8 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: sub x9, sp, #2032 +; CHECK-NEXT: and sp, x9, #0xfffffffffffff800 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: str x8, [x0] +; CHECK-NEXT: mov sp, x29 +; CHECK-NEXT: .cfi_def_cfa wsp, 16 +; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w30 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %v = alloca i8, i64 16, align 2048 + store ptr %v, ptr %out, align 8 + ret void +} + +; A large(-ish) allocation with a very large alignment requirement, but +; nevertheless small enough as to not need a loop. +define void @static_2032_align_2048(ptr %out) #0 { +; CHECK-LABEL: static_2032_align_2048: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: mov x29, sp +; CHECK-NEXT: .cfi_def_cfa w29, 16 +; CHECK-NEXT: .cfi_offset w30, -8 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: sub x9, sp, #2032 +; CHECK-NEXT: and sp, x9, #0xfffffffffffff800 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: str x8, [x0] +; CHECK-NEXT: mov sp, x29 +; CHECK-NEXT: .cfi_def_cfa wsp, 16 +; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w30 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %v = alloca i8, i64 2032, align 2048 + store ptr %v, ptr %out, align 8 + ret void +} + +; Test stack probing is enabled by module flags +define void @static_9232(ptr %out) uwtable(async) { +; CHECK-LABEL: static_9232: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: sub sp, sp, #2, lsl #12 // =8192 +; CHECK-NEXT: .cfi_def_cfa_offset 8208 +; CHECK-NEXT: sub sp, sp, #800 +; CHECK-NEXT: .cfi_def_cfa_offset 9008 +; CHECK-NEXT: str xzr, [sp], #-240 +; CHECK-NEXT: .cfi_def_cfa_offset 9248 +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: str x8, [x0] +; CHECK-NEXT: add sp, sp, #2, lsl #12 // =8192 +; CHECK-NEXT: .cfi_def_cfa_offset 1056 +; CHECK-NEXT: add sp, sp, #1040 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %v = alloca i8, i64 9232, align 1 + store ptr %v, ptr %out, align 8 + ret void +} + +; Test for a tight upper bound on the amount of stack adjustment +; due to stack realignment. No probes should appear. +define void @static_1008(ptr %out) #0 { +; CHECK-LABEL: static_1008: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: mov x29, sp +; CHECK-NEXT: .cfi_def_cfa w29, 16 +; CHECK-NEXT: .cfi_offset w30, -8 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: sub x9, sp, #1008 +; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0 +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: str x8, [x0] +; CHECK-NEXT: mov sp, x29 +; CHECK-NEXT: .cfi_def_cfa wsp, 16 +; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w30 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: ret +entry: + %v = alloca i8, i32 1008, align 32 + store ptr %v, ptr %out, align 8 + ret void +} + +attributes #0 = { uwtable(async) "probe-stack"="inline-asm" "stack-probe-size"="4096" "frame-pointer"="none" } + +!llvm.module.flags = !{!0, !1} + +!0 = !{i32 4, !"probe-stack", !"inline-asm"} +!1 = !{i32 8, !"stack-probe-size", i32 9000} -- GitLab From cb13e9286b6d4e384b5d4203e853d44e2eff0f0f Mon Sep 17 00:00:00 2001 From: Eduard Zingerman Date: Mon, 21 Aug 2023 21:24:40 +0300 Subject: [PATCH 006/699] [BPF] Attribute preserve_static_offset for structs This commit adds a new BPF specific structure attribte `__attribute__((preserve_static_offset))` and a pass to deal with it. This attribute may be attached to a struct or union declaration, where it notifies the compiler that this structure is a "context" structure. The following limitations apply to context structures: - runtime environment might patch access to the fields of this type by updating the field offset; BPF verifier limits access patterns allowed for certain data types. E.g. `struct __sk_buff` and `struct bpf_sock_ops`. For these types only `LD/ST ` memory loads and stores are allowed. This is so because offsets of the fields of these structures do not match real offsets in the running kernel. During BPF program load/verification loads and stores to the fields of these types are rewritten so that offsets match real offsets. For this rewrite to happen static offsets have to be encoded in the instructions. See `kernel/bpf/verifier.c:convert_ctx_access` function in the Linux kernel source tree for details. - runtime environment might disallow access to the field of the type through modified pointers. During BPF program verification a tag `PTR_TO_CTX` is tracked for register values. In case if register with such tag is modified BPF programs are not allowed to read or write memory using register. See kernel/bpf/verifier.c:check_mem_access function in the Linux kernel source tree for details. Access to the structure fields is translated to IR as a sequence: - `(load (getelementptr %ptr %offset))` or - `(store (getelementptr %ptr %offset))` During instruction selection phase such sequences are translated as a single load instruction with embedded offset, e.g. `LDW %ptr, %offset`, which matches access pattern necessary for the restricted set of types described above (when `%offset` is static). Multiple optimizer passes might separate these instructions, this includes: - SimplifyCFGPass (sinking) - InstCombine (sinking) - GVN (hoisting) The `preserve_static_offset` attribute marks structures for which the following transformations happen: - at the early IR processing stage: - `(load (getelementptr ...))` replaced by call to intrinsic `llvm.bpf.getelementptr.and.load`; - `(store (getelementptr ...))` replaced by call to intrinsic `llvm.bpf.getelementptr.and.store`; - at the late IR processing stage this modification is undone. Such handling prevents various optimizer passes from generating sequences of instructions that would be rejected by BPF verifier. The __attribute__((preserve_static_offset)) has a priority over __attribute__((preserve_access_index)). When preserve_access_index attribute is present preserve access index transformations are not applied. This addresses the issue reported by the following thread: https://lore.kernel.org/bpf/CAA-VZPmxh8o8EBcJ=m-DH4ytcxDFmo0JKsm1p1gf40kS0CE3NQ@mail.gmail.com/T/#m4b9ce2ce73b34f34172328f975235fc6f19841b6 Differential Revision: https://reviews.llvm.org/D133361 --- clang/include/clang/Basic/Attr.td | 8 + clang/include/clang/Basic/AttrDocs.td | 37 + clang/lib/CodeGen/CGExpr.cpp | 34 + clang/lib/Sema/SemaDeclAttr.cpp | 3 + .../CodeGen/bpf-preserve-static-offset-arr.c | 33 + .../bpf-preserve-static-offset-bitfield.c | 31 + .../bpf-preserve-static-offset-lvalue.c | 28 + .../bpf-preserve-static-offset-non-bpf.c | 18 + .../CodeGen/bpf-preserve-static-offset-pai.c | 29 + ...a-attribute-supported-attributes-list.test | 1 + ...attr-preserve-static-offset-warns-nonbpf.c | 6 + .../bpf-attr-preserve-static-offset-warns.c | 23 + .../Sema/bpf-attr-preserve-static-offset.c | 27 + llvm/include/llvm/IR/Intrinsics.td | 4 + llvm/include/llvm/IR/IntrinsicsBPF.td | 39 + llvm/lib/Target/BPF/BPF.h | 19 + .../Target/BPF/BPFAbstractMemberAccess.cpp | 77 +- llvm/lib/Target/BPF/BPFCORE.h | 4 + llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp | 56 ++ .../Target/BPF/BPFPreserveStaticOffset.cpp | 680 ++++++++++++++++++ llvm/lib/Target/BPF/BPFTargetMachine.cpp | 11 + llvm/lib/Target/BPF/CMakeLists.txt | 1 + .../BPF/preserve-static-offset/load-align.ll | 66 ++ .../preserve-static-offset/load-arr-pai.ll | 93 +++ .../BPF/preserve-static-offset/load-atomic.ll | 66 ++ .../preserve-static-offset/load-chain-2.ll | 82 +++ .../preserve-static-offset/load-chain-oob.ll | 73 ++ .../load-chain-u8-oob.ll | 74 ++ .../load-chain-u8-type-mismatch.ll | 73 ++ .../preserve-static-offset/load-chain-u8.ll | 71 ++ .../BPF/preserve-static-offset/load-chain.ll | 68 ++ .../BPF/preserve-static-offset/load-inline.ll | 85 +++ .../preserve-static-offset/load-non-const.ll | 75 ++ .../preserve-static-offset/load-ptr-pai.ll | 114 +++ .../BPF/preserve-static-offset/load-simple.ll | 71 ++ .../preserve-static-offset/load-struct-pai.ll | 105 +++ .../preserve-static-offset/load-undo-align.ll | 67 ++ .../load-undo-chain-oob.ll | 74 ++ .../load-undo-chain-u8.ll | 68 ++ .../preserve-static-offset/load-undo-chain.ll | 73 ++ .../load-undo-simple.ll | 65 ++ .../load-undo-volatile.ll | 64 ++ .../preserve-static-offset/load-union-pai.ll | 110 +++ .../load-unroll-inline.ll | 108 +++ .../BPF/preserve-static-offset/load-unroll.ll | 95 +++ .../preserve-static-offset/load-volatile.ll | 62 ++ .../BPF/preserve-static-offset/load-zero.ll | 57 ++ .../BPF/preserve-static-offset/store-align.ll | 59 ++ .../preserve-static-offset/store-atomic.ll | 60 ++ .../preserve-static-offset/store-chain-2.ll | 77 ++ .../preserve-static-offset/store-chain-oob.ll | 67 ++ .../store-chain-u8-oob.ll | 67 ++ .../preserve-static-offset/store-chain-u8.ll | 68 ++ .../BPF/preserve-static-offset/store-chain.ll | 64 ++ .../BPF/preserve-static-offset/store-pai.ll | 136 ++++ .../preserve-static-offset/store-simple.ll | 60 ++ .../store-undo-align.ll | 62 ++ .../store-undo-chain-oob.ll | 67 ++ .../store-undo-chain-u8.ll | 62 ++ .../store-undo-chain.ll | 68 ++ .../store-undo-simple.ll | 61 ++ .../store-undo-volatile.ll | 61 ++ .../store-unroll-inline.ll | 104 +++ .../preserve-static-offset/store-volatile.ll | 56 ++ .../BPF/preserve-static-offset/store-zero.ll | 51 ++ 65 files changed, 4343 insertions(+), 35 deletions(-) create mode 100644 clang/test/CodeGen/bpf-preserve-static-offset-arr.c create mode 100644 clang/test/CodeGen/bpf-preserve-static-offset-bitfield.c create mode 100644 clang/test/CodeGen/bpf-preserve-static-offset-lvalue.c create mode 100644 clang/test/CodeGen/bpf-preserve-static-offset-non-bpf.c create mode 100644 clang/test/CodeGen/bpf-preserve-static-offset-pai.c create mode 100644 clang/test/Sema/bpf-attr-preserve-static-offset-warns-nonbpf.c create mode 100644 clang/test/Sema/bpf-attr-preserve-static-offset-warns.c create mode 100644 clang/test/Sema/bpf-attr-preserve-static-offset.c create mode 100644 llvm/lib/Target/BPF/BPFPreserveStaticOffset.cpp create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-align.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-arr-pai.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-atomic.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-2.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-oob.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8-oob.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8-type-mismatch.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-chain.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-inline.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-non-const.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-ptr-pai.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-simple.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-struct-pai.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-align.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain-oob.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain-u8.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-simple.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-volatile.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-union-pai.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-unroll-inline.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-unroll.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-volatile.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-zero.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-align.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-atomic.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-2.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-oob.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-u8-oob.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-u8.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-chain.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-pai.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-simple.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-align.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain-oob.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain-u8.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-simple.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-volatile.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-unroll-inline.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-volatile.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-zero.ll diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td index 1800f584c7e1..121ed203829c 100644 --- a/clang/include/clang/Basic/Attr.td +++ b/clang/include/clang/Basic/Attr.td @@ -2024,6 +2024,14 @@ def BPFPreserveAccessIndex : InheritableAttr, let LangOpts = [COnly]; } +def BPFPreserveStaticOffset : InheritableAttr, + TargetSpecificAttr { + let Spellings = [Clang<"preserve_static_offset">]; + let Subjects = SubjectList<[Record], ErrorDiag>; + let Documentation = [BPFPreserveStaticOffsetDocs]; + let LangOpts = [COnly]; +} + def BTFDeclTag : InheritableAttr { let Spellings = [Clang<"btf_decl_tag">]; let Args = [StringArgument<"BTFDeclTag">]; diff --git a/clang/include/clang/Basic/AttrDocs.td b/clang/include/clang/Basic/AttrDocs.td index f2c4eb51b443..dafc811c5225 100644 --- a/clang/include/clang/Basic/AttrDocs.td +++ b/clang/include/clang/Basic/AttrDocs.td @@ -2199,6 +2199,43 @@ preserving struct or union member access debuginfo indices of this struct or union, similar to clang ``__builtin_preserve_access_index()``. }]; } + +def BPFPreserveStaticOffsetDocs : Documentation { + let Category = DocCatFunction; + let Content = [{ +Clang supports the ``__attribute__((preserve_static_offset))`` +attribute for the BPF target. This attribute may be attached to a +struct or union declaration. Reading or writing fields of types having +such annotation is guaranteed to generate LDX/ST/STX instruction with +offset corresponding to the field. + +For example: + +.. code-block:: c + + struct foo { + int a; + int b; + }; + + struct bar { + int a; + struct foo b; + } __attribute__((preserve_static_offset)); + + void buz(struct bar *g) { + g->b.a = 42; + } + +The assignment to ``g``'s field would produce an ST instruction with +offset 8: ``*(u32)(r1 + 8) = 42;``. + +Without this attribute generated instructions might be different, +depending on optimizations behavior. E.g. the example above could be +rewritten as ``r1 += 8; *(u32)(r1 + 0) = 42;``. + }]; +} + def BTFDeclTagDocs : Documentation { let Category = DocCatFunction; let Content = [{ diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp index 9d1f1a58f9e1..69cf7f76be9a 100644 --- a/clang/lib/CodeGen/CGExpr.cpp +++ b/clang/lib/CodeGen/CGExpr.cpp @@ -3833,6 +3833,33 @@ static QualType getFixedSizeElementType(const ASTContext &ctx, return eltType; } +static bool hasBPFPreserveStaticOffset(const RecordDecl *D) { + return D && D->hasAttr(); +} + +static bool hasBPFPreserveStaticOffset(const Expr *E) { + if (!E) + return false; + QualType PointeeType = E->getType()->getPointeeType(); + if (PointeeType.isNull()) + return false; + if (const auto *BaseDecl = PointeeType->getAsRecordDecl()) + return hasBPFPreserveStaticOffset(BaseDecl); + return false; +} + +// Wraps Addr with a call to llvm.preserve.static.offset intrinsic. +static Address wrapWithBPFPreserveStaticOffset(CodeGenFunction &CGF, + Address &Addr) { + if (!CGF.getTarget().getTriple().isBPF()) + return Addr; + + llvm::Function *Fn = + CGF.CGM.getIntrinsic(llvm::Intrinsic::preserve_static_offset); + llvm::CallInst *Call = CGF.Builder.CreateCall(Fn, {Addr.getPointer()}); + return Address(Call, Addr.getElementType(), Addr.getAlignment()); +} + /// Given an array base, check whether its member access belongs to a record /// with preserve_access_index attribute or not. static bool IsPreserveAIArrayBase(CodeGenFunction &CGF, const Expr *ArrayBase) { @@ -3894,6 +3921,9 @@ static Address emitArraySubscriptGEP(CodeGenFunction &CGF, Address addr, CharUnits eltAlign = getArrayElementAlign(addr.getAlignment(), indices.back(), eltSize); + if (hasBPFPreserveStaticOffset(Base)) + addr = wrapWithBPFPreserveStaticOffset(CGF, addr); + llvm::Value *eltPtr; auto LastIndex = dyn_cast(indices.back()); if (!LastIndex || @@ -4522,6 +4552,8 @@ LValue CodeGenFunction::EmitLValueForField(LValue base, Address Addr = base.getAddress(*this); unsigned Idx = RL.getLLVMFieldNo(field); const RecordDecl *rec = field->getParent(); + if (hasBPFPreserveStaticOffset(rec)) + Addr = wrapWithBPFPreserveStaticOffset(*this, Addr); if (!UseVolatile) { if (!IsInPreservedAIRegion && (!getDebugInfo() || !rec->hasAttr())) { @@ -4594,6 +4626,8 @@ LValue CodeGenFunction::EmitLValueForField(LValue base, } Address addr = base.getAddress(*this); + if (hasBPFPreserveStaticOffset(rec)) + addr = wrapWithBPFPreserveStaticOffset(*this, addr); if (auto *ClassDef = dyn_cast(rec)) { if (CGM.getCodeGenOpts().StrictVTablePointers && ClassDef->isDynamicClass()) { diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp index 87c78d742d0f..a345978bb870 100644 --- a/clang/lib/Sema/SemaDeclAttr.cpp +++ b/clang/lib/Sema/SemaDeclAttr.cpp @@ -9036,6 +9036,9 @@ ProcessDeclAttribute(Sema &S, Scope *scope, Decl *D, const ParsedAttr &AL, case ParsedAttr::AT_BPFPreserveAccessIndex: handleBPFPreserveAccessIndexAttr(S, D, AL); break; + case ParsedAttr::AT_BPFPreserveStaticOffset: + handleSimpleAttribute(S, D, AL); + break; case ParsedAttr::AT_BTFDeclTag: handleBTFDeclTagAttr(S, D, AL); break; diff --git a/clang/test/CodeGen/bpf-preserve-static-offset-arr.c b/clang/test/CodeGen/bpf-preserve-static-offset-arr.c new file mode 100644 index 000000000000..295bd2919fc6 --- /dev/null +++ b/clang/test/CodeGen/bpf-preserve-static-offset-arr.c @@ -0,0 +1,33 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: bpf-registered-target +// RUN: %clang -cc1 -triple bpf -disable-llvm-passes -S -emit-llvm -o - %s \ +// RUN: | FileCheck %s + +// Check that call to preserve.static.offset is generated when array +// member of a struct marked with __attribute__((preserve_static_offset)) +// is accessed. + +#define __ctx __attribute__((preserve_static_offset)) + +struct foo { + struct { + int a; + } b[7]; +} __ctx; + +// CHECK-LABEL: define dso_local i32 @arr_access +// CHECK-SAME: (ptr noundef [[P:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.preserve.static.offset(ptr [[TMP0]]) +// CHECK-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_FOO:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [7 x %struct.anon], ptr [[B]], i64 0, i64 2 +// CHECK-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[ARRAYIDX]], i32 0, i32 0 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 +// CHECK-NEXT: ret i32 [[TMP2]] +// +int arr_access(struct foo *p) { + return p->b[2].a; +} diff --git a/clang/test/CodeGen/bpf-preserve-static-offset-bitfield.c b/clang/test/CodeGen/bpf-preserve-static-offset-bitfield.c new file mode 100644 index 000000000000..e4fd2eeeeb66 --- /dev/null +++ b/clang/test/CodeGen/bpf-preserve-static-offset-bitfield.c @@ -0,0 +1,31 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: bpf-registered-target +// RUN: %clang -cc1 -triple bpf -disable-llvm-passes -S -emit-llvm -o - %s \ +// RUN: | FileCheck %s + +// Check that call to preserve.static.offset is generated when bitfield +// from a struct marked with __attribute__((preserve_static_offset)) is +// accessed. + +#define __ctx __attribute__((preserve_static_offset)) + +struct foo { + unsigned a:1; +} __ctx; + +// CHECK-LABEL: define dso_local void @lvalue_bitfield +// CHECK-SAME: (ptr noundef [[P:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.preserve.static.offset(ptr [[TMP0]]) +// CHECK-NEXT: [[BF_LOAD:%.*]] = load i8, ptr [[TMP1]], align 4 +// CHECK-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -2 +// CHECK-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 1 +// CHECK-NEXT: store i8 [[BF_SET]], ptr [[TMP1]], align 4 +// CHECK-NEXT: ret void +// +void lvalue_bitfield(struct foo *p) { + p->a = 1; +} diff --git a/clang/test/CodeGen/bpf-preserve-static-offset-lvalue.c b/clang/test/CodeGen/bpf-preserve-static-offset-lvalue.c new file mode 100644 index 000000000000..4f0c359366f5 --- /dev/null +++ b/clang/test/CodeGen/bpf-preserve-static-offset-lvalue.c @@ -0,0 +1,28 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: bpf-registered-target +// RUN: %clang -cc1 -triple bpf -disable-llvm-passes -S -emit-llvm -o - %s \ +// RUN: | FileCheck %s + +// Check that call to preserve.static.offset is generated when field of +// a struct marked with __attribute__((preserve_static_offset)) is accessed. + +#define __ctx __attribute__((preserve_static_offset)) + +struct foo { + int a; +} __ctx; + +// CHECK-LABEL: define dso_local void @lvalue +// CHECK-SAME: (ptr noundef [[P:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.preserve.static.offset(ptr [[TMP0]]) +// CHECK-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_FOO:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK-NEXT: store i32 42, ptr [[A]], align 4 +// CHECK-NEXT: ret void +// +void lvalue(struct foo *p) { + p->a = 42; +} diff --git a/clang/test/CodeGen/bpf-preserve-static-offset-non-bpf.c b/clang/test/CodeGen/bpf-preserve-static-offset-non-bpf.c new file mode 100644 index 000000000000..3fe8d2517fe3 --- /dev/null +++ b/clang/test/CodeGen/bpf-preserve-static-offset-non-bpf.c @@ -0,0 +1,18 @@ +// REQUIRES: x86-registered-target +// RUN: %clang -cc1 -triple x86_64 -disable-llvm-passes -S -emit-llvm -o - %s \ +// RUN: | FileCheck %s + +// Verify that __attribute__((preserve_static_offset)) +// has no effect for non-BPF target. + +#define __ctx __attribute__((preserve_static_offset)) + +struct foo { + int a; +} __ctx; + +// CHECK-NOT: @llvm_preserve_static_offset + +int bar(struct foo *p) { + return p->a; +} diff --git a/clang/test/CodeGen/bpf-preserve-static-offset-pai.c b/clang/test/CodeGen/bpf-preserve-static-offset-pai.c new file mode 100644 index 000000000000..df1f33b1a664 --- /dev/null +++ b/clang/test/CodeGen/bpf-preserve-static-offset-pai.c @@ -0,0 +1,29 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: bpf-registered-target +// RUN: %clang -cc1 -triple bpf -disable-llvm-passes -S -emit-llvm -o - %s \ +// RUN: | FileCheck %s + +// Verify that preserve_static_offset does not interfere with +// preserve_access_index at IR generation stage. + +#define __ctx __attribute__((preserve_static_offset)) +#define __pai __attribute__((preserve_access_index)) + +struct foo { + int a; +} __ctx __pai; + +// CHECK-LABEL: define dso_local i32 @bar +// CHECK-SAME: (ptr noundef [[P:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.preserve.static.offset(ptr [[TMP0]]) +// CHECK-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_FOO:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 +// CHECK-NEXT: ret i32 [[TMP2]] +// +int bar(struct foo *p) { + return p->a; +} diff --git a/clang/test/Misc/pragma-attribute-supported-attributes-list.test b/clang/test/Misc/pragma-attribute-supported-attributes-list.test index dd91f4f88ad6..707fc8875089 100644 --- a/clang/test/Misc/pragma-attribute-supported-attributes-list.test +++ b/clang/test/Misc/pragma-attribute-supported-attributes-list.test @@ -23,6 +23,7 @@ // CHECK-NEXT: Availability ((SubjectMatchRule_record, SubjectMatchRule_enum, SubjectMatchRule_enum_constant, SubjectMatchRule_field, SubjectMatchRule_function, SubjectMatchRule_namespace, SubjectMatchRule_objc_category, SubjectMatchRule_objc_implementation, SubjectMatchRule_objc_interface, SubjectMatchRule_objc_method, SubjectMatchRule_objc_property, SubjectMatchRule_objc_protocol, SubjectMatchRule_record, SubjectMatchRule_type_alias, SubjectMatchRule_variable)) // CHECK-NEXT: AvailableOnlyInDefaultEvalMethod (SubjectMatchRule_type_alias) // CHECK-NEXT: BPFPreserveAccessIndex (SubjectMatchRule_record) +// CHECK-NEXT: BPFPreserveStaticOffset (SubjectMatchRule_record) // CHECK-NEXT: BTFDeclTag (SubjectMatchRule_variable, SubjectMatchRule_function, SubjectMatchRule_record, SubjectMatchRule_field, SubjectMatchRule_type_alias) // CHECK-NEXT: BuiltinAlias (SubjectMatchRule_function) // CHECK-NEXT: CFAuditedTransfer (SubjectMatchRule_function) diff --git a/clang/test/Sema/bpf-attr-preserve-static-offset-warns-nonbpf.c b/clang/test/Sema/bpf-attr-preserve-static-offset-warns-nonbpf.c new file mode 100644 index 000000000000..d543e6f99952 --- /dev/null +++ b/clang/test/Sema/bpf-attr-preserve-static-offset-warns-nonbpf.c @@ -0,0 +1,6 @@ +// RUN: %clang_cc1 -fsyntax-only -verify %s + +#define __pso __attribute__((preserve_static_offset)) + +struct foo { int a; } __pso; // expected-warning{{unknown attribute}} +union quux { int a; } __pso; // expected-warning{{unknown attribute}} diff --git a/clang/test/Sema/bpf-attr-preserve-static-offset-warns.c b/clang/test/Sema/bpf-attr-preserve-static-offset-warns.c new file mode 100644 index 000000000000..1067ebe8f82b --- /dev/null +++ b/clang/test/Sema/bpf-attr-preserve-static-offset-warns.c @@ -0,0 +1,23 @@ +// RUN: %clang_cc1 -fsyntax-only -verify -triple bpf-pc-linux-gnu %s + +#define __pso __attribute__((preserve_static_offset)) + +// These are correct usages. +struct foo { int a; } __pso; +union quux { int a; } __pso; +struct doug { int a; } __pso __attribute__((packed)); + +// Rest are incorrect usages. +typedef int bar __pso; // expected-error{{attribute only applies to}} +struct goo { + int a __pso; // expected-error{{attribute only applies to}} +}; +int g __pso; // expected-error{{attribute only applies to}} +__pso void ffunc1(void); // expected-error{{attribute only applies to}} +void ffunc2(int a __pso); // expected-error{{attribute only applies to}} +void ffunc3(void) { + int a __pso; // expected-error{{attribute only applies to}} +} + +struct buz { int a; } __attribute__((preserve_static_offset("hello"))); // \ + expected-error{{attribute takes no arguments}} diff --git a/clang/test/Sema/bpf-attr-preserve-static-offset.c b/clang/test/Sema/bpf-attr-preserve-static-offset.c new file mode 100644 index 000000000000..5f53469869f3 --- /dev/null +++ b/clang/test/Sema/bpf-attr-preserve-static-offset.c @@ -0,0 +1,27 @@ +// RUN: %clang_cc1 -fsyntax-only -ast-dump -triple bpf-pc-linux-gnu %s | FileCheck %s + +// The 'preserve_static_offset' attribute should be propagated to +// inline declarations (foo's 'b', 'bb', 'c' but not 'd'). +// +// CHECK: RecordDecl {{.*}} struct foo definition +// CHECK-NEXT: BPFPreserveStaticOffsetAttr +// CHECK-NEXT: FieldDecl {{.*}} a +// CHECK-NEXT: RecordDecl {{.*}} struct definition +// CHECK-NEXT: FieldDecl {{.*}} aa +// CHECK-NEXT: FieldDecl {{.*}} b +// CHECK-NEXT: RecordDecl {{.*}} union bar definition +// CHECK-NEXT: BPFPreserveStaticOffsetAttr +// CHECK-NEXT: FieldDecl {{.*}} a +// CHECK-NEXT: FieldDecl {{.*}} b + +struct foo { + int a; + struct { + int aa; + } b; +} __attribute__((preserve_static_offset)); + +union bar { + int a; + long b; +} __attribute__((preserve_static_offset)); diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td index 060e964f77bf..b54c697296b2 100644 --- a/llvm/include/llvm/IR/Intrinsics.td +++ b/llvm/include/llvm/IR/Intrinsics.td @@ -2469,6 +2469,10 @@ def int_preserve_struct_access_index : DefaultAttrsIntrinsic<[llvm_anyptr_ty], [IntrNoMem, ImmArg>, ImmArg>]>; +def int_preserve_static_offset : DefaultAttrsIntrinsic<[llvm_ptr_ty], + [llvm_ptr_ty], + [IntrNoMem, IntrSpeculatable, + ReadNone >]>; //===------------ Intrinsics to perform common vector shuffles ------------===// diff --git a/llvm/include/llvm/IR/IntrinsicsBPF.td b/llvm/include/llvm/IR/IntrinsicsBPF.td index 8916b60d2be3..c7ec0916f1d1 100644 --- a/llvm/include/llvm/IR/IntrinsicsBPF.td +++ b/llvm/include/llvm/IR/IntrinsicsBPF.td @@ -37,4 +37,43 @@ let TargetPrefix = "bpf" in { // All intrinsics start with "llvm.bpf." def int_bpf_compare : ClangBuiltin<"__builtin_bpf_compare">, Intrinsic<[llvm_i1_ty], [llvm_i32_ty, llvm_anyint_ty, llvm_anyint_ty], [IntrNoMem]>; + def int_bpf_getelementptr_and_load : ClangBuiltin<"__builtin_bpf_getelementptr_and_load">, + Intrinsic<[llvm_any_ty], + [llvm_ptr_ty, // base ptr for getelementptr + llvm_i1_ty, // volatile + llvm_i8_ty, // atomic order + llvm_i8_ty, // synscope id + llvm_i8_ty, // alignment + llvm_i1_ty, // inbounds + llvm_vararg_ty], // indices for getelementptr insn + [IntrNoCallback, + IntrNoFree, + IntrWillReturn, + NoCapture >, + ImmArg >, // volatile + ImmArg >, // atomic order + ImmArg >, // synscope id + ImmArg >, // alignment + ImmArg >, // inbounds + ]>; + def int_bpf_getelementptr_and_store : ClangBuiltin<"__builtin_bpf_getelementptr_and_store">, + Intrinsic<[], + [llvm_any_ty, // value to store + llvm_ptr_ty, // base ptr for getelementptr + llvm_i1_ty, // volatile + llvm_i8_ty, // atomic order + llvm_i8_ty, // syncscope id + llvm_i8_ty, // alignment + llvm_i1_ty, // inbounds + llvm_vararg_ty], // indexes for getelementptr insn + [IntrNoCallback, + IntrNoFree, + IntrWillReturn, + NoCapture >, + ImmArg >, // volatile + ImmArg >, // atomic order + ImmArg >, // syncscope id + ImmArg >, // alignment + ImmArg >, // inbounds + ]>; } diff --git a/llvm/lib/Target/BPF/BPF.h b/llvm/lib/Target/BPF/BPF.h index 1f539d3270b7..436cd62c2581 100644 --- a/llvm/lib/Target/BPF/BPF.h +++ b/llvm/lib/Target/BPF/BPF.h @@ -10,6 +10,7 @@ #define LLVM_LIB_TARGET_BPF_BPF_H #include "MCTargetDesc/BPFMCTargetDesc.h" +#include "llvm/IR/Instructions.h" #include "llvm/IR/PassManager.h" #include "llvm/Pass.h" #include "llvm/Target/TargetMachine.h" @@ -62,6 +63,24 @@ class BPFAdjustOptPass : public PassInfoMixin { public: PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM); }; + +class BPFPreserveStaticOffsetPass + : public PassInfoMixin { + bool AllowPartial; + +public: + BPFPreserveStaticOffsetPass(bool AllowPartial) : AllowPartial(AllowPartial) {} + PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + + static bool isRequired() { return true; } + + static std::pair + reconstructLoad(CallInst *Call); + + static std::pair + reconstructStore(CallInst *Call); +}; + } // namespace llvm #endif diff --git a/llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp b/llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp index 1895d15c1f55..9634c16a30dc 100644 --- a/llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp +++ b/llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp @@ -172,8 +172,6 @@ private: bool IsValidAIChain(const MDNode *ParentMeta, uint32_t ParentAI, const MDNode *ChildMeta); bool removePreserveAccessIndexIntrinsic(Function &F); - void replaceWithGEP(std::vector &CallList, - uint32_t NumOfZerosIndex, uint32_t DIIndex); bool HasPreserveFieldInfoCall(CallInfoStack &CallStack); void GetStorageBitRange(DIDerivedType *MemberTy, Align RecordAlignment, uint32_t &StartBitOffset, uint32_t &EndBitOffset); @@ -185,7 +183,6 @@ private: std::string &AccessKey, MDNode *&BaseMeta); MDNode *computeAccessKey(CallInst *Call, CallInfo &CInfo, std::string &AccessKey, bool &IsInt32Ret); - uint64_t getConstant(const Value *IndexValue); bool transformGEPChain(CallInst *Call, CallInfo &CInfo); }; @@ -326,6 +323,12 @@ static Type *getBaseElementType(const CallInst *Call) { return Call->getParamElementType(0); } +static uint64_t getConstant(const Value *IndexValue) { + const ConstantInt *CV = dyn_cast(IndexValue); + assert(CV); + return CV->getValue().getZExtValue(); +} + /// Check whether a call is a preserve_*_access_index intrinsic call or not. bool BPFAbstractMemberAccess::IsPreserveDIAccessIndexCall(const CallInst *Call, CallInfo &CInfo) { @@ -410,26 +413,36 @@ bool BPFAbstractMemberAccess::IsPreserveDIAccessIndexCall(const CallInst *Call, return false; } -void BPFAbstractMemberAccess::replaceWithGEP(std::vector &CallList, - uint32_t DimensionIndex, - uint32_t GEPIndex) { - for (auto *Call : CallList) { - uint32_t Dimension = 1; - if (DimensionIndex > 0) - Dimension = getConstant(Call->getArgOperand(DimensionIndex)); - - Constant *Zero = - ConstantInt::get(Type::getInt32Ty(Call->getParent()->getContext()), 0); - SmallVector IdxList; - for (unsigned I = 0; I < Dimension; ++I) - IdxList.push_back(Zero); - IdxList.push_back(Call->getArgOperand(GEPIndex)); - - auto *GEP = GetElementPtrInst::CreateInBounds( - getBaseElementType(Call), Call->getArgOperand(0), IdxList, "", Call); - Call->replaceAllUsesWith(GEP); - Call->eraseFromParent(); - } +static void replaceWithGEP(CallInst *Call, uint32_t DimensionIndex, + uint32_t GEPIndex) { + uint32_t Dimension = 1; + if (DimensionIndex > 0) + Dimension = getConstant(Call->getArgOperand(DimensionIndex)); + + Constant *Zero = + ConstantInt::get(Type::getInt32Ty(Call->getParent()->getContext()), 0); + SmallVector IdxList; + for (unsigned I = 0; I < Dimension; ++I) + IdxList.push_back(Zero); + IdxList.push_back(Call->getArgOperand(GEPIndex)); + + auto *GEP = GetElementPtrInst::CreateInBounds( + getBaseElementType(Call), Call->getArgOperand(0), IdxList, "", Call); + Call->replaceAllUsesWith(GEP); + Call->eraseFromParent(); +} + +void BPFCoreSharedInfo::removeArrayAccessCall(CallInst *Call) { + replaceWithGEP(Call, 1, 2); +} + +void BPFCoreSharedInfo::removeStructAccessCall(CallInst *Call) { + replaceWithGEP(Call, 0, 1); +} + +void BPFCoreSharedInfo::removeUnionAccessCall(CallInst *Call) { + Call->replaceAllUsesWith(Call->getArgOperand(0)); + Call->eraseFromParent(); } bool BPFAbstractMemberAccess::removePreserveAccessIndexIntrinsic(Function &F) { @@ -464,12 +477,12 @@ bool BPFAbstractMemberAccess::removePreserveAccessIndexIntrinsic(Function &F) { // . addr = preserve_struct_access_index(base, gep_index, di_index) // is transformed to // addr = GEP(base, 0, gep_index) - replaceWithGEP(PreserveArrayIndexCalls, 1, 2); - replaceWithGEP(PreserveStructIndexCalls, 0, 1); - for (auto *Call : PreserveUnionIndexCalls) { - Call->replaceAllUsesWith(Call->getArgOperand(0)); - Call->eraseFromParent(); - } + for (CallInst *Call : PreserveArrayIndexCalls) + BPFCoreSharedInfo::removeArrayAccessCall(Call); + for (CallInst *Call : PreserveStructIndexCalls) + BPFCoreSharedInfo::removeStructAccessCall(Call); + for (CallInst *Call : PreserveUnionIndexCalls) + BPFCoreSharedInfo::removeUnionAccessCall(Call); return Found; } @@ -634,12 +647,6 @@ void BPFAbstractMemberAccess::collectAICallChains(Function &F) { } } -uint64_t BPFAbstractMemberAccess::getConstant(const Value *IndexValue) { - const ConstantInt *CV = dyn_cast(IndexValue); - assert(CV); - return CV->getValue().getZExtValue(); -} - /// Get the start and the end of storage offset for \p MemberTy. void BPFAbstractMemberAccess::GetStorageBitRange(DIDerivedType *MemberTy, Align RecordAlignment, diff --git a/llvm/lib/Target/BPF/BPFCORE.h b/llvm/lib/Target/BPF/BPFCORE.h index 9a547a775c96..f46a8ef62a7f 100644 --- a/llvm/lib/Target/BPF/BPFCORE.h +++ b/llvm/lib/Target/BPF/BPFCORE.h @@ -10,6 +10,7 @@ #define LLVM_LIB_TARGET_BPF_BPFCORE_H #include "llvm/ADT/StringRef.h" +#include "llvm/IR/Instructions.h" namespace llvm { @@ -53,6 +54,9 @@ public: static Instruction *insertPassThrough(Module *M, BasicBlock *BB, Instruction *Input, Instruction *Before); + static void removeArrayAccessCall(CallInst *Call); + static void removeStructAccessCall(CallInst *Call); + static void removeUnionAccessCall(CallInst *Call); }; } // namespace llvm diff --git a/llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp b/llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp index a3616ae7ebab..56c89f61b319 100644 --- a/llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp +++ b/llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp @@ -12,6 +12,8 @@ // The following are done for IR adjustment: // - remove __builtin_bpf_passthrough builtins. Target independent IR // optimizations are done and those builtins can be removed. +// - remove llvm.bpf.getelementptr.and.load builtins. +// - remove llvm.bpf.getelementptr.and.store builtins. // //===----------------------------------------------------------------------===// @@ -24,6 +26,7 @@ #include "llvm/IR/IRBuilder.h" #include "llvm/IR/Instruction.h" #include "llvm/IR/Instructions.h" +#include "llvm/IR/IntrinsicsBPF.h" #include "llvm/IR/Module.h" #include "llvm/IR/Type.h" #include "llvm/IR/User.h" @@ -51,6 +54,7 @@ private: bool removePassThroughBuiltin(Module &M); bool removeCompareBuiltin(Module &M); bool sinkMinMax(Module &M); + bool removeGEPBuiltins(Module &M); }; } // End anonymous namespace @@ -361,10 +365,62 @@ void BPFCheckAndAdjustIR::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); } +static void unrollGEPLoad(CallInst *Call) { + auto [GEP, Load] = BPFPreserveStaticOffsetPass::reconstructLoad(Call); + GEP->insertBefore(Call); + Load->insertBefore(Call); + Call->replaceAllUsesWith(Load); + Call->eraseFromParent(); +} + +static void unrollGEPStore(CallInst *Call) { + auto [GEP, Store] = BPFPreserveStaticOffsetPass::reconstructStore(Call); + GEP->insertBefore(Call); + Store->insertBefore(Call); + Call->eraseFromParent(); +} + +static bool removeGEPBuiltinsInFunc(Function &F) { + SmallVector GEPLoads; + SmallVector GEPStores; + for (auto &BB : F) + for (auto &Insn : BB) + if (auto *Call = dyn_cast(&Insn)) + if (auto *Called = Call->getCalledFunction()) + switch (Called->getIntrinsicID()) { + case Intrinsic::bpf_getelementptr_and_load: + GEPLoads.push_back(Call); + break; + case Intrinsic::bpf_getelementptr_and_store: + GEPStores.push_back(Call); + break; + } + + if (GEPLoads.empty() && GEPStores.empty()) + return false; + + for_each(GEPLoads, unrollGEPLoad); + for_each(GEPStores, unrollGEPStore); + + return true; +} + +// Rewrites the following builtins: +// - llvm.bpf.getelementptr.and.load +// - llvm.bpf.getelementptr.and.store +// As (load (getelementptr ...)) or (store (getelementptr ...)). +bool BPFCheckAndAdjustIR::removeGEPBuiltins(Module &M) { + bool Changed = false; + for (auto &F : M) + Changed = removeGEPBuiltinsInFunc(F) || Changed; + return Changed; +} + bool BPFCheckAndAdjustIR::adjustIR(Module &M) { bool Changed = removePassThroughBuiltin(M); Changed = removeCompareBuiltin(M) || Changed; Changed = sinkMinMax(M) || Changed; + Changed = removeGEPBuiltins(M) || Changed; return Changed; } diff --git a/llvm/lib/Target/BPF/BPFPreserveStaticOffset.cpp b/llvm/lib/Target/BPF/BPFPreserveStaticOffset.cpp new file mode 100644 index 000000000000..e30a10a9f267 --- /dev/null +++ b/llvm/lib/Target/BPF/BPFPreserveStaticOffset.cpp @@ -0,0 +1,680 @@ +//===------ BPFPreserveStaticOffset.cpp -----------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// TLDR: replaces llvm.preserve.static.offset + GEP + load / store +// with llvm.bpf.getelementptr.and.load / store +// +// This file implements BPFPreserveStaticOffsetPass transformation. +// This transformation address two BPF verifier specific issues: +// +// (a) Access to the fields of some structural types is allowed only +// using load and store instructions with static immediate offsets. +// +// Examples of such types are `struct __sk_buff` and `struct +// bpf_sock_ops`. This is so because offsets of the fields of +// these structures do not match real offsets in the running +// kernel. During BPF program load LDX and STX instructions +// referring to the fields of these types are rewritten so that +// offsets match real offsets. For this rewrite to happen field +// offsets have to be encoded as immediate operands of the +// instructions. +// +// See kernel/bpf/verifier.c:convert_ctx_access function in the +// Linux kernel source tree for details. +// +// (b) Pointers to context parameters of BPF programs must not be +// modified before access. +// +// During BPF program verification a tag PTR_TO_CTX is tracked for +// register values. In case if register with such tag is modified +// BPF program is not allowed to read or write memory using this +// register. See kernel/bpf/verifier.c:check_mem_access function +// in the Linux kernel source tree for details. +// +// The following sequence of the IR instructions: +// +// %x = getelementptr %ptr, %constant_offset +// %y = load %x +// +// Is translated as a single machine instruction: +// +// LDW %ptr, %constant_offset +// +// In order for cases (a) and (b) to work the sequence %x-%y above has +// to be preserved by the IR passes. +// +// However, several optimization passes might sink `load` instruction +// or hoist `getelementptr` instruction so that the instructions are +// no longer in sequence. Examples of such passes are: +// SimplifyCFGPass, InstCombinePass, GVNPass. +// After such modification the verifier would reject the BPF program. +// +// To avoid this issue the patterns like (load/store (getelementptr ...)) +// are replaced by calls to BPF specific intrinsic functions: +// - llvm.bpf.getelementptr.and.load +// - llvm.bpf.getelementptr.and.store +// +// These calls are lowered back to (load/store (getelementptr ...)) +// by BPFCheckAndAdjustIR pass right before the translation from IR to +// machine instructions. +// +// The transformation is split into the following steps: +// - When IR is generated from AST the calls to intrinsic function +// llvm.preserve.static.offset are inserted. +// - BPFPreserveStaticOffsetPass is executed as early as possible +// with AllowPatial set to true, this handles marked GEP chains +// with constant offsets. +// - BPFPreserveStaticOffsetPass is executed at ScalarOptimizerLateEPCallback +// with AllowPatial set to false, this handles marked GEP chains +// with offsets that became constant after loop unrolling, e.g. +// to handle the following code: +// +// struct context { int x[4]; } __attribute__((preserve_static_offset)); +// +// struct context *ctx = ...; +// #pragma clang loop unroll(full) +// for (int i = 0; i < 4; ++i) +// foo(ctx->x[i]); +// +// The early BPFPreserveStaticOffsetPass run is necessary to allow +// additional GVN / CSE opportunities after functions inlining. +// The relative order of optimization applied to function: +// - early stage (1) +// - ... +// - function inlining (2) +// - ... +// - loop unrolling +// - ... +// - ScalarOptimizerLateEPCallback (3) +// +// When function A is inlined into function B all optimizations for A +// are already done, while some passes remain for B. In case if +// BPFPreserveStaticOffsetPass is done at (3) but not done at (1) +// the code after (2) would contain a mix of +// (load (gep %p)) and (get.and.load %p) usages: +// - the (load (gep %p)) would come from the calling function; +// - the (get.and.load %p) would come from the callee function. +// Thus clobbering CSE / GVN passes done after inlining. + +#include "BPF.h" +#include "BPFCORE.h" +#include "llvm/ADT/SmallPtrSet.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/IR/Argument.h" +#include "llvm/IR/Attributes.h" +#include "llvm/IR/BasicBlock.h" +#include "llvm/IR/Constants.h" +#include "llvm/IR/DebugInfoMetadata.h" +#include "llvm/IR/DiagnosticInfo.h" +#include "llvm/IR/IRBuilder.h" +#include "llvm/IR/InstIterator.h" +#include "llvm/IR/Instructions.h" +#include "llvm/IR/Intrinsics.h" +#include "llvm/IR/IntrinsicsBPF.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" + +#define DEBUG_TYPE "bpf-preserve-static-offset" + +using namespace llvm; + +static const unsigned GepAndLoadFirstIdxArg = 6; +static const unsigned GepAndStoreFirstIdxArg = 7; + +static bool isIntrinsicCall(Value *I, Intrinsic::ID Id) { + if (auto *Call = dyn_cast(I)) + if (Function *Func = Call->getCalledFunction()) + return Func->getIntrinsicID() == Id; + return false; +} + +static bool isPreserveStaticOffsetCall(Value *I) { + return isIntrinsicCall(I, Intrinsic::preserve_static_offset); +} + +static CallInst *isGEPAndLoad(Value *I) { + if (isIntrinsicCall(I, Intrinsic::bpf_getelementptr_and_load)) + return cast(I); + return nullptr; +} + +static CallInst *isGEPAndStore(Value *I) { + if (isIntrinsicCall(I, Intrinsic::bpf_getelementptr_and_store)) + return cast(I); + return nullptr; +} + +template +static DILocation *mergeDILocations(SmallVector &Insns) { + DILocation *Merged = (*Insns.begin())->getDebugLoc(); + for (T *I : Insns) + Merged = DILocation::getMergedLocation(Merged, I->getDebugLoc()); + return Merged; +} + +static CallInst *makeIntrinsicCall(Module *M, + Intrinsic::BPFIntrinsics Intrinsic, + ArrayRef Types, + ArrayRef Args) { + + Function *Fn = Intrinsic::getDeclaration(M, Intrinsic, Types); + return CallInst::Create(Fn, Args); +} + +static void setParamElementType(CallInst *Call, unsigned ArgNo, Type *Type) { + LLVMContext &C = Call->getContext(); + Call->addParamAttr(ArgNo, Attribute::get(C, Attribute::ElementType, Type)); +} + +static void setParamReadNone(CallInst *Call, unsigned ArgNo) { + LLVMContext &C = Call->getContext(); + Call->addParamAttr(ArgNo, Attribute::get(C, Attribute::ReadNone)); +} + +static void setParamReadOnly(CallInst *Call, unsigned ArgNo) { + LLVMContext &C = Call->getContext(); + Call->addParamAttr(ArgNo, Attribute::get(C, Attribute::ReadOnly)); +} + +static void setParamWriteOnly(CallInst *Call, unsigned ArgNo) { + LLVMContext &C = Call->getContext(); + Call->addParamAttr(ArgNo, Attribute::get(C, Attribute::WriteOnly)); +} + +namespace { +struct GEPChainInfo { + bool InBounds; + Type *SourceElementType; + SmallVector Indices; + SmallVector Members; + + GEPChainInfo() { reset(); } + + void reset() { + InBounds = true; + SourceElementType = nullptr; + Indices.clear(); + Members.clear(); + } +}; +} // Anonymous namespace + +template > +static void fillCommonArgs(LLVMContext &C, SmallVector &Args, + GEPChainInfo &GEP, T *Insn) { + Type *Int8Ty = Type::getInt8Ty(C); + Type *Int1Ty = Type::getInt1Ty(C); + // Implementation of Align guarantees that ShiftValue < 64 + unsigned AlignShiftValue = Log2_64(Insn->getAlign().value()); + Args.push_back(GEP.Members[0]->getPointerOperand()); + Args.push_back(ConstantInt::get(Int1Ty, Insn->isVolatile())); + Args.push_back(ConstantInt::get(Int8Ty, (unsigned)Insn->getOrdering())); + Args.push_back(ConstantInt::get(Int8Ty, (unsigned)Insn->getSyncScopeID())); + Args.push_back(ConstantInt::get(Int8Ty, AlignShiftValue)); + Args.push_back(ConstantInt::get(Int1Ty, GEP.InBounds)); + Args.append(GEP.Indices.begin(), GEP.Indices.end()); +} + +static Instruction *makeGEPAndLoad(Module *M, GEPChainInfo &GEP, + LoadInst *Load) { + SmallVector Args; + fillCommonArgs(M->getContext(), Args, GEP, Load); + CallInst *Call = makeIntrinsicCall(M, Intrinsic::bpf_getelementptr_and_load, + {Load->getType()}, Args); + setParamElementType(Call, 0, GEP.SourceElementType); + Call->applyMergedLocation(mergeDILocations(GEP.Members), Load->getDebugLoc()); + Call->setName((*GEP.Members.rbegin())->getName()); + if (Load->isUnordered()) { + Call->setOnlyReadsMemory(); + Call->setOnlyAccessesArgMemory(); + setParamReadOnly(Call, 0); + } + for (unsigned I = GepAndLoadFirstIdxArg; I < Args.size(); ++I) + Call->addParamAttr(I, Attribute::ImmArg); + Call->setAAMetadata(Load->getAAMetadata()); + return Call; +} + +static Instruction *makeGEPAndStore(Module *M, GEPChainInfo &GEP, + StoreInst *Store) { + SmallVector Args; + Args.push_back(Store->getValueOperand()); + fillCommonArgs(M->getContext(), Args, GEP, Store); + CallInst *Call = + makeIntrinsicCall(M, Intrinsic::bpf_getelementptr_and_store, + {Store->getValueOperand()->getType()}, Args); + setParamElementType(Call, 1, GEP.SourceElementType); + if (Store->getValueOperand()->getType()->isPointerTy()) + setParamReadNone(Call, 0); + Call->applyMergedLocation(mergeDILocations(GEP.Members), + Store->getDebugLoc()); + if (Store->isUnordered()) { + Call->setOnlyWritesMemory(); + Call->setOnlyAccessesArgMemory(); + setParamWriteOnly(Call, 1); + } + for (unsigned I = GepAndStoreFirstIdxArg; I < Args.size(); ++I) + Call->addParamAttr(I, Attribute::ImmArg); + Call->setAAMetadata(Store->getAAMetadata()); + return Call; +} + +static unsigned getOperandAsUnsigned(CallInst *Call, unsigned ArgNo) { + if (auto *Int = dyn_cast(Call->getOperand(ArgNo))) + return Int->getValue().getZExtValue(); + std::string Report; + raw_string_ostream ReportS(Report); + ReportS << "Expecting ConstantInt as argument #" << ArgNo << " of " << *Call + << "\n"; + report_fatal_error(StringRef(Report)); +} + +static GetElementPtrInst *reconstructGEP(CallInst *Call, int Delta) { + SmallVector Indices; + Indices.append(Call->data_operands_begin() + 6 + Delta, + Call->data_operands_end()); + Type *GEPPointeeType = Call->getParamElementType(Delta); + auto *GEP = + GetElementPtrInst::Create(GEPPointeeType, Call->getOperand(Delta), + ArrayRef(Indices), Call->getName()); + GEP->setIsInBounds(getOperandAsUnsigned(Call, 5 + Delta)); + return GEP; +} + +template > +static void reconstructCommon(CallInst *Call, GetElementPtrInst *GEP, T *Insn, + int Delta) { + Insn->setVolatile(getOperandAsUnsigned(Call, 1 + Delta)); + Insn->setOrdering((AtomicOrdering)getOperandAsUnsigned(Call, 2 + Delta)); + Insn->setSyncScopeID(getOperandAsUnsigned(Call, 3 + Delta)); + unsigned AlignShiftValue = getOperandAsUnsigned(Call, 4 + Delta); + Insn->setAlignment(Align(1ULL << AlignShiftValue)); + GEP->setDebugLoc(Call->getDebugLoc()); + Insn->setDebugLoc(Call->getDebugLoc()); + Insn->setAAMetadata(Call->getAAMetadata()); +} + +std::pair +BPFPreserveStaticOffsetPass::reconstructLoad(CallInst *Call) { + GetElementPtrInst *GEP = reconstructGEP(Call, 0); + Type *ReturnType = Call->getFunctionType()->getReturnType(); + auto *Load = new LoadInst(ReturnType, GEP, "", + /* These would be set in reconstructCommon */ + false, Align(1)); + reconstructCommon(Call, GEP, Load, 0); + return std::pair{GEP, Load}; +} + +std::pair +BPFPreserveStaticOffsetPass::reconstructStore(CallInst *Call) { + GetElementPtrInst *GEP = reconstructGEP(Call, 1); + auto *Store = new StoreInst(Call->getOperand(0), GEP, + /* These would be set in reconstructCommon */ + false, Align(1)); + reconstructCommon(Call, GEP, Store, 1); + return std::pair{GEP, Store}; +} + +static bool isZero(Value *V) { + auto *CI = dyn_cast(V); + return CI && CI->isZero(); +} + +// Given a chain of GEP instructions collect information necessary to +// merge this chain as a single GEP instruction of form: +// getelementptr %, ptr %p, i32 0, , , ... +static bool foldGEPChainAsStructAccess(SmallVector &GEPs, + GEPChainInfo &Info) { + if (GEPs.empty()) + return false; + + if (!all_of(GEPs, [=](GetElementPtrInst *GEP) { + return GEP->hasAllConstantIndices(); + })) + return false; + + GetElementPtrInst *First = GEPs[0]; + Info.InBounds = First->isInBounds(); + Info.SourceElementType = First->getSourceElementType(); + Type *ResultElementType = First->getResultElementType(); + Info.Indices.append(First->idx_begin(), First->idx_end()); + Info.Members.push_back(First); + + for (auto *Iter = GEPs.begin() + 1; Iter != GEPs.end(); ++Iter) { + GetElementPtrInst *GEP = *Iter; + if (!isZero(*GEP->idx_begin())) { + Info.reset(); + return false; + } + if (!GEP->getSourceElementType() || + GEP->getSourceElementType() != ResultElementType) { + Info.reset(); + return false; + } + Info.InBounds &= GEP->isInBounds(); + Info.Indices.append(GEP->idx_begin() + 1, GEP->idx_end()); + Info.Members.push_back(GEP); + ResultElementType = GEP->getResultElementType(); + } + + return true; +} + +// Given a chain of GEP instructions collect information necessary to +// merge this chain as a single GEP instruction of form: +// getelementptr i8, ptr %p, i64 %offset +static bool foldGEPChainAsU8Access(SmallVector &GEPs, + GEPChainInfo &Info) { + if (GEPs.empty()) + return false; + + GetElementPtrInst *First = GEPs[0]; + const DataLayout &DL = First->getModule()->getDataLayout(); + LLVMContext &C = First->getContext(); + Type *PtrTy = First->getType()->getScalarType(); + APInt Offset(DL.getIndexTypeSizeInBits(PtrTy), 0); + for (GetElementPtrInst *GEP : GEPs) { + if (!GEP->accumulateConstantOffset(DL, Offset)) { + Info.reset(); + return false; + } + Info.InBounds &= GEP->isInBounds(); + Info.Members.push_back(GEP); + } + Info.SourceElementType = Type::getInt8Ty(C); + Info.Indices.push_back(ConstantInt::get(C, Offset)); + + return true; +} + +static void reportNonStaticGEPChain(Instruction *Insn) { + auto Msg = DiagnosticInfoUnsupported( + *Insn->getFunction(), + Twine("Non-constant offset in access to a field of a type marked " + "with preserve_static_offset might be rejected by BPF verifier") + .concat(Insn->getDebugLoc() + ? "" + : " (pass -g option to get exact location)"), + Insn->getDebugLoc(), DS_Warning); + Insn->getContext().diagnose(Msg); +} + +static bool allZeroIndices(SmallVector &GEPs) { + return GEPs.empty() || all_of(GEPs, [=](GetElementPtrInst *GEP) { + return GEP->hasAllZeroIndices(); + }); +} + +static bool tryToReplaceWithGEPBuiltin(Instruction *LoadOrStoreTemplate, + SmallVector &GEPs, + Instruction *InsnToReplace) { + GEPChainInfo GEPChain; + if (!foldGEPChainAsStructAccess(GEPs, GEPChain) && + !foldGEPChainAsU8Access(GEPs, GEPChain)) { + return false; + } + Module *M = InsnToReplace->getModule(); + if (auto *Load = dyn_cast(LoadOrStoreTemplate)) { + Instruction *Replacement = makeGEPAndLoad(M, GEPChain, Load); + Replacement->insertBefore(InsnToReplace); + InsnToReplace->replaceAllUsesWith(Replacement); + } + if (auto *Store = dyn_cast(LoadOrStoreTemplate)) { + Instruction *Replacement = makeGEPAndStore(M, GEPChain, Store); + Replacement->insertBefore(InsnToReplace); + } + return true; +} + +// Check if U->getPointerOperand() == I +static bool isPointerOperand(Value *I, User *U) { + if (auto *L = dyn_cast(U)) + return L->getPointerOperand() == I; + if (auto *S = dyn_cast(U)) + return S->getPointerOperand() == I; + if (auto *GEP = dyn_cast(U)) + return GEP->getPointerOperand() == I; + if (auto *Call = isGEPAndLoad(U)) + return Call->getArgOperand(0) == I; + if (auto *Call = isGEPAndStore(U)) + return Call->getArgOperand(1) == I; + return false; +} + +static bool isInlineableCall(User *U) { + if (auto *Call = dyn_cast(U)) + return Call->hasFnAttr(Attribute::InlineHint); + return false; +} + +static void rewriteAccessChain(Instruction *Insn, + SmallVector &GEPs, + SmallVector &Visited, + bool AllowPatial, bool &StillUsed); + +static void rewriteUses(Instruction *Insn, + SmallVector &GEPs, + SmallVector &Visited, bool AllowPatial, + bool &StillUsed) { + for (User *U : Insn->users()) { + auto *UI = dyn_cast(U); + if (UI && (isPointerOperand(Insn, UI) || isPreserveStaticOffsetCall(UI) || + isInlineableCall(UI))) + rewriteAccessChain(UI, GEPs, Visited, AllowPatial, StillUsed); + else + LLVM_DEBUG({ + llvm::dbgs() << "unsupported usage in BPFPreserveStaticOffsetPass:\n"; + llvm::dbgs() << " Insn: " << *Insn << "\n"; + llvm::dbgs() << " User: " << *U << "\n"; + }); + } +} + +// A DFS traversal of GEP chain trees starting from Root. +// +// Recursion descends through GEP instructions and +// llvm.preserve.static.offset calls. Recursion stops at any other +// instruction. If load or store instruction is reached it is replaced +// by a call to `llvm.bpf.getelementptr.and.load` or +// `llvm.bpf.getelementptr.and.store` intrinsic. +// If `llvm.bpf.getelementptr.and.load/store` is reached the accumulated +// GEPs are merged into the intrinsic call. +// If nested calls to `llvm.preserve.static.offset` are encountered these +// calls are marked for deletion. +// +// Parameters description: +// - Insn - current position in the tree +// - GEPs - GEP instructions for the current branch +// - Visited - a list of visited instructions in DFS order, +// order is important for unused instruction deletion. +// - AllowPartial - when true GEP chains that can't be folded are +// not reported, otherwise diagnostic message is show for such chains. +// - StillUsed - set to true if one of the GEP chains could not be +// folded, makes sense when AllowPartial is false, means that root +// preserve.static.offset call is still in use and should remain +// until the next run of this pass. +static void rewriteAccessChain(Instruction *Insn, + SmallVector &GEPs, + SmallVector &Visited, + bool AllowPatial, bool &StillUsed) { + auto MarkAndTraverseUses = [&]() { + Visited.push_back(Insn); + rewriteUses(Insn, GEPs, Visited, AllowPatial, StillUsed); + }; + auto TryToReplace = [&](Instruction *LoadOrStore) { + // Do nothing for (preserve.static.offset (load/store ..)) or for + // GEPs with zero indices. Such constructs lead to zero offset and + // are simplified by other passes. + if (allZeroIndices(GEPs)) + return; + if (tryToReplaceWithGEPBuiltin(LoadOrStore, GEPs, Insn)) { + Visited.push_back(Insn); + return; + } + if (!AllowPatial) + reportNonStaticGEPChain(Insn); + StillUsed = true; + }; + if (isa(Insn) || isa(Insn)) { + TryToReplace(Insn); + } else if (isGEPAndLoad(Insn)) { + auto [GEP, Load] = + BPFPreserveStaticOffsetPass::reconstructLoad(cast(Insn)); + GEPs.push_back(GEP); + TryToReplace(Load); + GEPs.pop_back(); + delete Load; + delete GEP; + } else if (isGEPAndStore(Insn)) { + // This case can't be merged with the above because + // `delete Load` / `delete Store` wants a concrete type, + // destructor of Instruction is protected. + auto [GEP, Store] = + BPFPreserveStaticOffsetPass::reconstructStore(cast(Insn)); + GEPs.push_back(GEP); + TryToReplace(Store); + GEPs.pop_back(); + delete Store; + delete GEP; + } else if (auto *GEP = dyn_cast(Insn)) { + GEPs.push_back(GEP); + MarkAndTraverseUses(); + GEPs.pop_back(); + } else if (isPreserveStaticOffsetCall(Insn)) { + MarkAndTraverseUses(); + } else if (isInlineableCall(Insn)) { + // Preserve preserve.static.offset call for parameters of + // functions that might be inlined. These would be removed on a + // second pass after inlining. + // Might happen when a pointer to a preserve_static_offset + // structure is passed as parameter of a function that would be + // inlined inside a loop that would be unrolled. + if (AllowPatial) + StillUsed = true; + } else { + SmallString<128> Buf; + raw_svector_ostream BufStream(Buf); + BufStream << *Insn; + report_fatal_error( + Twine("Unexpected rewriteAccessChain Insn = ").concat(Buf)); + } +} + +static void removeMarkerCall(Instruction *Marker) { + Marker->replaceAllUsesWith(Marker->getOperand(0)); + Marker->eraseFromParent(); +} + +static bool rewriteAccessChain(Instruction *Marker, bool AllowPatial, + SmallPtrSetImpl &RemovedMarkers) { + SmallVector GEPs; + SmallVector Visited; + bool StillUsed = false; + rewriteUses(Marker, GEPs, Visited, AllowPatial, StillUsed); + // Check if Visited instructions could be removed, iterate in + // reverse to unblock instructions higher in the chain. + for (auto V = Visited.rbegin(); V != Visited.rend(); ++V) { + if (isPreserveStaticOffsetCall(*V)) { + removeMarkerCall(*V); + RemovedMarkers.insert(*V); + } else if ((*V)->use_empty()) { + (*V)->eraseFromParent(); + } + } + return StillUsed; +} + +static std::vector +collectPreserveStaticOffsetCalls(Function &F) { + std::vector Calls; + for (Instruction &Insn : instructions(F)) + if (isPreserveStaticOffsetCall(&Insn)) + Calls.push_back(&Insn); + return Calls; +} + +bool isPreserveArrayIndex(Value *V) { + return isIntrinsicCall(V, Intrinsic::preserve_array_access_index); +} + +bool isPreserveStructIndex(Value *V) { + return isIntrinsicCall(V, Intrinsic::preserve_struct_access_index); +} + +bool isPreserveUnionIndex(Value *V) { + return isIntrinsicCall(V, Intrinsic::preserve_union_access_index); +} + +static void removePAICalls(Instruction *Marker) { + auto IsPointerOperand = [](Value *Op, User *U) { + if (auto *GEP = dyn_cast(U)) + return GEP->getPointerOperand() == Op; + if (isPreserveStaticOffsetCall(U) || isPreserveArrayIndex(U) || + isPreserveStructIndex(U) || isPreserveUnionIndex(U)) + return cast(U)->getArgOperand(0) == Op; + return false; + }; + + SmallVector WorkList; + WorkList.push_back(Marker); + do { + Value *V = WorkList.pop_back_val(); + for (User *U : V->users()) + if (IsPointerOperand(V, U)) + WorkList.push_back(U); + auto *Call = dyn_cast(V); + if (!Call) + continue; + if (isPreserveArrayIndex(V)) + BPFCoreSharedInfo::removeArrayAccessCall(Call); + if (isPreserveStructIndex(V)) + BPFCoreSharedInfo::removeStructAccessCall(Call); + if (isPreserveUnionIndex(V)) + BPFCoreSharedInfo::removeUnionAccessCall(Call); + } while (!WorkList.empty()); +} + +// Look for sequences: +// - llvm.preserve.static.offset -> getelementptr... -> load +// - llvm.preserve.static.offset -> getelementptr... -> store +// And replace those with calls to intrinsics: +// - llvm.bpf.getelementptr.and.load +// - llvm.bpf.getelementptr.and.store +static bool rewriteFunction(Function &F, bool AllowPartial) { + LLVM_DEBUG(dbgs() << "********** BPFPreserveStaticOffsetPass (AllowPartial=" + << AllowPartial << ") ************\n"); + + auto MarkerCalls = collectPreserveStaticOffsetCalls(F); + SmallPtrSet RemovedMarkers; + + LLVM_DEBUG(dbgs() << "There are " << MarkerCalls.size() + << " preserve.static.offset calls\n"); + + if (MarkerCalls.empty()) + return false; + + for (auto *Call : MarkerCalls) + removePAICalls(Call); + + for (auto *Call : MarkerCalls) { + if (RemovedMarkers.contains(Call)) + continue; + bool StillUsed = rewriteAccessChain(Call, AllowPartial, RemovedMarkers); + if (!StillUsed || !AllowPartial) + removeMarkerCall(Call); + } + + return true; +} + +PreservedAnalyses +llvm::BPFPreserveStaticOffsetPass::run(Function &F, + FunctionAnalysisManager &AM) { + return rewriteFunction(F, AllowPartial) ? PreservedAnalyses::none() + : PreservedAnalyses::all(); +} diff --git a/llvm/lib/Target/BPF/BPFTargetMachine.cpp b/llvm/lib/Target/BPF/BPFTargetMachine.cpp index 983a4ff6aa5c..65286c822c4b 100644 --- a/llvm/lib/Target/BPF/BPFTargetMachine.cpp +++ b/llvm/lib/Target/BPF/BPFTargetMachine.cpp @@ -105,11 +105,16 @@ void BPFTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) { FPM.addPass(BPFIRPeepholePass()); return true; } + if (PassName == "bpf-preserve-static-offset") { + FPM.addPass(BPFPreserveStaticOffsetPass(false)); + return true; + } return false; }); PB.registerPipelineStartEPCallback( [=](ModulePassManager &MPM, OptimizationLevel) { FunctionPassManager FPM; + FPM.addPass(BPFPreserveStaticOffsetPass(true)); FPM.addPass(BPFAbstractMemberAccessPass(this)); FPM.addPass(BPFPreserveDITypePass()); FPM.addPass(BPFIRPeepholePass()); @@ -119,6 +124,12 @@ void BPFTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) { OptimizationLevel Level) { FPM.addPass(SimplifyCFGPass(SimplifyCFGOptions().hoistCommonInsts(true))); }); + PB.registerScalarOptimizerLateEPCallback( + [=](FunctionPassManager &FPM, OptimizationLevel Level) { + // Run this after loop unrolling but before + // SimplifyCFGPass(... .sinkCommonInsts(true)) + FPM.addPass(BPFPreserveStaticOffsetPass(false)); + }); PB.registerPipelineEarlySimplificationEPCallback( [=](ModulePassManager &MPM, OptimizationLevel) { MPM.addPass(BPFAdjustOptPass()); diff --git a/llvm/lib/Target/BPF/CMakeLists.txt b/llvm/lib/Target/BPF/CMakeLists.txt index f4a8fa3674cd..6a96394a6aee 100644 --- a/llvm/lib/Target/BPF/CMakeLists.txt +++ b/llvm/lib/Target/BPF/CMakeLists.txt @@ -26,6 +26,7 @@ add_llvm_target(BPFCodeGen BPFISelLowering.cpp BPFMCInstLower.cpp BPFPreserveDIType.cpp + BPFPreserveStaticOffset.cpp BPFRegisterInfo.cpp BPFSelectionDAGInfo.cpp BPFSubtarget.cpp diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-align.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-align.ll new file mode 100644 index 000000000000..0a0f3c22e374 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-align.ll @@ -0,0 +1,66 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check handling of a load instruction for a field with non-standard +; alignment by bpf-preserve-static-offset. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; typedef int aligned_int __attribute__((aligned(128))); +; +; struct foo { +; int _; +; aligned_int a; +; } __ctx; +; +; extern void consume(int); +; +; void bar(struct foo *p) { +; consume(p->a); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.foo = type { i32, [124 x i8], i32, [124 x i8] } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %a = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 2 + %1 = load i32, ptr %a, align 128, !tbaa !2 + call void @consume(i32 noundef %1) + ret void +} + +; CHECK: %[[a1:.*]] = call i32 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 +; CHECK-SAME: (ptr readonly elementtype(%struct.foo) %{{[^,]+}}, +; CHECK-SAME: i1 false, i8 0, i8 1, i8 7, i1 true, i32 immarg 0, i32 immarg 2) +; ^^^^ +; alignment 2**7 +; CHECK-SAME: #[[v2:.*]], !tbaa +; CHECK-NEXT: call void @consume(i32 noundef %[[a1]]) +; CHECK: attributes #[[v2]] = { memory(argmem: read) } + +declare void @consume(i32 noundef) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 128} +!3 = !{!"foo", !4, i64 0, !4, i64 128} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-arr-pai.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-arr-pai.ll new file mode 100644 index 000000000000..d6b1f30fa386 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-arr-pai.ll @@ -0,0 +1,93 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; #define __pai __attribute__((preserve_access_index)) +; +; struct bar { +; int a[7]; +; } __pai __ctx; +; +; int buz(struct bar *p) { +; return p->a[5]; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -debug-info-kind=limited -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.bar = type { [7 x i32] } + +; Function Attrs: nounwind +define dso_local i32 @buz(ptr noundef %p) #0 !dbg !10 { +entry: + call void @llvm.dbg.value(metadata ptr %p, metadata !18, metadata !DIExpression()), !dbg !19 + %0 = call ptr @llvm.preserve.static.offset(ptr %p), !dbg !20 + %1 = call ptr @llvm.preserve.struct.access.index.p0.p0(ptr elementtype(%struct.bar) %0, i32 0, i32 0), !dbg !20, !llvm.preserve.access.index !14 + %2 = call ptr @llvm.preserve.array.access.index.p0.p0(ptr elementtype([7 x i32]) %1, i32 1, i32 5), !dbg !21, !llvm.preserve.access.index !3 + %3 = load i32, ptr %2, align 4, !dbg !21, !tbaa !22 + ret i32 %3, !dbg !26 +} + +; CHECK: define dso_local i32 @buz(ptr noundef %[[p:.*]]) {{.*}} { +; CHECK-NEXT: entry: +; CHECK-NEXT: call void @llvm.dbg.value +; CHECK-NEXT: %[[v5:.*]] = call i32 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 +; CHECK-SAME: (ptr readonly elementtype(%struct.bar) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 0, i32 immarg 5) +; CHECK-SAME: #[[v6:.*]], !tbaa +; CHECK-NEXT: ret i32 %[[v5]] +; CHECK-NEXT: } +; CHECK: attributes #[[v6]] = { memory(argmem: read) } + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) +declare ptr @llvm.preserve.struct.access.index.p0.p0(ptr, i32 immarg, i32 immarg) #2 + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) +declare ptr @llvm.preserve.array.access.index.p0.p0(ptr, i32 immarg, i32 immarg) #2 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare void @llvm.dbg.value(metadata, metadata, metadata) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!7, !8} +!llvm.ident = !{!9} + +!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, retainedTypes: !2, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "some-file.c", directory: "/some/dir/") +!2 = !{!3} +!3 = !DICompositeType(tag: DW_TAG_array_type, baseType: !4, size: 224, elements: !5) +!4 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!5 = !{!6} +!6 = !DISubrange(count: 7) +!7 = !{i32 2, !"Debug Info Version", i32 3} +!8 = !{i32 1, !"wchar_size", i32 4} +!9 = !{!"clang"} +!10 = distinct !DISubprogram(name: "buz", scope: !1, file: !1, line: 8, type: !11, scopeLine: 8, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !17) +!11 = !DISubroutineType(types: !12) +!12 = !{!4, !13} +!13 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !14, size: 64) +!14 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "bar", file: !1, line: 4, size: 224, elements: !15) +!15 = !{!16} +!16 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !14, file: !1, line: 5, baseType: !3, size: 224) +!17 = !{!18} +!18 = !DILocalVariable(name: "p", arg: 1, scope: !10, file: !1, line: 8, type: !13) +!19 = !DILocation(line: 0, scope: !10) +!20 = !DILocation(line: 9, column: 13, scope: !10) +!21 = !DILocation(line: 9, column: 10, scope: !10) +!22 = !{!23, !23, i64 0} +!23 = !{!"int", !24, i64 0} +!24 = !{!"omnipotent char", !25, i64 0} +!25 = !{!"Simple C/C++ TBAA"} +!26 = !DILocation(line: 9, column: 3, scope: !10) diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-atomic.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-atomic.ll new file mode 100644 index 000000000000..0a0c8ce9af5f --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-atomic.ll @@ -0,0 +1,66 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check handling of atomic load instruction by bpf-preserve-static-offset. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int _; +; int a; +; } __ctx; +; +; extern void consume(int); +; +; void bar(struct foo *p) { +; int r; +; __atomic_load(&p->a, &r, 2); +; consume(r); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.foo = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %a = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 + %1 = load atomic i32, ptr %a acquire, align 4 + call void @consume(i32 noundef %1) + ret void +} + +; CHECK: %[[a1:.*]] = call i32 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 +; CHECK-SAME: (ptr elementtype(%struct.foo) %[[p:.*]], +; i1 false, i8 4, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1) +; ^^^^ +; atomic order +; CHECK-NOT: #{{[0-9]+}} +; CHECK-NEXT: call void @consume(i32 noundef %[[a1]]) + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) +declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +declare void @consume(i32 noundef) #3 + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) +declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-2.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-2.ll new file mode 100644 index 000000000000..4832fb2a50c0 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-2.ll @@ -0,0 +1,82 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that bpf-preserve-static-offset folds GEP chains that end by +; getelementptr.and.load. +; +; Source (modified by hand): +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct bar { +; int aa; +; int bb; +; }; +; +; struct foo { +; int a; +; struct bar b; +; } __ctx; +; +; extern void consume(int); +; +; void bar(struct foo *p) { +; consume(p->b.bb); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - +; +; And modified to fold last getelementptr/load as a single +; getelementptr.and.load. + +%struct.foo = type { i32, %struct.bar } +%struct.bar = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 + %bb1 = call i32 (ptr, i1, i8, i8, i8, i1, ...) + @llvm.bpf.getelementptr.and.load.i32 + (ptr readonly elementtype(%struct.bar) %b, + i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1) + #4, !tbaa !2 + call void @consume(i32 noundef %bb1) + ret void +} + +; CHECK: define dso_local void @bar(ptr noundef %[[p:.*]]) +; CHECK: %[[bb1:.*]] = call i32 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 +; CHECK-SAME: (ptr readonly elementtype(%struct.foo) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1, i32 immarg 1) +; CHECK-SAME: #[[v2:.*]], !tbaa +; CHECK-NEXT: call void @consume(i32 noundef %[[bb1]]) +; CHECK: attributes #[[v2]] = { memory(argmem: read) } + +declare void @consume(i32 noundef) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +; Function Attrs: nocallback nofree nounwind willreturn +declare i32 @llvm.bpf.getelementptr.and.load.i32(ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #3 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #3 = { nocallback nofree nounwind willreturn } +attributes #4 = { memory(argmem: read) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 8} +!3 = !{!"foo", !4, i64 0, !7, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} +!7 = !{!"bar", !4, i64 0, !4, i64 4} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-oob.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-oob.ll new file mode 100644 index 000000000000..c4a92481a0b1 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-oob.ll @@ -0,0 +1,73 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that bpf-preserve-static-offset keeps track of 'inbounds' flags while +; folding chain of GEP instructions. +; +; Source (IR modified by hand): +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int a[2]; +; }; +; +; struct bar { +; int a; +; struct foo b; +; } __ctx; +; +; extern void consume(int); +; +; void buz(struct bar *p) { +; consume(p->b.a[1]); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - +; +; Modified to remove one of the 'inbounds' from one of the GEP instructions. + +%struct.bar = type { i32, %struct.foo } +%struct.foo = type { [2 x i32] } + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.bar, ptr %0, i32 0, i32 1 + %a = getelementptr %struct.foo, ptr %b, i32 0, i32 0 + %arrayidx = getelementptr inbounds [2 x i32], ptr %a, i64 0, i64 1 + %1 = load i32, ptr %arrayidx, align 4, !tbaa !2 + call void @consume(i32 noundef %1) + ret void +} + +; CHECK: %[[v1:.*]] = call i32 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 +; CHECK-SAME: (ptr readonly elementtype(%struct.bar) %{{[^,]+}}, +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 false, +; ^^^^^^^^ +; not inbounds +; CHECK-SAME: i32 immarg 0, i32 immarg 1, i32 immarg 0, i64 immarg 1) +; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +; folded gep chain +; CHECK-NEXT: call void @consume(i32 noundef %[[v1]]) + +declare void @consume(i32 noundef) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !3, i64 0} +!3 = !{!"int", !4, i64 0} +!4 = !{!"omnipotent char", !5, i64 0} +!5 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8-oob.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8-oob.ll new file mode 100644 index 000000000000..da3e01a455a5 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8-oob.ll @@ -0,0 +1,74 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that bpf-preserve-static-offset folds chain of GEP instructions. +; The GEP chain in this example has unexpected shape and thus is +; folded as i8 access. +; +; Source (IR modified by hand): +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; char a[2]; +; }; +; +; struct bar { +; char a; +; struct foo b; +; } __ctx; +; +; extern void consume(char); +; +; void buz(struct bar *p) { +; consume((&p->b)[1].a[1]); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - +; +; Modified to remove 'inbounds' from one of the GEP instructions. + +%struct.bar = type { i8, %struct.foo } +%struct.foo = type { [2 x i8] } + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.bar, ptr %0, i32 0, i32 1 + %arrayidx = getelementptr inbounds %struct.foo, ptr %b, i64 1 +; ^^^^^ +; folded as i8 access because of this index + %a = getelementptr %struct.foo, ptr %arrayidx, i32 0, i32 0 + %arrayidx1 = getelementptr inbounds [2 x i8], ptr %a, i64 0, i64 1 + %1 = load i8, ptr %arrayidx1, align 1, !tbaa !2 + call void @consume(i8 noundef signext %1) + ret void +} + +; CHECK: %[[v1:.*]] = call i8 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i8 +; CHECK-SAME: (ptr readonly elementtype(i8) %{{[^,]+}}, +; CHECK-SAME: i1 false, i8 0, i8 1, i8 0, i1 false, i64 immarg 4) +; ^^^^^^^^ ^^^^^^^^^^^^ +; not inbounds ---' | +; offset from 'struct bar' start -------------' +; CHECK-NEXT: call void @consume(i8 noundef signext %[[v1]]) + +declare void @consume(i8 noundef signext) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !3, i64 0} +!3 = !{!"omnipotent char", !4, i64 0} +!4 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8-type-mismatch.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8-type-mismatch.ll new file mode 100644 index 000000000000..757e06c507c6 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8-type-mismatch.ll @@ -0,0 +1,73 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that bpf-preserve-static-offset folds chain of GEP instructions. +; The GEP chain in this example has unexpected shape and thus is +; folded as i8 access. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; char aa; +; char bb; +; }; +; +; struct bar { +; char a; +; struct foo b; +; } __ctx; +; +; extern void consume(char); +; +; void buz(struct bar *p) { +; consume(((struct foo *)(((char*)&p->b) + 1))->bb); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.bar = type { i8, %struct.foo } +%struct.foo = type { i8, i8 } + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.bar, ptr %0, i32 0, i32 1 + %add.ptr = getelementptr inbounds i8, ptr %b, i64 1 +; ~~ +; these types do not match, thus GEP chain is folded as an offset +; ~~~~~~~~~~~ + %bb = getelementptr inbounds %struct.foo, ptr %add.ptr, i32 0, i32 1 + %1 = load i8, ptr %bb, align 1, !tbaa !2 + call void @consume(i8 noundef signext %1) + ret void +} + +; CHECK: %[[bb1:.*]] = call i8 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i8 +; CHECK-SAME: (ptr readonly elementtype(i8) %{{[^,]+}}, +; CHECK-SAME: i1 false, i8 0, i8 1, i8 0, i1 true, i64 immarg 3) +; ^^^^^^^^^^^^ +; offset from 'struct bar' start +; CHECK-NEXT: call void @consume(i8 noundef signext %[[bb1]]) + +declare void @consume(i8 noundef signext) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 1} +!3 = !{!"foo", !4, i64 0, !4, i64 1} +!4 = !{!"omnipotent char", !5, i64 0} +!5 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8.ll new file mode 100644 index 000000000000..e91aa93775e1 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8.ll @@ -0,0 +1,71 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that bpf-preserve-static-offset folds chain of GEP instructions. +; The GEP chain in this example has unexpected shape and thus is +; folded as i8 access. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; char a[2]; +; }; +; +; struct bar { +; char a; +; struct foo b; +; } __ctx; +; +; extern void consume(char); +; +; void buz(struct bar *p) { +; consume((&p->b)[1].a[1]); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.bar = type { i8, %struct.foo } +%struct.foo = type { [2 x i8] } + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.bar, ptr %0, i32 0, i32 1 + %arrayidx = getelementptr inbounds %struct.foo, ptr %b, i64 1 +; ^^^^^ +; folded as i8 access because of this index + %a = getelementptr inbounds %struct.foo, ptr %arrayidx, i32 0, i32 0 + %arrayidx1 = getelementptr inbounds [2 x i8], ptr %a, i64 0, i64 1 + %1 = load i8, ptr %arrayidx1, align 1, !tbaa !2 + call void @consume(i8 noundef signext %1) + ret void +} + +; CHECK: %[[v1:.*]] = call i8 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i8 +; CHECK-SAME: (ptr readonly elementtype(i8) %{{[^,]+}}, +; CHECK-SAME: i1 false, i8 0, i8 1, i8 0, i1 true, i64 immarg 4) +; ^^^^^^^^^^^^ +; offset from 'struct bar' start +; CHECK-NEXT: call void @consume(i8 noundef signext %[[v1]]) + +declare void @consume(i8 noundef signext) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !3, i64 0} +!3 = !{!"omnipotent char", !4, i64 0} +!4 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain.ll new file mode 100644 index 000000000000..ac08fed70c8a --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain.ll @@ -0,0 +1,68 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that bpf-preserve-static-offset folds chain of GEP instructions. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int a[2]; +; }; +; +; struct bar { +; int a; +; struct foo b; +; } __ctx; +; +; extern void consume(int); +; +; void buz(struct bar *p) { +; consume(p->b.a[1]); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.bar = type { i32, %struct.foo } +%struct.foo = type { [2 x i32] } + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.bar, ptr %0, i32 0, i32 1 + %a = getelementptr inbounds %struct.foo, ptr %b, i32 0, i32 0 + %arrayidx = getelementptr inbounds [2 x i32], ptr %a, i64 0, i64 1 + %1 = load i32, ptr %arrayidx, align 4, !tbaa !2 + call void @consume(i32 noundef %1) + ret void +} + +; CHECK: %[[v1:.*]] = call i32 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 +; CHECK-SAME: (ptr readonly elementtype(%struct.bar) %{{[^,]+}}, +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, +; CHECK-SAME: i32 immarg 0, i32 immarg 1, i32 immarg 0, i64 immarg 1) +; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +; folded gep chain +; CHECK-NEXT: call void @consume(i32 noundef %[[v1]]) + +declare void @consume(i32 noundef) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !3, i64 0} +!3 = !{!"int", !4, i64 0} +!4 = !{!"omnipotent char", !5, i64 0} +!5 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-inline.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-inline.ll new file mode 100644 index 000000000000..9149b350dd89 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-inline.ll @@ -0,0 +1,85 @@ +; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check position of bpf-preserve-static-offset pass in the pipeline: +; - preserve.static.offset call is preserved if address is passed as +; a parameter to an inline-able function; +; - second bpf-preserve-static-offset pass (after inlining) should introduce +; getelementptr.and.load call using the preserved marker. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct bar { +; int aa; +; int bb; +; }; +; +; struct foo { +; int a; +; struct bar b; +; } __ctx; +; +; extern void consume(int); +; +; static inline void bar(struct bar *p){ +; consume(p->bb); +; } +; +; void quux(struct foo *p) { +; bar(&p->b); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.foo = type { i32, %struct.bar } +%struct.bar = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @quux(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 + call void @bar(ptr noundef %b) + ret void +} + +; Function Attrs: inlinehint nounwind +define internal void @bar(ptr noundef %p) #1 { +entry: + %bb = getelementptr inbounds %struct.bar, ptr %p, i32 0, i32 1 + %0 = load i32, ptr %bb, align 4, !tbaa !2 + call void @consume(i32 noundef %0) + ret void +} + +; CHECK: define dso_local void @quux(ptr nocapture noundef readonly %[[p:.*]]) +; CHECK: %[[bb_i1:.*]] = tail call i32 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 +; CHECK-SAME: (ptr readonly elementtype(%struct.foo) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i64 immarg 0, i32 immarg 1, i32 immarg 1) +; CHECK-SAME: #[[v2:.*]], !tbaa +; CHECK-NEXT: tail call void @consume(i32 noundef %[[bb_i1]]) +; CHECK: attributes #[[v2]] = { memory(argmem: read) } + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +declare void @consume(i32 noundef) #3 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { inlinehint nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 4} +!3 = !{!"bar", !4, i64 0, !4, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-non-const.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-non-const.ll new file mode 100644 index 000000000000..2dd6edf4c4b8 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-non-const.ll @@ -0,0 +1,75 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s 2>&1 | FileCheck %s +; +; If load offset is not a constant bpf-preserve-static-offset should report a +; warning and remove preserve.static.offset call. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int a[7]; +; } __ctx; +; +; extern void consume(int); +; +; void bar(struct foo *p, unsigned long i) { +; consume(p->a[i]); +; } +; +; Compilation flag: +; clang -cc1 -O2 -debug-info-kind=line-tables-only -triple bpf \ +; -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +; CHECK: warning: some-file.c:10:11: in function bar void (ptr, i64): +; CHECK-SAME: Non-constant offset in access to a field of a type marked with +; CHECK-SAME: preserve_static_offset might be rejected by BPF verifier + +%struct.foo = type { [7 x i32] } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p, i64 noundef %i) #0 !dbg !5 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p), !dbg !8 + %a = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 0, !dbg !8 + %arrayidx = getelementptr inbounds [7 x i32], ptr %a, i64 0, i64 %i, !dbg !9 + %1 = load i32, ptr %arrayidx, align 4, !dbg !9, !tbaa !10 + call void @consume(i32 noundef %1), !dbg !14 + ret void, !dbg !15 +} + +; CHECK: define dso_local void @bar(ptr noundef %[[p:.*]], i64 noundef %[[i:.*]]) +; CHECK: %[[a:.*]] = getelementptr inbounds %struct.foo, ptr %[[p]], i32 0, i32 0, !dbg +; CHECK-NEXT: %[[arrayidx:.*]] = getelementptr inbounds [7 x i32], ptr %[[a]], i64 0, i64 %[[i]], !dbg +; CHECK-NEXT: %[[v5:.*]] = load i32, ptr %[[arrayidx]], align 4, !dbg {{.*}}, !tbaa +; CHECK-NEXT: call void @consume(i32 noundef %[[v5]]), !dbg + +declare void @consume(i32 noundef) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3} +!llvm.ident = !{!4} + +!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "some-file.c", directory: "/some/dir/") +!2 = !{i32 2, !"Debug Info Version", i32 3} +!3 = !{i32 1, !"wchar_size", i32 4} +!4 = !{!"clang"} +!5 = distinct !DISubprogram(name: "bar", scope: !1, file: !1, line: 9, type: !6, scopeLine: 9, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0) +!6 = !DISubroutineType(types: !7) +!7 = !{} +!8 = !DILocation(line: 10, column: 14, scope: !5) +!9 = !DILocation(line: 10, column: 11, scope: !5) +!10 = !{!11, !11, i64 0} +!11 = !{!"int", !12, i64 0} +!12 = !{!"omnipotent char", !13, i64 0} +!13 = !{!"Simple C/C++ TBAA"} +!14 = !DILocation(line: 10, column: 3, scope: !5) +!15 = !DILocation(line: 11, column: 1, scope: !5) diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-ptr-pai.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-ptr-pai.ll new file mode 100644 index 000000000000..6ec59c6b2c02 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-ptr-pai.ll @@ -0,0 +1,114 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; #define __pai __attribute__((preserve_access_index)) +; +; struct bar { +; int a; +; int b; +; } __pai; +; +; struct buz { +; int _1; +; struct bar *b; +; } __pai __ctx; +; +; void foo(struct buz *p) { +; p->b->b = 42; +; } +; +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes \ +; -debug-info-kind=limited -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.buz = type { i32, ptr } +%struct.bar = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @foo(ptr noundef %p) #0 !dbg !5 { +entry: + call void @llvm.dbg.value(metadata ptr %p, metadata !20, metadata !DIExpression()), !dbg !21 + %0 = call ptr @llvm.preserve.static.offset(ptr %p), !dbg !22 + %1 = call ptr @llvm.preserve.struct.access.index.p0.p0(ptr elementtype(%struct.buz) %0, i32 1, i32 1), !dbg !22, !llvm.preserve.access.index !9 + %2 = load ptr, ptr %1, align 8, !dbg !22, !tbaa !23 + %3 = call ptr @llvm.preserve.struct.access.index.p0.p0(ptr elementtype(%struct.bar) %2, i32 1, i32 1), !dbg !29, !llvm.preserve.access.index !15 + store i32 42, ptr %3, align 4, !dbg !30, !tbaa !31 + ret void, !dbg !33 +} + +; CHECK: define dso_local void @foo(ptr noundef %[[p:.*]]) {{.*}} { +; CHECK-NEXT: entry: +; CHECK-NEXT: call void @llvm.dbg.value +; CHECK-NEXT: %[[v5:.*]] = call ptr (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.p0 +; CHECK-SAME: (ptr readonly elementtype(%struct.buz) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 3, i1 true, i32 immarg 0, i32 immarg 1) +; CHECK-SAME: #[[v6:.*]], !tbaa +; CHECK-NEXT: %[[v8:.*]] = +; CHECK-SAME: call ptr @llvm.preserve.struct.access.index.p0.p0 +; CHECK-SAME: (ptr elementtype(%struct.bar) %[[v5]], i32 1, i32 1), +; CHECK-SAME: !dbg ![[#]], !llvm.preserve.access.index ![[#]] +; CHECK-NEXT: store i32 42, ptr %[[v8]], align 4, !dbg ![[#]], !tbaa +; CHECK-NEXT: ret void, !dbg +; CHECK-NEXT: } + +; CHECK : attributes #[[v6]] = { memory(argmem: read) } + + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) +declare ptr @llvm.preserve.struct.access.index.p0.p0(ptr, i32 immarg, i32 immarg) #2 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare void @llvm.dbg.value(metadata, metadata, metadata) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3} +!llvm.ident = !{!4} + +!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "some-file.c", directory: "/some/dir/") +!2 = !{i32 2, !"Debug Info Version", i32 3} +!3 = !{i32 1, !"wchar_size", i32 4} +!4 = !{!"clang"} +!5 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 14, type: !6, scopeLine: 14, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !19) +!6 = !DISubroutineType(types: !7) +!7 = !{null, !8} +!8 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !9, size: 64) +!9 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "buz", file: !1, line: 9, size: 128, elements: !10) +!10 = !{!11, !13} +!11 = !DIDerivedType(tag: DW_TAG_member, name: "_1", scope: !9, file: !1, line: 10, baseType: !12, size: 32) +!12 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!13 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !9, file: !1, line: 11, baseType: !14, size: 64, offset: 64) +!14 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !15, size: 64) +!15 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "bar", file: !1, line: 4, size: 64, elements: !16) +!16 = !{!17, !18} +!17 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !15, file: !1, line: 5, baseType: !12, size: 32) +!18 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !15, file: !1, line: 6, baseType: !12, size: 32, offset: 32) +!19 = !{!20} +!20 = !DILocalVariable(name: "p", arg: 1, scope: !5, file: !1, line: 14, type: !8) +!21 = !DILocation(line: 0, scope: !5) +!22 = !DILocation(line: 15, column: 6, scope: !5) +!23 = !{!24, !28, i64 8} +!24 = !{!"buz", !25, i64 0, !28, i64 8} +!25 = !{!"int", !26, i64 0} +!26 = !{!"omnipotent char", !27, i64 0} +!27 = !{!"Simple C/C++ TBAA"} +!28 = !{!"any pointer", !26, i64 0} +!29 = !DILocation(line: 15, column: 9, scope: !5) +!30 = !DILocation(line: 15, column: 11, scope: !5) +!31 = !{!32, !25, i64 4} +!32 = !{!"bar", !25, i64 0, !25, i64 4} +!33 = !DILocation(line: 16, column: 1, scope: !5) diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-simple.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-simple.ll new file mode 100644 index 000000000000..03ae7f3272dc --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-simple.ll @@ -0,0 +1,71 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check handling of a simple load instruction by bpf-preserve-static-offset. +; Verify: +; - presence of gep.and.load intrinsic call +; - correct attributes for intrinsic call +; - presence of tbaa annotations +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int _; +; int a; +; } __ctx; +; +; extern void consume(int); +; +; void bar(struct foo *p) { +; consume(p->a); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.foo = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %a = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 + %1 = load i32, ptr %a, align 4, !tbaa !2 + call void @consume(i32 noundef %1) + ret void +} + +; CHECK: define dso_local void @bar(ptr noundef %[[p:.*]]) +; CHECK: %[[a1:.*]] = call i32 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 +; CHECK-SAME: (ptr readonly elementtype(%struct.foo) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1) +; CHECK-SAME: #[[v1:.*]], !tbaa +; CHECK-NEXT: call void @consume(i32 noundef %[[a1]]) + +; CHECK: declare i32 +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32(ptr nocapture, {{.*}}) #[[v2:.*]] + +; CHECK: attributes #[[v2]] = { nocallback nofree nounwind willreturn } +; CHECK: attributes #[[v1]] = { memory(argmem: read) } + +declare void @consume(i32 noundef) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 4} +!3 = !{!"foo", !4, i64 0, !4, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-struct-pai.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-struct-pai.ll new file mode 100644 index 000000000000..5baa7ad0242c --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-struct-pai.ll @@ -0,0 +1,105 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; #define __pai __attribute__((preserve_access_index)) +; +; struct foo { +; int a; +; int b; +; }; +; +; struct bar { +; int _1; +; int _2; +; struct foo c; +; } __pai __ctx; +; +; int buz(struct bar *p) { +; return p->c.b; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes \ +; -debug-info-kind=limited -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.bar = type { i32, i32, %struct.foo } +%struct.foo = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local i32 @buz(ptr noundef %p) #0 !dbg !5 { +entry: + call void @llvm.dbg.value(metadata ptr %p, metadata !20, metadata !DIExpression()), !dbg !21 + %0 = call ptr @llvm.preserve.static.offset(ptr %p), !dbg !22 + %1 = call ptr @llvm.preserve.struct.access.index.p0.p0(ptr elementtype(%struct.bar) %0, i32 2, i32 2), !dbg !22, !llvm.preserve.access.index !10 + %b = getelementptr inbounds %struct.foo, ptr %1, i32 0, i32 1, !dbg !23 + %2 = load i32, ptr %b, align 4, !dbg !23, !tbaa !24 + ret i32 %2, !dbg !30 +} + +; CHECK: define dso_local i32 @buz(ptr noundef %[[p:.*]]) {{.*}} { +; CHECK-NEXT: entry: +; CHECK-NEXT: call void @llvm.dbg.value +; CHECK-NEXT: %[[b1:.*]] = call i32 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 +; CHECK-SAME: (ptr readonly elementtype(%struct.bar) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 2, i32 immarg 1) +; CHECK-SAME: #[[v5:.*]], !tbaa +; CHECK-NEXT: ret i32 %[[b1]] +; CHECK-NEXT: } + +; CHECK: attributes #[[v5]] = { memory(argmem: read) } + + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) +declare ptr @llvm.preserve.struct.access.index.p0.p0(ptr, i32 immarg, i32 immarg) #2 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare void @llvm.dbg.value(metadata, metadata, metadata) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3} +!llvm.ident = !{!4} + +!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "some-file.c", directory: "/some/dir/") +!2 = !{i32 2, !"Debug Info Version", i32 3} +!3 = !{i32 1, !"wchar_size", i32 4} +!4 = !{!"clang"} +!5 = distinct !DISubprogram(name: "buz", scope: !1, file: !1, line: 15, type: !6, scopeLine: 15, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !19) +!6 = !DISubroutineType(types: !7) +!7 = !{!8, !9} +!8 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!9 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !10, size: 64) +!10 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "bar", file: !1, line: 9, size: 128, elements: !11) +!11 = !{!12, !13, !14} +!12 = !DIDerivedType(tag: DW_TAG_member, name: "_1", scope: !10, file: !1, line: 10, baseType: !8, size: 32) +!13 = !DIDerivedType(tag: DW_TAG_member, name: "_2", scope: !10, file: !1, line: 11, baseType: !8, size: 32, offset: 32) +!14 = !DIDerivedType(tag: DW_TAG_member, name: "c", scope: !10, file: !1, line: 12, baseType: !15, size: 64, offset: 64) +!15 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "foo", file: !1, line: 4, size: 64, elements: !16) +!16 = !{!17, !18} +!17 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !15, file: !1, line: 5, baseType: !8, size: 32) +!18 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !15, file: !1, line: 6, baseType: !8, size: 32, offset: 32) +!19 = !{!20} +!20 = !DILocalVariable(name: "p", arg: 1, scope: !5, file: !1, line: 15, type: !9) +!21 = !DILocation(line: 0, scope: !5) +!22 = !DILocation(line: 16, column: 13, scope: !5) +!23 = !DILocation(line: 16, column: 15, scope: !5) +!24 = !{!25, !26, i64 12} +!25 = !{!"bar", !26, i64 0, !26, i64 4, !29, i64 8} +!26 = !{!"int", !27, i64 0} +!27 = !{!"omnipotent char", !28, i64 0} +!28 = !{!"Simple C/C++ TBAA"} +!29 = !{!"foo", !26, i64 0, !26, i64 4} +!30 = !DILocation(line: 16, column: 3, scope: !5) diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-align.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-align.ll new file mode 100644 index 000000000000..019c93c424b1 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-align.ll @@ -0,0 +1,67 @@ +; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that getelementptr.and.load unroll restores alignment spec. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; typedef int aligned_int __attribute__((aligned(128))); +; +; struct foo { +; int _; +; aligned_int a; +; } __ctx; +; +; extern void consume(int); +; +; void bar(struct foo *p) { +; consume(p->a); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=sroa,bpf-preserve-static-offset -S -o - + +%struct.foo = type { i32, [124 x i8], i32, [124 x i8] } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + %a1 = call i32 (ptr, i1, i8, i8, i8, i1, ...) + @llvm.bpf.getelementptr.and.load.i32 + (ptr readonly elementtype(%struct.foo) %p, + i1 false, i8 0, i8 1, i8 7, i1 true, i32 immarg 0, i32 immarg 2) + #4, !tbaa !2 + call void @consume(i32 noundef %a1) + ret void +} + +; CHECK: define dso_local void @bar(ptr noundef %[[p:.*]]) +; CHECK: %[[a11:.*]] = getelementptr inbounds %struct.foo, ptr %[[p]], i32 0, i32 2 +; CHECK: %[[v2:.*]] = load i32, ptr %[[a11]], align 128 +; CHECK: call void @consume(i32 noundef %[[v2]]) + +declare void @consume(i32 noundef) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +; Function Attrs: nocallback nofree nounwind willreturn +declare i32 @llvm.bpf.getelementptr.and.load.i32(ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #3 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #3 = { nocallback nofree nounwind willreturn } +attributes #4 = { memory(argmem: read) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 128} +!3 = !{!"foo", !4, i64 0, !4, i64 128} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain-oob.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain-oob.ll new file mode 100644 index 000000000000..d8fa3482b6cc --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain-oob.ll @@ -0,0 +1,74 @@ +; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that getelementptr.and.load unroll can skip 'inbounds' flag. +; +; Source (IR modified by hand): +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct bar { +; int aa; +; int bb; +; }; +; +; struct foo { +; int a; +; struct bar b; +; } __ctx; +; +; extern void consume(int); +; +; void buz(struct foo *p) { +; consume(p->b.bb); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=sroa,bpf-preserve-static-offset -S -o - +; +; Modified to set 'inbounds' flag to false. + +%struct.foo = type { i32, %struct.bar } +%struct.bar = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + %bb1 = call i32 (ptr, i1, i8, i8, i8, i1, ...) + @llvm.bpf.getelementptr.and.load.i32 + (ptr readonly elementtype(%struct.foo) %p, + i1 false, i8 0, i8 1, i8 2, i1 false, i32 immarg 0, i32 immarg 1, i32 immarg 1) + #4, !tbaa !2 + call void @consume(i32 noundef %bb1) + ret void +} + +; CHECK: define dso_local void @buz(ptr noundef %[[p:.*]]) +; CHECK: %[[bb11:.*]] = getelementptr %struct.foo, ptr %[[p]], i32 0, i32 1, i32 1 +; CHECK: %[[v2:.*]] = load i32, ptr %[[bb11]], align 4 +; CHECK: call void @consume(i32 noundef %[[v2]]) + +declare void @consume(i32 noundef) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +; Function Attrs: nocallback nofree nounwind willreturn +declare i32 @llvm.bpf.getelementptr.and.load.i32(ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #3 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #3 = { nocallback nofree nounwind willreturn } +attributes #4 = { memory(argmem: read) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 8} +!3 = !{!"foo", !4, i64 0, !7, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} +!7 = !{!"bar", !4, i64 0, !4, i64 4} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain-u8.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain-u8.ll new file mode 100644 index 000000000000..ac6f830bf5d4 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain-u8.ll @@ -0,0 +1,68 @@ +; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check unroll of getelementptr.and.load when direct memory offset is +; used instead of field indexes. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; char aa; +; char bb; +; }; +; +; struct bar { +; char a; +; struct foo b; +; } __ctx; +; +; extern void consume(char); +; +; void buz(struct bar *p) { +; consume(((struct foo *)(((char*)&p->b) + 1))->bb); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=sroa,bpf-preserve-static-offset -S -o - + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + %bb1 = call i8 (ptr, i1, i8, i8, i8, i1, ...) + @llvm.bpf.getelementptr.and.load.i8 + (ptr readonly elementtype(i8) %p, + i1 false, i8 0, i8 1, i8 0, i1 true, i64 immarg 3) + #4, !tbaa !2 + call void @consume(i8 noundef signext %bb1) + ret void +} + +; CHECK: define dso_local void @buz(ptr noundef %[[p:.*]]) +; CHECK: %[[bb11:.*]] = getelementptr inbounds i8, ptr %[[p]], i64 3 +; CHECK: %[[v2:.*]] = load i8, ptr %[[bb11]], align 1 +; CHECK: call void @consume(i8 noundef signext %[[v2]]) + +declare void @consume(i8 noundef signext) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +; Function Attrs: nocallback nofree nounwind willreturn +declare i8 @llvm.bpf.getelementptr.and.load.i8(ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #3 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #3 = { nocallback nofree nounwind willreturn } +attributes #4 = { memory(argmem: read) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 1} +!3 = !{!"foo", !4, i64 0, !4, i64 1} +!4 = !{!"omnipotent char", !5, i64 0} +!5 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain.ll new file mode 100644 index 000000000000..d6ffb270529a --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain.ll @@ -0,0 +1,73 @@ +; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check unroll of getelementptr.and.load when several field indexes +; are specified in a chain. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct bar { +; int aa; +; int bb; +; }; +; +; struct foo { +; int a; +; struct bar b; +; } __ctx; +; +; extern void consume(int); +; +; void buz(struct foo *p) { +; consume(p->b.bb); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=sroa,bpf-preserve-static-offset -S -o - + +%struct.foo = type { i32, %struct.bar } +%struct.bar = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + %bb1 = call i32 (ptr, i1, i8, i8, i8, i1, ...) + @llvm.bpf.getelementptr.and.load.i32 + (ptr readonly elementtype(%struct.foo) %p, + i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1, i32 immarg 1) + #4, !tbaa !2 + call void @consume(i32 noundef %bb1) + ret void +} + +; CHECK: define dso_local void @buz(ptr noundef %[[p:.*]]) +; CHECK: %[[bb11:.*]] = getelementptr inbounds %struct.foo, ptr %[[p]], i32 0, i32 1, i32 1 +; CHECK: %[[v2:.*]] = load i32, ptr %[[bb11]], align 4 +; CHECK: call void @consume(i32 noundef %[[v2]]) + +declare void @consume(i32 noundef) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +; Function Attrs: nocallback nofree nounwind willreturn +declare i32 @llvm.bpf.getelementptr.and.load.i32(ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #3 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #3 = { nocallback nofree nounwind willreturn } +attributes #4 = { memory(argmem: read) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 8} +!3 = !{!"foo", !4, i64 0, !7, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} +!7 = !{!"bar", !4, i64 0, !4, i64 4} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-simple.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-simple.ll new file mode 100644 index 000000000000..ae19dd7ad98d --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-simple.ll @@ -0,0 +1,65 @@ +; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check unroll of getelementptr.and.load. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int a; +; int b; +; } __ctx; +; +; extern void consume(int); +; +; void bar(struct foo *p){ +; consume(p->b); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=sroa,bpf-preserve-static-offset -S -o - + +%struct.foo = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + %b1 = call i32 (ptr, i1, i8, i8, i8, i1, ...) + @llvm.bpf.getelementptr.and.load.i32 + (ptr readonly elementtype(%struct.foo) %p, + i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1) + #4, !tbaa !2 + call void @consume(i32 noundef %b1) + ret void +} + +; CHECK: define dso_local void @bar(ptr noundef %[[p:.*]]) #[[v1:.*]] { +; CHECK: %[[b11:.*]] = getelementptr inbounds %struct.foo, ptr %[[p]], i32 0, i32 1 +; CHECK-NEXT: %[[v2:.*]] = load i32, ptr %[[b11]], align 4 +; CHECK-NEXT: call void @consume(i32 noundef %[[v2]]) + +declare void @consume(i32 noundef) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +; Function Attrs: nocallback nofree nounwind willreturn +declare i32 @llvm.bpf.getelementptr.and.load.i32(ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #3 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #3 = { nocallback nofree nounwind willreturn } +attributes #4 = { memory(argmem: read) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 4} +!3 = !{!"foo", !4, i64 0, !4, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-volatile.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-volatile.ll new file mode 100644 index 000000000000..d9634a3fc3a9 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-volatile.ll @@ -0,0 +1,64 @@ +; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that unroll of getelementptr.and.load restores volatile. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int a; +; volatile int b; +; } __ctx; +; +; extern void consume(int); +; +; void bar(struct foo *p){ +; consume(p->b); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=sroa,bpf-preserve-static-offset -S -o - + +%struct.foo = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + %b1 = call i32 (ptr, i1, i8, i8, i8, i1, ...) + @llvm.bpf.getelementptr.and.load.i32 + (ptr elementtype(%struct.foo) %p, + i1 true, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1), + !tbaa !2 + call void @consume(i32 noundef %b1) + ret void +} + +; CHECK: define dso_local void @bar(ptr noundef %[[p:.*]]) +; CHECK: %[[b11:.*]] = getelementptr inbounds %struct.foo, ptr %[[p]], i32 0, i32 1 +; CHECK: %[[v2:.*]] = load volatile i32, ptr %[[b11]], align 4 +; CHECK: call void @consume(i32 noundef %[[v2]]) + +declare void @consume(i32 noundef) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +; Function Attrs: nocallback nofree nounwind willreturn +declare i32 @llvm.bpf.getelementptr.and.load.i32(ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #3 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #3 = { nocallback nofree nounwind willreturn } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 4} +!3 = !{!"foo", !4, i64 0, !4, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-union-pai.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-union-pai.ll new file mode 100644 index 000000000000..f90e3c54b072 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-union-pai.ll @@ -0,0 +1,110 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; #define __pai __attribute__((preserve_access_index)) +; +; struct foo { +; char a[10]; +; } __pai; +; +; struct bar { +; int a; +; int b; +; } __pai; +; +; union buz { +; struct foo a; +; struct bar b; +; } __pai __ctx; +; +; int quux(union buz *p) { +; return p->b.b; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -debug-info-kind=limited -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.bar = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local i32 @quux(ptr noundef %p) #0 !dbg !5 { +entry: + call void @llvm.dbg.value(metadata ptr %p, metadata !26, metadata !DIExpression()), !dbg !27 + %0 = call ptr @llvm.preserve.static.offset(ptr %p), !dbg !28 + %1 = call ptr @llvm.preserve.union.access.index.p0.p0(ptr %0, i32 1), !dbg !28, !llvm.preserve.access.index !10 + %2 = call ptr @llvm.preserve.struct.access.index.p0.p0(ptr elementtype(%struct.bar) %1, i32 1, i32 1), !dbg !29, !llvm.preserve.access.index !21 + %3 = load i32, ptr %2, align 4, !dbg !29, !tbaa !30 + ret i32 %3, !dbg !33 +} + +; CHECK: define dso_local i32 @quux(ptr noundef %[[p:.*]]) {{.*}} { +; CHECK-NEXT: entry: +; CHECK-NEXT: call void @llvm.dbg.value +; CHECK-NEXT: %[[v5:.*]] = call i32 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 +; CHECK-SAME: (ptr readonly elementtype(%struct.bar) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1) +; CHECK-SAME: #[[v6:.*]], !tbaa +; CHECK-NEXT: ret i32 %[[v5]] +; CHECK-NEXT: } +; CHECK: attributes #[[v6]] = { memory(argmem: read) } + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) +declare ptr @llvm.preserve.union.access.index.p0.p0(ptr, i32 immarg) #2 + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) +declare ptr @llvm.preserve.struct.access.index.p0.p0(ptr, i32 immarg, i32 immarg) #2 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare void @llvm.dbg.value(metadata, metadata, metadata) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3} +!llvm.ident = !{!4} + +!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "some-file.c", directory: "/some/dir/") +!2 = !{i32 2, !"Debug Info Version", i32 3} +!3 = !{i32 1, !"wchar_size", i32 4} +!4 = !{!"clang"} +!5 = distinct !DISubprogram(name: "quux", scope: !1, file: !1, line: 18, type: !6, scopeLine: 18, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !25) +!6 = !DISubroutineType(types: !7) +!7 = !{!8, !9} +!8 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!9 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !10, size: 64) +!10 = distinct !DICompositeType(tag: DW_TAG_union_type, name: "buz", file: !1, line: 13, size: 96, elements: !11) +!11 = !{!12, !20} +!12 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !10, file: !1, line: 14, baseType: !13, size: 80) +!13 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "foo", file: !1, line: 4, size: 80, elements: !14) +!14 = !{!15} +!15 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !13, file: !1, line: 5, baseType: !16, size: 80) +!16 = !DICompositeType(tag: DW_TAG_array_type, baseType: !17, size: 80, elements: !18) +!17 = !DIBasicType(name: "char", size: 8, encoding: DW_ATE_signed_char) +!18 = !{!19} +!19 = !DISubrange(count: 10) +!20 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !10, file: !1, line: 15, baseType: !21, size: 64) +!21 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "bar", file: !1, line: 8, size: 64, elements: !22) +!22 = !{!23, !24} +!23 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !21, file: !1, line: 9, baseType: !8, size: 32) +!24 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !21, file: !1, line: 10, baseType: !8, size: 32, offset: 32) +!25 = !{!26} +!26 = !DILocalVariable(name: "p", arg: 1, scope: !5, file: !1, line: 18, type: !9) +!27 = !DILocation(line: 0, scope: !5) +!28 = !DILocation(line: 19, column: 13, scope: !5) +!29 = !DILocation(line: 19, column: 15, scope: !5) +!30 = !{!31, !31, i64 0} +!31 = !{!"omnipotent char", !32, i64 0} +!32 = !{!"Simple C/C++ TBAA"} +!33 = !DILocation(line: 19, column: 3, scope: !5) diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-unroll-inline.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-unroll-inline.ll new file mode 100644 index 000000000000..78172cd17dca --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-unroll-inline.ll @@ -0,0 +1,108 @@ +; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check position of bpf-preserve-static-offset pass in the pipeline: +; - preserve.static.offset call is preserved if address is passed as +; a parameter to an inline-able function; +; - second bpf-preserve-static-offset pass (after inlining) should introduce +; getelementptr.and.load call using the preserved marker after loops +; unrolling; +; - readonly and tbaa attributes should allow replacement of +; getelementptr.and.load calls by CSE transformation. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int a; +; int b[4]; +; } __ctx; +; +; extern void consume(int); +; +; static inline void bar(int * restrict p) { +; consume(p[1]); +; } +; +; void quux(struct foo *p){ +; unsigned long i = 0; +; #pragma clang loop unroll(full) +; while (i < 2) { +; bar(p->b); +; ++i; +; } +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.foo = type { i32, [4 x i32] } + +; Function Attrs: nounwind +define dso_local void @quux(ptr noundef %p) #0 { +entry: + br label %while.cond + +while.cond: ; preds = %while.body, %entry + %i.0 = phi i64 [ 0, %entry ], [ %inc, %while.body ] + %cmp = icmp ult i64 %i.0, 2 + br i1 %cmp, label %while.body, label %while.end + +while.body: ; preds = %while.cond + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 + %arraydecay = getelementptr inbounds [4 x i32], ptr %b, i64 0, i64 0 + call void @bar(ptr noundef %arraydecay) + %inc = add i64 %i.0, 1 + br label %while.cond, !llvm.loop !2 + +while.end: ; preds = %while.cond + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) +declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1 + +; Function Attrs: inlinehint nounwind +define internal void @bar(ptr noalias noundef %p) #2 { +entry: + %arrayidx = getelementptr inbounds i32, ptr %p, i64 1 + %0 = load i32, ptr %arrayidx, align 4, !tbaa !5 + call void @consume(i32 noundef %0) + ret void +} + +; CHECK: define dso_local void @quux(ptr nocapture noundef readonly %[[p:.*]]) +; CHECK: %[[v1:.*]] = tail call i32 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 +; CHECK-SAME: (ptr readonly elementtype(%struct.foo) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i64 immarg 0, i32 immarg 1, i64 immarg 1) +; CHECK: tail call void @consume(i32 noundef %[[v1]]) +; CHECK: tail call void @consume(i32 noundef %[[v1]]) + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #3 + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) +declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1 + +declare void @consume(i32 noundef) #4 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } +attributes #2 = { inlinehint nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #4 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = distinct !{!2, !3, !4} +!3 = !{!"llvm.loop.mustprogress"} +!4 = !{!"llvm.loop.unroll.full"} +!5 = !{!6, !6, i64 0} +!6 = !{!"int", !7, i64 0} +!7 = !{!"omnipotent char", !8, i64 0} +!8 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-unroll.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-unroll.ll new file mode 100644 index 000000000000..7c3303342bb6 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-unroll.ll @@ -0,0 +1,95 @@ +; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check position of bpf-preserve-static-offset pass in the pipeline: +; preserve.static.offset call should be preserved long enough to allow +; introduction of getelementptr.and.load after loops unrolling. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int a; +; int b[4]; +; } __ctx; +; +; extern void consume(int); +; +; void bar(struct foo *p){ +; unsigned long i = 0; +; #pragma clang loop unroll(full) +; while (i < 2) +; consume(p->b[i++]); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.foo = type { i32, [4 x i32] } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + br label %while.cond + +while.cond: ; preds = %while.body, %entry + %i.0 = phi i64 [ 0, %entry ], [ %inc, %while.body ] + %cmp = icmp ult i64 %i.0, 2 + br i1 %cmp, label %while.body, label %while.end + +while.body: ; preds = %while.cond + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 + %inc = add i64 %i.0, 1 + %arrayidx = getelementptr inbounds [4 x i32], ptr %b, i64 0, i64 %i.0 + %1 = load i32, ptr %arrayidx, align 4, !tbaa !2 + call void @consume(i32 noundef %1) + br label %while.cond, !llvm.loop !6 + +while.end: ; preds = %while.cond + ret void +} + +; CHECK: define dso_local void @bar(ptr nocapture noundef readonly %[[p:.*]]) +; CHECK: %[[v1:.*]] = tail call i32 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 +; CHECK-SAME: (ptr readonly elementtype(%struct.foo) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i64 immarg 0, i32 immarg 1, i64 immarg 0) +; CHECK-SAME: #[[attrs:.*]], !tbaa +; CHECK-NEXT: tail call void @consume(i32 noundef %[[v1]]) +; CHECK-NEXT: %[[v2:.*]] = tail call i32 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 +; CHECK-SAME: (ptr readonly elementtype(%struct.foo) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i64 immarg 0, i32 immarg 1, i64 immarg 1) +; CHECK-SAME: #[[attrs]], !tbaa +; CHECK-NEXT: tail call void @consume(i32 noundef %[[v2]]) +; CHECK: attributes #[[attrs]] = { memory(argmem: read) } + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) +declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1 + +declare void @consume(i32 noundef) #2 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #3 + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) +declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } +attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !3, i64 0} +!3 = !{!"int", !4, i64 0} +!4 = !{!"omnipotent char", !5, i64 0} +!5 = !{!"Simple C/C++ TBAA"} +!6 = distinct !{!6, !7, !8} +!7 = !{!"llvm.loop.mustprogress"} +!8 = !{!"llvm.loop.unroll.full"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-volatile.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-volatile.ll new file mode 100644 index 000000000000..819a4b31fb23 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-volatile.ll @@ -0,0 +1,62 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check handling of a volatile load instruction by bpf-preserve-static-offset. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int _; +; volatile int a; +; } __ctx; +; +; extern void consume(int); +; +; void bar(struct foo *p) { +; consume(p->a); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.foo = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %a = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 + %1 = load volatile i32, ptr %a, align 4, !tbaa !2 + call void @consume(i32 noundef %1) + ret void +} + +; CHECK: %[[a1:.*]] = call i32 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 +; CHECK-SAME: (ptr elementtype(%struct.foo) %{{[^,]+}}, +; CHECK-SAME: i1 true, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1) +; ^^^^^^^^ +; volatile +; CHECK-NOT: #{{[0-9]+}} +; CHECK-NEXT: call void @consume(i32 noundef %[[a1]]) + +declare void @consume(i32 noundef) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 4} +!3 = !{!"foo", !4, i64 0, !4, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-zero.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-zero.ll new file mode 100644 index 000000000000..681c9640cbb8 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-zero.ll @@ -0,0 +1,57 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that loads from zero offset are not modified by bpf-preserve-static-offset. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int a; +; } __ctx; +; +; extern void consume(int); +; +; void bar(struct foo *p) { +; consume(p->a); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.foo = type { i32 } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %a = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 0 + %1 = load i32, ptr %a, align 4, !tbaa !2 + call void @consume(i32 noundef %1) + ret void +} + +; CHECK: entry: +; CHECK-NEXT: %[[a:.*]] = getelementptr inbounds %struct.foo, ptr %[[p:.*]], i32 0, i32 0 +; CHECK-NEXT: %[[v2:.*]] = load i32, ptr %[[a]], align 4, !tbaa +; CHECK-NEXT: call void @consume(i32 noundef %[[v2]]) + +declare void @consume(i32 noundef) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 0} +!3 = !{!"foo", !4, i64 0} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-align.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-align.ll new file mode 100644 index 000000000000..667f8f5a8d8b --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-align.ll @@ -0,0 +1,59 @@ +; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check handling of a store instruction for a field with non-standard +; alignment by bpf-preserve-static-offset. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; typedef int aligned_int __attribute__((aligned(128))); +; +; struct foo { +; int _; +; aligned_int a; +; } __ctx; +; +; void bar(struct foo *p) { +; p->a = 7; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.foo = type { i32, [124 x i8], i32, [124 x i8] } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %a = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 2 + store i32 7, ptr %a, align 128, !tbaa !2 + ret void +} + +; CHECK: define dso_local void @bar(ptr nocapture noundef writeonly %[[p:.*]]) +; CHECK: tail call void (i32, ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i32 +; CHECK-SAME: (i32 7, +; CHECK-SAME: ptr writeonly elementtype(%struct.foo) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 7, i1 true, i32 immarg 0, i32 immarg 2) +; CHECK-SAME: #[[v2:.*]], !tbaa +; CHECK: attributes #[[v2]] = { memory(argmem: write) } + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 128} +!3 = !{!"foo", !4, i64 0, !4, i64 128} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-atomic.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-atomic.ll new file mode 100644 index 000000000000..443966337b9d --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-atomic.ll @@ -0,0 +1,60 @@ +; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check handling of atomic store instruction by bpf-preserve-static-offset. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int _; +; int a; +; } __ctx; +; +; void bar(struct foo *p) { +; int r; +; r = 7; +; __atomic_store(&p->a, &r, 3); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.foo = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %a = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 + store atomic i32 7, ptr %a release, align 4 + ret void +} + +; CHECK: define dso_local void @bar(ptr nocapture noundef %[[p:.*]]) +; CHECK: tail call void (i32, ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i32 +; CHECK-SAME: (i32 7, +; CHECK-SAME: ptr elementtype(%struct.foo) %[[p]], +; CHECK-SAME: i1 false, i8 5, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1) +; CHECK-NOT: #{{[0-9]+}} +; CHECK-NEXT: ret void + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) +declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) +declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-2.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-2.ll new file mode 100644 index 000000000000..49f3fa5b8383 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-2.ll @@ -0,0 +1,77 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that bpf-preserve-static-offset folds GEP chains that end by +; getelementptr.and.store. +; +; Source (modified by hand): +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct bar { +; int aa; +; int bb; +; }; +; +; struct foo { +; int a; +; struct bar b; +; } __ctx; +; +; void buz(struct foo *p) { +; p->b.bb = 42; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - +; +; And modified to fold last getelementptr/store as a single +; getelementptr.and.store. + +%struct.foo = type { i32, %struct.bar } +%struct.bar = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 + call void (i32, ptr, i1, i8, i8, i8, i1, ...) + @llvm.bpf.getelementptr.and.store.i32 + (i32 42, + ptr writeonly elementtype(%struct.bar) %b, + i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1) + #3, !tbaa !2 + ret void +} + +; CHECK: define dso_local void @buz(ptr noundef %[[p:.*]]) +; CHECK: call void (i32, ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i32 +; CHECK-SAME: (i32 42, +; CHECK-SAME: ptr writeonly elementtype(%struct.foo) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1, i32 immarg 1) +; CHECK-SAME: #[[v2:.*]], !tbaa +; CHECK: attributes #[[v2]] = { memory(argmem: write) } + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +; Function Attrs: nocallback nofree nounwind willreturn +declare void @llvm.bpf.getelementptr.and.store.i32(i32, ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #2 = { nocallback nofree nounwind willreturn } +attributes #3 = { memory(argmem: write) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 8} +!3 = !{!"foo", !4, i64 0, !7, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} +!7 = !{!"bar", !4, i64 0, !4, i64 4} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-oob.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-oob.ll new file mode 100644 index 000000000000..e2878f091303 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-oob.ll @@ -0,0 +1,67 @@ +; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that bpf-preserve-static-offset keeps track of 'inbounds' flags while +; folding chain of GEP instructions. +; +; Source (IR modified by hand): +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct bar { +; int aa; +; int bb; +; }; +; +; struct foo { +; int a; +; struct bar b; +; } __ctx; +; +; void buz(struct foo *p) { +; p->b.bb = 42; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - +; +; Modified to remove one of the 'inbounds' from one of the GEP instructions. + +%struct.foo = type { i32, %struct.bar } +%struct.bar = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 + %bb = getelementptr %struct.bar, ptr %b, i32 0, i32 1 + store i32 42, ptr %bb, align 4, !tbaa !2 + ret void +} + +; CHECK: define dso_local void @buz(ptr nocapture noundef writeonly %[[p:.*]]) +; CHECK: tail call void (i32, ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i32 +; CHECK-SAME: (i32 42, +; CHECK-SAME: ptr writeonly elementtype(%struct.foo) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 false, i32 immarg 0, i32 immarg 1, i32 immarg 1) +; CHECK-SAME: #[[v2:.*]], !tbaa +; CHECK: attributes #[[v2]] = { memory(argmem: write) } + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 8} +!3 = !{!"foo", !4, i64 0, !7, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} +!7 = !{!"bar", !4, i64 0, !4, i64 4} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-u8-oob.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-u8-oob.ll new file mode 100644 index 000000000000..a33732546677 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-u8-oob.ll @@ -0,0 +1,67 @@ +; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that bpf-preserve-static-offset folds chain of GEP instructions. +; The GEP chain in this example has type mismatch and thus is +; folded as i8 access. +; +; Source (modified by hand): +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; char aa; +; char bb; +; }; +; +; struct bar { +; char a; +; struct foo b; +; } __ctx; +; +; void buz(struct bar *p) { +; ((struct foo *)(((char*)&p->b) + 1))->bb = 42; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - +; +; Modified to remove one of the 'inbounds' from one of the getelementptr. + +%struct.bar = type { i8, %struct.foo } +%struct.foo = type { i8, i8 } + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.bar, ptr %0, i32 0, i32 1 + %add.ptr = getelementptr i8, ptr %b, i64 1 + %bb = getelementptr inbounds %struct.foo, ptr %add.ptr, i32 0, i32 1 + store i8 42, ptr %bb, align 1, !tbaa !2 + ret void +} + +; CHECK: define dso_local void @buz(ptr nocapture noundef writeonly %[[p:.*]]) +; CHECK: tail call void (i8, ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i8 +; CHECK-SAME: (i8 42, +; CHECK-SAME: ptr writeonly elementtype(i8) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 0, i1 false, i64 immarg 3) +; CHECK-SAME: #[[v2:.*]], !tbaa ![[v3:.*]] +; CHECK: attributes #[[v2]] = { memory(argmem: write) } + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 1} +!3 = !{!"foo", !4, i64 0, !4, i64 1} +!4 = !{!"omnipotent char", !5, i64 0} +!5 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-u8.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-u8.ll new file mode 100644 index 000000000000..92740603ae69 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-u8.ll @@ -0,0 +1,68 @@ +; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that bpf-preserve-static-offset folds chain of GEP instructions. +; The GEP chain in this example has type mismatch and thus is +; folded as i8 access. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; char aa; +; char bb; +; }; +; +; struct bar { +; char a; +; struct foo b; +; } __ctx; +; +; void buz(struct bar *p) { +; ((struct foo *)(((char*)&p->b) + 1))->bb = 42; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.bar = type { i8, %struct.foo } +%struct.foo = type { i8, i8 } + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.bar, ptr %0, i32 0, i32 1 + %add.ptr = getelementptr inbounds i8, ptr %b, i64 1 +; ~~ +; these types do not match, thus GEP chain is folded as an offset +; ~~~~~~~~~~~ + %bb = getelementptr inbounds %struct.foo, ptr %add.ptr, i32 0, i32 1 + store i8 42, ptr %bb, align 1, !tbaa !2 + ret void +} + +; CHECK: define dso_local void @buz(ptr nocapture noundef writeonly %[[p:.*]]) +; CHECK: tail call void (i8, ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i8 +; CHECK-SAME: (i8 42, +; CHECK-SAME: ptr writeonly elementtype(i8) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 0, i1 true, i64 immarg 3) +; CHECK-SAME: #[[v2:.*]], !tbaa ![[v3:.*]] +; CHECK: attributes #[[v2]] = { memory(argmem: write) } + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 1} +!3 = !{!"foo", !4, i64 0, !4, i64 1} +!4 = !{!"omnipotent char", !5, i64 0} +!5 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain.ll new file mode 100644 index 000000000000..d4c90616bf5c --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain.ll @@ -0,0 +1,64 @@ +; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that bpf-preserve-static-offset folds chain of GEP instructions. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct bar { +; int aa; +; int bb; +; }; +; +; struct foo { +; int a; +; struct bar b; +; } __ctx; +; +; void buz(struct foo *p) { +; p->b.bb = 42; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.foo = type { i32, %struct.bar } +%struct.bar = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 + %bb = getelementptr inbounds %struct.bar, ptr %b, i32 0, i32 1 + store i32 42, ptr %bb, align 4, !tbaa !2 + ret void +} + +; CHECK: define dso_local void @buz(ptr nocapture noundef writeonly %[[p:.*]]) +; CHECK: tail call void (i32, ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i32 +; CHECK-SAME: (i32 42, +; CHECK-SAME: ptr writeonly elementtype(%struct.foo) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1, i32 immarg 1) +; CHECK-SAME: #[[v2:.*]], !tbaa +; CHECK: attributes #[[v2]] = { memory(argmem: write) } + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 8} +!3 = !{!"foo", !4, i64 0, !7, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} +!7 = !{!"bar", !4, i64 0, !4, i64 4} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-pai.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-pai.ll new file mode 100644 index 000000000000..b22b26836826 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-pai.ll @@ -0,0 +1,136 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; #define __pai __attribute__((preserve_access_index)) +; +; struct foo { +; char a[10]; +; } __pai; +; +; struct bar { +; int a; +; int b; +; } __pai; +; +; struct buz { +; int _1; +; int _2; +; int _3; +; union { +; struct foo a; +; struct bar b[7]; +; }; +; } __pai __ctx; +; +; void quux(struct buz *p) { +; p->b[5].b = 42; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes \ +; -debug-info-kind=limited -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.buz = type { i32, i32, i32, %union.anon } +%union.anon = type { [7 x %struct.bar] } +%struct.bar = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @quux(ptr noundef %p) #0 !dbg !31 { +entry: + call void @llvm.dbg.value(metadata ptr %p, metadata !36, metadata !DIExpression()), !dbg !37 + %0 = call ptr @llvm.preserve.static.offset(ptr %p), !dbg !38 + %1 = call ptr @llvm.preserve.struct.access.index.p0.p0(ptr elementtype(%struct.buz) %0, i32 3, i32 3), !dbg !38, !llvm.preserve.access.index !4 + %2 = call ptr @llvm.preserve.union.access.index.p0.p0(ptr %1, i32 1), !dbg !38, !llvm.preserve.access.index !3 + %3 = call ptr @llvm.preserve.array.access.index.p0.p0(ptr elementtype([7 x %struct.bar]) %2, i32 1, i32 5), !dbg !39, !llvm.preserve.access.index !21 + %4 = call ptr @llvm.preserve.struct.access.index.p0.p0(ptr elementtype(%struct.bar) %3, i32 1, i32 1), !dbg !40, !llvm.preserve.access.index !22 + store i32 42, ptr %4, align 4, !dbg !41, !tbaa !42 + ret void, !dbg !45 +} + +; CHECK: define dso_local void @quux(ptr noundef %[[p:.*]]) {{.*}} { +; CHECK-NEXT: entry: +; CHECK-NEXT: call void @llvm.dbg.value +; CHECK-NEXT: call void (i32, ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i32 +; CHECK-SAME: (i32 42, +; CHECK-SAME: ptr writeonly elementtype(i8) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i64 immarg 56) +; CHECK-SAME: #[[v5:.*]], !tbaa +; CHECK-NEXT: ret void, !dbg +; CHECK-NEXT: } +; CHECK: attributes #[[v5]] = { memory(argmem: write) } + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) +declare ptr @llvm.preserve.struct.access.index.p0.p0(ptr, i32 immarg, i32 immarg) #2 + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) +declare ptr @llvm.preserve.union.access.index.p0.p0(ptr, i32 immarg) #2 + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) +declare ptr @llvm.preserve.array.access.index.p0.p0(ptr, i32 immarg, i32 immarg) #2 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare void @llvm.dbg.value(metadata, metadata, metadata) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!28, !29} +!llvm.ident = !{!30} + +!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, retainedTypes: !2, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "some-file.c", directory: "/some/dir/") +!2 = !{!3, !21} +!3 = distinct !DICompositeType(tag: DW_TAG_union_type, scope: !4, file: !1, line: 17, size: 448, elements: !11) +!4 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "buz", file: !1, line: 13, size: 544, elements: !5) +!5 = !{!6, !8, !9, !10} +!6 = !DIDerivedType(tag: DW_TAG_member, name: "_1", scope: !4, file: !1, line: 14, baseType: !7, size: 32) +!7 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!8 = !DIDerivedType(tag: DW_TAG_member, name: "_2", scope: !4, file: !1, line: 15, baseType: !7, size: 32, offset: 32) +!9 = !DIDerivedType(tag: DW_TAG_member, name: "_3", scope: !4, file: !1, line: 16, baseType: !7, size: 32, offset: 64) +!10 = !DIDerivedType(tag: DW_TAG_member, scope: !4, file: !1, line: 17, baseType: !3, size: 448, offset: 96) +!11 = !{!12, !20} +!12 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !3, file: !1, line: 18, baseType: !13, size: 80) +!13 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "foo", file: !1, line: 4, size: 80, elements: !14) +!14 = !{!15} +!15 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !13, file: !1, line: 5, baseType: !16, size: 80) +!16 = !DICompositeType(tag: DW_TAG_array_type, baseType: !17, size: 80, elements: !18) +!17 = !DIBasicType(name: "char", size: 8, encoding: DW_ATE_signed_char) +!18 = !{!19} +!19 = !DISubrange(count: 10) +!20 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !3, file: !1, line: 19, baseType: !21, size: 448) +!21 = !DICompositeType(tag: DW_TAG_array_type, baseType: !22, size: 448, elements: !26) +!22 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "bar", file: !1, line: 8, size: 64, elements: !23) +!23 = !{!24, !25} +!24 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !22, file: !1, line: 9, baseType: !7, size: 32) +!25 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !22, file: !1, line: 10, baseType: !7, size: 32, offset: 32) +!26 = !{!27} +!27 = !DISubrange(count: 7) +!28 = !{i32 2, !"Debug Info Version", i32 3} +!29 = !{i32 1, !"wchar_size", i32 4} +!30 = !{!"clang"} +!31 = distinct !DISubprogram(name: "quux", scope: !1, file: !1, line: 23, type: !32, scopeLine: 23, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !35) +!32 = !DISubroutineType(types: !33) +!33 = !{null, !34} +!34 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !4, size: 64) +!35 = !{!36} +!36 = !DILocalVariable(name: "p", arg: 1, scope: !31, file: !1, line: 23, type: !34) +!37 = !DILocation(line: 0, scope: !31) +!38 = !DILocation(line: 24, column: 6, scope: !31) +!39 = !DILocation(line: 24, column: 3, scope: !31) +!40 = !DILocation(line: 24, column: 11, scope: !31) +!41 = !DILocation(line: 24, column: 13, scope: !31) +!42 = !{!43, !43, i64 0} +!43 = !{!"omnipotent char", !44, i64 0} +!44 = !{!"Simple C/C++ TBAA"} +!45 = !DILocation(line: 25, column: 1, scope: !31) diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-simple.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-simple.ll new file mode 100644 index 000000000000..a603ad866739 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-simple.ll @@ -0,0 +1,60 @@ +; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check handling of a simple store instruction by bpf-preserve-static-offset. +; Verify: +; - presence of gep.and.store intrinsic call +; - correct attributes for intrinsic call +; - presence of tbaa annotations +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int _; +; int a; +; } __ctx; +; +; void bar(struct foo *p) { +; p->a = 7; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.foo = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %a = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 + store i32 7, ptr %a, align 4, !tbaa !2 + ret void +} + +; CHECK: define dso_local void @bar(ptr nocapture noundef writeonly %[[p:.*]]) +; CHECK: tail call void (i32, ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i32 +; CHECK-SAME: (i32 7, +; CHECK-SAME: ptr writeonly elementtype(%struct.foo) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1) +; CHECK-SAME: #[[v2:.*]], !tbaa +; CHECK: attributes #[[v2]] = { memory(argmem: write) } + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 4} +!3 = !{!"foo", !4, i64 0, !4, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-align.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-align.ll new file mode 100644 index 000000000000..7996fe0d1bb2 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-align.ll @@ -0,0 +1,62 @@ +; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that getelementptr.and.store unroll restores alignment spec. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; typedef int aligned_int __attribute__((aligned(128))); +; +; struct foo { +; int _; +; aligned_int a; +; } __ctx; +; +; void bar(struct foo *p) { +; p->a = 42; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=sroa,bpf-preserve-static-offset -S -o - + +%struct.foo = type { i32, [124 x i8], i32, [124 x i8] } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + call void (i32, ptr, i1, i8, i8, i8, i1, ...) + @llvm.bpf.getelementptr.and.store.i32 + (i32 42, + ptr writeonly elementtype(%struct.foo) %p, + i1 false, i8 0, i8 1, i8 7, i1 true, i32 immarg 0, i32 immarg 2) + #3, !tbaa !2 + ret void +} + +; CHECK: define dso_local void @bar(ptr noundef %[[p:.*]]) +; CHECK: %[[v2:.*]] = getelementptr inbounds %struct.foo, ptr %[[p]], i32 0, i32 2 +; CHECK: store i32 42, ptr %[[v2]], align 128 +; CHECK: ret void + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +; Function Attrs: nocallback nofree nounwind willreturn +declare void @llvm.bpf.getelementptr.and.store.i32(i32, ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #2 = { nocallback nofree nounwind willreturn } +attributes #3 = { memory(argmem: write) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 128} +!3 = !{!"foo", !4, i64 0, !4, i64 128} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain-oob.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain-oob.ll new file mode 100644 index 000000000000..d2731d32ed4c --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain-oob.ll @@ -0,0 +1,67 @@ +; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that getelementptr.and.load unroll can skip 'inbounds' flag. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct bar { +; int aa; +; int bb; +; }; +; +; struct foo { +; int a; +; struct bar b; +; } __ctx; +; +; void buz(struct foo *p) { +; p->b.bb = 42; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=sroa,bpf-preserve-static-offset -S -o - + +%struct.foo = type { i32, %struct.bar } +%struct.bar = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + call void (i32, ptr, i1, i8, i8, i8, i1, ...) + @llvm.bpf.getelementptr.and.store.i32 + (i32 42, + ptr writeonly elementtype(%struct.foo) %p, + i1 false, i8 0, i8 1, i8 2, i1 false, i32 immarg 0, i32 immarg 1, i32 immarg 1) + #3, !tbaa !2 + ret void +} + +; CHECK: define dso_local void @buz(ptr noundef %[[p:.*]]) +; CHECK: %[[v2:.*]] = getelementptr %struct.foo, ptr %[[p]], i32 0, i32 1, i32 1 +; CHECK: store i32 42, ptr %[[v2]], align 4 +; CHECK: ret void + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +; Function Attrs: nocallback nofree nounwind willreturn +declare void @llvm.bpf.getelementptr.and.store.i32(i32, ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #2 = { nocallback nofree nounwind willreturn } +attributes #3 = { memory(argmem: write) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 8} +!3 = !{!"foo", !4, i64 0, !7, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} +!7 = !{!"bar", !4, i64 0, !4, i64 4} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain-u8.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain-u8.ll new file mode 100644 index 000000000000..184c5c334905 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain-u8.ll @@ -0,0 +1,62 @@ +; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check unroll of getelementptr.and.store when direct memory offset is +; used instead of field indexes. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; char aa; +; char bb; +; }; +; +; struct bar { +; char a; +; struct foo b; +; } __ctx; +; +; void buz(struct bar *p) { +; ((struct foo *)(((char*)&p->b) + 1))->bb = 42; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=sroa,bpf-preserve-static-offset -S -o - + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + call void (i8, ptr, i1, i8, i8, i8, i1, ...) + @llvm.bpf.getelementptr.and.store.i8 + (i8 42, + ptr writeonly elementtype(i8) %p, + i1 false, i8 0, i8 1, i8 0, i1 true, i64 immarg 3) + #3, !tbaa !2 + ret void +} + +; CHECK: define dso_local void @buz(ptr noundef %[[p:.*]]) +; CHECK: %[[v2:.*]] = getelementptr inbounds i8, ptr %[[p]], i64 3 +; CHECK: store i8 42, ptr %[[v2]], align 1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +; Function Attrs: nocallback nofree nounwind willreturn +declare void @llvm.bpf.getelementptr.and.store.i8(i8, ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #2 = { nocallback nofree nounwind willreturn } +attributes #3 = { memory(argmem: write) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 1} +!3 = !{!"foo", !4, i64 0, !4, i64 1} +!4 = !{!"omnipotent char", !5, i64 0} +!5 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain.ll new file mode 100644 index 000000000000..2899ab03f50d --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain.ll @@ -0,0 +1,68 @@ +; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check unroll of getelementptr.and.store when several field indexes +; are specified in a chain. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct bar { +; int aa; +; int bb; +; }; +; +; struct foo { +; int a; +; struct bar b; +; } __ctx; +; +; void buz(struct foo *p) { +; p->b.bb = 42; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=sroa,bpf-preserve-static-offset -S -o - + +%struct.foo = type { i32, %struct.bar } +%struct.bar = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + call void (i32, ptr, i1, i8, i8, i8, i1, ...) + @llvm.bpf.getelementptr.and.store.i32 + (i32 42, + ptr writeonly elementtype(%struct.foo) %p, + i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1, i32 immarg 1) + #3, !tbaa !2 + ret void +} + +; CHECK: define dso_local void @buz(ptr noundef %[[p:.*]]) +; CHECK: %[[v2:.*]] = getelementptr inbounds %struct.foo, ptr %[[p]], i32 0, i32 1, i32 1 +; CHECK: store i32 42, ptr %[[v2]], align 4 +; CHECK: ret void + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +; Function Attrs: nocallback nofree nounwind willreturn +declare void @llvm.bpf.getelementptr.and.store.i32(i32, ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #2 = { nocallback nofree nounwind willreturn } +attributes #3 = { memory(argmem: write) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 8} +!3 = !{!"foo", !4, i64 0, !7, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} +!7 = !{!"bar", !4, i64 0, !4, i64 4} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-simple.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-simple.ll new file mode 100644 index 000000000000..8ad5eae98475 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-simple.ll @@ -0,0 +1,61 @@ +; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check unroll of getelementptr.and.store. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int a; +; int b; +; } __ctx; +; +; extern void consume(int); +; +; void bar(struct foo *p){ +; p->b = 42; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=sroa,bpf-preserve-static-offset -S -o - + +%struct.foo = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + call void (i32, ptr, i1, i8, i8, i8, i1, ...) + @llvm.bpf.getelementptr.and.store.i32 + (i32 42, + ptr writeonly elementtype(%struct.foo) %p, + i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1) + #3, !tbaa !2 + ret void +} + +; CHECK: define dso_local void @bar(ptr noundef %[[p:.*]]) +; CHECK: %[[v2:.*]] = getelementptr inbounds %struct.foo, ptr %[[p]], i32 0, i32 1 +; CHECK: store i32 42, ptr %[[v2]], align 4 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +; Function Attrs: nocallback nofree nounwind willreturn +declare void @llvm.bpf.getelementptr.and.store.i32(i32, ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #2 = { nocallback nofree nounwind willreturn } +attributes #3 = { memory(argmem: write) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 4} +!3 = !{!"foo", !4, i64 0, !4, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-volatile.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-volatile.ll new file mode 100644 index 000000000000..79495732f972 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-volatile.ll @@ -0,0 +1,61 @@ +; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that unroll of getelementptr.and.store restores volatile. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int a; +; volatile int b; +; } __ctx; +; +; extern void consume(int); +; +; void bar(struct foo *p){ +; p->b = 42; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=sroa,bpf-preserve-static-offset -S -o - + +%struct.foo = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + call void (i32, ptr, i1, i8, i8, i8, i1, ...) + @llvm.bpf.getelementptr.and.store.i32 + (i32 42, + ptr elementtype(%struct.foo) %p, + i1 true, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1), + !tbaa !2 + ret void +} + +; CHECK: define dso_local void @bar(ptr noundef %[[p:.*]]) +; CHECK: entry: +; CHECK: %[[v2:.*]] = getelementptr inbounds %struct.foo, ptr %[[p]], i32 0, i32 1 +; CHECK: store volatile i32 42, ptr %[[v2]], align 4 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +; Function Attrs: nocallback nofree nounwind willreturn +declare void @llvm.bpf.getelementptr.and.store.i32(i32, ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #2 = { nocallback nofree nounwind willreturn } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 4} +!3 = !{!"foo", !4, i64 0, !4, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-unroll-inline.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-unroll-inline.ll new file mode 100644 index 000000000000..161aded79eac --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-unroll-inline.ll @@ -0,0 +1,104 @@ +; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check position of bpf-preserve-static-offset pass in the pipeline: +; - preserve.static.offset call is preserved if address is passed as +; a parameter to an inline-able function; +; - second bpf-preserve-static-offset pass (after inlining) should introduce +; getelementptr.and.store call using the preserved marker after loops +; unrolling; +; - memory(argmem: readwrite) and tbaa attributes should allow +; removing one getelementptr.and.store call. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int a; +; int b[4]; +; } __ctx; +; +; static inline void bar(int * restrict p, unsigned long i) { +; p[0] = i; +; } +; +; void quux(struct foo *p){ +; unsigned long i = 0; +; #pragma clang loop unroll(full) +; while (i < 2) { +; bar(p->b, i); +; ++i; +; } +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.foo = type { i32, [4 x i32] } + +; Function Attrs: nounwind +define dso_local void @quux(ptr noundef %p) #0 { +entry: + br label %while.cond + +while.cond: ; preds = %while.body, %entry + %i.0 = phi i64 [ 0, %entry ], [ %inc, %while.body ] + %cmp = icmp ult i64 %i.0, 2 + br i1 %cmp, label %while.body, label %while.end + +while.body: ; preds = %while.cond + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 + %arraydecay = getelementptr inbounds [4 x i32], ptr %b, i64 0, i64 0 + call void @bar(ptr noundef %arraydecay, i64 noundef %i.0) + %inc = add i64 %i.0, 1 + br label %while.cond, !llvm.loop !2 + +while.end: ; preds = %while.cond + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) +declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1 + +; Function Attrs: inlinehint nounwind +define internal void @bar(ptr noalias noundef %p, i64 noundef %i) #2 { +entry: + %conv = trunc i64 %i to i32 + %arrayidx = getelementptr inbounds i32, ptr %p, i64 0 + store i32 %conv, ptr %arrayidx, align 4, !tbaa !5 + ret void +} + +; CHECK: define dso_local void @quux(ptr nocapture noundef writeonly %[[p:.*]]) +; CHECK-NEXT: entry: +; CHECK-NEXT: tail call void (i32, ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i32 +; CHECK-SAME: (i32 1, +; CHECK-SAME: ptr writeonly elementtype(%struct.foo) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i64 immarg 0, i32 immarg 1) +; CHECK-NEXT: ret void + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #3 + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) +declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } +attributes #2 = { inlinehint nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = distinct !{!2, !3, !4} +!3 = !{!"llvm.loop.mustprogress"} +!4 = !{!"llvm.loop.unroll.full"} +!5 = !{!6, !6, i64 0} +!6 = !{!"int", !7, i64 0} +!7 = !{!"omnipotent char", !8, i64 0} +!8 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-volatile.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-volatile.ll new file mode 100644 index 000000000000..8b0493a38efa --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-volatile.ll @@ -0,0 +1,56 @@ +; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check handling of a volatile store instruction by bpf-preserve-static-offset. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int a; +; volatile int b; +; } __ctx; +; +; void bar(struct foo *p) { +; p->b = 42; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.foo = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 + store volatile i32 42, ptr %b, align 4, !tbaa !2 + ret void +} + +; CHECK: define dso_local void @bar(ptr nocapture noundef %[[p:.*]]) +; CHECK: tail call void (i32, ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i32 +; CHECK-SAME: (i32 42, +; CHECK-SAME: ptr elementtype(%struct.foo) %[[p]], +; CHECK-SAME: i1 true, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1), +; CHECK-NOT: #{{[0-9]+}} +; CHECK-SAME: !tbaa + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 4} +!3 = !{!"foo", !4, i64 0, !4, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-zero.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-zero.ll new file mode 100644 index 000000000000..7f2a06af8d10 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-zero.ll @@ -0,0 +1,51 @@ +; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that stores from zero offset are not modified by bpf-preserve-static-offset. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int a; +; } __ctx; +; +; void bar(struct foo *p) { +; p->a = 0; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.foo = type { i32 } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %a = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 0 + store i32 0, ptr %a, align 4, !tbaa !2 + ret void +} + +; CHECK: define dso_local void @bar(ptr nocapture noundef writeonly %[[p:.*]]) +; CHECK-NEXT: entry: +; CHECK-NEXT: store i32 0, ptr %[[p]], align 4, !tbaa +; CHECK-NEXT: ret void + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 0} +!3 = !{!"foo", !4, i64 0} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} -- GitLab From d1bf1947e4e4f3ef75f2ba3ac9aa77dc38214de1 Mon Sep 17 00:00:00 2001 From: jimingham Date: Thu, 30 Nov 2023 09:48:04 -0800 Subject: [PATCH 007/699] Send an explicit interrupt to cancel an attach waitfor. (#72565) Currently when you interrupt a: (lldb) process attach -w -n some_process lldb just closes the connection to the stub and kills the lldb_private::Process it made for the attach. The stub at the other end notices the connection go down and exits because of that. But when communication to a device is handled through some kind of proxy server which isn't as well behaved as one would wish, that signal might not be reliable, causing debugserver to persist on the machine, waiting to steal the next instance of that process. We can work around those failures by sending an explicit interrupt before closing down the connection. The stub will also have to be waiting for the interrupt for this to make any difference. I changed debugserver to do that. I didn't make the equivalent change in lldb-server. So long as you aren't faced with a flakey connection, this should not be necessary. --- .../Process/gdb-remote/ProcessGDBRemote.cpp | 6 +- lldb/source/Target/Process.cpp | 9 ++- .../process/cancel_attach/TestCancelAttach.py | 57 +++++++++++++++++++ lldb/tools/debugserver/source/DNB.cpp | 30 +++++++++- 4 files changed, 97 insertions(+), 5 deletions(-) create mode 100644 lldb/test/API/python_api/process/cancel_attach/TestCancelAttach.py diff --git a/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp b/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp index e653ef5d8ac5..9648f1fd52cf 100644 --- a/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp +++ b/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp @@ -2371,8 +2371,10 @@ Status ProcessGDBRemote::DoHalt(bool &caused_stop) { Status error; if (m_public_state.GetValue() == eStateAttaching) { - // We are being asked to halt during an attach. We need to just close our - // file handle and debugserver will go away, and we can be done... + // We are being asked to halt during an attach. We used to just close our + // file handle and debugserver will go away, but with remote proxies, it + // is better to send a positive signal, so let's send the interrupt first... + caused_stop = m_gdb_comm.Interrupt(GetInterruptTimeout()); m_gdb_comm.Disconnect(); } else caused_stop = m_gdb_comm.Interrupt(GetInterruptTimeout()); diff --git a/lldb/source/Target/Process.cpp b/lldb/source/Target/Process.cpp index 21b80b8240ab..f3da2839e262 100644 --- a/lldb/source/Target/Process.cpp +++ b/lldb/source/Target/Process.cpp @@ -3156,8 +3156,8 @@ Status Process::Halt(bool clear_thread_plans, bool use_run_lock) { // Don't hijack and eat the eStateExited as the code that was doing the // attach will be waiting for this event... RestoreProcessEvents(); - SetExitStatus(SIGKILL, "Cancelled async attach."); Destroy(false); + SetExitStatus(SIGKILL, "Cancelled async attach."); return Status(); } @@ -3843,6 +3843,13 @@ thread_result_t Process::RunPrivateStateThread(bool is_secondary_thread) { ") woke up with an interrupt while attaching - " "forwarding interrupt.", __FUNCTION__, static_cast(this), GetID()); + // The server may be spinning waiting for a process to appear, in which + // case we should tell it to stop doing that. Normally, we don't NEED + // to do that because we will next close the communication to the stub + // and that will get it to shut down. But there are remote debugging + // cases where relying on that side-effect causes the shutdown to be + // flakey, so we should send a positive signal to interrupt the wait. + Status error = HaltPrivate(); BroadcastEvent(eBroadcastBitInterrupt, nullptr); } else if (StateIsRunningState(m_last_broadcast_state)) { LLDB_LOGF(log, diff --git a/lldb/test/API/python_api/process/cancel_attach/TestCancelAttach.py b/lldb/test/API/python_api/process/cancel_attach/TestCancelAttach.py new file mode 100644 index 000000000000..9172c3d333fd --- /dev/null +++ b/lldb/test/API/python_api/process/cancel_attach/TestCancelAttach.py @@ -0,0 +1,57 @@ +""" +Test using SendAsyncInterrupt to interrupt an "attach wait" +""" + +import lldb +import sys +import time +import threading +from lldbsuite.test.decorators import * +from lldbsuite.test.lldbtest import * +import lldbsuite.test.lldbutil + + +class AttachCancelTestCase(TestBase): + NO_DEBUG_INFO_TESTCASE = True + + def test_scripted_implementation(self): + """Test that cancelling a stuck "attach waitfor" works.""" + # First make an empty target for the attach: + target = self.dbg.CreateTarget(None) + + # We need to cancel this, so we need to do the attach + # on a separate thread: + class AttachThread(threading.Thread): + def __init__(self, target, error): + # Make this a daemon thread so if we don't manage to interrupt, + # Python will keep this thread from hanging the test. + threading.Thread.__init__(self, daemon=True) + self.target = target + self.error = error + + def run(self): + self.target.AttachToProcessWithName(lldb.SBListener(), "LLDB-No-Such-Process", True, self.error) + + error = lldb.SBError() + thread = AttachThread(target, error) + thread.start() + + # Now wait till the attach on the child thread has made a process + # for the attach attempt: + while not target.process.IsValid(): + time.sleep(1) + # I don't have a positive signal for "we started the attach attempt" + # so the best I can do is sleep a bit more here to give that a chance + # to start: + time.sleep(1) + + # Now send the attach interrupt: + target.process.SendAsyncInterrupt() + # We don't want to stall if we can't interrupt, so join with a timeout: + thread.join(60) + if thread.is_alive(): + self.fail("The attach thread is alive after timeout interval") + + # Now check the error, should say the attach was interrupted: + self.assertTrue(error.Fail(), "We succeeded in not attaching") + diff --git a/lldb/tools/debugserver/source/DNB.cpp b/lldb/tools/debugserver/source/DNB.cpp index f6c1130fdd80..0ec50df42d1f 100644 --- a/lldb/tools/debugserver/source/DNB.cpp +++ b/lldb/tools/debugserver/source/DNB.cpp @@ -50,6 +50,7 @@ #include "MacOSX/MachProcess.h" #include "MacOSX/MachTask.h" #include "MacOSX/ThreadInfo.h" +#include "RNBRemote.h" typedef std::shared_ptr MachProcessSP; typedef std::map ProcessMap; @@ -745,7 +746,6 @@ DNBProcessAttachWait(RNBContext *ctx, const char *waitfor_process_name, break; } } else { - // Get the current process list, and check for matches that // aren't in our original list. If anyone wants to attach // to an existing process by name, they should do it with @@ -799,7 +799,33 @@ DNBProcessAttachWait(RNBContext *ctx, const char *waitfor_process_name, break; } - ::usleep(waitfor_interval); // Sleep for WAITFOR_INTERVAL, then poll again + // Now we're going to wait a while before polling again. But we also + // need to check whether we've gotten an event from the debugger + // telling us to interrupt the wait. So we'll use the wait for a possible + // next event to also be our short pause... + struct timespec short_timeout; + DNBTimer::OffsetTimeOfDay(&short_timeout, 0, waitfor_interval); + uint32_t event_mask = RNBContext::event_read_packet_available + | RNBContext::event_read_thread_exiting; + nub_event_t set_events = ctx->Events().WaitForSetEvents(event_mask, + &short_timeout); + if (set_events & RNBContext::event_read_packet_available) { + // If we get any packet from the debugger while waiting on the async, + // it has to be telling us to interrupt. So always exit here. + // Over here in DNB land we can see that there was a packet, but all + // the methods to actually handle it are protected. It's not worth + // rearranging all that just to get which packet we were sent... + DNBLogError("Interrupted by packet while waiting for '%s' to appear.\n", + waitfor_process_name); + break; + } + if (set_events & RNBContext::event_read_thread_exiting) { + // The packet thread is shutting down, get out of here... + DNBLogError("Interrupted by packet thread shutdown while waiting for " + "%s to appear.\n", waitfor_process_name); + break; + } + } } -- GitLab From 2eff36b7d33fb9ea5c15ea8561fe6b30105d48f5 Mon Sep 17 00:00:00 2001 From: Shubham Sandeep Rastogi Date: Thu, 30 Nov 2023 09:53:15 -0800 Subject: [PATCH 008/699] Revert "[CodeGen] Port SafeStack to new pass manager (#73747)" (#73965) This reverts commit a4d5fd4d2ee9470e55345a9540f6b6fb6faf66e1. The above commit breaks greendragon lldb bots: Link to failing builds: https://green.lab.llvm.org/green/view/LLDB/job/lldb-cmake/63300/ https://green.lab.llvm.org/green/view/LLDB/job/as-lldb-cmake/10345/ I found this PR to be the offending one after using git bisect with the cmake invocation: cmake -G Ninja ../llvm -DCMAKE_BUILD_TYPE=Release -DCMAKE_EXPORT_COMPILE_COMMANDS=ON '-DLLVM_TARGETS_TO_BUILD=X86;ARM;AArch64' -DLLVM_ENABLE_ASSERTIONS:BOOL=TRUE -DLLVM_ENABLE_MODULES=On -DLLVM_ENABLE_PROJECTS='clang;lld;lldb;cross-project-tests' -DLLVM_VERSION_PATCH=99 '-DLLVM_ENABLE_RUNTIMES=libcxx;libcxxabi;compiler-rt' and running ninja lib/CodeGen/CMakeFiles/LLVMCodeGen.dir/CodeGenPassBuilder.cpp.o --- llvm/include/llvm/CodeGen/SafeStack.h | 28 -------------- llvm/lib/CodeGen/SafeStack.cpp | 37 ------------------- llvm/lib/Passes/PassBuilder.cpp | 1 - llvm/lib/Passes/PassRegistry.def | 1 - llvm/test/Transforms/SafeStack/AArch64/abi.ll | 1 - .../Transforms/SafeStack/AArch64/abi_ssp.ll | 2 - .../SafeStack/AArch64/unreachable.ll | 1 - llvm/test/Transforms/SafeStack/ARM/abi.ll | 1 - llvm/test/Transforms/SafeStack/ARM/debug.ll | 1 - llvm/test/Transforms/SafeStack/ARM/setjmp.ll | 1 - llvm/test/Transforms/SafeStack/X86/abi.ll | 4 -- llvm/test/Transforms/SafeStack/X86/abi_ssp.ll | 11 ------ .../Transforms/SafeStack/X86/addr-taken.ll | 2 - .../Transforms/SafeStack/X86/array-aligned.ll | 2 - llvm/test/Transforms/SafeStack/X86/array.ll | 2 - llvm/test/Transforms/SafeStack/X86/byval.ll | 2 - llvm/test/Transforms/SafeStack/X86/call.ll | 2 - llvm/test/Transforms/SafeStack/X86/cast.ll | 2 - .../Transforms/SafeStack/X86/coloring-ssp.ll | 1 - .../test/Transforms/SafeStack/X86/coloring.ll | 2 - .../Transforms/SafeStack/X86/coloring2.ll | 2 - .../SafeStack/X86/constant-gep-call.ll | 2 - .../Transforms/SafeStack/X86/constant-gep.ll | 2 - .../Transforms/SafeStack/X86/constant-geps.ll | 2 - .../SafeStack/X86/debug-loc-dynamic.ll | 2 - .../Transforms/SafeStack/X86/debug-loc.ll | 2 - .../Transforms/SafeStack/X86/debug-loc2.ll | 2 - .../SafeStack/X86/dynamic-alloca.ll | 2 - .../SafeStack/X86/escape-addr-pointer.ll | 2 - .../SafeStack/X86/escape-bitcast-store.ll | 2 - .../SafeStack/X86/escape-bitcast-store2.ll | 2 - .../Transforms/SafeStack/X86/escape-call.ll | 2 - .../SafeStack/X86/escape-casted-pointer.ll | 2 - .../SafeStack/X86/escape-gep-call.ll | 2 - .../SafeStack/X86/escape-gep-invoke.ll | 2 - .../SafeStack/X86/escape-gep-negative.ll | 2 - .../SafeStack/X86/escape-gep-ptrtoint.ll | 2 - .../SafeStack/X86/escape-gep-store.ll | 2 - .../SafeStack/X86/escape-phi-call.ll | 2 - .../SafeStack/X86/escape-select-call.ll | 2 - .../Transforms/SafeStack/X86/escape-vector.ll | 2 - llvm/test/Transforms/SafeStack/X86/invoke.ll | 2 - .../Transforms/SafeStack/X86/layout-frag.ll | 1 - .../SafeStack/X86/layout-region-split.ll | 1 - .../SafeStack/X86/memintrinsic-oob-read.ll | 2 - .../test/Transforms/SafeStack/X86/musttail.ll | 1 - llvm/test/Transforms/SafeStack/X86/no-attr.ll | 2 - .../SafeStack/X86/no-crash-on-lifetime.ll | 1 - .../Transforms/SafeStack/X86/phi-cycle.ll | 2 - llvm/test/Transforms/SafeStack/X86/phi.ll | 2 - llvm/test/Transforms/SafeStack/X86/pr54784.ll | 1 - llvm/test/Transforms/SafeStack/X86/ret.ll | 2 - llvm/test/Transforms/SafeStack/X86/setjmp.ll | 2 - llvm/test/Transforms/SafeStack/X86/setjmp2.ll | 2 - .../Transforms/SafeStack/X86/sink-to-use.ll | 2 - llvm/test/Transforms/SafeStack/X86/ssp.ll | 1 - llvm/test/Transforms/SafeStack/X86/store.ll | 2 - llvm/test/Transforms/SafeStack/X86/struct.ll | 2 - 58 files changed, 174 deletions(-) delete mode 100644 llvm/include/llvm/CodeGen/SafeStack.h diff --git a/llvm/include/llvm/CodeGen/SafeStack.h b/llvm/include/llvm/CodeGen/SafeStack.h deleted file mode 100644 index e8f0d141457b..000000000000 --- a/llvm/include/llvm/CodeGen/SafeStack.h +++ /dev/null @@ -1,28 +0,0 @@ -//===--------------------- llvm/CodeGen/SafeStack.h -------------*- C++-*--===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_CODEGEN_SAFESTACK_H -#define LLVM_CODEGEN_SAFESTACK_H - -#include "llvm/IR/PassManager.h" - -namespace llvm { - -class TargetMachine; - -class SafeStackPass : public PassInfoMixin { - const TargetMachine *TM; - -public: - explicit SafeStackPass(const TargetMachine *TM_) : TM(TM_) {} - PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM); -}; - -} // namespace llvm - -#endif // LLVM_CODEGEN_SAFESTACK_H diff --git a/llvm/lib/CodeGen/SafeStack.cpp b/llvm/lib/CodeGen/SafeStack.cpp index 88db57ad46b9..ef293faa1d06 100644 --- a/llvm/lib/CodeGen/SafeStack.cpp +++ b/llvm/lib/CodeGen/SafeStack.cpp @@ -14,7 +14,6 @@ // //===----------------------------------------------------------------------===// -#include "llvm/CodeGen/SafeStack.h" #include "SafeStackLayout.h" #include "llvm/ADT/APInt.h" #include "llvm/ADT/ArrayRef.h" @@ -928,42 +927,6 @@ public: } // end anonymous namespace -PreservedAnalyses SafeStackPass::run(Function &F, - FunctionAnalysisManager &FAM) { - LLVM_DEBUG(dbgs() << "[SafeStack] Function: " << F.getName() << "\n"); - - if (!F.hasFnAttribute(Attribute::SafeStack)) { - LLVM_DEBUG(dbgs() << "[SafeStack] safestack is not requested" - " for this function\n"); - return PreservedAnalyses::all(); - } - - if (F.isDeclaration()) { - LLVM_DEBUG(dbgs() << "[SafeStack] function definition" - " is not available\n"); - return PreservedAnalyses::all(); - } - - auto *TL = TM->getSubtargetImpl(F)->getTargetLowering(); - if (!TL) - report_fatal_error("TargetLowering instance is required"); - - auto &DL = F.getParent()->getDataLayout(); - - // preserve DominatorTree - auto &DT = FAM.getResult(F); - auto &SE = FAM.getResult(F); - DomTreeUpdater DTU(DT, DomTreeUpdater::UpdateStrategy::Lazy); - - bool Changed = SafeStack(F, *TL, DL, &DTU, SE).run(); - - if (!Changed) - return PreservedAnalyses::all(); - PreservedAnalyses PA; - PA.preserve(); - return PA; -} - char SafeStackLegacyPass::ID = 0; INITIALIZE_PASS_BEGIN(SafeStackLegacyPass, DEBUG_TYPE, diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp index 76326fecb807..aeb9726a186b 100644 --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -77,7 +77,6 @@ #include "llvm/CodeGen/ExpandLargeDivRem.h" #include "llvm/CodeGen/ExpandLargeFpConvert.h" #include "llvm/CodeGen/HardwareLoops.h" -#include "llvm/CodeGen/SafeStack.h" #include "llvm/CodeGen/TypePromotion.h" #include "llvm/IR/DebugInfo.h" #include "llvm/IR/Dominators.h" diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def index b4c69ad63c4e..1f1bc3222468 100644 --- a/llvm/lib/Passes/PassRegistry.def +++ b/llvm/lib/Passes/PassRegistry.def @@ -393,7 +393,6 @@ FUNCTION_PASS("print", UniformityInfoPrinterPass(dbgs())) FUNCTION_PASS("reassociate", ReassociatePass()) FUNCTION_PASS("redundant-dbg-inst-elim", RedundantDbgInstEliminationPass()) FUNCTION_PASS("reg2mem", RegToMemPass()) -FUNCTION_PASS("safe-stack", SafeStackPass(TM)) FUNCTION_PASS("scalarize-masked-mem-intrin", ScalarizeMaskedMemIntrinPass()) FUNCTION_PASS("scalarizer", ScalarizerPass()) FUNCTION_PASS("sccp", SCCPPass()) diff --git a/llvm/test/Transforms/SafeStack/AArch64/abi.ll b/llvm/test/Transforms/SafeStack/AArch64/abi.ll index 6d4ca0309682..18cf49920ace 100644 --- a/llvm/test/Transforms/SafeStack/AArch64/abi.ll +++ b/llvm/test/Transforms/SafeStack/AArch64/abi.ll @@ -1,5 +1,4 @@ ; RUN: opt -safe-stack -S -mtriple=aarch64-linux-android < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=aarch64-linux-android < %s -o - | FileCheck %s define void @foo() nounwind uwtable safestack { diff --git a/llvm/test/Transforms/SafeStack/AArch64/abi_ssp.ll b/llvm/test/Transforms/SafeStack/AArch64/abi_ssp.ll index 282d8c4390b6..aab2d5dd4a78 100644 --- a/llvm/test/Transforms/SafeStack/AArch64/abi_ssp.ll +++ b/llvm/test/Transforms/SafeStack/AArch64/abi_ssp.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=aarch64-linux-android < %s -o - | FileCheck --check-prefixes=TLS,ANDROID %s ; RUN: opt -safe-stack -S -mtriple=aarch64-unknown-fuchsia < %s -o - | FileCheck --check-prefixes=TLS,FUCHSIA %s -; RUN: opt -passes=safe-stack -S -mtriple=aarch64-linux-android < %s -o - | FileCheck --check-prefixes=TLS,ANDROID %s -; RUN: opt -passes=safe-stack -S -mtriple=aarch64-unknown-fuchsia < %s -o - | FileCheck --check-prefixes=TLS,FUCHSIA %s define void @foo() nounwind uwtable safestack sspreq { entry: diff --git a/llvm/test/Transforms/SafeStack/AArch64/unreachable.ll b/llvm/test/Transforms/SafeStack/AArch64/unreachable.ll index 23fd3bf9d8f2..430c4aa7ae45 100644 --- a/llvm/test/Transforms/SafeStack/AArch64/unreachable.ll +++ b/llvm/test/Transforms/SafeStack/AArch64/unreachable.ll @@ -1,5 +1,4 @@ ; RUN: opt -safe-stack -safe-stack-coloring -S -mtriple=aarch64-linux-android < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -safe-stack-coloring -S -mtriple=aarch64-linux-android < %s -o - | FileCheck %s define void @foo() nounwind uwtable safestack { entry: diff --git a/llvm/test/Transforms/SafeStack/ARM/abi.ll b/llvm/test/Transforms/SafeStack/ARM/abi.ll index 5584dedf697e..be4e2e35f976 100644 --- a/llvm/test/Transforms/SafeStack/ARM/abi.ll +++ b/llvm/test/Transforms/SafeStack/ARM/abi.ll @@ -1,5 +1,4 @@ ; RUN: opt -safe-stack -S -mtriple=arm-linux-android < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=arm-linux-android < %s -o - | FileCheck %s define void @foo() nounwind uwtable safestack { diff --git a/llvm/test/Transforms/SafeStack/ARM/debug.ll b/llvm/test/Transforms/SafeStack/ARM/debug.ll index c38ee62fa6aa..9a61b78d2d96 100644 --- a/llvm/test/Transforms/SafeStack/ARM/debug.ll +++ b/llvm/test/Transforms/SafeStack/ARM/debug.ll @@ -1,5 +1,4 @@ ; RUN: opt -safe-stack -safestack-use-pointer-address < %s -S | FileCheck %s -; RUN: opt -passes=safe-stack -safestack-use-pointer-address < %s -S | FileCheck %s target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "armv7-pc-linux-android" diff --git a/llvm/test/Transforms/SafeStack/ARM/setjmp.ll b/llvm/test/Transforms/SafeStack/ARM/setjmp.ll index 8da5f3549a4c..b86e778aabb1 100644 --- a/llvm/test/Transforms/SafeStack/ARM/setjmp.ll +++ b/llvm/test/Transforms/SafeStack/ARM/setjmp.ll @@ -1,6 +1,5 @@ ; Test stack pointer restore after setjmp() with the function-call safestack ABI. ; RUN: opt -safe-stack -S -mtriple=arm-linux-androideabi < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=arm-linux-androideabi < %s -o - | FileCheck %s @env = global [64 x i32] zeroinitializer, align 4 diff --git a/llvm/test/Transforms/SafeStack/X86/abi.ll b/llvm/test/Transforms/SafeStack/X86/abi.ll index 2afee3b2f342..37d8ea6a67f5 100644 --- a/llvm/test/Transforms/SafeStack/X86/abi.ll +++ b/llvm/test/Transforms/SafeStack/X86/abi.ll @@ -2,10 +2,6 @@ ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s --check-prefix=TLS ; RUN: opt -safe-stack -S -mtriple=i686-linux-android < %s -o - | FileCheck %s --check-prefix=DIRECT-TLS32 ; RUN: opt -safe-stack -S -mtriple=x86_64-linux-android < %s -o - | FileCheck %s --check-prefix=DIRECT-TLS64 -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s --check-prefix=TLS -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s --check-prefix=TLS -; RUN: opt -passes=safe-stack -S -mtriple=i686-linux-android < %s -o - | FileCheck %s --check-prefix=DIRECT-TLS32 -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-linux-android < %s -o - | FileCheck %s --check-prefix=DIRECT-TLS64 define void @foo() nounwind uwtable safestack { diff --git a/llvm/test/Transforms/SafeStack/X86/abi_ssp.ll b/llvm/test/Transforms/SafeStack/X86/abi_ssp.ll index e66127533d38..7cb754999c65 100644 --- a/llvm/test/Transforms/SafeStack/X86/abi_ssp.ll +++ b/llvm/test/Transforms/SafeStack/X86/abi_ssp.ll @@ -8,17 +8,6 @@ ; RUN: opt -safe-stack -S -mtriple=x86_64-unknown-fuchsia < %s -o - | FileCheck --check-prefixes=COMMON,FUCHSIA64 %s -; RUN: opt -passes=safe-stack -S -mtriple=i686-pc-linux-gnu < %s -o - | FileCheck --check-prefixes=COMMON,TLS32 %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck --check-prefixes=COMMON,TLS64 %s - -; RUN: opt -passes=safe-stack -S -mtriple=i686-linux-android < %s -o - | FileCheck --check-prefixes=COMMON,GLOBAL32 %s -; RUN: opt -passes=safe-stack -S -mtriple=i686-linux-android24 < %s -o - | FileCheck --check-prefixes=COMMON,TLS32 %s - -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-linux-android < %s -o - | FileCheck --check-prefixes=COMMON,TLS64 %s - -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-unknown-fuchsia < %s -o - | FileCheck --check-prefixes=COMMON,FUCHSIA64 %s - - define void @foo() safestack sspreq { entry: ; TLS32: %[[StackGuard:.*]] = load ptr, ptr addrspace(256) inttoptr (i32 20 to ptr addrspace(256)) diff --git a/llvm/test/Transforms/SafeStack/X86/addr-taken.ll b/llvm/test/Transforms/SafeStack/X86/addr-taken.ll index 7bbe9f4743d1..cd9f76217a45 100644 --- a/llvm/test/Transforms/SafeStack/X86/addr-taken.ll +++ b/llvm/test/Transforms/SafeStack/X86/addr-taken.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/array-aligned.ll b/llvm/test/Transforms/SafeStack/X86/array-aligned.ll index 509e50072b99..ed05d387b511 100644 --- a/llvm/test/Transforms/SafeStack/X86/array-aligned.ll +++ b/llvm/test/Transforms/SafeStack/X86/array-aligned.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/array.ll b/llvm/test/Transforms/SafeStack/X86/array.ll index e773e375529d..2bc57be3dd6a 100644 --- a/llvm/test/Transforms/SafeStack/X86/array.ll +++ b/llvm/test/Transforms/SafeStack/X86/array.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s ; array [4 x i8] ; Requires protector. diff --git a/llvm/test/Transforms/SafeStack/X86/byval.ll b/llvm/test/Transforms/SafeStack/X86/byval.ll index 29c6e22b7a27..761265e279d4 100644 --- a/llvm/test/Transforms/SafeStack/X86/byval.ll +++ b/llvm/test/Transforms/SafeStack/X86/byval.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/SafeStack/X86/call.ll b/llvm/test/Transforms/SafeStack/X86/call.ll index 9592b33b620b..bb1b46275e1c 100644 --- a/llvm/test/Transforms/SafeStack/X86/call.ll +++ b/llvm/test/Transforms/SafeStack/X86/call.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/SafeStack/X86/cast.ll b/llvm/test/Transforms/SafeStack/X86/cast.ll index 629cd61993d3..41f01c3b576a 100644 --- a/llvm/test/Transforms/SafeStack/X86/cast.ll +++ b/llvm/test/Transforms/SafeStack/X86/cast.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/coloring-ssp.ll b/llvm/test/Transforms/SafeStack/X86/coloring-ssp.ll index 8ff369ef063e..032ffd199477 100644 --- a/llvm/test/Transforms/SafeStack/X86/coloring-ssp.ll +++ b/llvm/test/Transforms/SafeStack/X86/coloring-ssp.ll @@ -1,5 +1,4 @@ ; RUN: opt -safe-stack -safe-stack-coloring=1 -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -safe-stack-coloring=1 -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s ; %x and %y share a stack slot between them, but not with the stack guard. define void @f() safestack sspreq { diff --git a/llvm/test/Transforms/SafeStack/X86/coloring.ll b/llvm/test/Transforms/SafeStack/X86/coloring.ll index 22e1487bdcfc..37bdccffd0c3 100644 --- a/llvm/test/Transforms/SafeStack/X86/coloring.ll +++ b/llvm/test/Transforms/SafeStack/X86/coloring.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -safe-stack-coloring=1 -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -safe-stack-coloring=1 -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -safe-stack-coloring=1 -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -safe-stack-coloring=1 -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s define void @f() safestack { entry: diff --git a/llvm/test/Transforms/SafeStack/X86/coloring2.ll b/llvm/test/Transforms/SafeStack/X86/coloring2.ll index 2e02ea66f9c7..b2f59906b603 100644 --- a/llvm/test/Transforms/SafeStack/X86/coloring2.ll +++ b/llvm/test/Transforms/SafeStack/X86/coloring2.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -safe-stack-coloring=1 -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -safe-stack-coloring=1 -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -safe-stack-coloring=1 -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -safe-stack-coloring=1 -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s ; x and y share the stack slot. define void @f() safestack { diff --git a/llvm/test/Transforms/SafeStack/X86/constant-gep-call.ll b/llvm/test/Transforms/SafeStack/X86/constant-gep-call.ll index 074977b27f66..880471a8a63d 100644 --- a/llvm/test/Transforms/SafeStack/X86/constant-gep-call.ll +++ b/llvm/test/Transforms/SafeStack/X86/constant-gep-call.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s %struct.nest = type { %struct.pair, %struct.pair } %struct.pair = type { i32, i32 } diff --git a/llvm/test/Transforms/SafeStack/X86/constant-gep.ll b/llvm/test/Transforms/SafeStack/X86/constant-gep.ll index 88429ca5304e..935c3624e387 100644 --- a/llvm/test/Transforms/SafeStack/X86/constant-gep.ll +++ b/llvm/test/Transforms/SafeStack/X86/constant-gep.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s %class.A = type { [2 x i8] } diff --git a/llvm/test/Transforms/SafeStack/X86/constant-geps.ll b/llvm/test/Transforms/SafeStack/X86/constant-geps.ll index fe05d0ed17f3..fd099db5f943 100644 --- a/llvm/test/Transforms/SafeStack/X86/constant-geps.ll +++ b/llvm/test/Transforms/SafeStack/X86/constant-geps.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s %struct.deep = type { %union.anon } %union.anon = type { %struct.anon } diff --git a/llvm/test/Transforms/SafeStack/X86/debug-loc-dynamic.ll b/llvm/test/Transforms/SafeStack/X86/debug-loc-dynamic.ll index 42d2aa91307f..b5d862b03b62 100644 --- a/llvm/test/Transforms/SafeStack/X86/debug-loc-dynamic.ll +++ b/llvm/test/Transforms/SafeStack/X86/debug-loc-dynamic.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - --try-experimental-debuginfo-iterators | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - --try-experimental-debuginfo-iterators | FileCheck %s ; Test llvm.dbg.value for dynamic allocas moved onto the unsafe stack. ; In the dynamic alloca case, the dbg.value does not change with the exception diff --git a/llvm/test/Transforms/SafeStack/X86/debug-loc.ll b/llvm/test/Transforms/SafeStack/X86/debug-loc.ll index 9a4df89f37b0..41240f7d7a91 100644 --- a/llvm/test/Transforms/SafeStack/X86/debug-loc.ll +++ b/llvm/test/Transforms/SafeStack/X86/debug-loc.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - --try-experimental-debuginfo-iterators | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - --try-experimental-debuginfo-iterators | FileCheck %s ; Test debug location for the local variables moved onto the unsafe stack. diff --git a/llvm/test/Transforms/SafeStack/X86/debug-loc2.ll b/llvm/test/Transforms/SafeStack/X86/debug-loc2.ll index 915126bc3bbe..a7164ef0f45c 100644 --- a/llvm/test/Transforms/SafeStack/X86/debug-loc2.ll +++ b/llvm/test/Transforms/SafeStack/X86/debug-loc2.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - --try-experimental-debuginfo-iterators | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - --try-experimental-debuginfo-iterators | FileCheck %s ; Test llvm.dbg.value for the local variables moved onto the unsafe stack. ; SafeStack rewrites them relative to the unsafe stack pointer (base address of diff --git a/llvm/test/Transforms/SafeStack/X86/dynamic-alloca.ll b/llvm/test/Transforms/SafeStack/X86/dynamic-alloca.ll index a8dec20973ba..d8377781bb6e 100644 --- a/llvm/test/Transforms/SafeStack/X86/dynamic-alloca.ll +++ b/llvm/test/Transforms/SafeStack/X86/dynamic-alloca.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/escape-addr-pointer.ll b/llvm/test/Transforms/SafeStack/X86/escape-addr-pointer.ll index 42448fb62024..a650ee9661f0 100644 --- a/llvm/test/Transforms/SafeStack/X86/escape-addr-pointer.ll +++ b/llvm/test/Transforms/SafeStack/X86/escape-addr-pointer.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/escape-bitcast-store.ll b/llvm/test/Transforms/SafeStack/X86/escape-bitcast-store.ll index 23a8edf4afce..bde9c3a21964 100644 --- a/llvm/test/Transforms/SafeStack/X86/escape-bitcast-store.ll +++ b/llvm/test/Transforms/SafeStack/X86/escape-bitcast-store.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/escape-bitcast-store2.ll b/llvm/test/Transforms/SafeStack/X86/escape-bitcast-store2.ll index 1a3c8ac215e0..8dd1233cd023 100644 --- a/llvm/test/Transforms/SafeStack/X86/escape-bitcast-store2.ll +++ b/llvm/test/Transforms/SafeStack/X86/escape-bitcast-store2.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/escape-call.ll b/llvm/test/Transforms/SafeStack/X86/escape-call.ll index 1d87cae52683..9af891e3f62e 100644 --- a/llvm/test/Transforms/SafeStack/X86/escape-call.ll +++ b/llvm/test/Transforms/SafeStack/X86/escape-call.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/escape-casted-pointer.ll b/llvm/test/Transforms/SafeStack/X86/escape-casted-pointer.ll index 9ca0fd39fbab..d482f0c8263f 100644 --- a/llvm/test/Transforms/SafeStack/X86/escape-casted-pointer.ll +++ b/llvm/test/Transforms/SafeStack/X86/escape-casted-pointer.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/escape-gep-call.ll b/llvm/test/Transforms/SafeStack/X86/escape-gep-call.ll index 60e4f91ed61e..759dc5d1cb1a 100644 --- a/llvm/test/Transforms/SafeStack/X86/escape-gep-call.ll +++ b/llvm/test/Transforms/SafeStack/X86/escape-gep-call.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s %struct.pair = type { i32, i32 } diff --git a/llvm/test/Transforms/SafeStack/X86/escape-gep-invoke.ll b/llvm/test/Transforms/SafeStack/X86/escape-gep-invoke.ll index db69fbfd38f6..d09a3d85d39e 100644 --- a/llvm/test/Transforms/SafeStack/X86/escape-gep-invoke.ll +++ b/llvm/test/Transforms/SafeStack/X86/escape-gep-invoke.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s %struct.pair = type { i32, i32 } diff --git a/llvm/test/Transforms/SafeStack/X86/escape-gep-negative.ll b/llvm/test/Transforms/SafeStack/X86/escape-gep-negative.ll index 96625c5aaad8..896cae962105 100644 --- a/llvm/test/Transforms/SafeStack/X86/escape-gep-negative.ll +++ b/llvm/test/Transforms/SafeStack/X86/escape-gep-negative.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/escape-gep-ptrtoint.ll b/llvm/test/Transforms/SafeStack/X86/escape-gep-ptrtoint.ll index 8a38781981af..60783b8d657a 100644 --- a/llvm/test/Transforms/SafeStack/X86/escape-gep-ptrtoint.ll +++ b/llvm/test/Transforms/SafeStack/X86/escape-gep-ptrtoint.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s %struct.pair = type { i32, i32 } diff --git a/llvm/test/Transforms/SafeStack/X86/escape-gep-store.ll b/llvm/test/Transforms/SafeStack/X86/escape-gep-store.ll index a2693ca76702..b7dad0eb34ba 100644 --- a/llvm/test/Transforms/SafeStack/X86/escape-gep-store.ll +++ b/llvm/test/Transforms/SafeStack/X86/escape-gep-store.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s %struct.pair = type { i32, i32 } diff --git a/llvm/test/Transforms/SafeStack/X86/escape-phi-call.ll b/llvm/test/Transforms/SafeStack/X86/escape-phi-call.ll index 57e116834ab0..1dd5d6e0d927 100644 --- a/llvm/test/Transforms/SafeStack/X86/escape-phi-call.ll +++ b/llvm/test/Transforms/SafeStack/X86/escape-phi-call.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/escape-select-call.ll b/llvm/test/Transforms/SafeStack/X86/escape-select-call.ll index 67b284aa1d1d..5d1046ca9660 100644 --- a/llvm/test/Transforms/SafeStack/X86/escape-select-call.ll +++ b/llvm/test/Transforms/SafeStack/X86/escape-select-call.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/escape-vector.ll b/llvm/test/Transforms/SafeStack/X86/escape-vector.ll index 055f558c966e..c725ba922cf0 100644 --- a/llvm/test/Transforms/SafeStack/X86/escape-vector.ll +++ b/llvm/test/Transforms/SafeStack/X86/escape-vector.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s %struct.vec = type { <4 x i32> } diff --git a/llvm/test/Transforms/SafeStack/X86/invoke.ll b/llvm/test/Transforms/SafeStack/X86/invoke.ll index 23d935eb06ac..5385169950cc 100644 --- a/llvm/test/Transforms/SafeStack/X86/invoke.ll +++ b/llvm/test/Transforms/SafeStack/X86/invoke.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/layout-frag.ll b/llvm/test/Transforms/SafeStack/X86/layout-frag.ll index b858fd613153..19c3855bc1cb 100644 --- a/llvm/test/Transforms/SafeStack/X86/layout-frag.ll +++ b/llvm/test/Transforms/SafeStack/X86/layout-frag.ll @@ -1,6 +1,5 @@ ; Test that safestack layout reuses a region w/o fragmentation. ; RUN: opt -safe-stack -safe-stack-coloring=1 -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -safe-stack-coloring=1 -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s define void @f() safestack { ; CHECK-LABEL: define void @f diff --git a/llvm/test/Transforms/SafeStack/X86/layout-region-split.ll b/llvm/test/Transforms/SafeStack/X86/layout-region-split.ll index b126fdff204f..3bee85527f82 100644 --- a/llvm/test/Transforms/SafeStack/X86/layout-region-split.ll +++ b/llvm/test/Transforms/SafeStack/X86/layout-region-split.ll @@ -1,6 +1,5 @@ ; Regression test for safestack layout. Used to fail with asan. ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s define void @f() safestack { ; CHECK-LABEL: define void @f diff --git a/llvm/test/Transforms/SafeStack/X86/memintrinsic-oob-read.ll b/llvm/test/Transforms/SafeStack/X86/memintrinsic-oob-read.ll index 75e40ad6921d..9bc247ed6c50 100644 --- a/llvm/test/Transforms/SafeStack/X86/memintrinsic-oob-read.ll +++ b/llvm/test/Transforms/SafeStack/X86/memintrinsic-oob-read.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/SafeStack/X86/musttail.ll b/llvm/test/Transforms/SafeStack/X86/musttail.ll index a6e127924bf5..32bc6674a2a2 100644 --- a/llvm/test/Transforms/SafeStack/X86/musttail.ll +++ b/llvm/test/Transforms/SafeStack/X86/musttail.ll @@ -1,7 +1,6 @@ ; To test that safestack does not break the musttail call contract. ; ; RUN: opt < %s --safe-stack -S | FileCheck %s -; RUN: opt < %s -passes=safe-stack -S | FileCheck %s target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/SafeStack/X86/no-attr.ll b/llvm/test/Transforms/SafeStack/X86/no-attr.ll index 1a292b5a84b3..7715ca59f168 100644 --- a/llvm/test/Transforms/SafeStack/X86/no-attr.ll +++ b/llvm/test/Transforms/SafeStack/X86/no-attr.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/no-crash-on-lifetime.ll b/llvm/test/Transforms/SafeStack/X86/no-crash-on-lifetime.ll index 76c638ebbd21..45e9fa3c2e3f 100644 --- a/llvm/test/Transforms/SafeStack/X86/no-crash-on-lifetime.ll +++ b/llvm/test/Transforms/SafeStack/X86/no-crash-on-lifetime.ll @@ -1,6 +1,5 @@ ; Check that the pass does not crash on the code. ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu %s -o /dev/null -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu %s -o /dev/null %class.F = type { %class.o, i8, [7 x i8] } %class.o = type <{ ptr, i32, [4 x i8] }> diff --git a/llvm/test/Transforms/SafeStack/X86/phi-cycle.ll b/llvm/test/Transforms/SafeStack/X86/phi-cycle.ll index cca87af96ccf..18e6a7d50fe4 100644 --- a/llvm/test/Transforms/SafeStack/X86/phi-cycle.ll +++ b/llvm/test/Transforms/SafeStack/X86/phi-cycle.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s %struct.small = type { i8 } diff --git a/llvm/test/Transforms/SafeStack/X86/phi.ll b/llvm/test/Transforms/SafeStack/X86/phi.ll index 8f0023edd54a..18380431f639 100644 --- a/llvm/test/Transforms/SafeStack/X86/phi.ll +++ b/llvm/test/Transforms/SafeStack/X86/phi.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s define void @f(i1 %d1, i1 %d2) safestack { entry: diff --git a/llvm/test/Transforms/SafeStack/X86/pr54784.ll b/llvm/test/Transforms/SafeStack/X86/pr54784.ll index 398a53848063..940f56004e81 100644 --- a/llvm/test/Transforms/SafeStack/X86/pr54784.ll +++ b/llvm/test/Transforms/SafeStack/X86/pr54784.ll @@ -1,6 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -S -safe-stack < %s | FileCheck %s -; RUN: opt -S -passes=safe-stack < %s | FileCheck %s target triple = "x86_64-unknown-unknown" diff --git a/llvm/test/Transforms/SafeStack/X86/ret.ll b/llvm/test/Transforms/SafeStack/X86/ret.ll index 40ed6f50d4d2..b8a3e0569d49 100644 --- a/llvm/test/Transforms/SafeStack/X86/ret.ll +++ b/llvm/test/Transforms/SafeStack/X86/ret.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/setjmp.ll b/llvm/test/Transforms/SafeStack/X86/setjmp.ll index e3003ccd9b86..64a39e081631 100644 --- a/llvm/test/Transforms/SafeStack/X86/setjmp.ll +++ b/llvm/test/Transforms/SafeStack/X86/setjmp.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s %struct.__jmp_buf_tag = type { [8 x i64], i32, %struct.__sigset_t } %struct.__sigset_t = type { [16 x i64] } diff --git a/llvm/test/Transforms/SafeStack/X86/setjmp2.ll b/llvm/test/Transforms/SafeStack/X86/setjmp2.ll index dbb9a08dc5a1..d5bd7c67109a 100644 --- a/llvm/test/Transforms/SafeStack/X86/setjmp2.ll +++ b/llvm/test/Transforms/SafeStack/X86/setjmp2.ll @@ -1,8 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3 ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s --check-prefix=I386 ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s --check-prefix=X86-64 -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s --check-prefix=I386 -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s --check-prefix=X86-64 %struct.__jmp_buf_tag = type { [8 x i64], i32, %struct.__sigset_t } %struct.__sigset_t = type { [16 x i64] } diff --git a/llvm/test/Transforms/SafeStack/X86/sink-to-use.ll b/llvm/test/Transforms/SafeStack/X86/sink-to-use.ll index e6a95c3be82b..1a7984a7c04a 100644 --- a/llvm/test/Transforms/SafeStack/X86/sink-to-use.ll +++ b/llvm/test/Transforms/SafeStack/X86/sink-to-use.ll @@ -1,8 +1,6 @@ ; Test that unsafe alloca address calculation is done immediately before each use. ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s define void @f() safestack { entry: diff --git a/llvm/test/Transforms/SafeStack/X86/ssp.ll b/llvm/test/Transforms/SafeStack/X86/ssp.ll index c40abc65ca37..56e1ac69d1d7 100644 --- a/llvm/test/Transforms/SafeStack/X86/ssp.ll +++ b/llvm/test/Transforms/SafeStack/X86/ssp.ll @@ -1,5 +1,4 @@ ; RUN: opt -safe-stack -S -mtriple=x86_64-unknown < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-unknown < %s -o - | FileCheck %s define void @foo() safestack sspreq { entry: diff --git a/llvm/test/Transforms/SafeStack/X86/store.ll b/llvm/test/Transforms/SafeStack/X86/store.ll index 1e737f1551d7..6fc08760a72c 100644 --- a/llvm/test/Transforms/SafeStack/X86/store.ll +++ b/llvm/test/Transforms/SafeStack/X86/store.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/struct.ll b/llvm/test/Transforms/SafeStack/X86/struct.ll index 0c841c12025b..8bce24bb5380 100644 --- a/llvm/test/Transforms/SafeStack/X86/struct.ll +++ b/llvm/test/Transforms/SafeStack/X86/struct.ll @@ -1,7 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s -; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s %struct.foo = type { [16 x i8] } -- GitLab From 306e13e499e45c8a2b24bd00937688fade8ad41e Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 30 Nov 2023 09:50:03 -0800 Subject: [PATCH 009/699] [RISCV][GISel] Remove unnecessary Observer notifications from legalizeVAStart. MIRBuilder already tells the observer when an instruction is created. No other legalizer code on any target tells the observer when it erases the instruction it was asked to legalize. --- llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 11 ++++------- llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h | 3 +-- 2 files changed, 5 insertions(+), 9 deletions(-) diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp index 9564ed9c4187..609c26c8e166 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp @@ -331,8 +331,7 @@ bool RISCVLegalizerInfo::legalizeShlAshrLshr( } bool RISCVLegalizerInfo::legalizeVAStart(MachineInstr &MI, - MachineIRBuilder &MIRBuilder, - GISelChangeObserver &Observer) const { + MachineIRBuilder &MIRBuilder) const { // Stores the address of the VarArgsFrameIndex slot into the memory location assert(MI.getOpcode() == TargetOpcode::G_VASTART); MachineFunction *MF = MI.getParent()->getParent(); @@ -341,10 +340,8 @@ bool RISCVLegalizerInfo::legalizeVAStart(MachineInstr &MI, LLT AddrTy = MIRBuilder.getMRI()->getType(MI.getOperand(0).getReg()); auto FINAddr = MIRBuilder.buildFrameIndex(AddrTy, FI); assert(MI.hasOneMemOperand()); - MachineInstr *LoweredMI = MIRBuilder.buildStore( - MI.getOperand(0).getReg(), FINAddr, *MI.memoperands()[0]); - Observer.createdInstr(*LoweredMI); - Observer.erasingInstr(MI); + MIRBuilder.buildStore(MI.getOperand(0).getReg(), FINAddr, + *MI.memoperands()[0]); MI.eraseFromParent(); return true; } @@ -390,7 +387,7 @@ bool RISCVLegalizerInfo::legalizeCustom(LegalizerHelper &Helper, return true; } case TargetOpcode::G_VASTART: - return legalizeVAStart(MI, MIRBuilder, Observer); + return legalizeVAStart(MI, MIRBuilder); } llvm_unreachable("expected switch to return"); diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h index c0e6088ac5c1..246ea90dcd74 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h +++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h @@ -36,8 +36,7 @@ private: bool legalizeShlAshrLshr(MachineInstr &MI, MachineIRBuilder &MIRBuilder, GISelChangeObserver &Observer) const; - bool legalizeVAStart(MachineInstr &MI, MachineIRBuilder &MIRBuilder, - GISelChangeObserver &Observer) const; + bool legalizeVAStart(MachineInstr &MI, MachineIRBuilder &MIRBuilder) const; }; } // end namespace llvm #endif -- GitLab From 28ad007927a4126e12b7aec7daa7f10bc1e29ae1 Mon Sep 17 00:00:00 2001 From: eleviant <56861949+eleviant@users.noreply.github.com> Date: Thu, 30 Nov 2023 19:02:25 +0100 Subject: [PATCH 010/699] [ThinLTO] Don't mark calloc function dead (#72673) Dead store elimination pass may fold malloc + memset calls into a single call to calloc. If calloc is not preserved and is not being called it can be marked dead which results in link error. --- lld/test/ELF/lto/libcall-archive-calloc.ll | 4 ++-- llvm/include/llvm/IR/RuntimeLibcalls.def | 2 ++ llvm/test/ThinLTO/X86/builtin-nostrip.ll | 13 +++++++++++-- 3 files changed, 15 insertions(+), 4 deletions(-) diff --git a/lld/test/ELF/lto/libcall-archive-calloc.ll b/lld/test/ELF/lto/libcall-archive-calloc.ll index 12d5d4ae572d..f082a6ce68ab 100644 --- a/lld/test/ELF/lto/libcall-archive-calloc.ll +++ b/lld/test/ELF/lto/libcall-archive-calloc.ll @@ -11,12 +11,12 @@ ; RUN: llvm-dis < t.0.4.opt.bc | FileCheck %s ; RUN: llvm-nm t | FileCheck %s --check-prefix=NM -; CHECK: declare noalias noundef ptr @calloc(i64 noundef, i64 noundef) +; CHECK: define dso_local void @calloc ; NM-NOT: {{.}} ; NM: {{.*}} T _start ;; TODO: Currently the symbol is lazy, which lowers to a SHN_ABS symbol at address 0. -; NM-NEXT: {{.*}} A calloc +; NM-NEXT: {{.*}} T calloc ; NM-NEXT: {{.*}} T foo ; NM-NEXT: {{.*}} T malloc ; NM-NEXT: {{.*}} T memset diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.def b/llvm/include/llvm/IR/RuntimeLibcalls.def index 6ec98e278988..19dea60bebf9 100644 --- a/llvm/include/llvm/IR/RuntimeLibcalls.def +++ b/llvm/include/llvm/IR/RuntimeLibcalls.def @@ -438,6 +438,8 @@ HANDLE_LIBCALL(UO_PPCF128, "__gcc_qunord") HANDLE_LIBCALL(MEMCPY, "memcpy") HANDLE_LIBCALL(MEMMOVE, "memmove") HANDLE_LIBCALL(MEMSET, "memset") +// DSEPass can emit calloc if it finds a pair of malloc/memset +HANDLE_LIBCALL(CALLOC, "calloc") HANDLE_LIBCALL(BZERO, nullptr) // Element-wise unordered-atomic memory of different sizes diff --git a/llvm/test/ThinLTO/X86/builtin-nostrip.ll b/llvm/test/ThinLTO/X86/builtin-nostrip.ll index 1b6a4ef87925..9ac58cf824d2 100644 --- a/llvm/test/ThinLTO/X86/builtin-nostrip.ll +++ b/llvm/test/ThinLTO/X86/builtin-nostrip.ll @@ -10,7 +10,8 @@ ; RUN: llvm-lto2 run %t1.bc -o %t.out -save-temps \ ; RUN: -r %t1.bc,bar,pl \ ; RUN: -r %t1.bc,__stack_chk_guard,pl \ -; RUN: -r %t1.bc,__stack_chk_fail,pl +; RUN: -r %t1.bc,__stack_chk_fail,pl \ +; RUN: -r %t1.bc,calloc,pl ; RUN: llvm-nm %t.out.1 | FileCheck %s --check-prefix=CHECK-NM ; Re-compile, this time without the thinlto indices. @@ -20,7 +21,8 @@ ; RUN: llvm-lto2 run %t4.bc -o %t5.out -save-temps \ ; RUN: -r %t4.bc,bar,pl \ ; RUN: -r %t4.bc,__stack_chk_guard,pl \ -; RUN: -r %t4.bc,__stack_chk_fail,pl +; RUN: -r %t4.bc,__stack_chk_fail,pl \ +; RUN: -r %t4.bc,calloc,pl ; RUN: llvm-nm %t5.out.0 | FileCheck %s --check-prefix=CHECK-NM ; Test the old lto interface without thinlto. @@ -30,6 +32,9 @@ ; CHECK-NM-NOT: bar ; CHECK-NM: T __stack_chk_fail ; CHECK-NM: D __stack_chk_guard +; Allow calloc to be internalized so --gc-sections can +; still eliminate it if it's not really used anywhere. +; CHECK-NM: {{[Tt]}} calloc ; CHECK-NM-NOT: bar target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" @@ -44,3 +49,7 @@ define void @bar() { define void @__stack_chk_fail() { ret void } + +define ptr @calloc(i64, i64) { + ret ptr null +} -- GitLab From 899fd0cd66044ce54744205218c8a24f1a163ef0 Mon Sep 17 00:00:00 2001 From: LLVM GN Syncbot Date: Thu, 30 Nov 2023 18:02:39 +0000 Subject: [PATCH 011/699] [gn build] Port cb13e9286b6d --- llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn index 7881905228a4..2e5b7e03bd65 100644 --- a/llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn @@ -74,6 +74,7 @@ static_library("LLVMBPFCodeGen") { "BPFMIPeephole.cpp", "BPFMISimplifyPatchable.cpp", "BPFPreserveDIType.cpp", + "BPFPreserveStaticOffset.cpp", "BPFRegisterInfo.cpp", "BPFSelectionDAGInfo.cpp", "BPFSubtarget.cpp", -- GitLab From 539e60c34a0a960f55eacf764f8c74d6c6c9d2b3 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Thu, 30 Nov 2023 16:32:17 +0000 Subject: [PATCH 012/699] [X86] X86FixupVectorConstantsPass - consistently use non-DQI 128/256-bit subvector broadcasts Without the predicate there's no benefit to using the DQI variants instead of the default AVX512F instructions --- .../Target/X86/X86FixupVectorConstants.cpp | 32 +- .../vector-interleaved-load-i16-stride-7.ll | 463 +- .../vector-interleaved-load-i16-stride-8.ll | 843 +-- .../vector-interleaved-load-i32-stride-8.ll | 1686 ++--- .../vector-interleaved-load-i64-stride-7.ll | 2673 +++---- .../vector-interleaved-load-i8-stride-3.ll | 111 +- .../vector-interleaved-load-i8-stride-7.ll | 8 +- .../vector-interleaved-store-i16-stride-7.ll | 6700 ++++++----------- .../vector-interleaved-store-i64-stride-6.ll | 6568 ++++++---------- .../vector-interleaved-store-i64-stride-7.ll | 40 +- .../vector-interleaved-store-i64-stride-8.ll | 5928 +++++---------- .../vector-interleaved-store-i8-stride-5.ll | 540 +- .../vector-interleaved-store-i8-stride-6.ll | 630 +- .../vector-interleaved-store-i8-stride-7.ll | 2718 +++---- llvm/test/CodeGen/X86/vector-lzcnt-512.ll | 32 +- .../zero_extend_vector_inreg_of_broadcast.ll | 8 +- ...d_vector_inreg_of_broadcast_from_memory.ll | 8 +- 17 files changed, 9698 insertions(+), 19290 deletions(-) diff --git a/llvm/lib/Target/X86/X86FixupVectorConstants.cpp b/llvm/lib/Target/X86/X86FixupVectorConstants.cpp index 4415c20496a1..99e92bbcf996 100644 --- a/llvm/lib/Target/X86/X86FixupVectorConstants.cpp +++ b/llvm/lib/Target/X86/X86FixupVectorConstants.cpp @@ -297,17 +297,16 @@ bool X86FixupVectorConstantsPass::processInstruction(MachineFunction &MF, case X86::VMOVAPSZ256rm: case X86::VMOVUPDZ256rm: case X86::VMOVUPSZ256rm: - return ConvertToBroadcast( - 0, HasDQI ? X86::VBROADCASTF64X2Z128rm : X86::VBROADCASTF32X4Z256rm, - X86::VBROADCASTSDZ256rm, X86::VBROADCASTSSZ256rm, 0, 0, 1); + return ConvertToBroadcast(0, X86::VBROADCASTF32X4Z256rm, + X86::VBROADCASTSDZ256rm, X86::VBROADCASTSSZ256rm, + 0, 0, 1); case X86::VMOVAPDZrm: case X86::VMOVAPSZrm: case X86::VMOVUPDZrm: case X86::VMOVUPSZrm: - return ConvertToBroadcast( - HasDQI ? X86::VBROADCASTF32X8rm : X86::VBROADCASTF64X4rm, - HasDQI ? X86::VBROADCASTF64X2rm : X86::VBROADCASTF32X4rm, - X86::VBROADCASTSDZrm, X86::VBROADCASTSSZrm, 0, 0, 1); + return ConvertToBroadcast(X86::VBROADCASTF64X4rm, X86::VBROADCASTF32X4rm, + X86::VBROADCASTSDZrm, X86::VBROADCASTSSZrm, 0, 0, + 1); /* Integer Loads */ case X86::VMOVDQArm: case X86::VMOVDQUrm: @@ -336,21 +335,18 @@ bool X86FixupVectorConstantsPass::processInstruction(MachineFunction &MF, case X86::VMOVDQA64Z256rm: case X86::VMOVDQU32Z256rm: case X86::VMOVDQU64Z256rm: - return ConvertToBroadcast( - 0, HasDQI ? X86::VBROADCASTI64X2Z128rm : X86::VBROADCASTI32X4Z256rm, - X86::VPBROADCASTQZ256rm, X86::VPBROADCASTDZ256rm, - HasBWI ? X86::VPBROADCASTWZ256rm : 0, - HasBWI ? X86::VPBROADCASTBZ256rm : 0, 1); + return ConvertToBroadcast(0, X86::VBROADCASTI32X4Z256rm, + X86::VPBROADCASTQZ256rm, X86::VPBROADCASTDZ256rm, + HasBWI ? X86::VPBROADCASTWZ256rm : 0, + HasBWI ? X86::VPBROADCASTBZ256rm : 0, 1); case X86::VMOVDQA32Zrm: case X86::VMOVDQA64Zrm: case X86::VMOVDQU32Zrm: case X86::VMOVDQU64Zrm: - return ConvertToBroadcast( - HasDQI ? X86::VBROADCASTI32X8rm : X86::VBROADCASTI64X4rm, - HasDQI ? X86::VBROADCASTI64X2rm : X86::VBROADCASTI32X4rm, - X86::VPBROADCASTQZrm, X86::VPBROADCASTDZrm, - HasBWI ? X86::VPBROADCASTWZrm : 0, HasBWI ? X86::VPBROADCASTBZrm : 0, - 1); + return ConvertToBroadcast(X86::VBROADCASTI64X4rm, X86::VBROADCASTI32X4rm, + X86::VPBROADCASTQZrm, X86::VPBROADCASTDZrm, + HasBWI ? X86::VPBROADCASTWZrm : 0, + HasBWI ? X86::VPBROADCASTBZrm : 0, 1); } auto ConvertToBroadcastAVX512 = [&](unsigned OpSrc32, unsigned OpSrc64) { diff --git a/llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll b/llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll index dc8fabe3a432..893bff29b21e 100644 --- a/llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll +++ b/llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll @@ -2794,307 +2794,156 @@ define void @load_i16_stride7_vf16(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, pt ; AVX512F-SLOW-NEXT: vzeroupper ; AVX512F-SLOW-NEXT: retq ; -; AVX512F-ONLY-FAST-LABEL: load_i16_stride7_vf16: -; AVX512F-ONLY-FAST: # %bb.0: -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 64(%rdi), %zmm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 128(%rdi), %zmm1 -; AVX512F-ONLY-FAST-NEXT: vbroadcasti32x4 {{.*#+}} ymm16 = [2,5,9,12,2,5,9,12] -; AVX512F-ONLY-FAST-NEXT: # ymm16 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm9 = [10,3,6,15,12,13,6,15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm2 = <2,6,9,u,13,u,u,u> -; AVX512F-ONLY-FAST-NEXT: vpermd %zmm0, %zmm2, %zmm8 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm2 = <2,5,9,u,12,u,u,u> -; AVX512F-ONLY-FAST-NEXT: vpermd %zmm0, %zmm2, %zmm6 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm2 = [8,1,12,5,12,5,14,15] -; AVX512F-ONLY-FAST-NEXT: vpermd %zmm0, %zmm2, %zmm3 -; AVX512F-ONLY-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [3,6,10,13,3,6,10,13] -; AVX512F-ONLY-FAST-NEXT: # ymm2 = mem[0,1,0,1] -; AVX512F-ONLY-FAST-NEXT: vpermd %zmm1, %zmm2, %zmm4 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 192(%rdi), %ymm2 -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm13 = ymm2[0,1,0,2] -; AVX512F-ONLY-FAST-NEXT: vpbroadcastd {{.*#+}} ymm10 = [20,21,26,27,20,21,26,27,20,21,26,27,20,21,26,27,20,21,26,27,20,21,26,27,20,21,26,27,20,21,26,27] -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm10, %ymm13, %ymm5 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm4 = ymm4[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,16,17,22,23,24,25,30,31,u,u,u,u] -; AVX512F-ONLY-FAST-NEXT: vpblendd {{.*#+}} ymm11 = ymm4[0,1,2,3,4,5,6],ymm5[7] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm3 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm3[6,7,12,13,2,3,16,17,30,31,u,u,u,u,u,u,u,u,u,u,u,u] -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rdi), %ymm4 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%rdi), %ymm5 -; AVX512F-ONLY-FAST-NEXT: vpblendd {{.*#+}} ymm12 = ymm4[0,1],ymm5[2],ymm4[3,4,5],ymm5[6],ymm4[7] -; AVX512F-ONLY-FAST-NEXT: vextracti128 $1, %ymm12, %xmm14 -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} xmm12 = xmm12[0,1,2,3],xmm14[4],xmm12[5],xmm14[6],xmm12[7] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm12 = ymm12[0,1,14,15,12,13,10,11,8,9],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm12[u,u,u,u,u,u,u,u,u,u,u,u] -; AVX512F-ONLY-FAST-NEXT: vpor %ymm3, %ymm12, %ymm3 -; AVX512F-ONLY-FAST-NEXT: vpblendd {{.*#+}} ymm3 = ymm3[0,1,2,3,4],ymm11[5,6,7] -; AVX512F-ONLY-FAST-NEXT: vmovdqa 160(%rdi), %ymm11 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 128(%rdi), %ymm12 -; AVX512F-ONLY-FAST-NEXT: vpblendd {{.*#+}} ymm14 = ymm12[0,1],ymm11[2],ymm12[3,4,5],ymm11[6],ymm12[7] -; AVX512F-ONLY-FAST-NEXT: vextracti128 $1, %ymm14, %xmm15 -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} xmm14 = xmm14[0,1,2,3],xmm15[4],xmm14[5],xmm15[6],xmm14[7] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} xmm14 = xmm14[0,1,0,1,14,15,12,13,10,11,8,9,u,u,u,u] -; AVX512F-ONLY-FAST-NEXT: vinserti128 $1, %xmm14, %ymm0, %ymm14 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm13 = ymm13[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,22,23,28,29] -; AVX512F-ONLY-FAST-NEXT: vpblendd {{.*#+}} ymm13 = ymm14[0,1,2,3,4,5,6],ymm13[7] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm6 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm6[0,1,6,7,8,9,18,19],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero -; AVX512F-ONLY-FAST-NEXT: vpblendd {{.*#+}} ymm14 = ymm4[0,1,2],ymm5[3],ymm4[4,5],ymm5[6],ymm4[7] -; AVX512F-ONLY-FAST-NEXT: vextracti128 $1, %ymm14, %xmm15 -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} xmm14 = xmm15[0],xmm14[1],xmm15[2,3,4,5],xmm14[6],xmm15[7] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm14 = ymm14[2,3,0,1,14,15,12,13,10,11],zero,zero,zero,zero,zero,zero,zero,zero,ymm14[u,u,u,u,u,u,u,u,u,u,u,u,u,u] -; AVX512F-ONLY-FAST-NEXT: vpor %ymm6, %ymm14, %ymm6 -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm13 = ymm6[0],ymm13[1,2,3,4,5,6,7],ymm6[8],ymm13[9,10,11,12,13,14,15] -; AVX512F-ONLY-FAST-NEXT: vpblendd {{.*#+}} ymm6 = ymm6[0,1,2,3],ymm13[4,5,6,7] -; AVX512F-ONLY-FAST-NEXT: vpblendd {{.*#+}} ymm13 = ymm12[0,1,2],ymm11[3],ymm12[4,5],ymm11[6],ymm12[7] -; AVX512F-ONLY-FAST-NEXT: vextracti128 $1, %ymm13, %xmm14 -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} xmm13 = xmm14[0],xmm13[1],xmm14[2,3,4,5],xmm13[6],xmm14[7] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} xmm13 = xmm13[0,1,2,3,0,1,14,15,12,13,10,11,u,u,u,u] -; AVX512F-ONLY-FAST-NEXT: vinserti128 $1, %xmm13, %ymm0, %ymm13 -; AVX512F-ONLY-FAST-NEXT: vpbroadcastq {{.*#+}} ymm14 = [2,5,2,5,2,5,2,5] -; AVX512F-ONLY-FAST-NEXT: vpermd %ymm2, %ymm14, %ymm14 -; AVX512F-ONLY-FAST-NEXT: vpshufhw {{.*#+}} ymm14 = ymm14[0,1,2,3,4,5,4,7,8,9,10,11,12,13,12,15] -; AVX512F-ONLY-FAST-NEXT: vpblendd {{.*#+}} ymm13 = ymm13[0,1,2,3,4,5,6],ymm14[7] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm8 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm8[2,3,4,5,10,11,16,17],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero -; AVX512F-ONLY-FAST-NEXT: vpblendd {{.*#+}} ymm14 = ymm5[0],ymm4[1],ymm5[2,3],ymm4[4],ymm5[5,6,7] -; AVX512F-ONLY-FAST-NEXT: vextracti128 $1, %ymm14, %xmm15 -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} xmm14 = xmm14[0],xmm15[1],xmm14[2,3,4,5],xmm15[6],xmm14[7] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm14 = ymm14[4,5,2,3,0,1,14,15,12,13],zero,zero,zero,zero,zero,zero,zero,zero,ymm14[u,u,u,u,u,u,u,u,u,u,u,u,u,u] -; AVX512F-ONLY-FAST-NEXT: vpor %ymm8, %ymm14, %ymm8 -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm13 = ymm8[0],ymm13[1,2,3,4,5,6,7],ymm8[8],ymm13[9,10,11,12,13,14,15] -; AVX512F-ONLY-FAST-NEXT: vpblendd {{.*#+}} ymm8 = ymm8[0,1,2,3],ymm13[4,5,6,7] -; AVX512F-ONLY-FAST-NEXT: vpblendd {{.*#+}} ymm13 = ymm11[0],ymm12[1],ymm11[2,3],ymm12[4],ymm11[5,6,7] -; AVX512F-ONLY-FAST-NEXT: vextracti128 $1, %ymm13, %xmm14 -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} xmm13 = xmm13[0],xmm14[1],xmm13[2,3,4,5],xmm14[6],xmm13[7] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} xmm13 = xmm13[0,1,4,5,2,3,0,1,14,15,12,13,u,u,u,u] -; AVX512F-ONLY-FAST-NEXT: vinserti128 $1, %xmm13, %ymm0, %ymm13 -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm14 = ymm2[0,1,1,3] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm15 = ymm14[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,24,25] -; AVX512F-ONLY-FAST-NEXT: vpblendd {{.*#+}} ymm15 = ymm13[0,1,2,3,4,5,6],ymm15[7] -; AVX512F-ONLY-FAST-NEXT: vpblendd {{.*#+}} ymm13 = ymm5[0],ymm4[1],ymm5[2,3,4],ymm4[5],ymm5[6,7] -; AVX512F-ONLY-FAST-NEXT: vextracti128 $1, %ymm13, %xmm7 -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} xmm7 = xmm7[0],xmm13[1],xmm7[2],xmm13[3],xmm7[4,5,6,7] -; AVX512F-ONLY-FAST-NEXT: vpermd %zmm0, %zmm9, %zmm9 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm9 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm9[4,5,10,11,0,1,22,23],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm7 = ymm7[6,7,4,5,2,3,0,1,14,15],zero,zero,zero,zero,zero,zero,zero,zero,ymm7[u,u,u,u,u,u,u,u,u,u,u,u,u,u] -; AVX512F-ONLY-FAST-NEXT: vpor %ymm7, %ymm9, %ymm7 -; AVX512F-ONLY-FAST-NEXT: vpermd %zmm1, %zmm16, %zmm13 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm9 = <0,3,7,10,14,u,u,u> -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm15 = ymm7[0],ymm15[1,2,3,4,5,6,7],ymm7[8],ymm15[9,10,11,12,13,14,15] -; AVX512F-ONLY-FAST-NEXT: vpblendd {{.*#+}} ymm7 = ymm7[0,1,2,3],ymm15[4,5,6,7] -; AVX512F-ONLY-FAST-NEXT: vpermd %zmm0, %zmm9, %zmm9 -; AVX512F-ONLY-FAST-NEXT: vpblendd {{.*#+}} ymm11 = ymm11[0],ymm12[1],ymm11[2,3,4],ymm12[5],ymm11[6,7] -; AVX512F-ONLY-FAST-NEXT: vextracti128 $1, %ymm11, %xmm12 -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} xmm11 = xmm12[0],xmm11[1],xmm12[2],xmm11[3],xmm12[4,5,6,7] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} xmm11 = xmm11[0,1,6,7,4,5,2,3,0,1,14,15,u,u,u,u] -; AVX512F-ONLY-FAST-NEXT: vinserti128 $1, %xmm11, %ymm0, %ymm11 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm10, %ymm14, %ymm10 -; AVX512F-ONLY-FAST-NEXT: vpblendd {{.*#+}} ymm11 = ymm11[0,1,2,3,4,5,6],ymm10[7] -; AVX512F-ONLY-FAST-NEXT: vpblendd {{.*#+}} ymm10 = ymm5[0,1],ymm4[2],ymm5[3,4],ymm4[5],ymm5[6,7] -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} xmm12 = [8,9,4,5,4,5,6,7,8,9,10,11,12,13,14,15] -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm12, %xmm10, %xmm14 -; AVX512F-ONLY-FAST-NEXT: vextracti128 $1, %ymm10, %xmm10 -; AVX512F-ONLY-FAST-NEXT: vpshuflw {{.*#+}} xmm10 = xmm10[3,1,2,3,4,5,6,7] -; AVX512F-ONLY-FAST-NEXT: vpunpcklwd {{.*#+}} xmm14 = xmm14[0],xmm10[0],xmm14[1],xmm10[1],xmm14[2],xmm10[2],xmm14[3],xmm10[3] -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm10 = -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm10, %ymm9, %ymm9 -; AVX512F-ONLY-FAST-NEXT: vpblendd {{.*#+}} ymm9 = ymm14[0,1],ymm9[2,3,4,5,6,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm11 = ymm9[0],ymm11[1,2,3,4,5,6,7],ymm9[8],ymm11[9,10,11,12,13,14,15] -; AVX512F-ONLY-FAST-NEXT: vpblendd {{.*#+}} ymm9 = ymm9[0,1,2,3],ymm11[4,5,6,7] -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm11 = <0,3,3,u,0,3,7,u> -; AVX512F-ONLY-FAST-NEXT: vpermd %ymm2, %ymm11, %ymm11 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm11 = ymm11[u,u,u,u,u,u,u,u,u,u,0,1,6,7,8,9,u,u,u,u,u,u,u,u,u,u,16,17,22,23,24,25] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm13 = ymm13[u,u,0,1,6,7,8,9,14,15,u,u,u,u,u,u,u,u,16,17,22,23,24,25,30,31,u,u,u,u,u,u] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm11 = ymm13[0,1,2,3,4],ymm11[5,6,7],ymm13[8,9,10,11,12],ymm11[13,14,15] -; AVX512F-ONLY-FAST-NEXT: vpblendd {{.*#+}} ymm13 = ymm5[0,1],ymm4[2,3],ymm5[4,5],ymm4[6,7] -; AVX512F-ONLY-FAST-NEXT: vextracti128 $1, %ymm13, %xmm14 -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm12, %xmm14, %xmm12 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm14 = <1,4,8,11,15,u,u,u> -; AVX512F-ONLY-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm15 = [2,6,9,13,2,6,9,13] -; AVX512F-ONLY-FAST-NEXT: # ymm15 = mem[0,1,0,1] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} ymm16 = <0,4,7,11,14,u,u,u> -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} xmm13 = xmm13[10,11,6,7,4,5,6,7,u,u,u,u,u,u,u,u] -; AVX512F-ONLY-FAST-NEXT: vpunpcklwd {{.*#+}} xmm12 = xmm13[0],xmm12[0],xmm13[1],xmm12[1],xmm13[2],xmm12[2],xmm13[3],xmm12[3] -; AVX512F-ONLY-FAST-NEXT: vpermd %zmm0, %zmm16, %zmm13 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm13 = ymm13[u,u,u,u,u,u,u,u,2,3,4,5,10,11,12,13,18,19,18,19,18,19,18,19,18,19,20,21,26,27,28,29] -; AVX512F-ONLY-FAST-NEXT: vpblendd {{.*#+}} ymm12 = ymm12[0,1],ymm13[2,3,4,5,6,7] -; AVX512F-ONLY-FAST-NEXT: vpermd %zmm1, %zmm15, %zmm1 -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm11 = ymm12[0],ymm11[1,2,3,4,5,6,7],ymm12[8],ymm11[9,10,11,12,13,14,15] -; AVX512F-ONLY-FAST-NEXT: vpblendd {{.*#+}} ymm11 = ymm12[0,1,2,3],ymm11[4,5,6,7] -; AVX512F-ONLY-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm12 = [0,4,7,0,0,4,7,0] -; AVX512F-ONLY-FAST-NEXT: # ymm12 = mem[0,1,0,1] -; AVX512F-ONLY-FAST-NEXT: vpermd %ymm2, %ymm12, %ymm2 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm2[u,u,u,u,u,u,u,u,u,u,2,3,4,5,10,11,u,u,u,u,u,u,u,u,u,u,18,19,20,21,26,27] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[u,u,2,3,4,5,10,11,12,13,u,u,u,u,u,u,u,u,18,19,20,21,26,27,28,29,u,u,u,u,u,u] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0,1,2,3,4],ymm2[5,6,7],ymm1[8,9,10,11,12],ymm2[13,14,15] -; AVX512F-ONLY-FAST-NEXT: vpermd %zmm0, %zmm14, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm10, %ymm0, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vpblendd {{.*#+}} ymm2 = ymm5[0,1,2],ymm4[3],ymm5[4,5],ymm4[6],ymm5[7] -; AVX512F-ONLY-FAST-NEXT: vextracti128 $1, %ymm2, %xmm4 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} xmm4 = xmm4[u,u,u,u,u,u,u,u,10,11,6,7,4,5,6,7] -; AVX512F-ONLY-FAST-NEXT: vpshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,6,4,6,7] -; AVX512F-ONLY-FAST-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm2[4],xmm4[4],xmm2[5],xmm4[5],xmm2[6],xmm4[6],xmm2[7],xmm4[7] -; AVX512F-ONLY-FAST-NEXT: vpblendd {{.*#+}} ymm0 = ymm2[0,1],ymm0[2,3,4,5,6,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm0[0],ymm1[1,2,3,4,5,6,7],ymm0[8],ymm1[9,10,11,12,13,14,15] -; AVX512F-ONLY-FAST-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7] -; AVX512F-ONLY-FAST-NEXT: vmovdqa %ymm3, (%rsi) -; AVX512F-ONLY-FAST-NEXT: vmovdqa %ymm6, (%rdx) -; AVX512F-ONLY-FAST-NEXT: vmovdqa %ymm8, (%rcx) -; AVX512F-ONLY-FAST-NEXT: vmovdqa %ymm7, (%r8) -; AVX512F-ONLY-FAST-NEXT: vmovdqa %ymm9, (%r9) -; AVX512F-ONLY-FAST-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512F-ONLY-FAST-NEXT: vmovdqa %ymm11, (%rax) -; AVX512F-ONLY-FAST-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512F-ONLY-FAST-NEXT: vmovdqa %ymm0, (%rax) -; AVX512F-ONLY-FAST-NEXT: vzeroupper -; AVX512F-ONLY-FAST-NEXT: retq -; -; AVX512DQ-FAST-LABEL: load_i16_stride7_vf16: -; AVX512DQ-FAST: # %bb.0: -; AVX512DQ-FAST-NEXT: vmovdqa64 64(%rdi), %zmm0 -; AVX512DQ-FAST-NEXT: vmovdqa64 128(%rdi), %zmm1 -; AVX512DQ-FAST-NEXT: vbroadcasti64x2 {{.*#+}} ymm16 = [2,5,9,12,2,5,9,12] -; AVX512DQ-FAST-NEXT: # ymm16 = mem[0,1,0,1] -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm9 = [10,3,6,15,12,13,6,15] -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm2 = <2,6,9,u,13,u,u,u> -; AVX512DQ-FAST-NEXT: vpermd %zmm0, %zmm2, %zmm8 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm2 = <2,5,9,u,12,u,u,u> -; AVX512DQ-FAST-NEXT: vpermd %zmm0, %zmm2, %zmm6 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm2 = [8,1,12,5,12,5,14,15] -; AVX512DQ-FAST-NEXT: vpermd %zmm0, %zmm2, %zmm3 -; AVX512DQ-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [3,6,10,13,3,6,10,13] -; AVX512DQ-FAST-NEXT: # ymm2 = mem[0,1,0,1] -; AVX512DQ-FAST-NEXT: vpermd %zmm1, %zmm2, %zmm4 -; AVX512DQ-FAST-NEXT: vmovdqa 192(%rdi), %ymm2 -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm13 = ymm2[0,1,0,2] -; AVX512DQ-FAST-NEXT: vpbroadcastd {{.*#+}} ymm10 = [20,21,26,27,20,21,26,27,20,21,26,27,20,21,26,27,20,21,26,27,20,21,26,27,20,21,26,27,20,21,26,27] -; AVX512DQ-FAST-NEXT: vpshufb %ymm10, %ymm13, %ymm5 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm4 = ymm4[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,16,17,22,23,24,25,30,31,u,u,u,u] -; AVX512DQ-FAST-NEXT: vpblendd {{.*#+}} ymm11 = ymm4[0,1,2,3,4,5,6],ymm5[7] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm3 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm3[6,7,12,13,2,3,16,17,30,31,u,u,u,u,u,u,u,u,u,u,u,u] -; AVX512DQ-FAST-NEXT: vmovdqa (%rdi), %ymm4 -; AVX512DQ-FAST-NEXT: vmovdqa 32(%rdi), %ymm5 -; AVX512DQ-FAST-NEXT: vpblendd {{.*#+}} ymm12 = ymm4[0,1],ymm5[2],ymm4[3,4,5],ymm5[6],ymm4[7] -; AVX512DQ-FAST-NEXT: vextracti128 $1, %ymm12, %xmm14 -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} xmm12 = xmm12[0,1,2,3],xmm14[4],xmm12[5],xmm14[6],xmm12[7] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm12 = ymm12[0,1,14,15,12,13,10,11,8,9],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm12[u,u,u,u,u,u,u,u,u,u,u,u] -; AVX512DQ-FAST-NEXT: vpor %ymm3, %ymm12, %ymm3 -; AVX512DQ-FAST-NEXT: vpblendd {{.*#+}} ymm3 = ymm3[0,1,2,3,4],ymm11[5,6,7] -; AVX512DQ-FAST-NEXT: vmovdqa 160(%rdi), %ymm11 -; AVX512DQ-FAST-NEXT: vmovdqa 128(%rdi), %ymm12 -; AVX512DQ-FAST-NEXT: vpblendd {{.*#+}} ymm14 = ymm12[0,1],ymm11[2],ymm12[3,4,5],ymm11[6],ymm12[7] -; AVX512DQ-FAST-NEXT: vextracti128 $1, %ymm14, %xmm15 -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} xmm14 = xmm14[0,1,2,3],xmm15[4],xmm14[5],xmm15[6],xmm14[7] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} xmm14 = xmm14[0,1,0,1,14,15,12,13,10,11,8,9,u,u,u,u] -; AVX512DQ-FAST-NEXT: vinserti128 $1, %xmm14, %ymm0, %ymm14 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm13 = ymm13[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,22,23,28,29] -; AVX512DQ-FAST-NEXT: vpblendd {{.*#+}} ymm13 = ymm14[0,1,2,3,4,5,6],ymm13[7] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm6 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm6[0,1,6,7,8,9,18,19],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero -; AVX512DQ-FAST-NEXT: vpblendd {{.*#+}} ymm14 = ymm4[0,1,2],ymm5[3],ymm4[4,5],ymm5[6],ymm4[7] -; AVX512DQ-FAST-NEXT: vextracti128 $1, %ymm14, %xmm15 -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} xmm14 = xmm15[0],xmm14[1],xmm15[2,3,4,5],xmm14[6],xmm15[7] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm14 = ymm14[2,3,0,1,14,15,12,13,10,11],zero,zero,zero,zero,zero,zero,zero,zero,ymm14[u,u,u,u,u,u,u,u,u,u,u,u,u,u] -; AVX512DQ-FAST-NEXT: vpor %ymm6, %ymm14, %ymm6 -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm13 = ymm6[0],ymm13[1,2,3,4,5,6,7],ymm6[8],ymm13[9,10,11,12,13,14,15] -; AVX512DQ-FAST-NEXT: vpblendd {{.*#+}} ymm6 = ymm6[0,1,2,3],ymm13[4,5,6,7] -; AVX512DQ-FAST-NEXT: vpblendd {{.*#+}} ymm13 = ymm12[0,1,2],ymm11[3],ymm12[4,5],ymm11[6],ymm12[7] -; AVX512DQ-FAST-NEXT: vextracti128 $1, %ymm13, %xmm14 -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} xmm13 = xmm14[0],xmm13[1],xmm14[2,3,4,5],xmm13[6],xmm14[7] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} xmm13 = xmm13[0,1,2,3,0,1,14,15,12,13,10,11,u,u,u,u] -; AVX512DQ-FAST-NEXT: vinserti128 $1, %xmm13, %ymm0, %ymm13 -; AVX512DQ-FAST-NEXT: vpbroadcastq {{.*#+}} ymm14 = [2,5,2,5,2,5,2,5] -; AVX512DQ-FAST-NEXT: vpermd %ymm2, %ymm14, %ymm14 -; AVX512DQ-FAST-NEXT: vpshufhw {{.*#+}} ymm14 = ymm14[0,1,2,3,4,5,4,7,8,9,10,11,12,13,12,15] -; AVX512DQ-FAST-NEXT: vpblendd {{.*#+}} ymm13 = ymm13[0,1,2,3,4,5,6],ymm14[7] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm8 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm8[2,3,4,5,10,11,16,17],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero -; AVX512DQ-FAST-NEXT: vpblendd {{.*#+}} ymm14 = ymm5[0],ymm4[1],ymm5[2,3],ymm4[4],ymm5[5,6,7] -; AVX512DQ-FAST-NEXT: vextracti128 $1, %ymm14, %xmm15 -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} xmm14 = xmm14[0],xmm15[1],xmm14[2,3,4,5],xmm15[6],xmm14[7] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm14 = ymm14[4,5,2,3,0,1,14,15,12,13],zero,zero,zero,zero,zero,zero,zero,zero,ymm14[u,u,u,u,u,u,u,u,u,u,u,u,u,u] -; AVX512DQ-FAST-NEXT: vpor %ymm8, %ymm14, %ymm8 -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm13 = ymm8[0],ymm13[1,2,3,4,5,6,7],ymm8[8],ymm13[9,10,11,12,13,14,15] -; AVX512DQ-FAST-NEXT: vpblendd {{.*#+}} ymm8 = ymm8[0,1,2,3],ymm13[4,5,6,7] -; AVX512DQ-FAST-NEXT: vpblendd {{.*#+}} ymm13 = ymm11[0],ymm12[1],ymm11[2,3],ymm12[4],ymm11[5,6,7] -; AVX512DQ-FAST-NEXT: vextracti128 $1, %ymm13, %xmm14 -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} xmm13 = xmm13[0],xmm14[1],xmm13[2,3,4,5],xmm14[6],xmm13[7] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} xmm13 = xmm13[0,1,4,5,2,3,0,1,14,15,12,13,u,u,u,u] -; AVX512DQ-FAST-NEXT: vinserti128 $1, %xmm13, %ymm0, %ymm13 -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm14 = ymm2[0,1,1,3] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm15 = ymm14[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,24,25] -; AVX512DQ-FAST-NEXT: vpblendd {{.*#+}} ymm15 = ymm13[0,1,2,3,4,5,6],ymm15[7] -; AVX512DQ-FAST-NEXT: vpblendd {{.*#+}} ymm13 = ymm5[0],ymm4[1],ymm5[2,3,4],ymm4[5],ymm5[6,7] -; AVX512DQ-FAST-NEXT: vextracti128 $1, %ymm13, %xmm7 -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} xmm7 = xmm7[0],xmm13[1],xmm7[2],xmm13[3],xmm7[4,5,6,7] -; AVX512DQ-FAST-NEXT: vpermd %zmm0, %zmm9, %zmm9 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm9 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm9[4,5,10,11,0,1,22,23],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm7 = ymm7[6,7,4,5,2,3,0,1,14,15],zero,zero,zero,zero,zero,zero,zero,zero,ymm7[u,u,u,u,u,u,u,u,u,u,u,u,u,u] -; AVX512DQ-FAST-NEXT: vpor %ymm7, %ymm9, %ymm7 -; AVX512DQ-FAST-NEXT: vpermd %zmm1, %zmm16, %zmm13 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm9 = <0,3,7,10,14,u,u,u> -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm15 = ymm7[0],ymm15[1,2,3,4,5,6,7],ymm7[8],ymm15[9,10,11,12,13,14,15] -; AVX512DQ-FAST-NEXT: vpblendd {{.*#+}} ymm7 = ymm7[0,1,2,3],ymm15[4,5,6,7] -; AVX512DQ-FAST-NEXT: vpermd %zmm0, %zmm9, %zmm9 -; AVX512DQ-FAST-NEXT: vpblendd {{.*#+}} ymm11 = ymm11[0],ymm12[1],ymm11[2,3,4],ymm12[5],ymm11[6,7] -; AVX512DQ-FAST-NEXT: vextracti128 $1, %ymm11, %xmm12 -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} xmm11 = xmm12[0],xmm11[1],xmm12[2],xmm11[3],xmm12[4,5,6,7] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} xmm11 = xmm11[0,1,6,7,4,5,2,3,0,1,14,15,u,u,u,u] -; AVX512DQ-FAST-NEXT: vinserti128 $1, %xmm11, %ymm0, %ymm11 -; AVX512DQ-FAST-NEXT: vpshufb %ymm10, %ymm14, %ymm10 -; AVX512DQ-FAST-NEXT: vpblendd {{.*#+}} ymm11 = ymm11[0,1,2,3,4,5,6],ymm10[7] -; AVX512DQ-FAST-NEXT: vpblendd {{.*#+}} ymm10 = ymm5[0,1],ymm4[2],ymm5[3,4],ymm4[5],ymm5[6,7] -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} xmm12 = [8,9,4,5,4,5,6,7,8,9,10,11,12,13,14,15] -; AVX512DQ-FAST-NEXT: vpshufb %xmm12, %xmm10, %xmm14 -; AVX512DQ-FAST-NEXT: vextracti128 $1, %ymm10, %xmm10 -; AVX512DQ-FAST-NEXT: vpshuflw {{.*#+}} xmm10 = xmm10[3,1,2,3,4,5,6,7] -; AVX512DQ-FAST-NEXT: vpunpcklwd {{.*#+}} xmm14 = xmm14[0],xmm10[0],xmm14[1],xmm10[1],xmm14[2],xmm10[2],xmm14[3],xmm10[3] -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm10 = -; AVX512DQ-FAST-NEXT: vpshufb %ymm10, %ymm9, %ymm9 -; AVX512DQ-FAST-NEXT: vpblendd {{.*#+}} ymm9 = ymm14[0,1],ymm9[2,3,4,5,6,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm11 = ymm9[0],ymm11[1,2,3,4,5,6,7],ymm9[8],ymm11[9,10,11,12,13,14,15] -; AVX512DQ-FAST-NEXT: vpblendd {{.*#+}} ymm9 = ymm9[0,1,2,3],ymm11[4,5,6,7] -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm11 = <0,3,3,u,0,3,7,u> -; AVX512DQ-FAST-NEXT: vpermd %ymm2, %ymm11, %ymm11 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm11 = ymm11[u,u,u,u,u,u,u,u,u,u,0,1,6,7,8,9,u,u,u,u,u,u,u,u,u,u,16,17,22,23,24,25] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm13 = ymm13[u,u,0,1,6,7,8,9,14,15,u,u,u,u,u,u,u,u,16,17,22,23,24,25,30,31,u,u,u,u,u,u] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm11 = ymm13[0,1,2,3,4],ymm11[5,6,7],ymm13[8,9,10,11,12],ymm11[13,14,15] -; AVX512DQ-FAST-NEXT: vpblendd {{.*#+}} ymm13 = ymm5[0,1],ymm4[2,3],ymm5[4,5],ymm4[6,7] -; AVX512DQ-FAST-NEXT: vextracti128 $1, %ymm13, %xmm14 -; AVX512DQ-FAST-NEXT: vpshufb %xmm12, %xmm14, %xmm12 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm14 = <1,4,8,11,15,u,u,u> -; AVX512DQ-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm15 = [2,6,9,13,2,6,9,13] -; AVX512DQ-FAST-NEXT: # ymm15 = mem[0,1,0,1] -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} ymm16 = <0,4,7,11,14,u,u,u> -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} xmm13 = xmm13[10,11,6,7,4,5,6,7,u,u,u,u,u,u,u,u] -; AVX512DQ-FAST-NEXT: vpunpcklwd {{.*#+}} xmm12 = xmm13[0],xmm12[0],xmm13[1],xmm12[1],xmm13[2],xmm12[2],xmm13[3],xmm12[3] -; AVX512DQ-FAST-NEXT: vpermd %zmm0, %zmm16, %zmm13 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm13 = ymm13[u,u,u,u,u,u,u,u,2,3,4,5,10,11,12,13,18,19,18,19,18,19,18,19,18,19,20,21,26,27,28,29] -; AVX512DQ-FAST-NEXT: vpblendd {{.*#+}} ymm12 = ymm12[0,1],ymm13[2,3,4,5,6,7] -; AVX512DQ-FAST-NEXT: vpermd %zmm1, %zmm15, %zmm1 -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm11 = ymm12[0],ymm11[1,2,3,4,5,6,7],ymm12[8],ymm11[9,10,11,12,13,14,15] -; AVX512DQ-FAST-NEXT: vpblendd {{.*#+}} ymm11 = ymm12[0,1,2,3],ymm11[4,5,6,7] -; AVX512DQ-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm12 = [0,4,7,0,0,4,7,0] -; AVX512DQ-FAST-NEXT: # ymm12 = mem[0,1,0,1] -; AVX512DQ-FAST-NEXT: vpermd %ymm2, %ymm12, %ymm2 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm2[u,u,u,u,u,u,u,u,u,u,2,3,4,5,10,11,u,u,u,u,u,u,u,u,u,u,18,19,20,21,26,27] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[u,u,2,3,4,5,10,11,12,13,u,u,u,u,u,u,u,u,18,19,20,21,26,27,28,29,u,u,u,u,u,u] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0,1,2,3,4],ymm2[5,6,7],ymm1[8,9,10,11,12],ymm2[13,14,15] -; AVX512DQ-FAST-NEXT: vpermd %zmm0, %zmm14, %zmm0 -; AVX512DQ-FAST-NEXT: vpshufb %ymm10, %ymm0, %ymm0 -; AVX512DQ-FAST-NEXT: vpblendd {{.*#+}} ymm2 = ymm5[0,1,2],ymm4[3],ymm5[4,5],ymm4[6],ymm5[7] -; AVX512DQ-FAST-NEXT: vextracti128 $1, %ymm2, %xmm4 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} xmm4 = xmm4[u,u,u,u,u,u,u,u,10,11,6,7,4,5,6,7] -; AVX512DQ-FAST-NEXT: vpshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,6,4,6,7] -; AVX512DQ-FAST-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm2[4],xmm4[4],xmm2[5],xmm4[5],xmm2[6],xmm4[6],xmm2[7],xmm4[7] -; AVX512DQ-FAST-NEXT: vpblendd {{.*#+}} ymm0 = ymm2[0,1],ymm0[2,3,4,5,6,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm0[0],ymm1[1,2,3,4,5,6,7],ymm0[8],ymm1[9,10,11,12,13,14,15] -; AVX512DQ-FAST-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7] -; AVX512DQ-FAST-NEXT: vmovdqa %ymm3, (%rsi) -; AVX512DQ-FAST-NEXT: vmovdqa %ymm6, (%rdx) -; AVX512DQ-FAST-NEXT: vmovdqa %ymm8, (%rcx) -; AVX512DQ-FAST-NEXT: vmovdqa %ymm7, (%r8) -; AVX512DQ-FAST-NEXT: vmovdqa %ymm9, (%r9) -; AVX512DQ-FAST-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQ-FAST-NEXT: vmovdqa %ymm11, (%rax) -; AVX512DQ-FAST-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQ-FAST-NEXT: vmovdqa %ymm0, (%rax) -; AVX512DQ-FAST-NEXT: vzeroupper -; AVX512DQ-FAST-NEXT: retq +; AVX512F-FAST-LABEL: load_i16_stride7_vf16: +; AVX512F-FAST: # %bb.0: +; AVX512F-FAST-NEXT: vmovdqa64 64(%rdi), %zmm0 +; AVX512F-FAST-NEXT: vmovdqa64 128(%rdi), %zmm1 +; AVX512F-FAST-NEXT: vbroadcasti32x4 {{.*#+}} ymm16 = [2,5,9,12,2,5,9,12] +; AVX512F-FAST-NEXT: # ymm16 = mem[0,1,2,3,0,1,2,3] +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm9 = [10,3,6,15,12,13,6,15] +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm2 = <2,6,9,u,13,u,u,u> +; AVX512F-FAST-NEXT: vpermd %zmm0, %zmm2, %zmm8 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm2 = <2,5,9,u,12,u,u,u> +; AVX512F-FAST-NEXT: vpermd %zmm0, %zmm2, %zmm6 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm2 = [8,1,12,5,12,5,14,15] +; AVX512F-FAST-NEXT: vpermd %zmm0, %zmm2, %zmm3 +; AVX512F-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [3,6,10,13,3,6,10,13] +; AVX512F-FAST-NEXT: # ymm2 = mem[0,1,0,1] +; AVX512F-FAST-NEXT: vpermd %zmm1, %zmm2, %zmm4 +; AVX512F-FAST-NEXT: vmovdqa 192(%rdi), %ymm2 +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm13 = ymm2[0,1,0,2] +; AVX512F-FAST-NEXT: vpbroadcastd {{.*#+}} ymm10 = [20,21,26,27,20,21,26,27,20,21,26,27,20,21,26,27,20,21,26,27,20,21,26,27,20,21,26,27,20,21,26,27] +; AVX512F-FAST-NEXT: vpshufb %ymm10, %ymm13, %ymm5 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm4 = ymm4[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,16,17,22,23,24,25,30,31,u,u,u,u] +; AVX512F-FAST-NEXT: vpblendd {{.*#+}} ymm11 = ymm4[0,1,2,3,4,5,6],ymm5[7] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm3 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm3[6,7,12,13,2,3,16,17,30,31,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX512F-FAST-NEXT: vmovdqa (%rdi), %ymm4 +; AVX512F-FAST-NEXT: vmovdqa 32(%rdi), %ymm5 +; AVX512F-FAST-NEXT: vpblendd {{.*#+}} ymm12 = ymm4[0,1],ymm5[2],ymm4[3,4,5],ymm5[6],ymm4[7] +; AVX512F-FAST-NEXT: vextracti128 $1, %ymm12, %xmm14 +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} xmm12 = xmm12[0,1,2,3],xmm14[4],xmm12[5],xmm14[6],xmm12[7] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm12 = ymm12[0,1,14,15,12,13,10,11,8,9],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm12[u,u,u,u,u,u,u,u,u,u,u,u] +; AVX512F-FAST-NEXT: vpor %ymm3, %ymm12, %ymm3 +; AVX512F-FAST-NEXT: vpblendd {{.*#+}} ymm3 = ymm3[0,1,2,3,4],ymm11[5,6,7] +; AVX512F-FAST-NEXT: vmovdqa 160(%rdi), %ymm11 +; AVX512F-FAST-NEXT: vmovdqa 128(%rdi), %ymm12 +; AVX512F-FAST-NEXT: vpblendd {{.*#+}} ymm14 = ymm12[0,1],ymm11[2],ymm12[3,4,5],ymm11[6],ymm12[7] +; AVX512F-FAST-NEXT: vextracti128 $1, %ymm14, %xmm15 +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} xmm14 = xmm14[0,1,2,3],xmm15[4],xmm14[5],xmm15[6],xmm14[7] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} xmm14 = xmm14[0,1,0,1,14,15,12,13,10,11,8,9,u,u,u,u] +; AVX512F-FAST-NEXT: vinserti128 $1, %xmm14, %ymm0, %ymm14 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm13 = ymm13[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,22,23,28,29] +; AVX512F-FAST-NEXT: vpblendd {{.*#+}} ymm13 = ymm14[0,1,2,3,4,5,6],ymm13[7] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm6 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm6[0,1,6,7,8,9,18,19],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero +; AVX512F-FAST-NEXT: vpblendd {{.*#+}} ymm14 = ymm4[0,1,2],ymm5[3],ymm4[4,5],ymm5[6],ymm4[7] +; AVX512F-FAST-NEXT: vextracti128 $1, %ymm14, %xmm15 +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} xmm14 = xmm15[0],xmm14[1],xmm15[2,3,4,5],xmm14[6],xmm15[7] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm14 = ymm14[2,3,0,1,14,15,12,13,10,11],zero,zero,zero,zero,zero,zero,zero,zero,ymm14[u,u,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX512F-FAST-NEXT: vpor %ymm6, %ymm14, %ymm6 +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm13 = ymm6[0],ymm13[1,2,3,4,5,6,7],ymm6[8],ymm13[9,10,11,12,13,14,15] +; AVX512F-FAST-NEXT: vpblendd {{.*#+}} ymm6 = ymm6[0,1,2,3],ymm13[4,5,6,7] +; AVX512F-FAST-NEXT: vpblendd {{.*#+}} ymm13 = ymm12[0,1,2],ymm11[3],ymm12[4,5],ymm11[6],ymm12[7] +; AVX512F-FAST-NEXT: vextracti128 $1, %ymm13, %xmm14 +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} xmm13 = xmm14[0],xmm13[1],xmm14[2,3,4,5],xmm13[6],xmm14[7] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} xmm13 = xmm13[0,1,2,3,0,1,14,15,12,13,10,11,u,u,u,u] +; AVX512F-FAST-NEXT: vinserti128 $1, %xmm13, %ymm0, %ymm13 +; AVX512F-FAST-NEXT: vpbroadcastq {{.*#+}} ymm14 = [2,5,2,5,2,5,2,5] +; AVX512F-FAST-NEXT: vpermd %ymm2, %ymm14, %ymm14 +; AVX512F-FAST-NEXT: vpshufhw {{.*#+}} ymm14 = ymm14[0,1,2,3,4,5,4,7,8,9,10,11,12,13,12,15] +; AVX512F-FAST-NEXT: vpblendd {{.*#+}} ymm13 = ymm13[0,1,2,3,4,5,6],ymm14[7] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm8 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm8[2,3,4,5,10,11,16,17],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero +; AVX512F-FAST-NEXT: vpblendd {{.*#+}} ymm14 = ymm5[0],ymm4[1],ymm5[2,3],ymm4[4],ymm5[5,6,7] +; AVX512F-FAST-NEXT: vextracti128 $1, %ymm14, %xmm15 +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} xmm14 = xmm14[0],xmm15[1],xmm14[2,3,4,5],xmm15[6],xmm14[7] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm14 = ymm14[4,5,2,3,0,1,14,15,12,13],zero,zero,zero,zero,zero,zero,zero,zero,ymm14[u,u,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX512F-FAST-NEXT: vpor %ymm8, %ymm14, %ymm8 +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm13 = ymm8[0],ymm13[1,2,3,4,5,6,7],ymm8[8],ymm13[9,10,11,12,13,14,15] +; AVX512F-FAST-NEXT: vpblendd {{.*#+}} ymm8 = ymm8[0,1,2,3],ymm13[4,5,6,7] +; AVX512F-FAST-NEXT: vpblendd {{.*#+}} ymm13 = ymm11[0],ymm12[1],ymm11[2,3],ymm12[4],ymm11[5,6,7] +; AVX512F-FAST-NEXT: vextracti128 $1, %ymm13, %xmm14 +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} xmm13 = xmm13[0],xmm14[1],xmm13[2,3,4,5],xmm14[6],xmm13[7] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} xmm13 = xmm13[0,1,4,5,2,3,0,1,14,15,12,13,u,u,u,u] +; AVX512F-FAST-NEXT: vinserti128 $1, %xmm13, %ymm0, %ymm13 +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm14 = ymm2[0,1,1,3] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm15 = ymm14[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,24,25] +; AVX512F-FAST-NEXT: vpblendd {{.*#+}} ymm15 = ymm13[0,1,2,3,4,5,6],ymm15[7] +; AVX512F-FAST-NEXT: vpblendd {{.*#+}} ymm13 = ymm5[0],ymm4[1],ymm5[2,3,4],ymm4[5],ymm5[6,7] +; AVX512F-FAST-NEXT: vextracti128 $1, %ymm13, %xmm7 +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} xmm7 = xmm7[0],xmm13[1],xmm7[2],xmm13[3],xmm7[4,5,6,7] +; AVX512F-FAST-NEXT: vpermd %zmm0, %zmm9, %zmm9 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm9 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm9[4,5,10,11,0,1,22,23],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm7 = ymm7[6,7,4,5,2,3,0,1,14,15],zero,zero,zero,zero,zero,zero,zero,zero,ymm7[u,u,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX512F-FAST-NEXT: vpor %ymm7, %ymm9, %ymm7 +; AVX512F-FAST-NEXT: vpermd %zmm1, %zmm16, %zmm13 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm9 = <0,3,7,10,14,u,u,u> +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm15 = ymm7[0],ymm15[1,2,3,4,5,6,7],ymm7[8],ymm15[9,10,11,12,13,14,15] +; AVX512F-FAST-NEXT: vpblendd {{.*#+}} ymm7 = ymm7[0,1,2,3],ymm15[4,5,6,7] +; AVX512F-FAST-NEXT: vpermd %zmm0, %zmm9, %zmm9 +; AVX512F-FAST-NEXT: vpblendd {{.*#+}} ymm11 = ymm11[0],ymm12[1],ymm11[2,3,4],ymm12[5],ymm11[6,7] +; AVX512F-FAST-NEXT: vextracti128 $1, %ymm11, %xmm12 +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} xmm11 = xmm12[0],xmm11[1],xmm12[2],xmm11[3],xmm12[4,5,6,7] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} xmm11 = xmm11[0,1,6,7,4,5,2,3,0,1,14,15,u,u,u,u] +; AVX512F-FAST-NEXT: vinserti128 $1, %xmm11, %ymm0, %ymm11 +; AVX512F-FAST-NEXT: vpshufb %ymm10, %ymm14, %ymm10 +; AVX512F-FAST-NEXT: vpblendd {{.*#+}} ymm11 = ymm11[0,1,2,3,4,5,6],ymm10[7] +; AVX512F-FAST-NEXT: vpblendd {{.*#+}} ymm10 = ymm5[0,1],ymm4[2],ymm5[3,4],ymm4[5],ymm5[6,7] +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} xmm12 = [8,9,4,5,4,5,6,7,8,9,10,11,12,13,14,15] +; AVX512F-FAST-NEXT: vpshufb %xmm12, %xmm10, %xmm14 +; AVX512F-FAST-NEXT: vextracti128 $1, %ymm10, %xmm10 +; AVX512F-FAST-NEXT: vpshuflw {{.*#+}} xmm10 = xmm10[3,1,2,3,4,5,6,7] +; AVX512F-FAST-NEXT: vpunpcklwd {{.*#+}} xmm14 = xmm14[0],xmm10[0],xmm14[1],xmm10[1],xmm14[2],xmm10[2],xmm14[3],xmm10[3] +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm10 = +; AVX512F-FAST-NEXT: vpshufb %ymm10, %ymm9, %ymm9 +; AVX512F-FAST-NEXT: vpblendd {{.*#+}} ymm9 = ymm14[0,1],ymm9[2,3,4,5,6,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm11 = ymm9[0],ymm11[1,2,3,4,5,6,7],ymm9[8],ymm11[9,10,11,12,13,14,15] +; AVX512F-FAST-NEXT: vpblendd {{.*#+}} ymm9 = ymm9[0,1,2,3],ymm11[4,5,6,7] +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm11 = <0,3,3,u,0,3,7,u> +; AVX512F-FAST-NEXT: vpermd %ymm2, %ymm11, %ymm11 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm11 = ymm11[u,u,u,u,u,u,u,u,u,u,0,1,6,7,8,9,u,u,u,u,u,u,u,u,u,u,16,17,22,23,24,25] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm13 = ymm13[u,u,0,1,6,7,8,9,14,15,u,u,u,u,u,u,u,u,16,17,22,23,24,25,30,31,u,u,u,u,u,u] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm11 = ymm13[0,1,2,3,4],ymm11[5,6,7],ymm13[8,9,10,11,12],ymm11[13,14,15] +; AVX512F-FAST-NEXT: vpblendd {{.*#+}} ymm13 = ymm5[0,1],ymm4[2,3],ymm5[4,5],ymm4[6,7] +; AVX512F-FAST-NEXT: vextracti128 $1, %ymm13, %xmm14 +; AVX512F-FAST-NEXT: vpshufb %xmm12, %xmm14, %xmm12 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm14 = <1,4,8,11,15,u,u,u> +; AVX512F-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm15 = [2,6,9,13,2,6,9,13] +; AVX512F-FAST-NEXT: # ymm15 = mem[0,1,0,1] +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} ymm16 = <0,4,7,11,14,u,u,u> +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} xmm13 = xmm13[10,11,6,7,4,5,6,7,u,u,u,u,u,u,u,u] +; AVX512F-FAST-NEXT: vpunpcklwd {{.*#+}} xmm12 = xmm13[0],xmm12[0],xmm13[1],xmm12[1],xmm13[2],xmm12[2],xmm13[3],xmm12[3] +; AVX512F-FAST-NEXT: vpermd %zmm0, %zmm16, %zmm13 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm13 = ymm13[u,u,u,u,u,u,u,u,2,3,4,5,10,11,12,13,18,19,18,19,18,19,18,19,18,19,20,21,26,27,28,29] +; AVX512F-FAST-NEXT: vpblendd {{.*#+}} ymm12 = ymm12[0,1],ymm13[2,3,4,5,6,7] +; AVX512F-FAST-NEXT: vpermd %zmm1, %zmm15, %zmm1 +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm11 = ymm12[0],ymm11[1,2,3,4,5,6,7],ymm12[8],ymm11[9,10,11,12,13,14,15] +; AVX512F-FAST-NEXT: vpblendd {{.*#+}} ymm11 = ymm12[0,1,2,3],ymm11[4,5,6,7] +; AVX512F-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm12 = [0,4,7,0,0,4,7,0] +; AVX512F-FAST-NEXT: # ymm12 = mem[0,1,0,1] +; AVX512F-FAST-NEXT: vpermd %ymm2, %ymm12, %ymm2 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm2[u,u,u,u,u,u,u,u,u,u,2,3,4,5,10,11,u,u,u,u,u,u,u,u,u,u,18,19,20,21,26,27] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[u,u,2,3,4,5,10,11,12,13,u,u,u,u,u,u,u,u,18,19,20,21,26,27,28,29,u,u,u,u,u,u] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0,1,2,3,4],ymm2[5,6,7],ymm1[8,9,10,11,12],ymm2[13,14,15] +; AVX512F-FAST-NEXT: vpermd %zmm0, %zmm14, %zmm0 +; AVX512F-FAST-NEXT: vpshufb %ymm10, %ymm0, %ymm0 +; AVX512F-FAST-NEXT: vpblendd {{.*#+}} ymm2 = ymm5[0,1,2],ymm4[3],ymm5[4,5],ymm4[6],ymm5[7] +; AVX512F-FAST-NEXT: vextracti128 $1, %ymm2, %xmm4 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} xmm4 = xmm4[u,u,u,u,u,u,u,u,10,11,6,7,4,5,6,7] +; AVX512F-FAST-NEXT: vpshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,6,4,6,7] +; AVX512F-FAST-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm2[4],xmm4[4],xmm2[5],xmm4[5],xmm2[6],xmm4[6],xmm2[7],xmm4[7] +; AVX512F-FAST-NEXT: vpblendd {{.*#+}} ymm0 = ymm2[0,1],ymm0[2,3,4,5,6,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm0[0],ymm1[1,2,3,4,5,6,7],ymm0[8],ymm1[9,10,11,12,13,14,15] +; AVX512F-FAST-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7] +; AVX512F-FAST-NEXT: vmovdqa %ymm3, (%rsi) +; AVX512F-FAST-NEXT: vmovdqa %ymm6, (%rdx) +; AVX512F-FAST-NEXT: vmovdqa %ymm8, (%rcx) +; AVX512F-FAST-NEXT: vmovdqa %ymm7, (%r8) +; AVX512F-FAST-NEXT: vmovdqa %ymm9, (%r9) +; AVX512F-FAST-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512F-FAST-NEXT: vmovdqa %ymm11, (%rax) +; AVX512F-FAST-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512F-FAST-NEXT: vmovdqa %ymm0, (%rax) +; AVX512F-FAST-NEXT: vzeroupper +; AVX512F-FAST-NEXT: retq ; ; AVX512BW-LABEL: load_i16_stride7_vf16: ; AVX512BW: # %bb.0: @@ -6874,13 +6723,13 @@ define void @load_i16_stride7_vf32(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, pt ; AVX512DQ-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [2,6,9,13,2,6,9,13] ; AVX512DQ-FAST-NEXT: # ymm1 = mem[0,1,0,1] ; AVX512DQ-FAST-NEXT: vmovdqa64 128(%rdi), %zmm24 -; AVX512DQ-FAST-NEXT: vbroadcasti64x2 {{.*#+}} ymm30 = [2,5,9,12,2,5,9,12] -; AVX512DQ-FAST-NEXT: # ymm30 = mem[0,1,0,1] +; AVX512DQ-FAST-NEXT: vbroadcasti32x4 {{.*#+}} ymm30 = [2,5,9,12,2,5,9,12] +; AVX512DQ-FAST-NEXT: # ymm30 = mem[0,1,2,3,0,1,2,3] ; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm2 = [10,3,6,15,12,13,6,15] ; AVX512DQ-FAST-NEXT: vpermd %zmm29, %zmm2, %zmm0 ; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vbroadcasti64x2 {{.*#+}} ymm21 = [3,6,10,13,3,6,10,13] -; AVX512DQ-FAST-NEXT: # ymm21 = mem[0,1,0,1] +; AVX512DQ-FAST-NEXT: vbroadcasti32x4 {{.*#+}} ymm21 = [3,6,10,13,3,6,10,13] +; AVX512DQ-FAST-NEXT: # ymm21 = mem[0,1,2,3,0,1,2,3] ; AVX512DQ-FAST-NEXT: vmovdqa64 384(%rdi), %zmm17 ; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} ymm19 = <1,u,u,u,5,8,12,15> ; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm2 = <2,6,9,u,13,u,u,u> @@ -15474,8 +15323,8 @@ define void @load_i16_stride7_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, pt ; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm26, %ymm2 ; AVX512DQ-FAST-NEXT: vpshufb %ymm0, %ymm2, %ymm2 ; AVX512DQ-FAST-NEXT: vmovdqa64 576(%rdi), %zmm18 -; AVX512DQ-FAST-NEXT: vbroadcasti64x2 {{.*#+}} ymm26 = [3,6,10,13,3,6,10,13] -; AVX512DQ-FAST-NEXT: # ymm26 = mem[0,1,0,1] +; AVX512DQ-FAST-NEXT: vbroadcasti32x4 {{.*#+}} ymm26 = [3,6,10,13,3,6,10,13] +; AVX512DQ-FAST-NEXT: # ymm26 = mem[0,1,2,3,0,1,2,3] ; AVX512DQ-FAST-NEXT: vpermd %zmm18, %zmm26, %zmm3 ; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm6 = <0,1,2,3,0,1,6,7,8,9,14,15,12,13,14,15,16,17,18,19,16,17,22,23,24,25,30,31,u,u,u,u> ; AVX512DQ-FAST-NEXT: vpshufb %ymm6, %ymm3, %ymm3 diff --git a/llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll b/llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll index e3d60d0a4dc1..c7fca67c75ae 100644 --- a/llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll +++ b/llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll @@ -8744,567 +8744,286 @@ define void @load_i16_stride8_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, pt ; AVX512F-FAST-NEXT: vzeroupper ; AVX512F-FAST-NEXT: retq ; -; AVX512BW-ONLY-LABEL: load_i16_stride8_vf64: -; AVX512BW-ONLY: # %bb.0: -; AVX512BW-ONLY-NEXT: subq $1096, %rsp # imm = 0x448 -; AVX512BW-ONLY-NEXT: vmovdqa64 704(%rdi), %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 640(%rdi), %zmm8 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 576(%rdi), %zmm28 -; AVX512BW-ONLY-NEXT: vmovdqa64 512(%rdi), %zmm11 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 832(%rdi), %zmm5 -; AVX512BW-ONLY-NEXT: vmovdqa64 768(%rdi), %zmm29 -; AVX512BW-ONLY-NEXT: vmovdqa64 960(%rdi), %zmm21 -; AVX512BW-ONLY-NEXT: vmovdqa64 896(%rdi), %zmm25 -; AVX512BW-ONLY-NEXT: vmovdqa64 (%rdi), %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%rdi), %zmm17 -; AVX512BW-ONLY-NEXT: vmovdqa64 128(%rdi), %zmm4 -; AVX512BW-ONLY-NEXT: vmovdqa64 192(%rdi), %zmm9 -; AVX512BW-ONLY-NEXT: vmovdqa64 320(%rdi), %zmm20 -; AVX512BW-ONLY-NEXT: vmovdqa64 256(%rdi), %zmm26 -; AVX512BW-ONLY-NEXT: vmovdqa64 448(%rdi), %zmm22 -; AVX512BW-ONLY-NEXT: vmovdqa64 384(%rdi), %zmm2 -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = [0,8,16,24,32,40,48,56,0,8,16,24,32,40,48,56,0,8,16,24,32,40,48,56,0,8,16,24,32,40,48,56] -; AVX512BW-ONLY-NEXT: # zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm12 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm22, %zmm0, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm20, %zmm0, %zmm2 -; AVX512BW-ONLY-NEXT: movb $-64, %al -; AVX512BW-ONLY-NEXT: kmovd %eax, %k1 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm1, %zmm2 {%k1} -; AVX512BW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [0,8,16,24,32,40,48,56,0,8,16,24,32,40,48,56] -; AVX512BW-ONLY-NEXT: # ymm1 = mem[0,1,0,1] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm10 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2w %zmm9, %zmm1, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm4 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm17, %zmm0, %zmm4 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm3 = ymm4[0,1,2,3],ymm3[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm3, %zmm2, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm21, %zmm0, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm5, %zmm0, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 {%k1} -; AVX512BW-ONLY-NEXT: vpermi2w %zmm28, %zmm11, %zmm0 -; AVX512BW-ONLY-NEXT: vpermi2w %zmm6, %zmm8, %zmm1 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm4 = [1,9,17,25,33,41,49,57,1,9,17,25,33,41,49,57,1,9,17,25,33,41,49,57,1,9,17,25,33,41,49,57] -; AVX512BW-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm22, %zmm4, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm1 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm20, %zmm4, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1} -; AVX512BW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [1,9,17,25,33,41,49,57,1,9,17,25,33,41,49,57] -; AVX512BW-ONLY-NEXT: # ymm2 = mem[0,1,0,1] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm9, %zmm2, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm17, %zmm4, %zmm2 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm2[0,1,2,3],ymm0[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm1, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = [2,10,18,26,34,42,50,58,2,10,18,26,34,42,50,58,2,10,18,26,34,42,50,58,2,10,18,26,34,42,50,58] -; AVX512BW-ONLY-NEXT: # zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm1 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm22, %zmm0, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm2 = [3,11,19,27,35,43,51,59,3,11,19,27,35,43,51,59,3,11,19,27,35,43,51,59,3,11,19,27,35,43,51,59] -; AVX512BW-ONLY-NEXT: # zmm2 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm1 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm22, %zmm2, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm10 = [4,12,20,28,36,44,52,60,4,12,20,28,36,44,52,60,4,12,20,28,36,44,52,60,4,12,20,28,36,44,52,60] -; AVX512BW-ONLY-NEXT: # zmm10 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm22, %zmm10, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm15 = [5,13,21,29,37,45,53,61,5,13,21,29,37,45,53,61,5,13,21,29,37,45,53,61,5,13,21,29,37,45,53,61] -; AVX512BW-ONLY-NEXT: # zmm15 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm1 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm22, %zmm15, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm13 = [6,14,22,30,38,46,54,62,6,14,22,30,38,46,54,62,6,14,22,30,38,46,54,62,6,14,22,30,38,46,54,62] -; AVX512BW-ONLY-NEXT: # zmm13 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm1 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm22, %zmm13, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm1 = [7,15,23,31,39,47,55,63,7,15,23,31,39,47,55,63,7,15,23,31,39,47,55,63,7,15,23,31,39,47,55,63] -; AVX512BW-ONLY-NEXT: # zmm1 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vpermt2w %zmm22, %zmm1, %zmm12 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm24 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm20, %zmm0, %zmm24 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm27 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm20, %zmm3, %zmm27 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm31 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm20, %zmm10, %zmm31 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm30 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm20, %zmm15, %zmm30 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm22 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm20, %zmm13, %zmm22 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm20, %zmm1, %zmm26 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm8 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm17, %zmm0, %zmm8 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm12 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm17, %zmm3, %zmm12 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm6 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm17, %zmm10, %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm6, (%rsp) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm6 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm17, %zmm15, %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm6 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm17, %zmm13, %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2w %zmm17, %zmm1, %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm18 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm21, %zmm4, %zmm18 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm19 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm21, %zmm0, %zmm19 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm23 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm6 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm21, %zmm3, %zmm23 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm16 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm21, %zmm10, %zmm16 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm20 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm21, %zmm15, %zmm20 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm17 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm21, %zmm13, %zmm17 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm21, %zmm1, %zmm25 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm9 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm5, %zmm4, %zmm9 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm11 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm5, %zmm0, %zmm11 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm14 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm5, %zmm6, %zmm14 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm21 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm5, %zmm10, %zmm21 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm15, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm5, %zmm15, %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm15 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm5, %zmm13, %zmm15 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm5, %zmm1, %zmm29 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermi2w %zmm28, %zmm0, %zmm4 -; AVX512BW-ONLY-NEXT: vpermi2w %zmm28, %zmm0, %zmm3 -; AVX512BW-ONLY-NEXT: vpermi2w %zmm28, %zmm0, %zmm6 -; AVX512BW-ONLY-NEXT: vpermi2w %zmm28, %zmm0, %zmm10 -; AVX512BW-ONLY-NEXT: vpermi2w %zmm28, %zmm0, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermi2w %zmm28, %zmm0, %zmm13 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm28, %zmm1, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm18, %zmm9 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm28 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm0 = [1,9,17,25,33,41,49,57,1,9,17,25,33,41,49,57] -; AVX512BW-ONLY-NEXT: # ymm0 = mem[0,1,0,1] -; AVX512BW-ONLY-NEXT: vpermi2w %zmm28, %zmm2, %zmm0 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm4[0,1,2,3],ymm0[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm9, %zmm18 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm24 {%k1} -; AVX512BW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm9 = [2,10,18,26,34,42,50,58,2,10,18,26,34,42,50,58] -; AVX512BW-ONLY-NEXT: # ymm9 = mem[0,1,0,1] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2w %zmm5, %zmm9, %zmm0 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm8[0,1,2,3],ymm0[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm24, %zmm24 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm19, %zmm11 {%k1} -; AVX512BW-ONLY-NEXT: vpermi2w %zmm28, %zmm2, %zmm9 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm1 = ymm3[0,1,2,3],ymm9[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm11, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm27 {%k1} -; AVX512BW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [3,11,19,27,35,43,51,59,3,11,19,27,35,43,51,59] -; AVX512BW-ONLY-NEXT: # ymm3 = mem[0,1,0,1] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm9 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm5, %zmm3, %zmm9 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm4 = ymm12[0,1,2,3],ymm9[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm27, %zmm4 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm14 {%k1} -; AVX512BW-ONLY-NEXT: vpermi2w %zmm28, %zmm2, %zmm3 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm3 = ymm6[0,1,2,3],ymm3[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm3, %zmm14, %zmm3 -; AVX512BW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm6 = [4,12,20,28,36,44,52,60,4,12,20,28,36,44,52,60] -; AVX512BW-ONLY-NEXT: # ymm6 = mem[0,1,0,1] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm8 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm5, %zmm6, %zmm8 -; AVX512BW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm9 = [5,13,21,29,37,45,53,61,5,13,21,29,37,45,53,61] -; AVX512BW-ONLY-NEXT: # ymm9 = mem[0,1,0,1] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm11 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm5, %zmm9, %zmm11 -; AVX512BW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm12 = [6,14,22,30,38,46,54,62,6,14,22,30,38,46,54,62] -; AVX512BW-ONLY-NEXT: # ymm12 = mem[0,1,0,1] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm14 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm5, %zmm12, %zmm14 -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} ymm19 = [7,15,23,31,39,47,55,63,7,15,23,31,39,47,55,63] -; AVX512BW-ONLY-NEXT: # ymm19 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vpermt2w %zmm5, %zmm19, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm5 -; AVX512BW-ONLY-NEXT: vpermi2w %zmm28, %zmm2, %zmm6 -; AVX512BW-ONLY-NEXT: vpermi2w %zmm28, %zmm2, %zmm9 -; AVX512BW-ONLY-NEXT: vpermi2w %zmm28, %zmm2, %zmm12 -; AVX512BW-ONLY-NEXT: vpermt2w %zmm28, %zmm19, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm0 -; AVX512BW-ONLY-NEXT: vpblendd $15, (%rsp), %ymm8, %ymm8 # 32-byte Folded Reload -; AVX512BW-ONLY-NEXT: # ymm8 = mem[0,1,2,3],ymm8[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm31 {%k1} -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm8, %zmm31, %zmm8 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm6 = ymm10[0,1,2,3],ymm6[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm16, %zmm21 {%k1} -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm6, %zmm21, %zmm6 -; AVX512BW-ONLY-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm11, %ymm10 # 32-byte Folded Reload -; AVX512BW-ONLY-NEXT: # ymm10 = mem[0,1,2,3],ymm11[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm30 {%k1} -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm30, %zmm10 -; AVX512BW-ONLY-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm9, %ymm9 # 32-byte Folded Reload -; AVX512BW-ONLY-NEXT: # ymm9 = mem[0,1,2,3],ymm9[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm20, %zmm7 {%k1} -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm9, %zmm7, %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm22 {%k1} -; AVX512BW-ONLY-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm14, %ymm9 # 32-byte Folded Reload -; AVX512BW-ONLY-NEXT: # ymm9 = mem[0,1,2,3],ymm14[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm9, %zmm22, %zmm9 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm17, %zmm15 {%k1} -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm2 = ymm13[0,1,2,3],ymm12[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm15, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm26 {%k1} -; AVX512BW-ONLY-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm5, %ymm11 # 32-byte Folded Reload -; AVX512BW-ONLY-NEXT: # ymm11 = mem[0,1,2,3],ymm5[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm11, %zmm26, %zmm5 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm29 {%k1} -; AVX512BW-ONLY-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm11 # 32-byte Folded Reload -; AVX512BW-ONLY-NEXT: # ymm11 = mem[0,1,2,3],ymm0[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm11, %zmm29, %zmm11 -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 64(%rsi) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, (%rsi) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm18, 64(%rdx) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, (%rdx) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm1, 64(%rcx) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm24, (%rcx) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm3, 64(%r8) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, (%r8) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm6, 64(%r9) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm8, (%r9) -; AVX512BW-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, 64(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, (%rax) -; AVX512BW-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, 64(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm9, (%rax) -; AVX512BW-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm11, 64(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, (%rax) -; AVX512BW-ONLY-NEXT: addq $1096, %rsp # imm = 0x448 -; AVX512BW-ONLY-NEXT: vzeroupper -; AVX512BW-ONLY-NEXT: retq -; -; AVX512DQBW-ONLY-LABEL: load_i16_stride8_vf64: -; AVX512DQBW-ONLY: # %bb.0: -; AVX512DQBW-ONLY-NEXT: subq $1096, %rsp # imm = 0x448 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 704(%rdi), %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 640(%rdi), %zmm8 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 576(%rdi), %zmm28 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 512(%rdi), %zmm11 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 832(%rdi), %zmm5 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 768(%rdi), %zmm29 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 960(%rdi), %zmm21 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 896(%rdi), %zmm25 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 (%rdi), %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%rdi), %zmm17 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 128(%rdi), %zmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 192(%rdi), %zmm9 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 320(%rdi), %zmm20 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 256(%rdi), %zmm26 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 448(%rdi), %zmm22 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 384(%rdi), %zmm2 -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = [0,8,16,24,32,40,48,56,0,8,16,24,32,40,48,56,0,8,16,24,32,40,48,56,0,8,16,24,32,40,48,56] -; AVX512DQBW-ONLY-NEXT: # zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm12 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm22, %zmm0, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm20, %zmm0, %zmm2 -; AVX512DQBW-ONLY-NEXT: movb $-64, %al -; AVX512DQBW-ONLY-NEXT: kmovd %eax, %k1 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm1, %zmm2 {%k1} -; AVX512DQBW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [0,8,16,24,32,40,48,56,0,8,16,24,32,40,48,56] -; AVX512DQBW-ONLY-NEXT: # ymm1 = mem[0,1,0,1] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm10 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm9, %zmm1, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm4 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm17, %zmm0, %zmm4 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm3 = ymm4[0,1,2,3],ymm3[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm3, %zmm2, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm21, %zmm0, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm5, %zmm0, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 {%k1} -; AVX512DQBW-ONLY-NEXT: vpermi2w %zmm28, %zmm11, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermi2w %zmm6, %zmm8, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm4 = [1,9,17,25,33,41,49,57,1,9,17,25,33,41,49,57,1,9,17,25,33,41,49,57,1,9,17,25,33,41,49,57] -; AVX512DQBW-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm22, %zmm4, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm20, %zmm4, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1} -; AVX512DQBW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [1,9,17,25,33,41,49,57,1,9,17,25,33,41,49,57] -; AVX512DQBW-ONLY-NEXT: # ymm2 = mem[0,1,0,1] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm9, %zmm2, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm17, %zmm4, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm2[0,1,2,3],ymm0[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm1, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = [2,10,18,26,34,42,50,58,2,10,18,26,34,42,50,58,2,10,18,26,34,42,50,58,2,10,18,26,34,42,50,58] -; AVX512DQBW-ONLY-NEXT: # zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm22, %zmm0, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm2 = [3,11,19,27,35,43,51,59,3,11,19,27,35,43,51,59,3,11,19,27,35,43,51,59,3,11,19,27,35,43,51,59] -; AVX512DQBW-ONLY-NEXT: # zmm2 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm22, %zmm2, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm10 = [4,12,20,28,36,44,52,60,4,12,20,28,36,44,52,60,4,12,20,28,36,44,52,60,4,12,20,28,36,44,52,60] -; AVX512DQBW-ONLY-NEXT: # zmm10 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm22, %zmm10, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm15 = [5,13,21,29,37,45,53,61,5,13,21,29,37,45,53,61,5,13,21,29,37,45,53,61,5,13,21,29,37,45,53,61] -; AVX512DQBW-ONLY-NEXT: # zmm15 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm22, %zmm15, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm13 = [6,14,22,30,38,46,54,62,6,14,22,30,38,46,54,62,6,14,22,30,38,46,54,62,6,14,22,30,38,46,54,62] -; AVX512DQBW-ONLY-NEXT: # zmm13 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm22, %zmm13, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm1 = [7,15,23,31,39,47,55,63,7,15,23,31,39,47,55,63,7,15,23,31,39,47,55,63,7,15,23,31,39,47,55,63] -; AVX512DQBW-ONLY-NEXT: # zmm1 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm22, %zmm1, %zmm12 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm24 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm20, %zmm0, %zmm24 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm27 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm20, %zmm3, %zmm27 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm31 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm20, %zmm10, %zmm31 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm30 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm20, %zmm15, %zmm30 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm22 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm20, %zmm13, %zmm22 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm20, %zmm1, %zmm26 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm17, %zmm0, %zmm8 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm12 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm17, %zmm3, %zmm12 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm17, %zmm10, %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm6, (%rsp) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm17, %zmm15, %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm17, %zmm13, %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm17, %zmm1, %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm18 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm21, %zmm4, %zmm18 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm19 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm21, %zmm0, %zmm19 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm23 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm21, %zmm3, %zmm23 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm16 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm21, %zmm10, %zmm16 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm20 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm21, %zmm15, %zmm20 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm17 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm21, %zmm13, %zmm17 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm21, %zmm1, %zmm25 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm9 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm5, %zmm4, %zmm9 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm11 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm5, %zmm0, %zmm11 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm14 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm5, %zmm6, %zmm14 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm21 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm5, %zmm10, %zmm21 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm15, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm5, %zmm15, %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm15 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm5, %zmm13, %zmm15 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm5, %zmm1, %zmm29 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermi2w %zmm28, %zmm0, %zmm4 -; AVX512DQBW-ONLY-NEXT: vpermi2w %zmm28, %zmm0, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermi2w %zmm28, %zmm0, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpermi2w %zmm28, %zmm0, %zmm10 -; AVX512DQBW-ONLY-NEXT: vpermi2w %zmm28, %zmm0, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermi2w %zmm28, %zmm0, %zmm13 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm28, %zmm1, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm18, %zmm9 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm28 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm0 = [1,9,17,25,33,41,49,57,1,9,17,25,33,41,49,57] -; AVX512DQBW-ONLY-NEXT: # ymm0 = mem[0,1,0,1] -; AVX512DQBW-ONLY-NEXT: vpermi2w %zmm28, %zmm2, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm4[0,1,2,3],ymm0[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm9, %zmm18 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm24 {%k1} -; AVX512DQBW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm9 = [2,10,18,26,34,42,50,58,2,10,18,26,34,42,50,58] -; AVX512DQBW-ONLY-NEXT: # ymm9 = mem[0,1,0,1] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm5, %zmm9, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm8[0,1,2,3],ymm0[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm24, %zmm24 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm19, %zmm11 {%k1} -; AVX512DQBW-ONLY-NEXT: vpermi2w %zmm28, %zmm2, %zmm9 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm1 = ymm3[0,1,2,3],ymm9[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm11, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm27 {%k1} -; AVX512DQBW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [3,11,19,27,35,43,51,59,3,11,19,27,35,43,51,59] -; AVX512DQBW-ONLY-NEXT: # ymm3 = mem[0,1,0,1] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm9 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm5, %zmm3, %zmm9 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm4 = ymm12[0,1,2,3],ymm9[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm27, %zmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm14 {%k1} -; AVX512DQBW-ONLY-NEXT: vpermi2w %zmm28, %zmm2, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm3 = ymm6[0,1,2,3],ymm3[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm3, %zmm14, %zmm3 -; AVX512DQBW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm6 = [4,12,20,28,36,44,52,60,4,12,20,28,36,44,52,60] -; AVX512DQBW-ONLY-NEXT: # ymm6 = mem[0,1,0,1] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm5, %zmm6, %zmm8 -; AVX512DQBW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm9 = [5,13,21,29,37,45,53,61,5,13,21,29,37,45,53,61] -; AVX512DQBW-ONLY-NEXT: # ymm9 = mem[0,1,0,1] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm11 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm5, %zmm9, %zmm11 -; AVX512DQBW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm12 = [6,14,22,30,38,46,54,62,6,14,22,30,38,46,54,62] -; AVX512DQBW-ONLY-NEXT: # ymm12 = mem[0,1,0,1] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm14 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm5, %zmm12, %zmm14 -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x2 {{.*#+}} ymm19 = [7,15,23,31,39,47,55,63,7,15,23,31,39,47,55,63] -; AVX512DQBW-ONLY-NEXT: # ymm19 = mem[0,1,0,1] -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm5, %zmm19, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm5 -; AVX512DQBW-ONLY-NEXT: vpermi2w %zmm28, %zmm2, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpermi2w %zmm28, %zmm2, %zmm9 -; AVX512DQBW-ONLY-NEXT: vpermi2w %zmm28, %zmm2, %zmm12 -; AVX512DQBW-ONLY-NEXT: vpermt2w %zmm28, %zmm19, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpblendd $15, (%rsp), %ymm8, %ymm8 # 32-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # ymm8 = mem[0,1,2,3],ymm8[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm31 {%k1} -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm8, %zmm31, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm6 = ymm10[0,1,2,3],ymm6[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm16, %zmm21 {%k1} -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm6, %zmm21, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm11, %ymm10 # 32-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # ymm10 = mem[0,1,2,3],ymm11[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm30 {%k1} -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm30, %zmm10 -; AVX512DQBW-ONLY-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm9, %ymm9 # 32-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # ymm9 = mem[0,1,2,3],ymm9[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm20, %zmm7 {%k1} -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm9, %zmm7, %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm22 {%k1} -; AVX512DQBW-ONLY-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm14, %ymm9 # 32-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # ymm9 = mem[0,1,2,3],ymm14[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm9, %zmm22, %zmm9 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm17, %zmm15 {%k1} -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm2 = ymm13[0,1,2,3],ymm12[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm15, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm26 {%k1} -; AVX512DQBW-ONLY-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm5, %ymm11 # 32-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # ymm11 = mem[0,1,2,3],ymm5[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm11, %zmm26, %zmm5 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm29 {%k1} -; AVX512DQBW-ONLY-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm11 # 32-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # ymm11 = mem[0,1,2,3],ymm0[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm11, %zmm29, %zmm11 -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 64(%rsi) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, (%rsi) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm18, 64(%rdx) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, (%rdx) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm1, 64(%rcx) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm24, (%rcx) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm3, 64(%r8) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, (%r8) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm6, 64(%r9) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm8, (%r9) -; AVX512DQBW-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, 64(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, (%rax) -; AVX512DQBW-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, 64(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm9, (%rax) -; AVX512DQBW-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm11, 64(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, (%rax) -; AVX512DQBW-ONLY-NEXT: addq $1096, %rsp # imm = 0x448 -; AVX512DQBW-ONLY-NEXT: vzeroupper -; AVX512DQBW-ONLY-NEXT: retq +; AVX512BW-LABEL: load_i16_stride8_vf64: +; AVX512BW: # %bb.0: +; AVX512BW-NEXT: subq $1096, %rsp # imm = 0x448 +; AVX512BW-NEXT: vmovdqa64 704(%rdi), %zmm6 +; AVX512BW-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 640(%rdi), %zmm8 +; AVX512BW-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 576(%rdi), %zmm28 +; AVX512BW-NEXT: vmovdqa64 512(%rdi), %zmm11 +; AVX512BW-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 832(%rdi), %zmm5 +; AVX512BW-NEXT: vmovdqa64 768(%rdi), %zmm29 +; AVX512BW-NEXT: vmovdqa64 960(%rdi), %zmm21 +; AVX512BW-NEXT: vmovdqa64 896(%rdi), %zmm25 +; AVX512BW-NEXT: vmovdqa64 (%rdi), %zmm7 +; AVX512BW-NEXT: vmovdqa64 64(%rdi), %zmm17 +; AVX512BW-NEXT: vmovdqa64 128(%rdi), %zmm4 +; AVX512BW-NEXT: vmovdqa64 192(%rdi), %zmm9 +; AVX512BW-NEXT: vmovdqa64 320(%rdi), %zmm20 +; AVX512BW-NEXT: vmovdqa64 256(%rdi), %zmm26 +; AVX512BW-NEXT: vmovdqa64 448(%rdi), %zmm22 +; AVX512BW-NEXT: vmovdqa64 384(%rdi), %zmm2 +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = [0,8,16,24,32,40,48,56,0,8,16,24,32,40,48,56,0,8,16,24,32,40,48,56,0,8,16,24,32,40,48,56] +; AVX512BW-NEXT: # zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm1 +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm12 +; AVX512BW-NEXT: vpermt2w %zmm22, %zmm0, %zmm1 +; AVX512BW-NEXT: vmovdqa64 %zmm26, %zmm2 +; AVX512BW-NEXT: vpermt2w %zmm20, %zmm0, %zmm2 +; AVX512BW-NEXT: movb $-64, %al +; AVX512BW-NEXT: kmovd %eax, %k1 +; AVX512BW-NEXT: vmovdqa64 %zmm1, %zmm2 {%k1} +; AVX512BW-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [0,8,16,24,32,40,48,56,0,8,16,24,32,40,48,56] +; AVX512BW-NEXT: # ymm1 = mem[0,1,0,1] +; AVX512BW-NEXT: vmovdqa64 %zmm4, %zmm3 +; AVX512BW-NEXT: vmovdqa64 %zmm4, %zmm10 +; AVX512BW-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2w %zmm9, %zmm1, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm4 +; AVX512BW-NEXT: vpermt2w %zmm17, %zmm0, %zmm4 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm3 = ymm4[0,1,2,3],ymm3[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm3, %zmm2, %zmm2 +; AVX512BW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm25, %zmm2 +; AVX512BW-NEXT: vpermt2w %zmm21, %zmm0, %zmm2 +; AVX512BW-NEXT: vmovdqa64 %zmm29, %zmm3 +; AVX512BW-NEXT: vpermt2w %zmm5, %zmm0, %zmm3 +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm3 {%k1} +; AVX512BW-NEXT: vpermi2w %zmm28, %zmm11, %zmm0 +; AVX512BW-NEXT: vpermi2w %zmm6, %zmm8, %zmm1 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm4 = [1,9,17,25,33,41,49,57,1,9,17,25,33,41,49,57,1,9,17,25,33,41,49,57,1,9,17,25,33,41,49,57] +; AVX512BW-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm12, %zmm0 +; AVX512BW-NEXT: vpermt2w %zmm22, %zmm4, %zmm0 +; AVX512BW-NEXT: vmovdqa64 %zmm26, %zmm1 +; AVX512BW-NEXT: vpermt2w %zmm20, %zmm4, %zmm1 +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1} +; AVX512BW-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [1,9,17,25,33,41,49,57,1,9,17,25,33,41,49,57] +; AVX512BW-NEXT: # ymm2 = mem[0,1,0,1] +; AVX512BW-NEXT: vmovdqa64 %zmm10, %zmm0 +; AVX512BW-NEXT: vpermt2w %zmm9, %zmm2, %zmm0 +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm2 +; AVX512BW-NEXT: vpermt2w %zmm17, %zmm4, %zmm2 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm0 = ymm2[0,1,2,3],ymm0[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm1, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = [2,10,18,26,34,42,50,58,2,10,18,26,34,42,50,58,2,10,18,26,34,42,50,58,2,10,18,26,34,42,50,58] +; AVX512BW-NEXT: # zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm12, %zmm1 +; AVX512BW-NEXT: vpermt2w %zmm22, %zmm0, %zmm1 +; AVX512BW-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm2 = [3,11,19,27,35,43,51,59,3,11,19,27,35,43,51,59,3,11,19,27,35,43,51,59,3,11,19,27,35,43,51,59] +; AVX512BW-NEXT: # zmm2 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm12, %zmm1 +; AVX512BW-NEXT: vpermt2w %zmm22, %zmm2, %zmm1 +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm10 = [4,12,20,28,36,44,52,60,4,12,20,28,36,44,52,60,4,12,20,28,36,44,52,60,4,12,20,28,36,44,52,60] +; AVX512BW-NEXT: # zmm10 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm12, %zmm2 +; AVX512BW-NEXT: vpermt2w %zmm22, %zmm10, %zmm2 +; AVX512BW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm15 = [5,13,21,29,37,45,53,61,5,13,21,29,37,45,53,61,5,13,21,29,37,45,53,61,5,13,21,29,37,45,53,61] +; AVX512BW-NEXT: # zmm15 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm12, %zmm1 +; AVX512BW-NEXT: vpermt2w %zmm22, %zmm15, %zmm1 +; AVX512BW-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm13 = [6,14,22,30,38,46,54,62,6,14,22,30,38,46,54,62,6,14,22,30,38,46,54,62,6,14,22,30,38,46,54,62] +; AVX512BW-NEXT: # zmm13 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm12, %zmm1 +; AVX512BW-NEXT: vpermt2w %zmm22, %zmm13, %zmm1 +; AVX512BW-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm1 = [7,15,23,31,39,47,55,63,7,15,23,31,39,47,55,63,7,15,23,31,39,47,55,63,7,15,23,31,39,47,55,63] +; AVX512BW-NEXT: # zmm1 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vpermt2w %zmm22, %zmm1, %zmm12 +; AVX512BW-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm26, %zmm24 +; AVX512BW-NEXT: vpermt2w %zmm20, %zmm0, %zmm24 +; AVX512BW-NEXT: vmovdqa64 %zmm26, %zmm27 +; AVX512BW-NEXT: vpermt2w %zmm20, %zmm3, %zmm27 +; AVX512BW-NEXT: vmovdqa64 %zmm26, %zmm31 +; AVX512BW-NEXT: vpermt2w %zmm20, %zmm10, %zmm31 +; AVX512BW-NEXT: vmovdqa64 %zmm26, %zmm30 +; AVX512BW-NEXT: vpermt2w %zmm20, %zmm15, %zmm30 +; AVX512BW-NEXT: vmovdqa64 %zmm26, %zmm22 +; AVX512BW-NEXT: vpermt2w %zmm20, %zmm13, %zmm22 +; AVX512BW-NEXT: vpermt2w %zmm20, %zmm1, %zmm26 +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm8 +; AVX512BW-NEXT: vpermt2w %zmm17, %zmm0, %zmm8 +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm12 +; AVX512BW-NEXT: vpermt2w %zmm17, %zmm3, %zmm12 +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm6 +; AVX512BW-NEXT: vpermt2w %zmm17, %zmm10, %zmm6 +; AVX512BW-NEXT: vmovdqu64 %zmm6, (%rsp) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm6 +; AVX512BW-NEXT: vpermt2w %zmm17, %zmm15, %zmm6 +; AVX512BW-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm6 +; AVX512BW-NEXT: vpermt2w %zmm17, %zmm13, %zmm6 +; AVX512BW-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2w %zmm17, %zmm1, %zmm7 +; AVX512BW-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm25, %zmm18 +; AVX512BW-NEXT: vpermt2w %zmm21, %zmm4, %zmm18 +; AVX512BW-NEXT: vmovdqa64 %zmm25, %zmm19 +; AVX512BW-NEXT: vpermt2w %zmm21, %zmm0, %zmm19 +; AVX512BW-NEXT: vmovdqa64 %zmm25, %zmm23 +; AVX512BW-NEXT: vmovdqa64 %zmm3, %zmm6 +; AVX512BW-NEXT: vpermt2w %zmm21, %zmm3, %zmm23 +; AVX512BW-NEXT: vmovdqa64 %zmm25, %zmm16 +; AVX512BW-NEXT: vpermt2w %zmm21, %zmm10, %zmm16 +; AVX512BW-NEXT: vmovdqa64 %zmm25, %zmm20 +; AVX512BW-NEXT: vpermt2w %zmm21, %zmm15, %zmm20 +; AVX512BW-NEXT: vmovdqa64 %zmm25, %zmm17 +; AVX512BW-NEXT: vpermt2w %zmm21, %zmm13, %zmm17 +; AVX512BW-NEXT: vpermt2w %zmm21, %zmm1, %zmm25 +; AVX512BW-NEXT: vmovdqa64 %zmm29, %zmm9 +; AVX512BW-NEXT: vpermt2w %zmm5, %zmm4, %zmm9 +; AVX512BW-NEXT: vmovdqa64 %zmm29, %zmm11 +; AVX512BW-NEXT: vpermt2w %zmm5, %zmm0, %zmm11 +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm3 +; AVX512BW-NEXT: vmovdqa64 %zmm29, %zmm14 +; AVX512BW-NEXT: vpermt2w %zmm5, %zmm6, %zmm14 +; AVX512BW-NEXT: vmovdqa64 %zmm29, %zmm21 +; AVX512BW-NEXT: vpermt2w %zmm5, %zmm10, %zmm21 +; AVX512BW-NEXT: vmovdqa64 %zmm29, %zmm7 +; AVX512BW-NEXT: vmovdqa64 %zmm15, %zmm2 +; AVX512BW-NEXT: vpermt2w %zmm5, %zmm15, %zmm7 +; AVX512BW-NEXT: vmovdqa64 %zmm29, %zmm15 +; AVX512BW-NEXT: vpermt2w %zmm5, %zmm13, %zmm15 +; AVX512BW-NEXT: vpermt2w %zmm5, %zmm1, %zmm29 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vpermi2w %zmm28, %zmm0, %zmm4 +; AVX512BW-NEXT: vpermi2w %zmm28, %zmm0, %zmm3 +; AVX512BW-NEXT: vpermi2w %zmm28, %zmm0, %zmm6 +; AVX512BW-NEXT: vpermi2w %zmm28, %zmm0, %zmm10 +; AVX512BW-NEXT: vpermi2w %zmm28, %zmm0, %zmm2 +; AVX512BW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermi2w %zmm28, %zmm0, %zmm13 +; AVX512BW-NEXT: vpermt2w %zmm28, %zmm1, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm18, %zmm9 {%k1} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm28 # 64-byte Reload +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512BW-NEXT: vbroadcasti128 {{.*#+}} ymm0 = [1,9,17,25,33,41,49,57,1,9,17,25,33,41,49,57] +; AVX512BW-NEXT: # ymm0 = mem[0,1,0,1] +; AVX512BW-NEXT: vpermi2w %zmm28, %zmm2, %zmm0 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm0 = ymm4[0,1,2,3],ymm0[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm9, %zmm18 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm24 {%k1} +; AVX512BW-NEXT: vbroadcasti128 {{.*#+}} ymm9 = [2,10,18,26,34,42,50,58,2,10,18,26,34,42,50,58] +; AVX512BW-NEXT: # ymm9 = mem[0,1,0,1] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm4, %zmm0 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vpermt2w %zmm5, %zmm9, %zmm0 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm0 = ymm8[0,1,2,3],ymm0[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm24, %zmm24 +; AVX512BW-NEXT: vmovdqa64 %zmm19, %zmm11 {%k1} +; AVX512BW-NEXT: vpermi2w %zmm28, %zmm2, %zmm9 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm1 = ymm3[0,1,2,3],ymm9[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm1, %zmm11, %zmm1 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm27 {%k1} +; AVX512BW-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [3,11,19,27,35,43,51,59,3,11,19,27,35,43,51,59] +; AVX512BW-NEXT: # ymm3 = mem[0,1,0,1] +; AVX512BW-NEXT: vmovdqa64 %zmm4, %zmm0 +; AVX512BW-NEXT: vmovdqa64 %zmm4, %zmm9 +; AVX512BW-NEXT: vpermt2w %zmm5, %zmm3, %zmm9 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm4 = ymm12[0,1,2,3],ymm9[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm4, %zmm27, %zmm4 +; AVX512BW-NEXT: vmovdqa64 %zmm23, %zmm14 {%k1} +; AVX512BW-NEXT: vpermi2w %zmm28, %zmm2, %zmm3 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm3 = ymm6[0,1,2,3],ymm3[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm3, %zmm14, %zmm3 +; AVX512BW-NEXT: vbroadcasti128 {{.*#+}} ymm6 = [4,12,20,28,36,44,52,60,4,12,20,28,36,44,52,60] +; AVX512BW-NEXT: # ymm6 = mem[0,1,0,1] +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm8 +; AVX512BW-NEXT: vpermt2w %zmm5, %zmm6, %zmm8 +; AVX512BW-NEXT: vbroadcasti128 {{.*#+}} ymm9 = [5,13,21,29,37,45,53,61,5,13,21,29,37,45,53,61] +; AVX512BW-NEXT: # ymm9 = mem[0,1,0,1] +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm11 +; AVX512BW-NEXT: vpermt2w %zmm5, %zmm9, %zmm11 +; AVX512BW-NEXT: vbroadcasti128 {{.*#+}} ymm12 = [6,14,22,30,38,46,54,62,6,14,22,30,38,46,54,62] +; AVX512BW-NEXT: # ymm12 = mem[0,1,0,1] +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm14 +; AVX512BW-NEXT: vpermt2w %zmm5, %zmm12, %zmm14 +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} ymm19 = [7,15,23,31,39,47,55,63,7,15,23,31,39,47,55,63] +; AVX512BW-NEXT: # ymm19 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vpermt2w %zmm5, %zmm19, %zmm0 +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm5 +; AVX512BW-NEXT: vpermi2w %zmm28, %zmm2, %zmm6 +; AVX512BW-NEXT: vpermi2w %zmm28, %zmm2, %zmm9 +; AVX512BW-NEXT: vpermi2w %zmm28, %zmm2, %zmm12 +; AVX512BW-NEXT: vpermt2w %zmm28, %zmm19, %zmm2 +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm0 +; AVX512BW-NEXT: vpblendd $15, (%rsp), %ymm8, %ymm8 # 32-byte Folded Reload +; AVX512BW-NEXT: # ymm8 = mem[0,1,2,3],ymm8[4,5,6,7] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm31 {%k1} +; AVX512BW-NEXT: vinserti64x4 $0, %ymm8, %zmm31, %zmm8 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm6 = ymm10[0,1,2,3],ymm6[4,5,6,7] +; AVX512BW-NEXT: vmovdqa64 %zmm16, %zmm21 {%k1} +; AVX512BW-NEXT: vinserti64x4 $0, %ymm6, %zmm21, %zmm6 +; AVX512BW-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm11, %ymm10 # 32-byte Folded Reload +; AVX512BW-NEXT: # ymm10 = mem[0,1,2,3],ymm11[4,5,6,7] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm30 {%k1} +; AVX512BW-NEXT: vinserti64x4 $0, %ymm10, %zmm30, %zmm10 +; AVX512BW-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm9, %ymm9 # 32-byte Folded Reload +; AVX512BW-NEXT: # ymm9 = mem[0,1,2,3],ymm9[4,5,6,7] +; AVX512BW-NEXT: vmovdqa64 %zmm20, %zmm7 {%k1} +; AVX512BW-NEXT: vinserti64x4 $0, %ymm9, %zmm7, %zmm7 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm22 {%k1} +; AVX512BW-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm14, %ymm9 # 32-byte Folded Reload +; AVX512BW-NEXT: # ymm9 = mem[0,1,2,3],ymm14[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm9, %zmm22, %zmm9 +; AVX512BW-NEXT: vmovdqa64 %zmm17, %zmm15 {%k1} +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm2 = ymm13[0,1,2,3],ymm12[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm2, %zmm15, %zmm2 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm11, %zmm26 {%k1} +; AVX512BW-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm5, %ymm11 # 32-byte Folded Reload +; AVX512BW-NEXT: # ymm11 = mem[0,1,2,3],ymm5[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm11, %zmm26, %zmm5 +; AVX512BW-NEXT: vmovdqa64 %zmm25, %zmm29 {%k1} +; AVX512BW-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm11 # 32-byte Folded Reload +; AVX512BW-NEXT: # ymm11 = mem[0,1,2,3],ymm0[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm11, %zmm29, %zmm11 +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 64(%rsi) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, (%rsi) +; AVX512BW-NEXT: vmovdqa64 %zmm18, 64(%rdx) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, (%rdx) +; AVX512BW-NEXT: vmovdqa64 %zmm1, 64(%rcx) +; AVX512BW-NEXT: vmovdqa64 %zmm24, (%rcx) +; AVX512BW-NEXT: vmovdqa64 %zmm3, 64(%r8) +; AVX512BW-NEXT: vmovdqa64 %zmm4, (%r8) +; AVX512BW-NEXT: vmovdqa64 %zmm6, 64(%r9) +; AVX512BW-NEXT: vmovdqa64 %zmm8, (%r9) +; AVX512BW-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512BW-NEXT: vmovdqa64 %zmm7, 64(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm10, (%rax) +; AVX512BW-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512BW-NEXT: vmovdqa64 %zmm2, 64(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm9, (%rax) +; AVX512BW-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512BW-NEXT: vmovdqa64 %zmm11, 64(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm5, (%rax) +; AVX512BW-NEXT: addq $1096, %rsp # imm = 0x448 +; AVX512BW-NEXT: vzeroupper +; AVX512BW-NEXT: retq %wide.vec = load <512 x i16>, ptr %in.vec, align 64 %strided.vec0 = shufflevector <512 x i16> %wide.vec, <512 x i16> poison, <64 x i32> %strided.vec1 = shufflevector <512 x i16> %wide.vec, <512 x i16> poison, <64 x i32> @@ -9334,6 +9053,7 @@ define void @load_i16_stride8_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, pt ; AVX512-FAST: {{.*}} ; AVX512-SLOW: {{.*}} ; AVX512BW-FAST: {{.*}} +; AVX512BW-ONLY: {{.*}} ; AVX512BW-ONLY-FAST: {{.*}} ; AVX512BW-ONLY-SLOW: {{.*}} ; AVX512BW-SLOW: {{.*}} @@ -9341,6 +9061,7 @@ define void @load_i16_stride8_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, pt ; AVX512DQ-ONLY: {{.*}} ; AVX512DQ-SLOW: {{.*}} ; AVX512DQBW-FAST: {{.*}} +; AVX512DQBW-ONLY: {{.*}} ; AVX512DQBW-SLOW: {{.*}} ; AVX512F: {{.*}} ; AVX512F-ONLY: {{.*}} diff --git a/llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-8.ll b/llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-8.ll index 794356f8bc27..1bd7025307d2 100644 --- a/llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-8.ll +++ b/llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-8.ll @@ -3687,1129 +3687,567 @@ define void @load_i32_stride8_vf32(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, pt ; AVX2-ONLY-NEXT: vzeroupper ; AVX2-ONLY-NEXT: retq ; -; AVX512F-ONLY-LABEL: load_i32_stride8_vf32: -; AVX512F-ONLY: # %bb.0: -; AVX512F-ONLY-NEXT: subq $1096, %rsp # imm = 0x448 -; AVX512F-ONLY-NEXT: vmovdqa64 704(%rdi), %zmm6 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 640(%rdi), %zmm8 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 576(%rdi), %zmm28 -; AVX512F-ONLY-NEXT: vmovdqa64 512(%rdi), %zmm11 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 832(%rdi), %zmm5 -; AVX512F-ONLY-NEXT: vmovdqa64 768(%rdi), %zmm29 -; AVX512F-ONLY-NEXT: vmovdqa64 960(%rdi), %zmm21 -; AVX512F-ONLY-NEXT: vmovdqa64 896(%rdi), %zmm25 -; AVX512F-ONLY-NEXT: vmovdqa64 (%rdi), %zmm7 -; AVX512F-ONLY-NEXT: vmovdqa64 64(%rdi), %zmm17 -; AVX512F-ONLY-NEXT: vmovdqa64 128(%rdi), %zmm4 -; AVX512F-ONLY-NEXT: vmovdqa64 192(%rdi), %zmm9 -; AVX512F-ONLY-NEXT: vmovdqa64 320(%rdi), %zmm20 -; AVX512F-ONLY-NEXT: vmovdqa64 256(%rdi), %zmm26 -; AVX512F-ONLY-NEXT: vmovdqa64 448(%rdi), %zmm22 -; AVX512F-ONLY-NEXT: vmovdqa64 384(%rdi), %zmm2 -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = [0,8,16,24,0,8,16,24,0,8,16,24,0,8,16,24] -; AVX512F-ONLY-NEXT: # zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm1 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm12 -; AVX512F-ONLY-NEXT: vpermt2d %zmm22, %zmm0, %zmm1 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm26, %zmm2 -; AVX512F-ONLY-NEXT: vpermt2d %zmm20, %zmm0, %zmm2 -; AVX512F-ONLY-NEXT: movb $-64, %al -; AVX512F-ONLY-NEXT: kmovw %eax, %k1 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm1, %zmm2 {%k1} -; AVX512F-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [0,8,16,24,0,8,16,24] -; AVX512F-ONLY-NEXT: # ymm1 = mem[0,1,0,1] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm10 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2d %zmm9, %zmm1, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, %zmm4 -; AVX512F-ONLY-NEXT: vpermt2d %zmm17, %zmm0, %zmm4 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm3 = ymm4[0,1,2,3],ymm3[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm3, %zmm2, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm25, %zmm2 -; AVX512F-ONLY-NEXT: vpermt2d %zmm21, %zmm0, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm29, %zmm3 -; AVX512F-ONLY-NEXT: vpermt2d %zmm5, %zmm0, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 {%k1} -; AVX512F-ONLY-NEXT: vpermi2d %zmm28, %zmm11, %zmm0 -; AVX512F-ONLY-NEXT: vpermi2d %zmm6, %zmm8, %zmm1 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm4 = [1,9,17,25,1,9,17,25,1,9,17,25,1,9,17,25] -; AVX512F-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm12, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2d %zmm22, %zmm4, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm26, %zmm1 -; AVX512F-ONLY-NEXT: vpermt2d %zmm20, %zmm4, %zmm1 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1} -; AVX512F-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [1,9,17,25,1,9,17,25] -; AVX512F-ONLY-NEXT: # ymm2 = mem[0,1,0,1] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm10, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2d %zmm9, %zmm2, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, %zmm2 -; AVX512F-ONLY-NEXT: vpermt2d %zmm17, %zmm4, %zmm2 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm2[0,1,2,3],ymm0[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm1, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = [2,10,18,26,2,10,18,26,2,10,18,26,2,10,18,26] -; AVX512F-ONLY-NEXT: # zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm12, %zmm1 -; AVX512F-ONLY-NEXT: vpermt2d %zmm22, %zmm0, %zmm1 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm2 = [3,11,19,27,3,11,19,27,3,11,19,27,3,11,19,27] -; AVX512F-ONLY-NEXT: # zmm2 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm12, %zmm1 -; AVX512F-ONLY-NEXT: vpermt2d %zmm22, %zmm2, %zmm1 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm10 = [4,12,20,28,4,12,20,28,4,12,20,28,4,12,20,28] -; AVX512F-ONLY-NEXT: # zmm10 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm12, %zmm2 -; AVX512F-ONLY-NEXT: vpermt2d %zmm22, %zmm10, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm15 = [5,13,21,29,5,13,21,29,5,13,21,29,5,13,21,29] -; AVX512F-ONLY-NEXT: # zmm15 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm12, %zmm1 -; AVX512F-ONLY-NEXT: vpermt2d %zmm22, %zmm15, %zmm1 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm13 = [6,14,22,30,6,14,22,30,6,14,22,30,6,14,22,30] -; AVX512F-ONLY-NEXT: # zmm13 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm12, %zmm1 -; AVX512F-ONLY-NEXT: vpermt2d %zmm22, %zmm13, %zmm1 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm1 = [7,15,23,31,7,15,23,31,7,15,23,31,7,15,23,31] -; AVX512F-ONLY-NEXT: # zmm1 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vpermt2d %zmm22, %zmm1, %zmm12 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm26, %zmm24 -; AVX512F-ONLY-NEXT: vpermt2d %zmm20, %zmm0, %zmm24 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm26, %zmm27 -; AVX512F-ONLY-NEXT: vpermt2d %zmm20, %zmm3, %zmm27 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm26, %zmm31 -; AVX512F-ONLY-NEXT: vpermt2d %zmm20, %zmm10, %zmm31 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm26, %zmm30 -; AVX512F-ONLY-NEXT: vpermt2d %zmm20, %zmm15, %zmm30 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm26, %zmm22 -; AVX512F-ONLY-NEXT: vpermt2d %zmm20, %zmm13, %zmm22 -; AVX512F-ONLY-NEXT: vpermt2d %zmm20, %zmm1, %zmm26 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, %zmm8 -; AVX512F-ONLY-NEXT: vpermt2d %zmm17, %zmm0, %zmm8 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, %zmm12 -; AVX512F-ONLY-NEXT: vpermt2d %zmm17, %zmm3, %zmm12 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, %zmm6 -; AVX512F-ONLY-NEXT: vpermt2d %zmm17, %zmm10, %zmm6 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm6, (%rsp) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, %zmm6 -; AVX512F-ONLY-NEXT: vpermt2d %zmm17, %zmm15, %zmm6 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, %zmm6 -; AVX512F-ONLY-NEXT: vpermt2d %zmm17, %zmm13, %zmm6 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2d %zmm17, %zmm1, %zmm7 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm25, %zmm18 -; AVX512F-ONLY-NEXT: vpermt2d %zmm21, %zmm4, %zmm18 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm25, %zmm19 -; AVX512F-ONLY-NEXT: vpermt2d %zmm21, %zmm0, %zmm19 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm25, %zmm23 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm3, %zmm6 -; AVX512F-ONLY-NEXT: vpermt2d %zmm21, %zmm3, %zmm23 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm25, %zmm16 -; AVX512F-ONLY-NEXT: vpermt2d %zmm21, %zmm10, %zmm16 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm25, %zmm20 -; AVX512F-ONLY-NEXT: vpermt2d %zmm21, %zmm15, %zmm20 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm25, %zmm17 -; AVX512F-ONLY-NEXT: vpermt2d %zmm21, %zmm13, %zmm17 -; AVX512F-ONLY-NEXT: vpermt2d %zmm21, %zmm1, %zmm25 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm29, %zmm9 -; AVX512F-ONLY-NEXT: vpermt2d %zmm5, %zmm4, %zmm9 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm29, %zmm11 -; AVX512F-ONLY-NEXT: vpermt2d %zmm5, %zmm0, %zmm11 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm29, %zmm14 -; AVX512F-ONLY-NEXT: vpermt2d %zmm5, %zmm6, %zmm14 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm29, %zmm21 -; AVX512F-ONLY-NEXT: vpermt2d %zmm5, %zmm10, %zmm21 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm29, %zmm7 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm15, %zmm2 -; AVX512F-ONLY-NEXT: vpermt2d %zmm5, %zmm15, %zmm7 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm29, %zmm15 -; AVX512F-ONLY-NEXT: vpermt2d %zmm5, %zmm13, %zmm15 -; AVX512F-ONLY-NEXT: vpermt2d %zmm5, %zmm1, %zmm29 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermi2d %zmm28, %zmm0, %zmm4 -; AVX512F-ONLY-NEXT: vpermi2d %zmm28, %zmm0, %zmm3 -; AVX512F-ONLY-NEXT: vpermi2d %zmm28, %zmm0, %zmm6 -; AVX512F-ONLY-NEXT: vpermi2d %zmm28, %zmm0, %zmm10 -; AVX512F-ONLY-NEXT: vpermi2d %zmm28, %zmm0, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermi2d %zmm28, %zmm0, %zmm13 -; AVX512F-ONLY-NEXT: vpermt2d %zmm28, %zmm1, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm18, %zmm9 {%k1} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm28 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512F-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm0 = [1,9,17,25,1,9,17,25] -; AVX512F-ONLY-NEXT: # ymm0 = mem[0,1,0,1] -; AVX512F-ONLY-NEXT: vpermi2d %zmm28, %zmm2, %zmm0 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm4[0,1,2,3],ymm0[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm9, %zmm18 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, %zmm24 {%k1} -; AVX512F-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm9 = [2,10,18,26,2,10,18,26] -; AVX512F-ONLY-NEXT: # ymm9 = mem[0,1,0,1] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2d %zmm5, %zmm9, %zmm0 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm8[0,1,2,3],ymm0[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm24, %zmm24 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm19, %zmm11 {%k1} -; AVX512F-ONLY-NEXT: vpermi2d %zmm28, %zmm2, %zmm9 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm1 = ymm3[0,1,2,3],ymm9[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm11, %zmm1 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, %zmm27 {%k1} -; AVX512F-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [3,11,19,27,3,11,19,27] -; AVX512F-ONLY-NEXT: # ymm3 = mem[0,1,0,1] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm9 -; AVX512F-ONLY-NEXT: vpermt2d %zmm5, %zmm3, %zmm9 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm4 = ymm12[0,1,2,3],ymm9[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm27, %zmm4 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm23, %zmm14 {%k1} -; AVX512F-ONLY-NEXT: vpermi2d %zmm28, %zmm2, %zmm3 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm3 = ymm6[0,1,2,3],ymm3[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm3, %zmm14, %zmm3 -; AVX512F-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm6 = [4,12,20,28,4,12,20,28] -; AVX512F-ONLY-NEXT: # ymm6 = mem[0,1,0,1] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, %zmm8 -; AVX512F-ONLY-NEXT: vpermt2d %zmm5, %zmm6, %zmm8 -; AVX512F-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm9 = [5,13,21,29,5,13,21,29] -; AVX512F-ONLY-NEXT: # ymm9 = mem[0,1,0,1] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, %zmm11 -; AVX512F-ONLY-NEXT: vpermt2d %zmm5, %zmm9, %zmm11 -; AVX512F-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm12 = [6,14,22,30,6,14,22,30] -; AVX512F-ONLY-NEXT: # ymm12 = mem[0,1,0,1] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, %zmm14 -; AVX512F-ONLY-NEXT: vpermt2d %zmm5, %zmm12, %zmm14 -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} ymm19 = [7,15,23,31,7,15,23,31] -; AVX512F-ONLY-NEXT: # ymm19 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vpermt2d %zmm5, %zmm19, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, %zmm5 -; AVX512F-ONLY-NEXT: vpermi2d %zmm28, %zmm2, %zmm6 -; AVX512F-ONLY-NEXT: vpermi2d %zmm28, %zmm2, %zmm9 -; AVX512F-ONLY-NEXT: vpermi2d %zmm28, %zmm2, %zmm12 -; AVX512F-ONLY-NEXT: vpermt2d %zmm28, %zmm19, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm0 -; AVX512F-ONLY-NEXT: vpblendd $15, (%rsp), %ymm8, %ymm8 # 32-byte Folded Reload -; AVX512F-ONLY-NEXT: # ymm8 = mem[0,1,2,3],ymm8[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm31 {%k1} -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm8, %zmm31, %zmm8 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm6 = ymm10[0,1,2,3],ymm6[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm16, %zmm21 {%k1} -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm6, %zmm21, %zmm6 -; AVX512F-ONLY-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm11, %ymm10 # 32-byte Folded Reload -; AVX512F-ONLY-NEXT: # ymm10 = mem[0,1,2,3],ymm11[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm30 {%k1} -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm30, %zmm10 -; AVX512F-ONLY-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm9, %ymm9 # 32-byte Folded Reload -; AVX512F-ONLY-NEXT: # ymm9 = mem[0,1,2,3],ymm9[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm20, %zmm7 {%k1} -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm9, %zmm7, %zmm7 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm22 {%k1} -; AVX512F-ONLY-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm14, %ymm9 # 32-byte Folded Reload -; AVX512F-ONLY-NEXT: # ymm9 = mem[0,1,2,3],ymm14[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm9, %zmm22, %zmm9 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm17, %zmm15 {%k1} -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm2 = ymm13[0,1,2,3],ymm12[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm15, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm11, %zmm26 {%k1} -; AVX512F-ONLY-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm5, %ymm11 # 32-byte Folded Reload -; AVX512F-ONLY-NEXT: # ymm11 = mem[0,1,2,3],ymm5[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm11, %zmm26, %zmm5 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm25, %zmm29 {%k1} -; AVX512F-ONLY-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm11 # 32-byte Folded Reload -; AVX512F-ONLY-NEXT: # ymm11 = mem[0,1,2,3],ymm0[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm11, %zmm29, %zmm11 -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 64(%rsi) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, (%rsi) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm18, 64(%rdx) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, (%rdx) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm1, 64(%rcx) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm24, (%rcx) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm3, 64(%r8) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, (%r8) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm6, 64(%r9) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm8, (%r9) -; AVX512F-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, 64(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm10, (%rax) -; AVX512F-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, 64(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm9, (%rax) -; AVX512F-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm11, 64(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm5, (%rax) -; AVX512F-ONLY-NEXT: addq $1096, %rsp # imm = 0x448 -; AVX512F-ONLY-NEXT: vzeroupper -; AVX512F-ONLY-NEXT: retq -; -; AVX512DQ-ONLY-LABEL: load_i32_stride8_vf32: -; AVX512DQ-ONLY: # %bb.0: -; AVX512DQ-ONLY-NEXT: subq $1096, %rsp # imm = 0x448 -; AVX512DQ-ONLY-NEXT: vmovdqa64 704(%rdi), %zmm6 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 640(%rdi), %zmm8 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 576(%rdi), %zmm28 -; AVX512DQ-ONLY-NEXT: vmovdqa64 512(%rdi), %zmm11 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 832(%rdi), %zmm5 -; AVX512DQ-ONLY-NEXT: vmovdqa64 768(%rdi), %zmm29 -; AVX512DQ-ONLY-NEXT: vmovdqa64 960(%rdi), %zmm21 -; AVX512DQ-ONLY-NEXT: vmovdqa64 896(%rdi), %zmm25 -; AVX512DQ-ONLY-NEXT: vmovdqa64 (%rdi), %zmm7 -; AVX512DQ-ONLY-NEXT: vmovdqa64 64(%rdi), %zmm17 -; AVX512DQ-ONLY-NEXT: vmovdqa64 128(%rdi), %zmm4 -; AVX512DQ-ONLY-NEXT: vmovdqa64 192(%rdi), %zmm9 -; AVX512DQ-ONLY-NEXT: vmovdqa64 320(%rdi), %zmm20 -; AVX512DQ-ONLY-NEXT: vmovdqa64 256(%rdi), %zmm26 -; AVX512DQ-ONLY-NEXT: vmovdqa64 448(%rdi), %zmm22 -; AVX512DQ-ONLY-NEXT: vmovdqa64 384(%rdi), %zmm2 -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = [0,8,16,24,0,8,16,24,0,8,16,24,0,8,16,24] -; AVX512DQ-ONLY-NEXT: # zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm12 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm22, %zmm0, %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm26, %zmm2 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm20, %zmm0, %zmm2 -; AVX512DQ-ONLY-NEXT: movb $-64, %al -; AVX512DQ-ONLY-NEXT: kmovw %eax, %k1 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm1, %zmm2 {%k1} -; AVX512DQ-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [0,8,16,24,0,8,16,24] -; AVX512DQ-ONLY-NEXT: # ymm1 = mem[0,1,0,1] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm10 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm9, %zmm1, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, %zmm4 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm17, %zmm0, %zmm4 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm3 = ymm4[0,1,2,3],ymm3[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm3, %zmm2, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm25, %zmm2 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm21, %zmm0, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm29, %zmm3 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm5, %zmm0, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 {%k1} -; AVX512DQ-ONLY-NEXT: vpermi2d %zmm28, %zmm11, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermi2d %zmm6, %zmm8, %zmm1 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm4 = [1,9,17,25,1,9,17,25,1,9,17,25,1,9,17,25] -; AVX512DQ-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm12, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm22, %zmm4, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm26, %zmm1 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm20, %zmm4, %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1} -; AVX512DQ-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [1,9,17,25,1,9,17,25] -; AVX512DQ-ONLY-NEXT: # ymm2 = mem[0,1,0,1] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm10, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm9, %zmm2, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, %zmm2 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm17, %zmm4, %zmm2 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm2[0,1,2,3],ymm0[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm1, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = [2,10,18,26,2,10,18,26,2,10,18,26,2,10,18,26] -; AVX512DQ-ONLY-NEXT: # zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm12, %zmm1 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm22, %zmm0, %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm2 = [3,11,19,27,3,11,19,27,3,11,19,27,3,11,19,27] -; AVX512DQ-ONLY-NEXT: # zmm2 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm12, %zmm1 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm22, %zmm2, %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm10 = [4,12,20,28,4,12,20,28,4,12,20,28,4,12,20,28] -; AVX512DQ-ONLY-NEXT: # zmm10 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm12, %zmm2 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm22, %zmm10, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm15 = [5,13,21,29,5,13,21,29,5,13,21,29,5,13,21,29] -; AVX512DQ-ONLY-NEXT: # zmm15 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm12, %zmm1 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm22, %zmm15, %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm13 = [6,14,22,30,6,14,22,30,6,14,22,30,6,14,22,30] -; AVX512DQ-ONLY-NEXT: # zmm13 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm12, %zmm1 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm22, %zmm13, %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm1 = [7,15,23,31,7,15,23,31,7,15,23,31,7,15,23,31] -; AVX512DQ-ONLY-NEXT: # zmm1 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm22, %zmm1, %zmm12 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm26, %zmm24 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm20, %zmm0, %zmm24 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm26, %zmm27 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm20, %zmm3, %zmm27 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm26, %zmm31 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm20, %zmm10, %zmm31 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm26, %zmm30 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm20, %zmm15, %zmm30 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm26, %zmm22 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm20, %zmm13, %zmm22 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm20, %zmm1, %zmm26 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, %zmm8 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm17, %zmm0, %zmm8 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, %zmm12 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm17, %zmm3, %zmm12 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, %zmm6 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm17, %zmm10, %zmm6 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm6, (%rsp) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, %zmm6 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm17, %zmm15, %zmm6 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, %zmm6 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm17, %zmm13, %zmm6 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm17, %zmm1, %zmm7 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm25, %zmm18 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm21, %zmm4, %zmm18 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm25, %zmm19 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm21, %zmm0, %zmm19 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm25, %zmm23 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm3, %zmm6 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm21, %zmm3, %zmm23 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm25, %zmm16 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm21, %zmm10, %zmm16 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm25, %zmm20 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm21, %zmm15, %zmm20 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm25, %zmm17 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm21, %zmm13, %zmm17 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm21, %zmm1, %zmm25 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm29, %zmm9 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm5, %zmm4, %zmm9 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm29, %zmm11 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm5, %zmm0, %zmm11 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm29, %zmm14 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm5, %zmm6, %zmm14 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm29, %zmm21 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm5, %zmm10, %zmm21 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm29, %zmm7 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm15, %zmm2 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm5, %zmm15, %zmm7 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm29, %zmm15 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm5, %zmm13, %zmm15 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm5, %zmm1, %zmm29 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermi2d %zmm28, %zmm0, %zmm4 -; AVX512DQ-ONLY-NEXT: vpermi2d %zmm28, %zmm0, %zmm3 -; AVX512DQ-ONLY-NEXT: vpermi2d %zmm28, %zmm0, %zmm6 -; AVX512DQ-ONLY-NEXT: vpermi2d %zmm28, %zmm0, %zmm10 -; AVX512DQ-ONLY-NEXT: vpermi2d %zmm28, %zmm0, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermi2d %zmm28, %zmm0, %zmm13 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm28, %zmm1, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm18, %zmm9 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm28 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm0 = [1,9,17,25,1,9,17,25] -; AVX512DQ-ONLY-NEXT: # ymm0 = mem[0,1,0,1] -; AVX512DQ-ONLY-NEXT: vpermi2d %zmm28, %zmm2, %zmm0 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm4[0,1,2,3],ymm0[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm9, %zmm18 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, %zmm24 {%k1} -; AVX512DQ-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm9 = [2,10,18,26,2,10,18,26] -; AVX512DQ-ONLY-NEXT: # ymm9 = mem[0,1,0,1] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm5, %zmm9, %zmm0 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm8[0,1,2,3],ymm0[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm24, %zmm24 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm19, %zmm11 {%k1} -; AVX512DQ-ONLY-NEXT: vpermi2d %zmm28, %zmm2, %zmm9 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm1 = ymm3[0,1,2,3],ymm9[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm11, %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, %zmm27 {%k1} -; AVX512DQ-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [3,11,19,27,3,11,19,27] -; AVX512DQ-ONLY-NEXT: # ymm3 = mem[0,1,0,1] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm9 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm5, %zmm3, %zmm9 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm4 = ymm12[0,1,2,3],ymm9[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm27, %zmm4 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm23, %zmm14 {%k1} -; AVX512DQ-ONLY-NEXT: vpermi2d %zmm28, %zmm2, %zmm3 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm3 = ymm6[0,1,2,3],ymm3[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm3, %zmm14, %zmm3 -; AVX512DQ-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm6 = [4,12,20,28,4,12,20,28] -; AVX512DQ-ONLY-NEXT: # ymm6 = mem[0,1,0,1] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, %zmm8 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm5, %zmm6, %zmm8 -; AVX512DQ-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm9 = [5,13,21,29,5,13,21,29] -; AVX512DQ-ONLY-NEXT: # ymm9 = mem[0,1,0,1] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, %zmm11 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm5, %zmm9, %zmm11 -; AVX512DQ-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm12 = [6,14,22,30,6,14,22,30] -; AVX512DQ-ONLY-NEXT: # ymm12 = mem[0,1,0,1] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, %zmm14 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm5, %zmm12, %zmm14 -; AVX512DQ-ONLY-NEXT: vbroadcasti64x2 {{.*#+}} ymm19 = [7,15,23,31,7,15,23,31] -; AVX512DQ-ONLY-NEXT: # ymm19 = mem[0,1,0,1] -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm5, %zmm19, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, %zmm5 -; AVX512DQ-ONLY-NEXT: vpermi2d %zmm28, %zmm2, %zmm6 -; AVX512DQ-ONLY-NEXT: vpermi2d %zmm28, %zmm2, %zmm9 -; AVX512DQ-ONLY-NEXT: vpermi2d %zmm28, %zmm2, %zmm12 -; AVX512DQ-ONLY-NEXT: vpermt2d %zmm28, %zmm19, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm0 -; AVX512DQ-ONLY-NEXT: vpblendd $15, (%rsp), %ymm8, %ymm8 # 32-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # ymm8 = mem[0,1,2,3],ymm8[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm31 {%k1} -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm8, %zmm31, %zmm8 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm6 = ymm10[0,1,2,3],ymm6[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm16, %zmm21 {%k1} -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm6, %zmm21, %zmm6 -; AVX512DQ-ONLY-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm11, %ymm10 # 32-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # ymm10 = mem[0,1,2,3],ymm11[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm30 {%k1} -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm30, %zmm10 -; AVX512DQ-ONLY-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm9, %ymm9 # 32-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # ymm9 = mem[0,1,2,3],ymm9[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm20, %zmm7 {%k1} -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm9, %zmm7, %zmm7 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm22 {%k1} -; AVX512DQ-ONLY-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm14, %ymm9 # 32-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # ymm9 = mem[0,1,2,3],ymm14[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm9, %zmm22, %zmm9 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm17, %zmm15 {%k1} -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm2 = ymm13[0,1,2,3],ymm12[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm15, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm11, %zmm26 {%k1} -; AVX512DQ-ONLY-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm5, %ymm11 # 32-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # ymm11 = mem[0,1,2,3],ymm5[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm11, %zmm26, %zmm5 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm25, %zmm29 {%k1} -; AVX512DQ-ONLY-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm11 # 32-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # ymm11 = mem[0,1,2,3],ymm0[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm11, %zmm29, %zmm11 -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 64(%rsi) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, (%rsi) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm18, 64(%rdx) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, (%rdx) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm1, 64(%rcx) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm24, (%rcx) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm3, 64(%r8) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, (%r8) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm6, 64(%r9) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm8, (%r9) -; AVX512DQ-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, 64(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm10, (%rax) -; AVX512DQ-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, 64(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm9, (%rax) -; AVX512DQ-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm11, 64(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm5, (%rax) -; AVX512DQ-ONLY-NEXT: addq $1096, %rsp # imm = 0x448 -; AVX512DQ-ONLY-NEXT: vzeroupper -; AVX512DQ-ONLY-NEXT: retq -; -; AVX512BW-ONLY-LABEL: load_i32_stride8_vf32: -; AVX512BW-ONLY: # %bb.0: -; AVX512BW-ONLY-NEXT: subq $1096, %rsp # imm = 0x448 -; AVX512BW-ONLY-NEXT: vmovdqa64 704(%rdi), %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 640(%rdi), %zmm8 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 576(%rdi), %zmm28 -; AVX512BW-ONLY-NEXT: vmovdqa64 512(%rdi), %zmm11 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 832(%rdi), %zmm5 -; AVX512BW-ONLY-NEXT: vmovdqa64 768(%rdi), %zmm29 -; AVX512BW-ONLY-NEXT: vmovdqa64 960(%rdi), %zmm21 -; AVX512BW-ONLY-NEXT: vmovdqa64 896(%rdi), %zmm25 -; AVX512BW-ONLY-NEXT: vmovdqa64 (%rdi), %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%rdi), %zmm17 -; AVX512BW-ONLY-NEXT: vmovdqa64 128(%rdi), %zmm4 -; AVX512BW-ONLY-NEXT: vmovdqa64 192(%rdi), %zmm9 -; AVX512BW-ONLY-NEXT: vmovdqa64 320(%rdi), %zmm20 -; AVX512BW-ONLY-NEXT: vmovdqa64 256(%rdi), %zmm26 -; AVX512BW-ONLY-NEXT: vmovdqa64 448(%rdi), %zmm22 -; AVX512BW-ONLY-NEXT: vmovdqa64 384(%rdi), %zmm2 -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = [0,8,16,24,0,8,16,24,0,8,16,24,0,8,16,24] -; AVX512BW-ONLY-NEXT: # zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm12 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm22, %zmm0, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm20, %zmm0, %zmm2 -; AVX512BW-ONLY-NEXT: movb $-64, %al -; AVX512BW-ONLY-NEXT: kmovd %eax, %k1 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm1, %zmm2 {%k1} -; AVX512BW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [0,8,16,24,0,8,16,24] -; AVX512BW-ONLY-NEXT: # ymm1 = mem[0,1,0,1] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm10 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2d %zmm9, %zmm1, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm4 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm17, %zmm0, %zmm4 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm3 = ymm4[0,1,2,3],ymm3[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm3, %zmm2, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm21, %zmm0, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm5, %zmm0, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 {%k1} -; AVX512BW-ONLY-NEXT: vpermi2d %zmm28, %zmm11, %zmm0 -; AVX512BW-ONLY-NEXT: vpermi2d %zmm6, %zmm8, %zmm1 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm4 = [1,9,17,25,1,9,17,25,1,9,17,25,1,9,17,25] -; AVX512BW-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm22, %zmm4, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm1 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm20, %zmm4, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1} -; AVX512BW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [1,9,17,25,1,9,17,25] -; AVX512BW-ONLY-NEXT: # ymm2 = mem[0,1,0,1] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm9, %zmm2, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm17, %zmm4, %zmm2 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm2[0,1,2,3],ymm0[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm1, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = [2,10,18,26,2,10,18,26,2,10,18,26,2,10,18,26] -; AVX512BW-ONLY-NEXT: # zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm1 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm22, %zmm0, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm2 = [3,11,19,27,3,11,19,27,3,11,19,27,3,11,19,27] -; AVX512BW-ONLY-NEXT: # zmm2 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm1 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm22, %zmm2, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm10 = [4,12,20,28,4,12,20,28,4,12,20,28,4,12,20,28] -; AVX512BW-ONLY-NEXT: # zmm10 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm22, %zmm10, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm15 = [5,13,21,29,5,13,21,29,5,13,21,29,5,13,21,29] -; AVX512BW-ONLY-NEXT: # zmm15 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm1 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm22, %zmm15, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm13 = [6,14,22,30,6,14,22,30,6,14,22,30,6,14,22,30] -; AVX512BW-ONLY-NEXT: # zmm13 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm1 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm22, %zmm13, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm1 = [7,15,23,31,7,15,23,31,7,15,23,31,7,15,23,31] -; AVX512BW-ONLY-NEXT: # zmm1 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vpermt2d %zmm22, %zmm1, %zmm12 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm24 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm20, %zmm0, %zmm24 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm27 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm20, %zmm3, %zmm27 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm31 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm20, %zmm10, %zmm31 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm30 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm20, %zmm15, %zmm30 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm22 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm20, %zmm13, %zmm22 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm20, %zmm1, %zmm26 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm8 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm17, %zmm0, %zmm8 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm12 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm17, %zmm3, %zmm12 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm6 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm17, %zmm10, %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm6, (%rsp) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm6 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm17, %zmm15, %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm6 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm17, %zmm13, %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2d %zmm17, %zmm1, %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm18 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm21, %zmm4, %zmm18 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm19 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm21, %zmm0, %zmm19 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm23 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm6 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm21, %zmm3, %zmm23 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm16 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm21, %zmm10, %zmm16 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm20 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm21, %zmm15, %zmm20 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm17 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm21, %zmm13, %zmm17 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm21, %zmm1, %zmm25 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm9 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm5, %zmm4, %zmm9 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm11 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm5, %zmm0, %zmm11 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm14 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm5, %zmm6, %zmm14 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm21 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm5, %zmm10, %zmm21 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm15, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm5, %zmm15, %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm15 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm5, %zmm13, %zmm15 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm5, %zmm1, %zmm29 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermi2d %zmm28, %zmm0, %zmm4 -; AVX512BW-ONLY-NEXT: vpermi2d %zmm28, %zmm0, %zmm3 -; AVX512BW-ONLY-NEXT: vpermi2d %zmm28, %zmm0, %zmm6 -; AVX512BW-ONLY-NEXT: vpermi2d %zmm28, %zmm0, %zmm10 -; AVX512BW-ONLY-NEXT: vpermi2d %zmm28, %zmm0, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermi2d %zmm28, %zmm0, %zmm13 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm28, %zmm1, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm18, %zmm9 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm28 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm0 = [1,9,17,25,1,9,17,25] -; AVX512BW-ONLY-NEXT: # ymm0 = mem[0,1,0,1] -; AVX512BW-ONLY-NEXT: vpermi2d %zmm28, %zmm2, %zmm0 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm4[0,1,2,3],ymm0[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm9, %zmm18 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm24 {%k1} -; AVX512BW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm9 = [2,10,18,26,2,10,18,26] -; AVX512BW-ONLY-NEXT: # ymm9 = mem[0,1,0,1] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2d %zmm5, %zmm9, %zmm0 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm8[0,1,2,3],ymm0[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm24, %zmm24 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm19, %zmm11 {%k1} -; AVX512BW-ONLY-NEXT: vpermi2d %zmm28, %zmm2, %zmm9 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm1 = ymm3[0,1,2,3],ymm9[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm11, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm27 {%k1} -; AVX512BW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [3,11,19,27,3,11,19,27] -; AVX512BW-ONLY-NEXT: # ymm3 = mem[0,1,0,1] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm9 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm5, %zmm3, %zmm9 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm4 = ymm12[0,1,2,3],ymm9[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm27, %zmm4 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm14 {%k1} -; AVX512BW-ONLY-NEXT: vpermi2d %zmm28, %zmm2, %zmm3 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm3 = ymm6[0,1,2,3],ymm3[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm3, %zmm14, %zmm3 -; AVX512BW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm6 = [4,12,20,28,4,12,20,28] -; AVX512BW-ONLY-NEXT: # ymm6 = mem[0,1,0,1] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm8 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm5, %zmm6, %zmm8 -; AVX512BW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm9 = [5,13,21,29,5,13,21,29] -; AVX512BW-ONLY-NEXT: # ymm9 = mem[0,1,0,1] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm11 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm5, %zmm9, %zmm11 -; AVX512BW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm12 = [6,14,22,30,6,14,22,30] -; AVX512BW-ONLY-NEXT: # ymm12 = mem[0,1,0,1] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm14 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm5, %zmm12, %zmm14 -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} ymm19 = [7,15,23,31,7,15,23,31] -; AVX512BW-ONLY-NEXT: # ymm19 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vpermt2d %zmm5, %zmm19, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm5 -; AVX512BW-ONLY-NEXT: vpermi2d %zmm28, %zmm2, %zmm6 -; AVX512BW-ONLY-NEXT: vpermi2d %zmm28, %zmm2, %zmm9 -; AVX512BW-ONLY-NEXT: vpermi2d %zmm28, %zmm2, %zmm12 -; AVX512BW-ONLY-NEXT: vpermt2d %zmm28, %zmm19, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm0 -; AVX512BW-ONLY-NEXT: vpblendd $15, (%rsp), %ymm8, %ymm8 # 32-byte Folded Reload -; AVX512BW-ONLY-NEXT: # ymm8 = mem[0,1,2,3],ymm8[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm31 {%k1} -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm8, %zmm31, %zmm8 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm6 = ymm10[0,1,2,3],ymm6[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm16, %zmm21 {%k1} -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm6, %zmm21, %zmm6 -; AVX512BW-ONLY-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm11, %ymm10 # 32-byte Folded Reload -; AVX512BW-ONLY-NEXT: # ymm10 = mem[0,1,2,3],ymm11[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm30 {%k1} -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm30, %zmm10 -; AVX512BW-ONLY-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm9, %ymm9 # 32-byte Folded Reload -; AVX512BW-ONLY-NEXT: # ymm9 = mem[0,1,2,3],ymm9[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm20, %zmm7 {%k1} -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm9, %zmm7, %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm22 {%k1} -; AVX512BW-ONLY-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm14, %ymm9 # 32-byte Folded Reload -; AVX512BW-ONLY-NEXT: # ymm9 = mem[0,1,2,3],ymm14[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm9, %zmm22, %zmm9 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm17, %zmm15 {%k1} -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm2 = ymm13[0,1,2,3],ymm12[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm15, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm26 {%k1} -; AVX512BW-ONLY-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm5, %ymm11 # 32-byte Folded Reload -; AVX512BW-ONLY-NEXT: # ymm11 = mem[0,1,2,3],ymm5[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm11, %zmm26, %zmm5 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm29 {%k1} -; AVX512BW-ONLY-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm11 # 32-byte Folded Reload -; AVX512BW-ONLY-NEXT: # ymm11 = mem[0,1,2,3],ymm0[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm11, %zmm29, %zmm11 -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 64(%rsi) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, (%rsi) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm18, 64(%rdx) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, (%rdx) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm1, 64(%rcx) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm24, (%rcx) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm3, 64(%r8) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, (%r8) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm6, 64(%r9) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm8, (%r9) -; AVX512BW-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, 64(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, (%rax) -; AVX512BW-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, 64(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm9, (%rax) -; AVX512BW-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm11, 64(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, (%rax) -; AVX512BW-ONLY-NEXT: addq $1096, %rsp # imm = 0x448 -; AVX512BW-ONLY-NEXT: vzeroupper -; AVX512BW-ONLY-NEXT: retq +; AVX512F-LABEL: load_i32_stride8_vf32: +; AVX512F: # %bb.0: +; AVX512F-NEXT: subq $1096, %rsp # imm = 0x448 +; AVX512F-NEXT: vmovdqa64 704(%rdi), %zmm6 +; AVX512F-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 640(%rdi), %zmm8 +; AVX512F-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 576(%rdi), %zmm28 +; AVX512F-NEXT: vmovdqa64 512(%rdi), %zmm11 +; AVX512F-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 832(%rdi), %zmm5 +; AVX512F-NEXT: vmovdqa64 768(%rdi), %zmm29 +; AVX512F-NEXT: vmovdqa64 960(%rdi), %zmm21 +; AVX512F-NEXT: vmovdqa64 896(%rdi), %zmm25 +; AVX512F-NEXT: vmovdqa64 (%rdi), %zmm7 +; AVX512F-NEXT: vmovdqa64 64(%rdi), %zmm17 +; AVX512F-NEXT: vmovdqa64 128(%rdi), %zmm4 +; AVX512F-NEXT: vmovdqa64 192(%rdi), %zmm9 +; AVX512F-NEXT: vmovdqa64 320(%rdi), %zmm20 +; AVX512F-NEXT: vmovdqa64 256(%rdi), %zmm26 +; AVX512F-NEXT: vmovdqa64 448(%rdi), %zmm22 +; AVX512F-NEXT: vmovdqa64 384(%rdi), %zmm2 +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = [0,8,16,24,0,8,16,24,0,8,16,24,0,8,16,24] +; AVX512F-NEXT: # zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm1 +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm12 +; AVX512F-NEXT: vpermt2d %zmm22, %zmm0, %zmm1 +; AVX512F-NEXT: vmovdqa64 %zmm26, %zmm2 +; AVX512F-NEXT: vpermt2d %zmm20, %zmm0, %zmm2 +; AVX512F-NEXT: movb $-64, %al +; AVX512F-NEXT: kmovw %eax, %k1 +; AVX512F-NEXT: vmovdqa64 %zmm1, %zmm2 {%k1} +; AVX512F-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [0,8,16,24,0,8,16,24] +; AVX512F-NEXT: # ymm1 = mem[0,1,0,1] +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm3 +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm10 +; AVX512F-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2d %zmm9, %zmm1, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm7, %zmm4 +; AVX512F-NEXT: vpermt2d %zmm17, %zmm0, %zmm4 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm3 = ymm4[0,1,2,3],ymm3[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm3, %zmm2, %zmm2 +; AVX512F-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm25, %zmm2 +; AVX512F-NEXT: vpermt2d %zmm21, %zmm0, %zmm2 +; AVX512F-NEXT: vmovdqa64 %zmm29, %zmm3 +; AVX512F-NEXT: vpermt2d %zmm5, %zmm0, %zmm3 +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm3 {%k1} +; AVX512F-NEXT: vpermi2d %zmm28, %zmm11, %zmm0 +; AVX512F-NEXT: vpermi2d %zmm6, %zmm8, %zmm1 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm4 = [1,9,17,25,1,9,17,25,1,9,17,25,1,9,17,25] +; AVX512F-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm12, %zmm0 +; AVX512F-NEXT: vpermt2d %zmm22, %zmm4, %zmm0 +; AVX512F-NEXT: vmovdqa64 %zmm26, %zmm1 +; AVX512F-NEXT: vpermt2d %zmm20, %zmm4, %zmm1 +; AVX512F-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1} +; AVX512F-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [1,9,17,25,1,9,17,25] +; AVX512F-NEXT: # ymm2 = mem[0,1,0,1] +; AVX512F-NEXT: vmovdqa64 %zmm10, %zmm0 +; AVX512F-NEXT: vpermt2d %zmm9, %zmm2, %zmm0 +; AVX512F-NEXT: vmovdqa64 %zmm7, %zmm2 +; AVX512F-NEXT: vpermt2d %zmm17, %zmm4, %zmm2 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm0 = ymm2[0,1,2,3],ymm0[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm0, %zmm1, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = [2,10,18,26,2,10,18,26,2,10,18,26,2,10,18,26] +; AVX512F-NEXT: # zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm12, %zmm1 +; AVX512F-NEXT: vpermt2d %zmm22, %zmm0, %zmm1 +; AVX512F-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm2 = [3,11,19,27,3,11,19,27,3,11,19,27,3,11,19,27] +; AVX512F-NEXT: # zmm2 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm12, %zmm1 +; AVX512F-NEXT: vpermt2d %zmm22, %zmm2, %zmm1 +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm10 = [4,12,20,28,4,12,20,28,4,12,20,28,4,12,20,28] +; AVX512F-NEXT: # zmm10 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm12, %zmm2 +; AVX512F-NEXT: vpermt2d %zmm22, %zmm10, %zmm2 +; AVX512F-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm15 = [5,13,21,29,5,13,21,29,5,13,21,29,5,13,21,29] +; AVX512F-NEXT: # zmm15 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm12, %zmm1 +; AVX512F-NEXT: vpermt2d %zmm22, %zmm15, %zmm1 +; AVX512F-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm13 = [6,14,22,30,6,14,22,30,6,14,22,30,6,14,22,30] +; AVX512F-NEXT: # zmm13 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm12, %zmm1 +; AVX512F-NEXT: vpermt2d %zmm22, %zmm13, %zmm1 +; AVX512F-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm1 = [7,15,23,31,7,15,23,31,7,15,23,31,7,15,23,31] +; AVX512F-NEXT: # zmm1 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vpermt2d %zmm22, %zmm1, %zmm12 +; AVX512F-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm26, %zmm24 +; AVX512F-NEXT: vpermt2d %zmm20, %zmm0, %zmm24 +; AVX512F-NEXT: vmovdqa64 %zmm26, %zmm27 +; AVX512F-NEXT: vpermt2d %zmm20, %zmm3, %zmm27 +; AVX512F-NEXT: vmovdqa64 %zmm26, %zmm31 +; AVX512F-NEXT: vpermt2d %zmm20, %zmm10, %zmm31 +; AVX512F-NEXT: vmovdqa64 %zmm26, %zmm30 +; AVX512F-NEXT: vpermt2d %zmm20, %zmm15, %zmm30 +; AVX512F-NEXT: vmovdqa64 %zmm26, %zmm22 +; AVX512F-NEXT: vpermt2d %zmm20, %zmm13, %zmm22 +; AVX512F-NEXT: vpermt2d %zmm20, %zmm1, %zmm26 +; AVX512F-NEXT: vmovdqa64 %zmm7, %zmm8 +; AVX512F-NEXT: vpermt2d %zmm17, %zmm0, %zmm8 +; AVX512F-NEXT: vmovdqa64 %zmm7, %zmm12 +; AVX512F-NEXT: vpermt2d %zmm17, %zmm3, %zmm12 +; AVX512F-NEXT: vmovdqa64 %zmm7, %zmm6 +; AVX512F-NEXT: vpermt2d %zmm17, %zmm10, %zmm6 +; AVX512F-NEXT: vmovdqu64 %zmm6, (%rsp) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm7, %zmm6 +; AVX512F-NEXT: vpermt2d %zmm17, %zmm15, %zmm6 +; AVX512F-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm7, %zmm6 +; AVX512F-NEXT: vpermt2d %zmm17, %zmm13, %zmm6 +; AVX512F-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2d %zmm17, %zmm1, %zmm7 +; AVX512F-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm25, %zmm18 +; AVX512F-NEXT: vpermt2d %zmm21, %zmm4, %zmm18 +; AVX512F-NEXT: vmovdqa64 %zmm25, %zmm19 +; AVX512F-NEXT: vpermt2d %zmm21, %zmm0, %zmm19 +; AVX512F-NEXT: vmovdqa64 %zmm25, %zmm23 +; AVX512F-NEXT: vmovdqa64 %zmm3, %zmm6 +; AVX512F-NEXT: vpermt2d %zmm21, %zmm3, %zmm23 +; AVX512F-NEXT: vmovdqa64 %zmm25, %zmm16 +; AVX512F-NEXT: vpermt2d %zmm21, %zmm10, %zmm16 +; AVX512F-NEXT: vmovdqa64 %zmm25, %zmm20 +; AVX512F-NEXT: vpermt2d %zmm21, %zmm15, %zmm20 +; AVX512F-NEXT: vmovdqa64 %zmm25, %zmm17 +; AVX512F-NEXT: vpermt2d %zmm21, %zmm13, %zmm17 +; AVX512F-NEXT: vpermt2d %zmm21, %zmm1, %zmm25 +; AVX512F-NEXT: vmovdqa64 %zmm29, %zmm9 +; AVX512F-NEXT: vpermt2d %zmm5, %zmm4, %zmm9 +; AVX512F-NEXT: vmovdqa64 %zmm29, %zmm11 +; AVX512F-NEXT: vpermt2d %zmm5, %zmm0, %zmm11 +; AVX512F-NEXT: vmovdqa64 %zmm0, %zmm3 +; AVX512F-NEXT: vmovdqa64 %zmm29, %zmm14 +; AVX512F-NEXT: vpermt2d %zmm5, %zmm6, %zmm14 +; AVX512F-NEXT: vmovdqa64 %zmm29, %zmm21 +; AVX512F-NEXT: vpermt2d %zmm5, %zmm10, %zmm21 +; AVX512F-NEXT: vmovdqa64 %zmm29, %zmm7 +; AVX512F-NEXT: vmovdqa64 %zmm15, %zmm2 +; AVX512F-NEXT: vpermt2d %zmm5, %zmm15, %zmm7 +; AVX512F-NEXT: vmovdqa64 %zmm29, %zmm15 +; AVX512F-NEXT: vpermt2d %zmm5, %zmm13, %zmm15 +; AVX512F-NEXT: vpermt2d %zmm5, %zmm1, %zmm29 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vpermi2d %zmm28, %zmm0, %zmm4 +; AVX512F-NEXT: vpermi2d %zmm28, %zmm0, %zmm3 +; AVX512F-NEXT: vpermi2d %zmm28, %zmm0, %zmm6 +; AVX512F-NEXT: vpermi2d %zmm28, %zmm0, %zmm10 +; AVX512F-NEXT: vpermi2d %zmm28, %zmm0, %zmm2 +; AVX512F-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermi2d %zmm28, %zmm0, %zmm13 +; AVX512F-NEXT: vpermt2d %zmm28, %zmm1, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm18, %zmm9 {%k1} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm28 # 64-byte Reload +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512F-NEXT: vbroadcasti128 {{.*#+}} ymm0 = [1,9,17,25,1,9,17,25] +; AVX512F-NEXT: # ymm0 = mem[0,1,0,1] +; AVX512F-NEXT: vpermi2d %zmm28, %zmm2, %zmm0 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm0 = ymm4[0,1,2,3],ymm0[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm0, %zmm9, %zmm18 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm0, %zmm24 {%k1} +; AVX512F-NEXT: vbroadcasti128 {{.*#+}} ymm9 = [2,10,18,26,2,10,18,26] +; AVX512F-NEXT: # ymm9 = mem[0,1,0,1] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm0 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512F-NEXT: vpermt2d %zmm5, %zmm9, %zmm0 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm0 = ymm8[0,1,2,3],ymm0[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm0, %zmm24, %zmm24 +; AVX512F-NEXT: vmovdqa64 %zmm19, %zmm11 {%k1} +; AVX512F-NEXT: vpermi2d %zmm28, %zmm2, %zmm9 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm3[0,1,2,3],ymm9[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm1, %zmm11, %zmm1 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm0, %zmm27 {%k1} +; AVX512F-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [3,11,19,27,3,11,19,27] +; AVX512F-NEXT: # ymm3 = mem[0,1,0,1] +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm0 +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm9 +; AVX512F-NEXT: vpermt2d %zmm5, %zmm3, %zmm9 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm4 = ymm12[0,1,2,3],ymm9[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm4, %zmm27, %zmm4 +; AVX512F-NEXT: vmovdqa64 %zmm23, %zmm14 {%k1} +; AVX512F-NEXT: vpermi2d %zmm28, %zmm2, %zmm3 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm3 = ymm6[0,1,2,3],ymm3[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm3, %zmm14, %zmm3 +; AVX512F-NEXT: vbroadcasti128 {{.*#+}} ymm6 = [4,12,20,28,4,12,20,28] +; AVX512F-NEXT: # ymm6 = mem[0,1,0,1] +; AVX512F-NEXT: vmovdqa64 %zmm0, %zmm8 +; AVX512F-NEXT: vpermt2d %zmm5, %zmm6, %zmm8 +; AVX512F-NEXT: vbroadcasti128 {{.*#+}} ymm9 = [5,13,21,29,5,13,21,29] +; AVX512F-NEXT: # ymm9 = mem[0,1,0,1] +; AVX512F-NEXT: vmovdqa64 %zmm0, %zmm11 +; AVX512F-NEXT: vpermt2d %zmm5, %zmm9, %zmm11 +; AVX512F-NEXT: vbroadcasti128 {{.*#+}} ymm12 = [6,14,22,30,6,14,22,30] +; AVX512F-NEXT: # ymm12 = mem[0,1,0,1] +; AVX512F-NEXT: vmovdqa64 %zmm0, %zmm14 +; AVX512F-NEXT: vpermt2d %zmm5, %zmm12, %zmm14 +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} ymm19 = [7,15,23,31,7,15,23,31] +; AVX512F-NEXT: # ymm19 = mem[0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vpermt2d %zmm5, %zmm19, %zmm0 +; AVX512F-NEXT: vmovdqa64 %zmm0, %zmm5 +; AVX512F-NEXT: vpermi2d %zmm28, %zmm2, %zmm6 +; AVX512F-NEXT: vpermi2d %zmm28, %zmm2, %zmm9 +; AVX512F-NEXT: vpermi2d %zmm28, %zmm2, %zmm12 +; AVX512F-NEXT: vpermt2d %zmm28, %zmm19, %zmm2 +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm0 +; AVX512F-NEXT: vpblendd $15, (%rsp), %ymm8, %ymm8 # 32-byte Folded Reload +; AVX512F-NEXT: # ymm8 = mem[0,1,2,3],ymm8[4,5,6,7] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm31 {%k1} +; AVX512F-NEXT: vinserti64x4 $0, %ymm8, %zmm31, %zmm8 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm6 = ymm10[0,1,2,3],ymm6[4,5,6,7] +; AVX512F-NEXT: vmovdqa64 %zmm16, %zmm21 {%k1} +; AVX512F-NEXT: vinserti64x4 $0, %ymm6, %zmm21, %zmm6 +; AVX512F-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm11, %ymm10 # 32-byte Folded Reload +; AVX512F-NEXT: # ymm10 = mem[0,1,2,3],ymm11[4,5,6,7] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm30 {%k1} +; AVX512F-NEXT: vinserti64x4 $0, %ymm10, %zmm30, %zmm10 +; AVX512F-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm9, %ymm9 # 32-byte Folded Reload +; AVX512F-NEXT: # ymm9 = mem[0,1,2,3],ymm9[4,5,6,7] +; AVX512F-NEXT: vmovdqa64 %zmm20, %zmm7 {%k1} +; AVX512F-NEXT: vinserti64x4 $0, %ymm9, %zmm7, %zmm7 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm22 {%k1} +; AVX512F-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm14, %ymm9 # 32-byte Folded Reload +; AVX512F-NEXT: # ymm9 = mem[0,1,2,3],ymm14[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm9, %zmm22, %zmm9 +; AVX512F-NEXT: vmovdqa64 %zmm17, %zmm15 {%k1} +; AVX512F-NEXT: vpblendd {{.*#+}} ymm2 = ymm13[0,1,2,3],ymm12[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm2, %zmm15, %zmm2 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm11, %zmm26 {%k1} +; AVX512F-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm5, %ymm11 # 32-byte Folded Reload +; AVX512F-NEXT: # ymm11 = mem[0,1,2,3],ymm5[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm11, %zmm26, %zmm5 +; AVX512F-NEXT: vmovdqa64 %zmm25, %zmm29 {%k1} +; AVX512F-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm11 # 32-byte Folded Reload +; AVX512F-NEXT: # ymm11 = mem[0,1,2,3],ymm0[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm11, %zmm29, %zmm11 +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 64(%rsi) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, (%rsi) +; AVX512F-NEXT: vmovdqa64 %zmm18, 64(%rdx) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, (%rdx) +; AVX512F-NEXT: vmovdqa64 %zmm1, 64(%rcx) +; AVX512F-NEXT: vmovdqa64 %zmm24, (%rcx) +; AVX512F-NEXT: vmovdqa64 %zmm3, 64(%r8) +; AVX512F-NEXT: vmovdqa64 %zmm4, (%r8) +; AVX512F-NEXT: vmovdqa64 %zmm6, 64(%r9) +; AVX512F-NEXT: vmovdqa64 %zmm8, (%r9) +; AVX512F-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512F-NEXT: vmovdqa64 %zmm7, 64(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm10, (%rax) +; AVX512F-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512F-NEXT: vmovdqa64 %zmm2, 64(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm9, (%rax) +; AVX512F-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512F-NEXT: vmovdqa64 %zmm11, 64(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm5, (%rax) +; AVX512F-NEXT: addq $1096, %rsp # imm = 0x448 +; AVX512F-NEXT: vzeroupper +; AVX512F-NEXT: retq ; -; AVX512DQBW-ONLY-LABEL: load_i32_stride8_vf32: -; AVX512DQBW-ONLY: # %bb.0: -; AVX512DQBW-ONLY-NEXT: subq $1096, %rsp # imm = 0x448 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 704(%rdi), %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 640(%rdi), %zmm8 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 576(%rdi), %zmm28 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 512(%rdi), %zmm11 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 832(%rdi), %zmm5 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 768(%rdi), %zmm29 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 960(%rdi), %zmm21 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 896(%rdi), %zmm25 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 (%rdi), %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%rdi), %zmm17 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 128(%rdi), %zmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 192(%rdi), %zmm9 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 320(%rdi), %zmm20 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 256(%rdi), %zmm26 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 448(%rdi), %zmm22 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 384(%rdi), %zmm2 -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = [0,8,16,24,0,8,16,24,0,8,16,24,0,8,16,24] -; AVX512DQBW-ONLY-NEXT: # zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm12 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm22, %zmm0, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm20, %zmm0, %zmm2 -; AVX512DQBW-ONLY-NEXT: movb $-64, %al -; AVX512DQBW-ONLY-NEXT: kmovd %eax, %k1 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm1, %zmm2 {%k1} -; AVX512DQBW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [0,8,16,24,0,8,16,24] -; AVX512DQBW-ONLY-NEXT: # ymm1 = mem[0,1,0,1] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm10 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm9, %zmm1, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm4 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm17, %zmm0, %zmm4 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm3 = ymm4[0,1,2,3],ymm3[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm3, %zmm2, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm21, %zmm0, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm5, %zmm0, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 {%k1} -; AVX512DQBW-ONLY-NEXT: vpermi2d %zmm28, %zmm11, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermi2d %zmm6, %zmm8, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm4 = [1,9,17,25,1,9,17,25,1,9,17,25,1,9,17,25] -; AVX512DQBW-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm22, %zmm4, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm20, %zmm4, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1} -; AVX512DQBW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [1,9,17,25,1,9,17,25] -; AVX512DQBW-ONLY-NEXT: # ymm2 = mem[0,1,0,1] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm9, %zmm2, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm17, %zmm4, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm2[0,1,2,3],ymm0[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm1, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = [2,10,18,26,2,10,18,26,2,10,18,26,2,10,18,26] -; AVX512DQBW-ONLY-NEXT: # zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm22, %zmm0, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm2 = [3,11,19,27,3,11,19,27,3,11,19,27,3,11,19,27] -; AVX512DQBW-ONLY-NEXT: # zmm2 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm22, %zmm2, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm10 = [4,12,20,28,4,12,20,28,4,12,20,28,4,12,20,28] -; AVX512DQBW-ONLY-NEXT: # zmm10 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm22, %zmm10, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm15 = [5,13,21,29,5,13,21,29,5,13,21,29,5,13,21,29] -; AVX512DQBW-ONLY-NEXT: # zmm15 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm22, %zmm15, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm13 = [6,14,22,30,6,14,22,30,6,14,22,30,6,14,22,30] -; AVX512DQBW-ONLY-NEXT: # zmm13 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm22, %zmm13, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm1 = [7,15,23,31,7,15,23,31,7,15,23,31,7,15,23,31] -; AVX512DQBW-ONLY-NEXT: # zmm1 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm22, %zmm1, %zmm12 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm24 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm20, %zmm0, %zmm24 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm27 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm20, %zmm3, %zmm27 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm31 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm20, %zmm10, %zmm31 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm30 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm20, %zmm15, %zmm30 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm22 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm20, %zmm13, %zmm22 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm20, %zmm1, %zmm26 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm17, %zmm0, %zmm8 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm12 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm17, %zmm3, %zmm12 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm17, %zmm10, %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm6, (%rsp) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm17, %zmm15, %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm17, %zmm13, %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm17, %zmm1, %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm18 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm21, %zmm4, %zmm18 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm19 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm21, %zmm0, %zmm19 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm23 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm21, %zmm3, %zmm23 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm16 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm21, %zmm10, %zmm16 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm20 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm21, %zmm15, %zmm20 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm17 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm21, %zmm13, %zmm17 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm21, %zmm1, %zmm25 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm9 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm5, %zmm4, %zmm9 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm11 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm5, %zmm0, %zmm11 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm14 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm5, %zmm6, %zmm14 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm21 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm5, %zmm10, %zmm21 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm15, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm5, %zmm15, %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm15 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm5, %zmm13, %zmm15 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm5, %zmm1, %zmm29 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermi2d %zmm28, %zmm0, %zmm4 -; AVX512DQBW-ONLY-NEXT: vpermi2d %zmm28, %zmm0, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermi2d %zmm28, %zmm0, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpermi2d %zmm28, %zmm0, %zmm10 -; AVX512DQBW-ONLY-NEXT: vpermi2d %zmm28, %zmm0, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermi2d %zmm28, %zmm0, %zmm13 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm28, %zmm1, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm18, %zmm9 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm28 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm0 = [1,9,17,25,1,9,17,25] -; AVX512DQBW-ONLY-NEXT: # ymm0 = mem[0,1,0,1] -; AVX512DQBW-ONLY-NEXT: vpermi2d %zmm28, %zmm2, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm4[0,1,2,3],ymm0[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm9, %zmm18 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm24 {%k1} -; AVX512DQBW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm9 = [2,10,18,26,2,10,18,26] -; AVX512DQBW-ONLY-NEXT: # ymm9 = mem[0,1,0,1] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm5, %zmm9, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm8[0,1,2,3],ymm0[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm24, %zmm24 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm19, %zmm11 {%k1} -; AVX512DQBW-ONLY-NEXT: vpermi2d %zmm28, %zmm2, %zmm9 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm1 = ymm3[0,1,2,3],ymm9[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm11, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm27 {%k1} -; AVX512DQBW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [3,11,19,27,3,11,19,27] -; AVX512DQBW-ONLY-NEXT: # ymm3 = mem[0,1,0,1] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm9 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm5, %zmm3, %zmm9 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm4 = ymm12[0,1,2,3],ymm9[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm27, %zmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm14 {%k1} -; AVX512DQBW-ONLY-NEXT: vpermi2d %zmm28, %zmm2, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm3 = ymm6[0,1,2,3],ymm3[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm3, %zmm14, %zmm3 -; AVX512DQBW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm6 = [4,12,20,28,4,12,20,28] -; AVX512DQBW-ONLY-NEXT: # ymm6 = mem[0,1,0,1] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm5, %zmm6, %zmm8 -; AVX512DQBW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm9 = [5,13,21,29,5,13,21,29] -; AVX512DQBW-ONLY-NEXT: # ymm9 = mem[0,1,0,1] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm11 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm5, %zmm9, %zmm11 -; AVX512DQBW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm12 = [6,14,22,30,6,14,22,30] -; AVX512DQBW-ONLY-NEXT: # ymm12 = mem[0,1,0,1] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm14 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm5, %zmm12, %zmm14 -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x2 {{.*#+}} ymm19 = [7,15,23,31,7,15,23,31] -; AVX512DQBW-ONLY-NEXT: # ymm19 = mem[0,1,0,1] -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm5, %zmm19, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm5 -; AVX512DQBW-ONLY-NEXT: vpermi2d %zmm28, %zmm2, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpermi2d %zmm28, %zmm2, %zmm9 -; AVX512DQBW-ONLY-NEXT: vpermi2d %zmm28, %zmm2, %zmm12 -; AVX512DQBW-ONLY-NEXT: vpermt2d %zmm28, %zmm19, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpblendd $15, (%rsp), %ymm8, %ymm8 # 32-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # ymm8 = mem[0,1,2,3],ymm8[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm31 {%k1} -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm8, %zmm31, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm6 = ymm10[0,1,2,3],ymm6[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm16, %zmm21 {%k1} -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm6, %zmm21, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm11, %ymm10 # 32-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # ymm10 = mem[0,1,2,3],ymm11[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm30 {%k1} -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm30, %zmm10 -; AVX512DQBW-ONLY-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm9, %ymm9 # 32-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # ymm9 = mem[0,1,2,3],ymm9[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm20, %zmm7 {%k1} -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm9, %zmm7, %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm22 {%k1} -; AVX512DQBW-ONLY-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm14, %ymm9 # 32-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # ymm9 = mem[0,1,2,3],ymm14[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm9, %zmm22, %zmm9 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm17, %zmm15 {%k1} -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm2 = ymm13[0,1,2,3],ymm12[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm15, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm26 {%k1} -; AVX512DQBW-ONLY-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm5, %ymm11 # 32-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # ymm11 = mem[0,1,2,3],ymm5[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm11, %zmm26, %zmm5 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm29 {%k1} -; AVX512DQBW-ONLY-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm11 # 32-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # ymm11 = mem[0,1,2,3],ymm0[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm11, %zmm29, %zmm11 -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 64(%rsi) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, (%rsi) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm18, 64(%rdx) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, (%rdx) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm1, 64(%rcx) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm24, (%rcx) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm3, 64(%r8) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, (%r8) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm6, 64(%r9) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm8, (%r9) -; AVX512DQBW-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, 64(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, (%rax) -; AVX512DQBW-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, 64(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm9, (%rax) -; AVX512DQBW-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm11, 64(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, (%rax) -; AVX512DQBW-ONLY-NEXT: addq $1096, %rsp # imm = 0x448 -; AVX512DQBW-ONLY-NEXT: vzeroupper -; AVX512DQBW-ONLY-NEXT: retq +; AVX512BW-LABEL: load_i32_stride8_vf32: +; AVX512BW: # %bb.0: +; AVX512BW-NEXT: subq $1096, %rsp # imm = 0x448 +; AVX512BW-NEXT: vmovdqa64 704(%rdi), %zmm6 +; AVX512BW-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 640(%rdi), %zmm8 +; AVX512BW-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 576(%rdi), %zmm28 +; AVX512BW-NEXT: vmovdqa64 512(%rdi), %zmm11 +; AVX512BW-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 832(%rdi), %zmm5 +; AVX512BW-NEXT: vmovdqa64 768(%rdi), %zmm29 +; AVX512BW-NEXT: vmovdqa64 960(%rdi), %zmm21 +; AVX512BW-NEXT: vmovdqa64 896(%rdi), %zmm25 +; AVX512BW-NEXT: vmovdqa64 (%rdi), %zmm7 +; AVX512BW-NEXT: vmovdqa64 64(%rdi), %zmm17 +; AVX512BW-NEXT: vmovdqa64 128(%rdi), %zmm4 +; AVX512BW-NEXT: vmovdqa64 192(%rdi), %zmm9 +; AVX512BW-NEXT: vmovdqa64 320(%rdi), %zmm20 +; AVX512BW-NEXT: vmovdqa64 256(%rdi), %zmm26 +; AVX512BW-NEXT: vmovdqa64 448(%rdi), %zmm22 +; AVX512BW-NEXT: vmovdqa64 384(%rdi), %zmm2 +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = [0,8,16,24,0,8,16,24,0,8,16,24,0,8,16,24] +; AVX512BW-NEXT: # zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm1 +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm12 +; AVX512BW-NEXT: vpermt2d %zmm22, %zmm0, %zmm1 +; AVX512BW-NEXT: vmovdqa64 %zmm26, %zmm2 +; AVX512BW-NEXT: vpermt2d %zmm20, %zmm0, %zmm2 +; AVX512BW-NEXT: movb $-64, %al +; AVX512BW-NEXT: kmovd %eax, %k1 +; AVX512BW-NEXT: vmovdqa64 %zmm1, %zmm2 {%k1} +; AVX512BW-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [0,8,16,24,0,8,16,24] +; AVX512BW-NEXT: # ymm1 = mem[0,1,0,1] +; AVX512BW-NEXT: vmovdqa64 %zmm4, %zmm3 +; AVX512BW-NEXT: vmovdqa64 %zmm4, %zmm10 +; AVX512BW-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2d %zmm9, %zmm1, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm4 +; AVX512BW-NEXT: vpermt2d %zmm17, %zmm0, %zmm4 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm3 = ymm4[0,1,2,3],ymm3[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm3, %zmm2, %zmm2 +; AVX512BW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm25, %zmm2 +; AVX512BW-NEXT: vpermt2d %zmm21, %zmm0, %zmm2 +; AVX512BW-NEXT: vmovdqa64 %zmm29, %zmm3 +; AVX512BW-NEXT: vpermt2d %zmm5, %zmm0, %zmm3 +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm3 {%k1} +; AVX512BW-NEXT: vpermi2d %zmm28, %zmm11, %zmm0 +; AVX512BW-NEXT: vpermi2d %zmm6, %zmm8, %zmm1 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm4 = [1,9,17,25,1,9,17,25,1,9,17,25,1,9,17,25] +; AVX512BW-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm12, %zmm0 +; AVX512BW-NEXT: vpermt2d %zmm22, %zmm4, %zmm0 +; AVX512BW-NEXT: vmovdqa64 %zmm26, %zmm1 +; AVX512BW-NEXT: vpermt2d %zmm20, %zmm4, %zmm1 +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1} +; AVX512BW-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [1,9,17,25,1,9,17,25] +; AVX512BW-NEXT: # ymm2 = mem[0,1,0,1] +; AVX512BW-NEXT: vmovdqa64 %zmm10, %zmm0 +; AVX512BW-NEXT: vpermt2d %zmm9, %zmm2, %zmm0 +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm2 +; AVX512BW-NEXT: vpermt2d %zmm17, %zmm4, %zmm2 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm0 = ymm2[0,1,2,3],ymm0[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm1, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = [2,10,18,26,2,10,18,26,2,10,18,26,2,10,18,26] +; AVX512BW-NEXT: # zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm12, %zmm1 +; AVX512BW-NEXT: vpermt2d %zmm22, %zmm0, %zmm1 +; AVX512BW-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm2 = [3,11,19,27,3,11,19,27,3,11,19,27,3,11,19,27] +; AVX512BW-NEXT: # zmm2 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm12, %zmm1 +; AVX512BW-NEXT: vpermt2d %zmm22, %zmm2, %zmm1 +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm10 = [4,12,20,28,4,12,20,28,4,12,20,28,4,12,20,28] +; AVX512BW-NEXT: # zmm10 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm12, %zmm2 +; AVX512BW-NEXT: vpermt2d %zmm22, %zmm10, %zmm2 +; AVX512BW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm15 = [5,13,21,29,5,13,21,29,5,13,21,29,5,13,21,29] +; AVX512BW-NEXT: # zmm15 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm12, %zmm1 +; AVX512BW-NEXT: vpermt2d %zmm22, %zmm15, %zmm1 +; AVX512BW-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm13 = [6,14,22,30,6,14,22,30,6,14,22,30,6,14,22,30] +; AVX512BW-NEXT: # zmm13 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm12, %zmm1 +; AVX512BW-NEXT: vpermt2d %zmm22, %zmm13, %zmm1 +; AVX512BW-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm1 = [7,15,23,31,7,15,23,31,7,15,23,31,7,15,23,31] +; AVX512BW-NEXT: # zmm1 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vpermt2d %zmm22, %zmm1, %zmm12 +; AVX512BW-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm26, %zmm24 +; AVX512BW-NEXT: vpermt2d %zmm20, %zmm0, %zmm24 +; AVX512BW-NEXT: vmovdqa64 %zmm26, %zmm27 +; AVX512BW-NEXT: vpermt2d %zmm20, %zmm3, %zmm27 +; AVX512BW-NEXT: vmovdqa64 %zmm26, %zmm31 +; AVX512BW-NEXT: vpermt2d %zmm20, %zmm10, %zmm31 +; AVX512BW-NEXT: vmovdqa64 %zmm26, %zmm30 +; AVX512BW-NEXT: vpermt2d %zmm20, %zmm15, %zmm30 +; AVX512BW-NEXT: vmovdqa64 %zmm26, %zmm22 +; AVX512BW-NEXT: vpermt2d %zmm20, %zmm13, %zmm22 +; AVX512BW-NEXT: vpermt2d %zmm20, %zmm1, %zmm26 +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm8 +; AVX512BW-NEXT: vpermt2d %zmm17, %zmm0, %zmm8 +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm12 +; AVX512BW-NEXT: vpermt2d %zmm17, %zmm3, %zmm12 +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm6 +; AVX512BW-NEXT: vpermt2d %zmm17, %zmm10, %zmm6 +; AVX512BW-NEXT: vmovdqu64 %zmm6, (%rsp) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm6 +; AVX512BW-NEXT: vpermt2d %zmm17, %zmm15, %zmm6 +; AVX512BW-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm6 +; AVX512BW-NEXT: vpermt2d %zmm17, %zmm13, %zmm6 +; AVX512BW-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2d %zmm17, %zmm1, %zmm7 +; AVX512BW-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm25, %zmm18 +; AVX512BW-NEXT: vpermt2d %zmm21, %zmm4, %zmm18 +; AVX512BW-NEXT: vmovdqa64 %zmm25, %zmm19 +; AVX512BW-NEXT: vpermt2d %zmm21, %zmm0, %zmm19 +; AVX512BW-NEXT: vmovdqa64 %zmm25, %zmm23 +; AVX512BW-NEXT: vmovdqa64 %zmm3, %zmm6 +; AVX512BW-NEXT: vpermt2d %zmm21, %zmm3, %zmm23 +; AVX512BW-NEXT: vmovdqa64 %zmm25, %zmm16 +; AVX512BW-NEXT: vpermt2d %zmm21, %zmm10, %zmm16 +; AVX512BW-NEXT: vmovdqa64 %zmm25, %zmm20 +; AVX512BW-NEXT: vpermt2d %zmm21, %zmm15, %zmm20 +; AVX512BW-NEXT: vmovdqa64 %zmm25, %zmm17 +; AVX512BW-NEXT: vpermt2d %zmm21, %zmm13, %zmm17 +; AVX512BW-NEXT: vpermt2d %zmm21, %zmm1, %zmm25 +; AVX512BW-NEXT: vmovdqa64 %zmm29, %zmm9 +; AVX512BW-NEXT: vpermt2d %zmm5, %zmm4, %zmm9 +; AVX512BW-NEXT: vmovdqa64 %zmm29, %zmm11 +; AVX512BW-NEXT: vpermt2d %zmm5, %zmm0, %zmm11 +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm3 +; AVX512BW-NEXT: vmovdqa64 %zmm29, %zmm14 +; AVX512BW-NEXT: vpermt2d %zmm5, %zmm6, %zmm14 +; AVX512BW-NEXT: vmovdqa64 %zmm29, %zmm21 +; AVX512BW-NEXT: vpermt2d %zmm5, %zmm10, %zmm21 +; AVX512BW-NEXT: vmovdqa64 %zmm29, %zmm7 +; AVX512BW-NEXT: vmovdqa64 %zmm15, %zmm2 +; AVX512BW-NEXT: vpermt2d %zmm5, %zmm15, %zmm7 +; AVX512BW-NEXT: vmovdqa64 %zmm29, %zmm15 +; AVX512BW-NEXT: vpermt2d %zmm5, %zmm13, %zmm15 +; AVX512BW-NEXT: vpermt2d %zmm5, %zmm1, %zmm29 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vpermi2d %zmm28, %zmm0, %zmm4 +; AVX512BW-NEXT: vpermi2d %zmm28, %zmm0, %zmm3 +; AVX512BW-NEXT: vpermi2d %zmm28, %zmm0, %zmm6 +; AVX512BW-NEXT: vpermi2d %zmm28, %zmm0, %zmm10 +; AVX512BW-NEXT: vpermi2d %zmm28, %zmm0, %zmm2 +; AVX512BW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermi2d %zmm28, %zmm0, %zmm13 +; AVX512BW-NEXT: vpermt2d %zmm28, %zmm1, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm18, %zmm9 {%k1} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm28 # 64-byte Reload +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512BW-NEXT: vbroadcasti128 {{.*#+}} ymm0 = [1,9,17,25,1,9,17,25] +; AVX512BW-NEXT: # ymm0 = mem[0,1,0,1] +; AVX512BW-NEXT: vpermi2d %zmm28, %zmm2, %zmm0 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm0 = ymm4[0,1,2,3],ymm0[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm9, %zmm18 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm24 {%k1} +; AVX512BW-NEXT: vbroadcasti128 {{.*#+}} ymm9 = [2,10,18,26,2,10,18,26] +; AVX512BW-NEXT: # ymm9 = mem[0,1,0,1] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm4, %zmm0 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vpermt2d %zmm5, %zmm9, %zmm0 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm0 = ymm8[0,1,2,3],ymm0[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm24, %zmm24 +; AVX512BW-NEXT: vmovdqa64 %zmm19, %zmm11 {%k1} +; AVX512BW-NEXT: vpermi2d %zmm28, %zmm2, %zmm9 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm1 = ymm3[0,1,2,3],ymm9[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm1, %zmm11, %zmm1 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm27 {%k1} +; AVX512BW-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [3,11,19,27,3,11,19,27] +; AVX512BW-NEXT: # ymm3 = mem[0,1,0,1] +; AVX512BW-NEXT: vmovdqa64 %zmm4, %zmm0 +; AVX512BW-NEXT: vmovdqa64 %zmm4, %zmm9 +; AVX512BW-NEXT: vpermt2d %zmm5, %zmm3, %zmm9 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm4 = ymm12[0,1,2,3],ymm9[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm4, %zmm27, %zmm4 +; AVX512BW-NEXT: vmovdqa64 %zmm23, %zmm14 {%k1} +; AVX512BW-NEXT: vpermi2d %zmm28, %zmm2, %zmm3 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm3 = ymm6[0,1,2,3],ymm3[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm3, %zmm14, %zmm3 +; AVX512BW-NEXT: vbroadcasti128 {{.*#+}} ymm6 = [4,12,20,28,4,12,20,28] +; AVX512BW-NEXT: # ymm6 = mem[0,1,0,1] +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm8 +; AVX512BW-NEXT: vpermt2d %zmm5, %zmm6, %zmm8 +; AVX512BW-NEXT: vbroadcasti128 {{.*#+}} ymm9 = [5,13,21,29,5,13,21,29] +; AVX512BW-NEXT: # ymm9 = mem[0,1,0,1] +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm11 +; AVX512BW-NEXT: vpermt2d %zmm5, %zmm9, %zmm11 +; AVX512BW-NEXT: vbroadcasti128 {{.*#+}} ymm12 = [6,14,22,30,6,14,22,30] +; AVX512BW-NEXT: # ymm12 = mem[0,1,0,1] +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm14 +; AVX512BW-NEXT: vpermt2d %zmm5, %zmm12, %zmm14 +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} ymm19 = [7,15,23,31,7,15,23,31] +; AVX512BW-NEXT: # ymm19 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vpermt2d %zmm5, %zmm19, %zmm0 +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm5 +; AVX512BW-NEXT: vpermi2d %zmm28, %zmm2, %zmm6 +; AVX512BW-NEXT: vpermi2d %zmm28, %zmm2, %zmm9 +; AVX512BW-NEXT: vpermi2d %zmm28, %zmm2, %zmm12 +; AVX512BW-NEXT: vpermt2d %zmm28, %zmm19, %zmm2 +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm0 +; AVX512BW-NEXT: vpblendd $15, (%rsp), %ymm8, %ymm8 # 32-byte Folded Reload +; AVX512BW-NEXT: # ymm8 = mem[0,1,2,3],ymm8[4,5,6,7] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm31 {%k1} +; AVX512BW-NEXT: vinserti64x4 $0, %ymm8, %zmm31, %zmm8 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm6 = ymm10[0,1,2,3],ymm6[4,5,6,7] +; AVX512BW-NEXT: vmovdqa64 %zmm16, %zmm21 {%k1} +; AVX512BW-NEXT: vinserti64x4 $0, %ymm6, %zmm21, %zmm6 +; AVX512BW-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm11, %ymm10 # 32-byte Folded Reload +; AVX512BW-NEXT: # ymm10 = mem[0,1,2,3],ymm11[4,5,6,7] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm30 {%k1} +; AVX512BW-NEXT: vinserti64x4 $0, %ymm10, %zmm30, %zmm10 +; AVX512BW-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm9, %ymm9 # 32-byte Folded Reload +; AVX512BW-NEXT: # ymm9 = mem[0,1,2,3],ymm9[4,5,6,7] +; AVX512BW-NEXT: vmovdqa64 %zmm20, %zmm7 {%k1} +; AVX512BW-NEXT: vinserti64x4 $0, %ymm9, %zmm7, %zmm7 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm22 {%k1} +; AVX512BW-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm14, %ymm9 # 32-byte Folded Reload +; AVX512BW-NEXT: # ymm9 = mem[0,1,2,3],ymm14[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm9, %zmm22, %zmm9 +; AVX512BW-NEXT: vmovdqa64 %zmm17, %zmm15 {%k1} +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm2 = ymm13[0,1,2,3],ymm12[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm2, %zmm15, %zmm2 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm11, %zmm26 {%k1} +; AVX512BW-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm5, %ymm11 # 32-byte Folded Reload +; AVX512BW-NEXT: # ymm11 = mem[0,1,2,3],ymm5[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm11, %zmm26, %zmm5 +; AVX512BW-NEXT: vmovdqa64 %zmm25, %zmm29 {%k1} +; AVX512BW-NEXT: vpblendd $15, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm11 # 32-byte Folded Reload +; AVX512BW-NEXT: # ymm11 = mem[0,1,2,3],ymm0[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm11, %zmm29, %zmm11 +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 64(%rsi) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, (%rsi) +; AVX512BW-NEXT: vmovdqa64 %zmm18, 64(%rdx) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, (%rdx) +; AVX512BW-NEXT: vmovdqa64 %zmm1, 64(%rcx) +; AVX512BW-NEXT: vmovdqa64 %zmm24, (%rcx) +; AVX512BW-NEXT: vmovdqa64 %zmm3, 64(%r8) +; AVX512BW-NEXT: vmovdqa64 %zmm4, (%r8) +; AVX512BW-NEXT: vmovdqa64 %zmm6, 64(%r9) +; AVX512BW-NEXT: vmovdqa64 %zmm8, (%r9) +; AVX512BW-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512BW-NEXT: vmovdqa64 %zmm7, 64(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm10, (%rax) +; AVX512BW-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512BW-NEXT: vmovdqa64 %zmm2, 64(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm9, (%rax) +; AVX512BW-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512BW-NEXT: vmovdqa64 %zmm11, 64(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm5, (%rax) +; AVX512BW-NEXT: addq $1096, %rsp # imm = 0x448 +; AVX512BW-NEXT: vzeroupper +; AVX512BW-NEXT: retq %wide.vec = load <256 x i32>, ptr %in.vec, align 64 %strided.vec0 = shufflevector <256 x i32> %wide.vec, <256 x i32> poison, <32 x i32> %strided.vec1 = shufflevector <256 x i32> %wide.vec, <256 x i32> poison, <32 x i32> @@ -9939,14 +9377,18 @@ define void @load_i32_stride8_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, pt ; AVX2-FAST-PERLANE: {{.*}} ; AVX2-SLOW: {{.*}} ; AVX512BW-FAST: {{.*}} +; AVX512BW-ONLY: {{.*}} ; AVX512BW-ONLY-FAST: {{.*}} ; AVX512BW-ONLY-SLOW: {{.*}} ; AVX512BW-SLOW: {{.*}} ; AVX512DQ-FAST: {{.*}} +; AVX512DQ-ONLY: {{.*}} ; AVX512DQ-SLOW: {{.*}} ; AVX512DQBW-FAST: {{.*}} +; AVX512DQBW-ONLY: {{.*}} ; AVX512DQBW-SLOW: {{.*}} ; AVX512F-FAST: {{.*}} +; AVX512F-ONLY: {{.*}} ; AVX512F-ONLY-FAST: {{.*}} ; AVX512F-ONLY-SLOW: {{.*}} ; AVX512F-SLOW: {{.*}} diff --git a/llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll b/llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll index 104e42930d4c..7d9c056716ce 100644 --- a/llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll +++ b/llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll @@ -3678,1787 +3678,896 @@ define void @load_i64_stride7_vf32(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, pt ; AVX2-ONLY-NEXT: vzeroupper ; AVX2-ONLY-NEXT: retq ; -; AVX512F-ONLY-LABEL: load_i64_stride7_vf32: -; AVX512F-ONLY: # %bb.0: -; AVX512F-ONLY-NEXT: subq $2216, %rsp # imm = 0x8A8 -; AVX512F-ONLY-NEXT: vmovdqa64 1664(%rdi), %zmm21 -; AVX512F-ONLY-NEXT: vmovdqa64 1600(%rdi), %zmm3 -; AVX512F-ONLY-NEXT: vmovdqa64 1216(%rdi), %zmm1 -; AVX512F-ONLY-NEXT: vmovdqa64 1152(%rdi), %zmm6 -; AVX512F-ONLY-NEXT: vmovdqa64 1088(%rdi), %zmm11 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovaps 1024(%rdi), %zmm0 -; AVX512F-ONLY-NEXT: vmovups %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 768(%rdi), %zmm2 -; AVX512F-ONLY-NEXT: vmovdqa64 704(%rdi), %zmm9 -; AVX512F-ONLY-NEXT: vmovdqa64 640(%rdi), %zmm15 -; AVX512F-ONLY-NEXT: vmovdqa64 576(%rdi), %zmm10 -; AVX512F-ONLY-NEXT: vmovdqa64 320(%rdi), %zmm0 -; AVX512F-ONLY-NEXT: vmovdqa64 256(%rdi), %zmm26 -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm7 = [10,3,10,3,10,3,10,3] -; AVX512F-ONLY-NEXT: # zmm7 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm26, %zmm8 -; AVX512F-ONLY-NEXT: vpermt2q %zmm0, %zmm7, %zmm8 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm9, %zmm8 -; AVX512F-ONLY-NEXT: vpermt2q %zmm2, %zmm7, %zmm8 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm6, %zmm8 -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm7, %zmm8 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermi2q %zmm21, %zmm3, %zmm7 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm7 = [11,4,11,4,11,4,11,4] -; AVX512F-ONLY-NEXT: # zmm7 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm6, %zmm8 -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm7, %zmm8 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, %zmm13 -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm7 = [13,6,13,6,13,6,13,6] -; AVX512F-ONLY-NEXT: # zmm7 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm9, %zmm8 -; AVX512F-ONLY-NEXT: vpermt2q %zmm2, %zmm13, %zmm8 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm26, %zmm8 -; AVX512F-ONLY-NEXT: vpermt2q %zmm0, %zmm13, %zmm8 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm20 = [12,5,12,5,12,5,12,5] -; AVX512F-ONLY-NEXT: # zmm20 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm9, %zmm18 -; AVX512F-ONLY-NEXT: vpermt2q %zmm2, %zmm20, %zmm18 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm26, %zmm23 -; AVX512F-ONLY-NEXT: vpermt2q %zmm0, %zmm20, %zmm23 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm9, %zmm17 -; AVX512F-ONLY-NEXT: vpermt2q %zmm2, %zmm7, %zmm17 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm26, %zmm25 -; AVX512F-ONLY-NEXT: vpermt2q %zmm0, %zmm7, %zmm25 -; AVX512F-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm28 = [0,7,14,0,0,7,14,0] -; AVX512F-ONLY-NEXT: # zmm28 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm9, %zmm8 -; AVX512F-ONLY-NEXT: vpermt2q %zmm2, %zmm28, %zmm8 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm26, %zmm16 -; AVX512F-ONLY-NEXT: vpermt2q %zmm0, %zmm28, %zmm16 -; AVX512F-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm30 = [9,0,7,0,9,0,7,0] -; AVX512F-ONLY-NEXT: # zmm30 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm14 -; AVX512F-ONLY-NEXT: vpermt2q %zmm9, %zmm30, %zmm14 -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm4 = [2,9,2,9,2,9,2,9] -; AVX512F-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vpermt2q %zmm2, %zmm4, %zmm9 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, %zmm8 -; AVX512F-ONLY-NEXT: vpermt2q %zmm26, %zmm30, %zmm8 -; AVX512F-ONLY-NEXT: vpermt2q %zmm0, %zmm4, %zmm26 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, %zmm2 -; AVX512F-ONLY-NEXT: vpermt2q %zmm11, %zmm7, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm10, %zmm11 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm10, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm15, %zmm10 -; AVX512F-ONLY-NEXT: vpermt2q %zmm15, %zmm7, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 192(%rdi), %zmm24 -; AVX512F-ONLY-NEXT: vmovdqa64 128(%rdi), %zmm12 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm12, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm24, %zmm7, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm3, %zmm5 -; AVX512F-ONLY-NEXT: vpermi2q %zmm21, %zmm3, %zmm13 -; AVX512F-ONLY-NEXT: vmovdqa64 1536(%rdi), %zmm15 -; AVX512F-ONLY-NEXT: vmovdqa64 1472(%rdi), %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm15, %zmm7, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm6, %zmm29 -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm20, %zmm29 -; AVX512F-ONLY-NEXT: vpermi2q %zmm21, %zmm3, %zmm20 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm6, %zmm31 -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm7, %zmm31 -; AVX512F-ONLY-NEXT: vpermi2q %zmm21, %zmm3, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm6, %zmm22 -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm28, %zmm22 -; AVX512F-ONLY-NEXT: vpermi2q %zmm21, %zmm3, %zmm28 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm1, %zmm3 -; AVX512F-ONLY-NEXT: vpermt2q %zmm6, %zmm30, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm6, %zmm0 -; AVX512F-ONLY-NEXT: vpermi2q %zmm5, %zmm21, %zmm30 -; AVX512F-ONLY-NEXT: vpermt2q %zmm21, %zmm4, %zmm5 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm5, %zmm21 -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm4, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqa64 384(%rdi), %zmm1 -; AVX512F-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [0,5,6,9,0,5,6,9] -; AVX512F-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm4, %zmm5 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 832(%rdi), %zmm5 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm4, %zmm6 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 1280(%rdi), %zmm6 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm6, %zmm4, %zmm7 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 1728(%rdi), %zmm7 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm27 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm7, %zmm4, %zmm27 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm27, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [0,5,6,10,0,5,6,10] -; AVX512F-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm6, %zmm4, %zmm19 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm19, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm4, %zmm19 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm19, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm4, %zmm19 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm19, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm7, %zmm4, %zmm13 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [0,5,6,11,0,5,6,11] -; AVX512F-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vpermt2q %zmm6, %zmm4, %zmm29 -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm4, %zmm18 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm18, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm4, %zmm23 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm23, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm7, %zmm4, %zmm20 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm20, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [0,5,6,12,0,5,6,12] -; AVX512F-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vpermt2q %zmm6, %zmm4, %zmm31 -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm4, %zmm17 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm17, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm4, %zmm25 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm25, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm7, %zmm4, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [4,5,6,13,4,5,6,13] -; AVX512F-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vpermt2q %zmm6, %zmm4, %zmm22 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm4, %zmm19 -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm4, %zmm16 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm16, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm7, %zmm4, %zmm28 -; AVX512F-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [4,5,6,14,4,5,6,14] -; AVX512F-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vpermt2q %zmm6, %zmm4, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm4, %zmm14 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm14, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm4, %zmm8 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm7, %zmm4, %zmm30 -; AVX512F-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [4,5,8,15,4,5,8,15] -; AVX512F-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm4, %zmm9 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm4, %zmm26 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm26, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm7, %zmm4, %zmm21 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm21, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm6, %zmm4, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: movb $24, %al -; AVX512F-ONLY-NEXT: kmovw %eax, %k1 -; AVX512F-ONLY-NEXT: vmovdqa64 512(%rdi), %zmm5 -; AVX512F-ONLY-NEXT: vmovdqa64 448(%rdi), %zmm7 -; AVX512F-ONLY-NEXT: vmovdqa64 {{.*#+}} ymm21 = <0,7,14,u> -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, %zmm18 -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm21, %zmm18 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm10, %zmm0 -; AVX512F-ONLY-NEXT: vshufi64x2 {{.*#+}} zmm18 {%k1} = zmm11[4,5,4,5],zmm10[4,5,4,5] -; AVX512F-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm10 = [14,0,0,7,14,0,0,7] -; AVX512F-ONLY-NEXT: # zmm10 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm11, %zmm26 -; AVX512F-ONLY-NEXT: vpermt2q %zmm0, %zmm10, %zmm26 -; AVX512F-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm16 = [7,0,9,0,7,0,9,0] -; AVX512F-ONLY-NEXT: # zmm16 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, %zmm27 -; AVX512F-ONLY-NEXT: vpermt2q %zmm11, %zmm16, %zmm27 -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} ymm20 = [4,11,4,11] -; AVX512F-ONLY-NEXT: # ymm20 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vpermt2q %zmm0, %zmm20, %zmm11 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 64(%rdi), %zmm1 -; AVX512F-ONLY-NEXT: vmovdqa64 (%rdi), %zmm14 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm14, %zmm17 -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm21, %zmm17 -; AVX512F-ONLY-NEXT: vshufi64x2 {{.*#+}} zmm17 {%k1} = zmm12[4,5,4,5],zmm24[4,5,4,5] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm12, %zmm23 -; AVX512F-ONLY-NEXT: vpermt2q %zmm24, %zmm10, %zmm23 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm24, %zmm25 -; AVX512F-ONLY-NEXT: vpermt2q %zmm12, %zmm16, %zmm25 -; AVX512F-ONLY-NEXT: vpermt2q %zmm24, %zmm20, %zmm12 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 960(%rdi), %zmm6 -; AVX512F-ONLY-NEXT: vmovdqa64 896(%rdi), %zmm11 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm11, %zmm12 -; AVX512F-ONLY-NEXT: vpermt2q %zmm6, %zmm21, %zmm12 -; AVX512F-ONLY-NEXT: vmovdqa64 1408(%rdi), %zmm4 -; AVX512F-ONLY-NEXT: vmovdqa64 1344(%rdi), %zmm8 -; AVX512F-ONLY-NEXT: vpermi2q %zmm4, %zmm8, %zmm21 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512F-ONLY-NEXT: vshufi64x2 {{.*#+}} zmm21 {%k1} = zmm3[4,5,4,5],zmm15[4,5,4,5] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm9, %zmm10, %zmm0 -; AVX512F-ONLY-NEXT: vpermi2q %zmm15, %zmm3, %zmm10 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm9, %zmm24 -; AVX512F-ONLY-NEXT: vpermt2q %zmm2, %zmm16, %zmm24 -; AVX512F-ONLY-NEXT: vpermi2q %zmm3, %zmm15, %zmm16 -; AVX512F-ONLY-NEXT: vpermt2q %zmm15, %zmm20, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vshufi64x2 {{.*#+}} zmm12 {%k1} = zmm2[4,5,4,5],zmm9[4,5,4,5] -; AVX512F-ONLY-NEXT: vpermt2q %zmm9, %zmm20, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa 912(%rdi), %xmm2 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} xmm2 = xmm2[0,1],mem[2,3] -; AVX512F-ONLY-NEXT: vinserti32x4 $0, %xmm2, %zmm0, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa 464(%rdi), %xmm0 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],mem[2,3] -; AVX512F-ONLY-NEXT: vinserti32x4 $0, %xmm0, %zmm26, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa 16(%rdi), %xmm0 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],mem[2,3] -; AVX512F-ONLY-NEXT: vinserti32x4 $0, %xmm0, %zmm23, %zmm26 -; AVX512F-ONLY-NEXT: vmovdqa 1360(%rdi), %xmm0 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],mem[2,3] -; AVX512F-ONLY-NEXT: vinserti32x4 $0, %xmm0, %zmm10, %zmm20 -; AVX512F-ONLY-NEXT: vinserti128 $1, 1088(%rdi), %ymm0, %ymm0 -; AVX512F-ONLY-NEXT: vmovdqa 1024(%rdi), %ymm2 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm2[0,1,2,3,4,5],ymm0[6,7] -; AVX512F-ONLY-NEXT: vmovdqa {{.*#+}} xmm10 = [4,11] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm11, %zmm13 -; AVX512F-ONLY-NEXT: vpermt2q %zmm6, %zmm10, %zmm13 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm13[0,1,2,3],ymm0[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm22, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vinserti128 $1, 640(%rdi), %ymm0, %ymm0 -; AVX512F-ONLY-NEXT: vmovdqa 576(%rdi), %ymm3 -; AVX512F-ONLY-NEXT: vmovdqu %ymm3, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3,4,5],ymm0[6,7] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, %zmm3 -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm10, %zmm3 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3],ymm0[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm19, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vinserti128 $1, 192(%rdi), %ymm0, %ymm0 -; AVX512F-ONLY-NEXT: vmovdqa 128(%rdi), %ymm3 -; AVX512F-ONLY-NEXT: vmovdqu %ymm3, (%rsp) # 32-byte Spill -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3,4,5],ymm0[6,7] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm14, %zmm3 -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm10, %zmm3 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3],ymm0[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vinserti128 $1, 1536(%rdi), %ymm0, %ymm0 -; AVX512F-ONLY-NEXT: vmovdqa 1472(%rdi), %ymm3 -; AVX512F-ONLY-NEXT: vmovdqu %ymm3, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3,4,5],ymm0[6,7] -; AVX512F-ONLY-NEXT: vpermi2q %zmm4, %zmm8, %zmm10 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm10[0,1,2,3],ymm0[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm28, %zmm28 -; AVX512F-ONLY-NEXT: vmovdqa 1088(%rdi), %ymm0 -; AVX512F-ONLY-NEXT: vpalignr {{.*#+}} ymm0 = ymm2[8,9,10,11,12,13,14,15],ymm0[0,1,2,3,4,5,6,7],ymm2[24,25,26,27,28,29,30,31],ymm0[16,17,18,19,20,21,22,23] -; AVX512F-ONLY-NEXT: vmovdqa64 %ymm0, %ymm23 -; AVX512F-ONLY-NEXT: vmovdqa {{.*#+}} ymm0 = <9,0,7,u> -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm5, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, %zmm9 -; AVX512F-ONLY-NEXT: vpermt2q %zmm7, %zmm0, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqa {{.*#+}} xmm2 = [5,12] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, %zmm13 -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm2, %zmm13 -; AVX512F-ONLY-NEXT: vmovdqa {{.*#+}} xmm7 = [6,13] -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm7, %zmm9 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm1, %zmm5 -; AVX512F-ONLY-NEXT: vpermt2q %zmm14, %zmm0, %zmm5 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm14, %zmm10 -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm2, %zmm10 -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm7, %zmm14 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm6, %zmm1 -; AVX512F-ONLY-NEXT: vpermt2q %zmm11, %zmm0, %zmm1 -; AVX512F-ONLY-NEXT: vpermi2q %zmm8, %zmm4, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqa 960(%rdi), %ymm15 -; AVX512F-ONLY-NEXT: vpalignr {{.*#+}} ymm15 = mem[8,9,10,11,12,13,14,15],ymm15[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm15[16,17,18,19,20,21,22,23] -; AVX512F-ONLY-NEXT: vextracti32x4 $1, %ymm15, %xmm19 -; AVX512F-ONLY-NEXT: vmovdqa 512(%rdi), %ymm15 -; AVX512F-ONLY-NEXT: vpalignr {{.*#+}} ymm15 = mem[8,9,10,11,12,13,14,15],ymm15[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm15[16,17,18,19,20,21,22,23] -; AVX512F-ONLY-NEXT: vextracti128 $1, %ymm15, %xmm15 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm11, %zmm9 -; AVX512F-ONLY-NEXT: vpermt2q %zmm6, %zmm2, %zmm9 -; AVX512F-ONLY-NEXT: vpermi2q %zmm4, %zmm8, %zmm2 -; AVX512F-ONLY-NEXT: vpermt2q %zmm4, %zmm7, %zmm8 -; AVX512F-ONLY-NEXT: vpermt2q %zmm6, %zmm7, %zmm11 -; AVX512F-ONLY-NEXT: movb $-32, %al -; AVX512F-ONLY-NEXT: kmovw %eax, %k2 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm17 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm18 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm12 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm21 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm1 {%k1} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm1 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm3 {%k1} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm3 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm5 {%k1} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm5 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm0 {%k1} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm0 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm22 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm29, %zmm22 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm29 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm29 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm26 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm20 {%k2} -; AVX512F-ONLY-NEXT: vinserti32x4 $0, %xmm19, %zmm24, %zmm4 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm31, %zmm4 {%k2} -; AVX512F-ONLY-NEXT: vinserti32x4 $0, %xmm15, %zmm27, %zmm6 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, %zmm6 {%k2} -; AVX512F-ONLY-NEXT: vmovdqa64 %ymm23, %ymm7 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm7 = ymm9[0,1,2,3],ymm7[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqa 64(%rdi), %ymm9 -; AVX512F-ONLY-NEXT: vpalignr {{.*#+}} ymm9 = mem[8,9,10,11,12,13,14,15],ymm9[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm9[16,17,18,19,20,21,22,23] -; AVX512F-ONLY-NEXT: vextracti128 $1, %ymm9, %xmm9 -; AVX512F-ONLY-NEXT: vinserti32x4 $0, %xmm9, %zmm25, %zmm9 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm15, %zmm9 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm7, %zmm15, %zmm19 -; AVX512F-ONLY-NEXT: vmovdqa 640(%rdi), %ymm15 -; AVX512F-ONLY-NEXT: vpalignr $8, {{[-0-9]+}}(%r{{[sb]}}p), %ymm15, %ymm15 # 32-byte Folded Reload -; AVX512F-ONLY-NEXT: # ymm15 = mem[8,9,10,11,12,13,14,15],ymm15[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm15[16,17,18,19,20,21,22,23] -; AVX512F-ONLY-NEXT: vmovdqa 1408(%rdi), %ymm7 -; AVX512F-ONLY-NEXT: vpalignr {{.*#+}} ymm7 = mem[8,9,10,11,12,13,14,15],ymm7[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm7[16,17,18,19,20,21,22,23] -; AVX512F-ONLY-NEXT: vextracti128 $1, %ymm7, %xmm7 -; AVX512F-ONLY-NEXT: vinserti32x4 $0, %xmm7, %zmm16, %zmm7 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm16, %zmm7 {%k2} -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm13 = ymm13[0,1,2,3],ymm15[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm13, %zmm15, %zmm13 -; AVX512F-ONLY-NEXT: vmovdqa 192(%rdi), %ymm15 -; AVX512F-ONLY-NEXT: vpalignr $8, (%rsp), %ymm15, %ymm15 # 32-byte Folded Reload -; AVX512F-ONLY-NEXT: # ymm15 = mem[8,9,10,11,12,13,14,15],ymm15[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm15[16,17,18,19,20,21,22,23] -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm10 = ymm10[0,1,2,3],ymm15[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm15, %zmm10 -; AVX512F-ONLY-NEXT: vmovdqa 1536(%rdi), %ymm15 -; AVX512F-ONLY-NEXT: vpalignr $8, {{[-0-9]+}}(%r{{[sb]}}p), %ymm15, %ymm15 # 32-byte Folded Reload -; AVX512F-ONLY-NEXT: # ymm15 = mem[8,9,10,11,12,13,14,15],ymm15[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm15[16,17,18,19,20,21,22,23] -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm15[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm30, %zmm2 -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload -; AVX512F-ONLY-NEXT: vblendps $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm15, %ymm15 # 32-byte Folded Reload -; AVX512F-ONLY-NEXT: # ymm15 = ymm15[0,1,2,3],mem[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload -; AVX512F-ONLY-NEXT: vinsertf64x4 $0, %ymm15, %zmm16, %zmm15 -; AVX512F-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm14, %ymm14 # 32-byte Folded Reload -; AVX512F-ONLY-NEXT: # ymm14 = ymm14[0,1,2,3],mem[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm14, %zmm16, %zmm14 -; AVX512F-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm8, %ymm8 # 32-byte Folded Reload -; AVX512F-ONLY-NEXT: # ymm8 = ymm8[0,1,2,3],mem[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm8, %zmm16, %zmm8 -; AVX512F-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm11, %ymm11 # 32-byte Folded Reload -; AVX512F-ONLY-NEXT: # ymm11 = ymm11[0,1,2,3],mem[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm11, %zmm16, %zmm11 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm21, 192(%rsi) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm12, 128(%rsi) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm18, 64(%rsi) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm17, (%rsi) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, 192(%rdx) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm5, (%rdx) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm3, 64(%rdx) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm1, 128(%rdx) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm20, 192(%rcx) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm26, (%rcx) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm29, 64(%rcx) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm22, 128(%rcx) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, 192(%r8) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm9, (%r8) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm6, 64(%r8) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, 128(%r8) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm28, 192(%r9) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, (%r9) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 64(%r9) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 128(%r9) -; AVX512F-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, 192(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm10, (%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm13, 64(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm19, 128(%rax) -; AVX512F-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm11, 128(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm8, 192(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm14, (%rax) -; AVX512F-ONLY-NEXT: vmovaps %zmm15, 64(%rax) -; AVX512F-ONLY-NEXT: addq $2216, %rsp # imm = 0x8A8 -; AVX512F-ONLY-NEXT: vzeroupper -; AVX512F-ONLY-NEXT: retq -; -; AVX512DQ-ONLY-LABEL: load_i64_stride7_vf32: -; AVX512DQ-ONLY: # %bb.0: -; AVX512DQ-ONLY-NEXT: subq $2216, %rsp # imm = 0x8A8 -; AVX512DQ-ONLY-NEXT: vmovdqa64 1664(%rdi), %zmm21 -; AVX512DQ-ONLY-NEXT: vmovdqa64 1600(%rdi), %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqa64 1216(%rdi), %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqa64 1152(%rdi), %zmm6 -; AVX512DQ-ONLY-NEXT: vmovdqa64 1088(%rdi), %zmm11 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovaps 1024(%rdi), %zmm0 -; AVX512DQ-ONLY-NEXT: vmovups %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 768(%rdi), %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqa64 704(%rdi), %zmm9 -; AVX512DQ-ONLY-NEXT: vmovdqa64 640(%rdi), %zmm15 -; AVX512DQ-ONLY-NEXT: vmovdqa64 576(%rdi), %zmm10 -; AVX512DQ-ONLY-NEXT: vmovdqa64 320(%rdi), %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqa64 256(%rdi), %zmm26 -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm7 = [10,3,10,3,10,3,10,3] -; AVX512DQ-ONLY-NEXT: # zmm7 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm26, %zmm8 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm0, %zmm7, %zmm8 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm9, %zmm8 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm2, %zmm7, %zmm8 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm6, %zmm8 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm7, %zmm8 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm21, %zmm3, %zmm7 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm7 = [11,4,11,4,11,4,11,4] -; AVX512DQ-ONLY-NEXT: # zmm7 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm6, %zmm8 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm7, %zmm8 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, %zmm13 -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm7 = [13,6,13,6,13,6,13,6] -; AVX512DQ-ONLY-NEXT: # zmm7 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm9, %zmm8 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm2, %zmm13, %zmm8 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm26, %zmm8 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm0, %zmm13, %zmm8 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm20 = [12,5,12,5,12,5,12,5] -; AVX512DQ-ONLY-NEXT: # zmm20 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm9, %zmm18 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm2, %zmm20, %zmm18 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm26, %zmm23 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm0, %zmm20, %zmm23 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm9, %zmm17 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm2, %zmm7, %zmm17 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm26, %zmm25 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm0, %zmm7, %zmm25 -; AVX512DQ-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm28 = [0,7,14,0,0,7,14,0] -; AVX512DQ-ONLY-NEXT: # zmm28 = mem[0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm9, %zmm8 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm2, %zmm28, %zmm8 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm26, %zmm16 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm0, %zmm28, %zmm16 -; AVX512DQ-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm30 = [9,0,7,0,9,0,7,0] -; AVX512DQ-ONLY-NEXT: # zmm30 = mem[0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm14 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm9, %zmm30, %zmm14 -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm4 = [2,9,2,9,2,9,2,9] -; AVX512DQ-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm2, %zmm4, %zmm9 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, %zmm8 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm26, %zmm30, %zmm8 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm0, %zmm4, %zmm26 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, %zmm2 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm11, %zmm7, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm10, %zmm11 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm10, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm15, %zmm10 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm15, %zmm7, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 192(%rdi), %zmm24 -; AVX512DQ-ONLY-NEXT: vmovdqa64 128(%rdi), %zmm12 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm12, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm24, %zmm7, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm3, %zmm5 -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm21, %zmm3, %zmm13 -; AVX512DQ-ONLY-NEXT: vmovdqa64 1536(%rdi), %zmm15 -; AVX512DQ-ONLY-NEXT: vmovdqa64 1472(%rdi), %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm15, %zmm7, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm6, %zmm29 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm20, %zmm29 -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm21, %zmm3, %zmm20 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm6, %zmm31 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm7, %zmm31 -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm21, %zmm3, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm6, %zmm22 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm28, %zmm22 -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm21, %zmm3, %zmm28 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm1, %zmm3 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm6, %zmm30, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm6, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm5, %zmm21, %zmm30 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm21, %zmm4, %zmm5 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm5, %zmm21 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm4, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqa64 384(%rdi), %zmm1 -; AVX512DQ-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [0,5,6,9,0,5,6,9] -; AVX512DQ-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm4, %zmm5 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 832(%rdi), %zmm5 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm4, %zmm6 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 1280(%rdi), %zmm6 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm6, %zmm4, %zmm7 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 1728(%rdi), %zmm7 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm27 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm7, %zmm4, %zmm27 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm27, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [0,5,6,10,0,5,6,10] -; AVX512DQ-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm6, %zmm4, %zmm19 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm19, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm4, %zmm19 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm19, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm4, %zmm19 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm19, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm7, %zmm4, %zmm13 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [0,5,6,11,0,5,6,11] -; AVX512DQ-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm6, %zmm4, %zmm29 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm4, %zmm18 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm18, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm4, %zmm23 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm23, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm7, %zmm4, %zmm20 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm20, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [0,5,6,12,0,5,6,12] -; AVX512DQ-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm6, %zmm4, %zmm31 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm4, %zmm17 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm17, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm4, %zmm25 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm25, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm7, %zmm4, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [4,5,6,13,4,5,6,13] -; AVX512DQ-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm6, %zmm4, %zmm22 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm4, %zmm19 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm4, %zmm16 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm16, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm7, %zmm4, %zmm28 -; AVX512DQ-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [4,5,6,14,4,5,6,14] -; AVX512DQ-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm6, %zmm4, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm4, %zmm14 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm14, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm4, %zmm8 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm7, %zmm4, %zmm30 -; AVX512DQ-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [4,5,8,15,4,5,8,15] -; AVX512DQ-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm4, %zmm9 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm4, %zmm26 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm26, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm7, %zmm4, %zmm21 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm21, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm6, %zmm4, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: movb $24, %al -; AVX512DQ-ONLY-NEXT: kmovw %eax, %k1 -; AVX512DQ-ONLY-NEXT: vmovdqa64 512(%rdi), %zmm5 -; AVX512DQ-ONLY-NEXT: vmovdqa64 448(%rdi), %zmm7 -; AVX512DQ-ONLY-NEXT: vmovdqa64 {{.*#+}} ymm21 = <0,7,14,u> -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, %zmm18 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm21, %zmm18 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm10, %zmm0 -; AVX512DQ-ONLY-NEXT: vshufi64x2 {{.*#+}} zmm18 {%k1} = zmm11[4,5,4,5],zmm10[4,5,4,5] -; AVX512DQ-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm10 = [14,0,0,7,14,0,0,7] -; AVX512DQ-ONLY-NEXT: # zmm10 = mem[0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm11, %zmm26 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm0, %zmm10, %zmm26 -; AVX512DQ-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm16 = [7,0,9,0,7,0,9,0] -; AVX512DQ-ONLY-NEXT: # zmm16 = mem[0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, %zmm27 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm11, %zmm16, %zmm27 -; AVX512DQ-ONLY-NEXT: vbroadcasti64x2 {{.*#+}} ymm20 = [4,11,4,11] -; AVX512DQ-ONLY-NEXT: # ymm20 = mem[0,1,0,1] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm0, %zmm20, %zmm11 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 64(%rdi), %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqa64 (%rdi), %zmm14 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm14, %zmm17 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm21, %zmm17 -; AVX512DQ-ONLY-NEXT: vshufi64x2 {{.*#+}} zmm17 {%k1} = zmm12[4,5,4,5],zmm24[4,5,4,5] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm12, %zmm23 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm24, %zmm10, %zmm23 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm24, %zmm25 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm12, %zmm16, %zmm25 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm24, %zmm20, %zmm12 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 960(%rdi), %zmm6 -; AVX512DQ-ONLY-NEXT: vmovdqa64 896(%rdi), %zmm11 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm11, %zmm12 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm6, %zmm21, %zmm12 -; AVX512DQ-ONLY-NEXT: vmovdqa64 1408(%rdi), %zmm4 -; AVX512DQ-ONLY-NEXT: vmovdqa64 1344(%rdi), %zmm8 -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm4, %zmm8, %zmm21 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vshufi64x2 {{.*#+}} zmm21 {%k1} = zmm3[4,5,4,5],zmm15[4,5,4,5] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm9, %zmm10, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm15, %zmm3, %zmm10 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm9, %zmm24 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm2, %zmm16, %zmm24 -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm3, %zmm15, %zmm16 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm15, %zmm20, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vshufi64x2 {{.*#+}} zmm12 {%k1} = zmm2[4,5,4,5],zmm9[4,5,4,5] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm9, %zmm20, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa 912(%rdi), %xmm2 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} xmm2 = xmm2[0,1],mem[2,3] -; AVX512DQ-ONLY-NEXT: vinserti32x4 $0, %xmm2, %zmm0, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa 464(%rdi), %xmm0 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],mem[2,3] -; AVX512DQ-ONLY-NEXT: vinserti32x4 $0, %xmm0, %zmm26, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa 16(%rdi), %xmm0 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],mem[2,3] -; AVX512DQ-ONLY-NEXT: vinserti32x4 $0, %xmm0, %zmm23, %zmm26 -; AVX512DQ-ONLY-NEXT: vmovdqa 1360(%rdi), %xmm0 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],mem[2,3] -; AVX512DQ-ONLY-NEXT: vinserti32x4 $0, %xmm0, %zmm10, %zmm20 -; AVX512DQ-ONLY-NEXT: vinserti128 $1, 1088(%rdi), %ymm0, %ymm0 -; AVX512DQ-ONLY-NEXT: vmovdqa 1024(%rdi), %ymm2 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm2[0,1,2,3,4,5],ymm0[6,7] -; AVX512DQ-ONLY-NEXT: vmovdqa {{.*#+}} xmm10 = [4,11] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm11, %zmm13 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm6, %zmm10, %zmm13 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm13[0,1,2,3],ymm0[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm22, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vinserti128 $1, 640(%rdi), %ymm0, %ymm0 -; AVX512DQ-ONLY-NEXT: vmovdqa 576(%rdi), %ymm3 -; AVX512DQ-ONLY-NEXT: vmovdqu %ymm3, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3,4,5],ymm0[6,7] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, %zmm3 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm10, %zmm3 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3],ymm0[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm19, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vinserti128 $1, 192(%rdi), %ymm0, %ymm0 -; AVX512DQ-ONLY-NEXT: vmovdqa 128(%rdi), %ymm3 -; AVX512DQ-ONLY-NEXT: vmovdqu %ymm3, (%rsp) # 32-byte Spill -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3,4,5],ymm0[6,7] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm14, %zmm3 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm10, %zmm3 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3],ymm0[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vinserti128 $1, 1536(%rdi), %ymm0, %ymm0 -; AVX512DQ-ONLY-NEXT: vmovdqa 1472(%rdi), %ymm3 -; AVX512DQ-ONLY-NEXT: vmovdqu %ymm3, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3,4,5],ymm0[6,7] -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm4, %zmm8, %zmm10 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm10[0,1,2,3],ymm0[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm28, %zmm28 -; AVX512DQ-ONLY-NEXT: vmovdqa 1088(%rdi), %ymm0 -; AVX512DQ-ONLY-NEXT: vpalignr {{.*#+}} ymm0 = ymm2[8,9,10,11,12,13,14,15],ymm0[0,1,2,3,4,5,6,7],ymm2[24,25,26,27,28,29,30,31],ymm0[16,17,18,19,20,21,22,23] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %ymm0, %ymm23 -; AVX512DQ-ONLY-NEXT: vmovdqa {{.*#+}} ymm0 = <9,0,7,u> -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm5, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, %zmm9 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm7, %zmm0, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqa {{.*#+}} xmm2 = [5,12] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, %zmm13 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm2, %zmm13 -; AVX512DQ-ONLY-NEXT: vmovdqa {{.*#+}} xmm7 = [6,13] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm7, %zmm9 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm1, %zmm5 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm14, %zmm0, %zmm5 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm14, %zmm10 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm2, %zmm10 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm7, %zmm14 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm6, %zmm1 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm11, %zmm0, %zmm1 -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm8, %zmm4, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqa 960(%rdi), %ymm15 -; AVX512DQ-ONLY-NEXT: vpalignr {{.*#+}} ymm15 = mem[8,9,10,11,12,13,14,15],ymm15[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm15[16,17,18,19,20,21,22,23] -; AVX512DQ-ONLY-NEXT: vextracti32x4 $1, %ymm15, %xmm19 -; AVX512DQ-ONLY-NEXT: vmovdqa 512(%rdi), %ymm15 -; AVX512DQ-ONLY-NEXT: vpalignr {{.*#+}} ymm15 = mem[8,9,10,11,12,13,14,15],ymm15[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm15[16,17,18,19,20,21,22,23] -; AVX512DQ-ONLY-NEXT: vextracti128 $1, %ymm15, %xmm15 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm11, %zmm9 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm6, %zmm2, %zmm9 -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm4, %zmm8, %zmm2 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm4, %zmm7, %zmm8 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm6, %zmm7, %zmm11 -; AVX512DQ-ONLY-NEXT: movb $-32, %al -; AVX512DQ-ONLY-NEXT: kmovw %eax, %k2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm17 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm18 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm12 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm21 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm1 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm1 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm3 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm3 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm5 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm5 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm0 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm0 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm22 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm29, %zmm22 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm29 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm29 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm26 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm20 {%k2} -; AVX512DQ-ONLY-NEXT: vinserti32x4 $0, %xmm19, %zmm24, %zmm4 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm31, %zmm4 {%k2} -; AVX512DQ-ONLY-NEXT: vinserti32x4 $0, %xmm15, %zmm27, %zmm6 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, %zmm6 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqa64 %ymm23, %ymm7 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm7 = ymm9[0,1,2,3],ymm7[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqa 64(%rdi), %ymm9 -; AVX512DQ-ONLY-NEXT: vpalignr {{.*#+}} ymm9 = mem[8,9,10,11,12,13,14,15],ymm9[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm9[16,17,18,19,20,21,22,23] -; AVX512DQ-ONLY-NEXT: vextracti128 $1, %ymm9, %xmm9 -; AVX512DQ-ONLY-NEXT: vinserti32x4 $0, %xmm9, %zmm25, %zmm9 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm15, %zmm9 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm7, %zmm15, %zmm19 -; AVX512DQ-ONLY-NEXT: vmovdqa 640(%rdi), %ymm15 -; AVX512DQ-ONLY-NEXT: vpalignr $8, {{[-0-9]+}}(%r{{[sb]}}p), %ymm15, %ymm15 # 32-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # ymm15 = mem[8,9,10,11,12,13,14,15],ymm15[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm15[16,17,18,19,20,21,22,23] -; AVX512DQ-ONLY-NEXT: vmovdqa 1408(%rdi), %ymm7 -; AVX512DQ-ONLY-NEXT: vpalignr {{.*#+}} ymm7 = mem[8,9,10,11,12,13,14,15],ymm7[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm7[16,17,18,19,20,21,22,23] -; AVX512DQ-ONLY-NEXT: vextracti128 $1, %ymm7, %xmm7 -; AVX512DQ-ONLY-NEXT: vinserti32x4 $0, %xmm7, %zmm16, %zmm7 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm16, %zmm7 {%k2} -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm13 = ymm13[0,1,2,3],ymm15[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm13, %zmm15, %zmm13 -; AVX512DQ-ONLY-NEXT: vmovdqa 192(%rdi), %ymm15 -; AVX512DQ-ONLY-NEXT: vpalignr $8, (%rsp), %ymm15, %ymm15 # 32-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # ymm15 = mem[8,9,10,11,12,13,14,15],ymm15[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm15[16,17,18,19,20,21,22,23] -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm10 = ymm10[0,1,2,3],ymm15[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm15, %zmm10 -; AVX512DQ-ONLY-NEXT: vmovdqa 1536(%rdi), %ymm15 -; AVX512DQ-ONLY-NEXT: vpalignr $8, {{[-0-9]+}}(%r{{[sb]}}p), %ymm15, %ymm15 # 32-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # ymm15 = mem[8,9,10,11,12,13,14,15],ymm15[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm15[16,17,18,19,20,21,22,23] -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm15[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm30, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vblendps $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm15, %ymm15 # 32-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # ymm15 = ymm15[0,1,2,3],mem[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vinsertf64x4 $0, %ymm15, %zmm16, %zmm15 -; AVX512DQ-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm14, %ymm14 # 32-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # ymm14 = ymm14[0,1,2,3],mem[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm14, %zmm16, %zmm14 -; AVX512DQ-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm8, %ymm8 # 32-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # ymm8 = ymm8[0,1,2,3],mem[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm8, %zmm16, %zmm8 -; AVX512DQ-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm11, %ymm11 # 32-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # ymm11 = ymm11[0,1,2,3],mem[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm11, %zmm16, %zmm11 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm21, 192(%rsi) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm12, 128(%rsi) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm18, 64(%rsi) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm17, (%rsi) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, 192(%rdx) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm5, (%rdx) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm3, 64(%rdx) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm1, 128(%rdx) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm20, 192(%rcx) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm26, (%rcx) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm29, 64(%rcx) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm22, 128(%rcx) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, 192(%r8) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm9, (%r8) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm6, 64(%r8) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, 128(%r8) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm28, 192(%r9) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, (%r9) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 64(%r9) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 128(%r9) -; AVX512DQ-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, 192(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm10, (%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm13, 64(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm19, 128(%rax) -; AVX512DQ-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm11, 128(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm8, 192(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm14, (%rax) -; AVX512DQ-ONLY-NEXT: vmovaps %zmm15, 64(%rax) -; AVX512DQ-ONLY-NEXT: addq $2216, %rsp # imm = 0x8A8 -; AVX512DQ-ONLY-NEXT: vzeroupper -; AVX512DQ-ONLY-NEXT: retq -; -; AVX512BW-ONLY-LABEL: load_i64_stride7_vf32: -; AVX512BW-ONLY: # %bb.0: -; AVX512BW-ONLY-NEXT: subq $2152, %rsp # imm = 0x868 -; AVX512BW-ONLY-NEXT: vmovdqa64 1664(%rdi), %zmm21 -; AVX512BW-ONLY-NEXT: vmovdqa64 1600(%rdi), %zmm31 -; AVX512BW-ONLY-NEXT: vmovdqa64 1216(%rdi), %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqa64 1152(%rdi), %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqa64 1088(%rdi), %zmm12 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 1024(%rdi), %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 768(%rdi), %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqa64 704(%rdi), %zmm10 -; AVX512BW-ONLY-NEXT: vmovdqa64 640(%rdi), %zmm11 -; AVX512BW-ONLY-NEXT: vmovaps 576(%rdi), %zmm0 -; AVX512BW-ONLY-NEXT: vmovups %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 320(%rdi), %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqa64 256(%rdi), %zmm5 -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm7 = [10,3,10,3,10,3,10,3] -; AVX512BW-ONLY-NEXT: # zmm7 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm8 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm0, %zmm7, %zmm8 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm8 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm1, %zmm7, %zmm8 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm8 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm7, %zmm8 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermi2q %zmm21, %zmm31, %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm7 = [11,4,11,4,11,4,11,4] -; AVX512BW-ONLY-NEXT: # zmm7 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm8 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm7, %zmm8 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm13 -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm7 = [13,6,13,6,13,6,13,6] -; AVX512BW-ONLY-NEXT: # zmm7 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm8 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm1, %zmm13, %zmm8 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm8 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm18 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm0, %zmm13, %zmm18 -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm19 = [12,5,12,5,12,5,12,5] -; AVX512BW-ONLY-NEXT: # zmm19 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm17 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm1, %zmm19, %zmm17 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm22 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm0, %zmm19, %zmm22 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm22, %zmm23 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm16 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm1, %zmm7, %zmm16 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm22 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm0, %zmm7, %zmm22 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm22, %zmm24 -; AVX512BW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm28 = [0,7,14,0,0,7,14,0] -; AVX512BW-ONLY-NEXT: # zmm28 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm15 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm1, %zmm28, %zmm15 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm25 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm0, %zmm28, %zmm25 -; AVX512BW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm29 = [9,0,7,0,9,0,7,0] -; AVX512BW-ONLY-NEXT: # zmm29 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm1, %zmm26 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm10, %zmm29, %zmm26 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm30 -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm4 = [2,9,2,9,2,9,2,9] -; AVX512BW-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm1, %zmm4, %zmm10 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm9 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm8, %zmm29, %zmm9 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm0, %zmm4, %zmm8 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm1 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm12, %zmm7, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm14 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm14, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm11, %zmm7, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 192(%rdi), %zmm22 -; AVX512BW-ONLY-NEXT: vmovdqa64 128(%rdi), %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm7, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm31, %zmm5 -; AVX512BW-ONLY-NEXT: vpermi2q %zmm21, %zmm31, %zmm13 -; AVX512BW-ONLY-NEXT: vmovdqa64 1536(%rdi), %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqa64 1472(%rdi), %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm3, %zmm7, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm31 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm19, %zmm31 -; AVX512BW-ONLY-NEXT: vpermi2q %zmm21, %zmm5, %zmm19 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm19, %zmm26 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm27 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm7, %zmm27 -; AVX512BW-ONLY-NEXT: vpermi2q %zmm21, %zmm5, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm20 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm28, %zmm20 -; AVX512BW-ONLY-NEXT: vpermi2q %zmm21, %zmm5, %zmm28 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm12 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm6, %zmm29, %zmm12 -; AVX512BW-ONLY-NEXT: vpermi2q %zmm5, %zmm21, %zmm29 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm21, %zmm4, %zmm5 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm21 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm4, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqa64 384(%rdi), %zmm2 -; AVX512BW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [0,5,6,9,0,5,6,9] -; AVX512BW-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm4, %zmm5 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 832(%rdi), %zmm5 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm5, %zmm4, %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 1280(%rdi), %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm6, %zmm4, %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 1728(%rdi), %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm4, %zmm19 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm19, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [0,5,6,10,0,5,6,10] -; AVX512BW-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm6, %zmm4, %zmm19 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm19, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm5, %zmm4, %zmm19 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm19, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm4, %zmm18 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm18, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm4, %zmm13 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [0,5,6,11,0,5,6,11] -; AVX512BW-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm6, %zmm4, %zmm31 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm5, %zmm4, %zmm17 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm17, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm4, %zmm23 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm23, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm4, %zmm26 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm26, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [0,5,6,12,0,5,6,12] -; AVX512BW-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm6, %zmm4, %zmm27 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm5, %zmm4, %zmm16 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm16, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm4, %zmm24 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm24, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm4, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [4,5,6,13,4,5,6,13] -; AVX512BW-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm6, %zmm4, %zmm20 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm5, %zmm4, %zmm15 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm15, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm4, %zmm25 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm25, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm4, %zmm28 -; AVX512BW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [4,5,6,14,4,5,6,14] -; AVX512BW-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm6, %zmm4, %zmm12 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm5, %zmm4, %zmm30 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm30, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm4, %zmm9 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm4, %zmm29 -; AVX512BW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [4,5,8,15,4,5,8,15] -; AVX512BW-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm5, %zmm4, %zmm10 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm4, %zmm8 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm4, %zmm21 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm21, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm6, %zmm4, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: movb $24, %al -; AVX512BW-ONLY-NEXT: kmovd %eax, %k1 -; AVX512BW-ONLY-NEXT: vmovdqa64 512(%rdi), %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqa64 448(%rdi), %zmm15 -; AVX512BW-ONLY-NEXT: vmovdqa64 {{.*#+}} ymm21 = <0,7,14,u> -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm15, %zmm24 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm21, %zmm24 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm0 -; AVX512BW-ONLY-NEXT: vshufi64x2 {{.*#+}} zmm24 {%k1} = zmm14[4,5,4,5],zmm11[4,5,4,5] -; AVX512BW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm11 = [14,0,0,7,14,0,0,7] -; AVX512BW-ONLY-NEXT: # zmm11 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm14, %zmm13 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm0, %zmm11, %zmm13 -; AVX512BW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm17 = [7,0,9,0,7,0,9,0] -; AVX512BW-ONLY-NEXT: # zmm17 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm26 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm14, %zmm17, %zmm26 -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} ymm19 = [4,11,4,11] -; AVX512BW-ONLY-NEXT: # ymm19 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm0, %zmm19, %zmm14 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm14, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%rdi), %zmm4 -; AVX512BW-ONLY-NEXT: vmovdqa64 (%rdi), %zmm14 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm14, %zmm18 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm4, %zmm21, %zmm18 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vshufi64x2 {{.*#+}} zmm18 {%k1} = zmm0[4,5,4,5],zmm22[4,5,4,5] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm23 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm11, %zmm23 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm22, %zmm30 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm0, %zmm17, %zmm30 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm19, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 960(%rdi), %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqa64 896(%rdi), %zmm10 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm16 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm21, %zmm16 -; AVX512BW-ONLY-NEXT: vmovdqa64 1408(%rdi), %zmm5 -; AVX512BW-ONLY-NEXT: vmovdqa64 1344(%rdi), %zmm8 -; AVX512BW-ONLY-NEXT: vpermi2q %zmm5, %zmm8, %zmm21 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vshufi64x2 {{.*#+}} zmm21 {%k1} = zmm6[4,5,4,5],zmm3[4,5,4,5] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm1, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm22 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm11, %zmm0 -; AVX512BW-ONLY-NEXT: vpermi2q %zmm3, %zmm6, %zmm11 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm22, %zmm25 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm1, %zmm17, %zmm25 -; AVX512BW-ONLY-NEXT: vpermi2q %zmm6, %zmm3, %zmm17 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm3, %zmm19, %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vshufi64x2 {{.*#+}} zmm16 {%k1} = zmm1[4,5,4,5],zmm22[4,5,4,5] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm19, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa 912(%rdi), %xmm1 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0,1],mem[2,3] -; AVX512BW-ONLY-NEXT: vinserti32x4 $0, %xmm1, %zmm0, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa 464(%rdi), %xmm0 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],mem[2,3] -; AVX512BW-ONLY-NEXT: vinserti32x4 $0, %xmm0, %zmm13, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa 16(%rdi), %xmm0 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],mem[2,3] -; AVX512BW-ONLY-NEXT: vinserti32x4 $0, %xmm0, %zmm23, %zmm23 -; AVX512BW-ONLY-NEXT: vmovdqa 1360(%rdi), %xmm0 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],mem[2,3] -; AVX512BW-ONLY-NEXT: vinserti32x4 $0, %xmm0, %zmm11, %zmm22 -; AVX512BW-ONLY-NEXT: vinserti128 $1, 1088(%rdi), %ymm0, %ymm0 -; AVX512BW-ONLY-NEXT: vmovdqa 1024(%rdi), %ymm1 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1,2,3,4,5],ymm0[6,7] -; AVX512BW-ONLY-NEXT: vmovdqa64 %ymm1, %ymm19 -; AVX512BW-ONLY-NEXT: vmovdqa {{.*#+}} xmm1 = [4,11] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm11 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm1, %zmm11 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm11[0,1,2,3],ymm0[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm20, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vinserti128 $1, 640(%rdi), %ymm0, %ymm0 -; AVX512BW-ONLY-NEXT: vmovdqa 576(%rdi), %ymm3 -; AVX512BW-ONLY-NEXT: vmovdqu %ymm3, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3,4,5],ymm0[6,7] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm15, %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm1, %zmm3 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3],ymm0[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vinserti128 $1, 192(%rdi), %ymm0, %ymm0 -; AVX512BW-ONLY-NEXT: vmovdqa 128(%rdi), %ymm3 -; AVX512BW-ONLY-NEXT: vmovdqu %ymm3, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3,4,5],ymm0[6,7] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm14, %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm4, %zmm1, %zmm3 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3],ymm0[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vinserti128 $1, 1536(%rdi), %ymm0, %ymm0 -; AVX512BW-ONLY-NEXT: vmovdqa 1472(%rdi), %ymm3 -; AVX512BW-ONLY-NEXT: vmovdqu %ymm3, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3,4,5],ymm0[6,7] -; AVX512BW-ONLY-NEXT: vpermi2q %zmm5, %zmm8, %zmm1 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm28, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa {{.*#+}} ymm0 = <9,0,7,u> -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm15, %zmm0, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqa {{.*#+}} xmm1 = [5,12] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm15, %zmm13 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm1, %zmm13 -; AVX512BW-ONLY-NEXT: vmovdqa {{.*#+}} xmm6 = [6,13] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm6, %zmm15 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm14, %zmm0, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm14, %zmm11 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm4, %zmm1, %zmm11 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm4, %zmm6, %zmm14 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm4 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm10, %zmm0, %zmm4 -; AVX512BW-ONLY-NEXT: vpermi2q %zmm8, %zmm5, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm9 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm1, %zmm9 -; AVX512BW-ONLY-NEXT: vpermi2q %zmm5, %zmm8, %zmm1 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm5, %zmm6, %zmm8 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm6, %zmm10 -; AVX512BW-ONLY-NEXT: vmovdqa 1088(%rdi), %ymm5 -; AVX512BW-ONLY-NEXT: vpalignr {{.*#+}} ymm5 = ymm19[8,9,10,11,12,13,14,15],ymm5[0,1,2,3,4,5,6,7],ymm19[24,25,26,27,28,29,30,31],ymm5[16,17,18,19,20,21,22,23] -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm5 = ymm9[0,1,2,3],ymm5[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm5, %zmm12, %zmm28 -; AVX512BW-ONLY-NEXT: movb $-32, %al -; AVX512BW-ONLY-NEXT: kmovd %eax, %k2 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm18 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm24 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm16 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm21 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm4 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm4 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm3 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm3 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm2 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm2 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm0 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm0 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm31, %zmm12 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm19 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm23 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm22 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqa 960(%rdi), %ymm6 -; AVX512BW-ONLY-NEXT: vpalignr {{.*#+}} ymm6 = mem[8,9,10,11,12,13,14,15],ymm6[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm6[16,17,18,19,20,21,22,23] -; AVX512BW-ONLY-NEXT: vextracti128 $1, %ymm6, %xmm6 -; AVX512BW-ONLY-NEXT: vinserti32x4 $0, %xmm6, %zmm25, %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm27, %zmm6 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqa 512(%rdi), %ymm7 -; AVX512BW-ONLY-NEXT: vpalignr {{.*#+}} ymm7 = mem[8,9,10,11,12,13,14,15],ymm7[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm7[16,17,18,19,20,21,22,23] -; AVX512BW-ONLY-NEXT: vextracti128 $1, %ymm7, %xmm7 -; AVX512BW-ONLY-NEXT: vinserti32x4 $0, %xmm7, %zmm26, %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm7 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqa 64(%rdi), %ymm9 -; AVX512BW-ONLY-NEXT: vpalignr {{.*#+}} ymm9 = mem[8,9,10,11,12,13,14,15],ymm9[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm9[16,17,18,19,20,21,22,23] -; AVX512BW-ONLY-NEXT: vextracti128 $1, %ymm9, %xmm9 -; AVX512BW-ONLY-NEXT: vinserti32x4 $0, %xmm9, %zmm30, %zmm9 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm9 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqa64 1408(%rdi), %ymm20 -; AVX512BW-ONLY-NEXT: vpalignr {{.*#+}} ymm20 = mem[8,9,10,11,12,13,14,15],ymm20[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm20[16,17,18,19,20,21,22,23] -; AVX512BW-ONLY-NEXT: vextracti32x4 $1, %ymm20, %xmm20 -; AVX512BW-ONLY-NEXT: vinserti32x4 $0, %xmm20, %zmm17, %zmm17 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm17 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqa64 640(%rdi), %ymm20 -; AVX512BW-ONLY-NEXT: vpalignr $8, {{[-0-9]+}}(%r{{[sb]}}p), %ymm20, %ymm5 # 32-byte Folded Reload -; AVX512BW-ONLY-NEXT: # ymm5 = mem[8,9,10,11,12,13,14,15],ymm20[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm20[16,17,18,19,20,21,22,23] -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm5 = ymm13[0,1,2,3],ymm5[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm5, %zmm13, %zmm5 -; AVX512BW-ONLY-NEXT: vmovdqa 192(%rdi), %ymm13 -; AVX512BW-ONLY-NEXT: vpalignr $8, {{[-0-9]+}}(%r{{[sb]}}p), %ymm13, %ymm13 # 32-byte Folded Reload -; AVX512BW-ONLY-NEXT: # ymm13 = mem[8,9,10,11,12,13,14,15],ymm13[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm13[16,17,18,19,20,21,22,23] -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm11 = ymm11[0,1,2,3],ymm13[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm11, %zmm13, %zmm11 -; AVX512BW-ONLY-NEXT: vmovdqa 1536(%rdi), %ymm13 -; AVX512BW-ONLY-NEXT: vpalignr $8, {{[-0-9]+}}(%r{{[sb]}}p), %ymm13, %ymm13 # 32-byte Folded Reload -; AVX512BW-ONLY-NEXT: # ymm13 = mem[8,9,10,11,12,13,14,15],ymm13[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm13[16,17,18,19,20,21,22,23] -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm13[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm29, %zmm1 -; AVX512BW-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm15, %ymm13 # 32-byte Folded Reload -; AVX512BW-ONLY-NEXT: # ymm13 = ymm15[0,1,2,3],mem[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm13, %zmm15, %zmm13 -; AVX512BW-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm14, %ymm14 # 32-byte Folded Reload -; AVX512BW-ONLY-NEXT: # ymm14 = ymm14[0,1,2,3],mem[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm14, %zmm15, %zmm14 -; AVX512BW-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm8, %ymm8 # 32-byte Folded Reload -; AVX512BW-ONLY-NEXT: # ymm8 = ymm8[0,1,2,3],mem[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm8, %zmm15, %zmm8 -; AVX512BW-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm10, %ymm10 # 32-byte Folded Reload -; AVX512BW-ONLY-NEXT: # ymm10 = ymm10[0,1,2,3],mem[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm15, %zmm10 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm21, 192(%rsi) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm16, 128(%rsi) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm24, 64(%rsi) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm18, (%rsi) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, 192(%rdx) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, (%rdx) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm3, 64(%rdx) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, 128(%rdx) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm22, 192(%rcx) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm23, (%rcx) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm19, 64(%rcx) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm12, 128(%rcx) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm17, 192(%r8) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm9, (%r8) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, 64(%r8) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm6, 128(%r8) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 192(%r9) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, (%r9) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 64(%r9) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 128(%r9) -; AVX512BW-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm1, 192(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm11, (%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, 64(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm28, 128(%rax) -; AVX512BW-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, 128(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm8, 192(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm14, (%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm13, 64(%rax) -; AVX512BW-ONLY-NEXT: addq $2152, %rsp # imm = 0x868 -; AVX512BW-ONLY-NEXT: vzeroupper -; AVX512BW-ONLY-NEXT: retq +; AVX512F-LABEL: load_i64_stride7_vf32: +; AVX512F: # %bb.0: +; AVX512F-NEXT: subq $2216, %rsp # imm = 0x8A8 +; AVX512F-NEXT: vmovdqa64 1664(%rdi), %zmm21 +; AVX512F-NEXT: vmovdqa64 1600(%rdi), %zmm3 +; AVX512F-NEXT: vmovdqa64 1216(%rdi), %zmm1 +; AVX512F-NEXT: vmovdqa64 1152(%rdi), %zmm6 +; AVX512F-NEXT: vmovdqa64 1088(%rdi), %zmm11 +; AVX512F-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovaps 1024(%rdi), %zmm0 +; AVX512F-NEXT: vmovups %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 768(%rdi), %zmm2 +; AVX512F-NEXT: vmovdqa64 704(%rdi), %zmm9 +; AVX512F-NEXT: vmovdqa64 640(%rdi), %zmm15 +; AVX512F-NEXT: vmovdqa64 576(%rdi), %zmm10 +; AVX512F-NEXT: vmovdqa64 320(%rdi), %zmm0 +; AVX512F-NEXT: vmovdqa64 256(%rdi), %zmm26 +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm7 = [10,3,10,3,10,3,10,3] +; AVX512F-NEXT: # zmm7 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm26, %zmm8 +; AVX512F-NEXT: vpermt2q %zmm0, %zmm7, %zmm8 +; AVX512F-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm9, %zmm8 +; AVX512F-NEXT: vpermt2q %zmm2, %zmm7, %zmm8 +; AVX512F-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm6, %zmm8 +; AVX512F-NEXT: vpermt2q %zmm1, %zmm7, %zmm8 +; AVX512F-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermi2q %zmm21, %zmm3, %zmm7 +; AVX512F-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm7 = [11,4,11,4,11,4,11,4] +; AVX512F-NEXT: # zmm7 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm6, %zmm8 +; AVX512F-NEXT: vpermt2q %zmm1, %zmm7, %zmm8 +; AVX512F-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm7, %zmm13 +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm7 = [13,6,13,6,13,6,13,6] +; AVX512F-NEXT: # zmm7 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm9, %zmm8 +; AVX512F-NEXT: vpermt2q %zmm2, %zmm13, %zmm8 +; AVX512F-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm26, %zmm8 +; AVX512F-NEXT: vpermt2q %zmm0, %zmm13, %zmm8 +; AVX512F-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm20 = [12,5,12,5,12,5,12,5] +; AVX512F-NEXT: # zmm20 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm9, %zmm18 +; AVX512F-NEXT: vpermt2q %zmm2, %zmm20, %zmm18 +; AVX512F-NEXT: vmovdqa64 %zmm26, %zmm23 +; AVX512F-NEXT: vpermt2q %zmm0, %zmm20, %zmm23 +; AVX512F-NEXT: vmovdqa64 %zmm9, %zmm17 +; AVX512F-NEXT: vpermt2q %zmm2, %zmm7, %zmm17 +; AVX512F-NEXT: vmovdqa64 %zmm26, %zmm25 +; AVX512F-NEXT: vpermt2q %zmm0, %zmm7, %zmm25 +; AVX512F-NEXT: vbroadcasti64x4 {{.*#+}} zmm28 = [0,7,14,0,0,7,14,0] +; AVX512F-NEXT: # zmm28 = mem[0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm9, %zmm8 +; AVX512F-NEXT: vpermt2q %zmm2, %zmm28, %zmm8 +; AVX512F-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm26, %zmm16 +; AVX512F-NEXT: vpermt2q %zmm0, %zmm28, %zmm16 +; AVX512F-NEXT: vbroadcasti64x4 {{.*#+}} zmm30 = [9,0,7,0,9,0,7,0] +; AVX512F-NEXT: # zmm30 = mem[0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm14 +; AVX512F-NEXT: vpermt2q %zmm9, %zmm30, %zmm14 +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm4 = [2,9,2,9,2,9,2,9] +; AVX512F-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vpermt2q %zmm2, %zmm4, %zmm9 +; AVX512F-NEXT: vmovdqa64 %zmm0, %zmm8 +; AVX512F-NEXT: vpermt2q %zmm26, %zmm30, %zmm8 +; AVX512F-NEXT: vpermt2q %zmm0, %zmm4, %zmm26 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm7, %zmm2 +; AVX512F-NEXT: vpermt2q %zmm11, %zmm7, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm10, %zmm11 +; AVX512F-NEXT: vmovdqa64 %zmm10, %zmm0 +; AVX512F-NEXT: vmovdqa64 %zmm15, %zmm10 +; AVX512F-NEXT: vpermt2q %zmm15, %zmm7, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 192(%rdi), %zmm24 +; AVX512F-NEXT: vmovdqa64 128(%rdi), %zmm12 +; AVX512F-NEXT: vmovdqa64 %zmm12, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm24, %zmm7, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm3, %zmm5 +; AVX512F-NEXT: vpermi2q %zmm21, %zmm3, %zmm13 +; AVX512F-NEXT: vmovdqa64 1536(%rdi), %zmm15 +; AVX512F-NEXT: vmovdqa64 1472(%rdi), %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm15, %zmm7, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm6, %zmm29 +; AVX512F-NEXT: vpermt2q %zmm1, %zmm20, %zmm29 +; AVX512F-NEXT: vpermi2q %zmm21, %zmm3, %zmm20 +; AVX512F-NEXT: vmovdqa64 %zmm6, %zmm31 +; AVX512F-NEXT: vpermt2q %zmm1, %zmm7, %zmm31 +; AVX512F-NEXT: vpermi2q %zmm21, %zmm3, %zmm2 +; AVX512F-NEXT: vmovdqa64 %zmm6, %zmm22 +; AVX512F-NEXT: vpermt2q %zmm1, %zmm28, %zmm22 +; AVX512F-NEXT: vpermi2q %zmm21, %zmm3, %zmm28 +; AVX512F-NEXT: vmovdqa64 %zmm1, %zmm3 +; AVX512F-NEXT: vpermt2q %zmm6, %zmm30, %zmm3 +; AVX512F-NEXT: vmovdqa64 %zmm6, %zmm0 +; AVX512F-NEXT: vpermi2q %zmm5, %zmm21, %zmm30 +; AVX512F-NEXT: vpermt2q %zmm21, %zmm4, %zmm5 +; AVX512F-NEXT: vmovdqa64 %zmm5, %zmm21 +; AVX512F-NEXT: vpermt2q %zmm1, %zmm4, %zmm0 +; AVX512F-NEXT: vmovdqa64 384(%rdi), %zmm1 +; AVX512F-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [0,5,6,9,0,5,6,9] +; AVX512F-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm1, %zmm4, %zmm5 +; AVX512F-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 832(%rdi), %zmm5 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm5, %zmm4, %zmm6 +; AVX512F-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 1280(%rdi), %zmm6 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm6, %zmm4, %zmm7 +; AVX512F-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 1728(%rdi), %zmm7 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm27 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm7, %zmm4, %zmm27 +; AVX512F-NEXT: vmovdqu64 %zmm27, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [0,5,6,10,0,5,6,10] +; AVX512F-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm6, %zmm4, %zmm19 +; AVX512F-NEXT: vmovdqu64 %zmm19, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm5, %zmm4, %zmm19 +; AVX512F-NEXT: vmovdqu64 %zmm19, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm1, %zmm4, %zmm19 +; AVX512F-NEXT: vmovdqu64 %zmm19, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm7, %zmm4, %zmm13 +; AVX512F-NEXT: vmovdqu64 %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [0,5,6,11,0,5,6,11] +; AVX512F-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vpermt2q %zmm6, %zmm4, %zmm29 +; AVX512F-NEXT: vpermt2q %zmm5, %zmm4, %zmm18 +; AVX512F-NEXT: vmovdqu64 %zmm18, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm1, %zmm4, %zmm23 +; AVX512F-NEXT: vmovdqu64 %zmm23, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm7, %zmm4, %zmm20 +; AVX512F-NEXT: vmovdqu64 %zmm20, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [0,5,6,12,0,5,6,12] +; AVX512F-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vpermt2q %zmm6, %zmm4, %zmm31 +; AVX512F-NEXT: vpermt2q %zmm5, %zmm4, %zmm17 +; AVX512F-NEXT: vmovdqu64 %zmm17, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm1, %zmm4, %zmm25 +; AVX512F-NEXT: vmovdqu64 %zmm25, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm7, %zmm4, %zmm2 +; AVX512F-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [4,5,6,13,4,5,6,13] +; AVX512F-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vpermt2q %zmm6, %zmm4, %zmm22 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm5, %zmm4, %zmm19 +; AVX512F-NEXT: vpermt2q %zmm1, %zmm4, %zmm16 +; AVX512F-NEXT: vmovdqu64 %zmm16, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm7, %zmm4, %zmm28 +; AVX512F-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [4,5,6,14,4,5,6,14] +; AVX512F-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vpermt2q %zmm6, %zmm4, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm5, %zmm4, %zmm14 +; AVX512F-NEXT: vmovdqu64 %zmm14, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm1, %zmm4, %zmm8 +; AVX512F-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm7, %zmm4, %zmm30 +; AVX512F-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [4,5,8,15,4,5,8,15] +; AVX512F-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vpermt2q %zmm5, %zmm4, %zmm9 +; AVX512F-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm1, %zmm4, %zmm26 +; AVX512F-NEXT: vmovdqu64 %zmm26, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm7, %zmm4, %zmm21 +; AVX512F-NEXT: vmovdqu64 %zmm21, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm6, %zmm4, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: movb $24, %al +; AVX512F-NEXT: kmovw %eax, %k1 +; AVX512F-NEXT: vmovdqa64 512(%rdi), %zmm5 +; AVX512F-NEXT: vmovdqa64 448(%rdi), %zmm7 +; AVX512F-NEXT: vmovdqa64 {{.*#+}} ymm21 = <0,7,14,u> +; AVX512F-NEXT: vmovdqa64 %zmm7, %zmm18 +; AVX512F-NEXT: vpermt2q %zmm5, %zmm21, %zmm18 +; AVX512F-NEXT: vmovdqa64 %zmm10, %zmm0 +; AVX512F-NEXT: vshufi64x2 {{.*#+}} zmm18 {%k1} = zmm11[4,5,4,5],zmm10[4,5,4,5] +; AVX512F-NEXT: vbroadcasti64x4 {{.*#+}} zmm10 = [14,0,0,7,14,0,0,7] +; AVX512F-NEXT: # zmm10 = mem[0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm11, %zmm26 +; AVX512F-NEXT: vpermt2q %zmm0, %zmm10, %zmm26 +; AVX512F-NEXT: vbroadcasti64x4 {{.*#+}} zmm16 = [7,0,9,0,7,0,9,0] +; AVX512F-NEXT: # zmm16 = mem[0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm0, %zmm27 +; AVX512F-NEXT: vpermt2q %zmm11, %zmm16, %zmm27 +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} ymm20 = [4,11,4,11] +; AVX512F-NEXT: # ymm20 = mem[0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vpermt2q %zmm0, %zmm20, %zmm11 +; AVX512F-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 64(%rdi), %zmm1 +; AVX512F-NEXT: vmovdqa64 (%rdi), %zmm14 +; AVX512F-NEXT: vmovdqa64 %zmm14, %zmm17 +; AVX512F-NEXT: vpermt2q %zmm1, %zmm21, %zmm17 +; AVX512F-NEXT: vshufi64x2 {{.*#+}} zmm17 {%k1} = zmm12[4,5,4,5],zmm24[4,5,4,5] +; AVX512F-NEXT: vmovdqa64 %zmm12, %zmm23 +; AVX512F-NEXT: vpermt2q %zmm24, %zmm10, %zmm23 +; AVX512F-NEXT: vmovdqa64 %zmm24, %zmm25 +; AVX512F-NEXT: vpermt2q %zmm12, %zmm16, %zmm25 +; AVX512F-NEXT: vpermt2q %zmm24, %zmm20, %zmm12 +; AVX512F-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 960(%rdi), %zmm6 +; AVX512F-NEXT: vmovdqa64 896(%rdi), %zmm11 +; AVX512F-NEXT: vmovdqa64 %zmm11, %zmm12 +; AVX512F-NEXT: vpermt2q %zmm6, %zmm21, %zmm12 +; AVX512F-NEXT: vmovdqa64 1408(%rdi), %zmm4 +; AVX512F-NEXT: vmovdqa64 1344(%rdi), %zmm8 +; AVX512F-NEXT: vpermi2q %zmm4, %zmm8, %zmm21 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload +; AVX512F-NEXT: vshufi64x2 {{.*#+}} zmm21 {%k1} = zmm3[4,5,4,5],zmm15[4,5,4,5] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm0 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm9, %zmm10, %zmm0 +; AVX512F-NEXT: vpermi2q %zmm15, %zmm3, %zmm10 +; AVX512F-NEXT: vmovdqa64 %zmm9, %zmm24 +; AVX512F-NEXT: vpermt2q %zmm2, %zmm16, %zmm24 +; AVX512F-NEXT: vpermi2q %zmm3, %zmm15, %zmm16 +; AVX512F-NEXT: vpermt2q %zmm15, %zmm20, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vshufi64x2 {{.*#+}} zmm12 {%k1} = zmm2[4,5,4,5],zmm9[4,5,4,5] +; AVX512F-NEXT: vpermt2q %zmm9, %zmm20, %zmm2 +; AVX512F-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa 912(%rdi), %xmm2 +; AVX512F-NEXT: vpblendd {{.*#+}} xmm2 = xmm2[0,1],mem[2,3] +; AVX512F-NEXT: vinserti32x4 $0, %xmm2, %zmm0, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa 464(%rdi), %xmm0 +; AVX512F-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],mem[2,3] +; AVX512F-NEXT: vinserti32x4 $0, %xmm0, %zmm26, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa 16(%rdi), %xmm0 +; AVX512F-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],mem[2,3] +; AVX512F-NEXT: vinserti32x4 $0, %xmm0, %zmm23, %zmm26 +; AVX512F-NEXT: vmovdqa 1360(%rdi), %xmm0 +; AVX512F-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],mem[2,3] +; AVX512F-NEXT: vinserti32x4 $0, %xmm0, %zmm10, %zmm20 +; AVX512F-NEXT: vinserti128 $1, 1088(%rdi), %ymm0, %ymm0 +; AVX512F-NEXT: vmovdqa 1024(%rdi), %ymm2 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm0 = ymm2[0,1,2,3,4,5],ymm0[6,7] +; AVX512F-NEXT: vmovdqa {{.*#+}} xmm10 = [4,11] +; AVX512F-NEXT: vmovdqa64 %zmm11, %zmm13 +; AVX512F-NEXT: vpermt2q %zmm6, %zmm10, %zmm13 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm0 = ymm13[0,1,2,3],ymm0[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm0, %zmm22, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vinserti128 $1, 640(%rdi), %ymm0, %ymm0 +; AVX512F-NEXT: vmovdqa 576(%rdi), %ymm3 +; AVX512F-NEXT: vmovdqu %ymm3, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3,4,5],ymm0[6,7] +; AVX512F-NEXT: vmovdqa64 %zmm7, %zmm3 +; AVX512F-NEXT: vpermt2q %zmm5, %zmm10, %zmm3 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3],ymm0[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm0, %zmm19, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vinserti128 $1, 192(%rdi), %ymm0, %ymm0 +; AVX512F-NEXT: vmovdqa 128(%rdi), %ymm3 +; AVX512F-NEXT: vmovdqu %ymm3, (%rsp) # 32-byte Spill +; AVX512F-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3,4,5],ymm0[6,7] +; AVX512F-NEXT: vmovdqa64 %zmm14, %zmm3 +; AVX512F-NEXT: vpermt2q %zmm1, %zmm10, %zmm3 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3],ymm0[4,5,6,7] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload +; AVX512F-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vinserti128 $1, 1536(%rdi), %ymm0, %ymm0 +; AVX512F-NEXT: vmovdqa 1472(%rdi), %ymm3 +; AVX512F-NEXT: vmovdqu %ymm3, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3,4,5],ymm0[6,7] +; AVX512F-NEXT: vpermi2q %zmm4, %zmm8, %zmm10 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm0 = ymm10[0,1,2,3],ymm0[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm0, %zmm28, %zmm28 +; AVX512F-NEXT: vmovdqa 1088(%rdi), %ymm0 +; AVX512F-NEXT: vpalignr {{.*#+}} ymm0 = ymm2[8,9,10,11,12,13,14,15],ymm0[0,1,2,3,4,5,6,7],ymm2[24,25,26,27,28,29,30,31],ymm0[16,17,18,19,20,21,22,23] +; AVX512F-NEXT: vmovdqa64 %ymm0, %ymm23 +; AVX512F-NEXT: vmovdqa {{.*#+}} ymm0 = <9,0,7,u> +; AVX512F-NEXT: vmovdqa64 %zmm5, %zmm3 +; AVX512F-NEXT: vmovdqa64 %zmm7, %zmm9 +; AVX512F-NEXT: vpermt2q %zmm7, %zmm0, %zmm3 +; AVX512F-NEXT: vmovdqa {{.*#+}} xmm2 = [5,12] +; AVX512F-NEXT: vmovdqa64 %zmm7, %zmm13 +; AVX512F-NEXT: vpermt2q %zmm5, %zmm2, %zmm13 +; AVX512F-NEXT: vmovdqa {{.*#+}} xmm7 = [6,13] +; AVX512F-NEXT: vpermt2q %zmm5, %zmm7, %zmm9 +; AVX512F-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm1, %zmm5 +; AVX512F-NEXT: vpermt2q %zmm14, %zmm0, %zmm5 +; AVX512F-NEXT: vmovdqa64 %zmm14, %zmm10 +; AVX512F-NEXT: vpermt2q %zmm1, %zmm2, %zmm10 +; AVX512F-NEXT: vpermt2q %zmm1, %zmm7, %zmm14 +; AVX512F-NEXT: vmovdqa64 %zmm6, %zmm1 +; AVX512F-NEXT: vpermt2q %zmm11, %zmm0, %zmm1 +; AVX512F-NEXT: vpermi2q %zmm8, %zmm4, %zmm0 +; AVX512F-NEXT: vmovdqa 960(%rdi), %ymm15 +; AVX512F-NEXT: vpalignr {{.*#+}} ymm15 = mem[8,9,10,11,12,13,14,15],ymm15[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm15[16,17,18,19,20,21,22,23] +; AVX512F-NEXT: vextracti32x4 $1, %ymm15, %xmm19 +; AVX512F-NEXT: vmovdqa 512(%rdi), %ymm15 +; AVX512F-NEXT: vpalignr {{.*#+}} ymm15 = mem[8,9,10,11,12,13,14,15],ymm15[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm15[16,17,18,19,20,21,22,23] +; AVX512F-NEXT: vextracti128 $1, %ymm15, %xmm15 +; AVX512F-NEXT: vmovdqa64 %zmm11, %zmm9 +; AVX512F-NEXT: vpermt2q %zmm6, %zmm2, %zmm9 +; AVX512F-NEXT: vpermi2q %zmm4, %zmm8, %zmm2 +; AVX512F-NEXT: vpermt2q %zmm4, %zmm7, %zmm8 +; AVX512F-NEXT: vpermt2q %zmm6, %zmm7, %zmm11 +; AVX512F-NEXT: movb $-32, %al +; AVX512F-NEXT: kmovw %eax, %k2 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm17 {%k2} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm18 {%k2} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm12 {%k2} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm21 {%k2} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm1 {%k1} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm1 {%k2} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm3 {%k1} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm3 {%k2} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm5 {%k1} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm5 {%k2} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm0 {%k1} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm0 {%k2} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm22 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm29, %zmm22 {%k2} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm29 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm29 {%k2} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm26 {%k2} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm20 {%k2} +; AVX512F-NEXT: vinserti32x4 $0, %xmm19, %zmm24, %zmm4 +; AVX512F-NEXT: vmovdqa64 %zmm31, %zmm4 {%k2} +; AVX512F-NEXT: vinserti32x4 $0, %xmm15, %zmm27, %zmm6 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm7, %zmm6 {%k2} +; AVX512F-NEXT: vmovdqa64 %ymm23, %ymm7 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm7 = ymm9[0,1,2,3],ymm7[4,5,6,7] +; AVX512F-NEXT: vmovdqa 64(%rdi), %ymm9 +; AVX512F-NEXT: vpalignr {{.*#+}} ymm9 = mem[8,9,10,11,12,13,14,15],ymm9[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm9[16,17,18,19,20,21,22,23] +; AVX512F-NEXT: vextracti128 $1, %ymm9, %xmm9 +; AVX512F-NEXT: vinserti32x4 $0, %xmm9, %zmm25, %zmm9 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm15, %zmm9 {%k2} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload +; AVX512F-NEXT: vinserti64x4 $0, %ymm7, %zmm15, %zmm19 +; AVX512F-NEXT: vmovdqa 640(%rdi), %ymm15 +; AVX512F-NEXT: vpalignr $8, {{[-0-9]+}}(%r{{[sb]}}p), %ymm15, %ymm15 # 32-byte Folded Reload +; AVX512F-NEXT: # ymm15 = mem[8,9,10,11,12,13,14,15],ymm15[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm15[16,17,18,19,20,21,22,23] +; AVX512F-NEXT: vmovdqa 1408(%rdi), %ymm7 +; AVX512F-NEXT: vpalignr {{.*#+}} ymm7 = mem[8,9,10,11,12,13,14,15],ymm7[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm7[16,17,18,19,20,21,22,23] +; AVX512F-NEXT: vextracti128 $1, %ymm7, %xmm7 +; AVX512F-NEXT: vinserti32x4 $0, %xmm7, %zmm16, %zmm7 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm16, %zmm7 {%k2} +; AVX512F-NEXT: vpblendd {{.*#+}} ymm13 = ymm13[0,1,2,3],ymm15[4,5,6,7] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload +; AVX512F-NEXT: vinserti64x4 $0, %ymm13, %zmm15, %zmm13 +; AVX512F-NEXT: vmovdqa 192(%rdi), %ymm15 +; AVX512F-NEXT: vpalignr $8, (%rsp), %ymm15, %ymm15 # 32-byte Folded Reload +; AVX512F-NEXT: # ymm15 = mem[8,9,10,11,12,13,14,15],ymm15[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm15[16,17,18,19,20,21,22,23] +; AVX512F-NEXT: vpblendd {{.*#+}} ymm10 = ymm10[0,1,2,3],ymm15[4,5,6,7] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload +; AVX512F-NEXT: vinserti64x4 $0, %ymm10, %zmm15, %zmm10 +; AVX512F-NEXT: vmovdqa 1536(%rdi), %ymm15 +; AVX512F-NEXT: vpalignr $8, {{[-0-9]+}}(%r{{[sb]}}p), %ymm15, %ymm15 # 32-byte Folded Reload +; AVX512F-NEXT: # ymm15 = mem[8,9,10,11,12,13,14,15],ymm15[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm15[16,17,18,19,20,21,22,23] +; AVX512F-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm15[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm2, %zmm30, %zmm2 +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload +; AVX512F-NEXT: vblendps $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm15, %ymm15 # 32-byte Folded Reload +; AVX512F-NEXT: # ymm15 = ymm15[0,1,2,3],mem[4,5,6,7] +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload +; AVX512F-NEXT: vinsertf64x4 $0, %ymm15, %zmm16, %zmm15 +; AVX512F-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm14, %ymm14 # 32-byte Folded Reload +; AVX512F-NEXT: # ymm14 = ymm14[0,1,2,3],mem[4,5,6,7] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload +; AVX512F-NEXT: vinserti64x4 $0, %ymm14, %zmm16, %zmm14 +; AVX512F-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm8, %ymm8 # 32-byte Folded Reload +; AVX512F-NEXT: # ymm8 = ymm8[0,1,2,3],mem[4,5,6,7] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload +; AVX512F-NEXT: vinserti64x4 $0, %ymm8, %zmm16, %zmm8 +; AVX512F-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm11, %ymm11 # 32-byte Folded Reload +; AVX512F-NEXT: # ymm11 = ymm11[0,1,2,3],mem[4,5,6,7] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload +; AVX512F-NEXT: vinserti64x4 $0, %ymm11, %zmm16, %zmm11 +; AVX512F-NEXT: vmovdqa64 %zmm21, 192(%rsi) +; AVX512F-NEXT: vmovdqa64 %zmm12, 128(%rsi) +; AVX512F-NEXT: vmovdqa64 %zmm18, 64(%rsi) +; AVX512F-NEXT: vmovdqa64 %zmm17, (%rsi) +; AVX512F-NEXT: vmovdqa64 %zmm0, 192(%rdx) +; AVX512F-NEXT: vmovdqa64 %zmm5, (%rdx) +; AVX512F-NEXT: vmovdqa64 %zmm3, 64(%rdx) +; AVX512F-NEXT: vmovdqa64 %zmm1, 128(%rdx) +; AVX512F-NEXT: vmovdqa64 %zmm20, 192(%rcx) +; AVX512F-NEXT: vmovdqa64 %zmm26, (%rcx) +; AVX512F-NEXT: vmovdqa64 %zmm29, 64(%rcx) +; AVX512F-NEXT: vmovdqa64 %zmm22, 128(%rcx) +; AVX512F-NEXT: vmovdqa64 %zmm7, 192(%r8) +; AVX512F-NEXT: vmovdqa64 %zmm9, (%r8) +; AVX512F-NEXT: vmovdqa64 %zmm6, 64(%r8) +; AVX512F-NEXT: vmovdqa64 %zmm4, 128(%r8) +; AVX512F-NEXT: vmovdqa64 %zmm28, 192(%r9) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, (%r9) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 64(%r9) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 128(%r9) +; AVX512F-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512F-NEXT: vmovdqa64 %zmm2, 192(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm10, (%rax) +; AVX512F-NEXT: vmovdqa64 %zmm13, 64(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm19, 128(%rax) +; AVX512F-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512F-NEXT: vmovdqa64 %zmm11, 128(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm8, 192(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm14, (%rax) +; AVX512F-NEXT: vmovaps %zmm15, 64(%rax) +; AVX512F-NEXT: addq $2216, %rsp # imm = 0x8A8 +; AVX512F-NEXT: vzeroupper +; AVX512F-NEXT: retq ; -; AVX512DQBW-ONLY-LABEL: load_i64_stride7_vf32: -; AVX512DQBW-ONLY: # %bb.0: -; AVX512DQBW-ONLY-NEXT: subq $2152, %rsp # imm = 0x868 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 1664(%rdi), %zmm21 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 1600(%rdi), %zmm31 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 1216(%rdi), %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 1152(%rdi), %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 1088(%rdi), %zmm12 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 1024(%rdi), %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 768(%rdi), %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 704(%rdi), %zmm10 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 640(%rdi), %zmm11 -; AVX512DQBW-ONLY-NEXT: vmovaps 576(%rdi), %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovups %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 320(%rdi), %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 256(%rdi), %zmm5 -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm7 = [10,3,10,3,10,3,10,3] -; AVX512DQBW-ONLY-NEXT: # zmm7 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm0, %zmm7, %zmm8 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm1, %zmm7, %zmm8 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm7, %zmm8 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm21, %zmm31, %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm7 = [11,4,11,4,11,4,11,4] -; AVX512DQBW-ONLY-NEXT: # zmm7 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm7, %zmm8 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm13 -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm7 = [13,6,13,6,13,6,13,6] -; AVX512DQBW-ONLY-NEXT: # zmm7 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm1, %zmm13, %zmm8 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm8 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm18 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm0, %zmm13, %zmm18 -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm19 = [12,5,12,5,12,5,12,5] -; AVX512DQBW-ONLY-NEXT: # zmm19 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm17 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm1, %zmm19, %zmm17 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm22 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm0, %zmm19, %zmm22 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm22, %zmm23 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm16 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm1, %zmm7, %zmm16 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm22 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm0, %zmm7, %zmm22 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm22, %zmm24 -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm28 = [0,7,14,0,0,7,14,0] -; AVX512DQBW-ONLY-NEXT: # zmm28 = mem[0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm15 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm1, %zmm28, %zmm15 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm25 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm0, %zmm28, %zmm25 -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm29 = [9,0,7,0,9,0,7,0] -; AVX512DQBW-ONLY-NEXT: # zmm29 = mem[0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm1, %zmm26 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm10, %zmm29, %zmm26 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm30 -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm4 = [2,9,2,9,2,9,2,9] -; AVX512DQBW-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm1, %zmm4, %zmm10 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm9 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm8, %zmm29, %zmm9 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm0, %zmm4, %zmm8 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm12, %zmm7, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm14 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm14, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm11, %zmm7, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 192(%rdi), %zmm22 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 128(%rdi), %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm7, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm31, %zmm5 -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm21, %zmm31, %zmm13 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 1536(%rdi), %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 1472(%rdi), %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm3, %zmm7, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm31 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm19, %zmm31 -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm21, %zmm5, %zmm19 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm19, %zmm26 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm27 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm7, %zmm27 -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm21, %zmm5, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm20 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm28, %zmm20 -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm21, %zmm5, %zmm28 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm12 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm6, %zmm29, %zmm12 -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm5, %zmm21, %zmm29 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm21, %zmm4, %zmm5 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm21 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm4, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 384(%rdi), %zmm2 -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [0,5,6,9,0,5,6,9] -; AVX512DQBW-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm4, %zmm5 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 832(%rdi), %zmm5 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm5, %zmm4, %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 1280(%rdi), %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm6, %zmm4, %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 1728(%rdi), %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm4, %zmm19 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm19, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [0,5,6,10,0,5,6,10] -; AVX512DQBW-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm6, %zmm4, %zmm19 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm19, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm5, %zmm4, %zmm19 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm19, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm4, %zmm18 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm18, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm4, %zmm13 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [0,5,6,11,0,5,6,11] -; AVX512DQBW-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm6, %zmm4, %zmm31 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm5, %zmm4, %zmm17 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm17, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm4, %zmm23 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm23, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm4, %zmm26 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm26, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [0,5,6,12,0,5,6,12] -; AVX512DQBW-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm6, %zmm4, %zmm27 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm5, %zmm4, %zmm16 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm16, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm4, %zmm24 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm24, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm4, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [4,5,6,13,4,5,6,13] -; AVX512DQBW-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm6, %zmm4, %zmm20 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm5, %zmm4, %zmm15 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm15, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm4, %zmm25 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm25, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm4, %zmm28 -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [4,5,6,14,4,5,6,14] -; AVX512DQBW-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm6, %zmm4, %zmm12 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm5, %zmm4, %zmm30 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm30, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm4, %zmm9 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm4, %zmm29 -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [4,5,8,15,4,5,8,15] -; AVX512DQBW-ONLY-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm5, %zmm4, %zmm10 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm4, %zmm8 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm4, %zmm21 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm21, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm6, %zmm4, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: movb $24, %al -; AVX512DQBW-ONLY-NEXT: kmovd %eax, %k1 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 512(%rdi), %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 448(%rdi), %zmm15 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 {{.*#+}} ymm21 = <0,7,14,u> -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm15, %zmm24 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm21, %zmm24 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm0 -; AVX512DQBW-ONLY-NEXT: vshufi64x2 {{.*#+}} zmm24 {%k1} = zmm14[4,5,4,5],zmm11[4,5,4,5] -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm11 = [14,0,0,7,14,0,0,7] -; AVX512DQBW-ONLY-NEXT: # zmm11 = mem[0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm14, %zmm13 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm0, %zmm11, %zmm13 -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm17 = [7,0,9,0,7,0,9,0] -; AVX512DQBW-ONLY-NEXT: # zmm17 = mem[0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm26 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm14, %zmm17, %zmm26 -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x2 {{.*#+}} ymm19 = [4,11,4,11] -; AVX512DQBW-ONLY-NEXT: # ymm19 = mem[0,1,0,1] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm0, %zmm19, %zmm14 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm14, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%rdi), %zmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 (%rdi), %zmm14 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm14, %zmm18 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm4, %zmm21, %zmm18 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vshufi64x2 {{.*#+}} zmm18 {%k1} = zmm0[4,5,4,5],zmm22[4,5,4,5] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm23 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm11, %zmm23 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm22, %zmm30 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm0, %zmm17, %zmm30 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm19, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 960(%rdi), %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 896(%rdi), %zmm10 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm16 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm21, %zmm16 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 1408(%rdi), %zmm5 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 1344(%rdi), %zmm8 -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm5, %zmm8, %zmm21 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vshufi64x2 {{.*#+}} zmm21 {%k1} = zmm6[4,5,4,5],zmm3[4,5,4,5] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm1, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm22 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm11, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm3, %zmm6, %zmm11 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm22, %zmm25 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm1, %zmm17, %zmm25 -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm6, %zmm3, %zmm17 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm3, %zmm19, %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vshufi64x2 {{.*#+}} zmm16 {%k1} = zmm1[4,5,4,5],zmm22[4,5,4,5] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm19, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa 912(%rdi), %xmm1 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0,1],mem[2,3] -; AVX512DQBW-ONLY-NEXT: vinserti32x4 $0, %xmm1, %zmm0, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa 464(%rdi), %xmm0 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],mem[2,3] -; AVX512DQBW-ONLY-NEXT: vinserti32x4 $0, %xmm0, %zmm13, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa 16(%rdi), %xmm0 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],mem[2,3] -; AVX512DQBW-ONLY-NEXT: vinserti32x4 $0, %xmm0, %zmm23, %zmm23 -; AVX512DQBW-ONLY-NEXT: vmovdqa 1360(%rdi), %xmm0 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],mem[2,3] -; AVX512DQBW-ONLY-NEXT: vinserti32x4 $0, %xmm0, %zmm11, %zmm22 -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, 1088(%rdi), %ymm0, %ymm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa 1024(%rdi), %ymm1 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1,2,3,4,5],ymm0[6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %ymm1, %ymm19 -; AVX512DQBW-ONLY-NEXT: vmovdqa {{.*#+}} xmm1 = [4,11] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm11 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm1, %zmm11 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm11[0,1,2,3],ymm0[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm20, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, 640(%rdi), %ymm0, %ymm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa 576(%rdi), %ymm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu %ymm3, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3,4,5],ymm0[6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm15, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm1, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3],ymm0[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, 192(%rdi), %ymm0, %ymm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa 128(%rdi), %ymm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu %ymm3, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3,4,5],ymm0[6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm14, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm4, %zmm1, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3],ymm0[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, 1536(%rdi), %ymm0, %ymm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa 1472(%rdi), %ymm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu %ymm3, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3,4,5],ymm0[6,7] -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm5, %zmm8, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm28, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa {{.*#+}} ymm0 = <9,0,7,u> -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm15, %zmm0, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqa {{.*#+}} xmm1 = [5,12] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm15, %zmm13 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm1, %zmm13 -; AVX512DQBW-ONLY-NEXT: vmovdqa {{.*#+}} xmm6 = [6,13] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm6, %zmm15 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm14, %zmm0, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm14, %zmm11 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm4, %zmm1, %zmm11 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm4, %zmm6, %zmm14 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm4 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm10, %zmm0, %zmm4 -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm8, %zmm5, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm9 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm1, %zmm9 -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm5, %zmm8, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm5, %zmm6, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm6, %zmm10 -; AVX512DQBW-ONLY-NEXT: vmovdqa 1088(%rdi), %ymm5 -; AVX512DQBW-ONLY-NEXT: vpalignr {{.*#+}} ymm5 = ymm19[8,9,10,11,12,13,14,15],ymm5[0,1,2,3,4,5,6,7],ymm19[24,25,26,27,28,29,30,31],ymm5[16,17,18,19,20,21,22,23] -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm5 = ymm9[0,1,2,3],ymm5[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm5, %zmm12, %zmm28 -; AVX512DQBW-ONLY-NEXT: movb $-32, %al -; AVX512DQBW-ONLY-NEXT: kmovd %eax, %k2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm18 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm24 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm16 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm21 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm4 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm4 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm3 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm3 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm2 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm2 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm0 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm0 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm31, %zmm12 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm19 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm23 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm22 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqa 960(%rdi), %ymm6 -; AVX512DQBW-ONLY-NEXT: vpalignr {{.*#+}} ymm6 = mem[8,9,10,11,12,13,14,15],ymm6[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm6[16,17,18,19,20,21,22,23] -; AVX512DQBW-ONLY-NEXT: vextracti128 $1, %ymm6, %xmm6 -; AVX512DQBW-ONLY-NEXT: vinserti32x4 $0, %xmm6, %zmm25, %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm27, %zmm6 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqa 512(%rdi), %ymm7 -; AVX512DQBW-ONLY-NEXT: vpalignr {{.*#+}} ymm7 = mem[8,9,10,11,12,13,14,15],ymm7[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm7[16,17,18,19,20,21,22,23] -; AVX512DQBW-ONLY-NEXT: vextracti128 $1, %ymm7, %xmm7 -; AVX512DQBW-ONLY-NEXT: vinserti32x4 $0, %xmm7, %zmm26, %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm7 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqa 64(%rdi), %ymm9 -; AVX512DQBW-ONLY-NEXT: vpalignr {{.*#+}} ymm9 = mem[8,9,10,11,12,13,14,15],ymm9[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm9[16,17,18,19,20,21,22,23] -; AVX512DQBW-ONLY-NEXT: vextracti128 $1, %ymm9, %xmm9 -; AVX512DQBW-ONLY-NEXT: vinserti32x4 $0, %xmm9, %zmm30, %zmm9 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm9 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 1408(%rdi), %ymm20 -; AVX512DQBW-ONLY-NEXT: vpalignr {{.*#+}} ymm20 = mem[8,9,10,11,12,13,14,15],ymm20[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm20[16,17,18,19,20,21,22,23] -; AVX512DQBW-ONLY-NEXT: vextracti32x4 $1, %ymm20, %xmm20 -; AVX512DQBW-ONLY-NEXT: vinserti32x4 $0, %xmm20, %zmm17, %zmm17 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm17 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 640(%rdi), %ymm20 -; AVX512DQBW-ONLY-NEXT: vpalignr $8, {{[-0-9]+}}(%r{{[sb]}}p), %ymm20, %ymm5 # 32-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # ymm5 = mem[8,9,10,11,12,13,14,15],ymm20[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm20[16,17,18,19,20,21,22,23] -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm5 = ymm13[0,1,2,3],ymm5[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm5, %zmm13, %zmm5 -; AVX512DQBW-ONLY-NEXT: vmovdqa 192(%rdi), %ymm13 -; AVX512DQBW-ONLY-NEXT: vpalignr $8, {{[-0-9]+}}(%r{{[sb]}}p), %ymm13, %ymm13 # 32-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # ymm13 = mem[8,9,10,11,12,13,14,15],ymm13[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm13[16,17,18,19,20,21,22,23] -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm11 = ymm11[0,1,2,3],ymm13[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm11, %zmm13, %zmm11 -; AVX512DQBW-ONLY-NEXT: vmovdqa 1536(%rdi), %ymm13 -; AVX512DQBW-ONLY-NEXT: vpalignr $8, {{[-0-9]+}}(%r{{[sb]}}p), %ymm13, %ymm13 # 32-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # ymm13 = mem[8,9,10,11,12,13,14,15],ymm13[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm13[16,17,18,19,20,21,22,23] -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm13[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm29, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm15, %ymm13 # 32-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # ymm13 = ymm15[0,1,2,3],mem[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm13, %zmm15, %zmm13 -; AVX512DQBW-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm14, %ymm14 # 32-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # ymm14 = ymm14[0,1,2,3],mem[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm14, %zmm15, %zmm14 -; AVX512DQBW-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm8, %ymm8 # 32-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # ymm8 = ymm8[0,1,2,3],mem[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm8, %zmm15, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm10, %ymm10 # 32-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # ymm10 = ymm10[0,1,2,3],mem[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm15, %zmm10 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm21, 192(%rsi) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm16, 128(%rsi) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm24, 64(%rsi) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm18, (%rsi) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, 192(%rdx) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, (%rdx) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm3, 64(%rdx) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, 128(%rdx) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm22, 192(%rcx) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm23, (%rcx) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm19, 64(%rcx) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm12, 128(%rcx) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm17, 192(%r8) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm9, (%r8) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, 64(%r8) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm6, 128(%r8) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 192(%r9) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, (%r9) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 64(%r9) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 128(%r9) -; AVX512DQBW-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm1, 192(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm11, (%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, 64(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm28, 128(%rax) -; AVX512DQBW-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, 128(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm8, 192(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm14, (%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm13, 64(%rax) -; AVX512DQBW-ONLY-NEXT: addq $2152, %rsp # imm = 0x868 -; AVX512DQBW-ONLY-NEXT: vzeroupper -; AVX512DQBW-ONLY-NEXT: retq +; AVX512BW-LABEL: load_i64_stride7_vf32: +; AVX512BW: # %bb.0: +; AVX512BW-NEXT: subq $2152, %rsp # imm = 0x868 +; AVX512BW-NEXT: vmovdqa64 1664(%rdi), %zmm21 +; AVX512BW-NEXT: vmovdqa64 1600(%rdi), %zmm31 +; AVX512BW-NEXT: vmovdqa64 1216(%rdi), %zmm2 +; AVX512BW-NEXT: vmovdqa64 1152(%rdi), %zmm6 +; AVX512BW-NEXT: vmovdqa64 1088(%rdi), %zmm12 +; AVX512BW-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 1024(%rdi), %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 768(%rdi), %zmm1 +; AVX512BW-NEXT: vmovdqa64 704(%rdi), %zmm10 +; AVX512BW-NEXT: vmovdqa64 640(%rdi), %zmm11 +; AVX512BW-NEXT: vmovaps 576(%rdi), %zmm0 +; AVX512BW-NEXT: vmovups %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 320(%rdi), %zmm0 +; AVX512BW-NEXT: vmovdqa64 256(%rdi), %zmm5 +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm7 = [10,3,10,3,10,3,10,3] +; AVX512BW-NEXT: # zmm7 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm8 +; AVX512BW-NEXT: vpermt2q %zmm0, %zmm7, %zmm8 +; AVX512BW-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm10, %zmm8 +; AVX512BW-NEXT: vpermt2q %zmm1, %zmm7, %zmm8 +; AVX512BW-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm6, %zmm8 +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm7, %zmm8 +; AVX512BW-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermi2q %zmm21, %zmm31, %zmm7 +; AVX512BW-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm7 = [11,4,11,4,11,4,11,4] +; AVX512BW-NEXT: # zmm7 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm6, %zmm8 +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm7, %zmm8 +; AVX512BW-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm13 +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm7 = [13,6,13,6,13,6,13,6] +; AVX512BW-NEXT: # zmm7 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm10, %zmm8 +; AVX512BW-NEXT: vpermt2q %zmm1, %zmm13, %zmm8 +; AVX512BW-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm8 +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm18 +; AVX512BW-NEXT: vpermt2q %zmm0, %zmm13, %zmm18 +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm19 = [12,5,12,5,12,5,12,5] +; AVX512BW-NEXT: # zmm19 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm10, %zmm17 +; AVX512BW-NEXT: vpermt2q %zmm1, %zmm19, %zmm17 +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm22 +; AVX512BW-NEXT: vpermt2q %zmm0, %zmm19, %zmm22 +; AVX512BW-NEXT: vmovdqa64 %zmm22, %zmm23 +; AVX512BW-NEXT: vmovdqa64 %zmm10, %zmm16 +; AVX512BW-NEXT: vpermt2q %zmm1, %zmm7, %zmm16 +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm22 +; AVX512BW-NEXT: vpermt2q %zmm0, %zmm7, %zmm22 +; AVX512BW-NEXT: vmovdqa64 %zmm22, %zmm24 +; AVX512BW-NEXT: vbroadcasti64x4 {{.*#+}} zmm28 = [0,7,14,0,0,7,14,0] +; AVX512BW-NEXT: # zmm28 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm10, %zmm15 +; AVX512BW-NEXT: vpermt2q %zmm1, %zmm28, %zmm15 +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm25 +; AVX512BW-NEXT: vpermt2q %zmm0, %zmm28, %zmm25 +; AVX512BW-NEXT: vbroadcasti64x4 {{.*#+}} zmm29 = [9,0,7,0,9,0,7,0] +; AVX512BW-NEXT: # zmm29 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm1, %zmm26 +; AVX512BW-NEXT: vpermt2q %zmm10, %zmm29, %zmm26 +; AVX512BW-NEXT: vmovdqa64 %zmm26, %zmm30 +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm4 = [2,9,2,9,2,9,2,9] +; AVX512BW-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vpermt2q %zmm1, %zmm4, %zmm10 +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm9 +; AVX512BW-NEXT: vpermt2q %zmm8, %zmm29, %zmm9 +; AVX512BW-NEXT: vpermt2q %zmm0, %zmm4, %zmm8 +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm1 +; AVX512BW-NEXT: vpermt2q %zmm12, %zmm7, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm14 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm14, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm11, %zmm7, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 192(%rdi), %zmm22 +; AVX512BW-NEXT: vmovdqa64 128(%rdi), %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm7, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm31, %zmm5 +; AVX512BW-NEXT: vpermi2q %zmm21, %zmm31, %zmm13 +; AVX512BW-NEXT: vmovdqa64 1536(%rdi), %zmm3 +; AVX512BW-NEXT: vmovdqa64 1472(%rdi), %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm3, %zmm7, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm6, %zmm0 +; AVX512BW-NEXT: vmovdqa64 %zmm6, %zmm31 +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm19, %zmm31 +; AVX512BW-NEXT: vpermi2q %zmm21, %zmm5, %zmm19 +; AVX512BW-NEXT: vmovdqa64 %zmm19, %zmm26 +; AVX512BW-NEXT: vmovdqa64 %zmm6, %zmm27 +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm7, %zmm27 +; AVX512BW-NEXT: vpermi2q %zmm21, %zmm5, %zmm1 +; AVX512BW-NEXT: vmovdqa64 %zmm6, %zmm20 +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm28, %zmm20 +; AVX512BW-NEXT: vpermi2q %zmm21, %zmm5, %zmm28 +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm12 +; AVX512BW-NEXT: vpermt2q %zmm6, %zmm29, %zmm12 +; AVX512BW-NEXT: vpermi2q %zmm5, %zmm21, %zmm29 +; AVX512BW-NEXT: vpermt2q %zmm21, %zmm4, %zmm5 +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm21 +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm4, %zmm0 +; AVX512BW-NEXT: vmovdqa64 384(%rdi), %zmm2 +; AVX512BW-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [0,5,6,9,0,5,6,9] +; AVX512BW-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm4, %zmm5 +; AVX512BW-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 832(%rdi), %zmm5 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm5, %zmm4, %zmm6 +; AVX512BW-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 1280(%rdi), %zmm6 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm6, %zmm4, %zmm7 +; AVX512BW-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 1728(%rdi), %zmm7 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm4, %zmm19 +; AVX512BW-NEXT: vmovdqu64 %zmm19, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [0,5,6,10,0,5,6,10] +; AVX512BW-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm6, %zmm4, %zmm19 +; AVX512BW-NEXT: vmovdqu64 %zmm19, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm5, %zmm4, %zmm19 +; AVX512BW-NEXT: vmovdqu64 %zmm19, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm4, %zmm18 +; AVX512BW-NEXT: vmovdqu64 %zmm18, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm4, %zmm13 +; AVX512BW-NEXT: vmovdqu64 %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [0,5,6,11,0,5,6,11] +; AVX512BW-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vpermt2q %zmm6, %zmm4, %zmm31 +; AVX512BW-NEXT: vpermt2q %zmm5, %zmm4, %zmm17 +; AVX512BW-NEXT: vmovdqu64 %zmm17, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm4, %zmm23 +; AVX512BW-NEXT: vmovdqu64 %zmm23, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm4, %zmm26 +; AVX512BW-NEXT: vmovdqu64 %zmm26, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [0,5,6,12,0,5,6,12] +; AVX512BW-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vpermt2q %zmm6, %zmm4, %zmm27 +; AVX512BW-NEXT: vpermt2q %zmm5, %zmm4, %zmm16 +; AVX512BW-NEXT: vmovdqu64 %zmm16, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm4, %zmm24 +; AVX512BW-NEXT: vmovdqu64 %zmm24, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm4, %zmm1 +; AVX512BW-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [4,5,6,13,4,5,6,13] +; AVX512BW-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vpermt2q %zmm6, %zmm4, %zmm20 +; AVX512BW-NEXT: vpermt2q %zmm5, %zmm4, %zmm15 +; AVX512BW-NEXT: vmovdqu64 %zmm15, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm4, %zmm25 +; AVX512BW-NEXT: vmovdqu64 %zmm25, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm4, %zmm28 +; AVX512BW-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [4,5,6,14,4,5,6,14] +; AVX512BW-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vpermt2q %zmm6, %zmm4, %zmm12 +; AVX512BW-NEXT: vpermt2q %zmm5, %zmm4, %zmm30 +; AVX512BW-NEXT: vmovdqu64 %zmm30, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm4, %zmm9 +; AVX512BW-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm4, %zmm29 +; AVX512BW-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [4,5,8,15,4,5,8,15] +; AVX512BW-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vpermt2q %zmm5, %zmm4, %zmm10 +; AVX512BW-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm4, %zmm8 +; AVX512BW-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm4, %zmm21 +; AVX512BW-NEXT: vmovdqu64 %zmm21, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm6, %zmm4, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: movb $24, %al +; AVX512BW-NEXT: kmovd %eax, %k1 +; AVX512BW-NEXT: vmovdqa64 512(%rdi), %zmm2 +; AVX512BW-NEXT: vmovdqa64 448(%rdi), %zmm15 +; AVX512BW-NEXT: vmovdqa64 {{.*#+}} ymm21 = <0,7,14,u> +; AVX512BW-NEXT: vmovdqa64 %zmm15, %zmm24 +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm21, %zmm24 +; AVX512BW-NEXT: vmovdqa64 %zmm11, %zmm0 +; AVX512BW-NEXT: vshufi64x2 {{.*#+}} zmm24 {%k1} = zmm14[4,5,4,5],zmm11[4,5,4,5] +; AVX512BW-NEXT: vbroadcasti64x4 {{.*#+}} zmm11 = [14,0,0,7,14,0,0,7] +; AVX512BW-NEXT: # zmm11 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm14, %zmm13 +; AVX512BW-NEXT: vpermt2q %zmm0, %zmm11, %zmm13 +; AVX512BW-NEXT: vbroadcasti64x4 {{.*#+}} zmm17 = [7,0,9,0,7,0,9,0] +; AVX512BW-NEXT: # zmm17 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm26 +; AVX512BW-NEXT: vpermt2q %zmm14, %zmm17, %zmm26 +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} ymm19 = [4,11,4,11] +; AVX512BW-NEXT: # ymm19 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vpermt2q %zmm0, %zmm19, %zmm14 +; AVX512BW-NEXT: vmovdqu64 %zmm14, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 64(%rdi), %zmm4 +; AVX512BW-NEXT: vmovdqa64 (%rdi), %zmm14 +; AVX512BW-NEXT: vmovdqa64 %zmm14, %zmm18 +; AVX512BW-NEXT: vpermt2q %zmm4, %zmm21, %zmm18 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vshufi64x2 {{.*#+}} zmm18 {%k1} = zmm0[4,5,4,5],zmm22[4,5,4,5] +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm23 +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm11, %zmm23 +; AVX512BW-NEXT: vmovdqa64 %zmm22, %zmm30 +; AVX512BW-NEXT: vpermt2q %zmm0, %zmm17, %zmm30 +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm19, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 960(%rdi), %zmm7 +; AVX512BW-NEXT: vmovdqa64 896(%rdi), %zmm10 +; AVX512BW-NEXT: vmovdqa64 %zmm10, %zmm16 +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm21, %zmm16 +; AVX512BW-NEXT: vmovdqa64 1408(%rdi), %zmm5 +; AVX512BW-NEXT: vmovdqa64 1344(%rdi), %zmm8 +; AVX512BW-NEXT: vpermi2q %zmm5, %zmm8, %zmm21 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload +; AVX512BW-NEXT: vshufi64x2 {{.*#+}} zmm21 {%k1} = zmm6[4,5,4,5],zmm3[4,5,4,5] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm1, %zmm0 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm22 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm11, %zmm0 +; AVX512BW-NEXT: vpermi2q %zmm3, %zmm6, %zmm11 +; AVX512BW-NEXT: vmovdqa64 %zmm22, %zmm25 +; AVX512BW-NEXT: vpermt2q %zmm1, %zmm17, %zmm25 +; AVX512BW-NEXT: vpermi2q %zmm6, %zmm3, %zmm17 +; AVX512BW-NEXT: vpermt2q %zmm3, %zmm19, %zmm6 +; AVX512BW-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vshufi64x2 {{.*#+}} zmm16 {%k1} = zmm1[4,5,4,5],zmm22[4,5,4,5] +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm19, %zmm1 +; AVX512BW-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa 912(%rdi), %xmm1 +; AVX512BW-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0,1],mem[2,3] +; AVX512BW-NEXT: vinserti32x4 $0, %xmm1, %zmm0, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa 464(%rdi), %xmm0 +; AVX512BW-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],mem[2,3] +; AVX512BW-NEXT: vinserti32x4 $0, %xmm0, %zmm13, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa 16(%rdi), %xmm0 +; AVX512BW-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],mem[2,3] +; AVX512BW-NEXT: vinserti32x4 $0, %xmm0, %zmm23, %zmm23 +; AVX512BW-NEXT: vmovdqa 1360(%rdi), %xmm0 +; AVX512BW-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],mem[2,3] +; AVX512BW-NEXT: vinserti32x4 $0, %xmm0, %zmm11, %zmm22 +; AVX512BW-NEXT: vinserti128 $1, 1088(%rdi), %ymm0, %ymm0 +; AVX512BW-NEXT: vmovdqa 1024(%rdi), %ymm1 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1,2,3,4,5],ymm0[6,7] +; AVX512BW-NEXT: vmovdqa64 %ymm1, %ymm19 +; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm1 = [4,11] +; AVX512BW-NEXT: vmovdqa64 %zmm10, %zmm11 +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm1, %zmm11 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm0 = ymm11[0,1,2,3],ymm0[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm20, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vinserti128 $1, 640(%rdi), %ymm0, %ymm0 +; AVX512BW-NEXT: vmovdqa 576(%rdi), %ymm3 +; AVX512BW-NEXT: vmovdqu %ymm3, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3,4,5],ymm0[6,7] +; AVX512BW-NEXT: vmovdqa64 %zmm15, %zmm3 +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm1, %zmm3 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3],ymm0[4,5,6,7] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vinserti128 $1, 192(%rdi), %ymm0, %ymm0 +; AVX512BW-NEXT: vmovdqa 128(%rdi), %ymm3 +; AVX512BW-NEXT: vmovdqu %ymm3, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3,4,5],ymm0[6,7] +; AVX512BW-NEXT: vmovdqa64 %zmm14, %zmm3 +; AVX512BW-NEXT: vpermt2q %zmm4, %zmm1, %zmm3 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3],ymm0[4,5,6,7] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vinserti128 $1, 1536(%rdi), %ymm0, %ymm0 +; AVX512BW-NEXT: vmovdqa 1472(%rdi), %ymm3 +; AVX512BW-NEXT: vmovdqu %ymm3, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3,4,5],ymm0[6,7] +; AVX512BW-NEXT: vpermi2q %zmm5, %zmm8, %zmm1 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm28, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm0 = <9,0,7,u> +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm3 +; AVX512BW-NEXT: vpermt2q %zmm15, %zmm0, %zmm3 +; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm1 = [5,12] +; AVX512BW-NEXT: vmovdqa64 %zmm15, %zmm13 +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm1, %zmm13 +; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm6 = [6,13] +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm6, %zmm15 +; AVX512BW-NEXT: vmovdqa64 %zmm4, %zmm2 +; AVX512BW-NEXT: vpermt2q %zmm14, %zmm0, %zmm2 +; AVX512BW-NEXT: vmovdqa64 %zmm14, %zmm11 +; AVX512BW-NEXT: vpermt2q %zmm4, %zmm1, %zmm11 +; AVX512BW-NEXT: vpermt2q %zmm4, %zmm6, %zmm14 +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm4 +; AVX512BW-NEXT: vpermt2q %zmm10, %zmm0, %zmm4 +; AVX512BW-NEXT: vpermi2q %zmm8, %zmm5, %zmm0 +; AVX512BW-NEXT: vmovdqa64 %zmm10, %zmm9 +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm1, %zmm9 +; AVX512BW-NEXT: vpermi2q %zmm5, %zmm8, %zmm1 +; AVX512BW-NEXT: vpermt2q %zmm5, %zmm6, %zmm8 +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm6, %zmm10 +; AVX512BW-NEXT: vmovdqa 1088(%rdi), %ymm5 +; AVX512BW-NEXT: vpalignr {{.*#+}} ymm5 = ymm19[8,9,10,11,12,13,14,15],ymm5[0,1,2,3,4,5,6,7],ymm19[24,25,26,27,28,29,30,31],ymm5[16,17,18,19,20,21,22,23] +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm5 = ymm9[0,1,2,3],ymm5[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm5, %zmm12, %zmm28 +; AVX512BW-NEXT: movb $-32, %al +; AVX512BW-NEXT: kmovd %eax, %k2 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm18 {%k2} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm24 {%k2} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm16 {%k2} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm21 {%k2} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm4 {%k1} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm4 {%k2} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm3 {%k1} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm3 {%k2} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm2 {%k1} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm2 {%k2} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm0 {%k1} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm0 {%k2} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm31, %zmm12 {%k2} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm19 {%k2} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm23 {%k2} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm22 {%k2} +; AVX512BW-NEXT: vmovdqa 960(%rdi), %ymm6 +; AVX512BW-NEXT: vpalignr {{.*#+}} ymm6 = mem[8,9,10,11,12,13,14,15],ymm6[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm6[16,17,18,19,20,21,22,23] +; AVX512BW-NEXT: vextracti128 $1, %ymm6, %xmm6 +; AVX512BW-NEXT: vinserti32x4 $0, %xmm6, %zmm25, %zmm6 +; AVX512BW-NEXT: vmovdqa64 %zmm27, %zmm6 {%k2} +; AVX512BW-NEXT: vmovdqa 512(%rdi), %ymm7 +; AVX512BW-NEXT: vpalignr {{.*#+}} ymm7 = mem[8,9,10,11,12,13,14,15],ymm7[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm7[16,17,18,19,20,21,22,23] +; AVX512BW-NEXT: vextracti128 $1, %ymm7, %xmm7 +; AVX512BW-NEXT: vinserti32x4 $0, %xmm7, %zmm26, %zmm7 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm7 {%k2} +; AVX512BW-NEXT: vmovdqa 64(%rdi), %ymm9 +; AVX512BW-NEXT: vpalignr {{.*#+}} ymm9 = mem[8,9,10,11,12,13,14,15],ymm9[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm9[16,17,18,19,20,21,22,23] +; AVX512BW-NEXT: vextracti128 $1, %ymm9, %xmm9 +; AVX512BW-NEXT: vinserti32x4 $0, %xmm9, %zmm30, %zmm9 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm9 {%k2} +; AVX512BW-NEXT: vmovdqa64 1408(%rdi), %ymm20 +; AVX512BW-NEXT: vpalignr {{.*#+}} ymm20 = mem[8,9,10,11,12,13,14,15],ymm20[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm20[16,17,18,19,20,21,22,23] +; AVX512BW-NEXT: vextracti32x4 $1, %ymm20, %xmm20 +; AVX512BW-NEXT: vinserti32x4 $0, %xmm20, %zmm17, %zmm17 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm17 {%k2} +; AVX512BW-NEXT: vmovdqa64 640(%rdi), %ymm20 +; AVX512BW-NEXT: vpalignr $8, {{[-0-9]+}}(%r{{[sb]}}p), %ymm20, %ymm5 # 32-byte Folded Reload +; AVX512BW-NEXT: # ymm5 = mem[8,9,10,11,12,13,14,15],ymm20[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm20[16,17,18,19,20,21,22,23] +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm5 = ymm13[0,1,2,3],ymm5[4,5,6,7] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload +; AVX512BW-NEXT: vinserti64x4 $0, %ymm5, %zmm13, %zmm5 +; AVX512BW-NEXT: vmovdqa 192(%rdi), %ymm13 +; AVX512BW-NEXT: vpalignr $8, {{[-0-9]+}}(%r{{[sb]}}p), %ymm13, %ymm13 # 32-byte Folded Reload +; AVX512BW-NEXT: # ymm13 = mem[8,9,10,11,12,13,14,15],ymm13[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm13[16,17,18,19,20,21,22,23] +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm11 = ymm11[0,1,2,3],ymm13[4,5,6,7] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload +; AVX512BW-NEXT: vinserti64x4 $0, %ymm11, %zmm13, %zmm11 +; AVX512BW-NEXT: vmovdqa 1536(%rdi), %ymm13 +; AVX512BW-NEXT: vpalignr $8, {{[-0-9]+}}(%r{{[sb]}}p), %ymm13, %ymm13 # 32-byte Folded Reload +; AVX512BW-NEXT: # ymm13 = mem[8,9,10,11,12,13,14,15],ymm13[0,1,2,3,4,5,6,7],mem[24,25,26,27,28,29,30,31],ymm13[16,17,18,19,20,21,22,23] +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm13[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm1, %zmm29, %zmm1 +; AVX512BW-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm15, %ymm13 # 32-byte Folded Reload +; AVX512BW-NEXT: # ymm13 = ymm15[0,1,2,3],mem[4,5,6,7] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload +; AVX512BW-NEXT: vinserti64x4 $0, %ymm13, %zmm15, %zmm13 +; AVX512BW-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm14, %ymm14 # 32-byte Folded Reload +; AVX512BW-NEXT: # ymm14 = ymm14[0,1,2,3],mem[4,5,6,7] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload +; AVX512BW-NEXT: vinserti64x4 $0, %ymm14, %zmm15, %zmm14 +; AVX512BW-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm8, %ymm8 # 32-byte Folded Reload +; AVX512BW-NEXT: # ymm8 = ymm8[0,1,2,3],mem[4,5,6,7] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload +; AVX512BW-NEXT: vinserti64x4 $0, %ymm8, %zmm15, %zmm8 +; AVX512BW-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm10, %ymm10 # 32-byte Folded Reload +; AVX512BW-NEXT: # ymm10 = ymm10[0,1,2,3],mem[4,5,6,7] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload +; AVX512BW-NEXT: vinserti64x4 $0, %ymm10, %zmm15, %zmm10 +; AVX512BW-NEXT: vmovdqa64 %zmm21, 192(%rsi) +; AVX512BW-NEXT: vmovdqa64 %zmm16, 128(%rsi) +; AVX512BW-NEXT: vmovdqa64 %zmm24, 64(%rsi) +; AVX512BW-NEXT: vmovdqa64 %zmm18, (%rsi) +; AVX512BW-NEXT: vmovdqa64 %zmm0, 192(%rdx) +; AVX512BW-NEXT: vmovdqa64 %zmm2, (%rdx) +; AVX512BW-NEXT: vmovdqa64 %zmm3, 64(%rdx) +; AVX512BW-NEXT: vmovdqa64 %zmm4, 128(%rdx) +; AVX512BW-NEXT: vmovdqa64 %zmm22, 192(%rcx) +; AVX512BW-NEXT: vmovdqa64 %zmm23, (%rcx) +; AVX512BW-NEXT: vmovdqa64 %zmm19, 64(%rcx) +; AVX512BW-NEXT: vmovdqa64 %zmm12, 128(%rcx) +; AVX512BW-NEXT: vmovdqa64 %zmm17, 192(%r8) +; AVX512BW-NEXT: vmovdqa64 %zmm9, (%r8) +; AVX512BW-NEXT: vmovdqa64 %zmm7, 64(%r8) +; AVX512BW-NEXT: vmovdqa64 %zmm6, 128(%r8) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 192(%r9) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, (%r9) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 64(%r9) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 128(%r9) +; AVX512BW-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512BW-NEXT: vmovdqa64 %zmm1, 192(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm11, (%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm5, 64(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm28, 128(%rax) +; AVX512BW-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512BW-NEXT: vmovdqa64 %zmm10, 128(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm8, 192(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm14, (%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm13, 64(%rax) +; AVX512BW-NEXT: addq $2152, %rsp # imm = 0x868 +; AVX512BW-NEXT: vzeroupper +; AVX512BW-NEXT: retq %wide.vec = load <224 x i64>, ptr %in.vec, align 64 %strided.vec0 = shufflevector <224 x i64> %wide.vec, <224 x i64> poison, <32 x i32> %strided.vec1 = shufflevector <224 x i64> %wide.vec, <224 x i64> poison, <32 x i32> @@ -10864,14 +9973,18 @@ define void @load_i64_stride7_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, pt ; AVX2-FAST-PERLANE: {{.*}} ; AVX2-SLOW: {{.*}} ; AVX512BW-FAST: {{.*}} +; AVX512BW-ONLY: {{.*}} ; AVX512BW-ONLY-FAST: {{.*}} ; AVX512BW-ONLY-SLOW: {{.*}} ; AVX512BW-SLOW: {{.*}} ; AVX512DQ-FAST: {{.*}} +; AVX512DQ-ONLY: {{.*}} ; AVX512DQ-SLOW: {{.*}} ; AVX512DQBW-FAST: {{.*}} +; AVX512DQBW-ONLY: {{.*}} ; AVX512DQBW-SLOW: {{.*}} ; AVX512F-FAST: {{.*}} +; AVX512F-ONLY: {{.*}} ; AVX512F-ONLY-FAST: {{.*}} ; AVX512F-ONLY-SLOW: {{.*}} ; AVX512F-SLOW: {{.*}} diff --git a/llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-3.ll b/llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-3.ll index e847933adf0a..bac0fbe9df6f 100644 --- a/llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-3.ll +++ b/llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-3.ll @@ -1467,79 +1467,42 @@ define void @load_i8_stride3_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; -; AVX512BW-ONLY-LABEL: load_i8_stride3_vf64: -; AVX512BW-ONLY: # %bb.0: -; AVX512BW-ONLY-NEXT: vmovdqa (%rdi), %xmm0 -; AVX512BW-ONLY-NEXT: vmovdqa 16(%rdi), %xmm1 -; AVX512BW-ONLY-NEXT: vmovdqa 32(%rdi), %xmm2 -; AVX512BW-ONLY-NEXT: vmovdqa 96(%rdi), %xmm3 -; AVX512BW-ONLY-NEXT: vmovdqa 112(%rdi), %xmm4 -; AVX512BW-ONLY-NEXT: vmovdqa 128(%rdi), %xmm5 -; AVX512BW-ONLY-NEXT: vinserti128 $1, 144(%rdi), %ymm3, %ymm3 -; AVX512BW-ONLY-NEXT: vinserti128 $1, 48(%rdi), %ymm0, %ymm0 -; AVX512BW-ONLY-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm0 -; AVX512BW-ONLY-NEXT: vinserti128 $1, 160(%rdi), %ymm4, %ymm3 -; AVX512BW-ONLY-NEXT: vinserti128 $1, 64(%rdi), %ymm1, %ymm1 -; AVX512BW-ONLY-NEXT: vinserti64x4 $1, %ymm3, %zmm1, %zmm1 -; AVX512BW-ONLY-NEXT: vinserti128 $1, 176(%rdi), %ymm5, %ymm3 -; AVX512BW-ONLY-NEXT: vinserti128 $1, 80(%rdi), %ymm2, %ymm2 -; AVX512BW-ONLY-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm2 -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm3 = [0,3,6,9,12,15,2,5,8,11,14,1,4,7,10,13,0,3,6,9,12,15,2,5,8,11,14,1,4,7,10,13,0,3,6,9,12,15,2,5,8,11,14,1,4,7,10,13,0,3,6,9,12,15,2,5,8,11,14,1,4,7,10,13] -; AVX512BW-ONLY-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vpshufb %zmm3, %zmm0, %zmm0 -; AVX512BW-ONLY-NEXT: vpshufb %zmm3, %zmm1, %zmm1 -; AVX512BW-ONLY-NEXT: vpshufb %zmm3, %zmm2, %zmm2 -; AVX512BW-ONLY-NEXT: vpalignr {{.*#+}} zmm3 = zmm2[11,12,13,14,15],zmm0[0,1,2,3,4,5,6,7,8,9,10],zmm2[27,28,29,30,31],zmm0[16,17,18,19,20,21,22,23,24,25,26],zmm2[43,44,45,46,47],zmm0[32,33,34,35,36,37,38,39,40,41,42],zmm2[59,60,61,62,63],zmm0[48,49,50,51,52,53,54,55,56,57,58] -; AVX512BW-ONLY-NEXT: vpalignr {{.*#+}} zmm0 = zmm0[11,12,13,14,15],zmm1[0,1,2,3,4,5,6,7,8,9,10],zmm0[27,28,29,30,31],zmm1[16,17,18,19,20,21,22,23,24,25,26],zmm0[43,44,45,46,47],zmm1[32,33,34,35,36,37,38,39,40,41,42],zmm0[59,60,61,62,63],zmm1[48,49,50,51,52,53,54,55,56,57,58] -; AVX512BW-ONLY-NEXT: vpalignr {{.*#+}} zmm1 = zmm1[11,12,13,14,15],zmm2[0,1,2,3,4,5,6,7,8,9,10],zmm1[27,28,29,30,31],zmm2[16,17,18,19,20,21,22,23,24,25,26],zmm1[43,44,45,46,47],zmm2[32,33,34,35,36,37,38,39,40,41,42],zmm1[59,60,61,62,63],zmm2[48,49,50,51,52,53,54,55,56,57,58] -; AVX512BW-ONLY-NEXT: movabsq $-576188069258921984, %rax # imm = 0xF800F800F800F800 -; AVX512BW-ONLY-NEXT: kmovq %rax, %k1 -; AVX512BW-ONLY-NEXT: vpblendmb %zmm1, %zmm0, %zmm2 {%k1} -; AVX512BW-ONLY-NEXT: vpalignr {{.*#+}} zmm1 = zmm3[11,12,13,14,15],zmm1[0,1,2,3,4,5,6,7,8,9,10],zmm3[27,28,29,30,31],zmm1[16,17,18,19,20,21,22,23,24,25,26],zmm3[43,44,45,46,47],zmm1[32,33,34,35,36,37,38,39,40,41,42],zmm3[59,60,61,62,63],zmm1[48,49,50,51,52,53,54,55,56,57,58] -; AVX512BW-ONLY-NEXT: vpalignr {{.*#+}} zmm0 = zmm0[11,12,13,14,15],zmm3[0,1,2,3,4,5,6,7,8,9,10],zmm0[27,28,29,30,31],zmm3[16,17,18,19,20,21,22,23,24,25,26],zmm0[43,44,45,46,47],zmm3[32,33,34,35,36,37,38,39,40,41,42],zmm0[59,60,61,62,63],zmm3[48,49,50,51,52,53,54,55,56,57,58] -; AVX512BW-ONLY-NEXT: vpalignr {{.*#+}} zmm0 = zmm0[10,11,12,13,14,15,0,1,2,3,4,5,6,7,8,9,26,27,28,29,30,31,16,17,18,19,20,21,22,23,24,25,42,43,44,45,46,47,32,33,34,35,36,37,38,39,40,41,58,59,60,61,62,63,48,49,50,51,52,53,54,55,56,57] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, (%rsi) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, (%rdx) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm1, (%rcx) -; AVX512BW-ONLY-NEXT: vzeroupper -; AVX512BW-ONLY-NEXT: retq -; -; AVX512DQBW-ONLY-LABEL: load_i8_stride3_vf64: -; AVX512DQBW-ONLY: # %bb.0: -; AVX512DQBW-ONLY-NEXT: vmovdqa (%rdi), %xmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa 16(%rdi), %xmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqa 32(%rdi), %xmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqa 96(%rdi), %xmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqa 112(%rdi), %xmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqa 128(%rdi), %xmm5 -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, 144(%rdi), %ymm3, %ymm3 -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, 48(%rdi), %ymm0, %ymm0 -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm0 -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, 160(%rdi), %ymm4, %ymm3 -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, 64(%rdi), %ymm1, %ymm1 -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $1, %ymm3, %zmm1, %zmm1 -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, 176(%rdi), %ymm5, %ymm3 -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, 80(%rdi), %ymm2, %ymm2 -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm2 -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x2 {{.*#+}} zmm3 = [0,3,6,9,12,15,2,5,8,11,14,1,4,7,10,13,0,3,6,9,12,15,2,5,8,11,14,1,4,7,10,13,0,3,6,9,12,15,2,5,8,11,14,1,4,7,10,13,0,3,6,9,12,15,2,5,8,11,14,1,4,7,10,13] -; AVX512DQBW-ONLY-NEXT: # zmm3 = mem[0,1,0,1,0,1,0,1] -; AVX512DQBW-ONLY-NEXT: vpshufb %zmm3, %zmm0, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpshufb %zmm3, %zmm1, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpshufb %zmm3, %zmm2, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpalignr {{.*#+}} zmm3 = zmm2[11,12,13,14,15],zmm0[0,1,2,3,4,5,6,7,8,9,10],zmm2[27,28,29,30,31],zmm0[16,17,18,19,20,21,22,23,24,25,26],zmm2[43,44,45,46,47],zmm0[32,33,34,35,36,37,38,39,40,41,42],zmm2[59,60,61,62,63],zmm0[48,49,50,51,52,53,54,55,56,57,58] -; AVX512DQBW-ONLY-NEXT: vpalignr {{.*#+}} zmm0 = zmm0[11,12,13,14,15],zmm1[0,1,2,3,4,5,6,7,8,9,10],zmm0[27,28,29,30,31],zmm1[16,17,18,19,20,21,22,23,24,25,26],zmm0[43,44,45,46,47],zmm1[32,33,34,35,36,37,38,39,40,41,42],zmm0[59,60,61,62,63],zmm1[48,49,50,51,52,53,54,55,56,57,58] -; AVX512DQBW-ONLY-NEXT: vpalignr {{.*#+}} zmm1 = zmm1[11,12,13,14,15],zmm2[0,1,2,3,4,5,6,7,8,9,10],zmm1[27,28,29,30,31],zmm2[16,17,18,19,20,21,22,23,24,25,26],zmm1[43,44,45,46,47],zmm2[32,33,34,35,36,37,38,39,40,41,42],zmm1[59,60,61,62,63],zmm2[48,49,50,51,52,53,54,55,56,57,58] -; AVX512DQBW-ONLY-NEXT: movabsq $-576188069258921984, %rax # imm = 0xF800F800F800F800 -; AVX512DQBW-ONLY-NEXT: kmovq %rax, %k1 -; AVX512DQBW-ONLY-NEXT: vpblendmb %zmm1, %zmm0, %zmm2 {%k1} -; AVX512DQBW-ONLY-NEXT: vpalignr {{.*#+}} zmm1 = zmm3[11,12,13,14,15],zmm1[0,1,2,3,4,5,6,7,8,9,10],zmm3[27,28,29,30,31],zmm1[16,17,18,19,20,21,22,23,24,25,26],zmm3[43,44,45,46,47],zmm1[32,33,34,35,36,37,38,39,40,41,42],zmm3[59,60,61,62,63],zmm1[48,49,50,51,52,53,54,55,56,57,58] -; AVX512DQBW-ONLY-NEXT: vpalignr {{.*#+}} zmm0 = zmm0[11,12,13,14,15],zmm3[0,1,2,3,4,5,6,7,8,9,10],zmm0[27,28,29,30,31],zmm3[16,17,18,19,20,21,22,23,24,25,26],zmm0[43,44,45,46,47],zmm3[32,33,34,35,36,37,38,39,40,41,42],zmm0[59,60,61,62,63],zmm3[48,49,50,51,52,53,54,55,56,57,58] -; AVX512DQBW-ONLY-NEXT: vpalignr {{.*#+}} zmm0 = zmm0[10,11,12,13,14,15,0,1,2,3,4,5,6,7,8,9,26,27,28,29,30,31,16,17,18,19,20,21,22,23,24,25,42,43,44,45,46,47,32,33,34,35,36,37,38,39,40,41,58,59,60,61,62,63,48,49,50,51,52,53,54,55,56,57] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, (%rsi) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, (%rdx) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm1, (%rcx) -; AVX512DQBW-ONLY-NEXT: vzeroupper -; AVX512DQBW-ONLY-NEXT: retq +; AVX512BW-LABEL: load_i8_stride3_vf64: +; AVX512BW: # %bb.0: +; AVX512BW-NEXT: vmovdqa (%rdi), %xmm0 +; AVX512BW-NEXT: vmovdqa 16(%rdi), %xmm1 +; AVX512BW-NEXT: vmovdqa 32(%rdi), %xmm2 +; AVX512BW-NEXT: vmovdqa 96(%rdi), %xmm3 +; AVX512BW-NEXT: vmovdqa 112(%rdi), %xmm4 +; AVX512BW-NEXT: vmovdqa 128(%rdi), %xmm5 +; AVX512BW-NEXT: vinserti128 $1, 144(%rdi), %ymm3, %ymm3 +; AVX512BW-NEXT: vinserti128 $1, 48(%rdi), %ymm0, %ymm0 +; AVX512BW-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm0 +; AVX512BW-NEXT: vinserti128 $1, 160(%rdi), %ymm4, %ymm3 +; AVX512BW-NEXT: vinserti128 $1, 64(%rdi), %ymm1, %ymm1 +; AVX512BW-NEXT: vinserti64x4 $1, %ymm3, %zmm1, %zmm1 +; AVX512BW-NEXT: vinserti128 $1, 176(%rdi), %ymm5, %ymm3 +; AVX512BW-NEXT: vinserti128 $1, 80(%rdi), %ymm2, %ymm2 +; AVX512BW-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm2 +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm3 = [0,3,6,9,12,15,2,5,8,11,14,1,4,7,10,13,0,3,6,9,12,15,2,5,8,11,14,1,4,7,10,13,0,3,6,9,12,15,2,5,8,11,14,1,4,7,10,13,0,3,6,9,12,15,2,5,8,11,14,1,4,7,10,13] +; AVX512BW-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vpshufb %zmm3, %zmm0, %zmm0 +; AVX512BW-NEXT: vpshufb %zmm3, %zmm1, %zmm1 +; AVX512BW-NEXT: vpshufb %zmm3, %zmm2, %zmm2 +; AVX512BW-NEXT: vpalignr {{.*#+}} zmm3 = zmm2[11,12,13,14,15],zmm0[0,1,2,3,4,5,6,7,8,9,10],zmm2[27,28,29,30,31],zmm0[16,17,18,19,20,21,22,23,24,25,26],zmm2[43,44,45,46,47],zmm0[32,33,34,35,36,37,38,39,40,41,42],zmm2[59,60,61,62,63],zmm0[48,49,50,51,52,53,54,55,56,57,58] +; AVX512BW-NEXT: vpalignr {{.*#+}} zmm0 = zmm0[11,12,13,14,15],zmm1[0,1,2,3,4,5,6,7,8,9,10],zmm0[27,28,29,30,31],zmm1[16,17,18,19,20,21,22,23,24,25,26],zmm0[43,44,45,46,47],zmm1[32,33,34,35,36,37,38,39,40,41,42],zmm0[59,60,61,62,63],zmm1[48,49,50,51,52,53,54,55,56,57,58] +; AVX512BW-NEXT: vpalignr {{.*#+}} zmm1 = zmm1[11,12,13,14,15],zmm2[0,1,2,3,4,5,6,7,8,9,10],zmm1[27,28,29,30,31],zmm2[16,17,18,19,20,21,22,23,24,25,26],zmm1[43,44,45,46,47],zmm2[32,33,34,35,36,37,38,39,40,41,42],zmm1[59,60,61,62,63],zmm2[48,49,50,51,52,53,54,55,56,57,58] +; AVX512BW-NEXT: movabsq $-576188069258921984, %rax # imm = 0xF800F800F800F800 +; AVX512BW-NEXT: kmovq %rax, %k1 +; AVX512BW-NEXT: vpblendmb %zmm1, %zmm0, %zmm2 {%k1} +; AVX512BW-NEXT: vpalignr {{.*#+}} zmm1 = zmm3[11,12,13,14,15],zmm1[0,1,2,3,4,5,6,7,8,9,10],zmm3[27,28,29,30,31],zmm1[16,17,18,19,20,21,22,23,24,25,26],zmm3[43,44,45,46,47],zmm1[32,33,34,35,36,37,38,39,40,41,42],zmm3[59,60,61,62,63],zmm1[48,49,50,51,52,53,54,55,56,57,58] +; AVX512BW-NEXT: vpalignr {{.*#+}} zmm0 = zmm0[11,12,13,14,15],zmm3[0,1,2,3,4,5,6,7,8,9,10],zmm0[27,28,29,30,31],zmm3[16,17,18,19,20,21,22,23,24,25,26],zmm0[43,44,45,46,47],zmm3[32,33,34,35,36,37,38,39,40,41,42],zmm0[59,60,61,62,63],zmm3[48,49,50,51,52,53,54,55,56,57,58] +; AVX512BW-NEXT: vpalignr {{.*#+}} zmm0 = zmm0[10,11,12,13,14,15,0,1,2,3,4,5,6,7,8,9,26,27,28,29,30,31,16,17,18,19,20,21,22,23,24,25,42,43,44,45,46,47,32,33,34,35,36,37,38,39,40,41,58,59,60,61,62,63,48,49,50,51,52,53,54,55,56,57] +; AVX512BW-NEXT: vmovdqa64 %zmm0, (%rsi) +; AVX512BW-NEXT: vmovdqa64 %zmm2, (%rdx) +; AVX512BW-NEXT: vmovdqa64 %zmm1, (%rcx) +; AVX512BW-NEXT: vzeroupper +; AVX512BW-NEXT: retq %wide.vec = load <192 x i8>, ptr %in.vec, align 64 %strided.vec0 = shufflevector <192 x i8> %wide.vec, <192 x i8> poison, <64 x i32> %strided.vec1 = shufflevector <192 x i8> %wide.vec, <192 x i8> poison, <64 x i32> @@ -1558,6 +1521,7 @@ define void @load_i8_stride3_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr ; AVX512-FAST: {{.*}} ; AVX512-SLOW: {{.*}} ; AVX512BW-FAST: {{.*}} +; AVX512BW-ONLY: {{.*}} ; AVX512BW-ONLY-FAST: {{.*}} ; AVX512BW-ONLY-SLOW: {{.*}} ; AVX512BW-SLOW: {{.*}} @@ -1565,6 +1529,7 @@ define void @load_i8_stride3_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr ; AVX512DQ-ONLY: {{.*}} ; AVX512DQ-SLOW: {{.*}} ; AVX512DQBW-FAST: {{.*}} +; AVX512DQBW-ONLY: {{.*}} ; AVX512DQBW-SLOW: {{.*}} ; AVX512F-FAST: {{.*}} ; AVX512F-ONLY: {{.*}} diff --git a/llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll b/llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll index 370a7d221369..0e3f8121db1d 100644 --- a/llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll +++ b/llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll @@ -12065,8 +12065,8 @@ define void @load_i8_stride7_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr ; AVX512DQBW-FAST-NEXT: vpshufb {{.*#+}} xmm20 = xmm20[u,u,u],zero,zero,xmm20[4,11],zero,zero,xmm20[0,7,14,u,u,u,u] ; AVX512DQBW-FAST-NEXT: vporq %xmm23, %xmm20, %xmm20 ; AVX512DQBW-FAST-NEXT: vinserti32x4 $1, %xmm20, %ymm0, %ymm15 -; AVX512DQBW-FAST-NEXT: vbroadcasti64x2 {{.*#+}} ymm20 = [1,3,4,6,1,3,4,6] -; AVX512DQBW-FAST-NEXT: # ymm20 = mem[0,1,0,1] +; AVX512DQBW-FAST-NEXT: vbroadcasti32x4 {{.*#+}} ymm20 = [1,3,4,6,1,3,4,6] +; AVX512DQBW-FAST-NEXT: # ymm20 = mem[0,1,2,3,0,1,2,3] ; AVX512DQBW-FAST-NEXT: vpermd %ymm19, %ymm20, %ymm20 ; AVX512DQBW-FAST-NEXT: vpshufb {{.*#+}} ymm14 = ymm20[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,17,20,27,30] ; AVX512DQBW-FAST-NEXT: vpblendd {{.*#+}} ymm14 = ymm15[0,1,2,3,4,5,6],ymm14[7] @@ -12089,8 +12089,8 @@ define void @load_i8_stride7_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr ; AVX512DQBW-FAST-NEXT: vpshufb {{.*#+}} xmm14 = xmm14[u,u,0,7,14],zero,zero,xmm14[3,10],zero,zero,zero,xmm14[u,u,u,u] ; AVX512DQBW-FAST-NEXT: vporq %xmm20, %xmm14, %xmm14 ; AVX512DQBW-FAST-NEXT: vinserti128 $1, %xmm14, %ymm0, %ymm14 -; AVX512DQBW-FAST-NEXT: vbroadcasti64x2 {{.*#+}} ymm20 = [1,3,5,6,1,3,5,6] -; AVX512DQBW-FAST-NEXT: # ymm20 = mem[0,1,0,1] +; AVX512DQBW-FAST-NEXT: vbroadcasti32x4 {{.*#+}} ymm20 = [1,3,5,6,1,3,5,6] +; AVX512DQBW-FAST-NEXT: # ymm20 = mem[0,1,2,3,0,1,2,3] ; AVX512DQBW-FAST-NEXT: vpermd %ymm19, %ymm20, %ymm19 ; AVX512DQBW-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm19[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,21,24,31] ; AVX512DQBW-FAST-NEXT: vpblendd {{.*#+}} ymm0 = ymm14[0,1,2,3,4,5,6],ymm0[7] diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll index 3a0e1d92b48c..5934b80893ce 100644 --- a/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll +++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll @@ -2315,537 +2315,271 @@ define void @store_i16_stride7_vf16(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve ; AVX2-FAST-PERLANE-NEXT: vzeroupper ; AVX2-FAST-PERLANE-NEXT: retq ; -; AVX512F-ONLY-SLOW-LABEL: store_i16_stride7_vf16: -; AVX512F-ONLY-SLOW: # %bb.0: -; AVX512F-ONLY-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rdi), %ymm8 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rsi), %ymm9 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rdx), %ymm6 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rcx), %ymm7 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%r8), %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%r9), %ymm3 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rax), %ymm13 -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm1 = ymm7[u,u,u,u,u,u],zero,zero,ymm7[14,15,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm7[16,17,u,u,u,u,u,u,u,u] -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm4 = ymm6[u,u,u,u,u,u,14,15],zero,zero,ymm6[u,u,u,u,u,u,u,u,u,u,16,17],zero,zero,ymm6[u,u,u,u,u,u,u,u] -; AVX512F-ONLY-SLOW-NEXT: vporq %ymm1, %ymm4, %ymm16 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rcx), %xmm14 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rdx), %xmm15 -; AVX512F-ONLY-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm15[4],xmm14[4],xmm15[5],xmm14[5],xmm15[6],xmm14[6],xmm15[7],xmm14[7] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %xmm0, %xmm21 -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm1 = zero,zero,zero,zero,ymm9[14,15,u,u,u,u],zero,zero,zero,zero,zero,zero,zero,zero,ymm9[16,17,u,u,u,u],zero,zero,zero,zero,zero,zero,zero,zero -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm4 = ymm8[12,13,14,15],zero,zero,ymm8[u,u,u,u,u,u,u,u,u,u,16,17],zero,zero,ymm8[u,u,u,u,u,u,u,u,16,17,18,19] -; AVX512F-ONLY-SLOW-NEXT: vporq %ymm1, %ymm4, %ymm17 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rdi), %xmm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rsi), %xmm4 -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm5 = ymm3[u,u,u,u,u,u,u,u,u,u],zero,zero,ymm3[14,15,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm3[16,17,u,u,u,u] -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm10 = ymm2[u,u,u,u,u,u,u,u,u,u,14,15],zero,zero,ymm2[u,u,u,u,u,u,u,u,u,u,16,17],zero,zero,ymm2[u,u,u,u] -; AVX512F-ONLY-SLOW-NEXT: vporq %ymm5, %ymm10, %ymm19 -; AVX512F-ONLY-SLOW-NEXT: vpbroadcastd 8(%rax), %ymm5 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} ymm10 = [65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535] -; AVX512F-ONLY-SLOW-NEXT: vpandn %ymm5, %ymm10, %ymm5 -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm10 = ymm13[12,13,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm13[14,15,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm13[16,17,u,u] -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm10, %zmm5, %zmm5 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm10 = ymm6[0,1,1,3,4,5,5,7] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} ymm12 = ymm7[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm12[0,0,0,0,4,4,4,4] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm10[0,1],ymm12[2],ymm10[3,4],ymm12[5],ymm10[6,7,8,9],ymm12[10],ymm10[11,12],ymm12[13],ymm10[14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm0, %ymm22 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm10 = ymm6[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm12 = ymm7[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,22,23,26,27,u,u,24,25,26,27,u,u,26,27,26,27] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm12 = ymm12[0,1],ymm10[2],ymm12[3,4],ymm10[5],ymm12[6,7,8,9],ymm10[10],ymm12[11,12],ymm10[13],ymm12[14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm10 = ymm8[1,1,1,1,5,5,5,5] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} ymm11 = ymm9[1,2,3,3,4,5,6,7,9,10,11,11,12,13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm11 = ymm11[0,0,2,1,4,4,6,5] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm11 = ymm11[0,1],ymm10[2],ymm11[3,4],ymm10[5],ymm11[6,7,8,9],ymm10[10],ymm11[11,12],ymm10[13],ymm11[14,15] -; AVX512F-ONLY-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm10 = xmm4[4],xmm1[4],xmm4[5],xmm1[5],xmm4[6],xmm1[6],xmm4[7],xmm1[7] -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm12, %zmm11, %zmm20 -; AVX512F-ONLY-SLOW-NEXT: vprold $16, %xmm4, %xmm11 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} xmm12 = xmm1[1,1,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} xmm11 = xmm12[0,1],xmm11[2],xmm12[3,4],xmm11[5],xmm12[6,7] -; AVX512F-ONLY-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm12 = xmm15[0],xmm14[0],xmm15[1],xmm14[1],xmm15[2],xmm14[2],xmm15[3],xmm14[3] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} xmm12 = xmm12[0,1,3,2,4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vbroadcasti64x4 {{.*#+}} zmm18 = [0,16,0,1,17,17,2,0,0,16,0,1,17,17,2,0] -; AVX512F-ONLY-SLOW-NEXT: # zmm18 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpermi2d %zmm12, %zmm11, %zmm18 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm11 = ymm8[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm12 = ymm9[0,1,2,3,5,4,6,7,8,9,10,11,13,12,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm12[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm12 = ymm11[0],ymm12[1],ymm11[2,3],ymm12[4],ymm11[5,6,7,8],ymm12[9],ymm11[10,11],ymm12[12],ymm11[13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%r9), %xmm11 -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} xmm14 = xmm14[u,u,4,5,u,u,u,u,6,7,u,u,u,u,8,9] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} xmm15 = xmm15[1,1,2,2] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} xmm14 = xmm15[0],xmm14[1],xmm15[2,3],xmm14[4],xmm15[5,6],xmm14[7] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%r8), %xmm15 -; AVX512F-ONLY-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3] -; AVX512F-ONLY-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm15[4],xmm11[4],xmm15[5],xmm11[5],xmm15[6],xmm11[6],xmm15[7],xmm11[7] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} xmm0 = [0,1,2,3,4,5,4,5,6,7,10,11,8,9,10,11] -; AVX512F-ONLY-SLOW-NEXT: vpshufb %xmm0, %xmm4, %xmm4 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %xmm0, %xmm1, %xmm0 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm14, %zmm0, %zmm1 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm2[0,0,2,1,4,4,6,5] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} ymm14 = ymm3[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm14 = ymm14[0,0,0,0,4,4,4,4] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm14 = ymm14[0,1,2],ymm0[3],ymm14[4,5],ymm0[6],ymm14[7,8,9,10],ymm0[11],ymm14[12,13],ymm0[14],ymm14[15] -; AVX512F-ONLY-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm15[0],xmm11[0],xmm15[1],xmm11[1],xmm15[2],xmm11[2],xmm15[3],xmm11[3] -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} xmm11 = xmm0[0,1,2,3,4,5,7,6] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,1,3,2,4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm15 = <0,1,0,1,0,1,1,3,16,18,19,19,19,19,u,u> -; AVX512F-ONLY-SLOW-NEXT: vpermi2d %zmm11, %zmm0, %zmm15 -; AVX512F-ONLY-SLOW-NEXT: vprold $16, %ymm3, %ymm0 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm11 = ymm2[1,2,2,3,5,6,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm11[0,1],ymm0[2],ymm11[3,4],ymm0[5],ymm11[6,7,8,9],ymm0[10],ymm11[11,12],ymm0[13],ymm11[14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm8 = ymm8[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm9 = ymm9[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm9 = ymm9[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm8 = ymm8[0,1,2],ymm9[3],ymm8[4,5],ymm9[6],ymm8[7,8,9,10],ymm9[11],ymm8[12,13],ymm9[14],ymm8[15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm6 = ymm6[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm7 = ymm7[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm7 = ymm7[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm6 = ymm6[0],ymm7[1],ymm6[2,3],ymm7[4],ymm6[5,6,7,8],ymm7[9],ymm6[10,11],ymm7[12],ymm6[13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %xmm21, %xmm7 -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} xmm7 = xmm7[0,2,3,3,4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm7[0,0,2,1] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} xmm9 = xmm10[2,1,2,3,4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} xmm9 = xmm9[0,1,2,3,4,5,5,4] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm9 = ymm9[0,0,1,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm4 = ymm4[0,0,1,1] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm10 = ymm22[2,1,3,2] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm11 = ymm12[0,2,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm12 = ymm14[2,2,3,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,1,3,2] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm8 = ymm8[2,1,3,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm6 = ymm6[0,2,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm3 = ymm3[0,1,2,3,5,6,7,7,8,9,10,11,13,14,15,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm3 = ymm3[2,2,2,3,6,6,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm2 = ymm3[0,1],ymm2[2],ymm3[3,4],ymm2[5],ymm3[6,7,8,9],ymm2[10],ymm3[11,12],ymm2[13],ymm3[14,15] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm2 = ymm2[2,2,2,3] -; AVX512F-ONLY-SLOW-NEXT: vbroadcasti64x4 {{.*#+}} zmm3 = [0,5,4,0,0,6,5,0,0,5,4,0,0,6,5,0] -; AVX512F-ONLY-SLOW-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpermd %zmm13, %zmm3, %zmm3 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm13 = ymm13[2,3,3,3,6,7,7,7] -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm16, %zmm7, %zmm7 -; AVX512F-ONLY-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %rcx -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm17, %zmm9, %zmm9 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm7, %zmm9 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm19, %zmm4, %zmm4 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm4, %zmm5 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm5 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm11, %zmm10, %zmm4 -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} zmm7 = zmm20[2,2,2,3,6,6,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm4, %zmm7 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm0, %zmm12, %zmm0 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm3 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm7, %zmm3 -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} zmm0 = zmm1[0,0,1,1,4,4,5,5] -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm18, %zmm0 -; AVX512F-ONLY-SLOW-NEXT: vpbroadcastd (%rax), %ymm1 -; AVX512F-ONLY-SLOW-NEXT: vpbroadcastd 4(%rax), %ymm4 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm4, %zmm1, %zmm1 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm15, %zmm1 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm8, %ymm6 -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm0 = ymm13[2,1,3,2] -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm0 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm6, %ymm0 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa %ymm0, 192(%rcx) -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %zmm1, (%rcx) -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %zmm3, 128(%rcx) -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %zmm5, 64(%rcx) -; AVX512F-ONLY-SLOW-NEXT: vzeroupper -; AVX512F-ONLY-SLOW-NEXT: retq -; -; AVX512F-ONLY-FAST-LABEL: store_i16_stride7_vf16: -; AVX512F-ONLY-FAST: # %bb.0: -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rdi), %ymm5 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rsi), %ymm7 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rdx), %ymm4 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rcx), %ymm6 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%r8), %ymm1 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%r9), %ymm2 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm0 = zero,zero,zero,zero,ymm7[14,15,u,u,u,u],zero,zero,zero,zero,zero,zero,zero,zero,ymm7[16,17,u,u,u,u],zero,zero,zero,zero,zero,zero,zero,zero -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm3 = ymm5[12,13,14,15],zero,zero,ymm5[u,u,u,u,u,u,u,u,u,u,16,17],zero,zero,ymm5[u,u,u,u,u,u,u,u,16,17,18,19] -; AVX512F-ONLY-FAST-NEXT: vporq %ymm0, %ymm3, %ymm16 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rdi), %xmm11 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rsi), %xmm12 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm6[u,u,u,u,u,u],zero,zero,ymm6[14,15,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm6[16,17,u,u,u,u,u,u,u,u] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm3 = ymm4[u,u,u,u,u,u,14,15],zero,zero,ymm4[u,u,u,u,u,u,u,u,u,u,16,17],zero,zero,ymm4[u,u,u,u,u,u,u,u] -; AVX512F-ONLY-FAST-NEXT: vporq %ymm0, %ymm3, %ymm17 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rcx), %xmm14 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm2[u,u,u,u,u,u,u,u,u,u],zero,zero,ymm2[14,15,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm2[16,17,u,u,u,u] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm3 = ymm1[u,u,u,u,u,u,u,u,u,u,14,15],zero,zero,ymm1[u,u,u,u,u,u,u,u,u,u,16,17],zero,zero,ymm1[u,u,u,u] -; AVX512F-ONLY-FAST-NEXT: vporq %ymm0, %ymm3, %ymm18 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm7[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,24,25,u,u,u,u,26,27,u,u,u,u,u,u] -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm5[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm3[0],ymm0[1],ymm3[2,3],ymm0[4],ymm3[5,6,7,8],ymm0[9],ymm3[10,11],ymm0[12],ymm3[13,14,15] -; AVX512F-ONLY-FAST-NEXT: vpunpcklwd {{.*#+}} ymm3 = ymm6[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11] -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm9 = ymm4[0,1,1,3,4,5,5,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm9[0,1],ymm3[2],ymm9[3,4],ymm3[5],ymm9[6,7,8,9],ymm3[10],ymm9[11,12],ymm3[13],ymm9[14,15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm9 = <2,u,3,2,u,10,10,11> -; AVX512F-ONLY-FAST-NEXT: vpermi2q %zmm0, %zmm3, %zmm9 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm0 = ymm4[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm3 = ymm6[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,22,23,26,27,u,u,24,25,26,27,u,u,26,27,26,27] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm3[0,1],ymm0[2],ymm3[3,4],ymm0[5],ymm3[6,7,8,9],ymm0[10],ymm3[11,12],ymm0[13],ymm3[14,15] -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm5[1,1,1,1,5,5,5,5] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm10 = ymm7[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,20,21,u,u,20,21,24,25,u,u,22,23,22,23] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm10[0,1],ymm3[2],ymm10[3,4],ymm3[5],ymm10[6,7,8,9],ymm3[10],ymm10[11,12],ymm3[13],ymm10[14,15] -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm3, %zmm19 -; AVX512F-ONLY-FAST-NEXT: vprold $16, %ymm2, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm1[1,2,2,3,5,6,6,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm3[0,1],ymm0[2],ymm3[3,4],ymm0[5],ymm3[6,7,8,9],ymm0[10],ymm3[11,12],ymm0[13],ymm3[14,15] -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm1[0,0,2,1,4,4,6,5] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm13 = ymm2[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,20,21,18,19,u,u,18,19,20,21,u,u,20,21] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm13[0,1,2],ymm3[3],ymm13[4,5],ymm3[6],ymm13[7,8,9,10],ymm3[11],ymm13[12,13],ymm3[14],ymm13[15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rdx), %xmm8 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm13 = [2,2,3,3,10,9,11,10] -; AVX512F-ONLY-FAST-NEXT: vpermi2q %zmm0, %zmm3, %zmm13 -; AVX512F-ONLY-FAST-NEXT: vprold $16, %xmm12, %xmm0 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} xmm3 = xmm11[1,1,2,3] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} xmm0 = xmm3[0,1],xmm0[2],xmm3[3,4],xmm0[5],xmm3[6,7] -; AVX512F-ONLY-FAST-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm8[0],xmm14[0],xmm8[1],xmm14[1],xmm8[2],xmm14[2],xmm8[3],xmm14[3] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} xmm3 = xmm3[0,1,2,3,0,1,2,3,6,7,4,5,6,7,4,5] -; AVX512F-ONLY-FAST-NEXT: vbroadcasti64x4 {{.*#+}} zmm15 = [0,8,1,9,0,8,1,9] -; AVX512F-ONLY-FAST-NEXT: # zmm15 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-FAST-NEXT: vpermi2q %zmm0, %zmm3, %zmm15 -; AVX512F-ONLY-FAST-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm12[4],xmm11[4],xmm12[5],xmm11[5],xmm12[6],xmm11[6],xmm12[7],xmm11[7] -; AVX512F-ONLY-FAST-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm8[4],xmm14[4],xmm8[5],xmm14[5],xmm8[6],xmm14[6],xmm8[7],xmm14[7] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} xmm14 = xmm14[u,u,4,5,u,u,u,u,6,7,u,u,u,u,8,9] -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} xmm8 = xmm8[1,1,2,2] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} xmm8 = xmm8[0],xmm14[1],xmm8[2,3],xmm14[4],xmm8[5,6],xmm14[7] -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%r9), %xmm14 -; AVX512F-ONLY-FAST-NEXT: vpunpcklwd {{.*#+}} xmm11 = xmm11[0],xmm12[0],xmm11[1],xmm12[1],xmm11[2],xmm12[2],xmm11[3],xmm12[3] -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} xmm12 = [0,1,2,3,4,5,4,5,6,7,10,11,8,9,10,11] -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm12, %xmm11, %xmm11 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm8, %zmm11, %zmm11 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%r8), %xmm8 -; AVX512F-ONLY-FAST-NEXT: vpunpckhwd {{.*#+}} xmm10 = xmm8[4],xmm14[4],xmm8[5],xmm14[5],xmm8[6],xmm14[6],xmm8[7],xmm14[7] -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm12, %xmm10, %xmm12 -; AVX512F-ONLY-FAST-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512F-ONLY-FAST-NEXT: vpbroadcastd 8(%rax), %ymm10 -; AVX512F-ONLY-FAST-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm10, %ymm10 -; AVX512F-ONLY-FAST-NEXT: vpunpcklwd {{.*#+}} xmm8 = xmm8[0],xmm14[0],xmm8[1],xmm14[1],xmm8[2],xmm14[2],xmm8[3],xmm14[3] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} xmm14 = xmm8[0,1,2,3,8,9,10,11,14,15,12,13,14,15,12,13] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} xmm8 = xmm8[0,1,2,3,6,7,4,5,6,7,4,5,12,13,14,15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm20 = [0,0,0,1,8,9,9,11] -; AVX512F-ONLY-FAST-NEXT: vpermi2q %zmm14, %zmm8, %zmm20 -; AVX512F-ONLY-FAST-NEXT: vbroadcasti64x4 {{.*#+}} zmm8 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm14 = ymm8[12,13,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm8[14,15,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm8[16,17,u,u] -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm14, %zmm10, %zmm10 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm7 = ymm7[u,u,u,u,u,u,u,u,u,u,u,u,14,15,u,u,u,u,u,u,u,u,28,29,u,u,u,u,30,31,u,u] -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm5 = ymm5[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm5 = ymm5[0,1,2],ymm7[3],ymm5[4,5],ymm7[6],ymm5[7,8,9,10],ymm7[11],ymm5[12,13],ymm7[14],ymm5[15] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm6 = ymm6[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,28,29,u,u,u,u,30,31,u,u,u,u,u,u] -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm4 = ymm4[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm4 = ymm4[0],ymm6[1],ymm4[2,3],ymm6[4],ymm4[5,6,7,8],ymm6[9],ymm4[10,11],ymm6[12],ymm4[13,14,15] -; AVX512F-ONLY-FAST-NEXT: vbroadcasti64x4 {{.*#+}} zmm6 = [0,13,4,0,0,14,5,0,0,13,4,0,0,14,5,0] -; AVX512F-ONLY-FAST-NEXT: # zmm6 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-FAST-NEXT: vpermd %zmm8, %zmm6, %zmm6 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm7 = <6,u,u,u,7,u,u,7> -; AVX512F-ONLY-FAST-NEXT: vpermd %ymm8, %ymm7, %ymm7 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} xmm3 = xmm3[4,5,2,3,4,5,6,7,8,9,10,11,10,11,8,9] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,0,1,3] -; AVX512F-ONLY-FAST-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,3,3,4,5,6,7] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,0,2,1] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm8 = ymm12[0,0,1,1] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm5 = ymm5[2,1,3,3] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm4 = ymm4[0,2,2,3] -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm2[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,26,27,28,29,u,u,28,29,26,27,u,u,30,31,30,31] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0,1],ymm1[2],ymm2[3,4],ymm1[5],ymm2[6,7,8,9],ymm1[10],ymm2[11,12],ymm1[13],ymm2[14,15] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,2,2,3] -; AVX512F-ONLY-FAST-NEXT: movq {{[0-9]+}}(%rsp), %rcx -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm16, %zmm3, %zmm2 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm17, %zmm0, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm18, %zmm8, %zmm2 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm10 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm10 -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} zmm0 = zmm19[2,2,2,3,6,6,6,7] -; AVX512F-ONLY-FAST-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm13, %zmm6 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm6 -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} zmm0 = zmm11[0,0,1,1,4,4,5,5] -; AVX512F-ONLY-FAST-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm15, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vpbroadcastd (%rax), %ymm2 -; AVX512F-ONLY-FAST-NEXT: vpbroadcastd 4(%rax), %ymm3 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm2 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm20, %zmm2 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm2 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm5, %ymm4 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm7, %ymm1 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm1 -; AVX512F-ONLY-FAST-NEXT: vmovdqa %ymm1, 192(%rcx) -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm2, (%rcx) -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm6, 128(%rcx) -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm10, 64(%rcx) -; AVX512F-ONLY-FAST-NEXT: vzeroupper -; AVX512F-ONLY-FAST-NEXT: retq -; -; AVX512DQ-SLOW-LABEL: store_i16_stride7_vf16: -; AVX512DQ-SLOW: # %bb.0: -; AVX512DQ-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQ-SLOW-NEXT: vmovdqa (%rdi), %ymm8 -; AVX512DQ-SLOW-NEXT: vmovdqa (%rsi), %ymm9 -; AVX512DQ-SLOW-NEXT: vmovdqa (%rdx), %ymm6 -; AVX512DQ-SLOW-NEXT: vmovdqa (%rcx), %ymm7 -; AVX512DQ-SLOW-NEXT: vmovdqa (%r8), %ymm2 -; AVX512DQ-SLOW-NEXT: vmovdqa (%r9), %ymm3 -; AVX512DQ-SLOW-NEXT: vmovdqa (%rax), %ymm13 -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm1 = ymm7[u,u,u,u,u,u],zero,zero,ymm7[14,15,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm7[16,17,u,u,u,u,u,u,u,u] -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm4 = ymm6[u,u,u,u,u,u,14,15],zero,zero,ymm6[u,u,u,u,u,u,u,u,u,u,16,17],zero,zero,ymm6[u,u,u,u,u,u,u,u] -; AVX512DQ-SLOW-NEXT: vporq %ymm1, %ymm4, %ymm16 -; AVX512DQ-SLOW-NEXT: vmovdqa (%rcx), %xmm14 -; AVX512DQ-SLOW-NEXT: vmovdqa (%rdx), %xmm15 -; AVX512DQ-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm15[4],xmm14[4],xmm15[5],xmm14[5],xmm15[6],xmm14[6],xmm15[7],xmm14[7] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %xmm0, %xmm21 -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm1 = zero,zero,zero,zero,ymm9[14,15,u,u,u,u],zero,zero,zero,zero,zero,zero,zero,zero,ymm9[16,17,u,u,u,u],zero,zero,zero,zero,zero,zero,zero,zero -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm4 = ymm8[12,13,14,15],zero,zero,ymm8[u,u,u,u,u,u,u,u,u,u,16,17],zero,zero,ymm8[u,u,u,u,u,u,u,u,16,17,18,19] -; AVX512DQ-SLOW-NEXT: vporq %ymm1, %ymm4, %ymm17 -; AVX512DQ-SLOW-NEXT: vmovdqa (%rdi), %xmm1 -; AVX512DQ-SLOW-NEXT: vmovdqa (%rsi), %xmm4 -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm5 = ymm3[u,u,u,u,u,u,u,u,u,u],zero,zero,ymm3[14,15,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm3[16,17,u,u,u,u] -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm10 = ymm2[u,u,u,u,u,u,u,u,u,u,14,15],zero,zero,ymm2[u,u,u,u,u,u,u,u,u,u,16,17],zero,zero,ymm2[u,u,u,u] -; AVX512DQ-SLOW-NEXT: vporq %ymm5, %ymm10, %ymm19 -; AVX512DQ-SLOW-NEXT: vpbroadcastd 8(%rax), %ymm5 -; AVX512DQ-SLOW-NEXT: vmovdqa {{.*#+}} ymm10 = [65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535] -; AVX512DQ-SLOW-NEXT: vpandn %ymm5, %ymm10, %ymm5 -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm10 = ymm13[12,13,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm13[14,15,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm13[16,17,u,u] -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm10, %zmm5, %zmm5 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm10 = ymm6[0,1,1,3,4,5,5,7] -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} ymm12 = ymm7[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm12[0,0,0,0,4,4,4,4] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm10[0,1],ymm12[2],ymm10[3,4],ymm12[5],ymm10[6,7,8,9],ymm12[10],ymm10[11,12],ymm12[13],ymm10[14,15] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm0, %ymm22 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm10 = ymm6[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm12 = ymm7[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,22,23,26,27,u,u,24,25,26,27,u,u,26,27,26,27] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm12 = ymm12[0,1],ymm10[2],ymm12[3,4],ymm10[5],ymm12[6,7,8,9],ymm10[10],ymm12[11,12],ymm10[13],ymm12[14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm10 = ymm8[1,1,1,1,5,5,5,5] -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} ymm11 = ymm9[1,2,3,3,4,5,6,7,9,10,11,11,12,13,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm11 = ymm11[0,0,2,1,4,4,6,5] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm11 = ymm11[0,1],ymm10[2],ymm11[3,4],ymm10[5],ymm11[6,7,8,9],ymm10[10],ymm11[11,12],ymm10[13],ymm11[14,15] -; AVX512DQ-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm10 = xmm4[4],xmm1[4],xmm4[5],xmm1[5],xmm4[6],xmm1[6],xmm4[7],xmm1[7] -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm12, %zmm11, %zmm20 -; AVX512DQ-SLOW-NEXT: vprold $16, %xmm4, %xmm11 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} xmm12 = xmm1[1,1,2,3] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} xmm11 = xmm12[0,1],xmm11[2],xmm12[3,4],xmm11[5],xmm12[6,7] -; AVX512DQ-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm12 = xmm15[0],xmm14[0],xmm15[1],xmm14[1],xmm15[2],xmm14[2],xmm15[3],xmm14[3] -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} xmm12 = xmm12[0,1,3,2,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vbroadcasti32x8 {{.*#+}} zmm18 = [0,16,0,1,17,17,2,0,0,16,0,1,17,17,2,0] -; AVX512DQ-SLOW-NEXT: # zmm18 = mem[0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpermi2d %zmm12, %zmm11, %zmm18 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm11 = ymm8[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} ymm12 = ymm9[0,1,2,3,5,4,6,7,8,9,10,11,13,12,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm12[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm12 = ymm11[0],ymm12[1],ymm11[2,3],ymm12[4],ymm11[5,6,7,8],ymm12[9],ymm11[10,11],ymm12[12],ymm11[13,14,15] -; AVX512DQ-SLOW-NEXT: vmovdqa (%r9), %xmm11 -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} xmm14 = xmm14[u,u,4,5,u,u,u,u,6,7,u,u,u,u,8,9] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} xmm15 = xmm15[1,1,2,2] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} xmm14 = xmm15[0],xmm14[1],xmm15[2,3],xmm14[4],xmm15[5,6],xmm14[7] -; AVX512DQ-SLOW-NEXT: vmovdqa (%r8), %xmm15 -; AVX512DQ-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3] -; AVX512DQ-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm15[4],xmm11[4],xmm15[5],xmm11[5],xmm15[6],xmm11[6],xmm15[7],xmm11[7] -; AVX512DQ-SLOW-NEXT: vmovdqa {{.*#+}} xmm0 = [0,1,2,3,4,5,4,5,6,7,10,11,8,9,10,11] -; AVX512DQ-SLOW-NEXT: vpshufb %xmm0, %xmm4, %xmm4 -; AVX512DQ-SLOW-NEXT: vpshufb %xmm0, %xmm1, %xmm0 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm14, %zmm0, %zmm1 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm2[0,0,2,1,4,4,6,5] -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} ymm14 = ymm3[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm14 = ymm14[0,0,0,0,4,4,4,4] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm14 = ymm14[0,1,2],ymm0[3],ymm14[4,5],ymm0[6],ymm14[7,8,9,10],ymm0[11],ymm14[12,13],ymm0[14],ymm14[15] -; AVX512DQ-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm15[0],xmm11[0],xmm15[1],xmm11[1],xmm15[2],xmm11[2],xmm15[3],xmm11[3] -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} xmm11 = xmm0[0,1,2,3,4,5,7,6] -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,1,3,2,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm15 = <0,1,0,1,0,1,1,3,16,18,19,19,19,19,u,u> -; AVX512DQ-SLOW-NEXT: vpermi2d %zmm11, %zmm0, %zmm15 -; AVX512DQ-SLOW-NEXT: vprold $16, %ymm3, %ymm0 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm11 = ymm2[1,2,2,3,5,6,6,7] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm11[0,1],ymm0[2],ymm11[3,4],ymm0[5],ymm11[6,7,8,9],ymm0[10],ymm11[11,12],ymm0[13],ymm11[14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm8 = ymm8[3,3,3,3,7,7,7,7] -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} ymm9 = ymm9[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm9 = ymm9[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm8 = ymm8[0,1,2],ymm9[3],ymm8[4,5],ymm9[6],ymm8[7,8,9,10],ymm9[11],ymm8[12,13],ymm9[14],ymm8[15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm6 = ymm6[3,3,3,3,7,7,7,7] -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} ymm7 = ymm7[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm7 = ymm7[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm6 = ymm6[0],ymm7[1],ymm6[2,3],ymm7[4],ymm6[5,6,7,8],ymm7[9],ymm6[10,11],ymm7[12],ymm6[13,14,15] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %xmm21, %xmm7 -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} xmm7 = xmm7[0,2,3,3,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm7[0,0,2,1] -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} xmm9 = xmm10[2,1,2,3,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} xmm9 = xmm9[0,1,2,3,4,5,5,4] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm9 = ymm9[0,0,1,3] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm4 = ymm4[0,0,1,1] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm10 = ymm22[2,1,3,2] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm11 = ymm12[0,2,2,3] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm12 = ymm14[2,2,3,3] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,1,3,2] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm8 = ymm8[2,1,3,3] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm6 = ymm6[0,2,2,3] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[3,3,3,3,7,7,7,7] -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} ymm3 = ymm3[0,1,2,3,5,6,7,7,8,9,10,11,13,14,15,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm3 = ymm3[2,2,2,3,6,6,6,7] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm2 = ymm3[0,1],ymm2[2],ymm3[3,4],ymm2[5],ymm3[6,7,8,9],ymm2[10],ymm3[11,12],ymm2[13],ymm3[14,15] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm2 = ymm2[2,2,2,3] -; AVX512DQ-SLOW-NEXT: vbroadcasti32x8 {{.*#+}} zmm3 = [0,5,4,0,0,6,5,0,0,5,4,0,0,6,5,0] -; AVX512DQ-SLOW-NEXT: # zmm3 = mem[0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpermd %zmm13, %zmm3, %zmm3 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm13 = ymm13[2,3,3,3,6,7,7,7] -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm16, %zmm7, %zmm7 -; AVX512DQ-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %rcx -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm17, %zmm9, %zmm9 -; AVX512DQ-SLOW-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm7, %zmm9 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm19, %zmm4, %zmm4 -; AVX512DQ-SLOW-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm4, %zmm5 -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm5 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm11, %zmm10, %zmm4 -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} zmm7 = zmm20[2,2,2,3,6,6,6,7] -; AVX512DQ-SLOW-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm4, %zmm7 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm0, %zmm12, %zmm0 -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm3 -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm7, %zmm3 -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} zmm0 = zmm1[0,0,1,1,4,4,5,5] -; AVX512DQ-SLOW-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm18, %zmm0 -; AVX512DQ-SLOW-NEXT: vpbroadcastd (%rax), %ymm1 -; AVX512DQ-SLOW-NEXT: vpbroadcastd 4(%rax), %ymm4 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm4, %zmm1, %zmm1 -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm15, %zmm1 -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1 -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm8, %ymm6 -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm0 = ymm13[2,1,3,2] -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm0 -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm6, %ymm0 -; AVX512DQ-SLOW-NEXT: vmovdqa %ymm0, 192(%rcx) -; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm1, (%rcx) -; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm3, 128(%rcx) -; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm5, 64(%rcx) -; AVX512DQ-SLOW-NEXT: vzeroupper -; AVX512DQ-SLOW-NEXT: retq +; AVX512F-SLOW-LABEL: store_i16_stride7_vf16: +; AVX512F-SLOW: # %bb.0: +; AVX512F-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512F-SLOW-NEXT: vmovdqa (%rdi), %ymm8 +; AVX512F-SLOW-NEXT: vmovdqa (%rsi), %ymm9 +; AVX512F-SLOW-NEXT: vmovdqa (%rdx), %ymm6 +; AVX512F-SLOW-NEXT: vmovdqa (%rcx), %ymm7 +; AVX512F-SLOW-NEXT: vmovdqa (%r8), %ymm2 +; AVX512F-SLOW-NEXT: vmovdqa (%r9), %ymm3 +; AVX512F-SLOW-NEXT: vmovdqa (%rax), %ymm13 +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm1 = ymm7[u,u,u,u,u,u],zero,zero,ymm7[14,15,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm7[16,17,u,u,u,u,u,u,u,u] +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm4 = ymm6[u,u,u,u,u,u,14,15],zero,zero,ymm6[u,u,u,u,u,u,u,u,u,u,16,17],zero,zero,ymm6[u,u,u,u,u,u,u,u] +; AVX512F-SLOW-NEXT: vporq %ymm1, %ymm4, %ymm16 +; AVX512F-SLOW-NEXT: vmovdqa (%rcx), %xmm14 +; AVX512F-SLOW-NEXT: vmovdqa (%rdx), %xmm15 +; AVX512F-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm15[4],xmm14[4],xmm15[5],xmm14[5],xmm15[6],xmm14[6],xmm15[7],xmm14[7] +; AVX512F-SLOW-NEXT: vmovdqa64 %xmm0, %xmm21 +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm1 = zero,zero,zero,zero,ymm9[14,15,u,u,u,u],zero,zero,zero,zero,zero,zero,zero,zero,ymm9[16,17,u,u,u,u],zero,zero,zero,zero,zero,zero,zero,zero +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm4 = ymm8[12,13,14,15],zero,zero,ymm8[u,u,u,u,u,u,u,u,u,u,16,17],zero,zero,ymm8[u,u,u,u,u,u,u,u,16,17,18,19] +; AVX512F-SLOW-NEXT: vporq %ymm1, %ymm4, %ymm17 +; AVX512F-SLOW-NEXT: vmovdqa (%rdi), %xmm1 +; AVX512F-SLOW-NEXT: vmovdqa (%rsi), %xmm4 +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm5 = ymm3[u,u,u,u,u,u,u,u,u,u],zero,zero,ymm3[14,15,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm3[16,17,u,u,u,u] +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm10 = ymm2[u,u,u,u,u,u,u,u,u,u,14,15],zero,zero,ymm2[u,u,u,u,u,u,u,u,u,u,16,17],zero,zero,ymm2[u,u,u,u] +; AVX512F-SLOW-NEXT: vporq %ymm5, %ymm10, %ymm19 +; AVX512F-SLOW-NEXT: vpbroadcastd 8(%rax), %ymm5 +; AVX512F-SLOW-NEXT: vmovdqa {{.*#+}} ymm10 = [65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535] +; AVX512F-SLOW-NEXT: vpandn %ymm5, %ymm10, %ymm5 +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm10 = ymm13[12,13,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm13[14,15,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm13[16,17,u,u] +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm10, %zmm5, %zmm5 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm10 = ymm6[0,1,1,3,4,5,5,7] +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} ymm12 = ymm7[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm12[0,0,0,0,4,4,4,4] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm10[0,1],ymm12[2],ymm10[3,4],ymm12[5],ymm10[6,7,8,9],ymm12[10],ymm10[11,12],ymm12[13],ymm10[14,15] +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm0, %ymm22 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm10 = ymm6[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm12 = ymm7[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,22,23,26,27,u,u,24,25,26,27,u,u,26,27,26,27] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm12 = ymm12[0,1],ymm10[2],ymm12[3,4],ymm10[5],ymm12[6,7,8,9],ymm10[10],ymm12[11,12],ymm10[13],ymm12[14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm10 = ymm8[1,1,1,1,5,5,5,5] +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} ymm11 = ymm9[1,2,3,3,4,5,6,7,9,10,11,11,12,13,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm11 = ymm11[0,0,2,1,4,4,6,5] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm11 = ymm11[0,1],ymm10[2],ymm11[3,4],ymm10[5],ymm11[6,7,8,9],ymm10[10],ymm11[11,12],ymm10[13],ymm11[14,15] +; AVX512F-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm10 = xmm4[4],xmm1[4],xmm4[5],xmm1[5],xmm4[6],xmm1[6],xmm4[7],xmm1[7] +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm12, %zmm11, %zmm20 +; AVX512F-SLOW-NEXT: vprold $16, %xmm4, %xmm11 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} xmm12 = xmm1[1,1,2,3] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} xmm11 = xmm12[0,1],xmm11[2],xmm12[3,4],xmm11[5],xmm12[6,7] +; AVX512F-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm12 = xmm15[0],xmm14[0],xmm15[1],xmm14[1],xmm15[2],xmm14[2],xmm15[3],xmm14[3] +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} xmm12 = xmm12[0,1,3,2,4,5,6,7] +; AVX512F-SLOW-NEXT: vbroadcasti64x4 {{.*#+}} zmm18 = [0,16,0,1,17,17,2,0,0,16,0,1,17,17,2,0] +; AVX512F-SLOW-NEXT: # zmm18 = mem[0,1,2,3,0,1,2,3] +; AVX512F-SLOW-NEXT: vpermi2d %zmm12, %zmm11, %zmm18 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm11 = ymm8[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} ymm12 = ymm9[0,1,2,3,5,4,6,7,8,9,10,11,13,12,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm12[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm12 = ymm11[0],ymm12[1],ymm11[2,3],ymm12[4],ymm11[5,6,7,8],ymm12[9],ymm11[10,11],ymm12[12],ymm11[13,14,15] +; AVX512F-SLOW-NEXT: vmovdqa (%r9), %xmm11 +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} xmm14 = xmm14[u,u,4,5,u,u,u,u,6,7,u,u,u,u,8,9] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} xmm15 = xmm15[1,1,2,2] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} xmm14 = xmm15[0],xmm14[1],xmm15[2,3],xmm14[4],xmm15[5,6],xmm14[7] +; AVX512F-SLOW-NEXT: vmovdqa (%r8), %xmm15 +; AVX512F-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3] +; AVX512F-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm15[4],xmm11[4],xmm15[5],xmm11[5],xmm15[6],xmm11[6],xmm15[7],xmm11[7] +; AVX512F-SLOW-NEXT: vmovdqa {{.*#+}} xmm0 = [0,1,2,3,4,5,4,5,6,7,10,11,8,9,10,11] +; AVX512F-SLOW-NEXT: vpshufb %xmm0, %xmm4, %xmm4 +; AVX512F-SLOW-NEXT: vpshufb %xmm0, %xmm1, %xmm0 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm14, %zmm0, %zmm1 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm2[0,0,2,1,4,4,6,5] +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} ymm14 = ymm3[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm14 = ymm14[0,0,0,0,4,4,4,4] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm14 = ymm14[0,1,2],ymm0[3],ymm14[4,5],ymm0[6],ymm14[7,8,9,10],ymm0[11],ymm14[12,13],ymm0[14],ymm14[15] +; AVX512F-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm15[0],xmm11[0],xmm15[1],xmm11[1],xmm15[2],xmm11[2],xmm15[3],xmm11[3] +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} xmm11 = xmm0[0,1,2,3,4,5,7,6] +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,1,3,2,4,5,6,7] +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm15 = <0,1,0,1,0,1,1,3,16,18,19,19,19,19,u,u> +; AVX512F-SLOW-NEXT: vpermi2d %zmm11, %zmm0, %zmm15 +; AVX512F-SLOW-NEXT: vprold $16, %ymm3, %ymm0 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm11 = ymm2[1,2,2,3,5,6,6,7] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm11[0,1],ymm0[2],ymm11[3,4],ymm0[5],ymm11[6,7,8,9],ymm0[10],ymm11[11,12],ymm0[13],ymm11[14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm8 = ymm8[3,3,3,3,7,7,7,7] +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} ymm9 = ymm9[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm9 = ymm9[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm8 = ymm8[0,1,2],ymm9[3],ymm8[4,5],ymm9[6],ymm8[7,8,9,10],ymm9[11],ymm8[12,13],ymm9[14],ymm8[15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm6 = ymm6[3,3,3,3,7,7,7,7] +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} ymm7 = ymm7[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm7 = ymm7[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm6 = ymm6[0],ymm7[1],ymm6[2,3],ymm7[4],ymm6[5,6,7,8],ymm7[9],ymm6[10,11],ymm7[12],ymm6[13,14,15] +; AVX512F-SLOW-NEXT: vmovdqa64 %xmm21, %xmm7 +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} xmm7 = xmm7[0,2,3,3,4,5,6,7] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm7[0,0,2,1] +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} xmm9 = xmm10[2,1,2,3,4,5,6,7] +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} xmm9 = xmm9[0,1,2,3,4,5,5,4] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm9 = ymm9[0,0,1,3] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm4 = ymm4[0,0,1,1] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm10 = ymm22[2,1,3,2] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm11 = ymm12[0,2,2,3] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm12 = ymm14[2,2,3,3] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,1,3,2] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm8 = ymm8[2,1,3,3] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm6 = ymm6[0,2,2,3] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[3,3,3,3,7,7,7,7] +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} ymm3 = ymm3[0,1,2,3,5,6,7,7,8,9,10,11,13,14,15,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm3 = ymm3[2,2,2,3,6,6,6,7] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm2 = ymm3[0,1],ymm2[2],ymm3[3,4],ymm2[5],ymm3[6,7,8,9],ymm2[10],ymm3[11,12],ymm2[13],ymm3[14,15] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm2 = ymm2[2,2,2,3] +; AVX512F-SLOW-NEXT: vbroadcasti64x4 {{.*#+}} zmm3 = [0,5,4,0,0,6,5,0,0,5,4,0,0,6,5,0] +; AVX512F-SLOW-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3] +; AVX512F-SLOW-NEXT: vpermd %zmm13, %zmm3, %zmm3 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm13 = ymm13[2,3,3,3,6,7,7,7] +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm16, %zmm7, %zmm7 +; AVX512F-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %rcx +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm17, %zmm9, %zmm9 +; AVX512F-SLOW-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm7, %zmm9 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm19, %zmm4, %zmm4 +; AVX512F-SLOW-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm4, %zmm5 +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm5 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm11, %zmm10, %zmm4 +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} zmm7 = zmm20[2,2,2,3,6,6,6,7] +; AVX512F-SLOW-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm4, %zmm7 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm0, %zmm12, %zmm0 +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm3 +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm7, %zmm3 +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} zmm0 = zmm1[0,0,1,1,4,4,5,5] +; AVX512F-SLOW-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm18, %zmm0 +; AVX512F-SLOW-NEXT: vpbroadcastd (%rax), %ymm1 +; AVX512F-SLOW-NEXT: vpbroadcastd 4(%rax), %ymm4 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm4, %zmm1, %zmm1 +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm15, %zmm1 +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1 +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm8, %ymm6 +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm0 = ymm13[2,1,3,2] +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm0 +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm6, %ymm0 +; AVX512F-SLOW-NEXT: vmovdqa %ymm0, 192(%rcx) +; AVX512F-SLOW-NEXT: vmovdqa64 %zmm1, (%rcx) +; AVX512F-SLOW-NEXT: vmovdqa64 %zmm3, 128(%rcx) +; AVX512F-SLOW-NEXT: vmovdqa64 %zmm5, 64(%rcx) +; AVX512F-SLOW-NEXT: vzeroupper +; AVX512F-SLOW-NEXT: retq ; -; AVX512DQ-FAST-LABEL: store_i16_stride7_vf16: -; AVX512DQ-FAST: # %bb.0: -; AVX512DQ-FAST-NEXT: vmovdqa (%rdi), %ymm5 -; AVX512DQ-FAST-NEXT: vmovdqa (%rsi), %ymm7 -; AVX512DQ-FAST-NEXT: vmovdqa (%rdx), %ymm4 -; AVX512DQ-FAST-NEXT: vmovdqa (%rcx), %ymm6 -; AVX512DQ-FAST-NEXT: vmovdqa (%r8), %ymm1 -; AVX512DQ-FAST-NEXT: vmovdqa (%r9), %ymm2 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm0 = zero,zero,zero,zero,ymm7[14,15,u,u,u,u],zero,zero,zero,zero,zero,zero,zero,zero,ymm7[16,17,u,u,u,u],zero,zero,zero,zero,zero,zero,zero,zero -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm3 = ymm5[12,13,14,15],zero,zero,ymm5[u,u,u,u,u,u,u,u,u,u,16,17],zero,zero,ymm5[u,u,u,u,u,u,u,u,16,17,18,19] -; AVX512DQ-FAST-NEXT: vporq %ymm0, %ymm3, %ymm16 -; AVX512DQ-FAST-NEXT: vmovdqa (%rdi), %xmm11 -; AVX512DQ-FAST-NEXT: vmovdqa (%rsi), %xmm12 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm6[u,u,u,u,u,u],zero,zero,ymm6[14,15,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm6[16,17,u,u,u,u,u,u,u,u] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm3 = ymm4[u,u,u,u,u,u,14,15],zero,zero,ymm4[u,u,u,u,u,u,u,u,u,u,16,17],zero,zero,ymm4[u,u,u,u,u,u,u,u] -; AVX512DQ-FAST-NEXT: vporq %ymm0, %ymm3, %ymm17 -; AVX512DQ-FAST-NEXT: vmovdqa (%rcx), %xmm14 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm2[u,u,u,u,u,u,u,u,u,u],zero,zero,ymm2[14,15,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm2[16,17,u,u,u,u] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm3 = ymm1[u,u,u,u,u,u,u,u,u,u,14,15],zero,zero,ymm1[u,u,u,u,u,u,u,u,u,u,16,17],zero,zero,ymm1[u,u,u,u] -; AVX512DQ-FAST-NEXT: vporq %ymm0, %ymm3, %ymm18 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm7[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,24,25,u,u,u,u,26,27,u,u,u,u,u,u] -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm5[2,2,2,2,6,6,6,6] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm3[0],ymm0[1],ymm3[2,3],ymm0[4],ymm3[5,6,7,8],ymm0[9],ymm3[10,11],ymm0[12],ymm3[13,14,15] -; AVX512DQ-FAST-NEXT: vpunpcklwd {{.*#+}} ymm3 = ymm6[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11] -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm9 = ymm4[0,1,1,3,4,5,5,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm9[0,1],ymm3[2],ymm9[3,4],ymm3[5],ymm9[6,7,8,9],ymm3[10],ymm9[11,12],ymm3[13],ymm9[14,15] -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm9 = <2,u,3,2,u,10,10,11> -; AVX512DQ-FAST-NEXT: vpermi2q %zmm0, %zmm3, %zmm9 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm0 = ymm4[2,2,2,2,6,6,6,6] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm3 = ymm6[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,22,23,26,27,u,u,24,25,26,27,u,u,26,27,26,27] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm3[0,1],ymm0[2],ymm3[3,4],ymm0[5],ymm3[6,7,8,9],ymm0[10],ymm3[11,12],ymm0[13],ymm3[14,15] -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm5[1,1,1,1,5,5,5,5] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm10 = ymm7[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,20,21,u,u,20,21,24,25,u,u,22,23,22,23] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm10[0,1],ymm3[2],ymm10[3,4],ymm3[5],ymm10[6,7,8,9],ymm3[10],ymm10[11,12],ymm3[13],ymm10[14,15] -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm3, %zmm19 -; AVX512DQ-FAST-NEXT: vprold $16, %ymm2, %ymm0 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm1[1,2,2,3,5,6,6,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm3[0,1],ymm0[2],ymm3[3,4],ymm0[5],ymm3[6,7,8,9],ymm0[10],ymm3[11,12],ymm0[13],ymm3[14,15] -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm1[0,0,2,1,4,4,6,5] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm13 = ymm2[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,20,21,18,19,u,u,18,19,20,21,u,u,20,21] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm13[0,1,2],ymm3[3],ymm13[4,5],ymm3[6],ymm13[7,8,9,10],ymm3[11],ymm13[12,13],ymm3[14],ymm13[15] -; AVX512DQ-FAST-NEXT: vmovdqa (%rdx), %xmm8 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm13 = [2,2,3,3,10,9,11,10] -; AVX512DQ-FAST-NEXT: vpermi2q %zmm0, %zmm3, %zmm13 -; AVX512DQ-FAST-NEXT: vprold $16, %xmm12, %xmm0 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} xmm3 = xmm11[1,1,2,3] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} xmm0 = xmm3[0,1],xmm0[2],xmm3[3,4],xmm0[5],xmm3[6,7] -; AVX512DQ-FAST-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm8[0],xmm14[0],xmm8[1],xmm14[1],xmm8[2],xmm14[2],xmm8[3],xmm14[3] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} xmm3 = xmm3[0,1,2,3,0,1,2,3,6,7,4,5,6,7,4,5] -; AVX512DQ-FAST-NEXT: vbroadcasti32x8 {{.*#+}} zmm15 = [0,8,1,9,0,8,1,9] -; AVX512DQ-FAST-NEXT: # zmm15 = mem[0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7] -; AVX512DQ-FAST-NEXT: vpermi2q %zmm0, %zmm3, %zmm15 -; AVX512DQ-FAST-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm12[4],xmm11[4],xmm12[5],xmm11[5],xmm12[6],xmm11[6],xmm12[7],xmm11[7] -; AVX512DQ-FAST-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm8[4],xmm14[4],xmm8[5],xmm14[5],xmm8[6],xmm14[6],xmm8[7],xmm14[7] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} xmm14 = xmm14[u,u,4,5,u,u,u,u,6,7,u,u,u,u,8,9] -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} xmm8 = xmm8[1,1,2,2] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} xmm8 = xmm8[0],xmm14[1],xmm8[2,3],xmm14[4],xmm8[5,6],xmm14[7] -; AVX512DQ-FAST-NEXT: vmovdqa (%r9), %xmm14 -; AVX512DQ-FAST-NEXT: vpunpcklwd {{.*#+}} xmm11 = xmm11[0],xmm12[0],xmm11[1],xmm12[1],xmm11[2],xmm12[2],xmm11[3],xmm12[3] -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} xmm12 = [0,1,2,3,4,5,4,5,6,7,10,11,8,9,10,11] -; AVX512DQ-FAST-NEXT: vpshufb %xmm12, %xmm11, %xmm11 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm8, %zmm11, %zmm11 -; AVX512DQ-FAST-NEXT: vmovdqa (%r8), %xmm8 -; AVX512DQ-FAST-NEXT: vpunpckhwd {{.*#+}} xmm10 = xmm8[4],xmm14[4],xmm8[5],xmm14[5],xmm8[6],xmm14[6],xmm8[7],xmm14[7] -; AVX512DQ-FAST-NEXT: vpshufb %xmm12, %xmm10, %xmm12 -; AVX512DQ-FAST-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQ-FAST-NEXT: vpbroadcastd 8(%rax), %ymm10 -; AVX512DQ-FAST-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm10, %ymm10 -; AVX512DQ-FAST-NEXT: vpunpcklwd {{.*#+}} xmm8 = xmm8[0],xmm14[0],xmm8[1],xmm14[1],xmm8[2],xmm14[2],xmm8[3],xmm14[3] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} xmm14 = xmm8[0,1,2,3,8,9,10,11,14,15,12,13,14,15,12,13] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} xmm8 = xmm8[0,1,2,3,6,7,4,5,6,7,4,5,12,13,14,15] -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm20 = [0,0,0,1,8,9,9,11] -; AVX512DQ-FAST-NEXT: vpermi2q %zmm14, %zmm8, %zmm20 -; AVX512DQ-FAST-NEXT: vbroadcasti64x4 {{.*#+}} zmm8 = mem[0,1,2,3,0,1,2,3] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm14 = ymm8[12,13,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm8[14,15,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm8[16,17,u,u] -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm14, %zmm10, %zmm10 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm7 = ymm7[u,u,u,u,u,u,u,u,u,u,u,u,14,15,u,u,u,u,u,u,u,u,28,29,u,u,u,u,30,31,u,u] -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm5 = ymm5[3,3,3,3,7,7,7,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm5 = ymm5[0,1,2],ymm7[3],ymm5[4,5],ymm7[6],ymm5[7,8,9,10],ymm7[11],ymm5[12,13],ymm7[14],ymm5[15] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm6 = ymm6[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,28,29,u,u,u,u,30,31,u,u,u,u,u,u] -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm4 = ymm4[3,3,3,3,7,7,7,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm4 = ymm4[0],ymm6[1],ymm4[2,3],ymm6[4],ymm4[5,6,7,8],ymm6[9],ymm4[10,11],ymm6[12],ymm4[13,14,15] -; AVX512DQ-FAST-NEXT: vbroadcasti64x4 {{.*#+}} zmm6 = [0,13,4,0,0,14,5,0,0,13,4,0,0,14,5,0] -; AVX512DQ-FAST-NEXT: # zmm6 = mem[0,1,2,3,0,1,2,3] -; AVX512DQ-FAST-NEXT: vpermd %zmm8, %zmm6, %zmm6 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm7 = <6,u,u,u,7,u,u,7> -; AVX512DQ-FAST-NEXT: vpermd %ymm8, %ymm7, %ymm7 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} xmm3 = xmm3[4,5,2,3,4,5,6,7,8,9,10,11,10,11,8,9] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,0,1,3] -; AVX512DQ-FAST-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,3,3,4,5,6,7] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,0,2,1] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm8 = ymm12[0,0,1,1] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm5 = ymm5[2,1,3,3] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm4 = ymm4[0,2,2,3] -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[3,3,3,3,7,7,7,7] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm2[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,26,27,28,29,u,u,28,29,26,27,u,u,30,31,30,31] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0,1],ymm1[2],ymm2[3,4],ymm1[5],ymm2[6,7,8,9],ymm1[10],ymm2[11,12],ymm1[13],ymm2[14,15] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,2,2,3] -; AVX512DQ-FAST-NEXT: movq {{[0-9]+}}(%rsp), %rcx -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm16, %zmm3, %zmm2 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm17, %zmm0, %zmm0 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm0 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm18, %zmm8, %zmm2 -; AVX512DQ-FAST-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm10 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm10 -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} zmm0 = zmm19[2,2,2,3,6,6,6,7] -; AVX512DQ-FAST-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm0 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm13, %zmm6 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm6 -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} zmm0 = zmm11[0,0,1,1,4,4,5,5] -; AVX512DQ-FAST-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm15, %zmm0 -; AVX512DQ-FAST-NEXT: vpbroadcastd (%rax), %ymm2 -; AVX512DQ-FAST-NEXT: vpbroadcastd 4(%rax), %ymm3 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm2 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm20, %zmm2 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm2 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm5, %ymm4 -; AVX512DQ-FAST-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm7, %ymm1 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm1 -; AVX512DQ-FAST-NEXT: vmovdqa %ymm1, 192(%rcx) -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm2, (%rcx) -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm6, 128(%rcx) -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm10, 64(%rcx) -; AVX512DQ-FAST-NEXT: vzeroupper -; AVX512DQ-FAST-NEXT: retq +; AVX512F-FAST-LABEL: store_i16_stride7_vf16: +; AVX512F-FAST: # %bb.0: +; AVX512F-FAST-NEXT: vmovdqa (%rdi), %ymm5 +; AVX512F-FAST-NEXT: vmovdqa (%rsi), %ymm7 +; AVX512F-FAST-NEXT: vmovdqa (%rdx), %ymm4 +; AVX512F-FAST-NEXT: vmovdqa (%rcx), %ymm6 +; AVX512F-FAST-NEXT: vmovdqa (%r8), %ymm1 +; AVX512F-FAST-NEXT: vmovdqa (%r9), %ymm2 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm0 = zero,zero,zero,zero,ymm7[14,15,u,u,u,u],zero,zero,zero,zero,zero,zero,zero,zero,ymm7[16,17,u,u,u,u],zero,zero,zero,zero,zero,zero,zero,zero +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm3 = ymm5[12,13,14,15],zero,zero,ymm5[u,u,u,u,u,u,u,u,u,u,16,17],zero,zero,ymm5[u,u,u,u,u,u,u,u,16,17,18,19] +; AVX512F-FAST-NEXT: vporq %ymm0, %ymm3, %ymm16 +; AVX512F-FAST-NEXT: vmovdqa (%rdi), %xmm11 +; AVX512F-FAST-NEXT: vmovdqa (%rsi), %xmm12 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm6[u,u,u,u,u,u],zero,zero,ymm6[14,15,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm6[16,17,u,u,u,u,u,u,u,u] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm3 = ymm4[u,u,u,u,u,u,14,15],zero,zero,ymm4[u,u,u,u,u,u,u,u,u,u,16,17],zero,zero,ymm4[u,u,u,u,u,u,u,u] +; AVX512F-FAST-NEXT: vporq %ymm0, %ymm3, %ymm17 +; AVX512F-FAST-NEXT: vmovdqa (%rcx), %xmm14 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm2[u,u,u,u,u,u,u,u,u,u],zero,zero,ymm2[14,15,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm2[16,17,u,u,u,u] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm3 = ymm1[u,u,u,u,u,u,u,u,u,u,14,15],zero,zero,ymm1[u,u,u,u,u,u,u,u,u,u,16,17],zero,zero,ymm1[u,u,u,u] +; AVX512F-FAST-NEXT: vporq %ymm0, %ymm3, %ymm18 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm7[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,24,25,u,u,u,u,26,27,u,u,u,u,u,u] +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm5[2,2,2,2,6,6,6,6] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm3[0],ymm0[1],ymm3[2,3],ymm0[4],ymm3[5,6,7,8],ymm0[9],ymm3[10,11],ymm0[12],ymm3[13,14,15] +; AVX512F-FAST-NEXT: vpunpcklwd {{.*#+}} ymm3 = ymm6[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11] +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm9 = ymm4[0,1,1,3,4,5,5,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm9[0,1],ymm3[2],ymm9[3,4],ymm3[5],ymm9[6,7,8,9],ymm3[10],ymm9[11,12],ymm3[13],ymm9[14,15] +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm9 = <2,u,3,2,u,10,10,11> +; AVX512F-FAST-NEXT: vpermi2q %zmm0, %zmm3, %zmm9 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm0 = ymm4[2,2,2,2,6,6,6,6] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm3 = ymm6[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,22,23,26,27,u,u,24,25,26,27,u,u,26,27,26,27] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm3[0,1],ymm0[2],ymm3[3,4],ymm0[5],ymm3[6,7,8,9],ymm0[10],ymm3[11,12],ymm0[13],ymm3[14,15] +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm5[1,1,1,1,5,5,5,5] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm10 = ymm7[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,20,21,u,u,20,21,24,25,u,u,22,23,22,23] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm10[0,1],ymm3[2],ymm10[3,4],ymm3[5],ymm10[6,7,8,9],ymm3[10],ymm10[11,12],ymm3[13],ymm10[14,15] +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm3, %zmm19 +; AVX512F-FAST-NEXT: vprold $16, %ymm2, %ymm0 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm1[1,2,2,3,5,6,6,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm3[0,1],ymm0[2],ymm3[3,4],ymm0[5],ymm3[6,7,8,9],ymm0[10],ymm3[11,12],ymm0[13],ymm3[14,15] +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm1[0,0,2,1,4,4,6,5] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm13 = ymm2[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,20,21,18,19,u,u,18,19,20,21,u,u,20,21] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm13[0,1,2],ymm3[3],ymm13[4,5],ymm3[6],ymm13[7,8,9,10],ymm3[11],ymm13[12,13],ymm3[14],ymm13[15] +; AVX512F-FAST-NEXT: vmovdqa (%rdx), %xmm8 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm13 = [2,2,3,3,10,9,11,10] +; AVX512F-FAST-NEXT: vpermi2q %zmm0, %zmm3, %zmm13 +; AVX512F-FAST-NEXT: vprold $16, %xmm12, %xmm0 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} xmm3 = xmm11[1,1,2,3] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} xmm0 = xmm3[0,1],xmm0[2],xmm3[3,4],xmm0[5],xmm3[6,7] +; AVX512F-FAST-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm8[0],xmm14[0],xmm8[1],xmm14[1],xmm8[2],xmm14[2],xmm8[3],xmm14[3] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} xmm3 = xmm3[0,1,2,3,0,1,2,3,6,7,4,5,6,7,4,5] +; AVX512F-FAST-NEXT: vbroadcasti64x4 {{.*#+}} zmm15 = [0,8,1,9,0,8,1,9] +; AVX512F-FAST-NEXT: # zmm15 = mem[0,1,2,3,0,1,2,3] +; AVX512F-FAST-NEXT: vpermi2q %zmm0, %zmm3, %zmm15 +; AVX512F-FAST-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm12[4],xmm11[4],xmm12[5],xmm11[5],xmm12[6],xmm11[6],xmm12[7],xmm11[7] +; AVX512F-FAST-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm8[4],xmm14[4],xmm8[5],xmm14[5],xmm8[6],xmm14[6],xmm8[7],xmm14[7] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} xmm14 = xmm14[u,u,4,5,u,u,u,u,6,7,u,u,u,u,8,9] +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} xmm8 = xmm8[1,1,2,2] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} xmm8 = xmm8[0],xmm14[1],xmm8[2,3],xmm14[4],xmm8[5,6],xmm14[7] +; AVX512F-FAST-NEXT: vmovdqa (%r9), %xmm14 +; AVX512F-FAST-NEXT: vpunpcklwd {{.*#+}} xmm11 = xmm11[0],xmm12[0],xmm11[1],xmm12[1],xmm11[2],xmm12[2],xmm11[3],xmm12[3] +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} xmm12 = [0,1,2,3,4,5,4,5,6,7,10,11,8,9,10,11] +; AVX512F-FAST-NEXT: vpshufb %xmm12, %xmm11, %xmm11 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm8, %zmm11, %zmm11 +; AVX512F-FAST-NEXT: vmovdqa (%r8), %xmm8 +; AVX512F-FAST-NEXT: vpunpckhwd {{.*#+}} xmm10 = xmm8[4],xmm14[4],xmm8[5],xmm14[5],xmm8[6],xmm14[6],xmm8[7],xmm14[7] +; AVX512F-FAST-NEXT: vpshufb %xmm12, %xmm10, %xmm12 +; AVX512F-FAST-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512F-FAST-NEXT: vpbroadcastd 8(%rax), %ymm10 +; AVX512F-FAST-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm10, %ymm10 +; AVX512F-FAST-NEXT: vpunpcklwd {{.*#+}} xmm8 = xmm8[0],xmm14[0],xmm8[1],xmm14[1],xmm8[2],xmm14[2],xmm8[3],xmm14[3] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} xmm14 = xmm8[0,1,2,3,8,9,10,11,14,15,12,13,14,15,12,13] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} xmm8 = xmm8[0,1,2,3,6,7,4,5,6,7,4,5,12,13,14,15] +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm20 = [0,0,0,1,8,9,9,11] +; AVX512F-FAST-NEXT: vpermi2q %zmm14, %zmm8, %zmm20 +; AVX512F-FAST-NEXT: vbroadcasti64x4 {{.*#+}} zmm8 = mem[0,1,2,3,0,1,2,3] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm14 = ymm8[12,13,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm8[14,15,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm8[16,17,u,u] +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm14, %zmm10, %zmm10 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm7 = ymm7[u,u,u,u,u,u,u,u,u,u,u,u,14,15,u,u,u,u,u,u,u,u,28,29,u,u,u,u,30,31,u,u] +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm5 = ymm5[3,3,3,3,7,7,7,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm5 = ymm5[0,1,2],ymm7[3],ymm5[4,5],ymm7[6],ymm5[7,8,9,10],ymm7[11],ymm5[12,13],ymm7[14],ymm5[15] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm6 = ymm6[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,28,29,u,u,u,u,30,31,u,u,u,u,u,u] +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm4 = ymm4[3,3,3,3,7,7,7,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm4 = ymm4[0],ymm6[1],ymm4[2,3],ymm6[4],ymm4[5,6,7,8],ymm6[9],ymm4[10,11],ymm6[12],ymm4[13,14,15] +; AVX512F-FAST-NEXT: vbroadcasti64x4 {{.*#+}} zmm6 = [0,13,4,0,0,14,5,0,0,13,4,0,0,14,5,0] +; AVX512F-FAST-NEXT: # zmm6 = mem[0,1,2,3,0,1,2,3] +; AVX512F-FAST-NEXT: vpermd %zmm8, %zmm6, %zmm6 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm7 = <6,u,u,u,7,u,u,7> +; AVX512F-FAST-NEXT: vpermd %ymm8, %ymm7, %ymm7 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} xmm3 = xmm3[4,5,2,3,4,5,6,7,8,9,10,11,10,11,8,9] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,0,1,3] +; AVX512F-FAST-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,3,3,4,5,6,7] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,0,2,1] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm8 = ymm12[0,0,1,1] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm5 = ymm5[2,1,3,3] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm4 = ymm4[0,2,2,3] +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[3,3,3,3,7,7,7,7] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm2[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,26,27,28,29,u,u,28,29,26,27,u,u,30,31,30,31] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0,1],ymm1[2],ymm2[3,4],ymm1[5],ymm2[6,7,8,9],ymm1[10],ymm2[11,12],ymm1[13],ymm2[14,15] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,2,2,3] +; AVX512F-FAST-NEXT: movq {{[0-9]+}}(%rsp), %rcx +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm16, %zmm3, %zmm2 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm17, %zmm0, %zmm0 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm0 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm18, %zmm8, %zmm2 +; AVX512F-FAST-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm10 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm10 +; AVX512F-FAST-NEXT: vpermq {{.*#+}} zmm0 = zmm19[2,2,2,3,6,6,6,7] +; AVX512F-FAST-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm0 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm13, %zmm6 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm6 +; AVX512F-FAST-NEXT: vpermq {{.*#+}} zmm0 = zmm11[0,0,1,1,4,4,5,5] +; AVX512F-FAST-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm15, %zmm0 +; AVX512F-FAST-NEXT: vpbroadcastd (%rax), %ymm2 +; AVX512F-FAST-NEXT: vpbroadcastd 4(%rax), %ymm3 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm2 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm20, %zmm2 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm2 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm5, %ymm4 +; AVX512F-FAST-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm7, %ymm1 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm1 +; AVX512F-FAST-NEXT: vmovdqa %ymm1, 192(%rcx) +; AVX512F-FAST-NEXT: vmovdqa64 %zmm2, (%rcx) +; AVX512F-FAST-NEXT: vmovdqa64 %zmm6, 128(%rcx) +; AVX512F-FAST-NEXT: vmovdqa64 %zmm10, 64(%rcx) +; AVX512F-FAST-NEXT: vzeroupper +; AVX512F-FAST-NEXT: retq ; ; AVX512BW-LABEL: store_i16_stride7_vf16: ; AVX512BW: # %bb.0: @@ -5248,1251 +4982,628 @@ define void @store_i16_stride7_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve ; AVX2-FAST-PERLANE-NEXT: vzeroupper ; AVX2-FAST-PERLANE-NEXT: retq ; -; AVX512F-ONLY-SLOW-LABEL: store_i16_stride7_vf32: -; AVX512F-ONLY-SLOW: # %bb.0: -; AVX512F-ONLY-SLOW-NEXT: subq $632, %rsp # imm = 0x278 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rcx), %ymm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} ymm9 = [128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128,128,128,128,128] -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm9, %ymm1, %ymm0 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm1, %ymm16 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rdx), %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} ymm13 = -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm13, %ymm2, %ymm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm2, %ymm29 -; AVX512F-ONLY-SLOW-NEXT: vpor %ymm0, %ymm1, %ymm0 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rsi), %ymm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} ymm12 = [128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128,128,128,128,128,128,128,128,128] -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm12, %ymm1, %ymm0 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa %ymm1, %ymm15 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rdi), %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} ymm14 = <12,13,14,15,128,128,u,u,u,u,u,u,u,u,u,u,16,17,128,128,u,u,u,u,u,u,u,u,16,17,18,19> -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm14, %ymm2, %ymm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm2, %ymm17 -; AVX512F-ONLY-SLOW-NEXT: vpor %ymm0, %ymm1, %ymm0 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%r9), %ymm10 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} ymm1 = [128,128,128,128,128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128] -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm1, %ymm10, %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%r8), %ymm11 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} ymm0 = -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm0, %ymm11, %ymm3 -; AVX512F-ONLY-SLOW-NEXT: vpor %ymm2, %ymm3, %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm2, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 32(%r9), %xmm3 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 32(%r8), %xmm6 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm11[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm4 = ymm10[0,1,2,3,5,6,7,7,8,9,10,11,13,14,15,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm4 = ymm4[2,2,2,3,6,6,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm4 = ymm4[0,1],ymm2[2],ymm4[3,4],ymm2[5],ymm4[6,7,8,9],ymm2[10],ymm4[11,12],ymm2[13],ymm4[14,15] -; AVX512F-ONLY-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm6[0],xmm3[0],xmm6[1],xmm3[1],xmm6[2],xmm3[2],xmm6[3],xmm3[3] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm7 = [4,5,4,5,4,5,6,7,16,17,16,17,16,17,17,19] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} xmm5 = xmm2[0,1,3,2,4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpermi2d %zmm5, %zmm4, %zmm7 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rcx), %xmm8 -; AVX512F-ONLY-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm6[4],xmm3[4],xmm6[5],xmm3[5],xmm6[6],xmm3[6],xmm6[7],xmm3[7] -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,5,7,6] -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} xmm3 = xmm3[0,1,2,3,4,5,4,5,6,7,10,11,8,9,10,11] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm4 = <16,18,19,19,19,19,u,u,0,1,0,1,2,3,2,3> -; AVX512F-ONLY-SLOW-NEXT: vpermi2d %zmm2, %zmm3, %zmm4 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 32(%rdi), %ymm3 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 32(%rsi), %ymm6 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm12, %ymm6, %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm14, %ymm3, %ymm4 -; AVX512F-ONLY-SLOW-NEXT: vpor %ymm2, %ymm4, %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 32(%rcx), %ymm12 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 32(%rdx), %ymm7 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm9, %ymm12, %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm13, %ymm7, %ymm4 -; AVX512F-ONLY-SLOW-NEXT: vpor %ymm2, %ymm4, %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 32(%r9), %ymm13 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 32(%r8), %ymm14 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm1, %ymm13, %ymm1 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm0, %ymm14, %ymm0 -; AVX512F-ONLY-SLOW-NEXT: vpor %ymm1, %ymm0, %ymm0 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rdx), %xmm0 -; AVX512F-ONLY-SLOW-NEXT: vpbroadcastq {{.*#+}} xmm2 = [6,7,4,5,0,0,8,9,6,7,4,5,0,0,8,9] -; AVX512F-ONLY-SLOW-NEXT: vpshufb %xmm2, %xmm8, %xmm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %xmm2, %xmm20 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,2,2] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0],xmm1[1],xmm2[2,3],xmm1[4],xmm2[5,6],xmm1[7] -; AVX512F-ONLY-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm0[0],xmm8[0],xmm0[1],xmm8[1],xmm0[2],xmm8[2],xmm0[3],xmm8[3] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} xmm2 = xmm2[0,1,3,2,4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm4 = -; AVX512F-ONLY-SLOW-NEXT: vpermi2d %zmm2, %zmm1, %zmm4 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%r9), %xmm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%r8), %xmm2 -; AVX512F-ONLY-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm4 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3] -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} xmm5 = xmm4[0,1,2,3,4,5,7,6] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} xmm4 = xmm4[0,1,3,2,4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm9 = <0,1,0,1,0,1,1,3,16,18,19,19,19,19,u,u> -; AVX512F-ONLY-SLOW-NEXT: vpermi2d %zmm5, %zmm4, %zmm9 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vprold $16, %ymm10, %ymm4 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm5 = ymm11[1,2,2,3,5,6,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm4 = ymm5[0,1],ymm4[2],ymm5[3,4],ymm4[5],ymm5[6,7,8,9],ymm4[10],ymm5[11,12],ymm4[13],ymm5[14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm5 = ymm11[0,0,2,1,4,4,6,5] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} ymm9 = ymm10[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm9 = ymm9[0,0,0,0,4,4,4,4] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm5 = ymm9[0,1,2],ymm5[3],ymm9[4,5],ymm5[6],ymm9[7,8,9,10],ymm5[11],ymm9[12,13],ymm5[14],ymm9[15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm27 = [2,2,3,3,10,9,11,10] -; AVX512F-ONLY-SLOW-NEXT: vpermi2q %zmm4, %zmm5, %zmm27 -; AVX512F-ONLY-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512F-ONLY-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm8[4],xmm0[5],xmm8[5],xmm0[6],xmm8[6],xmm0[7],xmm8[7] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %xmm0, %xmm31 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rax), %ymm4 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm4, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpbroadcastd 8(%rax), %ymm0 -; AVX512F-ONLY-SLOW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} ymm5 = [12,13,128,128,128,128,128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128] -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm5, %ymm4, %ymm4 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm5, %ymm28 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm4, %zmm0, %zmm0 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7] -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm0 = ymm12[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,22,23,26,27,u,u,24,25,26,27,u,u,26,27,26,27] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm7[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3,4],ymm1[5],ymm0[6,7,8,9],ymm1[10],ymm0[11,12],ymm1[13],ymm0[14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm0, %ymm30 -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm12[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm7[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2,3],ymm0[4],ymm1[5,6,7,8],ymm0[9],ymm1[10,11],ymm0[12],ymm1[13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm0, %ymm23 -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm6[0,1,2,3,5,4,6,7,8,9,10,11,13,12,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm3[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm10 = ymm1[0],ymm0[1],ymm1[2,3],ymm0[4],ymm1[5,6,7,8],ymm0[9],ymm1[10,11],ymm0[12],ymm1[13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm6[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm3[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3],ymm1[4,5],ymm0[6],ymm1[7,8,9,10],ymm0[11],ymm1[12,13],ymm0[14],ymm1[15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm0, %ymm19 -; AVX512F-ONLY-SLOW-NEXT: vprold $16, %ymm13, %ymm0 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm14[1,2,2,3,5,6,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1],ymm0[2],ymm1[3,4],ymm0[5],ymm1[6,7,8,9],ymm0[10],ymm1[11,12],ymm0[13],ymm1[14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm13[0,1,2,3,5,6,7,7,8,9,10,11,13,14,15,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,2,2,3,6,6,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm14[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3,4],ymm1[5],ymm0[6,7,8,9],ymm1[10],ymm0[11,12],ymm1[13],ymm0[14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm16, %ymm4 -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm4[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm29[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm5 = ymm1[0],ymm0[1],ymm1[2,3],ymm0[4],ymm1[5,6,7,8],ymm0[9],ymm1[10,11],ymm0[12],ymm1[13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm5, %ymm18 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa %ymm15, %ymm8 -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm15[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm17[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm5 = ymm1[0,1,2],ymm0[3],ymm1[4,5],ymm0[6],ymm1[7,8,9,10],ymm0[11],ymm1[12,13],ymm0[14],ymm1[15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 32(%rdi), %xmm0 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 32(%rsi), %xmm9 -; AVX512F-ONLY-SLOW-NEXT: vprold $16, %xmm9, %xmm1 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} xmm15 = xmm0[1,1,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} xmm1 = xmm15[0,1],xmm1[2],xmm15[3,4],xmm1[5],xmm15[6,7] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm0[0],xmm9[0],xmm0[1],xmm9[1],xmm0[2],xmm9[2],xmm0[3],xmm9[3] -; AVX512F-ONLY-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm9[4],xmm0[4],xmm9[5],xmm0[5],xmm9[6],xmm0[6],xmm9[7],xmm0[7] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 32(%rcx), %xmm9 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %xmm20, %xmm0 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %xmm0, %xmm9, %xmm0 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 32(%rdx), %xmm15 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} xmm11 = xmm15[1,1,2,2] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} xmm0 = xmm11[0],xmm0[1],xmm11[2,3],xmm0[4],xmm11[5,6],xmm0[7] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm0, %ymm26 -; AVX512F-ONLY-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm15[0],xmm9[0],xmm15[1],xmm9[1],xmm15[2],xmm9[2],xmm15[3],xmm9[3] -; AVX512F-ONLY-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm9 = xmm15[4],xmm9[4],xmm15[5],xmm9[5],xmm15[6],xmm9[6],xmm15[7],xmm9[7] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %xmm9, %xmm25 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm3 = ymm3[1,1,1,1,5,5,5,5] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} ymm6 = ymm6[1,2,3,3,4,5,6,7,9,10,11,11,12,13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm6 = ymm6[0,0,2,1,4,4,6,5] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm3 = ymm6[0,1],ymm3[2],ymm6[3,4],ymm3[5],ymm6[6,7,8,9],ymm3[10],ymm6[11,12],ymm3[13],ymm6[14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm3, %ymm24 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm3 = ymm7[0,1,1,3,4,5,5,7] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} ymm6 = ymm12[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm6 = ymm6[0,0,0,0,4,4,4,4] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm3 = ymm3[0,1],ymm6[2],ymm3[3,4],ymm6[5],ymm3[6,7,8,9],ymm6[10],ymm3[11,12],ymm6[13],ymm3[14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm3, %ymm22 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm3 = ymm14[0,0,2,1,4,4,6,5] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} ymm6 = ymm13[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm6 = ymm6[0,0,0,0,4,4,4,4] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm3 = ymm6[0,1,2],ymm3[3],ymm6[4,5],ymm3[6],ymm6[7,8,9,10],ymm3[11],ymm6[12,13],ymm3[14],ymm6[15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm3, %ymm21 -; AVX512F-ONLY-SLOW-NEXT: vbroadcasti64x4 {{.*#+}} zmm3 = [6,5,0,0,7,6,0,7,6,5,0,0,7,6,0,7] -; AVX512F-ONLY-SLOW-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 32(%rax), %ymm6 -; AVX512F-ONLY-SLOW-NEXT: vpermd %zmm6, %zmm3, %zmm3 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm28, %ymm7 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm7, %ymm6, %ymm11 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm6 = ymm6[0,1,1,3,4,5,5,7] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm6 = ymm6[0,2,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm6, %ymm6 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm6, %zmm11, %zmm6 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} xmm7 = [0,1,2,3,4,5,4,5,6,7,10,11,8,9,10,11] -; AVX512F-ONLY-SLOW-NEXT: vpshufb %xmm7, %xmm2, %xmm11 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %xmm7, %xmm1, %xmm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rdi), %xmm13 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rsi), %xmm14 -; AVX512F-ONLY-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm13[0],xmm14[0],xmm13[1],xmm14[1],xmm13[2],xmm14[2],xmm13[3],xmm14[3] -; AVX512F-ONLY-SLOW-NEXT: vpshufb %xmm7, %xmm2, %xmm2 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm2, %ymm20 -; AVX512F-ONLY-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm15 = xmm14[4],xmm13[4],xmm14[5],xmm13[5],xmm14[6],xmm13[6],xmm14[7],xmm13[7] -; AVX512F-ONLY-SLOW-NEXT: vprold $16, %xmm14, %xmm14 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} xmm13 = xmm13[1,1,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} xmm2 = xmm13[0,1],xmm14[2],xmm13[3,4],xmm14[5],xmm13[6,7] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm2, %ymm16 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa %ymm4, %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} ymm14 = ymm4[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm14 = ymm14[0,0,0,0,4,4,4,4] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm29, %ymm12 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm9 = ymm29[0,1,1,3,4,5,5,7] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm14 = ymm9[0,1],ymm14[2],ymm9[3,4],ymm14[5],ymm9[6,7,8,9],ymm14[10],ymm9[11,12],ymm14[13],ymm9[14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %xmm31, %xmm4 -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} xmm9 = xmm4[0,2,3,3,4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm9 = ymm9[0,0,2,1] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} xmm15 = xmm15[2,1,2,3,4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} xmm15 = xmm15[0,1,2,3,4,5,5,4] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm15 = ymm15[0,0,1,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm11 = ymm11[0,0,1,1] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm28 = ymm30[2,2,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm29 = ymm23[0,2,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm10 = ymm10[0,2,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm19[2,1,3,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm30 = ymm18[0,2,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,1,3,2,4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm31 = ymm5[2,1,3,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,0,1,1] -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm2 = ymm2[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,22,23,26,27,u,u,24,25,26,27,u,u,26,27,26,27] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm4 = ymm12[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm2 = ymm2[0,1],ymm4[2],ymm2[3,4],ymm4[5],ymm2[6,7,8,9],ymm4[10],ymm2[11,12],ymm4[13],ymm2[14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} ymm4 = ymm8[1,2,3,3,4,5,6,7,9,10,11,11,12,13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm4 = ymm4[0,0,2,1,4,4,6,5] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm5 = ymm17[1,1,1,1,5,5,5,5] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm4 = ymm4[0,1],ymm5[2],ymm4[3,4],ymm5[5],ymm4[6,7,8,9],ymm5[10],ymm4[11,12],ymm5[13],ymm4[14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm5 = ymm17[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm12 = ymm8[0,1,2,3,5,4,6,7,8,9,10,11,13,12,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm12[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm5 = ymm5[0],ymm12[1],ymm5[2,3],ymm12[4],ymm5[5,6,7,8],ymm12[9],ymm5[10,11],ymm12[12],ymm5[13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm29, %zmm28, %zmm12 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm7, %zmm10, %zmm7 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm10 = [65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535] -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $184, %zmm12, %zmm10, %zmm7 -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,1,1,3] -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm0, %zmm30, %zmm0 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm1, %zmm31, %zmm1 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $226, %zmm0, %zmm10, %zmm1 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm9, %zmm0 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm15, %zmm9 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm10 = [65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535] -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $226, %zmm0, %zmm10, %zmm9 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm0 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm11[0,1,2,3],zmm0[4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpermq $182, {{[-0-9]+}}(%r{{[sb]}}p), %ymm11 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # ymm11 = mem[2,1,3,2] -; AVX512F-ONLY-SLOW-NEXT: vpermq $234, {{[-0-9]+}}(%r{{[sb]}}p), %ymm12 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # ymm12 = mem[2,2,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpshufd $254, {{[-0-9]+}}(%r{{[sb]}}p), %ymm15 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # ymm15 = mem[2,3,3,3,6,7,7,7] -; AVX512F-ONLY-SLOW-NEXT: vpermq $96, {{[-0-9]+}}(%r{{[sb]}}p), %ymm17 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # ymm17 = mem[0,0,2,1] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw $230, {{[-0-9]+}}(%r{{[sb]}}p), %xmm8 # 16-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # xmm8 = mem[2,1,2,3,4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} xmm8 = xmm8[0,1,2,3,4,5,5,4] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm8 = ymm8[0,0,1,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm18 = ymm26[0,0,1,1] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %xmm25, %xmm13 -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} xmm13 = xmm13[0,2,3,3,4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm13 = ymm13[0,0,2,1] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm19 = ymm24[2,2,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm28 = ymm22[2,1,3,2] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm29 = ymm21[2,2,3,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm30 = ymm20[0,0,1,1] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm31 = ymm16[0,0,2,1] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm14 = ymm14[2,1,3,2] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm2 = ymm2[2,2,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm4 = ymm4[2,2,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm5 = ymm5[0,2,2,3] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $236, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm16, %zmm0 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm0 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm12, %zmm11, %zmm9 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm7, %zmm9 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm3 -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm15[2,1,3,2] -; AVX512F-ONLY-SLOW-NEXT: vpbroadcastd 32(%rax), %ymm9 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm9, %zmm7, %zmm7 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm7 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm7 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm8, %zmm17, %zmm1 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm13, %zmm18, %zmm8 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $226, %zmm1, %zmm10, %zmm8 -; AVX512F-ONLY-SLOW-NEXT: vpbroadcastd 36(%rax), %ymm1 -; AVX512F-ONLY-SLOW-NEXT: vpbroadcastd 40(%rax), %ymm9 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm9, %zmm1, %zmm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm1 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm8, %zmm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm8 # 64-byte Reload -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm19, %zmm8, %zmm8 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm28, %zmm9, %zmm9 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm8, %zmm9 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm29, %zmm0, %zmm8 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm10 # 64-byte Reload -; AVX512F-ONLY-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm8 = zmm10[0,1,2,3],zmm8[4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm8, %zmm6 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm6 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm31, %zmm30, %zmm8 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm8 -; AVX512F-ONLY-SLOW-NEXT: vpbroadcastd (%rax), %ymm9 -; AVX512F-ONLY-SLOW-NEXT: vpbroadcastd 4(%rax), %ymm10 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm10, %zmm9, %zmm9 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm10 # 64-byte Reload -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm10, %zmm9 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm8, %zmm9 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm2, %zmm14, %zmm2 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm5, %zmm4, %zmm4 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm4 -; AVX512F-ONLY-SLOW-NEXT: vbroadcasti64x4 {{.*#+}} zmm2 = [0,5,4,0,0,6,5,0,0,5,4,0,0,6,5,0] -; AVX512F-ONLY-SLOW-NEXT: # zmm2 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpermd (%rax), %zmm2, %zmm2 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm27, %zmm2 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm4, %zmm2 -; AVX512F-ONLY-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %zmm2, 128(%rax) -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %zmm9, (%rax) -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %zmm6, 320(%rax) -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %zmm1, 256(%rax) -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %zmm7, 192(%rax) -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %zmm0, 64(%rax) -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %zmm3, 384(%rax) -; AVX512F-ONLY-SLOW-NEXT: addq $632, %rsp # imm = 0x278 -; AVX512F-ONLY-SLOW-NEXT: vzeroupper -; AVX512F-ONLY-SLOW-NEXT: retq -; -; AVX512F-ONLY-FAST-LABEL: store_i16_stride7_vf32: -; AVX512F-ONLY-FAST: # %bb.0: -; AVX512F-ONLY-FAST-NEXT: subq $248, %rsp -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rcx), %ymm1 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm0 = [128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128,128,128,128,128] -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm0, %ymm1, %ymm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqa %ymm1, %ymm10 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rdx), %ymm4 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm1 = -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm1, %ymm4, %ymm3 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm4, %ymm18 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm4, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpor %ymm2, %ymm3, %ymm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm2, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rsi), %ymm4 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%rsi), %ymm11 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm3 = [128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128,128,128,128,128,128,128,128,128] -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm3, %ymm4, %ymm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqa %ymm4, %ymm9 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm4, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rdi), %ymm6 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm5 = <12,13,14,15,128,128,u,u,u,u,u,u,u,u,u,u,16,17,128,128,u,u,u,u,u,u,u,u,16,17,18,19> -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm5, %ymm6, %ymm4 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm6, %ymm16 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm6, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpor %ymm2, %ymm4, %ymm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm2, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%r9), %ymm13 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm2 = [128,128,128,128,128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128] -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm2, %ymm13, %ymm6 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%r8), %ymm14 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm4 = -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm4, %ymm14, %ymm7 -; AVX512F-ONLY-FAST-NEXT: vporq %ymm6, %ymm7, %ymm25 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm3, %ymm11, %ymm6 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%rdi), %ymm8 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm5, %ymm8, %ymm5 -; AVX512F-ONLY-FAST-NEXT: vpor %ymm6, %ymm5, %ymm3 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%rcx), %ymm3 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm0, %ymm3, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm3, %ymm29 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%rdx), %ymm12 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm1, %ymm12, %ymm1 -; AVX512F-ONLY-FAST-NEXT: vpor %ymm0, %ymm1, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%r9), %ymm15 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm2, %ymm15, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%r8), %ymm6 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm4, %ymm6, %ymm1 -; AVX512F-ONLY-FAST-NEXT: vporq %ymm0, %ymm1, %ymm21 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm0 = -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm0, %ymm11, %ymm1 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm2 = ymm8[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0,1,2],ymm1[3],ymm2[4,5],ymm1[6],ymm2[7,8,9,10],ymm1[11],ymm2[12,13],ymm1[14],ymm2[15] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm11[10,11,8,9,u,u,u,u,u,u,u,u,u,u,u,u,26,27,24,25,u,u,u,u,26,27,24,25,u,u,u,u] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm11, %ymm30 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm4 = ymm8[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm2 = ymm4[0],ymm2[1],ymm4[2,3],ymm2[4],ymm4[5,6,7,8],ymm2[9],ymm4[10,11],ymm2[12],ymm4[13,14,15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm24 = -; AVX512F-ONLY-FAST-NEXT: vpermi2q %zmm1, %zmm2, %zmm24 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm10[14,15,12,13,u,u,u,u,u,u,u,u,u,u,u,u,30,31,28,29,u,u,u,u,30,31,28,29,u,u,u,u] -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm2 = ymm18[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0],ymm1[1],ymm2[2,3],ymm1[4],ymm2[5,6,7,8],ymm1[9],ymm2[10,11],ymm1[12],ymm2[13,14,15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%rcx), %xmm10 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%rdx), %xmm5 -; AVX512F-ONLY-FAST-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm5[0],xmm10[0],xmm5[1],xmm10[1],xmm5[2],xmm10[2],xmm5[3],xmm10[3] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} xmm2 = xmm2[0,1,2,3,0,1,2,3,6,7,4,5,6,7,4,5] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm23 = -; AVX512F-ONLY-FAST-NEXT: vpermi2q %zmm2, %zmm1, %zmm23 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm0, %ymm9, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm1 = ymm16[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3],ymm1[4,5],ymm0[6],ymm1[7,8,9,10],ymm0[11],ymm1[12,13],ymm0[14],ymm1[15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%rdi), %xmm1 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} xmm11 = [0,1,2,3,4,5,4,5,6,7,10,11,8,9,10,11] -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%rsi), %xmm2 -; AVX512F-ONLY-FAST-NEXT: vpunpcklwd {{.*#+}} xmm4 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3] -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm11, %xmm4, %xmm4 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm20 = [2,1,3,3,8,8,9,9] -; AVX512F-ONLY-FAST-NEXT: vpermi2q %zmm4, %zmm0, %zmm20 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm13[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,26,27,28,29,26,27,28,29,26,27,28,29,30,31,30,31] -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm4 = ymm14[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm4 = ymm0[0,1],ymm4[2],ymm0[3,4],ymm4[5],ymm0[6,7,8,9],ymm4[10],ymm0[11,12],ymm4[13],ymm0[14,15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm22 = [2,2,2,3,8,8,8,9] -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%r9), %xmm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%r8), %xmm3 -; AVX512F-ONLY-FAST-NEXT: vmovdqa %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3] -; AVX512F-ONLY-FAST-NEXT: vmovdqa %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} xmm0 = [0,1,2,3,6,7,4,5,6,7,4,5,12,13,14,15] -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm0, %xmm3, %xmm7 -; AVX512F-ONLY-FAST-NEXT: vpermi2q %zmm7, %zmm4, %zmm22 -; AVX512F-ONLY-FAST-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7] -; AVX512F-ONLY-FAST-NEXT: vprold $16, %xmm2, %xmm2 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,2,3] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2],xmm1[3,4],xmm2[5],xmm1[6,7] -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} xmm7 = [4,5,2,3,4,5,6,7,8,9,10,11,10,11,8,9] -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm7, %xmm4, %xmm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm26 = -; AVX512F-ONLY-FAST-NEXT: vpermi2q %zmm2, %zmm1, %zmm26 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%r9), %xmm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%r8), %xmm9 -; AVX512F-ONLY-FAST-NEXT: vpunpcklwd {{.*#+}} xmm4 = xmm9[0],xmm2[0],xmm9[1],xmm2[1],xmm9[2],xmm2[2],xmm9[3],xmm2[3] -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm0, %xmm4, %xmm0 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} xmm4 = xmm4[0,1,2,3,8,9,10,11,14,15,12,13,14,15,12,13] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm27 = [0,0,0,1,8,9,9,11] -; AVX512F-ONLY-FAST-NEXT: vpermi2q %zmm4, %zmm0, %zmm27 -; AVX512F-ONLY-FAST-NEXT: vprold $16, %ymm13, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm4 = ymm14[1,2,2,3,5,6,6,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm4[0,1],ymm0[2],ymm4[3,4],ymm0[5],ymm4[6,7,8,9],ymm0[10],ymm4[11,12],ymm0[13],ymm4[14,15] -; AVX512F-ONLY-FAST-NEXT: vpbroadcastd {{.*#+}} ymm3 = [18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21] -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm3, %ymm13, %ymm4 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm13 = ymm14[0,0,2,1,4,4,6,5] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm4 = ymm4[0,1,2],ymm13[3],ymm4[4,5],ymm13[6],ymm4[7,8,9,10],ymm13[11],ymm4[12,13],ymm13[14],ymm4[15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm28 = [2,2,3,3,10,9,11,10] -; AVX512F-ONLY-FAST-NEXT: vpermi2q %zmm0, %zmm4, %zmm28 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rdi), %xmm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rsi), %xmm14 -; AVX512F-ONLY-FAST-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm14[4],xmm0[4],xmm14[5],xmm0[5],xmm14[6],xmm0[6],xmm14[7],xmm0[7] -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm7, %xmm4, %xmm1 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm1, %ymm19 -; AVX512F-ONLY-FAST-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm9[4],xmm2[4],xmm9[5],xmm2[5],xmm9[6],xmm2[6],xmm9[7],xmm2[7] -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm25, %zmm0, %zmm4 -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm11, %xmm2, %xmm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm25 = <0,0,1,1,12,13,u,15> -; AVX512F-ONLY-FAST-NEXT: vpermi2q %zmm4, %zmm2, %zmm25 -; AVX512F-ONLY-FAST-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512F-ONLY-FAST-NEXT: vpbroadcastd 8(%rax), %ymm2 -; AVX512F-ONLY-FAST-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rax), %ymm9 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm1 = [12,13,128,128,128,128,128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128] -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm1, %ymm9, %ymm4 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm4, %zmm2, %zmm31 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm30, %ymm2 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm2[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,20,21,18,19,20,21,24,25,26,27,22,23,22,23] -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm4 = ymm8[1,1,1,1,5,5,5,5] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm2 = ymm2[0,1],ymm4[2],ymm2[3,4],ymm4[5],ymm2[6,7,8,9],ymm4[10],ymm2[11,12],ymm4[13],ymm2[14,15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm2, %ymm18 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm29, %ymm7 -; AVX512F-ONLY-FAST-NEXT: vpunpcklwd {{.*#+}} ymm2 = ymm7[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11] -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm4 = ymm12[0,1,1,3,4,5,5,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm2 = ymm4[0,1],ymm2[2],ymm4[3,4],ymm2[5],ymm4[6,7,8,9],ymm2[10],ymm4[11,12],ymm2[13],ymm4[14,15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm2, %ymm17 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm3, %ymm15, %ymm2 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm6[0,0,2,1,4,4,6,5] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm2 = ymm2[0,1,2],ymm3[3],ymm2[4,5],ymm3[6],ymm2[7,8,9,10],ymm3[11],ymm2[12,13],ymm3[14],ymm2[15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm29 = <0,1,u,3,10,10,11,11> -; AVX512F-ONLY-FAST-NEXT: vpermi2q %zmm2, %zmm21, %zmm29 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%rax), %ymm8 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm1, %ymm8, %ymm1 -; AVX512F-ONLY-FAST-NEXT: vbroadcasti64x4 {{.*#+}} zmm21 = [0,13,4,0,0,14,5,0,0,13,4,0,0,14,5,0] -; AVX512F-ONLY-FAST-NEXT: # zmm21 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-FAST-NEXT: vpermd %ymm8, %ymm21, %ymm2 -; AVX512F-ONLY-FAST-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm16 -; AVX512F-ONLY-FAST-NEXT: vmovdqa %ymm7, %ymm4 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm7[14,15,12,13,u,u,u,u,u,u,u,u,u,u,u,u,30,31,28,29,u,u,u,u,30,31,28,29,u,u,u,u] -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm12[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm3[0],ymm2[1],ymm3[2,3],ymm2[4],ymm3[5,6,7,8],ymm2[9],ymm3[10,11],ymm2[12],ymm3[13,14,15] -; AVX512F-ONLY-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm7 = [22,23,26,27,0,0,24,25,26,27,0,0,26,27,26,27,22,23,26,27,0,0,24,25,26,27,0,0,26,27,26,27] -; AVX512F-ONLY-FAST-NEXT: # ymm7 = mem[0,1,0,1] -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm7, %ymm4, %ymm13 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm12 = ymm12[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm12 = ymm13[0,1],ymm12[2],ymm13[3,4],ymm12[5],ymm13[6,7,8,9],ymm12[10],ymm13[11,12],ymm12[13],ymm13[14,15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm30 = [2,2,2,3,8,10,10,11] -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm3, %zmm30, %zmm12 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm3 = ymm15[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,26,27,28,29,26,27,28,29,26,27,28,29,30,31,30,31] -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm13 = ymm6[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm3[0,1],ymm13[2],ymm3[3,4],ymm13[5],ymm3[6,7,8,9],ymm13[10],ymm3[11,12],ymm13[13],ymm3[14,15] -; AVX512F-ONLY-FAST-NEXT: vprold $16, %ymm15, %ymm13 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm6 = ymm6[1,2,2,3,5,6,6,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm6 = ymm6[0,1],ymm13[2],ymm6[3,4],ymm13[5],ymm6[6,7,8,9],ymm13[10],ymm6[11,12],ymm13[13],ymm6[14,15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm13 = [2,1,3,2,10,10,10,11] -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm3, %zmm13, %zmm6 -; AVX512F-ONLY-FAST-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm5[4],xmm10[4],xmm5[5],xmm10[5],xmm5[6],xmm10[6],xmm5[7],xmm10[7] -; AVX512F-ONLY-FAST-NEXT: vpbroadcastq {{.*#+}} xmm15 = [6,7,4,5,0,0,8,9,6,7,4,5,0,0,8,9] -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm15, %xmm10, %xmm10 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} xmm5 = xmm5[1,1,2,2] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} xmm5 = xmm5[0],xmm10[1],xmm5[2,3],xmm10[4],xmm5[5,6],xmm10[7] -; AVX512F-ONLY-FAST-NEXT: vpshuflw {{.*#+}} xmm3 = xmm3[0,2,3,3,4,5,6,7] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm2 = [0,0,1,1,8,8,10,9] -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm3, %zmm2, %zmm5 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpunpckhwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1, %xmm3 # 16-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: # xmm3 = xmm1[4],mem[4],xmm1[5],mem[5],xmm1[6],mem[6],xmm1[7],mem[7] -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} xmm10 = xmm1[0,1,2,3,8,9,10,11,14,15,12,13,14,15,12,13] -; AVX512F-ONLY-FAST-NEXT: vmovdqa %xmm11, %xmm1 -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm11, %xmm3, %xmm3 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm4 = [0,1,1,3,8,8,9,9] -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm3, %zmm4, %zmm10 -; AVX512F-ONLY-FAST-NEXT: vprold $16, %xmm14, %xmm3 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} xmm11 = xmm0[1,1,2,3] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} xmm3 = xmm11[0,1],xmm3[2],xmm11[3,4],xmm3[5],xmm11[6,7] -; AVX512F-ONLY-FAST-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm14[0],xmm0[1],xmm14[1],xmm0[2],xmm14[2],xmm0[3],xmm14[3] -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm1, %xmm0, %xmm11 -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm3, %zmm2, %zmm11 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rcx), %xmm0 -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm15, %xmm0, %xmm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rdx), %xmm3 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} xmm14 = xmm3[1,1,2,2] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} xmm2 = xmm14[0],xmm2[1],xmm14[2,3],xmm2[4],xmm14[5,6],xmm2[7] -; AVX512F-ONLY-FAST-NEXT: vpunpckhwd {{.*#+}} xmm14 = xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7] -; AVX512F-ONLY-FAST-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,0,1,2,3,6,7,4,5,6,7,4,5] -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm2, %zmm4, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm2 = [65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535] -; AVX512F-ONLY-FAST-NEXT: vpternlogq $226, %zmm24, %zmm2, %zmm12 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm12, %zmm6 -; AVX512F-ONLY-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm12 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm7, %ymm12, %ymm3 -; AVX512F-ONLY-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm4 = ymm1[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm3[0,1],ymm4[2],ymm3[3,4],ymm4[5],ymm3[6,7,8,9],ymm4[10],ymm3[11,12],ymm4[13],ymm3[14,15] -; AVX512F-ONLY-FAST-NEXT: vpunpcklwd {{.*#+}} ymm4 = ymm12[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11] -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm7 = ymm1[0,1,1,3,4,5,5,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm4 = ymm7[0,1],ymm4[2],ymm7[3,4],ymm4[5],ymm7[6,7,8,9],ymm4[10],ymm7[11,12],ymm4[13],ymm7[14,15] -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm3, %zmm13, %zmm4 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 (%rax), %zmm3 -; AVX512F-ONLY-FAST-NEXT: vbroadcasti64x4 {{.*#+}} zmm7 = [30,5,0,0,31,6,0,31,30,5,0,0,31,6,0,31] -; AVX512F-ONLY-FAST-NEXT: # zmm7 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-FAST-NEXT: vpermi2d %zmm3, %zmm8, %zmm7 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm6, %zmm7 -; AVX512F-ONLY-FAST-NEXT: vpbroadcastd 36(%rax), %ymm6 -; AVX512F-ONLY-FAST-NEXT: vpbroadcastd 40(%rax), %ymm8 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm8, %zmm6, %zmm6 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm10, %zmm6 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm8 = [65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535] -; AVX512F-ONLY-FAST-NEXT: vpternlogq $226, %zmm26, %zmm8, %zmm5 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm5, %zmm6 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm11, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vpbroadcastd (%rax), %ymm5 -; AVX512F-ONLY-FAST-NEXT: vpbroadcastd 4(%rax), %ymm10 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm10, %zmm5, %zmm5 -; AVX512F-ONLY-FAST-NEXT: vpshuflw {{.*#+}} xmm10 = xmm14[0,2,3,3,4,5,6,7] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm10 = ymm10[0,0,2,1] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm11 = ymm19[0,0,1,3] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm12 = ymm18[2,2,2,3] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm13 = ymm17[2,1,3,2] -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm27, %zmm5 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm5 -; AVX512F-ONLY-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm15 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm15[10,11,8,9,u,u,u,u,u,u,u,u,u,u,u,u,26,27,24,25,u,u,u,u,26,27,24,25,u,u,u,u] -; AVX512F-ONLY-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm14 = ymm1[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm14[0],ymm0[1],ymm14[2,3],ymm0[4],ymm14[5,6,7,8],ymm0[9],ymm14[10,11],ymm0[12],ymm14[13,14,15] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm14 = ymm15[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,20,21,18,19,20,21,24,25,26,27,22,23,22,23] -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm15 = ymm1[1,1,1,1,5,5,5,5] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm14 = ymm14[0,1],ymm15[2],ymm14[3,4],ymm15[5],ymm14[6,7,8,9],ymm15[10],ymm14[11,12],ymm15[13],ymm14[14,15] -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm0, %zmm30, %zmm14 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm4, %zmm14 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm0 = <6,u,u,u,7,u,u,7> -; AVX512F-ONLY-FAST-NEXT: vpermd %ymm9, %ymm0, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm9, %zmm3, %zmm3 -; AVX512F-ONLY-FAST-NEXT: vpermd %zmm3, %zmm21, %zmm3 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm28, %zmm3 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm14, %zmm3 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm10, %zmm4 # 32-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm11, %zmm9 # 32-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: vpternlogq $226, %zmm4, %zmm8, %zmm9 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $226, %zmm23, %zmm2, %zmm20 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm25, %zmm31 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm31 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm12, %zmm2, %zmm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm13, %zmm4, %zmm4 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm4 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm29, %zmm16 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm4, %zmm16 -; AVX512F-ONLY-FAST-NEXT: vpbroadcastd 32(%rax), %ymm2 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm22, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm20, %zmm0 -; AVX512F-ONLY-FAST-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm3, 128(%rax) -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm5, (%rax) -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm16, 320(%rax) -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm6, 256(%rax) -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm0, 192(%rax) -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm7, 384(%rax) -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm31, 64(%rax) -; AVX512F-ONLY-FAST-NEXT: addq $248, %rsp -; AVX512F-ONLY-FAST-NEXT: vzeroupper -; AVX512F-ONLY-FAST-NEXT: retq -; -; AVX512DQ-SLOW-LABEL: store_i16_stride7_vf32: -; AVX512DQ-SLOW: # %bb.0: -; AVX512DQ-SLOW-NEXT: subq $632, %rsp # imm = 0x278 -; AVX512DQ-SLOW-NEXT: vmovdqa (%rcx), %ymm1 -; AVX512DQ-SLOW-NEXT: vmovdqa {{.*#+}} ymm9 = [128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128,128,128,128,128] -; AVX512DQ-SLOW-NEXT: vpshufb %ymm9, %ymm1, %ymm0 -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm1, %ymm16 -; AVX512DQ-SLOW-NEXT: vmovdqa (%rdx), %ymm2 -; AVX512DQ-SLOW-NEXT: vmovdqa {{.*#+}} ymm13 = -; AVX512DQ-SLOW-NEXT: vpshufb %ymm13, %ymm2, %ymm1 -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm2, %ymm29 -; AVX512DQ-SLOW-NEXT: vpor %ymm0, %ymm1, %ymm0 -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqa (%rsi), %ymm1 -; AVX512DQ-SLOW-NEXT: vmovdqa {{.*#+}} ymm12 = [128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128,128,128,128,128,128,128,128,128] -; AVX512DQ-SLOW-NEXT: vpshufb %ymm12, %ymm1, %ymm0 -; AVX512DQ-SLOW-NEXT: vmovdqa %ymm1, %ymm15 -; AVX512DQ-SLOW-NEXT: vmovdqa (%rdi), %ymm2 -; AVX512DQ-SLOW-NEXT: vmovdqa {{.*#+}} ymm14 = <12,13,14,15,128,128,u,u,u,u,u,u,u,u,u,u,16,17,128,128,u,u,u,u,u,u,u,u,16,17,18,19> -; AVX512DQ-SLOW-NEXT: vpshufb %ymm14, %ymm2, %ymm1 -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm2, %ymm17 -; AVX512DQ-SLOW-NEXT: vpor %ymm0, %ymm1, %ymm0 -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqa (%r9), %ymm10 -; AVX512DQ-SLOW-NEXT: vmovdqa {{.*#+}} ymm1 = [128,128,128,128,128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128] -; AVX512DQ-SLOW-NEXT: vpshufb %ymm1, %ymm10, %ymm2 -; AVX512DQ-SLOW-NEXT: vmovdqa (%r8), %ymm11 -; AVX512DQ-SLOW-NEXT: vmovdqa {{.*#+}} ymm0 = -; AVX512DQ-SLOW-NEXT: vpshufb %ymm0, %ymm11, %ymm3 -; AVX512DQ-SLOW-NEXT: vpor %ymm2, %ymm3, %ymm2 -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm2, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqa 32(%r9), %xmm3 -; AVX512DQ-SLOW-NEXT: vmovdqa 32(%r8), %xmm6 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm11[3,3,3,3,7,7,7,7] -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} ymm4 = ymm10[0,1,2,3,5,6,7,7,8,9,10,11,13,14,15,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm4 = ymm4[2,2,2,3,6,6,6,7] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm4 = ymm4[0,1],ymm2[2],ymm4[3,4],ymm2[5],ymm4[6,7,8,9],ymm2[10],ymm4[11,12],ymm2[13],ymm4[14,15] -; AVX512DQ-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm6[0],xmm3[0],xmm6[1],xmm3[1],xmm6[2],xmm3[2],xmm6[3],xmm3[3] -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm7 = [4,5,4,5,4,5,6,7,16,17,16,17,16,17,17,19] -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} xmm5 = xmm2[0,1,3,2,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpermi2d %zmm5, %zmm4, %zmm7 -; AVX512DQ-SLOW-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqa (%rcx), %xmm8 -; AVX512DQ-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm6[4],xmm3[4],xmm6[5],xmm3[5],xmm6[6],xmm3[6],xmm6[7],xmm3[7] -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,5,7,6] -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} xmm3 = xmm3[0,1,2,3,4,5,4,5,6,7,10,11,8,9,10,11] -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm4 = <16,18,19,19,19,19,u,u,0,1,0,1,2,3,2,3> -; AVX512DQ-SLOW-NEXT: vpermi2d %zmm2, %zmm3, %zmm4 -; AVX512DQ-SLOW-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqa 32(%rdi), %ymm3 -; AVX512DQ-SLOW-NEXT: vmovdqa 32(%rsi), %ymm6 -; AVX512DQ-SLOW-NEXT: vpshufb %ymm12, %ymm6, %ymm2 -; AVX512DQ-SLOW-NEXT: vpshufb %ymm14, %ymm3, %ymm4 -; AVX512DQ-SLOW-NEXT: vpor %ymm2, %ymm4, %ymm2 -; AVX512DQ-SLOW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqa 32(%rcx), %ymm12 -; AVX512DQ-SLOW-NEXT: vmovdqa 32(%rdx), %ymm7 -; AVX512DQ-SLOW-NEXT: vpshufb %ymm9, %ymm12, %ymm2 -; AVX512DQ-SLOW-NEXT: vpshufb %ymm13, %ymm7, %ymm4 -; AVX512DQ-SLOW-NEXT: vpor %ymm2, %ymm4, %ymm2 -; AVX512DQ-SLOW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqa 32(%r9), %ymm13 -; AVX512DQ-SLOW-NEXT: vmovdqa 32(%r8), %ymm14 -; AVX512DQ-SLOW-NEXT: vpshufb %ymm1, %ymm13, %ymm1 -; AVX512DQ-SLOW-NEXT: vpshufb %ymm0, %ymm14, %ymm0 -; AVX512DQ-SLOW-NEXT: vpor %ymm1, %ymm0, %ymm0 -; AVX512DQ-SLOW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqa (%rdx), %xmm0 -; AVX512DQ-SLOW-NEXT: vpbroadcastq {{.*#+}} xmm2 = [6,7,4,5,0,0,8,9,6,7,4,5,0,0,8,9] -; AVX512DQ-SLOW-NEXT: vpshufb %xmm2, %xmm8, %xmm1 -; AVX512DQ-SLOW-NEXT: vmovdqa64 %xmm2, %xmm20 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,2,2] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0],xmm1[1],xmm2[2,3],xmm1[4],xmm2[5,6],xmm1[7] -; AVX512DQ-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm0[0],xmm8[0],xmm0[1],xmm8[1],xmm0[2],xmm8[2],xmm0[3],xmm8[3] -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} xmm2 = xmm2[0,1,3,2,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm4 = -; AVX512DQ-SLOW-NEXT: vpermi2d %zmm2, %zmm1, %zmm4 -; AVX512DQ-SLOW-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqa (%r9), %xmm1 -; AVX512DQ-SLOW-NEXT: vmovdqa (%r8), %xmm2 -; AVX512DQ-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm4 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3] -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} xmm5 = xmm4[0,1,2,3,4,5,7,6] -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} xmm4 = xmm4[0,1,3,2,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm9 = <0,1,0,1,0,1,1,3,16,18,19,19,19,19,u,u> -; AVX512DQ-SLOW-NEXT: vpermi2d %zmm5, %zmm4, %zmm9 -; AVX512DQ-SLOW-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-SLOW-NEXT: vprold $16, %ymm10, %ymm4 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm5 = ymm11[1,2,2,3,5,6,6,7] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm4 = ymm5[0,1],ymm4[2],ymm5[3,4],ymm4[5],ymm5[6,7,8,9],ymm4[10],ymm5[11,12],ymm4[13],ymm5[14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm5 = ymm11[0,0,2,1,4,4,6,5] -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} ymm9 = ymm10[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm9 = ymm9[0,0,0,0,4,4,4,4] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm5 = ymm9[0,1,2],ymm5[3],ymm9[4,5],ymm5[6],ymm9[7,8,9,10],ymm5[11],ymm9[12,13],ymm5[14],ymm9[15] -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm27 = [2,2,3,3,10,9,11,10] -; AVX512DQ-SLOW-NEXT: vpermi2q %zmm4, %zmm5, %zmm27 -; AVX512DQ-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQ-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm8[4],xmm0[5],xmm8[5],xmm0[6],xmm8[6],xmm0[7],xmm8[7] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %xmm0, %xmm31 -; AVX512DQ-SLOW-NEXT: vmovdqa (%rax), %ymm4 -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm4, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vpbroadcastd 8(%rax), %ymm0 -; AVX512DQ-SLOW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 -; AVX512DQ-SLOW-NEXT: vmovdqa {{.*#+}} ymm5 = [12,13,128,128,128,128,128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128] -; AVX512DQ-SLOW-NEXT: vpshufb %ymm5, %ymm4, %ymm4 -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm5, %ymm28 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm4, %zmm0, %zmm0 -; AVX512DQ-SLOW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7] -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm0 = ymm12[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,22,23,26,27,u,u,24,25,26,27,u,u,26,27,26,27] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm7[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3,4],ymm1[5],ymm0[6,7,8,9],ymm1[10],ymm0[11,12],ymm1[13],ymm0[14,15] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm0, %ymm30 -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm12[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm7[3,3,3,3,7,7,7,7] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2,3],ymm0[4],ymm1[5,6,7,8],ymm0[9],ymm1[10,11],ymm0[12],ymm1[13,14,15] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm0, %ymm23 -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm6[0,1,2,3,5,4,6,7,8,9,10,11,13,12,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm3[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm10 = ymm1[0],ymm0[1],ymm1[2,3],ymm0[4],ymm1[5,6,7,8],ymm0[9],ymm1[10,11],ymm0[12],ymm1[13,14,15] -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm6[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm3[3,3,3,3,7,7,7,7] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3],ymm1[4,5],ymm0[6],ymm1[7,8,9,10],ymm0[11],ymm1[12,13],ymm0[14],ymm1[15] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm0, %ymm19 -; AVX512DQ-SLOW-NEXT: vprold $16, %ymm13, %ymm0 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm14[1,2,2,3,5,6,6,7] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1],ymm0[2],ymm1[3,4],ymm0[5],ymm1[6,7,8,9],ymm0[10],ymm1[11,12],ymm0[13],ymm1[14,15] -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm13[0,1,2,3,5,6,7,7,8,9,10,11,13,14,15,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,2,2,3,6,6,6,7] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm14[3,3,3,3,7,7,7,7] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3,4],ymm1[5],ymm0[6,7,8,9],ymm1[10],ymm0[11,12],ymm1[13],ymm0[14,15] -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm16, %ymm4 -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm4[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm29[3,3,3,3,7,7,7,7] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm5 = ymm1[0],ymm0[1],ymm1[2,3],ymm0[4],ymm1[5,6,7,8],ymm0[9],ymm1[10,11],ymm0[12],ymm1[13,14,15] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm5, %ymm18 -; AVX512DQ-SLOW-NEXT: vmovdqa %ymm15, %ymm8 -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm15[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm17[3,3,3,3,7,7,7,7] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm5 = ymm1[0,1,2],ymm0[3],ymm1[4,5],ymm0[6],ymm1[7,8,9,10],ymm0[11],ymm1[12,13],ymm0[14],ymm1[15] -; AVX512DQ-SLOW-NEXT: vmovdqa 32(%rdi), %xmm0 -; AVX512DQ-SLOW-NEXT: vmovdqa 32(%rsi), %xmm9 -; AVX512DQ-SLOW-NEXT: vprold $16, %xmm9, %xmm1 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} xmm15 = xmm0[1,1,2,3] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} xmm1 = xmm15[0,1],xmm1[2],xmm15[3,4],xmm1[5],xmm15[6,7] -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm0[0],xmm9[0],xmm0[1],xmm9[1],xmm0[2],xmm9[2],xmm0[3],xmm9[3] -; AVX512DQ-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm9[4],xmm0[4],xmm9[5],xmm0[5],xmm9[6],xmm0[6],xmm9[7],xmm0[7] -; AVX512DQ-SLOW-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqa 32(%rcx), %xmm9 -; AVX512DQ-SLOW-NEXT: vmovdqa64 %xmm20, %xmm0 -; AVX512DQ-SLOW-NEXT: vpshufb %xmm0, %xmm9, %xmm0 -; AVX512DQ-SLOW-NEXT: vmovdqa 32(%rdx), %xmm15 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} xmm11 = xmm15[1,1,2,2] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} xmm0 = xmm11[0],xmm0[1],xmm11[2,3],xmm0[4],xmm11[5,6],xmm0[7] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm0, %ymm26 -; AVX512DQ-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm15[0],xmm9[0],xmm15[1],xmm9[1],xmm15[2],xmm9[2],xmm15[3],xmm9[3] -; AVX512DQ-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm9 = xmm15[4],xmm9[4],xmm15[5],xmm9[5],xmm15[6],xmm9[6],xmm15[7],xmm9[7] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %xmm9, %xmm25 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm3 = ymm3[1,1,1,1,5,5,5,5] -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} ymm6 = ymm6[1,2,3,3,4,5,6,7,9,10,11,11,12,13,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm6 = ymm6[0,0,2,1,4,4,6,5] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm3 = ymm6[0,1],ymm3[2],ymm6[3,4],ymm3[5],ymm6[6,7,8,9],ymm3[10],ymm6[11,12],ymm3[13],ymm6[14,15] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm3, %ymm24 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm3 = ymm7[0,1,1,3,4,5,5,7] -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} ymm6 = ymm12[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm6 = ymm6[0,0,0,0,4,4,4,4] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm3 = ymm3[0,1],ymm6[2],ymm3[3,4],ymm6[5],ymm3[6,7,8,9],ymm6[10],ymm3[11,12],ymm6[13],ymm3[14,15] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm3, %ymm22 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm3 = ymm14[0,0,2,1,4,4,6,5] -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} ymm6 = ymm13[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm6 = ymm6[0,0,0,0,4,4,4,4] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm3 = ymm6[0,1,2],ymm3[3],ymm6[4,5],ymm3[6],ymm6[7,8,9,10],ymm3[11],ymm6[12,13],ymm3[14],ymm6[15] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm3, %ymm21 -; AVX512DQ-SLOW-NEXT: vbroadcasti32x8 {{.*#+}} zmm3 = [6,5,0,0,7,6,0,7,6,5,0,0,7,6,0,7] -; AVX512DQ-SLOW-NEXT: # zmm3 = mem[0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vmovdqa 32(%rax), %ymm6 -; AVX512DQ-SLOW-NEXT: vpermd %zmm6, %zmm3, %zmm3 -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm28, %ymm7 -; AVX512DQ-SLOW-NEXT: vpshufb %ymm7, %ymm6, %ymm11 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm6 = ymm6[0,1,1,3,4,5,5,7] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm6 = ymm6[0,2,2,3] -; AVX512DQ-SLOW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm6, %ymm6 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm6, %zmm11, %zmm6 -; AVX512DQ-SLOW-NEXT: vmovdqa {{.*#+}} xmm7 = [0,1,2,3,4,5,4,5,6,7,10,11,8,9,10,11] -; AVX512DQ-SLOW-NEXT: vpshufb %xmm7, %xmm2, %xmm11 -; AVX512DQ-SLOW-NEXT: vpshufb %xmm7, %xmm1, %xmm1 -; AVX512DQ-SLOW-NEXT: vmovdqa (%rdi), %xmm13 -; AVX512DQ-SLOW-NEXT: vmovdqa (%rsi), %xmm14 -; AVX512DQ-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm13[0],xmm14[0],xmm13[1],xmm14[1],xmm13[2],xmm14[2],xmm13[3],xmm14[3] -; AVX512DQ-SLOW-NEXT: vpshufb %xmm7, %xmm2, %xmm2 -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm2, %ymm20 -; AVX512DQ-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm15 = xmm14[4],xmm13[4],xmm14[5],xmm13[5],xmm14[6],xmm13[6],xmm14[7],xmm13[7] -; AVX512DQ-SLOW-NEXT: vprold $16, %xmm14, %xmm14 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} xmm13 = xmm13[1,1,2,3] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} xmm2 = xmm13[0,1],xmm14[2],xmm13[3,4],xmm14[5],xmm13[6,7] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm2, %ymm16 -; AVX512DQ-SLOW-NEXT: vmovdqa %ymm4, %ymm2 -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} ymm14 = ymm4[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm14 = ymm14[0,0,0,0,4,4,4,4] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm29, %ymm12 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm9 = ymm29[0,1,1,3,4,5,5,7] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm14 = ymm9[0,1],ymm14[2],ymm9[3,4],ymm14[5],ymm9[6,7,8,9],ymm14[10],ymm9[11,12],ymm14[13],ymm9[14,15] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %xmm31, %xmm4 -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} xmm9 = xmm4[0,2,3,3,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm9 = ymm9[0,0,2,1] -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} xmm15 = xmm15[2,1,2,3,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} xmm15 = xmm15[0,1,2,3,4,5,5,4] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm15 = ymm15[0,0,1,3] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm11 = ymm11[0,0,1,1] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm28 = ymm30[2,2,2,3] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm29 = ymm23[0,2,2,3] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm10 = ymm10[0,2,2,3] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm19[2,1,3,3] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm30 = ymm18[0,2,2,3] -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,1,3,2,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm31 = ymm5[2,1,3,3] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,0,1,1] -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm2 = ymm2[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,22,23,26,27,u,u,24,25,26,27,u,u,26,27,26,27] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm4 = ymm12[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm2 = ymm2[0,1],ymm4[2],ymm2[3,4],ymm4[5],ymm2[6,7,8,9],ymm4[10],ymm2[11,12],ymm4[13],ymm2[14,15] -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} ymm4 = ymm8[1,2,3,3,4,5,6,7,9,10,11,11,12,13,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm4 = ymm4[0,0,2,1,4,4,6,5] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm5 = ymm17[1,1,1,1,5,5,5,5] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm4 = ymm4[0,1],ymm5[2],ymm4[3,4],ymm5[5],ymm4[6,7,8,9],ymm5[10],ymm4[11,12],ymm5[13],ymm4[14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm5 = ymm17[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} ymm12 = ymm8[0,1,2,3,5,4,6,7,8,9,10,11,13,12,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm12[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm5 = ymm5[0],ymm12[1],ymm5[2,3],ymm12[4],ymm5[5,6,7,8],ymm12[9],ymm5[10,11],ymm12[12],ymm5[13,14,15] -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm29, %zmm28, %zmm12 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm7, %zmm10, %zmm7 -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm10 = [65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535] -; AVX512DQ-SLOW-NEXT: vpternlogq $184, %zmm12, %zmm10, %zmm7 -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,1,1,3] -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm0, %zmm30, %zmm0 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm1, %zmm31, %zmm1 -; AVX512DQ-SLOW-NEXT: vpternlogq $226, %zmm0, %zmm10, %zmm1 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm9, %zmm0 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm15, %zmm9 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm10 = [65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535] -; AVX512DQ-SLOW-NEXT: vpternlogq $226, %zmm0, %zmm10, %zmm9 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm0 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm11[0,1,2,3],zmm0[4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpermq $182, {{[-0-9]+}}(%r{{[sb]}}p), %ymm11 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # ymm11 = mem[2,1,3,2] -; AVX512DQ-SLOW-NEXT: vpermq $234, {{[-0-9]+}}(%r{{[sb]}}p), %ymm12 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # ymm12 = mem[2,2,2,3] -; AVX512DQ-SLOW-NEXT: vpshufd $254, {{[-0-9]+}}(%r{{[sb]}}p), %ymm15 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # ymm15 = mem[2,3,3,3,6,7,7,7] -; AVX512DQ-SLOW-NEXT: vpermq $96, {{[-0-9]+}}(%r{{[sb]}}p), %ymm17 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # ymm17 = mem[0,0,2,1] -; AVX512DQ-SLOW-NEXT: vpshuflw $230, {{[-0-9]+}}(%r{{[sb]}}p), %xmm8 # 16-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # xmm8 = mem[2,1,2,3,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} xmm8 = xmm8[0,1,2,3,4,5,5,4] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm8 = ymm8[0,0,1,3] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm18 = ymm26[0,0,1,1] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %xmm25, %xmm13 -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} xmm13 = xmm13[0,2,3,3,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm13 = ymm13[0,0,2,1] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm19 = ymm24[2,2,2,3] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm28 = ymm22[2,1,3,2] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm29 = ymm21[2,2,3,3] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm30 = ymm20[0,0,1,1] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm31 = ymm16[0,0,2,1] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm14 = ymm14[2,1,3,2] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm2 = ymm2[2,2,2,3] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm4 = ymm4[2,2,2,3] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm5 = ymm5[0,2,2,3] -; AVX512DQ-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload -; AVX512DQ-SLOW-NEXT: vpternlogq $236, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm16, %zmm0 -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm0 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm12, %zmm11, %zmm9 -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm7, %zmm9 -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm3 -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm15[2,1,3,2] -; AVX512DQ-SLOW-NEXT: vpbroadcastd 32(%rax), %ymm9 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm9, %zmm7, %zmm7 -; AVX512DQ-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm7 -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm7 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm8, %zmm17, %zmm1 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm13, %zmm18, %zmm8 -; AVX512DQ-SLOW-NEXT: vpternlogq $226, %zmm1, %zmm10, %zmm8 -; AVX512DQ-SLOW-NEXT: vpbroadcastd 36(%rax), %ymm1 -; AVX512DQ-SLOW-NEXT: vpbroadcastd 40(%rax), %ymm9 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm9, %zmm1, %zmm1 -; AVX512DQ-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm1 -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm8, %zmm1 -; AVX512DQ-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm8 # 64-byte Reload -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm19, %zmm8, %zmm8 -; AVX512DQ-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm28, %zmm9, %zmm9 -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm8, %zmm9 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm29, %zmm0, %zmm8 -; AVX512DQ-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm10 # 64-byte Reload -; AVX512DQ-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm8 = zmm10[0,1,2,3],zmm8[4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm8, %zmm6 -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm6 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm31, %zmm30, %zmm8 -; AVX512DQ-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload -; AVX512DQ-SLOW-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm8 -; AVX512DQ-SLOW-NEXT: vpbroadcastd (%rax), %ymm9 -; AVX512DQ-SLOW-NEXT: vpbroadcastd 4(%rax), %ymm10 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm10, %zmm9, %zmm9 -; AVX512DQ-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm10 # 64-byte Reload -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm10, %zmm9 -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm8, %zmm9 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm2, %zmm14, %zmm2 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm5, %zmm4, %zmm4 -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm4 -; AVX512DQ-SLOW-NEXT: vbroadcasti32x8 {{.*#+}} zmm2 = [0,5,4,0,0,6,5,0,0,5,4,0,0,6,5,0] -; AVX512DQ-SLOW-NEXT: # zmm2 = mem[0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpermd (%rax), %zmm2, %zmm2 -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm27, %zmm2 -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm4, %zmm2 -; AVX512DQ-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm2, 128(%rax) -; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm9, (%rax) -; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm6, 320(%rax) -; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm1, 256(%rax) -; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm7, 192(%rax) -; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm0, 64(%rax) -; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm3, 384(%rax) -; AVX512DQ-SLOW-NEXT: addq $632, %rsp # imm = 0x278 -; AVX512DQ-SLOW-NEXT: vzeroupper -; AVX512DQ-SLOW-NEXT: retq +; AVX512F-SLOW-LABEL: store_i16_stride7_vf32: +; AVX512F-SLOW: # %bb.0: +; AVX512F-SLOW-NEXT: subq $632, %rsp # imm = 0x278 +; AVX512F-SLOW-NEXT: vmovdqa (%rcx), %ymm1 +; AVX512F-SLOW-NEXT: vmovdqa {{.*#+}} ymm9 = [128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128,128,128,128,128] +; AVX512F-SLOW-NEXT: vpshufb %ymm9, %ymm1, %ymm0 +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm1, %ymm16 +; AVX512F-SLOW-NEXT: vmovdqa (%rdx), %ymm2 +; AVX512F-SLOW-NEXT: vmovdqa {{.*#+}} ymm13 = +; AVX512F-SLOW-NEXT: vpshufb %ymm13, %ymm2, %ymm1 +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm2, %ymm29 +; AVX512F-SLOW-NEXT: vpor %ymm0, %ymm1, %ymm0 +; AVX512F-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vmovdqa (%rsi), %ymm1 +; AVX512F-SLOW-NEXT: vmovdqa {{.*#+}} ymm12 = [128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128,128,128,128,128,128,128,128,128] +; AVX512F-SLOW-NEXT: vpshufb %ymm12, %ymm1, %ymm0 +; AVX512F-SLOW-NEXT: vmovdqa %ymm1, %ymm15 +; AVX512F-SLOW-NEXT: vmovdqa (%rdi), %ymm2 +; AVX512F-SLOW-NEXT: vmovdqa {{.*#+}} ymm14 = <12,13,14,15,128,128,u,u,u,u,u,u,u,u,u,u,16,17,128,128,u,u,u,u,u,u,u,u,16,17,18,19> +; AVX512F-SLOW-NEXT: vpshufb %ymm14, %ymm2, %ymm1 +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm2, %ymm17 +; AVX512F-SLOW-NEXT: vpor %ymm0, %ymm1, %ymm0 +; AVX512F-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vmovdqa (%r9), %ymm10 +; AVX512F-SLOW-NEXT: vmovdqa {{.*#+}} ymm1 = [128,128,128,128,128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128] +; AVX512F-SLOW-NEXT: vpshufb %ymm1, %ymm10, %ymm2 +; AVX512F-SLOW-NEXT: vmovdqa (%r8), %ymm11 +; AVX512F-SLOW-NEXT: vmovdqa {{.*#+}} ymm0 = +; AVX512F-SLOW-NEXT: vpshufb %ymm0, %ymm11, %ymm3 +; AVX512F-SLOW-NEXT: vpor %ymm2, %ymm3, %ymm2 +; AVX512F-SLOW-NEXT: vmovdqu %ymm2, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vmovdqa 32(%r9), %xmm3 +; AVX512F-SLOW-NEXT: vmovdqa 32(%r8), %xmm6 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm11[3,3,3,3,7,7,7,7] +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} ymm4 = ymm10[0,1,2,3,5,6,7,7,8,9,10,11,13,14,15,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm4 = ymm4[2,2,2,3,6,6,6,7] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm4 = ymm4[0,1],ymm2[2],ymm4[3,4],ymm2[5],ymm4[6,7,8,9],ymm2[10],ymm4[11,12],ymm2[13],ymm4[14,15] +; AVX512F-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm6[0],xmm3[0],xmm6[1],xmm3[1],xmm6[2],xmm3[2],xmm6[3],xmm3[3] +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm7 = [4,5,4,5,4,5,6,7,16,17,16,17,16,17,17,19] +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} xmm5 = xmm2[0,1,3,2,4,5,6,7] +; AVX512F-SLOW-NEXT: vpermi2d %zmm5, %zmm4, %zmm7 +; AVX512F-SLOW-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-SLOW-NEXT: vmovdqa (%rcx), %xmm8 +; AVX512F-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm6[4],xmm3[4],xmm6[5],xmm3[5],xmm6[6],xmm3[6],xmm6[7],xmm3[7] +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,5,7,6] +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} xmm3 = xmm3[0,1,2,3,4,5,4,5,6,7,10,11,8,9,10,11] +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm4 = <16,18,19,19,19,19,u,u,0,1,0,1,2,3,2,3> +; AVX512F-SLOW-NEXT: vpermi2d %zmm2, %zmm3, %zmm4 +; AVX512F-SLOW-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-SLOW-NEXT: vmovdqa 32(%rdi), %ymm3 +; AVX512F-SLOW-NEXT: vmovdqa 32(%rsi), %ymm6 +; AVX512F-SLOW-NEXT: vpshufb %ymm12, %ymm6, %ymm2 +; AVX512F-SLOW-NEXT: vpshufb %ymm14, %ymm3, %ymm4 +; AVX512F-SLOW-NEXT: vpor %ymm2, %ymm4, %ymm2 +; AVX512F-SLOW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-SLOW-NEXT: vmovdqa 32(%rcx), %ymm12 +; AVX512F-SLOW-NEXT: vmovdqa 32(%rdx), %ymm7 +; AVX512F-SLOW-NEXT: vpshufb %ymm9, %ymm12, %ymm2 +; AVX512F-SLOW-NEXT: vpshufb %ymm13, %ymm7, %ymm4 +; AVX512F-SLOW-NEXT: vpor %ymm2, %ymm4, %ymm2 +; AVX512F-SLOW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-SLOW-NEXT: vmovdqa 32(%r9), %ymm13 +; AVX512F-SLOW-NEXT: vmovdqa 32(%r8), %ymm14 +; AVX512F-SLOW-NEXT: vpshufb %ymm1, %ymm13, %ymm1 +; AVX512F-SLOW-NEXT: vpshufb %ymm0, %ymm14, %ymm0 +; AVX512F-SLOW-NEXT: vpor %ymm1, %ymm0, %ymm0 +; AVX512F-SLOW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-SLOW-NEXT: vmovdqa (%rdx), %xmm0 +; AVX512F-SLOW-NEXT: vpbroadcastq {{.*#+}} xmm2 = [6,7,4,5,0,0,8,9,6,7,4,5,0,0,8,9] +; AVX512F-SLOW-NEXT: vpshufb %xmm2, %xmm8, %xmm1 +; AVX512F-SLOW-NEXT: vmovdqa64 %xmm2, %xmm20 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,2,2] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0],xmm1[1],xmm2[2,3],xmm1[4],xmm2[5,6],xmm1[7] +; AVX512F-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm0[0],xmm8[0],xmm0[1],xmm8[1],xmm0[2],xmm8[2],xmm0[3],xmm8[3] +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} xmm2 = xmm2[0,1,3,2,4,5,6,7] +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm4 = +; AVX512F-SLOW-NEXT: vpermi2d %zmm2, %zmm1, %zmm4 +; AVX512F-SLOW-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-SLOW-NEXT: vmovdqa (%r9), %xmm1 +; AVX512F-SLOW-NEXT: vmovdqa (%r8), %xmm2 +; AVX512F-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm4 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3] +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} xmm5 = xmm4[0,1,2,3,4,5,7,6] +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} xmm4 = xmm4[0,1,3,2,4,5,6,7] +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm9 = <0,1,0,1,0,1,1,3,16,18,19,19,19,19,u,u> +; AVX512F-SLOW-NEXT: vpermi2d %zmm5, %zmm4, %zmm9 +; AVX512F-SLOW-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-SLOW-NEXT: vprold $16, %ymm10, %ymm4 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm5 = ymm11[1,2,2,3,5,6,6,7] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm4 = ymm5[0,1],ymm4[2],ymm5[3,4],ymm4[5],ymm5[6,7,8,9],ymm4[10],ymm5[11,12],ymm4[13],ymm5[14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm5 = ymm11[0,0,2,1,4,4,6,5] +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} ymm9 = ymm10[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm9 = ymm9[0,0,0,0,4,4,4,4] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm5 = ymm9[0,1,2],ymm5[3],ymm9[4,5],ymm5[6],ymm9[7,8,9,10],ymm5[11],ymm9[12,13],ymm5[14],ymm9[15] +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm27 = [2,2,3,3,10,9,11,10] +; AVX512F-SLOW-NEXT: vpermi2q %zmm4, %zmm5, %zmm27 +; AVX512F-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512F-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm8[4],xmm0[5],xmm8[5],xmm0[6],xmm8[6],xmm0[7],xmm8[7] +; AVX512F-SLOW-NEXT: vmovdqa64 %xmm0, %xmm31 +; AVX512F-SLOW-NEXT: vmovdqa (%rax), %ymm4 +; AVX512F-SLOW-NEXT: vmovdqu %ymm4, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vpbroadcastd 8(%rax), %ymm0 +; AVX512F-SLOW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 +; AVX512F-SLOW-NEXT: vmovdqa {{.*#+}} ymm5 = [12,13,128,128,128,128,128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128] +; AVX512F-SLOW-NEXT: vpshufb %ymm5, %ymm4, %ymm4 +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm5, %ymm28 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm4, %zmm0, %zmm0 +; AVX512F-SLOW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7] +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm0 = ymm12[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,22,23,26,27,u,u,24,25,26,27,u,u,26,27,26,27] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm7[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3,4],ymm1[5],ymm0[6,7,8,9],ymm1[10],ymm0[11,12],ymm1[13],ymm0[14,15] +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm0, %ymm30 +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm12[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm7[3,3,3,3,7,7,7,7] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2,3],ymm0[4],ymm1[5,6,7,8],ymm0[9],ymm1[10,11],ymm0[12],ymm1[13,14,15] +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm0, %ymm23 +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm6[0,1,2,3,5,4,6,7,8,9,10,11,13,12,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm3[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm10 = ymm1[0],ymm0[1],ymm1[2,3],ymm0[4],ymm1[5,6,7,8],ymm0[9],ymm1[10,11],ymm0[12],ymm1[13,14,15] +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm6[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm3[3,3,3,3,7,7,7,7] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3],ymm1[4,5],ymm0[6],ymm1[7,8,9,10],ymm0[11],ymm1[12,13],ymm0[14],ymm1[15] +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm0, %ymm19 +; AVX512F-SLOW-NEXT: vprold $16, %ymm13, %ymm0 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm14[1,2,2,3,5,6,6,7] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1],ymm0[2],ymm1[3,4],ymm0[5],ymm1[6,7,8,9],ymm0[10],ymm1[11,12],ymm0[13],ymm1[14,15] +; AVX512F-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm13[0,1,2,3,5,6,7,7,8,9,10,11,13,14,15,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,2,2,3,6,6,6,7] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm14[3,3,3,3,7,7,7,7] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3,4],ymm1[5],ymm0[6,7,8,9],ymm1[10],ymm0[11,12],ymm1[13],ymm0[14,15] +; AVX512F-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm16, %ymm4 +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm4[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm29[3,3,3,3,7,7,7,7] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm5 = ymm1[0],ymm0[1],ymm1[2,3],ymm0[4],ymm1[5,6,7,8],ymm0[9],ymm1[10,11],ymm0[12],ymm1[13,14,15] +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm5, %ymm18 +; AVX512F-SLOW-NEXT: vmovdqa %ymm15, %ymm8 +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm15[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm17[3,3,3,3,7,7,7,7] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm5 = ymm1[0,1,2],ymm0[3],ymm1[4,5],ymm0[6],ymm1[7,8,9,10],ymm0[11],ymm1[12,13],ymm0[14],ymm1[15] +; AVX512F-SLOW-NEXT: vmovdqa 32(%rdi), %xmm0 +; AVX512F-SLOW-NEXT: vmovdqa 32(%rsi), %xmm9 +; AVX512F-SLOW-NEXT: vprold $16, %xmm9, %xmm1 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} xmm15 = xmm0[1,1,2,3] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} xmm1 = xmm15[0,1],xmm1[2],xmm15[3,4],xmm1[5],xmm15[6,7] +; AVX512F-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm0[0],xmm9[0],xmm0[1],xmm9[1],xmm0[2],xmm9[2],xmm0[3],xmm9[3] +; AVX512F-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm9[4],xmm0[4],xmm9[5],xmm0[5],xmm9[6],xmm0[6],xmm9[7],xmm0[7] +; AVX512F-SLOW-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512F-SLOW-NEXT: vmovdqa 32(%rcx), %xmm9 +; AVX512F-SLOW-NEXT: vmovdqa64 %xmm20, %xmm0 +; AVX512F-SLOW-NEXT: vpshufb %xmm0, %xmm9, %xmm0 +; AVX512F-SLOW-NEXT: vmovdqa 32(%rdx), %xmm15 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} xmm11 = xmm15[1,1,2,2] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} xmm0 = xmm11[0],xmm0[1],xmm11[2,3],xmm0[4],xmm11[5,6],xmm0[7] +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm0, %ymm26 +; AVX512F-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm15[0],xmm9[0],xmm15[1],xmm9[1],xmm15[2],xmm9[2],xmm15[3],xmm9[3] +; AVX512F-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm9 = xmm15[4],xmm9[4],xmm15[5],xmm9[5],xmm15[6],xmm9[6],xmm15[7],xmm9[7] +; AVX512F-SLOW-NEXT: vmovdqa64 %xmm9, %xmm25 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm3 = ymm3[1,1,1,1,5,5,5,5] +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} ymm6 = ymm6[1,2,3,3,4,5,6,7,9,10,11,11,12,13,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm6 = ymm6[0,0,2,1,4,4,6,5] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm3 = ymm6[0,1],ymm3[2],ymm6[3,4],ymm3[5],ymm6[6,7,8,9],ymm3[10],ymm6[11,12],ymm3[13],ymm6[14,15] +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm3, %ymm24 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm3 = ymm7[0,1,1,3,4,5,5,7] +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} ymm6 = ymm12[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm6 = ymm6[0,0,0,0,4,4,4,4] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm3 = ymm3[0,1],ymm6[2],ymm3[3,4],ymm6[5],ymm3[6,7,8,9],ymm6[10],ymm3[11,12],ymm6[13],ymm3[14,15] +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm3, %ymm22 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm3 = ymm14[0,0,2,1,4,4,6,5] +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} ymm6 = ymm13[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm6 = ymm6[0,0,0,0,4,4,4,4] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm3 = ymm6[0,1,2],ymm3[3],ymm6[4,5],ymm3[6],ymm6[7,8,9,10],ymm3[11],ymm6[12,13],ymm3[14],ymm6[15] +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm3, %ymm21 +; AVX512F-SLOW-NEXT: vbroadcasti64x4 {{.*#+}} zmm3 = [6,5,0,0,7,6,0,7,6,5,0,0,7,6,0,7] +; AVX512F-SLOW-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3] +; AVX512F-SLOW-NEXT: vmovdqa 32(%rax), %ymm6 +; AVX512F-SLOW-NEXT: vpermd %zmm6, %zmm3, %zmm3 +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm28, %ymm7 +; AVX512F-SLOW-NEXT: vpshufb %ymm7, %ymm6, %ymm11 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm6 = ymm6[0,1,1,3,4,5,5,7] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm6 = ymm6[0,2,2,3] +; AVX512F-SLOW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm6, %ymm6 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm6, %zmm11, %zmm6 +; AVX512F-SLOW-NEXT: vmovdqa {{.*#+}} xmm7 = [0,1,2,3,4,5,4,5,6,7,10,11,8,9,10,11] +; AVX512F-SLOW-NEXT: vpshufb %xmm7, %xmm2, %xmm11 +; AVX512F-SLOW-NEXT: vpshufb %xmm7, %xmm1, %xmm1 +; AVX512F-SLOW-NEXT: vmovdqa (%rdi), %xmm13 +; AVX512F-SLOW-NEXT: vmovdqa (%rsi), %xmm14 +; AVX512F-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm13[0],xmm14[0],xmm13[1],xmm14[1],xmm13[2],xmm14[2],xmm13[3],xmm14[3] +; AVX512F-SLOW-NEXT: vpshufb %xmm7, %xmm2, %xmm2 +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm2, %ymm20 +; AVX512F-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm15 = xmm14[4],xmm13[4],xmm14[5],xmm13[5],xmm14[6],xmm13[6],xmm14[7],xmm13[7] +; AVX512F-SLOW-NEXT: vprold $16, %xmm14, %xmm14 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} xmm13 = xmm13[1,1,2,3] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} xmm2 = xmm13[0,1],xmm14[2],xmm13[3,4],xmm14[5],xmm13[6,7] +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm2, %ymm16 +; AVX512F-SLOW-NEXT: vmovdqa %ymm4, %ymm2 +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} ymm14 = ymm4[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm14 = ymm14[0,0,0,0,4,4,4,4] +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm29, %ymm12 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm9 = ymm29[0,1,1,3,4,5,5,7] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm14 = ymm9[0,1],ymm14[2],ymm9[3,4],ymm14[5],ymm9[6,7,8,9],ymm14[10],ymm9[11,12],ymm14[13],ymm9[14,15] +; AVX512F-SLOW-NEXT: vmovdqa64 %xmm31, %xmm4 +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} xmm9 = xmm4[0,2,3,3,4,5,6,7] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm9 = ymm9[0,0,2,1] +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} xmm15 = xmm15[2,1,2,3,4,5,6,7] +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} xmm15 = xmm15[0,1,2,3,4,5,5,4] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm15 = ymm15[0,0,1,3] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm11 = ymm11[0,0,1,1] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm28 = ymm30[2,2,2,3] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm29 = ymm23[0,2,2,3] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm10 = ymm10[0,2,2,3] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm19[2,1,3,3] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm30 = ymm18[0,2,2,3] +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,1,3,2,4,5,6,7] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm31 = ymm5[2,1,3,3] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,0,1,1] +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm2 = ymm2[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,22,23,26,27,u,u,24,25,26,27,u,u,26,27,26,27] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm4 = ymm12[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm2 = ymm2[0,1],ymm4[2],ymm2[3,4],ymm4[5],ymm2[6,7,8,9],ymm4[10],ymm2[11,12],ymm4[13],ymm2[14,15] +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} ymm4 = ymm8[1,2,3,3,4,5,6,7,9,10,11,11,12,13,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm4 = ymm4[0,0,2,1,4,4,6,5] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm5 = ymm17[1,1,1,1,5,5,5,5] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm4 = ymm4[0,1],ymm5[2],ymm4[3,4],ymm5[5],ymm4[6,7,8,9],ymm5[10],ymm4[11,12],ymm5[13],ymm4[14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm5 = ymm17[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} ymm12 = ymm8[0,1,2,3,5,4,6,7,8,9,10,11,13,12,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm12[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm5 = ymm5[0],ymm12[1],ymm5[2,3],ymm12[4],ymm5[5,6,7,8],ymm12[9],ymm5[10,11],ymm12[12],ymm5[13,14,15] +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm29, %zmm28, %zmm12 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm7, %zmm10, %zmm7 +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm10 = [65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535] +; AVX512F-SLOW-NEXT: vpternlogq $184, %zmm12, %zmm10, %zmm7 +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,1,1,3] +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm0, %zmm30, %zmm0 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm1, %zmm31, %zmm1 +; AVX512F-SLOW-NEXT: vpternlogq $226, %zmm0, %zmm10, %zmm1 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm9, %zmm0 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm15, %zmm9 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm10 = [65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535] +; AVX512F-SLOW-NEXT: vpternlogq $226, %zmm0, %zmm10, %zmm9 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm0 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm11[0,1,2,3],zmm0[4,5,6,7] +; AVX512F-SLOW-NEXT: vpermq $182, {{[-0-9]+}}(%r{{[sb]}}p), %ymm11 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: # ymm11 = mem[2,1,3,2] +; AVX512F-SLOW-NEXT: vpermq $234, {{[-0-9]+}}(%r{{[sb]}}p), %ymm12 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: # ymm12 = mem[2,2,2,3] +; AVX512F-SLOW-NEXT: vpshufd $254, {{[-0-9]+}}(%r{{[sb]}}p), %ymm15 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: # ymm15 = mem[2,3,3,3,6,7,7,7] +; AVX512F-SLOW-NEXT: vpermq $96, {{[-0-9]+}}(%r{{[sb]}}p), %ymm17 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: # ymm17 = mem[0,0,2,1] +; AVX512F-SLOW-NEXT: vpshuflw $230, {{[-0-9]+}}(%r{{[sb]}}p), %xmm8 # 16-byte Folded Reload +; AVX512F-SLOW-NEXT: # xmm8 = mem[2,1,2,3,4,5,6,7] +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} xmm8 = xmm8[0,1,2,3,4,5,5,4] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm8 = ymm8[0,0,1,3] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm18 = ymm26[0,0,1,1] +; AVX512F-SLOW-NEXT: vmovdqa64 %xmm25, %xmm13 +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} xmm13 = xmm13[0,2,3,3,4,5,6,7] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm13 = ymm13[0,0,2,1] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm19 = ymm24[2,2,2,3] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm28 = ymm22[2,1,3,2] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm29 = ymm21[2,2,3,3] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm30 = ymm20[0,0,1,1] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm31 = ymm16[0,0,2,1] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm14 = ymm14[2,1,3,2] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm2 = ymm2[2,2,2,3] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm4 = ymm4[2,2,2,3] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm5 = ymm5[0,2,2,3] +; AVX512F-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload +; AVX512F-SLOW-NEXT: vpternlogq $236, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm16, %zmm0 +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm0 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm12, %zmm11, %zmm9 +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm7, %zmm9 +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm3 +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm15[2,1,3,2] +; AVX512F-SLOW-NEXT: vpbroadcastd 32(%rax), %ymm9 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm9, %zmm7, %zmm7 +; AVX512F-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm7 +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm7 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm8, %zmm17, %zmm1 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm13, %zmm18, %zmm8 +; AVX512F-SLOW-NEXT: vpternlogq $226, %zmm1, %zmm10, %zmm8 +; AVX512F-SLOW-NEXT: vpbroadcastd 36(%rax), %ymm1 +; AVX512F-SLOW-NEXT: vpbroadcastd 40(%rax), %ymm9 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm9, %zmm1, %zmm1 +; AVX512F-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm1 +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm8, %zmm1 +; AVX512F-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm8 # 64-byte Reload +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm19, %zmm8, %zmm8 +; AVX512F-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm28, %zmm9, %zmm9 +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm8, %zmm9 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm29, %zmm0, %zmm8 +; AVX512F-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm10 # 64-byte Reload +; AVX512F-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm8 = zmm10[0,1,2,3],zmm8[4,5,6,7] +; AVX512F-SLOW-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm8, %zmm6 +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm6 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm31, %zmm30, %zmm8 +; AVX512F-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload +; AVX512F-SLOW-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm8 +; AVX512F-SLOW-NEXT: vpbroadcastd (%rax), %ymm9 +; AVX512F-SLOW-NEXT: vpbroadcastd 4(%rax), %ymm10 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm10, %zmm9, %zmm9 +; AVX512F-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm10 # 64-byte Reload +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm10, %zmm9 +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm8, %zmm9 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm2, %zmm14, %zmm2 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm5, %zmm4, %zmm4 +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm4 +; AVX512F-SLOW-NEXT: vbroadcasti64x4 {{.*#+}} zmm2 = [0,5,4,0,0,6,5,0,0,5,4,0,0,6,5,0] +; AVX512F-SLOW-NEXT: # zmm2 = mem[0,1,2,3,0,1,2,3] +; AVX512F-SLOW-NEXT: vpermd (%rax), %zmm2, %zmm2 +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm27, %zmm2 +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm4, %zmm2 +; AVX512F-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512F-SLOW-NEXT: vmovdqa64 %zmm2, 128(%rax) +; AVX512F-SLOW-NEXT: vmovdqa64 %zmm9, (%rax) +; AVX512F-SLOW-NEXT: vmovdqa64 %zmm6, 320(%rax) +; AVX512F-SLOW-NEXT: vmovdqa64 %zmm1, 256(%rax) +; AVX512F-SLOW-NEXT: vmovdqa64 %zmm7, 192(%rax) +; AVX512F-SLOW-NEXT: vmovdqa64 %zmm0, 64(%rax) +; AVX512F-SLOW-NEXT: vmovdqa64 %zmm3, 384(%rax) +; AVX512F-SLOW-NEXT: addq $632, %rsp # imm = 0x278 +; AVX512F-SLOW-NEXT: vzeroupper +; AVX512F-SLOW-NEXT: retq ; -; AVX512DQ-FAST-LABEL: store_i16_stride7_vf32: -; AVX512DQ-FAST: # %bb.0: -; AVX512DQ-FAST-NEXT: subq $248, %rsp -; AVX512DQ-FAST-NEXT: vmovdqa (%rcx), %ymm1 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm0 = [128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128,128,128,128,128] -; AVX512DQ-FAST-NEXT: vpshufb %ymm0, %ymm1, %ymm2 -; AVX512DQ-FAST-NEXT: vmovdqa %ymm1, %ymm10 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa (%rdx), %ymm4 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm1 = -; AVX512DQ-FAST-NEXT: vpshufb %ymm1, %ymm4, %ymm3 -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm4, %ymm18 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm4, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vpor %ymm2, %ymm3, %ymm2 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm2, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa (%rsi), %ymm4 -; AVX512DQ-FAST-NEXT: vmovdqa 32(%rsi), %ymm11 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm3 = [128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128,128,128,128,128,128,128,128,128] -; AVX512DQ-FAST-NEXT: vpshufb %ymm3, %ymm4, %ymm2 -; AVX512DQ-FAST-NEXT: vmovdqa %ymm4, %ymm9 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm4, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa (%rdi), %ymm6 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm5 = <12,13,14,15,128,128,u,u,u,u,u,u,u,u,u,u,16,17,128,128,u,u,u,u,u,u,u,u,16,17,18,19> -; AVX512DQ-FAST-NEXT: vpshufb %ymm5, %ymm6, %ymm4 -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm6, %ymm16 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm6, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vpor %ymm2, %ymm4, %ymm2 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm2, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa (%r9), %ymm13 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm2 = [128,128,128,128,128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128] -; AVX512DQ-FAST-NEXT: vpshufb %ymm2, %ymm13, %ymm6 -; AVX512DQ-FAST-NEXT: vmovdqa (%r8), %ymm14 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm4 = -; AVX512DQ-FAST-NEXT: vpshufb %ymm4, %ymm14, %ymm7 -; AVX512DQ-FAST-NEXT: vporq %ymm6, %ymm7, %ymm25 -; AVX512DQ-FAST-NEXT: vpshufb %ymm3, %ymm11, %ymm6 -; AVX512DQ-FAST-NEXT: vmovdqa 32(%rdi), %ymm8 -; AVX512DQ-FAST-NEXT: vpshufb %ymm5, %ymm8, %ymm5 -; AVX512DQ-FAST-NEXT: vpor %ymm6, %ymm5, %ymm3 -; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa 32(%rcx), %ymm3 -; AVX512DQ-FAST-NEXT: vpshufb %ymm0, %ymm3, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm3, %ymm29 -; AVX512DQ-FAST-NEXT: vmovdqa 32(%rdx), %ymm12 -; AVX512DQ-FAST-NEXT: vpshufb %ymm1, %ymm12, %ymm1 -; AVX512DQ-FAST-NEXT: vpor %ymm0, %ymm1, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa 32(%r9), %ymm15 -; AVX512DQ-FAST-NEXT: vpshufb %ymm2, %ymm15, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqa 32(%r8), %ymm6 -; AVX512DQ-FAST-NEXT: vpshufb %ymm4, %ymm6, %ymm1 -; AVX512DQ-FAST-NEXT: vporq %ymm0, %ymm1, %ymm21 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm0 = -; AVX512DQ-FAST-NEXT: vpshufb %ymm0, %ymm11, %ymm1 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm2 = ymm8[3,3,3,3,7,7,7,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0,1,2],ymm1[3],ymm2[4,5],ymm1[6],ymm2[7,8,9,10],ymm1[11],ymm2[12,13],ymm1[14],ymm2[15] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm11[10,11,8,9,u,u,u,u,u,u,u,u,u,u,u,u,26,27,24,25,u,u,u,u,26,27,24,25,u,u,u,u] -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm11, %ymm30 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm4 = ymm8[2,2,2,2,6,6,6,6] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm2 = ymm4[0],ymm2[1],ymm4[2,3],ymm2[4],ymm4[5,6,7,8],ymm2[9],ymm4[10,11],ymm2[12],ymm4[13,14,15] -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm24 = -; AVX512DQ-FAST-NEXT: vpermi2q %zmm1, %zmm2, %zmm24 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm10[14,15,12,13,u,u,u,u,u,u,u,u,u,u,u,u,30,31,28,29,u,u,u,u,30,31,28,29,u,u,u,u] -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm2 = ymm18[3,3,3,3,7,7,7,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0],ymm1[1],ymm2[2,3],ymm1[4],ymm2[5,6,7,8],ymm1[9],ymm2[10,11],ymm1[12],ymm2[13,14,15] -; AVX512DQ-FAST-NEXT: vmovdqa 32(%rcx), %xmm10 -; AVX512DQ-FAST-NEXT: vmovdqa 32(%rdx), %xmm5 -; AVX512DQ-FAST-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm5[0],xmm10[0],xmm5[1],xmm10[1],xmm5[2],xmm10[2],xmm5[3],xmm10[3] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} xmm2 = xmm2[0,1,2,3,0,1,2,3,6,7,4,5,6,7,4,5] -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm23 = -; AVX512DQ-FAST-NEXT: vpermi2q %zmm2, %zmm1, %zmm23 -; AVX512DQ-FAST-NEXT: vpshufb %ymm0, %ymm9, %ymm0 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm1 = ymm16[3,3,3,3,7,7,7,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3],ymm1[4,5],ymm0[6],ymm1[7,8,9,10],ymm0[11],ymm1[12,13],ymm0[14],ymm1[15] -; AVX512DQ-FAST-NEXT: vmovdqa 32(%rdi), %xmm1 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} xmm11 = [0,1,2,3,4,5,4,5,6,7,10,11,8,9,10,11] -; AVX512DQ-FAST-NEXT: vmovdqa 32(%rsi), %xmm2 -; AVX512DQ-FAST-NEXT: vpunpcklwd {{.*#+}} xmm4 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3] -; AVX512DQ-FAST-NEXT: vpshufb %xmm11, %xmm4, %xmm4 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm20 = [2,1,3,3,8,8,9,9] -; AVX512DQ-FAST-NEXT: vpermi2q %zmm4, %zmm0, %zmm20 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm13[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,26,27,28,29,26,27,28,29,26,27,28,29,30,31,30,31] -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm4 = ymm14[3,3,3,3,7,7,7,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm4 = ymm0[0,1],ymm4[2],ymm0[3,4],ymm4[5],ymm0[6,7,8,9],ymm4[10],ymm0[11,12],ymm4[13],ymm0[14,15] -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm22 = [2,2,2,3,8,8,8,9] -; AVX512DQ-FAST-NEXT: vmovdqa 32(%r9), %xmm0 -; AVX512DQ-FAST-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa 32(%r8), %xmm3 -; AVX512DQ-FAST-NEXT: vmovdqa %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512DQ-FAST-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3] -; AVX512DQ-FAST-NEXT: vmovdqa %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} xmm0 = [0,1,2,3,6,7,4,5,6,7,4,5,12,13,14,15] -; AVX512DQ-FAST-NEXT: vpshufb %xmm0, %xmm3, %xmm7 -; AVX512DQ-FAST-NEXT: vpermi2q %zmm7, %zmm4, %zmm22 -; AVX512DQ-FAST-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7] -; AVX512DQ-FAST-NEXT: vprold $16, %xmm2, %xmm2 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,2,3] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2],xmm1[3,4],xmm2[5],xmm1[6,7] -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} xmm7 = [4,5,2,3,4,5,6,7,8,9,10,11,10,11,8,9] -; AVX512DQ-FAST-NEXT: vpshufb %xmm7, %xmm4, %xmm2 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm26 = -; AVX512DQ-FAST-NEXT: vpermi2q %zmm2, %zmm1, %zmm26 -; AVX512DQ-FAST-NEXT: vmovdqa (%r9), %xmm2 -; AVX512DQ-FAST-NEXT: vmovdqa (%r8), %xmm9 -; AVX512DQ-FAST-NEXT: vpunpcklwd {{.*#+}} xmm4 = xmm9[0],xmm2[0],xmm9[1],xmm2[1],xmm9[2],xmm2[2],xmm9[3],xmm2[3] -; AVX512DQ-FAST-NEXT: vpshufb %xmm0, %xmm4, %xmm0 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} xmm4 = xmm4[0,1,2,3,8,9,10,11,14,15,12,13,14,15,12,13] -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm27 = [0,0,0,1,8,9,9,11] -; AVX512DQ-FAST-NEXT: vpermi2q %zmm4, %zmm0, %zmm27 -; AVX512DQ-FAST-NEXT: vprold $16, %ymm13, %ymm0 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm4 = ymm14[1,2,2,3,5,6,6,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm4[0,1],ymm0[2],ymm4[3,4],ymm0[5],ymm4[6,7,8,9],ymm0[10],ymm4[11,12],ymm0[13],ymm4[14,15] -; AVX512DQ-FAST-NEXT: vpbroadcastd {{.*#+}} ymm3 = [18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21] -; AVX512DQ-FAST-NEXT: vpshufb %ymm3, %ymm13, %ymm4 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm13 = ymm14[0,0,2,1,4,4,6,5] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm4 = ymm4[0,1,2],ymm13[3],ymm4[4,5],ymm13[6],ymm4[7,8,9,10],ymm13[11],ymm4[12,13],ymm13[14],ymm4[15] -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm28 = [2,2,3,3,10,9,11,10] -; AVX512DQ-FAST-NEXT: vpermi2q %zmm0, %zmm4, %zmm28 -; AVX512DQ-FAST-NEXT: vmovdqa (%rdi), %xmm0 -; AVX512DQ-FAST-NEXT: vmovdqa (%rsi), %xmm14 -; AVX512DQ-FAST-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm14[4],xmm0[4],xmm14[5],xmm0[5],xmm14[6],xmm0[6],xmm14[7],xmm0[7] -; AVX512DQ-FAST-NEXT: vpshufb %xmm7, %xmm4, %xmm1 -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm1, %ymm19 -; AVX512DQ-FAST-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm9[4],xmm2[4],xmm9[5],xmm2[5],xmm9[6],xmm2[6],xmm9[7],xmm2[7] -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm25, %zmm0, %zmm4 -; AVX512DQ-FAST-NEXT: vpshufb %xmm11, %xmm2, %xmm2 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm25 = <0,0,1,1,12,13,u,15> -; AVX512DQ-FAST-NEXT: vpermi2q %zmm4, %zmm2, %zmm25 -; AVX512DQ-FAST-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQ-FAST-NEXT: vpbroadcastd 8(%rax), %ymm2 -; AVX512DQ-FAST-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2 -; AVX512DQ-FAST-NEXT: vmovdqa (%rax), %ymm9 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm1 = [12,13,128,128,128,128,128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128] -; AVX512DQ-FAST-NEXT: vpshufb %ymm1, %ymm9, %ymm4 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm4, %zmm2, %zmm31 -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm30, %ymm2 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm2[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,20,21,18,19,20,21,24,25,26,27,22,23,22,23] -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm4 = ymm8[1,1,1,1,5,5,5,5] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm2 = ymm2[0,1],ymm4[2],ymm2[3,4],ymm4[5],ymm2[6,7,8,9],ymm4[10],ymm2[11,12],ymm4[13],ymm2[14,15] -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm2, %ymm18 -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm29, %ymm7 -; AVX512DQ-FAST-NEXT: vpunpcklwd {{.*#+}} ymm2 = ymm7[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11] -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm4 = ymm12[0,1,1,3,4,5,5,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm2 = ymm4[0,1],ymm2[2],ymm4[3,4],ymm2[5],ymm4[6,7,8,9],ymm2[10],ymm4[11,12],ymm2[13],ymm4[14,15] -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm2, %ymm17 -; AVX512DQ-FAST-NEXT: vpshufb %ymm3, %ymm15, %ymm2 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm6[0,0,2,1,4,4,6,5] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm2 = ymm2[0,1,2],ymm3[3],ymm2[4,5],ymm3[6],ymm2[7,8,9,10],ymm3[11],ymm2[12,13],ymm3[14],ymm2[15] -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm29 = <0,1,u,3,10,10,11,11> -; AVX512DQ-FAST-NEXT: vpermi2q %zmm2, %zmm21, %zmm29 -; AVX512DQ-FAST-NEXT: vmovdqa 32(%rax), %ymm8 -; AVX512DQ-FAST-NEXT: vpshufb %ymm1, %ymm8, %ymm1 -; AVX512DQ-FAST-NEXT: vbroadcasti32x8 {{.*#+}} zmm21 = [0,13,4,0,0,14,5,0,0,13,4,0,0,14,5,0] -; AVX512DQ-FAST-NEXT: # zmm21 = mem[0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7] -; AVX512DQ-FAST-NEXT: vpermd %ymm8, %ymm21, %ymm2 -; AVX512DQ-FAST-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm16 -; AVX512DQ-FAST-NEXT: vmovdqa %ymm7, %ymm4 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm7[14,15,12,13,u,u,u,u,u,u,u,u,u,u,u,u,30,31,28,29,u,u,u,u,30,31,28,29,u,u,u,u] -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm12[3,3,3,3,7,7,7,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm3[0],ymm2[1],ymm3[2,3],ymm2[4],ymm3[5,6,7,8],ymm2[9],ymm3[10,11],ymm2[12],ymm3[13,14,15] -; AVX512DQ-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm7 = [22,23,26,27,0,0,24,25,26,27,0,0,26,27,26,27,22,23,26,27,0,0,24,25,26,27,0,0,26,27,26,27] -; AVX512DQ-FAST-NEXT: # ymm7 = mem[0,1,0,1] -; AVX512DQ-FAST-NEXT: vpshufb %ymm7, %ymm4, %ymm13 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm12 = ymm12[2,2,2,2,6,6,6,6] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm12 = ymm13[0,1],ymm12[2],ymm13[3,4],ymm12[5],ymm13[6,7,8,9],ymm12[10],ymm13[11,12],ymm12[13],ymm13[14,15] -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm30 = [2,2,2,3,8,10,10,11] -; AVX512DQ-FAST-NEXT: vpermt2q %zmm3, %zmm30, %zmm12 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm3 = ymm15[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,26,27,28,29,26,27,28,29,26,27,28,29,30,31,30,31] -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm13 = ymm6[3,3,3,3,7,7,7,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm3[0,1],ymm13[2],ymm3[3,4],ymm13[5],ymm3[6,7,8,9],ymm13[10],ymm3[11,12],ymm13[13],ymm3[14,15] -; AVX512DQ-FAST-NEXT: vprold $16, %ymm15, %ymm13 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm6 = ymm6[1,2,2,3,5,6,6,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm6 = ymm6[0,1],ymm13[2],ymm6[3,4],ymm13[5],ymm6[6,7,8,9],ymm13[10],ymm6[11,12],ymm13[13],ymm6[14,15] -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm13 = [2,1,3,2,10,10,10,11] -; AVX512DQ-FAST-NEXT: vpermt2q %zmm3, %zmm13, %zmm6 -; AVX512DQ-FAST-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm5[4],xmm10[4],xmm5[5],xmm10[5],xmm5[6],xmm10[6],xmm5[7],xmm10[7] -; AVX512DQ-FAST-NEXT: vpbroadcastq {{.*#+}} xmm15 = [6,7,4,5,0,0,8,9,6,7,4,5,0,0,8,9] -; AVX512DQ-FAST-NEXT: vpshufb %xmm15, %xmm10, %xmm10 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} xmm5 = xmm5[1,1,2,2] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} xmm5 = xmm5[0],xmm10[1],xmm5[2,3],xmm10[4],xmm5[5,6],xmm10[7] -; AVX512DQ-FAST-NEXT: vpshuflw {{.*#+}} xmm3 = xmm3[0,2,3,3,4,5,6,7] -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm2 = [0,0,1,1,8,8,10,9] -; AVX512DQ-FAST-NEXT: vpermt2q %zmm3, %zmm2, %zmm5 -; AVX512DQ-FAST-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload -; AVX512DQ-FAST-NEXT: vpunpckhwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1, %xmm3 # 16-byte Folded Reload -; AVX512DQ-FAST-NEXT: # xmm3 = xmm1[4],mem[4],xmm1[5],mem[5],xmm1[6],mem[6],xmm1[7],mem[7] -; AVX512DQ-FAST-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} xmm10 = xmm1[0,1,2,3,8,9,10,11,14,15,12,13,14,15,12,13] -; AVX512DQ-FAST-NEXT: vmovdqa %xmm11, %xmm1 -; AVX512DQ-FAST-NEXT: vpshufb %xmm11, %xmm3, %xmm3 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm4 = [0,1,1,3,8,8,9,9] -; AVX512DQ-FAST-NEXT: vpermt2q %zmm3, %zmm4, %zmm10 -; AVX512DQ-FAST-NEXT: vprold $16, %xmm14, %xmm3 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} xmm11 = xmm0[1,1,2,3] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} xmm3 = xmm11[0,1],xmm3[2],xmm11[3,4],xmm3[5],xmm11[6,7] -; AVX512DQ-FAST-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm14[0],xmm0[1],xmm14[1],xmm0[2],xmm14[2],xmm0[3],xmm14[3] -; AVX512DQ-FAST-NEXT: vpshufb %xmm1, %xmm0, %xmm11 -; AVX512DQ-FAST-NEXT: vpermt2q %zmm3, %zmm2, %zmm11 -; AVX512DQ-FAST-NEXT: vmovdqa (%rcx), %xmm0 -; AVX512DQ-FAST-NEXT: vpshufb %xmm15, %xmm0, %xmm2 -; AVX512DQ-FAST-NEXT: vmovdqa (%rdx), %xmm3 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} xmm14 = xmm3[1,1,2,2] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} xmm2 = xmm14[0],xmm2[1],xmm14[2,3],xmm2[4],xmm14[5,6],xmm2[7] -; AVX512DQ-FAST-NEXT: vpunpckhwd {{.*#+}} xmm14 = xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7] -; AVX512DQ-FAST-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,0,1,2,3,6,7,4,5,6,7,4,5] -; AVX512DQ-FAST-NEXT: vpermt2q %zmm2, %zmm4, %zmm0 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm2 = [65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535] -; AVX512DQ-FAST-NEXT: vpternlogq $226, %zmm24, %zmm2, %zmm12 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm12, %zmm6 -; AVX512DQ-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm12 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vpshufb %ymm7, %ymm12, %ymm3 -; AVX512DQ-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm4 = ymm1[2,2,2,2,6,6,6,6] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm3[0,1],ymm4[2],ymm3[3,4],ymm4[5],ymm3[6,7,8,9],ymm4[10],ymm3[11,12],ymm4[13],ymm3[14,15] -; AVX512DQ-FAST-NEXT: vpunpcklwd {{.*#+}} ymm4 = ymm12[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11] -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm7 = ymm1[0,1,1,3,4,5,5,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm4 = ymm7[0,1],ymm4[2],ymm7[3,4],ymm4[5],ymm7[6,7,8,9],ymm4[10],ymm7[11,12],ymm4[13],ymm7[14,15] -; AVX512DQ-FAST-NEXT: vpermt2q %zmm3, %zmm13, %zmm4 -; AVX512DQ-FAST-NEXT: vmovdqa64 (%rax), %zmm3 -; AVX512DQ-FAST-NEXT: vbroadcasti32x8 {{.*#+}} zmm7 = [30,5,0,0,31,6,0,31,30,5,0,0,31,6,0,31] -; AVX512DQ-FAST-NEXT: # zmm7 = mem[0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7] -; AVX512DQ-FAST-NEXT: vpermi2d %zmm3, %zmm8, %zmm7 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm6, %zmm7 -; AVX512DQ-FAST-NEXT: vpbroadcastd 36(%rax), %ymm6 -; AVX512DQ-FAST-NEXT: vpbroadcastd 40(%rax), %ymm8 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm8, %zmm6, %zmm6 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm10, %zmm6 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm8 = [65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535] -; AVX512DQ-FAST-NEXT: vpternlogq $226, %zmm26, %zmm8, %zmm5 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm5, %zmm6 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm11, %zmm0 -; AVX512DQ-FAST-NEXT: vpbroadcastd (%rax), %ymm5 -; AVX512DQ-FAST-NEXT: vpbroadcastd 4(%rax), %ymm10 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm10, %zmm5, %zmm5 -; AVX512DQ-FAST-NEXT: vpshuflw {{.*#+}} xmm10 = xmm14[0,2,3,3,4,5,6,7] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm10 = ymm10[0,0,2,1] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm11 = ymm19[0,0,1,3] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm12 = ymm18[2,2,2,3] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm13 = ymm17[2,1,3,2] -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm27, %zmm5 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm5 -; AVX512DQ-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm15 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm15[10,11,8,9,u,u,u,u,u,u,u,u,u,u,u,u,26,27,24,25,u,u,u,u,26,27,24,25,u,u,u,u] -; AVX512DQ-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm14 = ymm1[2,2,2,2,6,6,6,6] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm14[0],ymm0[1],ymm14[2,3],ymm0[4],ymm14[5,6,7,8],ymm0[9],ymm14[10,11],ymm0[12],ymm14[13,14,15] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm14 = ymm15[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,20,21,18,19,20,21,24,25,26,27,22,23,22,23] -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm15 = ymm1[1,1,1,1,5,5,5,5] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm14 = ymm14[0,1],ymm15[2],ymm14[3,4],ymm15[5],ymm14[6,7,8,9],ymm15[10],ymm14[11,12],ymm15[13],ymm14[14,15] -; AVX512DQ-FAST-NEXT: vpermt2q %zmm0, %zmm30, %zmm14 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm4, %zmm14 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm0 = <6,u,u,u,7,u,u,7> -; AVX512DQ-FAST-NEXT: vpermd %ymm9, %ymm0, %ymm0 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm9, %zmm3, %zmm3 -; AVX512DQ-FAST-NEXT: vpermd %zmm3, %zmm21, %zmm3 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm28, %zmm3 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm14, %zmm3 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm10, %zmm4 # 32-byte Folded Reload -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm11, %zmm9 # 32-byte Folded Reload -; AVX512DQ-FAST-NEXT: vpternlogq $226, %zmm4, %zmm8, %zmm9 -; AVX512DQ-FAST-NEXT: vpternlogq $226, %zmm23, %zmm2, %zmm20 -; AVX512DQ-FAST-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm25, %zmm31 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm31 -; AVX512DQ-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm12, %zmm2, %zmm2 -; AVX512DQ-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm13, %zmm4, %zmm4 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm4 -; AVX512DQ-FAST-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm29, %zmm16 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm4, %zmm16 -; AVX512DQ-FAST-NEXT: vpbroadcastd 32(%rax), %ymm2 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm22, %zmm0 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm20, %zmm0 -; AVX512DQ-FAST-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm3, 128(%rax) -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm5, (%rax) -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm16, 320(%rax) -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm6, 256(%rax) -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm0, 192(%rax) -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm7, 384(%rax) -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm31, 64(%rax) -; AVX512DQ-FAST-NEXT: addq $248, %rsp -; AVX512DQ-FAST-NEXT: vzeroupper -; AVX512DQ-FAST-NEXT: retq +; AVX512F-FAST-LABEL: store_i16_stride7_vf32: +; AVX512F-FAST: # %bb.0: +; AVX512F-FAST-NEXT: subq $248, %rsp +; AVX512F-FAST-NEXT: vmovdqa (%rcx), %ymm1 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm0 = [128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128,128,128,128,128] +; AVX512F-FAST-NEXT: vpshufb %ymm0, %ymm1, %ymm2 +; AVX512F-FAST-NEXT: vmovdqa %ymm1, %ymm10 +; AVX512F-FAST-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vmovdqa (%rdx), %ymm4 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm1 = +; AVX512F-FAST-NEXT: vpshufb %ymm1, %ymm4, %ymm3 +; AVX512F-FAST-NEXT: vmovdqa64 %ymm4, %ymm18 +; AVX512F-FAST-NEXT: vmovdqu %ymm4, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vpor %ymm2, %ymm3, %ymm2 +; AVX512F-FAST-NEXT: vmovdqu %ymm2, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vmovdqa (%rsi), %ymm4 +; AVX512F-FAST-NEXT: vmovdqa 32(%rsi), %ymm11 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm3 = [128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128,128,128,128,128,128,128,128,128] +; AVX512F-FAST-NEXT: vpshufb %ymm3, %ymm4, %ymm2 +; AVX512F-FAST-NEXT: vmovdqa %ymm4, %ymm9 +; AVX512F-FAST-NEXT: vmovdqu %ymm4, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vmovdqa (%rdi), %ymm6 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm5 = <12,13,14,15,128,128,u,u,u,u,u,u,u,u,u,u,16,17,128,128,u,u,u,u,u,u,u,u,16,17,18,19> +; AVX512F-FAST-NEXT: vpshufb %ymm5, %ymm6, %ymm4 +; AVX512F-FAST-NEXT: vmovdqa64 %ymm6, %ymm16 +; AVX512F-FAST-NEXT: vmovdqu %ymm6, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vpor %ymm2, %ymm4, %ymm2 +; AVX512F-FAST-NEXT: vmovdqu %ymm2, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vmovdqa (%r9), %ymm13 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm2 = [128,128,128,128,128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128] +; AVX512F-FAST-NEXT: vpshufb %ymm2, %ymm13, %ymm6 +; AVX512F-FAST-NEXT: vmovdqa (%r8), %ymm14 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm4 = +; AVX512F-FAST-NEXT: vpshufb %ymm4, %ymm14, %ymm7 +; AVX512F-FAST-NEXT: vporq %ymm6, %ymm7, %ymm25 +; AVX512F-FAST-NEXT: vpshufb %ymm3, %ymm11, %ymm6 +; AVX512F-FAST-NEXT: vmovdqa 32(%rdi), %ymm8 +; AVX512F-FAST-NEXT: vpshufb %ymm5, %ymm8, %ymm5 +; AVX512F-FAST-NEXT: vpor %ymm6, %ymm5, %ymm3 +; AVX512F-FAST-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-FAST-NEXT: vmovdqa 32(%rcx), %ymm3 +; AVX512F-FAST-NEXT: vpshufb %ymm0, %ymm3, %ymm0 +; AVX512F-FAST-NEXT: vmovdqa64 %ymm3, %ymm29 +; AVX512F-FAST-NEXT: vmovdqa 32(%rdx), %ymm12 +; AVX512F-FAST-NEXT: vpshufb %ymm1, %ymm12, %ymm1 +; AVX512F-FAST-NEXT: vpor %ymm0, %ymm1, %ymm0 +; AVX512F-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-FAST-NEXT: vmovdqa 32(%r9), %ymm15 +; AVX512F-FAST-NEXT: vpshufb %ymm2, %ymm15, %ymm0 +; AVX512F-FAST-NEXT: vmovdqa 32(%r8), %ymm6 +; AVX512F-FAST-NEXT: vpshufb %ymm4, %ymm6, %ymm1 +; AVX512F-FAST-NEXT: vporq %ymm0, %ymm1, %ymm21 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm0 = +; AVX512F-FAST-NEXT: vpshufb %ymm0, %ymm11, %ymm1 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm2 = ymm8[3,3,3,3,7,7,7,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0,1,2],ymm1[3],ymm2[4,5],ymm1[6],ymm2[7,8,9,10],ymm1[11],ymm2[12,13],ymm1[14],ymm2[15] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm11[10,11,8,9,u,u,u,u,u,u,u,u,u,u,u,u,26,27,24,25,u,u,u,u,26,27,24,25,u,u,u,u] +; AVX512F-FAST-NEXT: vmovdqa64 %ymm11, %ymm30 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm4 = ymm8[2,2,2,2,6,6,6,6] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm2 = ymm4[0],ymm2[1],ymm4[2,3],ymm2[4],ymm4[5,6,7,8],ymm2[9],ymm4[10,11],ymm2[12],ymm4[13,14,15] +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm24 = +; AVX512F-FAST-NEXT: vpermi2q %zmm1, %zmm2, %zmm24 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm10[14,15,12,13,u,u,u,u,u,u,u,u,u,u,u,u,30,31,28,29,u,u,u,u,30,31,28,29,u,u,u,u] +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm2 = ymm18[3,3,3,3,7,7,7,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0],ymm1[1],ymm2[2,3],ymm1[4],ymm2[5,6,7,8],ymm1[9],ymm2[10,11],ymm1[12],ymm2[13,14,15] +; AVX512F-FAST-NEXT: vmovdqa 32(%rcx), %xmm10 +; AVX512F-FAST-NEXT: vmovdqa 32(%rdx), %xmm5 +; AVX512F-FAST-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm5[0],xmm10[0],xmm5[1],xmm10[1],xmm5[2],xmm10[2],xmm5[3],xmm10[3] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} xmm2 = xmm2[0,1,2,3,0,1,2,3,6,7,4,5,6,7,4,5] +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm23 = +; AVX512F-FAST-NEXT: vpermi2q %zmm2, %zmm1, %zmm23 +; AVX512F-FAST-NEXT: vpshufb %ymm0, %ymm9, %ymm0 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm1 = ymm16[3,3,3,3,7,7,7,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3],ymm1[4,5],ymm0[6],ymm1[7,8,9,10],ymm0[11],ymm1[12,13],ymm0[14],ymm1[15] +; AVX512F-FAST-NEXT: vmovdqa 32(%rdi), %xmm1 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} xmm11 = [0,1,2,3,4,5,4,5,6,7,10,11,8,9,10,11] +; AVX512F-FAST-NEXT: vmovdqa 32(%rsi), %xmm2 +; AVX512F-FAST-NEXT: vpunpcklwd {{.*#+}} xmm4 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3] +; AVX512F-FAST-NEXT: vpshufb %xmm11, %xmm4, %xmm4 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm20 = [2,1,3,3,8,8,9,9] +; AVX512F-FAST-NEXT: vpermi2q %zmm4, %zmm0, %zmm20 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm13[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,26,27,28,29,26,27,28,29,26,27,28,29,30,31,30,31] +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm4 = ymm14[3,3,3,3,7,7,7,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm4 = ymm0[0,1],ymm4[2],ymm0[3,4],ymm4[5],ymm0[6,7,8,9],ymm4[10],ymm0[11,12],ymm4[13],ymm0[14,15] +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm22 = [2,2,2,3,8,8,8,9] +; AVX512F-FAST-NEXT: vmovdqa 32(%r9), %xmm0 +; AVX512F-FAST-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512F-FAST-NEXT: vmovdqa 32(%r8), %xmm3 +; AVX512F-FAST-NEXT: vmovdqa %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512F-FAST-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3] +; AVX512F-FAST-NEXT: vmovdqa %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} xmm0 = [0,1,2,3,6,7,4,5,6,7,4,5,12,13,14,15] +; AVX512F-FAST-NEXT: vpshufb %xmm0, %xmm3, %xmm7 +; AVX512F-FAST-NEXT: vpermi2q %zmm7, %zmm4, %zmm22 +; AVX512F-FAST-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7] +; AVX512F-FAST-NEXT: vprold $16, %xmm2, %xmm2 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,2,3] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2],xmm1[3,4],xmm2[5],xmm1[6,7] +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} xmm7 = [4,5,2,3,4,5,6,7,8,9,10,11,10,11,8,9] +; AVX512F-FAST-NEXT: vpshufb %xmm7, %xmm4, %xmm2 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm26 = +; AVX512F-FAST-NEXT: vpermi2q %zmm2, %zmm1, %zmm26 +; AVX512F-FAST-NEXT: vmovdqa (%r9), %xmm2 +; AVX512F-FAST-NEXT: vmovdqa (%r8), %xmm9 +; AVX512F-FAST-NEXT: vpunpcklwd {{.*#+}} xmm4 = xmm9[0],xmm2[0],xmm9[1],xmm2[1],xmm9[2],xmm2[2],xmm9[3],xmm2[3] +; AVX512F-FAST-NEXT: vpshufb %xmm0, %xmm4, %xmm0 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} xmm4 = xmm4[0,1,2,3,8,9,10,11,14,15,12,13,14,15,12,13] +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm27 = [0,0,0,1,8,9,9,11] +; AVX512F-FAST-NEXT: vpermi2q %zmm4, %zmm0, %zmm27 +; AVX512F-FAST-NEXT: vprold $16, %ymm13, %ymm0 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm4 = ymm14[1,2,2,3,5,6,6,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm4[0,1],ymm0[2],ymm4[3,4],ymm0[5],ymm4[6,7,8,9],ymm0[10],ymm4[11,12],ymm0[13],ymm4[14,15] +; AVX512F-FAST-NEXT: vpbroadcastd {{.*#+}} ymm3 = [18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21] +; AVX512F-FAST-NEXT: vpshufb %ymm3, %ymm13, %ymm4 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm13 = ymm14[0,0,2,1,4,4,6,5] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm4 = ymm4[0,1,2],ymm13[3],ymm4[4,5],ymm13[6],ymm4[7,8,9,10],ymm13[11],ymm4[12,13],ymm13[14],ymm4[15] +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm28 = [2,2,3,3,10,9,11,10] +; AVX512F-FAST-NEXT: vpermi2q %zmm0, %zmm4, %zmm28 +; AVX512F-FAST-NEXT: vmovdqa (%rdi), %xmm0 +; AVX512F-FAST-NEXT: vmovdqa (%rsi), %xmm14 +; AVX512F-FAST-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm14[4],xmm0[4],xmm14[5],xmm0[5],xmm14[6],xmm0[6],xmm14[7],xmm0[7] +; AVX512F-FAST-NEXT: vpshufb %xmm7, %xmm4, %xmm1 +; AVX512F-FAST-NEXT: vmovdqa64 %ymm1, %ymm19 +; AVX512F-FAST-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm9[4],xmm2[4],xmm9[5],xmm2[5],xmm9[6],xmm2[6],xmm9[7],xmm2[7] +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm25, %zmm0, %zmm4 +; AVX512F-FAST-NEXT: vpshufb %xmm11, %xmm2, %xmm2 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm25 = <0,0,1,1,12,13,u,15> +; AVX512F-FAST-NEXT: vpermi2q %zmm4, %zmm2, %zmm25 +; AVX512F-FAST-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512F-FAST-NEXT: vpbroadcastd 8(%rax), %ymm2 +; AVX512F-FAST-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2 +; AVX512F-FAST-NEXT: vmovdqa (%rax), %ymm9 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm1 = [12,13,128,128,128,128,128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128] +; AVX512F-FAST-NEXT: vpshufb %ymm1, %ymm9, %ymm4 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm4, %zmm2, %zmm31 +; AVX512F-FAST-NEXT: vmovdqa64 %ymm30, %ymm2 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm2[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,20,21,18,19,20,21,24,25,26,27,22,23,22,23] +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm4 = ymm8[1,1,1,1,5,5,5,5] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm2 = ymm2[0,1],ymm4[2],ymm2[3,4],ymm4[5],ymm2[6,7,8,9],ymm4[10],ymm2[11,12],ymm4[13],ymm2[14,15] +; AVX512F-FAST-NEXT: vmovdqa64 %ymm2, %ymm18 +; AVX512F-FAST-NEXT: vmovdqa64 %ymm29, %ymm7 +; AVX512F-FAST-NEXT: vpunpcklwd {{.*#+}} ymm2 = ymm7[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11] +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm4 = ymm12[0,1,1,3,4,5,5,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm2 = ymm4[0,1],ymm2[2],ymm4[3,4],ymm2[5],ymm4[6,7,8,9],ymm2[10],ymm4[11,12],ymm2[13],ymm4[14,15] +; AVX512F-FAST-NEXT: vmovdqa64 %ymm2, %ymm17 +; AVX512F-FAST-NEXT: vpshufb %ymm3, %ymm15, %ymm2 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm6[0,0,2,1,4,4,6,5] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm2 = ymm2[0,1,2],ymm3[3],ymm2[4,5],ymm3[6],ymm2[7,8,9,10],ymm3[11],ymm2[12,13],ymm3[14],ymm2[15] +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm29 = <0,1,u,3,10,10,11,11> +; AVX512F-FAST-NEXT: vpermi2q %zmm2, %zmm21, %zmm29 +; AVX512F-FAST-NEXT: vmovdqa 32(%rax), %ymm8 +; AVX512F-FAST-NEXT: vpshufb %ymm1, %ymm8, %ymm1 +; AVX512F-FAST-NEXT: vbroadcasti64x4 {{.*#+}} zmm21 = [0,13,4,0,0,14,5,0,0,13,4,0,0,14,5,0] +; AVX512F-FAST-NEXT: # zmm21 = mem[0,1,2,3,0,1,2,3] +; AVX512F-FAST-NEXT: vpermd %ymm8, %ymm21, %ymm2 +; AVX512F-FAST-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm16 +; AVX512F-FAST-NEXT: vmovdqa %ymm7, %ymm4 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm7[14,15,12,13,u,u,u,u,u,u,u,u,u,u,u,u,30,31,28,29,u,u,u,u,30,31,28,29,u,u,u,u] +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm12[3,3,3,3,7,7,7,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm3[0],ymm2[1],ymm3[2,3],ymm2[4],ymm3[5,6,7,8],ymm2[9],ymm3[10,11],ymm2[12],ymm3[13,14,15] +; AVX512F-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm7 = [22,23,26,27,0,0,24,25,26,27,0,0,26,27,26,27,22,23,26,27,0,0,24,25,26,27,0,0,26,27,26,27] +; AVX512F-FAST-NEXT: # ymm7 = mem[0,1,0,1] +; AVX512F-FAST-NEXT: vpshufb %ymm7, %ymm4, %ymm13 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm12 = ymm12[2,2,2,2,6,6,6,6] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm12 = ymm13[0,1],ymm12[2],ymm13[3,4],ymm12[5],ymm13[6,7,8,9],ymm12[10],ymm13[11,12],ymm12[13],ymm13[14,15] +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm30 = [2,2,2,3,8,10,10,11] +; AVX512F-FAST-NEXT: vpermt2q %zmm3, %zmm30, %zmm12 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm3 = ymm15[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,26,27,28,29,26,27,28,29,26,27,28,29,30,31,30,31] +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm13 = ymm6[3,3,3,3,7,7,7,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm3[0,1],ymm13[2],ymm3[3,4],ymm13[5],ymm3[6,7,8,9],ymm13[10],ymm3[11,12],ymm13[13],ymm3[14,15] +; AVX512F-FAST-NEXT: vprold $16, %ymm15, %ymm13 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm6 = ymm6[1,2,2,3,5,6,6,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm6 = ymm6[0,1],ymm13[2],ymm6[3,4],ymm13[5],ymm6[6,7,8,9],ymm13[10],ymm6[11,12],ymm13[13],ymm6[14,15] +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm13 = [2,1,3,2,10,10,10,11] +; AVX512F-FAST-NEXT: vpermt2q %zmm3, %zmm13, %zmm6 +; AVX512F-FAST-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm5[4],xmm10[4],xmm5[5],xmm10[5],xmm5[6],xmm10[6],xmm5[7],xmm10[7] +; AVX512F-FAST-NEXT: vpbroadcastq {{.*#+}} xmm15 = [6,7,4,5,0,0,8,9,6,7,4,5,0,0,8,9] +; AVX512F-FAST-NEXT: vpshufb %xmm15, %xmm10, %xmm10 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} xmm5 = xmm5[1,1,2,2] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} xmm5 = xmm5[0],xmm10[1],xmm5[2,3],xmm10[4],xmm5[5,6],xmm10[7] +; AVX512F-FAST-NEXT: vpshuflw {{.*#+}} xmm3 = xmm3[0,2,3,3,4,5,6,7] +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm2 = [0,0,1,1,8,8,10,9] +; AVX512F-FAST-NEXT: vpermt2q %zmm3, %zmm2, %zmm5 +; AVX512F-FAST-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload +; AVX512F-FAST-NEXT: vpunpckhwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1, %xmm3 # 16-byte Folded Reload +; AVX512F-FAST-NEXT: # xmm3 = xmm1[4],mem[4],xmm1[5],mem[5],xmm1[6],mem[6],xmm1[7],mem[7] +; AVX512F-FAST-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} xmm10 = xmm1[0,1,2,3,8,9,10,11,14,15,12,13,14,15,12,13] +; AVX512F-FAST-NEXT: vmovdqa %xmm11, %xmm1 +; AVX512F-FAST-NEXT: vpshufb %xmm11, %xmm3, %xmm3 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm4 = [0,1,1,3,8,8,9,9] +; AVX512F-FAST-NEXT: vpermt2q %zmm3, %zmm4, %zmm10 +; AVX512F-FAST-NEXT: vprold $16, %xmm14, %xmm3 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} xmm11 = xmm0[1,1,2,3] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} xmm3 = xmm11[0,1],xmm3[2],xmm11[3,4],xmm3[5],xmm11[6,7] +; AVX512F-FAST-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm14[0],xmm0[1],xmm14[1],xmm0[2],xmm14[2],xmm0[3],xmm14[3] +; AVX512F-FAST-NEXT: vpshufb %xmm1, %xmm0, %xmm11 +; AVX512F-FAST-NEXT: vpermt2q %zmm3, %zmm2, %zmm11 +; AVX512F-FAST-NEXT: vmovdqa (%rcx), %xmm0 +; AVX512F-FAST-NEXT: vpshufb %xmm15, %xmm0, %xmm2 +; AVX512F-FAST-NEXT: vmovdqa (%rdx), %xmm3 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} xmm14 = xmm3[1,1,2,2] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} xmm2 = xmm14[0],xmm2[1],xmm14[2,3],xmm2[4],xmm14[5,6],xmm2[7] +; AVX512F-FAST-NEXT: vpunpckhwd {{.*#+}} xmm14 = xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7] +; AVX512F-FAST-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,0,1,2,3,6,7,4,5,6,7,4,5] +; AVX512F-FAST-NEXT: vpermt2q %zmm2, %zmm4, %zmm0 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm2 = [65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535] +; AVX512F-FAST-NEXT: vpternlogq $226, %zmm24, %zmm2, %zmm12 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm12, %zmm6 +; AVX512F-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm12 # 32-byte Reload +; AVX512F-FAST-NEXT: vpshufb %ymm7, %ymm12, %ymm3 +; AVX512F-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm4 = ymm1[2,2,2,2,6,6,6,6] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm3[0,1],ymm4[2],ymm3[3,4],ymm4[5],ymm3[6,7,8,9],ymm4[10],ymm3[11,12],ymm4[13],ymm3[14,15] +; AVX512F-FAST-NEXT: vpunpcklwd {{.*#+}} ymm4 = ymm12[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11] +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm7 = ymm1[0,1,1,3,4,5,5,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm4 = ymm7[0,1],ymm4[2],ymm7[3,4],ymm4[5],ymm7[6,7,8,9],ymm4[10],ymm7[11,12],ymm4[13],ymm7[14,15] +; AVX512F-FAST-NEXT: vpermt2q %zmm3, %zmm13, %zmm4 +; AVX512F-FAST-NEXT: vmovdqa64 (%rax), %zmm3 +; AVX512F-FAST-NEXT: vbroadcasti64x4 {{.*#+}} zmm7 = [30,5,0,0,31,6,0,31,30,5,0,0,31,6,0,31] +; AVX512F-FAST-NEXT: # zmm7 = mem[0,1,2,3,0,1,2,3] +; AVX512F-FAST-NEXT: vpermi2d %zmm3, %zmm8, %zmm7 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm6, %zmm7 +; AVX512F-FAST-NEXT: vpbroadcastd 36(%rax), %ymm6 +; AVX512F-FAST-NEXT: vpbroadcastd 40(%rax), %ymm8 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm8, %zmm6, %zmm6 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm10, %zmm6 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm8 = [65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535] +; AVX512F-FAST-NEXT: vpternlogq $226, %zmm26, %zmm8, %zmm5 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm5, %zmm6 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm11, %zmm0 +; AVX512F-FAST-NEXT: vpbroadcastd (%rax), %ymm5 +; AVX512F-FAST-NEXT: vpbroadcastd 4(%rax), %ymm10 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm10, %zmm5, %zmm5 +; AVX512F-FAST-NEXT: vpshuflw {{.*#+}} xmm10 = xmm14[0,2,3,3,4,5,6,7] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm10 = ymm10[0,0,2,1] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm11 = ymm19[0,0,1,3] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm12 = ymm18[2,2,2,3] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm13 = ymm17[2,1,3,2] +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm27, %zmm5 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm5 +; AVX512F-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm15 # 32-byte Reload +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm15[10,11,8,9,u,u,u,u,u,u,u,u,u,u,u,u,26,27,24,25,u,u,u,u,26,27,24,25,u,u,u,u] +; AVX512F-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm14 = ymm1[2,2,2,2,6,6,6,6] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm14[0],ymm0[1],ymm14[2,3],ymm0[4],ymm14[5,6,7,8],ymm0[9],ymm14[10,11],ymm0[12],ymm14[13,14,15] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm14 = ymm15[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,20,21,18,19,20,21,24,25,26,27,22,23,22,23] +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm15 = ymm1[1,1,1,1,5,5,5,5] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm14 = ymm14[0,1],ymm15[2],ymm14[3,4],ymm15[5],ymm14[6,7,8,9],ymm15[10],ymm14[11,12],ymm15[13],ymm14[14,15] +; AVX512F-FAST-NEXT: vpermt2q %zmm0, %zmm30, %zmm14 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm4, %zmm14 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm0 = <6,u,u,u,7,u,u,7> +; AVX512F-FAST-NEXT: vpermd %ymm9, %ymm0, %ymm0 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm9, %zmm3, %zmm3 +; AVX512F-FAST-NEXT: vpermd %zmm3, %zmm21, %zmm3 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm28, %zmm3 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm14, %zmm3 +; AVX512F-FAST-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm10, %zmm4 # 32-byte Folded Reload +; AVX512F-FAST-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm11, %zmm9 # 32-byte Folded Reload +; AVX512F-FAST-NEXT: vpternlogq $226, %zmm4, %zmm8, %zmm9 +; AVX512F-FAST-NEXT: vpternlogq $226, %zmm23, %zmm2, %zmm20 +; AVX512F-FAST-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm25, %zmm31 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm31 +; AVX512F-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm12, %zmm2, %zmm2 +; AVX512F-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm13, %zmm4, %zmm4 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm4 +; AVX512F-FAST-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm29, %zmm16 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm4, %zmm16 +; AVX512F-FAST-NEXT: vpbroadcastd 32(%rax), %ymm2 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm22, %zmm0 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm20, %zmm0 +; AVX512F-FAST-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512F-FAST-NEXT: vmovdqa64 %zmm3, 128(%rax) +; AVX512F-FAST-NEXT: vmovdqa64 %zmm5, (%rax) +; AVX512F-FAST-NEXT: vmovdqa64 %zmm16, 320(%rax) +; AVX512F-FAST-NEXT: vmovdqa64 %zmm6, 256(%rax) +; AVX512F-FAST-NEXT: vmovdqa64 %zmm0, 192(%rax) +; AVX512F-FAST-NEXT: vmovdqa64 %zmm7, 384(%rax) +; AVX512F-FAST-NEXT: vmovdqa64 %zmm31, 64(%rax) +; AVX512F-FAST-NEXT: addq $248, %rsp +; AVX512F-FAST-NEXT: vzeroupper +; AVX512F-FAST-NEXT: retq ; ; AVX512BW-LABEL: store_i16_stride7_vf32: ; AVX512BW: # %bb.0: @@ -11576,2699 +10687,1352 @@ define void @store_i16_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve ; AVX2-FAST-PERLANE-NEXT: vzeroupper ; AVX2-FAST-PERLANE-NEXT: retq ; -; AVX512F-ONLY-SLOW-LABEL: store_i16_stride7_vf64: -; AVX512F-ONLY-SLOW: # %bb.0: -; AVX512F-ONLY-SLOW-NEXT: subq $2200, %rsp # imm = 0x898 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 96(%rcx), %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 96(%rdx), %ymm9 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 96(%rdi), %ymm7 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 96(%rsi), %ymm8 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} ymm0 = [128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128,128,128,128,128] -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm0, %ymm2, %ymm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm2, %ymm19 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} ymm11 = -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm11, %ymm9, %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vporq %ymm1, %ymm2, %ymm16 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} ymm12 = [128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128,128,128,128,128,128,128,128,128] -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm12, %ymm8, %ymm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} ymm13 = <12,13,14,15,128,128,u,u,u,u,u,u,u,u,u,u,16,17,128,128,u,u,u,u,u,u,u,u,16,17,18,19> -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm13, %ymm7, %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vporq %ymm1, %ymm2, %ymm17 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} ymm3 = [128,128,128,128,128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 64(%r9), %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm3, %ymm2, %ymm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa %ymm3, %ymm10 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm2, %ymm20 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 64(%r8), %ymm3 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} ymm15 = -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm15, %ymm3, %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm3, %ymm24 -; AVX512F-ONLY-SLOW-NEXT: vpor %ymm1, %ymm2, %ymm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 64(%rcx), %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm0, %ymm2, %ymm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm2, %ymm18 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 64(%rdx), %ymm6 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm11, %ymm6, %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vpor %ymm1, %ymm2, %ymm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 64(%rsi), %ymm5 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm12, %ymm5, %ymm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 64(%rdi), %ymm4 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm13, %ymm4, %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vpor %ymm1, %ymm2, %ymm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%r9), %ymm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm10, %ymm1, %ymm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa %ymm10, %ymm3 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%r8), %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm2, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm15, %ymm2, %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vpor %ymm1, %ymm2, %ymm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rcx), %ymm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm0, %ymm1, %ymm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rdx), %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm2, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm11, %ymm2, %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vpor %ymm1, %ymm2, %ymm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rsi), %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm12, %ymm2, %ymm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm2, %ymm23 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rdi), %ymm10 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm13, %ymm10, %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm10, %ymm25 -; AVX512F-ONLY-SLOW-NEXT: vpor %ymm1, %ymm2, %ymm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 32(%rcx), %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm0, %ymm2, %ymm0 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 32(%rdx), %ymm1 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm11, %ymm1, %ymm11 -; AVX512F-ONLY-SLOW-NEXT: vpor %ymm0, %ymm11, %ymm0 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 32(%rsi), %ymm0 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm12, %ymm0, %ymm12 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 32(%rdi), %ymm11 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm13, %ymm11, %ymm13 -; AVX512F-ONLY-SLOW-NEXT: vpor %ymm12, %ymm13, %ymm10 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 32(%r8), %ymm13 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm15, %ymm13, %ymm12 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 32(%r9), %ymm15 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm3, %ymm15, %ymm14 -; AVX512F-ONLY-SLOW-NEXT: vpor %ymm14, %ymm12, %ymm10 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vprold $16, %ymm15, %ymm12 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm14 = ymm13[1,2,2,3,5,6,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm12 = ymm14[0,1],ymm12[2],ymm14[3,4],ymm12[5],ymm14[6,7,8,9],ymm12[10],ymm14[11,12],ymm12[13],ymm14[14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm14 = ymm15[0,1,2,3,5,6,7,7,8,9,10,11,13,14,15,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm14 = ymm14[2,2,2,3,6,6,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm10 = ymm13[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm10 = ymm14[0,1],ymm10[2],ymm14[3,4],ymm10[5],ymm14[6,7,8,9],ymm10[10],ymm14[11,12],ymm10[13],ymm14[14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm14 = [2,1,3,2,10,10,10,11] -; AVX512F-ONLY-SLOW-NEXT: vpermi2q %zmm10, %zmm12, %zmm14 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 %zmm14, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vbroadcasti128 {{.*#+}} ymm12 = [22,23,26,27,0,0,24,25,26,27,0,0,26,27,26,27,22,23,26,27,0,0,24,25,26,27,0,0,26,27,26,27] -; AVX512F-ONLY-SLOW-NEXT: # ymm12 = mem[0,1,0,1] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm19, %ymm14 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm12, %ymm14, %ymm10 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm12, %ymm19 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm9[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm10 = ymm10[0,1],ymm12[2],ymm10[3,4],ymm12[5],ymm10[6,7,8,9],ymm12[10],ymm10[11,12],ymm12[13],ymm10[14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm10, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm10 = ymm14[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm10 = ymm10[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm9[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm10 = ymm12[0],ymm10[1],ymm12[2,3],ymm10[4],ymm12[5,6,7,8],ymm10[9],ymm12[10,11],ymm10[12],ymm12[13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm10, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm10 = ymm8[0,1,2,3,5,4,6,7,8,9,10,11,13,12,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm10 = ymm10[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm7[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm10 = ymm12[0],ymm10[1],ymm12[2,3],ymm10[4],ymm12[5,6,7,8],ymm10[9],ymm12[10,11],ymm10[12],ymm12[13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm10, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm10 = ymm8[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm10 = ymm10[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm7[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm10 = ymm12[0,1,2],ymm10[3],ymm12[4,5],ymm10[6],ymm12[7,8,9,10],ymm10[11],ymm12[12,13],ymm10[14],ymm12[15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm10, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm9 = ymm9[0,1,1,3,4,5,5,7] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} ymm10 = ymm14[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm10 = ymm10[0,0,0,0,4,4,4,4] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm9 = ymm9[0,1],ymm10[2],ymm9[3,4],ymm10[5],ymm9[6,7,8,9],ymm10[10],ymm9[11,12],ymm10[13],ymm9[14,15] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm9 = ymm9[2,1,3,2] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm7 = ymm7[1,1,1,1,5,5,5,5] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} ymm8 = ymm8[1,2,3,3,4,5,6,7,9,10,11,11,12,13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm8 = ymm8[0,0,2,1,4,4,6,5] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm7 = ymm8[0,1],ymm7[2],ymm8[3,4],ymm7[5],ymm8[6,7,8,9],ymm7[10],ymm8[11,12],ymm7[13],ymm8[14,15] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm7[2,2,2,3] -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm9, %zmm16, %zmm8 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm7, %zmm17, %zmm7 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm8, %zmm7 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm17 = [65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 96(%r8), %ymm12 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm12, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm8 = ymm12[u,u],zero,zero,zero,zero,zero,zero,zero,zero,ymm12[14,15,u,u,u,u],zero,zero,zero,zero,zero,zero,zero,zero,ymm12[16,17,u,u,u,u],zero,zero -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $248, %ymm17, %ymm7, %ymm8 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 96(%r9), %ymm14 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm14, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm3, %ymm14, %ymm9 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm10 = [65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535] -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $248, %ymm10, %ymm8, %ymm9 -; AVX512F-ONLY-SLOW-NEXT: vextracti64x4 $1, %zmm7, %ymm7 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm8 = ymm12[0,0,2,1,4,4,6,5] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm8 = ymm8[2,1,3,3] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm10 = [65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0] -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $184, %ymm7, %ymm10, %ymm8 -; AVX512F-ONLY-SLOW-NEXT: vprold $16, %ymm14, %ymm7 -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm7[2,2,2,2] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm10 = [65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535] -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $184, %ymm8, %ymm10, %ymm7 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %zmm10, %zmm16 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm7, %zmm0, %zmm7 -; AVX512F-ONLY-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm7 = zmm9[0,1,2,3],zmm7[4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512F-ONLY-SLOW-NEXT: vbroadcasti64x4 {{.*#+}} zmm8 = [6,5,0,0,7,6,0,7,6,5,0,0,7,6,0,7] -; AVX512F-ONLY-SLOW-NEXT: # zmm8 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 96(%rax), %ymm7 -; AVX512F-ONLY-SLOW-NEXT: vpermd %zmm7, %zmm8, %zmm9 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm9 = ymm7[0,1,1,3,4,5,5,7] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} ymm10 = [12,13,128,128,128,128,128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128] -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm10, %ymm7, %ymm7 -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm9 = ymm9[0,2,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpandnq %ymm9, %ymm17, %ymm9 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm9, %zmm7, %zmm7 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm14 = [65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535] -; AVX512F-ONLY-SLOW-NEXT: vpbroadcastd 72(%rax), %ymm7 -; AVX512F-ONLY-SLOW-NEXT: vpandn %ymm7, %ymm14, %ymm9 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 64(%rax), %ymm7 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm10, %ymm7, %ymm12 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm12, %zmm9, %zmm9 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpbroadcastd 8(%rax), %ymm9 -; AVX512F-ONLY-SLOW-NEXT: vpandn %ymm9, %ymm14, %ymm9 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rax), %ymm14 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm10, %ymm14, %ymm12 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm14, %ymm22 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm12, %zmm9, %zmm9 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} ymm9 = ymm2[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm9 = ymm9[0,0,0,0,4,4,4,4] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm1[0,1,1,3,4,5,5,7] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm9 = ymm12[0,1],ymm9[2],ymm12[3,4],ymm9[5],ymm12[6,7,8,9],ymm9[10],ymm12[11,12],ymm9[13],ymm12[14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm9, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} ymm9 = ymm0[1,2,3,3,4,5,6,7,9,10,11,11,12,13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm9 = ymm9[0,0,2,1,4,4,6,5] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm11[1,1,1,1,5,5,5,5] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm9 = ymm9[0,1],ymm12[2],ymm9[3,4],ymm12[5],ymm9[6,7,8,9],ymm12[10],ymm9[11,12],ymm12[13],ymm9[14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm9, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 32(%rax), %ymm9 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm10, %ymm9, %ymm10 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm9[0,1,1,3,4,5,5,7] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm12 = ymm12[0,2,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpandnq %ymm12, %ymm17, %ymm12 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm12, %zmm10, %zmm10 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm10 = ymm13[0,0,2,1,4,4,6,5] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} ymm12 = ymm15[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm12[0,0,0,0,4,4,4,4] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm10 = ymm12[0,1,2],ymm10[3],ymm12[4,5],ymm10[6],ymm12[7,8,9,10],ymm10[11],ymm12[12,13],ymm10[14],ymm12[15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm10, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm19, %ymm13 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm13, %ymm2, %ymm10 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm1[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm10 = ymm10[0,1],ymm12[2],ymm10[3,4],ymm12[5],ymm10[6,7,8,9],ymm12[10],ymm10[11,12],ymm12[13],ymm10[14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm10, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm2 = ymm2[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0],ymm2[1],ymm1[2,3],ymm2[4],ymm1[5,6,7,8],ymm2[9],ymm1[10,11],ymm2[12],ymm1[13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm1, %ymm31 -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm1 = ymm0[0,1,2,3,5,4,6,7,8,9,10,11,13,12,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm11[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0],ymm1[1],ymm2[2,3],ymm1[4],ymm2[5,6,7,8],ymm1[9],ymm2[10,11],ymm1[12],ymm2[13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm11[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3],ymm1[4,5],ymm0[6],ymm1[7,8,9,10],ymm0[11],ymm1[12,13],ymm0[14],ymm1[15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpermd %zmm9, %zmm8, %zmm0 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} ymm0 = ymm5[1,2,3,3,4,5,6,7,9,10,11,11,12,13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,0,2,1,4,4,6,5] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm4[1,1,1,1,5,5,5,5] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3,4],ymm1[5],ymm0[6,7,8,9],ymm1[10],ymm0[11,12],ymm1[13],ymm0[14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm5[0,1,2,3,5,4,6,7,8,9,10,11,13,12,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm4[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2,3],ymm0[4],ymm1[5,6,7,8],ymm0[9],ymm1[10,11],ymm0[12],ymm1[13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm18, %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} ymm0 = ymm2[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,0,0,0,4,4,4,4] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm6[0,1,1,3,4,5,5,7] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1],ymm0[2],ymm1[3,4],ymm0[5],ymm1[6,7,8,9],ymm0[10],ymm1[11,12],ymm0[13],ymm1[14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm13, %ymm2, %ymm0 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm18, %ymm3 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm6[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3,4],ymm1[5],ymm0[6,7,8,9],ymm1[10],ymm0[11,12],ymm1[13],ymm0[14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm20, %ymm8 -; AVX512F-ONLY-SLOW-NEXT: vprold $16, %ymm20, %ymm0 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm24[1,2,2,3,5,6,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1],ymm0[2],ymm1[3,4],ymm0[5],ymm1[6,7,8,9],ymm0[10],ymm1[11,12],ymm0[13],ymm1[14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} ymm1 = ymm8[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,0,0,0,4,4,4,4] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm24[0,0,2,1,4,4,6,5] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0,1,2],ymm2[3],ymm1[4,5],ymm2[6],ymm1[7,8,9,10],ymm2[11],ymm1[12,13],ymm2[14],ymm1[15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm10 = [2,2,3,3,10,9,11,10] -; AVX512F-ONLY-SLOW-NEXT: vpermt2q %zmm0, %zmm10, %zmm1 -; AVX512F-ONLY-SLOW-NEXT: vbroadcasti64x4 {{.*#+}} zmm11 = [0,5,4,0,0,6,5,0,0,5,4,0,0,6,5,0] -; AVX512F-ONLY-SLOW-NEXT: # zmm11 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpermd 64(%rax), %zmm11, %zmm0 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $184, %zmm1, %zmm17, %zmm0 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm6[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm1 = ymm3[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3],ymm1[4],ymm0[5,6,7,8],ymm1[9],ymm0[10,11],ymm1[12],ymm0[13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm4[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm1 = ymm5[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2],ymm1[3],ymm0[4,5],ymm1[6],ymm0[7,8,9,10],ymm1[11],ymm0[12,13],ymm1[14],ymm0[15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm24[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm1 = ymm8[0,1,2,3,5,6,7,7,8,9,10,11,13,14,15,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[2,2,2,3,6,6,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm2 = ymm1[0,1],ymm0[2],ymm1[3,4],ymm0[5],ymm1[6,7,8,9],ymm0[10],ymm1[11,12],ymm0[13],ymm1[14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm12 = [4,5,4,5,4,5,6,7,16,17,16,17,16,17,17,19] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 96(%r9), %xmm0 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 96(%r8), %xmm1 -; AVX512F-ONLY-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} xmm4 = xmm3[0,1,3,2,4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpermt2d %zmm4, %zmm12, %zmm2 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm4 = ymm7[2,3,3,3,6,7,7,7] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm4 = ymm4[2,1,3,2] -; AVX512F-ONLY-SLOW-NEXT: vpbroadcastd 96(%rax), %ymm5 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm5, %zmm4, %zmm4 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm5 = [65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535] -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $184, %zmm2, %zmm5, %zmm4 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %zmm5, %zmm15 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 96(%rsi), %xmm2 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 96(%rdi), %xmm4 -; AVX512F-ONLY-SLOW-NEXT: vprold $16, %xmm2, %xmm5 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} xmm6 = xmm4[1,1,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} xmm5 = xmm6[0,1],xmm5[2],xmm6[3,4],xmm5[5],xmm6[6,7] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm5, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm5 = xmm4[0],xmm2[0],xmm4[1],xmm2[1],xmm4[2],xmm2[2],xmm4[3],xmm2[3] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %xmm5, %xmm18 -; AVX512F-ONLY-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm2[4],xmm4[4],xmm2[5],xmm4[5],xmm2[6],xmm4[6],xmm2[7],xmm4[7] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 96(%rcx), %xmm2 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 96(%rdx), %xmm4 -; AVX512F-ONLY-SLOW-NEXT: vpbroadcastq {{.*#+}} xmm6 = [6,7,4,5,0,0,8,9,6,7,4,5,0,0,8,9] -; AVX512F-ONLY-SLOW-NEXT: vpshufb %xmm6, %xmm2, %xmm5 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa %xmm6, %xmm7 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} xmm6 = xmm4[1,1,2,2] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} xmm5 = xmm6[0],xmm5[1],xmm6[2,3],xmm5[4],xmm6[5,6],xmm5[7] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm5, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm5 = xmm4[0],xmm2[0],xmm4[1],xmm2[1],xmm4[2],xmm2[2],xmm4[3],xmm2[3] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa %xmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm4[4],xmm2[4],xmm4[5],xmm2[5],xmm4[6],xmm2[6],xmm4[7],xmm2[7] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} xmm2 = xmm3[0,1,2,3,4,5,7,6] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} xmm0 = [0,1,2,3,4,5,4,5,6,7,10,11,8,9,10,11] -; AVX512F-ONLY-SLOW-NEXT: vpshufb %xmm0, %xmm1, %xmm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm28 = <16,18,19,19,19,19,u,u,0,1,0,1,2,3,2,3> -; AVX512F-ONLY-SLOW-NEXT: vpermt2d %zmm2, %zmm28, %zmm1 -; AVX512F-ONLY-SLOW-NEXT: vpbroadcastd 100(%rax), %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vpbroadcastd 104(%rax), %ymm3 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm2 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $184, %zmm1, %zmm16, %zmm2 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 64(%rcx), %xmm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 64(%rdx), %xmm2 -; AVX512F-ONLY-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %xmm3, %xmm30 -; AVX512F-ONLY-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3] -; AVX512F-ONLY-SLOW-NEXT: vpshufb %xmm7, %xmm1, %xmm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa %xmm7, %xmm8 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,2,2] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0],xmm1[1],xmm2[2,3],xmm1[4],xmm2[5,6],xmm1[7] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} xmm2 = xmm3[0,1,3,2,4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm3 = <16,16,17,17,17,17,u,u,0,1,0,1,2,3,2,3> -; AVX512F-ONLY-SLOW-NEXT: vpermt2d %zmm2, %zmm3, %zmm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 64(%rdi), %xmm2 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 64(%rsi), %xmm4 -; AVX512F-ONLY-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm5 = xmm2[0],xmm4[0],xmm2[1],xmm4[1],xmm2[2],xmm4[2],xmm2[3],xmm4[3] -; AVX512F-ONLY-SLOW-NEXT: vpshufb %xmm0, %xmm5, %xmm5 -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm5 = ymm5[0,0,1,1] -; AVX512F-ONLY-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm6 = xmm4[4],xmm2[4],xmm4[5],xmm2[5],xmm4[6],xmm2[6],xmm4[7],xmm2[7] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %xmm6, %xmm26 -; AVX512F-ONLY-SLOW-NEXT: vprold $16, %xmm4, %xmm4 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm4[2],xmm2[3,4],xmm4[5],xmm2[6,7] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,0,2,1] -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm2, %zmm5, %zmm4 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm2 = [65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0] -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $226, %zmm1, %zmm2, %zmm4 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 64(%r9), %xmm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 64(%r8), %xmm4 -; AVX512F-ONLY-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm5 = xmm4[4],xmm1[4],xmm4[5],xmm1[5],xmm4[6],xmm1[6],xmm4[7],xmm1[7] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %xmm5, %xmm16 -; AVX512F-ONLY-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm4[0],xmm1[0],xmm4[1],xmm1[1],xmm4[2],xmm1[2],xmm4[3],xmm1[3] -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} xmm4 = xmm1[0,1,2,3,4,5,7,6] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} xmm1 = xmm1[0,1,3,2,4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm6 = <0,1,0,1,0,1,1,3,16,18,19,19,19,19,u,u> -; AVX512F-ONLY-SLOW-NEXT: vpermt2d %zmm4, %zmm6, %zmm1 -; AVX512F-ONLY-SLOW-NEXT: vpbroadcastd 64(%rax), %ymm4 -; AVX512F-ONLY-SLOW-NEXT: vpbroadcastd 68(%rax), %ymm5 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm5, %zmm4, %zmm4 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm9 = [65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535] -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $184, %zmm1, %zmm9, %zmm4 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rcx), %xmm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rdx), %xmm5 -; AVX512F-ONLY-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm5[4],xmm1[4],xmm5[5],xmm1[5],xmm5[6],xmm1[6],xmm5[7],xmm1[7] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %xmm4, %xmm19 -; AVX512F-ONLY-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm7 = xmm5[0],xmm1[0],xmm5[1],xmm1[1],xmm5[2],xmm1[2],xmm5[3],xmm1[3] -; AVX512F-ONLY-SLOW-NEXT: vpshufb %xmm8, %xmm1, %xmm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %xmm8, %xmm29 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} xmm5 = xmm5[1,1,2,2] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} xmm1 = xmm5[0],xmm1[1],xmm5[2,3],xmm1[4],xmm5[5,6],xmm1[7] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} xmm5 = xmm7[0,1,3,2,4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpermt2d %zmm5, %zmm3, %zmm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rdi), %xmm3 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rsi), %xmm5 -; AVX512F-ONLY-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm7 = xmm3[0],xmm5[0],xmm3[1],xmm5[1],xmm3[2],xmm5[2],xmm3[3],xmm5[3] -; AVX512F-ONLY-SLOW-NEXT: vpshufb %xmm0, %xmm7, %xmm7 -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm7[0,0,1,1] -; AVX512F-ONLY-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm14 = xmm5[4],xmm3[4],xmm5[5],xmm3[5],xmm5[6],xmm3[6],xmm5[7],xmm3[7] -; AVX512F-ONLY-SLOW-NEXT: vprold $16, %xmm5, %xmm5 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[1,1,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1],xmm5[2],xmm3[3,4],xmm5[5],xmm3[6,7] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,0,2,1] -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm3, %zmm7, %zmm3 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $226, %zmm1, %zmm2, %zmm3 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%r9), %xmm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%r8), %xmm2 -; AVX512F-ONLY-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7] -; AVX512F-ONLY-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3] -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} xmm2 = xmm1[0,1,2,3,4,5,7,6] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} xmm1 = xmm1[0,1,3,2,4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpermt2d %zmm2, %zmm6, %zmm1 -; AVX512F-ONLY-SLOW-NEXT: vpbroadcastd (%rax), %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vpbroadcastd 4(%rax), %ymm3 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm2 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $184, %zmm1, %zmm9, %zmm2 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm23, %ymm7 -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} ymm1 = ymm7[1,2,3,3,4,5,6,7,9,10,11,11,12,13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,0,2,1,4,4,6,5] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm25[1,1,1,1,5,5,5,5] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0,1],ymm2[2],ymm1[3,4],ymm2[5],ymm1[6,7,8,9],ymm2[10],ymm1[11,12],ymm2[13],ymm1[14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm1, %ymm20 -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm1 = ymm7[0,1,2,3,5,4,6,7,8,9,10,11,13,12,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm25[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0],ymm1[1],ymm2[2,3],ymm1[4],ymm2[5,6,7,8],ymm1[9],ymm2[10,11],ymm1[12],ymm2[13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm1, %ymm27 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm3 # 32-byte Reload -; AVX512F-ONLY-SLOW-NEXT: vprold $16, %ymm3, %ymm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm5 # 32-byte Reload -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm5[1,2,2,3,5,6,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0,1],ymm1[2],ymm2[3,4],ymm1[5],ymm2[6,7,8,9],ymm1[10],ymm2[11,12],ymm1[13],ymm2[14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} ymm2 = ymm3[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[0,0,0,0,4,4,4,4] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm6 = ymm5[0,0,2,1,4,4,6,5] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm2 = ymm2[0,1,2],ymm6[3],ymm2[4,5],ymm6[6],ymm2[7,8,9,10],ymm6[11],ymm2[12,13],ymm6[14],ymm2[15] -; AVX512F-ONLY-SLOW-NEXT: vpermt2q %zmm1, %zmm10, %zmm2 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm8 # 32-byte Reload -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} ymm1 = ymm8[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,0,0,0,4,4,4,4] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm10 # 32-byte Reload -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm6 = ymm10[0,1,1,3,4,5,5,7] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm6[0,1],ymm1[2],ymm6[3,4],ymm1[5],ymm6[6,7,8,9],ymm1[10],ymm6[11,12],ymm1[13],ymm6[14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm1, %ymm24 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %ymm13, %ymm8, %ymm1 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm6 = ymm10[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0,1],ymm6[2],ymm1[3,4],ymm6[5],ymm1[6,7,8,9],ymm6[10],ymm1[11,12],ymm6[13],ymm1[14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm1, %ymm21 -; AVX512F-ONLY-SLOW-NEXT: vpermd (%rax), %zmm11, %zmm1 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $184, %zmm2, %zmm17, %zmm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm10[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm2 = ymm8[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0],ymm2[1],ymm1[2,3],ymm2[4],ymm1[5,6,7,8],ymm2[9],ymm1[10,11],ymm2[12],ymm1[13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm25[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm2 = ymm7[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0,1,2],ymm2[3],ymm1[4,5],ymm2[6],ymm1[7,8,9,10],ymm2[11],ymm1[12,13],ymm2[14],ymm1[15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm5[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm2 = ymm3[0,1,2,3,5,6,7,7,8,9,10,11,13,14,15,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[2,2,2,3,6,6,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0,1],ymm1[2],ymm2[3,4],ymm1[5],ymm2[6,7,8,9],ymm1[10],ymm2[11,12],ymm1[13],ymm2[14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 32(%r9), %xmm7 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 32(%r8), %xmm2 -; AVX512F-ONLY-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm6 = xmm2[0],xmm7[0],xmm2[1],xmm7[1],xmm2[2],xmm7[2],xmm2[3],xmm7[3] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} xmm11 = xmm6[0,1,3,2,4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpermt2d %zmm11, %zmm12, %zmm1 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm11 = ymm22[2,3,3,3,6,7,7,7] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm11 = ymm11[2,1,3,2] -; AVX512F-ONLY-SLOW-NEXT: vpbroadcastd 32(%rax), %ymm12 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm12, %zmm11, %zmm25 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $184, %zmm1, %zmm15, %zmm25 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 32(%rdi), %xmm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 32(%rsi), %xmm12 -; AVX512F-ONLY-SLOW-NEXT: vprold $16, %xmm12, %xmm15 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} xmm13 = xmm1[1,1,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} xmm3 = xmm13[0,1],xmm15[2],xmm13[3,4],xmm15[5],xmm13[6,7] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm3, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm13 = xmm1[0],xmm12[0],xmm1[1],xmm12[1],xmm1[2],xmm12[2],xmm1[3],xmm12[3] -; AVX512F-ONLY-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm12[4],xmm1[4],xmm12[5],xmm1[5],xmm12[6],xmm1[6],xmm12[7],xmm1[7] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm2[4],xmm7[4],xmm2[5],xmm7[5],xmm2[6],xmm7[6],xmm2[7],xmm7[7] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %xmm16, %xmm1 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %xmm0, %xmm1, %xmm1 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %xmm0, %xmm4, %xmm3 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %xmm18, %xmm4 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %xmm0, %xmm4, %xmm4 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm4, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpshufb %xmm0, %xmm13, %xmm4 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm4, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpshufb %xmm0, %xmm2, %xmm2 -; AVX512F-ONLY-SLOW-NEXT: vpermq $234, {{[-0-9]+}}(%r{{[sb]}}p), %ymm23 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # ymm23 = mem[2,2,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq $232, {{[-0-9]+}}(%r{{[sb]}}p), %ymm22 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # ymm22 = mem[0,2,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq $232, {{[-0-9]+}}(%r{{[sb]}}p), %ymm18 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # ymm18 = mem[0,2,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq $246, {{[-0-9]+}}(%r{{[sb]}}p), %ymm17 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # ymm17 = mem[2,1,3,3] -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} xmm0 = xmm6[0,1,2,3,4,5,7,6] -; AVX512F-ONLY-SLOW-NEXT: vpermt2d %zmm0, %zmm28, %zmm2 -; AVX512F-ONLY-SLOW-NEXT: vpbroadcastd 36(%rax), %ymm0 -; AVX512F-ONLY-SLOW-NEXT: vpbroadcastd 40(%rax), %ymm6 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm6, %zmm0, %zmm28 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm28 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 32(%rcx), %xmm6 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %xmm29, %xmm0 -; AVX512F-ONLY-SLOW-NEXT: vpshufb %xmm0, %xmm6, %xmm2 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa 32(%rdx), %xmm0 -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} xmm7 = xmm0[1,1,2,2] -; AVX512F-ONLY-SLOW-NEXT: vpblendw {{.*#+}} xmm2 = xmm7[0],xmm2[1],xmm7[2,3],xmm2[4],xmm7[5,6],xmm2[7] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu %ymm2, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm0[0],xmm6[0],xmm0[1],xmm6[1],xmm0[2],xmm6[2],xmm0[3],xmm6[3] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm6[4],xmm0[5],xmm6[5],xmm0[6],xmm6[6],xmm0[7],xmm6[7] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm4 # 32-byte Reload -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm4[0,1,2,3,5,5,7,6,8,9,10,11,13,13,15,14] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm29 = ymm0[3,3,3,3] -; AVX512F-ONLY-SLOW-NEXT: vpshufd $233, {{[-0-9]+}}(%r{{[sb]}}p), %ymm2 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # ymm2 = mem[1,2,2,3,5,6,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm10 = ymm4[2,1,2,3,6,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} ymm10 = ymm10[0,0,3,3,4,5,6,7,8,8,11,11,12,13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm0 = ymm10[2,2,2,2] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,0,1,1] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %xmm30, %xmm4 -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} xmm10 = xmm4[0,2,3,3,4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm10 = ymm10[0,0,2,1] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %xmm26, %xmm4 -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} xmm8 = xmm4[2,1,2,3,4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} xmm8 = xmm8[0,1,2,3,4,5,5,4] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm8 = ymm8[0,0,1,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,0,1,1] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %xmm19, %xmm4 -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} xmm15 = xmm4[0,2,3,3,4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm15 = ymm15[0,0,2,1] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} xmm12 = xmm14[2,1,2,3,4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} xmm12 = xmm12[0,1,2,3,4,5,5,4] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm12 = ymm12[0,0,1,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq $182, {{[-0-9]+}}(%r{{[sb]}}p), %ymm4 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # ymm4 = mem[2,1,3,2] -; AVX512F-ONLY-SLOW-NEXT: vpermq $234, {{[-0-9]+}}(%r{{[sb]}}p), %ymm5 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # ymm5 = mem[2,2,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq $250, {{[-0-9]+}}(%r{{[sb]}}p), %ymm6 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # ymm6 = mem[2,2,3,3] -; AVX512F-ONLY-SLOW-NEXT: vpermpd $234, {{[-0-9]+}}(%r{{[sb]}}p), %ymm7 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # ymm7 = mem[2,2,2,3] -; AVX512F-ONLY-SLOW-NEXT: vmovups %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm31 = ymm31[0,2,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq $232, {{[-0-9]+}}(%r{{[sb]}}p), %ymm30 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # ymm30 = mem[0,2,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq $246, {{[-0-9]+}}(%r{{[sb]}}p), %ymm26 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # ymm26 = mem[2,1,3,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq $234, {{[-0-9]+}}(%r{{[sb]}}p), %ymm19 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # ymm19 = mem[2,2,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq $232, {{[-0-9]+}}(%r{{[sb]}}p), %ymm11 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # ymm11 = mem[0,2,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq $182, {{[-0-9]+}}(%r{{[sb]}}p), %ymm16 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # ymm16 = mem[2,1,3,2] -; AVX512F-ONLY-SLOW-NEXT: vpermq $234, {{[-0-9]+}}(%r{{[sb]}}p), %ymm7 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # ymm7 = mem[2,2,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm20 = ymm20[2,2,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm13 = ymm27[0,2,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm14 = ymm24[2,1,3,2] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm9 = ymm21[2,2,2,3] -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm22, %zmm23, %zmm22 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm17, %zmm18, %zmm23 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm27 = [65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535] -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $184, %zmm22, %zmm27, %zmm23 -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm2 = ymm2[2,1,3,2] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm17 = [65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535] -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $184, %ymm23, %ymm17, %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm17 = [65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535] -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $184, %ymm2, %ymm17, %ymm0 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm2 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm1[0,1,2,3],zmm2[4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $234, {{[-0-9]+}}(%r{{[sb]}}p), %zmm17, %zmm2 # 64-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm1 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm3 = zmm3[0,1,2,3],zmm1[4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $234, {{[-0-9]+}}(%r{{[sb]}}p), %zmm17, %zmm3 # 64-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm10, %zmm10 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm8, %zmm8 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm22 = [65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535] -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $226, %zmm10, %zmm22, %zmm8 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm17 = [0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535] -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $226, %zmm2, %zmm17, %zmm8 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm15, %zmm2 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm12, %zmm10 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $226, %zmm2, %zmm22, %zmm10 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $226, %zmm3, %zmm17, %zmm10 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm4, %zmm1, %zmm2 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm5, %zmm1, %zmm18 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm18 -; AVX512F-ONLY-SLOW-NEXT: vextracti64x4 $1, %zmm23, %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm1 = [65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535] -; AVX512F-ONLY-SLOW-NEXT: vpternlogd $226, 124(%r8){1to8}, %ymm1, %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm3 = [0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535] -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $184, %ymm2, %ymm3, %ymm29 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm21 # 64-byte Reload -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $248, {{[-0-9]+}}(%r{{[sb]}}p), %zmm3, %zmm21 # 64-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm6, %zmm0, %zmm2 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512F-ONLY-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm24 = zmm1[0,1,2,3],zmm2[4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $234, {{[-0-9]+}}(%r{{[sb]}}p), %zmm3, %zmm24 # 64-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm29, %zmm0, %zmm2 -; AVX512F-ONLY-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm2[4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm23 # 64-byte Reload -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm1 = [65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0] -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $184, %zmm0, %zmm1, %zmm23 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm29 # 64-byte Reload -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $184, {{[-0-9]+}}(%r{{[sb]}}p), %zmm1, %zmm29 # 64-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm0 = [65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm17 # 64-byte Reload -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $184, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm17 # 64-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $184, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm6 # 64-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm11, %zmm19, %zmm0 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm7, %zmm16, %zmm2 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm3 = [0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535] -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $226, %zmm0, %zmm3, %zmm2 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm13, %zmm20, %zmm0 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm9, %zmm14, %zmm4 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $226, %zmm0, %zmm3, %zmm4 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm0 = [65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $184, %zmm2, %zmm0, %zmm19 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm20 # 64-byte Reload -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $184, %zmm4, %zmm0, %zmm20 -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm31, %zmm0, %zmm0 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm26, %zmm30, %zmm2 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $184, %zmm0, %zmm27, %zmm2 -; AVX512F-ONLY-SLOW-NEXT: vpermq $232, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # ymm0 = mem[0,2,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw $180, {{[-0-9]+}}(%r{{[sb]}}p), %xmm3 # 16-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # xmm3 = mem[0,1,3,2,4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[0,0,1,1] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,1,1,3] -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm0 -; AVX512F-ONLY-SLOW-NEXT: vpermq $246, {{[-0-9]+}}(%r{{[sb]}}p), %ymm3 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # ymm3 = mem[2,1,3,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq $80, {{[-0-9]+}}(%r{{[sb]}}p), %ymm4 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # ymm4 = mem[0,0,1,1] -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm4, %zmm3, %zmm3 -; AVX512F-ONLY-SLOW-NEXT: vpermq $96, {{[-0-9]+}}(%r{{[sb]}}p), %ymm4 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # ymm4 = mem[0,0,2,1] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw $230, {{[-0-9]+}}(%r{{[sb]}}p), %xmm5 # 16-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # xmm5 = mem[2,1,2,3,4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} xmm5 = xmm5[0,1,2,3,4,5,5,4] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm5 = ymm5[0,0,1,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq $80, {{[-0-9]+}}(%r{{[sb]}}p), %ymm26 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # ymm26 = mem[0,0,1,1] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw $248, {{[-0-9]+}}(%r{{[sb]}}p), %xmm7 # 16-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # xmm7 = mem[0,2,3,3,4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm7[0,0,2,1] -; AVX512F-ONLY-SLOW-NEXT: vpermq $232, {{[-0-9]+}}(%r{{[sb]}}p), %ymm9 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # ymm9 = mem[0,2,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw $180, {{[-0-9]+}}(%r{{[sb]}}p), %xmm11 # 16-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # xmm11 = mem[0,1,3,2,4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} xmm11 = xmm11[0,0,1,1] -; AVX512F-ONLY-SLOW-NEXT: vpermq $246, {{[-0-9]+}}(%r{{[sb]}}p), %ymm12 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # ymm12 = mem[2,1,3,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq $80, {{[-0-9]+}}(%r{{[sb]}}p), %ymm13 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # ymm13 = mem[0,0,1,1] -; AVX512F-ONLY-SLOW-NEXT: vpermq $96, {{[-0-9]+}}(%r{{[sb]}}p), %ymm14 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # ymm14 = mem[0,0,2,1] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw $230, {{[-0-9]+}}(%r{{[sb]}}p), %xmm15 # 16-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # xmm15 = mem[2,1,2,3,4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} xmm15 = xmm15[0,1,2,3,4,5,5,4] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm15 = ymm15[0,0,1,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq $80, {{[-0-9]+}}(%r{{[sb]}}p), %ymm16 # 32-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # ymm16 = mem[0,0,1,1] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw $248, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload -; AVX512F-ONLY-SLOW-NEXT: # xmm1 = mem[0,2,3,3,4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,0,2,1] -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $226, %zmm0, %zmm27, %zmm3 -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm0 = ymm11[0,1,1,3] -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm0, %zmm9, %zmm0 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm13, %zmm12, %zmm9 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $226, %zmm0, %zmm27, %zmm9 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm0 = [0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $184, %zmm3, %zmm0, %zmm11 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $184, %zmm9, %zmm0, %zmm25 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm5, %zmm4, %zmm0 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm7, %zmm26, %zmm3 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $226, %zmm0, %zmm22, %zmm3 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm15, %zmm14, %zmm0 -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm1, %zmm16, %zmm1 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $226, %zmm0, %zmm22, %zmm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm0 = [65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0] -; AVX512F-ONLY-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $184, %zmm3, %zmm0, %zmm4 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $184, %zmm1, %zmm0, %zmm28 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm18, %zmm24 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %zmm29, %zmm0 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm0 -; AVX512F-ONLY-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %zmm24, 320(%rax) -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %zmm28, 256(%rax) -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %zmm25, 192(%rax) -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %zmm20, 128(%rax) -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %zmm10, 64(%rax) -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %zmm6, (%rax) -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %zmm17, 448(%rax) -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %zmm4, 704(%rax) -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %zmm11, 640(%rax) -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %zmm19, 576(%rax) -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %zmm8, 512(%rax) -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %zmm0, 384(%rax) -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %zmm21, 768(%rax) -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %zmm23, 832(%rax) -; AVX512F-ONLY-SLOW-NEXT: addq $2200, %rsp # imm = 0x898 -; AVX512F-ONLY-SLOW-NEXT: vzeroupper -; AVX512F-ONLY-SLOW-NEXT: retq -; -; AVX512F-ONLY-FAST-LABEL: store_i16_stride7_vf64: -; AVX512F-ONLY-FAST: # %bb.0: -; AVX512F-ONLY-FAST-NEXT: subq $1496, %rsp # imm = 0x5D8 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 96(%rcx), %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm15 = [128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128,128,128,128,128] -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm15, %ymm0, %ymm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm0, %ymm20 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 96(%rdx), %ymm9 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm0 = -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm0, %ymm9, %ymm3 -; AVX512F-ONLY-FAST-NEXT: vmovdqa %ymm0, %ymm10 -; AVX512F-ONLY-FAST-NEXT: vporq %ymm2, %ymm3, %ymm16 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 96(%rsi), %ymm6 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm14 = [128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128,128,128,128,128,128,128,128,128] -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm14, %ymm6, %ymm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 96(%rdi), %ymm7 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm11 = <12,13,14,15,128,128,u,u,u,u,u,u,u,u,u,u,16,17,128,128,u,u,u,u,u,u,u,u,16,17,18,19> -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm11, %ymm7, %ymm3 -; AVX512F-ONLY-FAST-NEXT: vporq %ymm2, %ymm3, %ymm17 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm3 = [128,128,128,128,128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128] -; AVX512F-ONLY-FAST-NEXT: vmovdqa 64(%r9), %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm3, %ymm0, %ymm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 64(%r8), %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm5 = -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm5, %ymm0, %ymm4 -; AVX512F-ONLY-FAST-NEXT: vporq %ymm2, %ymm4, %ymm18 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 64(%rcx), %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm0, (%rsp) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm15, %ymm0, %ymm8 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 64(%rdx), %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm10, %ymm0, %ymm12 -; AVX512F-ONLY-FAST-NEXT: vpor %ymm8, %ymm12, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa 64(%rsi), %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm14, %ymm0, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 64(%rdi), %ymm1 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm11, %ymm1, %ymm13 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm1, %ymm28 -; AVX512F-ONLY-FAST-NEXT: vpor %ymm0, %ymm13, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%r9), %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm3, %ymm0, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%r8), %ymm1 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm5, %ymm1, %ymm13 -; AVX512F-ONLY-FAST-NEXT: vporq %ymm0, %ymm13, %ymm19 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rcx), %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm15, %ymm0, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rdx), %ymm1 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa %ymm10, %ymm2 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm10, %ymm1, %ymm13 -; AVX512F-ONLY-FAST-NEXT: vpor %ymm0, %ymm13, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rsi), %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm14, %ymm0, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rdi), %ymm1 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm11, %ymm1, %ymm13 -; AVX512F-ONLY-FAST-NEXT: vpor %ymm0, %ymm13, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%rcx), %ymm10 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm15, %ymm10, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%rdx), %ymm15 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm2, %ymm15, %ymm13 -; AVX512F-ONLY-FAST-NEXT: vpor %ymm0, %ymm13, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%rsi), %ymm8 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm14, %ymm8, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%rdi), %ymm4 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm11, %ymm4, %ymm11 -; AVX512F-ONLY-FAST-NEXT: vpor %ymm0, %ymm11, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%r8), %ymm13 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm5, %ymm13, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%r9), %ymm14 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm3, %ymm14, %ymm5 -; AVX512F-ONLY-FAST-NEXT: vmovdqa %ymm3, %ymm12 -; AVX512F-ONLY-FAST-NEXT: vporq %ymm5, %ymm0, %ymm21 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm20, %ymm2 -; AVX512F-ONLY-FAST-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11] -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm11 = ymm9[0,1,1,3,4,5,5,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm11[0,1],ymm0[2],ymm11[3,4],ymm0[5],ymm11[6,7,8,9],ymm0[10],ymm11[11,12],ymm0[13],ymm11[14,15] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,1,3,2] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm11 = ymm6[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,20,21,18,19,20,21,24,25,26,27,22,23,22,23] -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm7[1,1,1,1,5,5,5,5] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm11[0,1],ymm3[2],ymm11[3,4],ymm3[5],ymm11[6,7,8,9],ymm3[10],ymm11[11,12],ymm3[13],ymm11[14,15] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm3 = ymm3[2,2,2,3] -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm16, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm3, %zmm17, %zmm3 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm3 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm25 = [65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535] -; AVX512F-ONLY-FAST-NEXT: vmovdqa 96(%r8), %ymm11 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm11[u,u],zero,zero,zero,zero,zero,zero,zero,zero,ymm11[14,15,u,u,u,u],zero,zero,zero,zero,zero,zero,zero,zero,ymm11[16,17,u,u,u,u],zero,zero -; AVX512F-ONLY-FAST-NEXT: vpternlogq $248, %ymm25, %ymm3, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 96(%r9), %ymm5 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm5, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm12, %ymm5, %ymm1 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm12 = [65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535] -; AVX512F-ONLY-FAST-NEXT: vpternlogq $248, %ymm12, %ymm0, %ymm1 -; AVX512F-ONLY-FAST-NEXT: vextracti64x4 $1, %zmm3, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm3 = -; AVX512F-ONLY-FAST-NEXT: vpermd %ymm11, %ymm3, %ymm3 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm17 = [65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0] -; AVX512F-ONLY-FAST-NEXT: vpternlogq $184, %ymm0, %ymm17, %ymm3 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm17, %zmm22 -; AVX512F-ONLY-FAST-NEXT: vprold $16, %ymm5, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,2,2,2] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm5 = [65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535] -; AVX512F-ONLY-FAST-NEXT: vpternlogq $184, %ymm3, %ymm5, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm1[0,1,2,3],zmm0[4,5,6,7] -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-FAST-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm1 = [0,1,4,5,4,5,5,7] -; AVX512F-ONLY-FAST-NEXT: vmovdqa 96(%rax), %ymm0 -; AVX512F-ONLY-FAST-NEXT: vpermd %ymm0, %ymm1, %ymm1 -; AVX512F-ONLY-FAST-NEXT: vpandnq %ymm1, %ymm25, %ymm1 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm5 = [12,13,128,128,128,128,128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128] -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm5, %ymm0, %ymm3 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm5, %ymm20 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm1, %zmm3, %zmm1 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm3 = -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm3, %ymm6, %ymm1 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm3, %ymm26 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm7[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm3[0,1,2],ymm1[3],ymm3[4,5],ymm1[6],ymm3[7,8,9,10],ymm1[11],ymm3[12,13],ymm1[14],ymm3[15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm5 = <10,11,8,9,u,u,u,u,u,u,u,u,u,u,u,u,26,27,24,25,u,u,u,u,26,27,24,25,u,u,u,u> -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm5, %ymm6, %ymm3 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm5, %ymm29 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm6 = ymm7[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm6[0],ymm3[1],ymm6[2,3],ymm3[4],ymm6[5,6,7,8],ymm3[9],ymm6[10,11],ymm3[12],ymm6[13,14,15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm6 = [0,2,2,3,10,9,11,11] -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm1, %zmm6, %zmm3 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm7 = <14,15,12,13,u,u,u,u,u,u,u,u,u,u,u,u,30,31,28,29,u,u,u,u,30,31,28,29,u,u,u,u> -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm7, %ymm2, %ymm1 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm7, %ymm27 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm7 = ymm9[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm7[0],ymm1[1],ymm7[2,3],ymm1[4],ymm7[5,6,7,8],ymm1[9],ymm7[10,11],ymm1[12],ymm7[13,14,15] -; AVX512F-ONLY-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm5 = [22,23,26,27,0,0,24,25,26,27,0,0,26,27,26,27,22,23,26,27,0,0,24,25,26,27,0,0,26,27,26,27] -; AVX512F-ONLY-FAST-NEXT: # ymm5 = mem[0,1,0,1] -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm5, %ymm2, %ymm7 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm5, %ymm16 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm9 = ymm9[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm7 = ymm7[0,1],ymm9[2],ymm7[3,4],ymm9[5],ymm7[6,7,8,9],ymm9[10],ymm7[11,12],ymm9[13],ymm7[14,15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm17 = [2,2,2,3,8,10,10,11] -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm1, %zmm17, %zmm7 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm1 = [65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535] -; AVX512F-ONLY-FAST-NEXT: vpternlogq $226, %zmm3, %zmm1, %zmm7 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm1, %zmm24 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm1 = <5,u,u,u,6,u,u,6> -; AVX512F-ONLY-FAST-NEXT: vpermd %ymm11, %ymm1, %ymm1 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 64(%rax), %zmm12 -; AVX512F-ONLY-FAST-NEXT: vbroadcasti64x4 {{.*#+}} zmm3 = [30,5,0,0,31,6,0,31,30,5,0,0,31,6,0,31] -; AVX512F-ONLY-FAST-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-FAST-NEXT: vpermi2d %zmm12, %zmm0, %zmm3 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm23 = [65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535] -; AVX512F-ONLY-FAST-NEXT: vpbroadcastd 72(%rax), %ymm0 -; AVX512F-ONLY-FAST-NEXT: vpandnq %ymm0, %ymm23, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 64(%rax), %ymm7 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm20, %ymm5 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm5, %ymm7, %ymm3 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm7, %ymm30 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm11 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm18, %zmm0, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 64(%r9), %xmm1 -; AVX512F-ONLY-FAST-NEXT: vmovdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa 64(%r8), %xmm2 -; AVX512F-ONLY-FAST-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %xmm2, %xmm20 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} xmm9 = [0,1,2,3,4,5,4,5,6,7,10,11,8,9,10,11] -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm9, %xmm3, %xmm3 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm18 = [0,0,1,1,12,13,14,15] -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm0, %zmm18, %zmm3 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $248, %zmm23, %zmm3, %zmm11 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpbroadcastd 8(%rax), %ymm0 -; AVX512F-ONLY-FAST-NEXT: vpandnq %ymm0, %ymm23, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rax), %ymm1 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm5, %ymm1, %ymm3 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm5 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm19, %zmm0, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%r9), %xmm1 -; AVX512F-ONLY-FAST-NEXT: vmovdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%r8), %xmm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7] -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm9, %xmm3, %xmm3 -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm0, %zmm18, %zmm3 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $248, %zmm23, %zmm3, %zmm5 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpbroadcastd {{.*#+}} ymm7 = [18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21] -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm7, %ymm14, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm13[0,0,2,1,4,4,6,5] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2],ymm3[3],ymm0[4,5],ymm3[6],ymm0[7,8,9,10],ymm3[11],ymm0[12,13],ymm3[14],ymm0[15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm3 = <0,1,u,3,10,10,11,11> -; AVX512F-ONLY-FAST-NEXT: vpermi2q %zmm0, %zmm21, %zmm3 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm8, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm26, %ymm9 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm9, %ymm8, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm4, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm4[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm3[0,1,2],ymm0[3],ymm3[4,5],ymm0[6],ymm3[7,8,9,10],ymm0[11],ymm3[12,13],ymm0[14],ymm3[15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm29, %ymm1 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm1, %ymm8, %ymm3 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm5 = ymm4[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm5[0],ymm3[1],ymm5[2,3],ymm3[4],ymm5[5,6,7,8],ymm3[9],ymm5[10,11],ymm3[12],ymm5[13,14,15] -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm0, %zmm6, %zmm3 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm10, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm27, %ymm11 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm11, %ymm10, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm15, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm5 = ymm15[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm5[0],ymm0[1],ymm5[2,3],ymm0[4],ymm5[5,6,7,8],ymm0[9],ymm5[10,11],ymm0[12],ymm5[13,14,15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm16, %ymm4 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm4, %ymm10, %ymm5 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm6 = ymm15[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm2 = ymm5[0,1],ymm6[2],ymm5[3,4],ymm6[5],ymm5[6,7,8,9],ymm6[10],ymm5[11,12],ymm6[13],ymm5[14,15] -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm0, %zmm17, %zmm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm24, %zmm16 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $226, %zmm3, %zmm24, %zmm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm15 = [26,27,28,29,26,27,28,29,26,27,28,29,30,31,30,31,26,27,28,29,26,27,28,29,26,27,28,29,30,31,30,31] -; AVX512F-ONLY-FAST-NEXT: # ymm15 = mem[0,1,0,1] -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm15, %ymm14, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm13[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1],ymm3[2],ymm0[3,4],ymm3[5],ymm0[6,7,8,9],ymm3[10],ymm0[11,12],ymm3[13],ymm0[14,15] -; AVX512F-ONLY-FAST-NEXT: vprold $16, %ymm14, %ymm3 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm5 = ymm13[1,2,2,3,5,6,6,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm5[0,1],ymm3[2],ymm5[3,4],ymm3[5],ymm5[6,7,8,9],ymm3[10],ymm5[11,12],ymm3[13],ymm5[14,15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm18 = [2,1,3,2,10,10,10,11] -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm0, %zmm18, %zmm3 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 (%rax), %zmm19 -; AVX512F-ONLY-FAST-NEXT: vbroadcasti64x4 {{.*#+}} zmm2 = [14,21,0,0,15,22,0,15,14,21,0,0,15,22,0,15] -; AVX512F-ONLY-FAST-NEXT: # zmm2 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%rax), %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpermi2d %zmm0, %zmm19, %zmm2 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $184, %zmm3, %zmm22, %zmm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm13 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm1, %ymm13, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm28[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm3[0],ymm0[1],ymm3[2,3],ymm0[4],ymm3[5,6,7,8],ymm0[9],ymm3[10,11],ymm0[12],ymm3[13,14,15] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm3 = ymm13[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,20,21,18,19,20,21,24,25,26,27,22,23,22,23] -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm5 = ymm28[1,1,1,1,5,5,5,5] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm3[0,1],ymm5[2],ymm3[3,4],ymm5[5],ymm3[6,7,8,9],ymm5[10],ymm3[11,12],ymm5[13],ymm3[14,15] -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm0, %zmm17, %zmm3 -; AVX512F-ONLY-FAST-NEXT: vmovdqu (%rsp), %ymm1 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm4, %ymm1, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm2 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm5 = ymm2[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1],ymm5[2],ymm0[3,4],ymm5[5],ymm0[6,7,8,9],ymm5[10],ymm0[11,12],ymm5[13],ymm0[14,15] -; AVX512F-ONLY-FAST-NEXT: vpunpcklwd {{.*#+}} ymm5 = ymm1[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11] -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm6 = ymm2[0,1,1,3,4,5,5,7] -; AVX512F-ONLY-FAST-NEXT: vmovdqa %ymm2, %ymm4 -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm5 = ymm6[0,1],ymm5[2],ymm6[3,4],ymm5[5],ymm6[6,7,8,9],ymm5[10],ymm6[11,12],ymm5[13],ymm6[14,15] -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm0, %zmm18, %zmm5 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm5 -; AVX512F-ONLY-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm8 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vprold $16, %ymm8, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm2 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm2[1,2,2,3,5,6,6,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm3[0,1],ymm0[2],ymm3[3,4],ymm0[5],ymm3[6,7,8,9],ymm0[10],ymm3[11,12],ymm0[13],ymm3[14,15] -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm7, %ymm8, %ymm3 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm6 = ymm2[0,0,2,1,4,4,6,5] -; AVX512F-ONLY-FAST-NEXT: vmovdqa %ymm2, %ymm14 -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm3[0,1,2],ymm6[3],ymm3[4,5],ymm6[6],ymm3[7,8,9,10],ymm6[11],ymm3[12,13],ymm6[14],ymm3[15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm2 = [2,2,3,3,10,9,11,10] -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm0, %zmm2, %zmm3 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm30, %zmm12, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vbroadcasti64x4 {{.*#+}} zmm2 = [0,13,4,0,0,14,5,0,0,13,4,0,0,14,5,0] -; AVX512F-ONLY-FAST-NEXT: # zmm2 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-FAST-NEXT: vpermd %zmm0, %zmm2, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $184, %zmm3, %zmm25, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm5, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm11, %ymm1, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm1 = ymm4[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0],ymm0[1],ymm1[2,3],ymm0[4],ymm1[5,6,7,8],ymm0[9],ymm1[10,11],ymm0[12],ymm1[13,14,15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa 96(%rcx), %xmm3 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 96(%rdx), %xmm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %xmm3, %xmm29 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,2,3,0,1,2,3,6,7,4,5,6,7,4,5] -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm2, %xmm0, %xmm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa %xmm2, %xmm7 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm31 = [0,2,2,3,8,9,9,11] -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm0, %zmm31, %zmm1 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm9, %ymm13, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm2 = ymm28[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm2[0,1,2],ymm0[3],ymm2[4,5],ymm0[6],ymm2[7,8,9,10],ymm0[11],ymm2[12,13],ymm0[14],ymm2[15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa 96(%rsi), %xmm4 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 96(%rdi), %xmm3 -; AVX512F-ONLY-FAST-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %xmm4, %xmm26 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %xmm3, %xmm24 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} xmm9 = [0,1,2,3,4,5,4,5,6,7,10,11,8,9,10,11] -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm9, %xmm2, %xmm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm3 = [2,1,3,3,8,8,9,9] -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm2, %zmm3, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $226, %zmm1, %zmm16, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm15, %ymm8, %ymm1 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm2 = ymm14[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm13 = ymm1[0,1],ymm2[2],ymm1[3,4],ymm2[5],ymm1[6,7,8,9],ymm2[10],ymm1[11,12],ymm2[13],ymm1[14,15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa 64(%rcx), %xmm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 64(%rdx), %xmm1 -; AVX512F-ONLY-FAST-NEXT: vpbroadcastq {{.*#+}} xmm4 = [6,7,4,5,0,0,8,9,6,7,4,5,0,0,8,9] -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm4, %xmm2, %xmm5 -; AVX512F-ONLY-FAST-NEXT: vmovdqa %xmm4, %xmm8 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} xmm6 = xmm1[1,1,2,2] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} xmm5 = xmm6[0],xmm5[1],xmm6[2,3],xmm5[4],xmm6[5,6],xmm5[7] -; AVX512F-ONLY-FAST-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7] -; AVX512F-ONLY-FAST-NEXT: vmovdqa %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3] -; AVX512F-ONLY-FAST-NEXT: vmovdqa %xmm7, %xmm14 -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm7, %xmm1, %xmm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm1 = [0,1,1,3,8,8,9,9] -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm5, %zmm1, %zmm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm1, %zmm11 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 64(%rdi), %xmm4 -; AVX512F-ONLY-FAST-NEXT: vmovdqa %xmm4, (%rsp) # 16-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa 64(%rsi), %xmm6 -; AVX512F-ONLY-FAST-NEXT: vmovdqa %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512F-ONLY-FAST-NEXT: vprold $16, %xmm6, %xmm1 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[1,1,2,3] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} xmm5 = xmm5[0,1],xmm1[2],xmm5[3,4],xmm1[5],xmm5[6,7] -; AVX512F-ONLY-FAST-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm4[0],xmm6[0],xmm4[1],xmm6[1],xmm4[2],xmm6[2],xmm4[3],xmm6[3] -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm9, %xmm1, %xmm1 -; AVX512F-ONLY-FAST-NEXT: vmovdqa %xmm9, %xmm3 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm27 = [0,0,1,1,8,8,10,9] -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm5, %zmm27, %zmm1 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm5 = [65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0] -; AVX512F-ONLY-FAST-NEXT: vpternlogq $226, %zmm2, %zmm5, %zmm1 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %xmm20, %xmm2 -; AVX512F-ONLY-FAST-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm2, %xmm2 # 16-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: # xmm2 = xmm2[0],mem[0],xmm2[1],mem[1],xmm2[2],mem[2],xmm2[3],mem[3] -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} xmm7 = [0,1,2,3,6,7,4,5,6,7,4,5,12,13,14,15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} xmm10 = [0,1,2,3,8,9,10,11,14,15,12,13,14,15,12,13] -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm10, %xmm2, %xmm6 -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm7, %xmm2, %xmm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm16 = [0,0,0,1,8,9,9,11] -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm6, %zmm16, %zmm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rcx), %xmm4 -; AVX512F-ONLY-FAST-NEXT: vmovdqa %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rdx), %xmm9 -; AVX512F-ONLY-FAST-NEXT: vmovdqa %xmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm8, %xmm4, %xmm6 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} xmm8 = xmm9[1,1,2,2] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} xmm6 = xmm8[0],xmm6[1],xmm8[2,3],xmm6[4],xmm8[5,6],xmm6[7] -; AVX512F-ONLY-FAST-NEXT: vpunpcklwd {{.*#+}} xmm8 = xmm9[0],xmm4[0],xmm9[1],xmm4[1],xmm9[2],xmm4[2],xmm9[3],xmm4[3] -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm14, %xmm8, %xmm8 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %xmm14, %xmm21 -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm6, %zmm11, %zmm8 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rdi), %xmm4 -; AVX512F-ONLY-FAST-NEXT: vmovdqa %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rsi), %xmm11 -; AVX512F-ONLY-FAST-NEXT: vmovdqa %xmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512F-ONLY-FAST-NEXT: vprold $16, %xmm11, %xmm6 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} xmm9 = xmm4[1,1,2,3] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} xmm6 = xmm9[0,1],xmm6[2],xmm9[3,4],xmm6[5],xmm9[6,7] -; AVX512F-ONLY-FAST-NEXT: vpunpcklwd {{.*#+}} xmm9 = xmm4[0],xmm11[0],xmm4[1],xmm11[1],xmm4[2],xmm11[2],xmm4[3],xmm11[3] -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm3, %xmm9, %xmm9 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %xmm3, %xmm28 -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm6, %zmm27, %zmm9 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $226, %zmm8, %zmm5, %zmm9 -; AVX512F-ONLY-FAST-NEXT: vpbroadcastd 64(%rax), %ymm5 -; AVX512F-ONLY-FAST-NEXT: vpbroadcastd 68(%rax), %ymm6 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm6, %zmm5, %zmm23 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm4 = [65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535] -; AVX512F-ONLY-FAST-NEXT: vpternlogq $184, %zmm2, %zmm4, %zmm23 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm2 = [65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535] -; AVX512F-ONLY-FAST-NEXT: vpternlogq $184, %zmm1, %zmm2, %zmm23 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1, %xmm1 # 16-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1],xmm1[2],mem[2],xmm1[3],mem[3] -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm10, %xmm1, %xmm5 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %xmm10, %xmm22 -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm7, %xmm1, %xmm1 -; AVX512F-ONLY-FAST-NEXT: vmovdqa %xmm7, %xmm3 -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm5, %zmm16, %zmm1 -; AVX512F-ONLY-FAST-NEXT: vpbroadcastd (%rax), %ymm5 -; AVX512F-ONLY-FAST-NEXT: vpbroadcastd 4(%rax), %ymm6 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm6, %zmm5, %zmm20 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $184, %zmm1, %zmm4, %zmm20 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $184, %zmm9, %zmm2, %zmm20 -; AVX512F-ONLY-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm4 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm4[10,11,8,9,u,u,u,u,u,u,u,u,u,u,u,u,26,27,24,25,u,u,u,u,26,27,24,25,u,u,u,u] -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %ymm17 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm2 = ymm17[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0],ymm1[1],ymm2[2,3],ymm1[4],ymm2[5,6,7,8],ymm1[9],ymm2[10,11],ymm1[12],ymm2[13,14,15] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm4[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,20,21,18,19,20,21,24,25,26,27,22,23,22,23] -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm5 = ymm17[1,1,1,1,5,5,5,5] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm2 = ymm2[0,1],ymm5[2],ymm2[3,4],ymm5[5],ymm2[6,7,8,9],ymm5[10],ymm2[11,12],ymm5[13],ymm2[14,15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm5 = [2,2,2,3,8,10,10,11] -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm1, %zmm5, %zmm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm9 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm9[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,22,23,26,27,u,u,24,25,26,27,u,u,26,27,26,27] -; AVX512F-ONLY-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm7 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm5 = ymm7[2,2,2,2,6,6,6,6] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0,1],ymm5[2],ymm1[3,4],ymm5[5],ymm1[6,7,8,9],ymm5[10],ymm1[11,12],ymm5[13],ymm1[14,15] -; AVX512F-ONLY-FAST-NEXT: vpunpcklwd {{.*#+}} ymm5 = ymm9[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11] -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm6 = ymm7[0,1,1,3,4,5,5,7] -; AVX512F-ONLY-FAST-NEXT: vmovdqa %ymm7, %ymm15 -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm8 = ymm6[0,1],ymm5[2],ymm6[3,4],ymm5[5],ymm6[6,7,8,9],ymm5[10],ymm6[11,12],ymm5[13],ymm6[14,15] -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm1, %zmm18, %zmm8 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm8 -; AVX512F-ONLY-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm5 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vprold $16, %ymm5, %ymm1 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %ymm16 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm2 = ymm16[1,2,2,3,5,6,6,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0,1],ymm1[2],ymm2[3,4],ymm1[5],ymm2[6,7,8,9],ymm1[10],ymm2[11,12],ymm1[13],ymm2[14,15] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm5[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm5, %ymm18 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm5 = ymm16[0,0,2,1,4,4,6,5] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm2 = ymm2[0,1,2],ymm5[3],ymm2[4,5],ymm5[6],ymm2[7,8,9,10],ymm5[11],ymm2[12,13],ymm5[14],ymm2[15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm5 = [2,2,3,3,10,9,11,10] -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm1, %zmm5, %zmm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm5 = [2,2,2,3,8,8,8,9] -; AVX512F-ONLY-FAST-NEXT: vmovdqa 96(%r9), %xmm11 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 96(%r8), %xmm7 -; AVX512F-ONLY-FAST-NEXT: vpunpcklwd {{.*#+}} xmm10 = xmm7[0],xmm11[0],xmm7[1],xmm11[1],xmm7[2],xmm11[2],xmm7[3],xmm11[3] -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm3, %xmm10, %xmm1 -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm1, %zmm5, %zmm13 -; AVX512F-ONLY-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm14 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm14, %zmm19, %zmm1 -; AVX512F-ONLY-FAST-NEXT: vbroadcasti64x4 {{.*#+}} zmm5 = [0,13,4,0,0,14,5,0,0,13,4,0,0,14,5,0] -; AVX512F-ONLY-FAST-NEXT: # zmm5 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-FAST-NEXT: vpermd %zmm1, %zmm5, %zmm19 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $184, %zmm2, %zmm25, %zmm19 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm8, %zmm19 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%rcx), %xmm12 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%rdx), %xmm8 -; AVX512F-ONLY-FAST-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm8[0],xmm12[0],xmm8[1],xmm12[1],xmm8[2],xmm12[2],xmm8[3],xmm12[3] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %xmm21, %xmm2 -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm2, %xmm1, %xmm1 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm9[14,15,12,13,u,u,u,u,u,u,u,u,u,u,u,u,30,31,28,29,u,u,u,u,30,31,28,29,u,u,u,u] -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm9 = ymm15[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm15 = ymm9[0],ymm2[1],ymm9[2,3],ymm2[4],ymm9[5,6,7,8],ymm2[9],ymm9[10,11],ymm2[12],ymm9[13,14,15] -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm1, %zmm31, %zmm15 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} ymm31 = [6,7,3,3,7,7,6,7] -; AVX512F-ONLY-FAST-NEXT: vpermd %ymm30, %ymm31, %ymm1 -; AVX512F-ONLY-FAST-NEXT: vpbroadcastd 96(%rax), %ymm2 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm21 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm30 = [65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535] -; AVX512F-ONLY-FAST-NEXT: vpternlogq $184, %zmm13, %zmm30, %zmm21 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm21 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %xmm24, %xmm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %xmm26, %xmm1 -; AVX512F-ONLY-FAST-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7] -; AVX512F-ONLY-FAST-NEXT: vprold $16, %xmm26, %xmm1 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} xmm2 = xmm24[1,1,2,3] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} xmm3 = xmm2[0,1],xmm1[2],xmm2[3,4],xmm1[5],xmm2[6,7] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm4[u,u,u,u,u,u,u,u,u,u,u,u,14,15,12,13,u,u,u,u,30,31,28,29,u,u,u,u,30,31,28,29] -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm2 = ymm17[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0,1,2],ymm1[3],ymm2[4,5],ymm1[6],ymm2[7,8,9,10],ymm1[11],ymm2[12,13],ymm1[14],ymm2[15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%rdi), %xmm5 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%rsi), %xmm4 -; AVX512F-ONLY-FAST-NEXT: vpunpcklwd {{.*#+}} xmm13 = xmm5[0],xmm4[0],xmm5[1],xmm4[1],xmm5[2],xmm4[2],xmm5[3],xmm4[3] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %xmm28, %xmm6 -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm6, %xmm13, %xmm13 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm2 = [2,1,3,3,8,8,9,9] -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm13, %zmm2, %zmm1 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[4,5,2,3,4,5,6,7,8,9,10,11,10,11,8,9] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm17 = [0,0,2,1,8,8,9,11] -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm0, %zmm17, %zmm3 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %xmm29, %xmm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm9 # 16-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm9[4],xmm0[4],xmm9[5],xmm0[5],xmm9[6],xmm0[6],xmm9[7],xmm0[7] -; AVX512F-ONLY-FAST-NEXT: vpbroadcastq {{.*#+}} xmm24 = [6,7,4,5,0,0,8,9,6,7,4,5,0,0,8,9] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %xmm24, %xmm13 -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm13, %xmm0, %xmm0 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} xmm9 = xmm9[1,1,2,2] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} xmm0 = xmm9[0],xmm0[1],xmm9[2,3],xmm0[4],xmm9[5,6],xmm0[7] -; AVX512F-ONLY-FAST-NEXT: vpshuflw {{.*#+}} xmm2 = xmm2[0,2,3,3,4,5,6,7] -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm2, %zmm27, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm25 = [65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535] -; AVX512F-ONLY-FAST-NEXT: vpternlogq $226, %zmm3, %zmm25, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm7[4],xmm11[4],xmm7[5],xmm11[5],xmm7[6],xmm11[6],xmm7[7],xmm11[7] -; AVX512F-ONLY-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm7 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpternlogq $184, %ymm3, %ymm30, %ymm7 -; AVX512F-ONLY-FAST-NEXT: vextracti64x4 $1, %zmm3, %ymm11 -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm6, %xmm2, %xmm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %xmm22, %xmm13 -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm13, %xmm10, %xmm3 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm28 = [0,1,1,3,8,8,9,9] -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm2, %zmm28, %zmm3 -; AVX512F-ONLY-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm6 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpshufhw {{.*#+}} ymm2 = ymm6[0,1,2,3,5,5,7,6,8,9,10,11,13,13,15,14] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm26 = ymm2[3,3,3,3] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm6[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,24,25,24,25,22,23,22,23,u,u,u,u,u,u,u,u] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm29 = ymm2[2,2,2,2] -; AVX512F-ONLY-FAST-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm15, %zmm1 -; AVX512F-ONLY-FAST-NEXT: vpbroadcastd 100(%rax), %ymm2 -; AVX512F-ONLY-FAST-NEXT: vpbroadcastd 104(%rax), %ymm6 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm6, %zmm2, %zmm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm22 = [65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535] -; AVX512F-ONLY-FAST-NEXT: vpternlogq $184, %zmm3, %zmm22, %zmm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm18, %ymm3 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm3 = ymm3[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,26,27,28,29,26,27,28,29,26,27,28,29,30,31,30,31] -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} ymm6 = ymm16[3,3,3,3,7,7,7,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm10 = ymm3[0,1],ymm6[2],ymm3[3,4],ymm6[5],ymm3[6,7,8,9],ymm6[10],ymm3[11,12],ymm6[13],ymm3[14,15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%r9), %xmm15 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%r8), %xmm3 -; AVX512F-ONLY-FAST-NEXT: vpunpcklwd {{.*#+}} xmm6 = xmm3[0],xmm15[0],xmm3[1],xmm15[1],xmm3[2],xmm15[2],xmm3[3],xmm15[3] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} xmm9 = xmm6[0,1,2,3,6,7,4,5,6,7,4,5,12,13,14,15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm16 = [2,2,2,3,8,8,8,9] -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm9, %zmm16, %zmm10 -; AVX512F-ONLY-FAST-NEXT: vpermd %ymm14, %ymm31, %ymm9 -; AVX512F-ONLY-FAST-NEXT: vpbroadcastd 32(%rax), %ymm18 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm18, %zmm9, %zmm9 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $184, %zmm10, %zmm30, %zmm9 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm9 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm1 = [65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0] -; AVX512F-ONLY-FAST-NEXT: vpternlogq $184, %zmm0, %zmm1, %zmm2 -; AVX512F-ONLY-FAST-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm4[4],xmm5[4],xmm4[5],xmm5[5],xmm4[6],xmm5[6],xmm4[7],xmm5[7] -; AVX512F-ONLY-FAST-NEXT: vprold $16, %xmm4, %xmm4 -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} xmm5 = xmm5[1,1,2,3] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} xmm4 = xmm5[0,1],xmm4[2],xmm5[3,4],xmm4[5],xmm5[6,7] -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} xmm10 = [4,5,2,3,4,5,6,7,8,9,10,11,10,11,8,9] -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm10, %xmm0, %xmm0 -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm0, %zmm17, %zmm4 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %xmm24, %xmm0 -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm0, %xmm12, %xmm0 -; AVX512F-ONLY-FAST-NEXT: vpunpckhwd {{.*#+}} xmm5 = xmm8[4],xmm12[4],xmm8[5],xmm12[5],xmm8[6],xmm12[6],xmm8[7],xmm12[7] -; AVX512F-ONLY-FAST-NEXT: vpshufd {{.*#+}} xmm8 = xmm8[1,1,2,2] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} xmm0 = xmm8[0],xmm0[1],xmm8[2,3],xmm0[4],xmm8[5,6],xmm0[7] -; AVX512F-ONLY-FAST-NEXT: vpshuflw {{.*#+}} xmm5 = xmm5[0,2,3,3,4,5,6,7] -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm5, %zmm27, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $226, %zmm4, %zmm25, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm3[4],xmm15[4],xmm3[5],xmm15[5],xmm3[6],xmm15[6],xmm3[7],xmm15[7] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} xmm3 = xmm3[0,1,2,3,4,5,4,5,6,7,10,11,8,9,10,11] -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm13, %xmm6, %xmm4 -; AVX512F-ONLY-FAST-NEXT: vpermt2q %zmm3, %zmm28, %zmm4 -; AVX512F-ONLY-FAST-NEXT: vpbroadcastd 36(%rax), %ymm3 -; AVX512F-ONLY-FAST-NEXT: vpbroadcastd 40(%rax), %ymm5 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm5, %zmm3, %zmm3 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $184, %zmm4, %zmm22, %zmm3 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $184, %zmm0, %zmm1, %zmm3 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm0 = [65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535] -; AVX512F-ONLY-FAST-NEXT: vpternlogq $184, %ymm7, %ymm0, %ymm29 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm0 = [65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535] -; AVX512F-ONLY-FAST-NEXT: vpternlogd $226, 124(%r8){1to8}, %ymm0, %ymm11 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm0 = [0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535] -; AVX512F-ONLY-FAST-NEXT: vpternlogq $184, %ymm11, %ymm0, %ymm26 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm26, %zmm0, %zmm1 -; AVX512F-ONLY-FAST-NEXT: vshufi64x2 {{.*#+}} zmm1 = zmm29[0,1,2,3],zmm1[4,5,6,7] -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm12 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpunpckhwd (%rsp), %xmm1, %xmm1 # 16-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: # xmm1 = xmm1[4],mem[4],xmm1[5],mem[5],xmm1[6],mem[6],xmm1[7],mem[7] -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm4 # 16-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpunpckhwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm4, %xmm4 # 16-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: # xmm4 = xmm4[4],mem[4],xmm4[5],mem[5],xmm4[6],mem[6],xmm4[7],mem[7] -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm5 # 16-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpunpckhwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm5, %xmm5 # 16-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: # xmm5 = xmm5[4],mem[4],xmm5[5],mem[5],xmm5[6],mem[6],xmm5[7],mem[7] -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm10, %xmm1, %xmm1 -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm10, %xmm5, %xmm5 -; AVX512F-ONLY-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm6 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpunpcklwd {{.*#+}} ymm6 = ymm6[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11] -; AVX512F-ONLY-FAST-NEXT: vpshufd $212, {{[-0-9]+}}(%r{{[sb]}}p), %ymm7 # 32-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: # ymm7 = mem[0,1,1,3,4,5,5,7] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm6 = ymm7[0,1],ymm6[2],ymm7[3,4],ymm6[5],ymm7[6,7,8,9],ymm6[10],ymm7[11,12],ymm6[13],ymm7[14,15] -; AVX512F-ONLY-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm7 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm7 = ymm7[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,20,21,18,19,20,21,24,25,26,27,22,23,22,23] -; AVX512F-ONLY-FAST-NEXT: vpshufd $85, {{[-0-9]+}}(%r{{[sb]}}p), %ymm8 # 32-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: # ymm8 = mem[1,1,1,1,5,5,5,5] -; AVX512F-ONLY-FAST-NEXT: vpblendw {{.*#+}} ymm7 = ymm7[0,1],ymm8[2],ymm7[3,4],ymm8[5],ymm7[6,7,8,9],ymm8[10],ymm7[11,12],ymm8[13],ymm7[14,15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm8 = [0,1,4,5,4,5,5,7] -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm10 # 64-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpermd %ymm10, %ymm8, %ymm8 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm10 = ymm10[12,13],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm10[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm10[16,17],zero,zero -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm11 = [65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535] -; AVX512F-ONLY-FAST-NEXT: vpandn %ymm8, %ymm11, %ymm8 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm8, %zmm10, %zmm8 -; AVX512F-ONLY-FAST-NEXT: vpshuflw $248, {{[-0-9]+}}(%r{{[sb]}}p), %xmm10 # 16-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: # xmm10 = mem[0,2,3,3,4,5,6,7] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm10 = ymm10[0,0,2,1] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,0,1,3] -; AVX512F-ONLY-FAST-NEXT: vpshuflw {{.*#+}} xmm4 = xmm4[0,2,3,3,4,5,6,7] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm4 = ymm4[0,0,2,1] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm5 = ymm5[0,0,1,3] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm6 = ymm6[2,1,3,2] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm7 = ymm7[2,2,2,3] -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm11, %zmm13 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm10, %zmm10 # 32-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm1, %zmm1 # 32-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: vpternlogq $226, %zmm10, %zmm25, %zmm1 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm4, %zmm4 # 32-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm5, %zmm5 # 32-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: vpternlogq $226, %zmm4, %zmm25, %zmm5 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm4 = [0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535] -; AVX512F-ONLY-FAST-NEXT: vpternlogq $226, {{[-0-9]+}}(%r{{[sb]}}p), %zmm4, %zmm1 # 64-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: vpternlogq $226, {{[-0-9]+}}(%r{{[sb]}}p), %zmm4, %zmm5 # 64-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm6, %zmm4, %zmm4 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm7, %zmm6, %zmm6 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm4, %zmm6 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpternlogq $248, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm4 # 64-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: vpternlogq $248, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm8 # 64-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm6, %zmm8 -; AVX512F-ONLY-FAST-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm8, 320(%rax) -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm3, 256(%rax) -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm9, 192(%rax) -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm19, 128(%rax) -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm20, (%rax) -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm23, 448(%rax) -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm2, 704(%rax) -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm21, 640(%rax) -; AVX512F-ONLY-FAST-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-FAST-NEXT: vmovaps %zmm0, 576(%rax) -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm13, 384(%rax) -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm5, 64(%rax) -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm1, 512(%rax) -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm12, 832(%rax) -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm4, 768(%rax) -; AVX512F-ONLY-FAST-NEXT: addq $1496, %rsp # imm = 0x5D8 -; AVX512F-ONLY-FAST-NEXT: vzeroupper -; AVX512F-ONLY-FAST-NEXT: retq -; -; AVX512DQ-SLOW-LABEL: store_i16_stride7_vf64: -; AVX512DQ-SLOW: # %bb.0: -; AVX512DQ-SLOW-NEXT: subq $2200, %rsp # imm = 0x898 -; AVX512DQ-SLOW-NEXT: vmovdqa 96(%rcx), %ymm2 -; AVX512DQ-SLOW-NEXT: vmovdqa 96(%rdx), %ymm9 -; AVX512DQ-SLOW-NEXT: vmovdqa 96(%rdi), %ymm7 -; AVX512DQ-SLOW-NEXT: vmovdqa 96(%rsi), %ymm8 -; AVX512DQ-SLOW-NEXT: vmovdqa {{.*#+}} ymm0 = [128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128,128,128,128,128] -; AVX512DQ-SLOW-NEXT: vpshufb %ymm0, %ymm2, %ymm1 -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm2, %ymm19 -; AVX512DQ-SLOW-NEXT: vmovdqa {{.*#+}} ymm11 = -; AVX512DQ-SLOW-NEXT: vpshufb %ymm11, %ymm9, %ymm2 -; AVX512DQ-SLOW-NEXT: vporq %ymm1, %ymm2, %ymm16 -; AVX512DQ-SLOW-NEXT: vmovdqa {{.*#+}} ymm12 = [128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128,128,128,128,128,128,128,128,128] -; AVX512DQ-SLOW-NEXT: vpshufb %ymm12, %ymm8, %ymm1 -; AVX512DQ-SLOW-NEXT: vmovdqa {{.*#+}} ymm13 = <12,13,14,15,128,128,u,u,u,u,u,u,u,u,u,u,16,17,128,128,u,u,u,u,u,u,u,u,16,17,18,19> -; AVX512DQ-SLOW-NEXT: vpshufb %ymm13, %ymm7, %ymm2 -; AVX512DQ-SLOW-NEXT: vporq %ymm1, %ymm2, %ymm17 -; AVX512DQ-SLOW-NEXT: vmovdqa {{.*#+}} ymm3 = [128,128,128,128,128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128] -; AVX512DQ-SLOW-NEXT: vmovdqa 64(%r9), %ymm2 -; AVX512DQ-SLOW-NEXT: vpshufb %ymm3, %ymm2, %ymm1 -; AVX512DQ-SLOW-NEXT: vmovdqa %ymm3, %ymm10 -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm2, %ymm20 -; AVX512DQ-SLOW-NEXT: vmovdqa 64(%r8), %ymm3 -; AVX512DQ-SLOW-NEXT: vmovdqa {{.*#+}} ymm15 = -; AVX512DQ-SLOW-NEXT: vpshufb %ymm15, %ymm3, %ymm2 -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm3, %ymm24 -; AVX512DQ-SLOW-NEXT: vpor %ymm1, %ymm2, %ymm1 -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqa 64(%rcx), %ymm2 -; AVX512DQ-SLOW-NEXT: vpshufb %ymm0, %ymm2, %ymm1 -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm2, %ymm18 -; AVX512DQ-SLOW-NEXT: vmovdqa 64(%rdx), %ymm6 -; AVX512DQ-SLOW-NEXT: vpshufb %ymm11, %ymm6, %ymm2 -; AVX512DQ-SLOW-NEXT: vpor %ymm1, %ymm2, %ymm1 -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqa 64(%rsi), %ymm5 -; AVX512DQ-SLOW-NEXT: vpshufb %ymm12, %ymm5, %ymm1 -; AVX512DQ-SLOW-NEXT: vmovdqa 64(%rdi), %ymm4 -; AVX512DQ-SLOW-NEXT: vpshufb %ymm13, %ymm4, %ymm2 -; AVX512DQ-SLOW-NEXT: vpor %ymm1, %ymm2, %ymm1 -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqa (%r9), %ymm1 -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vpshufb %ymm10, %ymm1, %ymm1 -; AVX512DQ-SLOW-NEXT: vmovdqa %ymm10, %ymm3 -; AVX512DQ-SLOW-NEXT: vmovdqa (%r8), %ymm2 -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm2, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vpshufb %ymm15, %ymm2, %ymm2 -; AVX512DQ-SLOW-NEXT: vpor %ymm1, %ymm2, %ymm1 -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqa (%rcx), %ymm1 -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vpshufb %ymm0, %ymm1, %ymm1 -; AVX512DQ-SLOW-NEXT: vmovdqa (%rdx), %ymm2 -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm2, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vpshufb %ymm11, %ymm2, %ymm2 -; AVX512DQ-SLOW-NEXT: vpor %ymm1, %ymm2, %ymm1 -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqa (%rsi), %ymm2 -; AVX512DQ-SLOW-NEXT: vpshufb %ymm12, %ymm2, %ymm1 -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm2, %ymm23 -; AVX512DQ-SLOW-NEXT: vmovdqa (%rdi), %ymm10 -; AVX512DQ-SLOW-NEXT: vpshufb %ymm13, %ymm10, %ymm2 -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm10, %ymm25 -; AVX512DQ-SLOW-NEXT: vpor %ymm1, %ymm2, %ymm1 -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqa 32(%rcx), %ymm2 -; AVX512DQ-SLOW-NEXT: vpshufb %ymm0, %ymm2, %ymm0 -; AVX512DQ-SLOW-NEXT: vmovdqa 32(%rdx), %ymm1 -; AVX512DQ-SLOW-NEXT: vpshufb %ymm11, %ymm1, %ymm11 -; AVX512DQ-SLOW-NEXT: vpor %ymm0, %ymm11, %ymm0 -; AVX512DQ-SLOW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqa 32(%rsi), %ymm0 -; AVX512DQ-SLOW-NEXT: vpshufb %ymm12, %ymm0, %ymm12 -; AVX512DQ-SLOW-NEXT: vmovdqa 32(%rdi), %ymm11 -; AVX512DQ-SLOW-NEXT: vpshufb %ymm13, %ymm11, %ymm13 -; AVX512DQ-SLOW-NEXT: vpor %ymm12, %ymm13, %ymm10 -; AVX512DQ-SLOW-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqa 32(%r8), %ymm13 -; AVX512DQ-SLOW-NEXT: vpshufb %ymm15, %ymm13, %ymm12 -; AVX512DQ-SLOW-NEXT: vmovdqa 32(%r9), %ymm15 -; AVX512DQ-SLOW-NEXT: vpshufb %ymm3, %ymm15, %ymm14 -; AVX512DQ-SLOW-NEXT: vpor %ymm14, %ymm12, %ymm10 -; AVX512DQ-SLOW-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-SLOW-NEXT: vprold $16, %ymm15, %ymm12 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm14 = ymm13[1,2,2,3,5,6,6,7] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm12 = ymm14[0,1],ymm12[2],ymm14[3,4],ymm12[5],ymm14[6,7,8,9],ymm12[10],ymm14[11,12],ymm12[13],ymm14[14,15] -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} ymm14 = ymm15[0,1,2,3,5,6,7,7,8,9,10,11,13,14,15,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm14 = ymm14[2,2,2,3,6,6,6,7] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm10 = ymm13[3,3,3,3,7,7,7,7] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm10 = ymm14[0,1],ymm10[2],ymm14[3,4],ymm10[5],ymm14[6,7,8,9],ymm10[10],ymm14[11,12],ymm10[13],ymm14[14,15] -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm14 = [2,1,3,2,10,10,10,11] -; AVX512DQ-SLOW-NEXT: vpermi2q %zmm10, %zmm12, %zmm14 -; AVX512DQ-SLOW-NEXT: vmovdqu64 %zmm14, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-SLOW-NEXT: vbroadcasti128 {{.*#+}} ymm12 = [22,23,26,27,0,0,24,25,26,27,0,0,26,27,26,27,22,23,26,27,0,0,24,25,26,27,0,0,26,27,26,27] -; AVX512DQ-SLOW-NEXT: # ymm12 = mem[0,1,0,1] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm19, %ymm14 -; AVX512DQ-SLOW-NEXT: vpshufb %ymm12, %ymm14, %ymm10 -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm12, %ymm19 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm9[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm10 = ymm10[0,1],ymm12[2],ymm10[3,4],ymm12[5],ymm10[6,7,8,9],ymm12[10],ymm10[11,12],ymm12[13],ymm10[14,15] -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm10, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} ymm10 = ymm14[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm10 = ymm10[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm9[3,3,3,3,7,7,7,7] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm10 = ymm12[0],ymm10[1],ymm12[2,3],ymm10[4],ymm12[5,6,7,8],ymm10[9],ymm12[10,11],ymm10[12],ymm12[13,14,15] -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm10, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} ymm10 = ymm8[0,1,2,3,5,4,6,7,8,9,10,11,13,12,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm10 = ymm10[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm7[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm10 = ymm12[0],ymm10[1],ymm12[2,3],ymm10[4],ymm12[5,6,7,8],ymm10[9],ymm12[10,11],ymm10[12],ymm12[13,14,15] -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm10, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} ymm10 = ymm8[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm10 = ymm10[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm7[3,3,3,3,7,7,7,7] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm10 = ymm12[0,1,2],ymm10[3],ymm12[4,5],ymm10[6],ymm12[7,8,9,10],ymm10[11],ymm12[12,13],ymm10[14],ymm12[15] -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm10, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm9 = ymm9[0,1,1,3,4,5,5,7] -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} ymm10 = ymm14[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm10 = ymm10[0,0,0,0,4,4,4,4] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm9 = ymm9[0,1],ymm10[2],ymm9[3,4],ymm10[5],ymm9[6,7,8,9],ymm10[10],ymm9[11,12],ymm10[13],ymm9[14,15] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm9 = ymm9[2,1,3,2] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm7 = ymm7[1,1,1,1,5,5,5,5] -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} ymm8 = ymm8[1,2,3,3,4,5,6,7,9,10,11,11,12,13,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm8 = ymm8[0,0,2,1,4,4,6,5] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm7 = ymm8[0,1],ymm7[2],ymm8[3,4],ymm7[5],ymm8[6,7,8,9],ymm7[10],ymm8[11,12],ymm7[13],ymm8[14,15] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm7[2,2,2,3] -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm9, %zmm16, %zmm8 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm7, %zmm17, %zmm7 -; AVX512DQ-SLOW-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm8, %zmm7 -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm17 = [65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535] -; AVX512DQ-SLOW-NEXT: vmovdqa 96(%r8), %ymm12 -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm12, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm8 = ymm12[u,u],zero,zero,zero,zero,zero,zero,zero,zero,ymm12[14,15,u,u,u,u],zero,zero,zero,zero,zero,zero,zero,zero,ymm12[16,17,u,u,u,u],zero,zero -; AVX512DQ-SLOW-NEXT: vpternlogq $248, %ymm17, %ymm7, %ymm8 -; AVX512DQ-SLOW-NEXT: vmovdqa 96(%r9), %ymm14 -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm14, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vpshufb %ymm3, %ymm14, %ymm9 -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm10 = [65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535] -; AVX512DQ-SLOW-NEXT: vpternlogq $248, %ymm10, %ymm8, %ymm9 -; AVX512DQ-SLOW-NEXT: vextracti64x4 $1, %zmm7, %ymm7 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm8 = ymm12[0,0,2,1,4,4,6,5] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm8 = ymm8[2,1,3,3] -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm10 = [65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0] -; AVX512DQ-SLOW-NEXT: vpternlogq $184, %ymm7, %ymm10, %ymm8 -; AVX512DQ-SLOW-NEXT: vprold $16, %ymm14, %ymm7 -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm7[2,2,2,2] -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm10 = [65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535] -; AVX512DQ-SLOW-NEXT: vpternlogq $184, %ymm8, %ymm10, %ymm7 -; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm10, %zmm16 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm7, %zmm0, %zmm7 -; AVX512DQ-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm7 = zmm9[0,1,2,3],zmm7[4,5,6,7] -; AVX512DQ-SLOW-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQ-SLOW-NEXT: vbroadcasti32x8 {{.*#+}} zmm8 = [6,5,0,0,7,6,0,7,6,5,0,0,7,6,0,7] -; AVX512DQ-SLOW-NEXT: # zmm8 = mem[0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vmovdqa 96(%rax), %ymm7 -; AVX512DQ-SLOW-NEXT: vpermd %zmm7, %zmm8, %zmm9 -; AVX512DQ-SLOW-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm9 = ymm7[0,1,1,3,4,5,5,7] -; AVX512DQ-SLOW-NEXT: vmovdqa {{.*#+}} ymm10 = [12,13,128,128,128,128,128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128] -; AVX512DQ-SLOW-NEXT: vpshufb %ymm10, %ymm7, %ymm7 -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm9 = ymm9[0,2,2,3] -; AVX512DQ-SLOW-NEXT: vpandnq %ymm9, %ymm17, %ymm9 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm9, %zmm7, %zmm7 -; AVX512DQ-SLOW-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm14 = [65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535] -; AVX512DQ-SLOW-NEXT: vpbroadcastd 72(%rax), %ymm7 -; AVX512DQ-SLOW-NEXT: vpandn %ymm7, %ymm14, %ymm9 -; AVX512DQ-SLOW-NEXT: vmovdqa 64(%rax), %ymm7 -; AVX512DQ-SLOW-NEXT: vpshufb %ymm10, %ymm7, %ymm12 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm12, %zmm9, %zmm9 -; AVX512DQ-SLOW-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-SLOW-NEXT: vpbroadcastd 8(%rax), %ymm9 -; AVX512DQ-SLOW-NEXT: vpandn %ymm9, %ymm14, %ymm9 -; AVX512DQ-SLOW-NEXT: vmovdqa (%rax), %ymm14 -; AVX512DQ-SLOW-NEXT: vpshufb %ymm10, %ymm14, %ymm12 -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm14, %ymm22 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm12, %zmm9, %zmm9 -; AVX512DQ-SLOW-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} ymm9 = ymm2[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm9 = ymm9[0,0,0,0,4,4,4,4] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm1[0,1,1,3,4,5,5,7] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm9 = ymm12[0,1],ymm9[2],ymm12[3,4],ymm9[5],ymm12[6,7,8,9],ymm9[10],ymm12[11,12],ymm9[13],ymm12[14,15] -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm9, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} ymm9 = ymm0[1,2,3,3,4,5,6,7,9,10,11,11,12,13,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm9 = ymm9[0,0,2,1,4,4,6,5] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm11[1,1,1,1,5,5,5,5] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm9 = ymm9[0,1],ymm12[2],ymm9[3,4],ymm12[5],ymm9[6,7,8,9],ymm12[10],ymm9[11,12],ymm12[13],ymm9[14,15] -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm9, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqa 32(%rax), %ymm9 -; AVX512DQ-SLOW-NEXT: vpshufb %ymm10, %ymm9, %ymm10 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm9[0,1,1,3,4,5,5,7] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm12 = ymm12[0,2,2,3] -; AVX512DQ-SLOW-NEXT: vpandnq %ymm12, %ymm17, %ymm12 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm12, %zmm10, %zmm10 -; AVX512DQ-SLOW-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm10 = ymm13[0,0,2,1,4,4,6,5] -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} ymm12 = ymm15[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm12[0,0,0,0,4,4,4,4] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm10 = ymm12[0,1,2],ymm10[3],ymm12[4,5],ymm10[6],ymm12[7,8,9,10],ymm10[11],ymm12[12,13],ymm10[14],ymm12[15] -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm10, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm19, %ymm13 -; AVX512DQ-SLOW-NEXT: vpshufb %ymm13, %ymm2, %ymm10 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm1[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm10 = ymm10[0,1],ymm12[2],ymm10[3,4],ymm12[5],ymm10[6,7,8,9],ymm12[10],ymm10[11,12],ymm12[13],ymm10[14,15] -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm10, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[3,3,3,3,7,7,7,7] -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} ymm2 = ymm2[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0],ymm2[1],ymm1[2,3],ymm2[4],ymm1[5,6,7,8],ymm2[9],ymm1[10,11],ymm2[12],ymm1[13,14,15] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm1, %ymm31 -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} ymm1 = ymm0[0,1,2,3,5,4,6,7,8,9,10,11,13,12,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm11[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0],ymm1[1],ymm2[2,3],ymm1[4],ymm2[5,6,7,8],ymm1[9],ymm2[10,11],ymm1[12],ymm2[13,14,15] -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm11[3,3,3,3,7,7,7,7] -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3],ymm1[4,5],ymm0[6],ymm1[7,8,9,10],ymm0[11],ymm1[12,13],ymm0[14],ymm1[15] -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vpermd %zmm9, %zmm8, %zmm0 -; AVX512DQ-SLOW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} ymm0 = ymm5[1,2,3,3,4,5,6,7,9,10,11,11,12,13,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,0,2,1,4,4,6,5] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm4[1,1,1,1,5,5,5,5] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3,4],ymm1[5],ymm0[6,7,8,9],ymm1[10],ymm0[11,12],ymm1[13],ymm0[14,15] -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm5[0,1,2,3,5,4,6,7,8,9,10,11,13,12,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm4[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2,3],ymm0[4],ymm1[5,6,7,8],ymm0[9],ymm1[10,11],ymm0[12],ymm1[13,14,15] -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm18, %ymm2 -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} ymm0 = ymm2[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,0,0,0,4,4,4,4] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm6[0,1,1,3,4,5,5,7] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1],ymm0[2],ymm1[3,4],ymm0[5],ymm1[6,7,8,9],ymm0[10],ymm1[11,12],ymm0[13],ymm1[14,15] -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vpshufb %ymm13, %ymm2, %ymm0 -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm18, %ymm3 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm6[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3,4],ymm1[5],ymm0[6,7,8,9],ymm1[10],ymm0[11,12],ymm1[13],ymm0[14,15] -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm20, %ymm8 -; AVX512DQ-SLOW-NEXT: vprold $16, %ymm20, %ymm0 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm24[1,2,2,3,5,6,6,7] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1],ymm0[2],ymm1[3,4],ymm0[5],ymm1[6,7,8,9],ymm0[10],ymm1[11,12],ymm0[13],ymm1[14,15] -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} ymm1 = ymm8[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,0,0,0,4,4,4,4] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm24[0,0,2,1,4,4,6,5] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0,1,2],ymm2[3],ymm1[4,5],ymm2[6],ymm1[7,8,9,10],ymm2[11],ymm1[12,13],ymm2[14],ymm1[15] -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm10 = [2,2,3,3,10,9,11,10] -; AVX512DQ-SLOW-NEXT: vpermt2q %zmm0, %zmm10, %zmm1 -; AVX512DQ-SLOW-NEXT: vbroadcasti32x8 {{.*#+}} zmm11 = [0,5,4,0,0,6,5,0,0,5,4,0,0,6,5,0] -; AVX512DQ-SLOW-NEXT: # zmm11 = mem[0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpermd 64(%rax), %zmm11, %zmm0 -; AVX512DQ-SLOW-NEXT: vpternlogq $184, %zmm1, %zmm17, %zmm0 -; AVX512DQ-SLOW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm6[3,3,3,3,7,7,7,7] -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} ymm1 = ymm3[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3],ymm1[4],ymm0[5,6,7,8],ymm1[9],ymm0[10,11],ymm1[12],ymm0[13,14,15] -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm4[3,3,3,3,7,7,7,7] -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} ymm1 = ymm5[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2],ymm1[3],ymm0[4,5],ymm1[6],ymm0[7,8,9,10],ymm1[11],ymm0[12,13],ymm1[14],ymm0[15] -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm24[3,3,3,3,7,7,7,7] -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} ymm1 = ymm8[0,1,2,3,5,6,7,7,8,9,10,11,13,14,15,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[2,2,2,3,6,6,6,7] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm2 = ymm1[0,1],ymm0[2],ymm1[3,4],ymm0[5],ymm1[6,7,8,9],ymm0[10],ymm1[11,12],ymm0[13],ymm1[14,15] -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm12 = [4,5,4,5,4,5,6,7,16,17,16,17,16,17,17,19] -; AVX512DQ-SLOW-NEXT: vmovdqa 96(%r9), %xmm0 -; AVX512DQ-SLOW-NEXT: vmovdqa 96(%r8), %xmm1 -; AVX512DQ-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} xmm4 = xmm3[0,1,3,2,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpermt2d %zmm4, %zmm12, %zmm2 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm4 = ymm7[2,3,3,3,6,7,7,7] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm4 = ymm4[2,1,3,2] -; AVX512DQ-SLOW-NEXT: vpbroadcastd 96(%rax), %ymm5 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm5, %zmm4, %zmm4 -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm5 = [65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535] -; AVX512DQ-SLOW-NEXT: vpternlogq $184, %zmm2, %zmm5, %zmm4 -; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm5, %zmm15 -; AVX512DQ-SLOW-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqa 96(%rsi), %xmm2 -; AVX512DQ-SLOW-NEXT: vmovdqa 96(%rdi), %xmm4 -; AVX512DQ-SLOW-NEXT: vprold $16, %xmm2, %xmm5 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} xmm6 = xmm4[1,1,2,3] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} xmm5 = xmm6[0,1],xmm5[2],xmm6[3,4],xmm5[5],xmm6[6,7] -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm5, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm5 = xmm4[0],xmm2[0],xmm4[1],xmm2[1],xmm4[2],xmm2[2],xmm4[3],xmm2[3] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %xmm5, %xmm18 -; AVX512DQ-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm2[4],xmm4[4],xmm2[5],xmm4[5],xmm2[6],xmm4[6],xmm2[7],xmm4[7] -; AVX512DQ-SLOW-NEXT: vmovdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqa 96(%rcx), %xmm2 -; AVX512DQ-SLOW-NEXT: vmovdqa 96(%rdx), %xmm4 -; AVX512DQ-SLOW-NEXT: vpbroadcastq {{.*#+}} xmm6 = [6,7,4,5,0,0,8,9,6,7,4,5,0,0,8,9] -; AVX512DQ-SLOW-NEXT: vpshufb %xmm6, %xmm2, %xmm5 -; AVX512DQ-SLOW-NEXT: vmovdqa %xmm6, %xmm7 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} xmm6 = xmm4[1,1,2,2] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} xmm5 = xmm6[0],xmm5[1],xmm6[2,3],xmm5[4],xmm6[5,6],xmm5[7] -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm5, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm5 = xmm4[0],xmm2[0],xmm4[1],xmm2[1],xmm4[2],xmm2[2],xmm4[3],xmm2[3] -; AVX512DQ-SLOW-NEXT: vmovdqa %xmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512DQ-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm4[4],xmm2[4],xmm4[5],xmm2[5],xmm4[6],xmm2[6],xmm4[7],xmm2[7] -; AVX512DQ-SLOW-NEXT: vmovdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512DQ-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} xmm2 = xmm3[0,1,2,3,4,5,7,6] -; AVX512DQ-SLOW-NEXT: vmovdqa {{.*#+}} xmm0 = [0,1,2,3,4,5,4,5,6,7,10,11,8,9,10,11] -; AVX512DQ-SLOW-NEXT: vpshufb %xmm0, %xmm1, %xmm1 -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm28 = <16,18,19,19,19,19,u,u,0,1,0,1,2,3,2,3> -; AVX512DQ-SLOW-NEXT: vpermt2d %zmm2, %zmm28, %zmm1 -; AVX512DQ-SLOW-NEXT: vpbroadcastd 100(%rax), %ymm2 -; AVX512DQ-SLOW-NEXT: vpbroadcastd 104(%rax), %ymm3 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm2 -; AVX512DQ-SLOW-NEXT: vpternlogq $184, %zmm1, %zmm16, %zmm2 -; AVX512DQ-SLOW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqa 64(%rcx), %xmm1 -; AVX512DQ-SLOW-NEXT: vmovdqa 64(%rdx), %xmm2 -; AVX512DQ-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %xmm3, %xmm30 -; AVX512DQ-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3] -; AVX512DQ-SLOW-NEXT: vpshufb %xmm7, %xmm1, %xmm1 -; AVX512DQ-SLOW-NEXT: vmovdqa %xmm7, %xmm8 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,2,2] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0],xmm1[1],xmm2[2,3],xmm1[4],xmm2[5,6],xmm1[7] -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} xmm2 = xmm3[0,1,3,2,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm3 = <16,16,17,17,17,17,u,u,0,1,0,1,2,3,2,3> -; AVX512DQ-SLOW-NEXT: vpermt2d %zmm2, %zmm3, %zmm1 -; AVX512DQ-SLOW-NEXT: vmovdqa 64(%rdi), %xmm2 -; AVX512DQ-SLOW-NEXT: vmovdqa 64(%rsi), %xmm4 -; AVX512DQ-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm5 = xmm2[0],xmm4[0],xmm2[1],xmm4[1],xmm2[2],xmm4[2],xmm2[3],xmm4[3] -; AVX512DQ-SLOW-NEXT: vpshufb %xmm0, %xmm5, %xmm5 -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm5 = ymm5[0,0,1,1] -; AVX512DQ-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm6 = xmm4[4],xmm2[4],xmm4[5],xmm2[5],xmm4[6],xmm2[6],xmm4[7],xmm2[7] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %xmm6, %xmm26 -; AVX512DQ-SLOW-NEXT: vprold $16, %xmm4, %xmm4 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,2,3] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm4[2],xmm2[3,4],xmm4[5],xmm2[6,7] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,0,2,1] -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm2, %zmm5, %zmm4 -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm2 = [65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0] -; AVX512DQ-SLOW-NEXT: vpternlogq $226, %zmm1, %zmm2, %zmm4 -; AVX512DQ-SLOW-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqa 64(%r9), %xmm1 -; AVX512DQ-SLOW-NEXT: vmovdqa 64(%r8), %xmm4 -; AVX512DQ-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm5 = xmm4[4],xmm1[4],xmm4[5],xmm1[5],xmm4[6],xmm1[6],xmm4[7],xmm1[7] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %xmm5, %xmm16 -; AVX512DQ-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm4[0],xmm1[0],xmm4[1],xmm1[1],xmm4[2],xmm1[2],xmm4[3],xmm1[3] -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} xmm4 = xmm1[0,1,2,3,4,5,7,6] -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} xmm1 = xmm1[0,1,3,2,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm6 = <0,1,0,1,0,1,1,3,16,18,19,19,19,19,u,u> -; AVX512DQ-SLOW-NEXT: vpermt2d %zmm4, %zmm6, %zmm1 -; AVX512DQ-SLOW-NEXT: vpbroadcastd 64(%rax), %ymm4 -; AVX512DQ-SLOW-NEXT: vpbroadcastd 68(%rax), %ymm5 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm5, %zmm4, %zmm4 -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm9 = [65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535] -; AVX512DQ-SLOW-NEXT: vpternlogq $184, %zmm1, %zmm9, %zmm4 -; AVX512DQ-SLOW-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqa (%rcx), %xmm1 -; AVX512DQ-SLOW-NEXT: vmovdqa (%rdx), %xmm5 -; AVX512DQ-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm5[4],xmm1[4],xmm5[5],xmm1[5],xmm5[6],xmm1[6],xmm5[7],xmm1[7] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %xmm4, %xmm19 -; AVX512DQ-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm7 = xmm5[0],xmm1[0],xmm5[1],xmm1[1],xmm5[2],xmm1[2],xmm5[3],xmm1[3] -; AVX512DQ-SLOW-NEXT: vpshufb %xmm8, %xmm1, %xmm1 -; AVX512DQ-SLOW-NEXT: vmovdqa64 %xmm8, %xmm29 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} xmm5 = xmm5[1,1,2,2] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} xmm1 = xmm5[0],xmm1[1],xmm5[2,3],xmm1[4],xmm5[5,6],xmm1[7] -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} xmm5 = xmm7[0,1,3,2,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpermt2d %zmm5, %zmm3, %zmm1 -; AVX512DQ-SLOW-NEXT: vmovdqa (%rdi), %xmm3 -; AVX512DQ-SLOW-NEXT: vmovdqa (%rsi), %xmm5 -; AVX512DQ-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm7 = xmm3[0],xmm5[0],xmm3[1],xmm5[1],xmm3[2],xmm5[2],xmm3[3],xmm5[3] -; AVX512DQ-SLOW-NEXT: vpshufb %xmm0, %xmm7, %xmm7 -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm7[0,0,1,1] -; AVX512DQ-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm14 = xmm5[4],xmm3[4],xmm5[5],xmm3[5],xmm5[6],xmm3[6],xmm5[7],xmm3[7] -; AVX512DQ-SLOW-NEXT: vprold $16, %xmm5, %xmm5 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[1,1,2,3] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1],xmm5[2],xmm3[3,4],xmm5[5],xmm3[6,7] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,0,2,1] -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm3, %zmm7, %zmm3 -; AVX512DQ-SLOW-NEXT: vpternlogq $226, %zmm1, %zmm2, %zmm3 -; AVX512DQ-SLOW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqa (%r9), %xmm1 -; AVX512DQ-SLOW-NEXT: vmovdqa (%r8), %xmm2 -; AVX512DQ-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7] -; AVX512DQ-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3] -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} xmm2 = xmm1[0,1,2,3,4,5,7,6] -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} xmm1 = xmm1[0,1,3,2,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpermt2d %zmm2, %zmm6, %zmm1 -; AVX512DQ-SLOW-NEXT: vpbroadcastd (%rax), %ymm2 -; AVX512DQ-SLOW-NEXT: vpbroadcastd 4(%rax), %ymm3 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm2 -; AVX512DQ-SLOW-NEXT: vpternlogq $184, %zmm1, %zmm9, %zmm2 -; AVX512DQ-SLOW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm23, %ymm7 -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} ymm1 = ymm7[1,2,3,3,4,5,6,7,9,10,11,11,12,13,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,0,2,1,4,4,6,5] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm25[1,1,1,1,5,5,5,5] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0,1],ymm2[2],ymm1[3,4],ymm2[5],ymm1[6,7,8,9],ymm2[10],ymm1[11,12],ymm2[13],ymm1[14,15] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm1, %ymm20 -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} ymm1 = ymm7[0,1,2,3,5,4,6,7,8,9,10,11,13,12,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm25[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0],ymm1[1],ymm2[2,3],ymm1[4],ymm2[5,6,7,8],ymm1[9],ymm2[10,11],ymm1[12],ymm2[13,14,15] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm1, %ymm27 -; AVX512DQ-SLOW-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm3 # 32-byte Reload -; AVX512DQ-SLOW-NEXT: vprold $16, %ymm3, %ymm1 -; AVX512DQ-SLOW-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm5 # 32-byte Reload -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm5[1,2,2,3,5,6,6,7] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0,1],ymm1[2],ymm2[3,4],ymm1[5],ymm2[6,7,8,9],ymm1[10],ymm2[11,12],ymm1[13],ymm2[14,15] -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} ymm2 = ymm3[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[0,0,0,0,4,4,4,4] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm6 = ymm5[0,0,2,1,4,4,6,5] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm2 = ymm2[0,1,2],ymm6[3],ymm2[4,5],ymm6[6],ymm2[7,8,9,10],ymm6[11],ymm2[12,13],ymm6[14],ymm2[15] -; AVX512DQ-SLOW-NEXT: vpermt2q %zmm1, %zmm10, %zmm2 -; AVX512DQ-SLOW-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm8 # 32-byte Reload -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} ymm1 = ymm8[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,0,0,0,4,4,4,4] -; AVX512DQ-SLOW-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm10 # 32-byte Reload -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm6 = ymm10[0,1,1,3,4,5,5,7] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm6[0,1],ymm1[2],ymm6[3,4],ymm1[5],ymm6[6,7,8,9],ymm1[10],ymm6[11,12],ymm1[13],ymm6[14,15] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm1, %ymm24 -; AVX512DQ-SLOW-NEXT: vpshufb %ymm13, %ymm8, %ymm1 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm6 = ymm10[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0,1],ymm6[2],ymm1[3,4],ymm6[5],ymm1[6,7,8,9],ymm6[10],ymm1[11,12],ymm6[13],ymm1[14,15] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm1, %ymm21 -; AVX512DQ-SLOW-NEXT: vpermd (%rax), %zmm11, %zmm1 -; AVX512DQ-SLOW-NEXT: vpternlogq $184, %zmm2, %zmm17, %zmm1 -; AVX512DQ-SLOW-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm10[3,3,3,3,7,7,7,7] -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} ymm2 = ymm8[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0],ymm2[1],ymm1[2,3],ymm2[4],ymm1[5,6,7,8],ymm2[9],ymm1[10,11],ymm2[12],ymm1[13,14,15] -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm25[3,3,3,3,7,7,7,7] -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} ymm2 = ymm7[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[2,2,2,2,6,6,6,6] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0,1,2],ymm2[3],ymm1[4,5],ymm2[6],ymm1[7,8,9,10],ymm2[11],ymm1[12,13],ymm2[14],ymm1[15] -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm5[3,3,3,3,7,7,7,7] -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} ymm2 = ymm3[0,1,2,3,5,6,7,7,8,9,10,11,13,14,15,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[2,2,2,3,6,6,6,7] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0,1],ymm1[2],ymm2[3,4],ymm1[5],ymm2[6,7,8,9],ymm1[10],ymm2[11,12],ymm1[13],ymm2[14,15] -; AVX512DQ-SLOW-NEXT: vmovdqa 32(%r9), %xmm7 -; AVX512DQ-SLOW-NEXT: vmovdqa 32(%r8), %xmm2 -; AVX512DQ-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm6 = xmm2[0],xmm7[0],xmm2[1],xmm7[1],xmm2[2],xmm7[2],xmm2[3],xmm7[3] -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} xmm11 = xmm6[0,1,3,2,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpermt2d %zmm11, %zmm12, %zmm1 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm11 = ymm22[2,3,3,3,6,7,7,7] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm11 = ymm11[2,1,3,2] -; AVX512DQ-SLOW-NEXT: vpbroadcastd 32(%rax), %ymm12 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm12, %zmm11, %zmm25 -; AVX512DQ-SLOW-NEXT: vpternlogq $184, %zmm1, %zmm15, %zmm25 -; AVX512DQ-SLOW-NEXT: vmovdqa 32(%rdi), %xmm1 -; AVX512DQ-SLOW-NEXT: vmovdqa 32(%rsi), %xmm12 -; AVX512DQ-SLOW-NEXT: vprold $16, %xmm12, %xmm15 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} xmm13 = xmm1[1,1,2,3] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} xmm3 = xmm13[0,1],xmm15[2],xmm13[3,4],xmm15[5],xmm13[6,7] -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm3, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm13 = xmm1[0],xmm12[0],xmm1[1],xmm12[1],xmm1[2],xmm12[2],xmm1[3],xmm12[3] -; AVX512DQ-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm12[4],xmm1[4],xmm12[5],xmm1[5],xmm12[6],xmm1[6],xmm12[7],xmm1[7] -; AVX512DQ-SLOW-NEXT: vmovdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512DQ-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm2[4],xmm7[4],xmm2[5],xmm7[5],xmm2[6],xmm7[6],xmm2[7],xmm7[7] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %xmm16, %xmm1 -; AVX512DQ-SLOW-NEXT: vpshufb %xmm0, %xmm1, %xmm1 -; AVX512DQ-SLOW-NEXT: vpshufb %xmm0, %xmm4, %xmm3 -; AVX512DQ-SLOW-NEXT: vmovdqa64 %xmm18, %xmm4 -; AVX512DQ-SLOW-NEXT: vpshufb %xmm0, %xmm4, %xmm4 -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm4, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vpshufb %xmm0, %xmm13, %xmm4 -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm4, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vpshufb %xmm0, %xmm2, %xmm2 -; AVX512DQ-SLOW-NEXT: vpermq $234, {{[-0-9]+}}(%r{{[sb]}}p), %ymm23 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # ymm23 = mem[2,2,2,3] -; AVX512DQ-SLOW-NEXT: vpermq $232, {{[-0-9]+}}(%r{{[sb]}}p), %ymm22 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # ymm22 = mem[0,2,2,3] -; AVX512DQ-SLOW-NEXT: vpermq $232, {{[-0-9]+}}(%r{{[sb]}}p), %ymm18 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # ymm18 = mem[0,2,2,3] -; AVX512DQ-SLOW-NEXT: vpermq $246, {{[-0-9]+}}(%r{{[sb]}}p), %ymm17 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # ymm17 = mem[2,1,3,3] -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} xmm0 = xmm6[0,1,2,3,4,5,7,6] -; AVX512DQ-SLOW-NEXT: vpermt2d %zmm0, %zmm28, %zmm2 -; AVX512DQ-SLOW-NEXT: vpbroadcastd 36(%rax), %ymm0 -; AVX512DQ-SLOW-NEXT: vpbroadcastd 40(%rax), %ymm6 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm6, %zmm0, %zmm28 -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm28 -; AVX512DQ-SLOW-NEXT: vmovdqa 32(%rcx), %xmm6 -; AVX512DQ-SLOW-NEXT: vmovdqa64 %xmm29, %xmm0 -; AVX512DQ-SLOW-NEXT: vpshufb %xmm0, %xmm6, %xmm2 -; AVX512DQ-SLOW-NEXT: vmovdqa 32(%rdx), %xmm0 -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} xmm7 = xmm0[1,1,2,2] -; AVX512DQ-SLOW-NEXT: vpblendw {{.*#+}} xmm2 = xmm7[0],xmm2[1],xmm7[2,3],xmm2[4],xmm7[5,6],xmm2[7] -; AVX512DQ-SLOW-NEXT: vmovdqu %ymm2, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm0[0],xmm6[0],xmm0[1],xmm6[1],xmm0[2],xmm6[2],xmm0[3],xmm6[3] -; AVX512DQ-SLOW-NEXT: vmovdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512DQ-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm6[4],xmm0[5],xmm6[5],xmm0[6],xmm6[6],xmm0[7],xmm6[7] -; AVX512DQ-SLOW-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512DQ-SLOW-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm4 # 32-byte Reload -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm4[0,1,2,3,5,5,7,6,8,9,10,11,13,13,15,14] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm29 = ymm0[3,3,3,3] -; AVX512DQ-SLOW-NEXT: vpshufd $233, {{[-0-9]+}}(%r{{[sb]}}p), %ymm2 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # ymm2 = mem[1,2,2,3,5,6,6,7] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm10 = ymm4[2,1,2,3,6,5,6,7] -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} ymm10 = ymm10[0,0,3,3,4,5,6,7,8,8,11,11,12,13,14,15] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm0 = ymm10[2,2,2,2] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,0,1,1] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %xmm30, %xmm4 -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} xmm10 = xmm4[0,2,3,3,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm10 = ymm10[0,0,2,1] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %xmm26, %xmm4 -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} xmm8 = xmm4[2,1,2,3,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} xmm8 = xmm8[0,1,2,3,4,5,5,4] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm8 = ymm8[0,0,1,3] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,0,1,1] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %xmm19, %xmm4 -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} xmm15 = xmm4[0,2,3,3,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm15 = ymm15[0,0,2,1] -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} xmm12 = xmm14[2,1,2,3,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} xmm12 = xmm12[0,1,2,3,4,5,5,4] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm12 = ymm12[0,0,1,3] -; AVX512DQ-SLOW-NEXT: vpermq $182, {{[-0-9]+}}(%r{{[sb]}}p), %ymm4 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # ymm4 = mem[2,1,3,2] -; AVX512DQ-SLOW-NEXT: vpermq $234, {{[-0-9]+}}(%r{{[sb]}}p), %ymm5 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # ymm5 = mem[2,2,2,3] -; AVX512DQ-SLOW-NEXT: vpermq $250, {{[-0-9]+}}(%r{{[sb]}}p), %ymm6 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # ymm6 = mem[2,2,3,3] -; AVX512DQ-SLOW-NEXT: vpermpd $234, {{[-0-9]+}}(%r{{[sb]}}p), %ymm7 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # ymm7 = mem[2,2,2,3] -; AVX512DQ-SLOW-NEXT: vmovups %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm31 = ymm31[0,2,2,3] -; AVX512DQ-SLOW-NEXT: vpermq $232, {{[-0-9]+}}(%r{{[sb]}}p), %ymm30 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # ymm30 = mem[0,2,2,3] -; AVX512DQ-SLOW-NEXT: vpermq $246, {{[-0-9]+}}(%r{{[sb]}}p), %ymm26 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # ymm26 = mem[2,1,3,3] -; AVX512DQ-SLOW-NEXT: vpermq $234, {{[-0-9]+}}(%r{{[sb]}}p), %ymm19 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # ymm19 = mem[2,2,2,3] -; AVX512DQ-SLOW-NEXT: vpermq $232, {{[-0-9]+}}(%r{{[sb]}}p), %ymm11 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # ymm11 = mem[0,2,2,3] -; AVX512DQ-SLOW-NEXT: vpermq $182, {{[-0-9]+}}(%r{{[sb]}}p), %ymm16 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # ymm16 = mem[2,1,3,2] -; AVX512DQ-SLOW-NEXT: vpermq $234, {{[-0-9]+}}(%r{{[sb]}}p), %ymm7 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # ymm7 = mem[2,2,2,3] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm20 = ymm20[2,2,2,3] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm13 = ymm27[0,2,2,3] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm14 = ymm24[2,1,3,2] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm9 = ymm21[2,2,2,3] -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm22, %zmm23, %zmm22 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm17, %zmm18, %zmm23 -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm27 = [65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535] -; AVX512DQ-SLOW-NEXT: vpternlogq $184, %zmm22, %zmm27, %zmm23 -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm2 = ymm2[2,1,3,2] -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm17 = [65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535] -; AVX512DQ-SLOW-NEXT: vpternlogq $184, %ymm23, %ymm17, %ymm2 -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm17 = [65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535] -; AVX512DQ-SLOW-NEXT: vpternlogq $184, %ymm2, %ymm17, %ymm0 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm2 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm1[0,1,2,3],zmm2[4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpternlogq $234, {{[-0-9]+}}(%r{{[sb]}}p), %zmm17, %zmm2 # 64-byte Folded Reload -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm1 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm3 = zmm3[0,1,2,3],zmm1[4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpternlogq $234, {{[-0-9]+}}(%r{{[sb]}}p), %zmm17, %zmm3 # 64-byte Folded Reload -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm10, %zmm10 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm8, %zmm8 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm22 = [65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535] -; AVX512DQ-SLOW-NEXT: vpternlogq $226, %zmm10, %zmm22, %zmm8 -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm17 = [0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535] -; AVX512DQ-SLOW-NEXT: vpternlogq $226, %zmm2, %zmm17, %zmm8 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm15, %zmm2 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm12, %zmm10 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: vpternlogq $226, %zmm2, %zmm22, %zmm10 -; AVX512DQ-SLOW-NEXT: vpternlogq $226, %zmm3, %zmm17, %zmm10 -; AVX512DQ-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm4, %zmm1, %zmm2 -; AVX512DQ-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm5, %zmm1, %zmm18 -; AVX512DQ-SLOW-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm18 -; AVX512DQ-SLOW-NEXT: vextracti64x4 $1, %zmm23, %ymm2 -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm1 = [65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535] -; AVX512DQ-SLOW-NEXT: vpternlogd $226, 124(%r8){1to8}, %ymm1, %ymm2 -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm3 = [0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535] -; AVX512DQ-SLOW-NEXT: vpternlogq $184, %ymm2, %ymm3, %ymm29 -; AVX512DQ-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm21 # 64-byte Reload -; AVX512DQ-SLOW-NEXT: vpternlogq $248, {{[-0-9]+}}(%r{{[sb]}}p), %zmm3, %zmm21 # 64-byte Folded Reload -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm6, %zmm0, %zmm2 -; AVX512DQ-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQ-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm24 = zmm1[0,1,2,3],zmm2[4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpternlogq $234, {{[-0-9]+}}(%r{{[sb]}}p), %zmm3, %zmm24 # 64-byte Folded Reload -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm29, %zmm0, %zmm2 -; AVX512DQ-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm2[4,5,6,7] -; AVX512DQ-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm23 # 64-byte Reload -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm1 = [65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0] -; AVX512DQ-SLOW-NEXT: vpternlogq $184, %zmm0, %zmm1, %zmm23 -; AVX512DQ-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm29 # 64-byte Reload -; AVX512DQ-SLOW-NEXT: vpternlogq $184, {{[-0-9]+}}(%r{{[sb]}}p), %zmm1, %zmm29 # 64-byte Folded Reload -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm0 = [65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535] -; AVX512DQ-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm17 # 64-byte Reload -; AVX512DQ-SLOW-NEXT: vpternlogq $184, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm17 # 64-byte Folded Reload -; AVX512DQ-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload -; AVX512DQ-SLOW-NEXT: vpternlogq $184, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm6 # 64-byte Folded Reload -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm11, %zmm19, %zmm0 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm7, %zmm16, %zmm2 -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm3 = [0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535] -; AVX512DQ-SLOW-NEXT: vpternlogq $226, %zmm0, %zmm3, %zmm2 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm13, %zmm20, %zmm0 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm9, %zmm14, %zmm4 -; AVX512DQ-SLOW-NEXT: vpternlogq $226, %zmm0, %zmm3, %zmm4 -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm0 = [65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0] -; AVX512DQ-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload -; AVX512DQ-SLOW-NEXT: vpternlogq $184, %zmm2, %zmm0, %zmm19 -; AVX512DQ-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm20 # 64-byte Reload -; AVX512DQ-SLOW-NEXT: vpternlogq $184, %zmm4, %zmm0, %zmm20 -; AVX512DQ-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm31, %zmm0, %zmm0 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm26, %zmm30, %zmm2 -; AVX512DQ-SLOW-NEXT: vpternlogq $184, %zmm0, %zmm27, %zmm2 -; AVX512DQ-SLOW-NEXT: vpermq $232, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # ymm0 = mem[0,2,2,3] -; AVX512DQ-SLOW-NEXT: vpshuflw $180, {{[-0-9]+}}(%r{{[sb]}}p), %xmm3 # 16-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # xmm3 = mem[0,1,3,2,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[0,0,1,1] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,1,1,3] -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm0 -; AVX512DQ-SLOW-NEXT: vpermq $246, {{[-0-9]+}}(%r{{[sb]}}p), %ymm3 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # ymm3 = mem[2,1,3,3] -; AVX512DQ-SLOW-NEXT: vpermq $80, {{[-0-9]+}}(%r{{[sb]}}p), %ymm4 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # ymm4 = mem[0,0,1,1] -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm4, %zmm3, %zmm3 -; AVX512DQ-SLOW-NEXT: vpermq $96, {{[-0-9]+}}(%r{{[sb]}}p), %ymm4 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # ymm4 = mem[0,0,2,1] -; AVX512DQ-SLOW-NEXT: vpshuflw $230, {{[-0-9]+}}(%r{{[sb]}}p), %xmm5 # 16-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # xmm5 = mem[2,1,2,3,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} xmm5 = xmm5[0,1,2,3,4,5,5,4] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm5 = ymm5[0,0,1,3] -; AVX512DQ-SLOW-NEXT: vpermq $80, {{[-0-9]+}}(%r{{[sb]}}p), %ymm26 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # ymm26 = mem[0,0,1,1] -; AVX512DQ-SLOW-NEXT: vpshuflw $248, {{[-0-9]+}}(%r{{[sb]}}p), %xmm7 # 16-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # xmm7 = mem[0,2,3,3,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm7[0,0,2,1] -; AVX512DQ-SLOW-NEXT: vpermq $232, {{[-0-9]+}}(%r{{[sb]}}p), %ymm9 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # ymm9 = mem[0,2,2,3] -; AVX512DQ-SLOW-NEXT: vpshuflw $180, {{[-0-9]+}}(%r{{[sb]}}p), %xmm11 # 16-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # xmm11 = mem[0,1,3,2,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} xmm11 = xmm11[0,0,1,1] -; AVX512DQ-SLOW-NEXT: vpermq $246, {{[-0-9]+}}(%r{{[sb]}}p), %ymm12 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # ymm12 = mem[2,1,3,3] -; AVX512DQ-SLOW-NEXT: vpermq $80, {{[-0-9]+}}(%r{{[sb]}}p), %ymm13 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # ymm13 = mem[0,0,1,1] -; AVX512DQ-SLOW-NEXT: vpermq $96, {{[-0-9]+}}(%r{{[sb]}}p), %ymm14 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # ymm14 = mem[0,0,2,1] -; AVX512DQ-SLOW-NEXT: vpshuflw $230, {{[-0-9]+}}(%r{{[sb]}}p), %xmm15 # 16-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # xmm15 = mem[2,1,2,3,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} xmm15 = xmm15[0,1,2,3,4,5,5,4] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm15 = ymm15[0,0,1,3] -; AVX512DQ-SLOW-NEXT: vpermq $80, {{[-0-9]+}}(%r{{[sb]}}p), %ymm16 # 32-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # ymm16 = mem[0,0,1,1] -; AVX512DQ-SLOW-NEXT: vpshuflw $248, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload -; AVX512DQ-SLOW-NEXT: # xmm1 = mem[0,2,3,3,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,0,2,1] -; AVX512DQ-SLOW-NEXT: vpternlogq $226, %zmm0, %zmm27, %zmm3 -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm0 = ymm11[0,1,1,3] -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm0, %zmm9, %zmm0 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm13, %zmm12, %zmm9 -; AVX512DQ-SLOW-NEXT: vpternlogq $226, %zmm0, %zmm27, %zmm9 -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm0 = [0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535] -; AVX512DQ-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512DQ-SLOW-NEXT: vpternlogq $184, %zmm3, %zmm0, %zmm11 -; AVX512DQ-SLOW-NEXT: vpternlogq $184, %zmm9, %zmm0, %zmm25 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm5, %zmm4, %zmm0 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm7, %zmm26, %zmm3 -; AVX512DQ-SLOW-NEXT: vpternlogq $226, %zmm0, %zmm22, %zmm3 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm15, %zmm14, %zmm0 -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm1, %zmm16, %zmm1 -; AVX512DQ-SLOW-NEXT: vpternlogq $226, %zmm0, %zmm22, %zmm1 -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm0 = [65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0] -; AVX512DQ-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQ-SLOW-NEXT: vpternlogq $184, %zmm3, %zmm0, %zmm4 -; AVX512DQ-SLOW-NEXT: vpternlogq $184, %zmm1, %zmm0, %zmm28 -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm18, %zmm24 -; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm29, %zmm0 -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm0 -; AVX512DQ-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm24, 320(%rax) -; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm28, 256(%rax) -; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm25, 192(%rax) -; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm20, 128(%rax) -; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm10, 64(%rax) -; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm6, (%rax) -; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm17, 448(%rax) -; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm4, 704(%rax) -; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm11, 640(%rax) -; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm19, 576(%rax) -; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm8, 512(%rax) -; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm0, 384(%rax) -; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm21, 768(%rax) -; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm23, 832(%rax) -; AVX512DQ-SLOW-NEXT: addq $2200, %rsp # imm = 0x898 -; AVX512DQ-SLOW-NEXT: vzeroupper -; AVX512DQ-SLOW-NEXT: retq +; AVX512F-SLOW-LABEL: store_i16_stride7_vf64: +; AVX512F-SLOW: # %bb.0: +; AVX512F-SLOW-NEXT: subq $2200, %rsp # imm = 0x898 +; AVX512F-SLOW-NEXT: vmovdqa 96(%rcx), %ymm2 +; AVX512F-SLOW-NEXT: vmovdqa 96(%rdx), %ymm9 +; AVX512F-SLOW-NEXT: vmovdqa 96(%rdi), %ymm7 +; AVX512F-SLOW-NEXT: vmovdqa 96(%rsi), %ymm8 +; AVX512F-SLOW-NEXT: vmovdqa {{.*#+}} ymm0 = [128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128,128,128,128,128] +; AVX512F-SLOW-NEXT: vpshufb %ymm0, %ymm2, %ymm1 +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm2, %ymm19 +; AVX512F-SLOW-NEXT: vmovdqa {{.*#+}} ymm11 = +; AVX512F-SLOW-NEXT: vpshufb %ymm11, %ymm9, %ymm2 +; AVX512F-SLOW-NEXT: vporq %ymm1, %ymm2, %ymm16 +; AVX512F-SLOW-NEXT: vmovdqa {{.*#+}} ymm12 = [128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128,128,128,128,128,128,128,128,128] +; AVX512F-SLOW-NEXT: vpshufb %ymm12, %ymm8, %ymm1 +; AVX512F-SLOW-NEXT: vmovdqa {{.*#+}} ymm13 = <12,13,14,15,128,128,u,u,u,u,u,u,u,u,u,u,16,17,128,128,u,u,u,u,u,u,u,u,16,17,18,19> +; AVX512F-SLOW-NEXT: vpshufb %ymm13, %ymm7, %ymm2 +; AVX512F-SLOW-NEXT: vporq %ymm1, %ymm2, %ymm17 +; AVX512F-SLOW-NEXT: vmovdqa {{.*#+}} ymm3 = [128,128,128,128,128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128] +; AVX512F-SLOW-NEXT: vmovdqa 64(%r9), %ymm2 +; AVX512F-SLOW-NEXT: vpshufb %ymm3, %ymm2, %ymm1 +; AVX512F-SLOW-NEXT: vmovdqa %ymm3, %ymm10 +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm2, %ymm20 +; AVX512F-SLOW-NEXT: vmovdqa 64(%r8), %ymm3 +; AVX512F-SLOW-NEXT: vmovdqa {{.*#+}} ymm15 = +; AVX512F-SLOW-NEXT: vpshufb %ymm15, %ymm3, %ymm2 +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm3, %ymm24 +; AVX512F-SLOW-NEXT: vpor %ymm1, %ymm2, %ymm1 +; AVX512F-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vmovdqa 64(%rcx), %ymm2 +; AVX512F-SLOW-NEXT: vpshufb %ymm0, %ymm2, %ymm1 +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm2, %ymm18 +; AVX512F-SLOW-NEXT: vmovdqa 64(%rdx), %ymm6 +; AVX512F-SLOW-NEXT: vpshufb %ymm11, %ymm6, %ymm2 +; AVX512F-SLOW-NEXT: vpor %ymm1, %ymm2, %ymm1 +; AVX512F-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vmovdqa 64(%rsi), %ymm5 +; AVX512F-SLOW-NEXT: vpshufb %ymm12, %ymm5, %ymm1 +; AVX512F-SLOW-NEXT: vmovdqa 64(%rdi), %ymm4 +; AVX512F-SLOW-NEXT: vpshufb %ymm13, %ymm4, %ymm2 +; AVX512F-SLOW-NEXT: vpor %ymm1, %ymm2, %ymm1 +; AVX512F-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vmovdqa (%r9), %ymm1 +; AVX512F-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vpshufb %ymm10, %ymm1, %ymm1 +; AVX512F-SLOW-NEXT: vmovdqa %ymm10, %ymm3 +; AVX512F-SLOW-NEXT: vmovdqa (%r8), %ymm2 +; AVX512F-SLOW-NEXT: vmovdqu %ymm2, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vpshufb %ymm15, %ymm2, %ymm2 +; AVX512F-SLOW-NEXT: vpor %ymm1, %ymm2, %ymm1 +; AVX512F-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vmovdqa (%rcx), %ymm1 +; AVX512F-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vpshufb %ymm0, %ymm1, %ymm1 +; AVX512F-SLOW-NEXT: vmovdqa (%rdx), %ymm2 +; AVX512F-SLOW-NEXT: vmovdqu %ymm2, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vpshufb %ymm11, %ymm2, %ymm2 +; AVX512F-SLOW-NEXT: vpor %ymm1, %ymm2, %ymm1 +; AVX512F-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vmovdqa (%rsi), %ymm2 +; AVX512F-SLOW-NEXT: vpshufb %ymm12, %ymm2, %ymm1 +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm2, %ymm23 +; AVX512F-SLOW-NEXT: vmovdqa (%rdi), %ymm10 +; AVX512F-SLOW-NEXT: vpshufb %ymm13, %ymm10, %ymm2 +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm10, %ymm25 +; AVX512F-SLOW-NEXT: vpor %ymm1, %ymm2, %ymm1 +; AVX512F-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vmovdqa 32(%rcx), %ymm2 +; AVX512F-SLOW-NEXT: vpshufb %ymm0, %ymm2, %ymm0 +; AVX512F-SLOW-NEXT: vmovdqa 32(%rdx), %ymm1 +; AVX512F-SLOW-NEXT: vpshufb %ymm11, %ymm1, %ymm11 +; AVX512F-SLOW-NEXT: vpor %ymm0, %ymm11, %ymm0 +; AVX512F-SLOW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-SLOW-NEXT: vmovdqa 32(%rsi), %ymm0 +; AVX512F-SLOW-NEXT: vpshufb %ymm12, %ymm0, %ymm12 +; AVX512F-SLOW-NEXT: vmovdqa 32(%rdi), %ymm11 +; AVX512F-SLOW-NEXT: vpshufb %ymm13, %ymm11, %ymm13 +; AVX512F-SLOW-NEXT: vpor %ymm12, %ymm13, %ymm10 +; AVX512F-SLOW-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-SLOW-NEXT: vmovdqa 32(%r8), %ymm13 +; AVX512F-SLOW-NEXT: vpshufb %ymm15, %ymm13, %ymm12 +; AVX512F-SLOW-NEXT: vmovdqa 32(%r9), %ymm15 +; AVX512F-SLOW-NEXT: vpshufb %ymm3, %ymm15, %ymm14 +; AVX512F-SLOW-NEXT: vpor %ymm14, %ymm12, %ymm10 +; AVX512F-SLOW-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-SLOW-NEXT: vprold $16, %ymm15, %ymm12 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm14 = ymm13[1,2,2,3,5,6,6,7] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm12 = ymm14[0,1],ymm12[2],ymm14[3,4],ymm12[5],ymm14[6,7,8,9],ymm12[10],ymm14[11,12],ymm12[13],ymm14[14,15] +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} ymm14 = ymm15[0,1,2,3,5,6,7,7,8,9,10,11,13,14,15,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm14 = ymm14[2,2,2,3,6,6,6,7] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm10 = ymm13[3,3,3,3,7,7,7,7] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm10 = ymm14[0,1],ymm10[2],ymm14[3,4],ymm10[5],ymm14[6,7,8,9],ymm10[10],ymm14[11,12],ymm10[13],ymm14[14,15] +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm14 = [2,1,3,2,10,10,10,11] +; AVX512F-SLOW-NEXT: vpermi2q %zmm10, %zmm12, %zmm14 +; AVX512F-SLOW-NEXT: vmovdqu64 %zmm14, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-SLOW-NEXT: vbroadcasti128 {{.*#+}} ymm12 = [22,23,26,27,0,0,24,25,26,27,0,0,26,27,26,27,22,23,26,27,0,0,24,25,26,27,0,0,26,27,26,27] +; AVX512F-SLOW-NEXT: # ymm12 = mem[0,1,0,1] +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm19, %ymm14 +; AVX512F-SLOW-NEXT: vpshufb %ymm12, %ymm14, %ymm10 +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm12, %ymm19 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm9[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm10 = ymm10[0,1],ymm12[2],ymm10[3,4],ymm12[5],ymm10[6,7,8,9],ymm12[10],ymm10[11,12],ymm12[13],ymm10[14,15] +; AVX512F-SLOW-NEXT: vmovdqu %ymm10, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} ymm10 = ymm14[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm10 = ymm10[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm9[3,3,3,3,7,7,7,7] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm10 = ymm12[0],ymm10[1],ymm12[2,3],ymm10[4],ymm12[5,6,7,8],ymm10[9],ymm12[10,11],ymm10[12],ymm12[13,14,15] +; AVX512F-SLOW-NEXT: vmovdqu %ymm10, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} ymm10 = ymm8[0,1,2,3,5,4,6,7,8,9,10,11,13,12,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm10 = ymm10[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm7[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm10 = ymm12[0],ymm10[1],ymm12[2,3],ymm10[4],ymm12[5,6,7,8],ymm10[9],ymm12[10,11],ymm10[12],ymm12[13,14,15] +; AVX512F-SLOW-NEXT: vmovdqu %ymm10, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} ymm10 = ymm8[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm10 = ymm10[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm7[3,3,3,3,7,7,7,7] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm10 = ymm12[0,1,2],ymm10[3],ymm12[4,5],ymm10[6],ymm12[7,8,9,10],ymm10[11],ymm12[12,13],ymm10[14],ymm12[15] +; AVX512F-SLOW-NEXT: vmovdqu %ymm10, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm9 = ymm9[0,1,1,3,4,5,5,7] +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} ymm10 = ymm14[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm10 = ymm10[0,0,0,0,4,4,4,4] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm9 = ymm9[0,1],ymm10[2],ymm9[3,4],ymm10[5],ymm9[6,7,8,9],ymm10[10],ymm9[11,12],ymm10[13],ymm9[14,15] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm9 = ymm9[2,1,3,2] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm7 = ymm7[1,1,1,1,5,5,5,5] +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} ymm8 = ymm8[1,2,3,3,4,5,6,7,9,10,11,11,12,13,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm8 = ymm8[0,0,2,1,4,4,6,5] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm7 = ymm8[0,1],ymm7[2],ymm8[3,4],ymm7[5],ymm8[6,7,8,9],ymm7[10],ymm8[11,12],ymm7[13],ymm8[14,15] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm7[2,2,2,3] +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm9, %zmm16, %zmm8 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm7, %zmm17, %zmm7 +; AVX512F-SLOW-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm8, %zmm7 +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm17 = [65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535] +; AVX512F-SLOW-NEXT: vmovdqa 96(%r8), %ymm12 +; AVX512F-SLOW-NEXT: vmovdqu %ymm12, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm8 = ymm12[u,u],zero,zero,zero,zero,zero,zero,zero,zero,ymm12[14,15,u,u,u,u],zero,zero,zero,zero,zero,zero,zero,zero,ymm12[16,17,u,u,u,u],zero,zero +; AVX512F-SLOW-NEXT: vpternlogq $248, %ymm17, %ymm7, %ymm8 +; AVX512F-SLOW-NEXT: vmovdqa 96(%r9), %ymm14 +; AVX512F-SLOW-NEXT: vmovdqu %ymm14, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vpshufb %ymm3, %ymm14, %ymm9 +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm10 = [65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535] +; AVX512F-SLOW-NEXT: vpternlogq $248, %ymm10, %ymm8, %ymm9 +; AVX512F-SLOW-NEXT: vextracti64x4 $1, %zmm7, %ymm7 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm8 = ymm12[0,0,2,1,4,4,6,5] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm8 = ymm8[2,1,3,3] +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm10 = [65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0] +; AVX512F-SLOW-NEXT: vpternlogq $184, %ymm7, %ymm10, %ymm8 +; AVX512F-SLOW-NEXT: vprold $16, %ymm14, %ymm7 +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm7[2,2,2,2] +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm10 = [65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535] +; AVX512F-SLOW-NEXT: vpternlogq $184, %ymm8, %ymm10, %ymm7 +; AVX512F-SLOW-NEXT: vmovdqa64 %zmm10, %zmm16 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm7, %zmm0, %zmm7 +; AVX512F-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm7 = zmm9[0,1,2,3],zmm7[4,5,6,7] +; AVX512F-SLOW-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512F-SLOW-NEXT: vbroadcasti64x4 {{.*#+}} zmm8 = [6,5,0,0,7,6,0,7,6,5,0,0,7,6,0,7] +; AVX512F-SLOW-NEXT: # zmm8 = mem[0,1,2,3,0,1,2,3] +; AVX512F-SLOW-NEXT: vmovdqa 96(%rax), %ymm7 +; AVX512F-SLOW-NEXT: vpermd %zmm7, %zmm8, %zmm9 +; AVX512F-SLOW-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm9 = ymm7[0,1,1,3,4,5,5,7] +; AVX512F-SLOW-NEXT: vmovdqa {{.*#+}} ymm10 = [12,13,128,128,128,128,128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128] +; AVX512F-SLOW-NEXT: vpshufb %ymm10, %ymm7, %ymm7 +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm9 = ymm9[0,2,2,3] +; AVX512F-SLOW-NEXT: vpandnq %ymm9, %ymm17, %ymm9 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm9, %zmm7, %zmm7 +; AVX512F-SLOW-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm14 = [65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535] +; AVX512F-SLOW-NEXT: vpbroadcastd 72(%rax), %ymm7 +; AVX512F-SLOW-NEXT: vpandn %ymm7, %ymm14, %ymm9 +; AVX512F-SLOW-NEXT: vmovdqa 64(%rax), %ymm7 +; AVX512F-SLOW-NEXT: vpshufb %ymm10, %ymm7, %ymm12 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm12, %zmm9, %zmm9 +; AVX512F-SLOW-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-SLOW-NEXT: vpbroadcastd 8(%rax), %ymm9 +; AVX512F-SLOW-NEXT: vpandn %ymm9, %ymm14, %ymm9 +; AVX512F-SLOW-NEXT: vmovdqa (%rax), %ymm14 +; AVX512F-SLOW-NEXT: vpshufb %ymm10, %ymm14, %ymm12 +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm14, %ymm22 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm12, %zmm9, %zmm9 +; AVX512F-SLOW-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} ymm9 = ymm2[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm9 = ymm9[0,0,0,0,4,4,4,4] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm1[0,1,1,3,4,5,5,7] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm9 = ymm12[0,1],ymm9[2],ymm12[3,4],ymm9[5],ymm12[6,7,8,9],ymm9[10],ymm12[11,12],ymm9[13],ymm12[14,15] +; AVX512F-SLOW-NEXT: vmovdqu %ymm9, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} ymm9 = ymm0[1,2,3,3,4,5,6,7,9,10,11,11,12,13,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm9 = ymm9[0,0,2,1,4,4,6,5] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm11[1,1,1,1,5,5,5,5] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm9 = ymm9[0,1],ymm12[2],ymm9[3,4],ymm12[5],ymm9[6,7,8,9],ymm12[10],ymm9[11,12],ymm12[13],ymm9[14,15] +; AVX512F-SLOW-NEXT: vmovdqu %ymm9, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vmovdqa 32(%rax), %ymm9 +; AVX512F-SLOW-NEXT: vpshufb %ymm10, %ymm9, %ymm10 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm9[0,1,1,3,4,5,5,7] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm12 = ymm12[0,2,2,3] +; AVX512F-SLOW-NEXT: vpandnq %ymm12, %ymm17, %ymm12 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm12, %zmm10, %zmm10 +; AVX512F-SLOW-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm10 = ymm13[0,0,2,1,4,4,6,5] +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} ymm12 = ymm15[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm12[0,0,0,0,4,4,4,4] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm10 = ymm12[0,1,2],ymm10[3],ymm12[4,5],ymm10[6],ymm12[7,8,9,10],ymm10[11],ymm12[12,13],ymm10[14],ymm12[15] +; AVX512F-SLOW-NEXT: vmovdqu %ymm10, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm19, %ymm13 +; AVX512F-SLOW-NEXT: vpshufb %ymm13, %ymm2, %ymm10 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm12 = ymm1[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm10 = ymm10[0,1],ymm12[2],ymm10[3,4],ymm12[5],ymm10[6,7,8,9],ymm12[10],ymm10[11,12],ymm12[13],ymm10[14,15] +; AVX512F-SLOW-NEXT: vmovdqu %ymm10, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[3,3,3,3,7,7,7,7] +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} ymm2 = ymm2[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0],ymm2[1],ymm1[2,3],ymm2[4],ymm1[5,6,7,8],ymm2[9],ymm1[10,11],ymm2[12],ymm1[13,14,15] +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm1, %ymm31 +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} ymm1 = ymm0[0,1,2,3,5,4,6,7,8,9,10,11,13,12,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm11[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0],ymm1[1],ymm2[2,3],ymm1[4],ymm2[5,6,7,8],ymm1[9],ymm2[10,11],ymm1[12],ymm2[13,14,15] +; AVX512F-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm11[3,3,3,3,7,7,7,7] +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3],ymm1[4,5],ymm0[6],ymm1[7,8,9,10],ymm0[11],ymm1[12,13],ymm0[14],ymm1[15] +; AVX512F-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vpermd %zmm9, %zmm8, %zmm0 +; AVX512F-SLOW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} ymm0 = ymm5[1,2,3,3,4,5,6,7,9,10,11,11,12,13,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,0,2,1,4,4,6,5] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm4[1,1,1,1,5,5,5,5] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3,4],ymm1[5],ymm0[6,7,8,9],ymm1[10],ymm0[11,12],ymm1[13],ymm0[14,15] +; AVX512F-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm5[0,1,2,3,5,4,6,7,8,9,10,11,13,12,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm4[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2,3],ymm0[4],ymm1[5,6,7,8],ymm0[9],ymm1[10,11],ymm0[12],ymm1[13,14,15] +; AVX512F-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm18, %ymm2 +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} ymm0 = ymm2[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,0,0,0,4,4,4,4] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm6[0,1,1,3,4,5,5,7] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1],ymm0[2],ymm1[3,4],ymm0[5],ymm1[6,7,8,9],ymm0[10],ymm1[11,12],ymm0[13],ymm1[14,15] +; AVX512F-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vpshufb %ymm13, %ymm2, %ymm0 +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm18, %ymm3 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm6[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3,4],ymm1[5],ymm0[6,7,8,9],ymm1[10],ymm0[11,12],ymm1[13],ymm0[14,15] +; AVX512F-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm20, %ymm8 +; AVX512F-SLOW-NEXT: vprold $16, %ymm20, %ymm0 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm24[1,2,2,3,5,6,6,7] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1],ymm0[2],ymm1[3,4],ymm0[5],ymm1[6,7,8,9],ymm0[10],ymm1[11,12],ymm0[13],ymm1[14,15] +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} ymm1 = ymm8[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,0,0,0,4,4,4,4] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm24[0,0,2,1,4,4,6,5] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0,1,2],ymm2[3],ymm1[4,5],ymm2[6],ymm1[7,8,9,10],ymm2[11],ymm1[12,13],ymm2[14],ymm1[15] +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm10 = [2,2,3,3,10,9,11,10] +; AVX512F-SLOW-NEXT: vpermt2q %zmm0, %zmm10, %zmm1 +; AVX512F-SLOW-NEXT: vbroadcasti64x4 {{.*#+}} zmm11 = [0,5,4,0,0,6,5,0,0,5,4,0,0,6,5,0] +; AVX512F-SLOW-NEXT: # zmm11 = mem[0,1,2,3,0,1,2,3] +; AVX512F-SLOW-NEXT: vpermd 64(%rax), %zmm11, %zmm0 +; AVX512F-SLOW-NEXT: vpternlogq $184, %zmm1, %zmm17, %zmm0 +; AVX512F-SLOW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm6[3,3,3,3,7,7,7,7] +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} ymm1 = ymm3[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3],ymm1[4],ymm0[5,6,7,8],ymm1[9],ymm0[10,11],ymm1[12],ymm0[13,14,15] +; AVX512F-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm4[3,3,3,3,7,7,7,7] +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} ymm1 = ymm5[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2],ymm1[3],ymm0[4,5],ymm1[6],ymm0[7,8,9,10],ymm1[11],ymm0[12,13],ymm1[14],ymm0[15] +; AVX512F-SLOW-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm24[3,3,3,3,7,7,7,7] +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} ymm1 = ymm8[0,1,2,3,5,6,7,7,8,9,10,11,13,14,15,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[2,2,2,3,6,6,6,7] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm2 = ymm1[0,1],ymm0[2],ymm1[3,4],ymm0[5],ymm1[6,7,8,9],ymm0[10],ymm1[11,12],ymm0[13],ymm1[14,15] +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm12 = [4,5,4,5,4,5,6,7,16,17,16,17,16,17,17,19] +; AVX512F-SLOW-NEXT: vmovdqa 96(%r9), %xmm0 +; AVX512F-SLOW-NEXT: vmovdqa 96(%r8), %xmm1 +; AVX512F-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} xmm4 = xmm3[0,1,3,2,4,5,6,7] +; AVX512F-SLOW-NEXT: vpermt2d %zmm4, %zmm12, %zmm2 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm4 = ymm7[2,3,3,3,6,7,7,7] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm4 = ymm4[2,1,3,2] +; AVX512F-SLOW-NEXT: vpbroadcastd 96(%rax), %ymm5 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm5, %zmm4, %zmm4 +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm5 = [65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535] +; AVX512F-SLOW-NEXT: vpternlogq $184, %zmm2, %zmm5, %zmm4 +; AVX512F-SLOW-NEXT: vmovdqa64 %zmm5, %zmm15 +; AVX512F-SLOW-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-SLOW-NEXT: vmovdqa 96(%rsi), %xmm2 +; AVX512F-SLOW-NEXT: vmovdqa 96(%rdi), %xmm4 +; AVX512F-SLOW-NEXT: vprold $16, %xmm2, %xmm5 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} xmm6 = xmm4[1,1,2,3] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} xmm5 = xmm6[0,1],xmm5[2],xmm6[3,4],xmm5[5],xmm6[6,7] +; AVX512F-SLOW-NEXT: vmovdqu %ymm5, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm5 = xmm4[0],xmm2[0],xmm4[1],xmm2[1],xmm4[2],xmm2[2],xmm4[3],xmm2[3] +; AVX512F-SLOW-NEXT: vmovdqa64 %xmm5, %xmm18 +; AVX512F-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm2[4],xmm4[4],xmm2[5],xmm4[5],xmm2[6],xmm4[6],xmm2[7],xmm4[7] +; AVX512F-SLOW-NEXT: vmovdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512F-SLOW-NEXT: vmovdqa 96(%rcx), %xmm2 +; AVX512F-SLOW-NEXT: vmovdqa 96(%rdx), %xmm4 +; AVX512F-SLOW-NEXT: vpbroadcastq {{.*#+}} xmm6 = [6,7,4,5,0,0,8,9,6,7,4,5,0,0,8,9] +; AVX512F-SLOW-NEXT: vpshufb %xmm6, %xmm2, %xmm5 +; AVX512F-SLOW-NEXT: vmovdqa %xmm6, %xmm7 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} xmm6 = xmm4[1,1,2,2] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} xmm5 = xmm6[0],xmm5[1],xmm6[2,3],xmm5[4],xmm6[5,6],xmm5[7] +; AVX512F-SLOW-NEXT: vmovdqu %ymm5, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm5 = xmm4[0],xmm2[0],xmm4[1],xmm2[1],xmm4[2],xmm2[2],xmm4[3],xmm2[3] +; AVX512F-SLOW-NEXT: vmovdqa %xmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512F-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm4[4],xmm2[4],xmm4[5],xmm2[5],xmm4[6],xmm2[6],xmm4[7],xmm2[7] +; AVX512F-SLOW-NEXT: vmovdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512F-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} xmm2 = xmm3[0,1,2,3,4,5,7,6] +; AVX512F-SLOW-NEXT: vmovdqa {{.*#+}} xmm0 = [0,1,2,3,4,5,4,5,6,7,10,11,8,9,10,11] +; AVX512F-SLOW-NEXT: vpshufb %xmm0, %xmm1, %xmm1 +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm28 = <16,18,19,19,19,19,u,u,0,1,0,1,2,3,2,3> +; AVX512F-SLOW-NEXT: vpermt2d %zmm2, %zmm28, %zmm1 +; AVX512F-SLOW-NEXT: vpbroadcastd 100(%rax), %ymm2 +; AVX512F-SLOW-NEXT: vpbroadcastd 104(%rax), %ymm3 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm2 +; AVX512F-SLOW-NEXT: vpternlogq $184, %zmm1, %zmm16, %zmm2 +; AVX512F-SLOW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-SLOW-NEXT: vmovdqa 64(%rcx), %xmm1 +; AVX512F-SLOW-NEXT: vmovdqa 64(%rdx), %xmm2 +; AVX512F-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7] +; AVX512F-SLOW-NEXT: vmovdqa64 %xmm3, %xmm30 +; AVX512F-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3] +; AVX512F-SLOW-NEXT: vpshufb %xmm7, %xmm1, %xmm1 +; AVX512F-SLOW-NEXT: vmovdqa %xmm7, %xmm8 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,2,2] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0],xmm1[1],xmm2[2,3],xmm1[4],xmm2[5,6],xmm1[7] +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} xmm2 = xmm3[0,1,3,2,4,5,6,7] +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm3 = <16,16,17,17,17,17,u,u,0,1,0,1,2,3,2,3> +; AVX512F-SLOW-NEXT: vpermt2d %zmm2, %zmm3, %zmm1 +; AVX512F-SLOW-NEXT: vmovdqa 64(%rdi), %xmm2 +; AVX512F-SLOW-NEXT: vmovdqa 64(%rsi), %xmm4 +; AVX512F-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm5 = xmm2[0],xmm4[0],xmm2[1],xmm4[1],xmm2[2],xmm4[2],xmm2[3],xmm4[3] +; AVX512F-SLOW-NEXT: vpshufb %xmm0, %xmm5, %xmm5 +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm5 = ymm5[0,0,1,1] +; AVX512F-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm6 = xmm4[4],xmm2[4],xmm4[5],xmm2[5],xmm4[6],xmm2[6],xmm4[7],xmm2[7] +; AVX512F-SLOW-NEXT: vmovdqa64 %xmm6, %xmm26 +; AVX512F-SLOW-NEXT: vprold $16, %xmm4, %xmm4 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,2,3] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm4[2],xmm2[3,4],xmm4[5],xmm2[6,7] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,0,2,1] +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm2, %zmm5, %zmm4 +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm2 = [65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0] +; AVX512F-SLOW-NEXT: vpternlogq $226, %zmm1, %zmm2, %zmm4 +; AVX512F-SLOW-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-SLOW-NEXT: vmovdqa 64(%r9), %xmm1 +; AVX512F-SLOW-NEXT: vmovdqa 64(%r8), %xmm4 +; AVX512F-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm5 = xmm4[4],xmm1[4],xmm4[5],xmm1[5],xmm4[6],xmm1[6],xmm4[7],xmm1[7] +; AVX512F-SLOW-NEXT: vmovdqa64 %xmm5, %xmm16 +; AVX512F-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm4[0],xmm1[0],xmm4[1],xmm1[1],xmm4[2],xmm1[2],xmm4[3],xmm1[3] +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} xmm4 = xmm1[0,1,2,3,4,5,7,6] +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} xmm1 = xmm1[0,1,3,2,4,5,6,7] +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm6 = <0,1,0,1,0,1,1,3,16,18,19,19,19,19,u,u> +; AVX512F-SLOW-NEXT: vpermt2d %zmm4, %zmm6, %zmm1 +; AVX512F-SLOW-NEXT: vpbroadcastd 64(%rax), %ymm4 +; AVX512F-SLOW-NEXT: vpbroadcastd 68(%rax), %ymm5 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm5, %zmm4, %zmm4 +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm9 = [65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535] +; AVX512F-SLOW-NEXT: vpternlogq $184, %zmm1, %zmm9, %zmm4 +; AVX512F-SLOW-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-SLOW-NEXT: vmovdqa (%rcx), %xmm1 +; AVX512F-SLOW-NEXT: vmovdqa (%rdx), %xmm5 +; AVX512F-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm5[4],xmm1[4],xmm5[5],xmm1[5],xmm5[6],xmm1[6],xmm5[7],xmm1[7] +; AVX512F-SLOW-NEXT: vmovdqa64 %xmm4, %xmm19 +; AVX512F-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm7 = xmm5[0],xmm1[0],xmm5[1],xmm1[1],xmm5[2],xmm1[2],xmm5[3],xmm1[3] +; AVX512F-SLOW-NEXT: vpshufb %xmm8, %xmm1, %xmm1 +; AVX512F-SLOW-NEXT: vmovdqa64 %xmm8, %xmm29 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} xmm5 = xmm5[1,1,2,2] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} xmm1 = xmm5[0],xmm1[1],xmm5[2,3],xmm1[4],xmm5[5,6],xmm1[7] +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} xmm5 = xmm7[0,1,3,2,4,5,6,7] +; AVX512F-SLOW-NEXT: vpermt2d %zmm5, %zmm3, %zmm1 +; AVX512F-SLOW-NEXT: vmovdqa (%rdi), %xmm3 +; AVX512F-SLOW-NEXT: vmovdqa (%rsi), %xmm5 +; AVX512F-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm7 = xmm3[0],xmm5[0],xmm3[1],xmm5[1],xmm3[2],xmm5[2],xmm3[3],xmm5[3] +; AVX512F-SLOW-NEXT: vpshufb %xmm0, %xmm7, %xmm7 +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm7[0,0,1,1] +; AVX512F-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm14 = xmm5[4],xmm3[4],xmm5[5],xmm3[5],xmm5[6],xmm3[6],xmm5[7],xmm3[7] +; AVX512F-SLOW-NEXT: vprold $16, %xmm5, %xmm5 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[1,1,2,3] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1],xmm5[2],xmm3[3,4],xmm5[5],xmm3[6,7] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,0,2,1] +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm3, %zmm7, %zmm3 +; AVX512F-SLOW-NEXT: vpternlogq $226, %zmm1, %zmm2, %zmm3 +; AVX512F-SLOW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-SLOW-NEXT: vmovdqa (%r9), %xmm1 +; AVX512F-SLOW-NEXT: vmovdqa (%r8), %xmm2 +; AVX512F-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7] +; AVX512F-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3] +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} xmm2 = xmm1[0,1,2,3,4,5,7,6] +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} xmm1 = xmm1[0,1,3,2,4,5,6,7] +; AVX512F-SLOW-NEXT: vpermt2d %zmm2, %zmm6, %zmm1 +; AVX512F-SLOW-NEXT: vpbroadcastd (%rax), %ymm2 +; AVX512F-SLOW-NEXT: vpbroadcastd 4(%rax), %ymm3 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm2 +; AVX512F-SLOW-NEXT: vpternlogq $184, %zmm1, %zmm9, %zmm2 +; AVX512F-SLOW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm23, %ymm7 +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} ymm1 = ymm7[1,2,3,3,4,5,6,7,9,10,11,11,12,13,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,0,2,1,4,4,6,5] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm25[1,1,1,1,5,5,5,5] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0,1],ymm2[2],ymm1[3,4],ymm2[5],ymm1[6,7,8,9],ymm2[10],ymm1[11,12],ymm2[13],ymm1[14,15] +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm1, %ymm20 +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} ymm1 = ymm7[0,1,2,3,5,4,6,7,8,9,10,11,13,12,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm25[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0],ymm1[1],ymm2[2,3],ymm1[4],ymm2[5,6,7,8],ymm1[9],ymm2[10,11],ymm1[12],ymm2[13,14,15] +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm1, %ymm27 +; AVX512F-SLOW-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm3 # 32-byte Reload +; AVX512F-SLOW-NEXT: vprold $16, %ymm3, %ymm1 +; AVX512F-SLOW-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm5 # 32-byte Reload +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm5[1,2,2,3,5,6,6,7] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0,1],ymm1[2],ymm2[3,4],ymm1[5],ymm2[6,7,8,9],ymm1[10],ymm2[11,12],ymm1[13],ymm2[14,15] +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} ymm2 = ymm3[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[0,0,0,0,4,4,4,4] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm6 = ymm5[0,0,2,1,4,4,6,5] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm2 = ymm2[0,1,2],ymm6[3],ymm2[4,5],ymm6[6],ymm2[7,8,9,10],ymm6[11],ymm2[12,13],ymm6[14],ymm2[15] +; AVX512F-SLOW-NEXT: vpermt2q %zmm1, %zmm10, %zmm2 +; AVX512F-SLOW-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm8 # 32-byte Reload +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} ymm1 = ymm8[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,0,0,0,4,4,4,4] +; AVX512F-SLOW-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm10 # 32-byte Reload +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm6 = ymm10[0,1,1,3,4,5,5,7] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm6[0,1],ymm1[2],ymm6[3,4],ymm1[5],ymm6[6,7,8,9],ymm1[10],ymm6[11,12],ymm1[13],ymm6[14,15] +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm1, %ymm24 +; AVX512F-SLOW-NEXT: vpshufb %ymm13, %ymm8, %ymm1 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm6 = ymm10[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0,1],ymm6[2],ymm1[3,4],ymm6[5],ymm1[6,7,8,9],ymm6[10],ymm1[11,12],ymm6[13],ymm1[14,15] +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm1, %ymm21 +; AVX512F-SLOW-NEXT: vpermd (%rax), %zmm11, %zmm1 +; AVX512F-SLOW-NEXT: vpternlogq $184, %zmm2, %zmm17, %zmm1 +; AVX512F-SLOW-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm10[3,3,3,3,7,7,7,7] +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} ymm2 = ymm8[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0],ymm2[1],ymm1[2,3],ymm2[4],ymm1[5,6,7,8],ymm2[9],ymm1[10,11],ymm2[12],ymm1[13,14,15] +; AVX512F-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm25[3,3,3,3,7,7,7,7] +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} ymm2 = ymm7[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[2,2,2,2,6,6,6,6] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0,1,2],ymm2[3],ymm1[4,5],ymm2[6],ymm1[7,8,9,10],ymm2[11],ymm1[12,13],ymm2[14],ymm1[15] +; AVX512F-SLOW-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm5[3,3,3,3,7,7,7,7] +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} ymm2 = ymm3[0,1,2,3,5,6,7,7,8,9,10,11,13,14,15,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[2,2,2,3,6,6,6,7] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0,1],ymm1[2],ymm2[3,4],ymm1[5],ymm2[6,7,8,9],ymm1[10],ymm2[11,12],ymm1[13],ymm2[14,15] +; AVX512F-SLOW-NEXT: vmovdqa 32(%r9), %xmm7 +; AVX512F-SLOW-NEXT: vmovdqa 32(%r8), %xmm2 +; AVX512F-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm6 = xmm2[0],xmm7[0],xmm2[1],xmm7[1],xmm2[2],xmm7[2],xmm2[3],xmm7[3] +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} xmm11 = xmm6[0,1,3,2,4,5,6,7] +; AVX512F-SLOW-NEXT: vpermt2d %zmm11, %zmm12, %zmm1 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm11 = ymm22[2,3,3,3,6,7,7,7] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm11 = ymm11[2,1,3,2] +; AVX512F-SLOW-NEXT: vpbroadcastd 32(%rax), %ymm12 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm12, %zmm11, %zmm25 +; AVX512F-SLOW-NEXT: vpternlogq $184, %zmm1, %zmm15, %zmm25 +; AVX512F-SLOW-NEXT: vmovdqa 32(%rdi), %xmm1 +; AVX512F-SLOW-NEXT: vmovdqa 32(%rsi), %xmm12 +; AVX512F-SLOW-NEXT: vprold $16, %xmm12, %xmm15 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} xmm13 = xmm1[1,1,2,3] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} xmm3 = xmm13[0,1],xmm15[2],xmm13[3,4],xmm15[5],xmm13[6,7] +; AVX512F-SLOW-NEXT: vmovdqu %ymm3, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm13 = xmm1[0],xmm12[0],xmm1[1],xmm12[1],xmm1[2],xmm12[2],xmm1[3],xmm12[3] +; AVX512F-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm12[4],xmm1[4],xmm12[5],xmm1[5],xmm12[6],xmm1[6],xmm12[7],xmm1[7] +; AVX512F-SLOW-NEXT: vmovdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512F-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm2[4],xmm7[4],xmm2[5],xmm7[5],xmm2[6],xmm7[6],xmm2[7],xmm7[7] +; AVX512F-SLOW-NEXT: vmovdqa64 %xmm16, %xmm1 +; AVX512F-SLOW-NEXT: vpshufb %xmm0, %xmm1, %xmm1 +; AVX512F-SLOW-NEXT: vpshufb %xmm0, %xmm4, %xmm3 +; AVX512F-SLOW-NEXT: vmovdqa64 %xmm18, %xmm4 +; AVX512F-SLOW-NEXT: vpshufb %xmm0, %xmm4, %xmm4 +; AVX512F-SLOW-NEXT: vmovdqu %ymm4, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vpshufb %xmm0, %xmm13, %xmm4 +; AVX512F-SLOW-NEXT: vmovdqu %ymm4, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vpshufb %xmm0, %xmm2, %xmm2 +; AVX512F-SLOW-NEXT: vpermq $234, {{[-0-9]+}}(%r{{[sb]}}p), %ymm23 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: # ymm23 = mem[2,2,2,3] +; AVX512F-SLOW-NEXT: vpermq $232, {{[-0-9]+}}(%r{{[sb]}}p), %ymm22 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: # ymm22 = mem[0,2,2,3] +; AVX512F-SLOW-NEXT: vpermq $232, {{[-0-9]+}}(%r{{[sb]}}p), %ymm18 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: # ymm18 = mem[0,2,2,3] +; AVX512F-SLOW-NEXT: vpermq $246, {{[-0-9]+}}(%r{{[sb]}}p), %ymm17 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: # ymm17 = mem[2,1,3,3] +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} xmm0 = xmm6[0,1,2,3,4,5,7,6] +; AVX512F-SLOW-NEXT: vpermt2d %zmm0, %zmm28, %zmm2 +; AVX512F-SLOW-NEXT: vpbroadcastd 36(%rax), %ymm0 +; AVX512F-SLOW-NEXT: vpbroadcastd 40(%rax), %ymm6 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm6, %zmm0, %zmm28 +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm28 +; AVX512F-SLOW-NEXT: vmovdqa 32(%rcx), %xmm6 +; AVX512F-SLOW-NEXT: vmovdqa64 %xmm29, %xmm0 +; AVX512F-SLOW-NEXT: vpshufb %xmm0, %xmm6, %xmm2 +; AVX512F-SLOW-NEXT: vmovdqa 32(%rdx), %xmm0 +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} xmm7 = xmm0[1,1,2,2] +; AVX512F-SLOW-NEXT: vpblendw {{.*#+}} xmm2 = xmm7[0],xmm2[1],xmm7[2,3],xmm2[4],xmm7[5,6],xmm2[7] +; AVX512F-SLOW-NEXT: vmovdqu %ymm2, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-SLOW-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm0[0],xmm6[0],xmm0[1],xmm6[1],xmm0[2],xmm6[2],xmm0[3],xmm6[3] +; AVX512F-SLOW-NEXT: vmovdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512F-SLOW-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm6[4],xmm0[5],xmm6[5],xmm0[6],xmm6[6],xmm0[7],xmm6[7] +; AVX512F-SLOW-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512F-SLOW-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm4 # 32-byte Reload +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm4[0,1,2,3,5,5,7,6,8,9,10,11,13,13,15,14] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm29 = ymm0[3,3,3,3] +; AVX512F-SLOW-NEXT: vpshufd $233, {{[-0-9]+}}(%r{{[sb]}}p), %ymm2 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: # ymm2 = mem[1,2,2,3,5,6,6,7] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm10 = ymm4[2,1,2,3,6,5,6,7] +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} ymm10 = ymm10[0,0,3,3,4,5,6,7,8,8,11,11,12,13,14,15] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm0 = ymm10[2,2,2,2] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,0,1,1] +; AVX512F-SLOW-NEXT: vmovdqa64 %xmm30, %xmm4 +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} xmm10 = xmm4[0,2,3,3,4,5,6,7] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm10 = ymm10[0,0,2,1] +; AVX512F-SLOW-NEXT: vmovdqa64 %xmm26, %xmm4 +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} xmm8 = xmm4[2,1,2,3,4,5,6,7] +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} xmm8 = xmm8[0,1,2,3,4,5,5,4] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm8 = ymm8[0,0,1,3] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,0,1,1] +; AVX512F-SLOW-NEXT: vmovdqa64 %xmm19, %xmm4 +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} xmm15 = xmm4[0,2,3,3,4,5,6,7] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm15 = ymm15[0,0,2,1] +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} xmm12 = xmm14[2,1,2,3,4,5,6,7] +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} xmm12 = xmm12[0,1,2,3,4,5,5,4] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm12 = ymm12[0,0,1,3] +; AVX512F-SLOW-NEXT: vpermq $182, {{[-0-9]+}}(%r{{[sb]}}p), %ymm4 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: # ymm4 = mem[2,1,3,2] +; AVX512F-SLOW-NEXT: vpermq $234, {{[-0-9]+}}(%r{{[sb]}}p), %ymm5 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: # ymm5 = mem[2,2,2,3] +; AVX512F-SLOW-NEXT: vpermq $250, {{[-0-9]+}}(%r{{[sb]}}p), %ymm6 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: # ymm6 = mem[2,2,3,3] +; AVX512F-SLOW-NEXT: vpermpd $234, {{[-0-9]+}}(%r{{[sb]}}p), %ymm7 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: # ymm7 = mem[2,2,2,3] +; AVX512F-SLOW-NEXT: vmovups %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm31 = ymm31[0,2,2,3] +; AVX512F-SLOW-NEXT: vpermq $232, {{[-0-9]+}}(%r{{[sb]}}p), %ymm30 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: # ymm30 = mem[0,2,2,3] +; AVX512F-SLOW-NEXT: vpermq $246, {{[-0-9]+}}(%r{{[sb]}}p), %ymm26 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: # ymm26 = mem[2,1,3,3] +; AVX512F-SLOW-NEXT: vpermq $234, {{[-0-9]+}}(%r{{[sb]}}p), %ymm19 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: # ymm19 = mem[2,2,2,3] +; AVX512F-SLOW-NEXT: vpermq $232, {{[-0-9]+}}(%r{{[sb]}}p), %ymm11 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: # ymm11 = mem[0,2,2,3] +; AVX512F-SLOW-NEXT: vpermq $182, {{[-0-9]+}}(%r{{[sb]}}p), %ymm16 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: # ymm16 = mem[2,1,3,2] +; AVX512F-SLOW-NEXT: vpermq $234, {{[-0-9]+}}(%r{{[sb]}}p), %ymm7 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: # ymm7 = mem[2,2,2,3] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm20 = ymm20[2,2,2,3] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm13 = ymm27[0,2,2,3] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm14 = ymm24[2,1,3,2] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm9 = ymm21[2,2,2,3] +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm22, %zmm23, %zmm22 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm17, %zmm18, %zmm23 +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm27 = [65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535] +; AVX512F-SLOW-NEXT: vpternlogq $184, %zmm22, %zmm27, %zmm23 +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm2 = ymm2[2,1,3,2] +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm17 = [65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535] +; AVX512F-SLOW-NEXT: vpternlogq $184, %ymm23, %ymm17, %ymm2 +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm17 = [65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535] +; AVX512F-SLOW-NEXT: vpternlogq $184, %ymm2, %ymm17, %ymm0 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm2 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm1[0,1,2,3],zmm2[4,5,6,7] +; AVX512F-SLOW-NEXT: vpternlogq $234, {{[-0-9]+}}(%r{{[sb]}}p), %zmm17, %zmm2 # 64-byte Folded Reload +; AVX512F-SLOW-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm1 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm3 = zmm3[0,1,2,3],zmm1[4,5,6,7] +; AVX512F-SLOW-NEXT: vpternlogq $234, {{[-0-9]+}}(%r{{[sb]}}p), %zmm17, %zmm3 # 64-byte Folded Reload +; AVX512F-SLOW-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm10, %zmm10 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm8, %zmm8 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm22 = [65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535] +; AVX512F-SLOW-NEXT: vpternlogq $226, %zmm10, %zmm22, %zmm8 +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm17 = [0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535] +; AVX512F-SLOW-NEXT: vpternlogq $226, %zmm2, %zmm17, %zmm8 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm15, %zmm2 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm12, %zmm10 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: vpternlogq $226, %zmm2, %zmm22, %zmm10 +; AVX512F-SLOW-NEXT: vpternlogq $226, %zmm3, %zmm17, %zmm10 +; AVX512F-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm4, %zmm1, %zmm2 +; AVX512F-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm5, %zmm1, %zmm18 +; AVX512F-SLOW-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm18 +; AVX512F-SLOW-NEXT: vextracti64x4 $1, %zmm23, %ymm2 +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm1 = [65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535] +; AVX512F-SLOW-NEXT: vpternlogd $226, 124(%r8){1to8}, %ymm1, %ymm2 +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm3 = [0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535] +; AVX512F-SLOW-NEXT: vpternlogq $184, %ymm2, %ymm3, %ymm29 +; AVX512F-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm21 # 64-byte Reload +; AVX512F-SLOW-NEXT: vpternlogq $248, {{[-0-9]+}}(%r{{[sb]}}p), %zmm3, %zmm21 # 64-byte Folded Reload +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm6, %zmm0, %zmm2 +; AVX512F-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512F-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm24 = zmm1[0,1,2,3],zmm2[4,5,6,7] +; AVX512F-SLOW-NEXT: vpternlogq $234, {{[-0-9]+}}(%r{{[sb]}}p), %zmm3, %zmm24 # 64-byte Folded Reload +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm29, %zmm0, %zmm2 +; AVX512F-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm2[4,5,6,7] +; AVX512F-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm23 # 64-byte Reload +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm1 = [65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0] +; AVX512F-SLOW-NEXT: vpternlogq $184, %zmm0, %zmm1, %zmm23 +; AVX512F-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm29 # 64-byte Reload +; AVX512F-SLOW-NEXT: vpternlogq $184, {{[-0-9]+}}(%r{{[sb]}}p), %zmm1, %zmm29 # 64-byte Folded Reload +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm0 = [65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535] +; AVX512F-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm17 # 64-byte Reload +; AVX512F-SLOW-NEXT: vpternlogq $184, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm17 # 64-byte Folded Reload +; AVX512F-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload +; AVX512F-SLOW-NEXT: vpternlogq $184, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm6 # 64-byte Folded Reload +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm11, %zmm19, %zmm0 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm7, %zmm16, %zmm2 +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm3 = [0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535] +; AVX512F-SLOW-NEXT: vpternlogq $226, %zmm0, %zmm3, %zmm2 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm13, %zmm20, %zmm0 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm9, %zmm14, %zmm4 +; AVX512F-SLOW-NEXT: vpternlogq $226, %zmm0, %zmm3, %zmm4 +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm0 = [65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0] +; AVX512F-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload +; AVX512F-SLOW-NEXT: vpternlogq $184, %zmm2, %zmm0, %zmm19 +; AVX512F-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm20 # 64-byte Reload +; AVX512F-SLOW-NEXT: vpternlogq $184, %zmm4, %zmm0, %zmm20 +; AVX512F-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm31, %zmm0, %zmm0 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm26, %zmm30, %zmm2 +; AVX512F-SLOW-NEXT: vpternlogq $184, %zmm0, %zmm27, %zmm2 +; AVX512F-SLOW-NEXT: vpermq $232, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: # ymm0 = mem[0,2,2,3] +; AVX512F-SLOW-NEXT: vpshuflw $180, {{[-0-9]+}}(%r{{[sb]}}p), %xmm3 # 16-byte Folded Reload +; AVX512F-SLOW-NEXT: # xmm3 = mem[0,1,3,2,4,5,6,7] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[0,0,1,1] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,1,1,3] +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm0 +; AVX512F-SLOW-NEXT: vpermq $246, {{[-0-9]+}}(%r{{[sb]}}p), %ymm3 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: # ymm3 = mem[2,1,3,3] +; AVX512F-SLOW-NEXT: vpermq $80, {{[-0-9]+}}(%r{{[sb]}}p), %ymm4 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: # ymm4 = mem[0,0,1,1] +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm4, %zmm3, %zmm3 +; AVX512F-SLOW-NEXT: vpermq $96, {{[-0-9]+}}(%r{{[sb]}}p), %ymm4 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: # ymm4 = mem[0,0,2,1] +; AVX512F-SLOW-NEXT: vpshuflw $230, {{[-0-9]+}}(%r{{[sb]}}p), %xmm5 # 16-byte Folded Reload +; AVX512F-SLOW-NEXT: # xmm5 = mem[2,1,2,3,4,5,6,7] +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} xmm5 = xmm5[0,1,2,3,4,5,5,4] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm5 = ymm5[0,0,1,3] +; AVX512F-SLOW-NEXT: vpermq $80, {{[-0-9]+}}(%r{{[sb]}}p), %ymm26 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: # ymm26 = mem[0,0,1,1] +; AVX512F-SLOW-NEXT: vpshuflw $248, {{[-0-9]+}}(%r{{[sb]}}p), %xmm7 # 16-byte Folded Reload +; AVX512F-SLOW-NEXT: # xmm7 = mem[0,2,3,3,4,5,6,7] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm7[0,0,2,1] +; AVX512F-SLOW-NEXT: vpermq $232, {{[-0-9]+}}(%r{{[sb]}}p), %ymm9 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: # ymm9 = mem[0,2,2,3] +; AVX512F-SLOW-NEXT: vpshuflw $180, {{[-0-9]+}}(%r{{[sb]}}p), %xmm11 # 16-byte Folded Reload +; AVX512F-SLOW-NEXT: # xmm11 = mem[0,1,3,2,4,5,6,7] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} xmm11 = xmm11[0,0,1,1] +; AVX512F-SLOW-NEXT: vpermq $246, {{[-0-9]+}}(%r{{[sb]}}p), %ymm12 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: # ymm12 = mem[2,1,3,3] +; AVX512F-SLOW-NEXT: vpermq $80, {{[-0-9]+}}(%r{{[sb]}}p), %ymm13 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: # ymm13 = mem[0,0,1,1] +; AVX512F-SLOW-NEXT: vpermq $96, {{[-0-9]+}}(%r{{[sb]}}p), %ymm14 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: # ymm14 = mem[0,0,2,1] +; AVX512F-SLOW-NEXT: vpshuflw $230, {{[-0-9]+}}(%r{{[sb]}}p), %xmm15 # 16-byte Folded Reload +; AVX512F-SLOW-NEXT: # xmm15 = mem[2,1,2,3,4,5,6,7] +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} xmm15 = xmm15[0,1,2,3,4,5,5,4] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm15 = ymm15[0,0,1,3] +; AVX512F-SLOW-NEXT: vpermq $80, {{[-0-9]+}}(%r{{[sb]}}p), %ymm16 # 32-byte Folded Reload +; AVX512F-SLOW-NEXT: # ymm16 = mem[0,0,1,1] +; AVX512F-SLOW-NEXT: vpshuflw $248, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload +; AVX512F-SLOW-NEXT: # xmm1 = mem[0,2,3,3,4,5,6,7] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,0,2,1] +; AVX512F-SLOW-NEXT: vpternlogq $226, %zmm0, %zmm27, %zmm3 +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm0 = ymm11[0,1,1,3] +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm0, %zmm9, %zmm0 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm13, %zmm12, %zmm9 +; AVX512F-SLOW-NEXT: vpternlogq $226, %zmm0, %zmm27, %zmm9 +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm0 = [0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535] +; AVX512F-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload +; AVX512F-SLOW-NEXT: vpternlogq $184, %zmm3, %zmm0, %zmm11 +; AVX512F-SLOW-NEXT: vpternlogq $184, %zmm9, %zmm0, %zmm25 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm5, %zmm4, %zmm0 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm7, %zmm26, %zmm3 +; AVX512F-SLOW-NEXT: vpternlogq $226, %zmm0, %zmm22, %zmm3 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm15, %zmm14, %zmm0 +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm1, %zmm16, %zmm1 +; AVX512F-SLOW-NEXT: vpternlogq $226, %zmm0, %zmm22, %zmm1 +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm0 = [65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0] +; AVX512F-SLOW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512F-SLOW-NEXT: vpternlogq $184, %zmm3, %zmm0, %zmm4 +; AVX512F-SLOW-NEXT: vpternlogq $184, %zmm1, %zmm0, %zmm28 +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm18, %zmm24 +; AVX512F-SLOW-NEXT: vmovdqa64 %zmm29, %zmm0 +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm0 +; AVX512F-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512F-SLOW-NEXT: vmovdqa64 %zmm24, 320(%rax) +; AVX512F-SLOW-NEXT: vmovdqa64 %zmm28, 256(%rax) +; AVX512F-SLOW-NEXT: vmovdqa64 %zmm25, 192(%rax) +; AVX512F-SLOW-NEXT: vmovdqa64 %zmm20, 128(%rax) +; AVX512F-SLOW-NEXT: vmovdqa64 %zmm10, 64(%rax) +; AVX512F-SLOW-NEXT: vmovdqa64 %zmm6, (%rax) +; AVX512F-SLOW-NEXT: vmovdqa64 %zmm17, 448(%rax) +; AVX512F-SLOW-NEXT: vmovdqa64 %zmm4, 704(%rax) +; AVX512F-SLOW-NEXT: vmovdqa64 %zmm11, 640(%rax) +; AVX512F-SLOW-NEXT: vmovdqa64 %zmm19, 576(%rax) +; AVX512F-SLOW-NEXT: vmovdqa64 %zmm8, 512(%rax) +; AVX512F-SLOW-NEXT: vmovdqa64 %zmm0, 384(%rax) +; AVX512F-SLOW-NEXT: vmovdqa64 %zmm21, 768(%rax) +; AVX512F-SLOW-NEXT: vmovdqa64 %zmm23, 832(%rax) +; AVX512F-SLOW-NEXT: addq $2200, %rsp # imm = 0x898 +; AVX512F-SLOW-NEXT: vzeroupper +; AVX512F-SLOW-NEXT: retq ; -; AVX512DQ-FAST-LABEL: store_i16_stride7_vf64: -; AVX512DQ-FAST: # %bb.0: -; AVX512DQ-FAST-NEXT: subq $1496, %rsp # imm = 0x5D8 -; AVX512DQ-FAST-NEXT: vmovdqa 96(%rcx), %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm15 = [128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128,128,128,128,128] -; AVX512DQ-FAST-NEXT: vpshufb %ymm15, %ymm0, %ymm2 -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm0, %ymm20 -; AVX512DQ-FAST-NEXT: vmovdqa 96(%rdx), %ymm9 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm0 = -; AVX512DQ-FAST-NEXT: vpshufb %ymm0, %ymm9, %ymm3 -; AVX512DQ-FAST-NEXT: vmovdqa %ymm0, %ymm10 -; AVX512DQ-FAST-NEXT: vporq %ymm2, %ymm3, %ymm16 -; AVX512DQ-FAST-NEXT: vmovdqa 96(%rsi), %ymm6 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm14 = [128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128,128,128,128,128,128,128,128,128] -; AVX512DQ-FAST-NEXT: vpshufb %ymm14, %ymm6, %ymm2 -; AVX512DQ-FAST-NEXT: vmovdqa 96(%rdi), %ymm7 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm11 = <12,13,14,15,128,128,u,u,u,u,u,u,u,u,u,u,16,17,128,128,u,u,u,u,u,u,u,u,16,17,18,19> -; AVX512DQ-FAST-NEXT: vpshufb %ymm11, %ymm7, %ymm3 -; AVX512DQ-FAST-NEXT: vporq %ymm2, %ymm3, %ymm17 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm3 = [128,128,128,128,128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128] -; AVX512DQ-FAST-NEXT: vmovdqa 64(%r9), %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vpshufb %ymm3, %ymm0, %ymm2 -; AVX512DQ-FAST-NEXT: vmovdqa 64(%r8), %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm5 = -; AVX512DQ-FAST-NEXT: vpshufb %ymm5, %ymm0, %ymm4 -; AVX512DQ-FAST-NEXT: vporq %ymm2, %ymm4, %ymm18 -; AVX512DQ-FAST-NEXT: vmovdqa 64(%rcx), %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm0, (%rsp) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vpshufb %ymm15, %ymm0, %ymm8 -; AVX512DQ-FAST-NEXT: vmovdqa 64(%rdx), %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vpshufb %ymm10, %ymm0, %ymm12 -; AVX512DQ-FAST-NEXT: vpor %ymm8, %ymm12, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa 64(%rsi), %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vpshufb %ymm14, %ymm0, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqa 64(%rdi), %ymm1 -; AVX512DQ-FAST-NEXT: vpshufb %ymm11, %ymm1, %ymm13 -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm1, %ymm28 -; AVX512DQ-FAST-NEXT: vpor %ymm0, %ymm13, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa (%r9), %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vpshufb %ymm3, %ymm0, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqa (%r8), %ymm1 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vpshufb %ymm5, %ymm1, %ymm13 -; AVX512DQ-FAST-NEXT: vporq %ymm0, %ymm13, %ymm19 -; AVX512DQ-FAST-NEXT: vmovdqa (%rcx), %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vpshufb %ymm15, %ymm0, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqa (%rdx), %ymm1 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa %ymm10, %ymm2 -; AVX512DQ-FAST-NEXT: vpshufb %ymm10, %ymm1, %ymm13 -; AVX512DQ-FAST-NEXT: vpor %ymm0, %ymm13, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa (%rsi), %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vpshufb %ymm14, %ymm0, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqa (%rdi), %ymm1 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vpshufb %ymm11, %ymm1, %ymm13 -; AVX512DQ-FAST-NEXT: vpor %ymm0, %ymm13, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa 32(%rcx), %ymm10 -; AVX512DQ-FAST-NEXT: vpshufb %ymm15, %ymm10, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqa 32(%rdx), %ymm15 -; AVX512DQ-FAST-NEXT: vpshufb %ymm2, %ymm15, %ymm13 -; AVX512DQ-FAST-NEXT: vpor %ymm0, %ymm13, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa 32(%rsi), %ymm8 -; AVX512DQ-FAST-NEXT: vpshufb %ymm14, %ymm8, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqa 32(%rdi), %ymm4 -; AVX512DQ-FAST-NEXT: vpshufb %ymm11, %ymm4, %ymm11 -; AVX512DQ-FAST-NEXT: vpor %ymm0, %ymm11, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa 32(%r8), %ymm13 -; AVX512DQ-FAST-NEXT: vpshufb %ymm5, %ymm13, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqa 32(%r9), %ymm14 -; AVX512DQ-FAST-NEXT: vpshufb %ymm3, %ymm14, %ymm5 -; AVX512DQ-FAST-NEXT: vmovdqa %ymm3, %ymm12 -; AVX512DQ-FAST-NEXT: vporq %ymm5, %ymm0, %ymm21 -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm20, %ymm2 -; AVX512DQ-FAST-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11] -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm11 = ymm9[0,1,1,3,4,5,5,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm11[0,1],ymm0[2],ymm11[3,4],ymm0[5],ymm11[6,7,8,9],ymm0[10],ymm11[11,12],ymm0[13],ymm11[14,15] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,1,3,2] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm11 = ymm6[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,20,21,18,19,20,21,24,25,26,27,22,23,22,23] -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm7[1,1,1,1,5,5,5,5] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm11[0,1],ymm3[2],ymm11[3,4],ymm3[5],ymm11[6,7,8,9],ymm3[10],ymm11[11,12],ymm3[13],ymm11[14,15] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm3 = ymm3[2,2,2,3] -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm16, %zmm0 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm3, %zmm17, %zmm3 -; AVX512DQ-FAST-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm3 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm25 = [65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535] -; AVX512DQ-FAST-NEXT: vmovdqa 96(%r8), %ymm11 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm11[u,u],zero,zero,zero,zero,zero,zero,zero,zero,ymm11[14,15,u,u,u,u],zero,zero,zero,zero,zero,zero,zero,zero,ymm11[16,17,u,u,u,u],zero,zero -; AVX512DQ-FAST-NEXT: vpternlogq $248, %ymm25, %ymm3, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqa 96(%r9), %ymm5 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm5, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vpshufb %ymm12, %ymm5, %ymm1 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm12 = [65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535] -; AVX512DQ-FAST-NEXT: vpternlogq $248, %ymm12, %ymm0, %ymm1 -; AVX512DQ-FAST-NEXT: vextracti64x4 $1, %zmm3, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm3 = -; AVX512DQ-FAST-NEXT: vpermd %ymm11, %ymm3, %ymm3 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm17 = [65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0] -; AVX512DQ-FAST-NEXT: vpternlogq $184, %ymm0, %ymm17, %ymm3 -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm17, %zmm22 -; AVX512DQ-FAST-NEXT: vprold $16, %ymm5, %ymm0 -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,2,2,2] -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm5 = [65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535] -; AVX512DQ-FAST-NEXT: vpternlogq $184, %ymm3, %ymm5, %ymm0 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm0 -; AVX512DQ-FAST-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm1[0,1,2,3],zmm0[4,5,6,7] -; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm1 = [0,1,4,5,4,5,5,7] -; AVX512DQ-FAST-NEXT: vmovdqa 96(%rax), %ymm0 -; AVX512DQ-FAST-NEXT: vpermd %ymm0, %ymm1, %ymm1 -; AVX512DQ-FAST-NEXT: vpandnq %ymm1, %ymm25, %ymm1 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm5 = [12,13,128,128,128,128,128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128] -; AVX512DQ-FAST-NEXT: vpshufb %ymm5, %ymm0, %ymm3 -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm5, %ymm20 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm1, %zmm3, %zmm1 -; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm3 = -; AVX512DQ-FAST-NEXT: vpshufb %ymm3, %ymm6, %ymm1 -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm3, %ymm26 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm7[3,3,3,3,7,7,7,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm3[0,1,2],ymm1[3],ymm3[4,5],ymm1[6],ymm3[7,8,9,10],ymm1[11],ymm3[12,13],ymm1[14],ymm3[15] -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm5 = <10,11,8,9,u,u,u,u,u,u,u,u,u,u,u,u,26,27,24,25,u,u,u,u,26,27,24,25,u,u,u,u> -; AVX512DQ-FAST-NEXT: vpshufb %ymm5, %ymm6, %ymm3 -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm5, %ymm29 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm6 = ymm7[2,2,2,2,6,6,6,6] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm6[0],ymm3[1],ymm6[2,3],ymm3[4],ymm6[5,6,7,8],ymm3[9],ymm6[10,11],ymm3[12],ymm6[13,14,15] -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm6 = [0,2,2,3,10,9,11,11] -; AVX512DQ-FAST-NEXT: vpermt2q %zmm1, %zmm6, %zmm3 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm7 = <14,15,12,13,u,u,u,u,u,u,u,u,u,u,u,u,30,31,28,29,u,u,u,u,30,31,28,29,u,u,u,u> -; AVX512DQ-FAST-NEXT: vpshufb %ymm7, %ymm2, %ymm1 -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm7, %ymm27 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm7 = ymm9[3,3,3,3,7,7,7,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm7[0],ymm1[1],ymm7[2,3],ymm1[4],ymm7[5,6,7,8],ymm1[9],ymm7[10,11],ymm1[12],ymm7[13,14,15] -; AVX512DQ-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm5 = [22,23,26,27,0,0,24,25,26,27,0,0,26,27,26,27,22,23,26,27,0,0,24,25,26,27,0,0,26,27,26,27] -; AVX512DQ-FAST-NEXT: # ymm5 = mem[0,1,0,1] -; AVX512DQ-FAST-NEXT: vpshufb %ymm5, %ymm2, %ymm7 -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm5, %ymm16 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm9 = ymm9[2,2,2,2,6,6,6,6] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm7 = ymm7[0,1],ymm9[2],ymm7[3,4],ymm9[5],ymm7[6,7,8,9],ymm9[10],ymm7[11,12],ymm9[13],ymm7[14,15] -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm17 = [2,2,2,3,8,10,10,11] -; AVX512DQ-FAST-NEXT: vpermt2q %zmm1, %zmm17, %zmm7 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm1 = [65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535] -; AVX512DQ-FAST-NEXT: vpternlogq $226, %zmm3, %zmm1, %zmm7 -; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm1, %zmm24 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm1 = <5,u,u,u,6,u,u,6> -; AVX512DQ-FAST-NEXT: vpermd %ymm11, %ymm1, %ymm1 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa64 64(%rax), %zmm12 -; AVX512DQ-FAST-NEXT: vbroadcasti32x8 {{.*#+}} zmm3 = [30,5,0,0,31,6,0,31,30,5,0,0,31,6,0,31] -; AVX512DQ-FAST-NEXT: # zmm3 = mem[0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7] -; AVX512DQ-FAST-NEXT: vpermi2d %zmm12, %zmm0, %zmm3 -; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm23 = [65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535] -; AVX512DQ-FAST-NEXT: vpbroadcastd 72(%rax), %ymm0 -; AVX512DQ-FAST-NEXT: vpandnq %ymm0, %ymm23, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqa 64(%rax), %ymm7 -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm20, %ymm5 -; AVX512DQ-FAST-NEXT: vpshufb %ymm5, %ymm7, %ymm3 -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm7, %ymm30 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm11 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm18, %zmm0, %zmm0 -; AVX512DQ-FAST-NEXT: vmovdqa 64(%r9), %xmm1 -; AVX512DQ-FAST-NEXT: vmovdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa 64(%r8), %xmm2 -; AVX512DQ-FAST-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7] -; AVX512DQ-FAST-NEXT: vmovdqa64 %xmm2, %xmm20 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} xmm9 = [0,1,2,3,4,5,4,5,6,7,10,11,8,9,10,11] -; AVX512DQ-FAST-NEXT: vpshufb %xmm9, %xmm3, %xmm3 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm18 = [0,0,1,1,12,13,14,15] -; AVX512DQ-FAST-NEXT: vpermt2q %zmm0, %zmm18, %zmm3 -; AVX512DQ-FAST-NEXT: vpternlogq $248, %zmm23, %zmm3, %zmm11 -; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vpbroadcastd 8(%rax), %ymm0 -; AVX512DQ-FAST-NEXT: vpandnq %ymm0, %ymm23, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqa (%rax), %ymm1 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vpshufb %ymm5, %ymm1, %ymm3 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm5 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm19, %zmm0, %zmm0 -; AVX512DQ-FAST-NEXT: vmovdqa (%r9), %xmm1 -; AVX512DQ-FAST-NEXT: vmovdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa (%r8), %xmm2 -; AVX512DQ-FAST-NEXT: vmovdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512DQ-FAST-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7] -; AVX512DQ-FAST-NEXT: vpshufb %xmm9, %xmm3, %xmm3 -; AVX512DQ-FAST-NEXT: vpermt2q %zmm0, %zmm18, %zmm3 -; AVX512DQ-FAST-NEXT: vpternlogq $248, %zmm23, %zmm3, %zmm5 -; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vpbroadcastd {{.*#+}} ymm7 = [18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21] -; AVX512DQ-FAST-NEXT: vpshufb %ymm7, %ymm14, %ymm0 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm13[0,0,2,1,4,4,6,5] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2],ymm3[3],ymm0[4,5],ymm3[6],ymm0[7,8,9,10],ymm3[11],ymm0[12,13],ymm3[14],ymm0[15] -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm3 = <0,1,u,3,10,10,11,11> -; AVX512DQ-FAST-NEXT: vpermi2q %zmm0, %zmm21, %zmm3 -; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqu %ymm8, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm26, %ymm9 -; AVX512DQ-FAST-NEXT: vpshufb %ymm9, %ymm8, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm4, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm4[3,3,3,3,7,7,7,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm3[0,1,2],ymm0[3],ymm3[4,5],ymm0[6],ymm3[7,8,9,10],ymm0[11],ymm3[12,13],ymm0[14],ymm3[15] -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm29, %ymm1 -; AVX512DQ-FAST-NEXT: vpshufb %ymm1, %ymm8, %ymm3 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm5 = ymm4[2,2,2,2,6,6,6,6] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm5[0],ymm3[1],ymm5[2,3],ymm3[4],ymm5[5,6,7,8],ymm3[9],ymm5[10,11],ymm3[12],ymm5[13,14,15] -; AVX512DQ-FAST-NEXT: vpermt2q %zmm0, %zmm6, %zmm3 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm10, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm27, %ymm11 -; AVX512DQ-FAST-NEXT: vpshufb %ymm11, %ymm10, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm15, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm5 = ymm15[3,3,3,3,7,7,7,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm5[0],ymm0[1],ymm5[2,3],ymm0[4],ymm5[5,6,7,8],ymm0[9],ymm5[10,11],ymm0[12],ymm5[13,14,15] -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm16, %ymm4 -; AVX512DQ-FAST-NEXT: vpshufb %ymm4, %ymm10, %ymm5 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm6 = ymm15[2,2,2,2,6,6,6,6] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm2 = ymm5[0,1],ymm6[2],ymm5[3,4],ymm6[5],ymm5[6,7,8,9],ymm6[10],ymm5[11,12],ymm6[13],ymm5[14,15] -; AVX512DQ-FAST-NEXT: vpermt2q %zmm0, %zmm17, %zmm2 -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm24, %zmm16 -; AVX512DQ-FAST-NEXT: vpternlogq $226, %zmm3, %zmm24, %zmm2 -; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm15 = [26,27,28,29,26,27,28,29,26,27,28,29,30,31,30,31,26,27,28,29,26,27,28,29,26,27,28,29,30,31,30,31] -; AVX512DQ-FAST-NEXT: # ymm15 = mem[0,1,0,1] -; AVX512DQ-FAST-NEXT: vpshufb %ymm15, %ymm14, %ymm0 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm13[3,3,3,3,7,7,7,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1],ymm3[2],ymm0[3,4],ymm3[5],ymm0[6,7,8,9],ymm3[10],ymm0[11,12],ymm3[13],ymm0[14,15] -; AVX512DQ-FAST-NEXT: vprold $16, %ymm14, %ymm3 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm5 = ymm13[1,2,2,3,5,6,6,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm5[0,1],ymm3[2],ymm5[3,4],ymm3[5],ymm5[6,7,8,9],ymm3[10],ymm5[11,12],ymm3[13],ymm5[14,15] -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm18 = [2,1,3,2,10,10,10,11] -; AVX512DQ-FAST-NEXT: vpermt2q %zmm0, %zmm18, %zmm3 -; AVX512DQ-FAST-NEXT: vmovdqa64 (%rax), %zmm19 -; AVX512DQ-FAST-NEXT: vbroadcasti32x8 {{.*#+}} zmm2 = [14,21,0,0,15,22,0,15,14,21,0,0,15,22,0,15] -; AVX512DQ-FAST-NEXT: # zmm2 = mem[0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7] -; AVX512DQ-FAST-NEXT: vmovdqa 32(%rax), %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vpermi2d %zmm0, %zmm19, %zmm2 -; AVX512DQ-FAST-NEXT: vpternlogq $184, %zmm3, %zmm22, %zmm2 -; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm13 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vpshufb %ymm1, %ymm13, %ymm0 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm28[2,2,2,2,6,6,6,6] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm3[0],ymm0[1],ymm3[2,3],ymm0[4],ymm3[5,6,7,8],ymm0[9],ymm3[10,11],ymm0[12],ymm3[13,14,15] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm3 = ymm13[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,20,21,18,19,20,21,24,25,26,27,22,23,22,23] -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm5 = ymm28[1,1,1,1,5,5,5,5] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm3[0,1],ymm5[2],ymm3[3,4],ymm5[5],ymm3[6,7,8,9],ymm5[10],ymm3[11,12],ymm5[13],ymm3[14,15] -; AVX512DQ-FAST-NEXT: vpermt2q %zmm0, %zmm17, %zmm3 -; AVX512DQ-FAST-NEXT: vmovdqu (%rsp), %ymm1 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vpshufb %ymm4, %ymm1, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm2 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm5 = ymm2[2,2,2,2,6,6,6,6] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1],ymm5[2],ymm0[3,4],ymm5[5],ymm0[6,7,8,9],ymm5[10],ymm0[11,12],ymm5[13],ymm0[14,15] -; AVX512DQ-FAST-NEXT: vpunpcklwd {{.*#+}} ymm5 = ymm1[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11] -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm6 = ymm2[0,1,1,3,4,5,5,7] -; AVX512DQ-FAST-NEXT: vmovdqa %ymm2, %ymm4 -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm5 = ymm6[0,1],ymm5[2],ymm6[3,4],ymm5[5],ymm6[6,7,8,9],ymm5[10],ymm6[11,12],ymm5[13],ymm6[14,15] -; AVX512DQ-FAST-NEXT: vpermt2q %zmm0, %zmm18, %zmm5 -; AVX512DQ-FAST-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm5 -; AVX512DQ-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm8 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vprold $16, %ymm8, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm2 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm2[1,2,2,3,5,6,6,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm3[0,1],ymm0[2],ymm3[3,4],ymm0[5],ymm3[6,7,8,9],ymm0[10],ymm3[11,12],ymm0[13],ymm3[14,15] -; AVX512DQ-FAST-NEXT: vpshufb %ymm7, %ymm8, %ymm3 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm6 = ymm2[0,0,2,1,4,4,6,5] -; AVX512DQ-FAST-NEXT: vmovdqa %ymm2, %ymm14 -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm3[0,1,2],ymm6[3],ymm3[4,5],ymm6[6],ymm3[7,8,9,10],ymm6[11],ymm3[12,13],ymm6[14],ymm3[15] -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm2 = [2,2,3,3,10,9,11,10] -; AVX512DQ-FAST-NEXT: vpermt2q %zmm0, %zmm2, %zmm3 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm30, %zmm12, %zmm0 -; AVX512DQ-FAST-NEXT: vbroadcasti32x8 {{.*#+}} zmm2 = [0,13,4,0,0,14,5,0,0,13,4,0,0,14,5,0] -; AVX512DQ-FAST-NEXT: # zmm2 = mem[0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7] -; AVX512DQ-FAST-NEXT: vpermd %zmm0, %zmm2, %zmm0 -; AVX512DQ-FAST-NEXT: vpternlogq $184, %zmm3, %zmm25, %zmm0 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm5, %zmm0 -; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vpshufb %ymm11, %ymm1, %ymm0 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm1 = ymm4[3,3,3,3,7,7,7,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0],ymm0[1],ymm1[2,3],ymm0[4],ymm1[5,6,7,8],ymm0[9],ymm1[10,11],ymm0[12],ymm1[13,14,15] -; AVX512DQ-FAST-NEXT: vmovdqa 96(%rcx), %xmm3 -; AVX512DQ-FAST-NEXT: vmovdqa 96(%rdx), %xmm0 -; AVX512DQ-FAST-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512DQ-FAST-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3] -; AVX512DQ-FAST-NEXT: vmovdqa64 %xmm3, %xmm29 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,2,3,0,1,2,3,6,7,4,5,6,7,4,5] -; AVX512DQ-FAST-NEXT: vpshufb %xmm2, %xmm0, %xmm0 -; AVX512DQ-FAST-NEXT: vmovdqa %xmm2, %xmm7 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm31 = [0,2,2,3,8,9,9,11] -; AVX512DQ-FAST-NEXT: vpermt2q %zmm0, %zmm31, %zmm1 -; AVX512DQ-FAST-NEXT: vpshufb %ymm9, %ymm13, %ymm0 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm2 = ymm28[3,3,3,3,7,7,7,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm2[0,1,2],ymm0[3],ymm2[4,5],ymm0[6],ymm2[7,8,9,10],ymm0[11],ymm2[12,13],ymm0[14],ymm2[15] -; AVX512DQ-FAST-NEXT: vmovdqa 96(%rsi), %xmm4 -; AVX512DQ-FAST-NEXT: vmovdqa 96(%rdi), %xmm3 -; AVX512DQ-FAST-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3] -; AVX512DQ-FAST-NEXT: vmovdqa64 %xmm4, %xmm26 -; AVX512DQ-FAST-NEXT: vmovdqa64 %xmm3, %xmm24 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} xmm9 = [0,1,2,3,4,5,4,5,6,7,10,11,8,9,10,11] -; AVX512DQ-FAST-NEXT: vpshufb %xmm9, %xmm2, %xmm2 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm3 = [2,1,3,3,8,8,9,9] -; AVX512DQ-FAST-NEXT: vpermt2q %zmm2, %zmm3, %zmm0 -; AVX512DQ-FAST-NEXT: vpternlogq $226, %zmm1, %zmm16, %zmm0 -; AVX512DQ-FAST-NEXT: vpshufb %ymm15, %ymm8, %ymm1 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm2 = ymm14[3,3,3,3,7,7,7,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm13 = ymm1[0,1],ymm2[2],ymm1[3,4],ymm2[5],ymm1[6,7,8,9],ymm2[10],ymm1[11,12],ymm2[13],ymm1[14,15] -; AVX512DQ-FAST-NEXT: vmovdqa 64(%rcx), %xmm2 -; AVX512DQ-FAST-NEXT: vmovdqa 64(%rdx), %xmm1 -; AVX512DQ-FAST-NEXT: vpbroadcastq {{.*#+}} xmm4 = [6,7,4,5,0,0,8,9,6,7,4,5,0,0,8,9] -; AVX512DQ-FAST-NEXT: vpshufb %xmm4, %xmm2, %xmm5 -; AVX512DQ-FAST-NEXT: vmovdqa %xmm4, %xmm8 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} xmm6 = xmm1[1,1,2,2] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} xmm5 = xmm6[0],xmm5[1],xmm6[2,3],xmm5[4],xmm6[5,6],xmm5[7] -; AVX512DQ-FAST-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7] -; AVX512DQ-FAST-NEXT: vmovdqa %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512DQ-FAST-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3] -; AVX512DQ-FAST-NEXT: vmovdqa %xmm7, %xmm14 -; AVX512DQ-FAST-NEXT: vpshufb %xmm7, %xmm1, %xmm2 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm1 = [0,1,1,3,8,8,9,9] -; AVX512DQ-FAST-NEXT: vpermt2q %zmm5, %zmm1, %zmm2 -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm1, %zmm11 -; AVX512DQ-FAST-NEXT: vmovdqa 64(%rdi), %xmm4 -; AVX512DQ-FAST-NEXT: vmovdqa %xmm4, (%rsp) # 16-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa 64(%rsi), %xmm6 -; AVX512DQ-FAST-NEXT: vmovdqa %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512DQ-FAST-NEXT: vprold $16, %xmm6, %xmm1 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[1,1,2,3] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} xmm5 = xmm5[0,1],xmm1[2],xmm5[3,4],xmm1[5],xmm5[6,7] -; AVX512DQ-FAST-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm4[0],xmm6[0],xmm4[1],xmm6[1],xmm4[2],xmm6[2],xmm4[3],xmm6[3] -; AVX512DQ-FAST-NEXT: vpshufb %xmm9, %xmm1, %xmm1 -; AVX512DQ-FAST-NEXT: vmovdqa %xmm9, %xmm3 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm27 = [0,0,1,1,8,8,10,9] -; AVX512DQ-FAST-NEXT: vpermt2q %zmm5, %zmm27, %zmm1 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm5 = [65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0] -; AVX512DQ-FAST-NEXT: vpternlogq $226, %zmm2, %zmm5, %zmm1 -; AVX512DQ-FAST-NEXT: vmovdqa64 %xmm20, %xmm2 -; AVX512DQ-FAST-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm2, %xmm2 # 16-byte Folded Reload -; AVX512DQ-FAST-NEXT: # xmm2 = xmm2[0],mem[0],xmm2[1],mem[1],xmm2[2],mem[2],xmm2[3],mem[3] -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} xmm7 = [0,1,2,3,6,7,4,5,6,7,4,5,12,13,14,15] -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} xmm10 = [0,1,2,3,8,9,10,11,14,15,12,13,14,15,12,13] -; AVX512DQ-FAST-NEXT: vpshufb %xmm10, %xmm2, %xmm6 -; AVX512DQ-FAST-NEXT: vpshufb %xmm7, %xmm2, %xmm2 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm16 = [0,0,0,1,8,9,9,11] -; AVX512DQ-FAST-NEXT: vpermt2q %zmm6, %zmm16, %zmm2 -; AVX512DQ-FAST-NEXT: vmovdqa (%rcx), %xmm4 -; AVX512DQ-FAST-NEXT: vmovdqa %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa (%rdx), %xmm9 -; AVX512DQ-FAST-NEXT: vmovdqa %xmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512DQ-FAST-NEXT: vpshufb %xmm8, %xmm4, %xmm6 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} xmm8 = xmm9[1,1,2,2] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} xmm6 = xmm8[0],xmm6[1],xmm8[2,3],xmm6[4],xmm8[5,6],xmm6[7] -; AVX512DQ-FAST-NEXT: vpunpcklwd {{.*#+}} xmm8 = xmm9[0],xmm4[0],xmm9[1],xmm4[1],xmm9[2],xmm4[2],xmm9[3],xmm4[3] -; AVX512DQ-FAST-NEXT: vpshufb %xmm14, %xmm8, %xmm8 -; AVX512DQ-FAST-NEXT: vmovdqa64 %xmm14, %xmm21 -; AVX512DQ-FAST-NEXT: vpermt2q %zmm6, %zmm11, %zmm8 -; AVX512DQ-FAST-NEXT: vmovdqa (%rdi), %xmm4 -; AVX512DQ-FAST-NEXT: vmovdqa %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa (%rsi), %xmm11 -; AVX512DQ-FAST-NEXT: vmovdqa %xmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512DQ-FAST-NEXT: vprold $16, %xmm11, %xmm6 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} xmm9 = xmm4[1,1,2,3] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} xmm6 = xmm9[0,1],xmm6[2],xmm9[3,4],xmm6[5],xmm9[6,7] -; AVX512DQ-FAST-NEXT: vpunpcklwd {{.*#+}} xmm9 = xmm4[0],xmm11[0],xmm4[1],xmm11[1],xmm4[2],xmm11[2],xmm4[3],xmm11[3] -; AVX512DQ-FAST-NEXT: vpshufb %xmm3, %xmm9, %xmm9 -; AVX512DQ-FAST-NEXT: vmovdqa64 %xmm3, %xmm28 -; AVX512DQ-FAST-NEXT: vpermt2q %zmm6, %zmm27, %zmm9 -; AVX512DQ-FAST-NEXT: vpternlogq $226, %zmm8, %zmm5, %zmm9 -; AVX512DQ-FAST-NEXT: vpbroadcastd 64(%rax), %ymm5 -; AVX512DQ-FAST-NEXT: vpbroadcastd 68(%rax), %ymm6 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm6, %zmm5, %zmm23 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm4 = [65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535] -; AVX512DQ-FAST-NEXT: vpternlogq $184, %zmm2, %zmm4, %zmm23 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm2 = [65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535] -; AVX512DQ-FAST-NEXT: vpternlogq $184, %zmm1, %zmm2, %zmm23 -; AVX512DQ-FAST-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload -; AVX512DQ-FAST-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1, %xmm1 # 16-byte Folded Reload -; AVX512DQ-FAST-NEXT: # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1],xmm1[2],mem[2],xmm1[3],mem[3] -; AVX512DQ-FAST-NEXT: vpshufb %xmm10, %xmm1, %xmm5 -; AVX512DQ-FAST-NEXT: vmovdqa64 %xmm10, %xmm22 -; AVX512DQ-FAST-NEXT: vpshufb %xmm7, %xmm1, %xmm1 -; AVX512DQ-FAST-NEXT: vmovdqa %xmm7, %xmm3 -; AVX512DQ-FAST-NEXT: vpermt2q %zmm5, %zmm16, %zmm1 -; AVX512DQ-FAST-NEXT: vpbroadcastd (%rax), %ymm5 -; AVX512DQ-FAST-NEXT: vpbroadcastd 4(%rax), %ymm6 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm6, %zmm5, %zmm20 -; AVX512DQ-FAST-NEXT: vpternlogq $184, %zmm1, %zmm4, %zmm20 -; AVX512DQ-FAST-NEXT: vpternlogq $184, %zmm9, %zmm2, %zmm20 -; AVX512DQ-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm4 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm4[10,11,8,9,u,u,u,u,u,u,u,u,u,u,u,u,26,27,24,25,u,u,u,u,26,27,24,25,u,u,u,u] -; AVX512DQ-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %ymm17 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm2 = ymm17[2,2,2,2,6,6,6,6] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0],ymm1[1],ymm2[2,3],ymm1[4],ymm2[5,6,7,8],ymm1[9],ymm2[10,11],ymm1[12],ymm2[13,14,15] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm4[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,20,21,18,19,20,21,24,25,26,27,22,23,22,23] -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm5 = ymm17[1,1,1,1,5,5,5,5] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm2 = ymm2[0,1],ymm5[2],ymm2[3,4],ymm5[5],ymm2[6,7,8,9],ymm5[10],ymm2[11,12],ymm5[13],ymm2[14,15] -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm5 = [2,2,2,3,8,10,10,11] -; AVX512DQ-FAST-NEXT: vpermt2q %zmm1, %zmm5, %zmm2 -; AVX512DQ-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm9 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm9[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,22,23,26,27,u,u,24,25,26,27,u,u,26,27,26,27] -; AVX512DQ-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm7 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm5 = ymm7[2,2,2,2,6,6,6,6] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0,1],ymm5[2],ymm1[3,4],ymm5[5],ymm1[6,7,8,9],ymm5[10],ymm1[11,12],ymm5[13],ymm1[14,15] -; AVX512DQ-FAST-NEXT: vpunpcklwd {{.*#+}} ymm5 = ymm9[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11] -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm6 = ymm7[0,1,1,3,4,5,5,7] -; AVX512DQ-FAST-NEXT: vmovdqa %ymm7, %ymm15 -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm8 = ymm6[0,1],ymm5[2],ymm6[3,4],ymm5[5],ymm6[6,7,8,9],ymm5[10],ymm6[11,12],ymm5[13],ymm6[14,15] -; AVX512DQ-FAST-NEXT: vpermt2q %zmm1, %zmm18, %zmm8 -; AVX512DQ-FAST-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm8 -; AVX512DQ-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm5 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vprold $16, %ymm5, %ymm1 -; AVX512DQ-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %ymm16 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm2 = ymm16[1,2,2,3,5,6,6,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0,1],ymm1[2],ymm2[3,4],ymm1[5],ymm2[6,7,8,9],ymm1[10],ymm2[11,12],ymm1[13],ymm2[14,15] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm5[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21] -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm5, %ymm18 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm5 = ymm16[0,0,2,1,4,4,6,5] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm2 = ymm2[0,1,2],ymm5[3],ymm2[4,5],ymm5[6],ymm2[7,8,9,10],ymm5[11],ymm2[12,13],ymm5[14],ymm2[15] -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm5 = [2,2,3,3,10,9,11,10] -; AVX512DQ-FAST-NEXT: vpermt2q %zmm1, %zmm5, %zmm2 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm5 = [2,2,2,3,8,8,8,9] -; AVX512DQ-FAST-NEXT: vmovdqa 96(%r9), %xmm11 -; AVX512DQ-FAST-NEXT: vmovdqa 96(%r8), %xmm7 -; AVX512DQ-FAST-NEXT: vpunpcklwd {{.*#+}} xmm10 = xmm7[0],xmm11[0],xmm7[1],xmm11[1],xmm7[2],xmm11[2],xmm7[3],xmm11[3] -; AVX512DQ-FAST-NEXT: vpshufb %xmm3, %xmm10, %xmm1 -; AVX512DQ-FAST-NEXT: vpermt2q %zmm1, %zmm5, %zmm13 -; AVX512DQ-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm14 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm14, %zmm19, %zmm1 -; AVX512DQ-FAST-NEXT: vbroadcasti32x8 {{.*#+}} zmm5 = [0,13,4,0,0,14,5,0,0,13,4,0,0,14,5,0] -; AVX512DQ-FAST-NEXT: # zmm5 = mem[0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7] -; AVX512DQ-FAST-NEXT: vpermd %zmm1, %zmm5, %zmm19 -; AVX512DQ-FAST-NEXT: vpternlogq $184, %zmm2, %zmm25, %zmm19 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm8, %zmm19 -; AVX512DQ-FAST-NEXT: vmovdqa 32(%rcx), %xmm12 -; AVX512DQ-FAST-NEXT: vmovdqa 32(%rdx), %xmm8 -; AVX512DQ-FAST-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm8[0],xmm12[0],xmm8[1],xmm12[1],xmm8[2],xmm12[2],xmm8[3],xmm12[3] -; AVX512DQ-FAST-NEXT: vmovdqa64 %xmm21, %xmm2 -; AVX512DQ-FAST-NEXT: vpshufb %xmm2, %xmm1, %xmm1 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm9[14,15,12,13,u,u,u,u,u,u,u,u,u,u,u,u,30,31,28,29,u,u,u,u,30,31,28,29,u,u,u,u] -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm9 = ymm15[3,3,3,3,7,7,7,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm15 = ymm9[0],ymm2[1],ymm9[2,3],ymm2[4],ymm9[5,6,7,8],ymm2[9],ymm9[10,11],ymm2[12],ymm9[13,14,15] -; AVX512DQ-FAST-NEXT: vpermt2q %zmm1, %zmm31, %zmm15 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} ymm31 = [6,7,3,3,7,7,6,7] -; AVX512DQ-FAST-NEXT: vpermd %ymm30, %ymm31, %ymm1 -; AVX512DQ-FAST-NEXT: vpbroadcastd 96(%rax), %ymm2 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm21 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm30 = [65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535] -; AVX512DQ-FAST-NEXT: vpternlogq $184, %zmm13, %zmm30, %zmm21 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm21 -; AVX512DQ-FAST-NEXT: vmovdqa64 %xmm24, %xmm2 -; AVX512DQ-FAST-NEXT: vmovdqa64 %xmm26, %xmm1 -; AVX512DQ-FAST-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7] -; AVX512DQ-FAST-NEXT: vprold $16, %xmm26, %xmm1 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} xmm2 = xmm24[1,1,2,3] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} xmm3 = xmm2[0,1],xmm1[2],xmm2[3,4],xmm1[5],xmm2[6,7] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm4[u,u,u,u,u,u,u,u,u,u,u,u,14,15,12,13,u,u,u,u,30,31,28,29,u,u,u,u,30,31,28,29] -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm2 = ymm17[3,3,3,3,7,7,7,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0,1,2],ymm1[3],ymm2[4,5],ymm1[6],ymm2[7,8,9,10],ymm1[11],ymm2[12,13],ymm1[14],ymm2[15] -; AVX512DQ-FAST-NEXT: vmovdqa 32(%rdi), %xmm5 -; AVX512DQ-FAST-NEXT: vmovdqa 32(%rsi), %xmm4 -; AVX512DQ-FAST-NEXT: vpunpcklwd {{.*#+}} xmm13 = xmm5[0],xmm4[0],xmm5[1],xmm4[1],xmm5[2],xmm4[2],xmm5[3],xmm4[3] -; AVX512DQ-FAST-NEXT: vmovdqa64 %xmm28, %xmm6 -; AVX512DQ-FAST-NEXT: vpshufb %xmm6, %xmm13, %xmm13 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm2 = [2,1,3,3,8,8,9,9] -; AVX512DQ-FAST-NEXT: vpermt2q %zmm13, %zmm2, %zmm1 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[4,5,2,3,4,5,6,7,8,9,10,11,10,11,8,9] -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm17 = [0,0,2,1,8,8,9,11] -; AVX512DQ-FAST-NEXT: vpermt2q %zmm0, %zmm17, %zmm3 -; AVX512DQ-FAST-NEXT: vmovdqa64 %xmm29, %xmm0 -; AVX512DQ-FAST-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm9 # 16-byte Reload -; AVX512DQ-FAST-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm9[4],xmm0[4],xmm9[5],xmm0[5],xmm9[6],xmm0[6],xmm9[7],xmm0[7] -; AVX512DQ-FAST-NEXT: vpbroadcastq {{.*#+}} xmm24 = [6,7,4,5,0,0,8,9,6,7,4,5,0,0,8,9] -; AVX512DQ-FAST-NEXT: vmovdqa64 %xmm24, %xmm13 -; AVX512DQ-FAST-NEXT: vpshufb %xmm13, %xmm0, %xmm0 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} xmm9 = xmm9[1,1,2,2] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} xmm0 = xmm9[0],xmm0[1],xmm9[2,3],xmm0[4],xmm9[5,6],xmm0[7] -; AVX512DQ-FAST-NEXT: vpshuflw {{.*#+}} xmm2 = xmm2[0,2,3,3,4,5,6,7] -; AVX512DQ-FAST-NEXT: vpermt2q %zmm2, %zmm27, %zmm0 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm25 = [65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535] -; AVX512DQ-FAST-NEXT: vpternlogq $226, %zmm3, %zmm25, %zmm0 -; AVX512DQ-FAST-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm7[4],xmm11[4],xmm7[5],xmm11[5],xmm7[6],xmm11[6],xmm7[7],xmm11[7] -; AVX512DQ-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm7 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512DQ-FAST-NEXT: vpternlogq $184, %ymm3, %ymm30, %ymm7 -; AVX512DQ-FAST-NEXT: vextracti64x4 $1, %zmm3, %ymm11 -; AVX512DQ-FAST-NEXT: vpshufb %xmm6, %xmm2, %xmm2 -; AVX512DQ-FAST-NEXT: vmovdqa64 %xmm22, %xmm13 -; AVX512DQ-FAST-NEXT: vpshufb %xmm13, %xmm10, %xmm3 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm28 = [0,1,1,3,8,8,9,9] -; AVX512DQ-FAST-NEXT: vpermt2q %zmm2, %zmm28, %zmm3 -; AVX512DQ-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm6 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vpshufhw {{.*#+}} ymm2 = ymm6[0,1,2,3,5,5,7,6,8,9,10,11,13,13,15,14] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm26 = ymm2[3,3,3,3] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm6[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,24,25,24,25,22,23,22,23,u,u,u,u,u,u,u,u] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm29 = ymm2[2,2,2,2] -; AVX512DQ-FAST-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm15, %zmm1 -; AVX512DQ-FAST-NEXT: vpbroadcastd 100(%rax), %ymm2 -; AVX512DQ-FAST-NEXT: vpbroadcastd 104(%rax), %ymm6 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm6, %zmm2, %zmm2 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm22 = [65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535] -; AVX512DQ-FAST-NEXT: vpternlogq $184, %zmm3, %zmm22, %zmm2 -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm18, %ymm3 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm3 = ymm3[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,26,27,28,29,26,27,28,29,26,27,28,29,30,31,30,31] -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} ymm6 = ymm16[3,3,3,3,7,7,7,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm10 = ymm3[0,1],ymm6[2],ymm3[3,4],ymm6[5],ymm3[6,7,8,9],ymm6[10],ymm3[11,12],ymm6[13],ymm3[14,15] -; AVX512DQ-FAST-NEXT: vmovdqa 32(%r9), %xmm15 -; AVX512DQ-FAST-NEXT: vmovdqa 32(%r8), %xmm3 -; AVX512DQ-FAST-NEXT: vpunpcklwd {{.*#+}} xmm6 = xmm3[0],xmm15[0],xmm3[1],xmm15[1],xmm3[2],xmm15[2],xmm3[3],xmm15[3] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} xmm9 = xmm6[0,1,2,3,6,7,4,5,6,7,4,5,12,13,14,15] -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm16 = [2,2,2,3,8,8,8,9] -; AVX512DQ-FAST-NEXT: vpermt2q %zmm9, %zmm16, %zmm10 -; AVX512DQ-FAST-NEXT: vpermd %ymm14, %ymm31, %ymm9 -; AVX512DQ-FAST-NEXT: vpbroadcastd 32(%rax), %ymm18 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm18, %zmm9, %zmm9 -; AVX512DQ-FAST-NEXT: vpternlogq $184, %zmm10, %zmm30, %zmm9 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm9 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm1 = [65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0] -; AVX512DQ-FAST-NEXT: vpternlogq $184, %zmm0, %zmm1, %zmm2 -; AVX512DQ-FAST-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm4[4],xmm5[4],xmm4[5],xmm5[5],xmm4[6],xmm5[6],xmm4[7],xmm5[7] -; AVX512DQ-FAST-NEXT: vprold $16, %xmm4, %xmm4 -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} xmm5 = xmm5[1,1,2,3] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} xmm4 = xmm5[0,1],xmm4[2],xmm5[3,4],xmm4[5],xmm5[6,7] -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} xmm10 = [4,5,2,3,4,5,6,7,8,9,10,11,10,11,8,9] -; AVX512DQ-FAST-NEXT: vpshufb %xmm10, %xmm0, %xmm0 -; AVX512DQ-FAST-NEXT: vpermt2q %zmm0, %zmm17, %zmm4 -; AVX512DQ-FAST-NEXT: vmovdqa64 %xmm24, %xmm0 -; AVX512DQ-FAST-NEXT: vpshufb %xmm0, %xmm12, %xmm0 -; AVX512DQ-FAST-NEXT: vpunpckhwd {{.*#+}} xmm5 = xmm8[4],xmm12[4],xmm8[5],xmm12[5],xmm8[6],xmm12[6],xmm8[7],xmm12[7] -; AVX512DQ-FAST-NEXT: vpshufd {{.*#+}} xmm8 = xmm8[1,1,2,2] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} xmm0 = xmm8[0],xmm0[1],xmm8[2,3],xmm0[4],xmm8[5,6],xmm0[7] -; AVX512DQ-FAST-NEXT: vpshuflw {{.*#+}} xmm5 = xmm5[0,2,3,3,4,5,6,7] -; AVX512DQ-FAST-NEXT: vpermt2q %zmm5, %zmm27, %zmm0 -; AVX512DQ-FAST-NEXT: vpternlogq $226, %zmm4, %zmm25, %zmm0 -; AVX512DQ-FAST-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm3[4],xmm15[4],xmm3[5],xmm15[5],xmm3[6],xmm15[6],xmm3[7],xmm15[7] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} xmm3 = xmm3[0,1,2,3,4,5,4,5,6,7,10,11,8,9,10,11] -; AVX512DQ-FAST-NEXT: vpshufb %xmm13, %xmm6, %xmm4 -; AVX512DQ-FAST-NEXT: vpermt2q %zmm3, %zmm28, %zmm4 -; AVX512DQ-FAST-NEXT: vpbroadcastd 36(%rax), %ymm3 -; AVX512DQ-FAST-NEXT: vpbroadcastd 40(%rax), %ymm5 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm5, %zmm3, %zmm3 -; AVX512DQ-FAST-NEXT: vpternlogq $184, %zmm4, %zmm22, %zmm3 -; AVX512DQ-FAST-NEXT: vpternlogq $184, %zmm0, %zmm1, %zmm3 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm0 = [65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535] -; AVX512DQ-FAST-NEXT: vpternlogq $184, %ymm7, %ymm0, %ymm29 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm0 = [65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535] -; AVX512DQ-FAST-NEXT: vpternlogd $226, 124(%r8){1to8}, %ymm0, %ymm11 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm0 = [0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535] -; AVX512DQ-FAST-NEXT: vpternlogq $184, %ymm11, %ymm0, %ymm26 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm26, %zmm0, %zmm1 -; AVX512DQ-FAST-NEXT: vshufi64x2 {{.*#+}} zmm1 = zmm29[0,1,2,3],zmm1[4,5,6,7] -; AVX512DQ-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm12 -; AVX512DQ-FAST-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload -; AVX512DQ-FAST-NEXT: vpunpckhwd (%rsp), %xmm1, %xmm1 # 16-byte Folded Reload -; AVX512DQ-FAST-NEXT: # xmm1 = xmm1[4],mem[4],xmm1[5],mem[5],xmm1[6],mem[6],xmm1[7],mem[7] -; AVX512DQ-FAST-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm4 # 16-byte Reload -; AVX512DQ-FAST-NEXT: vpunpckhwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm4, %xmm4 # 16-byte Folded Reload -; AVX512DQ-FAST-NEXT: # xmm4 = xmm4[4],mem[4],xmm4[5],mem[5],xmm4[6],mem[6],xmm4[7],mem[7] -; AVX512DQ-FAST-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm5 # 16-byte Reload -; AVX512DQ-FAST-NEXT: vpunpckhwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm5, %xmm5 # 16-byte Folded Reload -; AVX512DQ-FAST-NEXT: # xmm5 = xmm5[4],mem[4],xmm5[5],mem[5],xmm5[6],mem[6],xmm5[7],mem[7] -; AVX512DQ-FAST-NEXT: vpshufb %xmm10, %xmm1, %xmm1 -; AVX512DQ-FAST-NEXT: vpshufb %xmm10, %xmm5, %xmm5 -; AVX512DQ-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm6 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vpunpcklwd {{.*#+}} ymm6 = ymm6[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11] -; AVX512DQ-FAST-NEXT: vpshufd $212, {{[-0-9]+}}(%r{{[sb]}}p), %ymm7 # 32-byte Folded Reload -; AVX512DQ-FAST-NEXT: # ymm7 = mem[0,1,1,3,4,5,5,7] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm6 = ymm7[0,1],ymm6[2],ymm7[3,4],ymm6[5],ymm7[6,7,8,9],ymm6[10],ymm7[11,12],ymm6[13],ymm7[14,15] -; AVX512DQ-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm7 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm7 = ymm7[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,20,21,18,19,20,21,24,25,26,27,22,23,22,23] -; AVX512DQ-FAST-NEXT: vpshufd $85, {{[-0-9]+}}(%r{{[sb]}}p), %ymm8 # 32-byte Folded Reload -; AVX512DQ-FAST-NEXT: # ymm8 = mem[1,1,1,1,5,5,5,5] -; AVX512DQ-FAST-NEXT: vpblendw {{.*#+}} ymm7 = ymm7[0,1],ymm8[2],ymm7[3,4],ymm8[5],ymm7[6,7,8,9],ymm8[10],ymm7[11,12],ymm8[13],ymm7[14,15] -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm8 = [0,1,4,5,4,5,5,7] -; AVX512DQ-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm10 # 64-byte Reload -; AVX512DQ-FAST-NEXT: vpermd %ymm10, %ymm8, %ymm8 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm10 = ymm10[12,13],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm10[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm10[16,17],zero,zero -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm11 = [65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535] -; AVX512DQ-FAST-NEXT: vpandn %ymm8, %ymm11, %ymm8 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm8, %zmm10, %zmm8 -; AVX512DQ-FAST-NEXT: vpshuflw $248, {{[-0-9]+}}(%r{{[sb]}}p), %xmm10 # 16-byte Folded Reload -; AVX512DQ-FAST-NEXT: # xmm10 = mem[0,2,3,3,4,5,6,7] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm10 = ymm10[0,0,2,1] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,0,1,3] -; AVX512DQ-FAST-NEXT: vpshuflw {{.*#+}} xmm4 = xmm4[0,2,3,3,4,5,6,7] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm4 = ymm4[0,0,2,1] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm5 = ymm5[0,0,1,3] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm6 = ymm6[2,1,3,2] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm7 = ymm7[2,2,2,3] -; AVX512DQ-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512DQ-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm11, %zmm13 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm10, %zmm10 # 32-byte Folded Reload -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm1, %zmm1 # 32-byte Folded Reload -; AVX512DQ-FAST-NEXT: vpternlogq $226, %zmm10, %zmm25, %zmm1 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm4, %zmm4 # 32-byte Folded Reload -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm5, %zmm5 # 32-byte Folded Reload -; AVX512DQ-FAST-NEXT: vpternlogq $226, %zmm4, %zmm25, %zmm5 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm4 = [0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535] -; AVX512DQ-FAST-NEXT: vpternlogq $226, {{[-0-9]+}}(%r{{[sb]}}p), %zmm4, %zmm1 # 64-byte Folded Reload -; AVX512DQ-FAST-NEXT: vpternlogq $226, {{[-0-9]+}}(%r{{[sb]}}p), %zmm4, %zmm5 # 64-byte Folded Reload -; AVX512DQ-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm6, %zmm4, %zmm4 -; AVX512DQ-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm7, %zmm6, %zmm6 -; AVX512DQ-FAST-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm4, %zmm6 -; AVX512DQ-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQ-FAST-NEXT: vpternlogq $248, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm4 # 64-byte Folded Reload -; AVX512DQ-FAST-NEXT: vpternlogq $248, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm8 # 64-byte Folded Reload -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm6, %zmm8 -; AVX512DQ-FAST-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm8, 320(%rax) -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm3, 256(%rax) -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm9, 192(%rax) -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm19, 128(%rax) -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm20, (%rax) -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm23, 448(%rax) -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm2, 704(%rax) -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm21, 640(%rax) -; AVX512DQ-FAST-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-FAST-NEXT: vmovaps %zmm0, 576(%rax) -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm13, 384(%rax) -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm5, 64(%rax) -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm1, 512(%rax) -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm12, 832(%rax) -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm4, 768(%rax) -; AVX512DQ-FAST-NEXT: addq $1496, %rsp # imm = 0x5D8 -; AVX512DQ-FAST-NEXT: vzeroupper -; AVX512DQ-FAST-NEXT: retq +; AVX512F-FAST-LABEL: store_i16_stride7_vf64: +; AVX512F-FAST: # %bb.0: +; AVX512F-FAST-NEXT: subq $1496, %rsp # imm = 0x5D8 +; AVX512F-FAST-NEXT: vmovdqa 96(%rcx), %ymm0 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm15 = [128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128,128,128,128,128] +; AVX512F-FAST-NEXT: vpshufb %ymm15, %ymm0, %ymm2 +; AVX512F-FAST-NEXT: vmovdqa64 %ymm0, %ymm20 +; AVX512F-FAST-NEXT: vmovdqa 96(%rdx), %ymm9 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm0 = +; AVX512F-FAST-NEXT: vpshufb %ymm0, %ymm9, %ymm3 +; AVX512F-FAST-NEXT: vmovdqa %ymm0, %ymm10 +; AVX512F-FAST-NEXT: vporq %ymm2, %ymm3, %ymm16 +; AVX512F-FAST-NEXT: vmovdqa 96(%rsi), %ymm6 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm14 = [128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128,128,128,128,128,128,128,128,128] +; AVX512F-FAST-NEXT: vpshufb %ymm14, %ymm6, %ymm2 +; AVX512F-FAST-NEXT: vmovdqa 96(%rdi), %ymm7 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm11 = <12,13,14,15,128,128,u,u,u,u,u,u,u,u,u,u,16,17,128,128,u,u,u,u,u,u,u,u,16,17,18,19> +; AVX512F-FAST-NEXT: vpshufb %ymm11, %ymm7, %ymm3 +; AVX512F-FAST-NEXT: vporq %ymm2, %ymm3, %ymm17 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm3 = [128,128,128,128,128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128,128,128] +; AVX512F-FAST-NEXT: vmovdqa 64(%r9), %ymm0 +; AVX512F-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vpshufb %ymm3, %ymm0, %ymm2 +; AVX512F-FAST-NEXT: vmovdqa 64(%r8), %ymm0 +; AVX512F-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm5 = +; AVX512F-FAST-NEXT: vpshufb %ymm5, %ymm0, %ymm4 +; AVX512F-FAST-NEXT: vporq %ymm2, %ymm4, %ymm18 +; AVX512F-FAST-NEXT: vmovdqa 64(%rcx), %ymm0 +; AVX512F-FAST-NEXT: vmovdqu %ymm0, (%rsp) # 32-byte Spill +; AVX512F-FAST-NEXT: vpshufb %ymm15, %ymm0, %ymm8 +; AVX512F-FAST-NEXT: vmovdqa 64(%rdx), %ymm0 +; AVX512F-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vpshufb %ymm10, %ymm0, %ymm12 +; AVX512F-FAST-NEXT: vpor %ymm8, %ymm12, %ymm0 +; AVX512F-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vmovdqa 64(%rsi), %ymm0 +; AVX512F-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vpshufb %ymm14, %ymm0, %ymm0 +; AVX512F-FAST-NEXT: vmovdqa 64(%rdi), %ymm1 +; AVX512F-FAST-NEXT: vpshufb %ymm11, %ymm1, %ymm13 +; AVX512F-FAST-NEXT: vmovdqa64 %ymm1, %ymm28 +; AVX512F-FAST-NEXT: vpor %ymm0, %ymm13, %ymm0 +; AVX512F-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vmovdqa (%r9), %ymm0 +; AVX512F-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vpshufb %ymm3, %ymm0, %ymm0 +; AVX512F-FAST-NEXT: vmovdqa (%r8), %ymm1 +; AVX512F-FAST-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vpshufb %ymm5, %ymm1, %ymm13 +; AVX512F-FAST-NEXT: vporq %ymm0, %ymm13, %ymm19 +; AVX512F-FAST-NEXT: vmovdqa (%rcx), %ymm0 +; AVX512F-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vpshufb %ymm15, %ymm0, %ymm0 +; AVX512F-FAST-NEXT: vmovdqa (%rdx), %ymm1 +; AVX512F-FAST-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vmovdqa %ymm10, %ymm2 +; AVX512F-FAST-NEXT: vpshufb %ymm10, %ymm1, %ymm13 +; AVX512F-FAST-NEXT: vpor %ymm0, %ymm13, %ymm0 +; AVX512F-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vmovdqa (%rsi), %ymm0 +; AVX512F-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vpshufb %ymm14, %ymm0, %ymm0 +; AVX512F-FAST-NEXT: vmovdqa (%rdi), %ymm1 +; AVX512F-FAST-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vpshufb %ymm11, %ymm1, %ymm13 +; AVX512F-FAST-NEXT: vpor %ymm0, %ymm13, %ymm0 +; AVX512F-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vmovdqa 32(%rcx), %ymm10 +; AVX512F-FAST-NEXT: vpshufb %ymm15, %ymm10, %ymm0 +; AVX512F-FAST-NEXT: vmovdqa 32(%rdx), %ymm15 +; AVX512F-FAST-NEXT: vpshufb %ymm2, %ymm15, %ymm13 +; AVX512F-FAST-NEXT: vpor %ymm0, %ymm13, %ymm0 +; AVX512F-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-FAST-NEXT: vmovdqa 32(%rsi), %ymm8 +; AVX512F-FAST-NEXT: vpshufb %ymm14, %ymm8, %ymm0 +; AVX512F-FAST-NEXT: vmovdqa 32(%rdi), %ymm4 +; AVX512F-FAST-NEXT: vpshufb %ymm11, %ymm4, %ymm11 +; AVX512F-FAST-NEXT: vpor %ymm0, %ymm11, %ymm0 +; AVX512F-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-FAST-NEXT: vmovdqa 32(%r8), %ymm13 +; AVX512F-FAST-NEXT: vpshufb %ymm5, %ymm13, %ymm0 +; AVX512F-FAST-NEXT: vmovdqa 32(%r9), %ymm14 +; AVX512F-FAST-NEXT: vpshufb %ymm3, %ymm14, %ymm5 +; AVX512F-FAST-NEXT: vmovdqa %ymm3, %ymm12 +; AVX512F-FAST-NEXT: vporq %ymm5, %ymm0, %ymm21 +; AVX512F-FAST-NEXT: vmovdqa64 %ymm20, %ymm2 +; AVX512F-FAST-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11] +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm11 = ymm9[0,1,1,3,4,5,5,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm11[0,1],ymm0[2],ymm11[3,4],ymm0[5],ymm11[6,7,8,9],ymm0[10],ymm11[11,12],ymm0[13],ymm11[14,15] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,1,3,2] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm11 = ymm6[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,20,21,18,19,20,21,24,25,26,27,22,23,22,23] +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm7[1,1,1,1,5,5,5,5] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm11[0,1],ymm3[2],ymm11[3,4],ymm3[5],ymm11[6,7,8,9],ymm3[10],ymm11[11,12],ymm3[13],ymm11[14,15] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm3 = ymm3[2,2,2,3] +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm16, %zmm0 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm3, %zmm17, %zmm3 +; AVX512F-FAST-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm3 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm25 = [65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535] +; AVX512F-FAST-NEXT: vmovdqa 96(%r8), %ymm11 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm11[u,u],zero,zero,zero,zero,zero,zero,zero,zero,ymm11[14,15,u,u,u,u],zero,zero,zero,zero,zero,zero,zero,zero,ymm11[16,17,u,u,u,u],zero,zero +; AVX512F-FAST-NEXT: vpternlogq $248, %ymm25, %ymm3, %ymm0 +; AVX512F-FAST-NEXT: vmovdqa 96(%r9), %ymm5 +; AVX512F-FAST-NEXT: vmovdqu %ymm5, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vpshufb %ymm12, %ymm5, %ymm1 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm12 = [65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535] +; AVX512F-FAST-NEXT: vpternlogq $248, %ymm12, %ymm0, %ymm1 +; AVX512F-FAST-NEXT: vextracti64x4 $1, %zmm3, %ymm0 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm3 = +; AVX512F-FAST-NEXT: vpermd %ymm11, %ymm3, %ymm3 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm17 = [65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0] +; AVX512F-FAST-NEXT: vpternlogq $184, %ymm0, %ymm17, %ymm3 +; AVX512F-FAST-NEXT: vmovdqa64 %zmm17, %zmm22 +; AVX512F-FAST-NEXT: vprold $16, %ymm5, %ymm0 +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,2,2,2] +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm5 = [65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535] +; AVX512F-FAST-NEXT: vpternlogq $184, %ymm3, %ymm5, %ymm0 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm0 +; AVX512F-FAST-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm1[0,1,2,3],zmm0[4,5,6,7] +; AVX512F-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-FAST-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm1 = [0,1,4,5,4,5,5,7] +; AVX512F-FAST-NEXT: vmovdqa 96(%rax), %ymm0 +; AVX512F-FAST-NEXT: vpermd %ymm0, %ymm1, %ymm1 +; AVX512F-FAST-NEXT: vpandnq %ymm1, %ymm25, %ymm1 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm5 = [12,13,128,128,128,128,128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,128,128,128,128,16,17,128,128] +; AVX512F-FAST-NEXT: vpshufb %ymm5, %ymm0, %ymm3 +; AVX512F-FAST-NEXT: vmovdqa64 %ymm5, %ymm20 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm1, %zmm3, %zmm1 +; AVX512F-FAST-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm3 = +; AVX512F-FAST-NEXT: vpshufb %ymm3, %ymm6, %ymm1 +; AVX512F-FAST-NEXT: vmovdqa64 %ymm3, %ymm26 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm7[3,3,3,3,7,7,7,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm3[0,1,2],ymm1[3],ymm3[4,5],ymm1[6],ymm3[7,8,9,10],ymm1[11],ymm3[12,13],ymm1[14],ymm3[15] +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm5 = <10,11,8,9,u,u,u,u,u,u,u,u,u,u,u,u,26,27,24,25,u,u,u,u,26,27,24,25,u,u,u,u> +; AVX512F-FAST-NEXT: vpshufb %ymm5, %ymm6, %ymm3 +; AVX512F-FAST-NEXT: vmovdqa64 %ymm5, %ymm29 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm6 = ymm7[2,2,2,2,6,6,6,6] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm6[0],ymm3[1],ymm6[2,3],ymm3[4],ymm6[5,6,7,8],ymm3[9],ymm6[10,11],ymm3[12],ymm6[13,14,15] +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm6 = [0,2,2,3,10,9,11,11] +; AVX512F-FAST-NEXT: vpermt2q %zmm1, %zmm6, %zmm3 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm7 = <14,15,12,13,u,u,u,u,u,u,u,u,u,u,u,u,30,31,28,29,u,u,u,u,30,31,28,29,u,u,u,u> +; AVX512F-FAST-NEXT: vpshufb %ymm7, %ymm2, %ymm1 +; AVX512F-FAST-NEXT: vmovdqa64 %ymm7, %ymm27 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm7 = ymm9[3,3,3,3,7,7,7,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm7[0],ymm1[1],ymm7[2,3],ymm1[4],ymm7[5,6,7,8],ymm1[9],ymm7[10,11],ymm1[12],ymm7[13,14,15] +; AVX512F-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm5 = [22,23,26,27,0,0,24,25,26,27,0,0,26,27,26,27,22,23,26,27,0,0,24,25,26,27,0,0,26,27,26,27] +; AVX512F-FAST-NEXT: # ymm5 = mem[0,1,0,1] +; AVX512F-FAST-NEXT: vpshufb %ymm5, %ymm2, %ymm7 +; AVX512F-FAST-NEXT: vmovdqa64 %ymm5, %ymm16 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm9 = ymm9[2,2,2,2,6,6,6,6] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm7 = ymm7[0,1],ymm9[2],ymm7[3,4],ymm9[5],ymm7[6,7,8,9],ymm9[10],ymm7[11,12],ymm9[13],ymm7[14,15] +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm17 = [2,2,2,3,8,10,10,11] +; AVX512F-FAST-NEXT: vpermt2q %zmm1, %zmm17, %zmm7 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm1 = [65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535] +; AVX512F-FAST-NEXT: vpternlogq $226, %zmm3, %zmm1, %zmm7 +; AVX512F-FAST-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-FAST-NEXT: vmovdqa64 %zmm1, %zmm24 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm1 = <5,u,u,u,6,u,u,6> +; AVX512F-FAST-NEXT: vpermd %ymm11, %ymm1, %ymm1 +; AVX512F-FAST-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vmovdqa64 64(%rax), %zmm12 +; AVX512F-FAST-NEXT: vbroadcasti64x4 {{.*#+}} zmm3 = [30,5,0,0,31,6,0,31,30,5,0,0,31,6,0,31] +; AVX512F-FAST-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3] +; AVX512F-FAST-NEXT: vpermi2d %zmm12, %zmm0, %zmm3 +; AVX512F-FAST-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm23 = [65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535] +; AVX512F-FAST-NEXT: vpbroadcastd 72(%rax), %ymm0 +; AVX512F-FAST-NEXT: vpandnq %ymm0, %ymm23, %ymm0 +; AVX512F-FAST-NEXT: vmovdqa 64(%rax), %ymm7 +; AVX512F-FAST-NEXT: vmovdqa64 %ymm20, %ymm5 +; AVX512F-FAST-NEXT: vpshufb %ymm5, %ymm7, %ymm3 +; AVX512F-FAST-NEXT: vmovdqa64 %ymm7, %ymm30 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm11 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm18, %zmm0, %zmm0 +; AVX512F-FAST-NEXT: vmovdqa 64(%r9), %xmm1 +; AVX512F-FAST-NEXT: vmovdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512F-FAST-NEXT: vmovdqa 64(%r8), %xmm2 +; AVX512F-FAST-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7] +; AVX512F-FAST-NEXT: vmovdqa64 %xmm2, %xmm20 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} xmm9 = [0,1,2,3,4,5,4,5,6,7,10,11,8,9,10,11] +; AVX512F-FAST-NEXT: vpshufb %xmm9, %xmm3, %xmm3 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm18 = [0,0,1,1,12,13,14,15] +; AVX512F-FAST-NEXT: vpermt2q %zmm0, %zmm18, %zmm3 +; AVX512F-FAST-NEXT: vpternlogq $248, %zmm23, %zmm3, %zmm11 +; AVX512F-FAST-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-FAST-NEXT: vpbroadcastd 8(%rax), %ymm0 +; AVX512F-FAST-NEXT: vpandnq %ymm0, %ymm23, %ymm0 +; AVX512F-FAST-NEXT: vmovdqa (%rax), %ymm1 +; AVX512F-FAST-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vpshufb %ymm5, %ymm1, %ymm3 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm5 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm19, %zmm0, %zmm0 +; AVX512F-FAST-NEXT: vmovdqa (%r9), %xmm1 +; AVX512F-FAST-NEXT: vmovdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512F-FAST-NEXT: vmovdqa (%r8), %xmm2 +; AVX512F-FAST-NEXT: vmovdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512F-FAST-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7] +; AVX512F-FAST-NEXT: vpshufb %xmm9, %xmm3, %xmm3 +; AVX512F-FAST-NEXT: vpermt2q %zmm0, %zmm18, %zmm3 +; AVX512F-FAST-NEXT: vpternlogq $248, %zmm23, %zmm3, %zmm5 +; AVX512F-FAST-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-FAST-NEXT: vpbroadcastd {{.*#+}} ymm7 = [18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21] +; AVX512F-FAST-NEXT: vpshufb %ymm7, %ymm14, %ymm0 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm13[0,0,2,1,4,4,6,5] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2],ymm3[3],ymm0[4,5],ymm3[6],ymm0[7,8,9,10],ymm3[11],ymm0[12,13],ymm3[14],ymm0[15] +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm3 = <0,1,u,3,10,10,11,11> +; AVX512F-FAST-NEXT: vpermi2q %zmm0, %zmm21, %zmm3 +; AVX512F-FAST-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-FAST-NEXT: vmovdqu %ymm8, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vmovdqa64 %ymm26, %ymm9 +; AVX512F-FAST-NEXT: vpshufb %ymm9, %ymm8, %ymm0 +; AVX512F-FAST-NEXT: vmovdqu %ymm4, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm4[3,3,3,3,7,7,7,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm3[0,1,2],ymm0[3],ymm3[4,5],ymm0[6],ymm3[7,8,9,10],ymm0[11],ymm3[12,13],ymm0[14],ymm3[15] +; AVX512F-FAST-NEXT: vmovdqa64 %ymm29, %ymm1 +; AVX512F-FAST-NEXT: vpshufb %ymm1, %ymm8, %ymm3 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm5 = ymm4[2,2,2,2,6,6,6,6] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm5[0],ymm3[1],ymm5[2,3],ymm3[4],ymm5[5,6,7,8],ymm3[9],ymm5[10,11],ymm3[12],ymm5[13,14,15] +; AVX512F-FAST-NEXT: vpermt2q %zmm0, %zmm6, %zmm3 +; AVX512F-FAST-NEXT: vmovdqu %ymm10, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vmovdqa64 %ymm27, %ymm11 +; AVX512F-FAST-NEXT: vpshufb %ymm11, %ymm10, %ymm0 +; AVX512F-FAST-NEXT: vmovdqu %ymm15, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm5 = ymm15[3,3,3,3,7,7,7,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm5[0],ymm0[1],ymm5[2,3],ymm0[4],ymm5[5,6,7,8],ymm0[9],ymm5[10,11],ymm0[12],ymm5[13,14,15] +; AVX512F-FAST-NEXT: vmovdqa64 %ymm16, %ymm4 +; AVX512F-FAST-NEXT: vpshufb %ymm4, %ymm10, %ymm5 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm6 = ymm15[2,2,2,2,6,6,6,6] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm2 = ymm5[0,1],ymm6[2],ymm5[3,4],ymm6[5],ymm5[6,7,8,9],ymm6[10],ymm5[11,12],ymm6[13],ymm5[14,15] +; AVX512F-FAST-NEXT: vpermt2q %zmm0, %zmm17, %zmm2 +; AVX512F-FAST-NEXT: vmovdqa64 %zmm24, %zmm16 +; AVX512F-FAST-NEXT: vpternlogq $226, %zmm3, %zmm24, %zmm2 +; AVX512F-FAST-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm15 = [26,27,28,29,26,27,28,29,26,27,28,29,30,31,30,31,26,27,28,29,26,27,28,29,26,27,28,29,30,31,30,31] +; AVX512F-FAST-NEXT: # ymm15 = mem[0,1,0,1] +; AVX512F-FAST-NEXT: vpshufb %ymm15, %ymm14, %ymm0 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm13[3,3,3,3,7,7,7,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1],ymm3[2],ymm0[3,4],ymm3[5],ymm0[6,7,8,9],ymm3[10],ymm0[11,12],ymm3[13],ymm0[14,15] +; AVX512F-FAST-NEXT: vprold $16, %ymm14, %ymm3 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm5 = ymm13[1,2,2,3,5,6,6,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm5[0,1],ymm3[2],ymm5[3,4],ymm3[5],ymm5[6,7,8,9],ymm3[10],ymm5[11,12],ymm3[13],ymm5[14,15] +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm18 = [2,1,3,2,10,10,10,11] +; AVX512F-FAST-NEXT: vpermt2q %zmm0, %zmm18, %zmm3 +; AVX512F-FAST-NEXT: vmovdqa64 (%rax), %zmm19 +; AVX512F-FAST-NEXT: vbroadcasti64x4 {{.*#+}} zmm2 = [14,21,0,0,15,22,0,15,14,21,0,0,15,22,0,15] +; AVX512F-FAST-NEXT: # zmm2 = mem[0,1,2,3,0,1,2,3] +; AVX512F-FAST-NEXT: vmovdqa 32(%rax), %ymm0 +; AVX512F-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-FAST-NEXT: vpermi2d %zmm0, %zmm19, %zmm2 +; AVX512F-FAST-NEXT: vpternlogq $184, %zmm3, %zmm22, %zmm2 +; AVX512F-FAST-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm13 # 32-byte Reload +; AVX512F-FAST-NEXT: vpshufb %ymm1, %ymm13, %ymm0 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm28[2,2,2,2,6,6,6,6] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm3[0],ymm0[1],ymm3[2,3],ymm0[4],ymm3[5,6,7,8],ymm0[9],ymm3[10,11],ymm0[12],ymm3[13,14,15] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm3 = ymm13[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,20,21,18,19,20,21,24,25,26,27,22,23,22,23] +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm5 = ymm28[1,1,1,1,5,5,5,5] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm3[0,1],ymm5[2],ymm3[3,4],ymm5[5],ymm3[6,7,8,9],ymm5[10],ymm3[11,12],ymm5[13],ymm3[14,15] +; AVX512F-FAST-NEXT: vpermt2q %zmm0, %zmm17, %zmm3 +; AVX512F-FAST-NEXT: vmovdqu (%rsp), %ymm1 # 32-byte Reload +; AVX512F-FAST-NEXT: vpshufb %ymm4, %ymm1, %ymm0 +; AVX512F-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm2 # 32-byte Reload +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm5 = ymm2[2,2,2,2,6,6,6,6] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1],ymm5[2],ymm0[3,4],ymm5[5],ymm0[6,7,8,9],ymm5[10],ymm0[11,12],ymm5[13],ymm0[14,15] +; AVX512F-FAST-NEXT: vpunpcklwd {{.*#+}} ymm5 = ymm1[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11] +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm6 = ymm2[0,1,1,3,4,5,5,7] +; AVX512F-FAST-NEXT: vmovdqa %ymm2, %ymm4 +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm5 = ymm6[0,1],ymm5[2],ymm6[3,4],ymm5[5],ymm6[6,7,8,9],ymm5[10],ymm6[11,12],ymm5[13],ymm6[14,15] +; AVX512F-FAST-NEXT: vpermt2q %zmm0, %zmm18, %zmm5 +; AVX512F-FAST-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm5 +; AVX512F-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm8 # 32-byte Reload +; AVX512F-FAST-NEXT: vprold $16, %ymm8, %ymm0 +; AVX512F-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm2 # 32-byte Reload +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm3 = ymm2[1,2,2,3,5,6,6,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm3[0,1],ymm0[2],ymm3[3,4],ymm0[5],ymm3[6,7,8,9],ymm0[10],ymm3[11,12],ymm0[13],ymm3[14,15] +; AVX512F-FAST-NEXT: vpshufb %ymm7, %ymm8, %ymm3 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm6 = ymm2[0,0,2,1,4,4,6,5] +; AVX512F-FAST-NEXT: vmovdqa %ymm2, %ymm14 +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm3 = ymm3[0,1,2],ymm6[3],ymm3[4,5],ymm6[6],ymm3[7,8,9,10],ymm6[11],ymm3[12,13],ymm6[14],ymm3[15] +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm2 = [2,2,3,3,10,9,11,10] +; AVX512F-FAST-NEXT: vpermt2q %zmm0, %zmm2, %zmm3 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm30, %zmm12, %zmm0 +; AVX512F-FAST-NEXT: vbroadcasti64x4 {{.*#+}} zmm2 = [0,13,4,0,0,14,5,0,0,13,4,0,0,14,5,0] +; AVX512F-FAST-NEXT: # zmm2 = mem[0,1,2,3,0,1,2,3] +; AVX512F-FAST-NEXT: vpermd %zmm0, %zmm2, %zmm0 +; AVX512F-FAST-NEXT: vpternlogq $184, %zmm3, %zmm25, %zmm0 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm5, %zmm0 +; AVX512F-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-FAST-NEXT: vpshufb %ymm11, %ymm1, %ymm0 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm1 = ymm4[3,3,3,3,7,7,7,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0],ymm0[1],ymm1[2,3],ymm0[4],ymm1[5,6,7,8],ymm0[9],ymm1[10,11],ymm0[12],ymm1[13,14,15] +; AVX512F-FAST-NEXT: vmovdqa 96(%rcx), %xmm3 +; AVX512F-FAST-NEXT: vmovdqa 96(%rdx), %xmm0 +; AVX512F-FAST-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512F-FAST-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3] +; AVX512F-FAST-NEXT: vmovdqa64 %xmm3, %xmm29 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,2,3,0,1,2,3,6,7,4,5,6,7,4,5] +; AVX512F-FAST-NEXT: vpshufb %xmm2, %xmm0, %xmm0 +; AVX512F-FAST-NEXT: vmovdqa %xmm2, %xmm7 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm31 = [0,2,2,3,8,9,9,11] +; AVX512F-FAST-NEXT: vpermt2q %zmm0, %zmm31, %zmm1 +; AVX512F-FAST-NEXT: vpshufb %ymm9, %ymm13, %ymm0 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm2 = ymm28[3,3,3,3,7,7,7,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm2[0,1,2],ymm0[3],ymm2[4,5],ymm0[6],ymm2[7,8,9,10],ymm0[11],ymm2[12,13],ymm0[14],ymm2[15] +; AVX512F-FAST-NEXT: vmovdqa 96(%rsi), %xmm4 +; AVX512F-FAST-NEXT: vmovdqa 96(%rdi), %xmm3 +; AVX512F-FAST-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3] +; AVX512F-FAST-NEXT: vmovdqa64 %xmm4, %xmm26 +; AVX512F-FAST-NEXT: vmovdqa64 %xmm3, %xmm24 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} xmm9 = [0,1,2,3,4,5,4,5,6,7,10,11,8,9,10,11] +; AVX512F-FAST-NEXT: vpshufb %xmm9, %xmm2, %xmm2 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm3 = [2,1,3,3,8,8,9,9] +; AVX512F-FAST-NEXT: vpermt2q %zmm2, %zmm3, %zmm0 +; AVX512F-FAST-NEXT: vpternlogq $226, %zmm1, %zmm16, %zmm0 +; AVX512F-FAST-NEXT: vpshufb %ymm15, %ymm8, %ymm1 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm2 = ymm14[3,3,3,3,7,7,7,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm13 = ymm1[0,1],ymm2[2],ymm1[3,4],ymm2[5],ymm1[6,7,8,9],ymm2[10],ymm1[11,12],ymm2[13],ymm1[14,15] +; AVX512F-FAST-NEXT: vmovdqa 64(%rcx), %xmm2 +; AVX512F-FAST-NEXT: vmovdqa 64(%rdx), %xmm1 +; AVX512F-FAST-NEXT: vpbroadcastq {{.*#+}} xmm4 = [6,7,4,5,0,0,8,9,6,7,4,5,0,0,8,9] +; AVX512F-FAST-NEXT: vpshufb %xmm4, %xmm2, %xmm5 +; AVX512F-FAST-NEXT: vmovdqa %xmm4, %xmm8 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} xmm6 = xmm1[1,1,2,2] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} xmm5 = xmm6[0],xmm5[1],xmm6[2,3],xmm5[4],xmm6[5,6],xmm5[7] +; AVX512F-FAST-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7] +; AVX512F-FAST-NEXT: vmovdqa %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512F-FAST-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3] +; AVX512F-FAST-NEXT: vmovdqa %xmm7, %xmm14 +; AVX512F-FAST-NEXT: vpshufb %xmm7, %xmm1, %xmm2 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm1 = [0,1,1,3,8,8,9,9] +; AVX512F-FAST-NEXT: vpermt2q %zmm5, %zmm1, %zmm2 +; AVX512F-FAST-NEXT: vmovdqa64 %zmm1, %zmm11 +; AVX512F-FAST-NEXT: vmovdqa 64(%rdi), %xmm4 +; AVX512F-FAST-NEXT: vmovdqa %xmm4, (%rsp) # 16-byte Spill +; AVX512F-FAST-NEXT: vmovdqa 64(%rsi), %xmm6 +; AVX512F-FAST-NEXT: vmovdqa %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512F-FAST-NEXT: vprold $16, %xmm6, %xmm1 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[1,1,2,3] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} xmm5 = xmm5[0,1],xmm1[2],xmm5[3,4],xmm1[5],xmm5[6,7] +; AVX512F-FAST-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm4[0],xmm6[0],xmm4[1],xmm6[1],xmm4[2],xmm6[2],xmm4[3],xmm6[3] +; AVX512F-FAST-NEXT: vpshufb %xmm9, %xmm1, %xmm1 +; AVX512F-FAST-NEXT: vmovdqa %xmm9, %xmm3 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm27 = [0,0,1,1,8,8,10,9] +; AVX512F-FAST-NEXT: vpermt2q %zmm5, %zmm27, %zmm1 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm5 = [65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0] +; AVX512F-FAST-NEXT: vpternlogq $226, %zmm2, %zmm5, %zmm1 +; AVX512F-FAST-NEXT: vmovdqa64 %xmm20, %xmm2 +; AVX512F-FAST-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm2, %xmm2 # 16-byte Folded Reload +; AVX512F-FAST-NEXT: # xmm2 = xmm2[0],mem[0],xmm2[1],mem[1],xmm2[2],mem[2],xmm2[3],mem[3] +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} xmm7 = [0,1,2,3,6,7,4,5,6,7,4,5,12,13,14,15] +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} xmm10 = [0,1,2,3,8,9,10,11,14,15,12,13,14,15,12,13] +; AVX512F-FAST-NEXT: vpshufb %xmm10, %xmm2, %xmm6 +; AVX512F-FAST-NEXT: vpshufb %xmm7, %xmm2, %xmm2 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm16 = [0,0,0,1,8,9,9,11] +; AVX512F-FAST-NEXT: vpermt2q %zmm6, %zmm16, %zmm2 +; AVX512F-FAST-NEXT: vmovdqa (%rcx), %xmm4 +; AVX512F-FAST-NEXT: vmovdqa %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512F-FAST-NEXT: vmovdqa (%rdx), %xmm9 +; AVX512F-FAST-NEXT: vmovdqa %xmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512F-FAST-NEXT: vpshufb %xmm8, %xmm4, %xmm6 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} xmm8 = xmm9[1,1,2,2] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} xmm6 = xmm8[0],xmm6[1],xmm8[2,3],xmm6[4],xmm8[5,6],xmm6[7] +; AVX512F-FAST-NEXT: vpunpcklwd {{.*#+}} xmm8 = xmm9[0],xmm4[0],xmm9[1],xmm4[1],xmm9[2],xmm4[2],xmm9[3],xmm4[3] +; AVX512F-FAST-NEXT: vpshufb %xmm14, %xmm8, %xmm8 +; AVX512F-FAST-NEXT: vmovdqa64 %xmm14, %xmm21 +; AVX512F-FAST-NEXT: vpermt2q %zmm6, %zmm11, %zmm8 +; AVX512F-FAST-NEXT: vmovdqa (%rdi), %xmm4 +; AVX512F-FAST-NEXT: vmovdqa %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512F-FAST-NEXT: vmovdqa (%rsi), %xmm11 +; AVX512F-FAST-NEXT: vmovdqa %xmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512F-FAST-NEXT: vprold $16, %xmm11, %xmm6 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} xmm9 = xmm4[1,1,2,3] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} xmm6 = xmm9[0,1],xmm6[2],xmm9[3,4],xmm6[5],xmm9[6,7] +; AVX512F-FAST-NEXT: vpunpcklwd {{.*#+}} xmm9 = xmm4[0],xmm11[0],xmm4[1],xmm11[1],xmm4[2],xmm11[2],xmm4[3],xmm11[3] +; AVX512F-FAST-NEXT: vpshufb %xmm3, %xmm9, %xmm9 +; AVX512F-FAST-NEXT: vmovdqa64 %xmm3, %xmm28 +; AVX512F-FAST-NEXT: vpermt2q %zmm6, %zmm27, %zmm9 +; AVX512F-FAST-NEXT: vpternlogq $226, %zmm8, %zmm5, %zmm9 +; AVX512F-FAST-NEXT: vpbroadcastd 64(%rax), %ymm5 +; AVX512F-FAST-NEXT: vpbroadcastd 68(%rax), %ymm6 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm6, %zmm5, %zmm23 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm4 = [65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535] +; AVX512F-FAST-NEXT: vpternlogq $184, %zmm2, %zmm4, %zmm23 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm2 = [65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535] +; AVX512F-FAST-NEXT: vpternlogq $184, %zmm1, %zmm2, %zmm23 +; AVX512F-FAST-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload +; AVX512F-FAST-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1, %xmm1 # 16-byte Folded Reload +; AVX512F-FAST-NEXT: # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1],xmm1[2],mem[2],xmm1[3],mem[3] +; AVX512F-FAST-NEXT: vpshufb %xmm10, %xmm1, %xmm5 +; AVX512F-FAST-NEXT: vmovdqa64 %xmm10, %xmm22 +; AVX512F-FAST-NEXT: vpshufb %xmm7, %xmm1, %xmm1 +; AVX512F-FAST-NEXT: vmovdqa %xmm7, %xmm3 +; AVX512F-FAST-NEXT: vpermt2q %zmm5, %zmm16, %zmm1 +; AVX512F-FAST-NEXT: vpbroadcastd (%rax), %ymm5 +; AVX512F-FAST-NEXT: vpbroadcastd 4(%rax), %ymm6 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm6, %zmm5, %zmm20 +; AVX512F-FAST-NEXT: vpternlogq $184, %zmm1, %zmm4, %zmm20 +; AVX512F-FAST-NEXT: vpternlogq $184, %zmm9, %zmm2, %zmm20 +; AVX512F-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm4 # 32-byte Reload +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm4[10,11,8,9,u,u,u,u,u,u,u,u,u,u,u,u,26,27,24,25,u,u,u,u,26,27,24,25,u,u,u,u] +; AVX512F-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %ymm17 # 32-byte Reload +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm2 = ymm17[2,2,2,2,6,6,6,6] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0],ymm1[1],ymm2[2,3],ymm1[4],ymm2[5,6,7,8],ymm1[9],ymm2[10,11],ymm1[12],ymm2[13,14,15] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm4[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,20,21,18,19,20,21,24,25,26,27,22,23,22,23] +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm5 = ymm17[1,1,1,1,5,5,5,5] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm2 = ymm2[0,1],ymm5[2],ymm2[3,4],ymm5[5],ymm2[6,7,8,9],ymm5[10],ymm2[11,12],ymm5[13],ymm2[14,15] +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm5 = [2,2,2,3,8,10,10,11] +; AVX512F-FAST-NEXT: vpermt2q %zmm1, %zmm5, %zmm2 +; AVX512F-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm9 # 32-byte Reload +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm9[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,22,23,26,27,u,u,24,25,26,27,u,u,26,27,26,27] +; AVX512F-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm7 # 32-byte Reload +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm5 = ymm7[2,2,2,2,6,6,6,6] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0,1],ymm5[2],ymm1[3,4],ymm5[5],ymm1[6,7,8,9],ymm5[10],ymm1[11,12],ymm5[13],ymm1[14,15] +; AVX512F-FAST-NEXT: vpunpcklwd {{.*#+}} ymm5 = ymm9[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11] +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm6 = ymm7[0,1,1,3,4,5,5,7] +; AVX512F-FAST-NEXT: vmovdqa %ymm7, %ymm15 +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm8 = ymm6[0,1],ymm5[2],ymm6[3,4],ymm5[5],ymm6[6,7,8,9],ymm5[10],ymm6[11,12],ymm5[13],ymm6[14,15] +; AVX512F-FAST-NEXT: vpermt2q %zmm1, %zmm18, %zmm8 +; AVX512F-FAST-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm8 +; AVX512F-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm5 # 32-byte Reload +; AVX512F-FAST-NEXT: vprold $16, %ymm5, %ymm1 +; AVX512F-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %ymm16 # 32-byte Reload +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm2 = ymm16[1,2,2,3,5,6,6,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0,1],ymm1[2],ymm2[3,4],ymm1[5],ymm2[6,7,8,9],ymm1[10],ymm2[11,12],ymm1[13],ymm2[14,15] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm5[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,20,21,18,19,20,21,18,19,20,21,18,19,20,21] +; AVX512F-FAST-NEXT: vmovdqa64 %ymm5, %ymm18 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm5 = ymm16[0,0,2,1,4,4,6,5] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm2 = ymm2[0,1,2],ymm5[3],ymm2[4,5],ymm5[6],ymm2[7,8,9,10],ymm5[11],ymm2[12,13],ymm5[14],ymm2[15] +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm5 = [2,2,3,3,10,9,11,10] +; AVX512F-FAST-NEXT: vpermt2q %zmm1, %zmm5, %zmm2 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm5 = [2,2,2,3,8,8,8,9] +; AVX512F-FAST-NEXT: vmovdqa 96(%r9), %xmm11 +; AVX512F-FAST-NEXT: vmovdqa 96(%r8), %xmm7 +; AVX512F-FAST-NEXT: vpunpcklwd {{.*#+}} xmm10 = xmm7[0],xmm11[0],xmm7[1],xmm11[1],xmm7[2],xmm11[2],xmm7[3],xmm11[3] +; AVX512F-FAST-NEXT: vpshufb %xmm3, %xmm10, %xmm1 +; AVX512F-FAST-NEXT: vpermt2q %zmm1, %zmm5, %zmm13 +; AVX512F-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm14 # 32-byte Reload +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm14, %zmm19, %zmm1 +; AVX512F-FAST-NEXT: vbroadcasti64x4 {{.*#+}} zmm5 = [0,13,4,0,0,14,5,0,0,13,4,0,0,14,5,0] +; AVX512F-FAST-NEXT: # zmm5 = mem[0,1,2,3,0,1,2,3] +; AVX512F-FAST-NEXT: vpermd %zmm1, %zmm5, %zmm19 +; AVX512F-FAST-NEXT: vpternlogq $184, %zmm2, %zmm25, %zmm19 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm8, %zmm19 +; AVX512F-FAST-NEXT: vmovdqa 32(%rcx), %xmm12 +; AVX512F-FAST-NEXT: vmovdqa 32(%rdx), %xmm8 +; AVX512F-FAST-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm8[0],xmm12[0],xmm8[1],xmm12[1],xmm8[2],xmm12[2],xmm8[3],xmm12[3] +; AVX512F-FAST-NEXT: vmovdqa64 %xmm21, %xmm2 +; AVX512F-FAST-NEXT: vpshufb %xmm2, %xmm1, %xmm1 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm9[14,15,12,13,u,u,u,u,u,u,u,u,u,u,u,u,30,31,28,29,u,u,u,u,30,31,28,29,u,u,u,u] +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm9 = ymm15[3,3,3,3,7,7,7,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm15 = ymm9[0],ymm2[1],ymm9[2,3],ymm2[4],ymm9[5,6,7,8],ymm2[9],ymm9[10,11],ymm2[12],ymm9[13,14,15] +; AVX512F-FAST-NEXT: vpermt2q %zmm1, %zmm31, %zmm15 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} ymm31 = [6,7,3,3,7,7,6,7] +; AVX512F-FAST-NEXT: vpermd %ymm30, %ymm31, %ymm1 +; AVX512F-FAST-NEXT: vpbroadcastd 96(%rax), %ymm2 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm21 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm30 = [65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535] +; AVX512F-FAST-NEXT: vpternlogq $184, %zmm13, %zmm30, %zmm21 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm21 +; AVX512F-FAST-NEXT: vmovdqa64 %xmm24, %xmm2 +; AVX512F-FAST-NEXT: vmovdqa64 %xmm26, %xmm1 +; AVX512F-FAST-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7] +; AVX512F-FAST-NEXT: vprold $16, %xmm26, %xmm1 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} xmm2 = xmm24[1,1,2,3] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} xmm3 = xmm2[0,1],xmm1[2],xmm2[3,4],xmm1[5],xmm2[6,7] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm4[u,u,u,u,u,u,u,u,u,u,u,u,14,15,12,13,u,u,u,u,30,31,28,29,u,u,u,u,30,31,28,29] +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm2 = ymm17[3,3,3,3,7,7,7,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0,1,2],ymm1[3],ymm2[4,5],ymm1[6],ymm2[7,8,9,10],ymm1[11],ymm2[12,13],ymm1[14],ymm2[15] +; AVX512F-FAST-NEXT: vmovdqa 32(%rdi), %xmm5 +; AVX512F-FAST-NEXT: vmovdqa 32(%rsi), %xmm4 +; AVX512F-FAST-NEXT: vpunpcklwd {{.*#+}} xmm13 = xmm5[0],xmm4[0],xmm5[1],xmm4[1],xmm5[2],xmm4[2],xmm5[3],xmm4[3] +; AVX512F-FAST-NEXT: vmovdqa64 %xmm28, %xmm6 +; AVX512F-FAST-NEXT: vpshufb %xmm6, %xmm13, %xmm13 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm2 = [2,1,3,3,8,8,9,9] +; AVX512F-FAST-NEXT: vpermt2q %zmm13, %zmm2, %zmm1 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[4,5,2,3,4,5,6,7,8,9,10,11,10,11,8,9] +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm17 = [0,0,2,1,8,8,9,11] +; AVX512F-FAST-NEXT: vpermt2q %zmm0, %zmm17, %zmm3 +; AVX512F-FAST-NEXT: vmovdqa64 %xmm29, %xmm0 +; AVX512F-FAST-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm9 # 16-byte Reload +; AVX512F-FAST-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm9[4],xmm0[4],xmm9[5],xmm0[5],xmm9[6],xmm0[6],xmm9[7],xmm0[7] +; AVX512F-FAST-NEXT: vpbroadcastq {{.*#+}} xmm24 = [6,7,4,5,0,0,8,9,6,7,4,5,0,0,8,9] +; AVX512F-FAST-NEXT: vmovdqa64 %xmm24, %xmm13 +; AVX512F-FAST-NEXT: vpshufb %xmm13, %xmm0, %xmm0 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} xmm9 = xmm9[1,1,2,2] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} xmm0 = xmm9[0],xmm0[1],xmm9[2,3],xmm0[4],xmm9[5,6],xmm0[7] +; AVX512F-FAST-NEXT: vpshuflw {{.*#+}} xmm2 = xmm2[0,2,3,3,4,5,6,7] +; AVX512F-FAST-NEXT: vpermt2q %zmm2, %zmm27, %zmm0 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm25 = [65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535,65535,0,0,65535,65535,65535,65535] +; AVX512F-FAST-NEXT: vpternlogq $226, %zmm3, %zmm25, %zmm0 +; AVX512F-FAST-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm7[4],xmm11[4],xmm7[5],xmm11[5],xmm7[6],xmm11[6],xmm7[7],xmm11[7] +; AVX512F-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm7 # 32-byte Reload +; AVX512F-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload +; AVX512F-FAST-NEXT: vpternlogq $184, %ymm3, %ymm30, %ymm7 +; AVX512F-FAST-NEXT: vextracti64x4 $1, %zmm3, %ymm11 +; AVX512F-FAST-NEXT: vpshufb %xmm6, %xmm2, %xmm2 +; AVX512F-FAST-NEXT: vmovdqa64 %xmm22, %xmm13 +; AVX512F-FAST-NEXT: vpshufb %xmm13, %xmm10, %xmm3 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm28 = [0,1,1,3,8,8,9,9] +; AVX512F-FAST-NEXT: vpermt2q %zmm2, %zmm28, %zmm3 +; AVX512F-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm6 # 32-byte Reload +; AVX512F-FAST-NEXT: vpshufhw {{.*#+}} ymm2 = ymm6[0,1,2,3,5,5,7,6,8,9,10,11,13,13,15,14] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm26 = ymm2[3,3,3,3] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm6[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,24,25,24,25,22,23,22,23,u,u,u,u,u,u,u,u] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm29 = ymm2[2,2,2,2] +; AVX512F-FAST-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm15, %zmm1 +; AVX512F-FAST-NEXT: vpbroadcastd 100(%rax), %ymm2 +; AVX512F-FAST-NEXT: vpbroadcastd 104(%rax), %ymm6 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm6, %zmm2, %zmm2 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm22 = [65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535] +; AVX512F-FAST-NEXT: vpternlogq $184, %zmm3, %zmm22, %zmm2 +; AVX512F-FAST-NEXT: vmovdqa64 %ymm18, %ymm3 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm3 = ymm3[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,26,27,28,29,26,27,28,29,26,27,28,29,30,31,30,31] +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} ymm6 = ymm16[3,3,3,3,7,7,7,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm10 = ymm3[0,1],ymm6[2],ymm3[3,4],ymm6[5],ymm3[6,7,8,9],ymm6[10],ymm3[11,12],ymm6[13],ymm3[14,15] +; AVX512F-FAST-NEXT: vmovdqa 32(%r9), %xmm15 +; AVX512F-FAST-NEXT: vmovdqa 32(%r8), %xmm3 +; AVX512F-FAST-NEXT: vpunpcklwd {{.*#+}} xmm6 = xmm3[0],xmm15[0],xmm3[1],xmm15[1],xmm3[2],xmm15[2],xmm3[3],xmm15[3] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} xmm9 = xmm6[0,1,2,3,6,7,4,5,6,7,4,5,12,13,14,15] +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm16 = [2,2,2,3,8,8,8,9] +; AVX512F-FAST-NEXT: vpermt2q %zmm9, %zmm16, %zmm10 +; AVX512F-FAST-NEXT: vpermd %ymm14, %ymm31, %ymm9 +; AVX512F-FAST-NEXT: vpbroadcastd 32(%rax), %ymm18 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm18, %zmm9, %zmm9 +; AVX512F-FAST-NEXT: vpternlogq $184, %zmm10, %zmm30, %zmm9 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm9 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm1 = [65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0] +; AVX512F-FAST-NEXT: vpternlogq $184, %zmm0, %zmm1, %zmm2 +; AVX512F-FAST-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm4[4],xmm5[4],xmm4[5],xmm5[5],xmm4[6],xmm5[6],xmm4[7],xmm5[7] +; AVX512F-FAST-NEXT: vprold $16, %xmm4, %xmm4 +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} xmm5 = xmm5[1,1,2,3] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} xmm4 = xmm5[0,1],xmm4[2],xmm5[3,4],xmm4[5],xmm5[6,7] +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} xmm10 = [4,5,2,3,4,5,6,7,8,9,10,11,10,11,8,9] +; AVX512F-FAST-NEXT: vpshufb %xmm10, %xmm0, %xmm0 +; AVX512F-FAST-NEXT: vpermt2q %zmm0, %zmm17, %zmm4 +; AVX512F-FAST-NEXT: vmovdqa64 %xmm24, %xmm0 +; AVX512F-FAST-NEXT: vpshufb %xmm0, %xmm12, %xmm0 +; AVX512F-FAST-NEXT: vpunpckhwd {{.*#+}} xmm5 = xmm8[4],xmm12[4],xmm8[5],xmm12[5],xmm8[6],xmm12[6],xmm8[7],xmm12[7] +; AVX512F-FAST-NEXT: vpshufd {{.*#+}} xmm8 = xmm8[1,1,2,2] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} xmm0 = xmm8[0],xmm0[1],xmm8[2,3],xmm0[4],xmm8[5,6],xmm0[7] +; AVX512F-FAST-NEXT: vpshuflw {{.*#+}} xmm5 = xmm5[0,2,3,3,4,5,6,7] +; AVX512F-FAST-NEXT: vpermt2q %zmm5, %zmm27, %zmm0 +; AVX512F-FAST-NEXT: vpternlogq $226, %zmm4, %zmm25, %zmm0 +; AVX512F-FAST-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm3[4],xmm15[4],xmm3[5],xmm15[5],xmm3[6],xmm15[6],xmm3[7],xmm15[7] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} xmm3 = xmm3[0,1,2,3,4,5,4,5,6,7,10,11,8,9,10,11] +; AVX512F-FAST-NEXT: vpshufb %xmm13, %xmm6, %xmm4 +; AVX512F-FAST-NEXT: vpermt2q %zmm3, %zmm28, %zmm4 +; AVX512F-FAST-NEXT: vpbroadcastd 36(%rax), %ymm3 +; AVX512F-FAST-NEXT: vpbroadcastd 40(%rax), %ymm5 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm5, %zmm3, %zmm3 +; AVX512F-FAST-NEXT: vpternlogq $184, %zmm4, %zmm22, %zmm3 +; AVX512F-FAST-NEXT: vpternlogq $184, %zmm0, %zmm1, %zmm3 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm0 = [65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535] +; AVX512F-FAST-NEXT: vpternlogq $184, %ymm7, %ymm0, %ymm29 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm0 = [65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535] +; AVX512F-FAST-NEXT: vpternlogd $226, 124(%r8){1to8}, %ymm0, %ymm11 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm0 = [0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535] +; AVX512F-FAST-NEXT: vpternlogq $184, %ymm11, %ymm0, %ymm26 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm26, %zmm0, %zmm1 +; AVX512F-FAST-NEXT: vshufi64x2 {{.*#+}} zmm1 = zmm29[0,1,2,3],zmm1[4,5,6,7] +; AVX512F-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm12 +; AVX512F-FAST-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload +; AVX512F-FAST-NEXT: vpunpckhwd (%rsp), %xmm1, %xmm1 # 16-byte Folded Reload +; AVX512F-FAST-NEXT: # xmm1 = xmm1[4],mem[4],xmm1[5],mem[5],xmm1[6],mem[6],xmm1[7],mem[7] +; AVX512F-FAST-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm4 # 16-byte Reload +; AVX512F-FAST-NEXT: vpunpckhwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm4, %xmm4 # 16-byte Folded Reload +; AVX512F-FAST-NEXT: # xmm4 = xmm4[4],mem[4],xmm4[5],mem[5],xmm4[6],mem[6],xmm4[7],mem[7] +; AVX512F-FAST-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm5 # 16-byte Reload +; AVX512F-FAST-NEXT: vpunpckhwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm5, %xmm5 # 16-byte Folded Reload +; AVX512F-FAST-NEXT: # xmm5 = xmm5[4],mem[4],xmm5[5],mem[5],xmm5[6],mem[6],xmm5[7],mem[7] +; AVX512F-FAST-NEXT: vpshufb %xmm10, %xmm1, %xmm1 +; AVX512F-FAST-NEXT: vpshufb %xmm10, %xmm5, %xmm5 +; AVX512F-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm6 # 32-byte Reload +; AVX512F-FAST-NEXT: vpunpcklwd {{.*#+}} ymm6 = ymm6[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11] +; AVX512F-FAST-NEXT: vpshufd $212, {{[-0-9]+}}(%r{{[sb]}}p), %ymm7 # 32-byte Folded Reload +; AVX512F-FAST-NEXT: # ymm7 = mem[0,1,1,3,4,5,5,7] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm6 = ymm7[0,1],ymm6[2],ymm7[3,4],ymm6[5],ymm7[6,7,8,9],ymm6[10],ymm7[11,12],ymm6[13],ymm7[14,15] +; AVX512F-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm7 # 32-byte Reload +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm7 = ymm7[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,20,21,18,19,20,21,24,25,26,27,22,23,22,23] +; AVX512F-FAST-NEXT: vpshufd $85, {{[-0-9]+}}(%r{{[sb]}}p), %ymm8 # 32-byte Folded Reload +; AVX512F-FAST-NEXT: # ymm8 = mem[1,1,1,1,5,5,5,5] +; AVX512F-FAST-NEXT: vpblendw {{.*#+}} ymm7 = ymm7[0,1],ymm8[2],ymm7[3,4],ymm8[5],ymm7[6,7,8,9],ymm8[10],ymm7[11,12],ymm8[13],ymm7[14,15] +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm8 = [0,1,4,5,4,5,5,7] +; AVX512F-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm10 # 64-byte Reload +; AVX512F-FAST-NEXT: vpermd %ymm10, %ymm8, %ymm8 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm10 = ymm10[12,13],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm10[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm10[16,17],zero,zero +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm11 = [65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535] +; AVX512F-FAST-NEXT: vpandn %ymm8, %ymm11, %ymm8 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm8, %zmm10, %zmm8 +; AVX512F-FAST-NEXT: vpshuflw $248, {{[-0-9]+}}(%r{{[sb]}}p), %xmm10 # 16-byte Folded Reload +; AVX512F-FAST-NEXT: # xmm10 = mem[0,2,3,3,4,5,6,7] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm10 = ymm10[0,0,2,1] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,0,1,3] +; AVX512F-FAST-NEXT: vpshuflw {{.*#+}} xmm4 = xmm4[0,2,3,3,4,5,6,7] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm4 = ymm4[0,0,2,1] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm5 = ymm5[0,0,1,3] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm6 = ymm6[2,1,3,2] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm7 = ymm7[2,2,2,3] +; AVX512F-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload +; AVX512F-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm11, %zmm13 +; AVX512F-FAST-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm10, %zmm10 # 32-byte Folded Reload +; AVX512F-FAST-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm1, %zmm1 # 32-byte Folded Reload +; AVX512F-FAST-NEXT: vpternlogq $226, %zmm10, %zmm25, %zmm1 +; AVX512F-FAST-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm4, %zmm4 # 32-byte Folded Reload +; AVX512F-FAST-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm5, %zmm5 # 32-byte Folded Reload +; AVX512F-FAST-NEXT: vpternlogq $226, %zmm4, %zmm25, %zmm5 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm4 = [0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535] +; AVX512F-FAST-NEXT: vpternlogq $226, {{[-0-9]+}}(%r{{[sb]}}p), %zmm4, %zmm1 # 64-byte Folded Reload +; AVX512F-FAST-NEXT: vpternlogq $226, {{[-0-9]+}}(%r{{[sb]}}p), %zmm4, %zmm5 # 64-byte Folded Reload +; AVX512F-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm6, %zmm4, %zmm4 +; AVX512F-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm7, %zmm6, %zmm6 +; AVX512F-FAST-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm4, %zmm6 +; AVX512F-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512F-FAST-NEXT: vpternlogq $248, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm4 # 64-byte Folded Reload +; AVX512F-FAST-NEXT: vpternlogq $248, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm8 # 64-byte Folded Reload +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm6, %zmm8 +; AVX512F-FAST-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512F-FAST-NEXT: vmovdqa64 %zmm8, 320(%rax) +; AVX512F-FAST-NEXT: vmovdqa64 %zmm3, 256(%rax) +; AVX512F-FAST-NEXT: vmovdqa64 %zmm9, 192(%rax) +; AVX512F-FAST-NEXT: vmovdqa64 %zmm19, 128(%rax) +; AVX512F-FAST-NEXT: vmovdqa64 %zmm20, (%rax) +; AVX512F-FAST-NEXT: vmovdqa64 %zmm23, 448(%rax) +; AVX512F-FAST-NEXT: vmovdqa64 %zmm2, 704(%rax) +; AVX512F-FAST-NEXT: vmovdqa64 %zmm21, 640(%rax) +; AVX512F-FAST-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-FAST-NEXT: vmovaps %zmm0, 576(%rax) +; AVX512F-FAST-NEXT: vmovdqa64 %zmm13, 384(%rax) +; AVX512F-FAST-NEXT: vmovdqa64 %zmm5, 64(%rax) +; AVX512F-FAST-NEXT: vmovdqa64 %zmm1, 512(%rax) +; AVX512F-FAST-NEXT: vmovdqa64 %zmm12, 832(%rax) +; AVX512F-FAST-NEXT: vmovdqa64 %zmm4, 768(%rax) +; AVX512F-FAST-NEXT: addq $1496, %rsp # imm = 0x5D8 +; AVX512F-FAST-NEXT: vzeroupper +; AVX512F-FAST-NEXT: retq ; ; AVX512BW-LABEL: store_i16_stride7_vf64: ; AVX512BW: # %bb.0: @@ -14524,11 +12288,15 @@ define void @store_i16_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve ; AVX512BW-ONLY: {{.*}} ; AVX512BW-ONLY-FAST: {{.*}} ; AVX512BW-ONLY-SLOW: {{.*}} +; AVX512DQ-FAST: {{.*}} ; AVX512DQ-ONLY: {{.*}} +; AVX512DQ-SLOW: {{.*}} ; AVX512DQBW-FAST: {{.*}} ; AVX512DQBW-ONLY: {{.*}} ; AVX512DQBW-SLOW: {{.*}} ; AVX512F-ONLY: {{.*}} +; AVX512F-ONLY-FAST: {{.*}} +; AVX512F-ONLY-SLOW: {{.*}} ; FALLBACK0: {{.*}} ; FALLBACK1: {{.*}} ; FALLBACK10: {{.*}} diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll index e68da022c186..6ef479b87541 100644 --- a/llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll +++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll @@ -1442,565 +1442,285 @@ define void @store_i64_stride6_vf16(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve ; AVX2-ONLY-NEXT: vzeroupper ; AVX2-ONLY-NEXT: retq ; -; AVX512F-ONLY-LABEL: store_i64_stride6_vf16: -; AVX512F-ONLY: # %bb.0: -; AVX512F-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512F-ONLY-NEXT: vmovdqa64 64(%rdi), %zmm13 -; AVX512F-ONLY-NEXT: vmovdqa64 (%rdi), %zmm5 -; AVX512F-ONLY-NEXT: vmovdqa64 (%rsi), %zmm6 -; AVX512F-ONLY-NEXT: vmovdqa64 64(%rsi), %zmm14 -; AVX512F-ONLY-NEXT: vmovdqa64 64(%rdx), %zmm7 -; AVX512F-ONLY-NEXT: vmovdqa64 (%rdx), %zmm2 -; AVX512F-ONLY-NEXT: vmovdqa64 (%rcx), %zmm4 -; AVX512F-ONLY-NEXT: vmovdqa64 64(%rcx), %zmm11 -; AVX512F-ONLY-NEXT: vmovdqa64 (%r8), %zmm3 -; AVX512F-ONLY-NEXT: vmovdqa64 64(%r8), %zmm8 -; AVX512F-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm0 = [4,12,5,13,4,12,5,13] -; AVX512F-ONLY-NEXT: # zmm0 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm5, %zmm1 -; AVX512F-ONLY-NEXT: vpermt2q %zmm6, %zmm0, %zmm1 -; AVX512F-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm9 = [4,12,4,12] -; AVX512F-ONLY-NEXT: # ymm9 = mem[0,1,0,1] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm10 -; AVX512F-ONLY-NEXT: vpermt2q %zmm4, %zmm9, %zmm10 -; AVX512F-ONLY-NEXT: movb $12, %r10b -; AVX512F-ONLY-NEXT: kmovw %r10d, %k1 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm10, %zmm1 {%k1} -; AVX512F-ONLY-NEXT: movb $16, %r10b -; AVX512F-ONLY-NEXT: kmovw %r10d, %k2 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm3, %zmm1 {%k2} -; AVX512F-ONLY-NEXT: vpermi2q %zmm14, %zmm13, %zmm0 -; AVX512F-ONLY-NEXT: vpermi2q %zmm11, %zmm7, %zmm9 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm9, %zmm0 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 {%k2} -; AVX512F-ONLY-NEXT: vmovdqa64 (%r9), %zmm10 -; AVX512F-ONLY-NEXT: vmovdqa64 64(%r9), %zmm16 -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm18 = [6,14,6,14,6,14,6,14] -; AVX512F-ONLY-NEXT: # zmm18 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm13, %zmm15 -; AVX512F-ONLY-NEXT: vpermt2q %zmm14, %zmm18, %zmm15 -; AVX512F-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm12 = [5,13,6,14,5,13,6,14] -; AVX512F-ONLY-NEXT: # zmm12 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, %zmm9 -; AVX512F-ONLY-NEXT: vpermt2q %zmm11, %zmm12, %zmm9 -; AVX512F-ONLY-NEXT: movb $48, %r9b -; AVX512F-ONLY-NEXT: kmovw %r9d, %k2 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm15, %zmm9 {%k2} -; AVX512F-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm19 = <0,1,13,u,4,5,6,7> -; AVX512F-ONLY-NEXT: vpermt2q %zmm8, %zmm19, %zmm9 -; AVX512F-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm20 = [0,1,2,13,4,5,6,7] -; AVX512F-ONLY-NEXT: vpermt2q %zmm16, %zmm20, %zmm9 -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm21 = [2,10,2,10,2,10,2,10] -; AVX512F-ONLY-NEXT: # zmm21 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm13, %zmm22 -; AVX512F-ONLY-NEXT: vpermt2q %zmm14, %zmm21, %zmm22 -; AVX512F-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm17 = [1,9,2,10,1,9,2,10] -; AVX512F-ONLY-NEXT: # zmm17 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, %zmm15 -; AVX512F-ONLY-NEXT: vpermt2q %zmm11, %zmm17, %zmm15 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm22, %zmm15 {%k2} -; AVX512F-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm22 = <0,1,9,u,4,5,6,7> -; AVX512F-ONLY-NEXT: vpermt2q %zmm8, %zmm22, %zmm15 -; AVX512F-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm23 = [0,1,2,9,4,5,6,7] -; AVX512F-ONLY-NEXT: vpermt2q %zmm16, %zmm23, %zmm15 -; AVX512F-ONLY-NEXT: vpermi2q %zmm6, %zmm5, %zmm18 -; AVX512F-ONLY-NEXT: vpermi2q %zmm4, %zmm2, %zmm12 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm18, %zmm12 {%k2} -; AVX512F-ONLY-NEXT: vpermt2q %zmm3, %zmm19, %zmm12 -; AVX512F-ONLY-NEXT: vpermt2q %zmm10, %zmm20, %zmm12 -; AVX512F-ONLY-NEXT: vpermi2q %zmm6, %zmm5, %zmm21 -; AVX512F-ONLY-NEXT: vpermi2q %zmm4, %zmm2, %zmm17 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm21, %zmm17 {%k2} -; AVX512F-ONLY-NEXT: vpermt2q %zmm3, %zmm22, %zmm17 -; AVX512F-ONLY-NEXT: vpermt2q %zmm10, %zmm23, %zmm17 -; AVX512F-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm19 = [0,8,1,9,0,8,1,9] -; AVX512F-ONLY-NEXT: # zmm19 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm5, %zmm18 -; AVX512F-ONLY-NEXT: vpermt2q %zmm6, %zmm19, %zmm18 -; AVX512F-ONLY-NEXT: vmovdqa64 (%rdx), %xmm20 -; AVX512F-ONLY-NEXT: vmovdqa64 64(%rdx), %xmm21 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm20 = xmm20[0],mem[0] -; AVX512F-ONLY-NEXT: vinserti32x4 $1, %xmm20, %ymm0, %ymm20 -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm20, %zmm0, %zmm18 {%k1} -; AVX512F-ONLY-NEXT: vinserti32x4 $2, (%r8), %zmm18, %zmm18 -; AVX512F-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm20 = [0,1,2,3,4,8,6,7] -; AVX512F-ONLY-NEXT: vpermt2q %zmm10, %zmm20, %zmm18 -; AVX512F-ONLY-NEXT: vpermi2q %zmm14, %zmm13, %zmm19 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm21 = xmm21[0],mem[0] -; AVX512F-ONLY-NEXT: vinserti32x4 $1, %xmm21, %ymm0, %ymm21 -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm21, %zmm0, %zmm19 {%k1} -; AVX512F-ONLY-NEXT: vinserti32x4 $2, 64(%r8), %zmm19, %zmm19 -; AVX512F-ONLY-NEXT: vpermt2q %zmm16, %zmm20, %zmm19 -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm20 = [7,15,7,15,7,15,7,15] -; AVX512F-ONLY-NEXT: # zmm20 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, %zmm21 -; AVX512F-ONLY-NEXT: vpermt2q %zmm11, %zmm20, %zmm21 -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} ymm22 = [7,15,7,15] -; AVX512F-ONLY-NEXT: # ymm22 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vpermt2q %zmm14, %zmm22, %zmm13 -; AVX512F-ONLY-NEXT: vshufi64x2 {{.*#+}} zmm13 = zmm13[0,1,2,3],zmm21[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm14 = <14,u,2,3,4,5,15,u> -; AVX512F-ONLY-NEXT: vpermt2q %zmm8, %zmm14, %zmm13 -; AVX512F-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm21 = [0,14,2,3,4,5,6,15] -; AVX512F-ONLY-NEXT: vpermt2q %zmm16, %zmm21, %zmm13 -; AVX512F-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm23 = [0,1,2,3,4,12,6,7] -; AVX512F-ONLY-NEXT: vpermt2q %zmm16, %zmm23, %zmm0 -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm24 = [3,11,3,11,3,11,3,11] -; AVX512F-ONLY-NEXT: # zmm24 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vpermt2q %zmm11, %zmm24, %zmm7 -; AVX512F-ONLY-NEXT: vmovdqa (%rdi), %ymm11 -; AVX512F-ONLY-NEXT: vmovdqa64 64(%rdi), %ymm25 -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm25 = ymm25[1],mem[1],ymm25[3],mem[3] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm25, %zmm7, %zmm7 -; AVX512F-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm25 = <10,u,2,3,4,5,11,u> -; AVX512F-ONLY-NEXT: vpermt2q %zmm8, %zmm25, %zmm7 -; AVX512F-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm8 = [0,10,2,3,4,5,6,11] -; AVX512F-ONLY-NEXT: vpermt2q %zmm16, %zmm8, %zmm7 -; AVX512F-ONLY-NEXT: vpermi2q %zmm4, %zmm2, %zmm20 -; AVX512F-ONLY-NEXT: vpermt2q %zmm6, %zmm22, %zmm5 -; AVX512F-ONLY-NEXT: vshufi64x2 {{.*#+}} zmm5 = zmm5[0,1,2,3],zmm20[4,5,6,7] -; AVX512F-ONLY-NEXT: vpermt2q %zmm3, %zmm14, %zmm5 -; AVX512F-ONLY-NEXT: vpermt2q %zmm10, %zmm21, %zmm5 -; AVX512F-ONLY-NEXT: vpermt2q %zmm10, %zmm23, %zmm1 -; AVX512F-ONLY-NEXT: vpermt2q %zmm4, %zmm24, %zmm2 -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm4 = ymm11[1],mem[1],ymm11[3],mem[3] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm2, %zmm2 -; AVX512F-ONLY-NEXT: vpermt2q %zmm3, %zmm25, %zmm2 -; AVX512F-ONLY-NEXT: vpermt2q %zmm10, %zmm8, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm17, 64(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, 128(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm1, 192(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm12, 256(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm5, 320(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm15, 448(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, 512(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, 576(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm9, 640(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm13, 704(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm19, 384(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm18, (%rax) -; AVX512F-ONLY-NEXT: vzeroupper -; AVX512F-ONLY-NEXT: retq -; -; AVX512DQ-ONLY-LABEL: store_i64_stride6_vf16: -; AVX512DQ-ONLY: # %bb.0: -; AVX512DQ-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQ-ONLY-NEXT: vmovdqa64 64(%rdi), %zmm13 -; AVX512DQ-ONLY-NEXT: vmovdqa64 (%rdi), %zmm5 -; AVX512DQ-ONLY-NEXT: vmovdqa64 (%rsi), %zmm6 -; AVX512DQ-ONLY-NEXT: vmovdqa64 64(%rsi), %zmm14 -; AVX512DQ-ONLY-NEXT: vmovdqa64 64(%rdx), %zmm7 -; AVX512DQ-ONLY-NEXT: vmovdqa64 (%rdx), %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqa64 (%rcx), %zmm4 -; AVX512DQ-ONLY-NEXT: vmovdqa64 64(%rcx), %zmm11 -; AVX512DQ-ONLY-NEXT: vmovdqa64 (%r8), %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqa64 64(%r8), %zmm8 -; AVX512DQ-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm0 = [4,12,5,13,4,12,5,13] -; AVX512DQ-ONLY-NEXT: # zmm0 = mem[0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm5, %zmm1 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm6, %zmm0, %zmm1 -; AVX512DQ-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm9 = [4,12,4,12] -; AVX512DQ-ONLY-NEXT: # ymm9 = mem[0,1,0,1] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm10 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm4, %zmm9, %zmm10 -; AVX512DQ-ONLY-NEXT: movb $12, %r10b -; AVX512DQ-ONLY-NEXT: kmovw %r10d, %k1 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm10, %zmm1 {%k1} -; AVX512DQ-ONLY-NEXT: movb $16, %r10b -; AVX512DQ-ONLY-NEXT: kmovw %r10d, %k2 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm3, %zmm1 {%k2} -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm14, %zmm13, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm11, %zmm7, %zmm9 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm9, %zmm0 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqa64 (%r9), %zmm10 -; AVX512DQ-ONLY-NEXT: vmovdqa64 64(%r9), %zmm16 -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm18 = [6,14,6,14,6,14,6,14] -; AVX512DQ-ONLY-NEXT: # zmm18 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm13, %zmm15 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm14, %zmm18, %zmm15 -; AVX512DQ-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm12 = [5,13,6,14,5,13,6,14] -; AVX512DQ-ONLY-NEXT: # zmm12 = mem[0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, %zmm9 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm11, %zmm12, %zmm9 -; AVX512DQ-ONLY-NEXT: movb $48, %r9b -; AVX512DQ-ONLY-NEXT: kmovw %r9d, %k2 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm15, %zmm9 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm19 = <0,1,13,u,4,5,6,7> -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm8, %zmm19, %zmm9 -; AVX512DQ-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm20 = [0,1,2,13,4,5,6,7] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm16, %zmm20, %zmm9 -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm21 = [2,10,2,10,2,10,2,10] -; AVX512DQ-ONLY-NEXT: # zmm21 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm13, %zmm22 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm14, %zmm21, %zmm22 -; AVX512DQ-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm17 = [1,9,2,10,1,9,2,10] -; AVX512DQ-ONLY-NEXT: # zmm17 = mem[0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, %zmm15 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm11, %zmm17, %zmm15 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm22, %zmm15 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm22 = <0,1,9,u,4,5,6,7> -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm8, %zmm22, %zmm15 -; AVX512DQ-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm23 = [0,1,2,9,4,5,6,7] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm16, %zmm23, %zmm15 -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm6, %zmm5, %zmm18 -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm4, %zmm2, %zmm12 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm18, %zmm12 {%k2} -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm3, %zmm19, %zmm12 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm10, %zmm20, %zmm12 -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm6, %zmm5, %zmm21 -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm4, %zmm2, %zmm17 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm21, %zmm17 {%k2} -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm3, %zmm22, %zmm17 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm10, %zmm23, %zmm17 -; AVX512DQ-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm19 = [0,8,1,9,0,8,1,9] -; AVX512DQ-ONLY-NEXT: # zmm19 = mem[0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm5, %zmm18 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm6, %zmm19, %zmm18 -; AVX512DQ-ONLY-NEXT: vmovdqa64 (%rdx), %xmm20 -; AVX512DQ-ONLY-NEXT: vmovdqa64 64(%rdx), %xmm21 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm20 = xmm20[0],mem[0] -; AVX512DQ-ONLY-NEXT: vinserti32x4 $1, %xmm20, %ymm0, %ymm20 -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm20, %zmm0, %zmm18 {%k1} -; AVX512DQ-ONLY-NEXT: vinserti32x4 $2, (%r8), %zmm18, %zmm18 -; AVX512DQ-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm20 = [0,1,2,3,4,8,6,7] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm10, %zmm20, %zmm18 -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm14, %zmm13, %zmm19 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm21 = xmm21[0],mem[0] -; AVX512DQ-ONLY-NEXT: vinserti32x4 $1, %xmm21, %ymm0, %ymm21 -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm21, %zmm0, %zmm19 {%k1} -; AVX512DQ-ONLY-NEXT: vinserti32x4 $2, 64(%r8), %zmm19, %zmm19 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm16, %zmm20, %zmm19 -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm20 = [7,15,7,15,7,15,7,15] -; AVX512DQ-ONLY-NEXT: # zmm20 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, %zmm21 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm11, %zmm20, %zmm21 -; AVX512DQ-ONLY-NEXT: vbroadcasti64x2 {{.*#+}} ymm22 = [7,15,7,15] -; AVX512DQ-ONLY-NEXT: # ymm22 = mem[0,1,0,1] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm14, %zmm22, %zmm13 -; AVX512DQ-ONLY-NEXT: vshufi64x2 {{.*#+}} zmm13 = zmm13[0,1,2,3],zmm21[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm14 = <14,u,2,3,4,5,15,u> -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm8, %zmm14, %zmm13 -; AVX512DQ-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm21 = [0,14,2,3,4,5,6,15] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm16, %zmm21, %zmm13 -; AVX512DQ-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm23 = [0,1,2,3,4,12,6,7] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm16, %zmm23, %zmm0 -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm24 = [3,11,3,11,3,11,3,11] -; AVX512DQ-ONLY-NEXT: # zmm24 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm11, %zmm24, %zmm7 -; AVX512DQ-ONLY-NEXT: vmovdqa (%rdi), %ymm11 -; AVX512DQ-ONLY-NEXT: vmovdqa64 64(%rdi), %ymm25 -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm25 = ymm25[1],mem[1],ymm25[3],mem[3] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm25, %zmm7, %zmm7 -; AVX512DQ-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm25 = <10,u,2,3,4,5,11,u> -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm8, %zmm25, %zmm7 -; AVX512DQ-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm8 = [0,10,2,3,4,5,6,11] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm16, %zmm8, %zmm7 -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm4, %zmm2, %zmm20 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm6, %zmm22, %zmm5 -; AVX512DQ-ONLY-NEXT: vshufi64x2 {{.*#+}} zmm5 = zmm5[0,1,2,3],zmm20[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm3, %zmm14, %zmm5 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm10, %zmm21, %zmm5 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm10, %zmm23, %zmm1 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm4, %zmm24, %zmm2 -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm4 = ymm11[1],mem[1],ymm11[3],mem[3] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm2, %zmm2 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm3, %zmm25, %zmm2 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm10, %zmm8, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm17, 64(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, 128(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm1, 192(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm12, 256(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm5, 320(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm15, 448(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, 512(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, 576(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm9, 640(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm13, 704(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm19, 384(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm18, (%rax) -; AVX512DQ-ONLY-NEXT: vzeroupper -; AVX512DQ-ONLY-NEXT: retq -; -; AVX512BW-ONLY-LABEL: store_i64_stride6_vf16: -; AVX512BW-ONLY: # %bb.0: -; AVX512BW-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%rdi), %zmm13 -; AVX512BW-ONLY-NEXT: vmovdqa64 (%rdi), %zmm5 -; AVX512BW-ONLY-NEXT: vmovdqa64 (%rsi), %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%rsi), %zmm14 -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%rdx), %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqa64 (%rdx), %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqa64 (%rcx), %zmm4 -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%rcx), %zmm11 -; AVX512BW-ONLY-NEXT: vmovdqa64 (%r8), %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%r8), %zmm8 -; AVX512BW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm0 = [4,12,5,13,4,12,5,13] -; AVX512BW-ONLY-NEXT: # zmm0 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm1 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm6, %zmm0, %zmm1 -; AVX512BW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm9 = [4,12,4,12] -; AVX512BW-ONLY-NEXT: # ymm9 = mem[0,1,0,1] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm10 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm4, %zmm9, %zmm10 -; AVX512BW-ONLY-NEXT: movb $12, %r10b -; AVX512BW-ONLY-NEXT: kmovd %r10d, %k1 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm1 {%k1} -; AVX512BW-ONLY-NEXT: movb $16, %r10b -; AVX512BW-ONLY-NEXT: kmovd %r10d, %k2 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm1 {%k2} -; AVX512BW-ONLY-NEXT: vpermi2q %zmm14, %zmm13, %zmm0 -; AVX512BW-ONLY-NEXT: vpermi2q %zmm11, %zmm7, %zmm9 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm9, %zmm0 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqa64 (%r9), %zmm10 -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%r9), %zmm16 -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm18 = [6,14,6,14,6,14,6,14] -; AVX512BW-ONLY-NEXT: # zmm18 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm13, %zmm15 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm14, %zmm18, %zmm15 -; AVX512BW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm12 = [5,13,6,14,5,13,6,14] -; AVX512BW-ONLY-NEXT: # zmm12 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm9 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm11, %zmm12, %zmm9 -; AVX512BW-ONLY-NEXT: movb $48, %r9b -; AVX512BW-ONLY-NEXT: kmovd %r9d, %k2 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm15, %zmm9 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm19 = <0,1,13,u,4,5,6,7> -; AVX512BW-ONLY-NEXT: vpermt2q %zmm8, %zmm19, %zmm9 -; AVX512BW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm20 = [0,1,2,13,4,5,6,7] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm16, %zmm20, %zmm9 -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm21 = [2,10,2,10,2,10,2,10] -; AVX512BW-ONLY-NEXT: # zmm21 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm13, %zmm22 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm14, %zmm21, %zmm22 -; AVX512BW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm17 = [1,9,2,10,1,9,2,10] -; AVX512BW-ONLY-NEXT: # zmm17 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm15 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm11, %zmm17, %zmm15 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm22, %zmm15 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm22 = <0,1,9,u,4,5,6,7> -; AVX512BW-ONLY-NEXT: vpermt2q %zmm8, %zmm22, %zmm15 -; AVX512BW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm23 = [0,1,2,9,4,5,6,7] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm16, %zmm23, %zmm15 -; AVX512BW-ONLY-NEXT: vpermi2q %zmm6, %zmm5, %zmm18 -; AVX512BW-ONLY-NEXT: vpermi2q %zmm4, %zmm2, %zmm12 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm18, %zmm12 {%k2} -; AVX512BW-ONLY-NEXT: vpermt2q %zmm3, %zmm19, %zmm12 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm10, %zmm20, %zmm12 -; AVX512BW-ONLY-NEXT: vpermi2q %zmm6, %zmm5, %zmm21 -; AVX512BW-ONLY-NEXT: vpermi2q %zmm4, %zmm2, %zmm17 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm21, %zmm17 {%k2} -; AVX512BW-ONLY-NEXT: vpermt2q %zmm3, %zmm22, %zmm17 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm10, %zmm23, %zmm17 -; AVX512BW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm19 = [0,8,1,9,0,8,1,9] -; AVX512BW-ONLY-NEXT: # zmm19 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm18 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm6, %zmm19, %zmm18 -; AVX512BW-ONLY-NEXT: vmovdqa64 (%rdx), %xmm20 -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%rdx), %xmm21 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm20 = xmm20[0],mem[0] -; AVX512BW-ONLY-NEXT: vinserti32x4 $1, %xmm20, %ymm0, %ymm20 -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm20, %zmm0, %zmm18 {%k1} -; AVX512BW-ONLY-NEXT: vinserti32x4 $2, (%r8), %zmm18, %zmm18 -; AVX512BW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm20 = [0,1,2,3,4,8,6,7] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm10, %zmm20, %zmm18 -; AVX512BW-ONLY-NEXT: vpermi2q %zmm14, %zmm13, %zmm19 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm21 = xmm21[0],mem[0] -; AVX512BW-ONLY-NEXT: vinserti32x4 $1, %xmm21, %ymm0, %ymm21 -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm21, %zmm0, %zmm19 {%k1} -; AVX512BW-ONLY-NEXT: vinserti32x4 $2, 64(%r8), %zmm19, %zmm19 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm16, %zmm20, %zmm19 -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm20 = [7,15,7,15,7,15,7,15] -; AVX512BW-ONLY-NEXT: # zmm20 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm21 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm11, %zmm20, %zmm21 -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} ymm22 = [7,15,7,15] -; AVX512BW-ONLY-NEXT: # ymm22 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm14, %zmm22, %zmm13 -; AVX512BW-ONLY-NEXT: vshufi64x2 {{.*#+}} zmm13 = zmm13[0,1,2,3],zmm21[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm14 = <14,u,2,3,4,5,15,u> -; AVX512BW-ONLY-NEXT: vpermt2q %zmm8, %zmm14, %zmm13 -; AVX512BW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm21 = [0,14,2,3,4,5,6,15] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm16, %zmm21, %zmm13 -; AVX512BW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm23 = [0,1,2,3,4,12,6,7] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm16, %zmm23, %zmm0 -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm24 = [3,11,3,11,3,11,3,11] -; AVX512BW-ONLY-NEXT: # zmm24 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm11, %zmm24, %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqa (%rdi), %ymm11 -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%rdi), %ymm25 -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm25 = ymm25[1],mem[1],ymm25[3],mem[3] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm25, %zmm7, %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm25 = <10,u,2,3,4,5,11,u> -; AVX512BW-ONLY-NEXT: vpermt2q %zmm8, %zmm25, %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm8 = [0,10,2,3,4,5,6,11] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm16, %zmm8, %zmm7 -; AVX512BW-ONLY-NEXT: vpermi2q %zmm4, %zmm2, %zmm20 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm6, %zmm22, %zmm5 -; AVX512BW-ONLY-NEXT: vshufi64x2 {{.*#+}} zmm5 = zmm5[0,1,2,3],zmm20[4,5,6,7] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm3, %zmm14, %zmm5 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm10, %zmm21, %zmm5 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm10, %zmm23, %zmm1 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm4, %zmm24, %zmm2 -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm4 = ymm11[1],mem[1],ymm11[3],mem[3] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm2, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm3, %zmm25, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm10, %zmm8, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm17, 64(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, 128(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm1, 192(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm12, 256(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, 320(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm15, 448(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, 512(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, 576(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm9, 640(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm13, 704(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm19, 384(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm18, (%rax) -; AVX512BW-ONLY-NEXT: vzeroupper -; AVX512BW-ONLY-NEXT: retq +; AVX512F-LABEL: store_i64_stride6_vf16: +; AVX512F: # %bb.0: +; AVX512F-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512F-NEXT: vmovdqa64 64(%rdi), %zmm13 +; AVX512F-NEXT: vmovdqa64 (%rdi), %zmm5 +; AVX512F-NEXT: vmovdqa64 (%rsi), %zmm6 +; AVX512F-NEXT: vmovdqa64 64(%rsi), %zmm14 +; AVX512F-NEXT: vmovdqa64 64(%rdx), %zmm7 +; AVX512F-NEXT: vmovdqa64 (%rdx), %zmm2 +; AVX512F-NEXT: vmovdqa64 (%rcx), %zmm4 +; AVX512F-NEXT: vmovdqa64 64(%rcx), %zmm11 +; AVX512F-NEXT: vmovdqa64 (%r8), %zmm3 +; AVX512F-NEXT: vmovdqa64 64(%r8), %zmm8 +; AVX512F-NEXT: vbroadcasti64x4 {{.*#+}} zmm0 = [4,12,5,13,4,12,5,13] +; AVX512F-NEXT: # zmm0 = mem[0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm5, %zmm1 +; AVX512F-NEXT: vpermt2q %zmm6, %zmm0, %zmm1 +; AVX512F-NEXT: vbroadcasti128 {{.*#+}} ymm9 = [4,12,4,12] +; AVX512F-NEXT: # ymm9 = mem[0,1,0,1] +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm10 +; AVX512F-NEXT: vpermt2q %zmm4, %zmm9, %zmm10 +; AVX512F-NEXT: movb $12, %r10b +; AVX512F-NEXT: kmovw %r10d, %k1 +; AVX512F-NEXT: vmovdqa64 %zmm10, %zmm1 {%k1} +; AVX512F-NEXT: movb $16, %r10b +; AVX512F-NEXT: kmovw %r10d, %k2 +; AVX512F-NEXT: vmovdqa64 %zmm3, %zmm1 {%k2} +; AVX512F-NEXT: vpermi2q %zmm14, %zmm13, %zmm0 +; AVX512F-NEXT: vpermi2q %zmm11, %zmm7, %zmm9 +; AVX512F-NEXT: vmovdqa64 %zmm9, %zmm0 {%k1} +; AVX512F-NEXT: vmovdqa64 %zmm8, %zmm0 {%k2} +; AVX512F-NEXT: vmovdqa64 (%r9), %zmm10 +; AVX512F-NEXT: vmovdqa64 64(%r9), %zmm16 +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm18 = [6,14,6,14,6,14,6,14] +; AVX512F-NEXT: # zmm18 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm13, %zmm15 +; AVX512F-NEXT: vpermt2q %zmm14, %zmm18, %zmm15 +; AVX512F-NEXT: vbroadcasti64x4 {{.*#+}} zmm12 = [5,13,6,14,5,13,6,14] +; AVX512F-NEXT: # zmm12 = mem[0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm7, %zmm9 +; AVX512F-NEXT: vpermt2q %zmm11, %zmm12, %zmm9 +; AVX512F-NEXT: movb $48, %r9b +; AVX512F-NEXT: kmovw %r9d, %k2 +; AVX512F-NEXT: vmovdqa64 %zmm15, %zmm9 {%k2} +; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm19 = <0,1,13,u,4,5,6,7> +; AVX512F-NEXT: vpermt2q %zmm8, %zmm19, %zmm9 +; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm20 = [0,1,2,13,4,5,6,7] +; AVX512F-NEXT: vpermt2q %zmm16, %zmm20, %zmm9 +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm21 = [2,10,2,10,2,10,2,10] +; AVX512F-NEXT: # zmm21 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm13, %zmm22 +; AVX512F-NEXT: vpermt2q %zmm14, %zmm21, %zmm22 +; AVX512F-NEXT: vbroadcasti64x4 {{.*#+}} zmm17 = [1,9,2,10,1,9,2,10] +; AVX512F-NEXT: # zmm17 = mem[0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm7, %zmm15 +; AVX512F-NEXT: vpermt2q %zmm11, %zmm17, %zmm15 +; AVX512F-NEXT: vmovdqa64 %zmm22, %zmm15 {%k2} +; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm22 = <0,1,9,u,4,5,6,7> +; AVX512F-NEXT: vpermt2q %zmm8, %zmm22, %zmm15 +; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm23 = [0,1,2,9,4,5,6,7] +; AVX512F-NEXT: vpermt2q %zmm16, %zmm23, %zmm15 +; AVX512F-NEXT: vpermi2q %zmm6, %zmm5, %zmm18 +; AVX512F-NEXT: vpermi2q %zmm4, %zmm2, %zmm12 +; AVX512F-NEXT: vmovdqa64 %zmm18, %zmm12 {%k2} +; AVX512F-NEXT: vpermt2q %zmm3, %zmm19, %zmm12 +; AVX512F-NEXT: vpermt2q %zmm10, %zmm20, %zmm12 +; AVX512F-NEXT: vpermi2q %zmm6, %zmm5, %zmm21 +; AVX512F-NEXT: vpermi2q %zmm4, %zmm2, %zmm17 +; AVX512F-NEXT: vmovdqa64 %zmm21, %zmm17 {%k2} +; AVX512F-NEXT: vpermt2q %zmm3, %zmm22, %zmm17 +; AVX512F-NEXT: vpermt2q %zmm10, %zmm23, %zmm17 +; AVX512F-NEXT: vbroadcasti64x4 {{.*#+}} zmm19 = [0,8,1,9,0,8,1,9] +; AVX512F-NEXT: # zmm19 = mem[0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm5, %zmm18 +; AVX512F-NEXT: vpermt2q %zmm6, %zmm19, %zmm18 +; AVX512F-NEXT: vmovdqa64 (%rdx), %xmm20 +; AVX512F-NEXT: vmovdqa64 64(%rdx), %xmm21 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm20 = xmm20[0],mem[0] +; AVX512F-NEXT: vinserti32x4 $1, %xmm20, %ymm0, %ymm20 +; AVX512F-NEXT: vinserti64x4 $0, %ymm20, %zmm0, %zmm18 {%k1} +; AVX512F-NEXT: vinserti32x4 $2, (%r8), %zmm18, %zmm18 +; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm20 = [0,1,2,3,4,8,6,7] +; AVX512F-NEXT: vpermt2q %zmm10, %zmm20, %zmm18 +; AVX512F-NEXT: vpermi2q %zmm14, %zmm13, %zmm19 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm21 = xmm21[0],mem[0] +; AVX512F-NEXT: vinserti32x4 $1, %xmm21, %ymm0, %ymm21 +; AVX512F-NEXT: vinserti64x4 $0, %ymm21, %zmm0, %zmm19 {%k1} +; AVX512F-NEXT: vinserti32x4 $2, 64(%r8), %zmm19, %zmm19 +; AVX512F-NEXT: vpermt2q %zmm16, %zmm20, %zmm19 +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm20 = [7,15,7,15,7,15,7,15] +; AVX512F-NEXT: # zmm20 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm7, %zmm21 +; AVX512F-NEXT: vpermt2q %zmm11, %zmm20, %zmm21 +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} ymm22 = [7,15,7,15] +; AVX512F-NEXT: # ymm22 = mem[0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vpermt2q %zmm14, %zmm22, %zmm13 +; AVX512F-NEXT: vshufi64x2 {{.*#+}} zmm13 = zmm13[0,1,2,3],zmm21[4,5,6,7] +; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm14 = <14,u,2,3,4,5,15,u> +; AVX512F-NEXT: vpermt2q %zmm8, %zmm14, %zmm13 +; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm21 = [0,14,2,3,4,5,6,15] +; AVX512F-NEXT: vpermt2q %zmm16, %zmm21, %zmm13 +; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm23 = [0,1,2,3,4,12,6,7] +; AVX512F-NEXT: vpermt2q %zmm16, %zmm23, %zmm0 +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm24 = [3,11,3,11,3,11,3,11] +; AVX512F-NEXT: # zmm24 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vpermt2q %zmm11, %zmm24, %zmm7 +; AVX512F-NEXT: vmovdqa (%rdi), %ymm11 +; AVX512F-NEXT: vmovdqa64 64(%rdi), %ymm25 +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm25 = ymm25[1],mem[1],ymm25[3],mem[3] +; AVX512F-NEXT: vinserti64x4 $0, %ymm25, %zmm7, %zmm7 +; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm25 = <10,u,2,3,4,5,11,u> +; AVX512F-NEXT: vpermt2q %zmm8, %zmm25, %zmm7 +; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm8 = [0,10,2,3,4,5,6,11] +; AVX512F-NEXT: vpermt2q %zmm16, %zmm8, %zmm7 +; AVX512F-NEXT: vpermi2q %zmm4, %zmm2, %zmm20 +; AVX512F-NEXT: vpermt2q %zmm6, %zmm22, %zmm5 +; AVX512F-NEXT: vshufi64x2 {{.*#+}} zmm5 = zmm5[0,1,2,3],zmm20[4,5,6,7] +; AVX512F-NEXT: vpermt2q %zmm3, %zmm14, %zmm5 +; AVX512F-NEXT: vpermt2q %zmm10, %zmm21, %zmm5 +; AVX512F-NEXT: vpermt2q %zmm10, %zmm23, %zmm1 +; AVX512F-NEXT: vpermt2q %zmm4, %zmm24, %zmm2 +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm4 = ymm11[1],mem[1],ymm11[3],mem[3] +; AVX512F-NEXT: vinserti64x4 $0, %ymm4, %zmm2, %zmm2 +; AVX512F-NEXT: vpermt2q %zmm3, %zmm25, %zmm2 +; AVX512F-NEXT: vpermt2q %zmm10, %zmm8, %zmm2 +; AVX512F-NEXT: vmovdqa64 %zmm17, 64(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm2, 128(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm1, 192(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm12, 256(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm5, 320(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm15, 448(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm7, 512(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm0, 576(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm9, 640(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm13, 704(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm19, 384(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm18, (%rax) +; AVX512F-NEXT: vzeroupper +; AVX512F-NEXT: retq ; -; AVX512DQBW-ONLY-LABEL: store_i64_stride6_vf16: -; AVX512DQBW-ONLY: # %bb.0: -; AVX512DQBW-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%rdi), %zmm13 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 (%rdi), %zmm5 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 (%rsi), %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%rsi), %zmm14 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%rdx), %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 (%rdx), %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 (%rcx), %zmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%rcx), %zmm11 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 (%r8), %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%r8), %zmm8 -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm0 = [4,12,5,13,4,12,5,13] -; AVX512DQBW-ONLY-NEXT: # zmm0 = mem[0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm6, %zmm0, %zmm1 -; AVX512DQBW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm9 = [4,12,4,12] -; AVX512DQBW-ONLY-NEXT: # ymm9 = mem[0,1,0,1] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm10 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm4, %zmm9, %zmm10 -; AVX512DQBW-ONLY-NEXT: movb $12, %r10b -; AVX512DQBW-ONLY-NEXT: kmovd %r10d, %k1 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm1 {%k1} -; AVX512DQBW-ONLY-NEXT: movb $16, %r10b -; AVX512DQBW-ONLY-NEXT: kmovd %r10d, %k2 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm1 {%k2} -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm14, %zmm13, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm11, %zmm7, %zmm9 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm9, %zmm0 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 (%r9), %zmm10 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%r9), %zmm16 -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm18 = [6,14,6,14,6,14,6,14] -; AVX512DQBW-ONLY-NEXT: # zmm18 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm13, %zmm15 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm14, %zmm18, %zmm15 -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm12 = [5,13,6,14,5,13,6,14] -; AVX512DQBW-ONLY-NEXT: # zmm12 = mem[0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm9 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm11, %zmm12, %zmm9 -; AVX512DQBW-ONLY-NEXT: movb $48, %r9b -; AVX512DQBW-ONLY-NEXT: kmovd %r9d, %k2 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm15, %zmm9 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm19 = <0,1,13,u,4,5,6,7> -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm8, %zmm19, %zmm9 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm20 = [0,1,2,13,4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm16, %zmm20, %zmm9 -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm21 = [2,10,2,10,2,10,2,10] -; AVX512DQBW-ONLY-NEXT: # zmm21 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm13, %zmm22 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm14, %zmm21, %zmm22 -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm17 = [1,9,2,10,1,9,2,10] -; AVX512DQBW-ONLY-NEXT: # zmm17 = mem[0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm15 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm11, %zmm17, %zmm15 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm22, %zmm15 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm22 = <0,1,9,u,4,5,6,7> -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm8, %zmm22, %zmm15 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm23 = [0,1,2,9,4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm16, %zmm23, %zmm15 -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm6, %zmm5, %zmm18 -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm4, %zmm2, %zmm12 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm18, %zmm12 {%k2} -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm3, %zmm19, %zmm12 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm10, %zmm20, %zmm12 -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm6, %zmm5, %zmm21 -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm4, %zmm2, %zmm17 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm21, %zmm17 {%k2} -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm3, %zmm22, %zmm17 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm10, %zmm23, %zmm17 -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm19 = [0,8,1,9,0,8,1,9] -; AVX512DQBW-ONLY-NEXT: # zmm19 = mem[0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm18 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm6, %zmm19, %zmm18 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 (%rdx), %xmm20 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%rdx), %xmm21 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm20 = xmm20[0],mem[0] -; AVX512DQBW-ONLY-NEXT: vinserti32x4 $1, %xmm20, %ymm0, %ymm20 -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm20, %zmm0, %zmm18 {%k1} -; AVX512DQBW-ONLY-NEXT: vinserti32x4 $2, (%r8), %zmm18, %zmm18 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm20 = [0,1,2,3,4,8,6,7] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm10, %zmm20, %zmm18 -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm14, %zmm13, %zmm19 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm21 = xmm21[0],mem[0] -; AVX512DQBW-ONLY-NEXT: vinserti32x4 $1, %xmm21, %ymm0, %ymm21 -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm21, %zmm0, %zmm19 {%k1} -; AVX512DQBW-ONLY-NEXT: vinserti32x4 $2, 64(%r8), %zmm19, %zmm19 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm16, %zmm20, %zmm19 -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm20 = [7,15,7,15,7,15,7,15] -; AVX512DQBW-ONLY-NEXT: # zmm20 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm21 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm11, %zmm20, %zmm21 -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x2 {{.*#+}} ymm22 = [7,15,7,15] -; AVX512DQBW-ONLY-NEXT: # ymm22 = mem[0,1,0,1] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm14, %zmm22, %zmm13 -; AVX512DQBW-ONLY-NEXT: vshufi64x2 {{.*#+}} zmm13 = zmm13[0,1,2,3],zmm21[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm14 = <14,u,2,3,4,5,15,u> -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm8, %zmm14, %zmm13 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm21 = [0,14,2,3,4,5,6,15] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm16, %zmm21, %zmm13 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm23 = [0,1,2,3,4,12,6,7] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm16, %zmm23, %zmm0 -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm24 = [3,11,3,11,3,11,3,11] -; AVX512DQBW-ONLY-NEXT: # zmm24 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm11, %zmm24, %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqa (%rdi), %ymm11 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%rdi), %ymm25 -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm25 = ymm25[1],mem[1],ymm25[3],mem[3] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm25, %zmm7, %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm25 = <10,u,2,3,4,5,11,u> -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm8, %zmm25, %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm8 = [0,10,2,3,4,5,6,11] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm16, %zmm8, %zmm7 -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm4, %zmm2, %zmm20 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm6, %zmm22, %zmm5 -; AVX512DQBW-ONLY-NEXT: vshufi64x2 {{.*#+}} zmm5 = zmm5[0,1,2,3],zmm20[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm3, %zmm14, %zmm5 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm10, %zmm21, %zmm5 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm10, %zmm23, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm4, %zmm24, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm4 = ymm11[1],mem[1],ymm11[3],mem[3] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm2, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm3, %zmm25, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm10, %zmm8, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm17, 64(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, 128(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm1, 192(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm12, 256(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, 320(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm15, 448(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, 512(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, 576(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm9, 640(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm13, 704(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm19, 384(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm18, (%rax) -; AVX512DQBW-ONLY-NEXT: vzeroupper -; AVX512DQBW-ONLY-NEXT: retq +; AVX512BW-LABEL: store_i64_stride6_vf16: +; AVX512BW: # %bb.0: +; AVX512BW-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512BW-NEXT: vmovdqa64 64(%rdi), %zmm13 +; AVX512BW-NEXT: vmovdqa64 (%rdi), %zmm5 +; AVX512BW-NEXT: vmovdqa64 (%rsi), %zmm6 +; AVX512BW-NEXT: vmovdqa64 64(%rsi), %zmm14 +; AVX512BW-NEXT: vmovdqa64 64(%rdx), %zmm7 +; AVX512BW-NEXT: vmovdqa64 (%rdx), %zmm2 +; AVX512BW-NEXT: vmovdqa64 (%rcx), %zmm4 +; AVX512BW-NEXT: vmovdqa64 64(%rcx), %zmm11 +; AVX512BW-NEXT: vmovdqa64 (%r8), %zmm3 +; AVX512BW-NEXT: vmovdqa64 64(%r8), %zmm8 +; AVX512BW-NEXT: vbroadcasti64x4 {{.*#+}} zmm0 = [4,12,5,13,4,12,5,13] +; AVX512BW-NEXT: # zmm0 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm1 +; AVX512BW-NEXT: vpermt2q %zmm6, %zmm0, %zmm1 +; AVX512BW-NEXT: vbroadcasti128 {{.*#+}} ymm9 = [4,12,4,12] +; AVX512BW-NEXT: # ymm9 = mem[0,1,0,1] +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm10 +; AVX512BW-NEXT: vpermt2q %zmm4, %zmm9, %zmm10 +; AVX512BW-NEXT: movb $12, %r10b +; AVX512BW-NEXT: kmovd %r10d, %k1 +; AVX512BW-NEXT: vmovdqa64 %zmm10, %zmm1 {%k1} +; AVX512BW-NEXT: movb $16, %r10b +; AVX512BW-NEXT: kmovd %r10d, %k2 +; AVX512BW-NEXT: vmovdqa64 %zmm3, %zmm1 {%k2} +; AVX512BW-NEXT: vpermi2q %zmm14, %zmm13, %zmm0 +; AVX512BW-NEXT: vpermi2q %zmm11, %zmm7, %zmm9 +; AVX512BW-NEXT: vmovdqa64 %zmm9, %zmm0 {%k1} +; AVX512BW-NEXT: vmovdqa64 %zmm8, %zmm0 {%k2} +; AVX512BW-NEXT: vmovdqa64 (%r9), %zmm10 +; AVX512BW-NEXT: vmovdqa64 64(%r9), %zmm16 +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm18 = [6,14,6,14,6,14,6,14] +; AVX512BW-NEXT: # zmm18 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm13, %zmm15 +; AVX512BW-NEXT: vpermt2q %zmm14, %zmm18, %zmm15 +; AVX512BW-NEXT: vbroadcasti64x4 {{.*#+}} zmm12 = [5,13,6,14,5,13,6,14] +; AVX512BW-NEXT: # zmm12 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm9 +; AVX512BW-NEXT: vpermt2q %zmm11, %zmm12, %zmm9 +; AVX512BW-NEXT: movb $48, %r9b +; AVX512BW-NEXT: kmovd %r9d, %k2 +; AVX512BW-NEXT: vmovdqa64 %zmm15, %zmm9 {%k2} +; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm19 = <0,1,13,u,4,5,6,7> +; AVX512BW-NEXT: vpermt2q %zmm8, %zmm19, %zmm9 +; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm20 = [0,1,2,13,4,5,6,7] +; AVX512BW-NEXT: vpermt2q %zmm16, %zmm20, %zmm9 +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm21 = [2,10,2,10,2,10,2,10] +; AVX512BW-NEXT: # zmm21 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm13, %zmm22 +; AVX512BW-NEXT: vpermt2q %zmm14, %zmm21, %zmm22 +; AVX512BW-NEXT: vbroadcasti64x4 {{.*#+}} zmm17 = [1,9,2,10,1,9,2,10] +; AVX512BW-NEXT: # zmm17 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm15 +; AVX512BW-NEXT: vpermt2q %zmm11, %zmm17, %zmm15 +; AVX512BW-NEXT: vmovdqa64 %zmm22, %zmm15 {%k2} +; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm22 = <0,1,9,u,4,5,6,7> +; AVX512BW-NEXT: vpermt2q %zmm8, %zmm22, %zmm15 +; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm23 = [0,1,2,9,4,5,6,7] +; AVX512BW-NEXT: vpermt2q %zmm16, %zmm23, %zmm15 +; AVX512BW-NEXT: vpermi2q %zmm6, %zmm5, %zmm18 +; AVX512BW-NEXT: vpermi2q %zmm4, %zmm2, %zmm12 +; AVX512BW-NEXT: vmovdqa64 %zmm18, %zmm12 {%k2} +; AVX512BW-NEXT: vpermt2q %zmm3, %zmm19, %zmm12 +; AVX512BW-NEXT: vpermt2q %zmm10, %zmm20, %zmm12 +; AVX512BW-NEXT: vpermi2q %zmm6, %zmm5, %zmm21 +; AVX512BW-NEXT: vpermi2q %zmm4, %zmm2, %zmm17 +; AVX512BW-NEXT: vmovdqa64 %zmm21, %zmm17 {%k2} +; AVX512BW-NEXT: vpermt2q %zmm3, %zmm22, %zmm17 +; AVX512BW-NEXT: vpermt2q %zmm10, %zmm23, %zmm17 +; AVX512BW-NEXT: vbroadcasti64x4 {{.*#+}} zmm19 = [0,8,1,9,0,8,1,9] +; AVX512BW-NEXT: # zmm19 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm18 +; AVX512BW-NEXT: vpermt2q %zmm6, %zmm19, %zmm18 +; AVX512BW-NEXT: vmovdqa64 (%rdx), %xmm20 +; AVX512BW-NEXT: vmovdqa64 64(%rdx), %xmm21 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} xmm20 = xmm20[0],mem[0] +; AVX512BW-NEXT: vinserti32x4 $1, %xmm20, %ymm0, %ymm20 +; AVX512BW-NEXT: vinserti64x4 $0, %ymm20, %zmm0, %zmm18 {%k1} +; AVX512BW-NEXT: vinserti32x4 $2, (%r8), %zmm18, %zmm18 +; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm20 = [0,1,2,3,4,8,6,7] +; AVX512BW-NEXT: vpermt2q %zmm10, %zmm20, %zmm18 +; AVX512BW-NEXT: vpermi2q %zmm14, %zmm13, %zmm19 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} xmm21 = xmm21[0],mem[0] +; AVX512BW-NEXT: vinserti32x4 $1, %xmm21, %ymm0, %ymm21 +; AVX512BW-NEXT: vinserti64x4 $0, %ymm21, %zmm0, %zmm19 {%k1} +; AVX512BW-NEXT: vinserti32x4 $2, 64(%r8), %zmm19, %zmm19 +; AVX512BW-NEXT: vpermt2q %zmm16, %zmm20, %zmm19 +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm20 = [7,15,7,15,7,15,7,15] +; AVX512BW-NEXT: # zmm20 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm21 +; AVX512BW-NEXT: vpermt2q %zmm11, %zmm20, %zmm21 +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} ymm22 = [7,15,7,15] +; AVX512BW-NEXT: # ymm22 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vpermt2q %zmm14, %zmm22, %zmm13 +; AVX512BW-NEXT: vshufi64x2 {{.*#+}} zmm13 = zmm13[0,1,2,3],zmm21[4,5,6,7] +; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm14 = <14,u,2,3,4,5,15,u> +; AVX512BW-NEXT: vpermt2q %zmm8, %zmm14, %zmm13 +; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm21 = [0,14,2,3,4,5,6,15] +; AVX512BW-NEXT: vpermt2q %zmm16, %zmm21, %zmm13 +; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm23 = [0,1,2,3,4,12,6,7] +; AVX512BW-NEXT: vpermt2q %zmm16, %zmm23, %zmm0 +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm24 = [3,11,3,11,3,11,3,11] +; AVX512BW-NEXT: # zmm24 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vpermt2q %zmm11, %zmm24, %zmm7 +; AVX512BW-NEXT: vmovdqa (%rdi), %ymm11 +; AVX512BW-NEXT: vmovdqa64 64(%rdi), %ymm25 +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm25 = ymm25[1],mem[1],ymm25[3],mem[3] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm25, %zmm7, %zmm7 +; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm25 = <10,u,2,3,4,5,11,u> +; AVX512BW-NEXT: vpermt2q %zmm8, %zmm25, %zmm7 +; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm8 = [0,10,2,3,4,5,6,11] +; AVX512BW-NEXT: vpermt2q %zmm16, %zmm8, %zmm7 +; AVX512BW-NEXT: vpermi2q %zmm4, %zmm2, %zmm20 +; AVX512BW-NEXT: vpermt2q %zmm6, %zmm22, %zmm5 +; AVX512BW-NEXT: vshufi64x2 {{.*#+}} zmm5 = zmm5[0,1,2,3],zmm20[4,5,6,7] +; AVX512BW-NEXT: vpermt2q %zmm3, %zmm14, %zmm5 +; AVX512BW-NEXT: vpermt2q %zmm10, %zmm21, %zmm5 +; AVX512BW-NEXT: vpermt2q %zmm10, %zmm23, %zmm1 +; AVX512BW-NEXT: vpermt2q %zmm4, %zmm24, %zmm2 +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm4 = ymm11[1],mem[1],ymm11[3],mem[3] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm4, %zmm2, %zmm2 +; AVX512BW-NEXT: vpermt2q %zmm3, %zmm25, %zmm2 +; AVX512BW-NEXT: vpermt2q %zmm10, %zmm8, %zmm2 +; AVX512BW-NEXT: vmovdqa64 %zmm17, 64(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm2, 128(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm1, 192(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm12, 256(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm5, 320(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm15, 448(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm7, 512(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm0, 576(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm9, 640(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm13, 704(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm19, 384(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm18, (%rax) +; AVX512BW-NEXT: vzeroupper +; AVX512BW-NEXT: retq %in.vec0 = load <16 x i64>, ptr %in.vecptr0, align 64 %in.vec1 = load <16 x i64>, ptr %in.vecptr1, align 64 %in.vec2 = load <16 x i64>, ptr %in.vecptr2, align 64 @@ -3429,1121 +3149,563 @@ define void @store_i64_stride6_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve ; AVX2-ONLY-NEXT: vzeroupper ; AVX2-ONLY-NEXT: retq ; -; AVX512F-ONLY-LABEL: store_i64_stride6_vf32: -; AVX512F-ONLY: # %bb.0: -; AVX512F-ONLY-NEXT: subq $712, %rsp # imm = 0x2C8 -; AVX512F-ONLY-NEXT: vmovdqa64 (%rdi), %zmm7 -; AVX512F-ONLY-NEXT: vmovdqa64 64(%rdi), %zmm4 -; AVX512F-ONLY-NEXT: vmovdqa64 128(%rdi), %zmm2 -; AVX512F-ONLY-NEXT: vmovdqa64 192(%rdi), %zmm18 -; AVX512F-ONLY-NEXT: vmovdqa64 (%rsi), %zmm22 -; AVX512F-ONLY-NEXT: vmovdqa64 64(%rsi), %zmm1 -; AVX512F-ONLY-NEXT: vmovdqa64 128(%rsi), %zmm19 -; AVX512F-ONLY-NEXT: vmovdqa64 192(%rsi), %zmm21 -; AVX512F-ONLY-NEXT: vmovdqa64 (%rdx), %zmm8 -; AVX512F-ONLY-NEXT: vmovdqa64 64(%rdx), %zmm6 -; AVX512F-ONLY-NEXT: vmovdqa64 128(%rdx), %zmm5 -; AVX512F-ONLY-NEXT: vmovdqa64 192(%rdx), %zmm12 -; AVX512F-ONLY-NEXT: vmovdqa64 (%rcx), %zmm29 -; AVX512F-ONLY-NEXT: vmovdqa64 64(%rcx), %zmm27 -; AVX512F-ONLY-NEXT: vmovdqa64 128(%rcx), %zmm26 -; AVX512F-ONLY-NEXT: vmovdqa64 192(%rcx), %zmm25 -; AVX512F-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm11 = [4,12,5,13,4,12,5,13] -; AVX512F-ONLY-NEXT: # zmm11 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} ymm20 = [4,12,4,12] -; AVX512F-ONLY-NEXT: # ymm20 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm12, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm25, %zmm20, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm5, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm26, %zmm20, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm6, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm27, %zmm20, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermi2q %zmm29, %zmm8, %zmm20 -; AVX512F-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm10 = [1,9,2,10,1,9,2,10] -; AVX512F-ONLY-NEXT: # zmm10 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm29, %zmm10, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm13 = [5,13,6,14,5,13,6,14] -; AVX512F-ONLY-NEXT: # zmm13 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm8, %zmm17 -; AVX512F-ONLY-NEXT: vpermt2q %zmm29, %zmm13, %zmm17 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm6, %zmm31 -; AVX512F-ONLY-NEXT: vpermt2q %zmm27, %zmm10, %zmm31 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm6, %zmm14 -; AVX512F-ONLY-NEXT: vpermt2q %zmm27, %zmm13, %zmm14 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm5, %zmm15 -; AVX512F-ONLY-NEXT: vpermt2q %zmm26, %zmm10, %zmm15 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm5, %zmm16 -; AVX512F-ONLY-NEXT: vpermt2q %zmm26, %zmm13, %zmm16 -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm28 = [3,11,3,11,3,11,3,11] -; AVX512F-ONLY-NEXT: # zmm28 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm29, %zmm28, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = [7,15,7,15,7,15,7,15] -; AVX512F-ONLY-NEXT: # zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vpermt2q %zmm29, %zmm0, %zmm8 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm6, %zmm29 -; AVX512F-ONLY-NEXT: vpermt2q %zmm27, %zmm28, %zmm29 -; AVX512F-ONLY-NEXT: vpermt2q %zmm27, %zmm0, %zmm6 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm5, %zmm6 -; AVX512F-ONLY-NEXT: vpermt2q %zmm26, %zmm28, %zmm6 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm26, %zmm0, %zmm5 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm18, %zmm26 -; AVX512F-ONLY-NEXT: vpermt2q %zmm21, %zmm11, %zmm26 -; AVX512F-ONLY-NEXT: vpermi2q %zmm25, %zmm12, %zmm10 -; AVX512F-ONLY-NEXT: vpermi2q %zmm25, %zmm12, %zmm13 -; AVX512F-ONLY-NEXT: vpermi2q %zmm25, %zmm12, %zmm28 -; AVX512F-ONLY-NEXT: vpermt2q %zmm25, %zmm0, %zmm12 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm27 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm9 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm19, %zmm5 -; AVX512F-ONLY-NEXT: vpermt2q %zmm19, %zmm11, %zmm9 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm25 -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm11, %zmm25 -; AVX512F-ONLY-NEXT: vpermi2q %zmm22, %zmm7, %zmm11 -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm3 = [2,10,2,10,2,10,2,10] -; AVX512F-ONLY-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, %zmm23 -; AVX512F-ONLY-NEXT: vpermt2q %zmm22, %zmm3, %zmm23 -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm6 = [6,14,6,14,6,14,6,14] -; AVX512F-ONLY-NEXT: # zmm6 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, %zmm24 -; AVX512F-ONLY-NEXT: vpermt2q %zmm22, %zmm6, %zmm24 -; AVX512F-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm2 = [0,8,1,9,0,8,1,9] -; AVX512F-ONLY-NEXT: # zmm2 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, %zmm30 -; AVX512F-ONLY-NEXT: vpermt2q %zmm22, %zmm2, %zmm30 -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} ymm19 = [7,15,7,15] -; AVX512F-ONLY-NEXT: # ymm19 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vpermt2q %zmm22, %zmm19, %zmm7 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm22 -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm3, %zmm22 -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm6, %zmm4 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, %zmm8 -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm2, %zmm8 -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm19, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, (%rsp) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm27, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm3, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm27, %zmm1 -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm6, %zmm1 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm27, %zmm7 -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm2, %zmm7 -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm19, %zmm27 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm27, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermi2q %zmm21, %zmm18, %zmm3 -; AVX512F-ONLY-NEXT: vpermi2q %zmm21, %zmm18, %zmm6 -; AVX512F-ONLY-NEXT: vpermi2q %zmm21, %zmm18, %zmm2 -; AVX512F-ONLY-NEXT: vpermt2q %zmm21, %zmm19, %zmm18 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm18, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: movb $12, %al -; AVX512F-ONLY-NEXT: kmovw %eax, %k1 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm5, %zmm26 {%k1} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm5, %zmm9 {%k1} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm5, %zmm25 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm20, %zmm11 {%k1} -; AVX512F-ONLY-NEXT: movb $48, %al -; AVX512F-ONLY-NEXT: kmovw %eax, %k2 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm23, %zmm5 {%k2} -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm24, %zmm17 {%k2} -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm22, %zmm31 {%k2} -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm14 {%k2} -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, %zmm15 {%k2} -; AVX512F-ONLY-NEXT: vmovdqa64 (%r8), %zmm23 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm1, %zmm16 {%k2} -; AVX512F-ONLY-NEXT: vmovdqa64 64(%r8), %zmm1 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm3, %zmm10 {%k2} -; AVX512F-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm0 = <0,1,9,u,4,5,6,7> -; AVX512F-ONLY-NEXT: vpermt2q %zmm23, %zmm0, %zmm5 -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm0, %zmm31 -; AVX512F-ONLY-NEXT: vmovdqa64 128(%r8), %zmm3 -; AVX512F-ONLY-NEXT: vpermt2q %zmm3, %zmm0, %zmm15 -; AVX512F-ONLY-NEXT: vmovdqa64 192(%r8), %zmm22 -; AVX512F-ONLY-NEXT: vpermt2q %zmm22, %zmm0, %zmm10 -; AVX512F-ONLY-NEXT: vmovdqa64 (%r9), %zmm20 -; AVX512F-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm0 = [0,1,2,9,4,5,6,7] -; AVX512F-ONLY-NEXT: vpermt2q %zmm20, %zmm0, %zmm5 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 64(%r9), %zmm21 -; AVX512F-ONLY-NEXT: vpermt2q %zmm21, %zmm0, %zmm31 -; AVX512F-ONLY-NEXT: vmovdqa64 128(%r9), %zmm19 -; AVX512F-ONLY-NEXT: vpermt2q %zmm19, %zmm0, %zmm15 -; AVX512F-ONLY-NEXT: vmovdqa64 192(%r9), %zmm18 -; AVX512F-ONLY-NEXT: vpermt2q %zmm18, %zmm0, %zmm10 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm6, %zmm13 {%k2} -; AVX512F-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm0 = <0,1,13,u,4,5,6,7> -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm17, %zmm27 -; AVX512F-ONLY-NEXT: vpermt2q %zmm23, %zmm0, %zmm27 -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm0, %zmm14 -; AVX512F-ONLY-NEXT: vpermt2q %zmm3, %zmm0, %zmm16 -; AVX512F-ONLY-NEXT: vpermt2q %zmm22, %zmm0, %zmm13 -; AVX512F-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm0 = [0,1,2,13,4,5,6,7] -; AVX512F-ONLY-NEXT: vpermt2q %zmm20, %zmm0, %zmm27 -; AVX512F-ONLY-NEXT: vpermt2q %zmm21, %zmm0, %zmm14 -; AVX512F-ONLY-NEXT: vpermt2q %zmm19, %zmm0, %zmm16 -; AVX512F-ONLY-NEXT: vpermt2q %zmm18, %zmm0, %zmm13 -; AVX512F-ONLY-NEXT: vmovdqa (%rdx), %xmm0 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],mem[0] -; AVX512F-ONLY-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm0, %zmm30 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa 64(%rdx), %xmm0 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],mem[0] -; AVX512F-ONLY-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm0, %zmm8 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa 128(%rdx), %xmm0 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],mem[0] -; AVX512F-ONLY-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm0, %zmm7 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa 192(%rdx), %xmm0 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],mem[0] -; AVX512F-ONLY-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm0, %zmm2 {%k1} -; AVX512F-ONLY-NEXT: vinserti32x4 $2, (%r8), %zmm30, %zmm24 -; AVX512F-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm0 = [0,1,2,3,4,8,6,7] -; AVX512F-ONLY-NEXT: vpermt2q %zmm20, %zmm0, %zmm24 -; AVX512F-ONLY-NEXT: vinserti32x4 $2, 64(%r8), %zmm8, %zmm6 -; AVX512F-ONLY-NEXT: vpermt2q %zmm21, %zmm0, %zmm6 -; AVX512F-ONLY-NEXT: vinserti32x4 $2, 128(%r8), %zmm7, %zmm5 -; AVX512F-ONLY-NEXT: vpermt2q %zmm19, %zmm0, %zmm5 -; AVX512F-ONLY-NEXT: vinserti32x4 $2, 192(%r8), %zmm2, %zmm4 -; AVX512F-ONLY-NEXT: vpermt2q %zmm18, %zmm0, %zmm4 -; AVX512F-ONLY-NEXT: vmovdqa (%rdi), %ymm0 -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm2, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512F-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm2, %zmm2 # 64-byte Folded Reload -; AVX512F-ONLY-NEXT: # zmm2 = zmm2[0,1,2,3],mem[4,5,6,7] -; AVX512F-ONLY-NEXT: movb $16, %al -; AVX512F-ONLY-NEXT: kmovw %eax, %k1 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm23, %zmm11 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm7 = <10,u,2,3,4,5,11,u> -; AVX512F-ONLY-NEXT: vpermt2q %zmm23, %zmm7, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm17 = <14,u,2,3,4,5,15,u> -; AVX512F-ONLY-NEXT: vpermt2q %zmm23, %zmm17, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqa64 64(%rdi), %ymm23 -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm23 = ymm23[1],mem[1],ymm23[3],mem[3] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm23, %zmm29, %zmm23 -; AVX512F-ONLY-NEXT: vmovdqu64 (%rsp), %zmm8 # 64-byte Reload -; AVX512F-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm8, %zmm29 # 64-byte Folded Reload -; AVX512F-ONLY-NEXT: # zmm29 = zmm8[0,1,2,3],mem[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm1, %zmm25 {%k1} -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm7, %zmm23 -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm17, %zmm29 -; AVX512F-ONLY-NEXT: vmovdqa 128(%rdi), %ymm1 -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm1[1],mem[1],ymm1[3],mem[3] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm8 # 64-byte Reload -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm8, %zmm1 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm8 # 64-byte Reload -; AVX512F-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm8, %zmm30 # 64-byte Folded Reload -; AVX512F-ONLY-NEXT: # zmm30 = zmm8[0,1,2,3],mem[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm3, %zmm9 {%k1} -; AVX512F-ONLY-NEXT: vpermt2q %zmm3, %zmm7, %zmm1 -; AVX512F-ONLY-NEXT: vpermt2q %zmm3, %zmm17, %zmm30 -; AVX512F-ONLY-NEXT: vmovdqa 192(%rdi), %ymm3 -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm3 = ymm3[1],mem[1],ymm3[3],mem[3] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm3, %zmm28, %zmm3 -; AVX512F-ONLY-NEXT: vpermt2q %zmm22, %zmm7, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm22, %zmm26 {%k1} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 # 64-byte Reload -; AVX512F-ONLY-NEXT: vshufi64x2 {{.*#+}} zmm7 = zmm7[0,1,2,3],zmm12[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm28 = [0,10,2,3,4,5,6,11] -; AVX512F-ONLY-NEXT: vpermt2q %zmm20, %zmm28, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm22, %zmm17, %zmm7 -; AVX512F-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm17 = [0,1,2,3,4,12,6,7] -; AVX512F-ONLY-NEXT: vpermt2q %zmm20, %zmm17, %zmm11 -; AVX512F-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm22 = [0,14,2,3,4,5,6,15] -; AVX512F-ONLY-NEXT: vpermt2q %zmm20, %zmm22, %zmm2 -; AVX512F-ONLY-NEXT: vpermt2q %zmm21, %zmm28, %zmm23 -; AVX512F-ONLY-NEXT: vpermt2q %zmm21, %zmm17, %zmm25 -; AVX512F-ONLY-NEXT: vpermt2q %zmm21, %zmm22, %zmm29 -; AVX512F-ONLY-NEXT: vpermt2q %zmm19, %zmm28, %zmm1 -; AVX512F-ONLY-NEXT: vpermt2q %zmm19, %zmm17, %zmm9 -; AVX512F-ONLY-NEXT: vpermt2q %zmm19, %zmm22, %zmm30 -; AVX512F-ONLY-NEXT: vpermt2q %zmm18, %zmm28, %zmm3 -; AVX512F-ONLY-NEXT: vpermt2q %zmm18, %zmm17, %zmm26 -; AVX512F-ONLY-NEXT: vpermt2q %zmm18, %zmm22, %zmm7 -; AVX512F-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, 1472(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm13, 1408(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm26, 1344(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm3, 1280(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm10, 1216(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm30, 1088(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm16, 1024(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm9, 960(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm1, 896(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm15, 832(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm29, 704(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm14, 640(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm25, 576(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm23, 512(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm31, 448(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, 320(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm27, 256(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm11, 192(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, 128(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 64(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, 1152(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm5, 768(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm6, 384(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm24, (%rax) -; AVX512F-ONLY-NEXT: addq $712, %rsp # imm = 0x2C8 -; AVX512F-ONLY-NEXT: vzeroupper -; AVX512F-ONLY-NEXT: retq -; -; AVX512DQ-ONLY-LABEL: store_i64_stride6_vf32: -; AVX512DQ-ONLY: # %bb.0: -; AVX512DQ-ONLY-NEXT: subq $712, %rsp # imm = 0x2C8 -; AVX512DQ-ONLY-NEXT: vmovdqa64 (%rdi), %zmm7 -; AVX512DQ-ONLY-NEXT: vmovdqa64 64(%rdi), %zmm4 -; AVX512DQ-ONLY-NEXT: vmovdqa64 128(%rdi), %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqa64 192(%rdi), %zmm18 -; AVX512DQ-ONLY-NEXT: vmovdqa64 (%rsi), %zmm22 -; AVX512DQ-ONLY-NEXT: vmovdqa64 64(%rsi), %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqa64 128(%rsi), %zmm19 -; AVX512DQ-ONLY-NEXT: vmovdqa64 192(%rsi), %zmm21 -; AVX512DQ-ONLY-NEXT: vmovdqa64 (%rdx), %zmm8 -; AVX512DQ-ONLY-NEXT: vmovdqa64 64(%rdx), %zmm6 -; AVX512DQ-ONLY-NEXT: vmovdqa64 128(%rdx), %zmm5 -; AVX512DQ-ONLY-NEXT: vmovdqa64 192(%rdx), %zmm12 -; AVX512DQ-ONLY-NEXT: vmovdqa64 (%rcx), %zmm29 -; AVX512DQ-ONLY-NEXT: vmovdqa64 64(%rcx), %zmm27 -; AVX512DQ-ONLY-NEXT: vmovdqa64 128(%rcx), %zmm26 -; AVX512DQ-ONLY-NEXT: vmovdqa64 192(%rcx), %zmm25 -; AVX512DQ-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm11 = [4,12,5,13,4,12,5,13] -; AVX512DQ-ONLY-NEXT: # zmm11 = mem[0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vbroadcasti64x2 {{.*#+}} ymm20 = [4,12,4,12] -; AVX512DQ-ONLY-NEXT: # ymm20 = mem[0,1,0,1] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm12, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm25, %zmm20, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm5, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm26, %zmm20, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm6, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm27, %zmm20, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm29, %zmm8, %zmm20 -; AVX512DQ-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm10 = [1,9,2,10,1,9,2,10] -; AVX512DQ-ONLY-NEXT: # zmm10 = mem[0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm29, %zmm10, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm13 = [5,13,6,14,5,13,6,14] -; AVX512DQ-ONLY-NEXT: # zmm13 = mem[0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm8, %zmm17 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm29, %zmm13, %zmm17 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm6, %zmm31 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm27, %zmm10, %zmm31 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm6, %zmm14 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm27, %zmm13, %zmm14 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm5, %zmm15 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm26, %zmm10, %zmm15 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm5, %zmm16 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm26, %zmm13, %zmm16 -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm28 = [3,11,3,11,3,11,3,11] -; AVX512DQ-ONLY-NEXT: # zmm28 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm29, %zmm28, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = [7,15,7,15,7,15,7,15] -; AVX512DQ-ONLY-NEXT: # zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm29, %zmm0, %zmm8 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm6, %zmm29 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm27, %zmm28, %zmm29 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm27, %zmm0, %zmm6 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm5, %zmm6 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm26, %zmm28, %zmm6 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm26, %zmm0, %zmm5 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm18, %zmm26 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm21, %zmm11, %zmm26 -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm25, %zmm12, %zmm10 -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm25, %zmm12, %zmm13 -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm25, %zmm12, %zmm28 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm25, %zmm0, %zmm12 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm27 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm9 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm19, %zmm5 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm19, %zmm11, %zmm9 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm25 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm11, %zmm25 -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm22, %zmm7, %zmm11 -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm3 = [2,10,2,10,2,10,2,10] -; AVX512DQ-ONLY-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, %zmm23 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm22, %zmm3, %zmm23 -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm6 = [6,14,6,14,6,14,6,14] -; AVX512DQ-ONLY-NEXT: # zmm6 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, %zmm24 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm22, %zmm6, %zmm24 -; AVX512DQ-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm2 = [0,8,1,9,0,8,1,9] -; AVX512DQ-ONLY-NEXT: # zmm2 = mem[0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, %zmm30 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm22, %zmm2, %zmm30 -; AVX512DQ-ONLY-NEXT: vbroadcasti64x2 {{.*#+}} ymm19 = [7,15,7,15] -; AVX512DQ-ONLY-NEXT: # ymm19 = mem[0,1,0,1] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm22, %zmm19, %zmm7 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm22 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm3, %zmm22 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm6, %zmm4 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, %zmm8 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm2, %zmm8 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm19, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, (%rsp) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm27, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm3, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm27, %zmm1 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm6, %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm27, %zmm7 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm2, %zmm7 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm19, %zmm27 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm27, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm21, %zmm18, %zmm3 -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm21, %zmm18, %zmm6 -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm21, %zmm18, %zmm2 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm21, %zmm19, %zmm18 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm18, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: movb $12, %al -; AVX512DQ-ONLY-NEXT: kmovw %eax, %k1 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm5, %zmm26 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm5, %zmm9 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm5, %zmm25 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm20, %zmm11 {%k1} -; AVX512DQ-ONLY-NEXT: movb $48, %al -; AVX512DQ-ONLY-NEXT: kmovw %eax, %k2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm23, %zmm5 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm24, %zmm17 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm22, %zmm31 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm14 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, %zmm15 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqa64 (%r8), %zmm23 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm1, %zmm16 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqa64 64(%r8), %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm3, %zmm10 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm0 = <0,1,9,u,4,5,6,7> -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm23, %zmm0, %zmm5 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm0, %zmm31 -; AVX512DQ-ONLY-NEXT: vmovdqa64 128(%r8), %zmm3 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm3, %zmm0, %zmm15 -; AVX512DQ-ONLY-NEXT: vmovdqa64 192(%r8), %zmm22 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm22, %zmm0, %zmm10 -; AVX512DQ-ONLY-NEXT: vmovdqa64 (%r9), %zmm20 -; AVX512DQ-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm0 = [0,1,2,9,4,5,6,7] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm20, %zmm0, %zmm5 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 64(%r9), %zmm21 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm21, %zmm0, %zmm31 -; AVX512DQ-ONLY-NEXT: vmovdqa64 128(%r9), %zmm19 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm19, %zmm0, %zmm15 -; AVX512DQ-ONLY-NEXT: vmovdqa64 192(%r9), %zmm18 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm18, %zmm0, %zmm10 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm6, %zmm13 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm0 = <0,1,13,u,4,5,6,7> -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm17, %zmm27 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm23, %zmm0, %zmm27 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm0, %zmm14 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm3, %zmm0, %zmm16 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm22, %zmm0, %zmm13 -; AVX512DQ-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm0 = [0,1,2,13,4,5,6,7] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm20, %zmm0, %zmm27 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm21, %zmm0, %zmm14 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm19, %zmm0, %zmm16 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm18, %zmm0, %zmm13 -; AVX512DQ-ONLY-NEXT: vmovdqa (%rdx), %xmm0 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],mem[0] -; AVX512DQ-ONLY-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm0, %zmm30 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa 64(%rdx), %xmm0 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],mem[0] -; AVX512DQ-ONLY-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm0, %zmm8 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa 128(%rdx), %xmm0 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],mem[0] -; AVX512DQ-ONLY-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm0, %zmm7 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa 192(%rdx), %xmm0 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],mem[0] -; AVX512DQ-ONLY-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm0, %zmm2 {%k1} -; AVX512DQ-ONLY-NEXT: vinserti32x4 $2, (%r8), %zmm30, %zmm24 -; AVX512DQ-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm0 = [0,1,2,3,4,8,6,7] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm20, %zmm0, %zmm24 -; AVX512DQ-ONLY-NEXT: vinserti32x4 $2, 64(%r8), %zmm8, %zmm6 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm21, %zmm0, %zmm6 -; AVX512DQ-ONLY-NEXT: vinserti32x4 $2, 128(%r8), %zmm7, %zmm5 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm19, %zmm0, %zmm5 -; AVX512DQ-ONLY-NEXT: vinserti32x4 $2, 192(%r8), %zmm2, %zmm4 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm18, %zmm0, %zmm4 -; AVX512DQ-ONLY-NEXT: vmovdqa (%rdi), %ymm0 -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm2, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm2, %zmm2 # 64-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # zmm2 = zmm2[0,1,2,3],mem[4,5,6,7] -; AVX512DQ-ONLY-NEXT: movb $16, %al -; AVX512DQ-ONLY-NEXT: kmovw %eax, %k1 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm23, %zmm11 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm7 = <10,u,2,3,4,5,11,u> -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm23, %zmm7, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm17 = <14,u,2,3,4,5,15,u> -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm23, %zmm17, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqa64 64(%rdi), %ymm23 -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm23 = ymm23[1],mem[1],ymm23[3],mem[3] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm23, %zmm29, %zmm23 -; AVX512DQ-ONLY-NEXT: vmovdqu64 (%rsp), %zmm8 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm8, %zmm29 # 64-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # zmm29 = zmm8[0,1,2,3],mem[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm1, %zmm25 {%k1} -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm7, %zmm23 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm17, %zmm29 -; AVX512DQ-ONLY-NEXT: vmovdqa 128(%rdi), %ymm1 -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm1[1],mem[1],ymm1[3],mem[3] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm8 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm8, %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm8 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm8, %zmm30 # 64-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # zmm30 = zmm8[0,1,2,3],mem[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm3, %zmm9 {%k1} -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm3, %zmm7, %zmm1 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm3, %zmm17, %zmm30 -; AVX512DQ-ONLY-NEXT: vmovdqa 192(%rdi), %ymm3 -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm3 = ymm3[1],mem[1],ymm3[3],mem[3] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm3, %zmm28, %zmm3 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm22, %zmm7, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm22, %zmm26 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vshufi64x2 {{.*#+}} zmm7 = zmm7[0,1,2,3],zmm12[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm28 = [0,10,2,3,4,5,6,11] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm20, %zmm28, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm22, %zmm17, %zmm7 -; AVX512DQ-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm17 = [0,1,2,3,4,12,6,7] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm20, %zmm17, %zmm11 -; AVX512DQ-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm22 = [0,14,2,3,4,5,6,15] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm20, %zmm22, %zmm2 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm21, %zmm28, %zmm23 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm21, %zmm17, %zmm25 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm21, %zmm22, %zmm29 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm19, %zmm28, %zmm1 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm19, %zmm17, %zmm9 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm19, %zmm22, %zmm30 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm18, %zmm28, %zmm3 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm18, %zmm17, %zmm26 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm18, %zmm22, %zmm7 -; AVX512DQ-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, 1472(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm13, 1408(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm26, 1344(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm3, 1280(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm10, 1216(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm30, 1088(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm16, 1024(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm9, 960(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm1, 896(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm15, 832(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm29, 704(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm14, 640(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm25, 576(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm23, 512(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm31, 448(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, 320(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm27, 256(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm11, 192(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, 128(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 64(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, 1152(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm5, 768(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm6, 384(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm24, (%rax) -; AVX512DQ-ONLY-NEXT: addq $712, %rsp # imm = 0x2C8 -; AVX512DQ-ONLY-NEXT: vzeroupper -; AVX512DQ-ONLY-NEXT: retq -; -; AVX512BW-ONLY-LABEL: store_i64_stride6_vf32: -; AVX512BW-ONLY: # %bb.0: -; AVX512BW-ONLY-NEXT: subq $712, %rsp # imm = 0x2C8 -; AVX512BW-ONLY-NEXT: vmovdqa64 (%rdi), %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%rdi), %zmm4 -; AVX512BW-ONLY-NEXT: vmovdqa64 128(%rdi), %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqa64 192(%rdi), %zmm18 -; AVX512BW-ONLY-NEXT: vmovdqa64 (%rsi), %zmm22 -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%rsi), %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqa64 128(%rsi), %zmm19 -; AVX512BW-ONLY-NEXT: vmovdqa64 192(%rsi), %zmm21 -; AVX512BW-ONLY-NEXT: vmovdqa64 (%rdx), %zmm8 -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%rdx), %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqa64 128(%rdx), %zmm5 -; AVX512BW-ONLY-NEXT: vmovdqa64 192(%rdx), %zmm12 -; AVX512BW-ONLY-NEXT: vmovdqa64 (%rcx), %zmm29 -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%rcx), %zmm27 -; AVX512BW-ONLY-NEXT: vmovdqa64 128(%rcx), %zmm26 -; AVX512BW-ONLY-NEXT: vmovdqa64 192(%rcx), %zmm25 -; AVX512BW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm11 = [4,12,5,13,4,12,5,13] -; AVX512BW-ONLY-NEXT: # zmm11 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} ymm20 = [4,12,4,12] -; AVX512BW-ONLY-NEXT: # ymm20 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm25, %zmm20, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm26, %zmm20, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm27, %zmm20, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermi2q %zmm29, %zmm8, %zmm20 -; AVX512BW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm10 = [1,9,2,10,1,9,2,10] -; AVX512BW-ONLY-NEXT: # zmm10 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm29, %zmm10, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm13 = [5,13,6,14,5,13,6,14] -; AVX512BW-ONLY-NEXT: # zmm13 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm8, %zmm17 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm29, %zmm13, %zmm17 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm31 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm27, %zmm10, %zmm31 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm14 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm27, %zmm13, %zmm14 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm15 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm26, %zmm10, %zmm15 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm16 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm26, %zmm13, %zmm16 -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm28 = [3,11,3,11,3,11,3,11] -; AVX512BW-ONLY-NEXT: # zmm28 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm29, %zmm28, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = [7,15,7,15,7,15,7,15] -; AVX512BW-ONLY-NEXT: # zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm29, %zmm0, %zmm8 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm29 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm27, %zmm28, %zmm29 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm27, %zmm0, %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm6 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm26, %zmm28, %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm26, %zmm0, %zmm5 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm18, %zmm26 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm21, %zmm11, %zmm26 -; AVX512BW-ONLY-NEXT: vpermi2q %zmm25, %zmm12, %zmm10 -; AVX512BW-ONLY-NEXT: vpermi2q %zmm25, %zmm12, %zmm13 -; AVX512BW-ONLY-NEXT: vpermi2q %zmm25, %zmm12, %zmm28 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm25, %zmm0, %zmm12 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm27 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm9 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm19, %zmm5 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm19, %zmm11, %zmm9 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm25 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm1, %zmm11, %zmm25 -; AVX512BW-ONLY-NEXT: vpermi2q %zmm22, %zmm7, %zmm11 -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm3 = [2,10,2,10,2,10,2,10] -; AVX512BW-ONLY-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm23 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm3, %zmm23 -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm6 = [6,14,6,14,6,14,6,14] -; AVX512BW-ONLY-NEXT: # zmm6 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm24 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm6, %zmm24 -; AVX512BW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm2 = [0,8,1,9,0,8,1,9] -; AVX512BW-ONLY-NEXT: # zmm2 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm30 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm2, %zmm30 -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} ymm19 = [7,15,7,15] -; AVX512BW-ONLY-NEXT: # ymm19 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm19, %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm22 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm1, %zmm3, %zmm22 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm1, %zmm6, %zmm4 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm8 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm1, %zmm2, %zmm8 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm1, %zmm19, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, (%rsp) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm27, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm5, %zmm3, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm27, %zmm1 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm5, %zmm6, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm27, %zmm7 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm5, %zmm2, %zmm7 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm5, %zmm19, %zmm27 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm27, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermi2q %zmm21, %zmm18, %zmm3 -; AVX512BW-ONLY-NEXT: vpermi2q %zmm21, %zmm18, %zmm6 -; AVX512BW-ONLY-NEXT: vpermi2q %zmm21, %zmm18, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm21, %zmm19, %zmm18 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm18, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: movb $12, %al -; AVX512BW-ONLY-NEXT: kmovd %eax, %k1 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm26 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm9 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm25 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm20, %zmm11 {%k1} -; AVX512BW-ONLY-NEXT: movb $48, %al -; AVX512BW-ONLY-NEXT: kmovd %eax, %k2 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm5 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm24, %zmm17 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm22, %zmm31 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm14 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm15 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqa64 (%r8), %zmm23 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm1, %zmm16 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%r8), %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm10 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm0 = <0,1,9,u,4,5,6,7> -; AVX512BW-ONLY-NEXT: vpermt2q %zmm23, %zmm0, %zmm5 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm1, %zmm0, %zmm31 -; AVX512BW-ONLY-NEXT: vmovdqa64 128(%r8), %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm3, %zmm0, %zmm15 -; AVX512BW-ONLY-NEXT: vmovdqa64 192(%r8), %zmm22 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm0, %zmm10 -; AVX512BW-ONLY-NEXT: vmovdqa64 (%r9), %zmm20 -; AVX512BW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm0 = [0,1,2,9,4,5,6,7] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm20, %zmm0, %zmm5 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%r9), %zmm21 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm21, %zmm0, %zmm31 -; AVX512BW-ONLY-NEXT: vmovdqa64 128(%r9), %zmm19 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm19, %zmm0, %zmm15 -; AVX512BW-ONLY-NEXT: vmovdqa64 192(%r9), %zmm18 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm18, %zmm0, %zmm10 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm13 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm0 = <0,1,13,u,4,5,6,7> -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm17, %zmm27 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm23, %zmm0, %zmm27 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm1, %zmm0, %zmm14 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm3, %zmm0, %zmm16 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm0, %zmm13 -; AVX512BW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm0 = [0,1,2,13,4,5,6,7] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm20, %zmm0, %zmm27 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm21, %zmm0, %zmm14 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm19, %zmm0, %zmm16 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm18, %zmm0, %zmm13 -; AVX512BW-ONLY-NEXT: vmovdqa (%rdx), %xmm0 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],mem[0] -; AVX512BW-ONLY-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm0, %zmm30 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa 64(%rdx), %xmm0 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],mem[0] -; AVX512BW-ONLY-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm0, %zmm8 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa 128(%rdx), %xmm0 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],mem[0] -; AVX512BW-ONLY-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm0, %zmm7 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa 192(%rdx), %xmm0 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],mem[0] -; AVX512BW-ONLY-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm0, %zmm2 {%k1} -; AVX512BW-ONLY-NEXT: vinserti32x4 $2, (%r8), %zmm30, %zmm24 -; AVX512BW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm0 = [0,1,2,3,4,8,6,7] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm20, %zmm0, %zmm24 -; AVX512BW-ONLY-NEXT: vinserti32x4 $2, 64(%r8), %zmm8, %zmm6 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm21, %zmm0, %zmm6 -; AVX512BW-ONLY-NEXT: vinserti32x4 $2, 128(%r8), %zmm7, %zmm5 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm19, %zmm0, %zmm5 -; AVX512BW-ONLY-NEXT: vinserti32x4 $2, 192(%r8), %zmm2, %zmm4 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm18, %zmm0, %zmm4 -; AVX512BW-ONLY-NEXT: vmovdqa (%rdi), %ymm0 -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm2, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm2, %zmm2 # 64-byte Folded Reload -; AVX512BW-ONLY-NEXT: # zmm2 = zmm2[0,1,2,3],mem[4,5,6,7] -; AVX512BW-ONLY-NEXT: movb $16, %al -; AVX512BW-ONLY-NEXT: kmovd %eax, %k1 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm11 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm7 = <10,u,2,3,4,5,11,u> -; AVX512BW-ONLY-NEXT: vpermt2q %zmm23, %zmm7, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm17 = <14,u,2,3,4,5,15,u> -; AVX512BW-ONLY-NEXT: vpermt2q %zmm23, %zmm17, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%rdi), %ymm23 -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm23 = ymm23[1],mem[1],ymm23[3],mem[3] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm23, %zmm29, %zmm23 -; AVX512BW-ONLY-NEXT: vmovdqu64 (%rsp), %zmm8 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm8, %zmm29 # 64-byte Folded Reload -; AVX512BW-ONLY-NEXT: # zmm29 = zmm8[0,1,2,3],mem[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm1, %zmm25 {%k1} -; AVX512BW-ONLY-NEXT: vpermt2q %zmm1, %zmm7, %zmm23 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm1, %zmm17, %zmm29 -; AVX512BW-ONLY-NEXT: vmovdqa 128(%rdi), %ymm1 -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm1[1],mem[1],ymm1[3],mem[3] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm8 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm8, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm8 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm8, %zmm30 # 64-byte Folded Reload -; AVX512BW-ONLY-NEXT: # zmm30 = zmm8[0,1,2,3],mem[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm9 {%k1} -; AVX512BW-ONLY-NEXT: vpermt2q %zmm3, %zmm7, %zmm1 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm3, %zmm17, %zmm30 -; AVX512BW-ONLY-NEXT: vmovdqa 192(%rdi), %ymm3 -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm3 = ymm3[1],mem[1],ymm3[3],mem[3] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm3, %zmm28, %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm7, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm22, %zmm26 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vshufi64x2 {{.*#+}} zmm7 = zmm7[0,1,2,3],zmm12[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm28 = [0,10,2,3,4,5,6,11] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm20, %zmm28, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm17, %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm17 = [0,1,2,3,4,12,6,7] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm20, %zmm17, %zmm11 -; AVX512BW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm22 = [0,14,2,3,4,5,6,15] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm20, %zmm22, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm21, %zmm28, %zmm23 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm21, %zmm17, %zmm25 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm21, %zmm22, %zmm29 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm19, %zmm28, %zmm1 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm19, %zmm17, %zmm9 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm19, %zmm22, %zmm30 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm18, %zmm28, %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm18, %zmm17, %zmm26 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm18, %zmm22, %zmm7 -; AVX512BW-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, 1472(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm13, 1408(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm26, 1344(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm3, 1280(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, 1216(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm30, 1088(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm16, 1024(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm9, 960(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm1, 896(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm15, 832(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm29, 704(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm14, 640(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm25, 576(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm23, 512(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm31, 448(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, 320(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm27, 256(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm11, 192(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, 128(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 64(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, 1152(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, 768(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm6, 384(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm24, (%rax) -; AVX512BW-ONLY-NEXT: addq $712, %rsp # imm = 0x2C8 -; AVX512BW-ONLY-NEXT: vzeroupper -; AVX512BW-ONLY-NEXT: retq +; AVX512F-LABEL: store_i64_stride6_vf32: +; AVX512F: # %bb.0: +; AVX512F-NEXT: subq $712, %rsp # imm = 0x2C8 +; AVX512F-NEXT: vmovdqa64 (%rdi), %zmm7 +; AVX512F-NEXT: vmovdqa64 64(%rdi), %zmm4 +; AVX512F-NEXT: vmovdqa64 128(%rdi), %zmm2 +; AVX512F-NEXT: vmovdqa64 192(%rdi), %zmm18 +; AVX512F-NEXT: vmovdqa64 (%rsi), %zmm22 +; AVX512F-NEXT: vmovdqa64 64(%rsi), %zmm1 +; AVX512F-NEXT: vmovdqa64 128(%rsi), %zmm19 +; AVX512F-NEXT: vmovdqa64 192(%rsi), %zmm21 +; AVX512F-NEXT: vmovdqa64 (%rdx), %zmm8 +; AVX512F-NEXT: vmovdqa64 64(%rdx), %zmm6 +; AVX512F-NEXT: vmovdqa64 128(%rdx), %zmm5 +; AVX512F-NEXT: vmovdqa64 192(%rdx), %zmm12 +; AVX512F-NEXT: vmovdqa64 (%rcx), %zmm29 +; AVX512F-NEXT: vmovdqa64 64(%rcx), %zmm27 +; AVX512F-NEXT: vmovdqa64 128(%rcx), %zmm26 +; AVX512F-NEXT: vmovdqa64 192(%rcx), %zmm25 +; AVX512F-NEXT: vbroadcasti64x4 {{.*#+}} zmm11 = [4,12,5,13,4,12,5,13] +; AVX512F-NEXT: # zmm11 = mem[0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} ymm20 = [4,12,4,12] +; AVX512F-NEXT: # ymm20 = mem[0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm12, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm25, %zmm20, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm5, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm26, %zmm20, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm6, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm27, %zmm20, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermi2q %zmm29, %zmm8, %zmm20 +; AVX512F-NEXT: vbroadcasti64x4 {{.*#+}} zmm10 = [1,9,2,10,1,9,2,10] +; AVX512F-NEXT: # zmm10 = mem[0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm8, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm29, %zmm10, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vbroadcasti64x4 {{.*#+}} zmm13 = [5,13,6,14,5,13,6,14] +; AVX512F-NEXT: # zmm13 = mem[0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm8, %zmm17 +; AVX512F-NEXT: vpermt2q %zmm29, %zmm13, %zmm17 +; AVX512F-NEXT: vmovdqa64 %zmm6, %zmm31 +; AVX512F-NEXT: vpermt2q %zmm27, %zmm10, %zmm31 +; AVX512F-NEXT: vmovdqa64 %zmm6, %zmm14 +; AVX512F-NEXT: vpermt2q %zmm27, %zmm13, %zmm14 +; AVX512F-NEXT: vmovdqa64 %zmm5, %zmm15 +; AVX512F-NEXT: vpermt2q %zmm26, %zmm10, %zmm15 +; AVX512F-NEXT: vmovdqa64 %zmm5, %zmm16 +; AVX512F-NEXT: vpermt2q %zmm26, %zmm13, %zmm16 +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm28 = [3,11,3,11,3,11,3,11] +; AVX512F-NEXT: # zmm28 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm8, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm29, %zmm28, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = [7,15,7,15,7,15,7,15] +; AVX512F-NEXT: # zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vpermt2q %zmm29, %zmm0, %zmm8 +; AVX512F-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm6, %zmm29 +; AVX512F-NEXT: vpermt2q %zmm27, %zmm28, %zmm29 +; AVX512F-NEXT: vpermt2q %zmm27, %zmm0, %zmm6 +; AVX512F-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm5, %zmm6 +; AVX512F-NEXT: vpermt2q %zmm26, %zmm28, %zmm6 +; AVX512F-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm26, %zmm0, %zmm5 +; AVX512F-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm18, %zmm26 +; AVX512F-NEXT: vpermt2q %zmm21, %zmm11, %zmm26 +; AVX512F-NEXT: vpermi2q %zmm25, %zmm12, %zmm10 +; AVX512F-NEXT: vpermi2q %zmm25, %zmm12, %zmm13 +; AVX512F-NEXT: vpermi2q %zmm25, %zmm12, %zmm28 +; AVX512F-NEXT: vpermt2q %zmm25, %zmm0, %zmm12 +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm27 +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm9 +; AVX512F-NEXT: vmovdqa64 %zmm19, %zmm5 +; AVX512F-NEXT: vpermt2q %zmm19, %zmm11, %zmm9 +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm0 +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm25 +; AVX512F-NEXT: vpermt2q %zmm1, %zmm11, %zmm25 +; AVX512F-NEXT: vpermi2q %zmm22, %zmm7, %zmm11 +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm3 = [2,10,2,10,2,10,2,10] +; AVX512F-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm7, %zmm23 +; AVX512F-NEXT: vpermt2q %zmm22, %zmm3, %zmm23 +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm6 = [6,14,6,14,6,14,6,14] +; AVX512F-NEXT: # zmm6 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm7, %zmm24 +; AVX512F-NEXT: vpermt2q %zmm22, %zmm6, %zmm24 +; AVX512F-NEXT: vbroadcasti64x4 {{.*#+}} zmm2 = [0,8,1,9,0,8,1,9] +; AVX512F-NEXT: # zmm2 = mem[0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm7, %zmm30 +; AVX512F-NEXT: vpermt2q %zmm22, %zmm2, %zmm30 +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} ymm19 = [7,15,7,15] +; AVX512F-NEXT: # ymm19 = mem[0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vpermt2q %zmm22, %zmm19, %zmm7 +; AVX512F-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm22 +; AVX512F-NEXT: vpermt2q %zmm1, %zmm3, %zmm22 +; AVX512F-NEXT: vpermt2q %zmm1, %zmm6, %zmm4 +; AVX512F-NEXT: vmovdqa64 %zmm0, %zmm8 +; AVX512F-NEXT: vpermt2q %zmm1, %zmm2, %zmm8 +; AVX512F-NEXT: vpermt2q %zmm1, %zmm19, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, (%rsp) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm27, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm5, %zmm3, %zmm0 +; AVX512F-NEXT: vmovdqa64 %zmm27, %zmm1 +; AVX512F-NEXT: vpermt2q %zmm5, %zmm6, %zmm1 +; AVX512F-NEXT: vmovdqa64 %zmm27, %zmm7 +; AVX512F-NEXT: vpermt2q %zmm5, %zmm2, %zmm7 +; AVX512F-NEXT: vpermt2q %zmm5, %zmm19, %zmm27 +; AVX512F-NEXT: vmovdqu64 %zmm27, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermi2q %zmm21, %zmm18, %zmm3 +; AVX512F-NEXT: vpermi2q %zmm21, %zmm18, %zmm6 +; AVX512F-NEXT: vpermi2q %zmm21, %zmm18, %zmm2 +; AVX512F-NEXT: vpermt2q %zmm21, %zmm19, %zmm18 +; AVX512F-NEXT: vmovdqu64 %zmm18, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: movb $12, %al +; AVX512F-NEXT: kmovw %eax, %k1 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm5, %zmm26 {%k1} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm5, %zmm9 {%k1} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm5, %zmm25 {%k1} +; AVX512F-NEXT: vmovdqa64 %zmm20, %zmm11 {%k1} +; AVX512F-NEXT: movb $48, %al +; AVX512F-NEXT: kmovw %eax, %k2 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm23, %zmm5 {%k2} +; AVX512F-NEXT: vmovdqa64 %zmm24, %zmm17 {%k2} +; AVX512F-NEXT: vmovdqa64 %zmm22, %zmm31 {%k2} +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm14 {%k2} +; AVX512F-NEXT: vmovdqa64 %zmm0, %zmm15 {%k2} +; AVX512F-NEXT: vmovdqa64 (%r8), %zmm23 +; AVX512F-NEXT: vmovdqa64 %zmm1, %zmm16 {%k2} +; AVX512F-NEXT: vmovdqa64 64(%r8), %zmm1 +; AVX512F-NEXT: vmovdqa64 %zmm3, %zmm10 {%k2} +; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm0 = <0,1,9,u,4,5,6,7> +; AVX512F-NEXT: vpermt2q %zmm23, %zmm0, %zmm5 +; AVX512F-NEXT: vpermt2q %zmm1, %zmm0, %zmm31 +; AVX512F-NEXT: vmovdqa64 128(%r8), %zmm3 +; AVX512F-NEXT: vpermt2q %zmm3, %zmm0, %zmm15 +; AVX512F-NEXT: vmovdqa64 192(%r8), %zmm22 +; AVX512F-NEXT: vpermt2q %zmm22, %zmm0, %zmm10 +; AVX512F-NEXT: vmovdqa64 (%r9), %zmm20 +; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm0 = [0,1,2,9,4,5,6,7] +; AVX512F-NEXT: vpermt2q %zmm20, %zmm0, %zmm5 +; AVX512F-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 64(%r9), %zmm21 +; AVX512F-NEXT: vpermt2q %zmm21, %zmm0, %zmm31 +; AVX512F-NEXT: vmovdqa64 128(%r9), %zmm19 +; AVX512F-NEXT: vpermt2q %zmm19, %zmm0, %zmm15 +; AVX512F-NEXT: vmovdqa64 192(%r9), %zmm18 +; AVX512F-NEXT: vpermt2q %zmm18, %zmm0, %zmm10 +; AVX512F-NEXT: vmovdqa64 %zmm6, %zmm13 {%k2} +; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm0 = <0,1,13,u,4,5,6,7> +; AVX512F-NEXT: vmovdqa64 %zmm17, %zmm27 +; AVX512F-NEXT: vpermt2q %zmm23, %zmm0, %zmm27 +; AVX512F-NEXT: vpermt2q %zmm1, %zmm0, %zmm14 +; AVX512F-NEXT: vpermt2q %zmm3, %zmm0, %zmm16 +; AVX512F-NEXT: vpermt2q %zmm22, %zmm0, %zmm13 +; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm0 = [0,1,2,13,4,5,6,7] +; AVX512F-NEXT: vpermt2q %zmm20, %zmm0, %zmm27 +; AVX512F-NEXT: vpermt2q %zmm21, %zmm0, %zmm14 +; AVX512F-NEXT: vpermt2q %zmm19, %zmm0, %zmm16 +; AVX512F-NEXT: vpermt2q %zmm18, %zmm0, %zmm13 +; AVX512F-NEXT: vmovdqa (%rdx), %xmm0 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],mem[0] +; AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 +; AVX512F-NEXT: vinserti64x4 $0, %ymm0, %zmm0, %zmm30 {%k1} +; AVX512F-NEXT: vmovdqa 64(%rdx), %xmm0 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],mem[0] +; AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 +; AVX512F-NEXT: vinserti64x4 $0, %ymm0, %zmm0, %zmm8 {%k1} +; AVX512F-NEXT: vmovdqa 128(%rdx), %xmm0 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],mem[0] +; AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 +; AVX512F-NEXT: vinserti64x4 $0, %ymm0, %zmm0, %zmm7 {%k1} +; AVX512F-NEXT: vmovdqa 192(%rdx), %xmm0 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],mem[0] +; AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 +; AVX512F-NEXT: vinserti64x4 $0, %ymm0, %zmm0, %zmm2 {%k1} +; AVX512F-NEXT: vinserti32x4 $2, (%r8), %zmm30, %zmm24 +; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm0 = [0,1,2,3,4,8,6,7] +; AVX512F-NEXT: vpermt2q %zmm20, %zmm0, %zmm24 +; AVX512F-NEXT: vinserti32x4 $2, 64(%r8), %zmm8, %zmm6 +; AVX512F-NEXT: vpermt2q %zmm21, %zmm0, %zmm6 +; AVX512F-NEXT: vinserti32x4 $2, 128(%r8), %zmm7, %zmm5 +; AVX512F-NEXT: vpermt2q %zmm19, %zmm0, %zmm5 +; AVX512F-NEXT: vinserti32x4 $2, 192(%r8), %zmm2, %zmm4 +; AVX512F-NEXT: vpermt2q %zmm18, %zmm0, %zmm4 +; AVX512F-NEXT: vmovdqa (%rdi), %ymm0 +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512F-NEXT: vinserti64x4 $0, %ymm0, %zmm2, %zmm0 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512F-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm2, %zmm2 # 64-byte Folded Reload +; AVX512F-NEXT: # zmm2 = zmm2[0,1,2,3],mem[4,5,6,7] +; AVX512F-NEXT: movb $16, %al +; AVX512F-NEXT: kmovw %eax, %k1 +; AVX512F-NEXT: vmovdqa64 %zmm23, %zmm11 {%k1} +; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm7 = <10,u,2,3,4,5,11,u> +; AVX512F-NEXT: vpermt2q %zmm23, %zmm7, %zmm0 +; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm17 = <14,u,2,3,4,5,15,u> +; AVX512F-NEXT: vpermt2q %zmm23, %zmm17, %zmm2 +; AVX512F-NEXT: vmovdqa64 64(%rdi), %ymm23 +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm23 = ymm23[1],mem[1],ymm23[3],mem[3] +; AVX512F-NEXT: vinserti64x4 $0, %ymm23, %zmm29, %zmm23 +; AVX512F-NEXT: vmovdqu64 (%rsp), %zmm8 # 64-byte Reload +; AVX512F-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm8, %zmm29 # 64-byte Folded Reload +; AVX512F-NEXT: # zmm29 = zmm8[0,1,2,3],mem[4,5,6,7] +; AVX512F-NEXT: vmovdqa64 %zmm1, %zmm25 {%k1} +; AVX512F-NEXT: vpermt2q %zmm1, %zmm7, %zmm23 +; AVX512F-NEXT: vpermt2q %zmm1, %zmm17, %zmm29 +; AVX512F-NEXT: vmovdqa 128(%rdi), %ymm1 +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm1[1],mem[1],ymm1[3],mem[3] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm8 # 64-byte Reload +; AVX512F-NEXT: vinserti64x4 $0, %ymm1, %zmm8, %zmm1 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm8 # 64-byte Reload +; AVX512F-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm8, %zmm30 # 64-byte Folded Reload +; AVX512F-NEXT: # zmm30 = zmm8[0,1,2,3],mem[4,5,6,7] +; AVX512F-NEXT: vmovdqa64 %zmm3, %zmm9 {%k1} +; AVX512F-NEXT: vpermt2q %zmm3, %zmm7, %zmm1 +; AVX512F-NEXT: vpermt2q %zmm3, %zmm17, %zmm30 +; AVX512F-NEXT: vmovdqa 192(%rdi), %ymm3 +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm3 = ymm3[1],mem[1],ymm3[3],mem[3] +; AVX512F-NEXT: vinserti64x4 $0, %ymm3, %zmm28, %zmm3 +; AVX512F-NEXT: vpermt2q %zmm22, %zmm7, %zmm3 +; AVX512F-NEXT: vmovdqa64 %zmm22, %zmm26 {%k1} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 # 64-byte Reload +; AVX512F-NEXT: vshufi64x2 {{.*#+}} zmm7 = zmm7[0,1,2,3],zmm12[4,5,6,7] +; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm28 = [0,10,2,3,4,5,6,11] +; AVX512F-NEXT: vpermt2q %zmm20, %zmm28, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm22, %zmm17, %zmm7 +; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm17 = [0,1,2,3,4,12,6,7] +; AVX512F-NEXT: vpermt2q %zmm20, %zmm17, %zmm11 +; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm22 = [0,14,2,3,4,5,6,15] +; AVX512F-NEXT: vpermt2q %zmm20, %zmm22, %zmm2 +; AVX512F-NEXT: vpermt2q %zmm21, %zmm28, %zmm23 +; AVX512F-NEXT: vpermt2q %zmm21, %zmm17, %zmm25 +; AVX512F-NEXT: vpermt2q %zmm21, %zmm22, %zmm29 +; AVX512F-NEXT: vpermt2q %zmm19, %zmm28, %zmm1 +; AVX512F-NEXT: vpermt2q %zmm19, %zmm17, %zmm9 +; AVX512F-NEXT: vpermt2q %zmm19, %zmm22, %zmm30 +; AVX512F-NEXT: vpermt2q %zmm18, %zmm28, %zmm3 +; AVX512F-NEXT: vpermt2q %zmm18, %zmm17, %zmm26 +; AVX512F-NEXT: vpermt2q %zmm18, %zmm22, %zmm7 +; AVX512F-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512F-NEXT: vmovdqa64 %zmm7, 1472(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm13, 1408(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm26, 1344(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm3, 1280(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm10, 1216(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm30, 1088(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm16, 1024(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm9, 960(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm1, 896(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm15, 832(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm29, 704(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm14, 640(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm25, 576(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm23, 512(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm31, 448(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm2, 320(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm27, 256(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm11, 192(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm0, 128(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 64(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm4, 1152(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm5, 768(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm6, 384(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm24, (%rax) +; AVX512F-NEXT: addq $712, %rsp # imm = 0x2C8 +; AVX512F-NEXT: vzeroupper +; AVX512F-NEXT: retq ; -; AVX512DQBW-ONLY-LABEL: store_i64_stride6_vf32: -; AVX512DQBW-ONLY: # %bb.0: -; AVX512DQBW-ONLY-NEXT: subq $712, %rsp # imm = 0x2C8 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 (%rdi), %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%rdi), %zmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 128(%rdi), %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 192(%rdi), %zmm18 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 (%rsi), %zmm22 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%rsi), %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 128(%rsi), %zmm19 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 192(%rsi), %zmm21 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 (%rdx), %zmm8 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%rdx), %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 128(%rdx), %zmm5 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 192(%rdx), %zmm12 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 (%rcx), %zmm29 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%rcx), %zmm27 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 128(%rcx), %zmm26 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 192(%rcx), %zmm25 -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm11 = [4,12,5,13,4,12,5,13] -; AVX512DQBW-ONLY-NEXT: # zmm11 = mem[0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x2 {{.*#+}} ymm20 = [4,12,4,12] -; AVX512DQBW-ONLY-NEXT: # ymm20 = mem[0,1,0,1] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm25, %zmm20, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm26, %zmm20, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm27, %zmm20, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm29, %zmm8, %zmm20 -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm10 = [1,9,2,10,1,9,2,10] -; AVX512DQBW-ONLY-NEXT: # zmm10 = mem[0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm29, %zmm10, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm13 = [5,13,6,14,5,13,6,14] -; AVX512DQBW-ONLY-NEXT: # zmm13 = mem[0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm8, %zmm17 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm29, %zmm13, %zmm17 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm31 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm27, %zmm10, %zmm31 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm14 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm27, %zmm13, %zmm14 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm15 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm26, %zmm10, %zmm15 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm16 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm26, %zmm13, %zmm16 -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm28 = [3,11,3,11,3,11,3,11] -; AVX512DQBW-ONLY-NEXT: # zmm28 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm29, %zmm28, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = [7,15,7,15,7,15,7,15] -; AVX512DQBW-ONLY-NEXT: # zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm29, %zmm0, %zmm8 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm29 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm27, %zmm28, %zmm29 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm27, %zmm0, %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm26, %zmm28, %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm26, %zmm0, %zmm5 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm18, %zmm26 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm21, %zmm11, %zmm26 -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm25, %zmm12, %zmm10 -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm25, %zmm12, %zmm13 -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm25, %zmm12, %zmm28 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm25, %zmm0, %zmm12 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm27 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm9 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm19, %zmm5 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm19, %zmm11, %zmm9 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm25 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm1, %zmm11, %zmm25 -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm22, %zmm7, %zmm11 -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm3 = [2,10,2,10,2,10,2,10] -; AVX512DQBW-ONLY-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm23 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm3, %zmm23 -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm6 = [6,14,6,14,6,14,6,14] -; AVX512DQBW-ONLY-NEXT: # zmm6 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm24 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm6, %zmm24 -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm2 = [0,8,1,9,0,8,1,9] -; AVX512DQBW-ONLY-NEXT: # zmm2 = mem[0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm30 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm2, %zmm30 -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x2 {{.*#+}} ymm19 = [7,15,7,15] -; AVX512DQBW-ONLY-NEXT: # ymm19 = mem[0,1,0,1] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm19, %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm22 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm1, %zmm3, %zmm22 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm1, %zmm6, %zmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm1, %zmm2, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm1, %zmm19, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, (%rsp) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm27, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm5, %zmm3, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm27, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm5, %zmm6, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm27, %zmm7 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm5, %zmm2, %zmm7 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm5, %zmm19, %zmm27 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm27, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm21, %zmm18, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm21, %zmm18, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm21, %zmm18, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm21, %zmm19, %zmm18 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm18, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: movb $12, %al -; AVX512DQBW-ONLY-NEXT: kmovd %eax, %k1 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm26 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm9 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm25 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm20, %zmm11 {%k1} -; AVX512DQBW-ONLY-NEXT: movb $48, %al -; AVX512DQBW-ONLY-NEXT: kmovd %eax, %k2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm5 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm24, %zmm17 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm22, %zmm31 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm14 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm15 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 (%r8), %zmm23 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm1, %zmm16 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%r8), %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm10 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm0 = <0,1,9,u,4,5,6,7> -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm23, %zmm0, %zmm5 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm1, %zmm0, %zmm31 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 128(%r8), %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm3, %zmm0, %zmm15 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 192(%r8), %zmm22 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm0, %zmm10 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 (%r9), %zmm20 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm0 = [0,1,2,9,4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm20, %zmm0, %zmm5 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%r9), %zmm21 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm21, %zmm0, %zmm31 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 128(%r9), %zmm19 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm19, %zmm0, %zmm15 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 192(%r9), %zmm18 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm18, %zmm0, %zmm10 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm13 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm0 = <0,1,13,u,4,5,6,7> -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm17, %zmm27 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm23, %zmm0, %zmm27 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm1, %zmm0, %zmm14 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm3, %zmm0, %zmm16 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm0, %zmm13 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm0 = [0,1,2,13,4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm20, %zmm0, %zmm27 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm21, %zmm0, %zmm14 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm19, %zmm0, %zmm16 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm18, %zmm0, %zmm13 -; AVX512DQBW-ONLY-NEXT: vmovdqa (%rdx), %xmm0 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],mem[0] -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm0, %zmm30 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa 64(%rdx), %xmm0 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],mem[0] -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm0, %zmm8 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa 128(%rdx), %xmm0 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],mem[0] -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm0, %zmm7 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa 192(%rdx), %xmm0 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],mem[0] -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm0, %zmm2 {%k1} -; AVX512DQBW-ONLY-NEXT: vinserti32x4 $2, (%r8), %zmm30, %zmm24 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm0 = [0,1,2,3,4,8,6,7] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm20, %zmm0, %zmm24 -; AVX512DQBW-ONLY-NEXT: vinserti32x4 $2, 64(%r8), %zmm8, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm21, %zmm0, %zmm6 -; AVX512DQBW-ONLY-NEXT: vinserti32x4 $2, 128(%r8), %zmm7, %zmm5 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm19, %zmm0, %zmm5 -; AVX512DQBW-ONLY-NEXT: vinserti32x4 $2, 192(%r8), %zmm2, %zmm4 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm18, %zmm0, %zmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqa (%rdi), %ymm0 -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm2, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm2, %zmm2 # 64-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # zmm2 = zmm2[0,1,2,3],mem[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: movb $16, %al -; AVX512DQBW-ONLY-NEXT: kmovd %eax, %k1 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm11 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm7 = <10,u,2,3,4,5,11,u> -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm23, %zmm7, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm17 = <14,u,2,3,4,5,15,u> -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm23, %zmm17, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%rdi), %ymm23 -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm23 = ymm23[1],mem[1],ymm23[3],mem[3] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm23, %zmm29, %zmm23 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 (%rsp), %zmm8 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm8, %zmm29 # 64-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # zmm29 = zmm8[0,1,2,3],mem[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm1, %zmm25 {%k1} -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm1, %zmm7, %zmm23 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm1, %zmm17, %zmm29 -; AVX512DQBW-ONLY-NEXT: vmovdqa 128(%rdi), %ymm1 -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm1[1],mem[1],ymm1[3],mem[3] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm8 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm8, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm8 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm8, %zmm30 # 64-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # zmm30 = zmm8[0,1,2,3],mem[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm9 {%k1} -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm3, %zmm7, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm3, %zmm17, %zmm30 -; AVX512DQBW-ONLY-NEXT: vmovdqa 192(%rdi), %ymm3 -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm3 = ymm3[1],mem[1],ymm3[3],mem[3] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm3, %zmm28, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm7, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm22, %zmm26 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vshufi64x2 {{.*#+}} zmm7 = zmm7[0,1,2,3],zmm12[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm28 = [0,10,2,3,4,5,6,11] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm20, %zmm28, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm17, %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm17 = [0,1,2,3,4,12,6,7] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm20, %zmm17, %zmm11 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm22 = [0,14,2,3,4,5,6,15] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm20, %zmm22, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm21, %zmm28, %zmm23 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm21, %zmm17, %zmm25 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm21, %zmm22, %zmm29 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm19, %zmm28, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm19, %zmm17, %zmm9 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm19, %zmm22, %zmm30 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm18, %zmm28, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm18, %zmm17, %zmm26 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm18, %zmm22, %zmm7 -; AVX512DQBW-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, 1472(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm13, 1408(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm26, 1344(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm3, 1280(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, 1216(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm30, 1088(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm16, 1024(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm9, 960(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm1, 896(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm15, 832(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm29, 704(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm14, 640(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm25, 576(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm23, 512(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm31, 448(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, 320(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm27, 256(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm11, 192(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, 128(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 64(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, 1152(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, 768(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm6, 384(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm24, (%rax) -; AVX512DQBW-ONLY-NEXT: addq $712, %rsp # imm = 0x2C8 -; AVX512DQBW-ONLY-NEXT: vzeroupper -; AVX512DQBW-ONLY-NEXT: retq +; AVX512BW-LABEL: store_i64_stride6_vf32: +; AVX512BW: # %bb.0: +; AVX512BW-NEXT: subq $712, %rsp # imm = 0x2C8 +; AVX512BW-NEXT: vmovdqa64 (%rdi), %zmm7 +; AVX512BW-NEXT: vmovdqa64 64(%rdi), %zmm4 +; AVX512BW-NEXT: vmovdqa64 128(%rdi), %zmm2 +; AVX512BW-NEXT: vmovdqa64 192(%rdi), %zmm18 +; AVX512BW-NEXT: vmovdqa64 (%rsi), %zmm22 +; AVX512BW-NEXT: vmovdqa64 64(%rsi), %zmm1 +; AVX512BW-NEXT: vmovdqa64 128(%rsi), %zmm19 +; AVX512BW-NEXT: vmovdqa64 192(%rsi), %zmm21 +; AVX512BW-NEXT: vmovdqa64 (%rdx), %zmm8 +; AVX512BW-NEXT: vmovdqa64 64(%rdx), %zmm6 +; AVX512BW-NEXT: vmovdqa64 128(%rdx), %zmm5 +; AVX512BW-NEXT: vmovdqa64 192(%rdx), %zmm12 +; AVX512BW-NEXT: vmovdqa64 (%rcx), %zmm29 +; AVX512BW-NEXT: vmovdqa64 64(%rcx), %zmm27 +; AVX512BW-NEXT: vmovdqa64 128(%rcx), %zmm26 +; AVX512BW-NEXT: vmovdqa64 192(%rcx), %zmm25 +; AVX512BW-NEXT: vbroadcasti64x4 {{.*#+}} zmm11 = [4,12,5,13,4,12,5,13] +; AVX512BW-NEXT: # zmm11 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} ymm20 = [4,12,4,12] +; AVX512BW-NEXT: # ymm20 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm12, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm25, %zmm20, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm26, %zmm20, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm6, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm27, %zmm20, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermi2q %zmm29, %zmm8, %zmm20 +; AVX512BW-NEXT: vbroadcasti64x4 {{.*#+}} zmm10 = [1,9,2,10,1,9,2,10] +; AVX512BW-NEXT: # zmm10 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm8, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm29, %zmm10, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti64x4 {{.*#+}} zmm13 = [5,13,6,14,5,13,6,14] +; AVX512BW-NEXT: # zmm13 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm8, %zmm17 +; AVX512BW-NEXT: vpermt2q %zmm29, %zmm13, %zmm17 +; AVX512BW-NEXT: vmovdqa64 %zmm6, %zmm31 +; AVX512BW-NEXT: vpermt2q %zmm27, %zmm10, %zmm31 +; AVX512BW-NEXT: vmovdqa64 %zmm6, %zmm14 +; AVX512BW-NEXT: vpermt2q %zmm27, %zmm13, %zmm14 +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm15 +; AVX512BW-NEXT: vpermt2q %zmm26, %zmm10, %zmm15 +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm16 +; AVX512BW-NEXT: vpermt2q %zmm26, %zmm13, %zmm16 +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm28 = [3,11,3,11,3,11,3,11] +; AVX512BW-NEXT: # zmm28 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm8, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm29, %zmm28, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = [7,15,7,15,7,15,7,15] +; AVX512BW-NEXT: # zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vpermt2q %zmm29, %zmm0, %zmm8 +; AVX512BW-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm6, %zmm29 +; AVX512BW-NEXT: vpermt2q %zmm27, %zmm28, %zmm29 +; AVX512BW-NEXT: vpermt2q %zmm27, %zmm0, %zmm6 +; AVX512BW-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm6 +; AVX512BW-NEXT: vpermt2q %zmm26, %zmm28, %zmm6 +; AVX512BW-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm26, %zmm0, %zmm5 +; AVX512BW-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm18, %zmm26 +; AVX512BW-NEXT: vpermt2q %zmm21, %zmm11, %zmm26 +; AVX512BW-NEXT: vpermi2q %zmm25, %zmm12, %zmm10 +; AVX512BW-NEXT: vpermi2q %zmm25, %zmm12, %zmm13 +; AVX512BW-NEXT: vpermi2q %zmm25, %zmm12, %zmm28 +; AVX512BW-NEXT: vpermt2q %zmm25, %zmm0, %zmm12 +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm27 +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm9 +; AVX512BW-NEXT: vmovdqa64 %zmm19, %zmm5 +; AVX512BW-NEXT: vpermt2q %zmm19, %zmm11, %zmm9 +; AVX512BW-NEXT: vmovdqa64 %zmm4, %zmm0 +; AVX512BW-NEXT: vmovdqa64 %zmm4, %zmm25 +; AVX512BW-NEXT: vpermt2q %zmm1, %zmm11, %zmm25 +; AVX512BW-NEXT: vpermi2q %zmm22, %zmm7, %zmm11 +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm3 = [2,10,2,10,2,10,2,10] +; AVX512BW-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm23 +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm3, %zmm23 +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm6 = [6,14,6,14,6,14,6,14] +; AVX512BW-NEXT: # zmm6 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm24 +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm6, %zmm24 +; AVX512BW-NEXT: vbroadcasti64x4 {{.*#+}} zmm2 = [0,8,1,9,0,8,1,9] +; AVX512BW-NEXT: # zmm2 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm30 +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm2, %zmm30 +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} ymm19 = [7,15,7,15] +; AVX512BW-NEXT: # ymm19 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm19, %zmm7 +; AVX512BW-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm4, %zmm22 +; AVX512BW-NEXT: vpermt2q %zmm1, %zmm3, %zmm22 +; AVX512BW-NEXT: vpermt2q %zmm1, %zmm6, %zmm4 +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm8 +; AVX512BW-NEXT: vpermt2q %zmm1, %zmm2, %zmm8 +; AVX512BW-NEXT: vpermt2q %zmm1, %zmm19, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, (%rsp) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm27, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm5, %zmm3, %zmm0 +; AVX512BW-NEXT: vmovdqa64 %zmm27, %zmm1 +; AVX512BW-NEXT: vpermt2q %zmm5, %zmm6, %zmm1 +; AVX512BW-NEXT: vmovdqa64 %zmm27, %zmm7 +; AVX512BW-NEXT: vpermt2q %zmm5, %zmm2, %zmm7 +; AVX512BW-NEXT: vpermt2q %zmm5, %zmm19, %zmm27 +; AVX512BW-NEXT: vmovdqu64 %zmm27, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermi2q %zmm21, %zmm18, %zmm3 +; AVX512BW-NEXT: vpermi2q %zmm21, %zmm18, %zmm6 +; AVX512BW-NEXT: vpermi2q %zmm21, %zmm18, %zmm2 +; AVX512BW-NEXT: vpermt2q %zmm21, %zmm19, %zmm18 +; AVX512BW-NEXT: vmovdqu64 %zmm18, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: movb $12, %al +; AVX512BW-NEXT: kmovd %eax, %k1 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm26 {%k1} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm9 {%k1} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm25 {%k1} +; AVX512BW-NEXT: vmovdqa64 %zmm20, %zmm11 {%k1} +; AVX512BW-NEXT: movb $48, %al +; AVX512BW-NEXT: kmovd %eax, %k2 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm23, %zmm5 {%k2} +; AVX512BW-NEXT: vmovdqa64 %zmm24, %zmm17 {%k2} +; AVX512BW-NEXT: vmovdqa64 %zmm22, %zmm31 {%k2} +; AVX512BW-NEXT: vmovdqa64 %zmm4, %zmm14 {%k2} +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm15 {%k2} +; AVX512BW-NEXT: vmovdqa64 (%r8), %zmm23 +; AVX512BW-NEXT: vmovdqa64 %zmm1, %zmm16 {%k2} +; AVX512BW-NEXT: vmovdqa64 64(%r8), %zmm1 +; AVX512BW-NEXT: vmovdqa64 %zmm3, %zmm10 {%k2} +; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm0 = <0,1,9,u,4,5,6,7> +; AVX512BW-NEXT: vpermt2q %zmm23, %zmm0, %zmm5 +; AVX512BW-NEXT: vpermt2q %zmm1, %zmm0, %zmm31 +; AVX512BW-NEXT: vmovdqa64 128(%r8), %zmm3 +; AVX512BW-NEXT: vpermt2q %zmm3, %zmm0, %zmm15 +; AVX512BW-NEXT: vmovdqa64 192(%r8), %zmm22 +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm0, %zmm10 +; AVX512BW-NEXT: vmovdqa64 (%r9), %zmm20 +; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm0 = [0,1,2,9,4,5,6,7] +; AVX512BW-NEXT: vpermt2q %zmm20, %zmm0, %zmm5 +; AVX512BW-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 64(%r9), %zmm21 +; AVX512BW-NEXT: vpermt2q %zmm21, %zmm0, %zmm31 +; AVX512BW-NEXT: vmovdqa64 128(%r9), %zmm19 +; AVX512BW-NEXT: vpermt2q %zmm19, %zmm0, %zmm15 +; AVX512BW-NEXT: vmovdqa64 192(%r9), %zmm18 +; AVX512BW-NEXT: vpermt2q %zmm18, %zmm0, %zmm10 +; AVX512BW-NEXT: vmovdqa64 %zmm6, %zmm13 {%k2} +; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm0 = <0,1,13,u,4,5,6,7> +; AVX512BW-NEXT: vmovdqa64 %zmm17, %zmm27 +; AVX512BW-NEXT: vpermt2q %zmm23, %zmm0, %zmm27 +; AVX512BW-NEXT: vpermt2q %zmm1, %zmm0, %zmm14 +; AVX512BW-NEXT: vpermt2q %zmm3, %zmm0, %zmm16 +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm0, %zmm13 +; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm0 = [0,1,2,13,4,5,6,7] +; AVX512BW-NEXT: vpermt2q %zmm20, %zmm0, %zmm27 +; AVX512BW-NEXT: vpermt2q %zmm21, %zmm0, %zmm14 +; AVX512BW-NEXT: vpermt2q %zmm19, %zmm0, %zmm16 +; AVX512BW-NEXT: vpermt2q %zmm18, %zmm0, %zmm13 +; AVX512BW-NEXT: vmovdqa (%rdx), %xmm0 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],mem[0] +; AVX512BW-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm0, %zmm30 {%k1} +; AVX512BW-NEXT: vmovdqa 64(%rdx), %xmm0 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],mem[0] +; AVX512BW-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm0, %zmm8 {%k1} +; AVX512BW-NEXT: vmovdqa 128(%rdx), %xmm0 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],mem[0] +; AVX512BW-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm0, %zmm7 {%k1} +; AVX512BW-NEXT: vmovdqa 192(%rdx), %xmm0 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],mem[0] +; AVX512BW-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm0, %zmm2 {%k1} +; AVX512BW-NEXT: vinserti32x4 $2, (%r8), %zmm30, %zmm24 +; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm0 = [0,1,2,3,4,8,6,7] +; AVX512BW-NEXT: vpermt2q %zmm20, %zmm0, %zmm24 +; AVX512BW-NEXT: vinserti32x4 $2, 64(%r8), %zmm8, %zmm6 +; AVX512BW-NEXT: vpermt2q %zmm21, %zmm0, %zmm6 +; AVX512BW-NEXT: vinserti32x4 $2, 128(%r8), %zmm7, %zmm5 +; AVX512BW-NEXT: vpermt2q %zmm19, %zmm0, %zmm5 +; AVX512BW-NEXT: vinserti32x4 $2, 192(%r8), %zmm2, %zmm4 +; AVX512BW-NEXT: vpermt2q %zmm18, %zmm0, %zmm4 +; AVX512BW-NEXT: vmovdqa (%rdi), %ymm0 +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm2, %zmm0 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512BW-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm2, %zmm2 # 64-byte Folded Reload +; AVX512BW-NEXT: # zmm2 = zmm2[0,1,2,3],mem[4,5,6,7] +; AVX512BW-NEXT: movb $16, %al +; AVX512BW-NEXT: kmovd %eax, %k1 +; AVX512BW-NEXT: vmovdqa64 %zmm23, %zmm11 {%k1} +; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm7 = <10,u,2,3,4,5,11,u> +; AVX512BW-NEXT: vpermt2q %zmm23, %zmm7, %zmm0 +; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm17 = <14,u,2,3,4,5,15,u> +; AVX512BW-NEXT: vpermt2q %zmm23, %zmm17, %zmm2 +; AVX512BW-NEXT: vmovdqa64 64(%rdi), %ymm23 +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm23 = ymm23[1],mem[1],ymm23[3],mem[3] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm23, %zmm29, %zmm23 +; AVX512BW-NEXT: vmovdqu64 (%rsp), %zmm8 # 64-byte Reload +; AVX512BW-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm8, %zmm29 # 64-byte Folded Reload +; AVX512BW-NEXT: # zmm29 = zmm8[0,1,2,3],mem[4,5,6,7] +; AVX512BW-NEXT: vmovdqa64 %zmm1, %zmm25 {%k1} +; AVX512BW-NEXT: vpermt2q %zmm1, %zmm7, %zmm23 +; AVX512BW-NEXT: vpermt2q %zmm1, %zmm17, %zmm29 +; AVX512BW-NEXT: vmovdqa 128(%rdi), %ymm1 +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm1[1],mem[1],ymm1[3],mem[3] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm8 # 64-byte Reload +; AVX512BW-NEXT: vinserti64x4 $0, %ymm1, %zmm8, %zmm1 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm8 # 64-byte Reload +; AVX512BW-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm8, %zmm30 # 64-byte Folded Reload +; AVX512BW-NEXT: # zmm30 = zmm8[0,1,2,3],mem[4,5,6,7] +; AVX512BW-NEXT: vmovdqa64 %zmm3, %zmm9 {%k1} +; AVX512BW-NEXT: vpermt2q %zmm3, %zmm7, %zmm1 +; AVX512BW-NEXT: vpermt2q %zmm3, %zmm17, %zmm30 +; AVX512BW-NEXT: vmovdqa 192(%rdi), %ymm3 +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm3 = ymm3[1],mem[1],ymm3[3],mem[3] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm3, %zmm28, %zmm3 +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm7, %zmm3 +; AVX512BW-NEXT: vmovdqa64 %zmm22, %zmm26 {%k1} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 # 64-byte Reload +; AVX512BW-NEXT: vshufi64x2 {{.*#+}} zmm7 = zmm7[0,1,2,3],zmm12[4,5,6,7] +; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm28 = [0,10,2,3,4,5,6,11] +; AVX512BW-NEXT: vpermt2q %zmm20, %zmm28, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm17, %zmm7 +; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm17 = [0,1,2,3,4,12,6,7] +; AVX512BW-NEXT: vpermt2q %zmm20, %zmm17, %zmm11 +; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm22 = [0,14,2,3,4,5,6,15] +; AVX512BW-NEXT: vpermt2q %zmm20, %zmm22, %zmm2 +; AVX512BW-NEXT: vpermt2q %zmm21, %zmm28, %zmm23 +; AVX512BW-NEXT: vpermt2q %zmm21, %zmm17, %zmm25 +; AVX512BW-NEXT: vpermt2q %zmm21, %zmm22, %zmm29 +; AVX512BW-NEXT: vpermt2q %zmm19, %zmm28, %zmm1 +; AVX512BW-NEXT: vpermt2q %zmm19, %zmm17, %zmm9 +; AVX512BW-NEXT: vpermt2q %zmm19, %zmm22, %zmm30 +; AVX512BW-NEXT: vpermt2q %zmm18, %zmm28, %zmm3 +; AVX512BW-NEXT: vpermt2q %zmm18, %zmm17, %zmm26 +; AVX512BW-NEXT: vpermt2q %zmm18, %zmm22, %zmm7 +; AVX512BW-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512BW-NEXT: vmovdqa64 %zmm7, 1472(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm13, 1408(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm26, 1344(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm3, 1280(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm10, 1216(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm30, 1088(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm16, 1024(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm9, 960(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm1, 896(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm15, 832(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm29, 704(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm14, 640(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm25, 576(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm23, 512(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm31, 448(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm2, 320(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm27, 256(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm11, 192(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm0, 128(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 64(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm4, 1152(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm5, 768(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm6, 384(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm24, (%rax) +; AVX512BW-NEXT: addq $712, %rsp # imm = 0x2C8 +; AVX512BW-NEXT: vzeroupper +; AVX512BW-NEXT: retq %in.vec0 = load <32 x i64>, ptr %in.vecptr0, align 64 %in.vec1 = load <32 x i64>, ptr %in.vecptr1, align 64 %in.vec2 = load <32 x i64>, ptr %in.vecptr2, align 64 @@ -7516,2713 +6678,1359 @@ define void @store_i64_stride6_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve ; AVX2-ONLY-NEXT: vzeroupper ; AVX2-ONLY-NEXT: retq ; -; AVX512F-ONLY-LABEL: store_i64_stride6_vf64: -; AVX512F-ONLY: # %bb.0: -; AVX512F-ONLY-NEXT: subq $3400, %rsp # imm = 0xD48 -; AVX512F-ONLY-NEXT: vmovdqa64 (%rdx), %zmm13 -; AVX512F-ONLY-NEXT: vmovdqa64 64(%rdx), %zmm12 -; AVX512F-ONLY-NEXT: vmovdqa64 128(%rdx), %zmm11 -; AVX512F-ONLY-NEXT: vmovdqa64 192(%rdx), %zmm10 -; AVX512F-ONLY-NEXT: vmovdqa64 256(%rdx), %zmm9 -; AVX512F-ONLY-NEXT: vmovdqa64 320(%rdx), %zmm8 -; AVX512F-ONLY-NEXT: vmovdqa64 384(%rdx), %zmm7 -; AVX512F-ONLY-NEXT: vmovdqa64 448(%rdx), %zmm6 -; AVX512F-ONLY-NEXT: vmovdqa64 (%rcx), %zmm0 -; AVX512F-ONLY-NEXT: vmovdqa64 64(%rcx), %zmm1 -; AVX512F-ONLY-NEXT: vmovdqa64 128(%rcx), %zmm2 -; AVX512F-ONLY-NEXT: vmovdqa64 192(%rcx), %zmm30 -; AVX512F-ONLY-NEXT: vmovdqa64 256(%rcx), %zmm27 -; AVX512F-ONLY-NEXT: vmovdqa64 320(%rcx), %zmm24 -; AVX512F-ONLY-NEXT: vmovdqa64 384(%rcx), %zmm22 -; AVX512F-ONLY-NEXT: vmovdqa64 448(%rcx), %zmm21 -; AVX512F-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [4,12,4,12] -; AVX512F-ONLY-NEXT: # ymm3 = mem[0,1,0,1] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm6, %zmm4 -; AVX512F-ONLY-NEXT: vpermt2q %zmm21, %zmm3, %zmm4 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, %zmm4 -; AVX512F-ONLY-NEXT: vpermt2q %zmm22, %zmm3, %zmm4 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm8, %zmm4 -; AVX512F-ONLY-NEXT: vpermt2q %zmm24, %zmm3, %zmm4 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm9, %zmm4 -; AVX512F-ONLY-NEXT: vpermt2q %zmm27, %zmm3, %zmm4 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm10, %zmm4 -; AVX512F-ONLY-NEXT: vpermt2q %zmm30, %zmm3, %zmm4 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm11, %zmm4 -; AVX512F-ONLY-NEXT: vpermt2q %zmm2, %zmm3, %zmm4 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm12, %zmm4 -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm3, %zmm4 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermi2q %zmm0, %zmm13, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm5 = [1,9,2,10,1,9,2,10] -; AVX512F-ONLY-NEXT: # zmm5 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm13, %zmm3 -; AVX512F-ONLY-NEXT: vpermt2q %zmm0, %zmm5, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm5, %zmm4 -; AVX512F-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm5 = [5,13,6,14,5,13,6,14] -; AVX512F-ONLY-NEXT: # zmm5 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm13, %zmm3 -; AVX512F-ONLY-NEXT: vpermt2q %zmm0, %zmm5, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm12, %zmm3 -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm4, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm14 = [3,11,3,11,3,11,3,11] -; AVX512F-ONLY-NEXT: # zmm14 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm13, %zmm3 -; AVX512F-ONLY-NEXT: vpermt2q %zmm0, %zmm14, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm3 = [7,15,7,15,7,15,7,15] -; AVX512F-ONLY-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vpermt2q %zmm0, %zmm3, %zmm13 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm12, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm5, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm12, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm14, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm3, %zmm12 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm11, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm2, %zmm4, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm11, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm2, %zmm5, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm11, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm2, %zmm14, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm2, %zmm3, %zmm11 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm10, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm30, %zmm4, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm10, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm30, %zmm5, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm10, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm30, %zmm14, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm30, %zmm3, %zmm10 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm9, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm27, %zmm4, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm9, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm27, %zmm5, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm9, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm27, %zmm14, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm27, %zmm3, %zmm9 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm24, %zmm4, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm24, %zmm5, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm24, %zmm14, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm24, %zmm3, %zmm8 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm22, %zmm4, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm22, %zmm5, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm22, %zmm14, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm22, %zmm3, %zmm7 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermi2q %zmm21, %zmm6, %zmm4 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm4, (%rsp) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermi2q %zmm21, %zmm6, %zmm5 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermi2q %zmm21, %zmm6, %zmm14 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm14, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm21, %zmm3, %zmm6 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 448(%rdi), %zmm4 -; AVX512F-ONLY-NEXT: vmovdqa64 448(%rsi), %zmm11 -; AVX512F-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm28 = [4,12,5,13,4,12,5,13] -; AVX512F-ONLY-NEXT: # zmm28 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm11, %zmm28, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, %zmm8 -; AVX512F-ONLY-NEXT: vmovdqa64 384(%rdi), %zmm2 -; AVX512F-ONLY-NEXT: vmovdqa64 384(%rsi), %zmm13 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm1 -; AVX512F-ONLY-NEXT: vpermt2q %zmm13, %zmm28, %zmm1 -; AVX512F-ONLY-NEXT: vmovdqa64 320(%rdi), %zmm3 -; AVX512F-ONLY-NEXT: vmovdqa64 320(%rsi), %zmm15 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm3, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm15, %zmm28, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 256(%rdi), %zmm31 -; AVX512F-ONLY-NEXT: vmovdqa64 256(%rsi), %zmm17 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm31, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm17, %zmm28, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 192(%rdi), %zmm29 -; AVX512F-ONLY-NEXT: vmovdqa64 192(%rsi), %zmm18 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm29, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm18, %zmm28, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 128(%rdi), %zmm25 -; AVX512F-ONLY-NEXT: vmovdqa64 128(%rsi), %zmm19 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm25, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm19, %zmm28, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, %zmm5 -; AVX512F-ONLY-NEXT: vmovdqa64 64(%rdi), %zmm6 -; AVX512F-ONLY-NEXT: vmovdqa64 64(%rsi), %zmm20 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm6, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm20, %zmm28, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 (%rdi), %zmm7 -; AVX512F-ONLY-NEXT: vmovdqa64 (%rsi), %zmm22 -; AVX512F-ONLY-NEXT: vpermi2q %zmm22, %zmm7, %zmm28 -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm12 = [2,10,2,10,2,10,2,10] -; AVX512F-ONLY-NEXT: # zmm12 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, %zmm14 -; AVX512F-ONLY-NEXT: vpermt2q %zmm22, %zmm12, %zmm14 -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm10 = [6,14,6,14,6,14,6,14] -; AVX512F-ONLY-NEXT: # zmm10 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, %zmm16 -; AVX512F-ONLY-NEXT: vpermt2q %zmm22, %zmm10, %zmm16 -; AVX512F-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm21 = [0,8,1,9,0,8,1,9] -; AVX512F-ONLY-NEXT: # zmm21 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm22, %zmm21, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} ymm23 = [7,15,7,15] -; AVX512F-ONLY-NEXT: # ymm23 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vpermt2q %zmm22, %zmm23, %zmm7 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm6, %zmm22 -; AVX512F-ONLY-NEXT: vpermt2q %zmm20, %zmm12, %zmm22 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm6, %zmm24 -; AVX512F-ONLY-NEXT: vpermt2q %zmm20, %zmm10, %zmm24 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm6, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm20, %zmm21, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm20, %zmm23, %zmm6 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm25, %zmm20 -; AVX512F-ONLY-NEXT: vpermt2q %zmm19, %zmm12, %zmm20 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm25, %zmm26 -; AVX512F-ONLY-NEXT: vpermt2q %zmm19, %zmm10, %zmm26 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm25, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm19, %zmm21, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm19, %zmm23, %zmm25 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm29, %zmm19 -; AVX512F-ONLY-NEXT: vpermt2q %zmm18, %zmm12, %zmm19 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm29, %zmm27 -; AVX512F-ONLY-NEXT: vpermt2q %zmm18, %zmm10, %zmm27 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm29, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm18, %zmm21, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm18, %zmm23, %zmm29 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm31, %zmm18 -; AVX512F-ONLY-NEXT: vpermt2q %zmm17, %zmm12, %zmm18 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm31, %zmm9 -; AVX512F-ONLY-NEXT: vpermt2q %zmm17, %zmm10, %zmm9 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm31, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm17, %zmm21, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm17, %zmm23, %zmm31 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm3, %zmm17 -; AVX512F-ONLY-NEXT: vpermt2q %zmm15, %zmm12, %zmm17 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm3, %zmm30 -; AVX512F-ONLY-NEXT: vpermt2q %zmm15, %zmm10, %zmm30 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm3, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm15, %zmm21, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm15, %zmm23, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm15 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512F-ONLY-NEXT: vpermt2q %zmm13, %zmm12, %zmm3 -; AVX512F-ONLY-NEXT: vpermt2q %zmm13, %zmm10, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm15, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm13, %zmm21, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm13, %zmm23, %zmm15 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm15, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermi2q %zmm11, %zmm4, %zmm12 -; AVX512F-ONLY-NEXT: vpermi2q %zmm11, %zmm4, %zmm10 -; AVX512F-ONLY-NEXT: vpermi2q %zmm11, %zmm4, %zmm21 -; AVX512F-ONLY-NEXT: vpermt2q %zmm11, %zmm23, %zmm4 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: movb $12, %al -; AVX512F-ONLY-NEXT: kmovw %eax, %k1 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm11, %zmm8 {%k1} -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm11, %zmm1 {%k1} -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm8 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm11, %zmm8 {%k1} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm11, %zmm0 {%k1} -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm11, %zmm4 {%k1} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm11, %zmm5 {%k1} -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm11, %zmm1 {%k1} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm11, %zmm28 {%k1} -; AVX512F-ONLY-NEXT: movb $48, %al -; AVX512F-ONLY-NEXT: kmovw %eax, %k2 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm14, %zmm11 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm23 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm16, %zmm23 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm22, %zmm13 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm22 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm24, %zmm22 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm14 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm20, %zmm14 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm20 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm26, %zmm20 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm19, %zmm16 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm27, %zmm19 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm24 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm18, %zmm24 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm18 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm9, %zmm18 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm26 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm17, %zmm26 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm17 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm30, %zmm17 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm27 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm3, %zmm27 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm0 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 (%rsp), %zmm15 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm12, %zmm15 {%k2} -; AVX512F-ONLY-NEXT: vmovdqa64 (%r8), %zmm5 -; AVX512F-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm2 = <0,1,9,u,4,5,6,7> -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm2, %zmm11 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 64(%r8), %zmm3 -; AVX512F-ONLY-NEXT: vpermt2q %zmm3, %zmm2, %zmm13 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 128(%r8), %zmm9 -; AVX512F-ONLY-NEXT: vpermt2q %zmm9, %zmm2, %zmm14 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm14, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 192(%r8), %zmm11 -; AVX512F-ONLY-NEXT: vpermt2q %zmm11, %zmm2, %zmm16 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm16, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 256(%r8), %zmm13 -; AVX512F-ONLY-NEXT: vpermt2q %zmm13, %zmm2, %zmm24 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm24, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 320(%r8), %zmm14 -; AVX512F-ONLY-NEXT: vpermt2q %zmm14, %zmm2, %zmm26 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm26, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 384(%r8), %zmm16 -; AVX512F-ONLY-NEXT: vpermt2q %zmm16, %zmm2, %zmm27 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm27, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 448(%r8), %zmm12 -; AVX512F-ONLY-NEXT: vpermt2q %zmm12, %zmm2, %zmm15 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm15, (%rsp) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm10, %zmm15 {%k2} -; AVX512F-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm2 = <0,1,13,u,4,5,6,7> -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm2, %zmm23 -; AVX512F-ONLY-NEXT: vpermt2q %zmm3, %zmm2, %zmm22 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm22, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm9, %zmm2, %zmm20 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm20, %zmm24 -; AVX512F-ONLY-NEXT: vpermt2q %zmm11, %zmm2, %zmm19 -; AVX512F-ONLY-NEXT: vpermt2q %zmm13, %zmm2, %zmm18 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm18, %zmm26 -; AVX512F-ONLY-NEXT: vpermt2q %zmm14, %zmm2, %zmm17 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm17, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm16, %zmm2, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm12, %zmm2, %zmm15 -; AVX512F-ONLY-NEXT: vmovdqa (%rdi), %ymm2 -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm2 = ymm2[1],mem[1],ymm2[3],mem[3] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm0, %zmm10 -; AVX512F-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm7, %zmm7 # 64-byte Folded Reload -; AVX512F-ONLY-NEXT: # zmm7 = zmm7[0,1,2,3],mem[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqa 64(%rdi), %ymm2 -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm2 = ymm2[1],mem[1],ymm2[3],mem[3] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm0, %zmm0 -; AVX512F-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm6, %zmm6 # 64-byte Folded Reload -; AVX512F-ONLY-NEXT: # zmm6 = zmm6[0,1,2,3],mem[4,5,6,7] -; AVX512F-ONLY-NEXT: movb $16, %al -; AVX512F-ONLY-NEXT: kmovw %eax, %k2 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm3, %zmm1 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm1 = <10,u,2,3,4,5,11,u> -; AVX512F-ONLY-NEXT: vpermt2q %zmm3, %zmm1, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm2 = <14,u,2,3,4,5,15,u> -; AVX512F-ONLY-NEXT: vpermt2q %zmm3, %zmm2, %zmm6 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa 128(%rdi), %ymm3 -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm3 = ymm3[1],mem[1],ymm3[3],mem[3] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm3, %zmm0, %zmm3 -; AVX512F-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm25, %zmm6 # 64-byte Folded Reload -; AVX512F-ONLY-NEXT: # zmm6 = zmm25[0,1,2,3],mem[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm9, %zmm0 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm9, %zmm1, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm9, %zmm2, %zmm6 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa 192(%rdi), %ymm3 -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm3 = ymm3[1],mem[1],ymm3[3],mem[3] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm3, %zmm0, %zmm0 -; AVX512F-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm29, %zmm3 # 64-byte Folded Reload -; AVX512F-ONLY-NEXT: # zmm3 = zmm29[0,1,2,3],mem[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm11, %zmm4 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm11, %zmm1, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm11, %zmm2, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa 256(%rdi), %ymm0 -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm3 -; AVX512F-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm31, %zmm4 # 64-byte Folded Reload -; AVX512F-ONLY-NEXT: # zmm4 = zmm31[0,1,2,3],mem[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm13, %zmm0 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm13, %zmm1, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm13, %zmm2, %zmm4 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa 320(%rdi), %ymm0 -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm27 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm25 # 64-byte Folded Reload -; AVX512F-ONLY-NEXT: # zmm25 = zmm0[0,1,2,3],mem[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm14, %zmm8 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm14, %zmm1, %zmm27 -; AVX512F-ONLY-NEXT: vpermt2q %zmm14, %zmm2, %zmm25 -; AVX512F-ONLY-NEXT: vmovdqa 384(%rdi), %ymm0 -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm22 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm20 # 64-byte Folded Reload -; AVX512F-ONLY-NEXT: # zmm20 = zmm0[0,1,2,3],mem[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm16, %zmm0 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm16, %zmm1, %zmm22 -; AVX512F-ONLY-NEXT: vpermt2q %zmm16, %zmm2, %zmm20 -; AVX512F-ONLY-NEXT: vmovdqa 448(%rdi), %ymm0 -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm18 -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm1, %zmm10 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm10, %zmm11 -; AVX512F-ONLY-NEXT: vpermt2q %zmm12, %zmm1, %zmm18 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm17 # 64-byte Folded Reload -; AVX512F-ONLY-NEXT: # zmm17 = zmm0[0,1,2,3],mem[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm12, %zmm0 {%k2} -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm12, %zmm2, %zmm17 -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm2, %zmm7 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, %zmm13 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm5, %zmm28 {%k2} -; AVX512F-ONLY-NEXT: vmovdqa64 (%r9), %zmm6 -; AVX512F-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm10 = [0,1,2,9,4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm6, %zmm10, %zmm1 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 64(%r9), %zmm7 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm7, %zmm10, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 128(%r9), %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm2, %zmm10, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 192(%r9), %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm3, %zmm10, %zmm4 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 256(%r9), %zmm4 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm4, %zmm10, %zmm5 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 320(%r9), %zmm5 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm10, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 384(%r9), %zmm8 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm8, %zmm10, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 448(%r9), %zmm9 -; AVX512F-ONLY-NEXT: vmovdqu64 (%rsp), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm9, %zmm10, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, (%rsp) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm10 = [0,1,2,13,4,5,6,7] -; AVX512F-ONLY-NEXT: vpermt2q %zmm6, %zmm10, %zmm23 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm23, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm7, %zmm10, %zmm12 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm2, %zmm10, %zmm24 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm24, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm3, %zmm10, %zmm19 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm19, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm4, %zmm10, %zmm26 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm26, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm10, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm8, %zmm10, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm9, %zmm10, %zmm15 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm15, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa (%rdx), %xmm10 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512F-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm12 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa 64(%rdx), %xmm10 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512F-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm14 # 64-byte Reload -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm14 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa 128(%rdx), %xmm10 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512F-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm16 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa 192(%rdx), %xmm10 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512F-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm30 # 64-byte Reload -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm30 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa 256(%rdx), %xmm10 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512F-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm31 # 64-byte Reload -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm31 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa 320(%rdx), %xmm10 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512F-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm1 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa 384(%rdx), %xmm10 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512F-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm0 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa 448(%rdx), %xmm10 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512F-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm21 {%k1} -; AVX512F-ONLY-NEXT: vinserti32x4 $2, (%r8), %zmm12, %zmm10 -; AVX512F-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm29 = [0,1,2,3,4,8,6,7] -; AVX512F-ONLY-NEXT: vpermt2q %zmm6, %zmm29, %zmm10 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vinserti32x4 $2, 64(%r8), %zmm14, %zmm10 -; AVX512F-ONLY-NEXT: vpermt2q %zmm7, %zmm29, %zmm10 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vinserti32x4 $2, 128(%r8), %zmm16, %zmm10 -; AVX512F-ONLY-NEXT: vpermt2q %zmm2, %zmm29, %zmm10 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vinserti32x4 $2, 192(%r8), %zmm30, %zmm26 -; AVX512F-ONLY-NEXT: vpermt2q %zmm3, %zmm29, %zmm26 -; AVX512F-ONLY-NEXT: vinserti32x4 $2, 256(%r8), %zmm31, %zmm24 -; AVX512F-ONLY-NEXT: vpermt2q %zmm4, %zmm29, %zmm24 -; AVX512F-ONLY-NEXT: vinserti32x4 $2, 320(%r8), %zmm1, %zmm23 -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm29, %zmm23 -; AVX512F-ONLY-NEXT: vinserti32x4 $2, 384(%r8), %zmm0, %zmm19 -; AVX512F-ONLY-NEXT: vpermt2q %zmm8, %zmm29, %zmm19 -; AVX512F-ONLY-NEXT: vinserti32x4 $2, 448(%r8), %zmm21, %zmm21 -; AVX512F-ONLY-NEXT: vpermt2q %zmm9, %zmm29, %zmm21 -; AVX512F-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm29 = [0,10,2,3,4,5,6,11] -; AVX512F-ONLY-NEXT: vpermt2q %zmm6, %zmm29, %zmm11 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm30 = [0,1,2,3,4,12,6,7] -; AVX512F-ONLY-NEXT: vpermt2q %zmm6, %zmm30, %zmm28 -; AVX512F-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm31 = [0,14,2,3,4,5,6,15] -; AVX512F-ONLY-NEXT: vpermt2q %zmm6, %zmm31, %zmm13 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm7, %zmm29, %zmm16 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm7, %zmm30, %zmm15 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm14 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm7, %zmm31, %zmm14 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm2, %zmm29, %zmm13 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm2, %zmm30, %zmm12 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm2, %zmm31, %zmm11 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm10 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm3, %zmm29, %zmm10 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm3, %zmm30, %zmm7 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm3, %zmm31, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm4, %zmm29, %zmm1 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm4, %zmm30, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm4, %zmm31, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm29, %zmm27 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm30, %zmm4 -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm31, %zmm25 -; AVX512F-ONLY-NEXT: vpermt2q %zmm8, %zmm29, %zmm22 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm8, %zmm30, %zmm5 -; AVX512F-ONLY-NEXT: vpermt2q %zmm8, %zmm31, %zmm20 -; AVX512F-ONLY-NEXT: vpermt2q %zmm9, %zmm29, %zmm18 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm9, %zmm30, %zmm6 -; AVX512F-ONLY-NEXT: vpermt2q %zmm9, %zmm31, %zmm17 -; AVX512F-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm17, 3008(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm8 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm8, 2944(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm6, 2880(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm18, 2816(%rax) -; AVX512F-ONLY-NEXT: vmovups (%rsp), %zmm6 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm6, 2752(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm20, 2624(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm6, 2560(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm5, 2496(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm22, 2432(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm5, 2368(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm25, 2240(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm5, 2176(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, 2112(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm27, 2048(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm4, 1984(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, 1856(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 1792(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm3, 1728(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm1, 1664(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm3, 1600(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, 1472(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 1408(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, 1344(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm10, 1280(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm2, 1216(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm11, 1088(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 1024(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm12, 960(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm13, 896(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm1, 832(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm14, 704(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm1, 640(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm15, 576(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm16, 512(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 448(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 320(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 256(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm28, 192(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 128(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 64(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm21, 2688(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm19, 2304(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm23, 1920(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm24, 1536(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm26, 1152(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 768(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 384(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, (%rax) -; AVX512F-ONLY-NEXT: addq $3400, %rsp # imm = 0xD48 -; AVX512F-ONLY-NEXT: vzeroupper -; AVX512F-ONLY-NEXT: retq -; -; AVX512DQ-ONLY-LABEL: store_i64_stride6_vf64: -; AVX512DQ-ONLY: # %bb.0: -; AVX512DQ-ONLY-NEXT: subq $3400, %rsp # imm = 0xD48 -; AVX512DQ-ONLY-NEXT: vmovdqa64 (%rdx), %zmm13 -; AVX512DQ-ONLY-NEXT: vmovdqa64 64(%rdx), %zmm12 -; AVX512DQ-ONLY-NEXT: vmovdqa64 128(%rdx), %zmm11 -; AVX512DQ-ONLY-NEXT: vmovdqa64 192(%rdx), %zmm10 -; AVX512DQ-ONLY-NEXT: vmovdqa64 256(%rdx), %zmm9 -; AVX512DQ-ONLY-NEXT: vmovdqa64 320(%rdx), %zmm8 -; AVX512DQ-ONLY-NEXT: vmovdqa64 384(%rdx), %zmm7 -; AVX512DQ-ONLY-NEXT: vmovdqa64 448(%rdx), %zmm6 -; AVX512DQ-ONLY-NEXT: vmovdqa64 (%rcx), %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqa64 64(%rcx), %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqa64 128(%rcx), %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqa64 192(%rcx), %zmm30 -; AVX512DQ-ONLY-NEXT: vmovdqa64 256(%rcx), %zmm27 -; AVX512DQ-ONLY-NEXT: vmovdqa64 320(%rcx), %zmm24 -; AVX512DQ-ONLY-NEXT: vmovdqa64 384(%rcx), %zmm22 -; AVX512DQ-ONLY-NEXT: vmovdqa64 448(%rcx), %zmm21 -; AVX512DQ-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [4,12,4,12] -; AVX512DQ-ONLY-NEXT: # ymm3 = mem[0,1,0,1] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm6, %zmm4 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm21, %zmm3, %zmm4 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, %zmm4 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm22, %zmm3, %zmm4 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm8, %zmm4 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm24, %zmm3, %zmm4 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm9, %zmm4 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm27, %zmm3, %zmm4 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm10, %zmm4 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm30, %zmm3, %zmm4 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm11, %zmm4 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm2, %zmm3, %zmm4 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm12, %zmm4 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm3, %zmm4 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm0, %zmm13, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm5 = [1,9,2,10,1,9,2,10] -; AVX512DQ-ONLY-NEXT: # zmm5 = mem[0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm13, %zmm3 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm0, %zmm5, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm5, %zmm4 -; AVX512DQ-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm5 = [5,13,6,14,5,13,6,14] -; AVX512DQ-ONLY-NEXT: # zmm5 = mem[0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm13, %zmm3 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm0, %zmm5, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm12, %zmm3 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm4, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm14 = [3,11,3,11,3,11,3,11] -; AVX512DQ-ONLY-NEXT: # zmm14 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm13, %zmm3 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm0, %zmm14, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm3 = [7,15,7,15,7,15,7,15] -; AVX512DQ-ONLY-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm0, %zmm3, %zmm13 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm12, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm5, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm12, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm14, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm3, %zmm12 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm11, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm2, %zmm4, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm11, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm2, %zmm5, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm11, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm2, %zmm14, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm2, %zmm3, %zmm11 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm10, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm30, %zmm4, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm10, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm30, %zmm5, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm10, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm30, %zmm14, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm30, %zmm3, %zmm10 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm9, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm27, %zmm4, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm9, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm27, %zmm5, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm9, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm27, %zmm14, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm27, %zmm3, %zmm9 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm24, %zmm4, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm24, %zmm5, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm24, %zmm14, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm24, %zmm3, %zmm8 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm22, %zmm4, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm22, %zmm5, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm22, %zmm14, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm22, %zmm3, %zmm7 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm21, %zmm6, %zmm4 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm4, (%rsp) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm21, %zmm6, %zmm5 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm21, %zmm6, %zmm14 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm14, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm21, %zmm3, %zmm6 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 448(%rdi), %zmm4 -; AVX512DQ-ONLY-NEXT: vmovdqa64 448(%rsi), %zmm11 -; AVX512DQ-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm28 = [4,12,5,13,4,12,5,13] -; AVX512DQ-ONLY-NEXT: # zmm28 = mem[0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm11, %zmm28, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, %zmm8 -; AVX512DQ-ONLY-NEXT: vmovdqa64 384(%rdi), %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqa64 384(%rsi), %zmm13 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm1 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm13, %zmm28, %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqa64 320(%rdi), %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqa64 320(%rsi), %zmm15 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm3, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm15, %zmm28, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 256(%rdi), %zmm31 -; AVX512DQ-ONLY-NEXT: vmovdqa64 256(%rsi), %zmm17 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm31, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm17, %zmm28, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 192(%rdi), %zmm29 -; AVX512DQ-ONLY-NEXT: vmovdqa64 192(%rsi), %zmm18 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm29, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm18, %zmm28, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 128(%rdi), %zmm25 -; AVX512DQ-ONLY-NEXT: vmovdqa64 128(%rsi), %zmm19 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm25, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm19, %zmm28, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, %zmm5 -; AVX512DQ-ONLY-NEXT: vmovdqa64 64(%rdi), %zmm6 -; AVX512DQ-ONLY-NEXT: vmovdqa64 64(%rsi), %zmm20 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm6, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm20, %zmm28, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 (%rdi), %zmm7 -; AVX512DQ-ONLY-NEXT: vmovdqa64 (%rsi), %zmm22 -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm22, %zmm7, %zmm28 -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm12 = [2,10,2,10,2,10,2,10] -; AVX512DQ-ONLY-NEXT: # zmm12 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, %zmm14 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm22, %zmm12, %zmm14 -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm10 = [6,14,6,14,6,14,6,14] -; AVX512DQ-ONLY-NEXT: # zmm10 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, %zmm16 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm22, %zmm10, %zmm16 -; AVX512DQ-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm21 = [0,8,1,9,0,8,1,9] -; AVX512DQ-ONLY-NEXT: # zmm21 = mem[0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm22, %zmm21, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vbroadcasti64x2 {{.*#+}} ymm23 = [7,15,7,15] -; AVX512DQ-ONLY-NEXT: # ymm23 = mem[0,1,0,1] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm22, %zmm23, %zmm7 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm6, %zmm22 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm20, %zmm12, %zmm22 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm6, %zmm24 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm20, %zmm10, %zmm24 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm6, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm20, %zmm21, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm20, %zmm23, %zmm6 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm25, %zmm20 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm19, %zmm12, %zmm20 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm25, %zmm26 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm19, %zmm10, %zmm26 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm25, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm19, %zmm21, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm19, %zmm23, %zmm25 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm29, %zmm19 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm18, %zmm12, %zmm19 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm29, %zmm27 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm18, %zmm10, %zmm27 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm29, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm18, %zmm21, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm18, %zmm23, %zmm29 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm31, %zmm18 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm17, %zmm12, %zmm18 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm31, %zmm9 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm17, %zmm10, %zmm9 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm31, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm17, %zmm21, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm17, %zmm23, %zmm31 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm3, %zmm17 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm15, %zmm12, %zmm17 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm3, %zmm30 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm15, %zmm10, %zmm30 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm3, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm15, %zmm21, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm15, %zmm23, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm15 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm13, %zmm12, %zmm3 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm13, %zmm10, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm15, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm13, %zmm21, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm13, %zmm23, %zmm15 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm15, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm11, %zmm4, %zmm12 -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm11, %zmm4, %zmm10 -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm11, %zmm4, %zmm21 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm11, %zmm23, %zmm4 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: movb $12, %al -; AVX512DQ-ONLY-NEXT: kmovw %eax, %k1 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm11, %zmm8 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm11, %zmm1 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm8 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm11, %zmm8 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm11, %zmm0 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm11, %zmm4 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm11, %zmm5 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm11, %zmm1 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm11, %zmm28 {%k1} -; AVX512DQ-ONLY-NEXT: movb $48, %al -; AVX512DQ-ONLY-NEXT: kmovw %eax, %k2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm14, %zmm11 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm23 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm16, %zmm23 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm22, %zmm13 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm22 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm24, %zmm22 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm14 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm20, %zmm14 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm20 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm26, %zmm20 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm19, %zmm16 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm27, %zmm19 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm24 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm18, %zmm24 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm18 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm9, %zmm18 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm26 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm17, %zmm26 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm17 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm30, %zmm17 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm27 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm3, %zmm27 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm0 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 (%rsp), %zmm15 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm12, %zmm15 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqa64 (%r8), %zmm5 -; AVX512DQ-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm2 = <0,1,9,u,4,5,6,7> -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm2, %zmm11 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 64(%r8), %zmm3 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm3, %zmm2, %zmm13 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 128(%r8), %zmm9 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm9, %zmm2, %zmm14 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm14, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 192(%r8), %zmm11 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm11, %zmm2, %zmm16 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm16, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 256(%r8), %zmm13 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm13, %zmm2, %zmm24 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm24, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 320(%r8), %zmm14 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm14, %zmm2, %zmm26 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm26, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 384(%r8), %zmm16 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm16, %zmm2, %zmm27 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm27, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 448(%r8), %zmm12 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm12, %zmm2, %zmm15 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm15, (%rsp) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm10, %zmm15 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm2 = <0,1,13,u,4,5,6,7> -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm2, %zmm23 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm3, %zmm2, %zmm22 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm22, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm9, %zmm2, %zmm20 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm20, %zmm24 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm11, %zmm2, %zmm19 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm13, %zmm2, %zmm18 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm18, %zmm26 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm14, %zmm2, %zmm17 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm17, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm16, %zmm2, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm12, %zmm2, %zmm15 -; AVX512DQ-ONLY-NEXT: vmovdqa (%rdi), %ymm2 -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm2 = ymm2[1],mem[1],ymm2[3],mem[3] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm0, %zmm10 -; AVX512DQ-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm7, %zmm7 # 64-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # zmm7 = zmm7[0,1,2,3],mem[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqa 64(%rdi), %ymm2 -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm2 = ymm2[1],mem[1],ymm2[3],mem[3] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm0, %zmm0 -; AVX512DQ-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm6, %zmm6 # 64-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # zmm6 = zmm6[0,1,2,3],mem[4,5,6,7] -; AVX512DQ-ONLY-NEXT: movb $16, %al -; AVX512DQ-ONLY-NEXT: kmovw %eax, %k2 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm3, %zmm1 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm1 = <10,u,2,3,4,5,11,u> -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm3, %zmm1, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm2 = <14,u,2,3,4,5,15,u> -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm3, %zmm2, %zmm6 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa 128(%rdi), %ymm3 -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm3 = ymm3[1],mem[1],ymm3[3],mem[3] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm3, %zmm0, %zmm3 -; AVX512DQ-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm25, %zmm6 # 64-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # zmm6 = zmm25[0,1,2,3],mem[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm9, %zmm0 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm9, %zmm1, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm9, %zmm2, %zmm6 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa 192(%rdi), %ymm3 -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm3 = ymm3[1],mem[1],ymm3[3],mem[3] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm3, %zmm0, %zmm0 -; AVX512DQ-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm29, %zmm3 # 64-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # zmm3 = zmm29[0,1,2,3],mem[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm11, %zmm4 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm11, %zmm1, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm11, %zmm2, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa 256(%rdi), %ymm0 -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm3 -; AVX512DQ-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm31, %zmm4 # 64-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # zmm4 = zmm31[0,1,2,3],mem[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm13, %zmm0 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm13, %zmm1, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm13, %zmm2, %zmm4 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa 320(%rdi), %ymm0 -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm27 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm25 # 64-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # zmm25 = zmm0[0,1,2,3],mem[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm14, %zmm8 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm14, %zmm1, %zmm27 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm14, %zmm2, %zmm25 -; AVX512DQ-ONLY-NEXT: vmovdqa 384(%rdi), %ymm0 -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm22 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm20 # 64-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # zmm20 = zmm0[0,1,2,3],mem[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm16, %zmm0 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm16, %zmm1, %zmm22 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm16, %zmm2, %zmm20 -; AVX512DQ-ONLY-NEXT: vmovdqa 448(%rdi), %ymm0 -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm18 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm1, %zmm10 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm10, %zmm11 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm12, %zmm1, %zmm18 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm17 # 64-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # zmm17 = zmm0[0,1,2,3],mem[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm12, %zmm0 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm12, %zmm2, %zmm17 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm2, %zmm7 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, %zmm13 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm5, %zmm28 {%k2} -; AVX512DQ-ONLY-NEXT: vmovdqa64 (%r9), %zmm6 -; AVX512DQ-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm10 = [0,1,2,9,4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm6, %zmm10, %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 64(%r9), %zmm7 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm7, %zmm10, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 128(%r9), %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm2, %zmm10, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 192(%r9), %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm3, %zmm10, %zmm4 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 256(%r9), %zmm4 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm4, %zmm10, %zmm5 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 320(%r9), %zmm5 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm10, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 384(%r9), %zmm8 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm8, %zmm10, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 448(%r9), %zmm9 -; AVX512DQ-ONLY-NEXT: vmovdqu64 (%rsp), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm9, %zmm10, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, (%rsp) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm10 = [0,1,2,13,4,5,6,7] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm6, %zmm10, %zmm23 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm23, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm7, %zmm10, %zmm12 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm2, %zmm10, %zmm24 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm24, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm3, %zmm10, %zmm19 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm19, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm4, %zmm10, %zmm26 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm26, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm10, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm8, %zmm10, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm9, %zmm10, %zmm15 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm15, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa (%rdx), %xmm10 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512DQ-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm12 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa 64(%rdx), %xmm10 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512DQ-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm14 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm14 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa 128(%rdx), %xmm10 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512DQ-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm16 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa 192(%rdx), %xmm10 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512DQ-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm30 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm30 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa 256(%rdx), %xmm10 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512DQ-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm31 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm31 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa 320(%rdx), %xmm10 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512DQ-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm1 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa 384(%rdx), %xmm10 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512DQ-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm0 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa 448(%rdx), %xmm10 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512DQ-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm21 {%k1} -; AVX512DQ-ONLY-NEXT: vinserti32x4 $2, (%r8), %zmm12, %zmm10 -; AVX512DQ-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm29 = [0,1,2,3,4,8,6,7] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm6, %zmm29, %zmm10 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vinserti32x4 $2, 64(%r8), %zmm14, %zmm10 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm7, %zmm29, %zmm10 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vinserti32x4 $2, 128(%r8), %zmm16, %zmm10 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm2, %zmm29, %zmm10 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vinserti32x4 $2, 192(%r8), %zmm30, %zmm26 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm3, %zmm29, %zmm26 -; AVX512DQ-ONLY-NEXT: vinserti32x4 $2, 256(%r8), %zmm31, %zmm24 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm4, %zmm29, %zmm24 -; AVX512DQ-ONLY-NEXT: vinserti32x4 $2, 320(%r8), %zmm1, %zmm23 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm29, %zmm23 -; AVX512DQ-ONLY-NEXT: vinserti32x4 $2, 384(%r8), %zmm0, %zmm19 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm8, %zmm29, %zmm19 -; AVX512DQ-ONLY-NEXT: vinserti32x4 $2, 448(%r8), %zmm21, %zmm21 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm9, %zmm29, %zmm21 -; AVX512DQ-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm29 = [0,10,2,3,4,5,6,11] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm6, %zmm29, %zmm11 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm30 = [0,1,2,3,4,12,6,7] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm6, %zmm30, %zmm28 -; AVX512DQ-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm31 = [0,14,2,3,4,5,6,15] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm6, %zmm31, %zmm13 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm7, %zmm29, %zmm16 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm7, %zmm30, %zmm15 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm14 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm7, %zmm31, %zmm14 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm2, %zmm29, %zmm13 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm2, %zmm30, %zmm12 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm2, %zmm31, %zmm11 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm10 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm3, %zmm29, %zmm10 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm3, %zmm30, %zmm7 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm3, %zmm31, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm4, %zmm29, %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm4, %zmm30, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm4, %zmm31, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm29, %zmm27 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm30, %zmm4 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm31, %zmm25 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm8, %zmm29, %zmm22 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm8, %zmm30, %zmm5 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm8, %zmm31, %zmm20 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm9, %zmm29, %zmm18 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm9, %zmm30, %zmm6 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm9, %zmm31, %zmm17 -; AVX512DQ-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm17, 3008(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm8 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm8, 2944(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm6, 2880(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm18, 2816(%rax) -; AVX512DQ-ONLY-NEXT: vmovups (%rsp), %zmm6 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm6, 2752(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm20, 2624(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm6, 2560(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm5, 2496(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm22, 2432(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm5, 2368(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm25, 2240(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm5, 2176(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, 2112(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm27, 2048(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm4, 1984(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, 1856(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 1792(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm3, 1728(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm1, 1664(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm3, 1600(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, 1472(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 1408(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, 1344(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm10, 1280(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm2, 1216(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm11, 1088(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 1024(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm12, 960(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm13, 896(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm1, 832(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm14, 704(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm1, 640(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm15, 576(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm16, 512(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 448(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 320(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 256(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm28, 192(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 128(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 64(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm21, 2688(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm19, 2304(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm23, 1920(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm24, 1536(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm26, 1152(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 768(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 384(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, (%rax) -; AVX512DQ-ONLY-NEXT: addq $3400, %rsp # imm = 0xD48 -; AVX512DQ-ONLY-NEXT: vzeroupper -; AVX512DQ-ONLY-NEXT: retq -; -; AVX512BW-ONLY-LABEL: store_i64_stride6_vf64: -; AVX512BW-ONLY: # %bb.0: -; AVX512BW-ONLY-NEXT: subq $3400, %rsp # imm = 0xD48 -; AVX512BW-ONLY-NEXT: vmovdqa64 (%rdx), %zmm13 -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%rdx), %zmm12 -; AVX512BW-ONLY-NEXT: vmovdqa64 128(%rdx), %zmm11 -; AVX512BW-ONLY-NEXT: vmovdqa64 192(%rdx), %zmm10 -; AVX512BW-ONLY-NEXT: vmovdqa64 256(%rdx), %zmm9 -; AVX512BW-ONLY-NEXT: vmovdqa64 320(%rdx), %zmm8 -; AVX512BW-ONLY-NEXT: vmovdqa64 384(%rdx), %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqa64 448(%rdx), %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqa64 (%rcx), %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%rcx), %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqa64 128(%rcx), %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqa64 192(%rcx), %zmm30 -; AVX512BW-ONLY-NEXT: vmovdqa64 256(%rcx), %zmm27 -; AVX512BW-ONLY-NEXT: vmovdqa64 320(%rcx), %zmm24 -; AVX512BW-ONLY-NEXT: vmovdqa64 384(%rcx), %zmm22 -; AVX512BW-ONLY-NEXT: vmovdqa64 448(%rcx), %zmm21 -; AVX512BW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [4,12,4,12] -; AVX512BW-ONLY-NEXT: # ymm3 = mem[0,1,0,1] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm4 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm21, %zmm3, %zmm4 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm4 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm3, %zmm4 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm8, %zmm4 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm24, %zmm3, %zmm4 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm9, %zmm4 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm27, %zmm3, %zmm4 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm4 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm30, %zmm3, %zmm4 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm4 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm3, %zmm4 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm4 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm1, %zmm3, %zmm4 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermi2q %zmm0, %zmm13, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm5 = [1,9,2,10,1,9,2,10] -; AVX512BW-ONLY-NEXT: # zmm5 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm13, %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm0, %zmm5, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm4 -; AVX512BW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm5 = [5,13,6,14,5,13,6,14] -; AVX512BW-ONLY-NEXT: # zmm5 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm13, %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm0, %zmm5, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm1, %zmm4, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm14 = [3,11,3,11,3,11,3,11] -; AVX512BW-ONLY-NEXT: # zmm14 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm13, %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm0, %zmm14, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm3 = [7,15,7,15,7,15,7,15] -; AVX512BW-ONLY-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm0, %zmm3, %zmm13 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm1, %zmm5, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm1, %zmm14, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm1, %zmm3, %zmm12 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm4, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm5, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm14, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm3, %zmm11 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm30, %zmm4, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm30, %zmm5, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm30, %zmm14, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm30, %zmm3, %zmm10 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm9, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm27, %zmm4, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm9, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm27, %zmm5, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm9, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm27, %zmm14, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm27, %zmm3, %zmm9 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm24, %zmm4, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm24, %zmm5, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm24, %zmm14, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm24, %zmm3, %zmm8 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm4, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm5, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm14, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm3, %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermi2q %zmm21, %zmm6, %zmm4 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm4, (%rsp) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermi2q %zmm21, %zmm6, %zmm5 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermi2q %zmm21, %zmm6, %zmm14 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm14, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm21, %zmm3, %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 448(%rdi), %zmm4 -; AVX512BW-ONLY-NEXT: vmovdqa64 448(%rsi), %zmm11 -; AVX512BW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm28 = [4,12,5,13,4,12,5,13] -; AVX512BW-ONLY-NEXT: # zmm28 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm11, %zmm28, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm8 -; AVX512BW-ONLY-NEXT: vmovdqa64 384(%rdi), %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqa64 384(%rsi), %zmm13 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm1 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm13, %zmm28, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqa64 320(%rdi), %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqa64 320(%rsi), %zmm15 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm15, %zmm28, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 256(%rdi), %zmm31 -; AVX512BW-ONLY-NEXT: vmovdqa64 256(%rsi), %zmm17 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm31, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm17, %zmm28, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 192(%rdi), %zmm29 -; AVX512BW-ONLY-NEXT: vmovdqa64 192(%rsi), %zmm18 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm18, %zmm28, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 128(%rdi), %zmm25 -; AVX512BW-ONLY-NEXT: vmovdqa64 128(%rsi), %zmm19 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm19, %zmm28, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm5 -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%rdi), %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%rsi), %zmm20 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm20, %zmm28, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 (%rdi), %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqa64 (%rsi), %zmm22 -; AVX512BW-ONLY-NEXT: vpermi2q %zmm22, %zmm7, %zmm28 -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm12 = [2,10,2,10,2,10,2,10] -; AVX512BW-ONLY-NEXT: # zmm12 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm14 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm12, %zmm14 -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm10 = [6,14,6,14,6,14,6,14] -; AVX512BW-ONLY-NEXT: # zmm10 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm16 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm10, %zmm16 -; AVX512BW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm21 = [0,8,1,9,0,8,1,9] -; AVX512BW-ONLY-NEXT: # zmm21 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm21, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} ymm23 = [7,15,7,15] -; AVX512BW-ONLY-NEXT: # ymm23 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm23, %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm22 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm20, %zmm12, %zmm22 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm24 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm20, %zmm10, %zmm24 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm20, %zmm21, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm20, %zmm23, %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm20 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm19, %zmm12, %zmm20 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm26 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm19, %zmm10, %zmm26 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm19, %zmm21, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm19, %zmm23, %zmm25 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm19 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm18, %zmm12, %zmm19 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm27 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm18, %zmm10, %zmm27 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm18, %zmm21, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm18, %zmm23, %zmm29 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm31, %zmm18 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm17, %zmm12, %zmm18 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm31, %zmm9 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm17, %zmm10, %zmm9 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm31, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm17, %zmm21, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm17, %zmm23, %zmm31 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm17 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm15, %zmm12, %zmm17 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm30 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm15, %zmm10, %zmm30 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm15, %zmm21, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm15, %zmm23, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm15 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm13, %zmm12, %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm13, %zmm10, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm15, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm13, %zmm21, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm13, %zmm23, %zmm15 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm15, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermi2q %zmm11, %zmm4, %zmm12 -; AVX512BW-ONLY-NEXT: vpermi2q %zmm11, %zmm4, %zmm10 -; AVX512BW-ONLY-NEXT: vpermi2q %zmm11, %zmm4, %zmm21 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm11, %zmm23, %zmm4 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: movb $12, %al -; AVX512BW-ONLY-NEXT: kmovd %eax, %k1 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm8 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm1 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm8 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm8 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm0 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm4 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm5 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm1 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm28 {%k1} -; AVX512BW-ONLY-NEXT: movb $48, %al -; AVX512BW-ONLY-NEXT: kmovd %eax, %k2 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm14, %zmm11 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm23 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm16, %zmm23 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm22, %zmm13 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm22 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm24, %zmm22 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm14 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm20, %zmm14 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm20 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm20 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm19, %zmm16 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm27, %zmm19 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm24 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm18, %zmm24 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm18 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm9, %zmm18 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm26 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm17, %zmm26 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm17 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm30, %zmm17 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm27 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm27 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm0 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 (%rsp), %zmm15 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm15 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqa64 (%r8), %zmm5 -; AVX512BW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm2 = <0,1,9,u,4,5,6,7> -; AVX512BW-ONLY-NEXT: vpermt2q %zmm5, %zmm2, %zmm11 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%r8), %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm3, %zmm2, %zmm13 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 128(%r8), %zmm9 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm9, %zmm2, %zmm14 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm14, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 192(%r8), %zmm11 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm11, %zmm2, %zmm16 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm16, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 256(%r8), %zmm13 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm13, %zmm2, %zmm24 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm24, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 320(%r8), %zmm14 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm14, %zmm2, %zmm26 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm26, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 384(%r8), %zmm16 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm16, %zmm2, %zmm27 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm27, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 448(%r8), %zmm12 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm12, %zmm2, %zmm15 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm15, (%rsp) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm15 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm2 = <0,1,13,u,4,5,6,7> -; AVX512BW-ONLY-NEXT: vpermt2q %zmm5, %zmm2, %zmm23 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm3, %zmm2, %zmm22 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm22, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm9, %zmm2, %zmm20 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm20, %zmm24 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm11, %zmm2, %zmm19 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm13, %zmm2, %zmm18 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm18, %zmm26 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm14, %zmm2, %zmm17 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm17, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm16, %zmm2, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm12, %zmm2, %zmm15 -; AVX512BW-ONLY-NEXT: vmovdqa (%rdi), %ymm2 -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm2 = ymm2[1],mem[1],ymm2[3],mem[3] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm0, %zmm10 -; AVX512BW-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm7, %zmm7 # 64-byte Folded Reload -; AVX512BW-ONLY-NEXT: # zmm7 = zmm7[0,1,2,3],mem[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqa 64(%rdi), %ymm2 -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm2 = ymm2[1],mem[1],ymm2[3],mem[3] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm0, %zmm0 -; AVX512BW-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm6, %zmm6 # 64-byte Folded Reload -; AVX512BW-ONLY-NEXT: # zmm6 = zmm6[0,1,2,3],mem[4,5,6,7] -; AVX512BW-ONLY-NEXT: movb $16, %al -; AVX512BW-ONLY-NEXT: kmovd %eax, %k2 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm1 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm1 = <10,u,2,3,4,5,11,u> -; AVX512BW-ONLY-NEXT: vpermt2q %zmm3, %zmm1, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm2 = <14,u,2,3,4,5,15,u> -; AVX512BW-ONLY-NEXT: vpermt2q %zmm3, %zmm2, %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa 128(%rdi), %ymm3 -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm3 = ymm3[1],mem[1],ymm3[3],mem[3] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm3, %zmm0, %zmm3 -; AVX512BW-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm25, %zmm6 # 64-byte Folded Reload -; AVX512BW-ONLY-NEXT: # zmm6 = zmm25[0,1,2,3],mem[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm9, %zmm0 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm9, %zmm1, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm9, %zmm2, %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa 192(%rdi), %ymm3 -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm3 = ymm3[1],mem[1],ymm3[3],mem[3] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm3, %zmm0, %zmm0 -; AVX512BW-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm29, %zmm3 # 64-byte Folded Reload -; AVX512BW-ONLY-NEXT: # zmm3 = zmm29[0,1,2,3],mem[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm4 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm11, %zmm1, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm11, %zmm2, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa 256(%rdi), %ymm0 -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm3 -; AVX512BW-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm31, %zmm4 # 64-byte Folded Reload -; AVX512BW-ONLY-NEXT: # zmm4 = zmm31[0,1,2,3],mem[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm13, %zmm0 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm13, %zmm1, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm13, %zmm2, %zmm4 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa 320(%rdi), %ymm0 -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm27 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm25 # 64-byte Folded Reload -; AVX512BW-ONLY-NEXT: # zmm25 = zmm0[0,1,2,3],mem[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm14, %zmm8 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm14, %zmm1, %zmm27 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm14, %zmm2, %zmm25 -; AVX512BW-ONLY-NEXT: vmovdqa 384(%rdi), %ymm0 -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm22 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm20 # 64-byte Folded Reload -; AVX512BW-ONLY-NEXT: # zmm20 = zmm0[0,1,2,3],mem[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm16, %zmm0 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm16, %zmm1, %zmm22 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm16, %zmm2, %zmm20 -; AVX512BW-ONLY-NEXT: vmovdqa 448(%rdi), %ymm0 -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm18 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm5, %zmm1, %zmm10 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm11 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm12, %zmm1, %zmm18 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm17 # 64-byte Folded Reload -; AVX512BW-ONLY-NEXT: # zmm17 = zmm0[0,1,2,3],mem[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm0 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm12, %zmm2, %zmm17 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm5, %zmm2, %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm13 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm28 {%k2} -; AVX512BW-ONLY-NEXT: vmovdqa64 (%r9), %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm10 = [0,1,2,9,4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm6, %zmm10, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%r9), %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm10, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 128(%r9), %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm10, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 192(%r9), %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm3, %zmm10, %zmm4 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 256(%r9), %zmm4 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm4, %zmm10, %zmm5 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 320(%r9), %zmm5 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm5, %zmm10, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 384(%r9), %zmm8 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm8, %zmm10, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 448(%r9), %zmm9 -; AVX512BW-ONLY-NEXT: vmovdqu64 (%rsp), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm9, %zmm10, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, (%rsp) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm10 = [0,1,2,13,4,5,6,7] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm6, %zmm10, %zmm23 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm23, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm10, %zmm12 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm10, %zmm24 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm24, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm3, %zmm10, %zmm19 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm19, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm4, %zmm10, %zmm26 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm26, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm5, %zmm10, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm8, %zmm10, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm9, %zmm10, %zmm15 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm15, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa (%rdx), %xmm10 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512BW-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm12 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa 64(%rdx), %xmm10 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512BW-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm14 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm14 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa 128(%rdx), %xmm10 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512BW-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm16 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa 192(%rdx), %xmm10 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512BW-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm30 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm30 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa 256(%rdx), %xmm10 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512BW-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm31 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm31 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa 320(%rdx), %xmm10 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512BW-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm1 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa 384(%rdx), %xmm10 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512BW-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm0 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa 448(%rdx), %xmm10 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512BW-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm21 {%k1} -; AVX512BW-ONLY-NEXT: vinserti32x4 $2, (%r8), %zmm12, %zmm10 -; AVX512BW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm29 = [0,1,2,3,4,8,6,7] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm6, %zmm29, %zmm10 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vinserti32x4 $2, 64(%r8), %zmm14, %zmm10 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm29, %zmm10 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vinserti32x4 $2, 128(%r8), %zmm16, %zmm10 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm29, %zmm10 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vinserti32x4 $2, 192(%r8), %zmm30, %zmm26 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm3, %zmm29, %zmm26 -; AVX512BW-ONLY-NEXT: vinserti32x4 $2, 256(%r8), %zmm31, %zmm24 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm4, %zmm29, %zmm24 -; AVX512BW-ONLY-NEXT: vinserti32x4 $2, 320(%r8), %zmm1, %zmm23 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm5, %zmm29, %zmm23 -; AVX512BW-ONLY-NEXT: vinserti32x4 $2, 384(%r8), %zmm0, %zmm19 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm8, %zmm29, %zmm19 -; AVX512BW-ONLY-NEXT: vinserti32x4 $2, 448(%r8), %zmm21, %zmm21 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm9, %zmm29, %zmm21 -; AVX512BW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm29 = [0,10,2,3,4,5,6,11] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm6, %zmm29, %zmm11 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm30 = [0,1,2,3,4,12,6,7] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm6, %zmm30, %zmm28 -; AVX512BW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm31 = [0,14,2,3,4,5,6,15] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm6, %zmm31, %zmm13 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm29, %zmm16 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm30, %zmm15 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm14 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm31, %zmm14 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm29, %zmm13 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm30, %zmm12 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm31, %zmm11 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm10 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm3, %zmm29, %zmm10 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm3, %zmm30, %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm3, %zmm31, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm4, %zmm29, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm4, %zmm30, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm4, %zmm31, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm5, %zmm29, %zmm27 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm5, %zmm30, %zmm4 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm5, %zmm31, %zmm25 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm8, %zmm29, %zmm22 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm8, %zmm30, %zmm5 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm8, %zmm31, %zmm20 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm9, %zmm29, %zmm18 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm9, %zmm30, %zmm6 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm9, %zmm31, %zmm17 -; AVX512BW-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm17, 3008(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm8 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm8, 2944(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm6, 2880(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm18, 2816(%rax) -; AVX512BW-ONLY-NEXT: vmovups (%rsp), %zmm6 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm6, 2752(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm20, 2624(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm6, 2560(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, 2496(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm22, 2432(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm5, 2368(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm25, 2240(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm5, 2176(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, 2112(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm27, 2048(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm4, 1984(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, 1856(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 1792(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm3, 1728(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm1, 1664(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm3, 1600(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, 1472(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 1408(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, 1344(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, 1280(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm2, 1216(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm11, 1088(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 1024(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm12, 960(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm13, 896(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm1, 832(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm14, 704(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm1, 640(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm15, 576(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm16, 512(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 448(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 320(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 256(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm28, 192(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 128(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 64(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm21, 2688(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm19, 2304(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm23, 1920(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm24, 1536(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm26, 1152(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 768(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 384(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, (%rax) -; AVX512BW-ONLY-NEXT: addq $3400, %rsp # imm = 0xD48 -; AVX512BW-ONLY-NEXT: vzeroupper -; AVX512BW-ONLY-NEXT: retq +; AVX512F-LABEL: store_i64_stride6_vf64: +; AVX512F: # %bb.0: +; AVX512F-NEXT: subq $3400, %rsp # imm = 0xD48 +; AVX512F-NEXT: vmovdqa64 (%rdx), %zmm13 +; AVX512F-NEXT: vmovdqa64 64(%rdx), %zmm12 +; AVX512F-NEXT: vmovdqa64 128(%rdx), %zmm11 +; AVX512F-NEXT: vmovdqa64 192(%rdx), %zmm10 +; AVX512F-NEXT: vmovdqa64 256(%rdx), %zmm9 +; AVX512F-NEXT: vmovdqa64 320(%rdx), %zmm8 +; AVX512F-NEXT: vmovdqa64 384(%rdx), %zmm7 +; AVX512F-NEXT: vmovdqa64 448(%rdx), %zmm6 +; AVX512F-NEXT: vmovdqa64 (%rcx), %zmm0 +; AVX512F-NEXT: vmovdqa64 64(%rcx), %zmm1 +; AVX512F-NEXT: vmovdqa64 128(%rcx), %zmm2 +; AVX512F-NEXT: vmovdqa64 192(%rcx), %zmm30 +; AVX512F-NEXT: vmovdqa64 256(%rcx), %zmm27 +; AVX512F-NEXT: vmovdqa64 320(%rcx), %zmm24 +; AVX512F-NEXT: vmovdqa64 384(%rcx), %zmm22 +; AVX512F-NEXT: vmovdqa64 448(%rcx), %zmm21 +; AVX512F-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [4,12,4,12] +; AVX512F-NEXT: # ymm3 = mem[0,1,0,1] +; AVX512F-NEXT: vmovdqa64 %zmm6, %zmm4 +; AVX512F-NEXT: vpermt2q %zmm21, %zmm3, %zmm4 +; AVX512F-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm7, %zmm4 +; AVX512F-NEXT: vpermt2q %zmm22, %zmm3, %zmm4 +; AVX512F-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm8, %zmm4 +; AVX512F-NEXT: vpermt2q %zmm24, %zmm3, %zmm4 +; AVX512F-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm9, %zmm4 +; AVX512F-NEXT: vpermt2q %zmm27, %zmm3, %zmm4 +; AVX512F-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm10, %zmm4 +; AVX512F-NEXT: vpermt2q %zmm30, %zmm3, %zmm4 +; AVX512F-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm11, %zmm4 +; AVX512F-NEXT: vpermt2q %zmm2, %zmm3, %zmm4 +; AVX512F-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm12, %zmm4 +; AVX512F-NEXT: vpermt2q %zmm1, %zmm3, %zmm4 +; AVX512F-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermi2q %zmm0, %zmm13, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vbroadcasti64x4 {{.*#+}} zmm5 = [1,9,2,10,1,9,2,10] +; AVX512F-NEXT: # zmm5 = mem[0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm13, %zmm3 +; AVX512F-NEXT: vpermt2q %zmm0, %zmm5, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm5, %zmm4 +; AVX512F-NEXT: vbroadcasti64x4 {{.*#+}} zmm5 = [5,13,6,14,5,13,6,14] +; AVX512F-NEXT: # zmm5 = mem[0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm13, %zmm3 +; AVX512F-NEXT: vpermt2q %zmm0, %zmm5, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm12, %zmm3 +; AVX512F-NEXT: vpermt2q %zmm1, %zmm4, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm14 = [3,11,3,11,3,11,3,11] +; AVX512F-NEXT: # zmm14 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm13, %zmm3 +; AVX512F-NEXT: vpermt2q %zmm0, %zmm14, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm3 = [7,15,7,15,7,15,7,15] +; AVX512F-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vpermt2q %zmm0, %zmm3, %zmm13 +; AVX512F-NEXT: vmovdqu64 %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm12, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm1, %zmm5, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm12, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm1, %zmm14, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm1, %zmm3, %zmm12 +; AVX512F-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm11, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm2, %zmm4, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm11, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm2, %zmm5, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm11, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm2, %zmm14, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm2, %zmm3, %zmm11 +; AVX512F-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm10, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm30, %zmm4, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm10, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm30, %zmm5, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm10, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm30, %zmm14, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm30, %zmm3, %zmm10 +; AVX512F-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm9, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm27, %zmm4, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm9, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm27, %zmm5, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm9, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm27, %zmm14, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm27, %zmm3, %zmm9 +; AVX512F-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm8, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm24, %zmm4, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm8, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm24, %zmm5, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm8, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm24, %zmm14, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm24, %zmm3, %zmm8 +; AVX512F-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm7, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm22, %zmm4, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm7, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm22, %zmm5, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm7, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm22, %zmm14, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm22, %zmm3, %zmm7 +; AVX512F-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermi2q %zmm21, %zmm6, %zmm4 +; AVX512F-NEXT: vmovdqu64 %zmm4, (%rsp) # 64-byte Spill +; AVX512F-NEXT: vpermi2q %zmm21, %zmm6, %zmm5 +; AVX512F-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermi2q %zmm21, %zmm6, %zmm14 +; AVX512F-NEXT: vmovdqu64 %zmm14, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm21, %zmm3, %zmm6 +; AVX512F-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 448(%rdi), %zmm4 +; AVX512F-NEXT: vmovdqa64 448(%rsi), %zmm11 +; AVX512F-NEXT: vbroadcasti64x4 {{.*#+}} zmm28 = [4,12,5,13,4,12,5,13] +; AVX512F-NEXT: # zmm28 = mem[0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm11, %zmm28, %zmm0 +; AVX512F-NEXT: vmovdqa64 %zmm0, %zmm8 +; AVX512F-NEXT: vmovdqa64 384(%rdi), %zmm2 +; AVX512F-NEXT: vmovdqa64 384(%rsi), %zmm13 +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm1 +; AVX512F-NEXT: vpermt2q %zmm13, %zmm28, %zmm1 +; AVX512F-NEXT: vmovdqa64 320(%rdi), %zmm3 +; AVX512F-NEXT: vmovdqa64 320(%rsi), %zmm15 +; AVX512F-NEXT: vmovdqa64 %zmm3, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm15, %zmm28, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 256(%rdi), %zmm31 +; AVX512F-NEXT: vmovdqa64 256(%rsi), %zmm17 +; AVX512F-NEXT: vmovdqa64 %zmm31, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm17, %zmm28, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 192(%rdi), %zmm29 +; AVX512F-NEXT: vmovdqa64 192(%rsi), %zmm18 +; AVX512F-NEXT: vmovdqa64 %zmm29, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm18, %zmm28, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 128(%rdi), %zmm25 +; AVX512F-NEXT: vmovdqa64 128(%rsi), %zmm19 +; AVX512F-NEXT: vmovdqa64 %zmm25, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm19, %zmm28, %zmm0 +; AVX512F-NEXT: vmovdqa64 %zmm0, %zmm5 +; AVX512F-NEXT: vmovdqa64 64(%rdi), %zmm6 +; AVX512F-NEXT: vmovdqa64 64(%rsi), %zmm20 +; AVX512F-NEXT: vmovdqa64 %zmm6, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm20, %zmm28, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 (%rdi), %zmm7 +; AVX512F-NEXT: vmovdqa64 (%rsi), %zmm22 +; AVX512F-NEXT: vpermi2q %zmm22, %zmm7, %zmm28 +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm12 = [2,10,2,10,2,10,2,10] +; AVX512F-NEXT: # zmm12 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm7, %zmm14 +; AVX512F-NEXT: vpermt2q %zmm22, %zmm12, %zmm14 +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm10 = [6,14,6,14,6,14,6,14] +; AVX512F-NEXT: # zmm10 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm7, %zmm16 +; AVX512F-NEXT: vpermt2q %zmm22, %zmm10, %zmm16 +; AVX512F-NEXT: vbroadcasti64x4 {{.*#+}} zmm21 = [0,8,1,9,0,8,1,9] +; AVX512F-NEXT: # zmm21 = mem[0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm7, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm22, %zmm21, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} ymm23 = [7,15,7,15] +; AVX512F-NEXT: # ymm23 = mem[0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vpermt2q %zmm22, %zmm23, %zmm7 +; AVX512F-NEXT: vmovdqa64 %zmm6, %zmm22 +; AVX512F-NEXT: vpermt2q %zmm20, %zmm12, %zmm22 +; AVX512F-NEXT: vmovdqa64 %zmm6, %zmm24 +; AVX512F-NEXT: vpermt2q %zmm20, %zmm10, %zmm24 +; AVX512F-NEXT: vmovdqa64 %zmm6, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm20, %zmm21, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm20, %zmm23, %zmm6 +; AVX512F-NEXT: vmovdqa64 %zmm25, %zmm20 +; AVX512F-NEXT: vpermt2q %zmm19, %zmm12, %zmm20 +; AVX512F-NEXT: vmovdqa64 %zmm25, %zmm26 +; AVX512F-NEXT: vpermt2q %zmm19, %zmm10, %zmm26 +; AVX512F-NEXT: vmovdqa64 %zmm25, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm19, %zmm21, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm19, %zmm23, %zmm25 +; AVX512F-NEXT: vmovdqa64 %zmm29, %zmm19 +; AVX512F-NEXT: vpermt2q %zmm18, %zmm12, %zmm19 +; AVX512F-NEXT: vmovdqa64 %zmm29, %zmm27 +; AVX512F-NEXT: vpermt2q %zmm18, %zmm10, %zmm27 +; AVX512F-NEXT: vmovdqa64 %zmm29, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm18, %zmm21, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm18, %zmm23, %zmm29 +; AVX512F-NEXT: vmovdqa64 %zmm31, %zmm18 +; AVX512F-NEXT: vpermt2q %zmm17, %zmm12, %zmm18 +; AVX512F-NEXT: vmovdqa64 %zmm31, %zmm9 +; AVX512F-NEXT: vpermt2q %zmm17, %zmm10, %zmm9 +; AVX512F-NEXT: vmovdqa64 %zmm31, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm17, %zmm21, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm17, %zmm23, %zmm31 +; AVX512F-NEXT: vmovdqa64 %zmm3, %zmm17 +; AVX512F-NEXT: vpermt2q %zmm15, %zmm12, %zmm17 +; AVX512F-NEXT: vmovdqa64 %zmm3, %zmm30 +; AVX512F-NEXT: vpermt2q %zmm15, %zmm10, %zmm30 +; AVX512F-NEXT: vmovdqa64 %zmm3, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm15, %zmm21, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm15, %zmm23, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm15 +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm3 +; AVX512F-NEXT: vpermt2q %zmm13, %zmm12, %zmm3 +; AVX512F-NEXT: vpermt2q %zmm13, %zmm10, %zmm2 +; AVX512F-NEXT: vmovdqa64 %zmm15, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm13, %zmm21, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm13, %zmm23, %zmm15 +; AVX512F-NEXT: vmovdqu64 %zmm15, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermi2q %zmm11, %zmm4, %zmm12 +; AVX512F-NEXT: vpermi2q %zmm11, %zmm4, %zmm10 +; AVX512F-NEXT: vpermi2q %zmm11, %zmm4, %zmm21 +; AVX512F-NEXT: vpermt2q %zmm11, %zmm23, %zmm4 +; AVX512F-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: movb $12, %al +; AVX512F-NEXT: kmovw %eax, %k1 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm11, %zmm8 {%k1} +; AVX512F-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm11, %zmm1 {%k1} +; AVX512F-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm8 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm11, %zmm8 {%k1} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm11, %zmm0 {%k1} +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm11, %zmm4 {%k1} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm11, %zmm5 {%k1} +; AVX512F-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm11, %zmm1 {%k1} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm11, %zmm28 {%k1} +; AVX512F-NEXT: movb $48, %al +; AVX512F-NEXT: kmovw %eax, %k2 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm14, %zmm11 {%k2} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm23 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm16, %zmm23 {%k2} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm22, %zmm13 {%k2} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm22 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm24, %zmm22 {%k2} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm14 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm20, %zmm14 {%k2} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm20 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm26, %zmm20 {%k2} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm19, %zmm16 {%k2} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm27, %zmm19 {%k2} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm24 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm18, %zmm24 {%k2} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm18 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm9, %zmm18 {%k2} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm26 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm17, %zmm26 {%k2} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm17 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm30, %zmm17 {%k2} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm27 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm3, %zmm27 {%k2} +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm0 {%k2} +; AVX512F-NEXT: vmovdqu64 (%rsp), %zmm15 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm12, %zmm15 {%k2} +; AVX512F-NEXT: vmovdqa64 (%r8), %zmm5 +; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm2 = <0,1,9,u,4,5,6,7> +; AVX512F-NEXT: vpermt2q %zmm5, %zmm2, %zmm11 +; AVX512F-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 64(%r8), %zmm3 +; AVX512F-NEXT: vpermt2q %zmm3, %zmm2, %zmm13 +; AVX512F-NEXT: vmovdqu64 %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 128(%r8), %zmm9 +; AVX512F-NEXT: vpermt2q %zmm9, %zmm2, %zmm14 +; AVX512F-NEXT: vmovdqu64 %zmm14, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 192(%r8), %zmm11 +; AVX512F-NEXT: vpermt2q %zmm11, %zmm2, %zmm16 +; AVX512F-NEXT: vmovdqu64 %zmm16, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 256(%r8), %zmm13 +; AVX512F-NEXT: vpermt2q %zmm13, %zmm2, %zmm24 +; AVX512F-NEXT: vmovdqu64 %zmm24, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 320(%r8), %zmm14 +; AVX512F-NEXT: vpermt2q %zmm14, %zmm2, %zmm26 +; AVX512F-NEXT: vmovdqu64 %zmm26, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 384(%r8), %zmm16 +; AVX512F-NEXT: vpermt2q %zmm16, %zmm2, %zmm27 +; AVX512F-NEXT: vmovdqu64 %zmm27, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 448(%r8), %zmm12 +; AVX512F-NEXT: vpermt2q %zmm12, %zmm2, %zmm15 +; AVX512F-NEXT: vmovdqu64 %zmm15, (%rsp) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm10, %zmm15 {%k2} +; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm2 = <0,1,13,u,4,5,6,7> +; AVX512F-NEXT: vpermt2q %zmm5, %zmm2, %zmm23 +; AVX512F-NEXT: vpermt2q %zmm3, %zmm2, %zmm22 +; AVX512F-NEXT: vmovdqu64 %zmm22, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm9, %zmm2, %zmm20 +; AVX512F-NEXT: vmovdqa64 %zmm20, %zmm24 +; AVX512F-NEXT: vpermt2q %zmm11, %zmm2, %zmm19 +; AVX512F-NEXT: vpermt2q %zmm13, %zmm2, %zmm18 +; AVX512F-NEXT: vmovdqa64 %zmm18, %zmm26 +; AVX512F-NEXT: vpermt2q %zmm14, %zmm2, %zmm17 +; AVX512F-NEXT: vmovdqu64 %zmm17, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm16, %zmm2, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm12, %zmm2, %zmm15 +; AVX512F-NEXT: vmovdqa (%rdi), %ymm2 +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm2 = ymm2[1],mem[1],ymm2[3],mem[3] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vinserti64x4 $0, %ymm2, %zmm0, %zmm10 +; AVX512F-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm7, %zmm7 # 64-byte Folded Reload +; AVX512F-NEXT: # zmm7 = zmm7[0,1,2,3],mem[4,5,6,7] +; AVX512F-NEXT: vmovdqa 64(%rdi), %ymm2 +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm2 = ymm2[1],mem[1],ymm2[3],mem[3] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vinserti64x4 $0, %ymm2, %zmm0, %zmm0 +; AVX512F-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm6, %zmm6 # 64-byte Folded Reload +; AVX512F-NEXT: # zmm6 = zmm6[0,1,2,3],mem[4,5,6,7] +; AVX512F-NEXT: movb $16, %al +; AVX512F-NEXT: kmovw %eax, %k2 +; AVX512F-NEXT: vmovdqa64 %zmm3, %zmm1 {%k2} +; AVX512F-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm1 = <10,u,2,3,4,5,11,u> +; AVX512F-NEXT: vpermt2q %zmm3, %zmm1, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm2 = <14,u,2,3,4,5,15,u> +; AVX512F-NEXT: vpermt2q %zmm3, %zmm2, %zmm6 +; AVX512F-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa 128(%rdi), %ymm3 +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm3 = ymm3[1],mem[1],ymm3[3],mem[3] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vinserti64x4 $0, %ymm3, %zmm0, %zmm3 +; AVX512F-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm25, %zmm6 # 64-byte Folded Reload +; AVX512F-NEXT: # zmm6 = zmm25[0,1,2,3],mem[4,5,6,7] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm9, %zmm0 {%k2} +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm9, %zmm1, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm9, %zmm2, %zmm6 +; AVX512F-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa 192(%rdi), %ymm3 +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm3 = ymm3[1],mem[1],ymm3[3],mem[3] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vinserti64x4 $0, %ymm3, %zmm0, %zmm0 +; AVX512F-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm29, %zmm3 # 64-byte Folded Reload +; AVX512F-NEXT: # zmm3 = zmm29[0,1,2,3],mem[4,5,6,7] +; AVX512F-NEXT: vmovdqa64 %zmm11, %zmm4 {%k2} +; AVX512F-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm11, %zmm1, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm11, %zmm2, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa 256(%rdi), %ymm0 +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload +; AVX512F-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm3 +; AVX512F-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm31, %zmm4 # 64-byte Folded Reload +; AVX512F-NEXT: # zmm4 = zmm31[0,1,2,3],mem[4,5,6,7] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm13, %zmm0 {%k2} +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm13, %zmm1, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm13, %zmm2, %zmm4 +; AVX512F-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa 320(%rdi), %ymm0 +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload +; AVX512F-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm27 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm25 # 64-byte Folded Reload +; AVX512F-NEXT: # zmm25 = zmm0[0,1,2,3],mem[4,5,6,7] +; AVX512F-NEXT: vmovdqa64 %zmm14, %zmm8 {%k2} +; AVX512F-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm14, %zmm1, %zmm27 +; AVX512F-NEXT: vpermt2q %zmm14, %zmm2, %zmm25 +; AVX512F-NEXT: vmovdqa 384(%rdi), %ymm0 +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload +; AVX512F-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm22 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm20 # 64-byte Folded Reload +; AVX512F-NEXT: # zmm20 = zmm0[0,1,2,3],mem[4,5,6,7] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm16, %zmm0 {%k2} +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm16, %zmm1, %zmm22 +; AVX512F-NEXT: vpermt2q %zmm16, %zmm2, %zmm20 +; AVX512F-NEXT: vmovdqa 448(%rdi), %ymm0 +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload +; AVX512F-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm18 +; AVX512F-NEXT: vpermt2q %zmm5, %zmm1, %zmm10 +; AVX512F-NEXT: vmovdqa64 %zmm10, %zmm11 +; AVX512F-NEXT: vpermt2q %zmm12, %zmm1, %zmm18 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm17 # 64-byte Folded Reload +; AVX512F-NEXT: # zmm17 = zmm0[0,1,2,3],mem[4,5,6,7] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm12, %zmm0 {%k2} +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm12, %zmm2, %zmm17 +; AVX512F-NEXT: vpermt2q %zmm5, %zmm2, %zmm7 +; AVX512F-NEXT: vmovdqa64 %zmm7, %zmm13 +; AVX512F-NEXT: vmovdqa64 %zmm5, %zmm28 {%k2} +; AVX512F-NEXT: vmovdqa64 (%r9), %zmm6 +; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm10 = [0,1,2,9,4,5,6,7] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm6, %zmm10, %zmm1 +; AVX512F-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 64(%r9), %zmm7 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm7, %zmm10, %zmm2 +; AVX512F-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 128(%r9), %zmm2 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm2, %zmm10, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 192(%r9), %zmm3 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm3, %zmm10, %zmm4 +; AVX512F-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 256(%r9), %zmm4 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm4, %zmm10, %zmm5 +; AVX512F-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 320(%r9), %zmm5 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm5, %zmm10, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 384(%r9), %zmm8 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm8, %zmm10, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 448(%r9), %zmm9 +; AVX512F-NEXT: vmovdqu64 (%rsp), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm9, %zmm10, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, (%rsp) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm10 = [0,1,2,13,4,5,6,7] +; AVX512F-NEXT: vpermt2q %zmm6, %zmm10, %zmm23 +; AVX512F-NEXT: vmovdqu64 %zmm23, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm7, %zmm10, %zmm12 +; AVX512F-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm2, %zmm10, %zmm24 +; AVX512F-NEXT: vmovdqu64 %zmm24, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm3, %zmm10, %zmm19 +; AVX512F-NEXT: vmovdqu64 %zmm19, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm4, %zmm10, %zmm26 +; AVX512F-NEXT: vmovdqu64 %zmm26, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm5, %zmm10, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm8, %zmm10, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm9, %zmm10, %zmm15 +; AVX512F-NEXT: vmovdqu64 %zmm15, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa (%rdx), %xmm10 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] +; AVX512F-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload +; AVX512F-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm12 {%k1} +; AVX512F-NEXT: vmovdqa 64(%rdx), %xmm10 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] +; AVX512F-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm14 # 64-byte Reload +; AVX512F-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm14 {%k1} +; AVX512F-NEXT: vmovdqa 128(%rdx), %xmm10 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] +; AVX512F-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload +; AVX512F-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm16 {%k1} +; AVX512F-NEXT: vmovdqa 192(%rdx), %xmm10 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] +; AVX512F-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm30 # 64-byte Reload +; AVX512F-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm30 {%k1} +; AVX512F-NEXT: vmovdqa 256(%rdx), %xmm10 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] +; AVX512F-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm31 # 64-byte Reload +; AVX512F-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm31 {%k1} +; AVX512F-NEXT: vmovdqa 320(%rdx), %xmm10 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] +; AVX512F-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512F-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm1 {%k1} +; AVX512F-NEXT: vmovdqa 384(%rdx), %xmm10 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] +; AVX512F-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm0 {%k1} +; AVX512F-NEXT: vmovdqa 448(%rdx), %xmm10 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] +; AVX512F-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 +; AVX512F-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm21 {%k1} +; AVX512F-NEXT: vinserti32x4 $2, (%r8), %zmm12, %zmm10 +; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm29 = [0,1,2,3,4,8,6,7] +; AVX512F-NEXT: vpermt2q %zmm6, %zmm29, %zmm10 +; AVX512F-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vinserti32x4 $2, 64(%r8), %zmm14, %zmm10 +; AVX512F-NEXT: vpermt2q %zmm7, %zmm29, %zmm10 +; AVX512F-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vinserti32x4 $2, 128(%r8), %zmm16, %zmm10 +; AVX512F-NEXT: vpermt2q %zmm2, %zmm29, %zmm10 +; AVX512F-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vinserti32x4 $2, 192(%r8), %zmm30, %zmm26 +; AVX512F-NEXT: vpermt2q %zmm3, %zmm29, %zmm26 +; AVX512F-NEXT: vinserti32x4 $2, 256(%r8), %zmm31, %zmm24 +; AVX512F-NEXT: vpermt2q %zmm4, %zmm29, %zmm24 +; AVX512F-NEXT: vinserti32x4 $2, 320(%r8), %zmm1, %zmm23 +; AVX512F-NEXT: vpermt2q %zmm5, %zmm29, %zmm23 +; AVX512F-NEXT: vinserti32x4 $2, 384(%r8), %zmm0, %zmm19 +; AVX512F-NEXT: vpermt2q %zmm8, %zmm29, %zmm19 +; AVX512F-NEXT: vinserti32x4 $2, 448(%r8), %zmm21, %zmm21 +; AVX512F-NEXT: vpermt2q %zmm9, %zmm29, %zmm21 +; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm29 = [0,10,2,3,4,5,6,11] +; AVX512F-NEXT: vpermt2q %zmm6, %zmm29, %zmm11 +; AVX512F-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm30 = [0,1,2,3,4,12,6,7] +; AVX512F-NEXT: vpermt2q %zmm6, %zmm30, %zmm28 +; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm31 = [0,14,2,3,4,5,6,15] +; AVX512F-NEXT: vpermt2q %zmm6, %zmm31, %zmm13 +; AVX512F-NEXT: vmovdqu64 %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm7, %zmm29, %zmm16 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm7, %zmm30, %zmm15 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm14 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm7, %zmm31, %zmm14 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm2, %zmm29, %zmm13 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm2, %zmm30, %zmm12 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm2, %zmm31, %zmm11 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm10 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm3, %zmm29, %zmm10 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm3, %zmm30, %zmm7 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm3, %zmm31, %zmm2 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm4, %zmm29, %zmm1 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm4, %zmm30, %zmm3 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm4, %zmm31, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm5, %zmm29, %zmm27 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm5, %zmm30, %zmm4 +; AVX512F-NEXT: vpermt2q %zmm5, %zmm31, %zmm25 +; AVX512F-NEXT: vpermt2q %zmm8, %zmm29, %zmm22 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm8, %zmm30, %zmm5 +; AVX512F-NEXT: vpermt2q %zmm8, %zmm31, %zmm20 +; AVX512F-NEXT: vpermt2q %zmm9, %zmm29, %zmm18 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm9, %zmm30, %zmm6 +; AVX512F-NEXT: vpermt2q %zmm9, %zmm31, %zmm17 +; AVX512F-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512F-NEXT: vmovdqa64 %zmm17, 3008(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm8 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm8, 2944(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm6, 2880(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm18, 2816(%rax) +; AVX512F-NEXT: vmovups (%rsp), %zmm6 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm6, 2752(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm20, 2624(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm6, 2560(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm5, 2496(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm22, 2432(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm5, 2368(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm25, 2240(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm5, 2176(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm4, 2112(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm27, 2048(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm4, 1984(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm0, 1856(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 1792(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm3, 1728(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm1, 1664(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm3, 1600(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm2, 1472(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 1408(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm7, 1344(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm10, 1280(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm2, 1216(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm11, 1088(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 1024(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm12, 960(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm13, 896(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm1, 832(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm14, 704(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm1, 640(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm15, 576(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm16, 512(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 448(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 320(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 256(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm28, 192(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 128(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 64(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm21, 2688(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm19, 2304(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm23, 1920(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm24, 1536(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm26, 1152(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 768(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 384(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, (%rax) +; AVX512F-NEXT: addq $3400, %rsp # imm = 0xD48 +; AVX512F-NEXT: vzeroupper +; AVX512F-NEXT: retq ; -; AVX512DQBW-ONLY-LABEL: store_i64_stride6_vf64: -; AVX512DQBW-ONLY: # %bb.0: -; AVX512DQBW-ONLY-NEXT: subq $3400, %rsp # imm = 0xD48 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 (%rdx), %zmm13 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%rdx), %zmm12 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 128(%rdx), %zmm11 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 192(%rdx), %zmm10 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 256(%rdx), %zmm9 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 320(%rdx), %zmm8 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 384(%rdx), %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 448(%rdx), %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 (%rcx), %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%rcx), %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 128(%rcx), %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 192(%rcx), %zmm30 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 256(%rcx), %zmm27 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 320(%rcx), %zmm24 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 384(%rcx), %zmm22 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 448(%rcx), %zmm21 -; AVX512DQBW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [4,12,4,12] -; AVX512DQBW-ONLY-NEXT: # ymm3 = mem[0,1,0,1] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm4 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm21, %zmm3, %zmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm4 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm3, %zmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm8, %zmm4 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm24, %zmm3, %zmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm9, %zmm4 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm27, %zmm3, %zmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm4 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm30, %zmm3, %zmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm4 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm3, %zmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm4 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm1, %zmm3, %zmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm0, %zmm13, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm5 = [1,9,2,10,1,9,2,10] -; AVX512DQBW-ONLY-NEXT: # zmm5 = mem[0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm13, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm0, %zmm5, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm4 -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm5 = [5,13,6,14,5,13,6,14] -; AVX512DQBW-ONLY-NEXT: # zmm5 = mem[0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm13, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm0, %zmm5, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm1, %zmm4, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm14 = [3,11,3,11,3,11,3,11] -; AVX512DQBW-ONLY-NEXT: # zmm14 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm13, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm0, %zmm14, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm3 = [7,15,7,15,7,15,7,15] -; AVX512DQBW-ONLY-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm0, %zmm3, %zmm13 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm1, %zmm5, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm1, %zmm14, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm1, %zmm3, %zmm12 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm4, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm5, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm14, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm3, %zmm11 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm30, %zmm4, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm30, %zmm5, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm30, %zmm14, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm30, %zmm3, %zmm10 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm9, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm27, %zmm4, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm9, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm27, %zmm5, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm9, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm27, %zmm14, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm27, %zmm3, %zmm9 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm24, %zmm4, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm24, %zmm5, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm24, %zmm14, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm24, %zmm3, %zmm8 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm4, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm5, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm14, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm3, %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm21, %zmm6, %zmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm4, (%rsp) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm21, %zmm6, %zmm5 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm21, %zmm6, %zmm14 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm14, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm21, %zmm3, %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 448(%rdi), %zmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 448(%rsi), %zmm11 -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm28 = [4,12,5,13,4,12,5,13] -; AVX512DQBW-ONLY-NEXT: # zmm28 = mem[0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm11, %zmm28, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm8 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 384(%rdi), %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 384(%rsi), %zmm13 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm13, %zmm28, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 320(%rdi), %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 320(%rsi), %zmm15 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm15, %zmm28, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 256(%rdi), %zmm31 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 256(%rsi), %zmm17 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm31, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm17, %zmm28, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 192(%rdi), %zmm29 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 192(%rsi), %zmm18 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm18, %zmm28, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 128(%rdi), %zmm25 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 128(%rsi), %zmm19 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm19, %zmm28, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm5 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%rdi), %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%rsi), %zmm20 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm20, %zmm28, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 (%rdi), %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 (%rsi), %zmm22 -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm22, %zmm7, %zmm28 -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm12 = [2,10,2,10,2,10,2,10] -; AVX512DQBW-ONLY-NEXT: # zmm12 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm14 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm12, %zmm14 -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm10 = [6,14,6,14,6,14,6,14] -; AVX512DQBW-ONLY-NEXT: # zmm10 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm16 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm10, %zmm16 -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x4 {{.*#+}} zmm21 = [0,8,1,9,0,8,1,9] -; AVX512DQBW-ONLY-NEXT: # zmm21 = mem[0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm21, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x2 {{.*#+}} ymm23 = [7,15,7,15] -; AVX512DQBW-ONLY-NEXT: # ymm23 = mem[0,1,0,1] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm23, %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm22 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm20, %zmm12, %zmm22 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm24 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm20, %zmm10, %zmm24 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm20, %zmm21, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm20, %zmm23, %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm20 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm19, %zmm12, %zmm20 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm26 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm19, %zmm10, %zmm26 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm19, %zmm21, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm19, %zmm23, %zmm25 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm19 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm18, %zmm12, %zmm19 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm27 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm18, %zmm10, %zmm27 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm18, %zmm21, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm18, %zmm23, %zmm29 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm31, %zmm18 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm17, %zmm12, %zmm18 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm31, %zmm9 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm17, %zmm10, %zmm9 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm31, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm17, %zmm21, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm17, %zmm23, %zmm31 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm17 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm15, %zmm12, %zmm17 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm30 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm15, %zmm10, %zmm30 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm15, %zmm21, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm15, %zmm23, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm15 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm13, %zmm12, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm13, %zmm10, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm15, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm13, %zmm21, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm13, %zmm23, %zmm15 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm15, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm11, %zmm4, %zmm12 -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm11, %zmm4, %zmm10 -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm11, %zmm4, %zmm21 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm11, %zmm23, %zmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: movb $12, %al -; AVX512DQBW-ONLY-NEXT: kmovd %eax, %k1 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm8 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm1 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm8 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm8 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm0 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm4 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm5 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm1 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm28 {%k1} -; AVX512DQBW-ONLY-NEXT: movb $48, %al -; AVX512DQBW-ONLY-NEXT: kmovd %eax, %k2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm14, %zmm11 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm23 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm16, %zmm23 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm22, %zmm13 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm22 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm24, %zmm22 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm14 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm20, %zmm14 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm20 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm26, %zmm20 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm19, %zmm16 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm27, %zmm19 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm24 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm18, %zmm24 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm18 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm9, %zmm18 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm26 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm17, %zmm26 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm17 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm30, %zmm17 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm27 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm27 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm0 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 (%rsp), %zmm15 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm15 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 (%r8), %zmm5 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm2 = <0,1,9,u,4,5,6,7> -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm5, %zmm2, %zmm11 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%r8), %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm3, %zmm2, %zmm13 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 128(%r8), %zmm9 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm9, %zmm2, %zmm14 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm14, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 192(%r8), %zmm11 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm11, %zmm2, %zmm16 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm16, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 256(%r8), %zmm13 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm13, %zmm2, %zmm24 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm24, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 320(%r8), %zmm14 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm14, %zmm2, %zmm26 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm26, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 384(%r8), %zmm16 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm16, %zmm2, %zmm27 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm27, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 448(%r8), %zmm12 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm12, %zmm2, %zmm15 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm15, (%rsp) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm15 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm2 = <0,1,13,u,4,5,6,7> -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm5, %zmm2, %zmm23 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm3, %zmm2, %zmm22 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm22, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm9, %zmm2, %zmm20 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm20, %zmm24 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm11, %zmm2, %zmm19 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm13, %zmm2, %zmm18 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm18, %zmm26 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm14, %zmm2, %zmm17 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm17, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm16, %zmm2, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm12, %zmm2, %zmm15 -; AVX512DQBW-ONLY-NEXT: vmovdqa (%rdi), %ymm2 -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm2 = ymm2[1],mem[1],ymm2[3],mem[3] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm0, %zmm10 -; AVX512DQBW-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm7, %zmm7 # 64-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # zmm7 = zmm7[0,1,2,3],mem[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqa 64(%rdi), %ymm2 -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm2 = ymm2[1],mem[1],ymm2[3],mem[3] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm0, %zmm0 -; AVX512DQBW-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm6, %zmm6 # 64-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # zmm6 = zmm6[0,1,2,3],mem[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: movb $16, %al -; AVX512DQBW-ONLY-NEXT: kmovd %eax, %k2 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm1 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm1 = <10,u,2,3,4,5,11,u> -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm3, %zmm1, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm2 = <14,u,2,3,4,5,15,u> -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm3, %zmm2, %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa 128(%rdi), %ymm3 -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm3 = ymm3[1],mem[1],ymm3[3],mem[3] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm3, %zmm0, %zmm3 -; AVX512DQBW-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm25, %zmm6 # 64-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # zmm6 = zmm25[0,1,2,3],mem[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm9, %zmm0 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm9, %zmm1, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm9, %zmm2, %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa 192(%rdi), %ymm3 -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm3 = ymm3[1],mem[1],ymm3[3],mem[3] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm3, %zmm0, %zmm0 -; AVX512DQBW-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm29, %zmm3 # 64-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # zmm3 = zmm29[0,1,2,3],mem[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm4 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm11, %zmm1, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm11, %zmm2, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa 256(%rdi), %ymm0 -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm3 -; AVX512DQBW-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm31, %zmm4 # 64-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # zmm4 = zmm31[0,1,2,3],mem[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm13, %zmm0 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm13, %zmm1, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm13, %zmm2, %zmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa 320(%rdi), %ymm0 -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm27 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm25 # 64-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # zmm25 = zmm0[0,1,2,3],mem[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm14, %zmm8 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm14, %zmm1, %zmm27 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm14, %zmm2, %zmm25 -; AVX512DQBW-ONLY-NEXT: vmovdqa 384(%rdi), %ymm0 -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm22 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm20 # 64-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # zmm20 = zmm0[0,1,2,3],mem[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm16, %zmm0 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm16, %zmm1, %zmm22 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm16, %zmm2, %zmm20 -; AVX512DQBW-ONLY-NEXT: vmovdqa 448(%rdi), %ymm0 -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm18 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm5, %zmm1, %zmm10 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm11 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm12, %zmm1, %zmm18 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm17 # 64-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # zmm17 = zmm0[0,1,2,3],mem[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm0 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm12, %zmm2, %zmm17 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm5, %zmm2, %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm13 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm28 {%k2} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 (%r9), %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm10 = [0,1,2,9,4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm6, %zmm10, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%r9), %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm10, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 128(%r9), %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm10, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 192(%r9), %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm3, %zmm10, %zmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 256(%r9), %zmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm4, %zmm10, %zmm5 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 320(%r9), %zmm5 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm5, %zmm10, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 384(%r9), %zmm8 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm8, %zmm10, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 448(%r9), %zmm9 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 (%rsp), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm9, %zmm10, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, (%rsp) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm10 = [0,1,2,13,4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm6, %zmm10, %zmm23 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm23, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm10, %zmm12 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm10, %zmm24 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm24, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm3, %zmm10, %zmm19 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm19, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm4, %zmm10, %zmm26 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm26, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm5, %zmm10, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm8, %zmm10, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm9, %zmm10, %zmm15 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm15, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa (%rdx), %xmm10 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm12 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa 64(%rdx), %xmm10 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm14 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm14 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa 128(%rdx), %xmm10 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm16 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa 192(%rdx), %xmm10 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm30 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm30 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa 256(%rdx), %xmm10 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm31 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm31 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa 320(%rdx), %xmm10 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm1 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa 384(%rdx), %xmm10 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm0 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa 448(%rdx), %xmm10 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm21 {%k1} -; AVX512DQBW-ONLY-NEXT: vinserti32x4 $2, (%r8), %zmm12, %zmm10 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm29 = [0,1,2,3,4,8,6,7] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm6, %zmm29, %zmm10 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vinserti32x4 $2, 64(%r8), %zmm14, %zmm10 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm29, %zmm10 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vinserti32x4 $2, 128(%r8), %zmm16, %zmm10 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm29, %zmm10 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vinserti32x4 $2, 192(%r8), %zmm30, %zmm26 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm3, %zmm29, %zmm26 -; AVX512DQBW-ONLY-NEXT: vinserti32x4 $2, 256(%r8), %zmm31, %zmm24 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm4, %zmm29, %zmm24 -; AVX512DQBW-ONLY-NEXT: vinserti32x4 $2, 320(%r8), %zmm1, %zmm23 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm5, %zmm29, %zmm23 -; AVX512DQBW-ONLY-NEXT: vinserti32x4 $2, 384(%r8), %zmm0, %zmm19 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm8, %zmm29, %zmm19 -; AVX512DQBW-ONLY-NEXT: vinserti32x4 $2, 448(%r8), %zmm21, %zmm21 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm9, %zmm29, %zmm21 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm29 = [0,10,2,3,4,5,6,11] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm6, %zmm29, %zmm11 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm30 = [0,1,2,3,4,12,6,7] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm6, %zmm30, %zmm28 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 {{.*#+}} zmm31 = [0,14,2,3,4,5,6,15] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm6, %zmm31, %zmm13 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm29, %zmm16 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm30, %zmm15 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm14 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm31, %zmm14 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm29, %zmm13 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm30, %zmm12 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm31, %zmm11 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm10 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm3, %zmm29, %zmm10 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm3, %zmm30, %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm3, %zmm31, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm4, %zmm29, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm4, %zmm30, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm4, %zmm31, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm5, %zmm29, %zmm27 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm5, %zmm30, %zmm4 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm5, %zmm31, %zmm25 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm8, %zmm29, %zmm22 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm8, %zmm30, %zmm5 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm8, %zmm31, %zmm20 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm9, %zmm29, %zmm18 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm9, %zmm30, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm9, %zmm31, %zmm17 -; AVX512DQBW-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm17, 3008(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm8 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm8, 2944(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm6, 2880(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm18, 2816(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups (%rsp), %zmm6 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm6, 2752(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm20, 2624(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm6, 2560(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, 2496(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm22, 2432(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm5, 2368(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm25, 2240(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm5, 2176(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, 2112(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm27, 2048(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm4, 1984(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, 1856(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 1792(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm3, 1728(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm1, 1664(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm3, 1600(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, 1472(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 1408(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, 1344(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, 1280(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm2, 1216(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm11, 1088(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 1024(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm12, 960(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm13, 896(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm1, 832(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm14, 704(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm1, 640(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm15, 576(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm16, 512(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 448(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 320(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 256(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm28, 192(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 128(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 64(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm21, 2688(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm19, 2304(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm23, 1920(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm24, 1536(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm26, 1152(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 768(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 384(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, (%rax) -; AVX512DQBW-ONLY-NEXT: addq $3400, %rsp # imm = 0xD48 -; AVX512DQBW-ONLY-NEXT: vzeroupper -; AVX512DQBW-ONLY-NEXT: retq +; AVX512BW-LABEL: store_i64_stride6_vf64: +; AVX512BW: # %bb.0: +; AVX512BW-NEXT: subq $3400, %rsp # imm = 0xD48 +; AVX512BW-NEXT: vmovdqa64 (%rdx), %zmm13 +; AVX512BW-NEXT: vmovdqa64 64(%rdx), %zmm12 +; AVX512BW-NEXT: vmovdqa64 128(%rdx), %zmm11 +; AVX512BW-NEXT: vmovdqa64 192(%rdx), %zmm10 +; AVX512BW-NEXT: vmovdqa64 256(%rdx), %zmm9 +; AVX512BW-NEXT: vmovdqa64 320(%rdx), %zmm8 +; AVX512BW-NEXT: vmovdqa64 384(%rdx), %zmm7 +; AVX512BW-NEXT: vmovdqa64 448(%rdx), %zmm6 +; AVX512BW-NEXT: vmovdqa64 (%rcx), %zmm0 +; AVX512BW-NEXT: vmovdqa64 64(%rcx), %zmm1 +; AVX512BW-NEXT: vmovdqa64 128(%rcx), %zmm2 +; AVX512BW-NEXT: vmovdqa64 192(%rcx), %zmm30 +; AVX512BW-NEXT: vmovdqa64 256(%rcx), %zmm27 +; AVX512BW-NEXT: vmovdqa64 320(%rcx), %zmm24 +; AVX512BW-NEXT: vmovdqa64 384(%rcx), %zmm22 +; AVX512BW-NEXT: vmovdqa64 448(%rcx), %zmm21 +; AVX512BW-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [4,12,4,12] +; AVX512BW-NEXT: # ymm3 = mem[0,1,0,1] +; AVX512BW-NEXT: vmovdqa64 %zmm6, %zmm4 +; AVX512BW-NEXT: vpermt2q %zmm21, %zmm3, %zmm4 +; AVX512BW-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm4 +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm3, %zmm4 +; AVX512BW-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm8, %zmm4 +; AVX512BW-NEXT: vpermt2q %zmm24, %zmm3, %zmm4 +; AVX512BW-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm9, %zmm4 +; AVX512BW-NEXT: vpermt2q %zmm27, %zmm3, %zmm4 +; AVX512BW-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm10, %zmm4 +; AVX512BW-NEXT: vpermt2q %zmm30, %zmm3, %zmm4 +; AVX512BW-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm11, %zmm4 +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm3, %zmm4 +; AVX512BW-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm12, %zmm4 +; AVX512BW-NEXT: vpermt2q %zmm1, %zmm3, %zmm4 +; AVX512BW-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermi2q %zmm0, %zmm13, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti64x4 {{.*#+}} zmm5 = [1,9,2,10,1,9,2,10] +; AVX512BW-NEXT: # zmm5 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm13, %zmm3 +; AVX512BW-NEXT: vpermt2q %zmm0, %zmm5, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm4 +; AVX512BW-NEXT: vbroadcasti64x4 {{.*#+}} zmm5 = [5,13,6,14,5,13,6,14] +; AVX512BW-NEXT: # zmm5 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm13, %zmm3 +; AVX512BW-NEXT: vpermt2q %zmm0, %zmm5, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm12, %zmm3 +; AVX512BW-NEXT: vpermt2q %zmm1, %zmm4, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm14 = [3,11,3,11,3,11,3,11] +; AVX512BW-NEXT: # zmm14 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm13, %zmm3 +; AVX512BW-NEXT: vpermt2q %zmm0, %zmm14, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm3 = [7,15,7,15,7,15,7,15] +; AVX512BW-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vpermt2q %zmm0, %zmm3, %zmm13 +; AVX512BW-NEXT: vmovdqu64 %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm12, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm1, %zmm5, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm12, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm1, %zmm14, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm1, %zmm3, %zmm12 +; AVX512BW-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm11, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm4, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm11, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm5, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm11, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm14, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm3, %zmm11 +; AVX512BW-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm10, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm30, %zmm4, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm10, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm30, %zmm5, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm10, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm30, %zmm14, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm30, %zmm3, %zmm10 +; AVX512BW-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm9, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm27, %zmm4, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm9, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm27, %zmm5, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm9, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm27, %zmm14, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm27, %zmm3, %zmm9 +; AVX512BW-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm8, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm24, %zmm4, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm8, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm24, %zmm5, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm8, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm24, %zmm14, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm24, %zmm3, %zmm8 +; AVX512BW-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm4, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm5, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm14, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm3, %zmm7 +; AVX512BW-NEXT: vmovdqu64 %zmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermi2q %zmm21, %zmm6, %zmm4 +; AVX512BW-NEXT: vmovdqu64 %zmm4, (%rsp) # 64-byte Spill +; AVX512BW-NEXT: vpermi2q %zmm21, %zmm6, %zmm5 +; AVX512BW-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermi2q %zmm21, %zmm6, %zmm14 +; AVX512BW-NEXT: vmovdqu64 %zmm14, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm21, %zmm3, %zmm6 +; AVX512BW-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 448(%rdi), %zmm4 +; AVX512BW-NEXT: vmovdqa64 448(%rsi), %zmm11 +; AVX512BW-NEXT: vbroadcasti64x4 {{.*#+}} zmm28 = [4,12,5,13,4,12,5,13] +; AVX512BW-NEXT: # zmm28 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm4, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm11, %zmm28, %zmm0 +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm8 +; AVX512BW-NEXT: vmovdqa64 384(%rdi), %zmm2 +; AVX512BW-NEXT: vmovdqa64 384(%rsi), %zmm13 +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm1 +; AVX512BW-NEXT: vpermt2q %zmm13, %zmm28, %zmm1 +; AVX512BW-NEXT: vmovdqa64 320(%rdi), %zmm3 +; AVX512BW-NEXT: vmovdqa64 320(%rsi), %zmm15 +; AVX512BW-NEXT: vmovdqa64 %zmm3, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm15, %zmm28, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 256(%rdi), %zmm31 +; AVX512BW-NEXT: vmovdqa64 256(%rsi), %zmm17 +; AVX512BW-NEXT: vmovdqa64 %zmm31, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm17, %zmm28, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 192(%rdi), %zmm29 +; AVX512BW-NEXT: vmovdqa64 192(%rsi), %zmm18 +; AVX512BW-NEXT: vmovdqa64 %zmm29, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm18, %zmm28, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 128(%rdi), %zmm25 +; AVX512BW-NEXT: vmovdqa64 128(%rsi), %zmm19 +; AVX512BW-NEXT: vmovdqa64 %zmm25, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm19, %zmm28, %zmm0 +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm5 +; AVX512BW-NEXT: vmovdqa64 64(%rdi), %zmm6 +; AVX512BW-NEXT: vmovdqa64 64(%rsi), %zmm20 +; AVX512BW-NEXT: vmovdqa64 %zmm6, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm20, %zmm28, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 (%rdi), %zmm7 +; AVX512BW-NEXT: vmovdqa64 (%rsi), %zmm22 +; AVX512BW-NEXT: vpermi2q %zmm22, %zmm7, %zmm28 +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm12 = [2,10,2,10,2,10,2,10] +; AVX512BW-NEXT: # zmm12 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm14 +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm12, %zmm14 +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm10 = [6,14,6,14,6,14,6,14] +; AVX512BW-NEXT: # zmm10 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm16 +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm10, %zmm16 +; AVX512BW-NEXT: vbroadcasti64x4 {{.*#+}} zmm21 = [0,8,1,9,0,8,1,9] +; AVX512BW-NEXT: # zmm21 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm21, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} ymm23 = [7,15,7,15] +; AVX512BW-NEXT: # ymm23 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm23, %zmm7 +; AVX512BW-NEXT: vmovdqa64 %zmm6, %zmm22 +; AVX512BW-NEXT: vpermt2q %zmm20, %zmm12, %zmm22 +; AVX512BW-NEXT: vmovdqa64 %zmm6, %zmm24 +; AVX512BW-NEXT: vpermt2q %zmm20, %zmm10, %zmm24 +; AVX512BW-NEXT: vmovdqa64 %zmm6, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm20, %zmm21, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm20, %zmm23, %zmm6 +; AVX512BW-NEXT: vmovdqa64 %zmm25, %zmm20 +; AVX512BW-NEXT: vpermt2q %zmm19, %zmm12, %zmm20 +; AVX512BW-NEXT: vmovdqa64 %zmm25, %zmm26 +; AVX512BW-NEXT: vpermt2q %zmm19, %zmm10, %zmm26 +; AVX512BW-NEXT: vmovdqa64 %zmm25, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm19, %zmm21, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm19, %zmm23, %zmm25 +; AVX512BW-NEXT: vmovdqa64 %zmm29, %zmm19 +; AVX512BW-NEXT: vpermt2q %zmm18, %zmm12, %zmm19 +; AVX512BW-NEXT: vmovdqa64 %zmm29, %zmm27 +; AVX512BW-NEXT: vpermt2q %zmm18, %zmm10, %zmm27 +; AVX512BW-NEXT: vmovdqa64 %zmm29, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm18, %zmm21, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm18, %zmm23, %zmm29 +; AVX512BW-NEXT: vmovdqa64 %zmm31, %zmm18 +; AVX512BW-NEXT: vpermt2q %zmm17, %zmm12, %zmm18 +; AVX512BW-NEXT: vmovdqa64 %zmm31, %zmm9 +; AVX512BW-NEXT: vpermt2q %zmm17, %zmm10, %zmm9 +; AVX512BW-NEXT: vmovdqa64 %zmm31, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm17, %zmm21, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm17, %zmm23, %zmm31 +; AVX512BW-NEXT: vmovdqa64 %zmm3, %zmm17 +; AVX512BW-NEXT: vpermt2q %zmm15, %zmm12, %zmm17 +; AVX512BW-NEXT: vmovdqa64 %zmm3, %zmm30 +; AVX512BW-NEXT: vpermt2q %zmm15, %zmm10, %zmm30 +; AVX512BW-NEXT: vmovdqa64 %zmm3, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm15, %zmm21, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm15, %zmm23, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm15 +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm3 +; AVX512BW-NEXT: vpermt2q %zmm13, %zmm12, %zmm3 +; AVX512BW-NEXT: vpermt2q %zmm13, %zmm10, %zmm2 +; AVX512BW-NEXT: vmovdqa64 %zmm15, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm13, %zmm21, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm13, %zmm23, %zmm15 +; AVX512BW-NEXT: vmovdqu64 %zmm15, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermi2q %zmm11, %zmm4, %zmm12 +; AVX512BW-NEXT: vpermi2q %zmm11, %zmm4, %zmm10 +; AVX512BW-NEXT: vpermi2q %zmm11, %zmm4, %zmm21 +; AVX512BW-NEXT: vpermt2q %zmm11, %zmm23, %zmm4 +; AVX512BW-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: movb $12, %al +; AVX512BW-NEXT: kmovd %eax, %k1 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm11, %zmm8 {%k1} +; AVX512BW-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm11, %zmm1 {%k1} +; AVX512BW-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm8 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm11, %zmm8 {%k1} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm11, %zmm0 {%k1} +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm11, %zmm4 {%k1} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm11, %zmm5 {%k1} +; AVX512BW-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm11, %zmm1 {%k1} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm11, %zmm28 {%k1} +; AVX512BW-NEXT: movb $48, %al +; AVX512BW-NEXT: kmovd %eax, %k2 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm14, %zmm11 {%k2} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm23 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm16, %zmm23 {%k2} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm22, %zmm13 {%k2} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm22 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm24, %zmm22 {%k2} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm14 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm20, %zmm14 {%k2} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm20 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm26, %zmm20 {%k2} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm19, %zmm16 {%k2} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm19 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm27, %zmm19 {%k2} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm24 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm18, %zmm24 {%k2} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm18 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm9, %zmm18 {%k2} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm26 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm17, %zmm26 {%k2} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm17 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm30, %zmm17 {%k2} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm27 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm3, %zmm27 {%k2} +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm0 {%k2} +; AVX512BW-NEXT: vmovdqu64 (%rsp), %zmm15 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm12, %zmm15 {%k2} +; AVX512BW-NEXT: vmovdqa64 (%r8), %zmm5 +; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm2 = <0,1,9,u,4,5,6,7> +; AVX512BW-NEXT: vpermt2q %zmm5, %zmm2, %zmm11 +; AVX512BW-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 64(%r8), %zmm3 +; AVX512BW-NEXT: vpermt2q %zmm3, %zmm2, %zmm13 +; AVX512BW-NEXT: vmovdqu64 %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 128(%r8), %zmm9 +; AVX512BW-NEXT: vpermt2q %zmm9, %zmm2, %zmm14 +; AVX512BW-NEXT: vmovdqu64 %zmm14, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 192(%r8), %zmm11 +; AVX512BW-NEXT: vpermt2q %zmm11, %zmm2, %zmm16 +; AVX512BW-NEXT: vmovdqu64 %zmm16, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 256(%r8), %zmm13 +; AVX512BW-NEXT: vpermt2q %zmm13, %zmm2, %zmm24 +; AVX512BW-NEXT: vmovdqu64 %zmm24, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 320(%r8), %zmm14 +; AVX512BW-NEXT: vpermt2q %zmm14, %zmm2, %zmm26 +; AVX512BW-NEXT: vmovdqu64 %zmm26, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 384(%r8), %zmm16 +; AVX512BW-NEXT: vpermt2q %zmm16, %zmm2, %zmm27 +; AVX512BW-NEXT: vmovdqu64 %zmm27, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 448(%r8), %zmm12 +; AVX512BW-NEXT: vpermt2q %zmm12, %zmm2, %zmm15 +; AVX512BW-NEXT: vmovdqu64 %zmm15, (%rsp) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm10, %zmm15 {%k2} +; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm2 = <0,1,13,u,4,5,6,7> +; AVX512BW-NEXT: vpermt2q %zmm5, %zmm2, %zmm23 +; AVX512BW-NEXT: vpermt2q %zmm3, %zmm2, %zmm22 +; AVX512BW-NEXT: vmovdqu64 %zmm22, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm9, %zmm2, %zmm20 +; AVX512BW-NEXT: vmovdqa64 %zmm20, %zmm24 +; AVX512BW-NEXT: vpermt2q %zmm11, %zmm2, %zmm19 +; AVX512BW-NEXT: vpermt2q %zmm13, %zmm2, %zmm18 +; AVX512BW-NEXT: vmovdqa64 %zmm18, %zmm26 +; AVX512BW-NEXT: vpermt2q %zmm14, %zmm2, %zmm17 +; AVX512BW-NEXT: vmovdqu64 %zmm17, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm16, %zmm2, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm12, %zmm2, %zmm15 +; AVX512BW-NEXT: vmovdqa (%rdi), %ymm2 +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm2 = ymm2[1],mem[1],ymm2[3],mem[3] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vinserti64x4 $0, %ymm2, %zmm0, %zmm10 +; AVX512BW-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm7, %zmm7 # 64-byte Folded Reload +; AVX512BW-NEXT: # zmm7 = zmm7[0,1,2,3],mem[4,5,6,7] +; AVX512BW-NEXT: vmovdqa 64(%rdi), %ymm2 +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm2 = ymm2[1],mem[1],ymm2[3],mem[3] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vinserti64x4 $0, %ymm2, %zmm0, %zmm0 +; AVX512BW-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm6, %zmm6 # 64-byte Folded Reload +; AVX512BW-NEXT: # zmm6 = zmm6[0,1,2,3],mem[4,5,6,7] +; AVX512BW-NEXT: movb $16, %al +; AVX512BW-NEXT: kmovd %eax, %k2 +; AVX512BW-NEXT: vmovdqa64 %zmm3, %zmm1 {%k2} +; AVX512BW-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm1 = <10,u,2,3,4,5,11,u> +; AVX512BW-NEXT: vpermt2q %zmm3, %zmm1, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm2 = <14,u,2,3,4,5,15,u> +; AVX512BW-NEXT: vpermt2q %zmm3, %zmm2, %zmm6 +; AVX512BW-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa 128(%rdi), %ymm3 +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm3 = ymm3[1],mem[1],ymm3[3],mem[3] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vinserti64x4 $0, %ymm3, %zmm0, %zmm3 +; AVX512BW-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm25, %zmm6 # 64-byte Folded Reload +; AVX512BW-NEXT: # zmm6 = zmm25[0,1,2,3],mem[4,5,6,7] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm9, %zmm0 {%k2} +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm9, %zmm1, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm9, %zmm2, %zmm6 +; AVX512BW-NEXT: vmovdqu64 %zmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa 192(%rdi), %ymm3 +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm3 = ymm3[1],mem[1],ymm3[3],mem[3] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vinserti64x4 $0, %ymm3, %zmm0, %zmm0 +; AVX512BW-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm29, %zmm3 # 64-byte Folded Reload +; AVX512BW-NEXT: # zmm3 = zmm29[0,1,2,3],mem[4,5,6,7] +; AVX512BW-NEXT: vmovdqa64 %zmm11, %zmm4 {%k2} +; AVX512BW-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm11, %zmm1, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm11, %zmm2, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa 256(%rdi), %ymm0 +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm3 +; AVX512BW-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm31, %zmm4 # 64-byte Folded Reload +; AVX512BW-NEXT: # zmm4 = zmm31[0,1,2,3],mem[4,5,6,7] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm13, %zmm0 {%k2} +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm13, %zmm1, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm13, %zmm2, %zmm4 +; AVX512BW-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa 320(%rdi), %ymm0 +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm27 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm25 # 64-byte Folded Reload +; AVX512BW-NEXT: # zmm25 = zmm0[0,1,2,3],mem[4,5,6,7] +; AVX512BW-NEXT: vmovdqa64 %zmm14, %zmm8 {%k2} +; AVX512BW-NEXT: vmovdqu64 %zmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm14, %zmm1, %zmm27 +; AVX512BW-NEXT: vpermt2q %zmm14, %zmm2, %zmm25 +; AVX512BW-NEXT: vmovdqa 384(%rdi), %ymm0 +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm22 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm20 # 64-byte Folded Reload +; AVX512BW-NEXT: # zmm20 = zmm0[0,1,2,3],mem[4,5,6,7] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm16, %zmm0 {%k2} +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm16, %zmm1, %zmm22 +; AVX512BW-NEXT: vpermt2q %zmm16, %zmm2, %zmm20 +; AVX512BW-NEXT: vmovdqa 448(%rdi), %ymm0 +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm3, %zmm18 +; AVX512BW-NEXT: vpermt2q %zmm5, %zmm1, %zmm10 +; AVX512BW-NEXT: vmovdqa64 %zmm10, %zmm11 +; AVX512BW-NEXT: vpermt2q %zmm12, %zmm1, %zmm18 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vshufi64x2 $228, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm17 # 64-byte Folded Reload +; AVX512BW-NEXT: # zmm17 = zmm0[0,1,2,3],mem[4,5,6,7] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm12, %zmm0 {%k2} +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm12, %zmm2, %zmm17 +; AVX512BW-NEXT: vpermt2q %zmm5, %zmm2, %zmm7 +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm13 +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm28 {%k2} +; AVX512BW-NEXT: vmovdqa64 (%r9), %zmm6 +; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm10 = [0,1,2,9,4,5,6,7] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm6, %zmm10, %zmm1 +; AVX512BW-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 64(%r9), %zmm7 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm10, %zmm2 +; AVX512BW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 128(%r9), %zmm2 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm10, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 192(%r9), %zmm3 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm3, %zmm10, %zmm4 +; AVX512BW-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 256(%r9), %zmm4 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm4, %zmm10, %zmm5 +; AVX512BW-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 320(%r9), %zmm5 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm5, %zmm10, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 384(%r9), %zmm8 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm8, %zmm10, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 448(%r9), %zmm9 +; AVX512BW-NEXT: vmovdqu64 (%rsp), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm9, %zmm10, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, (%rsp) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm10 = [0,1,2,13,4,5,6,7] +; AVX512BW-NEXT: vpermt2q %zmm6, %zmm10, %zmm23 +; AVX512BW-NEXT: vmovdqu64 %zmm23, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm10, %zmm12 +; AVX512BW-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm10, %zmm24 +; AVX512BW-NEXT: vmovdqu64 %zmm24, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm3, %zmm10, %zmm19 +; AVX512BW-NEXT: vmovdqu64 %zmm19, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm4, %zmm10, %zmm26 +; AVX512BW-NEXT: vmovdqu64 %zmm26, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm5, %zmm10, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm8, %zmm10, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm9, %zmm10, %zmm15 +; AVX512BW-NEXT: vmovdqu64 %zmm15, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa (%rdx), %xmm10 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] +; AVX512BW-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload +; AVX512BW-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm12 {%k1} +; AVX512BW-NEXT: vmovdqa 64(%rdx), %xmm10 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] +; AVX512BW-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm14 # 64-byte Reload +; AVX512BW-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm14 {%k1} +; AVX512BW-NEXT: vmovdqa 128(%rdx), %xmm10 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] +; AVX512BW-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload +; AVX512BW-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm16 {%k1} +; AVX512BW-NEXT: vmovdqa 192(%rdx), %xmm10 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] +; AVX512BW-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm30 # 64-byte Reload +; AVX512BW-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm30 {%k1} +; AVX512BW-NEXT: vmovdqa 256(%rdx), %xmm10 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] +; AVX512BW-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm31 # 64-byte Reload +; AVX512BW-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm31 {%k1} +; AVX512BW-NEXT: vmovdqa 320(%rdx), %xmm10 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] +; AVX512BW-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512BW-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm1 {%k1} +; AVX512BW-NEXT: vmovdqa 384(%rdx), %xmm10 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] +; AVX512BW-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm0 {%k1} +; AVX512BW-NEXT: vmovdqa 448(%rdx), %xmm10 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm10[0],mem[0] +; AVX512BW-NEXT: vinserti128 $1, %xmm10, %ymm0, %ymm10 +; AVX512BW-NEXT: vinserti64x4 $0, %ymm10, %zmm0, %zmm21 {%k1} +; AVX512BW-NEXT: vinserti32x4 $2, (%r8), %zmm12, %zmm10 +; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm29 = [0,1,2,3,4,8,6,7] +; AVX512BW-NEXT: vpermt2q %zmm6, %zmm29, %zmm10 +; AVX512BW-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vinserti32x4 $2, 64(%r8), %zmm14, %zmm10 +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm29, %zmm10 +; AVX512BW-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vinserti32x4 $2, 128(%r8), %zmm16, %zmm10 +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm29, %zmm10 +; AVX512BW-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vinserti32x4 $2, 192(%r8), %zmm30, %zmm26 +; AVX512BW-NEXT: vpermt2q %zmm3, %zmm29, %zmm26 +; AVX512BW-NEXT: vinserti32x4 $2, 256(%r8), %zmm31, %zmm24 +; AVX512BW-NEXT: vpermt2q %zmm4, %zmm29, %zmm24 +; AVX512BW-NEXT: vinserti32x4 $2, 320(%r8), %zmm1, %zmm23 +; AVX512BW-NEXT: vpermt2q %zmm5, %zmm29, %zmm23 +; AVX512BW-NEXT: vinserti32x4 $2, 384(%r8), %zmm0, %zmm19 +; AVX512BW-NEXT: vpermt2q %zmm8, %zmm29, %zmm19 +; AVX512BW-NEXT: vinserti32x4 $2, 448(%r8), %zmm21, %zmm21 +; AVX512BW-NEXT: vpermt2q %zmm9, %zmm29, %zmm21 +; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm29 = [0,10,2,3,4,5,6,11] +; AVX512BW-NEXT: vpermt2q %zmm6, %zmm29, %zmm11 +; AVX512BW-NEXT: vmovdqu64 %zmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm30 = [0,1,2,3,4,12,6,7] +; AVX512BW-NEXT: vpermt2q %zmm6, %zmm30, %zmm28 +; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm31 = [0,14,2,3,4,5,6,15] +; AVX512BW-NEXT: vpermt2q %zmm6, %zmm31, %zmm13 +; AVX512BW-NEXT: vmovdqu64 %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm16 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm29, %zmm16 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm15 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm30, %zmm15 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm14 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm31, %zmm14 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm29, %zmm13 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm30, %zmm12 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm31, %zmm11 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm10 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm3, %zmm29, %zmm10 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm3, %zmm30, %zmm7 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm3, %zmm31, %zmm2 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm4, %zmm29, %zmm1 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm4, %zmm30, %zmm3 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm4, %zmm31, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm5, %zmm29, %zmm27 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm5, %zmm30, %zmm4 +; AVX512BW-NEXT: vpermt2q %zmm5, %zmm31, %zmm25 +; AVX512BW-NEXT: vpermt2q %zmm8, %zmm29, %zmm22 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm8, %zmm30, %zmm5 +; AVX512BW-NEXT: vpermt2q %zmm8, %zmm31, %zmm20 +; AVX512BW-NEXT: vpermt2q %zmm9, %zmm29, %zmm18 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm9, %zmm30, %zmm6 +; AVX512BW-NEXT: vpermt2q %zmm9, %zmm31, %zmm17 +; AVX512BW-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512BW-NEXT: vmovdqa64 %zmm17, 3008(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm8 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm8, 2944(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm6, 2880(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm18, 2816(%rax) +; AVX512BW-NEXT: vmovups (%rsp), %zmm6 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm6, 2752(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm20, 2624(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm6, 2560(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm5, 2496(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm22, 2432(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm5, 2368(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm25, 2240(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm5, 2176(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm4, 2112(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm27, 2048(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm4, 1984(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm0, 1856(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 1792(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm3, 1728(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm1, 1664(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm3, 1600(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm2, 1472(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 1408(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm7, 1344(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm10, 1280(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm2, 1216(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm11, 1088(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 1024(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm12, 960(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm13, 896(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm1, 832(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm14, 704(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm1, 640(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm15, 576(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm16, 512(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 448(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 320(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 256(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm28, 192(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 128(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 64(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm21, 2688(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm19, 2304(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm23, 1920(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm24, 1536(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm26, 1152(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 768(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 384(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, (%rax) +; AVX512BW-NEXT: addq $3400, %rsp # imm = 0xD48 +; AVX512BW-NEXT: vzeroupper +; AVX512BW-NEXT: retq %in.vec0 = load <64 x i64>, ptr %in.vecptr0, align 64 %in.vec1 = load <64 x i64>, ptr %in.vecptr1, align 64 %in.vec2 = load <64 x i64>, ptr %in.vecptr2, align 64 @@ -10249,14 +8057,18 @@ define void @store_i64_stride6_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve ; AVX512-FAST: {{.*}} ; AVX512-SLOW: {{.*}} ; AVX512BW-FAST: {{.*}} +; AVX512BW-ONLY: {{.*}} ; AVX512BW-ONLY-FAST: {{.*}} ; AVX512BW-ONLY-SLOW: {{.*}} ; AVX512BW-SLOW: {{.*}} ; AVX512DQ-FAST: {{.*}} +; AVX512DQ-ONLY: {{.*}} ; AVX512DQ-SLOW: {{.*}} ; AVX512DQBW-FAST: {{.*}} +; AVX512DQBW-ONLY: {{.*}} ; AVX512DQBW-SLOW: {{.*}} ; AVX512F-FAST: {{.*}} +; AVX512F-ONLY: {{.*}} ; AVX512F-ONLY-FAST: {{.*}} ; AVX512F-ONLY-SLOW: {{.*}} ; AVX512F-SLOW: {{.*}} diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll index 1e2a9d022f66..0de7beea9398 100644 --- a/llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll +++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll @@ -2949,8 +2949,8 @@ define void @store_i64_stride7_vf16(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve ; AVX512DQ-SLOW-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [6,14,6,14] ; AVX512DQ-SLOW-NEXT: # ymm1 = mem[0,1,0,1] ; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm6, %zmm0 -; AVX512DQ-SLOW-NEXT: vbroadcasti64x2 {{.*#+}} ymm16 = [15,7,15,7] -; AVX512DQ-SLOW-NEXT: # ymm16 = mem[0,1,0,1] +; AVX512DQ-SLOW-NEXT: vbroadcasti32x4 {{.*#+}} ymm16 = [15,7,15,7] +; AVX512DQ-SLOW-NEXT: # ymm16 = mem[0,1,2,3,0,1,2,3] ; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm4, %zmm10 ; AVX512DQ-SLOW-NEXT: vpermt2q %zmm13, %zmm16, %zmm10 ; AVX512DQ-SLOW-NEXT: vpermi2q %zmm7, %zmm6, %zmm16 @@ -3156,8 +3156,8 @@ define void @store_i64_stride7_vf16(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve ; AVX512DQ-FAST-NEXT: # zmm20 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] ; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm7, %zmm17 ; AVX512DQ-FAST-NEXT: vpermt2q %zmm9, %zmm20, %zmm17 -; AVX512DQ-FAST-NEXT: vbroadcasti64x2 {{.*#+}} ymm21 = [6,14,6,14] -; AVX512DQ-FAST-NEXT: # ymm21 = mem[0,1,0,1] +; AVX512DQ-FAST-NEXT: vbroadcasti32x4 {{.*#+}} ymm21 = [6,14,6,14] +; AVX512DQ-FAST-NEXT: # ymm21 = mem[0,1,2,3,0,1,2,3] ; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm3, %zmm18 ; AVX512DQ-FAST-NEXT: vpermt2q %zmm5, %zmm21, %zmm18 ; AVX512DQ-FAST-NEXT: vmovdqa64 (%r8), %zmm11 @@ -3215,8 +3215,8 @@ define void @store_i64_stride7_vf16(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve ; AVX512DQ-FAST-NEXT: vpermi2q %zmm22, %zmm14, %zmm28 ; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm1, %zmm29 ; AVX512DQ-FAST-NEXT: vpermt2q %zmm16, %zmm24, %zmm29 -; AVX512DQ-FAST-NEXT: vbroadcasti64x2 {{.*#+}} ymm26 = [15,7,15,7] -; AVX512DQ-FAST-NEXT: # ymm26 = mem[0,1,0,1] +; AVX512DQ-FAST-NEXT: vbroadcasti32x4 {{.*#+}} ymm26 = [15,7,15,7] +; AVX512DQ-FAST-NEXT: # ymm26 = mem[0,1,2,3,0,1,2,3] ; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm13, %zmm22 ; AVX512DQ-FAST-NEXT: vpermt2q %zmm0, %zmm26, %zmm22 ; AVX512DQ-FAST-NEXT: movb $24, %dil @@ -3791,8 +3791,8 @@ define void @store_i64_stride7_vf16(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve ; AVX512DQBW-SLOW-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [6,14,6,14] ; AVX512DQBW-SLOW-NEXT: # ymm1 = mem[0,1,0,1] ; AVX512DQBW-SLOW-NEXT: vmovdqa64 %zmm6, %zmm0 -; AVX512DQBW-SLOW-NEXT: vbroadcasti64x2 {{.*#+}} ymm16 = [15,7,15,7] -; AVX512DQBW-SLOW-NEXT: # ymm16 = mem[0,1,0,1] +; AVX512DQBW-SLOW-NEXT: vbroadcasti32x4 {{.*#+}} ymm16 = [15,7,15,7] +; AVX512DQBW-SLOW-NEXT: # ymm16 = mem[0,1,2,3,0,1,2,3] ; AVX512DQBW-SLOW-NEXT: vmovdqa64 %zmm4, %zmm10 ; AVX512DQBW-SLOW-NEXT: vpermt2q %zmm13, %zmm16, %zmm10 ; AVX512DQBW-SLOW-NEXT: vpermi2q %zmm7, %zmm6, %zmm16 @@ -3998,8 +3998,8 @@ define void @store_i64_stride7_vf16(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve ; AVX512DQBW-FAST-NEXT: # zmm20 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] ; AVX512DQBW-FAST-NEXT: vmovdqa64 %zmm7, %zmm17 ; AVX512DQBW-FAST-NEXT: vpermt2q %zmm9, %zmm20, %zmm17 -; AVX512DQBW-FAST-NEXT: vbroadcasti64x2 {{.*#+}} ymm21 = [6,14,6,14] -; AVX512DQBW-FAST-NEXT: # ymm21 = mem[0,1,0,1] +; AVX512DQBW-FAST-NEXT: vbroadcasti32x4 {{.*#+}} ymm21 = [6,14,6,14] +; AVX512DQBW-FAST-NEXT: # ymm21 = mem[0,1,2,3,0,1,2,3] ; AVX512DQBW-FAST-NEXT: vmovdqa64 %zmm3, %zmm18 ; AVX512DQBW-FAST-NEXT: vpermt2q %zmm5, %zmm21, %zmm18 ; AVX512DQBW-FAST-NEXT: vmovdqa64 (%r8), %zmm11 @@ -4057,8 +4057,8 @@ define void @store_i64_stride7_vf16(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve ; AVX512DQBW-FAST-NEXT: vpermi2q %zmm22, %zmm14, %zmm28 ; AVX512DQBW-FAST-NEXT: vmovdqa64 %zmm1, %zmm29 ; AVX512DQBW-FAST-NEXT: vpermt2q %zmm16, %zmm24, %zmm29 -; AVX512DQBW-FAST-NEXT: vbroadcasti64x2 {{.*#+}} ymm26 = [15,7,15,7] -; AVX512DQBW-FAST-NEXT: # ymm26 = mem[0,1,0,1] +; AVX512DQBW-FAST-NEXT: vbroadcasti32x4 {{.*#+}} ymm26 = [15,7,15,7] +; AVX512DQBW-FAST-NEXT: # ymm26 = mem[0,1,2,3,0,1,2,3] ; AVX512DQBW-FAST-NEXT: vmovdqa64 %zmm13, %zmm22 ; AVX512DQBW-FAST-NEXT: vpermt2q %zmm0, %zmm26, %zmm22 ; AVX512DQBW-FAST-NEXT: movb $24, %dil @@ -15820,13 +15820,13 @@ define void @store_i64_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve ; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm0, %zmm1 ; AVX512DQ-FAST-NEXT: vpermt2q %zmm26, %zmm21, %zmm1 ; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vbroadcasti64x2 {{.*#+}} ymm30 = [6,14,6,14] -; AVX512DQ-FAST-NEXT: # ymm30 = mem[0,1,0,1] +; AVX512DQ-FAST-NEXT: vbroadcasti32x4 {{.*#+}} ymm30 = [6,14,6,14] +; AVX512DQ-FAST-NEXT: # ymm30 = mem[0,1,2,3,0,1,2,3] ; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm0, %zmm1 ; AVX512DQ-FAST-NEXT: vpermt2q %zmm26, %zmm30, %zmm1 ; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vbroadcasti64x2 {{.*#+}} ymm18 = [15,7,15,7] -; AVX512DQ-FAST-NEXT: # ymm18 = mem[0,1,0,1] +; AVX512DQ-FAST-NEXT: vbroadcasti32x4 {{.*#+}} ymm18 = [15,7,15,7] +; AVX512DQ-FAST-NEXT: # ymm18 = mem[0,1,2,3,0,1,2,3] ; AVX512DQ-FAST-NEXT: vpermt2q %zmm26, %zmm18, %zmm0 ; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill ; AVX512DQ-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload @@ -19661,13 +19661,13 @@ define void @store_i64_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve ; AVX512DQBW-FAST-NEXT: vmovdqa64 %zmm0, %zmm1 ; AVX512DQBW-FAST-NEXT: vpermt2q %zmm26, %zmm21, %zmm1 ; AVX512DQBW-FAST-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-FAST-NEXT: vbroadcasti64x2 {{.*#+}} ymm30 = [6,14,6,14] -; AVX512DQBW-FAST-NEXT: # ymm30 = mem[0,1,0,1] +; AVX512DQBW-FAST-NEXT: vbroadcasti32x4 {{.*#+}} ymm30 = [6,14,6,14] +; AVX512DQBW-FAST-NEXT: # ymm30 = mem[0,1,2,3,0,1,2,3] ; AVX512DQBW-FAST-NEXT: vmovdqa64 %zmm0, %zmm1 ; AVX512DQBW-FAST-NEXT: vpermt2q %zmm26, %zmm30, %zmm1 ; AVX512DQBW-FAST-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-FAST-NEXT: vbroadcasti64x2 {{.*#+}} ymm18 = [15,7,15,7] -; AVX512DQBW-FAST-NEXT: # ymm18 = mem[0,1,0,1] +; AVX512DQBW-FAST-NEXT: vbroadcasti32x4 {{.*#+}} ymm18 = [15,7,15,7] +; AVX512DQBW-FAST-NEXT: # ymm18 = mem[0,1,2,3,0,1,2,3] ; AVX512DQBW-FAST-NEXT: vpermt2q %zmm26, %zmm18, %zmm0 ; AVX512DQBW-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill ; AVX512DQBW-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-8.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-8.ll index 6778ae0647ae..8bad8e79ae36 100644 --- a/llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-8.ll +++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-8.ll @@ -8876,3957 +8876,1981 @@ define void @store_i64_stride8_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve ; AVX2-ONLY-NEXT: vzeroupper ; AVX2-ONLY-NEXT: retq ; -; AVX512F-ONLY-LABEL: store_i64_stride8_vf64: -; AVX512F-ONLY: # %bb.0: -; AVX512F-ONLY-NEXT: subq $5512, %rsp # imm = 0x1588 -; AVX512F-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512F-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %r10 -; AVX512F-ONLY-NEXT: vmovdqa64 128(%rdi), %zmm2 -; AVX512F-ONLY-NEXT: vmovdqa64 64(%rdi), %zmm4 -; AVX512F-ONLY-NEXT: vmovdqa64 (%rdi), %zmm8 -; AVX512F-ONLY-NEXT: vmovdqa64 128(%rsi), %zmm17 -; AVX512F-ONLY-NEXT: vmovdqa64 64(%rsi), %zmm19 -; AVX512F-ONLY-NEXT: vmovdqa64 (%rsi), %zmm22 -; AVX512F-ONLY-NEXT: vmovdqa64 64(%rdx), %zmm5 -; AVX512F-ONLY-NEXT: vmovdqa64 (%rdx), %zmm10 -; AVX512F-ONLY-NEXT: vmovdqa64 64(%rcx), %zmm20 -; AVX512F-ONLY-NEXT: vmovdqa64 (%rcx), %zmm11 -; AVX512F-ONLY-NEXT: vmovdqa64 (%r8), %zmm1 -; AVX512F-ONLY-NEXT: vmovdqa64 64(%r8), %zmm25 -; AVX512F-ONLY-NEXT: vmovdqa64 128(%r8), %zmm23 -; AVX512F-ONLY-NEXT: vmovdqa64 (%r9), %zmm28 -; AVX512F-ONLY-NEXT: vmovdqa64 64(%r9), %zmm26 -; AVX512F-ONLY-NEXT: vmovdqa64 128(%r9), %zmm24 -; AVX512F-ONLY-NEXT: vmovdqa64 (%r10), %zmm21 -; AVX512F-ONLY-NEXT: vmovdqa64 64(%r10), %zmm14 -; AVX512F-ONLY-NEXT: vmovdqa64 (%rax), %zmm27 -; AVX512F-ONLY-NEXT: vmovdqa64 64(%rax), %zmm16 -; AVX512F-ONLY-NEXT: movb $-64, %r11b -; AVX512F-ONLY-NEXT: kmovw %r11d, %k1 -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm3 = [4,12,4,12,4,12,4,12] -; AVX512F-ONLY-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm21, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm27, %zmm3, %zmm0 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm12 = zmm1[0],zmm28[0],zmm1[2],zmm28[2],zmm1[4],zmm28[4],zmm1[6],zmm28[6] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, %zmm12 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm22, %zmm3, %zmm0 -; AVX512F-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm6 = [4,12,4,12] -; AVX512F-ONLY-NEXT: # ymm6 = mem[0,1,0,1] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm10, %zmm15 -; AVX512F-ONLY-NEXT: vpermt2q %zmm11, %zmm6, %zmm15 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm15[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm12, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm9 = [5,13,5,13,5,13,5,13] -; AVX512F-ONLY-NEXT: # zmm9 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm21, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm27, %zmm9, %zmm0 -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm12 = zmm1[1],zmm28[1],zmm1[3],zmm28[3],zmm1[5],zmm28[5],zmm1[7],zmm28[7] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, %zmm12 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm22, %zmm9, %zmm0 -; AVX512F-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm7 = [5,13,5,13] -; AVX512F-ONLY-NEXT: # ymm7 = mem[0,1,0,1] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm10, %zmm15 -; AVX512F-ONLY-NEXT: vpermt2q %zmm11, %zmm7, %zmm15 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm15[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm12, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm13 = [6,14,6,14,6,14,6,14] -; AVX512F-ONLY-NEXT: # zmm13 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm1, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm1, %zmm29 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm28, %zmm13, %zmm0 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm0 {%k1} = zmm21[0],zmm27[0],zmm21[2],zmm27[2],zmm21[4],zmm27[4],zmm21[6],zmm27[6] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm8, %zmm12 -; AVX512F-ONLY-NEXT: vpermt2q %zmm22, %zmm13, %zmm12 -; AVX512F-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [6,14,6,14] -; AVX512F-ONLY-NEXT: # ymm1 = mem[0,1,0,1] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm10, %zmm15 -; AVX512F-ONLY-NEXT: vpermt2q %zmm11, %zmm1, %zmm15 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm12 = ymm12[0,1,2,3],ymm15[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm12, %zmm0, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm18 = [7,15,7,15,7,15,7,15] -; AVX512F-ONLY-NEXT: # zmm18 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm29, %zmm12 -; AVX512F-ONLY-NEXT: vpermt2q %zmm28, %zmm18, %zmm12 -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm12 {%k1} = zmm21[1],zmm27[1],zmm21[3],zmm27[3],zmm21[5],zmm27[5],zmm21[7],zmm27[7] -; AVX512F-ONLY-NEXT: vpermt2q %zmm22, %zmm18, %zmm8 -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} ymm30 = [7,15,7,15] -; AVX512F-ONLY-NEXT: # ymm30 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vpermt2q %zmm11, %zmm30, %zmm10 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm8 = ymm8[0,1,2,3],ymm10[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm8, %zmm12, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm14, %zmm8 -; AVX512F-ONLY-NEXT: vpermt2q %zmm16, %zmm3, %zmm8 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm10 = zmm25[0],zmm26[0],zmm25[2],zmm26[2],zmm25[4],zmm26[4],zmm25[6],zmm26[6] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm8, %zmm10 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm8 -; AVX512F-ONLY-NEXT: vpermt2q %zmm19, %zmm3, %zmm8 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm5, %zmm11 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm6, %zmm15 -; AVX512F-ONLY-NEXT: vpermt2q %zmm20, %zmm6, %zmm11 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm8 = ymm8[0,1,2,3],ymm11[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm8, %zmm10, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm14, %zmm8 -; AVX512F-ONLY-NEXT: vpermt2q %zmm16, %zmm9, %zmm8 -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm10 = zmm25[1],zmm26[1],zmm25[3],zmm26[3],zmm25[5],zmm26[5],zmm25[7],zmm26[7] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm8, %zmm10 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm8 -; AVX512F-ONLY-NEXT: vpermt2q %zmm19, %zmm9, %zmm8 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm5, %zmm11 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, %zmm12 -; AVX512F-ONLY-NEXT: vpermt2q %zmm20, %zmm7, %zmm11 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm8 = ymm8[0,1,2,3],ymm11[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm8, %zmm10, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm8 -; AVX512F-ONLY-NEXT: vpermt2q %zmm19, %zmm13, %zmm8 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm5, %zmm10 -; AVX512F-ONLY-NEXT: vpermt2q %zmm20, %zmm1, %zmm10 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm8 = ymm8[0,1,2,3],ymm10[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm25, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm25, %zmm10 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm26, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm26, %zmm13, %zmm10 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm14, %zmm11 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm14, (%rsp) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm16, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm10 {%k1} = zmm14[0],zmm16[0],zmm14[2],zmm16[2],zmm14[4],zmm16[4],zmm14[6],zmm16[6] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm8, %zmm10, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 128(%r10), %zmm10 -; AVX512F-ONLY-NEXT: vpermt2q %zmm19, %zmm18, %zmm4 -; AVX512F-ONLY-NEXT: vmovdqa64 128(%rax), %zmm14 -; AVX512F-ONLY-NEXT: vpermt2q %zmm20, %zmm30, %zmm5 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm25, %zmm6 -; AVX512F-ONLY-NEXT: vpermt2q %zmm26, %zmm18, %zmm6 -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm6 {%k1} = zmm11[1],zmm16[1],zmm11[3],zmm16[3],zmm11[5],zmm16[5],zmm11[7],zmm16[7] -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3],ymm5[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm6, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm10, %zmm4 -; AVX512F-ONLY-NEXT: vpermt2q %zmm14, %zmm3, %zmm4 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm5 = zmm23[0],zmm24[0],zmm23[2],zmm24[2],zmm23[4],zmm24[4],zmm23[6],zmm24[6] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm5 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm6 -; AVX512F-ONLY-NEXT: vpermt2q %zmm17, %zmm3, %zmm6 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm3, %zmm11 -; AVX512F-ONLY-NEXT: vmovdqa64 128(%rdx), %zmm4 -; AVX512F-ONLY-NEXT: vmovdqa64 128(%rcx), %zmm7 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm8 -; AVX512F-ONLY-NEXT: vpermt2q %zmm7, %zmm15, %zmm8 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm6 = ymm6[0,1,2,3],ymm8[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm6, %zmm5, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm10, %zmm5 -; AVX512F-ONLY-NEXT: vpermt2q %zmm14, %zmm9, %zmm5 -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm6 = zmm23[1],zmm24[1],zmm23[3],zmm24[3],zmm23[5],zmm24[5],zmm23[7],zmm24[7] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm5, %zmm6 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm5 -; AVX512F-ONLY-NEXT: vpermt2q %zmm17, %zmm9, %zmm5 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm8 -; AVX512F-ONLY-NEXT: vpermt2q %zmm7, %zmm12, %zmm8 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm5 = ymm5[0,1,2,3],ymm8[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm5, %zmm6, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm5 -; AVX512F-ONLY-NEXT: vpermt2q %zmm17, %zmm13, %zmm5 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm6 -; AVX512F-ONLY-NEXT: vpermt2q %zmm7, %zmm1, %zmm6 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm5 = ymm5[0,1,2,3],ymm6[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm23, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm23, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm23, %zmm6 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm24, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm24, %zmm13, %zmm6 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm14, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm6 {%k1} = zmm10[0],zmm14[0],zmm10[2],zmm14[2],zmm10[4],zmm14[4],zmm10[6],zmm14[6] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm5, %zmm6, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm17, %zmm18, %zmm2 -; AVX512F-ONLY-NEXT: vpermt2q %zmm7, %zmm30, %zmm4 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm4[4,5,6,7] -; AVX512F-ONLY-NEXT: vpermt2q %zmm24, %zmm18, %zmm3 -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm3 {%k1} = zmm10[1],zmm14[1],zmm10[3],zmm14[3],zmm10[5],zmm14[5],zmm10[7],zmm14[7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm3, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 192(%r10), %zmm10 -; AVX512F-ONLY-NEXT: vmovdqa64 192(%rax), %zmm26 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm10, %zmm2 -; AVX512F-ONLY-NEXT: vpermt2q %zmm26, %zmm11, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqa64 192(%r8), %zmm23 -; AVX512F-ONLY-NEXT: vmovdqa64 192(%r9), %zmm29 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm4 = zmm23[0],zmm29[0],zmm23[2],zmm29[2],zmm23[4],zmm29[4],zmm23[6],zmm29[6] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa64 192(%rdi), %zmm2 -; AVX512F-ONLY-NEXT: vmovdqa64 192(%rsi), %zmm5 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm6 -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm11, %zmm6 -; AVX512F-ONLY-NEXT: vmovdqa64 192(%rdx), %zmm3 -; AVX512F-ONLY-NEXT: vmovdqa64 192(%rcx), %zmm7 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm3, %zmm8 -; AVX512F-ONLY-NEXT: vpermt2q %zmm7, %zmm15, %zmm8 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm6 = ymm6[0,1,2,3],ymm8[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm6, %zmm4, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm10, %zmm4 -; AVX512F-ONLY-NEXT: vpermt2q %zmm26, %zmm9, %zmm4 -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm6 = zmm23[1],zmm29[1],zmm23[3],zmm29[3],zmm23[5],zmm29[5],zmm23[7],zmm29[7] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm6 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm9, %zmm4 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm3, %zmm8 -; AVX512F-ONLY-NEXT: vpermt2q %zmm7, %zmm12, %zmm8 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3],ymm8[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm6, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm13, %zmm4 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm3, %zmm6 -; AVX512F-ONLY-NEXT: vpermt2q %zmm7, %zmm1, %zmm6 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3],ymm6[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm23, %zmm6 -; AVX512F-ONLY-NEXT: vpermt2q %zmm29, %zmm13, %zmm6 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm6 {%k1} = zmm10[0],zmm26[0],zmm10[2],zmm26[2],zmm10[4],zmm26[4],zmm10[6],zmm26[6] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm6, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm18, %zmm2 -; AVX512F-ONLY-NEXT: vpermt2q %zmm7, %zmm30, %zmm3 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm3[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm23, %zmm3 -; AVX512F-ONLY-NEXT: vpermt2q %zmm29, %zmm18, %zmm3 -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm3 {%k1} = zmm10[1],zmm26[1],zmm10[3],zmm26[3],zmm10[5],zmm26[5],zmm10[7],zmm26[7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm3, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 256(%r10), %zmm10 -; AVX512F-ONLY-NEXT: vmovdqa64 256(%rax), %zmm22 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm10, %zmm2 -; AVX512F-ONLY-NEXT: vpermt2q %zmm22, %zmm11, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqa64 256(%r8), %zmm0 -; AVX512F-ONLY-NEXT: vmovdqa64 256(%r9), %zmm24 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm4 = zmm0[0],zmm24[0],zmm0[2],zmm24[2],zmm0[4],zmm24[4],zmm0[6],zmm24[6] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, %zmm17 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa64 256(%rdi), %zmm2 -; AVX512F-ONLY-NEXT: vmovdqa64 256(%rsi), %zmm5 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm6 -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm11, %zmm6 -; AVX512F-ONLY-NEXT: vmovdqa64 256(%rdx), %zmm3 -; AVX512F-ONLY-NEXT: vmovdqa64 256(%rcx), %zmm7 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm3, %zmm8 -; AVX512F-ONLY-NEXT: vpermt2q %zmm7, %zmm15, %zmm8 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm6 = ymm6[0,1,2,3],ymm8[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm6, %zmm4, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm10, %zmm4 -; AVX512F-ONLY-NEXT: vpermt2q %zmm22, %zmm9, %zmm4 -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm6 = zmm17[1],zmm24[1],zmm17[3],zmm24[3],zmm17[5],zmm24[5],zmm17[7],zmm24[7] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm6 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm9, %zmm4 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm3, %zmm8 -; AVX512F-ONLY-NEXT: vpermt2q %zmm7, %zmm12, %zmm8 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3],ymm8[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm6, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm13, %zmm4 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm3, %zmm6 -; AVX512F-ONLY-NEXT: vpermt2q %zmm7, %zmm1, %zmm6 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3],ymm6[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm17, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm17, %zmm6 -; AVX512F-ONLY-NEXT: vpermt2q %zmm24, %zmm13, %zmm6 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm6 {%k1} = zmm10[0],zmm22[0],zmm10[2],zmm22[2],zmm10[4],zmm22[4],zmm10[6],zmm22[6] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm6, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm5, %zmm18, %zmm2 -; AVX512F-ONLY-NEXT: vpermt2q %zmm7, %zmm30, %zmm3 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm3[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm17, %zmm3 -; AVX512F-ONLY-NEXT: vpermt2q %zmm24, %zmm18, %zmm3 -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm3 {%k1} = zmm10[1],zmm22[1],zmm10[3],zmm22[3],zmm10[5],zmm22[5],zmm10[7],zmm22[7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm3, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 320(%rdi), %zmm2 -; AVX512F-ONLY-NEXT: vmovdqa64 320(%rsi), %zmm3 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm5 -; AVX512F-ONLY-NEXT: vpermt2q %zmm3, %zmm11, %zmm5 -; AVX512F-ONLY-NEXT: vmovdqa64 320(%rdx), %zmm14 -; AVX512F-ONLY-NEXT: vmovdqa64 320(%rcx), %zmm6 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm14, %zmm7 -; AVX512F-ONLY-NEXT: vpermt2q %zmm6, %zmm15, %zmm7 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm5 = ymm5[0,1,2,3],ymm7[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm14, %zmm7 -; AVX512F-ONLY-NEXT: vpermt2q %zmm6, %zmm12, %zmm7 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm14, %zmm8 -; AVX512F-ONLY-NEXT: vpermt2q %zmm6, %zmm1, %zmm8 -; AVX512F-ONLY-NEXT: vpermt2q %zmm6, %zmm30, %zmm14 -; AVX512F-ONLY-NEXT: vmovdqa64 384(%rdx), %zmm0 -; AVX512F-ONLY-NEXT: vmovdqa64 384(%rcx), %zmm6 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, %zmm10 -; AVX512F-ONLY-NEXT: vpermt2q %zmm6, %zmm15, %zmm10 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, %zmm10 -; AVX512F-ONLY-NEXT: vpermt2q %zmm6, %zmm12, %zmm10 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, %zmm10 -; AVX512F-ONLY-NEXT: vpermt2q %zmm6, %zmm1, %zmm10 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm6, %zmm30, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 448(%rdx), %zmm0 -; AVX512F-ONLY-NEXT: vmovdqa64 448(%rcx), %zmm6 -; AVX512F-ONLY-NEXT: vpermi2q %zmm6, %zmm0, %zmm15 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm15, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermi2q %zmm6, %zmm0, %zmm12 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermi2q %zmm6, %zmm0, %zmm1 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm6, %zmm30, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 320(%r10), %zmm31 -; AVX512F-ONLY-NEXT: vmovdqa64 320(%rax), %zmm12 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm31, %zmm1 -; AVX512F-ONLY-NEXT: vpermt2q %zmm12, %zmm11, %zmm1 -; AVX512F-ONLY-NEXT: vmovdqa64 320(%r8), %zmm17 -; AVX512F-ONLY-NEXT: vmovdqa64 320(%r9), %zmm4 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm10 = zmm17[0],zmm4[0],zmm17[2],zmm4[2],zmm17[4],zmm4[4],zmm17[6],zmm4[6] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm1, %zmm10 {%k1} -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm5, %zmm10, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm31, %zmm1 -; AVX512F-ONLY-NEXT: vpermt2q %zmm12, %zmm9, %zmm1 -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm5 = zmm17[1],zmm4[1],zmm17[3],zmm4[3],zmm17[5],zmm4[5],zmm17[7],zmm4[7] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm1, %zmm5 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm1 -; AVX512F-ONLY-NEXT: vpermt2q %zmm3, %zmm9, %zmm1 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm7[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm5, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm1 -; AVX512F-ONLY-NEXT: vpermt2q %zmm3, %zmm13, %zmm1 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm8[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm17, %zmm5 -; AVX512F-ONLY-NEXT: vpermt2q %zmm4, %zmm13, %zmm5 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm5 {%k1} = zmm31[0],zmm12[0],zmm31[2],zmm12[2],zmm31[4],zmm12[4],zmm31[6],zmm12[6] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm5, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm3, %zmm18, %zmm2 -; AVX512F-ONLY-NEXT: vpblendd {{.*#+}} ymm1 = ymm2[0,1,2,3],ymm14[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm17, %zmm2 -; AVX512F-ONLY-NEXT: vpermt2q %zmm4, %zmm18, %zmm2 -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm2 {%k1} = zmm31[1],zmm12[1],zmm31[3],zmm12[3],zmm31[5],zmm12[5],zmm31[7],zmm12[7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm2, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 384(%rdi), %zmm0 -; AVX512F-ONLY-NEXT: vmovdqa64 384(%rsi), %zmm1 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm11, %zmm2 -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm11, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, %zmm3 -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm9, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, %zmm3 -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm13, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm18, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 384(%r10), %zmm11 -; AVX512F-ONLY-NEXT: vmovdqa64 384(%rax), %zmm20 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm11, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm20, %zmm2, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm11, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm20, %zmm9, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 384(%r8), %zmm30 -; AVX512F-ONLY-NEXT: vmovdqa64 384(%r9), %zmm0 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm30, %zmm1 -; AVX512F-ONLY-NEXT: vpermt2q %zmm0, %zmm13, %zmm1 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 448(%r10), %zmm16 -; AVX512F-ONLY-NEXT: vmovdqa64 448(%rax), %zmm8 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm16, %zmm1 -; AVX512F-ONLY-NEXT: vpermt2q %zmm8, %zmm2, %zmm1 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 448(%rdi), %zmm3 -; AVX512F-ONLY-NEXT: vmovdqa64 448(%rsi), %zmm1 -; AVX512F-ONLY-NEXT: vpermi2q %zmm1, %zmm3, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm16, %zmm2 -; AVX512F-ONLY-NEXT: vpermt2q %zmm8, %zmm9, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermi2q %zmm1, %zmm3, %zmm9 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 448(%r8), %zmm19 -; AVX512F-ONLY-NEXT: vmovdqa64 448(%r9), %zmm7 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm19, %zmm2 -; AVX512F-ONLY-NEXT: vpermt2q %zmm7, %zmm13, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermi2q %zmm1, %zmm3, %zmm13 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm1, %zmm18, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm30, %zmm1 -; AVX512F-ONLY-NEXT: vpermt2q %zmm0, %zmm18, %zmm1 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm1, %zmm5 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm19, %zmm1 -; AVX512F-ONLY-NEXT: vpermt2q %zmm7, %zmm18, %zmm1 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm15 = [0,8,0,8,0,8,0,8] -; AVX512F-ONLY-NEXT: # zmm15 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm21, %zmm1 -; AVX512F-ONLY-NEXT: vpermt2q %zmm27, %zmm15, %zmm1 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm14 = [1,9,1,9,1,9,1,9] -; AVX512F-ONLY-NEXT: # zmm14 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm21, %zmm1 -; AVX512F-ONLY-NEXT: vpermt2q %zmm27, %zmm14, %zmm1 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm6 = [2,10,2,10,2,10,2,10] -; AVX512F-ONLY-NEXT: # zmm6 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm21, %zmm1 -; AVX512F-ONLY-NEXT: vpermt2q %zmm27, %zmm6, %zmm1 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm1 = [3,11,3,11,3,11,3,11] -; AVX512F-ONLY-NEXT: # zmm1 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512F-ONLY-NEXT: vpermt2q %zmm27, %zmm1, %zmm21 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm21, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512F-ONLY-NEXT: vpermt2q %zmm28, %zmm15, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512F-ONLY-NEXT: vpermt2q %zmm28, %zmm14, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm25 -; AVX512F-ONLY-NEXT: vpermt2q %zmm28, %zmm6, %zmm25 -; AVX512F-ONLY-NEXT: vpermt2q %zmm28, %zmm1, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 (%rsp), %zmm27 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm27, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm3, %zmm15, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm27, %zmm2 -; AVX512F-ONLY-NEXT: vpermt2q %zmm3, %zmm14, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm27, %zmm2 -; AVX512F-ONLY-NEXT: vpermt2q %zmm3, %zmm6, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm3, %zmm1, %zmm27 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm27, (%rsp) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm9, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm2, %zmm15, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm9, %zmm3 -; AVX512F-ONLY-NEXT: vpermt2q %zmm2, %zmm14, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm9, %zmm18 -; AVX512F-ONLY-NEXT: vpermt2q %zmm2, %zmm6, %zmm18 -; AVX512F-ONLY-NEXT: vpermt2q %zmm2, %zmm1, %zmm9 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm9, %zmm15, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512F-ONLY-NEXT: vpermt2q %zmm9, %zmm14, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512F-ONLY-NEXT: vpermt2q %zmm9, %zmm6, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm9, %zmm1, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm9, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpermt2q %zmm2, %zmm15, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm9, %zmm3 -; AVX512F-ONLY-NEXT: vpermt2q %zmm2, %zmm14, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm9, %zmm13 -; AVX512F-ONLY-NEXT: vpermt2q %zmm2, %zmm6, %zmm13 -; AVX512F-ONLY-NEXT: vpermt2q %zmm2, %zmm1, %zmm9 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512F-ONLY-NEXT: vpermt2q %zmm26, %zmm15, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512F-ONLY-NEXT: vpermt2q %zmm26, %zmm14, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512F-ONLY-NEXT: vpermt2q %zmm26, %zmm6, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm26, %zmm1, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm23, %zmm3 -; AVX512F-ONLY-NEXT: vpermt2q %zmm29, %zmm15, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm23, %zmm3 -; AVX512F-ONLY-NEXT: vpermt2q %zmm29, %zmm14, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm23, %zmm10 -; AVX512F-ONLY-NEXT: vpermt2q %zmm29, %zmm6, %zmm10 -; AVX512F-ONLY-NEXT: vpermt2q %zmm29, %zmm1, %zmm23 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm23, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm23 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm23, %zmm2 -; AVX512F-ONLY-NEXT: vpermt2q %zmm22, %zmm15, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm23, %zmm2 -; AVX512F-ONLY-NEXT: vpermt2q %zmm22, %zmm14, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm23, %zmm2 -; AVX512F-ONLY-NEXT: vpermt2q %zmm22, %zmm6, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm22, %zmm1, %zmm23 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512F-ONLY-NEXT: vpermt2q %zmm24, %zmm15, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512F-ONLY-NEXT: vpermt2q %zmm24, %zmm14, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm26 -; AVX512F-ONLY-NEXT: vpermt2q %zmm24, %zmm6, %zmm26 -; AVX512F-ONLY-NEXT: vpermt2q %zmm24, %zmm1, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm31, %zmm2 -; AVX512F-ONLY-NEXT: vpermt2q %zmm12, %zmm15, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm31, %zmm2 -; AVX512F-ONLY-NEXT: vpermt2q %zmm12, %zmm14, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm31, %zmm2 -; AVX512F-ONLY-NEXT: vpermt2q %zmm12, %zmm6, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vpermt2q %zmm12, %zmm1, %zmm31 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm17, %zmm29 -; AVX512F-ONLY-NEXT: vpermt2q %zmm4, %zmm15, %zmm29 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm17, %zmm2 -; AVX512F-ONLY-NEXT: vpermt2q %zmm4, %zmm14, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm17, %zmm24 -; AVX512F-ONLY-NEXT: vpermt2q %zmm4, %zmm6, %zmm24 -; AVX512F-ONLY-NEXT: vpermt2q %zmm4, %zmm1, %zmm17 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm11, %zmm2 -; AVX512F-ONLY-NEXT: vpermt2q %zmm20, %zmm15, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm11, %zmm2 -; AVX512F-ONLY-NEXT: vpermt2q %zmm20, %zmm14, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm9 {%k1} = zmm11[0],zmm20[0],zmm11[2],zmm20[2],zmm11[4],zmm20[4],zmm11[6],zmm20[6] -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm5 {%k1} = zmm11[1],zmm20[1],zmm11[3],zmm20[3],zmm11[5],zmm20[5],zmm11[7],zmm20[7] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm5, %zmm27 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm11, %zmm22 -; AVX512F-ONLY-NEXT: vpermt2q %zmm20, %zmm6, %zmm22 -; AVX512F-ONLY-NEXT: vpermt2q %zmm20, %zmm1, %zmm11 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm30, %zmm21 -; AVX512F-ONLY-NEXT: vpermt2q %zmm0, %zmm15, %zmm21 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm30, %zmm28 -; AVX512F-ONLY-NEXT: vpermt2q %zmm0, %zmm14, %zmm28 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm30, %zmm20 -; AVX512F-ONLY-NEXT: vpermt2q %zmm0, %zmm6, %zmm20 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm2 = zmm30[0],zmm0[0],zmm30[2],zmm0[2],zmm30[4],zmm0[4],zmm30[6],zmm0[6] -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm3 = zmm30[1],zmm0[1],zmm30[3],zmm0[3],zmm30[5],zmm0[5],zmm30[7],zmm0[7] -; AVX512F-ONLY-NEXT: vpermt2q %zmm0, %zmm1, %zmm30 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm16, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm8, %zmm15, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm16, %zmm0 -; AVX512F-ONLY-NEXT: vpermt2q %zmm8, %zmm14, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm4 {%k1} = zmm16[0],zmm8[0],zmm16[2],zmm8[2],zmm16[4],zmm8[4],zmm16[6],zmm8[6] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm5 {%k1} = zmm16[1],zmm8[1],zmm16[3],zmm8[3],zmm16[5],zmm8[5],zmm16[7],zmm8[7] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm16, %zmm12 -; AVX512F-ONLY-NEXT: vpermt2q %zmm8, %zmm6, %zmm12 -; AVX512F-ONLY-NEXT: vpermt2q %zmm8, %zmm1, %zmm16 -; AVX512F-ONLY-NEXT: vpermi2q %zmm7, %zmm19, %zmm15 -; AVX512F-ONLY-NEXT: vpermi2q %zmm7, %zmm19, %zmm14 -; AVX512F-ONLY-NEXT: vpermi2q %zmm7, %zmm19, %zmm6 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm8 = zmm19[0],zmm7[0],zmm19[2],zmm7[2],zmm19[4],zmm7[4],zmm19[6],zmm7[6] -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm0 = zmm19[1],zmm7[1],zmm19[3],zmm7[3],zmm19[5],zmm7[5],zmm19[7],zmm7[7] -; AVX512F-ONLY-NEXT: vpermt2q %zmm7, %zmm1, %zmm19 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload -; AVX512F-ONLY-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, %zmm2 {%k1} -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm2, %zmm1 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload -; AVX512F-ONLY-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 {%k1} -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm3, %zmm1 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload -; AVX512F-ONLY-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm9, %zmm1 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload -; AVX512F-ONLY-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm27, %zmm1 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload -; AVX512F-ONLY-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm8 {%k1} -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm8, %zmm1 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload -; AVX512F-ONLY-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm0 {%k1} -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm0, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 32-byte Folded Reload -; AVX512F-ONLY-NEXT: # ymm0 = ymm0[0,1,2,3],mem[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm4, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 32-byte Folded Reload -; AVX512F-ONLY-NEXT: # ymm0 = ymm0[0,1,2,3],mem[4,5,6,7] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm5, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, %zmm25 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa (%rcx), %ymm0 -; AVX512F-ONLY-NEXT: vmovdqa (%rdx), %ymm1 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512F-ONLY-NEXT: vmovdqa (%rsi), %ymm3 -; AVX512F-ONLY-NEXT: vmovdqa (%rdi), %ymm7 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm7[0],ymm3[0],ymm7[2],ymm3[2] -; AVX512F-ONLY-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm8[2,3],ymm2[2,3] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm25, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 {%k1} -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm7[1],ymm3[1],ymm7[3],ymm3[3] -; AVX512F-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm4, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, %zmm18 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa 64(%rcx), %ymm0 -; AVX512F-ONLY-NEXT: vmovdqa 64(%rdx), %ymm1 -; AVX512F-ONLY-NEXT: vmovdqa 64(%rsi), %ymm2 -; AVX512F-ONLY-NEXT: vmovdqa 64(%rdi), %ymm3 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm7 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm3[0],ymm2[0],ymm3[2],ymm2[2] -; AVX512F-ONLY-NEXT: vperm2i128 {{.*#+}} ymm7 = ymm8[2,3],ymm7[2,3] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm7, %zmm18, %zmm4 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 (%rsp), %zmm4 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm5 {%k1} -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm3[1],ymm2[1],ymm3[3],ymm2[3] -; AVX512F-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm5, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, %zmm13 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa 128(%rcx), %ymm0 -; AVX512F-ONLY-NEXT: vmovdqa 128(%rdx), %ymm1 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512F-ONLY-NEXT: vmovdqa 128(%rsi), %ymm3 -; AVX512F-ONLY-NEXT: vmovdqa 128(%rdi), %ymm7 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm7[0],ymm3[0],ymm7[2],ymm3[2] -; AVX512F-ONLY-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm8[2,3],ymm2[2,3] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm13, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm2, (%rsp) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 {%k1} -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm7[1],ymm3[1],ymm7[3],ymm3[3] -; AVX512F-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm4, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, %zmm10 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa 192(%rcx), %ymm0 -; AVX512F-ONLY-NEXT: vmovdqa 192(%rdx), %ymm1 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512F-ONLY-NEXT: vmovdqa 192(%rsi), %ymm3 -; AVX512F-ONLY-NEXT: vmovdqa 192(%rdi), %ymm7 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm7[0],ymm3[0],ymm7[2],ymm3[2] -; AVX512F-ONLY-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm8[2,3],ymm2[2,3] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm10, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 {%k1} -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm7[1],ymm3[1],ymm7[3],ymm3[3] -; AVX512F-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm4, %zmm9 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, %zmm26 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa 256(%rcx), %ymm0 -; AVX512F-ONLY-NEXT: vmovdqa 256(%rdx), %ymm1 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512F-ONLY-NEXT: vmovdqa 256(%rsi), %ymm3 -; AVX512F-ONLY-NEXT: vmovdqa 256(%rdi), %ymm7 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm7[0],ymm3[0],ymm7[2],ymm3[2] -; AVX512F-ONLY-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm8[2,3],ymm2[2,3] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm26, %zmm26 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm23, %zmm2 {%k1} -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm7[1],ymm3[1],ymm7[3],ymm3[3] -; AVX512F-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm2, %zmm7 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, %zmm24 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa 320(%rcx), %ymm0 -; AVX512F-ONLY-NEXT: vmovdqa 320(%rdx), %ymm1 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512F-ONLY-NEXT: vmovdqa 320(%rsi), %ymm3 -; AVX512F-ONLY-NEXT: vmovdqa64 320(%rdi), %ymm23 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm23[0],ymm3[0],ymm23[2],ymm3[2] -; AVX512F-ONLY-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm8[2,3],ymm2[2,3] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm24, %zmm8 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm31, %zmm17 {%k1} -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm23[1],ymm3[1],ymm23[3],ymm3[3] -; AVX512F-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm17, %zmm17 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm22, %zmm20 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa 384(%rcx), %ymm0 -; AVX512F-ONLY-NEXT: vmovdqa 384(%rdx), %ymm1 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512F-ONLY-NEXT: vmovdqa 384(%rsi), %ymm3 -; AVX512F-ONLY-NEXT: vmovdqa64 384(%rdi), %ymm18 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm13 = ymm18[0],ymm3[0],ymm18[2],ymm3[2] -; AVX512F-ONLY-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm13[2,3],ymm2[2,3] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm20, %zmm20 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm11, %zmm30 {%k1} -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm18[1],ymm3[1],ymm18[3],ymm3[3] -; AVX512F-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm30, %zmm24 -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm12, %zmm6 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa 448(%rcx), %ymm0 -; AVX512F-ONLY-NEXT: vmovdqa 448(%rdx), %ymm1 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512F-ONLY-NEXT: vmovdqa 448(%rsi), %ymm3 -; AVX512F-ONLY-NEXT: vmovdqa 448(%rdi), %ymm10 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm12 = ymm10[0],ymm3[0],ymm10[2],ymm3[2] -; AVX512F-ONLY-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm12[2,3],ymm2[2,3] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm6, %zmm31 -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm10[1],ymm3[1],ymm10[3],ymm3[3] -; AVX512F-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm16, %zmm19 {%k1} -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm19, %zmm0 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm1, %zmm4 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa (%rsi), %xmm1 -; AVX512F-ONLY-NEXT: vinserti128 $1, (%rcx), %ymm1, %ymm1 -; AVX512F-ONLY-NEXT: vmovdqa (%rdi), %xmm2 -; AVX512F-ONLY-NEXT: vinserti128 $1, (%rdx), %ymm2, %ymm2 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm3 = ymm2[0],ymm1[0],ymm2[2],ymm1[2] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm3, %zmm4, %zmm3 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm10 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, %zmm10 {%k1} -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm2[1],ymm1[1],ymm2[3],ymm1[3] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm10, %zmm2 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm1, %zmm11 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa 64(%rsi), %xmm1 -; AVX512F-ONLY-NEXT: vinserti128 $1, 64(%rcx), %ymm1, %ymm1 -; AVX512F-ONLY-NEXT: vmovdqa 64(%rdi), %xmm4 -; AVX512F-ONLY-NEXT: vinserti128 $1, 64(%rdx), %ymm4, %ymm4 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm10 = ymm4[0],ymm1[0],ymm4[2],ymm1[2] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm11, %zmm10 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm11, %zmm12 {%k1} -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm4[1],ymm1[1],ymm4[3],ymm1[3] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm12, %zmm11 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm1, %zmm13 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa 128(%rsi), %xmm1 -; AVX512F-ONLY-NEXT: vinserti128 $1, 128(%rcx), %ymm1, %ymm1 -; AVX512F-ONLY-NEXT: vmovdqa 128(%rdi), %xmm4 -; AVX512F-ONLY-NEXT: vinserti128 $1, 128(%rdx), %ymm4, %ymm12 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm4 = ymm12[0],ymm1[0],ymm12[2],ymm1[2] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm13, %zmm4 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm18 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm13, %zmm18 {%k1} -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm12[1],ymm1[1],ymm12[3],ymm1[3] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm18, %zmm19 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm18 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm1, %zmm18 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa 192(%rsi), %xmm1 -; AVX512F-ONLY-NEXT: vinserti128 $1, 192(%rcx), %ymm1, %ymm1 -; AVX512F-ONLY-NEXT: vmovdqa 192(%rdi), %xmm12 -; AVX512F-ONLY-NEXT: vinserti128 $1, 192(%rdx), %ymm12, %ymm12 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm13 = ymm12[0],ymm1[0],ymm12[2],ymm1[2] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm13, %zmm18, %zmm30 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm18 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm13, %zmm18 {%k1} -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm12[1],ymm1[1],ymm12[3],ymm1[3] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm18, %zmm1 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm12, %zmm5 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa 256(%rsi), %xmm12 -; AVX512F-ONLY-NEXT: vinserti128 $1, 256(%rcx), %ymm12, %ymm13 -; AVX512F-ONLY-NEXT: vmovdqa 256(%rdi), %xmm12 -; AVX512F-ONLY-NEXT: vinserti32x4 $1, 256(%rdx), %ymm12, %ymm18 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm12 = ymm18[0],ymm13[0],ymm18[2],ymm13[2] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm12, %zmm5, %zmm12 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm23 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm23, %zmm5 {%k1} -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm13 = ymm18[1],ymm13[1],ymm18[3],ymm13[3] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm13, %zmm5, %zmm23 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm5, %zmm29 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa 320(%rsi), %xmm13 -; AVX512F-ONLY-NEXT: vinserti128 $1, 320(%rcx), %ymm13, %ymm13 -; AVX512F-ONLY-NEXT: vmovdqa64 320(%rdi), %xmm18 -; AVX512F-ONLY-NEXT: vinserti32x4 $1, 320(%rdx), %ymm18, %ymm18 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm27 = ymm18[0],ymm13[0],ymm18[2],ymm13[2] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm27, %zmm29, %zmm22 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm5, %zmm6 {%k1} -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm13 = ymm18[1],ymm13[1],ymm18[3],ymm13[3] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm13, %zmm6, %zmm13 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm5, %zmm21 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa64 384(%rsi), %xmm18 -; AVX512F-ONLY-NEXT: vinserti32x4 $1, 384(%rcx), %ymm18, %ymm18 -; AVX512F-ONLY-NEXT: vmovdqa64 384(%rdi), %xmm25 -; AVX512F-ONLY-NEXT: vinserti32x4 $1, 384(%rdx), %ymm25, %ymm25 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm27 = ymm25[0],ymm18[0],ymm25[2],ymm18[2] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm27, %zmm21, %zmm16 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm5, %zmm28 {%k1} -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm18 = ymm25[1],ymm18[1],ymm25[3],ymm18[3] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm18, %zmm28, %zmm21 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm5, %zmm15 {%k1} -; AVX512F-ONLY-NEXT: vmovdqa64 448(%rsi), %xmm18 -; AVX512F-ONLY-NEXT: vinserti32x4 $1, 448(%rcx), %ymm18, %ymm18 -; AVX512F-ONLY-NEXT: vmovdqa64 448(%rdi), %xmm25 -; AVX512F-ONLY-NEXT: vinserti32x4 $1, 448(%rdx), %ymm25, %ymm25 -; AVX512F-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm27 = ymm25[0],ymm18[0],ymm25[2],ymm18[2] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm27, %zmm15, %zmm6 -; AVX512F-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm5, %zmm14 {%k1} -; AVX512F-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm18 = ymm25[1],ymm18[1],ymm25[3],ymm18[3] -; AVX512F-ONLY-NEXT: vinserti64x4 $0, %ymm18, %zmm14, %zmm5 -; AVX512F-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm0, 3776(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm31, 3712(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm24, 3264(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm20, 3200(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm17, 2752(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm8, 2688(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm7, 2240(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm26, 2176(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm9, 1728(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 1664(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 1216(%rax) -; AVX512F-ONLY-NEXT: vmovups (%rsp), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 1152(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 704(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 640(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 192(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 128(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 4032(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 3968(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 3904(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 3840(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm5, 3648(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm6, 3584(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 3520(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 3456(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 3392(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 3328(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm21, 3136(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm16, 3072(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 3008(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 2944(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 2880(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 2816(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm13, 2624(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm22, 2560(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 2496(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 2432(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 2368(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 2304(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm23, 2112(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm12, 2048(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 1984(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 1920(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 1856(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 1792(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm1, 1600(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm30, 1536(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 1472(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 1408(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 1344(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 1280(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm19, 1088(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm4, 1024(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 960(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 896(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 832(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 768(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm11, 576(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm10, 512(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 448(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 384(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 320(%rax) -; AVX512F-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-NEXT: vmovaps %zmm0, 256(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm2, 64(%rax) -; AVX512F-ONLY-NEXT: vmovdqa64 %zmm3, (%rax) -; AVX512F-ONLY-NEXT: addq $5512, %rsp # imm = 0x1588 -; AVX512F-ONLY-NEXT: vzeroupper -; AVX512F-ONLY-NEXT: retq -; -; AVX512DQ-ONLY-LABEL: store_i64_stride8_vf64: -; AVX512DQ-ONLY: # %bb.0: -; AVX512DQ-ONLY-NEXT: subq $5512, %rsp # imm = 0x1588 -; AVX512DQ-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQ-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %r10 -; AVX512DQ-ONLY-NEXT: vmovdqa64 128(%rdi), %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqa64 64(%rdi), %zmm4 -; AVX512DQ-ONLY-NEXT: vmovdqa64 (%rdi), %zmm8 -; AVX512DQ-ONLY-NEXT: vmovdqa64 128(%rsi), %zmm17 -; AVX512DQ-ONLY-NEXT: vmovdqa64 64(%rsi), %zmm19 -; AVX512DQ-ONLY-NEXT: vmovdqa64 (%rsi), %zmm22 -; AVX512DQ-ONLY-NEXT: vmovdqa64 64(%rdx), %zmm5 -; AVX512DQ-ONLY-NEXT: vmovdqa64 (%rdx), %zmm10 -; AVX512DQ-ONLY-NEXT: vmovdqa64 64(%rcx), %zmm20 -; AVX512DQ-ONLY-NEXT: vmovdqa64 (%rcx), %zmm11 -; AVX512DQ-ONLY-NEXT: vmovdqa64 (%r8), %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqa64 64(%r8), %zmm25 -; AVX512DQ-ONLY-NEXT: vmovdqa64 128(%r8), %zmm23 -; AVX512DQ-ONLY-NEXT: vmovdqa64 (%r9), %zmm28 -; AVX512DQ-ONLY-NEXT: vmovdqa64 64(%r9), %zmm26 -; AVX512DQ-ONLY-NEXT: vmovdqa64 128(%r9), %zmm24 -; AVX512DQ-ONLY-NEXT: vmovdqa64 (%r10), %zmm21 -; AVX512DQ-ONLY-NEXT: vmovdqa64 64(%r10), %zmm14 -; AVX512DQ-ONLY-NEXT: vmovdqa64 (%rax), %zmm27 -; AVX512DQ-ONLY-NEXT: vmovdqa64 64(%rax), %zmm16 -; AVX512DQ-ONLY-NEXT: movb $-64, %r11b -; AVX512DQ-ONLY-NEXT: kmovw %r11d, %k1 -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm3 = [4,12,4,12,4,12,4,12] -; AVX512DQ-ONLY-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm21, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm27, %zmm3, %zmm0 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm12 = zmm1[0],zmm28[0],zmm1[2],zmm28[2],zmm1[4],zmm28[4],zmm1[6],zmm28[6] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, %zmm12 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm22, %zmm3, %zmm0 -; AVX512DQ-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm6 = [4,12,4,12] -; AVX512DQ-ONLY-NEXT: # ymm6 = mem[0,1,0,1] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm10, %zmm15 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm11, %zmm6, %zmm15 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm15[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm12, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm9 = [5,13,5,13,5,13,5,13] -; AVX512DQ-ONLY-NEXT: # zmm9 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm21, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm27, %zmm9, %zmm0 -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm12 = zmm1[1],zmm28[1],zmm1[3],zmm28[3],zmm1[5],zmm28[5],zmm1[7],zmm28[7] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, %zmm12 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm22, %zmm9, %zmm0 -; AVX512DQ-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm7 = [5,13,5,13] -; AVX512DQ-ONLY-NEXT: # ymm7 = mem[0,1,0,1] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm10, %zmm15 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm11, %zmm7, %zmm15 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm15[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm12, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm13 = [6,14,6,14,6,14,6,14] -; AVX512DQ-ONLY-NEXT: # zmm13 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm1, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm1, %zmm29 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm28, %zmm13, %zmm0 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm0 {%k1} = zmm21[0],zmm27[0],zmm21[2],zmm27[2],zmm21[4],zmm27[4],zmm21[6],zmm27[6] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm8, %zmm12 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm22, %zmm13, %zmm12 -; AVX512DQ-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [6,14,6,14] -; AVX512DQ-ONLY-NEXT: # ymm1 = mem[0,1,0,1] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm10, %zmm15 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm11, %zmm1, %zmm15 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm12 = ymm12[0,1,2,3],ymm15[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm12, %zmm0, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm18 = [7,15,7,15,7,15,7,15] -; AVX512DQ-ONLY-NEXT: # zmm18 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm29, %zmm12 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm28, %zmm18, %zmm12 -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm12 {%k1} = zmm21[1],zmm27[1],zmm21[3],zmm27[3],zmm21[5],zmm27[5],zmm21[7],zmm27[7] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm22, %zmm18, %zmm8 -; AVX512DQ-ONLY-NEXT: vbroadcasti64x2 {{.*#+}} ymm30 = [7,15,7,15] -; AVX512DQ-ONLY-NEXT: # ymm30 = mem[0,1,0,1] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm11, %zmm30, %zmm10 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm8 = ymm8[0,1,2,3],ymm10[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm8, %zmm12, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm14, %zmm8 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm16, %zmm3, %zmm8 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm10 = zmm25[0],zmm26[0],zmm25[2],zmm26[2],zmm25[4],zmm26[4],zmm25[6],zmm26[6] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm8, %zmm10 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm8 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm19, %zmm3, %zmm8 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm5, %zmm11 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm6, %zmm15 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm20, %zmm6, %zmm11 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm8 = ymm8[0,1,2,3],ymm11[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm8, %zmm10, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm14, %zmm8 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm16, %zmm9, %zmm8 -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm10 = zmm25[1],zmm26[1],zmm25[3],zmm26[3],zmm25[5],zmm26[5],zmm25[7],zmm26[7] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm8, %zmm10 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm8 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm19, %zmm9, %zmm8 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm5, %zmm11 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, %zmm12 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm20, %zmm7, %zmm11 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm8 = ymm8[0,1,2,3],ymm11[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm8, %zmm10, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm8 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm19, %zmm13, %zmm8 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm5, %zmm10 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm20, %zmm1, %zmm10 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm8 = ymm8[0,1,2,3],ymm10[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm25, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm25, %zmm10 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm26, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm26, %zmm13, %zmm10 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm14, %zmm11 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm14, (%rsp) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm16, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm10 {%k1} = zmm14[0],zmm16[0],zmm14[2],zmm16[2],zmm14[4],zmm16[4],zmm14[6],zmm16[6] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm8, %zmm10, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 128(%r10), %zmm10 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm19, %zmm18, %zmm4 -; AVX512DQ-ONLY-NEXT: vmovdqa64 128(%rax), %zmm14 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm20, %zmm30, %zmm5 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm25, %zmm6 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm26, %zmm18, %zmm6 -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm6 {%k1} = zmm11[1],zmm16[1],zmm11[3],zmm16[3],zmm11[5],zmm16[5],zmm11[7],zmm16[7] -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3],ymm5[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm6, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm10, %zmm4 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm14, %zmm3, %zmm4 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm5 = zmm23[0],zmm24[0],zmm23[2],zmm24[2],zmm23[4],zmm24[4],zmm23[6],zmm24[6] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm5 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm6 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm17, %zmm3, %zmm6 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm3, %zmm11 -; AVX512DQ-ONLY-NEXT: vmovdqa64 128(%rdx), %zmm4 -; AVX512DQ-ONLY-NEXT: vmovdqa64 128(%rcx), %zmm7 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm8 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm7, %zmm15, %zmm8 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm6 = ymm6[0,1,2,3],ymm8[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm6, %zmm5, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm10, %zmm5 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm14, %zmm9, %zmm5 -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm6 = zmm23[1],zmm24[1],zmm23[3],zmm24[3],zmm23[5],zmm24[5],zmm23[7],zmm24[7] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm5, %zmm6 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm5 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm17, %zmm9, %zmm5 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm8 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm7, %zmm12, %zmm8 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm5 = ymm5[0,1,2,3],ymm8[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm5, %zmm6, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm5 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm17, %zmm13, %zmm5 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm6 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm7, %zmm1, %zmm6 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm5 = ymm5[0,1,2,3],ymm6[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm23, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm23, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm23, %zmm6 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm24, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm24, %zmm13, %zmm6 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm14, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm6 {%k1} = zmm10[0],zmm14[0],zmm10[2],zmm14[2],zmm10[4],zmm14[4],zmm10[6],zmm14[6] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm5, %zmm6, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm17, %zmm18, %zmm2 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm7, %zmm30, %zmm4 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm4[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm24, %zmm18, %zmm3 -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm3 {%k1} = zmm10[1],zmm14[1],zmm10[3],zmm14[3],zmm10[5],zmm14[5],zmm10[7],zmm14[7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm3, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 192(%r10), %zmm10 -; AVX512DQ-ONLY-NEXT: vmovdqa64 192(%rax), %zmm26 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm10, %zmm2 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm26, %zmm11, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqa64 192(%r8), %zmm23 -; AVX512DQ-ONLY-NEXT: vmovdqa64 192(%r9), %zmm29 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm4 = zmm23[0],zmm29[0],zmm23[2],zmm29[2],zmm23[4],zmm29[4],zmm23[6],zmm29[6] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa64 192(%rdi), %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqa64 192(%rsi), %zmm5 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm6 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm11, %zmm6 -; AVX512DQ-ONLY-NEXT: vmovdqa64 192(%rdx), %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqa64 192(%rcx), %zmm7 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm3, %zmm8 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm7, %zmm15, %zmm8 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm6 = ymm6[0,1,2,3],ymm8[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm6, %zmm4, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm10, %zmm4 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm26, %zmm9, %zmm4 -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm6 = zmm23[1],zmm29[1],zmm23[3],zmm29[3],zmm23[5],zmm29[5],zmm23[7],zmm29[7] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm6 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm9, %zmm4 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm3, %zmm8 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm7, %zmm12, %zmm8 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3],ymm8[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm6, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm13, %zmm4 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm3, %zmm6 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm7, %zmm1, %zmm6 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3],ymm6[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm23, %zmm6 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm29, %zmm13, %zmm6 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm6 {%k1} = zmm10[0],zmm26[0],zmm10[2],zmm26[2],zmm10[4],zmm26[4],zmm10[6],zmm26[6] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm6, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm18, %zmm2 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm7, %zmm30, %zmm3 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm3[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm23, %zmm3 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm29, %zmm18, %zmm3 -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm3 {%k1} = zmm10[1],zmm26[1],zmm10[3],zmm26[3],zmm10[5],zmm26[5],zmm10[7],zmm26[7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm3, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 256(%r10), %zmm10 -; AVX512DQ-ONLY-NEXT: vmovdqa64 256(%rax), %zmm22 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm10, %zmm2 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm22, %zmm11, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqa64 256(%r8), %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqa64 256(%r9), %zmm24 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm4 = zmm0[0],zmm24[0],zmm0[2],zmm24[2],zmm0[4],zmm24[4],zmm0[6],zmm24[6] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, %zmm17 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa64 256(%rdi), %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqa64 256(%rsi), %zmm5 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm6 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm11, %zmm6 -; AVX512DQ-ONLY-NEXT: vmovdqa64 256(%rdx), %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqa64 256(%rcx), %zmm7 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm3, %zmm8 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm7, %zmm15, %zmm8 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm6 = ymm6[0,1,2,3],ymm8[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm6, %zmm4, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm10, %zmm4 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm22, %zmm9, %zmm4 -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm6 = zmm17[1],zmm24[1],zmm17[3],zmm24[3],zmm17[5],zmm24[5],zmm17[7],zmm24[7] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm6 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm9, %zmm4 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm3, %zmm8 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm7, %zmm12, %zmm8 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3],ymm8[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm6, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm13, %zmm4 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm3, %zmm6 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm7, %zmm1, %zmm6 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3],ymm6[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm17, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm17, %zmm6 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm24, %zmm13, %zmm6 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm6 {%k1} = zmm10[0],zmm22[0],zmm10[2],zmm22[2],zmm10[4],zmm22[4],zmm10[6],zmm22[6] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm6, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm5, %zmm18, %zmm2 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm7, %zmm30, %zmm3 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm3[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm17, %zmm3 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm24, %zmm18, %zmm3 -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm3 {%k1} = zmm10[1],zmm22[1],zmm10[3],zmm22[3],zmm10[5],zmm22[5],zmm10[7],zmm22[7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm3, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 320(%rdi), %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqa64 320(%rsi), %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm5 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm3, %zmm11, %zmm5 -; AVX512DQ-ONLY-NEXT: vmovdqa64 320(%rdx), %zmm14 -; AVX512DQ-ONLY-NEXT: vmovdqa64 320(%rcx), %zmm6 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm14, %zmm7 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm6, %zmm15, %zmm7 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm5 = ymm5[0,1,2,3],ymm7[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm14, %zmm7 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm6, %zmm12, %zmm7 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm14, %zmm8 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm6, %zmm1, %zmm8 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm6, %zmm30, %zmm14 -; AVX512DQ-ONLY-NEXT: vmovdqa64 384(%rdx), %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqa64 384(%rcx), %zmm6 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, %zmm10 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm6, %zmm15, %zmm10 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, %zmm10 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm6, %zmm12, %zmm10 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, %zmm10 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm6, %zmm1, %zmm10 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm6, %zmm30, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 448(%rdx), %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqa64 448(%rcx), %zmm6 -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm6, %zmm0, %zmm15 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm15, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm6, %zmm0, %zmm12 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm6, %zmm0, %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm6, %zmm30, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 320(%r10), %zmm31 -; AVX512DQ-ONLY-NEXT: vmovdqa64 320(%rax), %zmm12 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm31, %zmm1 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm12, %zmm11, %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqa64 320(%r8), %zmm17 -; AVX512DQ-ONLY-NEXT: vmovdqa64 320(%r9), %zmm4 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm10 = zmm17[0],zmm4[0],zmm17[2],zmm4[2],zmm17[4],zmm4[4],zmm17[6],zmm4[6] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm1, %zmm10 {%k1} -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm5, %zmm10, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm31, %zmm1 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm12, %zmm9, %zmm1 -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm5 = zmm17[1],zmm4[1],zmm17[3],zmm4[3],zmm17[5],zmm4[5],zmm17[7],zmm4[7] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm1, %zmm5 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm1 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm3, %zmm9, %zmm1 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm7[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm5, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm1 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm3, %zmm13, %zmm1 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm8[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm17, %zmm5 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm4, %zmm13, %zmm5 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm5 {%k1} = zmm31[0],zmm12[0],zmm31[2],zmm12[2],zmm31[4],zmm12[4],zmm31[6],zmm12[6] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm5, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm3, %zmm18, %zmm2 -; AVX512DQ-ONLY-NEXT: vpblendd {{.*#+}} ymm1 = ymm2[0,1,2,3],ymm14[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm17, %zmm2 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm4, %zmm18, %zmm2 -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm2 {%k1} = zmm31[1],zmm12[1],zmm31[3],zmm12[3],zmm31[5],zmm12[5],zmm31[7],zmm12[7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm2, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 384(%rdi), %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqa64 384(%rsi), %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm11, %zmm2 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm11, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, %zmm3 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm9, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, %zmm3 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm13, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm18, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 384(%r10), %zmm11 -; AVX512DQ-ONLY-NEXT: vmovdqa64 384(%rax), %zmm20 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm11, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm20, %zmm2, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm11, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm20, %zmm9, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 384(%r8), %zmm30 -; AVX512DQ-ONLY-NEXT: vmovdqa64 384(%r9), %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm30, %zmm1 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm0, %zmm13, %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 448(%r10), %zmm16 -; AVX512DQ-ONLY-NEXT: vmovdqa64 448(%rax), %zmm8 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm16, %zmm1 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm8, %zmm2, %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 448(%rdi), %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqa64 448(%rsi), %zmm1 -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm1, %zmm3, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm16, %zmm2 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm8, %zmm9, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm1, %zmm3, %zmm9 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 448(%r8), %zmm19 -; AVX512DQ-ONLY-NEXT: vmovdqa64 448(%r9), %zmm7 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm19, %zmm2 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm7, %zmm13, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm1, %zmm3, %zmm13 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm1, %zmm18, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm30, %zmm1 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm0, %zmm18, %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm1, %zmm5 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm19, %zmm1 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm7, %zmm18, %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm15 = [0,8,0,8,0,8,0,8] -; AVX512DQ-ONLY-NEXT: # zmm15 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm21, %zmm1 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm27, %zmm15, %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm14 = [1,9,1,9,1,9,1,9] -; AVX512DQ-ONLY-NEXT: # zmm14 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm21, %zmm1 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm27, %zmm14, %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm6 = [2,10,2,10,2,10,2,10] -; AVX512DQ-ONLY-NEXT: # zmm6 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm21, %zmm1 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm27, %zmm6, %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm1 = [3,11,3,11,3,11,3,11] -; AVX512DQ-ONLY-NEXT: # zmm1 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm27, %zmm1, %zmm21 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm21, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm28, %zmm15, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm28, %zmm14, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm25 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm28, %zmm6, %zmm25 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm28, %zmm1, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 (%rsp), %zmm27 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm27, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm3, %zmm15, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm27, %zmm2 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm3, %zmm14, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm27, %zmm2 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm3, %zmm6, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm3, %zmm1, %zmm27 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm27, (%rsp) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm9, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm2, %zmm15, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm9, %zmm3 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm2, %zmm14, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm9, %zmm18 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm2, %zmm6, %zmm18 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm2, %zmm1, %zmm9 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm9, %zmm15, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm9, %zmm14, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm9, %zmm6, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm9, %zmm1, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm9, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm2, %zmm15, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm9, %zmm3 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm2, %zmm14, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm9, %zmm13 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm2, %zmm6, %zmm13 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm2, %zmm1, %zmm9 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm26, %zmm15, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm26, %zmm14, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm26, %zmm6, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm26, %zmm1, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm23, %zmm3 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm29, %zmm15, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm23, %zmm3 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm29, %zmm14, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm23, %zmm10 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm29, %zmm6, %zmm10 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm29, %zmm1, %zmm23 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm23, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm23 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm23, %zmm2 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm22, %zmm15, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm23, %zmm2 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm22, %zmm14, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm23, %zmm2 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm22, %zmm6, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm22, %zmm1, %zmm23 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm24, %zmm15, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm24, %zmm14, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm26 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm24, %zmm6, %zmm26 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm24, %zmm1, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm31, %zmm2 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm12, %zmm15, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm31, %zmm2 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm12, %zmm14, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm31, %zmm2 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm12, %zmm6, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm12, %zmm1, %zmm31 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm17, %zmm29 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm4, %zmm15, %zmm29 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm17, %zmm2 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm4, %zmm14, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm17, %zmm24 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm4, %zmm6, %zmm24 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm4, %zmm1, %zmm17 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm11, %zmm2 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm20, %zmm15, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm11, %zmm2 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm20, %zmm14, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm9 {%k1} = zmm11[0],zmm20[0],zmm11[2],zmm20[2],zmm11[4],zmm20[4],zmm11[6],zmm20[6] -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm5 {%k1} = zmm11[1],zmm20[1],zmm11[3],zmm20[3],zmm11[5],zmm20[5],zmm11[7],zmm20[7] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm5, %zmm27 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm11, %zmm22 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm20, %zmm6, %zmm22 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm20, %zmm1, %zmm11 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm30, %zmm21 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm0, %zmm15, %zmm21 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm30, %zmm28 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm0, %zmm14, %zmm28 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm30, %zmm20 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm0, %zmm6, %zmm20 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm2 = zmm30[0],zmm0[0],zmm30[2],zmm0[2],zmm30[4],zmm0[4],zmm30[6],zmm0[6] -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm3 = zmm30[1],zmm0[1],zmm30[3],zmm0[3],zmm30[5],zmm0[5],zmm30[7],zmm0[7] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm0, %zmm1, %zmm30 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm16, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm8, %zmm15, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm16, %zmm0 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm8, %zmm14, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm4 {%k1} = zmm16[0],zmm8[0],zmm16[2],zmm8[2],zmm16[4],zmm8[4],zmm16[6],zmm8[6] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm5 {%k1} = zmm16[1],zmm8[1],zmm16[3],zmm8[3],zmm16[5],zmm8[5],zmm16[7],zmm8[7] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm16, %zmm12 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm8, %zmm6, %zmm12 -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm8, %zmm1, %zmm16 -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm7, %zmm19, %zmm15 -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm7, %zmm19, %zmm14 -; AVX512DQ-ONLY-NEXT: vpermi2q %zmm7, %zmm19, %zmm6 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm8 = zmm19[0],zmm7[0],zmm19[2],zmm7[2],zmm19[4],zmm7[4],zmm19[6],zmm7[6] -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm0 = zmm19[1],zmm7[1],zmm19[3],zmm7[3],zmm19[5],zmm7[5],zmm19[7],zmm7[7] -; AVX512DQ-ONLY-NEXT: vpermt2q %zmm7, %zmm1, %zmm19 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, %zmm2 {%k1} -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm2, %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 {%k1} -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm3, %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm9, %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm27, %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm8 {%k1} -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm8, %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm0 {%k1} -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm0, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 32-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # ymm0 = ymm0[0,1,2,3],mem[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm4, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 32-byte Folded Reload -; AVX512DQ-ONLY-NEXT: # ymm0 = ymm0[0,1,2,3],mem[4,5,6,7] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm5, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, %zmm25 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa (%rcx), %ymm0 -; AVX512DQ-ONLY-NEXT: vmovdqa (%rdx), %ymm1 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512DQ-ONLY-NEXT: vmovdqa (%rsi), %ymm3 -; AVX512DQ-ONLY-NEXT: vmovdqa (%rdi), %ymm7 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm7[0],ymm3[0],ymm7[2],ymm3[2] -; AVX512DQ-ONLY-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm8[2,3],ymm2[2,3] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm25, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 {%k1} -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm7[1],ymm3[1],ymm7[3],ymm3[3] -; AVX512DQ-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm4, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, %zmm18 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa 64(%rcx), %ymm0 -; AVX512DQ-ONLY-NEXT: vmovdqa 64(%rdx), %ymm1 -; AVX512DQ-ONLY-NEXT: vmovdqa 64(%rsi), %ymm2 -; AVX512DQ-ONLY-NEXT: vmovdqa 64(%rdi), %ymm3 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm7 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm3[0],ymm2[0],ymm3[2],ymm2[2] -; AVX512DQ-ONLY-NEXT: vperm2i128 {{.*#+}} ymm7 = ymm8[2,3],ymm7[2,3] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm7, %zmm18, %zmm4 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 (%rsp), %zmm4 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm5 {%k1} -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm3[1],ymm2[1],ymm3[3],ymm2[3] -; AVX512DQ-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm5, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, %zmm13 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa 128(%rcx), %ymm0 -; AVX512DQ-ONLY-NEXT: vmovdqa 128(%rdx), %ymm1 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512DQ-ONLY-NEXT: vmovdqa 128(%rsi), %ymm3 -; AVX512DQ-ONLY-NEXT: vmovdqa 128(%rdi), %ymm7 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm7[0],ymm3[0],ymm7[2],ymm3[2] -; AVX512DQ-ONLY-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm8[2,3],ymm2[2,3] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm13, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm2, (%rsp) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 {%k1} -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm7[1],ymm3[1],ymm7[3],ymm3[3] -; AVX512DQ-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm4, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, %zmm10 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa 192(%rcx), %ymm0 -; AVX512DQ-ONLY-NEXT: vmovdqa 192(%rdx), %ymm1 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512DQ-ONLY-NEXT: vmovdqa 192(%rsi), %ymm3 -; AVX512DQ-ONLY-NEXT: vmovdqa 192(%rdi), %ymm7 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm7[0],ymm3[0],ymm7[2],ymm3[2] -; AVX512DQ-ONLY-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm8[2,3],ymm2[2,3] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm10, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 {%k1} -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm7[1],ymm3[1],ymm7[3],ymm3[3] -; AVX512DQ-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm4, %zmm9 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, %zmm26 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa 256(%rcx), %ymm0 -; AVX512DQ-ONLY-NEXT: vmovdqa 256(%rdx), %ymm1 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512DQ-ONLY-NEXT: vmovdqa 256(%rsi), %ymm3 -; AVX512DQ-ONLY-NEXT: vmovdqa 256(%rdi), %ymm7 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm7[0],ymm3[0],ymm7[2],ymm3[2] -; AVX512DQ-ONLY-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm8[2,3],ymm2[2,3] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm26, %zmm26 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm23, %zmm2 {%k1} -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm7[1],ymm3[1],ymm7[3],ymm3[3] -; AVX512DQ-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm2, %zmm7 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, %zmm24 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa 320(%rcx), %ymm0 -; AVX512DQ-ONLY-NEXT: vmovdqa 320(%rdx), %ymm1 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512DQ-ONLY-NEXT: vmovdqa 320(%rsi), %ymm3 -; AVX512DQ-ONLY-NEXT: vmovdqa64 320(%rdi), %ymm23 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm23[0],ymm3[0],ymm23[2],ymm3[2] -; AVX512DQ-ONLY-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm8[2,3],ymm2[2,3] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm24, %zmm8 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm31, %zmm17 {%k1} -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm23[1],ymm3[1],ymm23[3],ymm3[3] -; AVX512DQ-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm17, %zmm17 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm22, %zmm20 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa 384(%rcx), %ymm0 -; AVX512DQ-ONLY-NEXT: vmovdqa 384(%rdx), %ymm1 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512DQ-ONLY-NEXT: vmovdqa 384(%rsi), %ymm3 -; AVX512DQ-ONLY-NEXT: vmovdqa64 384(%rdi), %ymm18 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm13 = ymm18[0],ymm3[0],ymm18[2],ymm3[2] -; AVX512DQ-ONLY-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm13[2,3],ymm2[2,3] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm20, %zmm20 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm11, %zmm30 {%k1} -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm18[1],ymm3[1],ymm18[3],ymm3[3] -; AVX512DQ-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm30, %zmm24 -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm12, %zmm6 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa 448(%rcx), %ymm0 -; AVX512DQ-ONLY-NEXT: vmovdqa 448(%rdx), %ymm1 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512DQ-ONLY-NEXT: vmovdqa 448(%rsi), %ymm3 -; AVX512DQ-ONLY-NEXT: vmovdqa 448(%rdi), %ymm10 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm12 = ymm10[0],ymm3[0],ymm10[2],ymm3[2] -; AVX512DQ-ONLY-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm12[2,3],ymm2[2,3] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm6, %zmm31 -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm10[1],ymm3[1],ymm10[3],ymm3[3] -; AVX512DQ-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm16, %zmm19 {%k1} -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm19, %zmm0 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm1, %zmm4 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa (%rsi), %xmm1 -; AVX512DQ-ONLY-NEXT: vinserti128 $1, (%rcx), %ymm1, %ymm1 -; AVX512DQ-ONLY-NEXT: vmovdqa (%rdi), %xmm2 -; AVX512DQ-ONLY-NEXT: vinserti128 $1, (%rdx), %ymm2, %ymm2 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm3 = ymm2[0],ymm1[0],ymm2[2],ymm1[2] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm3, %zmm4, %zmm3 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm10 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, %zmm10 {%k1} -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm2[1],ymm1[1],ymm2[3],ymm1[3] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm10, %zmm2 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm1, %zmm11 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa 64(%rsi), %xmm1 -; AVX512DQ-ONLY-NEXT: vinserti128 $1, 64(%rcx), %ymm1, %ymm1 -; AVX512DQ-ONLY-NEXT: vmovdqa 64(%rdi), %xmm4 -; AVX512DQ-ONLY-NEXT: vinserti128 $1, 64(%rdx), %ymm4, %ymm4 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm10 = ymm4[0],ymm1[0],ymm4[2],ymm1[2] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm11, %zmm10 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm11, %zmm12 {%k1} -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm4[1],ymm1[1],ymm4[3],ymm1[3] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm12, %zmm11 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm1, %zmm13 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa 128(%rsi), %xmm1 -; AVX512DQ-ONLY-NEXT: vinserti128 $1, 128(%rcx), %ymm1, %ymm1 -; AVX512DQ-ONLY-NEXT: vmovdqa 128(%rdi), %xmm4 -; AVX512DQ-ONLY-NEXT: vinserti128 $1, 128(%rdx), %ymm4, %ymm12 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm4 = ymm12[0],ymm1[0],ymm12[2],ymm1[2] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm13, %zmm4 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm18 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm13, %zmm18 {%k1} -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm12[1],ymm1[1],ymm12[3],ymm1[3] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm18, %zmm19 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm18 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm1, %zmm18 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa 192(%rsi), %xmm1 -; AVX512DQ-ONLY-NEXT: vinserti128 $1, 192(%rcx), %ymm1, %ymm1 -; AVX512DQ-ONLY-NEXT: vmovdqa 192(%rdi), %xmm12 -; AVX512DQ-ONLY-NEXT: vinserti128 $1, 192(%rdx), %ymm12, %ymm12 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm13 = ymm12[0],ymm1[0],ymm12[2],ymm1[2] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm13, %zmm18, %zmm30 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm18 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm13, %zmm18 {%k1} -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm12[1],ymm1[1],ymm12[3],ymm1[3] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm18, %zmm1 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm12, %zmm5 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa 256(%rsi), %xmm12 -; AVX512DQ-ONLY-NEXT: vinserti128 $1, 256(%rcx), %ymm12, %ymm13 -; AVX512DQ-ONLY-NEXT: vmovdqa 256(%rdi), %xmm12 -; AVX512DQ-ONLY-NEXT: vinserti32x4 $1, 256(%rdx), %ymm12, %ymm18 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm12 = ymm18[0],ymm13[0],ymm18[2],ymm13[2] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm12, %zmm5, %zmm12 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm23 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm23, %zmm5 {%k1} -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm13 = ymm18[1],ymm13[1],ymm18[3],ymm13[3] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm13, %zmm5, %zmm23 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm5, %zmm29 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa 320(%rsi), %xmm13 -; AVX512DQ-ONLY-NEXT: vinserti128 $1, 320(%rcx), %ymm13, %ymm13 -; AVX512DQ-ONLY-NEXT: vmovdqa64 320(%rdi), %xmm18 -; AVX512DQ-ONLY-NEXT: vinserti32x4 $1, 320(%rdx), %ymm18, %ymm18 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm27 = ymm18[0],ymm13[0],ymm18[2],ymm13[2] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm27, %zmm29, %zmm22 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm5, %zmm6 {%k1} -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm13 = ymm18[1],ymm13[1],ymm18[3],ymm13[3] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm13, %zmm6, %zmm13 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm5, %zmm21 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa64 384(%rsi), %xmm18 -; AVX512DQ-ONLY-NEXT: vinserti32x4 $1, 384(%rcx), %ymm18, %ymm18 -; AVX512DQ-ONLY-NEXT: vmovdqa64 384(%rdi), %xmm25 -; AVX512DQ-ONLY-NEXT: vinserti32x4 $1, 384(%rdx), %ymm25, %ymm25 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm27 = ymm25[0],ymm18[0],ymm25[2],ymm18[2] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm27, %zmm21, %zmm16 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm5, %zmm28 {%k1} -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm18 = ymm25[1],ymm18[1],ymm25[3],ymm18[3] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm18, %zmm28, %zmm21 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm5, %zmm15 {%k1} -; AVX512DQ-ONLY-NEXT: vmovdqa64 448(%rsi), %xmm18 -; AVX512DQ-ONLY-NEXT: vinserti32x4 $1, 448(%rcx), %ymm18, %ymm18 -; AVX512DQ-ONLY-NEXT: vmovdqa64 448(%rdi), %xmm25 -; AVX512DQ-ONLY-NEXT: vinserti32x4 $1, 448(%rdx), %ymm25, %ymm25 -; AVX512DQ-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm27 = ymm25[0],ymm18[0],ymm25[2],ymm18[2] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm27, %zmm15, %zmm6 -; AVX512DQ-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm5, %zmm14 {%k1} -; AVX512DQ-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm18 = ymm25[1],ymm18[1],ymm25[3],ymm18[3] -; AVX512DQ-ONLY-NEXT: vinserti64x4 $0, %ymm18, %zmm14, %zmm5 -; AVX512DQ-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm0, 3776(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm31, 3712(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm24, 3264(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm20, 3200(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm17, 2752(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm8, 2688(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm7, 2240(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm26, 2176(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm9, 1728(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 1664(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 1216(%rax) -; AVX512DQ-ONLY-NEXT: vmovups (%rsp), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 1152(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 704(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 640(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 192(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 128(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 4032(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 3968(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 3904(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 3840(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm5, 3648(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm6, 3584(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 3520(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 3456(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 3392(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 3328(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm21, 3136(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm16, 3072(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 3008(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 2944(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 2880(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 2816(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm13, 2624(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm22, 2560(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 2496(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 2432(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 2368(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 2304(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm23, 2112(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm12, 2048(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 1984(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 1920(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 1856(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 1792(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm1, 1600(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm30, 1536(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 1472(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 1408(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 1344(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 1280(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm19, 1088(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm4, 1024(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 960(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 896(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 832(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 768(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm11, 576(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm10, 512(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 448(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 384(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 320(%rax) -; AVX512DQ-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-ONLY-NEXT: vmovaps %zmm0, 256(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm2, 64(%rax) -; AVX512DQ-ONLY-NEXT: vmovdqa64 %zmm3, (%rax) -; AVX512DQ-ONLY-NEXT: addq $5512, %rsp # imm = 0x1588 -; AVX512DQ-ONLY-NEXT: vzeroupper -; AVX512DQ-ONLY-NEXT: retq -; -; AVX512BW-ONLY-LABEL: store_i64_stride8_vf64: -; AVX512BW-ONLY: # %bb.0: -; AVX512BW-ONLY-NEXT: subq $5512, %rsp # imm = 0x1588 -; AVX512BW-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512BW-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %r10 -; AVX512BW-ONLY-NEXT: vmovdqa64 128(%rdi), %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%rdi), %zmm4 -; AVX512BW-ONLY-NEXT: vmovdqa64 (%rdi), %zmm8 -; AVX512BW-ONLY-NEXT: vmovdqa64 128(%rsi), %zmm17 -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%rsi), %zmm19 -; AVX512BW-ONLY-NEXT: vmovdqa64 (%rsi), %zmm22 -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%rdx), %zmm5 -; AVX512BW-ONLY-NEXT: vmovdqa64 (%rdx), %zmm10 -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%rcx), %zmm20 -; AVX512BW-ONLY-NEXT: vmovdqa64 (%rcx), %zmm11 -; AVX512BW-ONLY-NEXT: vmovdqa64 (%r8), %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%r8), %zmm25 -; AVX512BW-ONLY-NEXT: vmovdqa64 128(%r8), %zmm23 -; AVX512BW-ONLY-NEXT: vmovdqa64 (%r9), %zmm28 -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%r9), %zmm26 -; AVX512BW-ONLY-NEXT: vmovdqa64 128(%r9), %zmm24 -; AVX512BW-ONLY-NEXT: vmovdqa64 (%r10), %zmm21 -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%r10), %zmm14 -; AVX512BW-ONLY-NEXT: vmovdqa64 (%rax), %zmm27 -; AVX512BW-ONLY-NEXT: vmovdqa64 64(%rax), %zmm16 -; AVX512BW-ONLY-NEXT: movb $-64, %r11b -; AVX512BW-ONLY-NEXT: kmovd %r11d, %k1 -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm3 = [4,12,4,12,4,12,4,12] -; AVX512BW-ONLY-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm21, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm27, %zmm3, %zmm0 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm12 = zmm1[0],zmm28[0],zmm1[2],zmm28[2],zmm1[4],zmm28[4],zmm1[6],zmm28[6] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm12 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm3, %zmm0 -; AVX512BW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm6 = [4,12,4,12] -; AVX512BW-ONLY-NEXT: # ymm6 = mem[0,1,0,1] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm15 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm11, %zmm6, %zmm15 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm15[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm12, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm9 = [5,13,5,13,5,13,5,13] -; AVX512BW-ONLY-NEXT: # zmm9 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm21, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm27, %zmm9, %zmm0 -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm12 = zmm1[1],zmm28[1],zmm1[3],zmm28[3],zmm1[5],zmm28[5],zmm1[7],zmm28[7] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm12 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm9, %zmm0 -; AVX512BW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm7 = [5,13,5,13] -; AVX512BW-ONLY-NEXT: # ymm7 = mem[0,1,0,1] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm15 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm11, %zmm7, %zmm15 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm15[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm12, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm13 = [6,14,6,14,6,14,6,14] -; AVX512BW-ONLY-NEXT: # zmm13 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm1, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm1, %zmm29 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm28, %zmm13, %zmm0 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm0 {%k1} = zmm21[0],zmm27[0],zmm21[2],zmm27[2],zmm21[4],zmm27[4],zmm21[6],zmm27[6] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm8, %zmm12 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm13, %zmm12 -; AVX512BW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [6,14,6,14] -; AVX512BW-ONLY-NEXT: # ymm1 = mem[0,1,0,1] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm15 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm11, %zmm1, %zmm15 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm12 = ymm12[0,1,2,3],ymm15[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm12, %zmm0, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm18 = [7,15,7,15,7,15,7,15] -; AVX512BW-ONLY-NEXT: # zmm18 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm12 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm28, %zmm18, %zmm12 -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm12 {%k1} = zmm21[1],zmm27[1],zmm21[3],zmm27[3],zmm21[5],zmm27[5],zmm21[7],zmm27[7] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm18, %zmm8 -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} ymm30 = [7,15,7,15] -; AVX512BW-ONLY-NEXT: # ymm30 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm11, %zmm30, %zmm10 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm8 = ymm8[0,1,2,3],ymm10[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm8, %zmm12, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm14, %zmm8 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm16, %zmm3, %zmm8 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm10 = zmm25[0],zmm26[0],zmm25[2],zmm26[2],zmm25[4],zmm26[4],zmm25[6],zmm26[6] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm8, %zmm10 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm8 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm19, %zmm3, %zmm8 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm11 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm15 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm20, %zmm6, %zmm11 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm8 = ymm8[0,1,2,3],ymm11[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm8, %zmm10, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm14, %zmm8 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm16, %zmm9, %zmm8 -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm10 = zmm25[1],zmm26[1],zmm25[3],zmm26[3],zmm25[5],zmm26[5],zmm25[7],zmm26[7] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm8, %zmm10 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm8 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm19, %zmm9, %zmm8 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm11 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm12 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm20, %zmm7, %zmm11 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm8 = ymm8[0,1,2,3],ymm11[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm8, %zmm10, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm8 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm19, %zmm13, %zmm8 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm10 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm20, %zmm1, %zmm10 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm8 = ymm8[0,1,2,3],ymm10[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm25, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm10 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm26, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm26, %zmm13, %zmm10 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm14, %zmm11 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm14, (%rsp) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm16, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm10 {%k1} = zmm14[0],zmm16[0],zmm14[2],zmm16[2],zmm14[4],zmm16[4],zmm14[6],zmm16[6] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm8, %zmm10, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 128(%r10), %zmm10 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm19, %zmm18, %zmm4 -; AVX512BW-ONLY-NEXT: vmovdqa64 128(%rax), %zmm14 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm20, %zmm30, %zmm5 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm6 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm26, %zmm18, %zmm6 -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm6 {%k1} = zmm11[1],zmm16[1],zmm11[3],zmm16[3],zmm11[5],zmm16[5],zmm11[7],zmm16[7] -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3],ymm5[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm6, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm4 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm14, %zmm3, %zmm4 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm5 = zmm23[0],zmm24[0],zmm23[2],zmm24[2],zmm23[4],zmm24[4],zmm23[6],zmm24[6] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm5 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm6 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm17, %zmm3, %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm11 -; AVX512BW-ONLY-NEXT: vmovdqa64 128(%rdx), %zmm4 -; AVX512BW-ONLY-NEXT: vmovdqa64 128(%rcx), %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm8 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm15, %zmm8 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm6 = ymm6[0,1,2,3],ymm8[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm6, %zmm5, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm5 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm14, %zmm9, %zmm5 -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm6 = zmm23[1],zmm24[1],zmm23[3],zmm24[3],zmm23[5],zmm24[5],zmm23[7],zmm24[7] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm6 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm5 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm17, %zmm9, %zmm5 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm8 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm12, %zmm8 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm5 = ymm5[0,1,2,3],ymm8[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm5, %zmm6, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm5 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm17, %zmm13, %zmm5 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm6 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm1, %zmm6 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm5 = ymm5[0,1,2,3],ymm6[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm23, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm24, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm24, %zmm13, %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm14, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm6 {%k1} = zmm10[0],zmm14[0],zmm10[2],zmm14[2],zmm10[4],zmm14[4],zmm10[6],zmm14[6] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm5, %zmm6, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm17, %zmm18, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm30, %zmm4 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm4[4,5,6,7] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm24, %zmm18, %zmm3 -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm3 {%k1} = zmm10[1],zmm14[1],zmm10[3],zmm14[3],zmm10[5],zmm14[5],zmm10[7],zmm14[7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm3, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 192(%r10), %zmm10 -; AVX512BW-ONLY-NEXT: vmovdqa64 192(%rax), %zmm26 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm26, %zmm11, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqa64 192(%r8), %zmm23 -; AVX512BW-ONLY-NEXT: vmovdqa64 192(%r9), %zmm29 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm4 = zmm23[0],zmm29[0],zmm23[2],zmm29[2],zmm23[4],zmm29[4],zmm23[6],zmm29[6] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa64 192(%rdi), %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqa64 192(%rsi), %zmm5 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm6 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm5, %zmm11, %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqa64 192(%rdx), %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqa64 192(%rcx), %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm8 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm15, %zmm8 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm6 = ymm6[0,1,2,3],ymm8[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm6, %zmm4, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm4 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm26, %zmm9, %zmm4 -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm6 = zmm23[1],zmm29[1],zmm23[3],zmm29[3],zmm23[5],zmm29[5],zmm23[7],zmm29[7] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm6 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm5, %zmm9, %zmm4 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm8 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm12, %zmm8 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3],ymm8[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm6, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm5, %zmm13, %zmm4 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm6 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm1, %zmm6 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3],ymm6[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm6 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm29, %zmm13, %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm6 {%k1} = zmm10[0],zmm26[0],zmm10[2],zmm26[2],zmm10[4],zmm26[4],zmm10[6],zmm26[6] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm6, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm5, %zmm18, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm30, %zmm3 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm3[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm29, %zmm18, %zmm3 -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm3 {%k1} = zmm10[1],zmm26[1],zmm10[3],zmm26[3],zmm10[5],zmm26[5],zmm10[7],zmm26[7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm3, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 256(%r10), %zmm10 -; AVX512BW-ONLY-NEXT: vmovdqa64 256(%rax), %zmm22 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm11, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqa64 256(%r8), %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqa64 256(%r9), %zmm24 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm4 = zmm0[0],zmm24[0],zmm0[2],zmm24[2],zmm0[4],zmm24[4],zmm0[6],zmm24[6] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm17 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa64 256(%rdi), %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqa64 256(%rsi), %zmm5 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm6 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm5, %zmm11, %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqa64 256(%rdx), %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqa64 256(%rcx), %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm8 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm15, %zmm8 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm6 = ymm6[0,1,2,3],ymm8[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm6, %zmm4, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm4 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm9, %zmm4 -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm6 = zmm17[1],zmm24[1],zmm17[3],zmm24[3],zmm17[5],zmm24[5],zmm17[7],zmm24[7] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm6 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm5, %zmm9, %zmm4 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm8 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm12, %zmm8 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3],ymm8[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm6, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm5, %zmm13, %zmm4 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm6 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm1, %zmm6 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3],ymm6[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm17, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm17, %zmm6 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm24, %zmm13, %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm6 {%k1} = zmm10[0],zmm22[0],zmm10[2],zmm22[2],zmm10[4],zmm22[4],zmm10[6],zmm22[6] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm6, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm5, %zmm18, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm30, %zmm3 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm3[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm17, %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm24, %zmm18, %zmm3 -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm3 {%k1} = zmm10[1],zmm22[1],zmm10[3],zmm22[3],zmm10[5],zmm22[5],zmm10[7],zmm22[7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm3, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 320(%rdi), %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqa64 320(%rsi), %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm5 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm3, %zmm11, %zmm5 -; AVX512BW-ONLY-NEXT: vmovdqa64 320(%rdx), %zmm14 -; AVX512BW-ONLY-NEXT: vmovdqa64 320(%rcx), %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm14, %zmm7 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm6, %zmm15, %zmm7 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm5 = ymm5[0,1,2,3],ymm7[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm14, %zmm7 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm6, %zmm12, %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm14, %zmm8 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm6, %zmm1, %zmm8 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm6, %zmm30, %zmm14 -; AVX512BW-ONLY-NEXT: vmovdqa64 384(%rdx), %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqa64 384(%rcx), %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm10 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm6, %zmm15, %zmm10 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm10 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm6, %zmm12, %zmm10 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm10 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm6, %zmm1, %zmm10 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm6, %zmm30, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 448(%rdx), %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqa64 448(%rcx), %zmm6 -; AVX512BW-ONLY-NEXT: vpermi2q %zmm6, %zmm0, %zmm15 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm15, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermi2q %zmm6, %zmm0, %zmm12 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermi2q %zmm6, %zmm0, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm6, %zmm30, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 320(%r10), %zmm31 -; AVX512BW-ONLY-NEXT: vmovdqa64 320(%rax), %zmm12 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm31, %zmm1 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm12, %zmm11, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqa64 320(%r8), %zmm17 -; AVX512BW-ONLY-NEXT: vmovdqa64 320(%r9), %zmm4 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm10 = zmm17[0],zmm4[0],zmm17[2],zmm4[2],zmm17[4],zmm4[4],zmm17[6],zmm4[6] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm1, %zmm10 {%k1} -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm5, %zmm10, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm31, %zmm1 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm12, %zmm9, %zmm1 -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm5 = zmm17[1],zmm4[1],zmm17[3],zmm4[3],zmm17[5],zmm4[5],zmm17[7],zmm4[7] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm1, %zmm5 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm1 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm3, %zmm9, %zmm1 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm7[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm5, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm1 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm3, %zmm13, %zmm1 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm8[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm17, %zmm5 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm4, %zmm13, %zmm5 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm5 {%k1} = zmm31[0],zmm12[0],zmm31[2],zmm12[2],zmm31[4],zmm12[4],zmm31[6],zmm12[6] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm5, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm3, %zmm18, %zmm2 -; AVX512BW-ONLY-NEXT: vpblendd {{.*#+}} ymm1 = ymm2[0,1,2,3],ymm14[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm17, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm4, %zmm18, %zmm2 -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm2 {%k1} = zmm31[1],zmm12[1],zmm31[3],zmm12[3],zmm31[5],zmm12[5],zmm31[7],zmm12[7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm2, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 384(%rdi), %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqa64 384(%rsi), %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm1, %zmm11, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm1, %zmm9, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm1, %zmm13, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm1, %zmm18, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 384(%r10), %zmm11 -; AVX512BW-ONLY-NEXT: vmovdqa64 384(%rax), %zmm20 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm20, %zmm2, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm20, %zmm9, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 384(%r8), %zmm30 -; AVX512BW-ONLY-NEXT: vmovdqa64 384(%r9), %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm30, %zmm1 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm0, %zmm13, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 448(%r10), %zmm16 -; AVX512BW-ONLY-NEXT: vmovdqa64 448(%rax), %zmm8 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm16, %zmm1 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm8, %zmm2, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 448(%rdi), %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqa64 448(%rsi), %zmm1 -; AVX512BW-ONLY-NEXT: vpermi2q %zmm1, %zmm3, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm16, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm8, %zmm9, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermi2q %zmm1, %zmm3, %zmm9 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 448(%r8), %zmm19 -; AVX512BW-ONLY-NEXT: vmovdqa64 448(%r9), %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm19, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm13, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermi2q %zmm1, %zmm3, %zmm13 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm1, %zmm18, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm30, %zmm1 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm0, %zmm18, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm1, %zmm5 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm19, %zmm1 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm18, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm15 = [0,8,0,8,0,8,0,8] -; AVX512BW-ONLY-NEXT: # zmm15 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm21, %zmm1 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm27, %zmm15, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm14 = [1,9,1,9,1,9,1,9] -; AVX512BW-ONLY-NEXT: # zmm14 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm21, %zmm1 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm27, %zmm14, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm6 = [2,10,2,10,2,10,2,10] -; AVX512BW-ONLY-NEXT: # zmm6 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm21, %zmm1 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm27, %zmm6, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm1 = [3,11,3,11,3,11,3,11] -; AVX512BW-ONLY-NEXT: # zmm1 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm27, %zmm1, %zmm21 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm21, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm28, %zmm15, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm28, %zmm14, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm25 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm28, %zmm6, %zmm25 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm28, %zmm1, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 (%rsp), %zmm27 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm27, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm3, %zmm15, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm27, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm3, %zmm14, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm27, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm3, %zmm6, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm3, %zmm1, %zmm27 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm27, (%rsp) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm9, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm15, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm9, %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm14, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm9, %zmm18 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm6, %zmm18 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm1, %zmm9 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm9, %zmm15, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm9, %zmm14, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm9, %zmm6, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm9, %zmm1, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm9, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm15, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm9, %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm14, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm9, %zmm13 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm6, %zmm13 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm2, %zmm1, %zmm9 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm26, %zmm15, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm26, %zmm14, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm26, %zmm6, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm26, %zmm1, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm29, %zmm15, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm29, %zmm14, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm10 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm29, %zmm6, %zmm10 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm29, %zmm1, %zmm23 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm23, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm23 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm15, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm14, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm6, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm22, %zmm1, %zmm23 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm24, %zmm15, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm24, %zmm14, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm26 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm24, %zmm6, %zmm26 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm24, %zmm1, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm31, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm12, %zmm15, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm31, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm12, %zmm14, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm31, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm12, %zmm6, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vpermt2q %zmm12, %zmm1, %zmm31 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm17, %zmm29 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm4, %zmm15, %zmm29 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm17, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm4, %zmm14, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm17, %zmm24 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm4, %zmm6, %zmm24 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm4, %zmm1, %zmm17 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm20, %zmm15, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm2 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm20, %zmm14, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm9 {%k1} = zmm11[0],zmm20[0],zmm11[2],zmm20[2],zmm11[4],zmm20[4],zmm11[6],zmm20[6] -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm5 {%k1} = zmm11[1],zmm20[1],zmm11[3],zmm20[3],zmm11[5],zmm20[5],zmm11[7],zmm20[7] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm27 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm22 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm20, %zmm6, %zmm22 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm20, %zmm1, %zmm11 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm30, %zmm21 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm0, %zmm15, %zmm21 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm30, %zmm28 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm0, %zmm14, %zmm28 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm30, %zmm20 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm0, %zmm6, %zmm20 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm2 = zmm30[0],zmm0[0],zmm30[2],zmm0[2],zmm30[4],zmm0[4],zmm30[6],zmm0[6] -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm3 = zmm30[1],zmm0[1],zmm30[3],zmm0[3],zmm30[5],zmm0[5],zmm30[7],zmm0[7] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm0, %zmm1, %zmm30 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm16, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm8, %zmm15, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm16, %zmm0 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm8, %zmm14, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm4 {%k1} = zmm16[0],zmm8[0],zmm16[2],zmm8[2],zmm16[4],zmm8[4],zmm16[6],zmm8[6] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm5 {%k1} = zmm16[1],zmm8[1],zmm16[3],zmm8[3],zmm16[5],zmm8[5],zmm16[7],zmm8[7] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm16, %zmm12 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm8, %zmm6, %zmm12 -; AVX512BW-ONLY-NEXT: vpermt2q %zmm8, %zmm1, %zmm16 -; AVX512BW-ONLY-NEXT: vpermi2q %zmm7, %zmm19, %zmm15 -; AVX512BW-ONLY-NEXT: vpermi2q %zmm7, %zmm19, %zmm14 -; AVX512BW-ONLY-NEXT: vpermi2q %zmm7, %zmm19, %zmm6 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm8 = zmm19[0],zmm7[0],zmm19[2],zmm7[2],zmm19[4],zmm7[4],zmm19[6],zmm7[6] -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm0 = zmm19[1],zmm7[1],zmm19[3],zmm7[3],zmm19[5],zmm7[5],zmm19[7],zmm7[7] -; AVX512BW-ONLY-NEXT: vpermt2q %zmm7, %zmm1, %zmm19 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload -; AVX512BW-ONLY-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm2 {%k1} -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm2, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload -; AVX512BW-ONLY-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 {%k1} -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm3, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload -; AVX512BW-ONLY-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm9, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload -; AVX512BW-ONLY-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm27, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload -; AVX512BW-ONLY-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm8 {%k1} -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm8, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload -; AVX512BW-ONLY-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm0 {%k1} -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm0, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 32-byte Folded Reload -; AVX512BW-ONLY-NEXT: # ymm0 = ymm0[0,1,2,3],mem[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm4, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 32-byte Folded Reload -; AVX512BW-ONLY-NEXT: # ymm0 = ymm0[0,1,2,3],mem[4,5,6,7] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm5, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm25 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa (%rcx), %ymm0 -; AVX512BW-ONLY-NEXT: vmovdqa (%rdx), %ymm1 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512BW-ONLY-NEXT: vmovdqa (%rsi), %ymm3 -; AVX512BW-ONLY-NEXT: vmovdqa (%rdi), %ymm7 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm7[0],ymm3[0],ymm7[2],ymm3[2] -; AVX512BW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm8[2,3],ymm2[2,3] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm25, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 {%k1} -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm7[1],ymm3[1],ymm7[3],ymm3[3] -; AVX512BW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm4, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm18 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa 64(%rcx), %ymm0 -; AVX512BW-ONLY-NEXT: vmovdqa 64(%rdx), %ymm1 -; AVX512BW-ONLY-NEXT: vmovdqa 64(%rsi), %ymm2 -; AVX512BW-ONLY-NEXT: vmovdqa 64(%rdi), %ymm3 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm7 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm3[0],ymm2[0],ymm3[2],ymm2[2] -; AVX512BW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm7 = ymm8[2,3],ymm7[2,3] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm7, %zmm18, %zmm4 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 (%rsp), %zmm4 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm5 {%k1} -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm3[1],ymm2[1],ymm3[3],ymm2[3] -; AVX512BW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm5, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm13 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa 128(%rcx), %ymm0 -; AVX512BW-ONLY-NEXT: vmovdqa 128(%rdx), %ymm1 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512BW-ONLY-NEXT: vmovdqa 128(%rsi), %ymm3 -; AVX512BW-ONLY-NEXT: vmovdqa 128(%rdi), %ymm7 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm7[0],ymm3[0],ymm7[2],ymm3[2] -; AVX512BW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm8[2,3],ymm2[2,3] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm13, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm2, (%rsp) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 {%k1} -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm7[1],ymm3[1],ymm7[3],ymm3[3] -; AVX512BW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm4, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm10 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa 192(%rcx), %ymm0 -; AVX512BW-ONLY-NEXT: vmovdqa 192(%rdx), %ymm1 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512BW-ONLY-NEXT: vmovdqa 192(%rsi), %ymm3 -; AVX512BW-ONLY-NEXT: vmovdqa 192(%rdi), %ymm7 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm7[0],ymm3[0],ymm7[2],ymm3[2] -; AVX512BW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm8[2,3],ymm2[2,3] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm10, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 {%k1} -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm7[1],ymm3[1],ymm7[3],ymm3[3] -; AVX512BW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm4, %zmm9 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm26 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa 256(%rcx), %ymm0 -; AVX512BW-ONLY-NEXT: vmovdqa 256(%rdx), %ymm1 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512BW-ONLY-NEXT: vmovdqa 256(%rsi), %ymm3 -; AVX512BW-ONLY-NEXT: vmovdqa 256(%rdi), %ymm7 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm7[0],ymm3[0],ymm7[2],ymm3[2] -; AVX512BW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm8[2,3],ymm2[2,3] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm26, %zmm26 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm2 {%k1} -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm7[1],ymm3[1],ymm7[3],ymm3[3] -; AVX512BW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm2, %zmm7 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm24 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa 320(%rcx), %ymm0 -; AVX512BW-ONLY-NEXT: vmovdqa 320(%rdx), %ymm1 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512BW-ONLY-NEXT: vmovdqa 320(%rsi), %ymm3 -; AVX512BW-ONLY-NEXT: vmovdqa64 320(%rdi), %ymm23 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm23[0],ymm3[0],ymm23[2],ymm3[2] -; AVX512BW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm8[2,3],ymm2[2,3] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm24, %zmm8 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm31, %zmm17 {%k1} -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm23[1],ymm3[1],ymm23[3],ymm3[3] -; AVX512BW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm17, %zmm17 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm22, %zmm20 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa 384(%rcx), %ymm0 -; AVX512BW-ONLY-NEXT: vmovdqa 384(%rdx), %ymm1 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512BW-ONLY-NEXT: vmovdqa 384(%rsi), %ymm3 -; AVX512BW-ONLY-NEXT: vmovdqa64 384(%rdi), %ymm18 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm13 = ymm18[0],ymm3[0],ymm18[2],ymm3[2] -; AVX512BW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm13[2,3],ymm2[2,3] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm20, %zmm20 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm30 {%k1} -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm18[1],ymm3[1],ymm18[3],ymm3[3] -; AVX512BW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm30, %zmm24 -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm6 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa 448(%rcx), %ymm0 -; AVX512BW-ONLY-NEXT: vmovdqa 448(%rdx), %ymm1 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512BW-ONLY-NEXT: vmovdqa 448(%rsi), %ymm3 -; AVX512BW-ONLY-NEXT: vmovdqa 448(%rdi), %ymm10 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm12 = ymm10[0],ymm3[0],ymm10[2],ymm3[2] -; AVX512BW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm12[2,3],ymm2[2,3] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm6, %zmm31 -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm10[1],ymm3[1],ymm10[3],ymm3[3] -; AVX512BW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm16, %zmm19 {%k1} -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm19, %zmm0 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm1, %zmm4 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa (%rsi), %xmm1 -; AVX512BW-ONLY-NEXT: vinserti128 $1, (%rcx), %ymm1, %ymm1 -; AVX512BW-ONLY-NEXT: vmovdqa (%rdi), %xmm2 -; AVX512BW-ONLY-NEXT: vinserti128 $1, (%rdx), %ymm2, %ymm2 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm3 = ymm2[0],ymm1[0],ymm2[2],ymm1[2] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm3, %zmm4, %zmm3 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm10 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm10 {%k1} -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm2[1],ymm1[1],ymm2[3],ymm1[3] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm10, %zmm2 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm1, %zmm11 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa 64(%rsi), %xmm1 -; AVX512BW-ONLY-NEXT: vinserti128 $1, 64(%rcx), %ymm1, %ymm1 -; AVX512BW-ONLY-NEXT: vmovdqa 64(%rdi), %xmm4 -; AVX512BW-ONLY-NEXT: vinserti128 $1, 64(%rdx), %ymm4, %ymm4 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm10 = ymm4[0],ymm1[0],ymm4[2],ymm1[2] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm11, %zmm10 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm12 {%k1} -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm4[1],ymm1[1],ymm4[3],ymm1[3] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm12, %zmm11 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm1, %zmm13 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa 128(%rsi), %xmm1 -; AVX512BW-ONLY-NEXT: vinserti128 $1, 128(%rcx), %ymm1, %ymm1 -; AVX512BW-ONLY-NEXT: vmovdqa 128(%rdi), %xmm4 -; AVX512BW-ONLY-NEXT: vinserti128 $1, 128(%rdx), %ymm4, %ymm12 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm4 = ymm12[0],ymm1[0],ymm12[2],ymm1[2] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm13, %zmm4 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm18 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm13, %zmm18 {%k1} -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm12[1],ymm1[1],ymm12[3],ymm1[3] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm18, %zmm19 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm18 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm1, %zmm18 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa 192(%rsi), %xmm1 -; AVX512BW-ONLY-NEXT: vinserti128 $1, 192(%rcx), %ymm1, %ymm1 -; AVX512BW-ONLY-NEXT: vmovdqa 192(%rdi), %xmm12 -; AVX512BW-ONLY-NEXT: vinserti128 $1, 192(%rdx), %ymm12, %ymm12 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm13 = ymm12[0],ymm1[0],ymm12[2],ymm1[2] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm13, %zmm18, %zmm30 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm18 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm13, %zmm18 {%k1} -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm12[1],ymm1[1],ymm12[3],ymm1[3] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm18, %zmm1 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm5 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa 256(%rsi), %xmm12 -; AVX512BW-ONLY-NEXT: vinserti128 $1, 256(%rcx), %ymm12, %ymm13 -; AVX512BW-ONLY-NEXT: vmovdqa 256(%rdi), %xmm12 -; AVX512BW-ONLY-NEXT: vinserti32x4 $1, 256(%rdx), %ymm12, %ymm18 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm12 = ymm18[0],ymm13[0],ymm18[2],ymm13[2] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm12, %zmm5, %zmm12 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm23 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm5 {%k1} -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm13 = ymm18[1],ymm13[1],ymm18[3],ymm13[3] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm13, %zmm5, %zmm23 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm29 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa 320(%rsi), %xmm13 -; AVX512BW-ONLY-NEXT: vinserti128 $1, 320(%rcx), %ymm13, %ymm13 -; AVX512BW-ONLY-NEXT: vmovdqa64 320(%rdi), %xmm18 -; AVX512BW-ONLY-NEXT: vinserti32x4 $1, 320(%rdx), %ymm18, %ymm18 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm27 = ymm18[0],ymm13[0],ymm18[2],ymm13[2] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm27, %zmm29, %zmm22 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm6 {%k1} -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm13 = ymm18[1],ymm13[1],ymm18[3],ymm13[3] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm13, %zmm6, %zmm13 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm21 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa64 384(%rsi), %xmm18 -; AVX512BW-ONLY-NEXT: vinserti32x4 $1, 384(%rcx), %ymm18, %ymm18 -; AVX512BW-ONLY-NEXT: vmovdqa64 384(%rdi), %xmm25 -; AVX512BW-ONLY-NEXT: vinserti32x4 $1, 384(%rdx), %ymm25, %ymm25 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm27 = ymm25[0],ymm18[0],ymm25[2],ymm18[2] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm27, %zmm21, %zmm16 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm28 {%k1} -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm18 = ymm25[1],ymm18[1],ymm25[3],ymm18[3] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm18, %zmm28, %zmm21 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm15 {%k1} -; AVX512BW-ONLY-NEXT: vmovdqa64 448(%rsi), %xmm18 -; AVX512BW-ONLY-NEXT: vinserti32x4 $1, 448(%rcx), %ymm18, %ymm18 -; AVX512BW-ONLY-NEXT: vmovdqa64 448(%rdi), %xmm25 -; AVX512BW-ONLY-NEXT: vinserti32x4 $1, 448(%rdx), %ymm25, %ymm25 -; AVX512BW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm27 = ymm25[0],ymm18[0],ymm25[2],ymm18[2] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm27, %zmm15, %zmm6 -; AVX512BW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm14 {%k1} -; AVX512BW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm18 = ymm25[1],ymm18[1],ymm25[3],ymm18[3] -; AVX512BW-ONLY-NEXT: vinserti64x4 $0, %ymm18, %zmm14, %zmm5 -; AVX512BW-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm0, 3776(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm31, 3712(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm24, 3264(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm20, 3200(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm17, 2752(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm8, 2688(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm7, 2240(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm26, 2176(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm9, 1728(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 1664(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 1216(%rax) -; AVX512BW-ONLY-NEXT: vmovups (%rsp), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 1152(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 704(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 640(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 192(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 128(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 4032(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 3968(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 3904(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 3840(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm5, 3648(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm6, 3584(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 3520(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 3456(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 3392(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 3328(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm21, 3136(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm16, 3072(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 3008(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 2944(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 2880(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 2816(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm13, 2624(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm22, 2560(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 2496(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 2432(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 2368(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 2304(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm23, 2112(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm12, 2048(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 1984(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 1920(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 1856(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 1792(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm1, 1600(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm30, 1536(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 1472(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 1408(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 1344(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 1280(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm19, 1088(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm4, 1024(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 960(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 896(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 832(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 768(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm11, 576(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm10, 512(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 448(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 384(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 320(%rax) -; AVX512BW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512BW-ONLY-NEXT: vmovaps %zmm0, 256(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm2, 64(%rax) -; AVX512BW-ONLY-NEXT: vmovdqa64 %zmm3, (%rax) -; AVX512BW-ONLY-NEXT: addq $5512, %rsp # imm = 0x1588 -; AVX512BW-ONLY-NEXT: vzeroupper -; AVX512BW-ONLY-NEXT: retq +; AVX512F-LABEL: store_i64_stride8_vf64: +; AVX512F: # %bb.0: +; AVX512F-NEXT: subq $5512, %rsp # imm = 0x1588 +; AVX512F-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512F-NEXT: movq {{[0-9]+}}(%rsp), %r10 +; AVX512F-NEXT: vmovdqa64 128(%rdi), %zmm2 +; AVX512F-NEXT: vmovdqa64 64(%rdi), %zmm4 +; AVX512F-NEXT: vmovdqa64 (%rdi), %zmm8 +; AVX512F-NEXT: vmovdqa64 128(%rsi), %zmm17 +; AVX512F-NEXT: vmovdqa64 64(%rsi), %zmm19 +; AVX512F-NEXT: vmovdqa64 (%rsi), %zmm22 +; AVX512F-NEXT: vmovdqa64 64(%rdx), %zmm5 +; AVX512F-NEXT: vmovdqa64 (%rdx), %zmm10 +; AVX512F-NEXT: vmovdqa64 64(%rcx), %zmm20 +; AVX512F-NEXT: vmovdqa64 (%rcx), %zmm11 +; AVX512F-NEXT: vmovdqa64 (%r8), %zmm1 +; AVX512F-NEXT: vmovdqa64 64(%r8), %zmm25 +; AVX512F-NEXT: vmovdqa64 128(%r8), %zmm23 +; AVX512F-NEXT: vmovdqa64 (%r9), %zmm28 +; AVX512F-NEXT: vmovdqa64 64(%r9), %zmm26 +; AVX512F-NEXT: vmovdqa64 128(%r9), %zmm24 +; AVX512F-NEXT: vmovdqa64 (%r10), %zmm21 +; AVX512F-NEXT: vmovdqa64 64(%r10), %zmm14 +; AVX512F-NEXT: vmovdqa64 (%rax), %zmm27 +; AVX512F-NEXT: vmovdqa64 64(%rax), %zmm16 +; AVX512F-NEXT: movb $-64, %r11b +; AVX512F-NEXT: kmovw %r11d, %k1 +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm3 = [4,12,4,12,4,12,4,12] +; AVX512F-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm21, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm27, %zmm3, %zmm0 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} zmm12 = zmm1[0],zmm28[0],zmm1[2],zmm28[2],zmm1[4],zmm28[4],zmm1[6],zmm28[6] +; AVX512F-NEXT: vmovdqa64 %zmm0, %zmm12 {%k1} +; AVX512F-NEXT: vmovdqa64 %zmm8, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm22, %zmm3, %zmm0 +; AVX512F-NEXT: vbroadcasti128 {{.*#+}} ymm6 = [4,12,4,12] +; AVX512F-NEXT: # ymm6 = mem[0,1,0,1] +; AVX512F-NEXT: vmovdqa64 %zmm10, %zmm15 +; AVX512F-NEXT: vpermt2q %zmm11, %zmm6, %zmm15 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm15[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm0, %zmm12, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm9 = [5,13,5,13,5,13,5,13] +; AVX512F-NEXT: # zmm9 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm21, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm27, %zmm9, %zmm0 +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} zmm12 = zmm1[1],zmm28[1],zmm1[3],zmm28[3],zmm1[5],zmm28[5],zmm1[7],zmm28[7] +; AVX512F-NEXT: vmovdqa64 %zmm0, %zmm12 {%k1} +; AVX512F-NEXT: vmovdqa64 %zmm8, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm22, %zmm9, %zmm0 +; AVX512F-NEXT: vbroadcasti128 {{.*#+}} ymm7 = [5,13,5,13] +; AVX512F-NEXT: # ymm7 = mem[0,1,0,1] +; AVX512F-NEXT: vmovdqa64 %zmm10, %zmm15 +; AVX512F-NEXT: vpermt2q %zmm11, %zmm7, %zmm15 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm15[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm0, %zmm12, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm13 = [6,14,6,14,6,14,6,14] +; AVX512F-NEXT: # zmm13 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm1, %zmm0 +; AVX512F-NEXT: vmovdqa64 %zmm1, %zmm29 +; AVX512F-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm28, %zmm13, %zmm0 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} zmm0 {%k1} = zmm21[0],zmm27[0],zmm21[2],zmm27[2],zmm21[4],zmm27[4],zmm21[6],zmm27[6] +; AVX512F-NEXT: vmovdqa64 %zmm8, %zmm12 +; AVX512F-NEXT: vpermt2q %zmm22, %zmm13, %zmm12 +; AVX512F-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [6,14,6,14] +; AVX512F-NEXT: # ymm1 = mem[0,1,0,1] +; AVX512F-NEXT: vmovdqa64 %zmm10, %zmm15 +; AVX512F-NEXT: vpermt2q %zmm11, %zmm1, %zmm15 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm12 = ymm12[0,1,2,3],ymm15[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm12, %zmm0, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm18 = [7,15,7,15,7,15,7,15] +; AVX512F-NEXT: # zmm18 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm29, %zmm12 +; AVX512F-NEXT: vpermt2q %zmm28, %zmm18, %zmm12 +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} zmm12 {%k1} = zmm21[1],zmm27[1],zmm21[3],zmm27[3],zmm21[5],zmm27[5],zmm21[7],zmm27[7] +; AVX512F-NEXT: vpermt2q %zmm22, %zmm18, %zmm8 +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} ymm30 = [7,15,7,15] +; AVX512F-NEXT: # ymm30 = mem[0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vpermt2q %zmm11, %zmm30, %zmm10 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm8 = ymm8[0,1,2,3],ymm10[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm8, %zmm12, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm14, %zmm8 +; AVX512F-NEXT: vpermt2q %zmm16, %zmm3, %zmm8 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} zmm10 = zmm25[0],zmm26[0],zmm25[2],zmm26[2],zmm25[4],zmm26[4],zmm25[6],zmm26[6] +; AVX512F-NEXT: vmovdqa64 %zmm8, %zmm10 {%k1} +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm8 +; AVX512F-NEXT: vpermt2q %zmm19, %zmm3, %zmm8 +; AVX512F-NEXT: vmovdqa64 %zmm5, %zmm11 +; AVX512F-NEXT: vmovdqa64 %zmm6, %zmm15 +; AVX512F-NEXT: vpermt2q %zmm20, %zmm6, %zmm11 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm8 = ymm8[0,1,2,3],ymm11[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm8, %zmm10, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm14, %zmm8 +; AVX512F-NEXT: vpermt2q %zmm16, %zmm9, %zmm8 +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} zmm10 = zmm25[1],zmm26[1],zmm25[3],zmm26[3],zmm25[5],zmm26[5],zmm25[7],zmm26[7] +; AVX512F-NEXT: vmovdqa64 %zmm8, %zmm10 {%k1} +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm8 +; AVX512F-NEXT: vpermt2q %zmm19, %zmm9, %zmm8 +; AVX512F-NEXT: vmovdqa64 %zmm5, %zmm11 +; AVX512F-NEXT: vmovdqa64 %zmm7, %zmm12 +; AVX512F-NEXT: vpermt2q %zmm20, %zmm7, %zmm11 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm8 = ymm8[0,1,2,3],ymm11[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm8, %zmm10, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm8 +; AVX512F-NEXT: vpermt2q %zmm19, %zmm13, %zmm8 +; AVX512F-NEXT: vmovdqa64 %zmm5, %zmm10 +; AVX512F-NEXT: vpermt2q %zmm20, %zmm1, %zmm10 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm8 = ymm8[0,1,2,3],ymm10[4,5,6,7] +; AVX512F-NEXT: vmovdqu64 %zmm25, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm25, %zmm10 +; AVX512F-NEXT: vmovdqu64 %zmm26, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm26, %zmm13, %zmm10 +; AVX512F-NEXT: vmovdqa64 %zmm14, %zmm11 +; AVX512F-NEXT: vmovdqu64 %zmm14, (%rsp) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 %zmm16, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} zmm10 {%k1} = zmm14[0],zmm16[0],zmm14[2],zmm16[2],zmm14[4],zmm16[4],zmm14[6],zmm16[6] +; AVX512F-NEXT: vinserti64x4 $0, %ymm8, %zmm10, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 128(%r10), %zmm10 +; AVX512F-NEXT: vpermt2q %zmm19, %zmm18, %zmm4 +; AVX512F-NEXT: vmovdqa64 128(%rax), %zmm14 +; AVX512F-NEXT: vpermt2q %zmm20, %zmm30, %zmm5 +; AVX512F-NEXT: vmovdqa64 %zmm25, %zmm6 +; AVX512F-NEXT: vpermt2q %zmm26, %zmm18, %zmm6 +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} zmm6 {%k1} = zmm11[1],zmm16[1],zmm11[3],zmm16[3],zmm11[5],zmm16[5],zmm11[7],zmm16[7] +; AVX512F-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3],ymm5[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm4, %zmm6, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm10, %zmm4 +; AVX512F-NEXT: vpermt2q %zmm14, %zmm3, %zmm4 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} zmm5 = zmm23[0],zmm24[0],zmm23[2],zmm24[2],zmm23[4],zmm24[4],zmm23[6],zmm24[6] +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm5 {%k1} +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm6 +; AVX512F-NEXT: vpermt2q %zmm17, %zmm3, %zmm6 +; AVX512F-NEXT: vmovdqa64 %zmm3, %zmm11 +; AVX512F-NEXT: vmovdqa64 128(%rdx), %zmm4 +; AVX512F-NEXT: vmovdqa64 128(%rcx), %zmm7 +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm8 +; AVX512F-NEXT: vpermt2q %zmm7, %zmm15, %zmm8 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm6 = ymm6[0,1,2,3],ymm8[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm6, %zmm5, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm10, %zmm5 +; AVX512F-NEXT: vpermt2q %zmm14, %zmm9, %zmm5 +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} zmm6 = zmm23[1],zmm24[1],zmm23[3],zmm24[3],zmm23[5],zmm24[5],zmm23[7],zmm24[7] +; AVX512F-NEXT: vmovdqa64 %zmm5, %zmm6 {%k1} +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm5 +; AVX512F-NEXT: vpermt2q %zmm17, %zmm9, %zmm5 +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm8 +; AVX512F-NEXT: vpermt2q %zmm7, %zmm12, %zmm8 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm5 = ymm5[0,1,2,3],ymm8[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm5, %zmm6, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm5 +; AVX512F-NEXT: vpermt2q %zmm17, %zmm13, %zmm5 +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm6 +; AVX512F-NEXT: vpermt2q %zmm7, %zmm1, %zmm6 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm5 = ymm5[0,1,2,3],ymm6[4,5,6,7] +; AVX512F-NEXT: vmovdqa64 %zmm23, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm23, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm23, %zmm6 +; AVX512F-NEXT: vmovdqu64 %zmm24, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm24, %zmm13, %zmm6 +; AVX512F-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 %zmm14, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} zmm6 {%k1} = zmm10[0],zmm14[0],zmm10[2],zmm14[2],zmm10[4],zmm14[4],zmm10[6],zmm14[6] +; AVX512F-NEXT: vinserti64x4 $0, %ymm5, %zmm6, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm17, %zmm18, %zmm2 +; AVX512F-NEXT: vpermt2q %zmm7, %zmm30, %zmm4 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm4[4,5,6,7] +; AVX512F-NEXT: vpermt2q %zmm24, %zmm18, %zmm3 +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} zmm3 {%k1} = zmm10[1],zmm14[1],zmm10[3],zmm14[3],zmm10[5],zmm14[5],zmm10[7],zmm14[7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm2, %zmm3, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 192(%r10), %zmm10 +; AVX512F-NEXT: vmovdqa64 192(%rax), %zmm26 +; AVX512F-NEXT: vmovdqa64 %zmm10, %zmm2 +; AVX512F-NEXT: vpermt2q %zmm26, %zmm11, %zmm2 +; AVX512F-NEXT: vmovdqa64 192(%r8), %zmm23 +; AVX512F-NEXT: vmovdqa64 192(%r9), %zmm29 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} zmm4 = zmm23[0],zmm29[0],zmm23[2],zmm29[2],zmm23[4],zmm29[4],zmm23[6],zmm29[6] +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm4 {%k1} +; AVX512F-NEXT: vmovdqa64 192(%rdi), %zmm2 +; AVX512F-NEXT: vmovdqa64 192(%rsi), %zmm5 +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm6 +; AVX512F-NEXT: vpermt2q %zmm5, %zmm11, %zmm6 +; AVX512F-NEXT: vmovdqa64 192(%rdx), %zmm3 +; AVX512F-NEXT: vmovdqa64 192(%rcx), %zmm7 +; AVX512F-NEXT: vmovdqa64 %zmm3, %zmm8 +; AVX512F-NEXT: vpermt2q %zmm7, %zmm15, %zmm8 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm6 = ymm6[0,1,2,3],ymm8[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm6, %zmm4, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm10, %zmm4 +; AVX512F-NEXT: vpermt2q %zmm26, %zmm9, %zmm4 +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} zmm6 = zmm23[1],zmm29[1],zmm23[3],zmm29[3],zmm23[5],zmm29[5],zmm23[7],zmm29[7] +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm6 {%k1} +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm4 +; AVX512F-NEXT: vpermt2q %zmm5, %zmm9, %zmm4 +; AVX512F-NEXT: vmovdqa64 %zmm3, %zmm8 +; AVX512F-NEXT: vpermt2q %zmm7, %zmm12, %zmm8 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3],ymm8[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm4, %zmm6, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm4 +; AVX512F-NEXT: vpermt2q %zmm5, %zmm13, %zmm4 +; AVX512F-NEXT: vmovdqa64 %zmm3, %zmm6 +; AVX512F-NEXT: vpermt2q %zmm7, %zmm1, %zmm6 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3],ymm6[4,5,6,7] +; AVX512F-NEXT: vmovdqa64 %zmm23, %zmm6 +; AVX512F-NEXT: vpermt2q %zmm29, %zmm13, %zmm6 +; AVX512F-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} zmm6 {%k1} = zmm10[0],zmm26[0],zmm10[2],zmm26[2],zmm10[4],zmm26[4],zmm10[6],zmm26[6] +; AVX512F-NEXT: vinserti64x4 $0, %ymm4, %zmm6, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm5, %zmm18, %zmm2 +; AVX512F-NEXT: vpermt2q %zmm7, %zmm30, %zmm3 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm3[4,5,6,7] +; AVX512F-NEXT: vmovdqa64 %zmm23, %zmm3 +; AVX512F-NEXT: vpermt2q %zmm29, %zmm18, %zmm3 +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} zmm3 {%k1} = zmm10[1],zmm26[1],zmm10[3],zmm26[3],zmm10[5],zmm26[5],zmm10[7],zmm26[7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm2, %zmm3, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 256(%r10), %zmm10 +; AVX512F-NEXT: vmovdqa64 256(%rax), %zmm22 +; AVX512F-NEXT: vmovdqa64 %zmm10, %zmm2 +; AVX512F-NEXT: vpermt2q %zmm22, %zmm11, %zmm2 +; AVX512F-NEXT: vmovdqa64 256(%r8), %zmm0 +; AVX512F-NEXT: vmovdqa64 256(%r9), %zmm24 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} zmm4 = zmm0[0],zmm24[0],zmm0[2],zmm24[2],zmm0[4],zmm24[4],zmm0[6],zmm24[6] +; AVX512F-NEXT: vmovdqa64 %zmm0, %zmm17 +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm4 {%k1} +; AVX512F-NEXT: vmovdqa64 256(%rdi), %zmm2 +; AVX512F-NEXT: vmovdqa64 256(%rsi), %zmm5 +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm6 +; AVX512F-NEXT: vpermt2q %zmm5, %zmm11, %zmm6 +; AVX512F-NEXT: vmovdqa64 256(%rdx), %zmm3 +; AVX512F-NEXT: vmovdqa64 256(%rcx), %zmm7 +; AVX512F-NEXT: vmovdqa64 %zmm3, %zmm8 +; AVX512F-NEXT: vpermt2q %zmm7, %zmm15, %zmm8 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm6 = ymm6[0,1,2,3],ymm8[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm6, %zmm4, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm10, %zmm4 +; AVX512F-NEXT: vpermt2q %zmm22, %zmm9, %zmm4 +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} zmm6 = zmm17[1],zmm24[1],zmm17[3],zmm24[3],zmm17[5],zmm24[5],zmm17[7],zmm24[7] +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm6 {%k1} +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm4 +; AVX512F-NEXT: vpermt2q %zmm5, %zmm9, %zmm4 +; AVX512F-NEXT: vmovdqa64 %zmm3, %zmm8 +; AVX512F-NEXT: vpermt2q %zmm7, %zmm12, %zmm8 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3],ymm8[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm4, %zmm6, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm4 +; AVX512F-NEXT: vpermt2q %zmm5, %zmm13, %zmm4 +; AVX512F-NEXT: vmovdqa64 %zmm3, %zmm6 +; AVX512F-NEXT: vpermt2q %zmm7, %zmm1, %zmm6 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3],ymm6[4,5,6,7] +; AVX512F-NEXT: vmovdqu64 %zmm17, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm17, %zmm6 +; AVX512F-NEXT: vpermt2q %zmm24, %zmm13, %zmm6 +; AVX512F-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} zmm6 {%k1} = zmm10[0],zmm22[0],zmm10[2],zmm22[2],zmm10[4],zmm22[4],zmm10[6],zmm22[6] +; AVX512F-NEXT: vinserti64x4 $0, %ymm4, %zmm6, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm5, %zmm18, %zmm2 +; AVX512F-NEXT: vpermt2q %zmm7, %zmm30, %zmm3 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm3[4,5,6,7] +; AVX512F-NEXT: vmovdqa64 %zmm17, %zmm3 +; AVX512F-NEXT: vpermt2q %zmm24, %zmm18, %zmm3 +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} zmm3 {%k1} = zmm10[1],zmm22[1],zmm10[3],zmm22[3],zmm10[5],zmm22[5],zmm10[7],zmm22[7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm2, %zmm3, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 320(%rdi), %zmm2 +; AVX512F-NEXT: vmovdqa64 320(%rsi), %zmm3 +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm5 +; AVX512F-NEXT: vpermt2q %zmm3, %zmm11, %zmm5 +; AVX512F-NEXT: vmovdqa64 320(%rdx), %zmm14 +; AVX512F-NEXT: vmovdqa64 320(%rcx), %zmm6 +; AVX512F-NEXT: vmovdqa64 %zmm14, %zmm7 +; AVX512F-NEXT: vpermt2q %zmm6, %zmm15, %zmm7 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm5 = ymm5[0,1,2,3],ymm7[4,5,6,7] +; AVX512F-NEXT: vmovdqa64 %zmm14, %zmm7 +; AVX512F-NEXT: vpermt2q %zmm6, %zmm12, %zmm7 +; AVX512F-NEXT: vmovdqa64 %zmm14, %zmm8 +; AVX512F-NEXT: vpermt2q %zmm6, %zmm1, %zmm8 +; AVX512F-NEXT: vpermt2q %zmm6, %zmm30, %zmm14 +; AVX512F-NEXT: vmovdqa64 384(%rdx), %zmm0 +; AVX512F-NEXT: vmovdqa64 384(%rcx), %zmm6 +; AVX512F-NEXT: vmovdqa64 %zmm0, %zmm10 +; AVX512F-NEXT: vpermt2q %zmm6, %zmm15, %zmm10 +; AVX512F-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm0, %zmm10 +; AVX512F-NEXT: vpermt2q %zmm6, %zmm12, %zmm10 +; AVX512F-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm0, %zmm10 +; AVX512F-NEXT: vpermt2q %zmm6, %zmm1, %zmm10 +; AVX512F-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm6, %zmm30, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 448(%rdx), %zmm0 +; AVX512F-NEXT: vmovdqa64 448(%rcx), %zmm6 +; AVX512F-NEXT: vpermi2q %zmm6, %zmm0, %zmm15 +; AVX512F-NEXT: vmovdqu64 %zmm15, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermi2q %zmm6, %zmm0, %zmm12 +; AVX512F-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermi2q %zmm6, %zmm0, %zmm1 +; AVX512F-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm6, %zmm30, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 320(%r10), %zmm31 +; AVX512F-NEXT: vmovdqa64 320(%rax), %zmm12 +; AVX512F-NEXT: vmovdqa64 %zmm31, %zmm1 +; AVX512F-NEXT: vpermt2q %zmm12, %zmm11, %zmm1 +; AVX512F-NEXT: vmovdqa64 320(%r8), %zmm17 +; AVX512F-NEXT: vmovdqa64 320(%r9), %zmm4 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} zmm10 = zmm17[0],zmm4[0],zmm17[2],zmm4[2],zmm17[4],zmm4[4],zmm17[6],zmm4[6] +; AVX512F-NEXT: vmovdqa64 %zmm1, %zmm10 {%k1} +; AVX512F-NEXT: vinserti64x4 $0, %ymm5, %zmm10, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm31, %zmm1 +; AVX512F-NEXT: vpermt2q %zmm12, %zmm9, %zmm1 +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} zmm5 = zmm17[1],zmm4[1],zmm17[3],zmm4[3],zmm17[5],zmm4[5],zmm17[7],zmm4[7] +; AVX512F-NEXT: vmovdqa64 %zmm1, %zmm5 {%k1} +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm1 +; AVX512F-NEXT: vpermt2q %zmm3, %zmm9, %zmm1 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm7[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm1, %zmm5, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm1 +; AVX512F-NEXT: vpermt2q %zmm3, %zmm13, %zmm1 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm8[4,5,6,7] +; AVX512F-NEXT: vmovdqa64 %zmm17, %zmm5 +; AVX512F-NEXT: vpermt2q %zmm4, %zmm13, %zmm5 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} zmm5 {%k1} = zmm31[0],zmm12[0],zmm31[2],zmm12[2],zmm31[4],zmm12[4],zmm31[6],zmm12[6] +; AVX512F-NEXT: vinserti64x4 $0, %ymm1, %zmm5, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm3, %zmm18, %zmm2 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm2[0,1,2,3],ymm14[4,5,6,7] +; AVX512F-NEXT: vmovdqa64 %zmm17, %zmm2 +; AVX512F-NEXT: vpermt2q %zmm4, %zmm18, %zmm2 +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} zmm2 {%k1} = zmm31[1],zmm12[1],zmm31[3],zmm12[3],zmm31[5],zmm12[5],zmm31[7],zmm12[7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm1, %zmm2, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 384(%rdi), %zmm0 +; AVX512F-NEXT: vmovdqa64 384(%rsi), %zmm1 +; AVX512F-NEXT: vmovdqa64 %zmm0, %zmm3 +; AVX512F-NEXT: vmovdqa64 %zmm11, %zmm2 +; AVX512F-NEXT: vpermt2q %zmm1, %zmm11, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm0, %zmm3 +; AVX512F-NEXT: vpermt2q %zmm1, %zmm9, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm0, %zmm3 +; AVX512F-NEXT: vpermt2q %zmm1, %zmm13, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm1, %zmm18, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 384(%r10), %zmm11 +; AVX512F-NEXT: vmovdqa64 384(%rax), %zmm20 +; AVX512F-NEXT: vmovdqa64 %zmm11, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm20, %zmm2, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm11, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm20, %zmm9, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 384(%r8), %zmm30 +; AVX512F-NEXT: vmovdqa64 384(%r9), %zmm0 +; AVX512F-NEXT: vmovdqa64 %zmm30, %zmm1 +; AVX512F-NEXT: vpermt2q %zmm0, %zmm13, %zmm1 +; AVX512F-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 448(%r10), %zmm16 +; AVX512F-NEXT: vmovdqa64 448(%rax), %zmm8 +; AVX512F-NEXT: vmovdqa64 %zmm16, %zmm1 +; AVX512F-NEXT: vpermt2q %zmm8, %zmm2, %zmm1 +; AVX512F-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 448(%rdi), %zmm3 +; AVX512F-NEXT: vmovdqa64 448(%rsi), %zmm1 +; AVX512F-NEXT: vpermi2q %zmm1, %zmm3, %zmm2 +; AVX512F-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm16, %zmm2 +; AVX512F-NEXT: vpermt2q %zmm8, %zmm9, %zmm2 +; AVX512F-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermi2q %zmm1, %zmm3, %zmm9 +; AVX512F-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 448(%r8), %zmm19 +; AVX512F-NEXT: vmovdqa64 448(%r9), %zmm7 +; AVX512F-NEXT: vmovdqa64 %zmm19, %zmm2 +; AVX512F-NEXT: vpermt2q %zmm7, %zmm13, %zmm2 +; AVX512F-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermi2q %zmm1, %zmm3, %zmm13 +; AVX512F-NEXT: vmovdqu64 %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm1, %zmm18, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm30, %zmm1 +; AVX512F-NEXT: vpermt2q %zmm0, %zmm18, %zmm1 +; AVX512F-NEXT: vmovdqa64 %zmm1, %zmm5 +; AVX512F-NEXT: vmovdqa64 %zmm19, %zmm1 +; AVX512F-NEXT: vpermt2q %zmm7, %zmm18, %zmm1 +; AVX512F-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm15 = [0,8,0,8,0,8,0,8] +; AVX512F-NEXT: # zmm15 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm21, %zmm1 +; AVX512F-NEXT: vpermt2q %zmm27, %zmm15, %zmm1 +; AVX512F-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm14 = [1,9,1,9,1,9,1,9] +; AVX512F-NEXT: # zmm14 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm21, %zmm1 +; AVX512F-NEXT: vpermt2q %zmm27, %zmm14, %zmm1 +; AVX512F-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm6 = [2,10,2,10,2,10,2,10] +; AVX512F-NEXT: # zmm6 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vmovdqa64 %zmm21, %zmm1 +; AVX512F-NEXT: vpermt2q %zmm27, %zmm6, %zmm1 +; AVX512F-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} zmm1 = [3,11,3,11,3,11,3,11] +; AVX512F-NEXT: # zmm1 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512F-NEXT: vpermt2q %zmm27, %zmm1, %zmm21 +; AVX512F-NEXT: vmovdqu64 %zmm21, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm3 +; AVX512F-NEXT: vpermt2q %zmm28, %zmm15, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm3 +; AVX512F-NEXT: vpermt2q %zmm28, %zmm14, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm25 +; AVX512F-NEXT: vpermt2q %zmm28, %zmm6, %zmm25 +; AVX512F-NEXT: vpermt2q %zmm28, %zmm1, %zmm2 +; AVX512F-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 (%rsp), %zmm27 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm27, %zmm2 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm3, %zmm15, %zmm2 +; AVX512F-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm27, %zmm2 +; AVX512F-NEXT: vpermt2q %zmm3, %zmm14, %zmm2 +; AVX512F-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm27, %zmm2 +; AVX512F-NEXT: vpermt2q %zmm3, %zmm6, %zmm2 +; AVX512F-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm3, %zmm1, %zmm27 +; AVX512F-NEXT: vmovdqu64 %zmm27, (%rsp) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm9, %zmm3 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm2, %zmm15, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm9, %zmm3 +; AVX512F-NEXT: vpermt2q %zmm2, %zmm14, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm9, %zmm18 +; AVX512F-NEXT: vpermt2q %zmm2, %zmm6, %zmm18 +; AVX512F-NEXT: vpermt2q %zmm2, %zmm1, %zmm9 +; AVX512F-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm3 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm9, %zmm15, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm3 +; AVX512F-NEXT: vpermt2q %zmm9, %zmm14, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm3 +; AVX512F-NEXT: vpermt2q %zmm9, %zmm6, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm9, %zmm1, %zmm2 +; AVX512F-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm9, %zmm3 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512F-NEXT: vpermt2q %zmm2, %zmm15, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm9, %zmm3 +; AVX512F-NEXT: vpermt2q %zmm2, %zmm14, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm9, %zmm13 +; AVX512F-NEXT: vpermt2q %zmm2, %zmm6, %zmm13 +; AVX512F-NEXT: vpermt2q %zmm2, %zmm1, %zmm9 +; AVX512F-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm3 +; AVX512F-NEXT: vpermt2q %zmm26, %zmm15, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm3 +; AVX512F-NEXT: vpermt2q %zmm26, %zmm14, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm3 +; AVX512F-NEXT: vpermt2q %zmm26, %zmm6, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm26, %zmm1, %zmm2 +; AVX512F-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm23, %zmm3 +; AVX512F-NEXT: vpermt2q %zmm29, %zmm15, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm23, %zmm3 +; AVX512F-NEXT: vpermt2q %zmm29, %zmm14, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm23, %zmm10 +; AVX512F-NEXT: vpermt2q %zmm29, %zmm6, %zmm10 +; AVX512F-NEXT: vpermt2q %zmm29, %zmm1, %zmm23 +; AVX512F-NEXT: vmovdqu64 %zmm23, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm23 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm23, %zmm2 +; AVX512F-NEXT: vpermt2q %zmm22, %zmm15, %zmm2 +; AVX512F-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm23, %zmm2 +; AVX512F-NEXT: vpermt2q %zmm22, %zmm14, %zmm2 +; AVX512F-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm23, %zmm2 +; AVX512F-NEXT: vpermt2q %zmm22, %zmm6, %zmm2 +; AVX512F-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm22, %zmm1, %zmm23 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm3 +; AVX512F-NEXT: vpermt2q %zmm24, %zmm15, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm3 +; AVX512F-NEXT: vpermt2q %zmm24, %zmm14, %zmm3 +; AVX512F-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm26 +; AVX512F-NEXT: vpermt2q %zmm24, %zmm6, %zmm26 +; AVX512F-NEXT: vpermt2q %zmm24, %zmm1, %zmm2 +; AVX512F-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm31, %zmm2 +; AVX512F-NEXT: vpermt2q %zmm12, %zmm15, %zmm2 +; AVX512F-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm31, %zmm2 +; AVX512F-NEXT: vpermt2q %zmm12, %zmm14, %zmm2 +; AVX512F-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm31, %zmm2 +; AVX512F-NEXT: vpermt2q %zmm12, %zmm6, %zmm2 +; AVX512F-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vpermt2q %zmm12, %zmm1, %zmm31 +; AVX512F-NEXT: vmovdqa64 %zmm17, %zmm29 +; AVX512F-NEXT: vpermt2q %zmm4, %zmm15, %zmm29 +; AVX512F-NEXT: vmovdqa64 %zmm17, %zmm2 +; AVX512F-NEXT: vpermt2q %zmm4, %zmm14, %zmm2 +; AVX512F-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm17, %zmm24 +; AVX512F-NEXT: vpermt2q %zmm4, %zmm6, %zmm24 +; AVX512F-NEXT: vpermt2q %zmm4, %zmm1, %zmm17 +; AVX512F-NEXT: vmovdqa64 %zmm11, %zmm2 +; AVX512F-NEXT: vpermt2q %zmm20, %zmm15, %zmm2 +; AVX512F-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm11, %zmm2 +; AVX512F-NEXT: vpermt2q %zmm20, %zmm14, %zmm2 +; AVX512F-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} zmm9 {%k1} = zmm11[0],zmm20[0],zmm11[2],zmm20[2],zmm11[4],zmm20[4],zmm11[6],zmm20[6] +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} zmm5 {%k1} = zmm11[1],zmm20[1],zmm11[3],zmm20[3],zmm11[5],zmm20[5],zmm11[7],zmm20[7] +; AVX512F-NEXT: vmovdqa64 %zmm5, %zmm27 +; AVX512F-NEXT: vmovdqa64 %zmm11, %zmm22 +; AVX512F-NEXT: vpermt2q %zmm20, %zmm6, %zmm22 +; AVX512F-NEXT: vpermt2q %zmm20, %zmm1, %zmm11 +; AVX512F-NEXT: vmovdqa64 %zmm30, %zmm21 +; AVX512F-NEXT: vpermt2q %zmm0, %zmm15, %zmm21 +; AVX512F-NEXT: vmovdqa64 %zmm30, %zmm28 +; AVX512F-NEXT: vpermt2q %zmm0, %zmm14, %zmm28 +; AVX512F-NEXT: vmovdqa64 %zmm30, %zmm20 +; AVX512F-NEXT: vpermt2q %zmm0, %zmm6, %zmm20 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} zmm2 = zmm30[0],zmm0[0],zmm30[2],zmm0[2],zmm30[4],zmm0[4],zmm30[6],zmm0[6] +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} zmm3 = zmm30[1],zmm0[1],zmm30[3],zmm0[3],zmm30[5],zmm0[5],zmm30[7],zmm0[7] +; AVX512F-NEXT: vpermt2q %zmm0, %zmm1, %zmm30 +; AVX512F-NEXT: vmovdqa64 %zmm16, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm8, %zmm15, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqa64 %zmm16, %zmm0 +; AVX512F-NEXT: vpermt2q %zmm8, %zmm14, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} zmm4 {%k1} = zmm16[0],zmm8[0],zmm16[2],zmm8[2],zmm16[4],zmm8[4],zmm16[6],zmm8[6] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} zmm5 {%k1} = zmm16[1],zmm8[1],zmm16[3],zmm8[3],zmm16[5],zmm8[5],zmm16[7],zmm8[7] +; AVX512F-NEXT: vmovdqa64 %zmm16, %zmm12 +; AVX512F-NEXT: vpermt2q %zmm8, %zmm6, %zmm12 +; AVX512F-NEXT: vpermt2q %zmm8, %zmm1, %zmm16 +; AVX512F-NEXT: vpermi2q %zmm7, %zmm19, %zmm15 +; AVX512F-NEXT: vpermi2q %zmm7, %zmm19, %zmm14 +; AVX512F-NEXT: vpermi2q %zmm7, %zmm19, %zmm6 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} zmm8 = zmm19[0],zmm7[0],zmm19[2],zmm7[2],zmm19[4],zmm7[4],zmm19[6],zmm7[6] +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} zmm0 = zmm19[1],zmm7[1],zmm19[3],zmm7[3],zmm19[5],zmm7[5],zmm19[7],zmm7[7] +; AVX512F-NEXT: vpermt2q %zmm7, %zmm1, %zmm19 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512F-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload +; AVX512F-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm7, %zmm2 {%k1} +; AVX512F-NEXT: vinserti64x4 $0, %ymm1, %zmm2, %zmm1 +; AVX512F-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512F-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload +; AVX512F-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm3 {%k1} +; AVX512F-NEXT: vinserti64x4 $0, %ymm1, %zmm3, %zmm1 +; AVX512F-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512F-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload +; AVX512F-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm1, %zmm9, %zmm1 +; AVX512F-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512F-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload +; AVX512F-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm1, %zmm27, %zmm1 +; AVX512F-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512F-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload +; AVX512F-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm8 {%k1} +; AVX512F-NEXT: vinserti64x4 $0, %ymm1, %zmm8, %zmm1 +; AVX512F-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512F-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload +; AVX512F-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm0 {%k1} +; AVX512F-NEXT: vinserti64x4 $0, %ymm1, %zmm0, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 32-byte Folded Reload +; AVX512F-NEXT: # ymm0 = ymm0[0,1,2,3],mem[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm0, %zmm4, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 32-byte Folded Reload +; AVX512F-NEXT: # ymm0 = ymm0[0,1,2,3],mem[4,5,6,7] +; AVX512F-NEXT: vinserti64x4 $0, %ymm0, %zmm5, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm0, %zmm25 {%k1} +; AVX512F-NEXT: vmovdqa (%rcx), %ymm0 +; AVX512F-NEXT: vmovdqa (%rdx), %ymm1 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] +; AVX512F-NEXT: vmovdqa (%rsi), %ymm3 +; AVX512F-NEXT: vmovdqa (%rdi), %ymm7 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm7[0],ymm3[0],ymm7[2],ymm3[2] +; AVX512F-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm8[2,3],ymm2[2,3] +; AVX512F-NEXT: vinserti64x4 $0, %ymm2, %zmm25, %zmm2 +; AVX512F-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm4 {%k1} +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm7[1],ymm3[1],ymm7[3],ymm3[3] +; AVX512F-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] +; AVX512F-NEXT: vinserti64x4 $0, %ymm0, %zmm4, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm0, %zmm18 {%k1} +; AVX512F-NEXT: vmovdqa 64(%rcx), %ymm0 +; AVX512F-NEXT: vmovdqa 64(%rdx), %ymm1 +; AVX512F-NEXT: vmovdqa 64(%rsi), %ymm2 +; AVX512F-NEXT: vmovdqa 64(%rdi), %ymm3 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} ymm7 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm3[0],ymm2[0],ymm3[2],ymm2[2] +; AVX512F-NEXT: vperm2i128 {{.*#+}} ymm7 = ymm8[2,3],ymm7[2,3] +; AVX512F-NEXT: vinserti64x4 $0, %ymm7, %zmm18, %zmm4 +; AVX512F-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 (%rsp), %zmm4 # 64-byte Reload +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm5 {%k1} +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm3[1],ymm2[1],ymm3[3],ymm2[3] +; AVX512F-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] +; AVX512F-NEXT: vinserti64x4 $0, %ymm0, %zmm5, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm0, %zmm13 {%k1} +; AVX512F-NEXT: vmovdqa 128(%rcx), %ymm0 +; AVX512F-NEXT: vmovdqa 128(%rdx), %ymm1 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] +; AVX512F-NEXT: vmovdqa 128(%rsi), %ymm3 +; AVX512F-NEXT: vmovdqa 128(%rdi), %ymm7 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm7[0],ymm3[0],ymm7[2],ymm3[2] +; AVX512F-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm8[2,3],ymm2[2,3] +; AVX512F-NEXT: vinserti64x4 $0, %ymm2, %zmm13, %zmm2 +; AVX512F-NEXT: vmovdqu64 %zmm2, (%rsp) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm4 {%k1} +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm7[1],ymm3[1],ymm7[3],ymm3[3] +; AVX512F-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] +; AVX512F-NEXT: vinserti64x4 $0, %ymm0, %zmm4, %zmm0 +; AVX512F-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm0, %zmm10 {%k1} +; AVX512F-NEXT: vmovdqa 192(%rcx), %ymm0 +; AVX512F-NEXT: vmovdqa 192(%rdx), %ymm1 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] +; AVX512F-NEXT: vmovdqa 192(%rsi), %ymm3 +; AVX512F-NEXT: vmovdqa 192(%rdi), %ymm7 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm7[0],ymm3[0],ymm7[2],ymm3[2] +; AVX512F-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm8[2,3],ymm2[2,3] +; AVX512F-NEXT: vinserti64x4 $0, %ymm2, %zmm10, %zmm2 +; AVX512F-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm2, %zmm4 {%k1} +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm7[1],ymm3[1],ymm7[3],ymm3[3] +; AVX512F-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] +; AVX512F-NEXT: vinserti64x4 $0, %ymm0, %zmm4, %zmm9 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm0, %zmm26 {%k1} +; AVX512F-NEXT: vmovdqa 256(%rcx), %ymm0 +; AVX512F-NEXT: vmovdqa 256(%rdx), %ymm1 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] +; AVX512F-NEXT: vmovdqa 256(%rsi), %ymm3 +; AVX512F-NEXT: vmovdqa 256(%rdi), %ymm7 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm7[0],ymm3[0],ymm7[2],ymm3[2] +; AVX512F-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm8[2,3],ymm2[2,3] +; AVX512F-NEXT: vinserti64x4 $0, %ymm2, %zmm26, %zmm26 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm23, %zmm2 {%k1} +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm7[1],ymm3[1],ymm7[3],ymm3[3] +; AVX512F-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] +; AVX512F-NEXT: vinserti64x4 $0, %ymm0, %zmm2, %zmm7 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm0, %zmm24 {%k1} +; AVX512F-NEXT: vmovdqa 320(%rcx), %ymm0 +; AVX512F-NEXT: vmovdqa 320(%rdx), %ymm1 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] +; AVX512F-NEXT: vmovdqa 320(%rsi), %ymm3 +; AVX512F-NEXT: vmovdqa64 320(%rdi), %ymm23 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm23[0],ymm3[0],ymm23[2],ymm3[2] +; AVX512F-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm8[2,3],ymm2[2,3] +; AVX512F-NEXT: vinserti64x4 $0, %ymm2, %zmm24, %zmm8 +; AVX512F-NEXT: vmovdqa64 %zmm31, %zmm17 {%k1} +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm23[1],ymm3[1],ymm23[3],ymm3[3] +; AVX512F-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] +; AVX512F-NEXT: vinserti64x4 $0, %ymm0, %zmm17, %zmm17 +; AVX512F-NEXT: vmovdqa64 %zmm22, %zmm20 {%k1} +; AVX512F-NEXT: vmovdqa 384(%rcx), %ymm0 +; AVX512F-NEXT: vmovdqa 384(%rdx), %ymm1 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] +; AVX512F-NEXT: vmovdqa 384(%rsi), %ymm3 +; AVX512F-NEXT: vmovdqa64 384(%rdi), %ymm18 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} ymm13 = ymm18[0],ymm3[0],ymm18[2],ymm3[2] +; AVX512F-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm13[2,3],ymm2[2,3] +; AVX512F-NEXT: vinserti64x4 $0, %ymm2, %zmm20, %zmm20 +; AVX512F-NEXT: vmovdqa64 %zmm11, %zmm30 {%k1} +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm18[1],ymm3[1],ymm18[3],ymm3[3] +; AVX512F-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] +; AVX512F-NEXT: vinserti64x4 $0, %ymm0, %zmm30, %zmm24 +; AVX512F-NEXT: vmovdqa64 %zmm12, %zmm6 {%k1} +; AVX512F-NEXT: vmovdqa 448(%rcx), %ymm0 +; AVX512F-NEXT: vmovdqa 448(%rdx), %ymm1 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] +; AVX512F-NEXT: vmovdqa 448(%rsi), %ymm3 +; AVX512F-NEXT: vmovdqa 448(%rdi), %ymm10 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} ymm12 = ymm10[0],ymm3[0],ymm10[2],ymm3[2] +; AVX512F-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm12[2,3],ymm2[2,3] +; AVX512F-NEXT: vinserti64x4 $0, %ymm2, %zmm6, %zmm31 +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm10[1],ymm3[1],ymm10[3],ymm3[3] +; AVX512F-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] +; AVX512F-NEXT: vmovdqa64 %zmm16, %zmm19 {%k1} +; AVX512F-NEXT: vinserti64x4 $0, %ymm0, %zmm19, %zmm0 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm1, %zmm4 {%k1} +; AVX512F-NEXT: vmovdqa (%rsi), %xmm1 +; AVX512F-NEXT: vinserti128 $1, (%rcx), %ymm1, %ymm1 +; AVX512F-NEXT: vmovdqa (%rdi), %xmm2 +; AVX512F-NEXT: vinserti128 $1, (%rdx), %ymm2, %ymm2 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} ymm3 = ymm2[0],ymm1[0],ymm2[2],ymm1[2] +; AVX512F-NEXT: vinserti64x4 $0, %ymm3, %zmm4, %zmm3 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm10 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm4, %zmm10 {%k1} +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm2[1],ymm1[1],ymm2[3],ymm1[3] +; AVX512F-NEXT: vinserti64x4 $0, %ymm1, %zmm10, %zmm2 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm1, %zmm11 {%k1} +; AVX512F-NEXT: vmovdqa 64(%rsi), %xmm1 +; AVX512F-NEXT: vinserti128 $1, 64(%rcx), %ymm1, %ymm1 +; AVX512F-NEXT: vmovdqa 64(%rdi), %xmm4 +; AVX512F-NEXT: vinserti128 $1, 64(%rdx), %ymm4, %ymm4 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} ymm10 = ymm4[0],ymm1[0],ymm4[2],ymm1[2] +; AVX512F-NEXT: vinserti64x4 $0, %ymm10, %zmm11, %zmm10 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm11, %zmm12 {%k1} +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm4[1],ymm1[1],ymm4[3],ymm1[3] +; AVX512F-NEXT: vinserti64x4 $0, %ymm1, %zmm12, %zmm11 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm1, %zmm13 {%k1} +; AVX512F-NEXT: vmovdqa 128(%rsi), %xmm1 +; AVX512F-NEXT: vinserti128 $1, 128(%rcx), %ymm1, %ymm1 +; AVX512F-NEXT: vmovdqa 128(%rdi), %xmm4 +; AVX512F-NEXT: vinserti128 $1, 128(%rdx), %ymm4, %ymm12 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} ymm4 = ymm12[0],ymm1[0],ymm12[2],ymm1[2] +; AVX512F-NEXT: vinserti64x4 $0, %ymm4, %zmm13, %zmm4 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm18 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm13, %zmm18 {%k1} +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm12[1],ymm1[1],ymm12[3],ymm1[3] +; AVX512F-NEXT: vinserti64x4 $0, %ymm1, %zmm18, %zmm19 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm18 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm1, %zmm18 {%k1} +; AVX512F-NEXT: vmovdqa 192(%rsi), %xmm1 +; AVX512F-NEXT: vinserti128 $1, 192(%rcx), %ymm1, %ymm1 +; AVX512F-NEXT: vmovdqa 192(%rdi), %xmm12 +; AVX512F-NEXT: vinserti128 $1, 192(%rdx), %ymm12, %ymm12 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} ymm13 = ymm12[0],ymm1[0],ymm12[2],ymm1[2] +; AVX512F-NEXT: vinserti64x4 $0, %ymm13, %zmm18, %zmm30 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm18 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm13, %zmm18 {%k1} +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm12[1],ymm1[1],ymm12[3],ymm1[3] +; AVX512F-NEXT: vinserti64x4 $0, %ymm1, %zmm18, %zmm1 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm12, %zmm5 {%k1} +; AVX512F-NEXT: vmovdqa 256(%rsi), %xmm12 +; AVX512F-NEXT: vinserti128 $1, 256(%rcx), %ymm12, %ymm13 +; AVX512F-NEXT: vmovdqa 256(%rdi), %xmm12 +; AVX512F-NEXT: vinserti32x4 $1, 256(%rdx), %ymm12, %ymm18 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} ymm12 = ymm18[0],ymm13[0],ymm18[2],ymm13[2] +; AVX512F-NEXT: vinserti64x4 $0, %ymm12, %zmm5, %zmm12 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm23 # 64-byte Reload +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm23, %zmm5 {%k1} +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm13 = ymm18[1],ymm13[1],ymm18[3],ymm13[3] +; AVX512F-NEXT: vinserti64x4 $0, %ymm13, %zmm5, %zmm23 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm5, %zmm29 {%k1} +; AVX512F-NEXT: vmovdqa 320(%rsi), %xmm13 +; AVX512F-NEXT: vinserti128 $1, 320(%rcx), %ymm13, %ymm13 +; AVX512F-NEXT: vmovdqa64 320(%rdi), %xmm18 +; AVX512F-NEXT: vinserti32x4 $1, 320(%rdx), %ymm18, %ymm18 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} ymm27 = ymm18[0],ymm13[0],ymm18[2],ymm13[2] +; AVX512F-NEXT: vinserti64x4 $0, %ymm27, %zmm29, %zmm22 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm5, %zmm6 {%k1} +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm13 = ymm18[1],ymm13[1],ymm18[3],ymm13[3] +; AVX512F-NEXT: vinserti64x4 $0, %ymm13, %zmm6, %zmm13 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm5, %zmm21 {%k1} +; AVX512F-NEXT: vmovdqa64 384(%rsi), %xmm18 +; AVX512F-NEXT: vinserti32x4 $1, 384(%rcx), %ymm18, %ymm18 +; AVX512F-NEXT: vmovdqa64 384(%rdi), %xmm25 +; AVX512F-NEXT: vinserti32x4 $1, 384(%rdx), %ymm25, %ymm25 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} ymm27 = ymm25[0],ymm18[0],ymm25[2],ymm18[2] +; AVX512F-NEXT: vinserti64x4 $0, %ymm27, %zmm21, %zmm16 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm5, %zmm28 {%k1} +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm18 = ymm25[1],ymm18[1],ymm25[3],ymm18[3] +; AVX512F-NEXT: vinserti64x4 $0, %ymm18, %zmm28, %zmm21 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm5, %zmm15 {%k1} +; AVX512F-NEXT: vmovdqa64 448(%rsi), %xmm18 +; AVX512F-NEXT: vinserti32x4 $1, 448(%rcx), %ymm18, %ymm18 +; AVX512F-NEXT: vmovdqa64 448(%rdi), %xmm25 +; AVX512F-NEXT: vinserti32x4 $1, 448(%rdx), %ymm25, %ymm25 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} ymm27 = ymm25[0],ymm18[0],ymm25[2],ymm18[2] +; AVX512F-NEXT: vinserti64x4 $0, %ymm27, %zmm15, %zmm6 +; AVX512F-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512F-NEXT: vmovdqa64 %zmm5, %zmm14 {%k1} +; AVX512F-NEXT: vpunpckhqdq {{.*#+}} ymm18 = ymm25[1],ymm18[1],ymm25[3],ymm18[3] +; AVX512F-NEXT: vinserti64x4 $0, %ymm18, %zmm14, %zmm5 +; AVX512F-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512F-NEXT: vmovdqa64 %zmm0, 3776(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm31, 3712(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm24, 3264(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm20, 3200(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm17, 2752(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm8, 2688(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm7, 2240(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm26, 2176(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm9, 1728(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 1664(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 1216(%rax) +; AVX512F-NEXT: vmovups (%rsp), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 1152(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 704(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 640(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 192(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 128(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 4032(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 3968(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 3904(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 3840(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm5, 3648(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm6, 3584(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 3520(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 3456(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 3392(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 3328(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm21, 3136(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm16, 3072(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 3008(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 2944(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 2880(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 2816(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm13, 2624(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm22, 2560(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 2496(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 2432(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 2368(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 2304(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm23, 2112(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm12, 2048(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 1984(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 1920(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 1856(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 1792(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm1, 1600(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm30, 1536(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 1472(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 1408(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 1344(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 1280(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm19, 1088(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm4, 1024(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 960(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 896(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 832(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 768(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm11, 576(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm10, 512(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 448(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 384(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 320(%rax) +; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-NEXT: vmovaps %zmm0, 256(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm2, 64(%rax) +; AVX512F-NEXT: vmovdqa64 %zmm3, (%rax) +; AVX512F-NEXT: addq $5512, %rsp # imm = 0x1588 +; AVX512F-NEXT: vzeroupper +; AVX512F-NEXT: retq ; -; AVX512DQBW-ONLY-LABEL: store_i64_stride8_vf64: -; AVX512DQBW-ONLY: # %bb.0: -; AVX512DQBW-ONLY-NEXT: subq $5512, %rsp # imm = 0x1588 -; AVX512DQBW-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQBW-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %r10 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 128(%rdi), %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%rdi), %zmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 (%rdi), %zmm8 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 128(%rsi), %zmm17 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%rsi), %zmm19 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 (%rsi), %zmm22 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%rdx), %zmm5 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 (%rdx), %zmm10 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%rcx), %zmm20 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 (%rcx), %zmm11 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 (%r8), %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%r8), %zmm25 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 128(%r8), %zmm23 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 (%r9), %zmm28 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%r9), %zmm26 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 128(%r9), %zmm24 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 (%r10), %zmm21 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%r10), %zmm14 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 (%rax), %zmm27 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 64(%rax), %zmm16 -; AVX512DQBW-ONLY-NEXT: movb $-64, %r11b -; AVX512DQBW-ONLY-NEXT: kmovd %r11d, %k1 -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm3 = [4,12,4,12,4,12,4,12] -; AVX512DQBW-ONLY-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm21, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm27, %zmm3, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm12 = zmm1[0],zmm28[0],zmm1[2],zmm28[2],zmm1[4],zmm28[4],zmm1[6],zmm28[6] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm12 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm3, %zmm0 -; AVX512DQBW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm6 = [4,12,4,12] -; AVX512DQBW-ONLY-NEXT: # ymm6 = mem[0,1,0,1] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm15 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm11, %zmm6, %zmm15 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm15[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm12, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm9 = [5,13,5,13,5,13,5,13] -; AVX512DQBW-ONLY-NEXT: # zmm9 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm21, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm27, %zmm9, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm12 = zmm1[1],zmm28[1],zmm1[3],zmm28[3],zmm1[5],zmm28[5],zmm1[7],zmm28[7] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm12 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm8, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm9, %zmm0 -; AVX512DQBW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm7 = [5,13,5,13] -; AVX512DQBW-ONLY-NEXT: # ymm7 = mem[0,1,0,1] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm15 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm11, %zmm7, %zmm15 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm15[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm12, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm13 = [6,14,6,14,6,14,6,14] -; AVX512DQBW-ONLY-NEXT: # zmm13 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm1, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm1, %zmm29 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm28, %zmm13, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm0 {%k1} = zmm21[0],zmm27[0],zmm21[2],zmm27[2],zmm21[4],zmm27[4],zmm21[6],zmm27[6] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm8, %zmm12 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm13, %zmm12 -; AVX512DQBW-ONLY-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [6,14,6,14] -; AVX512DQBW-ONLY-NEXT: # ymm1 = mem[0,1,0,1] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm15 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm11, %zmm1, %zmm15 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm12 = ymm12[0,1,2,3],ymm15[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm12, %zmm0, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm18 = [7,15,7,15,7,15,7,15] -; AVX512DQBW-ONLY-NEXT: # zmm18 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm29, %zmm12 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm28, %zmm18, %zmm12 -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm12 {%k1} = zmm21[1],zmm27[1],zmm21[3],zmm27[3],zmm21[5],zmm27[5],zmm21[7],zmm27[7] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm18, %zmm8 -; AVX512DQBW-ONLY-NEXT: vbroadcasti64x2 {{.*#+}} ymm30 = [7,15,7,15] -; AVX512DQBW-ONLY-NEXT: # ymm30 = mem[0,1,0,1] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm11, %zmm30, %zmm10 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm8 = ymm8[0,1,2,3],ymm10[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm8, %zmm12, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm14, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm16, %zmm3, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm10 = zmm25[0],zmm26[0],zmm25[2],zmm26[2],zmm25[4],zmm26[4],zmm25[6],zmm26[6] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm8, %zmm10 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm19, %zmm3, %zmm8 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm11 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm6, %zmm15 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm20, %zmm6, %zmm11 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm8 = ymm8[0,1,2,3],ymm11[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm8, %zmm10, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm14, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm16, %zmm9, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm10 = zmm25[1],zmm26[1],zmm25[3],zmm26[3],zmm25[5],zmm26[5],zmm25[7],zmm26[7] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm8, %zmm10 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm19, %zmm9, %zmm8 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm11 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm12 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm20, %zmm7, %zmm11 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm8 = ymm8[0,1,2,3],ymm11[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm8, %zmm10, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm19, %zmm13, %zmm8 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm10 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm20, %zmm1, %zmm10 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm8 = ymm8[0,1,2,3],ymm10[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm25, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm10 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm26, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm26, %zmm13, %zmm10 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm14, %zmm11 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm14, (%rsp) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm16, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm10 {%k1} = zmm14[0],zmm16[0],zmm14[2],zmm16[2],zmm14[4],zmm16[4],zmm14[6],zmm16[6] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm8, %zmm10, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 128(%r10), %zmm10 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm19, %zmm18, %zmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 128(%rax), %zmm14 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm20, %zmm30, %zmm5 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm25, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm26, %zmm18, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm6 {%k1} = zmm11[1],zmm16[1],zmm11[3],zmm16[3],zmm11[5],zmm16[5],zmm11[7],zmm16[7] -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3],ymm5[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm6, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm4 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm14, %zmm3, %zmm4 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm5 = zmm23[0],zmm24[0],zmm23[2],zmm24[2],zmm23[4],zmm24[4],zmm23[6],zmm24[6] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm5 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm17, %zmm3, %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm11 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 128(%rdx), %zmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 128(%rcx), %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm15, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm6 = ymm6[0,1,2,3],ymm8[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm6, %zmm5, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm5 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm14, %zmm9, %zmm5 -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm6 = zmm23[1],zmm24[1],zmm23[3],zmm24[3],zmm23[5],zmm24[5],zmm23[7],zmm24[7] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm6 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm5 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm17, %zmm9, %zmm5 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm12, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm5 = ymm5[0,1,2,3],ymm8[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm5, %zmm6, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm5 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm17, %zmm13, %zmm5 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm1, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm5 = ymm5[0,1,2,3],ymm6[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm23, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm24, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm24, %zmm13, %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm14, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm6 {%k1} = zmm10[0],zmm14[0],zmm10[2],zmm14[2],zmm10[4],zmm14[4],zmm10[6],zmm14[6] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm5, %zmm6, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm17, %zmm18, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm30, %zmm4 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm4[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm24, %zmm18, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm3 {%k1} = zmm10[1],zmm14[1],zmm10[3],zmm14[3],zmm10[5],zmm14[5],zmm10[7],zmm14[7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm3, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 192(%r10), %zmm10 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 192(%rax), %zmm26 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm26, %zmm11, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 192(%r8), %zmm23 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 192(%r9), %zmm29 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm4 = zmm23[0],zmm29[0],zmm23[2],zmm29[2],zmm23[4],zmm29[4],zmm23[6],zmm29[6] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 192(%rdi), %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 192(%rsi), %zmm5 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm5, %zmm11, %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 192(%rdx), %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 192(%rcx), %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm15, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm6 = ymm6[0,1,2,3],ymm8[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm6, %zmm4, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm4 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm26, %zmm9, %zmm4 -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm6 = zmm23[1],zmm29[1],zmm23[3],zmm29[3],zmm23[5],zmm29[5],zmm23[7],zmm29[7] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm6 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm5, %zmm9, %zmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm12, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3],ymm8[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm6, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm5, %zmm13, %zmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm1, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3],ymm6[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm29, %zmm13, %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm6 {%k1} = zmm10[0],zmm26[0],zmm10[2],zmm26[2],zmm10[4],zmm26[4],zmm10[6],zmm26[6] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm6, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm5, %zmm18, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm30, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm3[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm29, %zmm18, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm3 {%k1} = zmm10[1],zmm26[1],zmm10[3],zmm26[3],zmm10[5],zmm26[5],zmm10[7],zmm26[7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm3, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 256(%r10), %zmm10 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 256(%rax), %zmm22 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm11, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 256(%r8), %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 256(%r9), %zmm24 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm4 = zmm0[0],zmm24[0],zmm0[2],zmm24[2],zmm0[4],zmm24[4],zmm0[6],zmm24[6] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm17 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 256(%rdi), %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 256(%rsi), %zmm5 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm5, %zmm11, %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 256(%rdx), %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 256(%rcx), %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm15, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm6 = ymm6[0,1,2,3],ymm8[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm6, %zmm4, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, %zmm4 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm9, %zmm4 -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm6 = zmm17[1],zmm24[1],zmm17[3],zmm24[3],zmm17[5],zmm24[5],zmm17[7],zmm24[7] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm6 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm5, %zmm9, %zmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm12, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3],ymm8[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm6, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm5, %zmm13, %zmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm3, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm1, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3],ymm6[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm17, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm17, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm24, %zmm13, %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm6 {%k1} = zmm10[0],zmm22[0],zmm10[2],zmm22[2],zmm10[4],zmm22[4],zmm10[6],zmm22[6] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm6, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm5, %zmm18, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm30, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm3[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm17, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm24, %zmm18, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm3 {%k1} = zmm10[1],zmm22[1],zmm10[3],zmm22[3],zmm10[5],zmm22[5],zmm10[7],zmm22[7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm3, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 320(%rdi), %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 320(%rsi), %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm5 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm3, %zmm11, %zmm5 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 320(%rdx), %zmm14 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 320(%rcx), %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm14, %zmm7 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm6, %zmm15, %zmm7 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm5 = ymm5[0,1,2,3],ymm7[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm14, %zmm7 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm6, %zmm12, %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm14, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm6, %zmm1, %zmm8 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm6, %zmm30, %zmm14 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 384(%rdx), %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 384(%rcx), %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm10 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm6, %zmm15, %zmm10 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm10 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm6, %zmm12, %zmm10 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm10 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm6, %zmm1, %zmm10 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm6, %zmm30, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 448(%rdx), %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 448(%rcx), %zmm6 -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm6, %zmm0, %zmm15 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm15, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm6, %zmm0, %zmm12 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm6, %zmm0, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm6, %zmm30, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 320(%r10), %zmm31 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 320(%rax), %zmm12 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm31, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm12, %zmm11, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 320(%r8), %zmm17 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 320(%r9), %zmm4 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm10 = zmm17[0],zmm4[0],zmm17[2],zmm4[2],zmm17[4],zmm4[4],zmm17[6],zmm4[6] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm1, %zmm10 {%k1} -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm5, %zmm10, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm31, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm12, %zmm9, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm5 = zmm17[1],zmm4[1],zmm17[3],zmm4[3],zmm17[5],zmm4[5],zmm17[7],zmm4[7] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm1, %zmm5 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm3, %zmm9, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm7[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm5, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm3, %zmm13, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm8[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm17, %zmm5 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm4, %zmm13, %zmm5 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm5 {%k1} = zmm31[0],zmm12[0],zmm31[2],zmm12[2],zmm31[4],zmm12[4],zmm31[6],zmm12[6] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm5, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm3, %zmm18, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpblendd {{.*#+}} ymm1 = ymm2[0,1,2,3],ymm14[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm17, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm4, %zmm18, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm2 {%k1} = zmm31[1],zmm12[1],zmm31[3],zmm12[3],zmm31[5],zmm12[5],zmm31[7],zmm12[7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm2, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 384(%rdi), %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 384(%rsi), %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm1, %zmm11, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm1, %zmm9, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm1, %zmm13, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm1, %zmm18, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 384(%r10), %zmm11 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 384(%rax), %zmm20 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm20, %zmm2, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm20, %zmm9, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 384(%r8), %zmm30 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 384(%r9), %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm30, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm0, %zmm13, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 448(%r10), %zmm16 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 448(%rax), %zmm8 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm16, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm8, %zmm2, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 448(%rdi), %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 448(%rsi), %zmm1 -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm1, %zmm3, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm16, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm8, %zmm9, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm1, %zmm3, %zmm9 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 448(%r8), %zmm19 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 448(%r9), %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm19, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm13, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm1, %zmm3, %zmm13 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm1, %zmm18, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm30, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm0, %zmm18, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm1, %zmm5 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm19, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm18, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm15 = [0,8,0,8,0,8,0,8] -; AVX512DQBW-ONLY-NEXT: # zmm15 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm21, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm27, %zmm15, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm14 = [1,9,1,9,1,9,1,9] -; AVX512DQBW-ONLY-NEXT: # zmm14 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm21, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm27, %zmm14, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm6 = [2,10,2,10,2,10,2,10] -; AVX512DQBW-ONLY-NEXT: # zmm6 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm21, %zmm1 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm27, %zmm6, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vbroadcasti32x4 {{.*#+}} zmm1 = [3,11,3,11,3,11,3,11] -; AVX512DQBW-ONLY-NEXT: # zmm1 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm27, %zmm1, %zmm21 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm21, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm28, %zmm15, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm28, %zmm14, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm25 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm28, %zmm6, %zmm25 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm28, %zmm1, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 (%rsp), %zmm27 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm27, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm3, %zmm15, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm27, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm3, %zmm14, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm27, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm3, %zmm6, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm3, %zmm1, %zmm27 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm27, (%rsp) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm9, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm15, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm9, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm14, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm9, %zmm18 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm6, %zmm18 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm1, %zmm9 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm9, %zmm15, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm9, %zmm14, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm9, %zmm6, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm9, %zmm1, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm9, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm15, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm9, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm14, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm9, %zmm13 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm6, %zmm13 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm2, %zmm1, %zmm9 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm26, %zmm15, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm26, %zmm14, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm26, %zmm6, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm26, %zmm1, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm29, %zmm15, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm29, %zmm14, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm10 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm29, %zmm6, %zmm10 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm29, %zmm1, %zmm23 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm23, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm23 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm15, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm14, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm6, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm22, %zmm1, %zmm23 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm24, %zmm15, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm24, %zmm14, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm26 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm24, %zmm6, %zmm26 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm24, %zmm1, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm31, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm12, %zmm15, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm31, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm12, %zmm14, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm31, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm12, %zmm6, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm12, %zmm1, %zmm31 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm17, %zmm29 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm4, %zmm15, %zmm29 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm17, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm4, %zmm14, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm17, %zmm24 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm4, %zmm6, %zmm24 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm4, %zmm1, %zmm17 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm20, %zmm15, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm2 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm20, %zmm14, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm9 {%k1} = zmm11[0],zmm20[0],zmm11[2],zmm20[2],zmm11[4],zmm20[4],zmm11[6],zmm20[6] -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm5 {%k1} = zmm11[1],zmm20[1],zmm11[3],zmm20[3],zmm11[5],zmm20[5],zmm11[7],zmm20[7] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm27 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm22 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm20, %zmm6, %zmm22 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm20, %zmm1, %zmm11 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm30, %zmm21 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm0, %zmm15, %zmm21 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm30, %zmm28 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm0, %zmm14, %zmm28 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm30, %zmm20 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm0, %zmm6, %zmm20 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm2 = zmm30[0],zmm0[0],zmm30[2],zmm0[2],zmm30[4],zmm0[4],zmm30[6],zmm0[6] -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm3 = zmm30[1],zmm0[1],zmm30[3],zmm0[3],zmm30[5],zmm0[5],zmm30[7],zmm0[7] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm0, %zmm1, %zmm30 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm16, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm8, %zmm15, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm16, %zmm0 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm8, %zmm14, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm4 {%k1} = zmm16[0],zmm8[0],zmm16[2],zmm8[2],zmm16[4],zmm8[4],zmm16[6],zmm8[6] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm5 {%k1} = zmm16[1],zmm8[1],zmm16[3],zmm8[3],zmm16[5],zmm8[5],zmm16[7],zmm8[7] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm16, %zmm12 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm8, %zmm6, %zmm12 -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm8, %zmm1, %zmm16 -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm7, %zmm19, %zmm15 -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm7, %zmm19, %zmm14 -; AVX512DQBW-ONLY-NEXT: vpermi2q %zmm7, %zmm19, %zmm6 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} zmm8 = zmm19[0],zmm7[0],zmm19[2],zmm7[2],zmm19[4],zmm7[4],zmm19[6],zmm7[6] -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} zmm0 = zmm19[1],zmm7[1],zmm19[3],zmm7[3],zmm19[5],zmm7[5],zmm19[7],zmm7[7] -; AVX512DQBW-ONLY-NEXT: vpermt2q %zmm7, %zmm1, %zmm19 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, %zmm2 {%k1} -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm2, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm3 {%k1} -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm3, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm9, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm27, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm8 {%k1} -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm8, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm0 {%k1} -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm0, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 32-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # ymm0 = ymm0[0,1,2,3],mem[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm4, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 32-byte Folded Reload -; AVX512DQBW-ONLY-NEXT: # ymm0 = ymm0[0,1,2,3],mem[4,5,6,7] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm5, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm25 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa (%rcx), %ymm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa (%rdx), %ymm1 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512DQBW-ONLY-NEXT: vmovdqa (%rsi), %ymm3 -; AVX512DQBW-ONLY-NEXT: vmovdqa (%rdi), %ymm7 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm7[0],ymm3[0],ymm7[2],ymm3[2] -; AVX512DQBW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm8[2,3],ymm2[2,3] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm25, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 {%k1} -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm7[1],ymm3[1],ymm7[3],ymm3[3] -; AVX512DQBW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm4, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm18 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa 64(%rcx), %ymm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa 64(%rdx), %ymm1 -; AVX512DQBW-ONLY-NEXT: vmovdqa 64(%rsi), %ymm2 -; AVX512DQBW-ONLY-NEXT: vmovdqa 64(%rdi), %ymm3 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm7 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm3[0],ymm2[0],ymm3[2],ymm2[2] -; AVX512DQBW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm7 = ymm8[2,3],ymm7[2,3] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm7, %zmm18, %zmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 (%rsp), %zmm4 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm5 {%k1} -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm3[1],ymm2[1],ymm3[3],ymm2[3] -; AVX512DQBW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm5, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm13 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa 128(%rcx), %ymm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa 128(%rdx), %ymm1 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512DQBW-ONLY-NEXT: vmovdqa 128(%rsi), %ymm3 -; AVX512DQBW-ONLY-NEXT: vmovdqa 128(%rdi), %ymm7 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm7[0],ymm3[0],ymm7[2],ymm3[2] -; AVX512DQBW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm8[2,3],ymm2[2,3] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm13, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm2, (%rsp) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 {%k1} -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm7[1],ymm3[1],ymm7[3],ymm3[3] -; AVX512DQBW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm4, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm10 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa 192(%rcx), %ymm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa 192(%rdx), %ymm1 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512DQBW-ONLY-NEXT: vmovdqa 192(%rsi), %ymm3 -; AVX512DQBW-ONLY-NEXT: vmovdqa 192(%rdi), %ymm7 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm7[0],ymm3[0],ymm7[2],ymm3[2] -; AVX512DQBW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm8[2,3],ymm2[2,3] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm10, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, %zmm4 {%k1} -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm7[1],ymm3[1],ymm7[3],ymm3[3] -; AVX512DQBW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm4, %zmm9 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm26 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa 256(%rcx), %ymm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa 256(%rdx), %ymm1 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512DQBW-ONLY-NEXT: vmovdqa 256(%rsi), %ymm3 -; AVX512DQBW-ONLY-NEXT: vmovdqa 256(%rdi), %ymm7 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm7[0],ymm3[0],ymm7[2],ymm3[2] -; AVX512DQBW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm8[2,3],ymm2[2,3] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm26, %zmm26 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm2 {%k1} -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm7[1],ymm3[1],ymm7[3],ymm3[3] -; AVX512DQBW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm2, %zmm7 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, %zmm24 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa 320(%rcx), %ymm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa 320(%rdx), %ymm1 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512DQBW-ONLY-NEXT: vmovdqa 320(%rsi), %ymm3 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 320(%rdi), %ymm23 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm23[0],ymm3[0],ymm23[2],ymm3[2] -; AVX512DQBW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm8[2,3],ymm2[2,3] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm24, %zmm8 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm31, %zmm17 {%k1} -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm23[1],ymm3[1],ymm23[3],ymm3[3] -; AVX512DQBW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm17, %zmm17 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm22, %zmm20 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa 384(%rcx), %ymm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa 384(%rdx), %ymm1 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512DQBW-ONLY-NEXT: vmovdqa 384(%rsi), %ymm3 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 384(%rdi), %ymm18 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm13 = ymm18[0],ymm3[0],ymm18[2],ymm3[2] -; AVX512DQBW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm13[2,3],ymm2[2,3] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm20, %zmm20 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm30 {%k1} -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm18[1],ymm3[1],ymm18[3],ymm3[3] -; AVX512DQBW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm30, %zmm24 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm6 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa 448(%rcx), %ymm0 -; AVX512DQBW-ONLY-NEXT: vmovdqa 448(%rdx), %ymm1 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] -; AVX512DQBW-ONLY-NEXT: vmovdqa 448(%rsi), %ymm3 -; AVX512DQBW-ONLY-NEXT: vmovdqa 448(%rdi), %ymm10 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm12 = ymm10[0],ymm3[0],ymm10[2],ymm3[2] -; AVX512DQBW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm12[2,3],ymm2[2,3] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm2, %zmm6, %zmm31 -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm10[1],ymm3[1],ymm10[3],ymm3[3] -; AVX512DQBW-ONLY-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm16, %zmm19 {%k1} -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm0, %zmm19, %zmm0 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm1, %zmm4 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa (%rsi), %xmm1 -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, (%rcx), %ymm1, %ymm1 -; AVX512DQBW-ONLY-NEXT: vmovdqa (%rdi), %xmm2 -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, (%rdx), %ymm2, %ymm2 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm3 = ymm2[0],ymm1[0],ymm2[2],ymm1[2] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm3, %zmm4, %zmm3 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm10 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, %zmm10 {%k1} -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm2[1],ymm1[1],ymm2[3],ymm1[3] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm10, %zmm2 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm1, %zmm11 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa 64(%rsi), %xmm1 -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, 64(%rcx), %ymm1, %ymm1 -; AVX512DQBW-ONLY-NEXT: vmovdqa 64(%rdi), %xmm4 -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, 64(%rdx), %ymm4, %ymm4 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm10 = ymm4[0],ymm1[0],ymm4[2],ymm1[2] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm10, %zmm11, %zmm10 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm11, %zmm12 {%k1} -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm4[1],ymm1[1],ymm4[3],ymm1[3] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm12, %zmm11 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm1, %zmm13 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa 128(%rsi), %xmm1 -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, 128(%rcx), %ymm1, %ymm1 -; AVX512DQBW-ONLY-NEXT: vmovdqa 128(%rdi), %xmm4 -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, 128(%rdx), %ymm4, %ymm12 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm4 = ymm12[0],ymm1[0],ymm12[2],ymm1[2] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm4, %zmm13, %zmm4 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm18 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm13, %zmm18 {%k1} -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm12[1],ymm1[1],ymm12[3],ymm1[3] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm18, %zmm19 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm18 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm1, %zmm18 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa 192(%rsi), %xmm1 -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, 192(%rcx), %ymm1, %ymm1 -; AVX512DQBW-ONLY-NEXT: vmovdqa 192(%rdi), %xmm12 -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, 192(%rdx), %ymm12, %ymm12 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm13 = ymm12[0],ymm1[0],ymm12[2],ymm1[2] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm13, %zmm18, %zmm30 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm18 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm13, %zmm18 {%k1} -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm12[1],ymm1[1],ymm12[3],ymm1[3] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm1, %zmm18, %zmm1 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm12, %zmm5 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa 256(%rsi), %xmm12 -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, 256(%rcx), %ymm12, %ymm13 -; AVX512DQBW-ONLY-NEXT: vmovdqa 256(%rdi), %xmm12 -; AVX512DQBW-ONLY-NEXT: vinserti32x4 $1, 256(%rdx), %ymm12, %ymm18 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm12 = ymm18[0],ymm13[0],ymm18[2],ymm13[2] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm12, %zmm5, %zmm12 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm23 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm23, %zmm5 {%k1} -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm13 = ymm18[1],ymm13[1],ymm18[3],ymm13[3] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm13, %zmm5, %zmm23 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm29 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa 320(%rsi), %xmm13 -; AVX512DQBW-ONLY-NEXT: vinserti128 $1, 320(%rcx), %ymm13, %ymm13 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 320(%rdi), %xmm18 -; AVX512DQBW-ONLY-NEXT: vinserti32x4 $1, 320(%rdx), %ymm18, %ymm18 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm27 = ymm18[0],ymm13[0],ymm18[2],ymm13[2] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm27, %zmm29, %zmm22 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm6 {%k1} -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm13 = ymm18[1],ymm13[1],ymm18[3],ymm13[3] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm13, %zmm6, %zmm13 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm21 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 384(%rsi), %xmm18 -; AVX512DQBW-ONLY-NEXT: vinserti32x4 $1, 384(%rcx), %ymm18, %ymm18 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 384(%rdi), %xmm25 -; AVX512DQBW-ONLY-NEXT: vinserti32x4 $1, 384(%rdx), %ymm25, %ymm25 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm27 = ymm25[0],ymm18[0],ymm25[2],ymm18[2] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm27, %zmm21, %zmm16 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm28 {%k1} -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm18 = ymm25[1],ymm18[1],ymm25[3],ymm18[3] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm18, %zmm28, %zmm21 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm15 {%k1} -; AVX512DQBW-ONLY-NEXT: vmovdqa64 448(%rsi), %xmm18 -; AVX512DQBW-ONLY-NEXT: vinserti32x4 $1, 448(%rcx), %ymm18, %ymm18 -; AVX512DQBW-ONLY-NEXT: vmovdqa64 448(%rdi), %xmm25 -; AVX512DQBW-ONLY-NEXT: vinserti32x4 $1, 448(%rdx), %ymm25, %ymm25 -; AVX512DQBW-ONLY-NEXT: vpunpcklqdq {{.*#+}} ymm27 = ymm25[0],ymm18[0],ymm25[2],ymm18[2] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm27, %zmm15, %zmm6 -; AVX512DQBW-ONLY-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, %zmm14 {%k1} -; AVX512DQBW-ONLY-NEXT: vpunpckhqdq {{.*#+}} ymm18 = ymm25[1],ymm18[1],ymm25[3],ymm18[3] -; AVX512DQBW-ONLY-NEXT: vinserti64x4 $0, %ymm18, %zmm14, %zmm5 -; AVX512DQBW-ONLY-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm0, 3776(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm31, 3712(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm24, 3264(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm20, 3200(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm17, 2752(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm8, 2688(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm7, 2240(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm26, 2176(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm9, 1728(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 1664(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 1216(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups (%rsp), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 1152(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 704(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 640(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 192(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 128(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 4032(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 3968(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 3904(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 3840(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm5, 3648(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm6, 3584(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 3520(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 3456(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 3392(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 3328(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm21, 3136(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm16, 3072(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 3008(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 2944(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 2880(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 2816(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm13, 2624(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm22, 2560(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 2496(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 2432(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 2368(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 2304(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm23, 2112(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm12, 2048(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 1984(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 1920(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 1856(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 1792(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm1, 1600(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm30, 1536(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 1472(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 1408(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 1344(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 1280(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm19, 1088(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm4, 1024(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 960(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 896(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 832(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 768(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm11, 576(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm10, 512(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 448(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 384(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 320(%rax) -; AVX512DQBW-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQBW-ONLY-NEXT: vmovaps %zmm0, 256(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm2, 64(%rax) -; AVX512DQBW-ONLY-NEXT: vmovdqa64 %zmm3, (%rax) -; AVX512DQBW-ONLY-NEXT: addq $5512, %rsp # imm = 0x1588 -; AVX512DQBW-ONLY-NEXT: vzeroupper -; AVX512DQBW-ONLY-NEXT: retq +; AVX512BW-LABEL: store_i64_stride8_vf64: +; AVX512BW: # %bb.0: +; AVX512BW-NEXT: subq $5512, %rsp # imm = 0x1588 +; AVX512BW-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512BW-NEXT: movq {{[0-9]+}}(%rsp), %r10 +; AVX512BW-NEXT: vmovdqa64 128(%rdi), %zmm2 +; AVX512BW-NEXT: vmovdqa64 64(%rdi), %zmm4 +; AVX512BW-NEXT: vmovdqa64 (%rdi), %zmm8 +; AVX512BW-NEXT: vmovdqa64 128(%rsi), %zmm17 +; AVX512BW-NEXT: vmovdqa64 64(%rsi), %zmm19 +; AVX512BW-NEXT: vmovdqa64 (%rsi), %zmm22 +; AVX512BW-NEXT: vmovdqa64 64(%rdx), %zmm5 +; AVX512BW-NEXT: vmovdqa64 (%rdx), %zmm10 +; AVX512BW-NEXT: vmovdqa64 64(%rcx), %zmm20 +; AVX512BW-NEXT: vmovdqa64 (%rcx), %zmm11 +; AVX512BW-NEXT: vmovdqa64 (%r8), %zmm1 +; AVX512BW-NEXT: vmovdqa64 64(%r8), %zmm25 +; AVX512BW-NEXT: vmovdqa64 128(%r8), %zmm23 +; AVX512BW-NEXT: vmovdqa64 (%r9), %zmm28 +; AVX512BW-NEXT: vmovdqa64 64(%r9), %zmm26 +; AVX512BW-NEXT: vmovdqa64 128(%r9), %zmm24 +; AVX512BW-NEXT: vmovdqa64 (%r10), %zmm21 +; AVX512BW-NEXT: vmovdqa64 64(%r10), %zmm14 +; AVX512BW-NEXT: vmovdqa64 (%rax), %zmm27 +; AVX512BW-NEXT: vmovdqa64 64(%rax), %zmm16 +; AVX512BW-NEXT: movb $-64, %r11b +; AVX512BW-NEXT: kmovd %r11d, %k1 +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm3 = [4,12,4,12,4,12,4,12] +; AVX512BW-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm21, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm27, %zmm3, %zmm0 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} zmm12 = zmm1[0],zmm28[0],zmm1[2],zmm28[2],zmm1[4],zmm28[4],zmm1[6],zmm28[6] +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm12 {%k1} +; AVX512BW-NEXT: vmovdqa64 %zmm8, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm3, %zmm0 +; AVX512BW-NEXT: vbroadcasti128 {{.*#+}} ymm6 = [4,12,4,12] +; AVX512BW-NEXT: # ymm6 = mem[0,1,0,1] +; AVX512BW-NEXT: vmovdqa64 %zmm10, %zmm15 +; AVX512BW-NEXT: vpermt2q %zmm11, %zmm6, %zmm15 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm15[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm12, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm9 = [5,13,5,13,5,13,5,13] +; AVX512BW-NEXT: # zmm9 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm21, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm27, %zmm9, %zmm0 +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} zmm12 = zmm1[1],zmm28[1],zmm1[3],zmm28[3],zmm1[5],zmm28[5],zmm1[7],zmm28[7] +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm12 {%k1} +; AVX512BW-NEXT: vmovdqa64 %zmm8, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm9, %zmm0 +; AVX512BW-NEXT: vbroadcasti128 {{.*#+}} ymm7 = [5,13,5,13] +; AVX512BW-NEXT: # ymm7 = mem[0,1,0,1] +; AVX512BW-NEXT: vmovdqa64 %zmm10, %zmm15 +; AVX512BW-NEXT: vpermt2q %zmm11, %zmm7, %zmm15 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm15[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm12, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm13 = [6,14,6,14,6,14,6,14] +; AVX512BW-NEXT: # zmm13 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm1, %zmm0 +; AVX512BW-NEXT: vmovdqa64 %zmm1, %zmm29 +; AVX512BW-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm28, %zmm13, %zmm0 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} zmm0 {%k1} = zmm21[0],zmm27[0],zmm21[2],zmm27[2],zmm21[4],zmm27[4],zmm21[6],zmm27[6] +; AVX512BW-NEXT: vmovdqa64 %zmm8, %zmm12 +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm13, %zmm12 +; AVX512BW-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [6,14,6,14] +; AVX512BW-NEXT: # ymm1 = mem[0,1,0,1] +; AVX512BW-NEXT: vmovdqa64 %zmm10, %zmm15 +; AVX512BW-NEXT: vpermt2q %zmm11, %zmm1, %zmm15 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm12 = ymm12[0,1,2,3],ymm15[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm12, %zmm0, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm18 = [7,15,7,15,7,15,7,15] +; AVX512BW-NEXT: # zmm18 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm29, %zmm12 +; AVX512BW-NEXT: vpermt2q %zmm28, %zmm18, %zmm12 +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} zmm12 {%k1} = zmm21[1],zmm27[1],zmm21[3],zmm27[3],zmm21[5],zmm27[5],zmm21[7],zmm27[7] +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm18, %zmm8 +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} ymm30 = [7,15,7,15] +; AVX512BW-NEXT: # ymm30 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vpermt2q %zmm11, %zmm30, %zmm10 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm8 = ymm8[0,1,2,3],ymm10[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm8, %zmm12, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm14, %zmm8 +; AVX512BW-NEXT: vpermt2q %zmm16, %zmm3, %zmm8 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} zmm10 = zmm25[0],zmm26[0],zmm25[2],zmm26[2],zmm25[4],zmm26[4],zmm25[6],zmm26[6] +; AVX512BW-NEXT: vmovdqa64 %zmm8, %zmm10 {%k1} +; AVX512BW-NEXT: vmovdqa64 %zmm4, %zmm8 +; AVX512BW-NEXT: vpermt2q %zmm19, %zmm3, %zmm8 +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm11 +; AVX512BW-NEXT: vmovdqa64 %zmm6, %zmm15 +; AVX512BW-NEXT: vpermt2q %zmm20, %zmm6, %zmm11 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm8 = ymm8[0,1,2,3],ymm11[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm8, %zmm10, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm14, %zmm8 +; AVX512BW-NEXT: vpermt2q %zmm16, %zmm9, %zmm8 +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} zmm10 = zmm25[1],zmm26[1],zmm25[3],zmm26[3],zmm25[5],zmm26[5],zmm25[7],zmm26[7] +; AVX512BW-NEXT: vmovdqa64 %zmm8, %zmm10 {%k1} +; AVX512BW-NEXT: vmovdqa64 %zmm4, %zmm8 +; AVX512BW-NEXT: vpermt2q %zmm19, %zmm9, %zmm8 +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm11 +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm12 +; AVX512BW-NEXT: vpermt2q %zmm20, %zmm7, %zmm11 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm8 = ymm8[0,1,2,3],ymm11[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm8, %zmm10, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm4, %zmm8 +; AVX512BW-NEXT: vpermt2q %zmm19, %zmm13, %zmm8 +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm10 +; AVX512BW-NEXT: vpermt2q %zmm20, %zmm1, %zmm10 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm8 = ymm8[0,1,2,3],ymm10[4,5,6,7] +; AVX512BW-NEXT: vmovdqu64 %zmm25, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm25, %zmm10 +; AVX512BW-NEXT: vmovdqu64 %zmm26, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm26, %zmm13, %zmm10 +; AVX512BW-NEXT: vmovdqa64 %zmm14, %zmm11 +; AVX512BW-NEXT: vmovdqu64 %zmm14, (%rsp) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 %zmm16, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} zmm10 {%k1} = zmm14[0],zmm16[0],zmm14[2],zmm16[2],zmm14[4],zmm16[4],zmm14[6],zmm16[6] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm8, %zmm10, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 128(%r10), %zmm10 +; AVX512BW-NEXT: vpermt2q %zmm19, %zmm18, %zmm4 +; AVX512BW-NEXT: vmovdqa64 128(%rax), %zmm14 +; AVX512BW-NEXT: vpermt2q %zmm20, %zmm30, %zmm5 +; AVX512BW-NEXT: vmovdqa64 %zmm25, %zmm6 +; AVX512BW-NEXT: vpermt2q %zmm26, %zmm18, %zmm6 +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} zmm6 {%k1} = zmm11[1],zmm16[1],zmm11[3],zmm16[3],zmm11[5],zmm16[5],zmm11[7],zmm16[7] +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3],ymm5[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm4, %zmm6, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm10, %zmm4 +; AVX512BW-NEXT: vpermt2q %zmm14, %zmm3, %zmm4 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} zmm5 = zmm23[0],zmm24[0],zmm23[2],zmm24[2],zmm23[4],zmm24[4],zmm23[6],zmm24[6] +; AVX512BW-NEXT: vmovdqa64 %zmm4, %zmm5 {%k1} +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm6 +; AVX512BW-NEXT: vpermt2q %zmm17, %zmm3, %zmm6 +; AVX512BW-NEXT: vmovdqa64 %zmm3, %zmm11 +; AVX512BW-NEXT: vmovdqa64 128(%rdx), %zmm4 +; AVX512BW-NEXT: vmovdqa64 128(%rcx), %zmm7 +; AVX512BW-NEXT: vmovdqa64 %zmm4, %zmm8 +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm15, %zmm8 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm6 = ymm6[0,1,2,3],ymm8[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm6, %zmm5, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm10, %zmm5 +; AVX512BW-NEXT: vpermt2q %zmm14, %zmm9, %zmm5 +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} zmm6 = zmm23[1],zmm24[1],zmm23[3],zmm24[3],zmm23[5],zmm24[5],zmm23[7],zmm24[7] +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm6 {%k1} +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm5 +; AVX512BW-NEXT: vpermt2q %zmm17, %zmm9, %zmm5 +; AVX512BW-NEXT: vmovdqa64 %zmm4, %zmm8 +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm12, %zmm8 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm5 = ymm5[0,1,2,3],ymm8[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm5, %zmm6, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm5 +; AVX512BW-NEXT: vpermt2q %zmm17, %zmm13, %zmm5 +; AVX512BW-NEXT: vmovdqa64 %zmm4, %zmm6 +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm1, %zmm6 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm5 = ymm5[0,1,2,3],ymm6[4,5,6,7] +; AVX512BW-NEXT: vmovdqa64 %zmm23, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm23, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm23, %zmm6 +; AVX512BW-NEXT: vmovdqu64 %zmm24, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm24, %zmm13, %zmm6 +; AVX512BW-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 %zmm14, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} zmm6 {%k1} = zmm10[0],zmm14[0],zmm10[2],zmm14[2],zmm10[4],zmm14[4],zmm10[6],zmm14[6] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm5, %zmm6, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm17, %zmm18, %zmm2 +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm30, %zmm4 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm4[4,5,6,7] +; AVX512BW-NEXT: vpermt2q %zmm24, %zmm18, %zmm3 +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} zmm3 {%k1} = zmm10[1],zmm14[1],zmm10[3],zmm14[3],zmm10[5],zmm14[5],zmm10[7],zmm14[7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm2, %zmm3, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 192(%r10), %zmm10 +; AVX512BW-NEXT: vmovdqa64 192(%rax), %zmm26 +; AVX512BW-NEXT: vmovdqa64 %zmm10, %zmm2 +; AVX512BW-NEXT: vpermt2q %zmm26, %zmm11, %zmm2 +; AVX512BW-NEXT: vmovdqa64 192(%r8), %zmm23 +; AVX512BW-NEXT: vmovdqa64 192(%r9), %zmm29 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} zmm4 = zmm23[0],zmm29[0],zmm23[2],zmm29[2],zmm23[4],zmm29[4],zmm23[6],zmm29[6] +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm4 {%k1} +; AVX512BW-NEXT: vmovdqa64 192(%rdi), %zmm2 +; AVX512BW-NEXT: vmovdqa64 192(%rsi), %zmm5 +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm6 +; AVX512BW-NEXT: vpermt2q %zmm5, %zmm11, %zmm6 +; AVX512BW-NEXT: vmovdqa64 192(%rdx), %zmm3 +; AVX512BW-NEXT: vmovdqa64 192(%rcx), %zmm7 +; AVX512BW-NEXT: vmovdqa64 %zmm3, %zmm8 +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm15, %zmm8 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm6 = ymm6[0,1,2,3],ymm8[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm6, %zmm4, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm10, %zmm4 +; AVX512BW-NEXT: vpermt2q %zmm26, %zmm9, %zmm4 +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} zmm6 = zmm23[1],zmm29[1],zmm23[3],zmm29[3],zmm23[5],zmm29[5],zmm23[7],zmm29[7] +; AVX512BW-NEXT: vmovdqa64 %zmm4, %zmm6 {%k1} +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm4 +; AVX512BW-NEXT: vpermt2q %zmm5, %zmm9, %zmm4 +; AVX512BW-NEXT: vmovdqa64 %zmm3, %zmm8 +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm12, %zmm8 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3],ymm8[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm4, %zmm6, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm4 +; AVX512BW-NEXT: vpermt2q %zmm5, %zmm13, %zmm4 +; AVX512BW-NEXT: vmovdqa64 %zmm3, %zmm6 +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm1, %zmm6 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3],ymm6[4,5,6,7] +; AVX512BW-NEXT: vmovdqa64 %zmm23, %zmm6 +; AVX512BW-NEXT: vpermt2q %zmm29, %zmm13, %zmm6 +; AVX512BW-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} zmm6 {%k1} = zmm10[0],zmm26[0],zmm10[2],zmm26[2],zmm10[4],zmm26[4],zmm10[6],zmm26[6] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm4, %zmm6, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm5, %zmm18, %zmm2 +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm30, %zmm3 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm3[4,5,6,7] +; AVX512BW-NEXT: vmovdqa64 %zmm23, %zmm3 +; AVX512BW-NEXT: vpermt2q %zmm29, %zmm18, %zmm3 +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} zmm3 {%k1} = zmm10[1],zmm26[1],zmm10[3],zmm26[3],zmm10[5],zmm26[5],zmm10[7],zmm26[7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm2, %zmm3, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 256(%r10), %zmm10 +; AVX512BW-NEXT: vmovdqa64 256(%rax), %zmm22 +; AVX512BW-NEXT: vmovdqa64 %zmm10, %zmm2 +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm11, %zmm2 +; AVX512BW-NEXT: vmovdqa64 256(%r8), %zmm0 +; AVX512BW-NEXT: vmovdqa64 256(%r9), %zmm24 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} zmm4 = zmm0[0],zmm24[0],zmm0[2],zmm24[2],zmm0[4],zmm24[4],zmm0[6],zmm24[6] +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm17 +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm4 {%k1} +; AVX512BW-NEXT: vmovdqa64 256(%rdi), %zmm2 +; AVX512BW-NEXT: vmovdqa64 256(%rsi), %zmm5 +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm6 +; AVX512BW-NEXT: vpermt2q %zmm5, %zmm11, %zmm6 +; AVX512BW-NEXT: vmovdqa64 256(%rdx), %zmm3 +; AVX512BW-NEXT: vmovdqa64 256(%rcx), %zmm7 +; AVX512BW-NEXT: vmovdqa64 %zmm3, %zmm8 +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm15, %zmm8 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm6 = ymm6[0,1,2,3],ymm8[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm6, %zmm4, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm10, %zmm4 +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm9, %zmm4 +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} zmm6 = zmm17[1],zmm24[1],zmm17[3],zmm24[3],zmm17[5],zmm24[5],zmm17[7],zmm24[7] +; AVX512BW-NEXT: vmovdqa64 %zmm4, %zmm6 {%k1} +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm4 +; AVX512BW-NEXT: vpermt2q %zmm5, %zmm9, %zmm4 +; AVX512BW-NEXT: vmovdqa64 %zmm3, %zmm8 +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm12, %zmm8 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3],ymm8[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm4, %zmm6, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm4 +; AVX512BW-NEXT: vpermt2q %zmm5, %zmm13, %zmm4 +; AVX512BW-NEXT: vmovdqa64 %zmm3, %zmm6 +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm1, %zmm6 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3],ymm6[4,5,6,7] +; AVX512BW-NEXT: vmovdqu64 %zmm17, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm17, %zmm6 +; AVX512BW-NEXT: vpermt2q %zmm24, %zmm13, %zmm6 +; AVX512BW-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} zmm6 {%k1} = zmm10[0],zmm22[0],zmm10[2],zmm22[2],zmm10[4],zmm22[4],zmm10[6],zmm22[6] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm4, %zmm6, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm5, %zmm18, %zmm2 +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm30, %zmm3 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm3[4,5,6,7] +; AVX512BW-NEXT: vmovdqa64 %zmm17, %zmm3 +; AVX512BW-NEXT: vpermt2q %zmm24, %zmm18, %zmm3 +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} zmm3 {%k1} = zmm10[1],zmm22[1],zmm10[3],zmm22[3],zmm10[5],zmm22[5],zmm10[7],zmm22[7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm2, %zmm3, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 320(%rdi), %zmm2 +; AVX512BW-NEXT: vmovdqa64 320(%rsi), %zmm3 +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm5 +; AVX512BW-NEXT: vpermt2q %zmm3, %zmm11, %zmm5 +; AVX512BW-NEXT: vmovdqa64 320(%rdx), %zmm14 +; AVX512BW-NEXT: vmovdqa64 320(%rcx), %zmm6 +; AVX512BW-NEXT: vmovdqa64 %zmm14, %zmm7 +; AVX512BW-NEXT: vpermt2q %zmm6, %zmm15, %zmm7 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm5 = ymm5[0,1,2,3],ymm7[4,5,6,7] +; AVX512BW-NEXT: vmovdqa64 %zmm14, %zmm7 +; AVX512BW-NEXT: vpermt2q %zmm6, %zmm12, %zmm7 +; AVX512BW-NEXT: vmovdqa64 %zmm14, %zmm8 +; AVX512BW-NEXT: vpermt2q %zmm6, %zmm1, %zmm8 +; AVX512BW-NEXT: vpermt2q %zmm6, %zmm30, %zmm14 +; AVX512BW-NEXT: vmovdqa64 384(%rdx), %zmm0 +; AVX512BW-NEXT: vmovdqa64 384(%rcx), %zmm6 +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm10 +; AVX512BW-NEXT: vpermt2q %zmm6, %zmm15, %zmm10 +; AVX512BW-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm10 +; AVX512BW-NEXT: vpermt2q %zmm6, %zmm12, %zmm10 +; AVX512BW-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm10 +; AVX512BW-NEXT: vpermt2q %zmm6, %zmm1, %zmm10 +; AVX512BW-NEXT: vmovdqu64 %zmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm6, %zmm30, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 448(%rdx), %zmm0 +; AVX512BW-NEXT: vmovdqa64 448(%rcx), %zmm6 +; AVX512BW-NEXT: vpermi2q %zmm6, %zmm0, %zmm15 +; AVX512BW-NEXT: vmovdqu64 %zmm15, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermi2q %zmm6, %zmm0, %zmm12 +; AVX512BW-NEXT: vmovdqu64 %zmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermi2q %zmm6, %zmm0, %zmm1 +; AVX512BW-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm6, %zmm30, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 320(%r10), %zmm31 +; AVX512BW-NEXT: vmovdqa64 320(%rax), %zmm12 +; AVX512BW-NEXT: vmovdqa64 %zmm31, %zmm1 +; AVX512BW-NEXT: vpermt2q %zmm12, %zmm11, %zmm1 +; AVX512BW-NEXT: vmovdqa64 320(%r8), %zmm17 +; AVX512BW-NEXT: vmovdqa64 320(%r9), %zmm4 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} zmm10 = zmm17[0],zmm4[0],zmm17[2],zmm4[2],zmm17[4],zmm4[4],zmm17[6],zmm4[6] +; AVX512BW-NEXT: vmovdqa64 %zmm1, %zmm10 {%k1} +; AVX512BW-NEXT: vinserti64x4 $0, %ymm5, %zmm10, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm31, %zmm1 +; AVX512BW-NEXT: vpermt2q %zmm12, %zmm9, %zmm1 +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} zmm5 = zmm17[1],zmm4[1],zmm17[3],zmm4[3],zmm17[5],zmm4[5],zmm17[7],zmm4[7] +; AVX512BW-NEXT: vmovdqa64 %zmm1, %zmm5 {%k1} +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm1 +; AVX512BW-NEXT: vpermt2q %zmm3, %zmm9, %zmm1 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm7[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm1, %zmm5, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm1 +; AVX512BW-NEXT: vpermt2q %zmm3, %zmm13, %zmm1 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm8[4,5,6,7] +; AVX512BW-NEXT: vmovdqa64 %zmm17, %zmm5 +; AVX512BW-NEXT: vpermt2q %zmm4, %zmm13, %zmm5 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} zmm5 {%k1} = zmm31[0],zmm12[0],zmm31[2],zmm12[2],zmm31[4],zmm12[4],zmm31[6],zmm12[6] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm1, %zmm5, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm3, %zmm18, %zmm2 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm1 = ymm2[0,1,2,3],ymm14[4,5,6,7] +; AVX512BW-NEXT: vmovdqa64 %zmm17, %zmm2 +; AVX512BW-NEXT: vpermt2q %zmm4, %zmm18, %zmm2 +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} zmm2 {%k1} = zmm31[1],zmm12[1],zmm31[3],zmm12[3],zmm31[5],zmm12[5],zmm31[7],zmm12[7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm1, %zmm2, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 384(%rdi), %zmm0 +; AVX512BW-NEXT: vmovdqa64 384(%rsi), %zmm1 +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm3 +; AVX512BW-NEXT: vmovdqa64 %zmm11, %zmm2 +; AVX512BW-NEXT: vpermt2q %zmm1, %zmm11, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm3 +; AVX512BW-NEXT: vpermt2q %zmm1, %zmm9, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm3 +; AVX512BW-NEXT: vpermt2q %zmm1, %zmm13, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm1, %zmm18, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 384(%r10), %zmm11 +; AVX512BW-NEXT: vmovdqa64 384(%rax), %zmm20 +; AVX512BW-NEXT: vmovdqa64 %zmm11, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm20, %zmm2, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm11, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm20, %zmm9, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 384(%r8), %zmm30 +; AVX512BW-NEXT: vmovdqa64 384(%r9), %zmm0 +; AVX512BW-NEXT: vmovdqa64 %zmm30, %zmm1 +; AVX512BW-NEXT: vpermt2q %zmm0, %zmm13, %zmm1 +; AVX512BW-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 448(%r10), %zmm16 +; AVX512BW-NEXT: vmovdqa64 448(%rax), %zmm8 +; AVX512BW-NEXT: vmovdqa64 %zmm16, %zmm1 +; AVX512BW-NEXT: vpermt2q %zmm8, %zmm2, %zmm1 +; AVX512BW-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 448(%rdi), %zmm3 +; AVX512BW-NEXT: vmovdqa64 448(%rsi), %zmm1 +; AVX512BW-NEXT: vpermi2q %zmm1, %zmm3, %zmm2 +; AVX512BW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm16, %zmm2 +; AVX512BW-NEXT: vpermt2q %zmm8, %zmm9, %zmm2 +; AVX512BW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermi2q %zmm1, %zmm3, %zmm9 +; AVX512BW-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 448(%r8), %zmm19 +; AVX512BW-NEXT: vmovdqa64 448(%r9), %zmm7 +; AVX512BW-NEXT: vmovdqa64 %zmm19, %zmm2 +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm13, %zmm2 +; AVX512BW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermi2q %zmm1, %zmm3, %zmm13 +; AVX512BW-NEXT: vmovdqu64 %zmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm1, %zmm18, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm30, %zmm1 +; AVX512BW-NEXT: vpermt2q %zmm0, %zmm18, %zmm1 +; AVX512BW-NEXT: vmovdqa64 %zmm1, %zmm5 +; AVX512BW-NEXT: vmovdqa64 %zmm19, %zmm1 +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm18, %zmm1 +; AVX512BW-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm15 = [0,8,0,8,0,8,0,8] +; AVX512BW-NEXT: # zmm15 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm21, %zmm1 +; AVX512BW-NEXT: vpermt2q %zmm27, %zmm15, %zmm1 +; AVX512BW-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm14 = [1,9,1,9,1,9,1,9] +; AVX512BW-NEXT: # zmm14 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm21, %zmm1 +; AVX512BW-NEXT: vpermt2q %zmm27, %zmm14, %zmm1 +; AVX512BW-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm6 = [2,10,2,10,2,10,2,10] +; AVX512BW-NEXT: # zmm6 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm21, %zmm1 +; AVX512BW-NEXT: vpermt2q %zmm27, %zmm6, %zmm1 +; AVX512BW-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm1 = [3,11,3,11,3,11,3,11] +; AVX512BW-NEXT: # zmm1 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vpermt2q %zmm27, %zmm1, %zmm21 +; AVX512BW-NEXT: vmovdqu64 %zmm21, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm3 +; AVX512BW-NEXT: vpermt2q %zmm28, %zmm15, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm3 +; AVX512BW-NEXT: vpermt2q %zmm28, %zmm14, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm25 +; AVX512BW-NEXT: vpermt2q %zmm28, %zmm6, %zmm25 +; AVX512BW-NEXT: vpermt2q %zmm28, %zmm1, %zmm2 +; AVX512BW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 (%rsp), %zmm27 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm27, %zmm2 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm3, %zmm15, %zmm2 +; AVX512BW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm27, %zmm2 +; AVX512BW-NEXT: vpermt2q %zmm3, %zmm14, %zmm2 +; AVX512BW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm27, %zmm2 +; AVX512BW-NEXT: vpermt2q %zmm3, %zmm6, %zmm2 +; AVX512BW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm3, %zmm1, %zmm27 +; AVX512BW-NEXT: vmovdqu64 %zmm27, (%rsp) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm9, %zmm3 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm15, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm9, %zmm3 +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm14, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm9, %zmm18 +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm6, %zmm18 +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm1, %zmm9 +; AVX512BW-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm3 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm9, %zmm15, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm3 +; AVX512BW-NEXT: vpermt2q %zmm9, %zmm14, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm3 +; AVX512BW-NEXT: vpermt2q %zmm9, %zmm6, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm9, %zmm1, %zmm2 +; AVX512BW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm9, %zmm3 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm15, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm9, %zmm3 +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm14, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm9, %zmm13 +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm6, %zmm13 +; AVX512BW-NEXT: vpermt2q %zmm2, %zmm1, %zmm9 +; AVX512BW-NEXT: vmovdqu64 %zmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm3 +; AVX512BW-NEXT: vpermt2q %zmm26, %zmm15, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm3 +; AVX512BW-NEXT: vpermt2q %zmm26, %zmm14, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm3 +; AVX512BW-NEXT: vpermt2q %zmm26, %zmm6, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm26, %zmm1, %zmm2 +; AVX512BW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm23, %zmm3 +; AVX512BW-NEXT: vpermt2q %zmm29, %zmm15, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm23, %zmm3 +; AVX512BW-NEXT: vpermt2q %zmm29, %zmm14, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm23, %zmm10 +; AVX512BW-NEXT: vpermt2q %zmm29, %zmm6, %zmm10 +; AVX512BW-NEXT: vpermt2q %zmm29, %zmm1, %zmm23 +; AVX512BW-NEXT: vmovdqu64 %zmm23, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm23 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm23, %zmm2 +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm15, %zmm2 +; AVX512BW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm23, %zmm2 +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm14, %zmm2 +; AVX512BW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm23, %zmm2 +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm6, %zmm2 +; AVX512BW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm22, %zmm1, %zmm23 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm3 +; AVX512BW-NEXT: vpermt2q %zmm24, %zmm15, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm3 +; AVX512BW-NEXT: vpermt2q %zmm24, %zmm14, %zmm3 +; AVX512BW-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm26 +; AVX512BW-NEXT: vpermt2q %zmm24, %zmm6, %zmm26 +; AVX512BW-NEXT: vpermt2q %zmm24, %zmm1, %zmm2 +; AVX512BW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm31, %zmm2 +; AVX512BW-NEXT: vpermt2q %zmm12, %zmm15, %zmm2 +; AVX512BW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm31, %zmm2 +; AVX512BW-NEXT: vpermt2q %zmm12, %zmm14, %zmm2 +; AVX512BW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm31, %zmm2 +; AVX512BW-NEXT: vpermt2q %zmm12, %zmm6, %zmm2 +; AVX512BW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vpermt2q %zmm12, %zmm1, %zmm31 +; AVX512BW-NEXT: vmovdqa64 %zmm17, %zmm29 +; AVX512BW-NEXT: vpermt2q %zmm4, %zmm15, %zmm29 +; AVX512BW-NEXT: vmovdqa64 %zmm17, %zmm2 +; AVX512BW-NEXT: vpermt2q %zmm4, %zmm14, %zmm2 +; AVX512BW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm17, %zmm24 +; AVX512BW-NEXT: vpermt2q %zmm4, %zmm6, %zmm24 +; AVX512BW-NEXT: vpermt2q %zmm4, %zmm1, %zmm17 +; AVX512BW-NEXT: vmovdqa64 %zmm11, %zmm2 +; AVX512BW-NEXT: vpermt2q %zmm20, %zmm15, %zmm2 +; AVX512BW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm11, %zmm2 +; AVX512BW-NEXT: vpermt2q %zmm20, %zmm14, %zmm2 +; AVX512BW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm9 # 64-byte Reload +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} zmm9 {%k1} = zmm11[0],zmm20[0],zmm11[2],zmm20[2],zmm11[4],zmm20[4],zmm11[6],zmm20[6] +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} zmm5 {%k1} = zmm11[1],zmm20[1],zmm11[3],zmm20[3],zmm11[5],zmm20[5],zmm11[7],zmm20[7] +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm27 +; AVX512BW-NEXT: vmovdqa64 %zmm11, %zmm22 +; AVX512BW-NEXT: vpermt2q %zmm20, %zmm6, %zmm22 +; AVX512BW-NEXT: vpermt2q %zmm20, %zmm1, %zmm11 +; AVX512BW-NEXT: vmovdqa64 %zmm30, %zmm21 +; AVX512BW-NEXT: vpermt2q %zmm0, %zmm15, %zmm21 +; AVX512BW-NEXT: vmovdqa64 %zmm30, %zmm28 +; AVX512BW-NEXT: vpermt2q %zmm0, %zmm14, %zmm28 +; AVX512BW-NEXT: vmovdqa64 %zmm30, %zmm20 +; AVX512BW-NEXT: vpermt2q %zmm0, %zmm6, %zmm20 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} zmm2 = zmm30[0],zmm0[0],zmm30[2],zmm0[2],zmm30[4],zmm0[4],zmm30[6],zmm0[6] +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} zmm3 = zmm30[1],zmm0[1],zmm30[3],zmm0[3],zmm30[5],zmm0[5],zmm30[7],zmm0[7] +; AVX512BW-NEXT: vpermt2q %zmm0, %zmm1, %zmm30 +; AVX512BW-NEXT: vmovdqa64 %zmm16, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm8, %zmm15, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqa64 %zmm16, %zmm0 +; AVX512BW-NEXT: vpermt2q %zmm8, %zmm14, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} zmm4 {%k1} = zmm16[0],zmm8[0],zmm16[2],zmm8[2],zmm16[4],zmm8[4],zmm16[6],zmm8[6] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} zmm5 {%k1} = zmm16[1],zmm8[1],zmm16[3],zmm8[3],zmm16[5],zmm8[5],zmm16[7],zmm8[7] +; AVX512BW-NEXT: vmovdqa64 %zmm16, %zmm12 +; AVX512BW-NEXT: vpermt2q %zmm8, %zmm6, %zmm12 +; AVX512BW-NEXT: vpermt2q %zmm8, %zmm1, %zmm16 +; AVX512BW-NEXT: vpermi2q %zmm7, %zmm19, %zmm15 +; AVX512BW-NEXT: vpermi2q %zmm7, %zmm19, %zmm14 +; AVX512BW-NEXT: vpermi2q %zmm7, %zmm19, %zmm6 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} zmm8 = zmm19[0],zmm7[0],zmm19[2],zmm7[2],zmm19[4],zmm7[4],zmm19[6],zmm7[6] +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} zmm0 = zmm19[1],zmm7[1],zmm19[3],zmm7[3],zmm19[5],zmm7[5],zmm19[7],zmm7[7] +; AVX512BW-NEXT: vpermt2q %zmm7, %zmm1, %zmm19 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512BW-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload +; AVX512BW-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm7, %zmm2 {%k1} +; AVX512BW-NEXT: vinserti64x4 $0, %ymm1, %zmm2, %zmm1 +; AVX512BW-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512BW-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload +; AVX512BW-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm3 {%k1} +; AVX512BW-NEXT: vinserti64x4 $0, %ymm1, %zmm3, %zmm1 +; AVX512BW-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512BW-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload +; AVX512BW-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm1, %zmm9, %zmm1 +; AVX512BW-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512BW-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload +; AVX512BW-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm1, %zmm27, %zmm1 +; AVX512BW-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512BW-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload +; AVX512BW-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm8 {%k1} +; AVX512BW-NEXT: vinserti64x4 $0, %ymm1, %zmm8, %zmm1 +; AVX512BW-NEXT: vmovdqu64 %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512BW-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1, %ymm1 # 32-byte Folded Reload +; AVX512BW-NEXT: # ymm1 = ymm1[0,1,2,3],mem[4,5,6,7] +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm0 {%k1} +; AVX512BW-NEXT: vinserti64x4 $0, %ymm1, %zmm0, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 32-byte Folded Reload +; AVX512BW-NEXT: # ymm0 = ymm0[0,1,2,3],mem[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm4, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vpblendd $240, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 32-byte Folded Reload +; AVX512BW-NEXT: # ymm0 = ymm0[0,1,2,3],mem[4,5,6,7] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm5, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm25 {%k1} +; AVX512BW-NEXT: vmovdqa (%rcx), %ymm0 +; AVX512BW-NEXT: vmovdqa (%rdx), %ymm1 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] +; AVX512BW-NEXT: vmovdqa (%rsi), %ymm3 +; AVX512BW-NEXT: vmovdqa (%rdi), %ymm7 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm7[0],ymm3[0],ymm7[2],ymm3[2] +; AVX512BW-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm8[2,3],ymm2[2,3] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm2, %zmm25, %zmm2 +; AVX512BW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm4 {%k1} +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm7[1],ymm3[1],ymm7[3],ymm3[3] +; AVX512BW-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm4, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm18 {%k1} +; AVX512BW-NEXT: vmovdqa 64(%rcx), %ymm0 +; AVX512BW-NEXT: vmovdqa 64(%rdx), %ymm1 +; AVX512BW-NEXT: vmovdqa 64(%rsi), %ymm2 +; AVX512BW-NEXT: vmovdqa 64(%rdi), %ymm3 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} ymm7 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm3[0],ymm2[0],ymm3[2],ymm2[2] +; AVX512BW-NEXT: vperm2i128 {{.*#+}} ymm7 = ymm8[2,3],ymm7[2,3] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm7, %zmm18, %zmm4 +; AVX512BW-NEXT: vmovdqu64 %zmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 (%rsp), %zmm4 # 64-byte Reload +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm4, %zmm5 {%k1} +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm3[1],ymm2[1],ymm3[3],ymm2[3] +; AVX512BW-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm5, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm13 {%k1} +; AVX512BW-NEXT: vmovdqa 128(%rcx), %ymm0 +; AVX512BW-NEXT: vmovdqa 128(%rdx), %ymm1 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] +; AVX512BW-NEXT: vmovdqa 128(%rsi), %ymm3 +; AVX512BW-NEXT: vmovdqa 128(%rdi), %ymm7 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm7[0],ymm3[0],ymm7[2],ymm3[2] +; AVX512BW-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm8[2,3],ymm2[2,3] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm2, %zmm13, %zmm2 +; AVX512BW-NEXT: vmovdqu64 %zmm2, (%rsp) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm4 {%k1} +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm7[1],ymm3[1],ymm7[3],ymm3[3] +; AVX512BW-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm4, %zmm0 +; AVX512BW-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm10 {%k1} +; AVX512BW-NEXT: vmovdqa 192(%rcx), %ymm0 +; AVX512BW-NEXT: vmovdqa 192(%rdx), %ymm1 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] +; AVX512BW-NEXT: vmovdqa 192(%rsi), %ymm3 +; AVX512BW-NEXT: vmovdqa 192(%rdi), %ymm7 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm7[0],ymm3[0],ymm7[2],ymm3[2] +; AVX512BW-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm8[2,3],ymm2[2,3] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm2, %zmm10, %zmm2 +; AVX512BW-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm4 {%k1} +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm7[1],ymm3[1],ymm7[3],ymm3[3] +; AVX512BW-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm4, %zmm9 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm26 {%k1} +; AVX512BW-NEXT: vmovdqa 256(%rcx), %ymm0 +; AVX512BW-NEXT: vmovdqa 256(%rdx), %ymm1 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] +; AVX512BW-NEXT: vmovdqa 256(%rsi), %ymm3 +; AVX512BW-NEXT: vmovdqa 256(%rdi), %ymm7 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm7[0],ymm3[0],ymm7[2],ymm3[2] +; AVX512BW-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm8[2,3],ymm2[2,3] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm2, %zmm26, %zmm26 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm23, %zmm2 {%k1} +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm7[1],ymm3[1],ymm7[3],ymm3[3] +; AVX512BW-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm2, %zmm7 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm0, %zmm24 {%k1} +; AVX512BW-NEXT: vmovdqa 320(%rcx), %ymm0 +; AVX512BW-NEXT: vmovdqa 320(%rdx), %ymm1 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] +; AVX512BW-NEXT: vmovdqa 320(%rsi), %ymm3 +; AVX512BW-NEXT: vmovdqa64 320(%rdi), %ymm23 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} ymm8 = ymm23[0],ymm3[0],ymm23[2],ymm3[2] +; AVX512BW-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm8[2,3],ymm2[2,3] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm2, %zmm24, %zmm8 +; AVX512BW-NEXT: vmovdqa64 %zmm31, %zmm17 {%k1} +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm23[1],ymm3[1],ymm23[3],ymm3[3] +; AVX512BW-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm17, %zmm17 +; AVX512BW-NEXT: vmovdqa64 %zmm22, %zmm20 {%k1} +; AVX512BW-NEXT: vmovdqa 384(%rcx), %ymm0 +; AVX512BW-NEXT: vmovdqa 384(%rdx), %ymm1 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] +; AVX512BW-NEXT: vmovdqa 384(%rsi), %ymm3 +; AVX512BW-NEXT: vmovdqa64 384(%rdi), %ymm18 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} ymm13 = ymm18[0],ymm3[0],ymm18[2],ymm3[2] +; AVX512BW-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm13[2,3],ymm2[2,3] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm2, %zmm20, %zmm20 +; AVX512BW-NEXT: vmovdqa64 %zmm11, %zmm30 {%k1} +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm18[1],ymm3[1],ymm18[3],ymm3[3] +; AVX512BW-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm30, %zmm24 +; AVX512BW-NEXT: vmovdqa64 %zmm12, %zmm6 {%k1} +; AVX512BW-NEXT: vmovdqa 448(%rcx), %ymm0 +; AVX512BW-NEXT: vmovdqa 448(%rdx), %ymm1 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] +; AVX512BW-NEXT: vmovdqa 448(%rsi), %ymm3 +; AVX512BW-NEXT: vmovdqa 448(%rdi), %ymm10 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} ymm12 = ymm10[0],ymm3[0],ymm10[2],ymm3[2] +; AVX512BW-NEXT: vperm2i128 {{.*#+}} ymm2 = ymm12[2,3],ymm2[2,3] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm2, %zmm6, %zmm31 +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3] +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm10[1],ymm3[1],ymm10[3],ymm3[3] +; AVX512BW-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3] +; AVX512BW-NEXT: vmovdqa64 %zmm16, %zmm19 {%k1} +; AVX512BW-NEXT: vinserti64x4 $0, %ymm0, %zmm19, %zmm0 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm1, %zmm4 {%k1} +; AVX512BW-NEXT: vmovdqa (%rsi), %xmm1 +; AVX512BW-NEXT: vinserti128 $1, (%rcx), %ymm1, %ymm1 +; AVX512BW-NEXT: vmovdqa (%rdi), %xmm2 +; AVX512BW-NEXT: vinserti128 $1, (%rdx), %ymm2, %ymm2 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} ymm3 = ymm2[0],ymm1[0],ymm2[2],ymm1[2] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm3, %zmm4, %zmm3 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Reload +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm10 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm4, %zmm10 {%k1} +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm2[1],ymm1[1],ymm2[3],ymm1[3] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm1, %zmm10, %zmm2 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm1, %zmm11 {%k1} +; AVX512BW-NEXT: vmovdqa 64(%rsi), %xmm1 +; AVX512BW-NEXT: vinserti128 $1, 64(%rcx), %ymm1, %ymm1 +; AVX512BW-NEXT: vmovdqa 64(%rdi), %xmm4 +; AVX512BW-NEXT: vinserti128 $1, 64(%rdx), %ymm4, %ymm4 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} ymm10 = ymm4[0],ymm1[0],ymm4[2],ymm1[2] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm10, %zmm11, %zmm10 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm11 # 64-byte Reload +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm11, %zmm12 {%k1} +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm4[1],ymm1[1],ymm4[3],ymm1[3] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm1, %zmm12, %zmm11 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm1, %zmm13 {%k1} +; AVX512BW-NEXT: vmovdqa 128(%rsi), %xmm1 +; AVX512BW-NEXT: vinserti128 $1, 128(%rcx), %ymm1, %ymm1 +; AVX512BW-NEXT: vmovdqa 128(%rdi), %xmm4 +; AVX512BW-NEXT: vinserti128 $1, 128(%rdx), %ymm4, %ymm12 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} ymm4 = ymm12[0],ymm1[0],ymm12[2],ymm1[2] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm4, %zmm13, %zmm4 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm18 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm13, %zmm18 {%k1} +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm12[1],ymm1[1],ymm12[3],ymm1[3] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm1, %zmm18, %zmm19 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm18 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm1, %zmm18 {%k1} +; AVX512BW-NEXT: vmovdqa 192(%rsi), %xmm1 +; AVX512BW-NEXT: vinserti128 $1, 192(%rcx), %ymm1, %ymm1 +; AVX512BW-NEXT: vmovdqa 192(%rdi), %xmm12 +; AVX512BW-NEXT: vinserti128 $1, 192(%rdx), %ymm12, %ymm12 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} ymm13 = ymm12[0],ymm1[0],ymm12[2],ymm1[2] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm13, %zmm18, %zmm30 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm13 # 64-byte Reload +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm18 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm13, %zmm18 {%k1} +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm12[1],ymm1[1],ymm12[3],ymm1[3] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm1, %zmm18, %zmm1 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm12 # 64-byte Reload +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm12, %zmm5 {%k1} +; AVX512BW-NEXT: vmovdqa 256(%rsi), %xmm12 +; AVX512BW-NEXT: vinserti128 $1, 256(%rcx), %ymm12, %ymm13 +; AVX512BW-NEXT: vmovdqa 256(%rdi), %xmm12 +; AVX512BW-NEXT: vinserti32x4 $1, 256(%rdx), %ymm12, %ymm18 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} ymm12 = ymm18[0],ymm13[0],ymm18[2],ymm13[2] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm12, %zmm5, %zmm12 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm23 # 64-byte Reload +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm23, %zmm5 {%k1} +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm13 = ymm18[1],ymm13[1],ymm18[3],ymm13[3] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm13, %zmm5, %zmm23 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm29 {%k1} +; AVX512BW-NEXT: vmovdqa 320(%rsi), %xmm13 +; AVX512BW-NEXT: vinserti128 $1, 320(%rcx), %ymm13, %ymm13 +; AVX512BW-NEXT: vmovdqa64 320(%rdi), %xmm18 +; AVX512BW-NEXT: vinserti32x4 $1, 320(%rdx), %ymm18, %ymm18 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} ymm27 = ymm18[0],ymm13[0],ymm18[2],ymm13[2] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm27, %zmm29, %zmm22 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm6 {%k1} +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm13 = ymm18[1],ymm13[1],ymm18[3],ymm13[3] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm13, %zmm6, %zmm13 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm21 {%k1} +; AVX512BW-NEXT: vmovdqa64 384(%rsi), %xmm18 +; AVX512BW-NEXT: vinserti32x4 $1, 384(%rcx), %ymm18, %ymm18 +; AVX512BW-NEXT: vmovdqa64 384(%rdi), %xmm25 +; AVX512BW-NEXT: vinserti32x4 $1, 384(%rdx), %ymm25, %ymm25 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} ymm27 = ymm25[0],ymm18[0],ymm25[2],ymm18[2] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm27, %zmm21, %zmm16 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm28 {%k1} +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm18 = ymm25[1],ymm18[1],ymm25[3],ymm18[3] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm18, %zmm28, %zmm21 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm15 {%k1} +; AVX512BW-NEXT: vmovdqa64 448(%rsi), %xmm18 +; AVX512BW-NEXT: vinserti32x4 $1, 448(%rcx), %ymm18, %ymm18 +; AVX512BW-NEXT: vmovdqa64 448(%rdi), %xmm25 +; AVX512BW-NEXT: vinserti32x4 $1, 448(%rdx), %ymm25, %ymm25 +; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} ymm27 = ymm25[0],ymm18[0],ymm25[2],ymm18[2] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm27, %zmm15, %zmm6 +; AVX512BW-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm5 # 64-byte Reload +; AVX512BW-NEXT: vmovdqa64 %zmm5, %zmm14 {%k1} +; AVX512BW-NEXT: vpunpckhqdq {{.*#+}} ymm18 = ymm25[1],ymm18[1],ymm25[3],ymm18[3] +; AVX512BW-NEXT: vinserti64x4 $0, %ymm18, %zmm14, %zmm5 +; AVX512BW-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512BW-NEXT: vmovdqa64 %zmm0, 3776(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm31, 3712(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm24, 3264(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm20, 3200(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm17, 2752(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm8, 2688(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm7, 2240(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm26, 2176(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm9, 1728(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 1664(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 1216(%rax) +; AVX512BW-NEXT: vmovups (%rsp), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 1152(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 704(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 640(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 192(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 128(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 4032(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 3968(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 3904(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 3840(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm5, 3648(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm6, 3584(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 3520(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 3456(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 3392(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 3328(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm21, 3136(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm16, 3072(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 3008(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 2944(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 2880(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 2816(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm13, 2624(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm22, 2560(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 2496(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 2432(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 2368(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 2304(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm23, 2112(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm12, 2048(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 1984(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 1920(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 1856(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 1792(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm1, 1600(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm30, 1536(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 1472(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 1408(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 1344(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 1280(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm19, 1088(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm4, 1024(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 960(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 896(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 832(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 768(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm11, 576(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm10, 512(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 448(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 384(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 320(%rax) +; AVX512BW-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512BW-NEXT: vmovaps %zmm0, 256(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm2, 64(%rax) +; AVX512BW-NEXT: vmovdqa64 %zmm3, (%rax) +; AVX512BW-NEXT: addq $5512, %rsp # imm = 0x1588 +; AVX512BW-NEXT: vzeroupper +; AVX512BW-NEXT: retq %in.vec0 = load <64 x i64>, ptr %in.vecptr0, align 64 %in.vec1 = load <64 x i64>, ptr %in.vecptr1, align 64 %in.vec2 = load <64 x i64>, ptr %in.vecptr2, align 64 @@ -12856,14 +10880,18 @@ define void @store_i64_stride8_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve ; AVX512-FAST: {{.*}} ; AVX512-SLOW: {{.*}} ; AVX512BW-FAST: {{.*}} +; AVX512BW-ONLY: {{.*}} ; AVX512BW-ONLY-FAST: {{.*}} ; AVX512BW-ONLY-SLOW: {{.*}} ; AVX512BW-SLOW: {{.*}} ; AVX512DQ-FAST: {{.*}} +; AVX512DQ-ONLY: {{.*}} ; AVX512DQ-SLOW: {{.*}} ; AVX512DQBW-FAST: {{.*}} +; AVX512DQBW-ONLY: {{.*}} ; AVX512DQBW-SLOW: {{.*}} ; AVX512F-FAST: {{.*}} +; AVX512F-ONLY: {{.*}} ; AVX512F-ONLY-FAST: {{.*}} ; AVX512F-ONLY-SLOW: {{.*}} ; AVX512F-SLOW: {{.*}} diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll index f101f22c58b1..f4fda97c0817 100644 --- a/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll +++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll @@ -4241,185 +4241,185 @@ define void @store_i8_stride5_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec ; AVX512F-FAST-NEXT: vzeroupper ; AVX512F-FAST-NEXT: retq ; -; AVX512BW-ONLY-SLOW-LABEL: store_i8_stride5_vf64: -; AVX512BW-ONLY-SLOW: # %bb.0: -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 (%r8), %zmm3 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa (%rcx), %ymm0 -; AVX512BW-ONLY-SLOW-NEXT: vpbroadcastq {{.*#+}} ymm8 = [9,14,11,0,13,10,15,12,9,14,11,0,13,10,15,12,9,14,11,0,13,10,15,12,9,14,11,0,13,10,15,12] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm8, %ymm0, %ymm2 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa (%rdx), %ymm1 -; AVX512BW-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm4 = ymm1[0,1,2,3,5,6,7,6,8,9,10,11,13,14,15,14] -; AVX512BW-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm4 = ymm4[2,2,3,3,6,6,7,7] -; AVX512BW-ONLY-SLOW-NEXT: movl $693250386, %eax # imm = 0x29522952 -; AVX512BW-ONLY-SLOW-NEXT: kmovd %eax, %k1 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %ymm4, %ymm2 {%k1} -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm2 = ymm2[2,2,3,3] -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa 32(%rdx), %xmm6 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa 32(%rcx), %xmm12 -; AVX512BW-ONLY-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm4 = xmm12[0],xmm6[0],xmm12[1],xmm6[1],xmm12[2],xmm6[2],xmm12[3],xmm6[3],xmm12[4],xmm6[4],xmm12[5],xmm6[5],xmm12[6],xmm6[6],xmm12[7],xmm6[7] -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} xmm7 = <2,u,1,0,5,4,u,3,u,7,6,11,10,u,9,8> -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm7, %xmm4, %xmm4 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm4 = ymm4[0,0,1,1] -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm4, %zmm2, %zmm10 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa (%rsi), %ymm4 -; AVX512BW-ONLY-SLOW-NEXT: vpbroadcastq {{.*#+}} ymm15 = [11,0,13,10,15,12,0,14,11,0,13,10,15,12,0,14,11,0,13,10,15,12,0,14,11,0,13,10,15,12,0,14] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm15, %ymm4, %ymm2 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa (%rdi), %ymm5 -; AVX512BW-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm9 = ymm5[0,1,2,3,6,5,6,7,8,9,10,11,14,13,14,15] -; AVX512BW-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm9 = ymm9[2,2,3,3,6,6,7,7] -; AVX512BW-ONLY-SLOW-NEXT: movl $1251232404, %eax # imm = 0x4A944A94 -; AVX512BW-ONLY-SLOW-NEXT: kmovd %eax, %k5 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %ymm9, %ymm2 {%k5} -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm2 = ymm2[2,2,3,3] -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa 32(%rsi), %xmm13 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa 32(%rdi), %xmm14 -; AVX512BW-ONLY-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm11 = xmm14[0],xmm13[0],xmm14[1],xmm13[1],xmm14[2],xmm13[2],xmm14[3],xmm13[3],xmm14[4],xmm13[4],xmm14[5],xmm13[5],xmm14[6],xmm13[6],xmm14[7],xmm13[7] -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} xmm9 = <0,1,4,5,u,2,3,6,7,10,11,u,8,9,12,13> -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm9, %xmm11, %xmm11 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm11 = ymm11[0,0,1,1] -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm11, %zmm2, %zmm2 -; AVX512BW-ONLY-SLOW-NEXT: movabsq $1785168781326730801, %rax # imm = 0x18C6318C6318C631 -; AVX512BW-ONLY-SLOW-NEXT: kmovq %rax, %k4 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm10, %zmm2 {%k4} -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 32(%r8), %ymm16 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm10 = [6,6,6,6,7,7,7,7,16,16,16,16,16,16,17,17] -; AVX512BW-ONLY-SLOW-NEXT: vpermi2d %zmm16, %zmm3, %zmm10 -; AVX512BW-ONLY-SLOW-NEXT: movabsq $2380225041768974402, %rax # imm = 0x2108421084210842 -; AVX512BW-ONLY-SLOW-NEXT: kmovq %rax, %k2 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm10, %zmm2 {%k2} -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 32(%rdx), %ymm23 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} ymm10 = [128,128,12,13,128,128,128,128,14,128,128,128,14,15,128,128,128,128,16,128,128,128,16,17,128,128,128,128,18,128,128,128] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm10, %ymm23, %ymm17 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 32(%rcx), %ymm24 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} ymm11 = [128,128,128,128,13,128,128,128,128,14,128,128,128,128,15,128,128,128,128,16,128,128,128,128,17,128,128,128,128,18,128,128] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm11, %ymm24, %ymm18 -; AVX512BW-ONLY-SLOW-NEXT: vporq %ymm17, %ymm18, %ymm17 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} xmm20 = <128,6,128,8,u,128,7,128,9,128,11,u,128,10,128,12> -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm20, %xmm12, %xmm12 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} xmm22 = <6,128,8,128,u,7,128,9,128,11,128,u,10,128,12,128> -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm22, %xmm6, %xmm6 -; AVX512BW-ONLY-SLOW-NEXT: vpor %xmm6, %xmm12, %xmm6 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm6 = ymm6[0,0,1,1] -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm17, %zmm6, %zmm6 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} xmm19 = <8,128,u,7,128,9,128,u,128,u,10,128,12,128,u,11> -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm19, %xmm14, %xmm12 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} xmm21 = <128,8,u,128,7,128,9,u,11,u,128,10,128,12,u,128> -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm21, %xmm13, %xmm13 -; AVX512BW-ONLY-SLOW-NEXT: vpor %xmm12, %xmm13, %xmm12 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm13 = ymm12[0,0,1,1] -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 32(%rdi), %ymm25 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} ymm12 = <3,3,3,u,4,4,4,4> -; AVX512BW-ONLY-SLOW-NEXT: vpermd %ymm25, %ymm12, %ymm17 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 32(%rsi), %ymm26 -; AVX512BW-ONLY-SLOW-NEXT: vpbroadcastq {{.*#+}} ymm14 = [0,0,13,2,15,0,1,14,0,0,13,2,15,0,1,14,0,0,13,2,15,0,1,14,0,0,13,2,15,0,1,14] -; AVX512BW-ONLY-SLOW-NEXT: movl $138547332, %eax # imm = 0x8421084 -; AVX512BW-ONLY-SLOW-NEXT: kmovd %eax, %k3 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm14, %ymm26, %ymm17 {%k3} -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm17, %zmm13, %zmm13 -; AVX512BW-ONLY-SLOW-NEXT: movabsq $-8330787646191410408, %rax # imm = 0x8C6318C6318C6318 -; AVX512BW-ONLY-SLOW-NEXT: kmovq %rax, %k2 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm13, %zmm6 {%k2} -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} ymm13 = <3,3,3,3,u,4,4,4> -; AVX512BW-ONLY-SLOW-NEXT: vpermd %ymm16, %ymm13, %ymm17 -; AVX512BW-ONLY-SLOW-NEXT: vpshufd {{.*#+}} xmm18 = mem[1,1,2,2] -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm18 = ymm18[0,1,1,1] -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm17, %zmm18, %zmm17 -; AVX512BW-ONLY-SLOW-NEXT: movabsq $4760450083537948804, %rax # imm = 0x4210842108421084 -; AVX512BW-ONLY-SLOW-NEXT: kmovq %rax, %k6 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm17, %zmm6 {%k6} -; AVX512BW-ONLY-SLOW-NEXT: vbroadcasti32x4 {{.*#+}} ymm17 = [19,128,21,128,128,20,128,22,128,24,128,128,23,128,25,128,19,128,21,128,128,20,128,22,128,24,128,128,23,128,25,128] -; AVX512BW-ONLY-SLOW-NEXT: # ymm17 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm17, %ymm26, %ymm18 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm27 = ymm18[2,2,3,3] -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm18 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,21,128,128,20,128,22,128,24,128,128,23,128,25,128,128] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm18, %ymm25, %ymm28 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm28 = ymm28[2,2,3,3] -; AVX512BW-ONLY-SLOW-NEXT: vporq %ymm27, %ymm28, %ymm27 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm15, %ymm26, %ymm15 -; AVX512BW-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm25 = ymm25[0,1,2,3,6,5,6,7,8,9,10,11,14,13,14,15] -; AVX512BW-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm25 = ymm25[2,2,3,3,6,6,7,7] -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %ymm25, %ymm15 {%k5} -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm15 = ymm15[2,2,3,3] -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm15, %zmm27, %zmm15 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm25 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,18,19,128,21,128,21,20,128,22,128,24,128,22,23,128,25] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm25, %ymm23, %ymm26 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm26 = ymm26[2,2,3,3] -; AVX512BW-ONLY-SLOW-NEXT: vbroadcasti32x4 {{.*#+}} ymm27 = [128,128,19,128,21,128,128,20,128,22,128,24,128,128,23,128,128,128,19,128,21,128,128,20,128,22,128,24,128,128,23,128] -; AVX512BW-ONLY-SLOW-NEXT: # ymm27 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm27, %ymm24, %ymm28 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm28 = ymm28[2,2,3,3] -; AVX512BW-ONLY-SLOW-NEXT: vporq %ymm26, %ymm28, %ymm26 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm8, %ymm24, %ymm8 -; AVX512BW-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm23 = ymm23[0,1,2,3,5,6,7,6,8,9,10,11,13,14,15,14] -; AVX512BW-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm23 = ymm23[2,2,3,3,6,6,7,7] -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %ymm23, %ymm8 {%k1} -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm8 = ymm8[2,2,3,3] -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm8, %zmm26, %zmm8 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm15, %zmm8 {%k4} -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm15 = [4,6,5,5,5,5,4,6,6,6,6,6,7,7,7,7] -; AVX512BW-ONLY-SLOW-NEXT: vpermd %zmm16, %zmm15, %zmm15 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 (%rdx), %xmm16 -; AVX512BW-ONLY-SLOW-NEXT: movabsq $-8925843906633654008, %rax # imm = 0x8421084210842108 -; AVX512BW-ONLY-SLOW-NEXT: kmovq %rax, %k1 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm15, %zmm8 {%k1} -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa (%rcx), %xmm15 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm20, %xmm15, %xmm20 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm22, %xmm16, %xmm22 -; AVX512BW-ONLY-SLOW-NEXT: vporq %xmm20, %xmm22, %xmm20 -; AVX512BW-ONLY-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm15 = xmm15[0],xmm16[0],xmm15[1],xmm16[1],xmm15[2],xmm16[2],xmm15[3],xmm16[3],xmm15[4],xmm16[4],xmm15[5],xmm16[5],xmm15[6],xmm16[6],xmm15[7],xmm16[7] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm7, %xmm15, %xmm7 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa (%rsi), %xmm15 -; AVX512BW-ONLY-SLOW-NEXT: vinserti32x4 $2, %xmm20, %zmm7, %zmm7 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 (%rdi), %xmm16 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm19, %xmm16, %xmm19 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm21, %xmm15, %xmm20 -; AVX512BW-ONLY-SLOW-NEXT: vporq %xmm19, %xmm20, %xmm19 -; AVX512BW-ONLY-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm15 = xmm16[0],xmm15[0],xmm16[1],xmm15[1],xmm16[2],xmm15[2],xmm16[3],xmm15[3],xmm16[4],xmm15[4],xmm16[5],xmm15[5],xmm16[6],xmm15[6],xmm16[7],xmm15[7] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm9, %xmm15, %xmm9 -; AVX512BW-ONLY-SLOW-NEXT: vinserti32x4 $2, %xmm19, %zmm9, %zmm9 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} zmm7 = zmm7[0,0,1,1,4,4,5,5] -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} zmm9 = zmm9[0,0,1,1,4,4,5,5] -; AVX512BW-ONLY-SLOW-NEXT: movabsq $-4165393823095705204, %rax # imm = 0xC6318C6318C6318C -; AVX512BW-ONLY-SLOW-NEXT: kmovq %rax, %k1 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm7, %zmm9 {%k1} -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm7 = [0,0,0,0,0,0,1,1,1,1,2,2,2,2,2,2] -; AVX512BW-ONLY-SLOW-NEXT: vpermd %zmm3, %zmm7, %zmm3 -; AVX512BW-ONLY-SLOW-NEXT: movabsq $595056260442243600, %rax # imm = 0x842108421084210 -; AVX512BW-ONLY-SLOW-NEXT: kmovq %rax, %k1 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm3, %zmm9 {%k1} -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm25, %ymm1, %ymm3 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm3 = ymm3[2,2,3,3] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm27, %ymm0, %ymm7 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm7[2,2,3,3] -; AVX512BW-ONLY-SLOW-NEXT: vpor %ymm3, %ymm7, %ymm3 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm10, %ymm1, %ymm1 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm11, %ymm0, %ymm0 -; AVX512BW-ONLY-SLOW-NEXT: vpor %ymm1, %ymm0, %ymm0 -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm0 -; AVX512BW-ONLY-SLOW-NEXT: vpermd %ymm5, %ymm12, %ymm1 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm14, %ymm4, %ymm1 {%k3} -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm17, %ymm4, %ymm3 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm18, %ymm5, %ymm4 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm3 = ymm3[2,2,3,3] -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm4 = ymm4[2,2,3,3] -; AVX512BW-ONLY-SLOW-NEXT: vpor %ymm3, %ymm4, %ymm3 -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm3, %zmm1, %zmm1 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm0, %zmm1 {%k2} -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa (%r8), %ymm0 -; AVX512BW-ONLY-SLOW-NEXT: vpermd %ymm0, %ymm13, %ymm3 -; AVX512BW-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,1,1,4,6,5,5] -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,3,3,2] -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm0, %zmm3, %zmm0 -; AVX512BW-ONLY-SLOW-NEXT: movabsq $1190112520884487201, %rax # imm = 0x1084210842108421 -; AVX512BW-ONLY-SLOW-NEXT: kmovq %rax, %k1 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm0, %zmm1 {%k1} -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 %zmm1, 64(%r9) -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 %zmm9, (%r9) -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 %zmm8, 256(%r9) -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 %zmm6, 192(%r9) -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 %zmm2, 128(%r9) -; AVX512BW-ONLY-SLOW-NEXT: vzeroupper -; AVX512BW-ONLY-SLOW-NEXT: retq +; AVX512BW-SLOW-LABEL: store_i8_stride5_vf64: +; AVX512BW-SLOW: # %bb.0: +; AVX512BW-SLOW-NEXT: vmovdqa64 (%r8), %zmm3 +; AVX512BW-SLOW-NEXT: vmovdqa (%rcx), %ymm0 +; AVX512BW-SLOW-NEXT: vpbroadcastq {{.*#+}} ymm8 = [9,14,11,0,13,10,15,12,9,14,11,0,13,10,15,12,9,14,11,0,13,10,15,12,9,14,11,0,13,10,15,12] +; AVX512BW-SLOW-NEXT: vpshufb %ymm8, %ymm0, %ymm2 +; AVX512BW-SLOW-NEXT: vmovdqa (%rdx), %ymm1 +; AVX512BW-SLOW-NEXT: vpshufhw {{.*#+}} ymm4 = ymm1[0,1,2,3,5,6,7,6,8,9,10,11,13,14,15,14] +; AVX512BW-SLOW-NEXT: vpshufd {{.*#+}} ymm4 = ymm4[2,2,3,3,6,6,7,7] +; AVX512BW-SLOW-NEXT: movl $693250386, %eax # imm = 0x29522952 +; AVX512BW-SLOW-NEXT: kmovd %eax, %k1 +; AVX512BW-SLOW-NEXT: vmovdqu8 %ymm4, %ymm2 {%k1} +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm2 = ymm2[2,2,3,3] +; AVX512BW-SLOW-NEXT: vmovdqa 32(%rdx), %xmm6 +; AVX512BW-SLOW-NEXT: vmovdqa 32(%rcx), %xmm12 +; AVX512BW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm4 = xmm12[0],xmm6[0],xmm12[1],xmm6[1],xmm12[2],xmm6[2],xmm12[3],xmm6[3],xmm12[4],xmm6[4],xmm12[5],xmm6[5],xmm12[6],xmm6[6],xmm12[7],xmm6[7] +; AVX512BW-SLOW-NEXT: vmovdqa {{.*#+}} xmm7 = <2,u,1,0,5,4,u,3,u,7,6,11,10,u,9,8> +; AVX512BW-SLOW-NEXT: vpshufb %xmm7, %xmm4, %xmm4 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm4 = ymm4[0,0,1,1] +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm4, %zmm2, %zmm10 +; AVX512BW-SLOW-NEXT: vmovdqa (%rsi), %ymm4 +; AVX512BW-SLOW-NEXT: vpbroadcastq {{.*#+}} ymm15 = [11,0,13,10,15,12,0,14,11,0,13,10,15,12,0,14,11,0,13,10,15,12,0,14,11,0,13,10,15,12,0,14] +; AVX512BW-SLOW-NEXT: vpshufb %ymm15, %ymm4, %ymm2 +; AVX512BW-SLOW-NEXT: vmovdqa (%rdi), %ymm5 +; AVX512BW-SLOW-NEXT: vpshufhw {{.*#+}} ymm9 = ymm5[0,1,2,3,6,5,6,7,8,9,10,11,14,13,14,15] +; AVX512BW-SLOW-NEXT: vpshufd {{.*#+}} ymm9 = ymm9[2,2,3,3,6,6,7,7] +; AVX512BW-SLOW-NEXT: movl $1251232404, %eax # imm = 0x4A944A94 +; AVX512BW-SLOW-NEXT: kmovd %eax, %k5 +; AVX512BW-SLOW-NEXT: vmovdqu8 %ymm9, %ymm2 {%k5} +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm2 = ymm2[2,2,3,3] +; AVX512BW-SLOW-NEXT: vmovdqa 32(%rsi), %xmm13 +; AVX512BW-SLOW-NEXT: vmovdqa 32(%rdi), %xmm14 +; AVX512BW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm11 = xmm14[0],xmm13[0],xmm14[1],xmm13[1],xmm14[2],xmm13[2],xmm14[3],xmm13[3],xmm14[4],xmm13[4],xmm14[5],xmm13[5],xmm14[6],xmm13[6],xmm14[7],xmm13[7] +; AVX512BW-SLOW-NEXT: vmovdqa {{.*#+}} xmm9 = <0,1,4,5,u,2,3,6,7,10,11,u,8,9,12,13> +; AVX512BW-SLOW-NEXT: vpshufb %xmm9, %xmm11, %xmm11 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm11 = ymm11[0,0,1,1] +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm11, %zmm2, %zmm2 +; AVX512BW-SLOW-NEXT: movabsq $1785168781326730801, %rax # imm = 0x18C6318C6318C631 +; AVX512BW-SLOW-NEXT: kmovq %rax, %k4 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm10, %zmm2 {%k4} +; AVX512BW-SLOW-NEXT: vmovdqa64 32(%r8), %ymm16 +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm10 = [6,6,6,6,7,7,7,7,16,16,16,16,16,16,17,17] +; AVX512BW-SLOW-NEXT: vpermi2d %zmm16, %zmm3, %zmm10 +; AVX512BW-SLOW-NEXT: movabsq $2380225041768974402, %rax # imm = 0x2108421084210842 +; AVX512BW-SLOW-NEXT: kmovq %rax, %k2 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm10, %zmm2 {%k2} +; AVX512BW-SLOW-NEXT: vmovdqa64 32(%rdx), %ymm23 +; AVX512BW-SLOW-NEXT: vmovdqa {{.*#+}} ymm10 = [128,128,12,13,128,128,128,128,14,128,128,128,14,15,128,128,128,128,16,128,128,128,16,17,128,128,128,128,18,128,128,128] +; AVX512BW-SLOW-NEXT: vpshufb %ymm10, %ymm23, %ymm17 +; AVX512BW-SLOW-NEXT: vmovdqa64 32(%rcx), %ymm24 +; AVX512BW-SLOW-NEXT: vmovdqa {{.*#+}} ymm11 = [128,128,128,128,13,128,128,128,128,14,128,128,128,128,15,128,128,128,128,16,128,128,128,128,17,128,128,128,128,18,128,128] +; AVX512BW-SLOW-NEXT: vpshufb %ymm11, %ymm24, %ymm18 +; AVX512BW-SLOW-NEXT: vporq %ymm17, %ymm18, %ymm17 +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} xmm20 = <128,6,128,8,u,128,7,128,9,128,11,u,128,10,128,12> +; AVX512BW-SLOW-NEXT: vpshufb %xmm20, %xmm12, %xmm12 +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} xmm22 = <6,128,8,128,u,7,128,9,128,11,128,u,10,128,12,128> +; AVX512BW-SLOW-NEXT: vpshufb %xmm22, %xmm6, %xmm6 +; AVX512BW-SLOW-NEXT: vpor %xmm6, %xmm12, %xmm6 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm6 = ymm6[0,0,1,1] +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm17, %zmm6, %zmm6 +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} xmm19 = <8,128,u,7,128,9,128,u,128,u,10,128,12,128,u,11> +; AVX512BW-SLOW-NEXT: vpshufb %xmm19, %xmm14, %xmm12 +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} xmm21 = <128,8,u,128,7,128,9,u,11,u,128,10,128,12,u,128> +; AVX512BW-SLOW-NEXT: vpshufb %xmm21, %xmm13, %xmm13 +; AVX512BW-SLOW-NEXT: vpor %xmm12, %xmm13, %xmm12 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm13 = ymm12[0,0,1,1] +; AVX512BW-SLOW-NEXT: vmovdqa64 32(%rdi), %ymm25 +; AVX512BW-SLOW-NEXT: vmovdqa {{.*#+}} ymm12 = <3,3,3,u,4,4,4,4> +; AVX512BW-SLOW-NEXT: vpermd %ymm25, %ymm12, %ymm17 +; AVX512BW-SLOW-NEXT: vmovdqa64 32(%rsi), %ymm26 +; AVX512BW-SLOW-NEXT: vpbroadcastq {{.*#+}} ymm14 = [0,0,13,2,15,0,1,14,0,0,13,2,15,0,1,14,0,0,13,2,15,0,1,14,0,0,13,2,15,0,1,14] +; AVX512BW-SLOW-NEXT: movl $138547332, %eax # imm = 0x8421084 +; AVX512BW-SLOW-NEXT: kmovd %eax, %k3 +; AVX512BW-SLOW-NEXT: vpshufb %ymm14, %ymm26, %ymm17 {%k3} +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm17, %zmm13, %zmm13 +; AVX512BW-SLOW-NEXT: movabsq $-8330787646191410408, %rax # imm = 0x8C6318C6318C6318 +; AVX512BW-SLOW-NEXT: kmovq %rax, %k2 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm13, %zmm6 {%k2} +; AVX512BW-SLOW-NEXT: vmovdqa {{.*#+}} ymm13 = <3,3,3,3,u,4,4,4> +; AVX512BW-SLOW-NEXT: vpermd %ymm16, %ymm13, %ymm17 +; AVX512BW-SLOW-NEXT: vpshufd {{.*#+}} xmm18 = mem[1,1,2,2] +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm18 = ymm18[0,1,1,1] +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm17, %zmm18, %zmm17 +; AVX512BW-SLOW-NEXT: movabsq $4760450083537948804, %rax # imm = 0x4210842108421084 +; AVX512BW-SLOW-NEXT: kmovq %rax, %k6 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm17, %zmm6 {%k6} +; AVX512BW-SLOW-NEXT: vbroadcasti32x4 {{.*#+}} ymm17 = [19,128,21,128,128,20,128,22,128,24,128,128,23,128,25,128,19,128,21,128,128,20,128,22,128,24,128,128,23,128,25,128] +; AVX512BW-SLOW-NEXT: # ymm17 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-SLOW-NEXT: vpshufb %ymm17, %ymm26, %ymm18 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm27 = ymm18[2,2,3,3] +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm18 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,21,128,128,20,128,22,128,24,128,128,23,128,25,128,128] +; AVX512BW-SLOW-NEXT: vpshufb %ymm18, %ymm25, %ymm28 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm28 = ymm28[2,2,3,3] +; AVX512BW-SLOW-NEXT: vporq %ymm27, %ymm28, %ymm27 +; AVX512BW-SLOW-NEXT: vpshufb %ymm15, %ymm26, %ymm15 +; AVX512BW-SLOW-NEXT: vpshufhw {{.*#+}} ymm25 = ymm25[0,1,2,3,6,5,6,7,8,9,10,11,14,13,14,15] +; AVX512BW-SLOW-NEXT: vpshufd {{.*#+}} ymm25 = ymm25[2,2,3,3,6,6,7,7] +; AVX512BW-SLOW-NEXT: vmovdqu8 %ymm25, %ymm15 {%k5} +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm15 = ymm15[2,2,3,3] +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm15, %zmm27, %zmm15 +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm25 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,18,19,128,21,128,21,20,128,22,128,24,128,22,23,128,25] +; AVX512BW-SLOW-NEXT: vpshufb %ymm25, %ymm23, %ymm26 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm26 = ymm26[2,2,3,3] +; AVX512BW-SLOW-NEXT: vbroadcasti32x4 {{.*#+}} ymm27 = [128,128,19,128,21,128,128,20,128,22,128,24,128,128,23,128,128,128,19,128,21,128,128,20,128,22,128,24,128,128,23,128] +; AVX512BW-SLOW-NEXT: # ymm27 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-SLOW-NEXT: vpshufb %ymm27, %ymm24, %ymm28 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm28 = ymm28[2,2,3,3] +; AVX512BW-SLOW-NEXT: vporq %ymm26, %ymm28, %ymm26 +; AVX512BW-SLOW-NEXT: vpshufb %ymm8, %ymm24, %ymm8 +; AVX512BW-SLOW-NEXT: vpshufhw {{.*#+}} ymm23 = ymm23[0,1,2,3,5,6,7,6,8,9,10,11,13,14,15,14] +; AVX512BW-SLOW-NEXT: vpshufd {{.*#+}} ymm23 = ymm23[2,2,3,3,6,6,7,7] +; AVX512BW-SLOW-NEXT: vmovdqu8 %ymm23, %ymm8 {%k1} +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm8 = ymm8[2,2,3,3] +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm8, %zmm26, %zmm8 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm15, %zmm8 {%k4} +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm15 = [4,6,5,5,5,5,4,6,6,6,6,6,7,7,7,7] +; AVX512BW-SLOW-NEXT: vpermd %zmm16, %zmm15, %zmm15 +; AVX512BW-SLOW-NEXT: vmovdqa64 (%rdx), %xmm16 +; AVX512BW-SLOW-NEXT: movabsq $-8925843906633654008, %rax # imm = 0x8421084210842108 +; AVX512BW-SLOW-NEXT: kmovq %rax, %k1 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm15, %zmm8 {%k1} +; AVX512BW-SLOW-NEXT: vmovdqa (%rcx), %xmm15 +; AVX512BW-SLOW-NEXT: vpshufb %xmm20, %xmm15, %xmm20 +; AVX512BW-SLOW-NEXT: vpshufb %xmm22, %xmm16, %xmm22 +; AVX512BW-SLOW-NEXT: vporq %xmm20, %xmm22, %xmm20 +; AVX512BW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm15 = xmm15[0],xmm16[0],xmm15[1],xmm16[1],xmm15[2],xmm16[2],xmm15[3],xmm16[3],xmm15[4],xmm16[4],xmm15[5],xmm16[5],xmm15[6],xmm16[6],xmm15[7],xmm16[7] +; AVX512BW-SLOW-NEXT: vpshufb %xmm7, %xmm15, %xmm7 +; AVX512BW-SLOW-NEXT: vmovdqa (%rsi), %xmm15 +; AVX512BW-SLOW-NEXT: vinserti32x4 $2, %xmm20, %zmm7, %zmm7 +; AVX512BW-SLOW-NEXT: vmovdqa64 (%rdi), %xmm16 +; AVX512BW-SLOW-NEXT: vpshufb %xmm19, %xmm16, %xmm19 +; AVX512BW-SLOW-NEXT: vpshufb %xmm21, %xmm15, %xmm20 +; AVX512BW-SLOW-NEXT: vporq %xmm19, %xmm20, %xmm19 +; AVX512BW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm15 = xmm16[0],xmm15[0],xmm16[1],xmm15[1],xmm16[2],xmm15[2],xmm16[3],xmm15[3],xmm16[4],xmm15[4],xmm16[5],xmm15[5],xmm16[6],xmm15[6],xmm16[7],xmm15[7] +; AVX512BW-SLOW-NEXT: vpshufb %xmm9, %xmm15, %xmm9 +; AVX512BW-SLOW-NEXT: vinserti32x4 $2, %xmm19, %zmm9, %zmm9 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} zmm7 = zmm7[0,0,1,1,4,4,5,5] +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} zmm9 = zmm9[0,0,1,1,4,4,5,5] +; AVX512BW-SLOW-NEXT: movabsq $-4165393823095705204, %rax # imm = 0xC6318C6318C6318C +; AVX512BW-SLOW-NEXT: kmovq %rax, %k1 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm7, %zmm9 {%k1} +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm7 = [0,0,0,0,0,0,1,1,1,1,2,2,2,2,2,2] +; AVX512BW-SLOW-NEXT: vpermd %zmm3, %zmm7, %zmm3 +; AVX512BW-SLOW-NEXT: movabsq $595056260442243600, %rax # imm = 0x842108421084210 +; AVX512BW-SLOW-NEXT: kmovq %rax, %k1 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm3, %zmm9 {%k1} +; AVX512BW-SLOW-NEXT: vpshufb %ymm25, %ymm1, %ymm3 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm3 = ymm3[2,2,3,3] +; AVX512BW-SLOW-NEXT: vpshufb %ymm27, %ymm0, %ymm7 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm7[2,2,3,3] +; AVX512BW-SLOW-NEXT: vpor %ymm3, %ymm7, %ymm3 +; AVX512BW-SLOW-NEXT: vpshufb %ymm10, %ymm1, %ymm1 +; AVX512BW-SLOW-NEXT: vpshufb %ymm11, %ymm0, %ymm0 +; AVX512BW-SLOW-NEXT: vpor %ymm1, %ymm0, %ymm0 +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm0 +; AVX512BW-SLOW-NEXT: vpermd %ymm5, %ymm12, %ymm1 +; AVX512BW-SLOW-NEXT: vpshufb %ymm14, %ymm4, %ymm1 {%k3} +; AVX512BW-SLOW-NEXT: vpshufb %ymm17, %ymm4, %ymm3 +; AVX512BW-SLOW-NEXT: vpshufb %ymm18, %ymm5, %ymm4 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm3 = ymm3[2,2,3,3] +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm4 = ymm4[2,2,3,3] +; AVX512BW-SLOW-NEXT: vpor %ymm3, %ymm4, %ymm3 +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm3, %zmm1, %zmm1 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm0, %zmm1 {%k2} +; AVX512BW-SLOW-NEXT: vmovdqa (%r8), %ymm0 +; AVX512BW-SLOW-NEXT: vpermd %ymm0, %ymm13, %ymm3 +; AVX512BW-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,1,1,4,6,5,5] +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,3,3,2] +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm0, %zmm3, %zmm0 +; AVX512BW-SLOW-NEXT: movabsq $1190112520884487201, %rax # imm = 0x1084210842108421 +; AVX512BW-SLOW-NEXT: kmovq %rax, %k1 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm0, %zmm1 {%k1} +; AVX512BW-SLOW-NEXT: vmovdqa64 %zmm1, 64(%r9) +; AVX512BW-SLOW-NEXT: vmovdqa64 %zmm9, (%r9) +; AVX512BW-SLOW-NEXT: vmovdqa64 %zmm8, 256(%r9) +; AVX512BW-SLOW-NEXT: vmovdqa64 %zmm6, 192(%r9) +; AVX512BW-SLOW-NEXT: vmovdqa64 %zmm2, 128(%r9) +; AVX512BW-SLOW-NEXT: vzeroupper +; AVX512BW-SLOW-NEXT: retq ; ; AVX512BW-FAST-LABEL: store_i8_stride5_vf64: ; AVX512BW-FAST: # %bb.0: @@ -4579,186 +4579,6 @@ define void @store_i8_stride5_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec ; AVX512BW-FAST-NEXT: vmovdqa64 %zmm0, 192(%r9) ; AVX512BW-FAST-NEXT: vzeroupper ; AVX512BW-FAST-NEXT: retq -; -; AVX512DQBW-SLOW-LABEL: store_i8_stride5_vf64: -; AVX512DQBW-SLOW: # %bb.0: -; AVX512DQBW-SLOW-NEXT: vmovdqa64 (%r8), %zmm3 -; AVX512DQBW-SLOW-NEXT: vmovdqa (%rcx), %ymm0 -; AVX512DQBW-SLOW-NEXT: vpbroadcastq {{.*#+}} ymm8 = [9,14,11,0,13,10,15,12,9,14,11,0,13,10,15,12,9,14,11,0,13,10,15,12,9,14,11,0,13,10,15,12] -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm8, %ymm0, %ymm2 -; AVX512DQBW-SLOW-NEXT: vmovdqa (%rdx), %ymm1 -; AVX512DQBW-SLOW-NEXT: vpshufhw {{.*#+}} ymm4 = ymm1[0,1,2,3,5,6,7,6,8,9,10,11,13,14,15,14] -; AVX512DQBW-SLOW-NEXT: vpshufd {{.*#+}} ymm4 = ymm4[2,2,3,3,6,6,7,7] -; AVX512DQBW-SLOW-NEXT: movl $693250386, %eax # imm = 0x29522952 -; AVX512DQBW-SLOW-NEXT: kmovd %eax, %k1 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %ymm4, %ymm2 {%k1} -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm2 = ymm2[2,2,3,3] -; AVX512DQBW-SLOW-NEXT: vmovdqa 32(%rdx), %xmm6 -; AVX512DQBW-SLOW-NEXT: vmovdqa 32(%rcx), %xmm12 -; AVX512DQBW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm4 = xmm12[0],xmm6[0],xmm12[1],xmm6[1],xmm12[2],xmm6[2],xmm12[3],xmm6[3],xmm12[4],xmm6[4],xmm12[5],xmm6[5],xmm12[6],xmm6[6],xmm12[7],xmm6[7] -; AVX512DQBW-SLOW-NEXT: vmovdqa {{.*#+}} xmm7 = <2,u,1,0,5,4,u,3,u,7,6,11,10,u,9,8> -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm7, %xmm4, %xmm4 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm4 = ymm4[0,0,1,1] -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm4, %zmm2, %zmm10 -; AVX512DQBW-SLOW-NEXT: vmovdqa (%rsi), %ymm4 -; AVX512DQBW-SLOW-NEXT: vpbroadcastq {{.*#+}} ymm15 = [11,0,13,10,15,12,0,14,11,0,13,10,15,12,0,14,11,0,13,10,15,12,0,14,11,0,13,10,15,12,0,14] -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm15, %ymm4, %ymm2 -; AVX512DQBW-SLOW-NEXT: vmovdqa (%rdi), %ymm5 -; AVX512DQBW-SLOW-NEXT: vpshufhw {{.*#+}} ymm9 = ymm5[0,1,2,3,6,5,6,7,8,9,10,11,14,13,14,15] -; AVX512DQBW-SLOW-NEXT: vpshufd {{.*#+}} ymm9 = ymm9[2,2,3,3,6,6,7,7] -; AVX512DQBW-SLOW-NEXT: movl $1251232404, %eax # imm = 0x4A944A94 -; AVX512DQBW-SLOW-NEXT: kmovd %eax, %k5 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %ymm9, %ymm2 {%k5} -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm2 = ymm2[2,2,3,3] -; AVX512DQBW-SLOW-NEXT: vmovdqa 32(%rsi), %xmm13 -; AVX512DQBW-SLOW-NEXT: vmovdqa 32(%rdi), %xmm14 -; AVX512DQBW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm11 = xmm14[0],xmm13[0],xmm14[1],xmm13[1],xmm14[2],xmm13[2],xmm14[3],xmm13[3],xmm14[4],xmm13[4],xmm14[5],xmm13[5],xmm14[6],xmm13[6],xmm14[7],xmm13[7] -; AVX512DQBW-SLOW-NEXT: vmovdqa {{.*#+}} xmm9 = <0,1,4,5,u,2,3,6,7,10,11,u,8,9,12,13> -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm9, %xmm11, %xmm11 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm11 = ymm11[0,0,1,1] -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm11, %zmm2, %zmm2 -; AVX512DQBW-SLOW-NEXT: movabsq $1785168781326730801, %rax # imm = 0x18C6318C6318C631 -; AVX512DQBW-SLOW-NEXT: kmovq %rax, %k4 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm10, %zmm2 {%k4} -; AVX512DQBW-SLOW-NEXT: vmovdqa64 32(%r8), %ymm16 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm10 = [6,6,6,6,7,7,7,7,16,16,16,16,16,16,17,17] -; AVX512DQBW-SLOW-NEXT: vpermi2d %zmm16, %zmm3, %zmm10 -; AVX512DQBW-SLOW-NEXT: movabsq $2380225041768974402, %rax # imm = 0x2108421084210842 -; AVX512DQBW-SLOW-NEXT: kmovq %rax, %k2 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm10, %zmm2 {%k2} -; AVX512DQBW-SLOW-NEXT: vmovdqa64 32(%rdx), %ymm23 -; AVX512DQBW-SLOW-NEXT: vmovdqa {{.*#+}} ymm10 = [128,128,12,13,128,128,128,128,14,128,128,128,14,15,128,128,128,128,16,128,128,128,16,17,128,128,128,128,18,128,128,128] -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm10, %ymm23, %ymm17 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 32(%rcx), %ymm24 -; AVX512DQBW-SLOW-NEXT: vmovdqa {{.*#+}} ymm11 = [128,128,128,128,13,128,128,128,128,14,128,128,128,128,15,128,128,128,128,16,128,128,128,128,17,128,128,128,128,18,128,128] -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm11, %ymm24, %ymm18 -; AVX512DQBW-SLOW-NEXT: vporq %ymm17, %ymm18, %ymm17 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} xmm20 = <128,6,128,8,u,128,7,128,9,128,11,u,128,10,128,12> -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm20, %xmm12, %xmm12 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} xmm22 = <6,128,8,128,u,7,128,9,128,11,128,u,10,128,12,128> -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm22, %xmm6, %xmm6 -; AVX512DQBW-SLOW-NEXT: vpor %xmm6, %xmm12, %xmm6 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm6 = ymm6[0,0,1,1] -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm17, %zmm6, %zmm6 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} xmm19 = <8,128,u,7,128,9,128,u,128,u,10,128,12,128,u,11> -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm19, %xmm14, %xmm12 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} xmm21 = <128,8,u,128,7,128,9,u,11,u,128,10,128,12,u,128> -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm21, %xmm13, %xmm13 -; AVX512DQBW-SLOW-NEXT: vpor %xmm12, %xmm13, %xmm12 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm13 = ymm12[0,0,1,1] -; AVX512DQBW-SLOW-NEXT: vmovdqa64 32(%rdi), %ymm25 -; AVX512DQBW-SLOW-NEXT: vmovdqa {{.*#+}} ymm12 = <3,3,3,u,4,4,4,4> -; AVX512DQBW-SLOW-NEXT: vpermd %ymm25, %ymm12, %ymm17 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 32(%rsi), %ymm26 -; AVX512DQBW-SLOW-NEXT: vpbroadcastq {{.*#+}} ymm14 = [0,0,13,2,15,0,1,14,0,0,13,2,15,0,1,14,0,0,13,2,15,0,1,14,0,0,13,2,15,0,1,14] -; AVX512DQBW-SLOW-NEXT: movl $138547332, %eax # imm = 0x8421084 -; AVX512DQBW-SLOW-NEXT: kmovd %eax, %k3 -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm14, %ymm26, %ymm17 {%k3} -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm17, %zmm13, %zmm13 -; AVX512DQBW-SLOW-NEXT: movabsq $-8330787646191410408, %rax # imm = 0x8C6318C6318C6318 -; AVX512DQBW-SLOW-NEXT: kmovq %rax, %k2 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm13, %zmm6 {%k2} -; AVX512DQBW-SLOW-NEXT: vmovdqa {{.*#+}} ymm13 = <3,3,3,3,u,4,4,4> -; AVX512DQBW-SLOW-NEXT: vpermd %ymm16, %ymm13, %ymm17 -; AVX512DQBW-SLOW-NEXT: vpshufd {{.*#+}} xmm18 = mem[1,1,2,2] -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm18 = ymm18[0,1,1,1] -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm17, %zmm18, %zmm17 -; AVX512DQBW-SLOW-NEXT: movabsq $4760450083537948804, %rax # imm = 0x4210842108421084 -; AVX512DQBW-SLOW-NEXT: kmovq %rax, %k6 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm17, %zmm6 {%k6} -; AVX512DQBW-SLOW-NEXT: vbroadcasti64x2 {{.*#+}} ymm17 = [19,128,21,128,128,20,128,22,128,24,128,128,23,128,25,128,19,128,21,128,128,20,128,22,128,24,128,128,23,128,25,128] -; AVX512DQBW-SLOW-NEXT: # ymm17 = mem[0,1,0,1] -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm17, %ymm26, %ymm18 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm27 = ymm18[2,2,3,3] -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm18 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,21,128,128,20,128,22,128,24,128,128,23,128,25,128,128] -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm18, %ymm25, %ymm28 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm28 = ymm28[2,2,3,3] -; AVX512DQBW-SLOW-NEXT: vporq %ymm27, %ymm28, %ymm27 -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm15, %ymm26, %ymm15 -; AVX512DQBW-SLOW-NEXT: vpshufhw {{.*#+}} ymm25 = ymm25[0,1,2,3,6,5,6,7,8,9,10,11,14,13,14,15] -; AVX512DQBW-SLOW-NEXT: vpshufd {{.*#+}} ymm25 = ymm25[2,2,3,3,6,6,7,7] -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %ymm25, %ymm15 {%k5} -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm15 = ymm15[2,2,3,3] -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm15, %zmm27, %zmm15 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm25 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,18,19,128,21,128,21,20,128,22,128,24,128,22,23,128,25] -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm25, %ymm23, %ymm26 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm26 = ymm26[2,2,3,3] -; AVX512DQBW-SLOW-NEXT: vbroadcasti64x2 {{.*#+}} ymm27 = [128,128,19,128,21,128,128,20,128,22,128,24,128,128,23,128,128,128,19,128,21,128,128,20,128,22,128,24,128,128,23,128] -; AVX512DQBW-SLOW-NEXT: # ymm27 = mem[0,1,0,1] -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm27, %ymm24, %ymm28 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm28 = ymm28[2,2,3,3] -; AVX512DQBW-SLOW-NEXT: vporq %ymm26, %ymm28, %ymm26 -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm8, %ymm24, %ymm8 -; AVX512DQBW-SLOW-NEXT: vpshufhw {{.*#+}} ymm23 = ymm23[0,1,2,3,5,6,7,6,8,9,10,11,13,14,15,14] -; AVX512DQBW-SLOW-NEXT: vpshufd {{.*#+}} ymm23 = ymm23[2,2,3,3,6,6,7,7] -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %ymm23, %ymm8 {%k1} -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm8 = ymm8[2,2,3,3] -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm8, %zmm26, %zmm8 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm15, %zmm8 {%k4} -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm15 = [4,6,5,5,5,5,4,6,6,6,6,6,7,7,7,7] -; AVX512DQBW-SLOW-NEXT: vpermd %zmm16, %zmm15, %zmm15 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 (%rdx), %xmm16 -; AVX512DQBW-SLOW-NEXT: movabsq $-8925843906633654008, %rax # imm = 0x8421084210842108 -; AVX512DQBW-SLOW-NEXT: kmovq %rax, %k1 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm15, %zmm8 {%k1} -; AVX512DQBW-SLOW-NEXT: vmovdqa (%rcx), %xmm15 -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm20, %xmm15, %xmm20 -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm22, %xmm16, %xmm22 -; AVX512DQBW-SLOW-NEXT: vporq %xmm20, %xmm22, %xmm20 -; AVX512DQBW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm15 = xmm15[0],xmm16[0],xmm15[1],xmm16[1],xmm15[2],xmm16[2],xmm15[3],xmm16[3],xmm15[4],xmm16[4],xmm15[5],xmm16[5],xmm15[6],xmm16[6],xmm15[7],xmm16[7] -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm7, %xmm15, %xmm7 -; AVX512DQBW-SLOW-NEXT: vmovdqa (%rsi), %xmm15 -; AVX512DQBW-SLOW-NEXT: vinserti32x4 $2, %xmm20, %zmm7, %zmm7 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 (%rdi), %xmm16 -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm19, %xmm16, %xmm19 -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm21, %xmm15, %xmm20 -; AVX512DQBW-SLOW-NEXT: vporq %xmm19, %xmm20, %xmm19 -; AVX512DQBW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm15 = xmm16[0],xmm15[0],xmm16[1],xmm15[1],xmm16[2],xmm15[2],xmm16[3],xmm15[3],xmm16[4],xmm15[4],xmm16[5],xmm15[5],xmm16[6],xmm15[6],xmm16[7],xmm15[7] -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm9, %xmm15, %xmm9 -; AVX512DQBW-SLOW-NEXT: vinserti32x4 $2, %xmm19, %zmm9, %zmm9 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} zmm7 = zmm7[0,0,1,1,4,4,5,5] -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} zmm9 = zmm9[0,0,1,1,4,4,5,5] -; AVX512DQBW-SLOW-NEXT: movabsq $-4165393823095705204, %rax # imm = 0xC6318C6318C6318C -; AVX512DQBW-SLOW-NEXT: kmovq %rax, %k1 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm7, %zmm9 {%k1} -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm7 = [0,0,0,0,0,0,1,1,1,1,2,2,2,2,2,2] -; AVX512DQBW-SLOW-NEXT: vpermd %zmm3, %zmm7, %zmm3 -; AVX512DQBW-SLOW-NEXT: movabsq $595056260442243600, %rax # imm = 0x842108421084210 -; AVX512DQBW-SLOW-NEXT: kmovq %rax, %k1 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm3, %zmm9 {%k1} -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm25, %ymm1, %ymm3 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm3 = ymm3[2,2,3,3] -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm27, %ymm0, %ymm7 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm7[2,2,3,3] -; AVX512DQBW-SLOW-NEXT: vpor %ymm3, %ymm7, %ymm3 -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm10, %ymm1, %ymm1 -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm11, %ymm0, %ymm0 -; AVX512DQBW-SLOW-NEXT: vpor %ymm1, %ymm0, %ymm0 -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm0 -; AVX512DQBW-SLOW-NEXT: vpermd %ymm5, %ymm12, %ymm1 -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm14, %ymm4, %ymm1 {%k3} -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm17, %ymm4, %ymm3 -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm18, %ymm5, %ymm4 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm3 = ymm3[2,2,3,3] -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm4 = ymm4[2,2,3,3] -; AVX512DQBW-SLOW-NEXT: vpor %ymm3, %ymm4, %ymm3 -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm3, %zmm1, %zmm1 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm0, %zmm1 {%k2} -; AVX512DQBW-SLOW-NEXT: vmovdqa (%r8), %ymm0 -; AVX512DQBW-SLOW-NEXT: vpermd %ymm0, %ymm13, %ymm3 -; AVX512DQBW-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,1,1,4,6,5,5] -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,3,3,2] -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm0, %zmm3, %zmm0 -; AVX512DQBW-SLOW-NEXT: movabsq $1190112520884487201, %rax # imm = 0x1084210842108421 -; AVX512DQBW-SLOW-NEXT: kmovq %rax, %k1 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm0, %zmm1 {%k1} -; AVX512DQBW-SLOW-NEXT: vmovdqa64 %zmm1, 64(%r9) -; AVX512DQBW-SLOW-NEXT: vmovdqa64 %zmm9, (%r9) -; AVX512DQBW-SLOW-NEXT: vmovdqa64 %zmm8, 256(%r9) -; AVX512DQBW-SLOW-NEXT: vmovdqa64 %zmm6, 192(%r9) -; AVX512DQBW-SLOW-NEXT: vmovdqa64 %zmm2, 128(%r9) -; AVX512DQBW-SLOW-NEXT: vzeroupper -; AVX512DQBW-SLOW-NEXT: retq %in.vec0 = load <64 x i8>, ptr %in.vecptr0, align 64 %in.vec1 = load <64 x i8>, ptr %in.vecptr1, align 64 %in.vec2 = load <64 x i8>, ptr %in.vecptr2, align 64 @@ -4781,11 +4601,13 @@ define void @store_i8_stride5_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec ; AVX512-SLOW: {{.*}} ; AVX512BW-ONLY: {{.*}} ; AVX512BW-ONLY-FAST: {{.*}} +; AVX512BW-ONLY-SLOW: {{.*}} ; AVX512DQ-FAST: {{.*}} ; AVX512DQ-ONLY: {{.*}} ; AVX512DQ-SLOW: {{.*}} ; AVX512DQBW-FAST: {{.*}} ; AVX512DQBW-ONLY: {{.*}} +; AVX512DQBW-SLOW: {{.*}} ; AVX512F-ONLY: {{.*}} ; AVX512F-ONLY-FAST: {{.*}} ; AVX512F-ONLY-SLOW: {{.*}} diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll index 493728470f30..3bc7b6e95822 100644 --- a/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll +++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll @@ -4671,215 +4671,215 @@ define void @store_i8_stride6_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec ; AVX512F-FAST-NEXT: vzeroupper ; AVX512F-FAST-NEXT: retq ; -; AVX512BW-ONLY-SLOW-LABEL: store_i8_stride6_vf64: -; AVX512BW-ONLY-SLOW: # %bb.0: -; AVX512BW-ONLY-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 (%r8), %zmm14 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 (%r9), %zmm12 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 (%rsi), %ymm16 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 (%rdi), %ymm17 -; AVX512BW-ONLY-SLOW-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm17[0],ymm16[0],ymm17[1],ymm16[1],ymm17[2],ymm16[2],ymm17[3],ymm16[3],ymm17[4],ymm16[4],ymm17[5],ymm16[5],ymm17[6],ymm16[6],ymm17[7],ymm16[7],ymm17[16],ymm16[16],ymm17[17],ymm16[17],ymm17[18],ymm16[18],ymm17[19],ymm16[19],ymm17[20],ymm16[20],ymm17[21],ymm16[21],ymm17[22],ymm16[22],ymm17[23],ymm16[23] -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa (%rsi), %xmm1 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa 32(%rsi), %xmm9 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa (%rdi), %xmm3 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa 32(%rdi), %xmm11 -; AVX512BW-ONLY-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm3[8],xmm1[8],xmm3[9],xmm1[9],xmm3[10],xmm1[10],xmm3[11],xmm1[11],xmm3[12],xmm1[12],xmm3[13],xmm1[13],xmm3[14],xmm1[14],xmm3[15],xmm1[15] -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm0, %zmm2, %zmm0 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm7 = [4,3,6,5,4,3,6,5,4,3,6,5,7,7,7,7,24,27,26,25,24,27,26,25,24,27,26,25,28,29,30,29] -; AVX512BW-ONLY-SLOW-NEXT: vpermw %zmm0, %zmm7, %zmm0 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa (%rcx), %xmm2 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa 32(%rcx), %xmm8 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa (%rdx), %xmm4 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa 32(%rdx), %xmm10 -; AVX512BW-ONLY-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm5 = xmm4[8],xmm2[8],xmm4[9],xmm2[9],xmm4[10],xmm2[10],xmm4[11],xmm2[11],xmm4[12],xmm2[12],xmm4[13],xmm2[13],xmm4[14],xmm2[14],xmm4[15],xmm2[15] -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm20 = [5,4,3,6,5,4,3,6,5,4,3,6,7,7,7,7] -; AVX512BW-ONLY-SLOW-NEXT: vpermw %ymm5, %ymm20, %ymm5 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 (%rcx), %ymm18 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 (%rdx), %ymm19 -; AVX512BW-ONLY-SLOW-NEXT: vpunpcklbw {{.*#+}} ymm6 = ymm19[0],ymm18[0],ymm19[1],ymm18[1],ymm19[2],ymm18[2],ymm19[3],ymm18[3],ymm19[4],ymm18[4],ymm19[5],ymm18[5],ymm19[6],ymm18[6],ymm19[7],ymm18[7],ymm19[16],ymm18[16],ymm19[17],ymm18[17],ymm19[18],ymm18[18],ymm19[19],ymm18[19],ymm19[20],ymm18[20],ymm19[21],ymm18[21],ymm19[22],ymm18[22],ymm19[23],ymm18[23] -; AVX512BW-ONLY-SLOW-NEXT: vprold $16, %ymm6, %ymm6 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm6 = ymm6[2,2,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm6, %zmm5, %zmm5 -; AVX512BW-ONLY-SLOW-NEXT: movl $613566756, %r10d # imm = 0x24924924 -; AVX512BW-ONLY-SLOW-NEXT: kmovd %r10d, %k1 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu16 %zmm5, %zmm0 {%k1} -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa (%r8), %xmm5 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa 32(%r8), %xmm13 -; AVX512BW-ONLY-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm6 = xmm5[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm23 = [2,5,4,3,2,5,4,3,2,5,4,3,6,5,6,7] -; AVX512BW-ONLY-SLOW-NEXT: vpermw %ymm6, %ymm23, %ymm6 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 (%r8), %ymm21 -; AVX512BW-ONLY-SLOW-NEXT: vbroadcasti32x4 {{.*#+}} ymm24 = [2,0,1,0,0,0,3,0,0,0,0,0,4,0,0,0,2,0,1,0,0,0,3,0,0,0,0,0,4,0,0,0] -; AVX512BW-ONLY-SLOW-NEXT: # ymm24 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm24, %ymm21, %ymm15 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm15 = ymm15[2,2,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm15, %zmm6, %zmm6 -; AVX512BW-ONLY-SLOW-NEXT: movl $1227133513, %r10d # imm = 0x49249249 -; AVX512BW-ONLY-SLOW-NEXT: kmovd %r10d, %k2 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu16 %zmm6, %zmm0 {%k2} -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa (%r9), %xmm6 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa 32(%r9), %xmm15 -; AVX512BW-ONLY-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm22 = xmm6[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] -; AVX512BW-ONLY-SLOW-NEXT: vpermw %ymm22, %ymm23, %ymm25 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 (%r9), %ymm22 -; AVX512BW-ONLY-SLOW-NEXT: vbroadcasti32x4 {{.*#+}} ymm26 = [0,2,0,1,0,0,0,3,0,0,0,0,0,4,0,0,0,2,0,1,0,0,0,3,0,0,0,0,0,4,0,0] -; AVX512BW-ONLY-SLOW-NEXT: # ymm26 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm26, %ymm22, %ymm27 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm27 = ymm27[2,2,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm27, %zmm25, %zmm25 -; AVX512BW-ONLY-SLOW-NEXT: movabsq $2342443691899625602, %r10 # imm = 0x2082082082082082 -; AVX512BW-ONLY-SLOW-NEXT: kmovq %r10, %k3 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm25, %zmm0 {%k3} -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 32(%rsi), %ymm25 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 32(%rdi), %ymm27 -; AVX512BW-ONLY-SLOW-NEXT: vpunpcklbw {{.*#+}} ymm28 = ymm27[0],ymm25[0],ymm27[1],ymm25[1],ymm27[2],ymm25[2],ymm27[3],ymm25[3],ymm27[4],ymm25[4],ymm27[5],ymm25[5],ymm27[6],ymm25[6],ymm27[7],ymm25[7],ymm27[16],ymm25[16],ymm27[17],ymm25[17],ymm27[18],ymm25[18],ymm27[19],ymm25[19],ymm27[20],ymm25[20],ymm27[21],ymm25[21],ymm27[22],ymm25[22],ymm27[23],ymm25[23] -; AVX512BW-ONLY-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm29 = xmm11[8],xmm9[8],xmm11[9],xmm9[9],xmm11[10],xmm9[10],xmm11[11],xmm9[11],xmm11[12],xmm9[12],xmm11[13],xmm9[13],xmm11[14],xmm9[14],xmm11[15],xmm9[15] -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm28, %zmm29, %zmm28 -; AVX512BW-ONLY-SLOW-NEXT: vpermw %zmm28, %zmm7, %zmm7 -; AVX512BW-ONLY-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm28 = xmm10[8],xmm8[8],xmm10[9],xmm8[9],xmm10[10],xmm8[10],xmm10[11],xmm8[11],xmm10[12],xmm8[12],xmm10[13],xmm8[13],xmm10[14],xmm8[14],xmm10[15],xmm8[15] -; AVX512BW-ONLY-SLOW-NEXT: vpermw %ymm28, %ymm20, %ymm20 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 32(%rcx), %ymm28 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 32(%rdx), %ymm29 -; AVX512BW-ONLY-SLOW-NEXT: vpunpcklbw {{.*#+}} ymm30 = ymm29[0],ymm28[0],ymm29[1],ymm28[1],ymm29[2],ymm28[2],ymm29[3],ymm28[3],ymm29[4],ymm28[4],ymm29[5],ymm28[5],ymm29[6],ymm28[6],ymm29[7],ymm28[7],ymm29[16],ymm28[16],ymm29[17],ymm28[17],ymm29[18],ymm28[18],ymm29[19],ymm28[19],ymm29[20],ymm28[20],ymm29[21],ymm28[21],ymm29[22],ymm28[22],ymm29[23],ymm28[23] -; AVX512BW-ONLY-SLOW-NEXT: vprold $16, %ymm30, %ymm30 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm30 = ymm30[2,2,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm30, %zmm20, %zmm20 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu16 %zmm20, %zmm7 {%k1} -; AVX512BW-ONLY-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm20 = xmm13[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] -; AVX512BW-ONLY-SLOW-NEXT: vpermw %ymm20, %ymm23, %ymm20 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 32(%r8), %ymm30 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm24, %ymm30, %ymm24 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm24 = ymm24[2,2,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm24, %zmm20, %zmm20 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu16 %zmm20, %zmm7 {%k2} -; AVX512BW-ONLY-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm20 = xmm15[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] -; AVX512BW-ONLY-SLOW-NEXT: vpermw %ymm20, %ymm23, %ymm20 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 32(%r9), %ymm24 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm26, %ymm24, %ymm23 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm23 = ymm23[2,2,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm23, %zmm20, %zmm20 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm20, %zmm7 {%k3} -; AVX512BW-ONLY-SLOW-NEXT: vpbroadcastq {{.*#+}} ymm26 = [8,7,6,9,0,0,10,0,8,7,6,9,0,0,10,0,8,7,6,9,0,0,10,0,8,7,6,9,0,0,10,0] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm26, %ymm25, %ymm20 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm26, %ymm27, %ymm23 -; AVX512BW-ONLY-SLOW-NEXT: vpunpcklbw {{.*#+}} ymm20 = ymm23[0],ymm20[0],ymm23[1],ymm20[1],ymm23[2],ymm20[2],ymm23[3],ymm20[3],ymm23[4],ymm20[4],ymm23[5],ymm20[5],ymm23[6],ymm20[6],ymm23[7],ymm20[7],ymm23[16],ymm20[16],ymm23[17],ymm20[17],ymm23[18],ymm20[18],ymm23[19],ymm20[19],ymm23[20],ymm20[20],ymm23[21],ymm20[21],ymm23[22],ymm20[22],ymm23[23],ymm20[23] -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm20 = ymm20[2,2,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vpunpckhbw {{.*#+}} ymm23 = ymm27[8],ymm25[8],ymm27[9],ymm25[9],ymm27[10],ymm25[10],ymm27[11],ymm25[11],ymm27[12],ymm25[12],ymm27[13],ymm25[13],ymm27[14],ymm25[14],ymm27[15],ymm25[15],ymm27[24],ymm25[24],ymm27[25],ymm25[25],ymm27[26],ymm25[26],ymm27[27],ymm25[27],ymm27[28],ymm25[28],ymm27[29],ymm25[29],ymm27[30],ymm25[30],ymm27[31],ymm25[31] -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm25 = [12,11,14,13,12,11,14,13,12,11,14,13,15,15,15,15] -; AVX512BW-ONLY-SLOW-NEXT: vpermw %ymm23, %ymm25, %ymm23 -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm23, %zmm20, %zmm27 -; AVX512BW-ONLY-SLOW-NEXT: vpbroadcastq {{.*#+}} ymm23 = [5,8,7,6,9,0,0,10,5,8,7,6,9,0,0,10,5,8,7,6,9,0,0,10,5,8,7,6,9,0,0,10] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm23, %ymm28, %ymm20 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm23, %ymm29, %ymm31 -; AVX512BW-ONLY-SLOW-NEXT: vpunpcklbw {{.*#+}} ymm20 = ymm31[0],ymm20[0],ymm31[1],ymm20[1],ymm31[2],ymm20[2],ymm31[3],ymm20[3],ymm31[4],ymm20[4],ymm31[5],ymm20[5],ymm31[6],ymm20[6],ymm31[7],ymm20[7],ymm31[16],ymm20[16],ymm31[17],ymm20[17],ymm31[18],ymm20[18],ymm31[19],ymm20[19],ymm31[20],ymm20[20],ymm31[21],ymm20[21],ymm31[22],ymm20[22],ymm31[23],ymm20[23] -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm20 = ymm20[2,2,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vpunpckhbw {{.*#+}} ymm28 = ymm29[8],ymm28[8],ymm29[9],ymm28[9],ymm29[10],ymm28[10],ymm29[11],ymm28[11],ymm29[12],ymm28[12],ymm29[13],ymm28[13],ymm29[14],ymm28[14],ymm29[15],ymm28[15],ymm29[24],ymm28[24],ymm29[25],ymm28[25],ymm29[26],ymm28[26],ymm29[27],ymm28[27],ymm29[28],ymm28[28],ymm29[29],ymm28[29],ymm29[30],ymm28[30],ymm29[31],ymm28[31] -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm29 = [13,12,11,14,13,12,11,14,13,12,11,14,15,15,15,15] -; AVX512BW-ONLY-SLOW-NEXT: vpermw %ymm28, %ymm29, %ymm28 -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm28, %zmm20, %zmm20 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu16 %zmm27, %zmm20 {%k1} -; AVX512BW-ONLY-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm27 = zmm30[0,1,2,3],zmm14[4,5,6,7] -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm28 = -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %zmm28, %zmm27, %zmm27 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} zmm27 = zmm27[2,2,2,3,6,6,6,7] -; AVX512BW-ONLY-SLOW-NEXT: movl $-1840700270, %ecx # imm = 0x92492492 -; AVX512BW-ONLY-SLOW-NEXT: kmovd %ecx, %k2 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu16 %zmm27, %zmm20 {%k2} -; AVX512BW-ONLY-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm24 = zmm24[0,1,2,3],zmm12[4,5,6,7] -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm27 = -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %zmm27, %zmm24, %zmm24 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} zmm24 = zmm24[2,2,2,3,6,6,6,7] -; AVX512BW-ONLY-SLOW-NEXT: movabsq $-9076969306111049208, %rcx # imm = 0x8208208208208208 -; AVX512BW-ONLY-SLOW-NEXT: kmovq %rcx, %k3 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm24, %zmm20 {%k3} -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm26, %ymm16, %ymm24 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm26, %ymm17, %ymm26 -; AVX512BW-ONLY-SLOW-NEXT: vpunpcklbw {{.*#+}} ymm24 = ymm26[0],ymm24[0],ymm26[1],ymm24[1],ymm26[2],ymm24[2],ymm26[3],ymm24[3],ymm26[4],ymm24[4],ymm26[5],ymm24[5],ymm26[6],ymm24[6],ymm26[7],ymm24[7],ymm26[16],ymm24[16],ymm26[17],ymm24[17],ymm26[18],ymm24[18],ymm26[19],ymm24[19],ymm26[20],ymm24[20],ymm26[21],ymm24[21],ymm26[22],ymm24[22],ymm26[23],ymm24[23] -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm24 = ymm24[2,2,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vpunpckhbw {{.*#+}} ymm16 = ymm17[8],ymm16[8],ymm17[9],ymm16[9],ymm17[10],ymm16[10],ymm17[11],ymm16[11],ymm17[12],ymm16[12],ymm17[13],ymm16[13],ymm17[14],ymm16[14],ymm17[15],ymm16[15],ymm17[24],ymm16[24],ymm17[25],ymm16[25],ymm17[26],ymm16[26],ymm17[27],ymm16[27],ymm17[28],ymm16[28],ymm17[29],ymm16[29],ymm17[30],ymm16[30],ymm17[31],ymm16[31] -; AVX512BW-ONLY-SLOW-NEXT: vpermw %ymm16, %ymm25, %ymm16 -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm16, %zmm24, %zmm17 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm23, %ymm18, %ymm16 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm23, %ymm19, %ymm24 -; AVX512BW-ONLY-SLOW-NEXT: vpunpcklbw {{.*#+}} ymm16 = ymm24[0],ymm16[0],ymm24[1],ymm16[1],ymm24[2],ymm16[2],ymm24[3],ymm16[3],ymm24[4],ymm16[4],ymm24[5],ymm16[5],ymm24[6],ymm16[6],ymm24[7],ymm16[7],ymm24[16],ymm16[16],ymm24[17],ymm16[17],ymm24[18],ymm16[18],ymm24[19],ymm16[19],ymm24[20],ymm16[20],ymm24[21],ymm16[21],ymm24[22],ymm16[22],ymm24[23],ymm16[23] -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm16 = ymm16[2,2,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vpunpckhbw {{.*#+}} ymm18 = ymm19[8],ymm18[8],ymm19[9],ymm18[9],ymm19[10],ymm18[10],ymm19[11],ymm18[11],ymm19[12],ymm18[12],ymm19[13],ymm18[13],ymm19[14],ymm18[14],ymm19[15],ymm18[15],ymm19[24],ymm18[24],ymm19[25],ymm18[25],ymm19[26],ymm18[26],ymm19[27],ymm18[27],ymm19[28],ymm18[28],ymm19[29],ymm18[29],ymm19[30],ymm18[30],ymm19[31],ymm18[31] -; AVX512BW-ONLY-SLOW-NEXT: vpermw %ymm18, %ymm29, %ymm18 -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm18, %zmm16, %zmm16 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu16 %zmm17, %zmm16 {%k1} -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm21, %zmm14, %zmm14 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %zmm28, %zmm14, %zmm14 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} zmm14 = zmm14[2,2,2,3,6,6,6,7] -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu16 %zmm14, %zmm16 {%k2} -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm22, %zmm12, %zmm12 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %zmm27, %zmm12, %zmm12 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} zmm12 = zmm12[2,2,2,3,6,6,6,7] -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm12, %zmm16 {%k3} -; AVX512BW-ONLY-SLOW-NEXT: vpbroadcastq {{.*#+}} xmm12 = [8,7,6,9,0,0,10,0,8,7,6,9,0,0,10,0] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm12, %xmm9, %xmm14 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm12, %xmm11, %xmm17 -; AVX512BW-ONLY-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm14 = xmm17[8],xmm14[8],xmm17[9],xmm14[9],xmm17[10],xmm14[10],xmm17[11],xmm14[11],xmm17[12],xmm14[12],xmm17[13],xmm14[13],xmm17[14],xmm14[14],xmm17[15],xmm14[15] -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm14 = ymm14[0,0,0,1] -; AVX512BW-ONLY-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm9 = xmm11[0],xmm9[0],xmm11[1],xmm9[1],xmm11[2],xmm9[2],xmm11[3],xmm9[3],xmm11[4],xmm9[4],xmm11[5],xmm9[5],xmm11[6],xmm9[6],xmm11[7],xmm9[7] -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} ymm11 = [0,3,2,1,0,3,2,1,0,3,2,1,4,5,6,5] -; AVX512BW-ONLY-SLOW-NEXT: vpermw %ymm9, %ymm11, %ymm9 -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm14, %zmm9, %zmm9 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm23, %xmm8, %xmm14 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm23, %xmm10, %xmm17 -; AVX512BW-ONLY-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm14 = xmm17[0],xmm14[0],xmm17[1],xmm14[1],xmm17[2],xmm14[2],xmm17[3],xmm14[3],xmm17[4],xmm14[4],xmm17[5],xmm14[5],xmm17[6],xmm14[6],xmm17[7],xmm14[7] -; AVX512BW-ONLY-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm8 = xmm10[0],xmm8[0],xmm10[1],xmm8[1],xmm10[2],xmm8[2],xmm10[3],xmm8[3],xmm10[4],xmm8[4],xmm10[5],xmm8[5],xmm10[6],xmm8[6],xmm10[7],xmm8[7] -; AVX512BW-ONLY-SLOW-NEXT: vprold $16, %xmm8, %xmm8 -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm14, %zmm8, %zmm8 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} zmm8 = zmm8[0,0,0,1,4,4,4,5] -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu16 %zmm8, %zmm9 {%k2} -; AVX512BW-ONLY-SLOW-NEXT: vpmovzxbw {{.*#+}} xmm8 = xmm13[0],zero,xmm13[1],zero,xmm13[2],zero,xmm13[3],zero,xmm13[4],zero,xmm13[5],zero,xmm13[6],zero,xmm13[7],zero -; AVX512BW-ONLY-SLOW-NEXT: vpshufd {{.*#+}} xmm10 = xmm13[2,1,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vpmovzxbw {{.*#+}} xmm10 = xmm10[0],zero,xmm10[1],zero,xmm10[2],zero,xmm10[3],zero,xmm10[4],zero,xmm10[5],zero,xmm10[6],zero,xmm10[7],zero -; AVX512BW-ONLY-SLOW-NEXT: vinserti32x4 $2, %xmm10, %zmm8, %zmm8 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm10 = [2,1,0,3,2,1,0,3,2,1,0,3,4,4,4,4,22,21,16,23,22,21,16,23,22,21,16,23,17,17,17,17] -; AVX512BW-ONLY-SLOW-NEXT: vpermw %zmm8, %zmm10, %zmm9 {%k1} -; AVX512BW-ONLY-SLOW-NEXT: vpshufd {{.*#+}} xmm8 = xmm15[2,1,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm8 = xmm8[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] -; AVX512BW-ONLY-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm13 = xmm15[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] -; AVX512BW-ONLY-SLOW-NEXT: vinserti32x4 $2, %xmm8, %zmm13, %zmm8 -; AVX512BW-ONLY-SLOW-NEXT: vpermw %zmm8, %zmm10, %zmm8 -; AVX512BW-ONLY-SLOW-NEXT: movabsq $585610922974906400, %rcx # imm = 0x820820820820820 -; AVX512BW-ONLY-SLOW-NEXT: kmovq %rcx, %k3 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm8, %zmm9 {%k3} -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm12, %xmm1, %xmm8 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm12, %xmm3, %xmm12 -; AVX512BW-ONLY-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm8 = xmm12[8],xmm8[8],xmm12[9],xmm8[9],xmm12[10],xmm8[10],xmm12[11],xmm8[11],xmm12[12],xmm8[12],xmm12[13],xmm8[13],xmm12[14],xmm8[14],xmm12[15],xmm8[15] -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm8 = ymm8[0,0,0,1] -; AVX512BW-ONLY-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3],xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7] -; AVX512BW-ONLY-SLOW-NEXT: vpermw %ymm1, %ymm11, %ymm1 -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm8, %zmm1, %zmm1 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm23, %xmm2, %xmm3 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm23, %xmm4, %xmm8 -; AVX512BW-ONLY-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm3 = xmm8[0],xmm3[0],xmm8[1],xmm3[1],xmm8[2],xmm3[2],xmm8[3],xmm3[3],xmm8[4],xmm3[4],xmm8[5],xmm3[5],xmm8[6],xmm3[6],xmm8[7],xmm3[7] -; AVX512BW-ONLY-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm2 = xmm4[0],xmm2[0],xmm4[1],xmm2[1],xmm4[2],xmm2[2],xmm4[3],xmm2[3],xmm4[4],xmm2[4],xmm4[5],xmm2[5],xmm4[6],xmm2[6],xmm4[7],xmm2[7] -; AVX512BW-ONLY-SLOW-NEXT: vprold $16, %xmm2, %xmm2 -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm2 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} zmm2 = zmm2[0,0,0,1,4,4,4,5] -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu16 %zmm2, %zmm1 {%k2} -; AVX512BW-ONLY-SLOW-NEXT: vpmovzxbw {{.*#+}} xmm2 = xmm5[0],zero,xmm5[1],zero,xmm5[2],zero,xmm5[3],zero,xmm5[4],zero,xmm5[5],zero,xmm5[6],zero,xmm5[7],zero -; AVX512BW-ONLY-SLOW-NEXT: vpshufd {{.*#+}} xmm3 = xmm5[2,1,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vpmovzxbw {{.*#+}} xmm3 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero,xmm3[4],zero,xmm3[5],zero,xmm3[6],zero,xmm3[7],zero -; AVX512BW-ONLY-SLOW-NEXT: vinserti32x4 $2, %xmm3, %zmm2, %zmm2 -; AVX512BW-ONLY-SLOW-NEXT: vpermw %zmm2, %zmm10, %zmm1 {%k1} -; AVX512BW-ONLY-SLOW-NEXT: vpshufd {{.*#+}} xmm2 = xmm6[2,1,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] -; AVX512BW-ONLY-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm3 = xmm6[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] -; AVX512BW-ONLY-SLOW-NEXT: vinserti32x4 $2, %xmm2, %zmm3, %zmm2 -; AVX512BW-ONLY-SLOW-NEXT: vpermw %zmm2, %zmm10, %zmm2 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm2, %zmm1 {%k3} -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 %zmm1, (%rax) -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 %zmm9, 192(%rax) -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 %zmm16, 128(%rax) -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 %zmm20, 320(%rax) -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 %zmm7, 256(%rax) -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 %zmm0, 64(%rax) -; AVX512BW-ONLY-SLOW-NEXT: vzeroupper -; AVX512BW-ONLY-SLOW-NEXT: retq +; AVX512BW-SLOW-LABEL: store_i8_stride6_vf64: +; AVX512BW-SLOW: # %bb.0: +; AVX512BW-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512BW-SLOW-NEXT: vmovdqa64 (%r8), %zmm14 +; AVX512BW-SLOW-NEXT: vmovdqa64 (%r9), %zmm12 +; AVX512BW-SLOW-NEXT: vmovdqa64 (%rsi), %ymm16 +; AVX512BW-SLOW-NEXT: vmovdqa64 (%rdi), %ymm17 +; AVX512BW-SLOW-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm17[0],ymm16[0],ymm17[1],ymm16[1],ymm17[2],ymm16[2],ymm17[3],ymm16[3],ymm17[4],ymm16[4],ymm17[5],ymm16[5],ymm17[6],ymm16[6],ymm17[7],ymm16[7],ymm17[16],ymm16[16],ymm17[17],ymm16[17],ymm17[18],ymm16[18],ymm17[19],ymm16[19],ymm17[20],ymm16[20],ymm17[21],ymm16[21],ymm17[22],ymm16[22],ymm17[23],ymm16[23] +; AVX512BW-SLOW-NEXT: vmovdqa (%rsi), %xmm1 +; AVX512BW-SLOW-NEXT: vmovdqa 32(%rsi), %xmm9 +; AVX512BW-SLOW-NEXT: vmovdqa (%rdi), %xmm3 +; AVX512BW-SLOW-NEXT: vmovdqa 32(%rdi), %xmm11 +; AVX512BW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm3[8],xmm1[8],xmm3[9],xmm1[9],xmm3[10],xmm1[10],xmm3[11],xmm1[11],xmm3[12],xmm1[12],xmm3[13],xmm1[13],xmm3[14],xmm1[14],xmm3[15],xmm1[15] +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm0, %zmm2, %zmm0 +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm7 = [4,3,6,5,4,3,6,5,4,3,6,5,7,7,7,7,24,27,26,25,24,27,26,25,24,27,26,25,28,29,30,29] +; AVX512BW-SLOW-NEXT: vpermw %zmm0, %zmm7, %zmm0 +; AVX512BW-SLOW-NEXT: vmovdqa (%rcx), %xmm2 +; AVX512BW-SLOW-NEXT: vmovdqa 32(%rcx), %xmm8 +; AVX512BW-SLOW-NEXT: vmovdqa (%rdx), %xmm4 +; AVX512BW-SLOW-NEXT: vmovdqa 32(%rdx), %xmm10 +; AVX512BW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm5 = xmm4[8],xmm2[8],xmm4[9],xmm2[9],xmm4[10],xmm2[10],xmm4[11],xmm2[11],xmm4[12],xmm2[12],xmm4[13],xmm2[13],xmm4[14],xmm2[14],xmm4[15],xmm2[15] +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm20 = [5,4,3,6,5,4,3,6,5,4,3,6,7,7,7,7] +; AVX512BW-SLOW-NEXT: vpermw %ymm5, %ymm20, %ymm5 +; AVX512BW-SLOW-NEXT: vmovdqa64 (%rcx), %ymm18 +; AVX512BW-SLOW-NEXT: vmovdqa64 (%rdx), %ymm19 +; AVX512BW-SLOW-NEXT: vpunpcklbw {{.*#+}} ymm6 = ymm19[0],ymm18[0],ymm19[1],ymm18[1],ymm19[2],ymm18[2],ymm19[3],ymm18[3],ymm19[4],ymm18[4],ymm19[5],ymm18[5],ymm19[6],ymm18[6],ymm19[7],ymm18[7],ymm19[16],ymm18[16],ymm19[17],ymm18[17],ymm19[18],ymm18[18],ymm19[19],ymm18[19],ymm19[20],ymm18[20],ymm19[21],ymm18[21],ymm19[22],ymm18[22],ymm19[23],ymm18[23] +; AVX512BW-SLOW-NEXT: vprold $16, %ymm6, %ymm6 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm6 = ymm6[2,2,2,3] +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm6, %zmm5, %zmm5 +; AVX512BW-SLOW-NEXT: movl $613566756, %r10d # imm = 0x24924924 +; AVX512BW-SLOW-NEXT: kmovd %r10d, %k1 +; AVX512BW-SLOW-NEXT: vmovdqu16 %zmm5, %zmm0 {%k1} +; AVX512BW-SLOW-NEXT: vmovdqa (%r8), %xmm5 +; AVX512BW-SLOW-NEXT: vmovdqa 32(%r8), %xmm13 +; AVX512BW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm6 = xmm5[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm23 = [2,5,4,3,2,5,4,3,2,5,4,3,6,5,6,7] +; AVX512BW-SLOW-NEXT: vpermw %ymm6, %ymm23, %ymm6 +; AVX512BW-SLOW-NEXT: vmovdqa64 (%r8), %ymm21 +; AVX512BW-SLOW-NEXT: vbroadcasti32x4 {{.*#+}} ymm24 = [2,0,1,0,0,0,3,0,0,0,0,0,4,0,0,0,2,0,1,0,0,0,3,0,0,0,0,0,4,0,0,0] +; AVX512BW-SLOW-NEXT: # ymm24 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-SLOW-NEXT: vpshufb %ymm24, %ymm21, %ymm15 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm15 = ymm15[2,2,2,3] +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm15, %zmm6, %zmm6 +; AVX512BW-SLOW-NEXT: movl $1227133513, %r10d # imm = 0x49249249 +; AVX512BW-SLOW-NEXT: kmovd %r10d, %k2 +; AVX512BW-SLOW-NEXT: vmovdqu16 %zmm6, %zmm0 {%k2} +; AVX512BW-SLOW-NEXT: vmovdqa (%r9), %xmm6 +; AVX512BW-SLOW-NEXT: vmovdqa 32(%r9), %xmm15 +; AVX512BW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm22 = xmm6[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] +; AVX512BW-SLOW-NEXT: vpermw %ymm22, %ymm23, %ymm25 +; AVX512BW-SLOW-NEXT: vmovdqa64 (%r9), %ymm22 +; AVX512BW-SLOW-NEXT: vbroadcasti32x4 {{.*#+}} ymm26 = [0,2,0,1,0,0,0,3,0,0,0,0,0,4,0,0,0,2,0,1,0,0,0,3,0,0,0,0,0,4,0,0] +; AVX512BW-SLOW-NEXT: # ymm26 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-SLOW-NEXT: vpshufb %ymm26, %ymm22, %ymm27 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm27 = ymm27[2,2,2,3] +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm27, %zmm25, %zmm25 +; AVX512BW-SLOW-NEXT: movabsq $2342443691899625602, %r10 # imm = 0x2082082082082082 +; AVX512BW-SLOW-NEXT: kmovq %r10, %k3 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm25, %zmm0 {%k3} +; AVX512BW-SLOW-NEXT: vmovdqa64 32(%rsi), %ymm25 +; AVX512BW-SLOW-NEXT: vmovdqa64 32(%rdi), %ymm27 +; AVX512BW-SLOW-NEXT: vpunpcklbw {{.*#+}} ymm28 = ymm27[0],ymm25[0],ymm27[1],ymm25[1],ymm27[2],ymm25[2],ymm27[3],ymm25[3],ymm27[4],ymm25[4],ymm27[5],ymm25[5],ymm27[6],ymm25[6],ymm27[7],ymm25[7],ymm27[16],ymm25[16],ymm27[17],ymm25[17],ymm27[18],ymm25[18],ymm27[19],ymm25[19],ymm27[20],ymm25[20],ymm27[21],ymm25[21],ymm27[22],ymm25[22],ymm27[23],ymm25[23] +; AVX512BW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm29 = xmm11[8],xmm9[8],xmm11[9],xmm9[9],xmm11[10],xmm9[10],xmm11[11],xmm9[11],xmm11[12],xmm9[12],xmm11[13],xmm9[13],xmm11[14],xmm9[14],xmm11[15],xmm9[15] +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm28, %zmm29, %zmm28 +; AVX512BW-SLOW-NEXT: vpermw %zmm28, %zmm7, %zmm7 +; AVX512BW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm28 = xmm10[8],xmm8[8],xmm10[9],xmm8[9],xmm10[10],xmm8[10],xmm10[11],xmm8[11],xmm10[12],xmm8[12],xmm10[13],xmm8[13],xmm10[14],xmm8[14],xmm10[15],xmm8[15] +; AVX512BW-SLOW-NEXT: vpermw %ymm28, %ymm20, %ymm20 +; AVX512BW-SLOW-NEXT: vmovdqa64 32(%rcx), %ymm28 +; AVX512BW-SLOW-NEXT: vmovdqa64 32(%rdx), %ymm29 +; AVX512BW-SLOW-NEXT: vpunpcklbw {{.*#+}} ymm30 = ymm29[0],ymm28[0],ymm29[1],ymm28[1],ymm29[2],ymm28[2],ymm29[3],ymm28[3],ymm29[4],ymm28[4],ymm29[5],ymm28[5],ymm29[6],ymm28[6],ymm29[7],ymm28[7],ymm29[16],ymm28[16],ymm29[17],ymm28[17],ymm29[18],ymm28[18],ymm29[19],ymm28[19],ymm29[20],ymm28[20],ymm29[21],ymm28[21],ymm29[22],ymm28[22],ymm29[23],ymm28[23] +; AVX512BW-SLOW-NEXT: vprold $16, %ymm30, %ymm30 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm30 = ymm30[2,2,2,3] +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm30, %zmm20, %zmm20 +; AVX512BW-SLOW-NEXT: vmovdqu16 %zmm20, %zmm7 {%k1} +; AVX512BW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm20 = xmm13[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] +; AVX512BW-SLOW-NEXT: vpermw %ymm20, %ymm23, %ymm20 +; AVX512BW-SLOW-NEXT: vmovdqa64 32(%r8), %ymm30 +; AVX512BW-SLOW-NEXT: vpshufb %ymm24, %ymm30, %ymm24 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm24 = ymm24[2,2,2,3] +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm24, %zmm20, %zmm20 +; AVX512BW-SLOW-NEXT: vmovdqu16 %zmm20, %zmm7 {%k2} +; AVX512BW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm20 = xmm15[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] +; AVX512BW-SLOW-NEXT: vpermw %ymm20, %ymm23, %ymm20 +; AVX512BW-SLOW-NEXT: vmovdqa64 32(%r9), %ymm24 +; AVX512BW-SLOW-NEXT: vpshufb %ymm26, %ymm24, %ymm23 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm23 = ymm23[2,2,2,3] +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm23, %zmm20, %zmm20 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm20, %zmm7 {%k3} +; AVX512BW-SLOW-NEXT: vpbroadcastq {{.*#+}} ymm26 = [8,7,6,9,0,0,10,0,8,7,6,9,0,0,10,0,8,7,6,9,0,0,10,0,8,7,6,9,0,0,10,0] +; AVX512BW-SLOW-NEXT: vpshufb %ymm26, %ymm25, %ymm20 +; AVX512BW-SLOW-NEXT: vpshufb %ymm26, %ymm27, %ymm23 +; AVX512BW-SLOW-NEXT: vpunpcklbw {{.*#+}} ymm20 = ymm23[0],ymm20[0],ymm23[1],ymm20[1],ymm23[2],ymm20[2],ymm23[3],ymm20[3],ymm23[4],ymm20[4],ymm23[5],ymm20[5],ymm23[6],ymm20[6],ymm23[7],ymm20[7],ymm23[16],ymm20[16],ymm23[17],ymm20[17],ymm23[18],ymm20[18],ymm23[19],ymm20[19],ymm23[20],ymm20[20],ymm23[21],ymm20[21],ymm23[22],ymm20[22],ymm23[23],ymm20[23] +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm20 = ymm20[2,2,2,3] +; AVX512BW-SLOW-NEXT: vpunpckhbw {{.*#+}} ymm23 = ymm27[8],ymm25[8],ymm27[9],ymm25[9],ymm27[10],ymm25[10],ymm27[11],ymm25[11],ymm27[12],ymm25[12],ymm27[13],ymm25[13],ymm27[14],ymm25[14],ymm27[15],ymm25[15],ymm27[24],ymm25[24],ymm27[25],ymm25[25],ymm27[26],ymm25[26],ymm27[27],ymm25[27],ymm27[28],ymm25[28],ymm27[29],ymm25[29],ymm27[30],ymm25[30],ymm27[31],ymm25[31] +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm25 = [12,11,14,13,12,11,14,13,12,11,14,13,15,15,15,15] +; AVX512BW-SLOW-NEXT: vpermw %ymm23, %ymm25, %ymm23 +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm23, %zmm20, %zmm27 +; AVX512BW-SLOW-NEXT: vpbroadcastq {{.*#+}} ymm23 = [5,8,7,6,9,0,0,10,5,8,7,6,9,0,0,10,5,8,7,6,9,0,0,10,5,8,7,6,9,0,0,10] +; AVX512BW-SLOW-NEXT: vpshufb %ymm23, %ymm28, %ymm20 +; AVX512BW-SLOW-NEXT: vpshufb %ymm23, %ymm29, %ymm31 +; AVX512BW-SLOW-NEXT: vpunpcklbw {{.*#+}} ymm20 = ymm31[0],ymm20[0],ymm31[1],ymm20[1],ymm31[2],ymm20[2],ymm31[3],ymm20[3],ymm31[4],ymm20[4],ymm31[5],ymm20[5],ymm31[6],ymm20[6],ymm31[7],ymm20[7],ymm31[16],ymm20[16],ymm31[17],ymm20[17],ymm31[18],ymm20[18],ymm31[19],ymm20[19],ymm31[20],ymm20[20],ymm31[21],ymm20[21],ymm31[22],ymm20[22],ymm31[23],ymm20[23] +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm20 = ymm20[2,2,2,3] +; AVX512BW-SLOW-NEXT: vpunpckhbw {{.*#+}} ymm28 = ymm29[8],ymm28[8],ymm29[9],ymm28[9],ymm29[10],ymm28[10],ymm29[11],ymm28[11],ymm29[12],ymm28[12],ymm29[13],ymm28[13],ymm29[14],ymm28[14],ymm29[15],ymm28[15],ymm29[24],ymm28[24],ymm29[25],ymm28[25],ymm29[26],ymm28[26],ymm29[27],ymm28[27],ymm29[28],ymm28[28],ymm29[29],ymm28[29],ymm29[30],ymm28[30],ymm29[31],ymm28[31] +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm29 = [13,12,11,14,13,12,11,14,13,12,11,14,15,15,15,15] +; AVX512BW-SLOW-NEXT: vpermw %ymm28, %ymm29, %ymm28 +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm28, %zmm20, %zmm20 +; AVX512BW-SLOW-NEXT: vmovdqu16 %zmm27, %zmm20 {%k1} +; AVX512BW-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm27 = zmm30[0,1,2,3],zmm14[4,5,6,7] +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm28 = +; AVX512BW-SLOW-NEXT: vpshufb %zmm28, %zmm27, %zmm27 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} zmm27 = zmm27[2,2,2,3,6,6,6,7] +; AVX512BW-SLOW-NEXT: movl $-1840700270, %ecx # imm = 0x92492492 +; AVX512BW-SLOW-NEXT: kmovd %ecx, %k2 +; AVX512BW-SLOW-NEXT: vmovdqu16 %zmm27, %zmm20 {%k2} +; AVX512BW-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm24 = zmm24[0,1,2,3],zmm12[4,5,6,7] +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm27 = +; AVX512BW-SLOW-NEXT: vpshufb %zmm27, %zmm24, %zmm24 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} zmm24 = zmm24[2,2,2,3,6,6,6,7] +; AVX512BW-SLOW-NEXT: movabsq $-9076969306111049208, %rcx # imm = 0x8208208208208208 +; AVX512BW-SLOW-NEXT: kmovq %rcx, %k3 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm24, %zmm20 {%k3} +; AVX512BW-SLOW-NEXT: vpshufb %ymm26, %ymm16, %ymm24 +; AVX512BW-SLOW-NEXT: vpshufb %ymm26, %ymm17, %ymm26 +; AVX512BW-SLOW-NEXT: vpunpcklbw {{.*#+}} ymm24 = ymm26[0],ymm24[0],ymm26[1],ymm24[1],ymm26[2],ymm24[2],ymm26[3],ymm24[3],ymm26[4],ymm24[4],ymm26[5],ymm24[5],ymm26[6],ymm24[6],ymm26[7],ymm24[7],ymm26[16],ymm24[16],ymm26[17],ymm24[17],ymm26[18],ymm24[18],ymm26[19],ymm24[19],ymm26[20],ymm24[20],ymm26[21],ymm24[21],ymm26[22],ymm24[22],ymm26[23],ymm24[23] +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm24 = ymm24[2,2,2,3] +; AVX512BW-SLOW-NEXT: vpunpckhbw {{.*#+}} ymm16 = ymm17[8],ymm16[8],ymm17[9],ymm16[9],ymm17[10],ymm16[10],ymm17[11],ymm16[11],ymm17[12],ymm16[12],ymm17[13],ymm16[13],ymm17[14],ymm16[14],ymm17[15],ymm16[15],ymm17[24],ymm16[24],ymm17[25],ymm16[25],ymm17[26],ymm16[26],ymm17[27],ymm16[27],ymm17[28],ymm16[28],ymm17[29],ymm16[29],ymm17[30],ymm16[30],ymm17[31],ymm16[31] +; AVX512BW-SLOW-NEXT: vpermw %ymm16, %ymm25, %ymm16 +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm16, %zmm24, %zmm17 +; AVX512BW-SLOW-NEXT: vpshufb %ymm23, %ymm18, %ymm16 +; AVX512BW-SLOW-NEXT: vpshufb %ymm23, %ymm19, %ymm24 +; AVX512BW-SLOW-NEXT: vpunpcklbw {{.*#+}} ymm16 = ymm24[0],ymm16[0],ymm24[1],ymm16[1],ymm24[2],ymm16[2],ymm24[3],ymm16[3],ymm24[4],ymm16[4],ymm24[5],ymm16[5],ymm24[6],ymm16[6],ymm24[7],ymm16[7],ymm24[16],ymm16[16],ymm24[17],ymm16[17],ymm24[18],ymm16[18],ymm24[19],ymm16[19],ymm24[20],ymm16[20],ymm24[21],ymm16[21],ymm24[22],ymm16[22],ymm24[23],ymm16[23] +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm16 = ymm16[2,2,2,3] +; AVX512BW-SLOW-NEXT: vpunpckhbw {{.*#+}} ymm18 = ymm19[8],ymm18[8],ymm19[9],ymm18[9],ymm19[10],ymm18[10],ymm19[11],ymm18[11],ymm19[12],ymm18[12],ymm19[13],ymm18[13],ymm19[14],ymm18[14],ymm19[15],ymm18[15],ymm19[24],ymm18[24],ymm19[25],ymm18[25],ymm19[26],ymm18[26],ymm19[27],ymm18[27],ymm19[28],ymm18[28],ymm19[29],ymm18[29],ymm19[30],ymm18[30],ymm19[31],ymm18[31] +; AVX512BW-SLOW-NEXT: vpermw %ymm18, %ymm29, %ymm18 +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm18, %zmm16, %zmm16 +; AVX512BW-SLOW-NEXT: vmovdqu16 %zmm17, %zmm16 {%k1} +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm21, %zmm14, %zmm14 +; AVX512BW-SLOW-NEXT: vpshufb %zmm28, %zmm14, %zmm14 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} zmm14 = zmm14[2,2,2,3,6,6,6,7] +; AVX512BW-SLOW-NEXT: vmovdqu16 %zmm14, %zmm16 {%k2} +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm22, %zmm12, %zmm12 +; AVX512BW-SLOW-NEXT: vpshufb %zmm27, %zmm12, %zmm12 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} zmm12 = zmm12[2,2,2,3,6,6,6,7] +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm12, %zmm16 {%k3} +; AVX512BW-SLOW-NEXT: vpbroadcastq {{.*#+}} xmm12 = [8,7,6,9,0,0,10,0,8,7,6,9,0,0,10,0] +; AVX512BW-SLOW-NEXT: vpshufb %xmm12, %xmm9, %xmm14 +; AVX512BW-SLOW-NEXT: vpshufb %xmm12, %xmm11, %xmm17 +; AVX512BW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm14 = xmm17[8],xmm14[8],xmm17[9],xmm14[9],xmm17[10],xmm14[10],xmm17[11],xmm14[11],xmm17[12],xmm14[12],xmm17[13],xmm14[13],xmm17[14],xmm14[14],xmm17[15],xmm14[15] +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm14 = ymm14[0,0,0,1] +; AVX512BW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm9 = xmm11[0],xmm9[0],xmm11[1],xmm9[1],xmm11[2],xmm9[2],xmm11[3],xmm9[3],xmm11[4],xmm9[4],xmm11[5],xmm9[5],xmm11[6],xmm9[6],xmm11[7],xmm9[7] +; AVX512BW-SLOW-NEXT: vmovdqa {{.*#+}} ymm11 = [0,3,2,1,0,3,2,1,0,3,2,1,4,5,6,5] +; AVX512BW-SLOW-NEXT: vpermw %ymm9, %ymm11, %ymm9 +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm14, %zmm9, %zmm9 +; AVX512BW-SLOW-NEXT: vpshufb %xmm23, %xmm8, %xmm14 +; AVX512BW-SLOW-NEXT: vpshufb %xmm23, %xmm10, %xmm17 +; AVX512BW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm14 = xmm17[0],xmm14[0],xmm17[1],xmm14[1],xmm17[2],xmm14[2],xmm17[3],xmm14[3],xmm17[4],xmm14[4],xmm17[5],xmm14[5],xmm17[6],xmm14[6],xmm17[7],xmm14[7] +; AVX512BW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm8 = xmm10[0],xmm8[0],xmm10[1],xmm8[1],xmm10[2],xmm8[2],xmm10[3],xmm8[3],xmm10[4],xmm8[4],xmm10[5],xmm8[5],xmm10[6],xmm8[6],xmm10[7],xmm8[7] +; AVX512BW-SLOW-NEXT: vprold $16, %xmm8, %xmm8 +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm14, %zmm8, %zmm8 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} zmm8 = zmm8[0,0,0,1,4,4,4,5] +; AVX512BW-SLOW-NEXT: vmovdqu16 %zmm8, %zmm9 {%k2} +; AVX512BW-SLOW-NEXT: vpmovzxbw {{.*#+}} xmm8 = xmm13[0],zero,xmm13[1],zero,xmm13[2],zero,xmm13[3],zero,xmm13[4],zero,xmm13[5],zero,xmm13[6],zero,xmm13[7],zero +; AVX512BW-SLOW-NEXT: vpshufd {{.*#+}} xmm10 = xmm13[2,1,2,3] +; AVX512BW-SLOW-NEXT: vpmovzxbw {{.*#+}} xmm10 = xmm10[0],zero,xmm10[1],zero,xmm10[2],zero,xmm10[3],zero,xmm10[4],zero,xmm10[5],zero,xmm10[6],zero,xmm10[7],zero +; AVX512BW-SLOW-NEXT: vinserti32x4 $2, %xmm10, %zmm8, %zmm8 +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm10 = [2,1,0,3,2,1,0,3,2,1,0,3,4,4,4,4,22,21,16,23,22,21,16,23,22,21,16,23,17,17,17,17] +; AVX512BW-SLOW-NEXT: vpermw %zmm8, %zmm10, %zmm9 {%k1} +; AVX512BW-SLOW-NEXT: vpshufd {{.*#+}} xmm8 = xmm15[2,1,2,3] +; AVX512BW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm8 = xmm8[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] +; AVX512BW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm13 = xmm15[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] +; AVX512BW-SLOW-NEXT: vinserti32x4 $2, %xmm8, %zmm13, %zmm8 +; AVX512BW-SLOW-NEXT: vpermw %zmm8, %zmm10, %zmm8 +; AVX512BW-SLOW-NEXT: movabsq $585610922974906400, %rcx # imm = 0x820820820820820 +; AVX512BW-SLOW-NEXT: kmovq %rcx, %k3 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm8, %zmm9 {%k3} +; AVX512BW-SLOW-NEXT: vpshufb %xmm12, %xmm1, %xmm8 +; AVX512BW-SLOW-NEXT: vpshufb %xmm12, %xmm3, %xmm12 +; AVX512BW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm8 = xmm12[8],xmm8[8],xmm12[9],xmm8[9],xmm12[10],xmm8[10],xmm12[11],xmm8[11],xmm12[12],xmm8[12],xmm12[13],xmm8[13],xmm12[14],xmm8[14],xmm12[15],xmm8[15] +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm8 = ymm8[0,0,0,1] +; AVX512BW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3],xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7] +; AVX512BW-SLOW-NEXT: vpermw %ymm1, %ymm11, %ymm1 +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm8, %zmm1, %zmm1 +; AVX512BW-SLOW-NEXT: vpshufb %xmm23, %xmm2, %xmm3 +; AVX512BW-SLOW-NEXT: vpshufb %xmm23, %xmm4, %xmm8 +; AVX512BW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm3 = xmm8[0],xmm3[0],xmm8[1],xmm3[1],xmm8[2],xmm3[2],xmm8[3],xmm3[3],xmm8[4],xmm3[4],xmm8[5],xmm3[5],xmm8[6],xmm3[6],xmm8[7],xmm3[7] +; AVX512BW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm2 = xmm4[0],xmm2[0],xmm4[1],xmm2[1],xmm4[2],xmm2[2],xmm4[3],xmm2[3],xmm4[4],xmm2[4],xmm4[5],xmm2[5],xmm4[6],xmm2[6],xmm4[7],xmm2[7] +; AVX512BW-SLOW-NEXT: vprold $16, %xmm2, %xmm2 +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm2 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} zmm2 = zmm2[0,0,0,1,4,4,4,5] +; AVX512BW-SLOW-NEXT: vmovdqu16 %zmm2, %zmm1 {%k2} +; AVX512BW-SLOW-NEXT: vpmovzxbw {{.*#+}} xmm2 = xmm5[0],zero,xmm5[1],zero,xmm5[2],zero,xmm5[3],zero,xmm5[4],zero,xmm5[5],zero,xmm5[6],zero,xmm5[7],zero +; AVX512BW-SLOW-NEXT: vpshufd {{.*#+}} xmm3 = xmm5[2,1,2,3] +; AVX512BW-SLOW-NEXT: vpmovzxbw {{.*#+}} xmm3 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero,xmm3[4],zero,xmm3[5],zero,xmm3[6],zero,xmm3[7],zero +; AVX512BW-SLOW-NEXT: vinserti32x4 $2, %xmm3, %zmm2, %zmm2 +; AVX512BW-SLOW-NEXT: vpermw %zmm2, %zmm10, %zmm1 {%k1} +; AVX512BW-SLOW-NEXT: vpshufd {{.*#+}} xmm2 = xmm6[2,1,2,3] +; AVX512BW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] +; AVX512BW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm3 = xmm6[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] +; AVX512BW-SLOW-NEXT: vinserti32x4 $2, %xmm2, %zmm3, %zmm2 +; AVX512BW-SLOW-NEXT: vpermw %zmm2, %zmm10, %zmm2 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm2, %zmm1 {%k3} +; AVX512BW-SLOW-NEXT: vmovdqa64 %zmm1, (%rax) +; AVX512BW-SLOW-NEXT: vmovdqa64 %zmm9, 192(%rax) +; AVX512BW-SLOW-NEXT: vmovdqa64 %zmm16, 128(%rax) +; AVX512BW-SLOW-NEXT: vmovdqa64 %zmm20, 320(%rax) +; AVX512BW-SLOW-NEXT: vmovdqa64 %zmm7, 256(%rax) +; AVX512BW-SLOW-NEXT: vmovdqa64 %zmm0, 64(%rax) +; AVX512BW-SLOW-NEXT: vzeroupper +; AVX512BW-SLOW-NEXT: retq ; ; AVX512BW-FAST-LABEL: store_i8_stride6_vf64: ; AVX512BW-FAST: # %bb.0: @@ -5083,216 +5083,6 @@ define void @store_i8_stride6_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec ; AVX512BW-FAST-NEXT: vmovdqa64 %zmm0, 320(%rax) ; AVX512BW-FAST-NEXT: vzeroupper ; AVX512BW-FAST-NEXT: retq -; -; AVX512DQBW-SLOW-LABEL: store_i8_stride6_vf64: -; AVX512DQBW-SLOW: # %bb.0: -; AVX512DQBW-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQBW-SLOW-NEXT: vmovdqa64 (%r8), %zmm14 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 (%r9), %zmm12 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 (%rsi), %ymm16 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 (%rdi), %ymm17 -; AVX512DQBW-SLOW-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm17[0],ymm16[0],ymm17[1],ymm16[1],ymm17[2],ymm16[2],ymm17[3],ymm16[3],ymm17[4],ymm16[4],ymm17[5],ymm16[5],ymm17[6],ymm16[6],ymm17[7],ymm16[7],ymm17[16],ymm16[16],ymm17[17],ymm16[17],ymm17[18],ymm16[18],ymm17[19],ymm16[19],ymm17[20],ymm16[20],ymm17[21],ymm16[21],ymm17[22],ymm16[22],ymm17[23],ymm16[23] -; AVX512DQBW-SLOW-NEXT: vmovdqa (%rsi), %xmm1 -; AVX512DQBW-SLOW-NEXT: vmovdqa 32(%rsi), %xmm9 -; AVX512DQBW-SLOW-NEXT: vmovdqa (%rdi), %xmm3 -; AVX512DQBW-SLOW-NEXT: vmovdqa 32(%rdi), %xmm11 -; AVX512DQBW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm3[8],xmm1[8],xmm3[9],xmm1[9],xmm3[10],xmm1[10],xmm3[11],xmm1[11],xmm3[12],xmm1[12],xmm3[13],xmm1[13],xmm3[14],xmm1[14],xmm3[15],xmm1[15] -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm0, %zmm2, %zmm0 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm7 = [4,3,6,5,4,3,6,5,4,3,6,5,7,7,7,7,24,27,26,25,24,27,26,25,24,27,26,25,28,29,30,29] -; AVX512DQBW-SLOW-NEXT: vpermw %zmm0, %zmm7, %zmm0 -; AVX512DQBW-SLOW-NEXT: vmovdqa (%rcx), %xmm2 -; AVX512DQBW-SLOW-NEXT: vmovdqa 32(%rcx), %xmm8 -; AVX512DQBW-SLOW-NEXT: vmovdqa (%rdx), %xmm4 -; AVX512DQBW-SLOW-NEXT: vmovdqa 32(%rdx), %xmm10 -; AVX512DQBW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm5 = xmm4[8],xmm2[8],xmm4[9],xmm2[9],xmm4[10],xmm2[10],xmm4[11],xmm2[11],xmm4[12],xmm2[12],xmm4[13],xmm2[13],xmm4[14],xmm2[14],xmm4[15],xmm2[15] -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm20 = [5,4,3,6,5,4,3,6,5,4,3,6,7,7,7,7] -; AVX512DQBW-SLOW-NEXT: vpermw %ymm5, %ymm20, %ymm5 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 (%rcx), %ymm18 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 (%rdx), %ymm19 -; AVX512DQBW-SLOW-NEXT: vpunpcklbw {{.*#+}} ymm6 = ymm19[0],ymm18[0],ymm19[1],ymm18[1],ymm19[2],ymm18[2],ymm19[3],ymm18[3],ymm19[4],ymm18[4],ymm19[5],ymm18[5],ymm19[6],ymm18[6],ymm19[7],ymm18[7],ymm19[16],ymm18[16],ymm19[17],ymm18[17],ymm19[18],ymm18[18],ymm19[19],ymm18[19],ymm19[20],ymm18[20],ymm19[21],ymm18[21],ymm19[22],ymm18[22],ymm19[23],ymm18[23] -; AVX512DQBW-SLOW-NEXT: vprold $16, %ymm6, %ymm6 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm6 = ymm6[2,2,2,3] -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm6, %zmm5, %zmm5 -; AVX512DQBW-SLOW-NEXT: movl $613566756, %r10d # imm = 0x24924924 -; AVX512DQBW-SLOW-NEXT: kmovd %r10d, %k1 -; AVX512DQBW-SLOW-NEXT: vmovdqu16 %zmm5, %zmm0 {%k1} -; AVX512DQBW-SLOW-NEXT: vmovdqa (%r8), %xmm5 -; AVX512DQBW-SLOW-NEXT: vmovdqa 32(%r8), %xmm13 -; AVX512DQBW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm6 = xmm5[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm23 = [2,5,4,3,2,5,4,3,2,5,4,3,6,5,6,7] -; AVX512DQBW-SLOW-NEXT: vpermw %ymm6, %ymm23, %ymm6 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 (%r8), %ymm21 -; AVX512DQBW-SLOW-NEXT: vbroadcasti64x2 {{.*#+}} ymm24 = [2,0,1,0,0,0,3,0,0,0,0,0,4,0,0,0,2,0,1,0,0,0,3,0,0,0,0,0,4,0,0,0] -; AVX512DQBW-SLOW-NEXT: # ymm24 = mem[0,1,0,1] -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm24, %ymm21, %ymm15 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm15 = ymm15[2,2,2,3] -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm15, %zmm6, %zmm6 -; AVX512DQBW-SLOW-NEXT: movl $1227133513, %r10d # imm = 0x49249249 -; AVX512DQBW-SLOW-NEXT: kmovd %r10d, %k2 -; AVX512DQBW-SLOW-NEXT: vmovdqu16 %zmm6, %zmm0 {%k2} -; AVX512DQBW-SLOW-NEXT: vmovdqa (%r9), %xmm6 -; AVX512DQBW-SLOW-NEXT: vmovdqa 32(%r9), %xmm15 -; AVX512DQBW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm22 = xmm6[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] -; AVX512DQBW-SLOW-NEXT: vpermw %ymm22, %ymm23, %ymm25 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 (%r9), %ymm22 -; AVX512DQBW-SLOW-NEXT: vbroadcasti64x2 {{.*#+}} ymm26 = [0,2,0,1,0,0,0,3,0,0,0,0,0,4,0,0,0,2,0,1,0,0,0,3,0,0,0,0,0,4,0,0] -; AVX512DQBW-SLOW-NEXT: # ymm26 = mem[0,1,0,1] -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm26, %ymm22, %ymm27 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm27 = ymm27[2,2,2,3] -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm27, %zmm25, %zmm25 -; AVX512DQBW-SLOW-NEXT: movabsq $2342443691899625602, %r10 # imm = 0x2082082082082082 -; AVX512DQBW-SLOW-NEXT: kmovq %r10, %k3 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm25, %zmm0 {%k3} -; AVX512DQBW-SLOW-NEXT: vmovdqa64 32(%rsi), %ymm25 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 32(%rdi), %ymm27 -; AVX512DQBW-SLOW-NEXT: vpunpcklbw {{.*#+}} ymm28 = ymm27[0],ymm25[0],ymm27[1],ymm25[1],ymm27[2],ymm25[2],ymm27[3],ymm25[3],ymm27[4],ymm25[4],ymm27[5],ymm25[5],ymm27[6],ymm25[6],ymm27[7],ymm25[7],ymm27[16],ymm25[16],ymm27[17],ymm25[17],ymm27[18],ymm25[18],ymm27[19],ymm25[19],ymm27[20],ymm25[20],ymm27[21],ymm25[21],ymm27[22],ymm25[22],ymm27[23],ymm25[23] -; AVX512DQBW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm29 = xmm11[8],xmm9[8],xmm11[9],xmm9[9],xmm11[10],xmm9[10],xmm11[11],xmm9[11],xmm11[12],xmm9[12],xmm11[13],xmm9[13],xmm11[14],xmm9[14],xmm11[15],xmm9[15] -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm28, %zmm29, %zmm28 -; AVX512DQBW-SLOW-NEXT: vpermw %zmm28, %zmm7, %zmm7 -; AVX512DQBW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm28 = xmm10[8],xmm8[8],xmm10[9],xmm8[9],xmm10[10],xmm8[10],xmm10[11],xmm8[11],xmm10[12],xmm8[12],xmm10[13],xmm8[13],xmm10[14],xmm8[14],xmm10[15],xmm8[15] -; AVX512DQBW-SLOW-NEXT: vpermw %ymm28, %ymm20, %ymm20 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 32(%rcx), %ymm28 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 32(%rdx), %ymm29 -; AVX512DQBW-SLOW-NEXT: vpunpcklbw {{.*#+}} ymm30 = ymm29[0],ymm28[0],ymm29[1],ymm28[1],ymm29[2],ymm28[2],ymm29[3],ymm28[3],ymm29[4],ymm28[4],ymm29[5],ymm28[5],ymm29[6],ymm28[6],ymm29[7],ymm28[7],ymm29[16],ymm28[16],ymm29[17],ymm28[17],ymm29[18],ymm28[18],ymm29[19],ymm28[19],ymm29[20],ymm28[20],ymm29[21],ymm28[21],ymm29[22],ymm28[22],ymm29[23],ymm28[23] -; AVX512DQBW-SLOW-NEXT: vprold $16, %ymm30, %ymm30 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm30 = ymm30[2,2,2,3] -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm30, %zmm20, %zmm20 -; AVX512DQBW-SLOW-NEXT: vmovdqu16 %zmm20, %zmm7 {%k1} -; AVX512DQBW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm20 = xmm13[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] -; AVX512DQBW-SLOW-NEXT: vpermw %ymm20, %ymm23, %ymm20 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 32(%r8), %ymm30 -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm24, %ymm30, %ymm24 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm24 = ymm24[2,2,2,3] -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm24, %zmm20, %zmm20 -; AVX512DQBW-SLOW-NEXT: vmovdqu16 %zmm20, %zmm7 {%k2} -; AVX512DQBW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm20 = xmm15[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] -; AVX512DQBW-SLOW-NEXT: vpermw %ymm20, %ymm23, %ymm20 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 32(%r9), %ymm24 -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm26, %ymm24, %ymm23 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm23 = ymm23[2,2,2,3] -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm23, %zmm20, %zmm20 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm20, %zmm7 {%k3} -; AVX512DQBW-SLOW-NEXT: vpbroadcastq {{.*#+}} ymm26 = [8,7,6,9,0,0,10,0,8,7,6,9,0,0,10,0,8,7,6,9,0,0,10,0,8,7,6,9,0,0,10,0] -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm26, %ymm25, %ymm20 -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm26, %ymm27, %ymm23 -; AVX512DQBW-SLOW-NEXT: vpunpcklbw {{.*#+}} ymm20 = ymm23[0],ymm20[0],ymm23[1],ymm20[1],ymm23[2],ymm20[2],ymm23[3],ymm20[3],ymm23[4],ymm20[4],ymm23[5],ymm20[5],ymm23[6],ymm20[6],ymm23[7],ymm20[7],ymm23[16],ymm20[16],ymm23[17],ymm20[17],ymm23[18],ymm20[18],ymm23[19],ymm20[19],ymm23[20],ymm20[20],ymm23[21],ymm20[21],ymm23[22],ymm20[22],ymm23[23],ymm20[23] -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm20 = ymm20[2,2,2,3] -; AVX512DQBW-SLOW-NEXT: vpunpckhbw {{.*#+}} ymm23 = ymm27[8],ymm25[8],ymm27[9],ymm25[9],ymm27[10],ymm25[10],ymm27[11],ymm25[11],ymm27[12],ymm25[12],ymm27[13],ymm25[13],ymm27[14],ymm25[14],ymm27[15],ymm25[15],ymm27[24],ymm25[24],ymm27[25],ymm25[25],ymm27[26],ymm25[26],ymm27[27],ymm25[27],ymm27[28],ymm25[28],ymm27[29],ymm25[29],ymm27[30],ymm25[30],ymm27[31],ymm25[31] -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm25 = [12,11,14,13,12,11,14,13,12,11,14,13,15,15,15,15] -; AVX512DQBW-SLOW-NEXT: vpermw %ymm23, %ymm25, %ymm23 -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm23, %zmm20, %zmm27 -; AVX512DQBW-SLOW-NEXT: vpbroadcastq {{.*#+}} ymm23 = [5,8,7,6,9,0,0,10,5,8,7,6,9,0,0,10,5,8,7,6,9,0,0,10,5,8,7,6,9,0,0,10] -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm23, %ymm28, %ymm20 -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm23, %ymm29, %ymm31 -; AVX512DQBW-SLOW-NEXT: vpunpcklbw {{.*#+}} ymm20 = ymm31[0],ymm20[0],ymm31[1],ymm20[1],ymm31[2],ymm20[2],ymm31[3],ymm20[3],ymm31[4],ymm20[4],ymm31[5],ymm20[5],ymm31[6],ymm20[6],ymm31[7],ymm20[7],ymm31[16],ymm20[16],ymm31[17],ymm20[17],ymm31[18],ymm20[18],ymm31[19],ymm20[19],ymm31[20],ymm20[20],ymm31[21],ymm20[21],ymm31[22],ymm20[22],ymm31[23],ymm20[23] -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm20 = ymm20[2,2,2,3] -; AVX512DQBW-SLOW-NEXT: vpunpckhbw {{.*#+}} ymm28 = ymm29[8],ymm28[8],ymm29[9],ymm28[9],ymm29[10],ymm28[10],ymm29[11],ymm28[11],ymm29[12],ymm28[12],ymm29[13],ymm28[13],ymm29[14],ymm28[14],ymm29[15],ymm28[15],ymm29[24],ymm28[24],ymm29[25],ymm28[25],ymm29[26],ymm28[26],ymm29[27],ymm28[27],ymm29[28],ymm28[28],ymm29[29],ymm28[29],ymm29[30],ymm28[30],ymm29[31],ymm28[31] -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm29 = [13,12,11,14,13,12,11,14,13,12,11,14,15,15,15,15] -; AVX512DQBW-SLOW-NEXT: vpermw %ymm28, %ymm29, %ymm28 -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm28, %zmm20, %zmm20 -; AVX512DQBW-SLOW-NEXT: vmovdqu16 %zmm27, %zmm20 {%k1} -; AVX512DQBW-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm27 = zmm30[0,1,2,3],zmm14[4,5,6,7] -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm28 = -; AVX512DQBW-SLOW-NEXT: vpshufb %zmm28, %zmm27, %zmm27 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} zmm27 = zmm27[2,2,2,3,6,6,6,7] -; AVX512DQBW-SLOW-NEXT: movl $-1840700270, %ecx # imm = 0x92492492 -; AVX512DQBW-SLOW-NEXT: kmovd %ecx, %k2 -; AVX512DQBW-SLOW-NEXT: vmovdqu16 %zmm27, %zmm20 {%k2} -; AVX512DQBW-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm24 = zmm24[0,1,2,3],zmm12[4,5,6,7] -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm27 = -; AVX512DQBW-SLOW-NEXT: vpshufb %zmm27, %zmm24, %zmm24 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} zmm24 = zmm24[2,2,2,3,6,6,6,7] -; AVX512DQBW-SLOW-NEXT: movabsq $-9076969306111049208, %rcx # imm = 0x8208208208208208 -; AVX512DQBW-SLOW-NEXT: kmovq %rcx, %k3 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm24, %zmm20 {%k3} -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm26, %ymm16, %ymm24 -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm26, %ymm17, %ymm26 -; AVX512DQBW-SLOW-NEXT: vpunpcklbw {{.*#+}} ymm24 = ymm26[0],ymm24[0],ymm26[1],ymm24[1],ymm26[2],ymm24[2],ymm26[3],ymm24[3],ymm26[4],ymm24[4],ymm26[5],ymm24[5],ymm26[6],ymm24[6],ymm26[7],ymm24[7],ymm26[16],ymm24[16],ymm26[17],ymm24[17],ymm26[18],ymm24[18],ymm26[19],ymm24[19],ymm26[20],ymm24[20],ymm26[21],ymm24[21],ymm26[22],ymm24[22],ymm26[23],ymm24[23] -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm24 = ymm24[2,2,2,3] -; AVX512DQBW-SLOW-NEXT: vpunpckhbw {{.*#+}} ymm16 = ymm17[8],ymm16[8],ymm17[9],ymm16[9],ymm17[10],ymm16[10],ymm17[11],ymm16[11],ymm17[12],ymm16[12],ymm17[13],ymm16[13],ymm17[14],ymm16[14],ymm17[15],ymm16[15],ymm17[24],ymm16[24],ymm17[25],ymm16[25],ymm17[26],ymm16[26],ymm17[27],ymm16[27],ymm17[28],ymm16[28],ymm17[29],ymm16[29],ymm17[30],ymm16[30],ymm17[31],ymm16[31] -; AVX512DQBW-SLOW-NEXT: vpermw %ymm16, %ymm25, %ymm16 -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm16, %zmm24, %zmm17 -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm23, %ymm18, %ymm16 -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm23, %ymm19, %ymm24 -; AVX512DQBW-SLOW-NEXT: vpunpcklbw {{.*#+}} ymm16 = ymm24[0],ymm16[0],ymm24[1],ymm16[1],ymm24[2],ymm16[2],ymm24[3],ymm16[3],ymm24[4],ymm16[4],ymm24[5],ymm16[5],ymm24[6],ymm16[6],ymm24[7],ymm16[7],ymm24[16],ymm16[16],ymm24[17],ymm16[17],ymm24[18],ymm16[18],ymm24[19],ymm16[19],ymm24[20],ymm16[20],ymm24[21],ymm16[21],ymm24[22],ymm16[22],ymm24[23],ymm16[23] -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm16 = ymm16[2,2,2,3] -; AVX512DQBW-SLOW-NEXT: vpunpckhbw {{.*#+}} ymm18 = ymm19[8],ymm18[8],ymm19[9],ymm18[9],ymm19[10],ymm18[10],ymm19[11],ymm18[11],ymm19[12],ymm18[12],ymm19[13],ymm18[13],ymm19[14],ymm18[14],ymm19[15],ymm18[15],ymm19[24],ymm18[24],ymm19[25],ymm18[25],ymm19[26],ymm18[26],ymm19[27],ymm18[27],ymm19[28],ymm18[28],ymm19[29],ymm18[29],ymm19[30],ymm18[30],ymm19[31],ymm18[31] -; AVX512DQBW-SLOW-NEXT: vpermw %ymm18, %ymm29, %ymm18 -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm18, %zmm16, %zmm16 -; AVX512DQBW-SLOW-NEXT: vmovdqu16 %zmm17, %zmm16 {%k1} -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm21, %zmm14, %zmm14 -; AVX512DQBW-SLOW-NEXT: vpshufb %zmm28, %zmm14, %zmm14 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} zmm14 = zmm14[2,2,2,3,6,6,6,7] -; AVX512DQBW-SLOW-NEXT: vmovdqu16 %zmm14, %zmm16 {%k2} -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm22, %zmm12, %zmm12 -; AVX512DQBW-SLOW-NEXT: vpshufb %zmm27, %zmm12, %zmm12 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} zmm12 = zmm12[2,2,2,3,6,6,6,7] -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm12, %zmm16 {%k3} -; AVX512DQBW-SLOW-NEXT: vpbroadcastq {{.*#+}} xmm12 = [8,7,6,9,0,0,10,0,8,7,6,9,0,0,10,0] -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm12, %xmm9, %xmm14 -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm12, %xmm11, %xmm17 -; AVX512DQBW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm14 = xmm17[8],xmm14[8],xmm17[9],xmm14[9],xmm17[10],xmm14[10],xmm17[11],xmm14[11],xmm17[12],xmm14[12],xmm17[13],xmm14[13],xmm17[14],xmm14[14],xmm17[15],xmm14[15] -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm14 = ymm14[0,0,0,1] -; AVX512DQBW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm9 = xmm11[0],xmm9[0],xmm11[1],xmm9[1],xmm11[2],xmm9[2],xmm11[3],xmm9[3],xmm11[4],xmm9[4],xmm11[5],xmm9[5],xmm11[6],xmm9[6],xmm11[7],xmm9[7] -; AVX512DQBW-SLOW-NEXT: vmovdqa {{.*#+}} ymm11 = [0,3,2,1,0,3,2,1,0,3,2,1,4,5,6,5] -; AVX512DQBW-SLOW-NEXT: vpermw %ymm9, %ymm11, %ymm9 -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm14, %zmm9, %zmm9 -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm23, %xmm8, %xmm14 -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm23, %xmm10, %xmm17 -; AVX512DQBW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm14 = xmm17[0],xmm14[0],xmm17[1],xmm14[1],xmm17[2],xmm14[2],xmm17[3],xmm14[3],xmm17[4],xmm14[4],xmm17[5],xmm14[5],xmm17[6],xmm14[6],xmm17[7],xmm14[7] -; AVX512DQBW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm8 = xmm10[0],xmm8[0],xmm10[1],xmm8[1],xmm10[2],xmm8[2],xmm10[3],xmm8[3],xmm10[4],xmm8[4],xmm10[5],xmm8[5],xmm10[6],xmm8[6],xmm10[7],xmm8[7] -; AVX512DQBW-SLOW-NEXT: vprold $16, %xmm8, %xmm8 -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm14, %zmm8, %zmm8 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} zmm8 = zmm8[0,0,0,1,4,4,4,5] -; AVX512DQBW-SLOW-NEXT: vmovdqu16 %zmm8, %zmm9 {%k2} -; AVX512DQBW-SLOW-NEXT: vpmovzxbw {{.*#+}} xmm8 = xmm13[0],zero,xmm13[1],zero,xmm13[2],zero,xmm13[3],zero,xmm13[4],zero,xmm13[5],zero,xmm13[6],zero,xmm13[7],zero -; AVX512DQBW-SLOW-NEXT: vpshufd {{.*#+}} xmm10 = xmm13[2,1,2,3] -; AVX512DQBW-SLOW-NEXT: vpmovzxbw {{.*#+}} xmm10 = xmm10[0],zero,xmm10[1],zero,xmm10[2],zero,xmm10[3],zero,xmm10[4],zero,xmm10[5],zero,xmm10[6],zero,xmm10[7],zero -; AVX512DQBW-SLOW-NEXT: vinserti32x4 $2, %xmm10, %zmm8, %zmm8 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm10 = [2,1,0,3,2,1,0,3,2,1,0,3,4,4,4,4,22,21,16,23,22,21,16,23,22,21,16,23,17,17,17,17] -; AVX512DQBW-SLOW-NEXT: vpermw %zmm8, %zmm10, %zmm9 {%k1} -; AVX512DQBW-SLOW-NEXT: vpshufd {{.*#+}} xmm8 = xmm15[2,1,2,3] -; AVX512DQBW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm8 = xmm8[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] -; AVX512DQBW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm13 = xmm15[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] -; AVX512DQBW-SLOW-NEXT: vinserti32x4 $2, %xmm8, %zmm13, %zmm8 -; AVX512DQBW-SLOW-NEXT: vpermw %zmm8, %zmm10, %zmm8 -; AVX512DQBW-SLOW-NEXT: movabsq $585610922974906400, %rcx # imm = 0x820820820820820 -; AVX512DQBW-SLOW-NEXT: kmovq %rcx, %k3 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm8, %zmm9 {%k3} -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm12, %xmm1, %xmm8 -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm12, %xmm3, %xmm12 -; AVX512DQBW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm8 = xmm12[8],xmm8[8],xmm12[9],xmm8[9],xmm12[10],xmm8[10],xmm12[11],xmm8[11],xmm12[12],xmm8[12],xmm12[13],xmm8[13],xmm12[14],xmm8[14],xmm12[15],xmm8[15] -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm8 = ymm8[0,0,0,1] -; AVX512DQBW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3],xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7] -; AVX512DQBW-SLOW-NEXT: vpermw %ymm1, %ymm11, %ymm1 -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm8, %zmm1, %zmm1 -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm23, %xmm2, %xmm3 -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm23, %xmm4, %xmm8 -; AVX512DQBW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm3 = xmm8[0],xmm3[0],xmm8[1],xmm3[1],xmm8[2],xmm3[2],xmm8[3],xmm3[3],xmm8[4],xmm3[4],xmm8[5],xmm3[5],xmm8[6],xmm3[6],xmm8[7],xmm3[7] -; AVX512DQBW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm2 = xmm4[0],xmm2[0],xmm4[1],xmm2[1],xmm4[2],xmm2[2],xmm4[3],xmm2[3],xmm4[4],xmm2[4],xmm4[5],xmm2[5],xmm4[6],xmm2[6],xmm4[7],xmm2[7] -; AVX512DQBW-SLOW-NEXT: vprold $16, %xmm2, %xmm2 -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm2 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} zmm2 = zmm2[0,0,0,1,4,4,4,5] -; AVX512DQBW-SLOW-NEXT: vmovdqu16 %zmm2, %zmm1 {%k2} -; AVX512DQBW-SLOW-NEXT: vpmovzxbw {{.*#+}} xmm2 = xmm5[0],zero,xmm5[1],zero,xmm5[2],zero,xmm5[3],zero,xmm5[4],zero,xmm5[5],zero,xmm5[6],zero,xmm5[7],zero -; AVX512DQBW-SLOW-NEXT: vpshufd {{.*#+}} xmm3 = xmm5[2,1,2,3] -; AVX512DQBW-SLOW-NEXT: vpmovzxbw {{.*#+}} xmm3 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero,xmm3[4],zero,xmm3[5],zero,xmm3[6],zero,xmm3[7],zero -; AVX512DQBW-SLOW-NEXT: vinserti32x4 $2, %xmm3, %zmm2, %zmm2 -; AVX512DQBW-SLOW-NEXT: vpermw %zmm2, %zmm10, %zmm1 {%k1} -; AVX512DQBW-SLOW-NEXT: vpshufd {{.*#+}} xmm2 = xmm6[2,1,2,3] -; AVX512DQBW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] -; AVX512DQBW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm3 = xmm6[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] -; AVX512DQBW-SLOW-NEXT: vinserti32x4 $2, %xmm2, %zmm3, %zmm2 -; AVX512DQBW-SLOW-NEXT: vpermw %zmm2, %zmm10, %zmm2 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm2, %zmm1 {%k3} -; AVX512DQBW-SLOW-NEXT: vmovdqa64 %zmm1, (%rax) -; AVX512DQBW-SLOW-NEXT: vmovdqa64 %zmm9, 192(%rax) -; AVX512DQBW-SLOW-NEXT: vmovdqa64 %zmm16, 128(%rax) -; AVX512DQBW-SLOW-NEXT: vmovdqa64 %zmm20, 320(%rax) -; AVX512DQBW-SLOW-NEXT: vmovdqa64 %zmm7, 256(%rax) -; AVX512DQBW-SLOW-NEXT: vmovdqa64 %zmm0, 64(%rax) -; AVX512DQBW-SLOW-NEXT: vzeroupper -; AVX512DQBW-SLOW-NEXT: retq %in.vec0 = load <64 x i8>, ptr %in.vecptr0, align 64 %in.vec1 = load <64 x i8>, ptr %in.vecptr1, align 64 %in.vec2 = load <64 x i8>, ptr %in.vecptr2, align 64 @@ -5317,11 +5107,13 @@ define void @store_i8_stride6_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec ; AVX512-SLOW: {{.*}} ; AVX512BW-ONLY: {{.*}} ; AVX512BW-ONLY-FAST: {{.*}} +; AVX512BW-ONLY-SLOW: {{.*}} ; AVX512DQ-FAST: {{.*}} ; AVX512DQ-ONLY: {{.*}} ; AVX512DQ-SLOW: {{.*}} ; AVX512DQBW-FAST: {{.*}} ; AVX512DQBW-ONLY: {{.*}} +; AVX512DQBW-SLOW: {{.*}} ; AVX512F-ONLY: {{.*}} ; AVX512F-ONLY-FAST: {{.*}} ; AVX512F-ONLY-SLOW: {{.*}} diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll index bb74d0f8fe7e..54ed0f184827 100644 --- a/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll +++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll @@ -3318,160 +3318,160 @@ define void @store_i8_stride7_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec ; AVX2-FAST-PERLANE-NEXT: vzeroupper ; AVX2-FAST-PERLANE-NEXT: retq ; -; AVX512F-ONLY-SLOW-LABEL: store_i8_stride7_vf32: -; AVX512F-ONLY-SLOW: # %bb.0: -; AVX512F-ONLY-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512F-ONLY-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %r10 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rdi), %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rsi), %ymm1 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rdx), %ymm11 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rcx), %ymm3 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%r8), %ymm5 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%r9), %ymm6 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%r10), %ymm4 -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm7 = ymm4[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,22,23,26,27,24,25,22,23,u,u,u,u,26,27,24,25] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} ymm8 = ymm4[2,1,1,2,4,5,6,7,10,9,9,10,12,13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm9 = -; AVX512F-ONLY-SLOW-NEXT: vpermi2d %zmm7, %zmm8, %zmm9 -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm7 = ymm6[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm6[20],zero,ymm6[18],zero,zero,zero,zero,ymm6[21],zero,ymm6[19],zero,zero,zero,zero,ymm6[22] -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm8 = ymm6[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm6[25],zero,ymm6[23],zero,zero,zero,zero,ymm6[26],zero,ymm6[24],zero,zero -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm8, %zmm7, %zmm7 -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} zmm7 = zmm7[2,3,2,3,6,7,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm8 = ymm5[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,20],zero,ymm5[18],zero,ymm5[20,21,20,21],zero,ymm5[19],zero,ymm5[19,20,21,22],zero -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm10 = ymm5[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,24,25,24,25],zero,ymm5[23],zero,ymm5[23,24,25,26],zero,ymm5[24],zero,ymm5[30,31] -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm10, %zmm8, %zmm8 -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} zmm8 = zmm8[2,3,2,3,6,7,6,7] -; AVX512F-ONLY-SLOW-NEXT: vporq %zmm7, %zmm8, %zmm7 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm7 -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm8 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,25,u,23,u,u,u,u,26,u,24,u,u,u,u,27,u] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm8 = ymm8[2,3,2,3] -; AVX512F-ONLY-SLOW-NEXT: vbroadcasti32x4 {{.*#+}} ymm16 = [18374967954648269055,71777218572844800,18374967954648269055,71777218572844800] -; AVX512F-ONLY-SLOW-NEXT: # ymm16 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpandq %ymm16, %ymm8, %ymm8 -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm9 = ymm11[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18],zero,ymm11[18,19,20,21],zero,ymm11[19],zero,ymm11[25,26,27,22],zero,ymm11[20],zero -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm9 = ymm9[2,3,2,3] -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm8, %zmm9, %zmm8 -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm9 = ymm3[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm3[18],zero,zero,zero,zero,ymm3[21],zero,ymm3[19],zero,zero,zero,zero,ymm3[22],zero,ymm3[20] -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm10 = ymm2[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm2[23],zero,zero,zero,zero,ymm2[26],zero,ymm2[24],zero,zero,zero,zero,ymm2[27],zero,ymm2[25] -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm10, %zmm9, %zmm9 -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} zmm9 = zmm9[2,3,2,3,6,7,6,7] -; AVX512F-ONLY-SLOW-NEXT: vporq %zmm9, %zmm8, %zmm9 -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} ymm8 = ymm2[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm8 = ymm8[0,0,1,1,4,4,5,5] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm8 = ymm8[2,3,2,3] -; AVX512F-ONLY-SLOW-NEXT: vbroadcasti32x4 {{.*#+}} ymm17 = [18374966859431673855,18446463693966278655,18374966859431673855,18446463693966278655] -; AVX512F-ONLY-SLOW-NEXT: # ymm17 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpandq %ymm17, %ymm8, %ymm8 -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm10 = ymm11[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,24,25],zero,ymm11[23],zero,ymm11[21,22,23,26],zero,ymm11[24],zero,ymm11[28,29,26,27] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm11, %ymm20 -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm10 = ymm10[2,3,2,3] -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm10, %zmm8, %zmm8 -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm10 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm1[21],zero,ymm1[19],zero,zero,zero,zero,ymm1[22],zero,ymm1[20],zero,zero -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm11 = ymm3[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm3[25],zero,ymm3[23],zero,zero,zero,zero,ymm3[26],zero,ymm3[24],zero,zero,zero,zero -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm11, %zmm10, %zmm10 -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} zmm10 = zmm10[2,3,2,3,6,7,6,7] -; AVX512F-ONLY-SLOW-NEXT: vporq %zmm10, %zmm8, %zmm8 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm8 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm7, %zmm8 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rsi), %xmm11 -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} xmm7 = xmm11[u],zero,xmm11[7],zero,xmm11[5,u,u,u],zero,xmm11[8],zero,xmm11[6,u,u,u],zero -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rdi), %xmm12 -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} xmm9 = xmm12[u,7],zero,xmm12[5],zero,xmm12[u,u,u,8],zero,xmm12[6],zero,xmm12[u,u,u,9] -; AVX512F-ONLY-SLOW-NEXT: vpor %xmm7, %xmm9, %xmm7 -; AVX512F-ONLY-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm9 = xmm12[0],xmm11[0],xmm12[1],xmm11[1],xmm12[2],xmm11[2],xmm12[3],xmm11[3],xmm12[4],xmm11[4],xmm12[5],xmm11[5],xmm12[6],xmm11[6],xmm12[7],xmm11[7] -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} xmm9 = xmm9[0,1,u,u,u,6,7,2,3,u,u,u,8,9,4,5] -; AVX512F-ONLY-SLOW-NEXT: vinserti32x4 $2, %xmm7, %zmm9, %zmm7 -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} zmm10 = zmm7[0,1,0,1,4,5,4,5] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rcx), %xmm7 -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} xmm13 = xmm7[u,u,u],zero,xmm7[7],zero,xmm7[5,u,u,u],zero,xmm7[8],zero,xmm7[6,u,u] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%rdx), %xmm9 -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} xmm14 = xmm9[u,u,u,7],zero,xmm9[5],zero,xmm9[u,u,u,8],zero,xmm9[6],zero,xmm9[u,u] -; AVX512F-ONLY-SLOW-NEXT: vpor %xmm13, %xmm14, %xmm13 -; AVX512F-ONLY-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm14 = xmm9[0],xmm7[0],xmm9[1],xmm7[1],xmm9[2],xmm7[2],xmm9[3],xmm7[3],xmm9[4],xmm7[4],xmm9[5],xmm7[5],xmm9[6],xmm7[6],xmm9[7],xmm7[7] -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} xmm14 = xmm14[4,5,0,1,u,u,u,6,7,2,3,u,u,u,8,9] -; AVX512F-ONLY-SLOW-NEXT: vinserti32x4 $2, %xmm13, %zmm14, %zmm13 -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} zmm18 = zmm13[0,1,0,1,4,5,4,5] -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm10, %zmm18 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%r9), %xmm13 -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} xmm10 = zero,xmm13[4,u,u,u],zero,xmm13[7],zero,xmm13[5,u,u,u],zero,xmm13[8],zero,xmm13[6] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%r8), %xmm14 -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} xmm15 = xmm14[4],zero,xmm14[u,u,u,7],zero,xmm14[5],zero,xmm14[u,u,u,8],zero,xmm14[6],zero -; AVX512F-ONLY-SLOW-NEXT: vpor %xmm10, %xmm15, %xmm10 -; AVX512F-ONLY-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm15 = xmm14[0],xmm13[0],xmm14[1],xmm13[1],xmm14[2],xmm13[2],xmm14[3],xmm13[3],xmm14[4],xmm13[4],xmm14[5],xmm13[5],xmm14[6],xmm13[6],xmm14[7],xmm13[7] -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} xmm15 = xmm15[u,u,4,5,0,1,u,u,u,6,7,2,3,u,u,u] -; AVX512F-ONLY-SLOW-NEXT: vinserti32x4 $2, %xmm10, %zmm15, %zmm10 -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} zmm19 = zmm10[0,1,0,1,4,5,4,5] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa (%r10), %xmm15 -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} xmm10 = xmm15[4,5,4,5,4,5,8,9,6,7,6,7,6,7,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} xmm0 = xmm15[1,1,0,0,4,5,6,7] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,2,0] -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm10, %zmm0, %zmm0 -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} zmm10 = zmm0[0,0,1,0,4,4,5,4] -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm19, %zmm10 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm18, %zmm10 -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm0 = zero,zero,zero,ymm1[14,u,u],zero,zero,zero,zero,ymm1[15,u,u],zero,zero,zero,zero,ymm1[16,u,u],zero,zero,zero,zero,ymm1[17,u,u],zero,zero,zero,zero,ymm1[18] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm1, %ymm19 -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm1 = ymm2[0,1,14],zero,ymm2[u,u,0,1,14,15],zero,ymm2[u,u,13,2,3,16],zero,ymm2[u,u,28,29,16,17],zero,ymm2[u,u,19,28,29,18],zero -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm2, %ymm18 -; AVX512F-ONLY-SLOW-NEXT: vpor %ymm0, %ymm1, %ymm0 -; AVX512F-ONLY-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm1 = xmm7[8],xmm9[8],xmm7[9],xmm9[9],xmm7[10],xmm9[10],xmm7[11],xmm9[11],xmm7[12],xmm9[12],xmm7[13],xmm9[13],xmm7[14],xmm9[14],xmm7[15],xmm9[15] -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[6,3,2,u,u,u,9,8,5,4,u,u,u,11,10,7] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,1,0,1] -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm1 = ymm3[u,u,u,u],zero,ymm3[14,u,u,u,u,u],zero,ymm3[15,u,u,u,u,u],zero,ymm3[16,u,u,u,u,u],zero,ymm3[17,u,u,u,u,u] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm20, %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm7 = ymm2[u,u,u,u,14],zero,ymm2[u,u,u,u,u,15],zero,ymm2[u,u,u,u,u,16],zero,ymm2[u,u,u,u,u,17],zero,ymm2[u,u,u,u,u] -; AVX512F-ONLY-SLOW-NEXT: vpor %ymm1, %ymm7, %ymm1 -; AVX512F-ONLY-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm7 = xmm11[8],xmm12[8],xmm11[9],xmm12[9],xmm11[10],xmm12[10],xmm11[11],xmm12[11],xmm11[12],xmm12[12],xmm11[13],xmm12[13],xmm11[14],xmm12[14],xmm11[15],xmm12[15] -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} xmm7 = xmm7[2,u,u,u,9,8,5,4,u,u,u,11,10,7,6,u] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm7[0,1,0,1] -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm1, %zmm7, %zmm1 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1 -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm0 = zero,ymm5[u,u,u,u,u,14],zero,ymm5[u,u,u,u,u,15],zero,ymm5[u,u,u,u,u,16],zero,ymm5[u,u,u,u,u,17],zero,ymm5[u,u,u] -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm7 = ymm6[13,u,u,u,u,u],zero,ymm6[14,u,u,u,u,u],zero,ymm6[15,u,u,u,u,u],zero,ymm6[16,u,u,u,u,u],zero,ymm6[17,u,u,u] -; AVX512F-ONLY-SLOW-NEXT: vpor %ymm0, %ymm7, %ymm0 -; AVX512F-ONLY-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm7 = xmm14[8],xmm13[8],xmm14[9],xmm13[9],xmm14[10],xmm13[10],xmm14[11],xmm13[11],xmm14[12],xmm13[12],xmm14[13],xmm13[13],xmm14[14],xmm13[14],xmm14[15],xmm13[15] -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} xmm7 = xmm7[u,6,7,2,3,u,u,u,8,9,4,5,u,u,u,10] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm7[0,1,0,1] -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm0, %zmm7, %zmm0 -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} xmm7 = xmm15[0,1,2,3,4,5,5,6] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} xmm7 = xmm7[2,2,3,3] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm7[0,1,0,1] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} ymm9 = [255,255,255,255,255,0,255,255,255,255,255,255,0,255,255,255,255,255,255,0,255,255,255,255,255,255,0,255,255,255,255,255] -; AVX512F-ONLY-SLOW-NEXT: vpandn %ymm7, %ymm9, %ymm7 -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm9 = zero,ymm4[13,u,u,u,u],zero,zero,ymm4[14,u,u,u,u],zero,zero,ymm4[15,u,u,u,u],zero,zero,ymm4[16,u,u,u,u],zero,zero,ymm4[17,u,u] -; AVX512F-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm9, %zmm7, %zmm7 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm7 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm7 -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm0 = ymm6[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,29,u,27,u,u,u,u,30,u,28,u,u,u,u,31,u] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,3,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm1 = ymm5[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm5[27],zero,zero,zero,zero,ymm5[30],zero,ymm5[28],zero,zero,zero,zero,ymm5[31],zero,ymm5[29] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,3,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $248, %ymm16, %ymm0, %ymm1 -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm0 = ymm4[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,28,29,26,27,28,29,30,31,30,31,28,29,28,29,30,31] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,3,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0 -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm1 = ymm3[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,27,u,u,u,u,30,u,28,u,u,u,u,31,u,29,u] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,3,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm2 = ymm2[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm2[30],zero,ymm2[28],zero,zero,zero,zero,ymm2[31],zero,ymm2[29],zero,zero -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm2 = ymm2[2,3,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $248, %ymm17, %ymm1, %ymm2 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm19, %ymm1 -; AVX512F-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,ymm1[30],zero,ymm1[28],zero,zero,zero,zero,ymm1[31],zero,ymm1[29],zero,zero,zero -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,3,2,3] -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %ymm18, %ymm3 -; AVX512F-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm3 = ymm3[0,1,2,3,6,7,7,6,8,9,10,11,14,15,15,14] -; AVX512F-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm3 = ymm3[2,2,3,3,6,6,7,7] -; AVX512F-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm3 = ymm3[2,3,2,3] -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $236, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm3 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm3 -; AVX512F-ONLY-SLOW-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm3 -; AVX512F-ONLY-SLOW-NEXT: vmovdqa %ymm3, 192(%rax) -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %zmm10, (%rax) -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %zmm8, 128(%rax) -; AVX512F-ONLY-SLOW-NEXT: vmovdqa64 %zmm7, 64(%rax) -; AVX512F-ONLY-SLOW-NEXT: vzeroupper -; AVX512F-ONLY-SLOW-NEXT: retq +; AVX512F-SLOW-LABEL: store_i8_stride7_vf32: +; AVX512F-SLOW: # %bb.0: +; AVX512F-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512F-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %r10 +; AVX512F-SLOW-NEXT: vmovdqa (%rdi), %ymm2 +; AVX512F-SLOW-NEXT: vmovdqa (%rsi), %ymm1 +; AVX512F-SLOW-NEXT: vmovdqa (%rdx), %ymm11 +; AVX512F-SLOW-NEXT: vmovdqa (%rcx), %ymm3 +; AVX512F-SLOW-NEXT: vmovdqa (%r8), %ymm5 +; AVX512F-SLOW-NEXT: vmovdqa (%r9), %ymm6 +; AVX512F-SLOW-NEXT: vmovdqa (%r10), %ymm4 +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm7 = ymm4[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,22,23,26,27,24,25,22,23,u,u,u,u,26,27,24,25] +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} ymm8 = ymm4[2,1,1,2,4,5,6,7,10,9,9,10,12,13,14,15] +; AVX512F-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm9 = +; AVX512F-SLOW-NEXT: vpermi2d %zmm7, %zmm8, %zmm9 +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm7 = ymm6[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm6[20],zero,ymm6[18],zero,zero,zero,zero,ymm6[21],zero,ymm6[19],zero,zero,zero,zero,ymm6[22] +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm8 = ymm6[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm6[25],zero,ymm6[23],zero,zero,zero,zero,ymm6[26],zero,ymm6[24],zero,zero +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm8, %zmm7, %zmm7 +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} zmm7 = zmm7[2,3,2,3,6,7,6,7] +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm8 = ymm5[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,20],zero,ymm5[18],zero,ymm5[20,21,20,21],zero,ymm5[19],zero,ymm5[19,20,21,22],zero +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm10 = ymm5[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,24,25,24,25],zero,ymm5[23],zero,ymm5[23,24,25,26],zero,ymm5[24],zero,ymm5[30,31] +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm10, %zmm8, %zmm8 +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} zmm8 = zmm8[2,3,2,3,6,7,6,7] +; AVX512F-SLOW-NEXT: vporq %zmm7, %zmm8, %zmm7 +; AVX512F-SLOW-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm7 +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm8 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,25,u,23,u,u,u,u,26,u,24,u,u,u,u,27,u] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm8 = ymm8[2,3,2,3] +; AVX512F-SLOW-NEXT: vbroadcasti32x4 {{.*#+}} ymm16 = [18374967954648269055,71777218572844800,18374967954648269055,71777218572844800] +; AVX512F-SLOW-NEXT: # ymm16 = mem[0,1,2,3,0,1,2,3] +; AVX512F-SLOW-NEXT: vpandq %ymm16, %ymm8, %ymm8 +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm9 = ymm11[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18],zero,ymm11[18,19,20,21],zero,ymm11[19],zero,ymm11[25,26,27,22],zero,ymm11[20],zero +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm9 = ymm9[2,3,2,3] +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm8, %zmm9, %zmm8 +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm9 = ymm3[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm3[18],zero,zero,zero,zero,ymm3[21],zero,ymm3[19],zero,zero,zero,zero,ymm3[22],zero,ymm3[20] +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm10 = ymm2[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm2[23],zero,zero,zero,zero,ymm2[26],zero,ymm2[24],zero,zero,zero,zero,ymm2[27],zero,ymm2[25] +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm10, %zmm9, %zmm9 +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} zmm9 = zmm9[2,3,2,3,6,7,6,7] +; AVX512F-SLOW-NEXT: vporq %zmm9, %zmm8, %zmm9 +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} ymm8 = ymm2[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm8 = ymm8[0,0,1,1,4,4,5,5] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm8 = ymm8[2,3,2,3] +; AVX512F-SLOW-NEXT: vbroadcasti32x4 {{.*#+}} ymm17 = [18374966859431673855,18446463693966278655,18374966859431673855,18446463693966278655] +; AVX512F-SLOW-NEXT: # ymm17 = mem[0,1,2,3,0,1,2,3] +; AVX512F-SLOW-NEXT: vpandq %ymm17, %ymm8, %ymm8 +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm10 = ymm11[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,24,25],zero,ymm11[23],zero,ymm11[21,22,23,26],zero,ymm11[24],zero,ymm11[28,29,26,27] +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm11, %ymm20 +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm10 = ymm10[2,3,2,3] +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm10, %zmm8, %zmm8 +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm10 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm1[21],zero,ymm1[19],zero,zero,zero,zero,ymm1[22],zero,ymm1[20],zero,zero +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm11 = ymm3[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm3[25],zero,ymm3[23],zero,zero,zero,zero,ymm3[26],zero,ymm3[24],zero,zero,zero,zero +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm11, %zmm10, %zmm10 +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} zmm10 = zmm10[2,3,2,3,6,7,6,7] +; AVX512F-SLOW-NEXT: vporq %zmm10, %zmm8, %zmm8 +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm8 +; AVX512F-SLOW-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm7, %zmm8 +; AVX512F-SLOW-NEXT: vmovdqa (%rsi), %xmm11 +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} xmm7 = xmm11[u],zero,xmm11[7],zero,xmm11[5,u,u,u],zero,xmm11[8],zero,xmm11[6,u,u,u],zero +; AVX512F-SLOW-NEXT: vmovdqa (%rdi), %xmm12 +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} xmm9 = xmm12[u,7],zero,xmm12[5],zero,xmm12[u,u,u,8],zero,xmm12[6],zero,xmm12[u,u,u,9] +; AVX512F-SLOW-NEXT: vpor %xmm7, %xmm9, %xmm7 +; AVX512F-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm9 = xmm12[0],xmm11[0],xmm12[1],xmm11[1],xmm12[2],xmm11[2],xmm12[3],xmm11[3],xmm12[4],xmm11[4],xmm12[5],xmm11[5],xmm12[6],xmm11[6],xmm12[7],xmm11[7] +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} xmm9 = xmm9[0,1,u,u,u,6,7,2,3,u,u,u,8,9,4,5] +; AVX512F-SLOW-NEXT: vinserti32x4 $2, %xmm7, %zmm9, %zmm7 +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} zmm10 = zmm7[0,1,0,1,4,5,4,5] +; AVX512F-SLOW-NEXT: vmovdqa (%rcx), %xmm7 +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} xmm13 = xmm7[u,u,u],zero,xmm7[7],zero,xmm7[5,u,u,u],zero,xmm7[8],zero,xmm7[6,u,u] +; AVX512F-SLOW-NEXT: vmovdqa (%rdx), %xmm9 +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} xmm14 = xmm9[u,u,u,7],zero,xmm9[5],zero,xmm9[u,u,u,8],zero,xmm9[6],zero,xmm9[u,u] +; AVX512F-SLOW-NEXT: vpor %xmm13, %xmm14, %xmm13 +; AVX512F-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm14 = xmm9[0],xmm7[0],xmm9[1],xmm7[1],xmm9[2],xmm7[2],xmm9[3],xmm7[3],xmm9[4],xmm7[4],xmm9[5],xmm7[5],xmm9[6],xmm7[6],xmm9[7],xmm7[7] +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} xmm14 = xmm14[4,5,0,1,u,u,u,6,7,2,3,u,u,u,8,9] +; AVX512F-SLOW-NEXT: vinserti32x4 $2, %xmm13, %zmm14, %zmm13 +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} zmm18 = zmm13[0,1,0,1,4,5,4,5] +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm10, %zmm18 +; AVX512F-SLOW-NEXT: vmovdqa (%r9), %xmm13 +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} xmm10 = zero,xmm13[4,u,u,u],zero,xmm13[7],zero,xmm13[5,u,u,u],zero,xmm13[8],zero,xmm13[6] +; AVX512F-SLOW-NEXT: vmovdqa (%r8), %xmm14 +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} xmm15 = xmm14[4],zero,xmm14[u,u,u,7],zero,xmm14[5],zero,xmm14[u,u,u,8],zero,xmm14[6],zero +; AVX512F-SLOW-NEXT: vpor %xmm10, %xmm15, %xmm10 +; AVX512F-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm15 = xmm14[0],xmm13[0],xmm14[1],xmm13[1],xmm14[2],xmm13[2],xmm14[3],xmm13[3],xmm14[4],xmm13[4],xmm14[5],xmm13[5],xmm14[6],xmm13[6],xmm14[7],xmm13[7] +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} xmm15 = xmm15[u,u,4,5,0,1,u,u,u,6,7,2,3,u,u,u] +; AVX512F-SLOW-NEXT: vinserti32x4 $2, %xmm10, %zmm15, %zmm10 +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} zmm19 = zmm10[0,1,0,1,4,5,4,5] +; AVX512F-SLOW-NEXT: vmovdqa (%r10), %xmm15 +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} xmm10 = xmm15[4,5,4,5,4,5,8,9,6,7,6,7,6,7,6,7] +; AVX512F-SLOW-NEXT: vpshuflw {{.*#+}} xmm0 = xmm15[1,1,0,0,4,5,6,7] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,2,0] +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm10, %zmm0, %zmm0 +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} zmm10 = zmm0[0,0,1,0,4,4,5,4] +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm19, %zmm10 +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm18, %zmm10 +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm0 = zero,zero,zero,ymm1[14,u,u],zero,zero,zero,zero,ymm1[15,u,u],zero,zero,zero,zero,ymm1[16,u,u],zero,zero,zero,zero,ymm1[17,u,u],zero,zero,zero,zero,ymm1[18] +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm1, %ymm19 +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm1 = ymm2[0,1,14],zero,ymm2[u,u,0,1,14,15],zero,ymm2[u,u,13,2,3,16],zero,ymm2[u,u,28,29,16,17],zero,ymm2[u,u,19,28,29,18],zero +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm2, %ymm18 +; AVX512F-SLOW-NEXT: vpor %ymm0, %ymm1, %ymm0 +; AVX512F-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm1 = xmm7[8],xmm9[8],xmm7[9],xmm9[9],xmm7[10],xmm9[10],xmm7[11],xmm9[11],xmm7[12],xmm9[12],xmm7[13],xmm9[13],xmm7[14],xmm9[14],xmm7[15],xmm9[15] +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[6,3,2,u,u,u,9,8,5,4,u,u,u,11,10,7] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,1,0,1] +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm1 = ymm3[u,u,u,u],zero,ymm3[14,u,u,u,u,u],zero,ymm3[15,u,u,u,u,u],zero,ymm3[16,u,u,u,u,u],zero,ymm3[17,u,u,u,u,u] +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm20, %ymm2 +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm7 = ymm2[u,u,u,u,14],zero,ymm2[u,u,u,u,u,15],zero,ymm2[u,u,u,u,u,16],zero,ymm2[u,u,u,u,u,17],zero,ymm2[u,u,u,u,u] +; AVX512F-SLOW-NEXT: vpor %ymm1, %ymm7, %ymm1 +; AVX512F-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm7 = xmm11[8],xmm12[8],xmm11[9],xmm12[9],xmm11[10],xmm12[10],xmm11[11],xmm12[11],xmm11[12],xmm12[12],xmm11[13],xmm12[13],xmm11[14],xmm12[14],xmm11[15],xmm12[15] +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} xmm7 = xmm7[2,u,u,u,9,8,5,4,u,u,u,11,10,7,6,u] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm7[0,1,0,1] +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm1, %zmm7, %zmm1 +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1 +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm0 = zero,ymm5[u,u,u,u,u,14],zero,ymm5[u,u,u,u,u,15],zero,ymm5[u,u,u,u,u,16],zero,ymm5[u,u,u,u,u,17],zero,ymm5[u,u,u] +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm7 = ymm6[13,u,u,u,u,u],zero,ymm6[14,u,u,u,u,u],zero,ymm6[15,u,u,u,u,u],zero,ymm6[16,u,u,u,u,u],zero,ymm6[17,u,u,u] +; AVX512F-SLOW-NEXT: vpor %ymm0, %ymm7, %ymm0 +; AVX512F-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm7 = xmm14[8],xmm13[8],xmm14[9],xmm13[9],xmm14[10],xmm13[10],xmm14[11],xmm13[11],xmm14[12],xmm13[12],xmm14[13],xmm13[13],xmm14[14],xmm13[14],xmm14[15],xmm13[15] +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} xmm7 = xmm7[u,6,7,2,3,u,u,u,8,9,4,5,u,u,u,10] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm7[0,1,0,1] +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm0, %zmm7, %zmm0 +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} xmm7 = xmm15[0,1,2,3,4,5,5,6] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} xmm7 = xmm7[2,2,3,3] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm7[0,1,0,1] +; AVX512F-SLOW-NEXT: vmovdqa {{.*#+}} ymm9 = [255,255,255,255,255,0,255,255,255,255,255,255,0,255,255,255,255,255,255,0,255,255,255,255,255,255,0,255,255,255,255,255] +; AVX512F-SLOW-NEXT: vpandn %ymm7, %ymm9, %ymm7 +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm9 = zero,ymm4[13,u,u,u,u],zero,zero,ymm4[14,u,u,u,u],zero,zero,ymm4[15,u,u,u,u],zero,zero,ymm4[16,u,u,u,u],zero,zero,ymm4[17,u,u] +; AVX512F-SLOW-NEXT: vinserti64x4 $1, %ymm9, %zmm7, %zmm7 +; AVX512F-SLOW-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm7 +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm7 +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm0 = ymm6[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,29,u,27,u,u,u,u,30,u,28,u,u,u,u,31,u] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,3,2,3] +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm1 = ymm5[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm5[27],zero,zero,zero,zero,ymm5[30],zero,ymm5[28],zero,zero,zero,zero,ymm5[31],zero,ymm5[29] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,3,2,3] +; AVX512F-SLOW-NEXT: vpternlogq $248, %ymm16, %ymm0, %ymm1 +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm0 = ymm4[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,28,29,26,27,28,29,30,31,30,31,28,29,28,29,30,31] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,3,2,3] +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0 +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm1 = ymm3[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,27,u,u,u,u,30,u,28,u,u,u,u,31,u,29,u] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,3,2,3] +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm2 = ymm2[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm2[30],zero,ymm2[28],zero,zero,zero,zero,ymm2[31],zero,ymm2[29],zero,zero +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm2 = ymm2[2,3,2,3] +; AVX512F-SLOW-NEXT: vpternlogq $248, %ymm17, %ymm1, %ymm2 +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm19, %ymm1 +; AVX512F-SLOW-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,ymm1[30],zero,ymm1[28],zero,zero,zero,zero,ymm1[31],zero,ymm1[29],zero,zero,zero +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,3,2,3] +; AVX512F-SLOW-NEXT: vmovdqa64 %ymm18, %ymm3 +; AVX512F-SLOW-NEXT: vpshufhw {{.*#+}} ymm3 = ymm3[0,1,2,3,6,7,7,6,8,9,10,11,14,15,15,14] +; AVX512F-SLOW-NEXT: vpshufd {{.*#+}} ymm3 = ymm3[2,2,3,3,6,6,7,7] +; AVX512F-SLOW-NEXT: vpermq {{.*#+}} ymm3 = ymm3[2,3,2,3] +; AVX512F-SLOW-NEXT: vpternlogq $236, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm3 +; AVX512F-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm3 +; AVX512F-SLOW-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm3 +; AVX512F-SLOW-NEXT: vmovdqa %ymm3, 192(%rax) +; AVX512F-SLOW-NEXT: vmovdqa64 %zmm10, (%rax) +; AVX512F-SLOW-NEXT: vmovdqa64 %zmm8, 128(%rax) +; AVX512F-SLOW-NEXT: vmovdqa64 %zmm7, 64(%rax) +; AVX512F-SLOW-NEXT: vzeroupper +; AVX512F-SLOW-NEXT: retq ; ; AVX512F-FAST-LABEL: store_i8_stride7_vf32: ; AVX512F-FAST: # %bb.0: @@ -3622,161 +3622,6 @@ define void @store_i8_stride7_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec ; AVX512F-FAST-NEXT: vzeroupper ; AVX512F-FAST-NEXT: retq ; -; AVX512DQ-SLOW-LABEL: store_i8_stride7_vf32: -; AVX512DQ-SLOW: # %bb.0: -; AVX512DQ-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQ-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %r10 -; AVX512DQ-SLOW-NEXT: vmovdqa (%rdi), %ymm2 -; AVX512DQ-SLOW-NEXT: vmovdqa (%rsi), %ymm1 -; AVX512DQ-SLOW-NEXT: vmovdqa (%rdx), %ymm11 -; AVX512DQ-SLOW-NEXT: vmovdqa (%rcx), %ymm3 -; AVX512DQ-SLOW-NEXT: vmovdqa (%r8), %ymm5 -; AVX512DQ-SLOW-NEXT: vmovdqa (%r9), %ymm6 -; AVX512DQ-SLOW-NEXT: vmovdqa (%r10), %ymm4 -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm7 = ymm4[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,22,23,26,27,24,25,22,23,u,u,u,u,26,27,24,25] -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} ymm8 = ymm4[2,1,1,2,4,5,6,7,10,9,9,10,12,13,14,15] -; AVX512DQ-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm9 = -; AVX512DQ-SLOW-NEXT: vpermi2d %zmm7, %zmm8, %zmm9 -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm7 = ymm6[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm6[20],zero,ymm6[18],zero,zero,zero,zero,ymm6[21],zero,ymm6[19],zero,zero,zero,zero,ymm6[22] -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm8 = ymm6[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm6[25],zero,ymm6[23],zero,zero,zero,zero,ymm6[26],zero,ymm6[24],zero,zero -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm8, %zmm7, %zmm7 -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} zmm7 = zmm7[2,3,2,3,6,7,6,7] -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm8 = ymm5[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,20],zero,ymm5[18],zero,ymm5[20,21,20,21],zero,ymm5[19],zero,ymm5[19,20,21,22],zero -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm10 = ymm5[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,24,25,24,25],zero,ymm5[23],zero,ymm5[23,24,25,26],zero,ymm5[24],zero,ymm5[30,31] -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm10, %zmm8, %zmm8 -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} zmm8 = zmm8[2,3,2,3,6,7,6,7] -; AVX512DQ-SLOW-NEXT: vporq %zmm7, %zmm8, %zmm7 -; AVX512DQ-SLOW-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm7 -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm8 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,25,u,23,u,u,u,u,26,u,24,u,u,u,u,27,u] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm8 = ymm8[2,3,2,3] -; AVX512DQ-SLOW-NEXT: vbroadcasti64x2 {{.*#+}} ymm16 = [18374967954648269055,71777218572844800,18374967954648269055,71777218572844800] -; AVX512DQ-SLOW-NEXT: # ymm16 = mem[0,1,0,1] -; AVX512DQ-SLOW-NEXT: vpandq %ymm16, %ymm8, %ymm8 -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm9 = ymm11[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18],zero,ymm11[18,19,20,21],zero,ymm11[19],zero,ymm11[25,26,27,22],zero,ymm11[20],zero -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm9 = ymm9[2,3,2,3] -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm8, %zmm9, %zmm8 -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm9 = ymm3[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm3[18],zero,zero,zero,zero,ymm3[21],zero,ymm3[19],zero,zero,zero,zero,ymm3[22],zero,ymm3[20] -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm10 = ymm2[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm2[23],zero,zero,zero,zero,ymm2[26],zero,ymm2[24],zero,zero,zero,zero,ymm2[27],zero,ymm2[25] -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm10, %zmm9, %zmm9 -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} zmm9 = zmm9[2,3,2,3,6,7,6,7] -; AVX512DQ-SLOW-NEXT: vporq %zmm9, %zmm8, %zmm9 -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} ymm8 = ymm2[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm8 = ymm8[0,0,1,1,4,4,5,5] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm8 = ymm8[2,3,2,3] -; AVX512DQ-SLOW-NEXT: vbroadcasti64x2 {{.*#+}} ymm17 = [18374966859431673855,18446463693966278655,18374966859431673855,18446463693966278655] -; AVX512DQ-SLOW-NEXT: # ymm17 = mem[0,1,0,1] -; AVX512DQ-SLOW-NEXT: vpandq %ymm17, %ymm8, %ymm8 -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm10 = ymm11[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,24,25],zero,ymm11[23],zero,ymm11[21,22,23,26],zero,ymm11[24],zero,ymm11[28,29,26,27] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm11, %ymm20 -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm10 = ymm10[2,3,2,3] -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm10, %zmm8, %zmm8 -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm10 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm1[21],zero,ymm1[19],zero,zero,zero,zero,ymm1[22],zero,ymm1[20],zero,zero -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm11 = ymm3[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm3[25],zero,ymm3[23],zero,zero,zero,zero,ymm3[26],zero,ymm3[24],zero,zero,zero,zero -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm11, %zmm10, %zmm10 -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} zmm10 = zmm10[2,3,2,3,6,7,6,7] -; AVX512DQ-SLOW-NEXT: vporq %zmm10, %zmm8, %zmm8 -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm8 -; AVX512DQ-SLOW-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm7, %zmm8 -; AVX512DQ-SLOW-NEXT: vmovdqa (%rsi), %xmm11 -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} xmm7 = xmm11[u],zero,xmm11[7],zero,xmm11[5,u,u,u],zero,xmm11[8],zero,xmm11[6,u,u,u],zero -; AVX512DQ-SLOW-NEXT: vmovdqa (%rdi), %xmm12 -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} xmm9 = xmm12[u,7],zero,xmm12[5],zero,xmm12[u,u,u,8],zero,xmm12[6],zero,xmm12[u,u,u,9] -; AVX512DQ-SLOW-NEXT: vpor %xmm7, %xmm9, %xmm7 -; AVX512DQ-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm9 = xmm12[0],xmm11[0],xmm12[1],xmm11[1],xmm12[2],xmm11[2],xmm12[3],xmm11[3],xmm12[4],xmm11[4],xmm12[5],xmm11[5],xmm12[6],xmm11[6],xmm12[7],xmm11[7] -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} xmm9 = xmm9[0,1,u,u,u,6,7,2,3,u,u,u,8,9,4,5] -; AVX512DQ-SLOW-NEXT: vinserti32x4 $2, %xmm7, %zmm9, %zmm7 -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} zmm10 = zmm7[0,1,0,1,4,5,4,5] -; AVX512DQ-SLOW-NEXT: vmovdqa (%rcx), %xmm7 -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} xmm13 = xmm7[u,u,u],zero,xmm7[7],zero,xmm7[5,u,u,u],zero,xmm7[8],zero,xmm7[6,u,u] -; AVX512DQ-SLOW-NEXT: vmovdqa (%rdx), %xmm9 -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} xmm14 = xmm9[u,u,u,7],zero,xmm9[5],zero,xmm9[u,u,u,8],zero,xmm9[6],zero,xmm9[u,u] -; AVX512DQ-SLOW-NEXT: vpor %xmm13, %xmm14, %xmm13 -; AVX512DQ-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm14 = xmm9[0],xmm7[0],xmm9[1],xmm7[1],xmm9[2],xmm7[2],xmm9[3],xmm7[3],xmm9[4],xmm7[4],xmm9[5],xmm7[5],xmm9[6],xmm7[6],xmm9[7],xmm7[7] -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} xmm14 = xmm14[4,5,0,1,u,u,u,6,7,2,3,u,u,u,8,9] -; AVX512DQ-SLOW-NEXT: vinserti32x4 $2, %xmm13, %zmm14, %zmm13 -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} zmm18 = zmm13[0,1,0,1,4,5,4,5] -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm10, %zmm18 -; AVX512DQ-SLOW-NEXT: vmovdqa (%r9), %xmm13 -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} xmm10 = zero,xmm13[4,u,u,u],zero,xmm13[7],zero,xmm13[5,u,u,u],zero,xmm13[8],zero,xmm13[6] -; AVX512DQ-SLOW-NEXT: vmovdqa (%r8), %xmm14 -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} xmm15 = xmm14[4],zero,xmm14[u,u,u,7],zero,xmm14[5],zero,xmm14[u,u,u,8],zero,xmm14[6],zero -; AVX512DQ-SLOW-NEXT: vpor %xmm10, %xmm15, %xmm10 -; AVX512DQ-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm15 = xmm14[0],xmm13[0],xmm14[1],xmm13[1],xmm14[2],xmm13[2],xmm14[3],xmm13[3],xmm14[4],xmm13[4],xmm14[5],xmm13[5],xmm14[6],xmm13[6],xmm14[7],xmm13[7] -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} xmm15 = xmm15[u,u,4,5,0,1,u,u,u,6,7,2,3,u,u,u] -; AVX512DQ-SLOW-NEXT: vinserti32x4 $2, %xmm10, %zmm15, %zmm10 -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} zmm19 = zmm10[0,1,0,1,4,5,4,5] -; AVX512DQ-SLOW-NEXT: vmovdqa (%r10), %xmm15 -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} xmm10 = xmm15[4,5,4,5,4,5,8,9,6,7,6,7,6,7,6,7] -; AVX512DQ-SLOW-NEXT: vpshuflw {{.*#+}} xmm0 = xmm15[1,1,0,0,4,5,6,7] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,2,0] -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm10, %zmm0, %zmm0 -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} zmm10 = zmm0[0,0,1,0,4,4,5,4] -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm19, %zmm10 -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm18, %zmm10 -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm0 = zero,zero,zero,ymm1[14,u,u],zero,zero,zero,zero,ymm1[15,u,u],zero,zero,zero,zero,ymm1[16,u,u],zero,zero,zero,zero,ymm1[17,u,u],zero,zero,zero,zero,ymm1[18] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm1, %ymm19 -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm1 = ymm2[0,1,14],zero,ymm2[u,u,0,1,14,15],zero,ymm2[u,u,13,2,3,16],zero,ymm2[u,u,28,29,16,17],zero,ymm2[u,u,19,28,29,18],zero -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm2, %ymm18 -; AVX512DQ-SLOW-NEXT: vpor %ymm0, %ymm1, %ymm0 -; AVX512DQ-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm1 = xmm7[8],xmm9[8],xmm7[9],xmm9[9],xmm7[10],xmm9[10],xmm7[11],xmm9[11],xmm7[12],xmm9[12],xmm7[13],xmm9[13],xmm7[14],xmm9[14],xmm7[15],xmm9[15] -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[6,3,2,u,u,u,9,8,5,4,u,u,u,11,10,7] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,1,0,1] -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm1 = ymm3[u,u,u,u],zero,ymm3[14,u,u,u,u,u],zero,ymm3[15,u,u,u,u,u],zero,ymm3[16,u,u,u,u,u],zero,ymm3[17,u,u,u,u,u] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm20, %ymm2 -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm7 = ymm2[u,u,u,u,14],zero,ymm2[u,u,u,u,u,15],zero,ymm2[u,u,u,u,u,16],zero,ymm2[u,u,u,u,u,17],zero,ymm2[u,u,u,u,u] -; AVX512DQ-SLOW-NEXT: vpor %ymm1, %ymm7, %ymm1 -; AVX512DQ-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm7 = xmm11[8],xmm12[8],xmm11[9],xmm12[9],xmm11[10],xmm12[10],xmm11[11],xmm12[11],xmm11[12],xmm12[12],xmm11[13],xmm12[13],xmm11[14],xmm12[14],xmm11[15],xmm12[15] -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} xmm7 = xmm7[2,u,u,u,9,8,5,4,u,u,u,11,10,7,6,u] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm7[0,1,0,1] -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm1, %zmm7, %zmm1 -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1 -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm0 = zero,ymm5[u,u,u,u,u,14],zero,ymm5[u,u,u,u,u,15],zero,ymm5[u,u,u,u,u,16],zero,ymm5[u,u,u,u,u,17],zero,ymm5[u,u,u] -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm7 = ymm6[13,u,u,u,u,u],zero,ymm6[14,u,u,u,u,u],zero,ymm6[15,u,u,u,u,u],zero,ymm6[16,u,u,u,u,u],zero,ymm6[17,u,u,u] -; AVX512DQ-SLOW-NEXT: vpor %ymm0, %ymm7, %ymm0 -; AVX512DQ-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm7 = xmm14[8],xmm13[8],xmm14[9],xmm13[9],xmm14[10],xmm13[10],xmm14[11],xmm13[11],xmm14[12],xmm13[12],xmm14[13],xmm13[13],xmm14[14],xmm13[14],xmm14[15],xmm13[15] -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} xmm7 = xmm7[u,6,7,2,3,u,u,u,8,9,4,5,u,u,u,10] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm7[0,1,0,1] -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm0, %zmm7, %zmm0 -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} xmm7 = xmm15[0,1,2,3,4,5,5,6] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} xmm7 = xmm7[2,2,3,3] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm7[0,1,0,1] -; AVX512DQ-SLOW-NEXT: vmovdqa {{.*#+}} ymm9 = [255,255,255,255,255,0,255,255,255,255,255,255,0,255,255,255,255,255,255,0,255,255,255,255,255,255,0,255,255,255,255,255] -; AVX512DQ-SLOW-NEXT: vpandn %ymm7, %ymm9, %ymm7 -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm9 = zero,ymm4[13,u,u,u,u],zero,zero,ymm4[14,u,u,u,u],zero,zero,ymm4[15,u,u,u,u],zero,zero,ymm4[16,u,u,u,u],zero,zero,ymm4[17,u,u] -; AVX512DQ-SLOW-NEXT: vinserti64x4 $1, %ymm9, %zmm7, %zmm7 -; AVX512DQ-SLOW-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm7 -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm7 -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm0 = ymm6[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,29,u,27,u,u,u,u,30,u,28,u,u,u,u,31,u] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,3,2,3] -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm1 = ymm5[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm5[27],zero,zero,zero,zero,ymm5[30],zero,ymm5[28],zero,zero,zero,zero,ymm5[31],zero,ymm5[29] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,3,2,3] -; AVX512DQ-SLOW-NEXT: vpternlogq $248, %ymm16, %ymm0, %ymm1 -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm0 = ymm4[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,28,29,26,27,28,29,30,31,30,31,28,29,28,29,30,31] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,3,2,3] -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0 -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm1 = ymm3[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,27,u,u,u,u,30,u,28,u,u,u,u,31,u,29,u] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,3,2,3] -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm2 = ymm2[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm2[30],zero,ymm2[28],zero,zero,zero,zero,ymm2[31],zero,ymm2[29],zero,zero -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm2 = ymm2[2,3,2,3] -; AVX512DQ-SLOW-NEXT: vpternlogq $248, %ymm17, %ymm1, %ymm2 -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm19, %ymm1 -; AVX512DQ-SLOW-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,ymm1[30],zero,ymm1[28],zero,zero,zero,zero,ymm1[31],zero,ymm1[29],zero,zero,zero -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,3,2,3] -; AVX512DQ-SLOW-NEXT: vmovdqa64 %ymm18, %ymm3 -; AVX512DQ-SLOW-NEXT: vpshufhw {{.*#+}} ymm3 = ymm3[0,1,2,3,6,7,7,6,8,9,10,11,14,15,15,14] -; AVX512DQ-SLOW-NEXT: vpshufd {{.*#+}} ymm3 = ymm3[2,2,3,3,6,6,7,7] -; AVX512DQ-SLOW-NEXT: vpermq {{.*#+}} ymm3 = ymm3[2,3,2,3] -; AVX512DQ-SLOW-NEXT: vpternlogq $236, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm3 -; AVX512DQ-SLOW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm3 -; AVX512DQ-SLOW-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm3 -; AVX512DQ-SLOW-NEXT: vmovdqa %ymm3, 192(%rax) -; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm10, (%rax) -; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm8, 128(%rax) -; AVX512DQ-SLOW-NEXT: vmovdqa64 %zmm7, 64(%rax) -; AVX512DQ-SLOW-NEXT: vzeroupper -; AVX512DQ-SLOW-NEXT: retq -; ; AVX512BW-SLOW-LABEL: store_i8_stride7_vf32: ; AVX512BW-SLOW: # %bb.0: ; AVX512BW-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %rax @@ -7817,1193 +7662,756 @@ define void @store_i8_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec ; AVX512F-SLOW-NEXT: vzeroupper ; AVX512F-SLOW-NEXT: retq ; -; AVX512F-ONLY-FAST-LABEL: store_i8_stride7_vf64: -; AVX512F-ONLY-FAST: # %bb.0: -; AVX512F-ONLY-FAST-NEXT: subq $1256, %rsp # imm = 0x4E8 -; AVX512F-ONLY-FAST-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%rcx), %ymm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%rdx), %ymm1 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm1[30],zero,ymm1[28],zero,zero,zero,zero,ymm1[31],zero,ymm1[29],zero,zero -; AVX512F-ONLY-FAST-NEXT: vmovdqa %ymm1, %ymm14 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm2[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm2[25],zero,ymm2[23],zero,zero,zero,zero,ymm2[26],zero,ymm2[24],zero,zero,zero,zero -; AVX512F-ONLY-FAST-NEXT: vmovdqa %ymm2, %ymm13 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%rsi), %ymm1 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%rdi), %ymm2 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,ymm1[30],zero,ymm1[28],zero,zero,zero,zero,ymm1[31],zero,ymm1[29],zero,zero,zero -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm1, %ymm16 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm2[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm2[23],zero,zero,zero,zero,ymm2[26],zero,ymm2[24],zero,zero,zero,zero,ymm2[27],zero,ymm2[25] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm2, %ymm17 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%r9), %ymm4 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%r8), %ymm1 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm1[27],zero,zero,zero,zero,ymm1[30],zero,ymm1[28],zero,zero,zero,zero,ymm1[31],zero,ymm1[29] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm1, %ymm18 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm4[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm4[25],zero,ymm4[23],zero,zero,zero,zero,ymm4[26],zero,ymm4[24],zero,zero -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm4, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%rax), %ymm1 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,28,29,26,27,28,29,30,31,30,31,28,29,28,29,30,31] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,22,23,26,27,24,25,22,23,24,25,26,27,26,27,24,25] -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rsi), %ymm1 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm0 = zero,zero,zero,ymm1[14],zero,zero,zero,zero,zero,zero,ymm1[15],zero,zero,zero,zero,zero,zero,ymm1[16],zero,zero,zero,zero,zero,zero,ymm1[17],zero,zero,zero,zero,zero,zero,ymm1[18] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm1, %ymm23 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rdi), %ymm1 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[0,1,14],zero,ymm1[12,13,0,1,14,15],zero,ymm1[3,12,13,2,3,16],zero,ymm1[30,31,28,29,16,17],zero,ymm1[31,18,19,28,29,18],zero -; AVX512F-ONLY-FAST-NEXT: vpor %ymm0, %ymm1, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rcx), %ymm1 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm7 = [128,128,128,128,128,14,128,128,128,128,128,128,15,128,128,128,128,128,128,16,128,128,128,128,128,128,17,128,128,128,128,128] -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm7, %ymm1, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm1, %ymm26 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rdx), %ymm1 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,0,1,14,128,14,15,0,1,14,15,128,13,14,15,16,17,16,128,30,31,30,31,16,17,128,31,28,29,30,31] -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm2, %ymm1, %ymm3 -; AVX512F-ONLY-FAST-NEXT: vpor %ymm0, %ymm3, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%r8), %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm5 = [128,128,128,128,128,128,14,128,128,128,128,128,128,15,128,128,128,128,128,128,16,128,128,128,128,128,128,17,128,128,128,128] -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm5, %ymm0, %ymm3 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm5, %ymm25 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%r9), %ymm5 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm5, (%rsp) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm0 = [13,0,0,0,128,16,128,14,0,0,0,128,17,128,15,0,13,0,0,0,128,16,128,14,0,0,0,128,17,128,15,0] -; AVX512F-ONLY-FAST-NEXT: # ymm0 = mem[0,1,0,1] -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm0, %ymm5, %ymm5 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm0, %ymm30 -; AVX512F-ONLY-FAST-NEXT: vporq %ymm3, %ymm5, %ymm24 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%rdx), %xmm3 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%rcx), %xmm6 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} xmm8 = -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm8, %xmm6, %xmm5 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %xmm6, %xmm28 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} xmm9 = -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm9, %xmm3, %xmm6 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %xmm9, %xmm19 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %xmm3, %xmm29 -; AVX512F-ONLY-FAST-NEXT: vpor %xmm5, %xmm6, %xmm3 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%rdi), %xmm10 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%rsi), %xmm6 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} xmm11 = -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm11, %xmm6, %xmm5 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} xmm3 = -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm3, %xmm10, %xmm9 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %xmm10, %xmm27 -; AVX512F-ONLY-FAST-NEXT: vpor %xmm5, %xmm9, %xmm5 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%r9), %xmm15 -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%r8), %xmm10 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} xmm5 = <128,4,u,u,u,128,7,128,5,u,u,u,128,8,128,6> -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm5, %xmm15, %xmm9 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} xmm0 = <4,128,u,u,u,7,128,5,128,u,u,u,8,128,6,128> -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm0, %xmm10, %xmm12 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %xmm0, %xmm21 -; AVX512F-ONLY-FAST-NEXT: vporq %xmm9, %xmm12, %xmm22 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm7, %ymm13, %ymm7 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm13, %ymm20 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm2, %ymm14, %ymm2 -; AVX512F-ONLY-FAST-NEXT: vpor %ymm7, %ymm2, %ymm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm16, %ymm7 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm2 = zero,zero,zero,ymm7[14],zero,zero,zero,zero,zero,zero,ymm7[15],zero,zero,zero,zero,zero,zero,ymm7[16],zero,zero,zero,zero,zero,zero,ymm7[17],zero,zero,zero,zero,zero,zero,ymm7[18] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm17, %ymm7 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm7 = ymm7[0,1,14],zero,ymm7[12,13,0,1,14,15],zero,ymm7[3,12,13,2,3,16],zero,ymm7[30,31,28,29,16,17],zero,ymm7[31,18,19,28,29,18],zero -; AVX512F-ONLY-FAST-NEXT: vpor %ymm2, %ymm7, %ymm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm18, %ymm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %ymm18, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm25, %ymm7 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm7, %ymm2, %ymm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm30, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm0, %ymm4, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vpor %ymm2, %ymm0, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rsi), %xmm13 -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm11, %xmm13, %xmm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rdi), %xmm9 -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm3, %xmm9, %xmm2 -; AVX512F-ONLY-FAST-NEXT: vporq %xmm0, %xmm2, %xmm31 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rcx), %xmm14 -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm8, %xmm14, %xmm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rdx), %xmm8 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %xmm19, %xmm2 -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm2, %xmm8, %xmm2 -; AVX512F-ONLY-FAST-NEXT: vpor %xmm0, %xmm2, %xmm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%r9), %xmm2 -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm5, %xmm2, %xmm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa %xmm2, %xmm3 -; AVX512F-ONLY-FAST-NEXT: vmovdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%r8), %xmm4 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %xmm21, %xmm2 -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm2, %xmm4, %xmm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqa %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpor %xmm0, %xmm2, %xmm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm0[23],zero,zero,zero,zero,ymm0[26],zero,ymm0[24],zero,zero,zero,zero,ymm0[27],zero,ymm0[25] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm23, %ymm12 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm12[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm12[21],zero,ymm12[19],zero,zero,zero,zero,ymm12[22],zero,ymm12[20],zero,zero -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm2, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm26, %ymm11 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm11[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm11[25],zero,ymm11[23],zero,zero,zero,zero,ymm11[26],zero,ymm11[24],zero,zero,zero,zero -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm11[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm11[18],zero,zero,zero,zero,ymm11[21],zero,ymm11[19],zero,zero,zero,zero,ymm11[22],zero,ymm11[20] -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm2, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [24,25,128,23,128,21,22,23,26,128,24,128,28,29,26,27,24,25,128,23,128,21,22,23,26,128,24,128,28,29,26,27] -; AVX512F-ONLY-FAST-NEXT: # ymm2 = mem[0,1,0,1] -; AVX512F-ONLY-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm5 = [18,128,18,19,20,21,128,19,128,25,26,27,22,128,20,128,18,128,18,19,20,21,128,19,128,25,26,27,22,128,20,128] -; AVX512F-ONLY-FAST-NEXT: # ymm5 = mem[0,1,0,1] -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm2, %ymm1, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm2, %ymm19 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm5, %ymm1, %ymm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm5, %ymm30 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm2, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm24, %zmm0, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm4[8],xmm3[8],xmm4[9],xmm3[9],xmm4[10],xmm3[10],xmm4[11],xmm3[11],xmm4[12],xmm3[12],xmm4[13],xmm3[13],xmm4[14],xmm3[14],xmm4[15],xmm3[15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} xmm3 = -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm3, %xmm2, %xmm2 -; AVX512F-ONLY-FAST-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm2[0,1,0,1],zmm0[4,5,6,7] -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [2,2,3,3,2,2,3,3] -; AVX512F-ONLY-FAST-NEXT: # ymm2 = mem[0,1,0,1] -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rax), %xmm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,5,6] -; AVX512F-ONLY-FAST-NEXT: vpermd %ymm0, %ymm2, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa (%rax), %ymm4 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm4, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm5 = [128,13,128,128,128,128,128,128,14,128,128,128,128,128,128,15,128,128,128,128,128,128,16,128,128,128,128,128,128,17,128,128] -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm5, %ymm4, %ymm4 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm5, %ymm18 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm4, %zmm0, %zmm24 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm1[30],zero,ymm1[28],zero,zero,zero,zero,ymm1[31],zero,ymm1[29],zero,zero -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm0, %ymm23 -; AVX512F-ONLY-FAST-NEXT: vpbroadcastq {{.*#+}} ymm1 = [13,12,11,0,0,0,15,14,13,12,11,0,0,0,15,14,13,12,11,0,0,0,15,14,13,12,11,0,0,0,15,14] -; AVX512F-ONLY-FAST-NEXT: vmovdqu (%rsp), %ymm0 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm1, %ymm0, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm1, %ymm25 -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,3,2,3] -; AVX512F-ONLY-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm1[27],zero,zero,zero,zero,ymm1[30],zero,ymm1[28],zero,zero,zero,zero,ymm1[31],zero,ymm1[29] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,3,2,3] -; AVX512F-ONLY-FAST-NEXT: vbroadcasti32x4 {{.*#+}} ymm26 = [18374967954648269055,71777218572844800,18374967954648269055,71777218572844800] -; AVX512F-ONLY-FAST-NEXT: # ymm26 = mem[0,1,2,3,0,1,2,3] -; AVX512F-ONLY-FAST-NEXT: vpternlogq $248, %ymm26, %ymm0, %ymm1 -; AVX512F-ONLY-FAST-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm10[0],xmm15[0],xmm10[1],xmm15[1],xmm10[2],xmm15[2],xmm10[3],xmm15[3],xmm10[4],xmm15[4],xmm10[5],xmm15[5],xmm10[6],xmm15[6],xmm10[7],xmm15[7] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[u,u,4,5,0,1,u,u,u,6,7,2,3,u,u,u] -; AVX512F-ONLY-FAST-NEXT: vshufi64x2 {{.*#+}} zmm21 = zmm1[0,1,2,3],zmm0[0,1,0,1] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %xmm29, %xmm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %xmm28, %xmm1 -; AVX512F-ONLY-FAST-NEXT: vpunpcklbw {{.*#+}} xmm7 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] -; AVX512F-ONLY-FAST-NEXT: vpunpckhbw {{.*#+}} xmm0 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15] -; AVX512F-ONLY-FAST-NEXT: vpunpckhbw {{.*#+}} xmm1 = xmm14[8],xmm8[8],xmm14[9],xmm8[9],xmm14[10],xmm8[10],xmm14[11],xmm8[11],xmm14[12],xmm8[12],xmm14[13],xmm8[13],xmm14[14],xmm8[14],xmm14[15],xmm8[15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} xmm4 = <6,3,2,u,u,u,9,8,5,4,u,u,u,11,10,7> -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm4, %xmm1, %xmm1 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm4, %xmm0, %xmm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512F-ONLY-FAST-NEXT: vinserti32x4 $2, %xmm0, %zmm1, %zmm28 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %xmm27, %xmm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa %xmm6, %xmm1 -; AVX512F-ONLY-FAST-NEXT: vpunpcklbw {{.*#+}} xmm6 = xmm0[0],xmm6[0],xmm0[1],xmm6[1],xmm0[2],xmm6[2],xmm0[3],xmm6[3],xmm0[4],xmm6[4],xmm0[5],xmm6[5],xmm0[6],xmm6[6],xmm0[7],xmm6[7] -; AVX512F-ONLY-FAST-NEXT: vpunpckhbw {{.*#+}} xmm1 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15] -; AVX512F-ONLY-FAST-NEXT: vpunpckhbw {{.*#+}} xmm4 = xmm13[8],xmm9[8],xmm13[9],xmm9[9],xmm13[10],xmm9[10],xmm13[11],xmm9[11],xmm13[12],xmm9[12],xmm13[13],xmm9[13],xmm13[14],xmm9[14],xmm13[15],xmm9[15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} xmm5 = <2,u,u,u,9,8,5,4,u,u,u,11,10,7,6,u> -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm5, %xmm4, %xmm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm5, %xmm1, %xmm1 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-FAST-NEXT: vinserti32x4 $2, %xmm1, %zmm0, %zmm27 -; AVX512F-ONLY-FAST-NEXT: vpunpckhbw {{.*#+}} xmm1 = xmm10[8],xmm15[8],xmm10[9],xmm15[9],xmm10[10],xmm15[10],xmm10[11],xmm15[11],xmm10[12],xmm15[12],xmm10[13],xmm15[13],xmm10[14],xmm15[14],xmm10[15],xmm15[15] -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm3, %xmm1, %xmm1 -; AVX512F-ONLY-FAST-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm22[0,1,0,1],zmm1[0,1,0,1] -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-FAST-NEXT: vmovdqa 32(%rax), %xmm0 -; AVX512F-ONLY-FAST-NEXT: vpshufhw {{.*#+}} xmm1 = xmm0[0,1,2,3,4,5,5,6] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %xmm0, %xmm29 -; AVX512F-ONLY-FAST-NEXT: vpermd %ymm1, %ymm2, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpbroadcastq {{.*#+}} ymm1 = [11,0,0,0,15,14,13,12,11,0,0,0,15,14,13,12,11,0,0,0,15,14,13,12,11,0,0,0,15,14,13,12] -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm1, %ymm11, %ymm5 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm20, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm1, %ymm0, %ymm1 -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm22 = ymm1[2,3,2,3] -; AVX512F-ONLY-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm2 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm19, %ymm1 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm1, %ymm2, %ymm1 -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm20 = ymm1[2,3,2,3] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm10 = ymm0[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm0[18],zero,zero,zero,zero,ymm0[21],zero,ymm0[19],zero,zero,zero,zero,ymm0[22],zero,ymm0[20] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm30, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm0, %ymm2, %ymm4 -; AVX512F-ONLY-FAST-NEXT: vpbroadcastq {{.*#+}} ymm2 = [9,8,7,0,0,0,11,10,9,8,7,0,0,0,11,10,9,8,7,0,0,0,11,10,9,8,7,0,0,0,11,10] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm16, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm2, %ymm0, %ymm1 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm2, %ymm30 -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm19 = ymm1[2,3,2,3] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm11 = ymm0[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm0[21],zero,ymm0[19],zero,zero,zero,zero,ymm0[22],zero,ymm0[20],zero,zero -; AVX512F-ONLY-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm18, %ymm1 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm1, %ymm0, %ymm3 -; AVX512F-ONLY-FAST-NEXT: vpshuflw {{.*#+}} ymm0 = ymm0[2,1,1,2,4,5,6,7,10,9,9,10,12,13,14,15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm1 = [4,5,4,5,5,7,4,5] -; AVX512F-ONLY-FAST-NEXT: vpermd %ymm0, %ymm1, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm3, %zmm16 -; AVX512F-ONLY-FAST-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm9[0],xmm13[0],xmm9[1],xmm13[1],xmm9[2],xmm13[2],xmm9[3],xmm13[3],xmm9[4],xmm13[4],xmm9[5],xmm13[5],xmm9[6],xmm13[6],xmm9[7],xmm13[7] -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} xmm9 = <0,1,u,u,u,6,7,2,3,u,u,u,8,9,4,5> -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm9, %xmm6, %xmm6 -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm9, %xmm0, %xmm0 -; AVX512F-ONLY-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm9 = [28,29,30,128,28,128,30,31,30,31,128,29,128,31,28,29,28,29,30,128,28,128,30,31,30,31,128,29,128,31,28,29] -; AVX512F-ONLY-FAST-NEXT: # ymm9 = mem[0,1,0,1] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm17, %ymm3 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm9, %ymm3, %ymm15 -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm17 = ymm15[2,3,2,3] -; AVX512F-ONLY-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm25, %ymm2 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm2, %ymm1, %ymm13 -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm18 = ymm13[2,3,2,3] -; AVX512F-ONLY-FAST-NEXT: vinserti32x4 $2, %xmm31, %zmm0, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512F-ONLY-FAST-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm8[0],xmm14[0],xmm8[1],xmm14[1],xmm8[2],xmm14[2],xmm8[3],xmm14[3],xmm8[4],xmm14[4],xmm8[5],xmm14[5],xmm8[6],xmm14[6],xmm8[7],xmm14[7] -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} xmm8 = <4,5,0,1,u,u,u,6,7,2,3,u,u,u,8,9> -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm8, %xmm7, %xmm7 -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm8, %xmm0, %xmm13 -; AVX512F-ONLY-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm8 = ymm0[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,24,25,24,25],zero,ymm0[23],zero,ymm0[23,24,25,26],zero,ymm0[24],zero,ymm0[30,31] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm0, %ymm25 -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm15 = ymm8[2,3,2,3] -; AVX512F-ONLY-FAST-NEXT: vmovdqa %ymm12, %ymm1 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm12 = ymm12[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,ymm12[30],zero,ymm12[28],zero,zero,zero,zero,ymm12[31],zero,ymm12[29],zero,zero,zero -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm12 = ymm12[2,3,2,3] -; AVX512F-ONLY-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm2 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm9, %ymm2, %ymm9 -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm9 = ymm9[2,3,2,3] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm6 = ymm6[0,1,0,1] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm5 = ymm5[2,3,2,3] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm0 = ymm23[2,3,2,3] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm7 = ymm7[0,1,0,1] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm10 = ymm10[2,3,2,3] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm4 = ymm4[2,3,2,3] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm8 = ymm11[2,3,2,3] -; AVX512F-ONLY-FAST-NEXT: vinserti32x4 $2, {{[-0-9]+}}(%r{{[sb]}}p), %zmm13, %zmm31 # 16-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm11 = [18,19,20,21,128,19,128,21,20,21,22,128,20,128,22,23,18,19,20,21,128,19,128,21,20,21,22,128,20,128,22,23] -; AVX512F-ONLY-FAST-NEXT: # ymm11 = mem[0,1,0,1] -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm11, %ymm3, %ymm14 -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm14 = ymm14[2,3,2,3] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm30, %ymm3 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm3, %ymm1, %ymm13 -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm13 = ymm13[2,3,2,3] -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm11, %ymm2, %ymm1 -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,3,2,3] -; AVX512F-ONLY-FAST-NEXT: vpor %ymm12, %ymm9, %ymm9 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm6, %zmm9, %zmm6 -; AVX512F-ONLY-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm9 = [18374966859431673855,18446463693966278655,18374966859431673855,18446463693966278655] -; AVX512F-ONLY-FAST-NEXT: # ymm9 = mem[0,1,0,1] -; AVX512F-ONLY-FAST-NEXT: vpternlogq $248, %ymm9, %ymm5, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm7, %zmm0, %zmm7 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm0 = [255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255] -; AVX512F-ONLY-FAST-NEXT: vpternlogq $226, %zmm6, %zmm0, %zmm7 -; AVX512F-ONLY-FAST-NEXT: vpor %ymm4, %ymm10, %ymm4 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm4, %zmm2, %zmm4 -; AVX512F-ONLY-FAST-NEXT: vpor %ymm8, %ymm14, %ymm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm5 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $226, %zmm4, %zmm0, %zmm5 -; AVX512F-ONLY-FAST-NEXT: vpandq %ymm9, %ymm22, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm20, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vpermq $238, {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: # zmm2 = mem[2,3,2,3,6,7,6,7] -; AVX512F-ONLY-FAST-NEXT: vporq %zmm2, %zmm0, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vpandq %ymm26, %ymm19, %ymm2 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm17, %zmm2, %zmm2 -; AVX512F-ONLY-FAST-NEXT: vpermq $238, {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: # zmm4 = mem[2,3,2,3,6,7,6,7] -; AVX512F-ONLY-FAST-NEXT: vporq %zmm4, %zmm2, %zmm2 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm2 -; AVX512F-ONLY-FAST-NEXT: vpandq %ymm26, %ymm18, %ymm0 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm15, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vpermq $238, {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: # zmm4 = mem[2,3,2,3,6,7,6,7] -; AVX512F-ONLY-FAST-NEXT: vporq %zmm4, %zmm0, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 {{.*#+}} zmm4 = [255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255] -; AVX512F-ONLY-FAST-NEXT: vpternlogq $184, %zmm2, %zmm4, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} zmm2 = zmm28[0,1,0,1,4,5,4,5] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} zmm8 = zmm27[0,1,0,1,4,5,4,5] -; AVX512F-ONLY-FAST-NEXT: vpternlogq $226, %zmm2, %zmm4, %zmm8 -; AVX512F-ONLY-FAST-NEXT: vpandq %ymm26, %ymm13, %ymm2 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1 -; AVX512F-ONLY-FAST-NEXT: vpermq $238, {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: # zmm2 = mem[2,3,2,3,6,7,6,7] -; AVX512F-ONLY-FAST-NEXT: vporq %zmm2, %zmm1, %zmm1 -; AVX512F-ONLY-FAST-NEXT: vpermq $238, {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: # zmm2 = mem[2,3,2,3,6,7,6,7] -; AVX512F-ONLY-FAST-NEXT: vpermq $238, {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: # zmm6 = mem[2,3,2,3,6,7,6,7] -; AVX512F-ONLY-FAST-NEXT: vporq %zmm2, %zmm6, %zmm9 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $226, %zmm1, %zmm4, %zmm9 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpunpcklbw {{[-0-9]+}}(%r{{[sb]}}p), %xmm1, %xmm1 # 16-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1],xmm1[2],mem[2],xmm1[3],mem[3],xmm1[4],mem[4],xmm1[5],mem[5],xmm1[6],mem[6],xmm1[7],mem[7] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[u,u,4,5,0,1,u,u,u,6,7,2,3,u,u,u] -; AVX512F-ONLY-FAST-NEXT: vshufi64x2 $0, {{[-0-9]+}}(%r{{[sb]}}p), %zmm1, %zmm18 # 64-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: # zmm18 = zmm1[0,1,0,1],mem[0,1,0,1] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %xmm29, %xmm3 -; AVX512F-ONLY-FAST-NEXT: vpshuflw {{.*#+}} xmm2 = xmm3[1,1,0,0,4,5,6,7] -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,0,1,2,0,0,1] -; AVX512F-ONLY-FAST-NEXT: vpermd %ymm2, %ymm4, %ymm19 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpshuflw {{.*#+}} xmm6 = xmm1[1,1,0,0,4,5,6,7] -; AVX512F-ONLY-FAST-NEXT: vpermd %ymm6, %ymm4, %ymm17 -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} xmm6 = [4,5,4,5,4,5,8,9,6,7,6,7,6,7,6,7] -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm6, %xmm3, %xmm10 -; AVX512F-ONLY-FAST-NEXT: vpshufb %xmm6, %xmm1, %xmm6 -; AVX512F-ONLY-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm11 = [128,20,128,18,128,128,128,128,21,128,19,128,128,128,128,22,128,20,128,18,128,128,128,128,21,128,19,128,128,128,128,22] -; AVX512F-ONLY-FAST-NEXT: # ymm11 = mem[0,1,0,1] -; AVX512F-ONLY-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm11, %ymm1, %ymm12 -; AVX512F-ONLY-FAST-NEXT: vmovdqu (%rsp), %ymm1 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm13 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm1[25],zero,ymm1[23],zero,zero,zero,zero,ymm1[26],zero,ymm1[24],zero,zero -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm11, %ymm1, %ymm11 -; AVX512F-ONLY-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm14 = [20,128,18,128,20,21,20,21,128,19,128,19,20,21,22,128,20,128,18,128,20,21,20,21,128,19,128,19,20,21,22,128] -; AVX512F-ONLY-FAST-NEXT: # ymm14 = mem[0,1,0,1] -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %ymm25, %ymm1 -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm14, %ymm1, %ymm15 -; AVX512F-ONLY-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm2 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm2[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,24,25,24,25],zero,ymm2[23],zero,ymm2[23,24,25,26],zero,ymm2[24],zero,ymm2[30,31] -; AVX512F-ONLY-FAST-NEXT: vpshufb %ymm14, %ymm2, %ymm14 -; AVX512F-ONLY-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm3 # 32-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpshuflw {{.*#+}} ymm4 = ymm3[2,1,1,2,4,5,6,7,10,9,9,10,12,13,14,15] -; AVX512F-ONLY-FAST-NEXT: vmovdqa {{.*#+}} ymm2 = [4,5,4,5,5,7,4,5] -; AVX512F-ONLY-FAST-NEXT: vpermd %ymm4, %ymm2, %ymm20 -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm3[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,28,29,26,27,28,29,30,31,30,31,28,29,28,29,30,31] -; AVX512F-ONLY-FAST-NEXT: vpshufb {{.*#+}} ymm4 = ymm3[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,22,23,26,27,24,25,22,23,24,25,26,27,26,27,24,25] -; AVX512F-ONLY-FAST-NEXT: vpermq $238, {{[-0-9]+}}(%r{{[sb]}}p), %zmm22 # 64-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: # zmm22 = mem[2,3,2,3,6,7,6,7] -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm22 -; AVX512F-ONLY-FAST-NEXT: vpermq $68, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: # ymm0 = mem[0,1,0,1] -; AVX512F-ONLY-FAST-NEXT: vpermq $68, {{[-0-9]+}}(%r{{[sb]}}p), %ymm23 # 32-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: # ymm23 = mem[0,1,0,1] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm2 = ymm2[2,3,2,3] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm10 = ymm10[0,0,1,0] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm12 = ymm12[2,3,2,3] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm15 = ymm15[2,3,2,3] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm6 = ymm6[0,0,1,0] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm13 = ymm13[2,3,2,3] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,3,2,3] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm11 = ymm11[2,3,2,3] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm14 = ymm14[2,3,2,3] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} ymm4 = ymm4[2,3,2,3] -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm0 # 32-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm23, %zmm23 # 32-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm23 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm24 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm23, %zmm24 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm19, %zmm2, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm21 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm7, %zmm21 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm10, %zmm0 # 32-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm8, %zmm0 -; AVX512F-ONLY-FAST-NEXT: vpor %ymm12, %ymm15, %ymm2 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm2 -; AVX512F-ONLY-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 # 64-byte Reload -; AVX512F-ONLY-FAST-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm7[0,1,2,3],zmm2[4,5,6,7] -; AVX512F-ONLY-FAST-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm16 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm5, %zmm16 -; AVX512F-ONLY-FAST-NEXT: vpermq $68, {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Folded Reload -; AVX512F-ONLY-FAST-NEXT: # zmm2 = mem[0,1,0,1,4,5,4,5] -; AVX512F-ONLY-FAST-NEXT: vpermq {{.*#+}} zmm5 = zmm31[0,1,0,1,4,5,4,5] -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm5 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm6, %zmm17, %zmm2 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm18, %zmm2 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm5, %zmm2 -; AVX512F-ONLY-FAST-NEXT: vpor %ymm1, %ymm13, %ymm1 -; AVX512F-ONLY-FAST-NEXT: vpor %ymm11, %ymm14, %ymm5 -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm1 -; AVX512F-ONLY-FAST-NEXT: vshufi64x2 {{.*#+}} zmm1 = zmm5[0,1,2,3],zmm1[4,5,6,7] -; AVX512F-ONLY-FAST-NEXT: vinserti64x4 $1, %ymm4, %zmm20, %zmm4 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm4 -; AVX512F-ONLY-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm4 -; AVX512F-ONLY-FAST-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm4, 128(%rax) -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm2, (%rax) -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm16, 320(%rax) -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm0, 256(%rax) -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm21, 192(%rax) -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm24, 64(%rax) -; AVX512F-ONLY-FAST-NEXT: vmovdqa64 %zmm22, 384(%rax) -; AVX512F-ONLY-FAST-NEXT: addq $1256, %rsp # imm = 0x4E8 -; AVX512F-ONLY-FAST-NEXT: vzeroupper -; AVX512F-ONLY-FAST-NEXT: retq -; -; AVX512DQ-FAST-LABEL: store_i8_stride7_vf64: -; AVX512DQ-FAST: # %bb.0: -; AVX512DQ-FAST-NEXT: subq $1256, %rsp # imm = 0x4E8 -; AVX512DQ-FAST-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQ-FAST-NEXT: vmovdqa 32(%rcx), %ymm2 -; AVX512DQ-FAST-NEXT: vmovdqa 32(%rdx), %ymm1 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm1[30],zero,ymm1[28],zero,zero,zero,zero,ymm1[31],zero,ymm1[29],zero,zero -; AVX512DQ-FAST-NEXT: vmovdqa %ymm1, %ymm14 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm2[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm2[25],zero,ymm2[23],zero,zero,zero,zero,ymm2[26],zero,ymm2[24],zero,zero,zero,zero -; AVX512DQ-FAST-NEXT: vmovdqa %ymm2, %ymm13 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 -; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa 32(%rsi), %ymm1 -; AVX512DQ-FAST-NEXT: vmovdqa 32(%rdi), %ymm2 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,ymm1[30],zero,ymm1[28],zero,zero,zero,zero,ymm1[31],zero,ymm1[29],zero,zero,zero -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm1, %ymm16 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm2[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm2[23],zero,zero,zero,zero,ymm2[26],zero,ymm2[24],zero,zero,zero,zero,ymm2[27],zero,ymm2[25] -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm2, %ymm17 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 -; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa 32(%r9), %ymm4 -; AVX512DQ-FAST-NEXT: vmovdqa 32(%r8), %ymm1 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm1[27],zero,zero,zero,zero,ymm1[30],zero,ymm1[28],zero,zero,zero,zero,ymm1[31],zero,ymm1[29] -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm1, %ymm18 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm4[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm4[25],zero,ymm4[23],zero,zero,zero,zero,ymm4[26],zero,ymm4[24],zero,zero -; AVX512DQ-FAST-NEXT: vmovdqu %ymm4, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 -; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa 32(%rax), %ymm1 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,28,29,26,27,28,29,30,31,30,31,28,29,28,29,30,31] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,22,23,26,27,24,25,22,23,24,25,26,27,26,27,24,25] -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 -; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa (%rsi), %ymm1 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm0 = zero,zero,zero,ymm1[14],zero,zero,zero,zero,zero,zero,ymm1[15],zero,zero,zero,zero,zero,zero,ymm1[16],zero,zero,zero,zero,zero,zero,ymm1[17],zero,zero,zero,zero,zero,zero,ymm1[18] -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm1, %ymm23 -; AVX512DQ-FAST-NEXT: vmovdqa (%rdi), %ymm1 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[0,1,14],zero,ymm1[12,13,0,1,14,15],zero,ymm1[3,12,13,2,3,16],zero,ymm1[30,31,28,29,16,17],zero,ymm1[31,18,19,28,29,18],zero -; AVX512DQ-FAST-NEXT: vpor %ymm0, %ymm1, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa (%rcx), %ymm1 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm7 = [128,128,128,128,128,14,128,128,128,128,128,128,15,128,128,128,128,128,128,16,128,128,128,128,128,128,17,128,128,128,128,128] -; AVX512DQ-FAST-NEXT: vpshufb %ymm7, %ymm1, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm1, %ymm26 -; AVX512DQ-FAST-NEXT: vmovdqa (%rdx), %ymm1 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,0,1,14,128,14,15,0,1,14,15,128,13,14,15,16,17,16,128,30,31,30,31,16,17,128,31,28,29,30,31] -; AVX512DQ-FAST-NEXT: vpshufb %ymm2, %ymm1, %ymm3 -; AVX512DQ-FAST-NEXT: vpor %ymm0, %ymm3, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa (%r8), %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm5 = [128,128,128,128,128,128,14,128,128,128,128,128,128,15,128,128,128,128,128,128,16,128,128,128,128,128,128,17,128,128,128,128] -; AVX512DQ-FAST-NEXT: vpshufb %ymm5, %ymm0, %ymm3 -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm5, %ymm25 -; AVX512DQ-FAST-NEXT: vmovdqa (%r9), %ymm5 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm5, (%rsp) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm0 = [13,0,0,0,128,16,128,14,0,0,0,128,17,128,15,0,13,0,0,0,128,16,128,14,0,0,0,128,17,128,15,0] -; AVX512DQ-FAST-NEXT: # ymm0 = mem[0,1,0,1] -; AVX512DQ-FAST-NEXT: vpshufb %ymm0, %ymm5, %ymm5 -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm0, %ymm30 -; AVX512DQ-FAST-NEXT: vporq %ymm3, %ymm5, %ymm24 -; AVX512DQ-FAST-NEXT: vmovdqa 32(%rdx), %xmm3 -; AVX512DQ-FAST-NEXT: vmovdqa 32(%rcx), %xmm6 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} xmm8 = -; AVX512DQ-FAST-NEXT: vpshufb %xmm8, %xmm6, %xmm5 -; AVX512DQ-FAST-NEXT: vmovdqa64 %xmm6, %xmm28 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} xmm9 = -; AVX512DQ-FAST-NEXT: vpshufb %xmm9, %xmm3, %xmm6 -; AVX512DQ-FAST-NEXT: vmovdqa64 %xmm9, %xmm19 -; AVX512DQ-FAST-NEXT: vmovdqa64 %xmm3, %xmm29 -; AVX512DQ-FAST-NEXT: vpor %xmm5, %xmm6, %xmm3 -; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa 32(%rdi), %xmm10 -; AVX512DQ-FAST-NEXT: vmovdqa 32(%rsi), %xmm6 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} xmm11 = -; AVX512DQ-FAST-NEXT: vpshufb %xmm11, %xmm6, %xmm5 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} xmm3 = -; AVX512DQ-FAST-NEXT: vpshufb %xmm3, %xmm10, %xmm9 -; AVX512DQ-FAST-NEXT: vmovdqa64 %xmm10, %xmm27 -; AVX512DQ-FAST-NEXT: vpor %xmm5, %xmm9, %xmm5 -; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa 32(%r9), %xmm15 -; AVX512DQ-FAST-NEXT: vmovdqa 32(%r8), %xmm10 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} xmm5 = <128,4,u,u,u,128,7,128,5,u,u,u,128,8,128,6> -; AVX512DQ-FAST-NEXT: vpshufb %xmm5, %xmm15, %xmm9 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} xmm0 = <4,128,u,u,u,7,128,5,128,u,u,u,8,128,6,128> -; AVX512DQ-FAST-NEXT: vpshufb %xmm0, %xmm10, %xmm12 -; AVX512DQ-FAST-NEXT: vmovdqa64 %xmm0, %xmm21 -; AVX512DQ-FAST-NEXT: vporq %xmm9, %xmm12, %xmm22 -; AVX512DQ-FAST-NEXT: vpshufb %ymm7, %ymm13, %ymm7 -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm13, %ymm20 -; AVX512DQ-FAST-NEXT: vpshufb %ymm2, %ymm14, %ymm2 -; AVX512DQ-FAST-NEXT: vpor %ymm7, %ymm2, %ymm2 -; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm16, %ymm7 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm2 = zero,zero,zero,ymm7[14],zero,zero,zero,zero,zero,zero,ymm7[15],zero,zero,zero,zero,zero,zero,ymm7[16],zero,zero,zero,zero,zero,zero,ymm7[17],zero,zero,zero,zero,zero,zero,ymm7[18] -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm17, %ymm7 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm7 = ymm7[0,1,14],zero,ymm7[12,13,0,1,14,15],zero,ymm7[3,12,13,2,3,16],zero,ymm7[30,31,28,29,16,17],zero,ymm7[31,18,19,28,29,18],zero -; AVX512DQ-FAST-NEXT: vpor %ymm2, %ymm7, %ymm2 -; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm18, %ymm2 -; AVX512DQ-FAST-NEXT: vmovdqu64 %ymm18, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm25, %ymm7 -; AVX512DQ-FAST-NEXT: vpshufb %ymm7, %ymm2, %ymm2 -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm30, %ymm0 -; AVX512DQ-FAST-NEXT: vpshufb %ymm0, %ymm4, %ymm0 -; AVX512DQ-FAST-NEXT: vpor %ymm2, %ymm0, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa (%rsi), %xmm13 -; AVX512DQ-FAST-NEXT: vpshufb %xmm11, %xmm13, %xmm0 -; AVX512DQ-FAST-NEXT: vmovdqa (%rdi), %xmm9 -; AVX512DQ-FAST-NEXT: vpshufb %xmm3, %xmm9, %xmm2 -; AVX512DQ-FAST-NEXT: vporq %xmm0, %xmm2, %xmm31 -; AVX512DQ-FAST-NEXT: vmovdqa (%rcx), %xmm14 -; AVX512DQ-FAST-NEXT: vpshufb %xmm8, %xmm14, %xmm0 -; AVX512DQ-FAST-NEXT: vmovdqa (%rdx), %xmm8 -; AVX512DQ-FAST-NEXT: vmovdqa64 %xmm19, %xmm2 -; AVX512DQ-FAST-NEXT: vpshufb %xmm2, %xmm8, %xmm2 -; AVX512DQ-FAST-NEXT: vpor %xmm0, %xmm2, %xmm0 -; AVX512DQ-FAST-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa (%r9), %xmm2 -; AVX512DQ-FAST-NEXT: vpshufb %xmm5, %xmm2, %xmm0 -; AVX512DQ-FAST-NEXT: vmovdqa %xmm2, %xmm3 -; AVX512DQ-FAST-NEXT: vmovdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa (%r8), %xmm4 -; AVX512DQ-FAST-NEXT: vmovdqa64 %xmm21, %xmm2 -; AVX512DQ-FAST-NEXT: vpshufb %xmm2, %xmm4, %xmm2 -; AVX512DQ-FAST-NEXT: vmovdqa %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512DQ-FAST-NEXT: vpor %xmm0, %xmm2, %xmm0 -; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm0[23],zero,zero,zero,zero,ymm0[26],zero,ymm0[24],zero,zero,zero,zero,ymm0[27],zero,ymm0[25] -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm23, %ymm12 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm12[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm12[21],zero,ymm12[19],zero,zero,zero,zero,ymm12[22],zero,ymm12[20],zero,zero -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm2, %zmm0 -; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm26, %ymm11 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm11[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm11[25],zero,ymm11[23],zero,zero,zero,zero,ymm11[26],zero,ymm11[24],zero,zero,zero,zero -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm11[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm11[18],zero,zero,zero,zero,ymm11[21],zero,ymm11[19],zero,zero,zero,zero,ymm11[22],zero,ymm11[20] -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm2, %zmm0 -; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [24,25,128,23,128,21,22,23,26,128,24,128,28,29,26,27,24,25,128,23,128,21,22,23,26,128,24,128,28,29,26,27] -; AVX512DQ-FAST-NEXT: # ymm2 = mem[0,1,0,1] -; AVX512DQ-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm5 = [18,128,18,19,20,21,128,19,128,25,26,27,22,128,20,128,18,128,18,19,20,21,128,19,128,25,26,27,22,128,20,128] -; AVX512DQ-FAST-NEXT: # ymm5 = mem[0,1,0,1] -; AVX512DQ-FAST-NEXT: vpshufb %ymm2, %ymm1, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm2, %ymm19 -; AVX512DQ-FAST-NEXT: vpshufb %ymm5, %ymm1, %ymm2 -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm5, %ymm30 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm2, %zmm0 -; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm24, %zmm0, %zmm0 -; AVX512DQ-FAST-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm4[8],xmm3[8],xmm4[9],xmm3[9],xmm4[10],xmm3[10],xmm4[11],xmm3[11],xmm4[12],xmm3[12],xmm4[13],xmm3[13],xmm4[14],xmm3[14],xmm4[15],xmm3[15] -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} xmm3 = -; AVX512DQ-FAST-NEXT: vpshufb %xmm3, %xmm2, %xmm2 -; AVX512DQ-FAST-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm2[0,1,0,1],zmm0[4,5,6,7] -; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [2,2,3,3,2,2,3,3] -; AVX512DQ-FAST-NEXT: # ymm2 = mem[0,1,0,1] -; AVX512DQ-FAST-NEXT: vmovdqa (%rax), %xmm0 -; AVX512DQ-FAST-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX512DQ-FAST-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,5,6] -; AVX512DQ-FAST-NEXT: vpermd %ymm0, %ymm2, %ymm0 -; AVX512DQ-FAST-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqa (%rax), %ymm4 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm4, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm5 = [128,13,128,128,128,128,128,128,14,128,128,128,128,128,128,15,128,128,128,128,128,128,16,128,128,128,128,128,128,17,128,128] -; AVX512DQ-FAST-NEXT: vpshufb %ymm5, %ymm4, %ymm4 -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm5, %ymm18 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm4, %zmm0, %zmm24 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm1[30],zero,ymm1[28],zero,zero,zero,zero,ymm1[31],zero,ymm1[29],zero,zero -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm0, %ymm23 -; AVX512DQ-FAST-NEXT: vpbroadcastq {{.*#+}} ymm1 = [13,12,11,0,0,0,15,14,13,12,11,0,0,0,15,14,13,12,11,0,0,0,15,14,13,12,11,0,0,0,15,14] -; AVX512DQ-FAST-NEXT: vmovdqu (%rsp), %ymm0 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vpshufb %ymm1, %ymm0, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm1, %ymm25 -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,3,2,3] -; AVX512DQ-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm1[27],zero,zero,zero,zero,ymm1[30],zero,ymm1[28],zero,zero,zero,zero,ymm1[31],zero,ymm1[29] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,3,2,3] -; AVX512DQ-FAST-NEXT: vbroadcasti64x2 {{.*#+}} ymm26 = [18374967954648269055,71777218572844800,18374967954648269055,71777218572844800] -; AVX512DQ-FAST-NEXT: # ymm26 = mem[0,1,0,1] -; AVX512DQ-FAST-NEXT: vpternlogq $248, %ymm26, %ymm0, %ymm1 -; AVX512DQ-FAST-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm10[0],xmm15[0],xmm10[1],xmm15[1],xmm10[2],xmm15[2],xmm10[3],xmm15[3],xmm10[4],xmm15[4],xmm10[5],xmm15[5],xmm10[6],xmm15[6],xmm10[7],xmm15[7] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[u,u,4,5,0,1,u,u,u,6,7,2,3,u,u,u] -; AVX512DQ-FAST-NEXT: vshufi64x2 {{.*#+}} zmm21 = zmm1[0,1,2,3],zmm0[0,1,0,1] -; AVX512DQ-FAST-NEXT: vmovdqa64 %xmm29, %xmm0 -; AVX512DQ-FAST-NEXT: vmovdqa64 %xmm28, %xmm1 -; AVX512DQ-FAST-NEXT: vpunpcklbw {{.*#+}} xmm7 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] -; AVX512DQ-FAST-NEXT: vpunpckhbw {{.*#+}} xmm0 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15] -; AVX512DQ-FAST-NEXT: vpunpckhbw {{.*#+}} xmm1 = xmm14[8],xmm8[8],xmm14[9],xmm8[9],xmm14[10],xmm8[10],xmm14[11],xmm8[11],xmm14[12],xmm8[12],xmm14[13],xmm8[13],xmm14[14],xmm8[14],xmm14[15],xmm8[15] -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} xmm4 = <6,3,2,u,u,u,9,8,5,4,u,u,u,11,10,7> -; AVX512DQ-FAST-NEXT: vpshufb %xmm4, %xmm1, %xmm1 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vpshufb %xmm4, %xmm0, %xmm0 -; AVX512DQ-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload -; AVX512DQ-FAST-NEXT: vinserti32x4 $2, %xmm0, %zmm1, %zmm28 -; AVX512DQ-FAST-NEXT: vmovdqa64 %xmm27, %xmm0 -; AVX512DQ-FAST-NEXT: vmovdqa %xmm6, %xmm1 -; AVX512DQ-FAST-NEXT: vpunpcklbw {{.*#+}} xmm6 = xmm0[0],xmm6[0],xmm0[1],xmm6[1],xmm0[2],xmm6[2],xmm0[3],xmm6[3],xmm0[4],xmm6[4],xmm0[5],xmm6[5],xmm0[6],xmm6[6],xmm0[7],xmm6[7] -; AVX512DQ-FAST-NEXT: vpunpckhbw {{.*#+}} xmm1 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15] -; AVX512DQ-FAST-NEXT: vpunpckhbw {{.*#+}} xmm4 = xmm13[8],xmm9[8],xmm13[9],xmm9[9],xmm13[10],xmm9[10],xmm13[11],xmm9[11],xmm13[12],xmm9[12],xmm13[13],xmm9[13],xmm13[14],xmm9[14],xmm13[15],xmm9[15] -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} xmm5 = <2,u,u,u,9,8,5,4,u,u,u,11,10,7,6,u> -; AVX512DQ-FAST-NEXT: vpshufb %xmm5, %xmm4, %xmm0 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vpshufb %xmm5, %xmm1, %xmm1 -; AVX512DQ-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-FAST-NEXT: vinserti32x4 $2, %xmm1, %zmm0, %zmm27 -; AVX512DQ-FAST-NEXT: vpunpckhbw {{.*#+}} xmm1 = xmm10[8],xmm15[8],xmm10[9],xmm15[9],xmm10[10],xmm15[10],xmm10[11],xmm15[11],xmm10[12],xmm15[12],xmm10[13],xmm15[13],xmm10[14],xmm15[14],xmm10[15],xmm15[15] -; AVX512DQ-FAST-NEXT: vpshufb %xmm3, %xmm1, %xmm1 -; AVX512DQ-FAST-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm22[0,1,0,1],zmm1[0,1,0,1] -; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vmovdqa 32(%rax), %xmm0 -; AVX512DQ-FAST-NEXT: vpshufhw {{.*#+}} xmm1 = xmm0[0,1,2,3,4,5,5,6] -; AVX512DQ-FAST-NEXT: vmovdqa64 %xmm0, %xmm29 -; AVX512DQ-FAST-NEXT: vpermd %ymm1, %ymm2, %ymm0 -; AVX512DQ-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill -; AVX512DQ-FAST-NEXT: vpbroadcastq {{.*#+}} ymm1 = [11,0,0,0,15,14,13,12,11,0,0,0,15,14,13,12,11,0,0,0,15,14,13,12,11,0,0,0,15,14,13,12] -; AVX512DQ-FAST-NEXT: vpshufb %ymm1, %ymm11, %ymm5 -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm20, %ymm0 -; AVX512DQ-FAST-NEXT: vpshufb %ymm1, %ymm0, %ymm1 -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm22 = ymm1[2,3,2,3] -; AVX512DQ-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm2 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm19, %ymm1 -; AVX512DQ-FAST-NEXT: vpshufb %ymm1, %ymm2, %ymm1 -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm20 = ymm1[2,3,2,3] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm10 = ymm0[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm0[18],zero,zero,zero,zero,ymm0[21],zero,ymm0[19],zero,zero,zero,zero,ymm0[22],zero,ymm0[20] -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm30, %ymm0 -; AVX512DQ-FAST-NEXT: vpshufb %ymm0, %ymm2, %ymm4 -; AVX512DQ-FAST-NEXT: vpbroadcastq {{.*#+}} ymm2 = [9,8,7,0,0,0,11,10,9,8,7,0,0,0,11,10,9,8,7,0,0,0,11,10,9,8,7,0,0,0,11,10] -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm16, %ymm0 -; AVX512DQ-FAST-NEXT: vpshufb %ymm2, %ymm0, %ymm1 -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm2, %ymm30 -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm19 = ymm1[2,3,2,3] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm11 = ymm0[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm0[21],zero,ymm0[19],zero,zero,zero,zero,ymm0[22],zero,ymm0[20],zero,zero -; AVX512DQ-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm18, %ymm1 -; AVX512DQ-FAST-NEXT: vpshufb %ymm1, %ymm0, %ymm3 -; AVX512DQ-FAST-NEXT: vpshuflw {{.*#+}} ymm0 = ymm0[2,1,1,2,4,5,6,7,10,9,9,10,12,13,14,15] -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm1 = [4,5,4,5,5,7,4,5] -; AVX512DQ-FAST-NEXT: vpermd %ymm0, %ymm1, %ymm0 -; AVX512DQ-FAST-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm3, %zmm16 -; AVX512DQ-FAST-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm9[0],xmm13[0],xmm9[1],xmm13[1],xmm9[2],xmm13[2],xmm9[3],xmm13[3],xmm9[4],xmm13[4],xmm9[5],xmm13[5],xmm9[6],xmm13[6],xmm9[7],xmm13[7] -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} xmm9 = <0,1,u,u,u,6,7,2,3,u,u,u,8,9,4,5> -; AVX512DQ-FAST-NEXT: vpshufb %xmm9, %xmm6, %xmm6 -; AVX512DQ-FAST-NEXT: vpshufb %xmm9, %xmm0, %xmm0 -; AVX512DQ-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm9 = [28,29,30,128,28,128,30,31,30,31,128,29,128,31,28,29,28,29,30,128,28,128,30,31,30,31,128,29,128,31,28,29] -; AVX512DQ-FAST-NEXT: # ymm9 = mem[0,1,0,1] -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm17, %ymm3 -; AVX512DQ-FAST-NEXT: vpshufb %ymm9, %ymm3, %ymm15 -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm17 = ymm15[2,3,2,3] -; AVX512DQ-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm25, %ymm2 -; AVX512DQ-FAST-NEXT: vpshufb %ymm2, %ymm1, %ymm13 -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm18 = ymm13[2,3,2,3] -; AVX512DQ-FAST-NEXT: vinserti32x4 $2, %xmm31, %zmm0, %zmm0 -; AVX512DQ-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill -; AVX512DQ-FAST-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm8[0],xmm14[0],xmm8[1],xmm14[1],xmm8[2],xmm14[2],xmm8[3],xmm14[3],xmm8[4],xmm14[4],xmm8[5],xmm14[5],xmm8[6],xmm14[6],xmm8[7],xmm14[7] -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} xmm8 = <4,5,0,1,u,u,u,6,7,2,3,u,u,u,8,9> -; AVX512DQ-FAST-NEXT: vpshufb %xmm8, %xmm7, %xmm7 -; AVX512DQ-FAST-NEXT: vpshufb %xmm8, %xmm0, %xmm13 -; AVX512DQ-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm8 = ymm0[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,24,25,24,25],zero,ymm0[23],zero,ymm0[23,24,25,26],zero,ymm0[24],zero,ymm0[30,31] -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm0, %ymm25 -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm15 = ymm8[2,3,2,3] -; AVX512DQ-FAST-NEXT: vmovdqa %ymm12, %ymm1 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm12 = ymm12[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,ymm12[30],zero,ymm12[28],zero,zero,zero,zero,ymm12[31],zero,ymm12[29],zero,zero,zero -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm12 = ymm12[2,3,2,3] -; AVX512DQ-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm2 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vpshufb %ymm9, %ymm2, %ymm9 -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm9 = ymm9[2,3,2,3] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm6 = ymm6[0,1,0,1] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm5 = ymm5[2,3,2,3] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm0 = ymm23[2,3,2,3] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm7 = ymm7[0,1,0,1] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm10 = ymm10[2,3,2,3] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm4 = ymm4[2,3,2,3] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm8 = ymm11[2,3,2,3] -; AVX512DQ-FAST-NEXT: vinserti32x4 $2, {{[-0-9]+}}(%r{{[sb]}}p), %zmm13, %zmm31 # 16-byte Folded Reload -; AVX512DQ-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm11 = [18,19,20,21,128,19,128,21,20,21,22,128,20,128,22,23,18,19,20,21,128,19,128,21,20,21,22,128,20,128,22,23] -; AVX512DQ-FAST-NEXT: # ymm11 = mem[0,1,0,1] -; AVX512DQ-FAST-NEXT: vpshufb %ymm11, %ymm3, %ymm14 -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm14 = ymm14[2,3,2,3] -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm30, %ymm3 -; AVX512DQ-FAST-NEXT: vpshufb %ymm3, %ymm1, %ymm13 -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm13 = ymm13[2,3,2,3] -; AVX512DQ-FAST-NEXT: vpshufb %ymm11, %ymm2, %ymm1 -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,3,2,3] -; AVX512DQ-FAST-NEXT: vpor %ymm12, %ymm9, %ymm9 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm6, %zmm9, %zmm6 -; AVX512DQ-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm9 = [18374966859431673855,18446463693966278655,18374966859431673855,18446463693966278655] -; AVX512DQ-FAST-NEXT: # ymm9 = mem[0,1,0,1] -; AVX512DQ-FAST-NEXT: vpternlogq $248, %ymm9, %ymm5, %ymm0 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm7, %zmm0, %zmm7 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm0 = [255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255] -; AVX512DQ-FAST-NEXT: vpternlogq $226, %zmm6, %zmm0, %zmm7 -; AVX512DQ-FAST-NEXT: vpor %ymm4, %ymm10, %ymm4 -; AVX512DQ-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm4, %zmm2, %zmm4 -; AVX512DQ-FAST-NEXT: vpor %ymm8, %ymm14, %ymm2 -; AVX512DQ-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm5 -; AVX512DQ-FAST-NEXT: vpternlogq $226, %zmm4, %zmm0, %zmm5 -; AVX512DQ-FAST-NEXT: vpandq %ymm9, %ymm22, %ymm0 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm20, %zmm0 -; AVX512DQ-FAST-NEXT: vpermq $238, {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Folded Reload -; AVX512DQ-FAST-NEXT: # zmm2 = mem[2,3,2,3,6,7,6,7] -; AVX512DQ-FAST-NEXT: vporq %zmm2, %zmm0, %zmm0 -; AVX512DQ-FAST-NEXT: vpandq %ymm26, %ymm19, %ymm2 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm17, %zmm2, %zmm2 -; AVX512DQ-FAST-NEXT: vpermq $238, {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Folded Reload -; AVX512DQ-FAST-NEXT: # zmm4 = mem[2,3,2,3,6,7,6,7] -; AVX512DQ-FAST-NEXT: vporq %zmm4, %zmm2, %zmm2 -; AVX512DQ-FAST-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm2 -; AVX512DQ-FAST-NEXT: vpandq %ymm26, %ymm18, %ymm0 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm15, %zmm0 -; AVX512DQ-FAST-NEXT: vpermq $238, {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Folded Reload -; AVX512DQ-FAST-NEXT: # zmm4 = mem[2,3,2,3,6,7,6,7] -; AVX512DQ-FAST-NEXT: vporq %zmm4, %zmm0, %zmm0 -; AVX512DQ-FAST-NEXT: vmovdqa64 {{.*#+}} zmm4 = [255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255] -; AVX512DQ-FAST-NEXT: vpternlogq $184, %zmm2, %zmm4, %zmm0 -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} zmm2 = zmm28[0,1,0,1,4,5,4,5] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} zmm8 = zmm27[0,1,0,1,4,5,4,5] -; AVX512DQ-FAST-NEXT: vpternlogq $226, %zmm2, %zmm4, %zmm8 -; AVX512DQ-FAST-NEXT: vpandq %ymm26, %ymm13, %ymm2 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1 -; AVX512DQ-FAST-NEXT: vpermq $238, {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Folded Reload -; AVX512DQ-FAST-NEXT: # zmm2 = mem[2,3,2,3,6,7,6,7] -; AVX512DQ-FAST-NEXT: vporq %zmm2, %zmm1, %zmm1 -; AVX512DQ-FAST-NEXT: vpermq $238, {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Folded Reload -; AVX512DQ-FAST-NEXT: # zmm2 = mem[2,3,2,3,6,7,6,7] -; AVX512DQ-FAST-NEXT: vpermq $238, {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Folded Reload -; AVX512DQ-FAST-NEXT: # zmm6 = mem[2,3,2,3,6,7,6,7] -; AVX512DQ-FAST-NEXT: vporq %zmm2, %zmm6, %zmm9 -; AVX512DQ-FAST-NEXT: vpternlogq $226, %zmm1, %zmm4, %zmm9 -; AVX512DQ-FAST-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload -; AVX512DQ-FAST-NEXT: vpunpcklbw {{[-0-9]+}}(%r{{[sb]}}p), %xmm1, %xmm1 # 16-byte Folded Reload -; AVX512DQ-FAST-NEXT: # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1],xmm1[2],mem[2],xmm1[3],mem[3],xmm1[4],mem[4],xmm1[5],mem[5],xmm1[6],mem[6],xmm1[7],mem[7] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[u,u,4,5,0,1,u,u,u,6,7,2,3,u,u,u] -; AVX512DQ-FAST-NEXT: vshufi64x2 $0, {{[-0-9]+}}(%r{{[sb]}}p), %zmm1, %zmm18 # 64-byte Folded Reload -; AVX512DQ-FAST-NEXT: # zmm18 = zmm1[0,1,0,1],mem[0,1,0,1] -; AVX512DQ-FAST-NEXT: vmovdqa64 %xmm29, %xmm3 -; AVX512DQ-FAST-NEXT: vpshuflw {{.*#+}} xmm2 = xmm3[1,1,0,0,4,5,6,7] -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,0,1,2,0,0,1] -; AVX512DQ-FAST-NEXT: vpermd %ymm2, %ymm4, %ymm19 -; AVX512DQ-FAST-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload -; AVX512DQ-FAST-NEXT: vpshuflw {{.*#+}} xmm6 = xmm1[1,1,0,0,4,5,6,7] -; AVX512DQ-FAST-NEXT: vpermd %ymm6, %ymm4, %ymm17 -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} xmm6 = [4,5,4,5,4,5,8,9,6,7,6,7,6,7,6,7] -; AVX512DQ-FAST-NEXT: vpshufb %xmm6, %xmm3, %xmm10 -; AVX512DQ-FAST-NEXT: vpshufb %xmm6, %xmm1, %xmm6 -; AVX512DQ-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm11 = [128,20,128,18,128,128,128,128,21,128,19,128,128,128,128,22,128,20,128,18,128,128,128,128,21,128,19,128,128,128,128,22] -; AVX512DQ-FAST-NEXT: # ymm11 = mem[0,1,0,1] -; AVX512DQ-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vpshufb %ymm11, %ymm1, %ymm12 -; AVX512DQ-FAST-NEXT: vmovdqu (%rsp), %ymm1 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm13 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm1[25],zero,ymm1[23],zero,zero,zero,zero,ymm1[26],zero,ymm1[24],zero,zero -; AVX512DQ-FAST-NEXT: vpshufb %ymm11, %ymm1, %ymm11 -; AVX512DQ-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm14 = [20,128,18,128,20,21,20,21,128,19,128,19,20,21,22,128,20,128,18,128,20,21,20,21,128,19,128,19,20,21,22,128] -; AVX512DQ-FAST-NEXT: # ymm14 = mem[0,1,0,1] -; AVX512DQ-FAST-NEXT: vmovdqa64 %ymm25, %ymm1 -; AVX512DQ-FAST-NEXT: vpshufb %ymm14, %ymm1, %ymm15 -; AVX512DQ-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm2 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm2[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,24,25,24,25],zero,ymm2[23],zero,ymm2[23,24,25,26],zero,ymm2[24],zero,ymm2[30,31] -; AVX512DQ-FAST-NEXT: vpshufb %ymm14, %ymm2, %ymm14 -; AVX512DQ-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm3 # 32-byte Reload -; AVX512DQ-FAST-NEXT: vpshuflw {{.*#+}} ymm4 = ymm3[2,1,1,2,4,5,6,7,10,9,9,10,12,13,14,15] -; AVX512DQ-FAST-NEXT: vmovdqa {{.*#+}} ymm2 = [4,5,4,5,5,7,4,5] -; AVX512DQ-FAST-NEXT: vpermd %ymm4, %ymm2, %ymm20 -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm3[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,28,29,26,27,28,29,30,31,30,31,28,29,28,29,30,31] -; AVX512DQ-FAST-NEXT: vpshufb {{.*#+}} ymm4 = ymm3[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,22,23,26,27,24,25,22,23,24,25,26,27,26,27,24,25] -; AVX512DQ-FAST-NEXT: vpermq $238, {{[-0-9]+}}(%r{{[sb]}}p), %zmm22 # 64-byte Folded Reload -; AVX512DQ-FAST-NEXT: # zmm22 = mem[2,3,2,3,6,7,6,7] -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm22 -; AVX512DQ-FAST-NEXT: vpermq $68, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Folded Reload -; AVX512DQ-FAST-NEXT: # ymm0 = mem[0,1,0,1] -; AVX512DQ-FAST-NEXT: vpermq $68, {{[-0-9]+}}(%r{{[sb]}}p), %ymm23 # 32-byte Folded Reload -; AVX512DQ-FAST-NEXT: # ymm23 = mem[0,1,0,1] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm2 = ymm2[2,3,2,3] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm10 = ymm10[0,0,1,0] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm12 = ymm12[2,3,2,3] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm15 = ymm15[2,3,2,3] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm6 = ymm6[0,0,1,0] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm13 = ymm13[2,3,2,3] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,3,2,3] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm11 = ymm11[2,3,2,3] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm14 = ymm14[2,3,2,3] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} ymm4 = ymm4[2,3,2,3] -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm0 # 32-byte Folded Reload -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm23, %zmm23 # 32-byte Folded Reload -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm23 -; AVX512DQ-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload -; AVX512DQ-FAST-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm24 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm23, %zmm24 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm19, %zmm2, %zmm0 -; AVX512DQ-FAST-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm21 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm7, %zmm21 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm10, %zmm0 # 32-byte Folded Reload -; AVX512DQ-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm0 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm8, %zmm0 -; AVX512DQ-FAST-NEXT: vpor %ymm12, %ymm15, %ymm2 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm2 -; AVX512DQ-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 # 64-byte Reload -; AVX512DQ-FAST-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm7[0,1,2,3],zmm2[4,5,6,7] -; AVX512DQ-FAST-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm16 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm5, %zmm16 -; AVX512DQ-FAST-NEXT: vpermq $68, {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Folded Reload -; AVX512DQ-FAST-NEXT: # zmm2 = mem[0,1,0,1,4,5,4,5] -; AVX512DQ-FAST-NEXT: vpermq {{.*#+}} zmm5 = zmm31[0,1,0,1,4,5,4,5] -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm5 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm6, %zmm17, %zmm2 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm18, %zmm2 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm5, %zmm2 -; AVX512DQ-FAST-NEXT: vpor %ymm1, %ymm13, %ymm1 -; AVX512DQ-FAST-NEXT: vpor %ymm11, %ymm14, %ymm5 -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm1 -; AVX512DQ-FAST-NEXT: vshufi64x2 {{.*#+}} zmm1 = zmm5[0,1,2,3],zmm1[4,5,6,7] -; AVX512DQ-FAST-NEXT: vinserti64x4 $1, %ymm4, %zmm20, %zmm4 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm4 -; AVX512DQ-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm4 -; AVX512DQ-FAST-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm4, 128(%rax) -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm2, (%rax) -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm16, 320(%rax) -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm0, 256(%rax) -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm21, 192(%rax) -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm24, 64(%rax) -; AVX512DQ-FAST-NEXT: vmovdqa64 %zmm22, 384(%rax) -; AVX512DQ-FAST-NEXT: addq $1256, %rsp # imm = 0x4E8 -; AVX512DQ-FAST-NEXT: vzeroupper -; AVX512DQ-FAST-NEXT: retq +; AVX512F-FAST-LABEL: store_i8_stride7_vf64: +; AVX512F-FAST: # %bb.0: +; AVX512F-FAST-NEXT: subq $1256, %rsp # imm = 0x4E8 +; AVX512F-FAST-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512F-FAST-NEXT: vmovdqa 32(%rcx), %ymm2 +; AVX512F-FAST-NEXT: vmovdqa 32(%rdx), %ymm1 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm1[30],zero,ymm1[28],zero,zero,zero,zero,ymm1[31],zero,ymm1[29],zero,zero +; AVX512F-FAST-NEXT: vmovdqa %ymm1, %ymm14 +; AVX512F-FAST-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm2[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm2[25],zero,ymm2[23],zero,zero,zero,zero,ymm2[26],zero,ymm2[24],zero,zero,zero,zero +; AVX512F-FAST-NEXT: vmovdqa %ymm2, %ymm13 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 +; AVX512F-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-FAST-NEXT: vmovdqa 32(%rsi), %ymm1 +; AVX512F-FAST-NEXT: vmovdqa 32(%rdi), %ymm2 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,ymm1[30],zero,ymm1[28],zero,zero,zero,zero,ymm1[31],zero,ymm1[29],zero,zero,zero +; AVX512F-FAST-NEXT: vmovdqa64 %ymm1, %ymm16 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm2[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm2[23],zero,zero,zero,zero,ymm2[26],zero,ymm2[24],zero,zero,zero,zero,ymm2[27],zero,ymm2[25] +; AVX512F-FAST-NEXT: vmovdqa64 %ymm2, %ymm17 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 +; AVX512F-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-FAST-NEXT: vmovdqa 32(%r9), %ymm4 +; AVX512F-FAST-NEXT: vmovdqa 32(%r8), %ymm1 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm1[27],zero,zero,zero,zero,ymm1[30],zero,ymm1[28],zero,zero,zero,zero,ymm1[31],zero,ymm1[29] +; AVX512F-FAST-NEXT: vmovdqa64 %ymm1, %ymm18 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm4[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm4[25],zero,ymm4[23],zero,zero,zero,zero,ymm4[26],zero,ymm4[24],zero,zero +; AVX512F-FAST-NEXT: vmovdqu %ymm4, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 +; AVX512F-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-FAST-NEXT: vmovdqa 32(%rax), %ymm1 +; AVX512F-FAST-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,28,29,26,27,28,29,30,31,30,31,28,29,28,29,30,31] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,22,23,26,27,24,25,22,23,24,25,26,27,26,27,24,25] +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 +; AVX512F-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-FAST-NEXT: vmovdqa (%rsi), %ymm1 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm0 = zero,zero,zero,ymm1[14],zero,zero,zero,zero,zero,zero,ymm1[15],zero,zero,zero,zero,zero,zero,ymm1[16],zero,zero,zero,zero,zero,zero,ymm1[17],zero,zero,zero,zero,zero,zero,ymm1[18] +; AVX512F-FAST-NEXT: vmovdqa64 %ymm1, %ymm23 +; AVX512F-FAST-NEXT: vmovdqa (%rdi), %ymm1 +; AVX512F-FAST-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[0,1,14],zero,ymm1[12,13,0,1,14,15],zero,ymm1[3,12,13,2,3,16],zero,ymm1[30,31,28,29,16,17],zero,ymm1[31,18,19,28,29,18],zero +; AVX512F-FAST-NEXT: vpor %ymm0, %ymm1, %ymm0 +; AVX512F-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vmovdqa (%rcx), %ymm1 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm7 = [128,128,128,128,128,14,128,128,128,128,128,128,15,128,128,128,128,128,128,16,128,128,128,128,128,128,17,128,128,128,128,128] +; AVX512F-FAST-NEXT: vpshufb %ymm7, %ymm1, %ymm0 +; AVX512F-FAST-NEXT: vmovdqa64 %ymm1, %ymm26 +; AVX512F-FAST-NEXT: vmovdqa (%rdx), %ymm1 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,0,1,14,128,14,15,0,1,14,15,128,13,14,15,16,17,16,128,30,31,30,31,16,17,128,31,28,29,30,31] +; AVX512F-FAST-NEXT: vpshufb %ymm2, %ymm1, %ymm3 +; AVX512F-FAST-NEXT: vpor %ymm0, %ymm3, %ymm0 +; AVX512F-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vmovdqa (%r8), %ymm0 +; AVX512F-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm5 = [128,128,128,128,128,128,14,128,128,128,128,128,128,15,128,128,128,128,128,128,16,128,128,128,128,128,128,17,128,128,128,128] +; AVX512F-FAST-NEXT: vpshufb %ymm5, %ymm0, %ymm3 +; AVX512F-FAST-NEXT: vmovdqa64 %ymm5, %ymm25 +; AVX512F-FAST-NEXT: vmovdqa (%r9), %ymm5 +; AVX512F-FAST-NEXT: vmovdqu %ymm5, (%rsp) # 32-byte Spill +; AVX512F-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm0 = [13,0,0,0,128,16,128,14,0,0,0,128,17,128,15,0,13,0,0,0,128,16,128,14,0,0,0,128,17,128,15,0] +; AVX512F-FAST-NEXT: # ymm0 = mem[0,1,0,1] +; AVX512F-FAST-NEXT: vpshufb %ymm0, %ymm5, %ymm5 +; AVX512F-FAST-NEXT: vmovdqa64 %ymm0, %ymm30 +; AVX512F-FAST-NEXT: vporq %ymm3, %ymm5, %ymm24 +; AVX512F-FAST-NEXT: vmovdqa 32(%rdx), %xmm3 +; AVX512F-FAST-NEXT: vmovdqa 32(%rcx), %xmm6 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} xmm8 = +; AVX512F-FAST-NEXT: vpshufb %xmm8, %xmm6, %xmm5 +; AVX512F-FAST-NEXT: vmovdqa64 %xmm6, %xmm28 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} xmm9 = +; AVX512F-FAST-NEXT: vpshufb %xmm9, %xmm3, %xmm6 +; AVX512F-FAST-NEXT: vmovdqa64 %xmm9, %xmm19 +; AVX512F-FAST-NEXT: vmovdqa64 %xmm3, %xmm29 +; AVX512F-FAST-NEXT: vpor %xmm5, %xmm6, %xmm3 +; AVX512F-FAST-NEXT: vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-FAST-NEXT: vmovdqa 32(%rdi), %xmm10 +; AVX512F-FAST-NEXT: vmovdqa 32(%rsi), %xmm6 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} xmm11 = +; AVX512F-FAST-NEXT: vpshufb %xmm11, %xmm6, %xmm5 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} xmm3 = +; AVX512F-FAST-NEXT: vpshufb %xmm3, %xmm10, %xmm9 +; AVX512F-FAST-NEXT: vmovdqa64 %xmm10, %xmm27 +; AVX512F-FAST-NEXT: vpor %xmm5, %xmm9, %xmm5 +; AVX512F-FAST-NEXT: vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-FAST-NEXT: vmovdqa 32(%r9), %xmm15 +; AVX512F-FAST-NEXT: vmovdqa 32(%r8), %xmm10 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} xmm5 = <128,4,u,u,u,128,7,128,5,u,u,u,128,8,128,6> +; AVX512F-FAST-NEXT: vpshufb %xmm5, %xmm15, %xmm9 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} xmm0 = <4,128,u,u,u,7,128,5,128,u,u,u,8,128,6,128> +; AVX512F-FAST-NEXT: vpshufb %xmm0, %xmm10, %xmm12 +; AVX512F-FAST-NEXT: vmovdqa64 %xmm0, %xmm21 +; AVX512F-FAST-NEXT: vporq %xmm9, %xmm12, %xmm22 +; AVX512F-FAST-NEXT: vpshufb %ymm7, %ymm13, %ymm7 +; AVX512F-FAST-NEXT: vmovdqa64 %ymm13, %ymm20 +; AVX512F-FAST-NEXT: vpshufb %ymm2, %ymm14, %ymm2 +; AVX512F-FAST-NEXT: vpor %ymm7, %ymm2, %ymm2 +; AVX512F-FAST-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-FAST-NEXT: vmovdqa64 %ymm16, %ymm7 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm2 = zero,zero,zero,ymm7[14],zero,zero,zero,zero,zero,zero,ymm7[15],zero,zero,zero,zero,zero,zero,ymm7[16],zero,zero,zero,zero,zero,zero,ymm7[17],zero,zero,zero,zero,zero,zero,ymm7[18] +; AVX512F-FAST-NEXT: vmovdqa64 %ymm17, %ymm7 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm7 = ymm7[0,1,14],zero,ymm7[12,13,0,1,14,15],zero,ymm7[3,12,13,2,3,16],zero,ymm7[30,31,28,29,16,17],zero,ymm7[31,18,19,28,29,18],zero +; AVX512F-FAST-NEXT: vpor %ymm2, %ymm7, %ymm2 +; AVX512F-FAST-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-FAST-NEXT: vmovdqa64 %ymm18, %ymm2 +; AVX512F-FAST-NEXT: vmovdqu64 %ymm18, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vmovdqa64 %ymm25, %ymm7 +; AVX512F-FAST-NEXT: vpshufb %ymm7, %ymm2, %ymm2 +; AVX512F-FAST-NEXT: vmovdqa64 %ymm30, %ymm0 +; AVX512F-FAST-NEXT: vpshufb %ymm0, %ymm4, %ymm0 +; AVX512F-FAST-NEXT: vpor %ymm2, %ymm0, %ymm0 +; AVX512F-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-FAST-NEXT: vmovdqa (%rsi), %xmm13 +; AVX512F-FAST-NEXT: vpshufb %xmm11, %xmm13, %xmm0 +; AVX512F-FAST-NEXT: vmovdqa (%rdi), %xmm9 +; AVX512F-FAST-NEXT: vpshufb %xmm3, %xmm9, %xmm2 +; AVX512F-FAST-NEXT: vporq %xmm0, %xmm2, %xmm31 +; AVX512F-FAST-NEXT: vmovdqa (%rcx), %xmm14 +; AVX512F-FAST-NEXT: vpshufb %xmm8, %xmm14, %xmm0 +; AVX512F-FAST-NEXT: vmovdqa (%rdx), %xmm8 +; AVX512F-FAST-NEXT: vmovdqa64 %xmm19, %xmm2 +; AVX512F-FAST-NEXT: vpshufb %xmm2, %xmm8, %xmm2 +; AVX512F-FAST-NEXT: vpor %xmm0, %xmm2, %xmm0 +; AVX512F-FAST-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512F-FAST-NEXT: vmovdqa (%r9), %xmm2 +; AVX512F-FAST-NEXT: vpshufb %xmm5, %xmm2, %xmm0 +; AVX512F-FAST-NEXT: vmovdqa %xmm2, %xmm3 +; AVX512F-FAST-NEXT: vmovdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512F-FAST-NEXT: vmovdqa (%r8), %xmm4 +; AVX512F-FAST-NEXT: vmovdqa64 %xmm21, %xmm2 +; AVX512F-FAST-NEXT: vpshufb %xmm2, %xmm4, %xmm2 +; AVX512F-FAST-NEXT: vmovdqa %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512F-FAST-NEXT: vpor %xmm0, %xmm2, %xmm0 +; AVX512F-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm0[23],zero,zero,zero,zero,ymm0[26],zero,ymm0[24],zero,zero,zero,zero,ymm0[27],zero,ymm0[25] +; AVX512F-FAST-NEXT: vmovdqa64 %ymm23, %ymm12 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm12[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm12[21],zero,ymm12[19],zero,zero,zero,zero,ymm12[22],zero,ymm12[20],zero,zero +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm2, %zmm0 +; AVX512F-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-FAST-NEXT: vmovdqa64 %ymm26, %ymm11 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm11[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm11[25],zero,ymm11[23],zero,zero,zero,zero,ymm11[26],zero,ymm11[24],zero,zero,zero,zero +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm11[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm11[18],zero,zero,zero,zero,ymm11[21],zero,ymm11[19],zero,zero,zero,zero,ymm11[22],zero,ymm11[20] +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm2, %zmm0 +; AVX512F-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [24,25,128,23,128,21,22,23,26,128,24,128,28,29,26,27,24,25,128,23,128,21,22,23,26,128,24,128,28,29,26,27] +; AVX512F-FAST-NEXT: # ymm2 = mem[0,1,0,1] +; AVX512F-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm5 = [18,128,18,19,20,21,128,19,128,25,26,27,22,128,20,128,18,128,18,19,20,21,128,19,128,25,26,27,22,128,20,128] +; AVX512F-FAST-NEXT: # ymm5 = mem[0,1,0,1] +; AVX512F-FAST-NEXT: vpshufb %ymm2, %ymm1, %ymm0 +; AVX512F-FAST-NEXT: vmovdqa64 %ymm2, %ymm19 +; AVX512F-FAST-NEXT: vpshufb %ymm5, %ymm1, %ymm2 +; AVX512F-FAST-NEXT: vmovdqa64 %ymm5, %ymm30 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm2, %zmm0 +; AVX512F-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm24, %zmm0, %zmm0 +; AVX512F-FAST-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm4[8],xmm3[8],xmm4[9],xmm3[9],xmm4[10],xmm3[10],xmm4[11],xmm3[11],xmm4[12],xmm3[12],xmm4[13],xmm3[13],xmm4[14],xmm3[14],xmm4[15],xmm3[15] +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} xmm3 = +; AVX512F-FAST-NEXT: vpshufb %xmm3, %xmm2, %xmm2 +; AVX512F-FAST-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm2[0,1,0,1],zmm0[4,5,6,7] +; AVX512F-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [2,2,3,3,2,2,3,3] +; AVX512F-FAST-NEXT: # ymm2 = mem[0,1,0,1] +; AVX512F-FAST-NEXT: vmovdqa (%rax), %xmm0 +; AVX512F-FAST-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512F-FAST-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,5,6] +; AVX512F-FAST-NEXT: vpermd %ymm0, %ymm2, %ymm0 +; AVX512F-FAST-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 +; AVX512F-FAST-NEXT: vmovdqa (%rax), %ymm4 +; AVX512F-FAST-NEXT: vmovdqu %ymm4, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm5 = [128,13,128,128,128,128,128,128,14,128,128,128,128,128,128,15,128,128,128,128,128,128,16,128,128,128,128,128,128,17,128,128] +; AVX512F-FAST-NEXT: vpshufb %ymm5, %ymm4, %ymm4 +; AVX512F-FAST-NEXT: vmovdqa64 %ymm5, %ymm18 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm4, %zmm0, %zmm24 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm1[30],zero,ymm1[28],zero,zero,zero,zero,ymm1[31],zero,ymm1[29],zero,zero +; AVX512F-FAST-NEXT: vmovdqa64 %ymm0, %ymm23 +; AVX512F-FAST-NEXT: vpbroadcastq {{.*#+}} ymm1 = [13,12,11,0,0,0,15,14,13,12,11,0,0,0,15,14,13,12,11,0,0,0,15,14,13,12,11,0,0,0,15,14] +; AVX512F-FAST-NEXT: vmovdqu (%rsp), %ymm0 # 32-byte Reload +; AVX512F-FAST-NEXT: vpshufb %ymm1, %ymm0, %ymm0 +; AVX512F-FAST-NEXT: vmovdqa64 %ymm1, %ymm25 +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,3,2,3] +; AVX512F-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm1[27],zero,zero,zero,zero,ymm1[30],zero,ymm1[28],zero,zero,zero,zero,ymm1[31],zero,ymm1[29] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,3,2,3] +; AVX512F-FAST-NEXT: vbroadcasti32x4 {{.*#+}} ymm26 = [18374967954648269055,71777218572844800,18374967954648269055,71777218572844800] +; AVX512F-FAST-NEXT: # ymm26 = mem[0,1,2,3,0,1,2,3] +; AVX512F-FAST-NEXT: vpternlogq $248, %ymm26, %ymm0, %ymm1 +; AVX512F-FAST-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm10[0],xmm15[0],xmm10[1],xmm15[1],xmm10[2],xmm15[2],xmm10[3],xmm15[3],xmm10[4],xmm15[4],xmm10[5],xmm15[5],xmm10[6],xmm15[6],xmm10[7],xmm15[7] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[u,u,4,5,0,1,u,u,u,6,7,2,3,u,u,u] +; AVX512F-FAST-NEXT: vshufi64x2 {{.*#+}} zmm21 = zmm1[0,1,2,3],zmm0[0,1,0,1] +; AVX512F-FAST-NEXT: vmovdqa64 %xmm29, %xmm0 +; AVX512F-FAST-NEXT: vmovdqa64 %xmm28, %xmm1 +; AVX512F-FAST-NEXT: vpunpcklbw {{.*#+}} xmm7 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] +; AVX512F-FAST-NEXT: vpunpckhbw {{.*#+}} xmm0 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15] +; AVX512F-FAST-NEXT: vpunpckhbw {{.*#+}} xmm1 = xmm14[8],xmm8[8],xmm14[9],xmm8[9],xmm14[10],xmm8[10],xmm14[11],xmm8[11],xmm14[12],xmm8[12],xmm14[13],xmm8[13],xmm14[14],xmm8[14],xmm14[15],xmm8[15] +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} xmm4 = <6,3,2,u,u,u,9,8,5,4,u,u,u,11,10,7> +; AVX512F-FAST-NEXT: vpshufb %xmm4, %xmm1, %xmm1 +; AVX512F-FAST-NEXT: vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vpshufb %xmm4, %xmm0, %xmm0 +; AVX512F-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload +; AVX512F-FAST-NEXT: vinserti32x4 $2, %xmm0, %zmm1, %zmm28 +; AVX512F-FAST-NEXT: vmovdqa64 %xmm27, %xmm0 +; AVX512F-FAST-NEXT: vmovdqa %xmm6, %xmm1 +; AVX512F-FAST-NEXT: vpunpcklbw {{.*#+}} xmm6 = xmm0[0],xmm6[0],xmm0[1],xmm6[1],xmm0[2],xmm6[2],xmm0[3],xmm6[3],xmm0[4],xmm6[4],xmm0[5],xmm6[5],xmm0[6],xmm6[6],xmm0[7],xmm6[7] +; AVX512F-FAST-NEXT: vpunpckhbw {{.*#+}} xmm1 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15] +; AVX512F-FAST-NEXT: vpunpckhbw {{.*#+}} xmm4 = xmm13[8],xmm9[8],xmm13[9],xmm9[9],xmm13[10],xmm9[10],xmm13[11],xmm9[11],xmm13[12],xmm9[12],xmm13[13],xmm9[13],xmm13[14],xmm9[14],xmm13[15],xmm9[15] +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} xmm5 = <2,u,u,u,9,8,5,4,u,u,u,11,10,7,6,u> +; AVX512F-FAST-NEXT: vpshufb %xmm5, %xmm4, %xmm0 +; AVX512F-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vpshufb %xmm5, %xmm1, %xmm1 +; AVX512F-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-FAST-NEXT: vinserti32x4 $2, %xmm1, %zmm0, %zmm27 +; AVX512F-FAST-NEXT: vpunpckhbw {{.*#+}} xmm1 = xmm10[8],xmm15[8],xmm10[9],xmm15[9],xmm10[10],xmm15[10],xmm10[11],xmm15[11],xmm10[12],xmm15[12],xmm10[13],xmm15[13],xmm10[14],xmm15[14],xmm10[15],xmm15[15] +; AVX512F-FAST-NEXT: vpshufb %xmm3, %xmm1, %xmm1 +; AVX512F-FAST-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm22[0,1,0,1],zmm1[0,1,0,1] +; AVX512F-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-FAST-NEXT: vmovdqa 32(%rax), %xmm0 +; AVX512F-FAST-NEXT: vpshufhw {{.*#+}} xmm1 = xmm0[0,1,2,3,4,5,5,6] +; AVX512F-FAST-NEXT: vmovdqa64 %xmm0, %xmm29 +; AVX512F-FAST-NEXT: vpermd %ymm1, %ymm2, %ymm0 +; AVX512F-FAST-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill +; AVX512F-FAST-NEXT: vpbroadcastq {{.*#+}} ymm1 = [11,0,0,0,15,14,13,12,11,0,0,0,15,14,13,12,11,0,0,0,15,14,13,12,11,0,0,0,15,14,13,12] +; AVX512F-FAST-NEXT: vpshufb %ymm1, %ymm11, %ymm5 +; AVX512F-FAST-NEXT: vmovdqa64 %ymm20, %ymm0 +; AVX512F-FAST-NEXT: vpshufb %ymm1, %ymm0, %ymm1 +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm22 = ymm1[2,3,2,3] +; AVX512F-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm2 # 32-byte Reload +; AVX512F-FAST-NEXT: vmovdqa64 %ymm19, %ymm1 +; AVX512F-FAST-NEXT: vpshufb %ymm1, %ymm2, %ymm1 +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm20 = ymm1[2,3,2,3] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm10 = ymm0[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm0[18],zero,zero,zero,zero,ymm0[21],zero,ymm0[19],zero,zero,zero,zero,ymm0[22],zero,ymm0[20] +; AVX512F-FAST-NEXT: vmovdqa64 %ymm30, %ymm0 +; AVX512F-FAST-NEXT: vpshufb %ymm0, %ymm2, %ymm4 +; AVX512F-FAST-NEXT: vpbroadcastq {{.*#+}} ymm2 = [9,8,7,0,0,0,11,10,9,8,7,0,0,0,11,10,9,8,7,0,0,0,11,10,9,8,7,0,0,0,11,10] +; AVX512F-FAST-NEXT: vmovdqa64 %ymm16, %ymm0 +; AVX512F-FAST-NEXT: vpshufb %ymm2, %ymm0, %ymm1 +; AVX512F-FAST-NEXT: vmovdqa64 %ymm2, %ymm30 +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm19 = ymm1[2,3,2,3] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm11 = ymm0[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm0[21],zero,ymm0[19],zero,zero,zero,zero,ymm0[22],zero,ymm0[20],zero,zero +; AVX512F-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload +; AVX512F-FAST-NEXT: vmovdqa64 %ymm18, %ymm1 +; AVX512F-FAST-NEXT: vpshufb %ymm1, %ymm0, %ymm3 +; AVX512F-FAST-NEXT: vpshuflw {{.*#+}} ymm0 = ymm0[2,1,1,2,4,5,6,7,10,9,9,10,12,13,14,15] +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm1 = [4,5,4,5,5,7,4,5] +; AVX512F-FAST-NEXT: vpermd %ymm0, %ymm1, %ymm0 +; AVX512F-FAST-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm3, %zmm16 +; AVX512F-FAST-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm9[0],xmm13[0],xmm9[1],xmm13[1],xmm9[2],xmm13[2],xmm9[3],xmm13[3],xmm9[4],xmm13[4],xmm9[5],xmm13[5],xmm9[6],xmm13[6],xmm9[7],xmm13[7] +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} xmm9 = <0,1,u,u,u,6,7,2,3,u,u,u,8,9,4,5> +; AVX512F-FAST-NEXT: vpshufb %xmm9, %xmm6, %xmm6 +; AVX512F-FAST-NEXT: vpshufb %xmm9, %xmm0, %xmm0 +; AVX512F-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm9 = [28,29,30,128,28,128,30,31,30,31,128,29,128,31,28,29,28,29,30,128,28,128,30,31,30,31,128,29,128,31,28,29] +; AVX512F-FAST-NEXT: # ymm9 = mem[0,1,0,1] +; AVX512F-FAST-NEXT: vmovdqa64 %ymm17, %ymm3 +; AVX512F-FAST-NEXT: vpshufb %ymm9, %ymm3, %ymm15 +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm17 = ymm15[2,3,2,3] +; AVX512F-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload +; AVX512F-FAST-NEXT: vmovdqa64 %ymm25, %ymm2 +; AVX512F-FAST-NEXT: vpshufb %ymm2, %ymm1, %ymm13 +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm18 = ymm13[2,3,2,3] +; AVX512F-FAST-NEXT: vinserti32x4 $2, %xmm31, %zmm0, %zmm0 +; AVX512F-FAST-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill +; AVX512F-FAST-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm8[0],xmm14[0],xmm8[1],xmm14[1],xmm8[2],xmm14[2],xmm8[3],xmm14[3],xmm8[4],xmm14[4],xmm8[5],xmm14[5],xmm8[6],xmm14[6],xmm8[7],xmm14[7] +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} xmm8 = <4,5,0,1,u,u,u,6,7,2,3,u,u,u,8,9> +; AVX512F-FAST-NEXT: vpshufb %xmm8, %xmm7, %xmm7 +; AVX512F-FAST-NEXT: vpshufb %xmm8, %xmm0, %xmm13 +; AVX512F-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm8 = ymm0[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,24,25,24,25],zero,ymm0[23],zero,ymm0[23,24,25,26],zero,ymm0[24],zero,ymm0[30,31] +; AVX512F-FAST-NEXT: vmovdqa64 %ymm0, %ymm25 +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm15 = ymm8[2,3,2,3] +; AVX512F-FAST-NEXT: vmovdqa %ymm12, %ymm1 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm12 = ymm12[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,ymm12[30],zero,ymm12[28],zero,zero,zero,zero,ymm12[31],zero,ymm12[29],zero,zero,zero +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm12 = ymm12[2,3,2,3] +; AVX512F-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm2 # 32-byte Reload +; AVX512F-FAST-NEXT: vpshufb %ymm9, %ymm2, %ymm9 +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm9 = ymm9[2,3,2,3] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm6 = ymm6[0,1,0,1] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm5 = ymm5[2,3,2,3] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm0 = ymm23[2,3,2,3] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm7 = ymm7[0,1,0,1] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm10 = ymm10[2,3,2,3] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm4 = ymm4[2,3,2,3] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm8 = ymm11[2,3,2,3] +; AVX512F-FAST-NEXT: vinserti32x4 $2, {{[-0-9]+}}(%r{{[sb]}}p), %zmm13, %zmm31 # 16-byte Folded Reload +; AVX512F-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm11 = [18,19,20,21,128,19,128,21,20,21,22,128,20,128,22,23,18,19,20,21,128,19,128,21,20,21,22,128,20,128,22,23] +; AVX512F-FAST-NEXT: # ymm11 = mem[0,1,0,1] +; AVX512F-FAST-NEXT: vpshufb %ymm11, %ymm3, %ymm14 +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm14 = ymm14[2,3,2,3] +; AVX512F-FAST-NEXT: vmovdqa64 %ymm30, %ymm3 +; AVX512F-FAST-NEXT: vpshufb %ymm3, %ymm1, %ymm13 +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm13 = ymm13[2,3,2,3] +; AVX512F-FAST-NEXT: vpshufb %ymm11, %ymm2, %ymm1 +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,3,2,3] +; AVX512F-FAST-NEXT: vpor %ymm12, %ymm9, %ymm9 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm6, %zmm9, %zmm6 +; AVX512F-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm9 = [18374966859431673855,18446463693966278655,18374966859431673855,18446463693966278655] +; AVX512F-FAST-NEXT: # ymm9 = mem[0,1,0,1] +; AVX512F-FAST-NEXT: vpternlogq $248, %ymm9, %ymm5, %ymm0 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm7, %zmm0, %zmm7 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm0 = [255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255] +; AVX512F-FAST-NEXT: vpternlogq $226, %zmm6, %zmm0, %zmm7 +; AVX512F-FAST-NEXT: vpor %ymm4, %ymm10, %ymm4 +; AVX512F-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm4, %zmm2, %zmm4 +; AVX512F-FAST-NEXT: vpor %ymm8, %ymm14, %ymm2 +; AVX512F-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm5 +; AVX512F-FAST-NEXT: vpternlogq $226, %zmm4, %zmm0, %zmm5 +; AVX512F-FAST-NEXT: vpandq %ymm9, %ymm22, %ymm0 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm20, %zmm0 +; AVX512F-FAST-NEXT: vpermq $238, {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Folded Reload +; AVX512F-FAST-NEXT: # zmm2 = mem[2,3,2,3,6,7,6,7] +; AVX512F-FAST-NEXT: vporq %zmm2, %zmm0, %zmm0 +; AVX512F-FAST-NEXT: vpandq %ymm26, %ymm19, %ymm2 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm17, %zmm2, %zmm2 +; AVX512F-FAST-NEXT: vpermq $238, {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Folded Reload +; AVX512F-FAST-NEXT: # zmm4 = mem[2,3,2,3,6,7,6,7] +; AVX512F-FAST-NEXT: vporq %zmm4, %zmm2, %zmm2 +; AVX512F-FAST-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm2 +; AVX512F-FAST-NEXT: vpandq %ymm26, %ymm18, %ymm0 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm0, %zmm15, %zmm0 +; AVX512F-FAST-NEXT: vpermq $238, {{[-0-9]+}}(%r{{[sb]}}p), %zmm4 # 64-byte Folded Reload +; AVX512F-FAST-NEXT: # zmm4 = mem[2,3,2,3,6,7,6,7] +; AVX512F-FAST-NEXT: vporq %zmm4, %zmm0, %zmm0 +; AVX512F-FAST-NEXT: vmovdqa64 {{.*#+}} zmm4 = [255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255,255,255,255,255,0,0,255] +; AVX512F-FAST-NEXT: vpternlogq $184, %zmm2, %zmm4, %zmm0 +; AVX512F-FAST-NEXT: vpermq {{.*#+}} zmm2 = zmm28[0,1,0,1,4,5,4,5] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} zmm8 = zmm27[0,1,0,1,4,5,4,5] +; AVX512F-FAST-NEXT: vpternlogq $226, %zmm2, %zmm4, %zmm8 +; AVX512F-FAST-NEXT: vpandq %ymm26, %ymm13, %ymm2 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1 +; AVX512F-FAST-NEXT: vpermq $238, {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Folded Reload +; AVX512F-FAST-NEXT: # zmm2 = mem[2,3,2,3,6,7,6,7] +; AVX512F-FAST-NEXT: vporq %zmm2, %zmm1, %zmm1 +; AVX512F-FAST-NEXT: vpermq $238, {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Folded Reload +; AVX512F-FAST-NEXT: # zmm2 = mem[2,3,2,3,6,7,6,7] +; AVX512F-FAST-NEXT: vpermq $238, {{[-0-9]+}}(%r{{[sb]}}p), %zmm6 # 64-byte Folded Reload +; AVX512F-FAST-NEXT: # zmm6 = mem[2,3,2,3,6,7,6,7] +; AVX512F-FAST-NEXT: vporq %zmm2, %zmm6, %zmm9 +; AVX512F-FAST-NEXT: vpternlogq $226, %zmm1, %zmm4, %zmm9 +; AVX512F-FAST-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload +; AVX512F-FAST-NEXT: vpunpcklbw {{[-0-9]+}}(%r{{[sb]}}p), %xmm1, %xmm1 # 16-byte Folded Reload +; AVX512F-FAST-NEXT: # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1],xmm1[2],mem[2],xmm1[3],mem[3],xmm1[4],mem[4],xmm1[5],mem[5],xmm1[6],mem[6],xmm1[7],mem[7] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[u,u,4,5,0,1,u,u,u,6,7,2,3,u,u,u] +; AVX512F-FAST-NEXT: vshufi64x2 $0, {{[-0-9]+}}(%r{{[sb]}}p), %zmm1, %zmm18 # 64-byte Folded Reload +; AVX512F-FAST-NEXT: # zmm18 = zmm1[0,1,0,1],mem[0,1,0,1] +; AVX512F-FAST-NEXT: vmovdqa64 %xmm29, %xmm3 +; AVX512F-FAST-NEXT: vpshuflw {{.*#+}} xmm2 = xmm3[1,1,0,0,4,5,6,7] +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,0,1,2,0,0,1] +; AVX512F-FAST-NEXT: vpermd %ymm2, %ymm4, %ymm19 +; AVX512F-FAST-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload +; AVX512F-FAST-NEXT: vpshuflw {{.*#+}} xmm6 = xmm1[1,1,0,0,4,5,6,7] +; AVX512F-FAST-NEXT: vpermd %ymm6, %ymm4, %ymm17 +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} xmm6 = [4,5,4,5,4,5,8,9,6,7,6,7,6,7,6,7] +; AVX512F-FAST-NEXT: vpshufb %xmm6, %xmm3, %xmm10 +; AVX512F-FAST-NEXT: vpshufb %xmm6, %xmm1, %xmm6 +; AVX512F-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm11 = [128,20,128,18,128,128,128,128,21,128,19,128,128,128,128,22,128,20,128,18,128,128,128,128,21,128,19,128,128,128,128,22] +; AVX512F-FAST-NEXT: # ymm11 = mem[0,1,0,1] +; AVX512F-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload +; AVX512F-FAST-NEXT: vpshufb %ymm11, %ymm1, %ymm12 +; AVX512F-FAST-NEXT: vmovdqu (%rsp), %ymm1 # 32-byte Reload +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm13 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm1[25],zero,ymm1[23],zero,zero,zero,zero,ymm1[26],zero,ymm1[24],zero,zero +; AVX512F-FAST-NEXT: vpshufb %ymm11, %ymm1, %ymm11 +; AVX512F-FAST-NEXT: vbroadcasti128 {{.*#+}} ymm14 = [20,128,18,128,20,21,20,21,128,19,128,19,20,21,22,128,20,128,18,128,20,21,20,21,128,19,128,19,20,21,22,128] +; AVX512F-FAST-NEXT: # ymm14 = mem[0,1,0,1] +; AVX512F-FAST-NEXT: vmovdqa64 %ymm25, %ymm1 +; AVX512F-FAST-NEXT: vpshufb %ymm14, %ymm1, %ymm15 +; AVX512F-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm2 # 32-byte Reload +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm2[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,24,25,24,25],zero,ymm2[23],zero,ymm2[23,24,25,26],zero,ymm2[24],zero,ymm2[30,31] +; AVX512F-FAST-NEXT: vpshufb %ymm14, %ymm2, %ymm14 +; AVX512F-FAST-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm3 # 32-byte Reload +; AVX512F-FAST-NEXT: vpshuflw {{.*#+}} ymm4 = ymm3[2,1,1,2,4,5,6,7,10,9,9,10,12,13,14,15] +; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm2 = [4,5,4,5,5,7,4,5] +; AVX512F-FAST-NEXT: vpermd %ymm4, %ymm2, %ymm20 +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm3[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,28,29,26,27,28,29,30,31,30,31,28,29,28,29,30,31] +; AVX512F-FAST-NEXT: vpshufb {{.*#+}} ymm4 = ymm3[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,22,23,26,27,24,25,22,23,24,25,26,27,26,27,24,25] +; AVX512F-FAST-NEXT: vpermq $238, {{[-0-9]+}}(%r{{[sb]}}p), %zmm22 # 64-byte Folded Reload +; AVX512F-FAST-NEXT: # zmm22 = mem[2,3,2,3,6,7,6,7] +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm22 +; AVX512F-FAST-NEXT: vpermq $68, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Folded Reload +; AVX512F-FAST-NEXT: # ymm0 = mem[0,1,0,1] +; AVX512F-FAST-NEXT: vpermq $68, {{[-0-9]+}}(%r{{[sb]}}p), %ymm23 # 32-byte Folded Reload +; AVX512F-FAST-NEXT: # ymm23 = mem[0,1,0,1] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm2 = ymm2[2,3,2,3] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm10 = ymm10[0,0,1,0] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm12 = ymm12[2,3,2,3] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm15 = ymm15[2,3,2,3] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm6 = ymm6[0,0,1,0] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm13 = ymm13[2,3,2,3] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,3,2,3] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm11 = ymm11[2,3,2,3] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm14 = ymm14[2,3,2,3] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} ymm4 = ymm4[2,3,2,3] +; AVX512F-FAST-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm0 # 32-byte Folded Reload +; AVX512F-FAST-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm23, %zmm23 # 32-byte Folded Reload +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm23 +; AVX512F-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload +; AVX512F-FAST-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm24 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm23, %zmm24 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm19, %zmm2, %zmm0 +; AVX512F-FAST-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm21 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm7, %zmm21 +; AVX512F-FAST-NEXT: vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm10, %zmm0 # 32-byte Folded Reload +; AVX512F-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm0 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm8, %zmm0 +; AVX512F-FAST-NEXT: vpor %ymm12, %ymm15, %ymm2 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm2 +; AVX512F-FAST-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm7 # 64-byte Reload +; AVX512F-FAST-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm7[0,1,2,3],zmm2[4,5,6,7] +; AVX512F-FAST-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm16 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm5, %zmm16 +; AVX512F-FAST-NEXT: vpermq $68, {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Folded Reload +; AVX512F-FAST-NEXT: # zmm2 = mem[0,1,0,1,4,5,4,5] +; AVX512F-FAST-NEXT: vpermq {{.*#+}} zmm5 = zmm31[0,1,0,1,4,5,4,5] +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm5 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm6, %zmm17, %zmm2 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm18, %zmm2 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm5, %zmm2 +; AVX512F-FAST-NEXT: vpor %ymm1, %ymm13, %ymm1 +; AVX512F-FAST-NEXT: vpor %ymm11, %ymm14, %ymm5 +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm1 +; AVX512F-FAST-NEXT: vshufi64x2 {{.*#+}} zmm1 = zmm5[0,1,2,3],zmm1[4,5,6,7] +; AVX512F-FAST-NEXT: vinserti64x4 $1, %ymm4, %zmm20, %zmm4 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm4 +; AVX512F-FAST-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm4 +; AVX512F-FAST-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512F-FAST-NEXT: vmovdqa64 %zmm4, 128(%rax) +; AVX512F-FAST-NEXT: vmovdqa64 %zmm2, (%rax) +; AVX512F-FAST-NEXT: vmovdqa64 %zmm16, 320(%rax) +; AVX512F-FAST-NEXT: vmovdqa64 %zmm0, 256(%rax) +; AVX512F-FAST-NEXT: vmovdqa64 %zmm21, 192(%rax) +; AVX512F-FAST-NEXT: vmovdqa64 %zmm24, 64(%rax) +; AVX512F-FAST-NEXT: vmovdqa64 %zmm22, 384(%rax) +; AVX512F-FAST-NEXT: addq $1256, %rsp # imm = 0x4E8 +; AVX512F-FAST-NEXT: vzeroupper +; AVX512F-FAST-NEXT: retq ; -; AVX512BW-ONLY-SLOW-LABEL: store_i8_stride7_vf64: -; AVX512BW-ONLY-SLOW: # %bb.0: -; AVX512BW-ONLY-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa (%rax), %ymm15 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa 32(%rax), %ymm2 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} ymm9 = [12,13,2,3,12,13,0,1,14,15,2,3,0,1,14,15,28,29,18,19,28,29,16,17,30,31,18,19,16,17,30,31] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm9, %ymm15, %ymm0 -; AVX512BW-ONLY-SLOW-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [4,5,4,5,5,6,5,6,4,5,4,5,5,6,5,6] -; AVX512BW-ONLY-SLOW-NEXT: # ymm1 = mem[0,1,0,1] -; AVX512BW-ONLY-SLOW-NEXT: vpermw %ymm15, %ymm1, %ymm1 -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm3 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa (%r9), %ymm10 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm22 = [13,128,128,128,128,128,128,14,128,128,128,128,128,128,15,128,128,128,128,128,128,16,128,128,128,128,128,128,17,128,128,128] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm22, %ymm10, %ymm0 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa (%r8), %ymm11 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm23 = [128,128,128,128,128,128,14,128,128,128,128,128,128,15,128,128,128,128,128,128,16,128,128,128,128,128,128,17,128,128,128,128] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm23, %ymm11, %ymm1 -; AVX512BW-ONLY-SLOW-NEXT: vpor %ymm0, %ymm1, %ymm5 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa (%r9), %xmm4 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa (%r8), %xmm1 -; AVX512BW-ONLY-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm6 = xmm1[8],xmm4[8],xmm1[9],xmm4[9],xmm1[10],xmm4[10],xmm1[11],xmm4[11],xmm1[12],xmm4[12],xmm1[13],xmm4[13],xmm1[14],xmm4[14],xmm1[15],xmm4[15] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb {{.*#+}} xmm6 = xmm6[u,6,7,2,3,u,u,u,8,9,4,5,u,u,u,10] -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm6 = ymm6[0,1,0,1] -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm5, %zmm6, %zmm20 -; AVX512BW-ONLY-SLOW-NEXT: movabsq $2323999253380730912, %r10 # imm = 0x2040810204081020 -; AVX512BW-ONLY-SLOW-NEXT: kmovq %r10, %k1 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm3, %zmm20 {%k1} -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 (%rdx), %ymm16 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} ymm14 = [0,1,0,1,14,128,14,15,0,1,14,15,128,13,14,15,16,17,16,128,30,31,30,31,16,17,128,31,28,29,30,31] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm14, %ymm16, %ymm3 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 (%rcx), %ymm17 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm25 = [128,128,128,128,128,14,128,128,128,128,128,128,15,128,128,128,128,128,128,16,128,128,128,128,128,128,17,128,128,128,128,128] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm25, %ymm17, %ymm5 -; AVX512BW-ONLY-SLOW-NEXT: vpor %ymm3, %ymm5, %ymm3 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa (%rdx), %xmm5 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa (%rcx), %xmm6 -; AVX512BW-ONLY-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm7 = xmm6[8],xmm5[8],xmm6[9],xmm5[9],xmm6[10],xmm5[10],xmm6[11],xmm5[11],xmm6[12],xmm5[12],xmm6[13],xmm5[13],xmm6[14],xmm5[14],xmm6[15],xmm5[15] -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} xmm12 = <6,3,2,u,u,u,9,8,5,4,u,u,u,11,10,7> -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm12, %xmm7, %xmm7 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm7[0,1,0,1] -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm3, %zmm7, %zmm21 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 (%rdi), %ymm18 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm26 = [0,1,14,128,12,13,0,1,14,15,128,3,12,13,2,3,16,128,30,31,28,29,16,17,128,31,18,19,28,29,18,128] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm26, %ymm18, %ymm3 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 (%rsi), %ymm19 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm27 = [128,128,128,14,128,128,128,128,128,128,15,128,128,128,128,128,128,16,128,128,128,128,128,128,17,128,128,128,128,128,128,18] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm27, %ymm19, %ymm7 -; AVX512BW-ONLY-SLOW-NEXT: vpor %ymm3, %ymm7, %ymm3 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa (%rdi), %xmm7 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa (%rsi), %xmm8 -; AVX512BW-ONLY-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm24 = xmm8[8],xmm7[8],xmm8[9],xmm7[9],xmm8[10],xmm7[10],xmm8[11],xmm7[11],xmm8[12],xmm7[12],xmm8[13],xmm7[13],xmm8[14],xmm7[14],xmm8[15],xmm7[15] -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} xmm13 = <2,u,u,u,9,8,5,4,u,u,u,11,10,7,6,u> -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm13, %xmm24, %xmm24 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm24 = ymm24[0,1,0,1] -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm3, %zmm24, %zmm3 -; AVX512BW-ONLY-SLOW-NEXT: movabsq $435749860008887046, %r10 # imm = 0x60C183060C18306 -; AVX512BW-ONLY-SLOW-NEXT: kmovq %r10, %k1 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm21, %zmm3 {%k1} -; AVX512BW-ONLY-SLOW-NEXT: movabsq $4066998693416279096, %r10 # imm = 0x3870E1C3870E1C38 -; AVX512BW-ONLY-SLOW-NEXT: kmovq %r10, %k1 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm20, %zmm3 {%k1} -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm21 = [10,9,9,10,10,9,9,10,9,10,14,15,10,9,9,10,27,29,28,27,28,29,29,28,27,29,28,27,28,29,29,28] -; AVX512BW-ONLY-SLOW-NEXT: vpermw %ymm2, %ymm21, %ymm20 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm9, %ymm2, %ymm9 -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm20, %zmm9, %zmm9 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 32(%r9), %ymm20 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm22, %ymm20, %ymm24 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 32(%r8), %ymm22 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm23, %ymm22, %ymm23 -; AVX512BW-ONLY-SLOW-NEXT: vporq %ymm24, %ymm23, %ymm24 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm23 = -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm23, %ymm20, %ymm28 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm28 = ymm28[2,3,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm29 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm22[20],zero,ymm22[18],zero,ymm22[20,21,20,21],zero,ymm22[19],zero,ymm22[19,20,21,22],zero -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm29 = ymm29[2,3,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vporq %ymm29, %ymm28, %ymm28 -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm28, %zmm24, %zmm28 -; AVX512BW-ONLY-SLOW-NEXT: movabsq $145249953336295682, %r10 # imm = 0x204081020408102 -; AVX512BW-ONLY-SLOW-NEXT: kmovq %r10, %k1 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm9, %zmm28 {%k1} -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 32(%rsi), %ymm29 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 32(%rdi), %ymm30 -; AVX512BW-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} ymm9 = ymm30[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512BW-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm9 = ymm9[0,0,1,1,4,4,5,5] -; AVX512BW-ONLY-SLOW-NEXT: vpbroadcastd {{.*#+}} ymm24 = [5,4,3,6,5,4,3,6,5,4,3,6,5,4,3,6,5,4,3,6,5,4,3,6,5,4,3,6,5,4,3,6] -; AVX512BW-ONLY-SLOW-NEXT: movl $676341840, %r10d # imm = 0x28502850 -; AVX512BW-ONLY-SLOW-NEXT: kmovd %r10d, %k1 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm24, %ymm29, %ymm9 {%k1} -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm9 = ymm9[2,3,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm26, %ymm30, %ymm26 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm27, %ymm29, %ymm27 -; AVX512BW-ONLY-SLOW-NEXT: vporq %ymm26, %ymm27, %ymm26 -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm9, %zmm26, %zmm9 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 32(%rdx), %ymm31 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm14, %ymm31, %ymm14 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa 32(%rcx), %ymm0 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm25, %ymm0, %ymm25 -; AVX512BW-ONLY-SLOW-NEXT: vporq %ymm14, %ymm25, %ymm14 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm26 = -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm26, %ymm0, %ymm25 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm25 = ymm25[2,3,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm27 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm31[18],zero,ymm31[18,19,20,21],zero,ymm31[19],zero,ymm31[25,26,27,22],zero,ymm31[20],zero -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm27 = ymm27[2,3,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vporq %ymm27, %ymm25, %ymm25 -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm25, %zmm14, %zmm14 -; AVX512BW-ONLY-SLOW-NEXT: movabsq $3485998880071096368, %r10 # imm = 0x3060C183060C1830 -; AVX512BW-ONLY-SLOW-NEXT: kmovq %r10, %k2 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm14, %zmm9 {%k2} -; AVX512BW-ONLY-SLOW-NEXT: movabsq $-4357498600088870461, %r10 # imm = 0xC3870E1C3870E1C3 -; AVX512BW-ONLY-SLOW-NEXT: kmovq %r10, %k3 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm28, %zmm9 {%k3} -; AVX512BW-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm14 = ymm30[0,1,2,3,6,7,7,6,8,9,10,11,14,15,15,14] -; AVX512BW-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm14 = ymm14[2,2,3,3,6,6,7,7] -; AVX512BW-ONLY-SLOW-NEXT: vpbroadcastd {{.*#+}} ymm25 = [13,12,15,14,13,12,15,14,13,12,15,14,13,12,15,14,13,12,15,14,13,12,15,14,13,12,15,14,13,12,15,14] -; AVX512BW-ONLY-SLOW-NEXT: movl $338170920, %r10d # imm = 0x14281428 -; AVX512BW-ONLY-SLOW-NEXT: kmovd %r10d, %k4 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm25, %ymm29, %ymm14 {%k4} -; AVX512BW-ONLY-SLOW-NEXT: vbroadcasti32x4 {{.*#+}} ymm28 = [25,128,23,128,128,128,128,26,128,24,128,128,128,128,27,128,25,128,23,128,128,128,128,26,128,24,128,128,128,128,27,128] -; AVX512BW-ONLY-SLOW-NEXT: # ymm28 = mem[0,1,2,3,0,1,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm28, %ymm29, %ymm27 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm27 = ymm27[2,3,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm29 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,23,128,128,128,128,26,128,24,128,128,128,128,27,128,25] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm29, %ymm30, %ymm30 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm30 = ymm30[2,3,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vporq %ymm27, %ymm30, %ymm27 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm14 = ymm14[2,3,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm14, %zmm27, %zmm14 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm27 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm31[24,25],zero,ymm31[23],zero,ymm31[21,22,23,26],zero,ymm31[24],zero,ymm31[28,29,26,27] -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm27 = ymm27[2,3,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm30 = ymm0[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm0[25],zero,ymm0[23],zero,zero,zero,zero,ymm0[26],zero,ymm0[24],zero,zero,zero,zero -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm30 = ymm30[2,3,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vporq %ymm27, %ymm30, %ymm30 -; AVX512BW-ONLY-SLOW-NEXT: vpbroadcastq {{.*#+}} ymm27 = [11,0,0,0,15,14,13,12,11,0,0,0,15,14,13,12,11,0,0,0,15,14,13,12,11,0,0,0,15,14,13,12] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm27, %ymm0, %ymm0 -; AVX512BW-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm31 = ymm31[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512BW-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm31 = ymm31[0,2,3,3,4,6,7,7] -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %ymm31, %ymm0 {%k1} -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,3,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm0, %zmm30, %zmm0 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 (%r8), %zmm30 -; AVX512BW-ONLY-SLOW-NEXT: movabsq $1742999440035548184, %r10 # imm = 0x183060C183060C18 -; AVX512BW-ONLY-SLOW-NEXT: kmovq %r10, %k3 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm0, %zmm14 {%k3} -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 (%r9), %zmm0 -; AVX512BW-ONLY-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm22 = zmm22[0,1,2,3],zmm0[4,5,6,7] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb {{.*#+}} zmm22 = zmm22[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,24,25,24,25],zero,zmm22[23],zero,zmm22[23,24,25,26],zero,zmm22[24],zero,zmm22[30,31,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,61],zero,zmm22[59],zero,zero,zero,zero,zmm22[62],zero,zmm22[60],zero,zero,zero,zero,zmm22[63],zero -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} zmm22 = zmm22[2,3,2,3,6,7,6,7] -; AVX512BW-ONLY-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm20 = zmm20[0,1,2,3],zmm30[4,5,6,7] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb {{.*#+}} zmm20 = zmm20[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,zmm20[25],zero,zmm20[23],zero,zero,zero,zero,zmm20[26],zero,zmm20[24],zero,zero,zmm20[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zmm20[59],zero,zero,zero,zero,zmm20[62],zero,zmm20[60],zero,zero,zero,zero,zmm20[63],zero,zmm20[61] -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} zmm20 = zmm20[2,3,2,3,6,7,6,7] -; AVX512BW-ONLY-SLOW-NEXT: vporq %zmm22, %zmm20, %zmm20 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 (%rax), %zmm22 -; AVX512BW-ONLY-SLOW-NEXT: movabsq $6971997760142192736, %rax # imm = 0x60C183060C183060 -; AVX512BW-ONLY-SLOW-NEXT: kmovq %rax, %k3 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm20, %zmm14 {%k3} -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm20 = [11,13,12,11,12,13,13,12,11,13,12,11,12,13,13,12,62,61,62,63,63,62,62,63,62,61,62,63,63,62,62,63] -; AVX512BW-ONLY-SLOW-NEXT: vpermi2w %zmm22, %zmm2, %zmm20 -; AVX512BW-ONLY-SLOW-NEXT: movabsq $-9150747060186627967, %rax # imm = 0x8102040810204081 -; AVX512BW-ONLY-SLOW-NEXT: kmovq %rax, %k5 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm20, %zmm14 {%k5} -; AVX512BW-ONLY-SLOW-NEXT: vpshuflw {{.*#+}} ymm20 = ymm18[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512BW-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm20 = ymm20[0,0,1,1,4,4,5,5] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm24, %ymm19, %ymm20 {%k1} -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm28, %ymm19, %ymm24 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm24 = ymm24[2,3,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm29, %ymm18, %ymm28 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm28 = ymm28[2,3,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vporq %ymm24, %ymm28, %ymm24 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm20 = ymm20[2,3,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm24, %zmm20, %zmm28 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 (%rcx), %zmm20 -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm17, %zmm20, %zmm20 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %zmm26, %zmm20, %zmm20 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 (%rdx), %zmm24 -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm16, %zmm24, %zmm24 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb {{.*#+}} zmm24 = zmm24[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18],zero,zmm24[18,19,20,21],zero,zmm24[19],zero,zmm24[25,26,27,22],zero,zmm24[20],zero,zmm24[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,56,57],zero,zmm24[55],zero,zmm24[53,54,55,58],zero,zmm24[56],zero,zmm24[60,61,58,59] -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} zmm24 = zmm24[2,3,2,3,6,7,6,7] -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} zmm20 = zmm20[2,3,2,3,6,7,6,7] -; AVX512BW-ONLY-SLOW-NEXT: vporq %zmm24, %zmm20, %zmm20 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 32(%r9), %xmm24 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm28, %zmm20 {%k3} -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 32(%r8), %xmm26 -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm10, %zmm0, %zmm0 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %zmm23, %zmm0, %zmm0 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 32(%rdx), %xmm23 -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm11, %zmm30, %zmm28 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb {{.*#+}} zmm28 = zmm28[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,20],zero,zmm28[18],zero,zmm28[20,21,20,21],zero,zmm28[19],zero,zmm28[19,20,21,22],zero,zmm28[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,56,57,56,57],zero,zmm28[55],zero,zmm28[55,56,57,58],zero,zmm28[56],zero,zmm28[62,63] -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} zmm28 = zmm28[2,3,2,3,6,7,6,7] -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} zmm0 = zmm0[2,3,2,3,6,7,6,7] -; AVX512BW-ONLY-SLOW-NEXT: vporq %zmm28, %zmm0, %zmm0 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 32(%rcx), %xmm28 -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm15, %zmm22, %zmm15 -; AVX512BW-ONLY-SLOW-NEXT: vpermw %zmm15, %zmm21, %zmm21 -; AVX512BW-ONLY-SLOW-NEXT: movabsq $1161999626690365456, %rax # imm = 0x1020408102040810 -; AVX512BW-ONLY-SLOW-NEXT: kmovq %rax, %k5 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm21, %zmm0 {%k5} -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 32(%rdi), %xmm21 -; AVX512BW-ONLY-SLOW-NEXT: movabsq $2033499346708139548, %rax # imm = 0x1C3870E1C3870E1C -; AVX512BW-ONLY-SLOW-NEXT: kmovq %rax, %k5 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm0, %zmm20 {%k5} -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa 32(%rsi), %xmm0 -; AVX512BW-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm18 = ymm18[0,1,2,3,6,7,7,6,8,9,10,11,14,15,15,14] -; AVX512BW-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm29 = ymm18[2,2,3,3,6,6,7,7] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm25, %ymm19, %ymm29 {%k4} -; AVX512BW-ONLY-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm19 = xmm21[0],xmm0[0],xmm21[1],xmm0[1],xmm21[2],xmm0[2],xmm21[3],xmm0[3],xmm21[4],xmm0[4],xmm21[5],xmm0[5],xmm21[6],xmm0[6],xmm21[7],xmm0[7] -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} xmm18 = <0,1,u,u,u,6,7,2,3,u,u,u,8,9,4,5> -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm18, %xmm19, %xmm19 -; AVX512BW-ONLY-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm19 = zmm29[2,3,2,3],zmm19[0,1,0,1] -; AVX512BW-ONLY-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm25 = xmm23[0],xmm28[0],xmm23[1],xmm28[1],xmm23[2],xmm28[2],xmm23[3],xmm28[3],xmm23[4],xmm28[4],xmm23[5],xmm28[5],xmm23[6],xmm28[6],xmm23[7],xmm28[7] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %ymm27, %ymm17, %ymm27 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} xmm17 = <4,5,0,1,u,u,u,6,7,2,3,u,u,u,8,9> -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm17, %xmm25, %xmm25 -; AVX512BW-ONLY-SLOW-NEXT: vpshufhw {{.*#+}} ymm16 = ymm16[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512BW-ONLY-SLOW-NEXT: vpshufd {{.*#+}} ymm16 = ymm16[0,2,3,3,4,6,7,7] -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %ymm16, %ymm27 {%k1} -; AVX512BW-ONLY-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm16 = zmm27[2,3,2,3],zmm25[0,1,0,1] -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm19, %zmm16 {%k2} -; AVX512BW-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm10 = ymm10[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,29],zero,ymm10[27],zero,zero,zero,zero,ymm10[30],zero,ymm10[28],zero,zero,zero,zero,ymm10[31],zero -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm10 = ymm10[2,3,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb {{.*#+}} ymm11 = ymm11[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm11[27],zero,zero,zero,zero,ymm11[30],zero,ymm11[28],zero,zero,zero,zero,ymm11[31],zero,ymm11[29] -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm11 = ymm11[2,3,2,3] -; AVX512BW-ONLY-SLOW-NEXT: vpor %ymm10, %ymm11, %ymm11 -; AVX512BW-ONLY-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm19 = xmm26[0],xmm24[0],xmm26[1],xmm24[1],xmm26[2],xmm24[2],xmm26[3],xmm24[3],xmm26[4],xmm24[4],xmm26[5],xmm24[5],xmm26[6],xmm24[6],xmm26[7],xmm24[7] -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} xmm10 = -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm10, %xmm19, %xmm19 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} ymm19 = ymm19[0,1,0,1] -; AVX512BW-ONLY-SLOW-NEXT: vinserti64x4 $1, %ymm19, %zmm11, %zmm11 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm19 = [14,13,14,15,15,14,14,15,14,13,14,15,15,14,14,15,17,17,16,16,17,17,16,16,20,21,17,17,17,17,16,16] -; AVX512BW-ONLY-SLOW-NEXT: vpermw %zmm22, %zmm19, %zmm19 -; AVX512BW-ONLY-SLOW-NEXT: movabsq $580999813345182728, %rax # imm = 0x810204081020408 -; AVX512BW-ONLY-SLOW-NEXT: kmovq %rax, %k1 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm19, %zmm11 {%k1} -; AVX512BW-ONLY-SLOW-NEXT: movabsq $1016749673354069774, %rax # imm = 0xE1C3870E1C3870E -; AVX512BW-ONLY-SLOW-NEXT: kmovq %rax, %k1 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm11, %zmm16 {%k1} -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} xmm19 = -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm19, %xmm28, %xmm11 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} xmm25 = -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm25, %xmm23, %xmm27 -; AVX512BW-ONLY-SLOW-NEXT: vporq %xmm11, %xmm27, %xmm11 -; AVX512BW-ONLY-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm23 = xmm28[8],xmm23[8],xmm28[9],xmm23[9],xmm28[10],xmm23[10],xmm28[11],xmm23[11],xmm28[12],xmm23[12],xmm28[13],xmm23[13],xmm28[14],xmm23[14],xmm28[15],xmm23[15] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm12, %xmm23, %xmm12 -; AVX512BW-ONLY-SLOW-NEXT: vinserti32x4 $2, %xmm12, %zmm11, %zmm11 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} xmm12 = -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm12, %xmm0, %xmm23 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} xmm27 = -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm27, %xmm21, %xmm28 -; AVX512BW-ONLY-SLOW-NEXT: vporq %xmm23, %xmm28, %xmm23 -; AVX512BW-ONLY-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm0 = xmm0[8],xmm21[8],xmm0[9],xmm21[9],xmm0[10],xmm21[10],xmm0[11],xmm21[11],xmm0[12],xmm21[12],xmm0[13],xmm21[13],xmm0[14],xmm21[14],xmm0[15],xmm21[15] -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} zmm21 = zmm11[0,1,0,1,4,5,4,5] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm13, %xmm0, %xmm0 -; AVX512BW-ONLY-SLOW-NEXT: vinserti32x4 $2, %xmm0, %zmm23, %zmm0 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} zmm11 = zmm0[0,1,0,1,4,5,4,5] -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm21, %zmm11 {%k3} -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} xmm0 = <128,4,u,u,u,128,7,128,5,u,u,u,128,8,128,6> -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm0, %xmm24, %xmm13 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm21 = [2,2,2,4,2,2,2,4,3,3,3,3,2,2,2,4,52,53,52,53,53,54,53,54,52,53,52,53,53,54,53,54] -; AVX512BW-ONLY-SLOW-NEXT: vpermi2w %zmm22, %zmm2, %zmm21 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa {{.*#+}} xmm2 = <4,128,u,u,u,7,128,5,128,u,u,u,8,128,6,128> -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm2, %xmm26, %xmm22 -; AVX512BW-ONLY-SLOW-NEXT: vporq %xmm13, %xmm22, %xmm13 -; AVX512BW-ONLY-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm22 = xmm26[8],xmm24[8],xmm26[9],xmm24[9],xmm26[10],xmm24[10],xmm26[11],xmm24[11],xmm26[12],xmm24[12],xmm26[13],xmm24[13],xmm26[14],xmm24[14],xmm26[15],xmm24[15] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb {{.*#+}} xmm22 = xmm22[u,6,7,2,3,u,u,u,8,9,4,5,u,u,u,10] -; AVX512BW-ONLY-SLOW-NEXT: vinserti32x4 $2, %xmm22, %zmm13, %zmm13 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} zmm13 = zmm13[0,1,0,1,4,5,4,5] -; AVX512BW-ONLY-SLOW-NEXT: movabsq $290499906672591364, %rax # imm = 0x408102040810204 -; AVX512BW-ONLY-SLOW-NEXT: kmovq %rax, %k1 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm21, %zmm13 {%k1} -; AVX512BW-ONLY-SLOW-NEXT: movabsq $-8714997200177740921, %rax # imm = 0x870E1C3870E1C387 -; AVX512BW-ONLY-SLOW-NEXT: kmovq %rax, %k1 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm13, %zmm11 {%k1} -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm19, %xmm6, %xmm13 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm25, %xmm5, %xmm19 -; AVX512BW-ONLY-SLOW-NEXT: vporq %xmm13, %xmm19, %xmm13 -; AVX512BW-ONLY-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm5 = xmm5[0],xmm6[0],xmm5[1],xmm6[1],xmm5[2],xmm6[2],xmm5[3],xmm6[3],xmm5[4],xmm6[4],xmm5[5],xmm6[5],xmm5[6],xmm6[6],xmm5[7],xmm6[7] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm17, %xmm5, %xmm5 -; AVX512BW-ONLY-SLOW-NEXT: vinserti32x4 $2, %xmm13, %zmm5, %zmm5 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm12, %xmm8, %xmm6 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm27, %xmm7, %xmm12 -; AVX512BW-ONLY-SLOW-NEXT: vpor %xmm6, %xmm12, %xmm6 -; AVX512BW-ONLY-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm7 = xmm7[0],xmm8[0],xmm7[1],xmm8[1],xmm7[2],xmm8[2],xmm7[3],xmm8[3],xmm7[4],xmm8[4],xmm7[5],xmm8[5],xmm7[6],xmm8[6],xmm7[7],xmm8[7] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm18, %xmm7, %xmm7 -; AVX512BW-ONLY-SLOW-NEXT: vinserti32x4 $2, %xmm6, %zmm7, %zmm6 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} zmm5 = zmm5[0,1,0,1,4,5,4,5] -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} zmm6 = zmm6[0,1,0,1,4,5,4,5] -; AVX512BW-ONLY-SLOW-NEXT: movabsq $871499720017774092, %rax # imm = 0xC183060C183060C -; AVX512BW-ONLY-SLOW-NEXT: kmovq %rax, %k1 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm5, %zmm6 {%k1} -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm0, %xmm4, %xmm0 -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm2, %xmm1, %xmm2 -; AVX512BW-ONLY-SLOW-NEXT: vpor %xmm0, %xmm2, %xmm0 -; AVX512BW-ONLY-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3],xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7] -; AVX512BW-ONLY-SLOW-NEXT: vpshufb %xmm10, %xmm1, %xmm1 -; AVX512BW-ONLY-SLOW-NEXT: vinserti32x4 $2, %xmm0, %zmm1, %zmm0 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm1 = [1,1,0,0,1,1,0,0,4,5,1,1,1,1,0,0,18,18,18,20,18,18,18,20,19,19,19,19,18,18,18,20] -; AVX512BW-ONLY-SLOW-NEXT: vpermw %zmm15, %zmm1, %zmm1 -; AVX512BW-ONLY-SLOW-NEXT: vpermq {{.*#+}} zmm0 = zmm0[0,1,0,1,4,5,4,5] -; AVX512BW-ONLY-SLOW-NEXT: movabsq $4647998506761461824, %rax # imm = 0x4081020408102040 -; AVX512BW-ONLY-SLOW-NEXT: kmovq %rax, %k1 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm1, %zmm0 {%k1} -; AVX512BW-ONLY-SLOW-NEXT: movabsq $8133997386832558192, %rax # imm = 0x70E1C3870E1C3870 -; AVX512BW-ONLY-SLOW-NEXT: kmovq %rax, %k1 -; AVX512BW-ONLY-SLOW-NEXT: vmovdqu8 %zmm0, %zmm6 {%k1} -; AVX512BW-ONLY-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 %zmm6, (%rax) -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 %zmm9, 320(%rax) -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 %zmm11, 256(%rax) -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 %zmm16, 192(%rax) -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 %zmm20, 128(%rax) -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 %zmm3, 64(%rax) -; AVX512BW-ONLY-SLOW-NEXT: vmovdqa64 %zmm14, 384(%rax) -; AVX512BW-ONLY-SLOW-NEXT: vzeroupper -; AVX512BW-ONLY-SLOW-NEXT: retq +; AVX512BW-SLOW-LABEL: store_i8_stride7_vf64: +; AVX512BW-SLOW: # %bb.0: +; AVX512BW-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512BW-SLOW-NEXT: vmovdqa (%rax), %ymm15 +; AVX512BW-SLOW-NEXT: vmovdqa 32(%rax), %ymm2 +; AVX512BW-SLOW-NEXT: vmovdqa {{.*#+}} ymm9 = [12,13,2,3,12,13,0,1,14,15,2,3,0,1,14,15,28,29,18,19,28,29,16,17,30,31,18,19,16,17,30,31] +; AVX512BW-SLOW-NEXT: vpshufb %ymm9, %ymm15, %ymm0 +; AVX512BW-SLOW-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [4,5,4,5,5,6,5,6,4,5,4,5,5,6,5,6] +; AVX512BW-SLOW-NEXT: # ymm1 = mem[0,1,0,1] +; AVX512BW-SLOW-NEXT: vpermw %ymm15, %ymm1, %ymm1 +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm3 +; AVX512BW-SLOW-NEXT: vmovdqa (%r9), %ymm10 +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm22 = [13,128,128,128,128,128,128,14,128,128,128,128,128,128,15,128,128,128,128,128,128,16,128,128,128,128,128,128,17,128,128,128] +; AVX512BW-SLOW-NEXT: vpshufb %ymm22, %ymm10, %ymm0 +; AVX512BW-SLOW-NEXT: vmovdqa (%r8), %ymm11 +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm23 = [128,128,128,128,128,128,14,128,128,128,128,128,128,15,128,128,128,128,128,128,16,128,128,128,128,128,128,17,128,128,128,128] +; AVX512BW-SLOW-NEXT: vpshufb %ymm23, %ymm11, %ymm1 +; AVX512BW-SLOW-NEXT: vpor %ymm0, %ymm1, %ymm5 +; AVX512BW-SLOW-NEXT: vmovdqa (%r9), %xmm4 +; AVX512BW-SLOW-NEXT: vmovdqa (%r8), %xmm1 +; AVX512BW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm6 = xmm1[8],xmm4[8],xmm1[9],xmm4[9],xmm1[10],xmm4[10],xmm1[11],xmm4[11],xmm1[12],xmm4[12],xmm1[13],xmm4[13],xmm1[14],xmm4[14],xmm1[15],xmm4[15] +; AVX512BW-SLOW-NEXT: vpshufb {{.*#+}} xmm6 = xmm6[u,6,7,2,3,u,u,u,8,9,4,5,u,u,u,10] +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm6 = ymm6[0,1,0,1] +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm5, %zmm6, %zmm20 +; AVX512BW-SLOW-NEXT: movabsq $2323999253380730912, %r10 # imm = 0x2040810204081020 +; AVX512BW-SLOW-NEXT: kmovq %r10, %k1 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm3, %zmm20 {%k1} +; AVX512BW-SLOW-NEXT: vmovdqa64 (%rdx), %ymm16 +; AVX512BW-SLOW-NEXT: vmovdqa {{.*#+}} ymm14 = [0,1,0,1,14,128,14,15,0,1,14,15,128,13,14,15,16,17,16,128,30,31,30,31,16,17,128,31,28,29,30,31] +; AVX512BW-SLOW-NEXT: vpshufb %ymm14, %ymm16, %ymm3 +; AVX512BW-SLOW-NEXT: vmovdqa64 (%rcx), %ymm17 +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm25 = [128,128,128,128,128,14,128,128,128,128,128,128,15,128,128,128,128,128,128,16,128,128,128,128,128,128,17,128,128,128,128,128] +; AVX512BW-SLOW-NEXT: vpshufb %ymm25, %ymm17, %ymm5 +; AVX512BW-SLOW-NEXT: vpor %ymm3, %ymm5, %ymm3 +; AVX512BW-SLOW-NEXT: vmovdqa (%rdx), %xmm5 +; AVX512BW-SLOW-NEXT: vmovdqa (%rcx), %xmm6 +; AVX512BW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm7 = xmm6[8],xmm5[8],xmm6[9],xmm5[9],xmm6[10],xmm5[10],xmm6[11],xmm5[11],xmm6[12],xmm5[12],xmm6[13],xmm5[13],xmm6[14],xmm5[14],xmm6[15],xmm5[15] +; AVX512BW-SLOW-NEXT: vmovdqa {{.*#+}} xmm12 = <6,3,2,u,u,u,9,8,5,4,u,u,u,11,10,7> +; AVX512BW-SLOW-NEXT: vpshufb %xmm12, %xmm7, %xmm7 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm7[0,1,0,1] +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm3, %zmm7, %zmm21 +; AVX512BW-SLOW-NEXT: vmovdqa64 (%rdi), %ymm18 +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm26 = [0,1,14,128,12,13,0,1,14,15,128,3,12,13,2,3,16,128,30,31,28,29,16,17,128,31,18,19,28,29,18,128] +; AVX512BW-SLOW-NEXT: vpshufb %ymm26, %ymm18, %ymm3 +; AVX512BW-SLOW-NEXT: vmovdqa64 (%rsi), %ymm19 +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm27 = [128,128,128,14,128,128,128,128,128,128,15,128,128,128,128,128,128,16,128,128,128,128,128,128,17,128,128,128,128,128,128,18] +; AVX512BW-SLOW-NEXT: vpshufb %ymm27, %ymm19, %ymm7 +; AVX512BW-SLOW-NEXT: vpor %ymm3, %ymm7, %ymm3 +; AVX512BW-SLOW-NEXT: vmovdqa (%rdi), %xmm7 +; AVX512BW-SLOW-NEXT: vmovdqa (%rsi), %xmm8 +; AVX512BW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm24 = xmm8[8],xmm7[8],xmm8[9],xmm7[9],xmm8[10],xmm7[10],xmm8[11],xmm7[11],xmm8[12],xmm7[12],xmm8[13],xmm7[13],xmm8[14],xmm7[14],xmm8[15],xmm7[15] +; AVX512BW-SLOW-NEXT: vmovdqa {{.*#+}} xmm13 = <2,u,u,u,9,8,5,4,u,u,u,11,10,7,6,u> +; AVX512BW-SLOW-NEXT: vpshufb %xmm13, %xmm24, %xmm24 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm24 = ymm24[0,1,0,1] +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm3, %zmm24, %zmm3 +; AVX512BW-SLOW-NEXT: movabsq $435749860008887046, %r10 # imm = 0x60C183060C18306 +; AVX512BW-SLOW-NEXT: kmovq %r10, %k1 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm21, %zmm3 {%k1} +; AVX512BW-SLOW-NEXT: movabsq $4066998693416279096, %r10 # imm = 0x3870E1C3870E1C38 +; AVX512BW-SLOW-NEXT: kmovq %r10, %k1 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm20, %zmm3 {%k1} +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm21 = [10,9,9,10,10,9,9,10,9,10,14,15,10,9,9,10,27,29,28,27,28,29,29,28,27,29,28,27,28,29,29,28] +; AVX512BW-SLOW-NEXT: vpermw %ymm2, %ymm21, %ymm20 +; AVX512BW-SLOW-NEXT: vpshufb %ymm9, %ymm2, %ymm9 +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm20, %zmm9, %zmm9 +; AVX512BW-SLOW-NEXT: vmovdqa64 32(%r9), %ymm20 +; AVX512BW-SLOW-NEXT: vpshufb %ymm22, %ymm20, %ymm24 +; AVX512BW-SLOW-NEXT: vmovdqa64 32(%r8), %ymm22 +; AVX512BW-SLOW-NEXT: vpshufb %ymm23, %ymm22, %ymm23 +; AVX512BW-SLOW-NEXT: vporq %ymm24, %ymm23, %ymm24 +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm23 = +; AVX512BW-SLOW-NEXT: vpshufb %ymm23, %ymm20, %ymm28 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm28 = ymm28[2,3,2,3] +; AVX512BW-SLOW-NEXT: vpshufb {{.*#+}} ymm29 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm22[20],zero,ymm22[18],zero,ymm22[20,21,20,21],zero,ymm22[19],zero,ymm22[19,20,21,22],zero +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm29 = ymm29[2,3,2,3] +; AVX512BW-SLOW-NEXT: vporq %ymm29, %ymm28, %ymm28 +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm28, %zmm24, %zmm28 +; AVX512BW-SLOW-NEXT: movabsq $145249953336295682, %r10 # imm = 0x204081020408102 +; AVX512BW-SLOW-NEXT: kmovq %r10, %k1 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm9, %zmm28 {%k1} +; AVX512BW-SLOW-NEXT: vmovdqa64 32(%rsi), %ymm29 +; AVX512BW-SLOW-NEXT: vmovdqa64 32(%rdi), %ymm30 +; AVX512BW-SLOW-NEXT: vpshuflw {{.*#+}} ymm9 = ymm30[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] +; AVX512BW-SLOW-NEXT: vpshufd {{.*#+}} ymm9 = ymm9[0,0,1,1,4,4,5,5] +; AVX512BW-SLOW-NEXT: vpbroadcastd {{.*#+}} ymm24 = [5,4,3,6,5,4,3,6,5,4,3,6,5,4,3,6,5,4,3,6,5,4,3,6,5,4,3,6,5,4,3,6] +; AVX512BW-SLOW-NEXT: movl $676341840, %r10d # imm = 0x28502850 +; AVX512BW-SLOW-NEXT: kmovd %r10d, %k1 +; AVX512BW-SLOW-NEXT: vpshufb %ymm24, %ymm29, %ymm9 {%k1} +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm9 = ymm9[2,3,2,3] +; AVX512BW-SLOW-NEXT: vpshufb %ymm26, %ymm30, %ymm26 +; AVX512BW-SLOW-NEXT: vpshufb %ymm27, %ymm29, %ymm27 +; AVX512BW-SLOW-NEXT: vporq %ymm26, %ymm27, %ymm26 +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm9, %zmm26, %zmm9 +; AVX512BW-SLOW-NEXT: vmovdqa64 32(%rdx), %ymm31 +; AVX512BW-SLOW-NEXT: vpshufb %ymm14, %ymm31, %ymm14 +; AVX512BW-SLOW-NEXT: vmovdqa 32(%rcx), %ymm0 +; AVX512BW-SLOW-NEXT: vpshufb %ymm25, %ymm0, %ymm25 +; AVX512BW-SLOW-NEXT: vporq %ymm14, %ymm25, %ymm14 +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm26 = +; AVX512BW-SLOW-NEXT: vpshufb %ymm26, %ymm0, %ymm25 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm25 = ymm25[2,3,2,3] +; AVX512BW-SLOW-NEXT: vpshufb {{.*#+}} ymm27 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm31[18],zero,ymm31[18,19,20,21],zero,ymm31[19],zero,ymm31[25,26,27,22],zero,ymm31[20],zero +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm27 = ymm27[2,3,2,3] +; AVX512BW-SLOW-NEXT: vporq %ymm27, %ymm25, %ymm25 +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm25, %zmm14, %zmm14 +; AVX512BW-SLOW-NEXT: movabsq $3485998880071096368, %r10 # imm = 0x3060C183060C1830 +; AVX512BW-SLOW-NEXT: kmovq %r10, %k2 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm14, %zmm9 {%k2} +; AVX512BW-SLOW-NEXT: movabsq $-4357498600088870461, %r10 # imm = 0xC3870E1C3870E1C3 +; AVX512BW-SLOW-NEXT: kmovq %r10, %k3 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm28, %zmm9 {%k3} +; AVX512BW-SLOW-NEXT: vpshufhw {{.*#+}} ymm14 = ymm30[0,1,2,3,6,7,7,6,8,9,10,11,14,15,15,14] +; AVX512BW-SLOW-NEXT: vpshufd {{.*#+}} ymm14 = ymm14[2,2,3,3,6,6,7,7] +; AVX512BW-SLOW-NEXT: vpbroadcastd {{.*#+}} ymm25 = [13,12,15,14,13,12,15,14,13,12,15,14,13,12,15,14,13,12,15,14,13,12,15,14,13,12,15,14,13,12,15,14] +; AVX512BW-SLOW-NEXT: movl $338170920, %r10d # imm = 0x14281428 +; AVX512BW-SLOW-NEXT: kmovd %r10d, %k4 +; AVX512BW-SLOW-NEXT: vpshufb %ymm25, %ymm29, %ymm14 {%k4} +; AVX512BW-SLOW-NEXT: vbroadcasti32x4 {{.*#+}} ymm28 = [25,128,23,128,128,128,128,26,128,24,128,128,128,128,27,128,25,128,23,128,128,128,128,26,128,24,128,128,128,128,27,128] +; AVX512BW-SLOW-NEXT: # ymm28 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-SLOW-NEXT: vpshufb %ymm28, %ymm29, %ymm27 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm27 = ymm27[2,3,2,3] +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm29 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,23,128,128,128,128,26,128,24,128,128,128,128,27,128,25] +; AVX512BW-SLOW-NEXT: vpshufb %ymm29, %ymm30, %ymm30 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm30 = ymm30[2,3,2,3] +; AVX512BW-SLOW-NEXT: vporq %ymm27, %ymm30, %ymm27 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm14 = ymm14[2,3,2,3] +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm14, %zmm27, %zmm14 +; AVX512BW-SLOW-NEXT: vpshufb {{.*#+}} ymm27 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm31[24,25],zero,ymm31[23],zero,ymm31[21,22,23,26],zero,ymm31[24],zero,ymm31[28,29,26,27] +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm27 = ymm27[2,3,2,3] +; AVX512BW-SLOW-NEXT: vpshufb {{.*#+}} ymm30 = ymm0[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm0[25],zero,ymm0[23],zero,zero,zero,zero,ymm0[26],zero,ymm0[24],zero,zero,zero,zero +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm30 = ymm30[2,3,2,3] +; AVX512BW-SLOW-NEXT: vporq %ymm27, %ymm30, %ymm30 +; AVX512BW-SLOW-NEXT: vpbroadcastq {{.*#+}} ymm27 = [11,0,0,0,15,14,13,12,11,0,0,0,15,14,13,12,11,0,0,0,15,14,13,12,11,0,0,0,15,14,13,12] +; AVX512BW-SLOW-NEXT: vpshufb %ymm27, %ymm0, %ymm0 +; AVX512BW-SLOW-NEXT: vpshufhw {{.*#+}} ymm31 = ymm31[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] +; AVX512BW-SLOW-NEXT: vpshufd {{.*#+}} ymm31 = ymm31[0,2,3,3,4,6,7,7] +; AVX512BW-SLOW-NEXT: vmovdqu8 %ymm31, %ymm0 {%k1} +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,3,2,3] +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm0, %zmm30, %zmm0 +; AVX512BW-SLOW-NEXT: vmovdqa64 (%r8), %zmm30 +; AVX512BW-SLOW-NEXT: movabsq $1742999440035548184, %r10 # imm = 0x183060C183060C18 +; AVX512BW-SLOW-NEXT: kmovq %r10, %k3 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm0, %zmm14 {%k3} +; AVX512BW-SLOW-NEXT: vmovdqa64 (%r9), %zmm0 +; AVX512BW-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm22 = zmm22[0,1,2,3],zmm0[4,5,6,7] +; AVX512BW-SLOW-NEXT: vpshufb {{.*#+}} zmm22 = zmm22[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,24,25,24,25],zero,zmm22[23],zero,zmm22[23,24,25,26],zero,zmm22[24],zero,zmm22[30,31,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,61],zero,zmm22[59],zero,zero,zero,zero,zmm22[62],zero,zmm22[60],zero,zero,zero,zero,zmm22[63],zero +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} zmm22 = zmm22[2,3,2,3,6,7,6,7] +; AVX512BW-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm20 = zmm20[0,1,2,3],zmm30[4,5,6,7] +; AVX512BW-SLOW-NEXT: vpshufb {{.*#+}} zmm20 = zmm20[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,zmm20[25],zero,zmm20[23],zero,zero,zero,zero,zmm20[26],zero,zmm20[24],zero,zero,zmm20[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zmm20[59],zero,zero,zero,zero,zmm20[62],zero,zmm20[60],zero,zero,zero,zero,zmm20[63],zero,zmm20[61] +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} zmm20 = zmm20[2,3,2,3,6,7,6,7] +; AVX512BW-SLOW-NEXT: vporq %zmm22, %zmm20, %zmm20 +; AVX512BW-SLOW-NEXT: vmovdqa64 (%rax), %zmm22 +; AVX512BW-SLOW-NEXT: movabsq $6971997760142192736, %rax # imm = 0x60C183060C183060 +; AVX512BW-SLOW-NEXT: kmovq %rax, %k3 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm20, %zmm14 {%k3} +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm20 = [11,13,12,11,12,13,13,12,11,13,12,11,12,13,13,12,62,61,62,63,63,62,62,63,62,61,62,63,63,62,62,63] +; AVX512BW-SLOW-NEXT: vpermi2w %zmm22, %zmm2, %zmm20 +; AVX512BW-SLOW-NEXT: movabsq $-9150747060186627967, %rax # imm = 0x8102040810204081 +; AVX512BW-SLOW-NEXT: kmovq %rax, %k5 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm20, %zmm14 {%k5} +; AVX512BW-SLOW-NEXT: vpshuflw {{.*#+}} ymm20 = ymm18[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] +; AVX512BW-SLOW-NEXT: vpshufd {{.*#+}} ymm20 = ymm20[0,0,1,1,4,4,5,5] +; AVX512BW-SLOW-NEXT: vpshufb %ymm24, %ymm19, %ymm20 {%k1} +; AVX512BW-SLOW-NEXT: vpshufb %ymm28, %ymm19, %ymm24 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm24 = ymm24[2,3,2,3] +; AVX512BW-SLOW-NEXT: vpshufb %ymm29, %ymm18, %ymm28 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm28 = ymm28[2,3,2,3] +; AVX512BW-SLOW-NEXT: vporq %ymm24, %ymm28, %ymm24 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm20 = ymm20[2,3,2,3] +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm24, %zmm20, %zmm28 +; AVX512BW-SLOW-NEXT: vmovdqa64 (%rcx), %zmm20 +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm17, %zmm20, %zmm20 +; AVX512BW-SLOW-NEXT: vpshufb %zmm26, %zmm20, %zmm20 +; AVX512BW-SLOW-NEXT: vmovdqa64 (%rdx), %zmm24 +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm16, %zmm24, %zmm24 +; AVX512BW-SLOW-NEXT: vpshufb {{.*#+}} zmm24 = zmm24[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18],zero,zmm24[18,19,20,21],zero,zmm24[19],zero,zmm24[25,26,27,22],zero,zmm24[20],zero,zmm24[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,56,57],zero,zmm24[55],zero,zmm24[53,54,55,58],zero,zmm24[56],zero,zmm24[60,61,58,59] +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} zmm24 = zmm24[2,3,2,3,6,7,6,7] +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} zmm20 = zmm20[2,3,2,3,6,7,6,7] +; AVX512BW-SLOW-NEXT: vporq %zmm24, %zmm20, %zmm20 +; AVX512BW-SLOW-NEXT: vmovdqa64 32(%r9), %xmm24 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm28, %zmm20 {%k3} +; AVX512BW-SLOW-NEXT: vmovdqa64 32(%r8), %xmm26 +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm10, %zmm0, %zmm0 +; AVX512BW-SLOW-NEXT: vpshufb %zmm23, %zmm0, %zmm0 +; AVX512BW-SLOW-NEXT: vmovdqa64 32(%rdx), %xmm23 +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm11, %zmm30, %zmm28 +; AVX512BW-SLOW-NEXT: vpshufb {{.*#+}} zmm28 = zmm28[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,20],zero,zmm28[18],zero,zmm28[20,21,20,21],zero,zmm28[19],zero,zmm28[19,20,21,22],zero,zmm28[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,56,57,56,57],zero,zmm28[55],zero,zmm28[55,56,57,58],zero,zmm28[56],zero,zmm28[62,63] +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} zmm28 = zmm28[2,3,2,3,6,7,6,7] +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} zmm0 = zmm0[2,3,2,3,6,7,6,7] +; AVX512BW-SLOW-NEXT: vporq %zmm28, %zmm0, %zmm0 +; AVX512BW-SLOW-NEXT: vmovdqa64 32(%rcx), %xmm28 +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm15, %zmm22, %zmm15 +; AVX512BW-SLOW-NEXT: vpermw %zmm15, %zmm21, %zmm21 +; AVX512BW-SLOW-NEXT: movabsq $1161999626690365456, %rax # imm = 0x1020408102040810 +; AVX512BW-SLOW-NEXT: kmovq %rax, %k5 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm21, %zmm0 {%k5} +; AVX512BW-SLOW-NEXT: vmovdqa64 32(%rdi), %xmm21 +; AVX512BW-SLOW-NEXT: movabsq $2033499346708139548, %rax # imm = 0x1C3870E1C3870E1C +; AVX512BW-SLOW-NEXT: kmovq %rax, %k5 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm0, %zmm20 {%k5} +; AVX512BW-SLOW-NEXT: vmovdqa 32(%rsi), %xmm0 +; AVX512BW-SLOW-NEXT: vpshufhw {{.*#+}} ymm18 = ymm18[0,1,2,3,6,7,7,6,8,9,10,11,14,15,15,14] +; AVX512BW-SLOW-NEXT: vpshufd {{.*#+}} ymm29 = ymm18[2,2,3,3,6,6,7,7] +; AVX512BW-SLOW-NEXT: vpshufb %ymm25, %ymm19, %ymm29 {%k4} +; AVX512BW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm19 = xmm21[0],xmm0[0],xmm21[1],xmm0[1],xmm21[2],xmm0[2],xmm21[3],xmm0[3],xmm21[4],xmm0[4],xmm21[5],xmm0[5],xmm21[6],xmm0[6],xmm21[7],xmm0[7] +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} xmm18 = <0,1,u,u,u,6,7,2,3,u,u,u,8,9,4,5> +; AVX512BW-SLOW-NEXT: vpshufb %xmm18, %xmm19, %xmm19 +; AVX512BW-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm19 = zmm29[2,3,2,3],zmm19[0,1,0,1] +; AVX512BW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm25 = xmm23[0],xmm28[0],xmm23[1],xmm28[1],xmm23[2],xmm28[2],xmm23[3],xmm28[3],xmm23[4],xmm28[4],xmm23[5],xmm28[5],xmm23[6],xmm28[6],xmm23[7],xmm28[7] +; AVX512BW-SLOW-NEXT: vpshufb %ymm27, %ymm17, %ymm27 +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} xmm17 = <4,5,0,1,u,u,u,6,7,2,3,u,u,u,8,9> +; AVX512BW-SLOW-NEXT: vpshufb %xmm17, %xmm25, %xmm25 +; AVX512BW-SLOW-NEXT: vpshufhw {{.*#+}} ymm16 = ymm16[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] +; AVX512BW-SLOW-NEXT: vpshufd {{.*#+}} ymm16 = ymm16[0,2,3,3,4,6,7,7] +; AVX512BW-SLOW-NEXT: vmovdqu8 %ymm16, %ymm27 {%k1} +; AVX512BW-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm16 = zmm27[2,3,2,3],zmm25[0,1,0,1] +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm19, %zmm16 {%k2} +; AVX512BW-SLOW-NEXT: vpshufb {{.*#+}} ymm10 = ymm10[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,29],zero,ymm10[27],zero,zero,zero,zero,ymm10[30],zero,ymm10[28],zero,zero,zero,zero,ymm10[31],zero +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm10 = ymm10[2,3,2,3] +; AVX512BW-SLOW-NEXT: vpshufb {{.*#+}} ymm11 = ymm11[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm11[27],zero,zero,zero,zero,ymm11[30],zero,ymm11[28],zero,zero,zero,zero,ymm11[31],zero,ymm11[29] +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm11 = ymm11[2,3,2,3] +; AVX512BW-SLOW-NEXT: vpor %ymm10, %ymm11, %ymm11 +; AVX512BW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm19 = xmm26[0],xmm24[0],xmm26[1],xmm24[1],xmm26[2],xmm24[2],xmm26[3],xmm24[3],xmm26[4],xmm24[4],xmm26[5],xmm24[5],xmm26[6],xmm24[6],xmm26[7],xmm24[7] +; AVX512BW-SLOW-NEXT: vmovdqa {{.*#+}} xmm10 = +; AVX512BW-SLOW-NEXT: vpshufb %xmm10, %xmm19, %xmm19 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm19 = ymm19[0,1,0,1] +; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm19, %zmm11, %zmm11 +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm19 = [14,13,14,15,15,14,14,15,14,13,14,15,15,14,14,15,17,17,16,16,17,17,16,16,20,21,17,17,17,17,16,16] +; AVX512BW-SLOW-NEXT: vpermw %zmm22, %zmm19, %zmm19 +; AVX512BW-SLOW-NEXT: movabsq $580999813345182728, %rax # imm = 0x810204081020408 +; AVX512BW-SLOW-NEXT: kmovq %rax, %k1 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm19, %zmm11 {%k1} +; AVX512BW-SLOW-NEXT: movabsq $1016749673354069774, %rax # imm = 0xE1C3870E1C3870E +; AVX512BW-SLOW-NEXT: kmovq %rax, %k1 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm11, %zmm16 {%k1} +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} xmm19 = +; AVX512BW-SLOW-NEXT: vpshufb %xmm19, %xmm28, %xmm11 +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} xmm25 = +; AVX512BW-SLOW-NEXT: vpshufb %xmm25, %xmm23, %xmm27 +; AVX512BW-SLOW-NEXT: vporq %xmm11, %xmm27, %xmm11 +; AVX512BW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm23 = xmm28[8],xmm23[8],xmm28[9],xmm23[9],xmm28[10],xmm23[10],xmm28[11],xmm23[11],xmm28[12],xmm23[12],xmm28[13],xmm23[13],xmm28[14],xmm23[14],xmm28[15],xmm23[15] +; AVX512BW-SLOW-NEXT: vpshufb %xmm12, %xmm23, %xmm12 +; AVX512BW-SLOW-NEXT: vinserti32x4 $2, %xmm12, %zmm11, %zmm11 +; AVX512BW-SLOW-NEXT: vmovdqa {{.*#+}} xmm12 = +; AVX512BW-SLOW-NEXT: vpshufb %xmm12, %xmm0, %xmm23 +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} xmm27 = +; AVX512BW-SLOW-NEXT: vpshufb %xmm27, %xmm21, %xmm28 +; AVX512BW-SLOW-NEXT: vporq %xmm23, %xmm28, %xmm23 +; AVX512BW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm0 = xmm0[8],xmm21[8],xmm0[9],xmm21[9],xmm0[10],xmm21[10],xmm0[11],xmm21[11],xmm0[12],xmm21[12],xmm0[13],xmm21[13],xmm0[14],xmm21[14],xmm0[15],xmm21[15] +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} zmm21 = zmm11[0,1,0,1,4,5,4,5] +; AVX512BW-SLOW-NEXT: vpshufb %xmm13, %xmm0, %xmm0 +; AVX512BW-SLOW-NEXT: vinserti32x4 $2, %xmm0, %zmm23, %zmm0 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} zmm11 = zmm0[0,1,0,1,4,5,4,5] +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm21, %zmm11 {%k3} +; AVX512BW-SLOW-NEXT: vmovdqa {{.*#+}} xmm0 = <128,4,u,u,u,128,7,128,5,u,u,u,128,8,128,6> +; AVX512BW-SLOW-NEXT: vpshufb %xmm0, %xmm24, %xmm13 +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm21 = [2,2,2,4,2,2,2,4,3,3,3,3,2,2,2,4,52,53,52,53,53,54,53,54,52,53,52,53,53,54,53,54] +; AVX512BW-SLOW-NEXT: vpermi2w %zmm22, %zmm2, %zmm21 +; AVX512BW-SLOW-NEXT: vmovdqa {{.*#+}} xmm2 = <4,128,u,u,u,7,128,5,128,u,u,u,8,128,6,128> +; AVX512BW-SLOW-NEXT: vpshufb %xmm2, %xmm26, %xmm22 +; AVX512BW-SLOW-NEXT: vporq %xmm13, %xmm22, %xmm13 +; AVX512BW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm22 = xmm26[8],xmm24[8],xmm26[9],xmm24[9],xmm26[10],xmm24[10],xmm26[11],xmm24[11],xmm26[12],xmm24[12],xmm26[13],xmm24[13],xmm26[14],xmm24[14],xmm26[15],xmm24[15] +; AVX512BW-SLOW-NEXT: vpshufb {{.*#+}} xmm22 = xmm22[u,6,7,2,3,u,u,u,8,9,4,5,u,u,u,10] +; AVX512BW-SLOW-NEXT: vinserti32x4 $2, %xmm22, %zmm13, %zmm13 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} zmm13 = zmm13[0,1,0,1,4,5,4,5] +; AVX512BW-SLOW-NEXT: movabsq $290499906672591364, %rax # imm = 0x408102040810204 +; AVX512BW-SLOW-NEXT: kmovq %rax, %k1 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm21, %zmm13 {%k1} +; AVX512BW-SLOW-NEXT: movabsq $-8714997200177740921, %rax # imm = 0x870E1C3870E1C387 +; AVX512BW-SLOW-NEXT: kmovq %rax, %k1 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm13, %zmm11 {%k1} +; AVX512BW-SLOW-NEXT: vpshufb %xmm19, %xmm6, %xmm13 +; AVX512BW-SLOW-NEXT: vpshufb %xmm25, %xmm5, %xmm19 +; AVX512BW-SLOW-NEXT: vporq %xmm13, %xmm19, %xmm13 +; AVX512BW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm5 = xmm5[0],xmm6[0],xmm5[1],xmm6[1],xmm5[2],xmm6[2],xmm5[3],xmm6[3],xmm5[4],xmm6[4],xmm5[5],xmm6[5],xmm5[6],xmm6[6],xmm5[7],xmm6[7] +; AVX512BW-SLOW-NEXT: vpshufb %xmm17, %xmm5, %xmm5 +; AVX512BW-SLOW-NEXT: vinserti32x4 $2, %xmm13, %zmm5, %zmm5 +; AVX512BW-SLOW-NEXT: vpshufb %xmm12, %xmm8, %xmm6 +; AVX512BW-SLOW-NEXT: vpshufb %xmm27, %xmm7, %xmm12 +; AVX512BW-SLOW-NEXT: vpor %xmm6, %xmm12, %xmm6 +; AVX512BW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm7 = xmm7[0],xmm8[0],xmm7[1],xmm8[1],xmm7[2],xmm8[2],xmm7[3],xmm8[3],xmm7[4],xmm8[4],xmm7[5],xmm8[5],xmm7[6],xmm8[6],xmm7[7],xmm8[7] +; AVX512BW-SLOW-NEXT: vpshufb %xmm18, %xmm7, %xmm7 +; AVX512BW-SLOW-NEXT: vinserti32x4 $2, %xmm6, %zmm7, %zmm6 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} zmm5 = zmm5[0,1,0,1,4,5,4,5] +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} zmm6 = zmm6[0,1,0,1,4,5,4,5] +; AVX512BW-SLOW-NEXT: movabsq $871499720017774092, %rax # imm = 0xC183060C183060C +; AVX512BW-SLOW-NEXT: kmovq %rax, %k1 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm5, %zmm6 {%k1} +; AVX512BW-SLOW-NEXT: vpshufb %xmm0, %xmm4, %xmm0 +; AVX512BW-SLOW-NEXT: vpshufb %xmm2, %xmm1, %xmm2 +; AVX512BW-SLOW-NEXT: vpor %xmm0, %xmm2, %xmm0 +; AVX512BW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3],xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7] +; AVX512BW-SLOW-NEXT: vpshufb %xmm10, %xmm1, %xmm1 +; AVX512BW-SLOW-NEXT: vinserti32x4 $2, %xmm0, %zmm1, %zmm0 +; AVX512BW-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm1 = [1,1,0,0,1,1,0,0,4,5,1,1,1,1,0,0,18,18,18,20,18,18,18,20,19,19,19,19,18,18,18,20] +; AVX512BW-SLOW-NEXT: vpermw %zmm15, %zmm1, %zmm1 +; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} zmm0 = zmm0[0,1,0,1,4,5,4,5] +; AVX512BW-SLOW-NEXT: movabsq $4647998506761461824, %rax # imm = 0x4081020408102040 +; AVX512BW-SLOW-NEXT: kmovq %rax, %k1 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm1, %zmm0 {%k1} +; AVX512BW-SLOW-NEXT: movabsq $8133997386832558192, %rax # imm = 0x70E1C3870E1C3870 +; AVX512BW-SLOW-NEXT: kmovq %rax, %k1 +; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm0, %zmm6 {%k1} +; AVX512BW-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512BW-SLOW-NEXT: vmovdqa64 %zmm6, (%rax) +; AVX512BW-SLOW-NEXT: vmovdqa64 %zmm9, 320(%rax) +; AVX512BW-SLOW-NEXT: vmovdqa64 %zmm11, 256(%rax) +; AVX512BW-SLOW-NEXT: vmovdqa64 %zmm16, 192(%rax) +; AVX512BW-SLOW-NEXT: vmovdqa64 %zmm20, 128(%rax) +; AVX512BW-SLOW-NEXT: vmovdqa64 %zmm3, 64(%rax) +; AVX512BW-SLOW-NEXT: vmovdqa64 %zmm14, 384(%rax) +; AVX512BW-SLOW-NEXT: vzeroupper +; AVX512BW-SLOW-NEXT: retq ; ; AVX512BW-FAST-LABEL: store_i8_stride7_vf64: ; AVX512BW-FAST: # %bb.0: @@ -9319,320 +8727,6 @@ define void @store_i8_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec ; AVX512BW-FAST-NEXT: addq $200, %rsp ; AVX512BW-FAST-NEXT: vzeroupper ; AVX512BW-FAST-NEXT: retq -; -; AVX512DQBW-SLOW-LABEL: store_i8_stride7_vf64: -; AVX512DQBW-SLOW: # %bb.0: -; AVX512DQBW-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQBW-SLOW-NEXT: vmovdqa (%rax), %ymm15 -; AVX512DQBW-SLOW-NEXT: vmovdqa 32(%rax), %ymm2 -; AVX512DQBW-SLOW-NEXT: vmovdqa {{.*#+}} ymm9 = [12,13,2,3,12,13,0,1,14,15,2,3,0,1,14,15,28,29,18,19,28,29,16,17,30,31,18,19,16,17,30,31] -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm9, %ymm15, %ymm0 -; AVX512DQBW-SLOW-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [4,5,4,5,5,6,5,6,4,5,4,5,5,6,5,6] -; AVX512DQBW-SLOW-NEXT: # ymm1 = mem[0,1,0,1] -; AVX512DQBW-SLOW-NEXT: vpermw %ymm15, %ymm1, %ymm1 -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm3 -; AVX512DQBW-SLOW-NEXT: vmovdqa (%r9), %ymm10 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm22 = [13,128,128,128,128,128,128,14,128,128,128,128,128,128,15,128,128,128,128,128,128,16,128,128,128,128,128,128,17,128,128,128] -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm22, %ymm10, %ymm0 -; AVX512DQBW-SLOW-NEXT: vmovdqa (%r8), %ymm11 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm23 = [128,128,128,128,128,128,14,128,128,128,128,128,128,15,128,128,128,128,128,128,16,128,128,128,128,128,128,17,128,128,128,128] -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm23, %ymm11, %ymm1 -; AVX512DQBW-SLOW-NEXT: vpor %ymm0, %ymm1, %ymm5 -; AVX512DQBW-SLOW-NEXT: vmovdqa (%r9), %xmm4 -; AVX512DQBW-SLOW-NEXT: vmovdqa (%r8), %xmm1 -; AVX512DQBW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm6 = xmm1[8],xmm4[8],xmm1[9],xmm4[9],xmm1[10],xmm4[10],xmm1[11],xmm4[11],xmm1[12],xmm4[12],xmm1[13],xmm4[13],xmm1[14],xmm4[14],xmm1[15],xmm4[15] -; AVX512DQBW-SLOW-NEXT: vpshufb {{.*#+}} xmm6 = xmm6[u,6,7,2,3,u,u,u,8,9,4,5,u,u,u,10] -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm6 = ymm6[0,1,0,1] -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm5, %zmm6, %zmm20 -; AVX512DQBW-SLOW-NEXT: movabsq $2323999253380730912, %r10 # imm = 0x2040810204081020 -; AVX512DQBW-SLOW-NEXT: kmovq %r10, %k1 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm3, %zmm20 {%k1} -; AVX512DQBW-SLOW-NEXT: vmovdqa64 (%rdx), %ymm16 -; AVX512DQBW-SLOW-NEXT: vmovdqa {{.*#+}} ymm14 = [0,1,0,1,14,128,14,15,0,1,14,15,128,13,14,15,16,17,16,128,30,31,30,31,16,17,128,31,28,29,30,31] -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm14, %ymm16, %ymm3 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 (%rcx), %ymm17 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm25 = [128,128,128,128,128,14,128,128,128,128,128,128,15,128,128,128,128,128,128,16,128,128,128,128,128,128,17,128,128,128,128,128] -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm25, %ymm17, %ymm5 -; AVX512DQBW-SLOW-NEXT: vpor %ymm3, %ymm5, %ymm3 -; AVX512DQBW-SLOW-NEXT: vmovdqa (%rdx), %xmm5 -; AVX512DQBW-SLOW-NEXT: vmovdqa (%rcx), %xmm6 -; AVX512DQBW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm7 = xmm6[8],xmm5[8],xmm6[9],xmm5[9],xmm6[10],xmm5[10],xmm6[11],xmm5[11],xmm6[12],xmm5[12],xmm6[13],xmm5[13],xmm6[14],xmm5[14],xmm6[15],xmm5[15] -; AVX512DQBW-SLOW-NEXT: vmovdqa {{.*#+}} xmm12 = <6,3,2,u,u,u,9,8,5,4,u,u,u,11,10,7> -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm12, %xmm7, %xmm7 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm7 = ymm7[0,1,0,1] -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm3, %zmm7, %zmm21 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 (%rdi), %ymm18 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm26 = [0,1,14,128,12,13,0,1,14,15,128,3,12,13,2,3,16,128,30,31,28,29,16,17,128,31,18,19,28,29,18,128] -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm26, %ymm18, %ymm3 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 (%rsi), %ymm19 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm27 = [128,128,128,14,128,128,128,128,128,128,15,128,128,128,128,128,128,16,128,128,128,128,128,128,17,128,128,128,128,128,128,18] -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm27, %ymm19, %ymm7 -; AVX512DQBW-SLOW-NEXT: vpor %ymm3, %ymm7, %ymm3 -; AVX512DQBW-SLOW-NEXT: vmovdqa (%rdi), %xmm7 -; AVX512DQBW-SLOW-NEXT: vmovdqa (%rsi), %xmm8 -; AVX512DQBW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm24 = xmm8[8],xmm7[8],xmm8[9],xmm7[9],xmm8[10],xmm7[10],xmm8[11],xmm7[11],xmm8[12],xmm7[12],xmm8[13],xmm7[13],xmm8[14],xmm7[14],xmm8[15],xmm7[15] -; AVX512DQBW-SLOW-NEXT: vmovdqa {{.*#+}} xmm13 = <2,u,u,u,9,8,5,4,u,u,u,11,10,7,6,u> -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm13, %xmm24, %xmm24 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm24 = ymm24[0,1,0,1] -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm3, %zmm24, %zmm3 -; AVX512DQBW-SLOW-NEXT: movabsq $435749860008887046, %r10 # imm = 0x60C183060C18306 -; AVX512DQBW-SLOW-NEXT: kmovq %r10, %k1 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm21, %zmm3 {%k1} -; AVX512DQBW-SLOW-NEXT: movabsq $4066998693416279096, %r10 # imm = 0x3870E1C3870E1C38 -; AVX512DQBW-SLOW-NEXT: kmovq %r10, %k1 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm20, %zmm3 {%k1} -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm21 = [10,9,9,10,10,9,9,10,9,10,14,15,10,9,9,10,27,29,28,27,28,29,29,28,27,29,28,27,28,29,29,28] -; AVX512DQBW-SLOW-NEXT: vpermw %ymm2, %ymm21, %ymm20 -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm9, %ymm2, %ymm9 -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm20, %zmm9, %zmm9 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 32(%r9), %ymm20 -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm22, %ymm20, %ymm24 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 32(%r8), %ymm22 -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm23, %ymm22, %ymm23 -; AVX512DQBW-SLOW-NEXT: vporq %ymm24, %ymm23, %ymm24 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm23 = -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm23, %ymm20, %ymm28 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm28 = ymm28[2,3,2,3] -; AVX512DQBW-SLOW-NEXT: vpshufb {{.*#+}} ymm29 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm22[20],zero,ymm22[18],zero,ymm22[20,21,20,21],zero,ymm22[19],zero,ymm22[19,20,21,22],zero -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm29 = ymm29[2,3,2,3] -; AVX512DQBW-SLOW-NEXT: vporq %ymm29, %ymm28, %ymm28 -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm28, %zmm24, %zmm28 -; AVX512DQBW-SLOW-NEXT: movabsq $145249953336295682, %r10 # imm = 0x204081020408102 -; AVX512DQBW-SLOW-NEXT: kmovq %r10, %k1 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm9, %zmm28 {%k1} -; AVX512DQBW-SLOW-NEXT: vmovdqa64 32(%rsi), %ymm29 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 32(%rdi), %ymm30 -; AVX512DQBW-SLOW-NEXT: vpshuflw {{.*#+}} ymm9 = ymm30[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512DQBW-SLOW-NEXT: vpshufd {{.*#+}} ymm9 = ymm9[0,0,1,1,4,4,5,5] -; AVX512DQBW-SLOW-NEXT: vpbroadcastd {{.*#+}} ymm24 = [5,4,3,6,5,4,3,6,5,4,3,6,5,4,3,6,5,4,3,6,5,4,3,6,5,4,3,6,5,4,3,6] -; AVX512DQBW-SLOW-NEXT: movl $676341840, %r10d # imm = 0x28502850 -; AVX512DQBW-SLOW-NEXT: kmovd %r10d, %k1 -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm24, %ymm29, %ymm9 {%k1} -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm9 = ymm9[2,3,2,3] -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm26, %ymm30, %ymm26 -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm27, %ymm29, %ymm27 -; AVX512DQBW-SLOW-NEXT: vporq %ymm26, %ymm27, %ymm26 -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm9, %zmm26, %zmm9 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 32(%rdx), %ymm31 -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm14, %ymm31, %ymm14 -; AVX512DQBW-SLOW-NEXT: vmovdqa 32(%rcx), %ymm0 -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm25, %ymm0, %ymm25 -; AVX512DQBW-SLOW-NEXT: vporq %ymm14, %ymm25, %ymm14 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm26 = -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm26, %ymm0, %ymm25 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm25 = ymm25[2,3,2,3] -; AVX512DQBW-SLOW-NEXT: vpshufb {{.*#+}} ymm27 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm31[18],zero,ymm31[18,19,20,21],zero,ymm31[19],zero,ymm31[25,26,27,22],zero,ymm31[20],zero -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm27 = ymm27[2,3,2,3] -; AVX512DQBW-SLOW-NEXT: vporq %ymm27, %ymm25, %ymm25 -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm25, %zmm14, %zmm14 -; AVX512DQBW-SLOW-NEXT: movabsq $3485998880071096368, %r10 # imm = 0x3060C183060C1830 -; AVX512DQBW-SLOW-NEXT: kmovq %r10, %k2 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm14, %zmm9 {%k2} -; AVX512DQBW-SLOW-NEXT: movabsq $-4357498600088870461, %r10 # imm = 0xC3870E1C3870E1C3 -; AVX512DQBW-SLOW-NEXT: kmovq %r10, %k3 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm28, %zmm9 {%k3} -; AVX512DQBW-SLOW-NEXT: vpshufhw {{.*#+}} ymm14 = ymm30[0,1,2,3,6,7,7,6,8,9,10,11,14,15,15,14] -; AVX512DQBW-SLOW-NEXT: vpshufd {{.*#+}} ymm14 = ymm14[2,2,3,3,6,6,7,7] -; AVX512DQBW-SLOW-NEXT: vpbroadcastd {{.*#+}} ymm25 = [13,12,15,14,13,12,15,14,13,12,15,14,13,12,15,14,13,12,15,14,13,12,15,14,13,12,15,14,13,12,15,14] -; AVX512DQBW-SLOW-NEXT: movl $338170920, %r10d # imm = 0x14281428 -; AVX512DQBW-SLOW-NEXT: kmovd %r10d, %k4 -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm25, %ymm29, %ymm14 {%k4} -; AVX512DQBW-SLOW-NEXT: vbroadcasti64x2 {{.*#+}} ymm28 = [25,128,23,128,128,128,128,26,128,24,128,128,128,128,27,128,25,128,23,128,128,128,128,26,128,24,128,128,128,128,27,128] -; AVX512DQBW-SLOW-NEXT: # ymm28 = mem[0,1,0,1] -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm28, %ymm29, %ymm27 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm27 = ymm27[2,3,2,3] -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} ymm29 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,23,128,128,128,128,26,128,24,128,128,128,128,27,128,25] -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm29, %ymm30, %ymm30 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm30 = ymm30[2,3,2,3] -; AVX512DQBW-SLOW-NEXT: vporq %ymm27, %ymm30, %ymm27 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm14 = ymm14[2,3,2,3] -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm14, %zmm27, %zmm14 -; AVX512DQBW-SLOW-NEXT: vpshufb {{.*#+}} ymm27 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm31[24,25],zero,ymm31[23],zero,ymm31[21,22,23,26],zero,ymm31[24],zero,ymm31[28,29,26,27] -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm27 = ymm27[2,3,2,3] -; AVX512DQBW-SLOW-NEXT: vpshufb {{.*#+}} ymm30 = ymm0[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm0[25],zero,ymm0[23],zero,zero,zero,zero,ymm0[26],zero,ymm0[24],zero,zero,zero,zero -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm30 = ymm30[2,3,2,3] -; AVX512DQBW-SLOW-NEXT: vporq %ymm27, %ymm30, %ymm30 -; AVX512DQBW-SLOW-NEXT: vpbroadcastq {{.*#+}} ymm27 = [11,0,0,0,15,14,13,12,11,0,0,0,15,14,13,12,11,0,0,0,15,14,13,12,11,0,0,0,15,14,13,12] -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm27, %ymm0, %ymm0 -; AVX512DQBW-SLOW-NEXT: vpshufhw {{.*#+}} ymm31 = ymm31[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512DQBW-SLOW-NEXT: vpshufd {{.*#+}} ymm31 = ymm31[0,2,3,3,4,6,7,7] -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %ymm31, %ymm0 {%k1} -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,3,2,3] -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm0, %zmm30, %zmm0 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 (%r8), %zmm30 -; AVX512DQBW-SLOW-NEXT: movabsq $1742999440035548184, %r10 # imm = 0x183060C183060C18 -; AVX512DQBW-SLOW-NEXT: kmovq %r10, %k3 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm0, %zmm14 {%k3} -; AVX512DQBW-SLOW-NEXT: vmovdqa64 (%r9), %zmm0 -; AVX512DQBW-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm22 = zmm22[0,1,2,3],zmm0[4,5,6,7] -; AVX512DQBW-SLOW-NEXT: vpshufb {{.*#+}} zmm22 = zmm22[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,24,25,24,25],zero,zmm22[23],zero,zmm22[23,24,25,26],zero,zmm22[24],zero,zmm22[30,31,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,61],zero,zmm22[59],zero,zero,zero,zero,zmm22[62],zero,zmm22[60],zero,zero,zero,zero,zmm22[63],zero -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} zmm22 = zmm22[2,3,2,3,6,7,6,7] -; AVX512DQBW-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm20 = zmm20[0,1,2,3],zmm30[4,5,6,7] -; AVX512DQBW-SLOW-NEXT: vpshufb {{.*#+}} zmm20 = zmm20[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,zmm20[25],zero,zmm20[23],zero,zero,zero,zero,zmm20[26],zero,zmm20[24],zero,zero,zmm20[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zmm20[59],zero,zero,zero,zero,zmm20[62],zero,zmm20[60],zero,zero,zero,zero,zmm20[63],zero,zmm20[61] -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} zmm20 = zmm20[2,3,2,3,6,7,6,7] -; AVX512DQBW-SLOW-NEXT: vporq %zmm22, %zmm20, %zmm20 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 (%rax), %zmm22 -; AVX512DQBW-SLOW-NEXT: movabsq $6971997760142192736, %rax # imm = 0x60C183060C183060 -; AVX512DQBW-SLOW-NEXT: kmovq %rax, %k3 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm20, %zmm14 {%k3} -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm20 = [11,13,12,11,12,13,13,12,11,13,12,11,12,13,13,12,62,61,62,63,63,62,62,63,62,61,62,63,63,62,62,63] -; AVX512DQBW-SLOW-NEXT: vpermi2w %zmm22, %zmm2, %zmm20 -; AVX512DQBW-SLOW-NEXT: movabsq $-9150747060186627967, %rax # imm = 0x8102040810204081 -; AVX512DQBW-SLOW-NEXT: kmovq %rax, %k5 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm20, %zmm14 {%k5} -; AVX512DQBW-SLOW-NEXT: vpshuflw {{.*#+}} ymm20 = ymm18[1,2,2,3,4,5,6,7,9,10,10,11,12,13,14,15] -; AVX512DQBW-SLOW-NEXT: vpshufd {{.*#+}} ymm20 = ymm20[0,0,1,1,4,4,5,5] -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm24, %ymm19, %ymm20 {%k1} -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm28, %ymm19, %ymm24 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm24 = ymm24[2,3,2,3] -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm29, %ymm18, %ymm28 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm28 = ymm28[2,3,2,3] -; AVX512DQBW-SLOW-NEXT: vporq %ymm24, %ymm28, %ymm24 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm20 = ymm20[2,3,2,3] -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm24, %zmm20, %zmm28 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 (%rcx), %zmm20 -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm17, %zmm20, %zmm20 -; AVX512DQBW-SLOW-NEXT: vpshufb %zmm26, %zmm20, %zmm20 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 (%rdx), %zmm24 -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm16, %zmm24, %zmm24 -; AVX512DQBW-SLOW-NEXT: vpshufb {{.*#+}} zmm24 = zmm24[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18],zero,zmm24[18,19,20,21],zero,zmm24[19],zero,zmm24[25,26,27,22],zero,zmm24[20],zero,zmm24[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,56,57],zero,zmm24[55],zero,zmm24[53,54,55,58],zero,zmm24[56],zero,zmm24[60,61,58,59] -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} zmm24 = zmm24[2,3,2,3,6,7,6,7] -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} zmm20 = zmm20[2,3,2,3,6,7,6,7] -; AVX512DQBW-SLOW-NEXT: vporq %zmm24, %zmm20, %zmm20 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 32(%r9), %xmm24 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm28, %zmm20 {%k3} -; AVX512DQBW-SLOW-NEXT: vmovdqa64 32(%r8), %xmm26 -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm10, %zmm0, %zmm0 -; AVX512DQBW-SLOW-NEXT: vpshufb %zmm23, %zmm0, %zmm0 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 32(%rdx), %xmm23 -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm11, %zmm30, %zmm28 -; AVX512DQBW-SLOW-NEXT: vpshufb {{.*#+}} zmm28 = zmm28[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,20],zero,zmm28[18],zero,zmm28[20,21,20,21],zero,zmm28[19],zero,zmm28[19,20,21,22],zero,zmm28[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,56,57,56,57],zero,zmm28[55],zero,zmm28[55,56,57,58],zero,zmm28[56],zero,zmm28[62,63] -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} zmm28 = zmm28[2,3,2,3,6,7,6,7] -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} zmm0 = zmm0[2,3,2,3,6,7,6,7] -; AVX512DQBW-SLOW-NEXT: vporq %zmm28, %zmm0, %zmm0 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 32(%rcx), %xmm28 -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm15, %zmm22, %zmm15 -; AVX512DQBW-SLOW-NEXT: vpermw %zmm15, %zmm21, %zmm21 -; AVX512DQBW-SLOW-NEXT: movabsq $1161999626690365456, %rax # imm = 0x1020408102040810 -; AVX512DQBW-SLOW-NEXT: kmovq %rax, %k5 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm21, %zmm0 {%k5} -; AVX512DQBW-SLOW-NEXT: vmovdqa64 32(%rdi), %xmm21 -; AVX512DQBW-SLOW-NEXT: movabsq $2033499346708139548, %rax # imm = 0x1C3870E1C3870E1C -; AVX512DQBW-SLOW-NEXT: kmovq %rax, %k5 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm0, %zmm20 {%k5} -; AVX512DQBW-SLOW-NEXT: vmovdqa 32(%rsi), %xmm0 -; AVX512DQBW-SLOW-NEXT: vpshufhw {{.*#+}} ymm18 = ymm18[0,1,2,3,6,7,7,6,8,9,10,11,14,15,15,14] -; AVX512DQBW-SLOW-NEXT: vpshufd {{.*#+}} ymm29 = ymm18[2,2,3,3,6,6,7,7] -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm25, %ymm19, %ymm29 {%k4} -; AVX512DQBW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm19 = xmm21[0],xmm0[0],xmm21[1],xmm0[1],xmm21[2],xmm0[2],xmm21[3],xmm0[3],xmm21[4],xmm0[4],xmm21[5],xmm0[5],xmm21[6],xmm0[6],xmm21[7],xmm0[7] -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} xmm18 = <0,1,u,u,u,6,7,2,3,u,u,u,8,9,4,5> -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm18, %xmm19, %xmm19 -; AVX512DQBW-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm19 = zmm29[2,3,2,3],zmm19[0,1,0,1] -; AVX512DQBW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm25 = xmm23[0],xmm28[0],xmm23[1],xmm28[1],xmm23[2],xmm28[2],xmm23[3],xmm28[3],xmm23[4],xmm28[4],xmm23[5],xmm28[5],xmm23[6],xmm28[6],xmm23[7],xmm28[7] -; AVX512DQBW-SLOW-NEXT: vpshufb %ymm27, %ymm17, %ymm27 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} xmm17 = <4,5,0,1,u,u,u,6,7,2,3,u,u,u,8,9> -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm17, %xmm25, %xmm25 -; AVX512DQBW-SLOW-NEXT: vpshufhw {{.*#+}} ymm16 = ymm16[0,1,2,3,7,6,6,7,8,9,10,11,15,14,14,15] -; AVX512DQBW-SLOW-NEXT: vpshufd {{.*#+}} ymm16 = ymm16[0,2,3,3,4,6,7,7] -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %ymm16, %ymm27 {%k1} -; AVX512DQBW-SLOW-NEXT: vshufi64x2 {{.*#+}} zmm16 = zmm27[2,3,2,3],zmm25[0,1,0,1] -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm19, %zmm16 {%k2} -; AVX512DQBW-SLOW-NEXT: vpshufb {{.*#+}} ymm10 = ymm10[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,29],zero,ymm10[27],zero,zero,zero,zero,ymm10[30],zero,ymm10[28],zero,zero,zero,zero,ymm10[31],zero -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm10 = ymm10[2,3,2,3] -; AVX512DQBW-SLOW-NEXT: vpshufb {{.*#+}} ymm11 = ymm11[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm11[27],zero,zero,zero,zero,ymm11[30],zero,ymm11[28],zero,zero,zero,zero,ymm11[31],zero,ymm11[29] -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm11 = ymm11[2,3,2,3] -; AVX512DQBW-SLOW-NEXT: vpor %ymm10, %ymm11, %ymm11 -; AVX512DQBW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm19 = xmm26[0],xmm24[0],xmm26[1],xmm24[1],xmm26[2],xmm24[2],xmm26[3],xmm24[3],xmm26[4],xmm24[4],xmm26[5],xmm24[5],xmm26[6],xmm24[6],xmm26[7],xmm24[7] -; AVX512DQBW-SLOW-NEXT: vmovdqa {{.*#+}} xmm10 = -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm10, %xmm19, %xmm19 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} ymm19 = ymm19[0,1,0,1] -; AVX512DQBW-SLOW-NEXT: vinserti64x4 $1, %ymm19, %zmm11, %zmm11 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm19 = [14,13,14,15,15,14,14,15,14,13,14,15,15,14,14,15,17,17,16,16,17,17,16,16,20,21,17,17,17,17,16,16] -; AVX512DQBW-SLOW-NEXT: vpermw %zmm22, %zmm19, %zmm19 -; AVX512DQBW-SLOW-NEXT: movabsq $580999813345182728, %rax # imm = 0x810204081020408 -; AVX512DQBW-SLOW-NEXT: kmovq %rax, %k1 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm19, %zmm11 {%k1} -; AVX512DQBW-SLOW-NEXT: movabsq $1016749673354069774, %rax # imm = 0xE1C3870E1C3870E -; AVX512DQBW-SLOW-NEXT: kmovq %rax, %k1 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm11, %zmm16 {%k1} -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} xmm19 = -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm19, %xmm28, %xmm11 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} xmm25 = -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm25, %xmm23, %xmm27 -; AVX512DQBW-SLOW-NEXT: vporq %xmm11, %xmm27, %xmm11 -; AVX512DQBW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm23 = xmm28[8],xmm23[8],xmm28[9],xmm23[9],xmm28[10],xmm23[10],xmm28[11],xmm23[11],xmm28[12],xmm23[12],xmm28[13],xmm23[13],xmm28[14],xmm23[14],xmm28[15],xmm23[15] -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm12, %xmm23, %xmm12 -; AVX512DQBW-SLOW-NEXT: vinserti32x4 $2, %xmm12, %zmm11, %zmm11 -; AVX512DQBW-SLOW-NEXT: vmovdqa {{.*#+}} xmm12 = -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm12, %xmm0, %xmm23 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} xmm27 = -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm27, %xmm21, %xmm28 -; AVX512DQBW-SLOW-NEXT: vporq %xmm23, %xmm28, %xmm23 -; AVX512DQBW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm0 = xmm0[8],xmm21[8],xmm0[9],xmm21[9],xmm0[10],xmm21[10],xmm0[11],xmm21[11],xmm0[12],xmm21[12],xmm0[13],xmm21[13],xmm0[14],xmm21[14],xmm0[15],xmm21[15] -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} zmm21 = zmm11[0,1,0,1,4,5,4,5] -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm13, %xmm0, %xmm0 -; AVX512DQBW-SLOW-NEXT: vinserti32x4 $2, %xmm0, %zmm23, %zmm0 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} zmm11 = zmm0[0,1,0,1,4,5,4,5] -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm21, %zmm11 {%k3} -; AVX512DQBW-SLOW-NEXT: vmovdqa {{.*#+}} xmm0 = <128,4,u,u,u,128,7,128,5,u,u,u,128,8,128,6> -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm0, %xmm24, %xmm13 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm21 = [2,2,2,4,2,2,2,4,3,3,3,3,2,2,2,4,52,53,52,53,53,54,53,54,52,53,52,53,53,54,53,54] -; AVX512DQBW-SLOW-NEXT: vpermi2w %zmm22, %zmm2, %zmm21 -; AVX512DQBW-SLOW-NEXT: vmovdqa {{.*#+}} xmm2 = <4,128,u,u,u,7,128,5,128,u,u,u,8,128,6,128> -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm2, %xmm26, %xmm22 -; AVX512DQBW-SLOW-NEXT: vporq %xmm13, %xmm22, %xmm13 -; AVX512DQBW-SLOW-NEXT: vpunpckhbw {{.*#+}} xmm22 = xmm26[8],xmm24[8],xmm26[9],xmm24[9],xmm26[10],xmm24[10],xmm26[11],xmm24[11],xmm26[12],xmm24[12],xmm26[13],xmm24[13],xmm26[14],xmm24[14],xmm26[15],xmm24[15] -; AVX512DQBW-SLOW-NEXT: vpshufb {{.*#+}} xmm22 = xmm22[u,6,7,2,3,u,u,u,8,9,4,5,u,u,u,10] -; AVX512DQBW-SLOW-NEXT: vinserti32x4 $2, %xmm22, %zmm13, %zmm13 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} zmm13 = zmm13[0,1,0,1,4,5,4,5] -; AVX512DQBW-SLOW-NEXT: movabsq $290499906672591364, %rax # imm = 0x408102040810204 -; AVX512DQBW-SLOW-NEXT: kmovq %rax, %k1 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm21, %zmm13 {%k1} -; AVX512DQBW-SLOW-NEXT: movabsq $-8714997200177740921, %rax # imm = 0x870E1C3870E1C387 -; AVX512DQBW-SLOW-NEXT: kmovq %rax, %k1 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm13, %zmm11 {%k1} -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm19, %xmm6, %xmm13 -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm25, %xmm5, %xmm19 -; AVX512DQBW-SLOW-NEXT: vporq %xmm13, %xmm19, %xmm13 -; AVX512DQBW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm5 = xmm5[0],xmm6[0],xmm5[1],xmm6[1],xmm5[2],xmm6[2],xmm5[3],xmm6[3],xmm5[4],xmm6[4],xmm5[5],xmm6[5],xmm5[6],xmm6[6],xmm5[7],xmm6[7] -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm17, %xmm5, %xmm5 -; AVX512DQBW-SLOW-NEXT: vinserti32x4 $2, %xmm13, %zmm5, %zmm5 -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm12, %xmm8, %xmm6 -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm27, %xmm7, %xmm12 -; AVX512DQBW-SLOW-NEXT: vpor %xmm6, %xmm12, %xmm6 -; AVX512DQBW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm7 = xmm7[0],xmm8[0],xmm7[1],xmm8[1],xmm7[2],xmm8[2],xmm7[3],xmm8[3],xmm7[4],xmm8[4],xmm7[5],xmm8[5],xmm7[6],xmm8[6],xmm7[7],xmm8[7] -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm18, %xmm7, %xmm7 -; AVX512DQBW-SLOW-NEXT: vinserti32x4 $2, %xmm6, %zmm7, %zmm6 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} zmm5 = zmm5[0,1,0,1,4,5,4,5] -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} zmm6 = zmm6[0,1,0,1,4,5,4,5] -; AVX512DQBW-SLOW-NEXT: movabsq $871499720017774092, %rax # imm = 0xC183060C183060C -; AVX512DQBW-SLOW-NEXT: kmovq %rax, %k1 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm5, %zmm6 {%k1} -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm0, %xmm4, %xmm0 -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm2, %xmm1, %xmm2 -; AVX512DQBW-SLOW-NEXT: vpor %xmm0, %xmm2, %xmm0 -; AVX512DQBW-SLOW-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3],xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7] -; AVX512DQBW-SLOW-NEXT: vpshufb %xmm10, %xmm1, %xmm1 -; AVX512DQBW-SLOW-NEXT: vinserti32x4 $2, %xmm0, %zmm1, %zmm0 -; AVX512DQBW-SLOW-NEXT: vmovdqa64 {{.*#+}} zmm1 = [1,1,0,0,1,1,0,0,4,5,1,1,1,1,0,0,18,18,18,20,18,18,18,20,19,19,19,19,18,18,18,20] -; AVX512DQBW-SLOW-NEXT: vpermw %zmm15, %zmm1, %zmm1 -; AVX512DQBW-SLOW-NEXT: vpermq {{.*#+}} zmm0 = zmm0[0,1,0,1,4,5,4,5] -; AVX512DQBW-SLOW-NEXT: movabsq $4647998506761461824, %rax # imm = 0x4081020408102040 -; AVX512DQBW-SLOW-NEXT: kmovq %rax, %k1 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm1, %zmm0 {%k1} -; AVX512DQBW-SLOW-NEXT: movabsq $8133997386832558192, %rax # imm = 0x70E1C3870E1C3870 -; AVX512DQBW-SLOW-NEXT: kmovq %rax, %k1 -; AVX512DQBW-SLOW-NEXT: vmovdqu8 %zmm0, %zmm6 {%k1} -; AVX512DQBW-SLOW-NEXT: movq {{[0-9]+}}(%rsp), %rax -; AVX512DQBW-SLOW-NEXT: vmovdqa64 %zmm6, (%rax) -; AVX512DQBW-SLOW-NEXT: vmovdqa64 %zmm9, 320(%rax) -; AVX512DQBW-SLOW-NEXT: vmovdqa64 %zmm11, 256(%rax) -; AVX512DQBW-SLOW-NEXT: vmovdqa64 %zmm16, 192(%rax) -; AVX512DQBW-SLOW-NEXT: vmovdqa64 %zmm20, 128(%rax) -; AVX512DQBW-SLOW-NEXT: vmovdqa64 %zmm3, 64(%rax) -; AVX512DQBW-SLOW-NEXT: vmovdqa64 %zmm14, 384(%rax) -; AVX512DQBW-SLOW-NEXT: vzeroupper -; AVX512DQBW-SLOW-NEXT: retq %in.vec0 = load <64 x i8>, ptr %in.vecptr0, align 64 %in.vec1 = load <64 x i8>, ptr %in.vecptr1, align 64 %in.vec2 = load <64 x i8>, ptr %in.vecptr2, align 64 @@ -9660,10 +8754,16 @@ define void @store_i8_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec ; AVX512-SLOW: {{.*}} ; AVX512BW-ONLY: {{.*}} ; AVX512BW-ONLY-FAST: {{.*}} +; AVX512BW-ONLY-SLOW: {{.*}} +; AVX512DQ-FAST: {{.*}} ; AVX512DQ-ONLY: {{.*}} +; AVX512DQ-SLOW: {{.*}} ; AVX512DQBW-FAST: {{.*}} ; AVX512DQBW-ONLY: {{.*}} +; AVX512DQBW-SLOW: {{.*}} ; AVX512F-ONLY: {{.*}} +; AVX512F-ONLY-FAST: {{.*}} +; AVX512F-ONLY-SLOW: {{.*}} ; FALLBACK0: {{.*}} ; FALLBACK1: {{.*}} ; FALLBACK10: {{.*}} diff --git a/llvm/test/CodeGen/X86/vector-lzcnt-512.ll b/llvm/test/CodeGen/X86/vector-lzcnt-512.ll index 3c5e3adf038f..efecfa47eb4a 100644 --- a/llvm/test/CodeGen/X86/vector-lzcnt-512.ll +++ b/llvm/test/CodeGen/X86/vector-lzcnt-512.ll @@ -31,8 +31,8 @@ define <8 x i64> @testv8i64(<8 x i64> %in) nounwind { ; AVX512BW-NEXT: vporq %zmm1, %zmm0, %zmm0 ; AVX512BW-NEXT: vpbroadcastb {{.*#+}} zmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512BW-NEXT: vpandnq %zmm1, %zmm0, %zmm2 -; AVX512BW-NEXT: vbroadcasti64x2 {{.*#+}} zmm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; AVX512BW-NEXT: # zmm3 = mem[0,1,0,1,0,1,0,1] +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX512BW-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] ; AVX512BW-NEXT: vpshufb %zmm2, %zmm3, %zmm2 ; AVX512BW-NEXT: vpternlogq $15, %zmm0, %zmm0, %zmm0 ; AVX512BW-NEXT: vpsrlw $4, %zmm0, %zmm0 @@ -110,8 +110,8 @@ define <8 x i64> @testv8i64u(<8 x i64> %in) nounwind { ; AVX512BW-NEXT: vporq %zmm1, %zmm0, %zmm0 ; AVX512BW-NEXT: vpbroadcastb {{.*#+}} zmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512BW-NEXT: vpandnq %zmm1, %zmm0, %zmm2 -; AVX512BW-NEXT: vbroadcasti64x2 {{.*#+}} zmm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; AVX512BW-NEXT: # zmm3 = mem[0,1,0,1,0,1,0,1] +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX512BW-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] ; AVX512BW-NEXT: vpshufb %zmm2, %zmm3, %zmm2 ; AVX512BW-NEXT: vpternlogq $15, %zmm0, %zmm0, %zmm0 ; AVX512BW-NEXT: vpsrlw $4, %zmm0, %zmm0 @@ -187,8 +187,8 @@ define <16 x i32> @testv16i32(<16 x i32> %in) nounwind { ; AVX512BW-NEXT: vpord %zmm1, %zmm0, %zmm0 ; AVX512BW-NEXT: vpbroadcastb {{.*#+}} zmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512BW-NEXT: vpandnq %zmm1, %zmm0, %zmm2 -; AVX512BW-NEXT: vbroadcasti64x2 {{.*#+}} zmm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; AVX512BW-NEXT: # zmm3 = mem[0,1,0,1,0,1,0,1] +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX512BW-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] ; AVX512BW-NEXT: vpshufb %zmm2, %zmm3, %zmm2 ; AVX512BW-NEXT: vpternlogq $15, %zmm0, %zmm0, %zmm0 ; AVX512BW-NEXT: vpsrlw $4, %zmm0, %zmm0 @@ -274,8 +274,8 @@ define <16 x i32> @testv16i32u(<16 x i32> %in) nounwind { ; AVX512BW-NEXT: vpord %zmm1, %zmm0, %zmm0 ; AVX512BW-NEXT: vpbroadcastb {{.*#+}} zmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512BW-NEXT: vpandnq %zmm1, %zmm0, %zmm2 -; AVX512BW-NEXT: vbroadcasti64x2 {{.*#+}} zmm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; AVX512BW-NEXT: # zmm3 = mem[0,1,0,1,0,1,0,1] +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX512BW-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] ; AVX512BW-NEXT: vpshufb %zmm2, %zmm3, %zmm2 ; AVX512BW-NEXT: vpternlogq $15, %zmm0, %zmm0, %zmm0 ; AVX512BW-NEXT: vpsrlw $4, %zmm0, %zmm0 @@ -369,8 +369,8 @@ define <32 x i16> @testv32i16(<32 x i16> %in) nounwind { ; AVX512BW: # %bb.0: ; AVX512BW-NEXT: vpsrlw $4, %zmm0, %zmm1 ; AVX512BW-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %zmm1 -; AVX512BW-NEXT: vbroadcasti64x2 {{.*#+}} zmm2 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] -; AVX512BW-NEXT: # zmm2 = mem[0,1,0,1,0,1,0,1] +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm2 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] +; AVX512BW-NEXT: # zmm2 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] ; AVX512BW-NEXT: vpshufb %zmm1, %zmm2, %zmm3 ; AVX512BW-NEXT: vpshufb %zmm0, %zmm2, %zmm2 ; AVX512BW-NEXT: vptestnmb %zmm1, %zmm1, %k0 @@ -455,8 +455,8 @@ define <32 x i16> @testv32i16u(<32 x i16> %in) nounwind { ; AVX512BW: # %bb.0: ; AVX512BW-NEXT: vpsrlw $4, %zmm0, %zmm1 ; AVX512BW-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %zmm1 -; AVX512BW-NEXT: vbroadcasti64x2 {{.*#+}} zmm2 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] -; AVX512BW-NEXT: # zmm2 = mem[0,1,0,1,0,1,0,1] +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm2 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] +; AVX512BW-NEXT: # zmm2 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] ; AVX512BW-NEXT: vpshufb %zmm1, %zmm2, %zmm3 ; AVX512BW-NEXT: vpshufb %zmm0, %zmm2, %zmm2 ; AVX512BW-NEXT: vptestnmb %zmm1, %zmm1, %k0 @@ -561,8 +561,8 @@ define <64 x i8> @testv64i8(<64 x i8> %in) nounwind { ; AVX512BW: # %bb.0: ; AVX512BW-NEXT: vpsrlw $4, %zmm0, %zmm1 ; AVX512BW-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %zmm1 -; AVX512BW-NEXT: vbroadcasti64x2 {{.*#+}} zmm2 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] -; AVX512BW-NEXT: # zmm2 = mem[0,1,0,1,0,1,0,1] +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm2 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] +; AVX512BW-NEXT: # zmm2 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] ; AVX512BW-NEXT: vpshufb %zmm1, %zmm2, %zmm3 ; AVX512BW-NEXT: vpshufb %zmm0, %zmm2, %zmm0 ; AVX512BW-NEXT: vptestnmb %zmm1, %zmm1, %k0 @@ -651,8 +651,8 @@ define <64 x i8> @testv64i8u(<64 x i8> %in) nounwind { ; AVX512BW: # %bb.0: ; AVX512BW-NEXT: vpsrlw $4, %zmm0, %zmm1 ; AVX512BW-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %zmm1 -; AVX512BW-NEXT: vbroadcasti64x2 {{.*#+}} zmm2 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] -; AVX512BW-NEXT: # zmm2 = mem[0,1,0,1,0,1,0,1] +; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm2 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] +; AVX512BW-NEXT: # zmm2 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] ; AVX512BW-NEXT: vpshufb %zmm1, %zmm2, %zmm3 ; AVX512BW-NEXT: vpshufb %zmm0, %zmm2, %zmm0 ; AVX512BW-NEXT: vptestnmb %zmm1, %zmm1, %k0 diff --git a/llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll b/llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll index 3ce4bb3306ab..86e878261dcc 100644 --- a/llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll +++ b/llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll @@ -5256,8 +5256,8 @@ define void @vec384_i32_widen_to_i192_factor6_broadcast_to_v2i192_factor2(ptr %i ; AVX512DQ-NEXT: vpaddb 32(%rsi), %ymm1, %ymm1 ; AVX512DQ-NEXT: vpaddb (%rsi), %ymm0, %ymm0 ; AVX512DQ-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 -; AVX512DQ-NEXT: vbroadcasti32x8 {{.*#+}} zmm1 = [16,29,30,31,4,5,16,7,16,29,30,31,4,5,16,7] -; AVX512DQ-NEXT: # zmm1 = mem[0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7] +; AVX512DQ-NEXT: vbroadcasti64x4 {{.*#+}} zmm1 = [16,29,30,31,4,5,16,7,16,29,30,31,4,5,16,7] +; AVX512DQ-NEXT: # zmm1 = mem[0,1,2,3,0,1,2,3] ; AVX512DQ-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX512DQ-NEXT: vpermt2d %zmm0, %zmm1, %zmm2 ; AVX512DQ-NEXT: vpaddb (%rdx), %ymm2, %ymm0 @@ -5540,8 +5540,8 @@ define void @vec384_i64_widen_to_i192_factor3_broadcast_to_v2i192_factor2(ptr %i ; AVX512DQ-NEXT: vpaddb (%rsi), %ymm0, %ymm0 ; AVX512DQ-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 ; AVX512DQ-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; AVX512DQ-NEXT: vbroadcasti32x8 {{.*#+}} zmm2 = [0,7,10,0,0,7,10,0] -; AVX512DQ-NEXT: # zmm2 = mem[0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7] +; AVX512DQ-NEXT: vbroadcasti64x4 {{.*#+}} zmm2 = [0,7,10,0,0,7,10,0] +; AVX512DQ-NEXT: # zmm2 = mem[0,1,2,3,0,1,2,3] ; AVX512DQ-NEXT: vpermi2q %zmm1, %zmm0, %zmm2 ; AVX512DQ-NEXT: vpaddb (%rdx), %ymm2, %ymm0 ; AVX512DQ-NEXT: vmovaps 32(%rdx), %ymm1 diff --git a/llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast_from_memory.ll b/llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast_from_memory.ll index 134908f4c739..b88e2921484d 100644 --- a/llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast_from_memory.ll +++ b/llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast_from_memory.ll @@ -4217,8 +4217,8 @@ define void @vec384_i32_widen_to_i192_factor6_broadcast_to_v2i192_factor2(ptr %i ; ; AVX512DQ-LABEL: vec384_i32_widen_to_i192_factor6_broadcast_to_v2i192_factor2: ; AVX512DQ: # %bb.0: -; AVX512DQ-NEXT: vbroadcasti32x8 {{.*#+}} zmm0 = [16,29,30,31,4,5,16,7,16,29,30,31,4,5,16,7] -; AVX512DQ-NEXT: # zmm0 = mem[0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7] +; AVX512DQ-NEXT: vbroadcasti64x4 {{.*#+}} zmm0 = [16,29,30,31,4,5,16,7,16,29,30,31,4,5,16,7] +; AVX512DQ-NEXT: # zmm0 = mem[0,1,2,3,0,1,2,3] ; AVX512DQ-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX512DQ-NEXT: vpermt2d (%rdi), %zmm0, %zmm1 ; AVX512DQ-NEXT: vpaddb (%rsi), %ymm1, %ymm0 @@ -4439,8 +4439,8 @@ define void @vec384_i64_widen_to_i192_factor3_broadcast_to_v2i192_factor2(ptr %i ; AVX512DQ: # %bb.0: ; AVX512DQ-NEXT: vmovdqa64 (%rdi), %zmm0 ; AVX512DQ-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; AVX512DQ-NEXT: vbroadcasti32x8 {{.*#+}} zmm2 = [0,7,10,0,0,7,10,0] -; AVX512DQ-NEXT: # zmm2 = mem[0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7] +; AVX512DQ-NEXT: vbroadcasti64x4 {{.*#+}} zmm2 = [0,7,10,0,0,7,10,0] +; AVX512DQ-NEXT: # zmm2 = mem[0,1,2,3,0,1,2,3] ; AVX512DQ-NEXT: vpermi2q %zmm1, %zmm0, %zmm2 ; AVX512DQ-NEXT: vpaddb (%rsi), %ymm2, %ymm0 ; AVX512DQ-NEXT: vmovaps 32(%rsi), %ymm1 -- GitLab From 169db80e41936811c6744f2c513a1ed00d97f10e Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Thu, 30 Nov 2023 18:11:21 +0000 Subject: [PATCH 013/699] [X86] Canonicalize fp zero vectors from bitcasted integer zero vectors Generic code is supposed to handle this but can be blocked by hasOneUse checks. Noticed while investigating #26392 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 6 + .../CodeGen/X86/2011-10-19-widen_vselect.ll | 6 +- llvm/test/CodeGen/X86/2012-07-10-extload64.ll | 4 +- llvm/test/CodeGen/X86/fold-load-vec.ll | 2 +- llvm/test/CodeGen/X86/fold-pcmpeqd-2.ll | 18 +- llvm/test/CodeGen/X86/half.ll | 14 +- llvm/test/CodeGen/X86/nontemporal-3.ll | 646 +++--------------- llvm/test/CodeGen/X86/pr13577.ll | 3 +- llvm/test/CodeGen/X86/pr41619.ll | 3 +- llvm/test/CodeGen/X86/vec_zero_cse.ll | 4 +- .../vector-shuffle-combining-avx512bwvl.ll | 9 +- 11 files changed, 136 insertions(+), 579 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 6167be7bdf84..b73779edc5f7 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -42930,6 +42930,12 @@ static SDValue combineBitcast(SDNode *N, SelectionDAG &DAG, } } + // Canonicalize fp zero vectors - these sometimes don't fold due to one use + // limits. + if (VT.isVector() && TLI.isTypeLegal(VT) && ISD::isBuildVectorAllZeros(N) && + (VT.getScalarType() == MVT::f32 || VT.getScalarType() == MVT::f64)) + return getZeroVector(VT.getSimpleVT(), Subtarget, DAG, SDLoc(N0)); + // Try to remove a bitcast of constant vXi1 vector. We have to legalize // most of these to scalar anyway. if (Subtarget.hasAVX512() && VT.isScalarInteger() && diff --git a/llvm/test/CodeGen/X86/2011-10-19-widen_vselect.ll b/llvm/test/CodeGen/X86/2011-10-19-widen_vselect.ll index e7f62b9dfc22..d3f410d37567 100644 --- a/llvm/test/CodeGen/X86/2011-10-19-widen_vselect.ll +++ b/llvm/test/CodeGen/X86/2011-10-19-widen_vselect.ll @@ -49,14 +49,12 @@ entry: define void @zero_test() { ; X86-LABEL: zero_test: ; X86: # %bb.0: # %entry -; X86-NEXT: xorps %xmm0, %xmm0 -; X86-NEXT: movlps %xmm0, (%eax) +; X86-NEXT: movl $0, (%eax) ; X86-NEXT: retl ; ; X64-LABEL: zero_test: ; X64: # %bb.0: # %entry -; X64-NEXT: xorps %xmm0, %xmm0 -; X64-NEXT: movlps %xmm0, (%rax) +; X64-NEXT: movq $0, (%rax) ; X64-NEXT: retq entry: %0 = select <2 x i1> undef, <2 x float> undef, <2 x float> zeroinitializer diff --git a/llvm/test/CodeGen/X86/2012-07-10-extload64.ll b/llvm/test/CodeGen/X86/2012-07-10-extload64.ll index b6ec3b34eb10..f4ec8bde3700 100644 --- a/llvm/test/CodeGen/X86/2012-07-10-extload64.ll +++ b/llvm/test/CodeGen/X86/2012-07-10-extload64.ll @@ -29,8 +29,8 @@ define void @store_64(ptr %ptr) { ; X86-LABEL: store_64: ; X86: # %bb.0: # %BB ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax -; X86-NEXT: xorps %xmm0, %xmm0 -; X86-NEXT: movlps %xmm0, (%eax) +; X86-NEXT: movl $0, 4(%eax) +; X86-NEXT: movl $0, (%eax) ; X86-NEXT: retl ; ; X64-LABEL: store_64: diff --git a/llvm/test/CodeGen/X86/fold-load-vec.ll b/llvm/test/CodeGen/X86/fold-load-vec.ll index 348929cdf9f7..0bf846a0930b 100644 --- a/llvm/test/CodeGen/X86/fold-load-vec.ll +++ b/llvm/test/CodeGen/X86/fold-load-vec.ll @@ -10,8 +10,8 @@ define void @sample_test(ptr %source, ptr %dest) nounwind { ; CHECK-NEXT: subq $24, %rsp ; CHECK-NEXT: movq %rdi, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movq %rsi, {{[0-9]+}}(%rsp) +; CHECK-NEXT: movq $0, (%rsp) ; CHECK-NEXT: xorps %xmm0, %xmm0 -; CHECK-NEXT: movlps %xmm0, (%rsp) ; CHECK-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] ; CHECK-NEXT: movlps %xmm0, (%rsp) ; CHECK-NEXT: movlps %xmm0, (%rsi) diff --git a/llvm/test/CodeGen/X86/fold-pcmpeqd-2.ll b/llvm/test/CodeGen/X86/fold-pcmpeqd-2.ll index 88425ea87845..713ecf5414ba 100644 --- a/llvm/test/CodeGen/X86/fold-pcmpeqd-2.ll +++ b/llvm/test/CodeGen/X86/fold-pcmpeqd-2.ll @@ -51,11 +51,6 @@ define void @program_1(ptr %dest, ptr %t0, <4 x float> %p0, <4 x float> %p1, <4 ; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload ; X32-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 ; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill -; X32-NEXT: xorps %xmm0, %xmm0 -; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill -; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload -; X32-NEXT: mulps %xmm0, %xmm0 -; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill ; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload ; X32-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 ; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill @@ -64,8 +59,10 @@ define void @program_1(ptr %dest, ptr %t0, <4 x float> %p0, <4 x float> %p1, <4 ; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload ; X32-NEXT: cmpunordps %xmm0, %xmm0 ; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill +; X32-NEXT: xorps %xmm0, %xmm0 +; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill ; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload -; X32-NEXT: minps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 +; X32-NEXT: minps %xmm0, %xmm0 ; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill ; X32-NEXT: xorps %xmm0, %xmm0 ; X32-NEXT: movaps %xmm0, {{[0-9]+}}(%esp) @@ -135,11 +132,6 @@ define void @program_1(ptr %dest, ptr %t0, <4 x float> %p0, <4 x float> %p1, <4 ; X64-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload ; X64-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; X64-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill -; X64-NEXT: xorps %xmm0, %xmm0 -; X64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill -; X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload -; X64-NEXT: mulps %xmm0, %xmm0 -; X64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; X64-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload ; X64-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; X64-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill @@ -148,8 +140,10 @@ define void @program_1(ptr %dest, ptr %t0, <4 x float> %p0, <4 x float> %p1, <4 ; X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; X64-NEXT: cmpunordps %xmm0, %xmm0 ; X64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill +; X64-NEXT: xorps %xmm0, %xmm0 +; X64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload -; X64-NEXT: minps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; X64-NEXT: minps %xmm0, %xmm0 ; X64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; X64-NEXT: xorl %ebx, %ebx ; X64-NEXT: xorps %xmm3, %xmm3 diff --git a/llvm/test/CodeGen/X86/half.ll b/llvm/test/CodeGen/X86/half.ll index 596e465ee8ca..722525720316 100644 --- a/llvm/test/CodeGen/X86/half.ll +++ b/llvm/test/CodeGen/X86/half.ll @@ -1082,12 +1082,11 @@ define void @main.158() #0 { ; BWON-F16C-LABEL: main.158: ; BWON-F16C: # %bb.0: # %entry ; BWON-F16C-NEXT: vxorps %xmm0, %xmm0, %xmm0 -; BWON-F16C-NEXT: vcvtps2ph $4, %xmm0, %xmm0 -; BWON-F16C-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero -; BWON-F16C-NEXT: vcvtph2ps %xmm0, %xmm0 -; BWON-F16C-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero -; BWON-F16C-NEXT: vucomiss %xmm0, %xmm1 -; BWON-F16C-NEXT: vxorps %xmm0, %xmm0, %xmm0 +; BWON-F16C-NEXT: vcvtps2ph $4, %xmm0, %xmm1 +; BWON-F16C-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero +; BWON-F16C-NEXT: vcvtph2ps %xmm1, %xmm1 +; BWON-F16C-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero +; BWON-F16C-NEXT: vucomiss %xmm1, %xmm2 ; BWON-F16C-NEXT: jae .LBB20_2 ; BWON-F16C-NEXT: # %bb.1: # %entry ; BWON-F16C-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero @@ -1100,8 +1099,7 @@ define void @main.158() #0 { ; CHECK-I686-LABEL: main.158: ; CHECK-I686: # %bb.0: # %entry ; CHECK-I686-NEXT: subl $12, %esp -; CHECK-I686-NEXT: pxor %xmm0, %xmm0 -; CHECK-I686-NEXT: movd %xmm0, (%esp) +; CHECK-I686-NEXT: movl $0, (%esp) ; CHECK-I686-NEXT: calll __truncsfhf2 ; CHECK-I686-NEXT: pextrw $0, %xmm0, %eax ; CHECK-I686-NEXT: movw %ax, (%esp) diff --git a/llvm/test/CodeGen/X86/nontemporal-3.ll b/llvm/test/CodeGen/X86/nontemporal-3.ll index a2d2c5ca4301..f9872b10097a 100644 --- a/llvm/test/CodeGen/X86/nontemporal-3.ll +++ b/llvm/test/CodeGen/X86/nontemporal-3.ll @@ -93,247 +93,66 @@ define void @test_zero_v4f64_align1(ptr %dst) nounwind { } define void @test_zero_v8f32_align1(ptr %dst) nounwind { -; SSE2-LABEL: test_zero_v8f32_align1: -; SSE2: # %bb.0: -; SSE2-NEXT: xorl %eax, %eax -; SSE2-NEXT: movntiq %rax, 8(%rdi) -; SSE2-NEXT: movntiq %rax, (%rdi) -; SSE2-NEXT: movntiq %rax, 24(%rdi) -; SSE2-NEXT: movntiq %rax, 16(%rdi) -; SSE2-NEXT: retq -; -; SSE4A-LABEL: test_zero_v8f32_align1: -; SSE4A: # %bb.0: -; SSE4A-NEXT: xorl %eax, %eax -; SSE4A-NEXT: movntiq %rax, 8(%rdi) -; SSE4A-NEXT: movntiq %rax, 24(%rdi) -; SSE4A-NEXT: xorps %xmm0, %xmm0 -; SSE4A-NEXT: movntsd %xmm0, (%rdi) -; SSE4A-NEXT: movntsd %xmm0, 16(%rdi) -; SSE4A-NEXT: retq -; -; SSE41-LABEL: test_zero_v8f32_align1: -; SSE41: # %bb.0: -; SSE41-NEXT: xorl %eax, %eax -; SSE41-NEXT: movntiq %rax, 8(%rdi) -; SSE41-NEXT: movntiq %rax, (%rdi) -; SSE41-NEXT: movntiq %rax, 24(%rdi) -; SSE41-NEXT: movntiq %rax, 16(%rdi) -; SSE41-NEXT: retq -; -; AVX-LABEL: test_zero_v8f32_align1: -; AVX: # %bb.0: -; AVX-NEXT: xorl %eax, %eax -; AVX-NEXT: movntiq %rax, 8(%rdi) -; AVX-NEXT: movntiq %rax, (%rdi) -; AVX-NEXT: movntiq %rax, 24(%rdi) -; AVX-NEXT: movntiq %rax, 16(%rdi) -; AVX-NEXT: retq -; -; AVX512-LABEL: test_zero_v8f32_align1: -; AVX512: # %bb.0: -; AVX512-NEXT: xorl %eax, %eax -; AVX512-NEXT: movntiq %rax, 8(%rdi) -; AVX512-NEXT: movntiq %rax, (%rdi) -; AVX512-NEXT: movntiq %rax, 24(%rdi) -; AVX512-NEXT: movntiq %rax, 16(%rdi) -; AVX512-NEXT: retq +; CHECK-LABEL: test_zero_v8f32_align1: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: movntiq %rax, 8(%rdi) +; CHECK-NEXT: movntiq %rax, (%rdi) +; CHECK-NEXT: movntiq %rax, 24(%rdi) +; CHECK-NEXT: movntiq %rax, 16(%rdi) +; CHECK-NEXT: retq store <8 x float> zeroinitializer, ptr %dst, align 1, !nontemporal !1 ret void } define void @test_zero_v4i64_align1(ptr %dst) nounwind { -; SSE2-LABEL: test_zero_v4i64_align1: -; SSE2: # %bb.0: -; SSE2-NEXT: xorl %eax, %eax -; SSE2-NEXT: movntiq %rax, 8(%rdi) -; SSE2-NEXT: movntiq %rax, (%rdi) -; SSE2-NEXT: movntiq %rax, 24(%rdi) -; SSE2-NEXT: movntiq %rax, 16(%rdi) -; SSE2-NEXT: retq -; -; SSE4A-LABEL: test_zero_v4i64_align1: -; SSE4A: # %bb.0: -; SSE4A-NEXT: xorps %xmm0, %xmm0 -; SSE4A-NEXT: movntsd %xmm0, 8(%rdi) -; SSE4A-NEXT: movntsd %xmm0, (%rdi) -; SSE4A-NEXT: movntsd %xmm0, 24(%rdi) -; SSE4A-NEXT: movntsd %xmm0, 16(%rdi) -; SSE4A-NEXT: retq -; -; SSE41-LABEL: test_zero_v4i64_align1: -; SSE41: # %bb.0: -; SSE41-NEXT: xorl %eax, %eax -; SSE41-NEXT: movntiq %rax, 8(%rdi) -; SSE41-NEXT: movntiq %rax, (%rdi) -; SSE41-NEXT: movntiq %rax, 24(%rdi) -; SSE41-NEXT: movntiq %rax, 16(%rdi) -; SSE41-NEXT: retq -; -; AVX-LABEL: test_zero_v4i64_align1: -; AVX: # %bb.0: -; AVX-NEXT: xorl %eax, %eax -; AVX-NEXT: movntiq %rax, 8(%rdi) -; AVX-NEXT: movntiq %rax, (%rdi) -; AVX-NEXT: movntiq %rax, 24(%rdi) -; AVX-NEXT: movntiq %rax, 16(%rdi) -; AVX-NEXT: retq -; -; AVX512-LABEL: test_zero_v4i64_align1: -; AVX512: # %bb.0: -; AVX512-NEXT: xorl %eax, %eax -; AVX512-NEXT: movntiq %rax, 8(%rdi) -; AVX512-NEXT: movntiq %rax, (%rdi) -; AVX512-NEXT: movntiq %rax, 24(%rdi) -; AVX512-NEXT: movntiq %rax, 16(%rdi) -; AVX512-NEXT: retq +; CHECK-LABEL: test_zero_v4i64_align1: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: movntiq %rax, 8(%rdi) +; CHECK-NEXT: movntiq %rax, (%rdi) +; CHECK-NEXT: movntiq %rax, 24(%rdi) +; CHECK-NEXT: movntiq %rax, 16(%rdi) +; CHECK-NEXT: retq store <4 x i64> zeroinitializer, ptr %dst, align 1, !nontemporal !1 ret void } define void @test_zero_v8i32_align1(ptr %dst) nounwind { -; SSE2-LABEL: test_zero_v8i32_align1: -; SSE2: # %bb.0: -; SSE2-NEXT: xorl %eax, %eax -; SSE2-NEXT: movntiq %rax, 8(%rdi) -; SSE2-NEXT: movntiq %rax, (%rdi) -; SSE2-NEXT: movntiq %rax, 24(%rdi) -; SSE2-NEXT: movntiq %rax, 16(%rdi) -; SSE2-NEXT: retq -; -; SSE4A-LABEL: test_zero_v8i32_align1: -; SSE4A: # %bb.0: -; SSE4A-NEXT: xorps %xmm0, %xmm0 -; SSE4A-NEXT: movntsd %xmm0, 8(%rdi) -; SSE4A-NEXT: movntsd %xmm0, (%rdi) -; SSE4A-NEXT: movntsd %xmm0, 24(%rdi) -; SSE4A-NEXT: movntsd %xmm0, 16(%rdi) -; SSE4A-NEXT: retq -; -; SSE41-LABEL: test_zero_v8i32_align1: -; SSE41: # %bb.0: -; SSE41-NEXT: xorl %eax, %eax -; SSE41-NEXT: movntiq %rax, 8(%rdi) -; SSE41-NEXT: movntiq %rax, (%rdi) -; SSE41-NEXT: movntiq %rax, 24(%rdi) -; SSE41-NEXT: movntiq %rax, 16(%rdi) -; SSE41-NEXT: retq -; -; AVX-LABEL: test_zero_v8i32_align1: -; AVX: # %bb.0: -; AVX-NEXT: xorl %eax, %eax -; AVX-NEXT: movntiq %rax, 8(%rdi) -; AVX-NEXT: movntiq %rax, (%rdi) -; AVX-NEXT: movntiq %rax, 24(%rdi) -; AVX-NEXT: movntiq %rax, 16(%rdi) -; AVX-NEXT: retq -; -; AVX512-LABEL: test_zero_v8i32_align1: -; AVX512: # %bb.0: -; AVX512-NEXT: xorl %eax, %eax -; AVX512-NEXT: movntiq %rax, 8(%rdi) -; AVX512-NEXT: movntiq %rax, (%rdi) -; AVX512-NEXT: movntiq %rax, 24(%rdi) -; AVX512-NEXT: movntiq %rax, 16(%rdi) -; AVX512-NEXT: retq +; CHECK-LABEL: test_zero_v8i32_align1: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: movntiq %rax, 8(%rdi) +; CHECK-NEXT: movntiq %rax, (%rdi) +; CHECK-NEXT: movntiq %rax, 24(%rdi) +; CHECK-NEXT: movntiq %rax, 16(%rdi) +; CHECK-NEXT: retq store <8 x i32> zeroinitializer, ptr %dst, align 1, !nontemporal !1 ret void } define void @test_zero_v16i16_align1(ptr %dst) nounwind { -; SSE2-LABEL: test_zero_v16i16_align1: -; SSE2: # %bb.0: -; SSE2-NEXT: xorl %eax, %eax -; SSE2-NEXT: movntiq %rax, 8(%rdi) -; SSE2-NEXT: movntiq %rax, (%rdi) -; SSE2-NEXT: movntiq %rax, 24(%rdi) -; SSE2-NEXT: movntiq %rax, 16(%rdi) -; SSE2-NEXT: retq -; -; SSE4A-LABEL: test_zero_v16i16_align1: -; SSE4A: # %bb.0: -; SSE4A-NEXT: xorps %xmm0, %xmm0 -; SSE4A-NEXT: movntsd %xmm0, 8(%rdi) -; SSE4A-NEXT: movntsd %xmm0, (%rdi) -; SSE4A-NEXT: movntsd %xmm0, 24(%rdi) -; SSE4A-NEXT: movntsd %xmm0, 16(%rdi) -; SSE4A-NEXT: retq -; -; SSE41-LABEL: test_zero_v16i16_align1: -; SSE41: # %bb.0: -; SSE41-NEXT: xorl %eax, %eax -; SSE41-NEXT: movntiq %rax, 8(%rdi) -; SSE41-NEXT: movntiq %rax, (%rdi) -; SSE41-NEXT: movntiq %rax, 24(%rdi) -; SSE41-NEXT: movntiq %rax, 16(%rdi) -; SSE41-NEXT: retq -; -; AVX-LABEL: test_zero_v16i16_align1: -; AVX: # %bb.0: -; AVX-NEXT: xorl %eax, %eax -; AVX-NEXT: movntiq %rax, 8(%rdi) -; AVX-NEXT: movntiq %rax, (%rdi) -; AVX-NEXT: movntiq %rax, 24(%rdi) -; AVX-NEXT: movntiq %rax, 16(%rdi) -; AVX-NEXT: retq -; -; AVX512-LABEL: test_zero_v16i16_align1: -; AVX512: # %bb.0: -; AVX512-NEXT: xorl %eax, %eax -; AVX512-NEXT: movntiq %rax, 8(%rdi) -; AVX512-NEXT: movntiq %rax, (%rdi) -; AVX512-NEXT: movntiq %rax, 24(%rdi) -; AVX512-NEXT: movntiq %rax, 16(%rdi) -; AVX512-NEXT: retq +; CHECK-LABEL: test_zero_v16i16_align1: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: movntiq %rax, 8(%rdi) +; CHECK-NEXT: movntiq %rax, (%rdi) +; CHECK-NEXT: movntiq %rax, 24(%rdi) +; CHECK-NEXT: movntiq %rax, 16(%rdi) +; CHECK-NEXT: retq store <16 x i16> zeroinitializer, ptr %dst, align 1, !nontemporal !1 ret void } define void @test_zero_v32i8_align1(ptr %dst) nounwind { -; SSE2-LABEL: test_zero_v32i8_align1: -; SSE2: # %bb.0: -; SSE2-NEXT: xorl %eax, %eax -; SSE2-NEXT: movntiq %rax, 8(%rdi) -; SSE2-NEXT: movntiq %rax, (%rdi) -; SSE2-NEXT: movntiq %rax, 24(%rdi) -; SSE2-NEXT: movntiq %rax, 16(%rdi) -; SSE2-NEXT: retq -; -; SSE4A-LABEL: test_zero_v32i8_align1: -; SSE4A: # %bb.0: -; SSE4A-NEXT: xorps %xmm0, %xmm0 -; SSE4A-NEXT: movntsd %xmm0, 8(%rdi) -; SSE4A-NEXT: movntsd %xmm0, (%rdi) -; SSE4A-NEXT: movntsd %xmm0, 24(%rdi) -; SSE4A-NEXT: movntsd %xmm0, 16(%rdi) -; SSE4A-NEXT: retq -; -; SSE41-LABEL: test_zero_v32i8_align1: -; SSE41: # %bb.0: -; SSE41-NEXT: xorl %eax, %eax -; SSE41-NEXT: movntiq %rax, 8(%rdi) -; SSE41-NEXT: movntiq %rax, (%rdi) -; SSE41-NEXT: movntiq %rax, 24(%rdi) -; SSE41-NEXT: movntiq %rax, 16(%rdi) -; SSE41-NEXT: retq -; -; AVX-LABEL: test_zero_v32i8_align1: -; AVX: # %bb.0: -; AVX-NEXT: xorl %eax, %eax -; AVX-NEXT: movntiq %rax, 8(%rdi) -; AVX-NEXT: movntiq %rax, (%rdi) -; AVX-NEXT: movntiq %rax, 24(%rdi) -; AVX-NEXT: movntiq %rax, 16(%rdi) -; AVX-NEXT: retq -; -; AVX512-LABEL: test_zero_v32i8_align1: -; AVX512: # %bb.0: -; AVX512-NEXT: xorl %eax, %eax -; AVX512-NEXT: movntiq %rax, 8(%rdi) -; AVX512-NEXT: movntiq %rax, (%rdi) -; AVX512-NEXT: movntiq %rax, 24(%rdi) -; AVX512-NEXT: movntiq %rax, 16(%rdi) -; AVX512-NEXT: retq +; CHECK-LABEL: test_zero_v32i8_align1: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: movntiq %rax, 8(%rdi) +; CHECK-NEXT: movntiq %rax, (%rdi) +; CHECK-NEXT: movntiq %rax, 24(%rdi) +; CHECK-NEXT: movntiq %rax, 16(%rdi) +; CHECK-NEXT: retq store <32 x i8> zeroinitializer, ptr %dst, align 1, !nontemporal !1 ret void } @@ -508,347 +327,86 @@ define void @test_zero_v8f64_align1(ptr %dst) nounwind { } define void @test_zero_v16f32_align1(ptr %dst) nounwind { -; SSE2-LABEL: test_zero_v16f32_align1: -; SSE2: # %bb.0: -; SSE2-NEXT: xorl %eax, %eax -; SSE2-NEXT: movntiq %rax, 8(%rdi) -; SSE2-NEXT: movntiq %rax, (%rdi) -; SSE2-NEXT: movntiq %rax, 24(%rdi) -; SSE2-NEXT: movntiq %rax, 16(%rdi) -; SSE2-NEXT: movntiq %rax, 40(%rdi) -; SSE2-NEXT: movntiq %rax, 32(%rdi) -; SSE2-NEXT: movntiq %rax, 56(%rdi) -; SSE2-NEXT: movntiq %rax, 48(%rdi) -; SSE2-NEXT: retq -; -; SSE4A-LABEL: test_zero_v16f32_align1: -; SSE4A: # %bb.0: -; SSE4A-NEXT: xorl %eax, %eax -; SSE4A-NEXT: movntiq %rax, 8(%rdi) -; SSE4A-NEXT: movntiq %rax, 24(%rdi) -; SSE4A-NEXT: movntiq %rax, 40(%rdi) -; SSE4A-NEXT: movntiq %rax, 56(%rdi) -; SSE4A-NEXT: xorps %xmm0, %xmm0 -; SSE4A-NEXT: movntsd %xmm0, (%rdi) -; SSE4A-NEXT: movntsd %xmm0, 16(%rdi) -; SSE4A-NEXT: movntsd %xmm0, 32(%rdi) -; SSE4A-NEXT: movntsd %xmm0, 48(%rdi) -; SSE4A-NEXT: retq -; -; SSE41-LABEL: test_zero_v16f32_align1: -; SSE41: # %bb.0: -; SSE41-NEXT: xorl %eax, %eax -; SSE41-NEXT: movntiq %rax, 8(%rdi) -; SSE41-NEXT: movntiq %rax, (%rdi) -; SSE41-NEXT: movntiq %rax, 24(%rdi) -; SSE41-NEXT: movntiq %rax, 16(%rdi) -; SSE41-NEXT: movntiq %rax, 40(%rdi) -; SSE41-NEXT: movntiq %rax, 32(%rdi) -; SSE41-NEXT: movntiq %rax, 56(%rdi) -; SSE41-NEXT: movntiq %rax, 48(%rdi) -; SSE41-NEXT: retq -; -; AVX-LABEL: test_zero_v16f32_align1: -; AVX: # %bb.0: -; AVX-NEXT: xorl %eax, %eax -; AVX-NEXT: movntiq %rax, 8(%rdi) -; AVX-NEXT: movntiq %rax, (%rdi) -; AVX-NEXT: movntiq %rax, 24(%rdi) -; AVX-NEXT: movntiq %rax, 16(%rdi) -; AVX-NEXT: movntiq %rax, 40(%rdi) -; AVX-NEXT: movntiq %rax, 32(%rdi) -; AVX-NEXT: movntiq %rax, 56(%rdi) -; AVX-NEXT: movntiq %rax, 48(%rdi) -; AVX-NEXT: retq -; -; AVX512-LABEL: test_zero_v16f32_align1: -; AVX512: # %bb.0: -; AVX512-NEXT: xorl %eax, %eax -; AVX512-NEXT: movntiq %rax, 8(%rdi) -; AVX512-NEXT: movntiq %rax, (%rdi) -; AVX512-NEXT: movntiq %rax, 24(%rdi) -; AVX512-NEXT: movntiq %rax, 16(%rdi) -; AVX512-NEXT: movntiq %rax, 40(%rdi) -; AVX512-NEXT: movntiq %rax, 32(%rdi) -; AVX512-NEXT: movntiq %rax, 56(%rdi) -; AVX512-NEXT: movntiq %rax, 48(%rdi) -; AVX512-NEXT: retq +; CHECK-LABEL: test_zero_v16f32_align1: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: movntiq %rax, 8(%rdi) +; CHECK-NEXT: movntiq %rax, (%rdi) +; CHECK-NEXT: movntiq %rax, 24(%rdi) +; CHECK-NEXT: movntiq %rax, 16(%rdi) +; CHECK-NEXT: movntiq %rax, 40(%rdi) +; CHECK-NEXT: movntiq %rax, 32(%rdi) +; CHECK-NEXT: movntiq %rax, 56(%rdi) +; CHECK-NEXT: movntiq %rax, 48(%rdi) +; CHECK-NEXT: retq store <16 x float> zeroinitializer, ptr %dst, align 1, !nontemporal !1 ret void } define void @test_zero_v8i64_align1(ptr %dst) nounwind { -; SSE2-LABEL: test_zero_v8i64_align1: -; SSE2: # %bb.0: -; SSE2-NEXT: xorl %eax, %eax -; SSE2-NEXT: movntiq %rax, 8(%rdi) -; SSE2-NEXT: movntiq %rax, (%rdi) -; SSE2-NEXT: movntiq %rax, 24(%rdi) -; SSE2-NEXT: movntiq %rax, 16(%rdi) -; SSE2-NEXT: movntiq %rax, 40(%rdi) -; SSE2-NEXT: movntiq %rax, 32(%rdi) -; SSE2-NEXT: movntiq %rax, 56(%rdi) -; SSE2-NEXT: movntiq %rax, 48(%rdi) -; SSE2-NEXT: retq -; -; SSE4A-LABEL: test_zero_v8i64_align1: -; SSE4A: # %bb.0: -; SSE4A-NEXT: xorps %xmm0, %xmm0 -; SSE4A-NEXT: movntsd %xmm0, 8(%rdi) -; SSE4A-NEXT: movntsd %xmm0, (%rdi) -; SSE4A-NEXT: movntsd %xmm0, 24(%rdi) -; SSE4A-NEXT: movntsd %xmm0, 16(%rdi) -; SSE4A-NEXT: movntsd %xmm0, 40(%rdi) -; SSE4A-NEXT: movntsd %xmm0, 32(%rdi) -; SSE4A-NEXT: movntsd %xmm0, 56(%rdi) -; SSE4A-NEXT: movntsd %xmm0, 48(%rdi) -; SSE4A-NEXT: retq -; -; SSE41-LABEL: test_zero_v8i64_align1: -; SSE41: # %bb.0: -; SSE41-NEXT: xorl %eax, %eax -; SSE41-NEXT: movntiq %rax, 8(%rdi) -; SSE41-NEXT: movntiq %rax, (%rdi) -; SSE41-NEXT: movntiq %rax, 24(%rdi) -; SSE41-NEXT: movntiq %rax, 16(%rdi) -; SSE41-NEXT: movntiq %rax, 40(%rdi) -; SSE41-NEXT: movntiq %rax, 32(%rdi) -; SSE41-NEXT: movntiq %rax, 56(%rdi) -; SSE41-NEXT: movntiq %rax, 48(%rdi) -; SSE41-NEXT: retq -; -; AVX-LABEL: test_zero_v8i64_align1: -; AVX: # %bb.0: -; AVX-NEXT: xorl %eax, %eax -; AVX-NEXT: movntiq %rax, 8(%rdi) -; AVX-NEXT: movntiq %rax, (%rdi) -; AVX-NEXT: movntiq %rax, 24(%rdi) -; AVX-NEXT: movntiq %rax, 16(%rdi) -; AVX-NEXT: movntiq %rax, 40(%rdi) -; AVX-NEXT: movntiq %rax, 32(%rdi) -; AVX-NEXT: movntiq %rax, 56(%rdi) -; AVX-NEXT: movntiq %rax, 48(%rdi) -; AVX-NEXT: retq -; -; AVX512-LABEL: test_zero_v8i64_align1: -; AVX512: # %bb.0: -; AVX512-NEXT: xorl %eax, %eax -; AVX512-NEXT: movntiq %rax, 8(%rdi) -; AVX512-NEXT: movntiq %rax, (%rdi) -; AVX512-NEXT: movntiq %rax, 24(%rdi) -; AVX512-NEXT: movntiq %rax, 16(%rdi) -; AVX512-NEXT: movntiq %rax, 40(%rdi) -; AVX512-NEXT: movntiq %rax, 32(%rdi) -; AVX512-NEXT: movntiq %rax, 56(%rdi) -; AVX512-NEXT: movntiq %rax, 48(%rdi) -; AVX512-NEXT: retq +; CHECK-LABEL: test_zero_v8i64_align1: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: movntiq %rax, 8(%rdi) +; CHECK-NEXT: movntiq %rax, (%rdi) +; CHECK-NEXT: movntiq %rax, 24(%rdi) +; CHECK-NEXT: movntiq %rax, 16(%rdi) +; CHECK-NEXT: movntiq %rax, 40(%rdi) +; CHECK-NEXT: movntiq %rax, 32(%rdi) +; CHECK-NEXT: movntiq %rax, 56(%rdi) +; CHECK-NEXT: movntiq %rax, 48(%rdi) +; CHECK-NEXT: retq store <8 x i64> zeroinitializer, ptr %dst, align 1, !nontemporal !1 ret void } define void @test_zero_v16i32_align1(ptr %dst) nounwind { -; SSE2-LABEL: test_zero_v16i32_align1: -; SSE2: # %bb.0: -; SSE2-NEXT: xorl %eax, %eax -; SSE2-NEXT: movntiq %rax, 8(%rdi) -; SSE2-NEXT: movntiq %rax, (%rdi) -; SSE2-NEXT: movntiq %rax, 24(%rdi) -; SSE2-NEXT: movntiq %rax, 16(%rdi) -; SSE2-NEXT: movntiq %rax, 40(%rdi) -; SSE2-NEXT: movntiq %rax, 32(%rdi) -; SSE2-NEXT: movntiq %rax, 56(%rdi) -; SSE2-NEXT: movntiq %rax, 48(%rdi) -; SSE2-NEXT: retq -; -; SSE4A-LABEL: test_zero_v16i32_align1: -; SSE4A: # %bb.0: -; SSE4A-NEXT: xorps %xmm0, %xmm0 -; SSE4A-NEXT: movntsd %xmm0, 8(%rdi) -; SSE4A-NEXT: movntsd %xmm0, (%rdi) -; SSE4A-NEXT: movntsd %xmm0, 24(%rdi) -; SSE4A-NEXT: movntsd %xmm0, 16(%rdi) -; SSE4A-NEXT: movntsd %xmm0, 40(%rdi) -; SSE4A-NEXT: movntsd %xmm0, 32(%rdi) -; SSE4A-NEXT: movntsd %xmm0, 56(%rdi) -; SSE4A-NEXT: movntsd %xmm0, 48(%rdi) -; SSE4A-NEXT: retq -; -; SSE41-LABEL: test_zero_v16i32_align1: -; SSE41: # %bb.0: -; SSE41-NEXT: xorl %eax, %eax -; SSE41-NEXT: movntiq %rax, 8(%rdi) -; SSE41-NEXT: movntiq %rax, (%rdi) -; SSE41-NEXT: movntiq %rax, 24(%rdi) -; SSE41-NEXT: movntiq %rax, 16(%rdi) -; SSE41-NEXT: movntiq %rax, 40(%rdi) -; SSE41-NEXT: movntiq %rax, 32(%rdi) -; SSE41-NEXT: movntiq %rax, 56(%rdi) -; SSE41-NEXT: movntiq %rax, 48(%rdi) -; SSE41-NEXT: retq -; -; AVX-LABEL: test_zero_v16i32_align1: -; AVX: # %bb.0: -; AVX-NEXT: xorl %eax, %eax -; AVX-NEXT: movntiq %rax, 8(%rdi) -; AVX-NEXT: movntiq %rax, (%rdi) -; AVX-NEXT: movntiq %rax, 24(%rdi) -; AVX-NEXT: movntiq %rax, 16(%rdi) -; AVX-NEXT: movntiq %rax, 40(%rdi) -; AVX-NEXT: movntiq %rax, 32(%rdi) -; AVX-NEXT: movntiq %rax, 56(%rdi) -; AVX-NEXT: movntiq %rax, 48(%rdi) -; AVX-NEXT: retq -; -; AVX512-LABEL: test_zero_v16i32_align1: -; AVX512: # %bb.0: -; AVX512-NEXT: xorl %eax, %eax -; AVX512-NEXT: movntiq %rax, 8(%rdi) -; AVX512-NEXT: movntiq %rax, (%rdi) -; AVX512-NEXT: movntiq %rax, 24(%rdi) -; AVX512-NEXT: movntiq %rax, 16(%rdi) -; AVX512-NEXT: movntiq %rax, 40(%rdi) -; AVX512-NEXT: movntiq %rax, 32(%rdi) -; AVX512-NEXT: movntiq %rax, 56(%rdi) -; AVX512-NEXT: movntiq %rax, 48(%rdi) -; AVX512-NEXT: retq +; CHECK-LABEL: test_zero_v16i32_align1: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: movntiq %rax, 8(%rdi) +; CHECK-NEXT: movntiq %rax, (%rdi) +; CHECK-NEXT: movntiq %rax, 24(%rdi) +; CHECK-NEXT: movntiq %rax, 16(%rdi) +; CHECK-NEXT: movntiq %rax, 40(%rdi) +; CHECK-NEXT: movntiq %rax, 32(%rdi) +; CHECK-NEXT: movntiq %rax, 56(%rdi) +; CHECK-NEXT: movntiq %rax, 48(%rdi) +; CHECK-NEXT: retq store <16 x i32> zeroinitializer, ptr %dst, align 1, !nontemporal !1 ret void } define void @test_zero_v32i16_align1(ptr %dst) nounwind { -; SSE2-LABEL: test_zero_v32i16_align1: -; SSE2: # %bb.0: -; SSE2-NEXT: xorl %eax, %eax -; SSE2-NEXT: movntiq %rax, 8(%rdi) -; SSE2-NEXT: movntiq %rax, (%rdi) -; SSE2-NEXT: movntiq %rax, 24(%rdi) -; SSE2-NEXT: movntiq %rax, 16(%rdi) -; SSE2-NEXT: movntiq %rax, 40(%rdi) -; SSE2-NEXT: movntiq %rax, 32(%rdi) -; SSE2-NEXT: movntiq %rax, 56(%rdi) -; SSE2-NEXT: movntiq %rax, 48(%rdi) -; SSE2-NEXT: retq -; -; SSE4A-LABEL: test_zero_v32i16_align1: -; SSE4A: # %bb.0: -; SSE4A-NEXT: xorps %xmm0, %xmm0 -; SSE4A-NEXT: movntsd %xmm0, 8(%rdi) -; SSE4A-NEXT: movntsd %xmm0, (%rdi) -; SSE4A-NEXT: movntsd %xmm0, 24(%rdi) -; SSE4A-NEXT: movntsd %xmm0, 16(%rdi) -; SSE4A-NEXT: movntsd %xmm0, 40(%rdi) -; SSE4A-NEXT: movntsd %xmm0, 32(%rdi) -; SSE4A-NEXT: movntsd %xmm0, 56(%rdi) -; SSE4A-NEXT: movntsd %xmm0, 48(%rdi) -; SSE4A-NEXT: retq -; -; SSE41-LABEL: test_zero_v32i16_align1: -; SSE41: # %bb.0: -; SSE41-NEXT: xorl %eax, %eax -; SSE41-NEXT: movntiq %rax, 8(%rdi) -; SSE41-NEXT: movntiq %rax, (%rdi) -; SSE41-NEXT: movntiq %rax, 24(%rdi) -; SSE41-NEXT: movntiq %rax, 16(%rdi) -; SSE41-NEXT: movntiq %rax, 40(%rdi) -; SSE41-NEXT: movntiq %rax, 32(%rdi) -; SSE41-NEXT: movntiq %rax, 56(%rdi) -; SSE41-NEXT: movntiq %rax, 48(%rdi) -; SSE41-NEXT: retq -; -; AVX-LABEL: test_zero_v32i16_align1: -; AVX: # %bb.0: -; AVX-NEXT: xorl %eax, %eax -; AVX-NEXT: movntiq %rax, 8(%rdi) -; AVX-NEXT: movntiq %rax, (%rdi) -; AVX-NEXT: movntiq %rax, 24(%rdi) -; AVX-NEXT: movntiq %rax, 16(%rdi) -; AVX-NEXT: movntiq %rax, 40(%rdi) -; AVX-NEXT: movntiq %rax, 32(%rdi) -; AVX-NEXT: movntiq %rax, 56(%rdi) -; AVX-NEXT: movntiq %rax, 48(%rdi) -; AVX-NEXT: retq -; -; AVX512-LABEL: test_zero_v32i16_align1: -; AVX512: # %bb.0: -; AVX512-NEXT: xorl %eax, %eax -; AVX512-NEXT: movntiq %rax, 8(%rdi) -; AVX512-NEXT: movntiq %rax, (%rdi) -; AVX512-NEXT: movntiq %rax, 24(%rdi) -; AVX512-NEXT: movntiq %rax, 16(%rdi) -; AVX512-NEXT: movntiq %rax, 40(%rdi) -; AVX512-NEXT: movntiq %rax, 32(%rdi) -; AVX512-NEXT: movntiq %rax, 56(%rdi) -; AVX512-NEXT: movntiq %rax, 48(%rdi) -; AVX512-NEXT: retq +; CHECK-LABEL: test_zero_v32i16_align1: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: movntiq %rax, 8(%rdi) +; CHECK-NEXT: movntiq %rax, (%rdi) +; CHECK-NEXT: movntiq %rax, 24(%rdi) +; CHECK-NEXT: movntiq %rax, 16(%rdi) +; CHECK-NEXT: movntiq %rax, 40(%rdi) +; CHECK-NEXT: movntiq %rax, 32(%rdi) +; CHECK-NEXT: movntiq %rax, 56(%rdi) +; CHECK-NEXT: movntiq %rax, 48(%rdi) +; CHECK-NEXT: retq store <32 x i16> zeroinitializer, ptr %dst, align 1, !nontemporal !1 ret void } define void @test_zero_v64i8_align1(ptr %dst) nounwind { -; SSE2-LABEL: test_zero_v64i8_align1: -; SSE2: # %bb.0: -; SSE2-NEXT: xorl %eax, %eax -; SSE2-NEXT: movntiq %rax, 8(%rdi) -; SSE2-NEXT: movntiq %rax, (%rdi) -; SSE2-NEXT: movntiq %rax, 24(%rdi) -; SSE2-NEXT: movntiq %rax, 16(%rdi) -; SSE2-NEXT: movntiq %rax, 40(%rdi) -; SSE2-NEXT: movntiq %rax, 32(%rdi) -; SSE2-NEXT: movntiq %rax, 56(%rdi) -; SSE2-NEXT: movntiq %rax, 48(%rdi) -; SSE2-NEXT: retq -; -; SSE4A-LABEL: test_zero_v64i8_align1: -; SSE4A: # %bb.0: -; SSE4A-NEXT: xorps %xmm0, %xmm0 -; SSE4A-NEXT: movntsd %xmm0, 8(%rdi) -; SSE4A-NEXT: movntsd %xmm0, (%rdi) -; SSE4A-NEXT: movntsd %xmm0, 24(%rdi) -; SSE4A-NEXT: movntsd %xmm0, 16(%rdi) -; SSE4A-NEXT: movntsd %xmm0, 40(%rdi) -; SSE4A-NEXT: movntsd %xmm0, 32(%rdi) -; SSE4A-NEXT: movntsd %xmm0, 56(%rdi) -; SSE4A-NEXT: movntsd %xmm0, 48(%rdi) -; SSE4A-NEXT: retq -; -; SSE41-LABEL: test_zero_v64i8_align1: -; SSE41: # %bb.0: -; SSE41-NEXT: xorl %eax, %eax -; SSE41-NEXT: movntiq %rax, 8(%rdi) -; SSE41-NEXT: movntiq %rax, (%rdi) -; SSE41-NEXT: movntiq %rax, 24(%rdi) -; SSE41-NEXT: movntiq %rax, 16(%rdi) -; SSE41-NEXT: movntiq %rax, 40(%rdi) -; SSE41-NEXT: movntiq %rax, 32(%rdi) -; SSE41-NEXT: movntiq %rax, 56(%rdi) -; SSE41-NEXT: movntiq %rax, 48(%rdi) -; SSE41-NEXT: retq -; -; AVX-LABEL: test_zero_v64i8_align1: -; AVX: # %bb.0: -; AVX-NEXT: xorl %eax, %eax -; AVX-NEXT: movntiq %rax, 8(%rdi) -; AVX-NEXT: movntiq %rax, (%rdi) -; AVX-NEXT: movntiq %rax, 24(%rdi) -; AVX-NEXT: movntiq %rax, 16(%rdi) -; AVX-NEXT: movntiq %rax, 40(%rdi) -; AVX-NEXT: movntiq %rax, 32(%rdi) -; AVX-NEXT: movntiq %rax, 56(%rdi) -; AVX-NEXT: movntiq %rax, 48(%rdi) -; AVX-NEXT: retq -; -; AVX512-LABEL: test_zero_v64i8_align1: -; AVX512: # %bb.0: -; AVX512-NEXT: xorl %eax, %eax -; AVX512-NEXT: movntiq %rax, 8(%rdi) -; AVX512-NEXT: movntiq %rax, (%rdi) -; AVX512-NEXT: movntiq %rax, 24(%rdi) -; AVX512-NEXT: movntiq %rax, 16(%rdi) -; AVX512-NEXT: movntiq %rax, 40(%rdi) -; AVX512-NEXT: movntiq %rax, 32(%rdi) -; AVX512-NEXT: movntiq %rax, 56(%rdi) -; AVX512-NEXT: movntiq %rax, 48(%rdi) -; AVX512-NEXT: retq +; CHECK-LABEL: test_zero_v64i8_align1: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: movntiq %rax, 8(%rdi) +; CHECK-NEXT: movntiq %rax, (%rdi) +; CHECK-NEXT: movntiq %rax, 24(%rdi) +; CHECK-NEXT: movntiq %rax, 16(%rdi) +; CHECK-NEXT: movntiq %rax, 40(%rdi) +; CHECK-NEXT: movntiq %rax, 32(%rdi) +; CHECK-NEXT: movntiq %rax, 56(%rdi) +; CHECK-NEXT: movntiq %rax, 48(%rdi) +; CHECK-NEXT: retq store <64 x i8> zeroinitializer, ptr %dst, align 1, !nontemporal !1 ret void } @@ -1214,3 +772,7 @@ define void @test_zero_v64i8_align32(ptr %dst) nounwind { } !1 = !{i32 1} +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; SSE2: {{.*}} +; SSE41: {{.*}} +; SSE4A: {{.*}} diff --git a/llvm/test/CodeGen/X86/pr13577.ll b/llvm/test/CodeGen/X86/pr13577.ll index 7511560d85f5..ef359e740c09 100644 --- a/llvm/test/CodeGen/X86/pr13577.ll +++ b/llvm/test/CodeGen/X86/pr13577.ll @@ -29,7 +29,8 @@ declare x86_fp80 @copysignl(x86_fp80, x86_fp80) nounwind readnone define float @pr26070() { ; CHECK-LABEL: pr26070: ; CHECK: ## %bb.0: -; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; CHECK-NEXT: xorps %xmm0, %xmm0 +; CHECK-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-NEXT: retq %c = call float @copysignf(float 1.0, float undef) readnone ret float %c diff --git a/llvm/test/CodeGen/X86/pr41619.ll b/llvm/test/CodeGen/X86/pr41619.ll index 7d1d139a38a5..88dcd7798f0c 100644 --- a/llvm/test/CodeGen/X86/pr41619.ll +++ b/llvm/test/CodeGen/X86/pr41619.ll @@ -7,10 +7,9 @@ define void @foo(double %arg) { ; CHECK: ## %bb.0: ## %bb ; CHECK-NEXT: vmovq %xmm0, %rax ; CHECK-NEXT: vmovd %eax, %xmm0 -; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; CHECK-NEXT: vmovq %xmm0, %rax ; CHECK-NEXT: movl %eax, (%rax) -; CHECK-NEXT: vmovlps %xmm1, (%rax) +; CHECK-NEXT: movq $0, (%rax) ; CHECK-NEXT: retq bb: %tmp = bitcast double %arg to i64 diff --git a/llvm/test/CodeGen/X86/vec_zero_cse.ll b/llvm/test/CodeGen/X86/vec_zero_cse.ll index 99185277ba74..800dd59c2626 100644 --- a/llvm/test/CodeGen/X86/vec_zero_cse.ll +++ b/llvm/test/CodeGen/X86/vec_zero_cse.ll @@ -15,8 +15,8 @@ define void @test1() { ; X32: # %bb.0: ; X32-NEXT: movl $0, M1+4 ; X32-NEXT: movl $0, M1 -; X32-NEXT: xorps %xmm0, %xmm0 -; X32-NEXT: movlps %xmm0, M2 +; X32-NEXT: movl $0, M2+4 +; X32-NEXT: movl $0, M2 ; X32-NEXT: retl ; ; X64-LABEL: test1: diff --git a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll index 23c37af1db2f..eb5fc1523c08 100644 --- a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll +++ b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll @@ -108,11 +108,10 @@ define void @PR46178(ptr %0) { ; X86-NEXT: vmovdqu (%eax), %ymm1 ; X86-NEXT: vpmovqw %ymm0, %xmm0 ; X86-NEXT: vpmovqw %ymm1, %xmm1 -; X86-NEXT: vpsllw $8, %xmm0, %xmm0 -; X86-NEXT: vpsraw $8, %xmm0, %xmm0 -; X86-NEXT: vpsllw $8, %xmm1, %xmm1 -; X86-NEXT: vpsraw $8, %xmm1, %xmm1 -; X86-NEXT: vpunpcklqdq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2] +; X86-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 +; X86-NEXT: vpsllw $8, %ymm0, %ymm0 +; X86-NEXT: vpsraw $8, %ymm0, %ymm0 +; X86-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,1,1] ; X86-NEXT: vmovdqu %ymm0, (%eax) ; X86-NEXT: vzeroupper ; X86-NEXT: retl -- GitLab From 89165e8b1dfa8bf152b89a5f1db2a8ff760b3850 Mon Sep 17 00:00:00 2001 From: Peter Klausler <35819229+klausler@users.noreply.github.com> Date: Thu, 30 Nov 2023 10:58:51 -0800 Subject: [PATCH 014/699] [flang][openacc] Disable CUDA argument checks in OpenACC regions (#72310) Checks for CUDA Fortran data attribute compatibility don't need to be applied in OpenACC regions. --- flang/include/flang/Semantics/scope.h | 2 +- flang/include/flang/Semantics/tools.h | 3 ++- flang/lib/Semantics/check-call.cpp | 7 +++++-- flang/lib/Semantics/resolve-names.cpp | 11 ++++++++++- flang/lib/Semantics/tools.cpp | 8 ++++++++ flang/test/Semantics/cuf10.cuf | 11 ++++++++++- 6 files changed, 36 insertions(+), 6 deletions(-) diff --git a/flang/include/flang/Semantics/scope.h b/flang/include/flang/Semantics/scope.h index d2d42d0a79af..21072772d184 100644 --- a/flang/include/flang/Semantics/scope.h +++ b/flang/include/flang/Semantics/scope.h @@ -61,7 +61,7 @@ class Scope { public: ENUM_CLASS(Kind, Global, IntrinsicModules, Module, MainProgram, Subprogram, BlockData, DerivedType, BlockConstruct, Forall, OtherConstruct, - ImpliedDos) + OpenACCConstruct, ImpliedDos) using ImportKind = common::ImportKind; // Create the Global scope -- the root of the scope tree diff --git a/flang/include/flang/Semantics/tools.h b/flang/include/flang/Semantics/tools.h index 633787f45e85..b24508184701 100644 --- a/flang/include/flang/Semantics/tools.h +++ b/flang/include/flang/Semantics/tools.h @@ -44,7 +44,8 @@ const Scope &GetProgramUnitOrBlockConstructContaining(const Symbol &); const Scope *FindModuleContaining(const Scope &); const Scope *FindModuleFileContaining(const Scope &); const Scope *FindPureProcedureContaining(const Scope &); -const Scope *FindPureProcedureContaining(const Symbol &); +const Scope *FindOpenACCConstructContaining(const Scope *); + const Symbol *FindPointerComponent(const Scope &); const Symbol *FindPointerComponent(const DerivedTypeSpec &); const Symbol *FindPointerComponent(const DeclTypeSpec &); diff --git a/flang/lib/Semantics/check-call.cpp b/flang/lib/Semantics/check-call.cpp index efc2cb0a291d..b3f3b74b04ee 100644 --- a/flang/lib/Semantics/check-call.cpp +++ b/flang/lib/Semantics/check-call.cpp @@ -856,9 +856,12 @@ static void CheckExplicitDataArg(const characteristics::DummyDataObject &dummy, } } - // CUDA + // CUDA specific checks + // TODO: These are disabled in OpenACC constructs, which may not be + // correct when the target is not a GPU. if (!intrinsic && - !dummy.attrs.test(characteristics::DummyDataObject::Attr::Value)) { + !dummy.attrs.test(characteristics::DummyDataObject::Attr::Value) && + !FindOpenACCConstructContaining(scope)) { std::optional actualDataAttr, dummyDataAttr; if (const auto *actualObject{actualLastSymbol ? actualLastSymbol->detailsIf() diff --git a/flang/lib/Semantics/resolve-names.cpp b/flang/lib/Semantics/resolve-names.cpp index 0e59c3dd3b1a..0f69c1ccd285 100644 --- a/flang/lib/Semantics/resolve-names.cpp +++ b/flang/lib/Semantics/resolve-names.cpp @@ -1332,6 +1332,8 @@ public: bool Pre(const parser::OpenACCBlockConstruct &); void Post(const parser::OpenACCBlockConstruct &); + bool Pre(const parser::OpenACCCombinedConstruct &); + void Post(const parser::OpenACCCombinedConstruct &); bool Pre(const parser::AccBeginBlockDirective &x) { AddAccSourceRange(x.source); return true; @@ -1377,7 +1379,7 @@ void AccVisitor::AddAccSourceRange(const parser::CharBlock &source) { bool AccVisitor::Pre(const parser::OpenACCBlockConstruct &x) { if (NeedsScope(x)) { - PushScope(Scope::Kind::OtherConstruct, nullptr); + PushScope(Scope::Kind::OpenACCConstruct, nullptr); } return true; } @@ -1388,6 +1390,13 @@ void AccVisitor::Post(const parser::OpenACCBlockConstruct &x) { } } +bool AccVisitor::Pre(const parser::OpenACCCombinedConstruct &x) { + PushScope(Scope::Kind::OpenACCConstruct, nullptr); + return true; +} + +void AccVisitor::Post(const parser::OpenACCCombinedConstruct &x) { PopScope(); } + // Create scopes for OpenMP constructs class OmpVisitor : public virtual DeclarationVisitor { public: diff --git a/flang/lib/Semantics/tools.cpp b/flang/lib/Semantics/tools.cpp index 7d6ab2c83cc5..39d6fdc97512 100644 --- a/flang/lib/Semantics/tools.cpp +++ b/flang/lib/Semantics/tools.cpp @@ -108,6 +108,14 @@ const Scope *FindPureProcedureContaining(const Scope &start) { } } +const Scope *FindOpenACCConstructContaining(const Scope *scope) { + return scope ? FindScopeContaining(*scope, + [](const Scope &s) { + return s.kind() == Scope::Kind::OpenACCConstruct; + }) + : nullptr; +} + // 7.5.2.4 "same derived type" test -- rely on IsTkCompatibleWith() and its // infrastructure to detect and handle comparisons on distinct (but "same") // sequence/bind(C) derived types diff --git a/flang/test/Semantics/cuf10.cuf b/flang/test/Semantics/cuf10.cuf index 0d05222d446d..047503b3cca4 100644 --- a/flang/test/Semantics/cuf10.cuf +++ b/flang/test/Semantics/cuf10.cuf @@ -1,4 +1,4 @@ -! RUN: %python %S/test_errors.py %s %flang_fc1 +! RUN: %python %S/test_errors.py %s %flang_fc1 -fopenacc module m real, device :: a(4,8) real, managed, allocatable :: b(:,:) @@ -9,9 +9,18 @@ module m real a(n,m), c(n,m) real, managed :: b(n,m) end + attributes(device) subroutine devsub(a,n) + integer, value :: n + real, device :: a(n) + end subroutine test + real c(4) allocate(b(4,8)) !ERROR: dummy argument 'm=' has ATTRIBUTES(DEVICE) but its associated actual argument has no CUDA data attribute call kernel<<<1,32>>>(a,b,b,4,8) + !$acc parallel loop copy(c) + do j = 1, 1 + call devsub(c,4) ! not checked in OpenACC construct + end do end end -- GitLab From ae485e661ffce1f8fcd13d64974beee14b0e8af0 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 30 Nov 2023 10:53:59 -0800 Subject: [PATCH 015/699] [RISCV][GISel] Use customFor instead of customIf by pulling out a subtarget check. NFC --- llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp index 609c26c8e166..153bac34986e 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp @@ -57,11 +57,10 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) getActionDefinitionsBuilder({G_SADDO, G_SSUBO}).minScalar(0, sXLen).lower(); - getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL}) - .customIf([=, &ST](const LegalityQuery &Query) { - return ST.is64Bit() && typeIs(0, s32)(Query) && typeIs(1, s32)(Query); - }) - .legalFor({{s32, s32}, {s32, sXLen}, {sXLen, sXLen}}) + auto &ShiftActions = getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL}); + if (ST.is64Bit()) + ShiftActions.customFor({{s32, s32}}); + ShiftActions.legalFor({{s32, s32}, {s32, sXLen}, {sXLen, sXLen}}) .widenScalarToNextPow2(0) .clampScalar(1, s32, sXLen) .clampScalar(0, s32, sXLen) -- GitLab From aea94c90b39b2694f3a1b2f23f06f005c9d3459b Mon Sep 17 00:00:00 2001 From: Peter Klausler <35819229+klausler@users.noreply.github.com> Date: Thu, 30 Nov 2023 11:15:34 -0800 Subject: [PATCH 016/699] [flang] Adjust checks of ICHAR/IACHAR argument length (#72312) The compiler will now emit an error for length == 0 and an off-by-default portability warning for length > 1. Previously, the message was an unconditional warning for length /= 1. --- flang/lib/Evaluate/fold-integer.cpp | 10 ++++++++-- flang/test/Semantics/ichar01.f90 | 13 +++++++++++++ 2 files changed, 21 insertions(+), 2 deletions(-) create mode 100644 flang/test/Semantics/ichar01.f90 diff --git a/flang/lib/Evaluate/fold-integer.cpp b/flang/lib/Evaluate/fold-integer.cpp index 2882369105f6..c60648fb195f 100644 --- a/flang/lib/Evaluate/fold-integer.cpp +++ b/flang/lib/Evaluate/fold-integer.cpp @@ -677,10 +677,16 @@ Expr> FoldIntrinsicFunction( auto *someChar{UnwrapExpr>(args[0])}; CHECK(someChar); if (auto len{ToInt64(someChar->LEN())}) { - if (len.value() != 1) { + if (len.value() < 1) { + context.messages().Say( + "Character in intrinsic function %s must have length one"_err_en_US, + name); + } else if (len.value() > 1 && + context.languageFeatures().ShouldWarn( + common::UsageWarning::Portability)) { // Do not die, this was not checked before context.messages().Say( - "Character in intrinsic function %s must have length one"_warn_en_US, + "Character in intrinsic function %s should have length one"_port_en_US, name); } else { return common::visit( diff --git a/flang/test/Semantics/ichar01.f90 b/flang/test/Semantics/ichar01.f90 new file mode 100644 index 000000000000..5eb25a97e6d9 --- /dev/null +++ b/flang/test/Semantics/ichar01.f90 @@ -0,0 +1,13 @@ +! RUN: %python %S/test_errors.py %s %flang_fc1 -pedantic +!ERROR: Character in intrinsic function ichar must have length one +print *, ichar('') +!ERROR: Character in intrinsic function iachar must have length one +print *, iachar('') +print *, ichar('a') +print *, iachar('a') +!PORTABILITY: Character in intrinsic function ichar should have length one +print *, ichar('ab') +!PORTABILITY: Character in intrinsic function iachar should have length one +print *, iachar('ab') +end + -- GitLab From 5a314609b4a77470fea18f64427d618d5d0bae06 Mon Sep 17 00:00:00 2001 From: Youngsuk Kim Date: Thu, 30 Nov 2023 11:20:47 -0600 Subject: [PATCH 017/699] [llvm] Replace calls to Type::getPointerTo (NFC) Clean-up towards removing method Type::getPointerTo. --- .../Target/AMDGPU/AMDGPUCtorDtorLowering.cpp | 2 +- .../Target/NVPTX/NVPTXCtorDtorLowering.cpp | 2 +- llvm/unittests/IR/InstructionsTest.cpp | 23 ++++++++++--------- llvm/unittests/IR/VectorBuilderTest.cpp | 3 +-- 4 files changed, 15 insertions(+), 15 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCtorDtorLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCtorDtorLowering.cpp index d0a2f7c27e25..3afefcf55d49 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCtorDtorLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUCtorDtorLowering.cpp @@ -128,7 +128,7 @@ static void createInitOrFiniCalls(Function &F, bool IsCtor) { LoopBB, ExitBB); IRB.SetInsertPoint(LoopBB); auto *CallBackPHI = IRB.CreatePHI(PtrTy, 2, "ptr"); - auto *CallBack = IRB.CreateLoad(CallBackTy->getPointerTo(F.getAddressSpace()), + auto *CallBack = IRB.CreateLoad(IRB.getPtrTy(F.getAddressSpace()), CallBackPHI, "callback"); IRB.CreateCall(CallBackTy, CallBack); auto *NewCallBack = diff --git a/llvm/lib/Target/NVPTX/NVPTXCtorDtorLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXCtorDtorLowering.cpp index e941b7e7b7f9..f77a1f0272c8 100644 --- a/llvm/lib/Target/NVPTX/NVPTXCtorDtorLowering.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXCtorDtorLowering.cpp @@ -189,7 +189,7 @@ static void createInitOrFiniCalls(Function &F, bool IsCtor) { LoopBB, ExitBB); IRB.SetInsertPoint(LoopBB); auto *CallBackPHI = IRB.CreatePHI(PtrTy, 2, "ptr"); - auto *CallBack = IRB.CreateLoad(CallBackTy->getPointerTo(F.getAddressSpace()), + auto *CallBack = IRB.CreateLoad(IRB.getPtrTy(F.getAddressSpace()), CallBackPHI, "callback"); IRB.CreateCall(CallBackTy, CallBack); auto *NewCallBack = diff --git a/llvm/unittests/IR/InstructionsTest.cpp b/llvm/unittests/IR/InstructionsTest.cpp index 0ef3f66dbaee..b03f45e57123 100644 --- a/llvm/unittests/IR/InstructionsTest.cpp +++ b/llvm/unittests/IR/InstructionsTest.cpp @@ -714,7 +714,7 @@ TEST(InstructionsTest, CloneCall) { Type *Int32Ty = Type::getInt32Ty(C); Type *ArgTys[] = {Int32Ty, Int32Ty, Int32Ty}; FunctionType *FnTy = FunctionType::get(Int32Ty, ArgTys, /*isVarArg=*/false); - Value *Callee = Constant::getNullValue(FnTy->getPointerTo()); + Value *Callee = Constant::getNullValue(PointerType::getUnqual(C)); Value *Args[] = { ConstantInt::get(Int32Ty, 1), ConstantInt::get(Int32Ty, 2), @@ -748,7 +748,7 @@ TEST(InstructionsTest, AlterCallBundles) { LLVMContext C; Type *Int32Ty = Type::getInt32Ty(C); FunctionType *FnTy = FunctionType::get(Int32Ty, Int32Ty, /*isVarArg=*/false); - Value *Callee = Constant::getNullValue(FnTy->getPointerTo()); + Value *Callee = Constant::getNullValue(PointerType::getUnqual(C)); Value *Args[] = {ConstantInt::get(Int32Ty, 42)}; OperandBundleDef OldBundle("before", UndefValue::get(Int32Ty)); std::unique_ptr Call( @@ -775,7 +775,7 @@ TEST(InstructionsTest, AlterInvokeBundles) { LLVMContext C; Type *Int32Ty = Type::getInt32Ty(C); FunctionType *FnTy = FunctionType::get(Int32Ty, Int32Ty, /*isVarArg=*/false); - Value *Callee = Constant::getNullValue(FnTy->getPointerTo()); + Value *Callee = Constant::getNullValue(PointerType::getUnqual(C)); Value *Args[] = {ConstantInt::get(Int32Ty, 42)}; std::unique_ptr NormalDest(BasicBlock::Create(C)); std::unique_ptr UnwindDest(BasicBlock::Create(C)); @@ -1501,50 +1501,51 @@ TEST(InstructionsTest, FPCallIsFPMathOperator) { Type *ITy = Type::getInt32Ty(C); FunctionType *IFnTy = FunctionType::get(ITy, {}); - Value *ICallee = Constant::getNullValue(IFnTy->getPointerTo()); + PointerType *PtrTy = PointerType::getUnqual(C); + Value *ICallee = Constant::getNullValue(PtrTy); std::unique_ptr ICall(CallInst::Create(IFnTy, ICallee, {}, "")); EXPECT_FALSE(isa(ICall)); Type *VITy = FixedVectorType::get(ITy, 2); FunctionType *VIFnTy = FunctionType::get(VITy, {}); - Value *VICallee = Constant::getNullValue(VIFnTy->getPointerTo()); + Value *VICallee = Constant::getNullValue(PtrTy); std::unique_ptr VICall(CallInst::Create(VIFnTy, VICallee, {}, "")); EXPECT_FALSE(isa(VICall)); Type *AITy = ArrayType::get(ITy, 2); FunctionType *AIFnTy = FunctionType::get(AITy, {}); - Value *AICallee = Constant::getNullValue(AIFnTy->getPointerTo()); + Value *AICallee = Constant::getNullValue(PtrTy); std::unique_ptr AICall(CallInst::Create(AIFnTy, AICallee, {}, "")); EXPECT_FALSE(isa(AICall)); Type *FTy = Type::getFloatTy(C); FunctionType *FFnTy = FunctionType::get(FTy, {}); - Value *FCallee = Constant::getNullValue(FFnTy->getPointerTo()); + Value *FCallee = Constant::getNullValue(PtrTy); std::unique_ptr FCall(CallInst::Create(FFnTy, FCallee, {}, "")); EXPECT_TRUE(isa(FCall)); Type *VFTy = FixedVectorType::get(FTy, 2); FunctionType *VFFnTy = FunctionType::get(VFTy, {}); - Value *VFCallee = Constant::getNullValue(VFFnTy->getPointerTo()); + Value *VFCallee = Constant::getNullValue(PtrTy); std::unique_ptr VFCall(CallInst::Create(VFFnTy, VFCallee, {}, "")); EXPECT_TRUE(isa(VFCall)); Type *AFTy = ArrayType::get(FTy, 2); FunctionType *AFFnTy = FunctionType::get(AFTy, {}); - Value *AFCallee = Constant::getNullValue(AFFnTy->getPointerTo()); + Value *AFCallee = Constant::getNullValue(PtrTy); std::unique_ptr AFCall(CallInst::Create(AFFnTy, AFCallee, {}, "")); EXPECT_TRUE(isa(AFCall)); Type *AVFTy = ArrayType::get(VFTy, 2); FunctionType *AVFFnTy = FunctionType::get(AVFTy, {}); - Value *AVFCallee = Constant::getNullValue(AVFFnTy->getPointerTo()); + Value *AVFCallee = Constant::getNullValue(PtrTy); std::unique_ptr AVFCall( CallInst::Create(AVFFnTy, AVFCallee, {}, "")); EXPECT_TRUE(isa(AVFCall)); Type *AAVFTy = ArrayType::get(AVFTy, 2); FunctionType *AAVFFnTy = FunctionType::get(AAVFTy, {}); - Value *AAVFCallee = Constant::getNullValue(AAVFFnTy->getPointerTo()); + Value *AAVFCallee = Constant::getNullValue(PtrTy); std::unique_ptr AAVFCall( CallInst::Create(AAVFFnTy, AAVFCallee, {}, "")); EXPECT_TRUE(isa(AAVFCall)); diff --git a/llvm/unittests/IR/VectorBuilderTest.cpp b/llvm/unittests/IR/VectorBuilderTest.cpp index 82ce045ab4b0..4f9e9d7c494d 100644 --- a/llvm/unittests/IR/VectorBuilderTest.cpp +++ b/llvm/unittests/IR/VectorBuilderTest.cpp @@ -221,9 +221,8 @@ TEST_F(VectorBuilderTest, TestCreateLoadStore) { auto *FloatVecTy = FixedVectorType::get(Type::getFloatTy(Context), VectorNumElements); - auto *FloatVecPtrTy = FloatVecTy->getPointerTo(); - Value *FloatVecPtr = UndefValue::get(FloatVecPtrTy); + Value *FloatVecPtr = UndefValue::get(Builder.getPtrTy(0)); Value *FloatVec = UndefValue::get(FloatVecTy); // vp.load -- GitLab From 065796bb9293b222fa3d63311af542a98b96d09a Mon Sep 17 00:00:00 2001 From: "Ivan R. Ivanov" Date: Fri, 1 Dec 2023 04:21:03 +0900 Subject: [PATCH 018/699] [clang][OpenMP] Fix missing DI for __kmpc_global_thread_num (#73856) Co-authored-by: Ivan Radanov Ivanov --- clang/lib/CodeGen/CGOpenMPRuntime.cpp | 1 + clang/test/OpenMP/debug-info-kmpc.cpp | 17 +++++++++++++++++ 2 files changed, 18 insertions(+) create mode 100644 clang/test/OpenMP/debug-info-kmpc.cpp diff --git a/clang/lib/CodeGen/CGOpenMPRuntime.cpp b/clang/lib/CodeGen/CGOpenMPRuntime.cpp index d2be8141a3a4..55648963df36 100644 --- a/clang/lib/CodeGen/CGOpenMPRuntime.cpp +++ b/clang/lib/CodeGen/CGOpenMPRuntime.cpp @@ -1441,6 +1441,7 @@ llvm::Value *CGOpenMPRuntime::getThreadID(CodeGenFunction &CGF, setLocThreadIdInsertPt(CGF); CGBuilderTy::InsertPointGuard IPG(CGF.Builder); CGF.Builder.SetInsertPoint(Elem.second.ServiceInsertPt); + auto DL = ApplyDebugLocation::CreateDefaultArtificial(CGF, Loc); llvm::CallInst *Call = CGF.Builder.CreateCall( OMPBuilder.getOrCreateRuntimeFunction(CGM.getModule(), OMPRTL___kmpc_global_thread_num), diff --git a/clang/test/OpenMP/debug-info-kmpc.cpp b/clang/test/OpenMP/debug-info-kmpc.cpp new file mode 100644 index 000000000000..ee4e0108469c --- /dev/null +++ b/clang/test/OpenMP/debug-info-kmpc.cpp @@ -0,0 +1,17 @@ +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fopenmp-is-target-device "-debug-info-kind=constructor" -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s + +// Check that we properly attach debug info to the __kmpc_global_thread_num call +// CHECK: call {{.*}} @__kmpc_global_thread_num{{.*}}!dbg + +extern int bar(); +void foo() { +#pragma omp target teams + { +#pragma omp parallel + { + bar(); + } + } +} + -- GitLab From 418a3a45773a2a3fee1125534a073cec62c88b1e Mon Sep 17 00:00:00 2001 From: Schrodinger ZHU Yifan Date: Thu, 30 Nov 2023 14:22:36 -0500 Subject: [PATCH 019/699] [libc][SysMMan] implement mincore (#73704) Implement `mincore` as specified in https://man7.org/linux/man-pages/man2/mincore.2.html --- libc/config/linux/aarch64/entrypoints.txt | 1 + libc/config/linux/riscv/entrypoints.txt | 1 + libc/config/linux/x86_64/entrypoints.txt | 1 + libc/spec/linux.td | 15 ++- libc/spec/spec.td | 2 + libc/src/sys/mman/CMakeLists.txt | 7 ++ libc/src/sys/mman/linux/CMakeLists.txt | 13 ++ libc/src/sys/mman/linux/mincore.cpp | 28 +++++ libc/src/sys/mman/mincore.h | 20 +++ libc/test/src/sys/mman/linux/CMakeLists.txt | 16 +++ libc/test/src/sys/mman/linux/mincore_test.cpp | 115 ++++++++++++++++++ 11 files changed, 218 insertions(+), 1 deletion(-) create mode 100644 libc/src/sys/mman/linux/mincore.cpp create mode 100644 libc/src/sys/mman/mincore.h create mode 100644 libc/test/src/sys/mman/linux/mincore_test.cpp diff --git a/libc/config/linux/aarch64/entrypoints.txt b/libc/config/linux/aarch64/entrypoints.txt index 7a60c44570c4..ba3a7c557964 100644 --- a/libc/config/linux/aarch64/entrypoints.txt +++ b/libc/config/linux/aarch64/entrypoints.txt @@ -136,6 +136,7 @@ set(TARGET_LIBC_ENTRYPOINTS libc.src.sys.mman.mprotect libc.src.sys.mman.munmap libc.src.sys.mman.posix_madvise + libc.src.sys.mman.mincore # sys/random.h entrypoints libc.src.sys.random.getrandom diff --git a/libc/config/linux/riscv/entrypoints.txt b/libc/config/linux/riscv/entrypoints.txt index 28687ef8e234..63c1f9227f91 100644 --- a/libc/config/linux/riscv/entrypoints.txt +++ b/libc/config/linux/riscv/entrypoints.txt @@ -142,6 +142,7 @@ set(TARGET_LIBC_ENTRYPOINTS libc.src.sys.mman.mprotect libc.src.sys.mman.munmap libc.src.sys.mman.posix_madvise + libc.src.sys.mman.mincore # sys/random.h entrypoints libc.src.sys.random.getrandom diff --git a/libc/config/linux/x86_64/entrypoints.txt b/libc/config/linux/x86_64/entrypoints.txt index 43266e0e5b66..eb5457678e99 100644 --- a/libc/config/linux/x86_64/entrypoints.txt +++ b/libc/config/linux/x86_64/entrypoints.txt @@ -142,6 +142,7 @@ set(TARGET_LIBC_ENTRYPOINTS libc.src.sys.mman.mprotect libc.src.sys.mman.munmap libc.src.sys.mman.posix_madvise + libc.src.sys.mman.mincore # sys/random.h entrypoints libc.src.sys.random.getrandom diff --git a/libc/spec/linux.td b/libc/spec/linux.td index ba5f99c12ecd..eab0a987b920 100644 --- a/libc/spec/linux.td +++ b/libc/spec/linux.td @@ -76,7 +76,20 @@ def Linux : StandardSpec<"Linux"> { HeaderSpec SysMMan = HeaderSpec< "sys/mman.h", - [Macro<"MAP_ANONYMOUS">] + [Macro<"MAP_ANONYMOUS">], + [], // Types + [], // Enumerations + [ + FunctionSpec< + "mincore", + RetValSpec, + [ + ArgSpec, + ArgSpec, + ArgSpec, + ] + >, + ] // Functions >; diff --git a/libc/spec/spec.td b/libc/spec/spec.td index 9b689b5eb502..818cfaee6b61 100644 --- a/libc/spec/spec.td +++ b/libc/spec/spec.td @@ -49,6 +49,7 @@ def FloatType : NamedType<"float">; def DoubleType : NamedType<"double">; def LongDoubleType : NamedType<"long double">; def CharType : NamedType<"char">; +def UnsignedCharType : NamedType<"unsigned char">; // TODO: Add compatibility layer to use C23 type _Float128 if possible. def Float128Type : NamedType<"__float128">; @@ -109,6 +110,7 @@ def IntPtr : PtrType; def RestrictedIntPtr : RestrictedPtrType; def FloatPtr : PtrType; def DoublePtr : PtrType; +def UnsignedCharPtr : PtrType; def SigHandlerT : NamedType<"__sighandler_t">; diff --git a/libc/src/sys/mman/CMakeLists.txt b/libc/src/sys/mman/CMakeLists.txt index e336bfd5d6db..2d17429a26b4 100644 --- a/libc/src/sys/mman/CMakeLists.txt +++ b/libc/src/sys/mman/CMakeLists.txt @@ -36,3 +36,10 @@ add_entrypoint_object( DEPENDS .${LIBC_TARGET_OS}.posix_madvise ) + +add_entrypoint_object( + mincore + ALIAS + DEPENDS + .${LIBC_TARGET_OS}.mincore +) diff --git a/libc/src/sys/mman/linux/CMakeLists.txt b/libc/src/sys/mman/linux/CMakeLists.txt index 163e7dead888..ce0cda7f2227 100644 --- a/libc/src/sys/mman/linux/CMakeLists.txt +++ b/libc/src/sys/mman/linux/CMakeLists.txt @@ -61,3 +61,16 @@ add_entrypoint_object( libc.include.sys_syscall libc.src.__support.OSUtil.osutil ) + +add_entrypoint_object( + mincore + SRCS + mincore.cpp + HDRS + ../mincore.h + DEPENDS + libc.include.sys_mman + libc.include.sys_syscall + libc.src.__support.OSUtil.osutil + libc.src.errno.errno +) diff --git a/libc/src/sys/mman/linux/mincore.cpp b/libc/src/sys/mman/linux/mincore.cpp new file mode 100644 index 000000000000..8220c69ef2cb --- /dev/null +++ b/libc/src/sys/mman/linux/mincore.cpp @@ -0,0 +1,28 @@ +//===---------- Linux implementation of the mincore function --------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/sys/mman/mincore.h" + +#include "src/__support/OSUtil/syscall.h" // For internal syscall function. + +#include "src/errno/libc_errno.h" +#include // For syscall numbers. + +namespace LIBC_NAMESPACE { + +LLVM_LIBC_FUNCTION(int, mincore, (void *addr, size_t len, unsigned char *vec)) { + long ret = syscall_impl(SYS_mincore, reinterpret_cast(addr), len, + reinterpret_cast(vec)); + if (ret < 0) { + libc_errno = static_cast(-ret); + return -1; + } + return 0; +} + +} // namespace LIBC_NAMESPACE diff --git a/libc/src/sys/mman/mincore.h b/libc/src/sys/mman/mincore.h new file mode 100644 index 000000000000..403afaeb6af9 --- /dev/null +++ b/libc/src/sys/mman/mincore.h @@ -0,0 +1,20 @@ +//===-- Implementation header for mincore function --------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SRC_SYS_MMAN_MINCORE_H +#define LLVM_LIBC_SRC_SYS_MMAN_MINCORE_H + +#include // For size_t + +namespace LIBC_NAMESPACE { + +int mincore(void *addr, size_t len, unsigned char *vec); + +} // namespace LIBC_NAMESPACE + +#endif // LLVM_LIBC_SRC_SYS_MMAN_MINCORE_H diff --git a/libc/test/src/sys/mman/linux/CMakeLists.txt b/libc/test/src/sys/mman/linux/CMakeLists.txt index 66743be175fe..5402ae030b34 100644 --- a/libc/test/src/sys/mman/linux/CMakeLists.txt +++ b/libc/test/src/sys/mman/linux/CMakeLists.txt @@ -62,3 +62,19 @@ add_libc_unittest( libc.src.sys.mman.posix_madvise libc.test.UnitTest.ErrnoSetterMatcher ) + +add_libc_unittest( + mincore_test + SUITE + libc_sys_mman_unittests + SRCS + mincore_test.cpp + DEPENDS + libc.include.sys_mman + libc.src.errno.errno + libc.src.sys.mman.mmap + libc.src.sys.mman.munmap + libc.src.sys.mman.madvise + libc.src.sys.mman.mincore + libc.test.UnitTest.ErrnoSetterMatcher +) diff --git a/libc/test/src/sys/mman/linux/mincore_test.cpp b/libc/test/src/sys/mman/linux/mincore_test.cpp new file mode 100644 index 000000000000..7c8ca3b4ffa4 --- /dev/null +++ b/libc/test/src/sys/mman/linux/mincore_test.cpp @@ -0,0 +1,115 @@ +//===-- Unittests for mincore ---------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/errno/libc_errno.h" +#include "src/sys/mman/madvise.h" +#include "src/sys/mman/mincore.h" +#include "src/sys/mman/mmap.h" +#include "src/sys/mman/munmap.h" +#include "test/UnitTest/ErrnoSetterMatcher.h" +#include "test/UnitTest/LibcTest.h" +#include "test/UnitTest/Test.h" + +#include // For EXEC_PAGESIZE +#include + +using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; +using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; + +TEST(LlvmLibcMincoreTest, UnMappedMemory) { + libc_errno = 0; + unsigned char vec; + int res = LIBC_NAMESPACE::mincore(nullptr, 1, &vec); + EXPECT_THAT(res, Fails(ENOMEM, -1)); +} + +TEST(LlvmLibcMincoreTest, InvalidVec) { + void *addr = LIBC_NAMESPACE::mmap(nullptr, 4 * EXEC_PAGESIZE, PROT_READ, + MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); + EXPECT_NE(addr, MAP_FAILED); + EXPECT_EQ(reinterpret_cast(addr) % EXEC_PAGESIZE, 0ul); + libc_errno = 0; + int res = LIBC_NAMESPACE::mincore(addr, 1, nullptr); + EXPECT_THAT(res, Fails(EFAULT, -1)); + void *area = + LIBC_NAMESPACE::mmap(nullptr, EXEC_PAGESIZE, PROT_READ | PROT_WRITE, + MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); + EXPECT_NE(area, MAP_FAILED); + unsigned char *ptr = static_cast(area) + EXEC_PAGESIZE - 3; + res = LIBC_NAMESPACE::mincore(addr, 4 * EXEC_PAGESIZE, ptr); + EXPECT_THAT(res, Fails(EFAULT, -1)); + EXPECT_THAT(LIBC_NAMESPACE::munmap(addr, EXEC_PAGESIZE), Succeeds()); + EXPECT_THAT(LIBC_NAMESPACE::munmap(area, 2), Succeeds()); +} + +TEST(LlvmLibcMincoreTest, UnalignedAddr) { + void *addr = LIBC_NAMESPACE::mmap(nullptr, EXEC_PAGESIZE, PROT_READ, + MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); + EXPECT_NE(addr, MAP_FAILED); + EXPECT_EQ(reinterpret_cast(addr) % EXEC_PAGESIZE, 0ul); + libc_errno = 0; + int res = LIBC_NAMESPACE::mincore(static_cast(addr) + 1, 1, nullptr); + EXPECT_THAT(res, Fails(EINVAL, -1)); + EXPECT_THAT(LIBC_NAMESPACE::munmap(addr, EXEC_PAGESIZE), Succeeds()); +} + +TEST(LlvmLibcMincoreTest, NoError) { + void *addr = LIBC_NAMESPACE::mmap(nullptr, EXEC_PAGESIZE, PROT_READ, + MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); + EXPECT_NE(addr, MAP_FAILED); + EXPECT_EQ(reinterpret_cast(addr) % EXEC_PAGESIZE, 0ul); + unsigned char vec; + libc_errno = 0; + int res = LIBC_NAMESPACE::mincore(addr, 1, &vec); + EXPECT_THAT(res, Succeeds()); + EXPECT_THAT(LIBC_NAMESPACE::munmap(addr, EXEC_PAGESIZE), Succeeds()); +} + +TEST(LlvmLibcMincoreTest, NegativeLength) { + void *addr = LIBC_NAMESPACE::mmap(nullptr, EXEC_PAGESIZE, PROT_READ, + MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); + EXPECT_NE(addr, MAP_FAILED); + EXPECT_EQ(reinterpret_cast(addr) % EXEC_PAGESIZE, 0ul); + unsigned char vec; + libc_errno = 0; + int res = LIBC_NAMESPACE::mincore(addr, -1, &vec); + EXPECT_THAT(res, Fails(ENOMEM, -1)); + EXPECT_THAT(LIBC_NAMESPACE::munmap(addr, EXEC_PAGESIZE), Succeeds()); +} + +TEST(LlvmLibcMincoreTest, PageOut) { + unsigned char vec; + void *addr = + LIBC_NAMESPACE::mmap(nullptr, EXEC_PAGESIZE, PROT_READ | PROT_WRITE, + MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); + EXPECT_NE(addr, MAP_FAILED); + EXPECT_EQ(reinterpret_cast(addr) % EXEC_PAGESIZE, 0ul); + + // touch the page + { + static_cast(addr)[0] = 0; + libc_errno = 0; + int res = LIBC_NAMESPACE::mincore(addr, 1, &vec); + EXPECT_EQ(vec & 1u, 1u); + EXPECT_THAT(res, Succeeds()); + } + + // page out the memory + { + libc_errno = 0; + EXPECT_THAT(LIBC_NAMESPACE::madvise(addr, EXEC_PAGESIZE, MADV_DONTNEED), + Succeeds()); + + libc_errno = 0; + int res = LIBC_NAMESPACE::mincore(addr, EXEC_PAGESIZE, &vec); + EXPECT_EQ(vec & 1u, 0u); + EXPECT_THAT(res, Succeeds()); + } + + EXPECT_THAT(LIBC_NAMESPACE::munmap(addr, EXEC_PAGESIZE), Succeeds()); +} -- GitLab From 26f2f9397a681fd6a580bf80104c2e4afd599dca Mon Sep 17 00:00:00 2001 From: Peter Klausler <35819229+klausler@users.noreply.github.com> Date: Thu, 30 Nov 2023 11:23:04 -0800 Subject: [PATCH 020/699] [flang] Update to: Adjust checks of ICHAR/IACHAR argument length (#73972) When applying ICHAR/IACHAR to a character constant with length greater than one, resize the character constant to its first character. --- flang/lib/Evaluate/fold-integer.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/flang/lib/Evaluate/fold-integer.cpp b/flang/lib/Evaluate/fold-integer.cpp index c60648fb195f..ba4bc6a04750 100644 --- a/flang/lib/Evaluate/fold-integer.cpp +++ b/flang/lib/Evaluate/fold-integer.cpp @@ -697,7 +697,8 @@ Expr> FoldIntrinsicFunction( ScalarFunc( #ifndef _MSC_VER [&FromInt64](const Scalar &c) { - return FromInt64(CharacterUtils::ICHAR(c)); + return FromInt64(CharacterUtils::ICHAR( + CharacterUtils::Resize(c, 1))); })); #else // _MSC_VER // MSVC 14 get confused by the original code above and @@ -707,7 +708,8 @@ Expr> FoldIntrinsicFunction( // so remove the FromInt64 error checking lambda that // seems to have caused the proble. [](const Scalar &c) { - return CharacterUtils::ICHAR(c); + return CharacterUtils::ICHAR( + CharacterUtils::Resize(c, 1)); })); #endif // _MSC_VER }, -- GitLab From a112921d88c28b9d3ac30cad7dbc961a33f22926 Mon Sep 17 00:00:00 2001 From: Emilia Kond Date: Thu, 30 Nov 2023 21:26:39 +0200 Subject: [PATCH 021/699] [clang-format] Don't skip stringizing when determining brace kind (#73886) PR #69473 introduced skipping PP directives when determining the brace kind of an lbrace. However, it did so by skipping to the end of the line when encountering a hash character. This means it also skipped to the end of line when encountering a macro stringizing operator, which, unlike PP directives, don't have effect until the end of line. This led to cases where the rbrace could be completely skipped if it was on the same line as a stringizing operator. This patch skips hash characters if we're already in a PP directive, as you can't define a macro inside of a macro Fixes https://github.com/llvm/llvm-project/issues/72662 --- clang/lib/Format/UnwrappedLineParser.cpp | 2 +- clang/unittests/Format/TokenAnnotatorTest.cpp | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/clang/lib/Format/UnwrappedLineParser.cpp b/clang/lib/Format/UnwrappedLineParser.cpp index a5a4419b9823..9a9a16a3caac 100644 --- a/clang/lib/Format/UnwrappedLineParser.cpp +++ b/clang/lib/Format/UnwrappedLineParser.cpp @@ -496,7 +496,7 @@ void UnwrappedLineParser::calculateBraceTypes(bool ExpectClassBody) { do { NextTok = Tokens->getNextToken(); } while (NextTok->is(tok::comment)); - while (NextTok->is(tok::hash)) { + while (NextTok->is(tok::hash) && !Line->InMacroBody) { NextTok = Tokens->getNextToken(); do { NextTok = Tokens->getNextToken(); diff --git a/clang/unittests/Format/TokenAnnotatorTest.cpp b/clang/unittests/Format/TokenAnnotatorTest.cpp index bc734573ce0c..65b1f0f4b576 100644 --- a/clang/unittests/Format/TokenAnnotatorTest.cpp +++ b/clang/unittests/Format/TokenAnnotatorTest.cpp @@ -1851,6 +1851,22 @@ TEST_F(TokenAnnotatorTest, UnderstandsTrailingReturnArrow) { EXPECT_TOKEN(Tokens[13], tok::arrow, TT_Unknown); } +TEST_F(TokenAnnotatorTest, UnderstandHashInMacro) { + auto Tokens = annotate("#define Foo(Bar) \\\n" + " { \\\n" + " #Bar \\\n" + " }"); + ASSERT_EQ(Tokens.size(), 11u) << Tokens; + EXPECT_BRACE_KIND(Tokens[6], BK_Block); + EXPECT_BRACE_KIND(Tokens[9], BK_Block); + + Tokens = annotate("#define Foo(Bar) \\\n" + " { #Bar }"); + ASSERT_EQ(Tokens.size(), 11u) << Tokens; + EXPECT_BRACE_KIND(Tokens[6], BK_Block); + EXPECT_BRACE_KIND(Tokens[9], BK_Block); +} + TEST_F(TokenAnnotatorTest, UnderstandsAttributeMacros) { // '__attribute__' has special handling. auto Tokens = annotate("__attribute__(X) void Foo(void);"); -- GitLab From 7f82c90621770919dc457d8bb5d12d7f3b29e2e1 Mon Sep 17 00:00:00 2001 From: Han-Chung Wang Date: Thu, 30 Nov 2023 11:27:06 -0800 Subject: [PATCH 022/699] [mlir][vector] Add support for vector.maskedstore sub-type emulation. (#73871) The idea is similar to vector.maskedload + vector.store emulation. What the emulation does is: 1. Get a compressed mask and load the data from destination. 2. Bitcast the data to original vector type. 3. Select values between `op.valueToStore` and the data from load using original mask. 4. Bitcast the new value and store it to destination using compressed masked. --- .../Transforms/VectorEmulateNarrowType.cpp | 231 +++++++++++++----- .../Vector/vector-emulate-narrow-type.mlir | 72 ++++++ 2 files changed, 241 insertions(+), 62 deletions(-) diff --git a/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp b/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp index 6aea0343bfc9..ead7d645cb5b 100644 --- a/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp +++ b/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp @@ -32,6 +32,79 @@ using namespace mlir; #define DBGSNL() (llvm::dbgs() << "\n") #define LDBG(X) LLVM_DEBUG(DBGS() << X << "\n") +/// Returns a compressed mask. The mask value is set only if any mask is present +/// in the scale range. E.g., if `scale` equals to 2, the following mask: +/// +/// %mask = [1, 1, 1, 0, 0, 0] +/// +/// will return the following new compressed mask: +/// +/// %mask = [1, 1, 0] +static FailureOr getCompressedMaskOp(OpBuilder &rewriter, + Location loc, Value mask, + int origElements, int scale) { + auto numElements = (origElements + scale - 1) / scale; + + Operation *maskOp = mask.getDefiningOp(); + SmallVector extractOps; + // Finding the mask creation operation. + while (maskOp && !isa(maskOp)) { + if (auto extractOp = dyn_cast(maskOp)) { + maskOp = extractOp.getVector().getDefiningOp(); + extractOps.push_back(extractOp); + } + } + auto createMaskOp = dyn_cast_or_null(maskOp); + auto constantMaskOp = dyn_cast_or_null(maskOp); + if (!createMaskOp && !constantMaskOp) + return failure(); + + // Computing the "compressed" mask. All the emulation logic (i.e. computing + // new mask index) only happens on the last dimension of the vectors. + Operation *newMask = nullptr; + SmallVector shape( + maskOp->getResultTypes()[0].cast().getShape()); + shape.back() = numElements; + auto newMaskType = VectorType::get(shape, rewriter.getI1Type()); + if (createMaskOp) { + OperandRange maskOperands = createMaskOp.getOperands(); + size_t numMaskOperands = maskOperands.size(); + AffineExpr s0; + bindSymbols(rewriter.getContext(), s0); + s0 = s0 + scale - 1; + s0 = s0.floorDiv(scale); + OpFoldResult origIndex = + getAsOpFoldResult(maskOperands[numMaskOperands - 1]); + OpFoldResult maskIndex = + affine::makeComposedFoldedAffineApply(rewriter, loc, s0, origIndex); + SmallVector newMaskOperands(maskOperands.drop_back()); + newMaskOperands.push_back( + getValueOrCreateConstantIndexOp(rewriter, loc, maskIndex)); + newMask = rewriter.create(loc, newMaskType, + newMaskOperands); + } else if (constantMaskOp) { + ArrayRef maskDimSizes = + constantMaskOp.getMaskDimSizes().getValue(); + size_t numMaskOperands = maskDimSizes.size(); + auto origIndex = + cast(maskDimSizes[numMaskOperands - 1]).getInt(); + IntegerAttr maskIndexAttr = + rewriter.getI64IntegerAttr((origIndex + scale - 1) / scale); + SmallVector newMaskDimSizes(maskDimSizes.drop_back()); + newMaskDimSizes.push_back(maskIndexAttr); + newMask = rewriter.create( + loc, newMaskType, rewriter.getArrayAttr(newMaskDimSizes)); + } + + while (!extractOps.empty()) { + newMask = rewriter.create( + loc, newMask->getResults()[0], extractOps.back().getMixedPosition()); + extractOps.pop_back(); + } + + return newMask; +} + namespace { //===----------------------------------------------------------------------===// @@ -99,6 +172,94 @@ struct ConvertVectorStore final : OpConversionPattern { } }; +//===----------------------------------------------------------------------===// +// ConvertVectorMaskedStore +//===----------------------------------------------------------------------===// + +struct ConvertVectorMaskedStore final + : OpConversionPattern { + using OpConversionPattern::OpConversionPattern; + + LogicalResult + matchAndRewrite(vector::MaskedStoreOp op, OpAdaptor adaptor, + ConversionPatternRewriter &rewriter) const override { + + auto loc = op.getLoc(); + auto convertedType = cast(adaptor.getBase().getType()); + Type oldElementType = op.getValueToStore().getType().getElementType(); + Type newElementType = convertedType.getElementType(); + int srcBits = oldElementType.getIntOrFloatBitWidth(); + int dstBits = newElementType.getIntOrFloatBitWidth(); + + if (dstBits % srcBits != 0) { + return rewriter.notifyMatchFailure( + op, "only dstBits % srcBits == 0 supported"); + } + + int scale = dstBits / srcBits; + int origElements = op.getValueToStore().getType().getNumElements(); + if (origElements % scale != 0) + return failure(); + + auto stridedMetadata = + rewriter.create(loc, op.getBase()); + OpFoldResult linearizedIndicesOfr; + std::tie(std::ignore, linearizedIndicesOfr) = + memref::getLinearizedMemRefOffsetAndSize( + rewriter, loc, srcBits, dstBits, + stridedMetadata.getConstifiedMixedOffset(), + stridedMetadata.getConstifiedMixedSizes(), + stridedMetadata.getConstifiedMixedStrides(), + getAsOpFoldResult(adaptor.getIndices())); + Value linearizedIndices = + getValueOrCreateConstantIndexOp(rewriter, loc, linearizedIndicesOfr); + + // Load the whole data and use arith.select to handle the corner cases. + // E.g., given these input values: + // + // %mask = [1, 1, 1, 0, 0, 0] + // %0[%c0, %c0] contains [0x1, 0x2, 0x3, 0x4, 0x5, 0x6] + // %value_to_store = [0x7, 0x8, 0x9, 0xA, 0xB, 0xC] + // + // we'll have + // + // expected output: [0x7, 0x8, 0x9, 0x4, 0x5, 0x6] + // + // %new_mask = [1, 1, 0] + // %maskedload = [0x12, 0x34, 0x0] + // %bitcast = [0x1, 0x2, 0x3, 0x4, 0x0, 0x0] + // %select_using_original_mask = [0x7, 0x8, 0x9, 0x4, 0x0, 0x0] + // %packed_data = [0x78, 0x94, 0x00] + // + // Using the new mask to store %packed_data results in expected output. + FailureOr newMask = + getCompressedMaskOp(rewriter, loc, op.getMask(), origElements, scale); + if (failed(newMask)) + return failure(); + + auto numElements = (origElements + scale - 1) / scale; + auto newType = VectorType::get(numElements, newElementType); + auto passThru = rewriter.create( + loc, newType, rewriter.getZeroAttr(newType)); + + auto newLoad = rewriter.create( + loc, newType, adaptor.getBase(), linearizedIndices, + newMask.value()->getResult(0), passThru); + + Value valueToStore = rewriter.create( + loc, op.getValueToStore().getType(), newLoad); + valueToStore = rewriter.create( + loc, op.getMask(), op.getValueToStore(), valueToStore); + valueToStore = + rewriter.create(loc, newType, valueToStore); + + rewriter.replaceOpWithNewOp( + op, adaptor.getBase(), linearizedIndices, newMask.value()->getResult(0), + valueToStore); + return success(); + } +}; + //===----------------------------------------------------------------------===// // ConvertVectorLoad //===----------------------------------------------------------------------===// @@ -236,7 +397,6 @@ struct ConvertVectorMaskedLoad final // TODO: Currently, only the even number of elements loading is supported. // To deal with the odd number of elements, one has to extract the // subvector at the proper offset after bit-casting. - auto origType = op.getVectorType(); auto origElements = origType.getNumElements(); if (origElements % scale != 0) @@ -244,7 +404,6 @@ struct ConvertVectorMaskedLoad final auto stridedMetadata = rewriter.create(loc, op.getBase()); - OpFoldResult linearizedIndices; std::tie(std::ignore, linearizedIndices) = memref::getLinearizedMemRefOffsetAndSize( @@ -254,66 +413,13 @@ struct ConvertVectorMaskedLoad final stridedMetadata.getConstifiedMixedStrides(), getAsOpFoldResult(adaptor.getIndices())); - auto numElements = (origElements + scale - 1) / scale; - auto newType = VectorType::get(numElements, newElementType); - - auto maskOp = op.getMask().getDefiningOp(); - SmallVector extractOps; - // Finding the mask creation operation. - while (maskOp && - !isa(maskOp)) { - if (auto extractOp = dyn_cast(maskOp)) { - maskOp = extractOp.getVector().getDefiningOp(); - extractOps.push_back(extractOp); - } - } - auto createMaskOp = dyn_cast_or_null(maskOp); - auto constantMaskOp = dyn_cast_or_null(maskOp); - if (!createMaskOp && !constantMaskOp) + FailureOr newMask = + getCompressedMaskOp(rewriter, loc, op.getMask(), origElements, scale); + if (failed(newMask)) return failure(); - // Computing the "compressed" mask. All the emulation logic (i.e. computing - // new mask index) only happens on the last dimension of the vectors. - Operation *newMask = nullptr; - auto shape = llvm::to_vector( - maskOp->getResultTypes()[0].cast().getShape().drop_back()); - shape.push_back(numElements); - auto newMaskType = VectorType::get(shape, rewriter.getI1Type()); - if (createMaskOp) { - auto maskOperands = createMaskOp.getOperands(); - auto numMaskOperands = maskOperands.size(); - AffineExpr s0; - bindSymbols(rewriter.getContext(), s0); - s0 = s0 + scale - 1; - s0 = s0.floorDiv(scale); - OpFoldResult origIndex = - getAsOpFoldResult(maskOperands[numMaskOperands - 1]); - OpFoldResult maskIndex = - affine::makeComposedFoldedAffineApply(rewriter, loc, s0, origIndex); - auto newMaskOperands = llvm::to_vector(maskOperands.drop_back()); - newMaskOperands.push_back( - getValueOrCreateConstantIndexOp(rewriter, loc, maskIndex)); - newMask = rewriter.create(loc, newMaskType, - newMaskOperands); - } else if (constantMaskOp) { - auto maskDimSizes = constantMaskOp.getMaskDimSizes().getValue(); - auto numMaskOperands = maskDimSizes.size(); - auto origIndex = - cast(maskDimSizes[numMaskOperands - 1]).getInt(); - auto maskIndex = - rewriter.getI64IntegerAttr((origIndex + scale - 1) / scale); - auto newMaskDimSizes = llvm::to_vector(maskDimSizes.drop_back()); - newMaskDimSizes.push_back(maskIndex); - newMask = rewriter.create( - loc, newMaskType, rewriter.getArrayAttr(newMaskDimSizes)); - } - - while (!extractOps.empty()) { - newMask = rewriter.create( - loc, newMask->getResults()[0], extractOps.back().getMixedPosition()); - extractOps.pop_back(); - } - + auto numElements = (origElements + scale - 1) / scale; + auto newType = VectorType::get(numElements, newElementType); auto newPassThru = rewriter.create(loc, newType, op.getPassThru()); @@ -321,7 +427,7 @@ struct ConvertVectorMaskedLoad final auto newLoad = rewriter.create( loc, newType, adaptor.getBase(), getValueOrCreateConstantIndexOp(rewriter, loc, linearizedIndices), - newMask->getResult(0), newPassThru); + newMask.value()->getResult(0), newPassThru); // Setting the part that originally was not effectively loaded from memory // to pass through. @@ -821,7 +927,8 @@ void vector::populateVectorNarrowTypeEmulationPatterns( // Populate `vector.*` conversion patterns. patterns.add(typeConverter, patterns.getContext()); + ConvertVectorMaskedStore, ConvertVectorTransferRead>( + typeConverter, patterns.getContext()); } void vector::populateVectorNarrowTypeRewritePatterns( diff --git a/mlir/test/Dialect/Vector/vector-emulate-narrow-type.mlir b/mlir/test/Dialect/Vector/vector-emulate-narrow-type.mlir index af0f98a1c447..cba299b2a1d9 100644 --- a/mlir/test/Dialect/Vector/vector-emulate-narrow-type.mlir +++ b/mlir/test/Dialect/Vector/vector-emulate-narrow-type.mlir @@ -428,3 +428,75 @@ func.func @vector_store_i4_dynamic(%arg0: vector<8xi4>, %arg1: index, %arg2: ind // CHECK32: %[[INDEX:.+]] = affine.apply #[[MAP1]]()[%[[ARG3]], %[[ARG2]], %[[ARG4]]] // CHECK32: %[[VEC_I8:.+]] = vector.bitcast %[[ARG0]] : vector<8xi4> to vector<1xi32> // CHECK32: vector.store %[[VEC_I8:.+]], %[[ALLOC:.+]][%[[INDEX:.+]]] : memref, vector<1xi32> + +// ----- + +func.func @vector_maskedstore_i8(%arg0: index, %arg1: index, %arg2: index, %value: vector<8xi8>) { + %0 = memref.alloc() : memref<3x8xi8> + %mask = vector.create_mask %arg2 : vector<8xi1> + vector.maskedstore %0[%arg0, %arg1], %mask, %value : memref<3x8xi8>, vector<8xi1>, vector<8xi8> + return +} +// Expect no conversions, i8 is supported. +// CHECK: func @vector_maskedstore_i8( +// CHECK-SAME: %[[ARG0:[a-zA-Z0-9]+]] +// CHECK-SAME: %[[ARG1:[a-zA-Z0-9]+]] +// CHECK-SAME: %[[ARG2:[a-zA-Z0-9]+]] +// CHECK-SAME: %[[VAL:[a-zA-Z0-9]+]] +// CHECK-NEXT: %[[ALLOC:.+]] = memref.alloc() : memref<3x8xi8> +// CHECK-NEXT: %[[MASK:.+]] = vector.create_mask %[[ARG2]] : vector<8xi1> +// CHECK-NEXT: vector.maskedstore %[[ALLOC]][%[[ARG0]], %[[ARG1]]], %[[MASK]], %[[VAL]] +// CHECK-NEXT: return + +// CHECK32-DAG: #[[LOAD_IDX_MAP:.+]] = affine_map<()[s0, s1] -> (s0 * 2 + s1 floordiv 4)> +// CHECK32-DAG: #[[MASK_IDX_MAP:.+]] = affine_map<()[s0] -> ((s0 + 3) floordiv 4)> +// CHECK32: func @vector_maskedstore_i8( +// CHECK32-SAME: %[[ARG0:[a-zA-Z0-9]+]] +// CHECK32-SAME: %[[ARG1:[a-zA-Z0-9]+]] +// CHECK32-SAME: %[[ARG2:[a-zA-Z0-9]+]] +// CHECK32-SAME: %[[VAL:[a-zA-Z0-9]+]] +// CHECK32: %[[ALLOC:.+]] = memref.alloc() : memref<6xi32> +// CHECK32: %[[ORIG_MASK:.+]] = vector.create_mask %[[ARG2]] : vector<8xi1> +// CHECK32: %[[LIDX:.+]] = affine.apply #[[LOAD_IDX_MAP]]()[%[[ARG0]], %[[ARG1]]] +// CHECK32: %[[MASK_IDX:.+]] = affine.apply #[[MASK_IDX_MAP]]()[%[[ARG2]]] +// CHECK32: %[[NEW_MASK:.+]] = vector.create_mask %[[MASK_IDX]] : vector<2xi1> +// CHECK32: %[[PASS_THRU:.+]] = arith.constant dense<0> : vector<2xi32> +// CHECK32: %[[LOAD:.+]] = vector.maskedload %[[ALLOC]][%[[LIDX]]], %[[NEW_MASK]], %[[PASS_THRU]] +// CHECK32: %[[BITCAST:.+]] = vector.bitcast %[[LOAD]] : vector<2xi32> to vector<8xi8> +// CHECK32: %[[SELECT:.+]] = arith.select %[[ORIG_MASK]], %[[VAL]], %[[BITCAST]] : vector<8xi1>, vector<8xi8> +// CHECK32: %[[NEW_VAL:.+]] = vector.bitcast %[[SELECT]] : vector<8xi8> to vector<2xi32> +// CHECK32: vector.maskedstore %[[ALLOC]][%[[LIDX]]], %[[NEW_MASK]], %[[NEW_VAL]] + +// ----- + +func.func @vector_cst_maskedstore_i8(%arg0: index, %arg1: index, %value: vector<8xi8>) { + %0 = memref.alloc() : memref<3x8xi8> + %mask = vector.constant_mask [4] : vector<8xi1> + vector.maskedstore %0[%arg0, %arg1], %mask, %value : memref<3x8xi8>, vector<8xi1>, vector<8xi8> + return +} +// Expect no conversions, i8 is supported. +// CHECK: func @vector_cst_maskedstore_i8( +// CHECK-SAME: %[[ARG0:[a-zA-Z0-9]+]] +// CHECK-SAME: %[[ARG1:[a-zA-Z0-9]+]] +// CHECK-SAME: %[[VAL:[a-zA-Z0-9]+]] +// CHECK-NEXT: %[[ALLOC:.+]] = memref.alloc() : memref<3x8xi8> +// CHECK-NEXT: %[[MASK:.+]] = vector.constant_mask [4] : vector<8xi1> +// CHECK-NEXT: vector.maskedstore %[[ALLOC]][%[[ARG0]], %[[ARG1]]], %[[MASK]], %[[VAL]] +// CHECK-NEXT: return + +// CHECK32-DAG: #[[LOAD_IDX_MAP:.+]] = affine_map<()[s0, s1] -> (s0 * 2 + s1 floordiv 4)> +// CHECK32: func @vector_cst_maskedstore_i8( +// CHECK32-SAME: %[[ARG0:[a-zA-Z0-9]+]] +// CHECK32-SAME: %[[ARG1:[a-zA-Z0-9]+]] +// CHECK32-SAME: %[[VAL:[a-zA-Z0-9]+]] +// CHECK32: %[[ALLOC:.+]] = memref.alloc() : memref<6xi32> +// CHECK32: %[[ORIG_MASK:.+]] = vector.constant_mask [4] : vector<8xi1> +// CHECK32: %[[LIDX:.+]] = affine.apply #[[LOAD_IDX_MAP]]()[%[[ARG0]], %[[ARG1]]] +// CHECK32: %[[NEW_MASK:.+]] = vector.constant_mask [1] : vector<2xi1> +// CHECK32: %[[PASS_THRU:.+]] = arith.constant dense<0> : vector<2xi32> +// CHECK32: %[[LOAD:.+]] = vector.maskedload %[[ALLOC]][%[[LIDX]]], %[[NEW_MASK]], %[[PASS_THRU]] +// CHECK32: %[[BITCAST:.+]] = vector.bitcast %[[LOAD]] : vector<2xi32> to vector<8xi8> +// CHECK32: %[[SELECT:.+]] = arith.select %[[ORIG_MASK]], %[[VAL]], %[[BITCAST]] : vector<8xi1>, vector<8xi8> +// CHECK32: %[[NEW_VAL:.+]] = vector.bitcast %[[SELECT]] : vector<8xi8> to vector<2xi32> +// CHECK32: vector.maskedstore %[[ALLOC]][%[[LIDX]]], %[[NEW_MASK]], %[[NEW_VAL]] -- GitLab From 96906a92bebe76a1f6510701756aa40280b3a019 Mon Sep 17 00:00:00 2001 From: Jacob Lambert Date: Thu, 30 Nov 2023 11:33:39 -0800 Subject: [PATCH 023/699] [clang-offload-bundler][NFC] Remove blank line in doc (#73968) --- clang/docs/ClangOffloadBundler.rst | 1 - 1 file changed, 1 deletion(-) diff --git a/clang/docs/ClangOffloadBundler.rst b/clang/docs/ClangOffloadBundler.rst index 1d163db1a9a6..1f8c85a08f8c 100644 --- a/clang/docs/ClangOffloadBundler.rst +++ b/clang/docs/ClangOffloadBundler.rst @@ -500,7 +500,6 @@ Additional Options while Archive Unbundling as defined in :ref:`code-object-composition` before creating device-specific archive(s). - **-debug-only=CodeObjectCompatibility** Verbose printing of matched/unmatched comparisons between bundle entry id of a device binary from HDA and bundle entry ID of a given target processor -- GitLab From f1eddf5c39e7e203fbc8fb5f9293b9baa8bbb04b Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Thu, 30 Nov 2023 11:42:53 -0800 Subject: [PATCH 024/699] [Driver] Mark OpenBSD-specific -nopie as TargetSpecific after #72578 so that we get an `error: unsupported option '-nopie' for target ...` instead of a warning. --- clang/include/clang/Driver/Options.td | 2 +- clang/test/Driver/linux-ld.c | 6 +++++- clang/test/Driver/solaris-ld.c | 6 +++--- 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 7dd2755350f7..fae70e61375d 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -5169,7 +5169,7 @@ def nodriverkitlib : Flag<["-"], "nodriverkitlib">; def nofixprebinding : Flag<["-"], "nofixprebinding">; def nolibc : Flag<["-"], "nolibc">; def nomultidefs : Flag<["-"], "nomultidefs">; -def nopie : Flag<["-"], "nopie">, Visibility<[ClangOption, FlangOption]>; +def nopie : Flag<["-"], "nopie">, Visibility<[ClangOption, FlangOption]>, Flags<[TargetSpecific]>; // OpenBSD def no_pie : Flag<["-"], "no-pie">, Visibility<[ClangOption, FlangOption]>; def noprebind : Flag<["-"], "noprebind">; def noprofilelib : Flag<["-"], "noprofilelib">; diff --git a/clang/test/Driver/linux-ld.c b/clang/test/Driver/linux-ld.c index 7adb078f755d..15643d6491ae 100644 --- a/clang/test/Driver/linux-ld.c +++ b/clang/test/Driver/linux-ld.c @@ -209,7 +209,7 @@ // CHECK-CLANG-LD-STATIC-PIE-STATIC: "{{.*}}rcrt1.o" // CHECK-CLANG-LD-STATIC-PIE-STATIC: "--start-group" "-lgcc" "-lgcc_eh" "-lc" "--end-group" // -// RUN: not %clang -static-pie -nopie -### %s -no-pie 2>&1 \ +// RUN: not %clang -static-pie -### %s -no-pie 2>&1 \ // RUN: --target=x86_64-unknown-linux -rtlib=platform \ // RUN: --gcc-toolchain="" \ // RUN: --sysroot=%S/Inputs/basic_linux_tree \ @@ -1861,3 +1861,7 @@ // CHECK-OE-AARCH64: "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed" "-lc" "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed" // CHECK-OE-AARCH64: "[[SYSROOT]]/usr/lib64/aarch64-oe-linux/6.3.0{{/|\\\\}}crtend.o" // CHECK-OE-AARCH64: "[[SYSROOT]]/usr/lib64/aarch64-oe-linux/6.3.0/../../../lib64{{/|\\\\}}crtn.o" + +/// -nopie is OpenBSD-specific. +// RUN: not %clang -### --target=x86_64-unknown-linux-gnu %s -nopie 2>&1 | FileCheck %s --check-prefix=CHECK-NOPIE +// CHECK-NOPIE: error: unsupported option '-nopie' for target 'x86_64-unknown-linux-gnu' diff --git a/clang/test/Driver/solaris-ld.c b/clang/test/Driver/solaris-ld.c index 8f7f168c3872..df4fa7b4c9eb 100644 --- a/clang/test/Driver/solaris-ld.c +++ b/clang/test/Driver/solaris-ld.c @@ -132,11 +132,11 @@ // RUN: --gcc-toolchain="" \ // RUN: --sysroot=%S/Inputs/solaris_sparc_tree 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-PIE-GLD %s -// RUN: %clang --target=sparc-sun-solaris2.11 -### %s -nopie -fuse-ld= \ +// RUN: %clang --target=sparc-sun-solaris2.11 -### %s -no-pie -fuse-ld= \ // RUN: --gcc-toolchain="" \ // RUN: --sysroot=%S/Inputs/solaris_sparc_tree 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-NOPIE-LD %s -// RUN: %clang --target=sparc-sun-solaris2.11 -### %s -nopie -fuse-ld=gld \ +// RUN: %clang --target=sparc-sun-solaris2.11 -### %s -no-pie -fuse-ld=gld \ // RUN: --gcc-toolchain="" \ // RUN: --sysroot=%S/Inputs/solaris_sparc_tree 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-NOPIE-GLD %s @@ -191,7 +191,7 @@ // RUN: --gcc-toolchain="" \ // RUN: --sysroot=%S/Inputs/solaris_sparc_tree 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-CRTS %s -// RUN: %clang --target=sparc-sun-solaris2.11 -### %s -nopie \ +// RUN: %clang --target=sparc-sun-solaris2.11 -### %s -no-pie \ // RUN: --gcc-toolchain="" \ // RUN: --sysroot=%S/Inputs/solaris_sparc_tree 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-NOCRTS %s -- GitLab From bf4a876309cdc73e3907801abba02d2f1d2d7b6e Mon Sep 17 00:00:00 2001 From: Peter Klausler <35819229+klausler@users.noreply.github.com> Date: Thu, 30 Nov 2023 11:44:43 -0800 Subject: [PATCH 025/699] [flang] Move and extend REDUCE() compile-time checking (#72570) Move the code to check the arguments of references to the intrinsic function REDUCE() into Semantics/check-calls.cpp, and add checks for several requirements from the standard that weren't yet caught. --- flang/lib/Evaluate/intrinsics.cpp | 117 +++++-------------- flang/lib/Semantics/check-call.cpp | 140 ++++++++++++++++++++++- flang/test/Semantics/misc-intrinsics.f90 | 8 +- flang/test/Semantics/reduce01.f90 | 45 +++++++- 4 files changed, 213 insertions(+), 97 deletions(-) diff --git a/flang/lib/Evaluate/intrinsics.cpp b/flang/lib/Evaluate/intrinsics.cpp index c5faf319fafb..08cec73d88ce 100644 --- a/flang/lib/Evaluate/intrinsics.cpp +++ b/flang/lib/Evaluate/intrinsics.cpp @@ -2330,6 +2330,12 @@ std::optional IntrinsicInterface::Match( } if (auto dc{characteristics::DummyArgument::FromActual(std::move(kw), *expr, context, /*forImplicitInterface=*/false)}) { + if (auto *dummyProc{ + std::get_if(&dc->u)}) { + // Dummy procedures are never elemental. + dummyProc->procedure.value().attrs.reset( + characteristics::Procedure::Attr::Elemental); + } dummyArgs.emplace_back(std::move(*dc)); if (d.typePattern.kindCode == KindCode::same && !sameDummyArg) { sameDummyArg = j; @@ -2874,8 +2880,7 @@ static bool CheckAtomicDefineAndRef(FoldingContext &context, } // Applies any semantic checks peculiar to an intrinsic. -// TODO: Move the rest of these checks to Semantics/check-call.cpp, which is -// where ASSOCIATED() and TRANSFER() are now validated. +// TODO: Move the rest of these checks to Semantics/check-call.cpp. static bool ApplySpecificChecks(SpecificCall &call, FoldingContext &context) { bool ok{true}; const std::string &name{call.specificIntrinsic.name}; @@ -2891,7 +2896,7 @@ static bool ApplySpecificChecks(SpecificCall &call, FoldingContext &context) { arg ? arg->sourceLocation() : context.messages().at(), "Argument of ALLOCATED() must be an ALLOCATABLE object or component"_err_en_US); } - } else if (name == "associated") { + } else if (name == "associated" || name == "reduce") { // Now handled in Semantics/check-call.cpp } else if (name == "atomic_and" || name == "atomic_or" || name == "atomic_xor") { @@ -2967,90 +2972,6 @@ static bool ApplySpecificChecks(SpecificCall &call, FoldingContext &context) { arg ? arg->sourceLocation() : context.messages().at(), "Argument of PRESENT() must be the name of an OPTIONAL dummy argument"_err_en_US); } - } else if (name == "reduce") { // 16.9.161 - std::optional arrayType; - if (const auto &array{call.arguments[0]}) { - arrayType = array->GetType(); - } - std::optional procChars; - parser::CharBlock at{context.messages().at()}; - if (const auto &operation{call.arguments[1]}) { - if (const auto *expr{operation->UnwrapExpr()}) { - if (const auto *designator{ - std::get_if(&expr->u)}) { - procChars = - characteristics::Procedure::Characterize(*designator, context); - } else if (const auto *ref{std::get_if(&expr->u)}) { - procChars = characteristics::Procedure::Characterize(*ref, context); - } - } - if (auto operationAt{operation->sourceLocation()}) { - at = *operationAt; - } - } - if (!arrayType || !procChars) { - ok = false; // error recovery - } else { - const auto *result{procChars->functionResult->GetTypeAndShape()}; - if (!procChars->IsPure() || procChars->dummyArguments.size() != 2 || - !procChars->functionResult) { - ok = false; - context.messages().Say(at, - "OPERATION= argument of REDUCE() must be a pure function of two data arguments"_err_en_US); - } else if (!result || result->Rank() != 0) { - ok = false; - context.messages().Say(at, - "OPERATION= argument of REDUCE() must be a scalar function"_err_en_US); - } else if (result->type().IsPolymorphic() || - !arrayType->IsTkLenCompatibleWith(result->type())) { - ok = false; - context.messages().Say(at, - "OPERATION= argument of REDUCE() must have the same type as ARRAY="_err_en_US); - } else { - const characteristics::DummyDataObject *data[2]{}; - for (int j{0}; j < 2; ++j) { - const auto &dummy{procChars->dummyArguments.at(j)}; - data[j] = std::get_if(&dummy.u); - ok = ok && data[j]; - } - if (!ok) { - context.messages().Say(at, - "OPERATION= argument of REDUCE() may not have dummy procedure arguments"_err_en_US); - } else { - for (int j{0}; j < 2; ++j) { - ok = ok && - !data[j]->attrs.test( - characteristics::DummyDataObject::Attr::Optional) && - !data[j]->attrs.test( - characteristics::DummyDataObject::Attr::Allocatable) && - !data[j]->attrs.test( - characteristics::DummyDataObject::Attr::Pointer) && - data[j]->type.Rank() == 0 && - !data[j]->type.type().IsPolymorphic() && - data[j]->type.type().IsTkCompatibleWith(*arrayType); - } - if (!ok) { - context.messages().Say(at, - "Arguments of OPERATION= procedure of REDUCE() must be both scalar of the same type as ARRAY=, and neither allocatable, pointer, polymorphic, nor optional"_err_en_US); - } else if (data[0]->attrs.test(characteristics::DummyDataObject:: - Attr::Asynchronous) != - data[1]->attrs.test( - characteristics::DummyDataObject::Attr::Asynchronous) || - data[0]->attrs.test( - characteristics::DummyDataObject::Attr::Volatile) != - data[1]->attrs.test( - characteristics::DummyDataObject::Attr::Volatile) || - data[0]->attrs.test( - characteristics::DummyDataObject::Attr::Target) != - data[1]->attrs.test( - characteristics::DummyDataObject::Attr::Target)) { - ok = false; - context.messages().Say(at, - "If either argument of the OPERATION= procedure of REDUCE() has the ASYNCHRONOUS, VOLATILE, or TARGET attribute, both must have that attribute"_err_en_US); - } - } - } - } } else if (name == "ucobound") { return CheckDimAgainstCorank(call, context); } @@ -3143,6 +3064,28 @@ std::optional IntrinsicProcTable::Implementation::Probe( } else if (buffer.empty()) { buffer.Annex(std::move(localBuffer)); } else { + // When there are multiple entries in the table for an + // intrinsic that has multiple forms depending on the + // presence of DIM=, use messages from a later entry if + // the messages from an earlier entry complain about the + // DIM= argument and it wasn't specified with a keyword. + for (const auto &m : buffer.messages()) { + if (m.ToString().find("'dim='") != std::string::npos) { + bool hadDimKeyword{false}; + for (const auto &a : arguments) { + if (a) { + if (auto kw{a->keyword()}; kw && kw == "dim") { + hadDimKeyword = true; + break; + } + } + } + if (!hadDimKeyword) { + buffer = std::move(localBuffer); + } + break; + } + } localBuffer.clear(); } return std::nullopt; diff --git a/flang/lib/Semantics/check-call.cpp b/flang/lib/Semantics/check-call.cpp index b3f3b74b04ee..f28a44e27ad6 100644 --- a/flang/lib/Semantics/check-call.cpp +++ b/flang/lib/Semantics/check-call.cpp @@ -1162,7 +1162,7 @@ static void CheckExplicitInterfaceArg(evaluate::ActualArgument &arg, messages.Say( "Assumed-type '%s' may be associated only with an assumed-type %s"_err_en_US, assumed.name(), dummyName); - } else if (object.type.attrs().test(evaluate::characteristics:: + } else if (object.type.attrs().test(characteristics:: TypeAndShape::Attr::AssumedRank) && !IsAssumedShape(assumed) && !evaluate::IsAssumedRank(assumed)) { @@ -1414,6 +1414,142 @@ static void CheckAssociated(evaluate::ActualArguments &arguments, } } +// REDUCE (F'2023 16.9.173) +static void CheckReduce( + evaluate::ActualArguments &arguments, evaluate::FoldingContext &context) { + std::optional arrayType; + parser::ContextualMessages &messages{context.messages()}; + if (const auto &array{arguments[0]}) { + arrayType = array->GetType(); + if (!arguments[/*identity=*/4]) { + if (const auto *expr{array->UnwrapExpr()}) { + if (auto shape{ + evaluate::GetShape(context, *expr, /*invariantOnly=*/false)}) { + if (const auto &dim{arguments[2]}; dim && array->Rank() > 1) { + // Partial reduction + auto dimVal{evaluate::ToInt64(dim->UnwrapExpr())}; + std::int64_t j{0}; + int zeroDims{0}; + bool isSelectedDimEmpty{false}; + for (const auto &extent : *shape) { + ++j; + if (evaluate::ToInt64(extent) == 0) { + ++zeroDims; + isSelectedDimEmpty |= dimVal && j == *dimVal; + } + } + if (isSelectedDimEmpty && zeroDims == 1) { + messages.Say( + "IDENTITY= must be present when DIM=%d and the array has zero extent on that dimension"_err_en_US, + static_cast(dimVal.value())); + } + } else { // no DIM= or DIM=1 on a vector: total reduction + for (const auto &extent : *shape) { + if (evaluate::ToInt64(extent) == 0) { + messages.Say( + "IDENTITY= must be present when the array is empty and the result is scalar"_err_en_US); + break; + } + } + } + } + } + } + } + std::optional procChars; + if (const auto &operation{arguments[1]}) { + if (const auto *expr{operation->UnwrapExpr()}) { + if (const auto *designator{ + std::get_if(&expr->u)}) { + procChars = + characteristics::Procedure::Characterize(*designator, context); + } else if (const auto *ref{ + std::get_if(&expr->u)}) { + procChars = characteristics::Procedure::Characterize(*ref, context); + } + } + } + const auto *result{ + procChars ? procChars->functionResult->GetTypeAndShape() : nullptr}; + if (!procChars || !procChars->IsPure() || + procChars->dummyArguments.size() != 2 || !procChars->functionResult) { + messages.Say( + "OPERATION= argument of REDUCE() must be a pure function of two data arguments"_err_en_US); + } else if (!result || result->Rank() != 0) { + messages.Say( + "OPERATION= argument of REDUCE() must be a scalar function"_err_en_US); + } else if (result->type().IsPolymorphic() || + (arrayType && !arrayType->IsTkLenCompatibleWith(result->type()))) { + messages.Say( + "OPERATION= argument of REDUCE() must have the same type as ARRAY="_err_en_US); + } else { + const characteristics::DummyDataObject *data[2]{}; + for (int j{0}; j < 2; ++j) { + const auto &dummy{procChars->dummyArguments.at(j)}; + data[j] = std::get_if(&dummy.u); + } + if (!data[0] || !data[1]) { + messages.Say( + "OPERATION= argument of REDUCE() may not have dummy procedure arguments"_err_en_US); + } else { + for (int j{0}; j < 2; ++j) { + if (data[j]->attrs.test( + characteristics::DummyDataObject::Attr::Optional) || + data[j]->attrs.test( + characteristics::DummyDataObject::Attr::Allocatable) || + data[j]->attrs.test( + characteristics::DummyDataObject::Attr::Pointer) || + data[j]->type.Rank() != 0 || data[j]->type.type().IsPolymorphic() || + (arrayType && + !data[j]->type.type().IsTkCompatibleWith(*arrayType))) { + messages.Say( + "Arguments of OPERATION= procedure of REDUCE() must be both scalar of the same type as ARRAY=, and neither allocatable, pointer, polymorphic, nor optional"_err_en_US); + } + } + static constexpr characteristics::DummyDataObject::Attr attrs[]{ + characteristics::DummyDataObject::Attr::Asynchronous, + characteristics::DummyDataObject::Attr::Target, + characteristics::DummyDataObject::Attr::Value, + }; + for (std::size_t j{0}; j < sizeof attrs / sizeof *attrs; ++j) { + if (data[0]->attrs.test(attrs[j]) != data[1]->attrs.test(attrs[j])) { + messages.Say( + "If either argument of the OPERATION= procedure of REDUCE() has the ASYNCHRONOUS, TARGET, or VALUE attribute, both must have that attribute"_err_en_US); + break; + } + } + } + } + // When the MASK= is present and has no .TRUE. element, and there is + // no IDENTITY=, it's an error. + if (const auto &mask{arguments[3]}; mask && !arguments[/*identity*/ 4]) { + if (const auto *expr{mask->UnwrapExpr()}) { + if (const auto *logical{ + std::get_if>(&expr->u)}) { + if (common::visit( + [](const auto &kindExpr) { + using KindExprType = std::decay_t; + using KindLogical = typename KindExprType::Result; + if (const auto *c{evaluate::UnwrapConstantValue( + kindExpr)}) { + for (const auto &element : c->values()) { + if (element.IsTrue()) { + return false; + } + } + return true; + } + return false; + }, + logical->u)) { + messages.Say( + "MASK= has no .TRUE. element, so IDENTITY= must be present"_err_en_US); + } + } + } + } +} + // TRANSFER (16.9.193) static void CheckTransferOperandType(SemanticsContext &context, const evaluate::DynamicType &type, const char *which) { @@ -1486,6 +1622,8 @@ static void CheckSpecificIntrinsic(evaluate::ActualArguments &arguments, const evaluate::SpecificIntrinsic &intrinsic) { if (intrinsic.name == "associated") { CheckAssociated(arguments, context, scope); + } else if (intrinsic.name == "reduce") { + CheckReduce(arguments, context.foldingContext()); } else if (intrinsic.name == "transfer") { CheckTransfer(arguments, context, scope); } diff --git a/flang/test/Semantics/misc-intrinsics.f90 b/flang/test/Semantics/misc-intrinsics.f90 index 195906eef9d7..14dcdb05ac6c 100644 --- a/flang/test/Semantics/misc-intrinsics.f90 +++ b/flang/test/Semantics/misc-intrinsics.f90 @@ -10,17 +10,17 @@ program test_size real, dimension(..) :: assumedRank !ERROR: A dim= argument is required for 'size' when the array is assumed-size print *, size(arg) - !ERROR: missing mandatory 'dim=' argument + !ERROR: A dim= argument is required for 'ubound' when the array is assumed-size print *, ubound(arg) !ERROR: The 'source=' argument to the intrinsic function 'shape' may not be assumed-size print *, shape(arg) !ERROR: The 'harvest=' argument to the intrinsic procedure 'random_number' may not be assumed-size call random_number(arg) - !ERROR: missing mandatory 'dim=' argument + !ERROR: 'array=' argument has unacceptable rank 0 print *, lbound(scalar) !ERROR: 'array=' argument has unacceptable rank 0 print *, size(scalar) - !ERROR: missing mandatory 'dim=' argument + !ERROR: 'array=' argument has unacceptable rank 0 print *, ubound(scalar) !ERROR: DIM=0 dimension must be positive print *, lbound(arg, 0) @@ -45,7 +45,7 @@ program test_size rank(*) !ERROR: A dim= argument is required for 'size' when the array is assumed-size print *, size(assumedRank) - !ERROR: missing mandatory 'dim=' argument + !ERROR: A dim= argument is required for 'ubound' when the array is assumed-size print *, ubound(assumedRank) !ERROR: The 'source=' argument to the intrinsic function 'shape' may not be assumed-size print *, shape(assumedRank) diff --git a/flang/test/Semantics/reduce01.f90 b/flang/test/Semantics/reduce01.f90 index 8c5a46312ec0..ad63a42d73ca 100644 --- a/flang/test/Semantics/reduce01.f90 +++ b/flang/test/Semantics/reduce01.f90 @@ -5,6 +5,10 @@ module m character(len=len) :: ch end type contains + pure real function f(x,y) + real, intent(in) :: x, y + f = x + y + end function impure real function f1(x,y) f1 = x + y end function @@ -47,10 +51,20 @@ module m real, intent(in) :: y f9 = x + y end function - pure real function f10(x,y) + pure real function f10a(x,y) + real, intent(in), asynchronous :: x + real, intent(in) :: y + f10a = x + y + end function + pure real function f10b(x,y) real, intent(in), target :: x real, intent(in) :: y - f10 = x + y + f10b = x + y + end function + pure real function f10c(x,y) + real, intent(in), value :: x + real, intent(in) :: y + f10c = x + y end function pure function f11(x,y) result(res) type(pdt(*)), intent(in) :: x, y @@ -59,7 +73,7 @@ module m end function subroutine errors - real :: a(10,10), b + real :: a(10,10), b, c(10) !ERROR: OPERATION= argument of REDUCE() must be a pure function of two data arguments b = reduce(a, f1) !ERROR: OPERATION= argument of REDUCE() must be a scalar function @@ -78,8 +92,29 @@ module m b = reduce(a, f8) !ERROR: Arguments of OPERATION= procedure of REDUCE() must be both scalar of the same type as ARRAY=, and neither allocatable, pointer, polymorphic, nor optional b = reduce(a, f9) - !ERROR: If either argument of the OPERATION= procedure of REDUCE() has the ASYNCHRONOUS, VOLATILE, or TARGET attribute, both must have that attribute - b = reduce(a, f10) + !ERROR: If either argument of the OPERATION= procedure of REDUCE() has the ASYNCHRONOUS, TARGET, or VALUE attribute, both must have that attribute + b = reduce(a, f10a) + !ERROR: If either argument of the OPERATION= procedure of REDUCE() has the ASYNCHRONOUS, TARGET, or VALUE attribute, both must have that attribute + b = reduce(a, f10b) + !ERROR: If either argument of the OPERATION= procedure of REDUCE() has the ASYNCHRONOUS, TARGET, or VALUE attribute, both must have that attribute + b = reduce(a, f10c) + !ERROR: IDENTITY= must be present when the array is empty and the result is scalar + b = reduce(a(1:0,:), f) + !ERROR: IDENTITY= must be present when the array is empty and the result is scalar + b = reduce(a(1:0, 1), f, dim=1) + !ERROR: IDENTITY= must be present when DIM=1 and the array has zero extent on that dimension + c = reduce(a(1:0, :), f, dim=1) + !ERROR: IDENTITY= must be present when DIM=1 and the array has zero extent on that dimension + c = reduce(a(1:0, :), f, dim=1) + !ERROR: IDENTITY= must be present when DIM=2 and the array has zero extent on that dimension + c = reduce(a(:, 1:0), f, dim=2) + c(1:0) = reduce(a(1:0, 1:0), f, dim=1) ! ok, result is empty + c(1:0) = reduce(a(1:0, 1:0), f, dim=2) ! ok, result is empty + !ERROR: MASK= has no .TRUE. element, so IDENTITY= must be present + b = reduce(a, f, .false.) + !ERROR: MASK= has no .TRUE. element, so IDENTITY= must be present + b = reduce(a, f, reshape([(j > 100, j=1, 100)], shape(a))) + b = reduce(a, f, reshape([(j == 50, j=1, 100)], shape(a))) ! ok end subroutine subroutine not_errors type(pdt(10)) :: a(10), b -- GitLab From 0584e6c1669dbfc6252f5b069e2a895389660120 Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Thu, 30 Nov 2023 13:46:52 -0600 Subject: [PATCH 026/699] [libc] Explicitly pin memory for the HSA memory transfer (#73973) Summary: This portion of code handles mapping the RPC client memory over to the device. HSA copies need to be between two slices of memory that HSA has allocated. Previously we used coarse-grained memory to act as the host source. However, the support for this varies depending on the kernel and version and should not be relied upon. This patch changes that handling to use the `hsa_amd_memory_lock` API to explicitly pin memory to a location sufficient for a DMA transfer to the GPU. --- libc/utils/gpu/loader/amdgpu/Loader.cpp | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/libc/utils/gpu/loader/amdgpu/Loader.cpp b/libc/utils/gpu/loader/amdgpu/Loader.cpp index 4272cf40bfd1..5c28607b2f29 100644 --- a/libc/utils/gpu/loader/amdgpu/Loader.cpp +++ b/libc/utils/gpu/loader/amdgpu/Loader.cpp @@ -482,12 +482,11 @@ int load(int argc, char **argv, char **envp, void *image, size_t size, handle_error(err); void *rpc_client_buffer; - if (hsa_status_t err = hsa_amd_memory_pool_allocate( - coarsegrained_pool, rpc_get_client_size(), - /*flags=*/0, &rpc_client_buffer)) + if (hsa_status_t err = hsa_amd_memory_lock( + const_cast(rpc_get_client_buffer(device_id)), + rpc_get_client_size(), + /*agents=*/nullptr, 0, &rpc_client_buffer)) handle_error(err); - std::memcpy(rpc_client_buffer, rpc_get_client_buffer(device_id), - rpc_get_client_size()); // Copy the RPC client buffer to the address pointed to by the symbol. if (hsa_status_t err = @@ -495,7 +494,8 @@ int load(int argc, char **argv, char **envp, void *image, size_t size, rpc_client_buffer, host_agent, rpc_get_client_size())) handle_error(err); - if (hsa_status_t err = hsa_amd_memory_pool_free(rpc_client_buffer)) + if (hsa_status_t err = hsa_amd_memory_unlock( + const_cast(rpc_get_client_buffer(device_id)))) handle_error(err); if (hsa_status_t err = hsa_amd_memory_pool_free(rpc_client_host)) handle_error(err); -- GitLab From 284da049f5feb62b40f5abc41dda7895e3d81d72 Mon Sep 17 00:00:00 2001 From: Mircea Trofin Date: Thu, 30 Nov 2023 11:58:26 -0800 Subject: [PATCH 027/699] [coro][pgo] Don't promote pgo counters in the suspend basic block (#71263) If a suspend happens in the resume part (this can happen in the case of chained coroutines), and that's part of a loop, the pre-split CFG has the suspend block as an exit of that loop. PGO Counter Promotion will then try to commit the temporary counter to the global in that "exit" block (it also does that in the other loop exit BBs, which also includes the "destroy" case). This interferes with symmetric transfer. We don't need to commit the counter in the suspend case - it's not a loop exit from the perspective of the behavior of the program. The regular loop exit, together with the "destroy" case, completely cover any updates that may need to happen to the global counter. --- .../llvm/Transforms/Instrumentation/CFGMST.h | 15 +- .../llvm/Transforms/Utils/BasicBlockUtils.h | 19 ++ .../Instrumentation/InstrProfiling.cpp | 8 +- llvm/lib/Transforms/Utils/BasicBlockUtils.cpp | 12 ++ ...-split-musttail-chain-pgo-counter-promo.ll | 175 ++++++++++++++++++ .../Transforms/Utils/BasicBlockUtilsTest.cpp | 61 ++++++ 6 files changed, 277 insertions(+), 13 deletions(-) create mode 100644 llvm/test/Transforms/Coroutines/coro-split-musttail-chain-pgo-counter-promo.ll diff --git a/llvm/include/llvm/Transforms/Instrumentation/CFGMST.h b/llvm/include/llvm/Transforms/Instrumentation/CFGMST.h index cd2ae61334d0..682ae877f7ae 100644 --- a/llvm/include/llvm/Transforms/Instrumentation/CFGMST.h +++ b/llvm/include/llvm/Transforms/Instrumentation/CFGMST.h @@ -100,20 +100,11 @@ template class CFGMST { // i8 0, label %await.ready // i8 1, label %exit // ] - const BasicBlock *EdgeTarget = E->DestBB; - if (!EdgeTarget) + if (!E->DestBB) return; assert(E->SrcBB); - const Function *F = EdgeTarget->getParent(); - if (!F->isPresplitCoroutine()) - return; - - const Instruction *TI = E->SrcBB->getTerminator(); - if (auto *SWInst = dyn_cast(TI)) - if (auto *Intrinsic = dyn_cast(SWInst->getCondition())) - if (Intrinsic->getIntrinsicID() == Intrinsic::coro_suspend && - SWInst->getDefaultDest() == EdgeTarget) - E->Removed = true; + if (llvm::isPresplitCoroSuspendExitEdge(*E->SrcBB, *E->DestBB)) + E->Removed = true; } // Traverse the CFG using a stack. Find all the edges and assign the weight. diff --git a/llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h b/llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h index e6dde450b7df..e650ac80efbc 100644 --- a/llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h +++ b/llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h @@ -705,6 +705,25 @@ void InvertBranch(BranchInst *PBI, IRBuilderBase &Builder); // Check whether the function only has simple terminator: // br/brcond/unreachable/ret bool hasOnlySimpleTerminator(const Function &F); + +// Returns true if these basic blocks belong to a presplit coroutine and the +// edge corresponds to the 'default' case in the switch statement in the +// pattern: +// +// %0 = call i8 @llvm.coro.suspend(token none, i1 false) +// switch i8 %0, label %suspend [i8 0, label %resume +// i8 1, label %cleanup] +// +// i.e. the edge to the `%suspend` BB. This edge is special in that it will +// be elided by coroutine lowering (coro-split), and the `%suspend` BB needs +// to be kept as-is. It's not a real CFG edge - post-lowering, it will end +// up being a `ret`, and it must be thus lowerable to support symmetric +// transfer. For example: +// - this edge is not a loop exit edge if encountered in a loop (and should +// be ignored) +// - must not be split for PGO instrumentation, for example. +bool isPresplitCoroSuspendExitEdge(const BasicBlock &Src, + const BasicBlock &Dest); } // end namespace llvm #endif // LLVM_TRANSFORMS_UTILS_BASICBLOCKUTILS_H diff --git a/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp b/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp index 73a7116f74e1..10258e254679 100644 --- a/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp +++ b/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp @@ -14,6 +14,7 @@ #include "llvm/Transforms/Instrumentation/InstrProfiling.h" #include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringRef.h" #include "llvm/ADT/Twine.h" @@ -23,6 +24,7 @@ #include "llvm/Analysis/TargetLibraryInfo.h" #include "llvm/IR/Attributes.h" #include "llvm/IR/BasicBlock.h" +#include "llvm/IR/CFG.h" #include "llvm/IR/Constant.h" #include "llvm/IR/Constants.h" #include "llvm/IR/DIBuilder.h" @@ -48,6 +50,7 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/TargetParser/Triple.h" #include "llvm/Transforms/Instrumentation/PGOInstrumentation.h" +#include "llvm/Transforms/Utils/BasicBlockUtils.h" #include "llvm/Transforms/Utils/ModuleUtils.h" #include "llvm/Transforms/Utils/SSAUpdater.h" #include @@ -243,7 +246,10 @@ public: return; for (BasicBlock *ExitBlock : LoopExitBlocks) { - if (BlockSet.insert(ExitBlock).second) { + if (BlockSet.insert(ExitBlock).second && + llvm::none_of(predecessors(ExitBlock), [&](const BasicBlock *Pred) { + return llvm::isPresplitCoroSuspendExitEdge(*Pred, *ExitBlock); + })) { ExitBlocks.push_back(ExitBlock); InsertPts.push_back(&*ExitBlock->getFirstInsertionPt()); } diff --git a/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp b/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp index 168998fbee11..ccee97025e3c 100644 --- a/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp +++ b/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp @@ -2149,3 +2149,15 @@ bool llvm::hasOnlySimpleTerminator(const Function &F) { } return true; } + +bool llvm::isPresplitCoroSuspendExitEdge(const BasicBlock &Src, + const BasicBlock &Dest) { + assert(Src.getParent() == Dest.getParent()); + if (!Src.getParent()->isPresplitCoroutine()) + return false; + if (auto *SW = dyn_cast(Src.getTerminator())) + if (auto *Intr = dyn_cast(SW->getCondition())) + return Intr->getIntrinsicID() == Intrinsic::coro_suspend && + SW->getDefaultDest() == &Dest; + return false; +} diff --git a/llvm/test/Transforms/Coroutines/coro-split-musttail-chain-pgo-counter-promo.ll b/llvm/test/Transforms/Coroutines/coro-split-musttail-chain-pgo-counter-promo.ll new file mode 100644 index 000000000000..ddd293eed240 --- /dev/null +++ b/llvm/test/Transforms/Coroutines/coro-split-musttail-chain-pgo-counter-promo.ll @@ -0,0 +1,175 @@ +; REQUIRES: x86-registered-target +; RUN: opt -passes='pgo-instr-gen,instrprof,coro-split' -do-counter-promotion=true -S < %s | FileCheck %s + +; CHECK-LABEL: define internal fastcc void @f.resume +; CHECK: musttail call fastcc void +; CHECK-NEXT: ret void +; CHECK: musttail call fastcc void +; CHECK-NEXT: ret void +; CHECK-LABEL: define internal fastcc void @f.destroy +target triple = "x86_64-grtev4-linux-gnu" + +%CoroutinePromise = type { ptr, i64, [8 x i8], ptr} +%Awaitable.1 = type { ptr } +%Awaitable.2 = type { ptr, ptr } + +declare void @await_suspend(ptr noundef nonnull align 1 dereferenceable(1), ptr) local_unnamed_addr +declare ptr @await_transform_await_suspend(ptr noundef nonnull align 8 dereferenceable(16), ptr) local_unnamed_addr +declare void @destroy_frame_slowpath(ptr noundef nonnull align 16 dereferenceable(32)) local_unnamed_addr +declare ptr @other_coro(); +declare void @heap_delete(ptr noundef, i64 noundef, i64 noundef) local_unnamed_addr +declare noundef nonnull ptr @heap_allocate(i64 noundef, i64 noundef) local_unnamed_addr + +declare void @llvm.assume(i1 noundef) +declare i64 @llvm.coro.align.i64() +declare i1 @llvm.coro.alloc(token) +declare ptr @llvm.coro.begin(token, ptr writeonly) +declare i1 @llvm.coro.end(ptr, i1, token) +declare ptr @llvm.coro.free(token, ptr nocapture readonly) +declare token @llvm.coro.id(i32, ptr readnone, ptr nocapture readonly, ptr) +declare token @llvm.coro.save(ptr) +declare i64 @llvm.coro.size.i64() +declare ptr @llvm.coro.subfn.addr(ptr nocapture readonly, i8) +declare i8 @llvm.coro.suspend(token, i1) +declare void @llvm.instrprof.increment(ptr, i64, i32, i32) +declare void @llvm.instrprof.value.profile(ptr, i64, i64, i32, i32) +declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) +declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) + +; Function Attrs: noinline nounwind presplitcoroutine uwtable +define ptr @f(i32 %0) presplitcoroutine align 32 { + %2 = alloca i32, align 8 + %3 = alloca %CoroutinePromise, align 16 + %4 = alloca %Awaitable.1, align 8 + %5 = alloca %Awaitable.2, align 8 + %6 = call token @llvm.coro.id(i32 8, ptr nonnull %3, ptr nonnull @f, ptr null) + %7 = call i1 @llvm.coro.alloc(token %6) + br i1 %7, label %8, label %12 + +8: ; preds = %1 + %9 = call i64 @llvm.coro.size.i64() + %10 = call i64 @llvm.coro.align.i64() + %11 = call noalias noundef nonnull ptr @heap_allocate(i64 noundef %9, i64 noundef %10) #27 + call void @llvm.assume(i1 true) [ "align"(ptr %11, i64 %10) ] + br label %12 + +12: ; preds = %8, %1 + %13 = phi ptr [ null, %1 ], [ %11, %8 ] + %14 = call ptr @llvm.coro.begin(token %6, ptr %13) #28 + call void @llvm.lifetime.start.p0(i64 32, ptr nonnull %3) #9 + store ptr null, ptr %3, align 16 + %15 = getelementptr inbounds {ptr, i64}, ptr %3, i64 0, i32 1 + store i64 0, ptr %15, align 8 + call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %4) #9 + store ptr %3, ptr %4, align 8 + %16 = call token @llvm.coro.save(ptr null) + call void @await_suspend(ptr noundef nonnull align 1 dereferenceable(1) %4, ptr %14) #9 + %17 = call i8 @llvm.coro.suspend(token %16, i1 false) + switch i8 %17, label %61 [ + i8 0, label %18 + i8 1, label %21 + ] + +18: ; preds = %12 + call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %4) #9 + %19 = icmp slt i32 0, %0 + br i1 %19, label %20, label %36 + +20: ; preds = %18 + br label %22 + +21: ; preds = %12 + call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %4) #9 + br label %54 + +22: ; preds = %20, %31 + %23 = phi i32 [ 0, %20 ], [ %32, %31 ] + call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %5) #9 + %24 = call ptr @other_coro() + store ptr %3, ptr %5, align 8 + %25 = getelementptr inbounds { ptr, ptr }, ptr %5, i64 0, i32 1 + store ptr %24, ptr %25, align 8 + %26 = call token @llvm.coro.save(ptr null) + %27 = call ptr @await_transform_await_suspend(ptr noundef nonnull align 8 dereferenceable(16) %5, ptr %14) + %28 = call ptr @llvm.coro.subfn.addr(ptr %27, i8 0) + %29 = ptrtoint ptr %28 to i64 + call fastcc void %28(ptr %27) #9 + %30 = call i8 @llvm.coro.suspend(token %26, i1 false) + switch i8 %30, label %60 [ + i8 0, label %31 + i8 1, label %34 + ] + +31: ; preds = %22 + call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %5) #9 + %32 = add nuw nsw i32 %23, 1 + %33 = icmp slt i32 %32, %0 + br i1 %33, label %22, label %35, !llvm.loop !0 + +34: ; preds = %22 + call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %5) #9 + br label %54 + +35: ; preds = %31 + br label %36 + +36: ; preds = %35, %18 + %37 = call token @llvm.coro.save(ptr null) + %38 = getelementptr inbounds i8, ptr %14, i64 16 + %39 = getelementptr inbounds i8, ptr %14, i64 32 + %40 = load i64, ptr %39, align 8 + %41 = load ptr, ptr %38, align 16 + %42 = icmp eq ptr %41, null + br i1 %42, label %43, label %46 + +43: ; preds = %36 + %44 = call ptr @llvm.coro.subfn.addr(ptr nonnull %14, i8 1) + %45 = ptrtoint ptr %44 to i64 + call fastcc void %44(ptr nonnull %14) #9 + br label %47 + +46: ; preds = %36 + call void @destroy_frame_slowpath(ptr noundef nonnull align 16 dereferenceable(32) %38) #9 + br label %47 + +47: ; preds = %43, %46 + %48 = inttoptr i64 %40 to ptr + %49 = call ptr @llvm.coro.subfn.addr(ptr %48, i8 0) + %50 = ptrtoint ptr %49 to i64 + call fastcc void %49(ptr %48) #9 + %51 = call i8 @llvm.coro.suspend(token %37, i1 true) #28 + switch i8 %51, label %61 [ + i8 0, label %53 + i8 1, label %52 + ] + +52: ; preds = %47 + br label %54 + +53: ; preds = %47 + call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %2) #9 + unreachable + +54: ; preds = %52, %34, %21 + call void @llvm.lifetime.end.p0(i64 32, ptr nonnull %3) #9 + %55 = call ptr @llvm.coro.free(token %6, ptr %14) + %56 = icmp eq ptr %55, null + br i1 %56, label %61, label %57 + +57: ; preds = %54 + %58 = call i64 @llvm.coro.size.i64() + %59 = call i64 @llvm.coro.align.i64() + call void @heap_delete(ptr noundef nonnull %55, i64 noundef %58, i64 noundef %59) #9 + br label %61 + +60: ; preds = %22 + br label %61 + +61: ; preds = %60, %57, %54, %47, %12 + %62 = getelementptr inbounds i8, ptr %3, i64 -16 + %63 = call i1 @llvm.coro.end(ptr null, i1 false, token none) #28 + ret ptr %62 +} + +!0 = distinct !{!0, !1} +!1 = !{!"llvm.loop.mustprogress"} diff --git a/llvm/unittests/Transforms/Utils/BasicBlockUtilsTest.cpp b/llvm/unittests/Transforms/Utils/BasicBlockUtilsTest.cpp index 2da38c60044b..5152cbe19c21 100644 --- a/llvm/unittests/Transforms/Utils/BasicBlockUtilsTest.cpp +++ b/llvm/unittests/Transforms/Utils/BasicBlockUtilsTest.cpp @@ -611,3 +611,64 @@ L19: EXPECT_EQ(BranchProbability::getRaw(1), BPI.getEdgeProbability(EntryBB, UnreachableBB)); } + +TEST(BasicBlockUtils, IsPresplitCoroSuspendExitTest) { + LLVMContext C; + std::unique_ptr M = parseIR(C, R"IR( +define void @positive_case(i32 %0) #0 { +entry: + %save = call token @llvm.coro.save(ptr null) + %suspend = call i8 @llvm.coro.suspend(token %save, i1 false) + switch i8 %suspend, label %exit [ + i8 0, label %resume + i8 1, label %destroy + ] +resume: + ret void +destroy: + ret void +exit: + call i1 @llvm.coro.end(ptr null, i1 false, token none) + ret void +} + +define void @notpresplit(i32 %0) { +entry: + %save = call token @llvm.coro.save(ptr null) + %suspend = call i8 @llvm.coro.suspend(token %save, i1 false) + switch i8 %suspend, label %exit [ + i8 0, label %resume + i8 1, label %destroy + ] +resume: + ret void +destroy: + ret void +exit: + call i1 @llvm.coro.end(ptr null, i1 false, token none) + ret void +} + +declare token @llvm.coro.save(ptr) +declare i8 @llvm.coro.suspend(token, i1) +declare i1 @llvm.coro.end(ptr, i1, token) + +attributes #0 = { presplitcoroutine } +)IR"); + + auto FindExit = [](const Function &F) -> const BasicBlock * { + for (const auto &BB : F) + if (BB.getName() == "exit") + return &BB; + return nullptr; + }; + Function *P = M->getFunction("positive_case"); + const auto &ExitP = *FindExit(*P); + EXPECT_TRUE(llvm::isPresplitCoroSuspendExitEdge(*ExitP.getSinglePredecessor(), + ExitP)); + + Function *N = M->getFunction("notpresplit"); + const auto &ExitN = *FindExit(*N); + EXPECT_FALSE(llvm::isPresplitCoroSuspendExitEdge( + *ExitN.getSinglePredecessor(), ExitN)); +} -- GitLab From fcf5154a27ba27de91d9b4527a75daeb92563ff4 Mon Sep 17 00:00:00 2001 From: Peter Klausler <35819229+klausler@users.noreply.github.com> Date: Thu, 30 Nov 2023 11:59:19 -0800 Subject: [PATCH 028/699] [flang] Fix IsVariable() to be false for procedure pointers (#72577) The implementation of the predicate evaluate::IsVariable() needs to recognize procedure pointers and return a false result for them. --- flang/include/flang/Evaluate/tools.h | 7 +++++++ flang/test/Semantics/associated.f90 | 3 +++ 2 files changed, 10 insertions(+) diff --git a/flang/include/flang/Evaluate/tools.h b/flang/include/flang/Evaluate/tools.h index 55262a912d95..ba065c4ee1b1 100644 --- a/flang/include/flang/Evaluate/tools.h +++ b/flang/include/flang/Evaluate/tools.h @@ -59,6 +59,13 @@ struct IsVariableHelper } } return false; + } else if constexpr (std::is_same_v) { + if (std::holds_alternative(x.u) || + std::holds_alternative(x.u)) { + return false; // procedure pointer + } else { + return (*this)(x.u); + } } else { return (*this)(x.u); } diff --git a/flang/test/Semantics/associated.f90 b/flang/test/Semantics/associated.f90 index bf8bcf474986..1da94d28ae6b 100644 --- a/flang/test/Semantics/associated.f90 +++ b/flang/test/Semantics/associated.f90 @@ -92,6 +92,7 @@ subroutine assoc() integer, target :: targetIntArr(2) integer, target :: targetIntCoarray[*] integer, pointer :: intPointerArr(:) + procedure(objPtrFunc), pointer :: objPtrFuncPointer !ERROR: Assumed-rank array cannot be forwarded to 'target=' argument lvar = associated(assumedRank, assumedRank) @@ -204,6 +205,8 @@ subroutine assoc() lvar = associated(intProcPointer1, elementalProc) !ERROR: POINTER= argument 'intpointervar1' is an object pointer but the TARGET= argument 'intfunc' is not a variable lvar = associated (intPointerVar1, intFunc) + !ERROR: POINTER= argument 'intpointervar1' is an object pointer but the TARGET= argument 'objptrfuncpointer' is not a variable + lvar = associated (intPointerVar1, objPtrFuncPointer) !ERROR: In assignment to object pointer 'intpointervar1', the target 'intfunc' is a procedure designator intPointerVar1 => intFunc !ERROR: In assignment to procedure pointer 'intprocpointer1', the target is not a procedure or procedure pointer -- GitLab From c12de1487670ab009e738b905ad8296a8cb2c685 Mon Sep 17 00:00:00 2001 From: Douglas Yung Date: Thu, 30 Nov 2023 11:58:32 -0800 Subject: [PATCH 029/699] Revert "[X86] Canonicalize fp zero vectors from bitcasted integer zero vectors" This reverts commit 169db80e41936811c6744f2c513a1ed00d97f10e. This change is causing many test failures on Windows bots: - https://lab.llvm.org/buildbot/#/builders/235/builds/3616 - https://lab.llvm.org/buildbot/#/builders/233/builds/4883 - https://lab.llvm.org/buildbot/#/builders/216/builds/31174 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 6 - .../CodeGen/X86/2011-10-19-widen_vselect.ll | 6 +- llvm/test/CodeGen/X86/2012-07-10-extload64.ll | 4 +- llvm/test/CodeGen/X86/fold-load-vec.ll | 2 +- llvm/test/CodeGen/X86/fold-pcmpeqd-2.ll | 18 +- llvm/test/CodeGen/X86/half.ll | 14 +- llvm/test/CodeGen/X86/nontemporal-3.ll | 646 +++++++++++++++--- llvm/test/CodeGen/X86/pr13577.ll | 3 +- llvm/test/CodeGen/X86/pr41619.ll | 3 +- llvm/test/CodeGen/X86/vec_zero_cse.ll | 4 +- .../vector-shuffle-combining-avx512bwvl.ll | 9 +- 11 files changed, 579 insertions(+), 136 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index b73779edc5f7..6167be7bdf84 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -42930,12 +42930,6 @@ static SDValue combineBitcast(SDNode *N, SelectionDAG &DAG, } } - // Canonicalize fp zero vectors - these sometimes don't fold due to one use - // limits. - if (VT.isVector() && TLI.isTypeLegal(VT) && ISD::isBuildVectorAllZeros(N) && - (VT.getScalarType() == MVT::f32 || VT.getScalarType() == MVT::f64)) - return getZeroVector(VT.getSimpleVT(), Subtarget, DAG, SDLoc(N0)); - // Try to remove a bitcast of constant vXi1 vector. We have to legalize // most of these to scalar anyway. if (Subtarget.hasAVX512() && VT.isScalarInteger() && diff --git a/llvm/test/CodeGen/X86/2011-10-19-widen_vselect.ll b/llvm/test/CodeGen/X86/2011-10-19-widen_vselect.ll index d3f410d37567..e7f62b9dfc22 100644 --- a/llvm/test/CodeGen/X86/2011-10-19-widen_vselect.ll +++ b/llvm/test/CodeGen/X86/2011-10-19-widen_vselect.ll @@ -49,12 +49,14 @@ entry: define void @zero_test() { ; X86-LABEL: zero_test: ; X86: # %bb.0: # %entry -; X86-NEXT: movl $0, (%eax) +; X86-NEXT: xorps %xmm0, %xmm0 +; X86-NEXT: movlps %xmm0, (%eax) ; X86-NEXT: retl ; ; X64-LABEL: zero_test: ; X64: # %bb.0: # %entry -; X64-NEXT: movq $0, (%rax) +; X64-NEXT: xorps %xmm0, %xmm0 +; X64-NEXT: movlps %xmm0, (%rax) ; X64-NEXT: retq entry: %0 = select <2 x i1> undef, <2 x float> undef, <2 x float> zeroinitializer diff --git a/llvm/test/CodeGen/X86/2012-07-10-extload64.ll b/llvm/test/CodeGen/X86/2012-07-10-extload64.ll index f4ec8bde3700..b6ec3b34eb10 100644 --- a/llvm/test/CodeGen/X86/2012-07-10-extload64.ll +++ b/llvm/test/CodeGen/X86/2012-07-10-extload64.ll @@ -29,8 +29,8 @@ define void @store_64(ptr %ptr) { ; X86-LABEL: store_64: ; X86: # %bb.0: # %BB ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax -; X86-NEXT: movl $0, 4(%eax) -; X86-NEXT: movl $0, (%eax) +; X86-NEXT: xorps %xmm0, %xmm0 +; X86-NEXT: movlps %xmm0, (%eax) ; X86-NEXT: retl ; ; X64-LABEL: store_64: diff --git a/llvm/test/CodeGen/X86/fold-load-vec.ll b/llvm/test/CodeGen/X86/fold-load-vec.ll index 0bf846a0930b..348929cdf9f7 100644 --- a/llvm/test/CodeGen/X86/fold-load-vec.ll +++ b/llvm/test/CodeGen/X86/fold-load-vec.ll @@ -10,8 +10,8 @@ define void @sample_test(ptr %source, ptr %dest) nounwind { ; CHECK-NEXT: subq $24, %rsp ; CHECK-NEXT: movq %rdi, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movq %rsi, {{[0-9]+}}(%rsp) -; CHECK-NEXT: movq $0, (%rsp) ; CHECK-NEXT: xorps %xmm0, %xmm0 +; CHECK-NEXT: movlps %xmm0, (%rsp) ; CHECK-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] ; CHECK-NEXT: movlps %xmm0, (%rsp) ; CHECK-NEXT: movlps %xmm0, (%rsi) diff --git a/llvm/test/CodeGen/X86/fold-pcmpeqd-2.ll b/llvm/test/CodeGen/X86/fold-pcmpeqd-2.ll index 713ecf5414ba..88425ea87845 100644 --- a/llvm/test/CodeGen/X86/fold-pcmpeqd-2.ll +++ b/llvm/test/CodeGen/X86/fold-pcmpeqd-2.ll @@ -51,6 +51,11 @@ define void @program_1(ptr %dest, ptr %t0, <4 x float> %p0, <4 x float> %p1, <4 ; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload ; X32-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 ; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill +; X32-NEXT: xorps %xmm0, %xmm0 +; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill +; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload +; X32-NEXT: mulps %xmm0, %xmm0 +; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill ; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload ; X32-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 ; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill @@ -59,10 +64,8 @@ define void @program_1(ptr %dest, ptr %t0, <4 x float> %p0, <4 x float> %p1, <4 ; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload ; X32-NEXT: cmpunordps %xmm0, %xmm0 ; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill -; X32-NEXT: xorps %xmm0, %xmm0 -; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill ; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload -; X32-NEXT: minps %xmm0, %xmm0 +; X32-NEXT: minps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 ; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill ; X32-NEXT: xorps %xmm0, %xmm0 ; X32-NEXT: movaps %xmm0, {{[0-9]+}}(%esp) @@ -132,6 +135,11 @@ define void @program_1(ptr %dest, ptr %t0, <4 x float> %p0, <4 x float> %p1, <4 ; X64-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload ; X64-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; X64-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill +; X64-NEXT: xorps %xmm0, %xmm0 +; X64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill +; X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload +; X64-NEXT: mulps %xmm0, %xmm0 +; X64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; X64-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload ; X64-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; X64-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill @@ -140,10 +148,8 @@ define void @program_1(ptr %dest, ptr %t0, <4 x float> %p0, <4 x float> %p1, <4 ; X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; X64-NEXT: cmpunordps %xmm0, %xmm0 ; X64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill -; X64-NEXT: xorps %xmm0, %xmm0 -; X64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload -; X64-NEXT: minps %xmm0, %xmm0 +; X64-NEXT: minps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; X64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; X64-NEXT: xorl %ebx, %ebx ; X64-NEXT: xorps %xmm3, %xmm3 diff --git a/llvm/test/CodeGen/X86/half.ll b/llvm/test/CodeGen/X86/half.ll index 722525720316..596e465ee8ca 100644 --- a/llvm/test/CodeGen/X86/half.ll +++ b/llvm/test/CodeGen/X86/half.ll @@ -1082,11 +1082,12 @@ define void @main.158() #0 { ; BWON-F16C-LABEL: main.158: ; BWON-F16C: # %bb.0: # %entry ; BWON-F16C-NEXT: vxorps %xmm0, %xmm0, %xmm0 -; BWON-F16C-NEXT: vcvtps2ph $4, %xmm0, %xmm1 -; BWON-F16C-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero -; BWON-F16C-NEXT: vcvtph2ps %xmm1, %xmm1 -; BWON-F16C-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero -; BWON-F16C-NEXT: vucomiss %xmm1, %xmm2 +; BWON-F16C-NEXT: vcvtps2ph $4, %xmm0, %xmm0 +; BWON-F16C-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero +; BWON-F16C-NEXT: vcvtph2ps %xmm0, %xmm0 +; BWON-F16C-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero +; BWON-F16C-NEXT: vucomiss %xmm0, %xmm1 +; BWON-F16C-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; BWON-F16C-NEXT: jae .LBB20_2 ; BWON-F16C-NEXT: # %bb.1: # %entry ; BWON-F16C-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero @@ -1099,7 +1100,8 @@ define void @main.158() #0 { ; CHECK-I686-LABEL: main.158: ; CHECK-I686: # %bb.0: # %entry ; CHECK-I686-NEXT: subl $12, %esp -; CHECK-I686-NEXT: movl $0, (%esp) +; CHECK-I686-NEXT: pxor %xmm0, %xmm0 +; CHECK-I686-NEXT: movd %xmm0, (%esp) ; CHECK-I686-NEXT: calll __truncsfhf2 ; CHECK-I686-NEXT: pextrw $0, %xmm0, %eax ; CHECK-I686-NEXT: movw %ax, (%esp) diff --git a/llvm/test/CodeGen/X86/nontemporal-3.ll b/llvm/test/CodeGen/X86/nontemporal-3.ll index f9872b10097a..a2d2c5ca4301 100644 --- a/llvm/test/CodeGen/X86/nontemporal-3.ll +++ b/llvm/test/CodeGen/X86/nontemporal-3.ll @@ -93,66 +93,247 @@ define void @test_zero_v4f64_align1(ptr %dst) nounwind { } define void @test_zero_v8f32_align1(ptr %dst) nounwind { -; CHECK-LABEL: test_zero_v8f32_align1: -; CHECK: # %bb.0: -; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: movntiq %rax, 8(%rdi) -; CHECK-NEXT: movntiq %rax, (%rdi) -; CHECK-NEXT: movntiq %rax, 24(%rdi) -; CHECK-NEXT: movntiq %rax, 16(%rdi) -; CHECK-NEXT: retq +; SSE2-LABEL: test_zero_v8f32_align1: +; SSE2: # %bb.0: +; SSE2-NEXT: xorl %eax, %eax +; SSE2-NEXT: movntiq %rax, 8(%rdi) +; SSE2-NEXT: movntiq %rax, (%rdi) +; SSE2-NEXT: movntiq %rax, 24(%rdi) +; SSE2-NEXT: movntiq %rax, 16(%rdi) +; SSE2-NEXT: retq +; +; SSE4A-LABEL: test_zero_v8f32_align1: +; SSE4A: # %bb.0: +; SSE4A-NEXT: xorl %eax, %eax +; SSE4A-NEXT: movntiq %rax, 8(%rdi) +; SSE4A-NEXT: movntiq %rax, 24(%rdi) +; SSE4A-NEXT: xorps %xmm0, %xmm0 +; SSE4A-NEXT: movntsd %xmm0, (%rdi) +; SSE4A-NEXT: movntsd %xmm0, 16(%rdi) +; SSE4A-NEXT: retq +; +; SSE41-LABEL: test_zero_v8f32_align1: +; SSE41: # %bb.0: +; SSE41-NEXT: xorl %eax, %eax +; SSE41-NEXT: movntiq %rax, 8(%rdi) +; SSE41-NEXT: movntiq %rax, (%rdi) +; SSE41-NEXT: movntiq %rax, 24(%rdi) +; SSE41-NEXT: movntiq %rax, 16(%rdi) +; SSE41-NEXT: retq +; +; AVX-LABEL: test_zero_v8f32_align1: +; AVX: # %bb.0: +; AVX-NEXT: xorl %eax, %eax +; AVX-NEXT: movntiq %rax, 8(%rdi) +; AVX-NEXT: movntiq %rax, (%rdi) +; AVX-NEXT: movntiq %rax, 24(%rdi) +; AVX-NEXT: movntiq %rax, 16(%rdi) +; AVX-NEXT: retq +; +; AVX512-LABEL: test_zero_v8f32_align1: +; AVX512: # %bb.0: +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: movntiq %rax, 8(%rdi) +; AVX512-NEXT: movntiq %rax, (%rdi) +; AVX512-NEXT: movntiq %rax, 24(%rdi) +; AVX512-NEXT: movntiq %rax, 16(%rdi) +; AVX512-NEXT: retq store <8 x float> zeroinitializer, ptr %dst, align 1, !nontemporal !1 ret void } define void @test_zero_v4i64_align1(ptr %dst) nounwind { -; CHECK-LABEL: test_zero_v4i64_align1: -; CHECK: # %bb.0: -; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: movntiq %rax, 8(%rdi) -; CHECK-NEXT: movntiq %rax, (%rdi) -; CHECK-NEXT: movntiq %rax, 24(%rdi) -; CHECK-NEXT: movntiq %rax, 16(%rdi) -; CHECK-NEXT: retq +; SSE2-LABEL: test_zero_v4i64_align1: +; SSE2: # %bb.0: +; SSE2-NEXT: xorl %eax, %eax +; SSE2-NEXT: movntiq %rax, 8(%rdi) +; SSE2-NEXT: movntiq %rax, (%rdi) +; SSE2-NEXT: movntiq %rax, 24(%rdi) +; SSE2-NEXT: movntiq %rax, 16(%rdi) +; SSE2-NEXT: retq +; +; SSE4A-LABEL: test_zero_v4i64_align1: +; SSE4A: # %bb.0: +; SSE4A-NEXT: xorps %xmm0, %xmm0 +; SSE4A-NEXT: movntsd %xmm0, 8(%rdi) +; SSE4A-NEXT: movntsd %xmm0, (%rdi) +; SSE4A-NEXT: movntsd %xmm0, 24(%rdi) +; SSE4A-NEXT: movntsd %xmm0, 16(%rdi) +; SSE4A-NEXT: retq +; +; SSE41-LABEL: test_zero_v4i64_align1: +; SSE41: # %bb.0: +; SSE41-NEXT: xorl %eax, %eax +; SSE41-NEXT: movntiq %rax, 8(%rdi) +; SSE41-NEXT: movntiq %rax, (%rdi) +; SSE41-NEXT: movntiq %rax, 24(%rdi) +; SSE41-NEXT: movntiq %rax, 16(%rdi) +; SSE41-NEXT: retq +; +; AVX-LABEL: test_zero_v4i64_align1: +; AVX: # %bb.0: +; AVX-NEXT: xorl %eax, %eax +; AVX-NEXT: movntiq %rax, 8(%rdi) +; AVX-NEXT: movntiq %rax, (%rdi) +; AVX-NEXT: movntiq %rax, 24(%rdi) +; AVX-NEXT: movntiq %rax, 16(%rdi) +; AVX-NEXT: retq +; +; AVX512-LABEL: test_zero_v4i64_align1: +; AVX512: # %bb.0: +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: movntiq %rax, 8(%rdi) +; AVX512-NEXT: movntiq %rax, (%rdi) +; AVX512-NEXT: movntiq %rax, 24(%rdi) +; AVX512-NEXT: movntiq %rax, 16(%rdi) +; AVX512-NEXT: retq store <4 x i64> zeroinitializer, ptr %dst, align 1, !nontemporal !1 ret void } define void @test_zero_v8i32_align1(ptr %dst) nounwind { -; CHECK-LABEL: test_zero_v8i32_align1: -; CHECK: # %bb.0: -; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: movntiq %rax, 8(%rdi) -; CHECK-NEXT: movntiq %rax, (%rdi) -; CHECK-NEXT: movntiq %rax, 24(%rdi) -; CHECK-NEXT: movntiq %rax, 16(%rdi) -; CHECK-NEXT: retq +; SSE2-LABEL: test_zero_v8i32_align1: +; SSE2: # %bb.0: +; SSE2-NEXT: xorl %eax, %eax +; SSE2-NEXT: movntiq %rax, 8(%rdi) +; SSE2-NEXT: movntiq %rax, (%rdi) +; SSE2-NEXT: movntiq %rax, 24(%rdi) +; SSE2-NEXT: movntiq %rax, 16(%rdi) +; SSE2-NEXT: retq +; +; SSE4A-LABEL: test_zero_v8i32_align1: +; SSE4A: # %bb.0: +; SSE4A-NEXT: xorps %xmm0, %xmm0 +; SSE4A-NEXT: movntsd %xmm0, 8(%rdi) +; SSE4A-NEXT: movntsd %xmm0, (%rdi) +; SSE4A-NEXT: movntsd %xmm0, 24(%rdi) +; SSE4A-NEXT: movntsd %xmm0, 16(%rdi) +; SSE4A-NEXT: retq +; +; SSE41-LABEL: test_zero_v8i32_align1: +; SSE41: # %bb.0: +; SSE41-NEXT: xorl %eax, %eax +; SSE41-NEXT: movntiq %rax, 8(%rdi) +; SSE41-NEXT: movntiq %rax, (%rdi) +; SSE41-NEXT: movntiq %rax, 24(%rdi) +; SSE41-NEXT: movntiq %rax, 16(%rdi) +; SSE41-NEXT: retq +; +; AVX-LABEL: test_zero_v8i32_align1: +; AVX: # %bb.0: +; AVX-NEXT: xorl %eax, %eax +; AVX-NEXT: movntiq %rax, 8(%rdi) +; AVX-NEXT: movntiq %rax, (%rdi) +; AVX-NEXT: movntiq %rax, 24(%rdi) +; AVX-NEXT: movntiq %rax, 16(%rdi) +; AVX-NEXT: retq +; +; AVX512-LABEL: test_zero_v8i32_align1: +; AVX512: # %bb.0: +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: movntiq %rax, 8(%rdi) +; AVX512-NEXT: movntiq %rax, (%rdi) +; AVX512-NEXT: movntiq %rax, 24(%rdi) +; AVX512-NEXT: movntiq %rax, 16(%rdi) +; AVX512-NEXT: retq store <8 x i32> zeroinitializer, ptr %dst, align 1, !nontemporal !1 ret void } define void @test_zero_v16i16_align1(ptr %dst) nounwind { -; CHECK-LABEL: test_zero_v16i16_align1: -; CHECK: # %bb.0: -; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: movntiq %rax, 8(%rdi) -; CHECK-NEXT: movntiq %rax, (%rdi) -; CHECK-NEXT: movntiq %rax, 24(%rdi) -; CHECK-NEXT: movntiq %rax, 16(%rdi) -; CHECK-NEXT: retq +; SSE2-LABEL: test_zero_v16i16_align1: +; SSE2: # %bb.0: +; SSE2-NEXT: xorl %eax, %eax +; SSE2-NEXT: movntiq %rax, 8(%rdi) +; SSE2-NEXT: movntiq %rax, (%rdi) +; SSE2-NEXT: movntiq %rax, 24(%rdi) +; SSE2-NEXT: movntiq %rax, 16(%rdi) +; SSE2-NEXT: retq +; +; SSE4A-LABEL: test_zero_v16i16_align1: +; SSE4A: # %bb.0: +; SSE4A-NEXT: xorps %xmm0, %xmm0 +; SSE4A-NEXT: movntsd %xmm0, 8(%rdi) +; SSE4A-NEXT: movntsd %xmm0, (%rdi) +; SSE4A-NEXT: movntsd %xmm0, 24(%rdi) +; SSE4A-NEXT: movntsd %xmm0, 16(%rdi) +; SSE4A-NEXT: retq +; +; SSE41-LABEL: test_zero_v16i16_align1: +; SSE41: # %bb.0: +; SSE41-NEXT: xorl %eax, %eax +; SSE41-NEXT: movntiq %rax, 8(%rdi) +; SSE41-NEXT: movntiq %rax, (%rdi) +; SSE41-NEXT: movntiq %rax, 24(%rdi) +; SSE41-NEXT: movntiq %rax, 16(%rdi) +; SSE41-NEXT: retq +; +; AVX-LABEL: test_zero_v16i16_align1: +; AVX: # %bb.0: +; AVX-NEXT: xorl %eax, %eax +; AVX-NEXT: movntiq %rax, 8(%rdi) +; AVX-NEXT: movntiq %rax, (%rdi) +; AVX-NEXT: movntiq %rax, 24(%rdi) +; AVX-NEXT: movntiq %rax, 16(%rdi) +; AVX-NEXT: retq +; +; AVX512-LABEL: test_zero_v16i16_align1: +; AVX512: # %bb.0: +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: movntiq %rax, 8(%rdi) +; AVX512-NEXT: movntiq %rax, (%rdi) +; AVX512-NEXT: movntiq %rax, 24(%rdi) +; AVX512-NEXT: movntiq %rax, 16(%rdi) +; AVX512-NEXT: retq store <16 x i16> zeroinitializer, ptr %dst, align 1, !nontemporal !1 ret void } define void @test_zero_v32i8_align1(ptr %dst) nounwind { -; CHECK-LABEL: test_zero_v32i8_align1: -; CHECK: # %bb.0: -; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: movntiq %rax, 8(%rdi) -; CHECK-NEXT: movntiq %rax, (%rdi) -; CHECK-NEXT: movntiq %rax, 24(%rdi) -; CHECK-NEXT: movntiq %rax, 16(%rdi) -; CHECK-NEXT: retq +; SSE2-LABEL: test_zero_v32i8_align1: +; SSE2: # %bb.0: +; SSE2-NEXT: xorl %eax, %eax +; SSE2-NEXT: movntiq %rax, 8(%rdi) +; SSE2-NEXT: movntiq %rax, (%rdi) +; SSE2-NEXT: movntiq %rax, 24(%rdi) +; SSE2-NEXT: movntiq %rax, 16(%rdi) +; SSE2-NEXT: retq +; +; SSE4A-LABEL: test_zero_v32i8_align1: +; SSE4A: # %bb.0: +; SSE4A-NEXT: xorps %xmm0, %xmm0 +; SSE4A-NEXT: movntsd %xmm0, 8(%rdi) +; SSE4A-NEXT: movntsd %xmm0, (%rdi) +; SSE4A-NEXT: movntsd %xmm0, 24(%rdi) +; SSE4A-NEXT: movntsd %xmm0, 16(%rdi) +; SSE4A-NEXT: retq +; +; SSE41-LABEL: test_zero_v32i8_align1: +; SSE41: # %bb.0: +; SSE41-NEXT: xorl %eax, %eax +; SSE41-NEXT: movntiq %rax, 8(%rdi) +; SSE41-NEXT: movntiq %rax, (%rdi) +; SSE41-NEXT: movntiq %rax, 24(%rdi) +; SSE41-NEXT: movntiq %rax, 16(%rdi) +; SSE41-NEXT: retq +; +; AVX-LABEL: test_zero_v32i8_align1: +; AVX: # %bb.0: +; AVX-NEXT: xorl %eax, %eax +; AVX-NEXT: movntiq %rax, 8(%rdi) +; AVX-NEXT: movntiq %rax, (%rdi) +; AVX-NEXT: movntiq %rax, 24(%rdi) +; AVX-NEXT: movntiq %rax, 16(%rdi) +; AVX-NEXT: retq +; +; AVX512-LABEL: test_zero_v32i8_align1: +; AVX512: # %bb.0: +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: movntiq %rax, 8(%rdi) +; AVX512-NEXT: movntiq %rax, (%rdi) +; AVX512-NEXT: movntiq %rax, 24(%rdi) +; AVX512-NEXT: movntiq %rax, 16(%rdi) +; AVX512-NEXT: retq store <32 x i8> zeroinitializer, ptr %dst, align 1, !nontemporal !1 ret void } @@ -327,86 +508,347 @@ define void @test_zero_v8f64_align1(ptr %dst) nounwind { } define void @test_zero_v16f32_align1(ptr %dst) nounwind { -; CHECK-LABEL: test_zero_v16f32_align1: -; CHECK: # %bb.0: -; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: movntiq %rax, 8(%rdi) -; CHECK-NEXT: movntiq %rax, (%rdi) -; CHECK-NEXT: movntiq %rax, 24(%rdi) -; CHECK-NEXT: movntiq %rax, 16(%rdi) -; CHECK-NEXT: movntiq %rax, 40(%rdi) -; CHECK-NEXT: movntiq %rax, 32(%rdi) -; CHECK-NEXT: movntiq %rax, 56(%rdi) -; CHECK-NEXT: movntiq %rax, 48(%rdi) -; CHECK-NEXT: retq +; SSE2-LABEL: test_zero_v16f32_align1: +; SSE2: # %bb.0: +; SSE2-NEXT: xorl %eax, %eax +; SSE2-NEXT: movntiq %rax, 8(%rdi) +; SSE2-NEXT: movntiq %rax, (%rdi) +; SSE2-NEXT: movntiq %rax, 24(%rdi) +; SSE2-NEXT: movntiq %rax, 16(%rdi) +; SSE2-NEXT: movntiq %rax, 40(%rdi) +; SSE2-NEXT: movntiq %rax, 32(%rdi) +; SSE2-NEXT: movntiq %rax, 56(%rdi) +; SSE2-NEXT: movntiq %rax, 48(%rdi) +; SSE2-NEXT: retq +; +; SSE4A-LABEL: test_zero_v16f32_align1: +; SSE4A: # %bb.0: +; SSE4A-NEXT: xorl %eax, %eax +; SSE4A-NEXT: movntiq %rax, 8(%rdi) +; SSE4A-NEXT: movntiq %rax, 24(%rdi) +; SSE4A-NEXT: movntiq %rax, 40(%rdi) +; SSE4A-NEXT: movntiq %rax, 56(%rdi) +; SSE4A-NEXT: xorps %xmm0, %xmm0 +; SSE4A-NEXT: movntsd %xmm0, (%rdi) +; SSE4A-NEXT: movntsd %xmm0, 16(%rdi) +; SSE4A-NEXT: movntsd %xmm0, 32(%rdi) +; SSE4A-NEXT: movntsd %xmm0, 48(%rdi) +; SSE4A-NEXT: retq +; +; SSE41-LABEL: test_zero_v16f32_align1: +; SSE41: # %bb.0: +; SSE41-NEXT: xorl %eax, %eax +; SSE41-NEXT: movntiq %rax, 8(%rdi) +; SSE41-NEXT: movntiq %rax, (%rdi) +; SSE41-NEXT: movntiq %rax, 24(%rdi) +; SSE41-NEXT: movntiq %rax, 16(%rdi) +; SSE41-NEXT: movntiq %rax, 40(%rdi) +; SSE41-NEXT: movntiq %rax, 32(%rdi) +; SSE41-NEXT: movntiq %rax, 56(%rdi) +; SSE41-NEXT: movntiq %rax, 48(%rdi) +; SSE41-NEXT: retq +; +; AVX-LABEL: test_zero_v16f32_align1: +; AVX: # %bb.0: +; AVX-NEXT: xorl %eax, %eax +; AVX-NEXT: movntiq %rax, 8(%rdi) +; AVX-NEXT: movntiq %rax, (%rdi) +; AVX-NEXT: movntiq %rax, 24(%rdi) +; AVX-NEXT: movntiq %rax, 16(%rdi) +; AVX-NEXT: movntiq %rax, 40(%rdi) +; AVX-NEXT: movntiq %rax, 32(%rdi) +; AVX-NEXT: movntiq %rax, 56(%rdi) +; AVX-NEXT: movntiq %rax, 48(%rdi) +; AVX-NEXT: retq +; +; AVX512-LABEL: test_zero_v16f32_align1: +; AVX512: # %bb.0: +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: movntiq %rax, 8(%rdi) +; AVX512-NEXT: movntiq %rax, (%rdi) +; AVX512-NEXT: movntiq %rax, 24(%rdi) +; AVX512-NEXT: movntiq %rax, 16(%rdi) +; AVX512-NEXT: movntiq %rax, 40(%rdi) +; AVX512-NEXT: movntiq %rax, 32(%rdi) +; AVX512-NEXT: movntiq %rax, 56(%rdi) +; AVX512-NEXT: movntiq %rax, 48(%rdi) +; AVX512-NEXT: retq store <16 x float> zeroinitializer, ptr %dst, align 1, !nontemporal !1 ret void } define void @test_zero_v8i64_align1(ptr %dst) nounwind { -; CHECK-LABEL: test_zero_v8i64_align1: -; CHECK: # %bb.0: -; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: movntiq %rax, 8(%rdi) -; CHECK-NEXT: movntiq %rax, (%rdi) -; CHECK-NEXT: movntiq %rax, 24(%rdi) -; CHECK-NEXT: movntiq %rax, 16(%rdi) -; CHECK-NEXT: movntiq %rax, 40(%rdi) -; CHECK-NEXT: movntiq %rax, 32(%rdi) -; CHECK-NEXT: movntiq %rax, 56(%rdi) -; CHECK-NEXT: movntiq %rax, 48(%rdi) -; CHECK-NEXT: retq +; SSE2-LABEL: test_zero_v8i64_align1: +; SSE2: # %bb.0: +; SSE2-NEXT: xorl %eax, %eax +; SSE2-NEXT: movntiq %rax, 8(%rdi) +; SSE2-NEXT: movntiq %rax, (%rdi) +; SSE2-NEXT: movntiq %rax, 24(%rdi) +; SSE2-NEXT: movntiq %rax, 16(%rdi) +; SSE2-NEXT: movntiq %rax, 40(%rdi) +; SSE2-NEXT: movntiq %rax, 32(%rdi) +; SSE2-NEXT: movntiq %rax, 56(%rdi) +; SSE2-NEXT: movntiq %rax, 48(%rdi) +; SSE2-NEXT: retq +; +; SSE4A-LABEL: test_zero_v8i64_align1: +; SSE4A: # %bb.0: +; SSE4A-NEXT: xorps %xmm0, %xmm0 +; SSE4A-NEXT: movntsd %xmm0, 8(%rdi) +; SSE4A-NEXT: movntsd %xmm0, (%rdi) +; SSE4A-NEXT: movntsd %xmm0, 24(%rdi) +; SSE4A-NEXT: movntsd %xmm0, 16(%rdi) +; SSE4A-NEXT: movntsd %xmm0, 40(%rdi) +; SSE4A-NEXT: movntsd %xmm0, 32(%rdi) +; SSE4A-NEXT: movntsd %xmm0, 56(%rdi) +; SSE4A-NEXT: movntsd %xmm0, 48(%rdi) +; SSE4A-NEXT: retq +; +; SSE41-LABEL: test_zero_v8i64_align1: +; SSE41: # %bb.0: +; SSE41-NEXT: xorl %eax, %eax +; SSE41-NEXT: movntiq %rax, 8(%rdi) +; SSE41-NEXT: movntiq %rax, (%rdi) +; SSE41-NEXT: movntiq %rax, 24(%rdi) +; SSE41-NEXT: movntiq %rax, 16(%rdi) +; SSE41-NEXT: movntiq %rax, 40(%rdi) +; SSE41-NEXT: movntiq %rax, 32(%rdi) +; SSE41-NEXT: movntiq %rax, 56(%rdi) +; SSE41-NEXT: movntiq %rax, 48(%rdi) +; SSE41-NEXT: retq +; +; AVX-LABEL: test_zero_v8i64_align1: +; AVX: # %bb.0: +; AVX-NEXT: xorl %eax, %eax +; AVX-NEXT: movntiq %rax, 8(%rdi) +; AVX-NEXT: movntiq %rax, (%rdi) +; AVX-NEXT: movntiq %rax, 24(%rdi) +; AVX-NEXT: movntiq %rax, 16(%rdi) +; AVX-NEXT: movntiq %rax, 40(%rdi) +; AVX-NEXT: movntiq %rax, 32(%rdi) +; AVX-NEXT: movntiq %rax, 56(%rdi) +; AVX-NEXT: movntiq %rax, 48(%rdi) +; AVX-NEXT: retq +; +; AVX512-LABEL: test_zero_v8i64_align1: +; AVX512: # %bb.0: +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: movntiq %rax, 8(%rdi) +; AVX512-NEXT: movntiq %rax, (%rdi) +; AVX512-NEXT: movntiq %rax, 24(%rdi) +; AVX512-NEXT: movntiq %rax, 16(%rdi) +; AVX512-NEXT: movntiq %rax, 40(%rdi) +; AVX512-NEXT: movntiq %rax, 32(%rdi) +; AVX512-NEXT: movntiq %rax, 56(%rdi) +; AVX512-NEXT: movntiq %rax, 48(%rdi) +; AVX512-NEXT: retq store <8 x i64> zeroinitializer, ptr %dst, align 1, !nontemporal !1 ret void } define void @test_zero_v16i32_align1(ptr %dst) nounwind { -; CHECK-LABEL: test_zero_v16i32_align1: -; CHECK: # %bb.0: -; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: movntiq %rax, 8(%rdi) -; CHECK-NEXT: movntiq %rax, (%rdi) -; CHECK-NEXT: movntiq %rax, 24(%rdi) -; CHECK-NEXT: movntiq %rax, 16(%rdi) -; CHECK-NEXT: movntiq %rax, 40(%rdi) -; CHECK-NEXT: movntiq %rax, 32(%rdi) -; CHECK-NEXT: movntiq %rax, 56(%rdi) -; CHECK-NEXT: movntiq %rax, 48(%rdi) -; CHECK-NEXT: retq +; SSE2-LABEL: test_zero_v16i32_align1: +; SSE2: # %bb.0: +; SSE2-NEXT: xorl %eax, %eax +; SSE2-NEXT: movntiq %rax, 8(%rdi) +; SSE2-NEXT: movntiq %rax, (%rdi) +; SSE2-NEXT: movntiq %rax, 24(%rdi) +; SSE2-NEXT: movntiq %rax, 16(%rdi) +; SSE2-NEXT: movntiq %rax, 40(%rdi) +; SSE2-NEXT: movntiq %rax, 32(%rdi) +; SSE2-NEXT: movntiq %rax, 56(%rdi) +; SSE2-NEXT: movntiq %rax, 48(%rdi) +; SSE2-NEXT: retq +; +; SSE4A-LABEL: test_zero_v16i32_align1: +; SSE4A: # %bb.0: +; SSE4A-NEXT: xorps %xmm0, %xmm0 +; SSE4A-NEXT: movntsd %xmm0, 8(%rdi) +; SSE4A-NEXT: movntsd %xmm0, (%rdi) +; SSE4A-NEXT: movntsd %xmm0, 24(%rdi) +; SSE4A-NEXT: movntsd %xmm0, 16(%rdi) +; SSE4A-NEXT: movntsd %xmm0, 40(%rdi) +; SSE4A-NEXT: movntsd %xmm0, 32(%rdi) +; SSE4A-NEXT: movntsd %xmm0, 56(%rdi) +; SSE4A-NEXT: movntsd %xmm0, 48(%rdi) +; SSE4A-NEXT: retq +; +; SSE41-LABEL: test_zero_v16i32_align1: +; SSE41: # %bb.0: +; SSE41-NEXT: xorl %eax, %eax +; SSE41-NEXT: movntiq %rax, 8(%rdi) +; SSE41-NEXT: movntiq %rax, (%rdi) +; SSE41-NEXT: movntiq %rax, 24(%rdi) +; SSE41-NEXT: movntiq %rax, 16(%rdi) +; SSE41-NEXT: movntiq %rax, 40(%rdi) +; SSE41-NEXT: movntiq %rax, 32(%rdi) +; SSE41-NEXT: movntiq %rax, 56(%rdi) +; SSE41-NEXT: movntiq %rax, 48(%rdi) +; SSE41-NEXT: retq +; +; AVX-LABEL: test_zero_v16i32_align1: +; AVX: # %bb.0: +; AVX-NEXT: xorl %eax, %eax +; AVX-NEXT: movntiq %rax, 8(%rdi) +; AVX-NEXT: movntiq %rax, (%rdi) +; AVX-NEXT: movntiq %rax, 24(%rdi) +; AVX-NEXT: movntiq %rax, 16(%rdi) +; AVX-NEXT: movntiq %rax, 40(%rdi) +; AVX-NEXT: movntiq %rax, 32(%rdi) +; AVX-NEXT: movntiq %rax, 56(%rdi) +; AVX-NEXT: movntiq %rax, 48(%rdi) +; AVX-NEXT: retq +; +; AVX512-LABEL: test_zero_v16i32_align1: +; AVX512: # %bb.0: +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: movntiq %rax, 8(%rdi) +; AVX512-NEXT: movntiq %rax, (%rdi) +; AVX512-NEXT: movntiq %rax, 24(%rdi) +; AVX512-NEXT: movntiq %rax, 16(%rdi) +; AVX512-NEXT: movntiq %rax, 40(%rdi) +; AVX512-NEXT: movntiq %rax, 32(%rdi) +; AVX512-NEXT: movntiq %rax, 56(%rdi) +; AVX512-NEXT: movntiq %rax, 48(%rdi) +; AVX512-NEXT: retq store <16 x i32> zeroinitializer, ptr %dst, align 1, !nontemporal !1 ret void } define void @test_zero_v32i16_align1(ptr %dst) nounwind { -; CHECK-LABEL: test_zero_v32i16_align1: -; CHECK: # %bb.0: -; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: movntiq %rax, 8(%rdi) -; CHECK-NEXT: movntiq %rax, (%rdi) -; CHECK-NEXT: movntiq %rax, 24(%rdi) -; CHECK-NEXT: movntiq %rax, 16(%rdi) -; CHECK-NEXT: movntiq %rax, 40(%rdi) -; CHECK-NEXT: movntiq %rax, 32(%rdi) -; CHECK-NEXT: movntiq %rax, 56(%rdi) -; CHECK-NEXT: movntiq %rax, 48(%rdi) -; CHECK-NEXT: retq +; SSE2-LABEL: test_zero_v32i16_align1: +; SSE2: # %bb.0: +; SSE2-NEXT: xorl %eax, %eax +; SSE2-NEXT: movntiq %rax, 8(%rdi) +; SSE2-NEXT: movntiq %rax, (%rdi) +; SSE2-NEXT: movntiq %rax, 24(%rdi) +; SSE2-NEXT: movntiq %rax, 16(%rdi) +; SSE2-NEXT: movntiq %rax, 40(%rdi) +; SSE2-NEXT: movntiq %rax, 32(%rdi) +; SSE2-NEXT: movntiq %rax, 56(%rdi) +; SSE2-NEXT: movntiq %rax, 48(%rdi) +; SSE2-NEXT: retq +; +; SSE4A-LABEL: test_zero_v32i16_align1: +; SSE4A: # %bb.0: +; SSE4A-NEXT: xorps %xmm0, %xmm0 +; SSE4A-NEXT: movntsd %xmm0, 8(%rdi) +; SSE4A-NEXT: movntsd %xmm0, (%rdi) +; SSE4A-NEXT: movntsd %xmm0, 24(%rdi) +; SSE4A-NEXT: movntsd %xmm0, 16(%rdi) +; SSE4A-NEXT: movntsd %xmm0, 40(%rdi) +; SSE4A-NEXT: movntsd %xmm0, 32(%rdi) +; SSE4A-NEXT: movntsd %xmm0, 56(%rdi) +; SSE4A-NEXT: movntsd %xmm0, 48(%rdi) +; SSE4A-NEXT: retq +; +; SSE41-LABEL: test_zero_v32i16_align1: +; SSE41: # %bb.0: +; SSE41-NEXT: xorl %eax, %eax +; SSE41-NEXT: movntiq %rax, 8(%rdi) +; SSE41-NEXT: movntiq %rax, (%rdi) +; SSE41-NEXT: movntiq %rax, 24(%rdi) +; SSE41-NEXT: movntiq %rax, 16(%rdi) +; SSE41-NEXT: movntiq %rax, 40(%rdi) +; SSE41-NEXT: movntiq %rax, 32(%rdi) +; SSE41-NEXT: movntiq %rax, 56(%rdi) +; SSE41-NEXT: movntiq %rax, 48(%rdi) +; SSE41-NEXT: retq +; +; AVX-LABEL: test_zero_v32i16_align1: +; AVX: # %bb.0: +; AVX-NEXT: xorl %eax, %eax +; AVX-NEXT: movntiq %rax, 8(%rdi) +; AVX-NEXT: movntiq %rax, (%rdi) +; AVX-NEXT: movntiq %rax, 24(%rdi) +; AVX-NEXT: movntiq %rax, 16(%rdi) +; AVX-NEXT: movntiq %rax, 40(%rdi) +; AVX-NEXT: movntiq %rax, 32(%rdi) +; AVX-NEXT: movntiq %rax, 56(%rdi) +; AVX-NEXT: movntiq %rax, 48(%rdi) +; AVX-NEXT: retq +; +; AVX512-LABEL: test_zero_v32i16_align1: +; AVX512: # %bb.0: +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: movntiq %rax, 8(%rdi) +; AVX512-NEXT: movntiq %rax, (%rdi) +; AVX512-NEXT: movntiq %rax, 24(%rdi) +; AVX512-NEXT: movntiq %rax, 16(%rdi) +; AVX512-NEXT: movntiq %rax, 40(%rdi) +; AVX512-NEXT: movntiq %rax, 32(%rdi) +; AVX512-NEXT: movntiq %rax, 56(%rdi) +; AVX512-NEXT: movntiq %rax, 48(%rdi) +; AVX512-NEXT: retq store <32 x i16> zeroinitializer, ptr %dst, align 1, !nontemporal !1 ret void } define void @test_zero_v64i8_align1(ptr %dst) nounwind { -; CHECK-LABEL: test_zero_v64i8_align1: -; CHECK: # %bb.0: -; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: movntiq %rax, 8(%rdi) -; CHECK-NEXT: movntiq %rax, (%rdi) -; CHECK-NEXT: movntiq %rax, 24(%rdi) -; CHECK-NEXT: movntiq %rax, 16(%rdi) -; CHECK-NEXT: movntiq %rax, 40(%rdi) -; CHECK-NEXT: movntiq %rax, 32(%rdi) -; CHECK-NEXT: movntiq %rax, 56(%rdi) -; CHECK-NEXT: movntiq %rax, 48(%rdi) -; CHECK-NEXT: retq +; SSE2-LABEL: test_zero_v64i8_align1: +; SSE2: # %bb.0: +; SSE2-NEXT: xorl %eax, %eax +; SSE2-NEXT: movntiq %rax, 8(%rdi) +; SSE2-NEXT: movntiq %rax, (%rdi) +; SSE2-NEXT: movntiq %rax, 24(%rdi) +; SSE2-NEXT: movntiq %rax, 16(%rdi) +; SSE2-NEXT: movntiq %rax, 40(%rdi) +; SSE2-NEXT: movntiq %rax, 32(%rdi) +; SSE2-NEXT: movntiq %rax, 56(%rdi) +; SSE2-NEXT: movntiq %rax, 48(%rdi) +; SSE2-NEXT: retq +; +; SSE4A-LABEL: test_zero_v64i8_align1: +; SSE4A: # %bb.0: +; SSE4A-NEXT: xorps %xmm0, %xmm0 +; SSE4A-NEXT: movntsd %xmm0, 8(%rdi) +; SSE4A-NEXT: movntsd %xmm0, (%rdi) +; SSE4A-NEXT: movntsd %xmm0, 24(%rdi) +; SSE4A-NEXT: movntsd %xmm0, 16(%rdi) +; SSE4A-NEXT: movntsd %xmm0, 40(%rdi) +; SSE4A-NEXT: movntsd %xmm0, 32(%rdi) +; SSE4A-NEXT: movntsd %xmm0, 56(%rdi) +; SSE4A-NEXT: movntsd %xmm0, 48(%rdi) +; SSE4A-NEXT: retq +; +; SSE41-LABEL: test_zero_v64i8_align1: +; SSE41: # %bb.0: +; SSE41-NEXT: xorl %eax, %eax +; SSE41-NEXT: movntiq %rax, 8(%rdi) +; SSE41-NEXT: movntiq %rax, (%rdi) +; SSE41-NEXT: movntiq %rax, 24(%rdi) +; SSE41-NEXT: movntiq %rax, 16(%rdi) +; SSE41-NEXT: movntiq %rax, 40(%rdi) +; SSE41-NEXT: movntiq %rax, 32(%rdi) +; SSE41-NEXT: movntiq %rax, 56(%rdi) +; SSE41-NEXT: movntiq %rax, 48(%rdi) +; SSE41-NEXT: retq +; +; AVX-LABEL: test_zero_v64i8_align1: +; AVX: # %bb.0: +; AVX-NEXT: xorl %eax, %eax +; AVX-NEXT: movntiq %rax, 8(%rdi) +; AVX-NEXT: movntiq %rax, (%rdi) +; AVX-NEXT: movntiq %rax, 24(%rdi) +; AVX-NEXT: movntiq %rax, 16(%rdi) +; AVX-NEXT: movntiq %rax, 40(%rdi) +; AVX-NEXT: movntiq %rax, 32(%rdi) +; AVX-NEXT: movntiq %rax, 56(%rdi) +; AVX-NEXT: movntiq %rax, 48(%rdi) +; AVX-NEXT: retq +; +; AVX512-LABEL: test_zero_v64i8_align1: +; AVX512: # %bb.0: +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: movntiq %rax, 8(%rdi) +; AVX512-NEXT: movntiq %rax, (%rdi) +; AVX512-NEXT: movntiq %rax, 24(%rdi) +; AVX512-NEXT: movntiq %rax, 16(%rdi) +; AVX512-NEXT: movntiq %rax, 40(%rdi) +; AVX512-NEXT: movntiq %rax, 32(%rdi) +; AVX512-NEXT: movntiq %rax, 56(%rdi) +; AVX512-NEXT: movntiq %rax, 48(%rdi) +; AVX512-NEXT: retq store <64 x i8> zeroinitializer, ptr %dst, align 1, !nontemporal !1 ret void } @@ -772,7 +1214,3 @@ define void @test_zero_v64i8_align32(ptr %dst) nounwind { } !1 = !{i32 1} -;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; SSE2: {{.*}} -; SSE41: {{.*}} -; SSE4A: {{.*}} diff --git a/llvm/test/CodeGen/X86/pr13577.ll b/llvm/test/CodeGen/X86/pr13577.ll index ef359e740c09..7511560d85f5 100644 --- a/llvm/test/CodeGen/X86/pr13577.ll +++ b/llvm/test/CodeGen/X86/pr13577.ll @@ -29,8 +29,7 @@ declare x86_fp80 @copysignl(x86_fp80, x86_fp80) nounwind readnone define float @pr26070() { ; CHECK-LABEL: pr26070: ; CHECK: ## %bb.0: -; CHECK-NEXT: xorps %xmm0, %xmm0 -; CHECK-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-NEXT: retq %c = call float @copysignf(float 1.0, float undef) readnone ret float %c diff --git a/llvm/test/CodeGen/X86/pr41619.ll b/llvm/test/CodeGen/X86/pr41619.ll index 88dcd7798f0c..7d1d139a38a5 100644 --- a/llvm/test/CodeGen/X86/pr41619.ll +++ b/llvm/test/CodeGen/X86/pr41619.ll @@ -7,9 +7,10 @@ define void @foo(double %arg) { ; CHECK: ## %bb.0: ## %bb ; CHECK-NEXT: vmovq %xmm0, %rax ; CHECK-NEXT: vmovd %eax, %xmm0 +; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; CHECK-NEXT: vmovq %xmm0, %rax ; CHECK-NEXT: movl %eax, (%rax) -; CHECK-NEXT: movq $0, (%rax) +; CHECK-NEXT: vmovlps %xmm1, (%rax) ; CHECK-NEXT: retq bb: %tmp = bitcast double %arg to i64 diff --git a/llvm/test/CodeGen/X86/vec_zero_cse.ll b/llvm/test/CodeGen/X86/vec_zero_cse.ll index 800dd59c2626..99185277ba74 100644 --- a/llvm/test/CodeGen/X86/vec_zero_cse.ll +++ b/llvm/test/CodeGen/X86/vec_zero_cse.ll @@ -15,8 +15,8 @@ define void @test1() { ; X32: # %bb.0: ; X32-NEXT: movl $0, M1+4 ; X32-NEXT: movl $0, M1 -; X32-NEXT: movl $0, M2+4 -; X32-NEXT: movl $0, M2 +; X32-NEXT: xorps %xmm0, %xmm0 +; X32-NEXT: movlps %xmm0, M2 ; X32-NEXT: retl ; ; X64-LABEL: test1: diff --git a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll index eb5fc1523c08..23c37af1db2f 100644 --- a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll +++ b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll @@ -108,10 +108,11 @@ define void @PR46178(ptr %0) { ; X86-NEXT: vmovdqu (%eax), %ymm1 ; X86-NEXT: vpmovqw %ymm0, %xmm0 ; X86-NEXT: vpmovqw %ymm1, %xmm1 -; X86-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 -; X86-NEXT: vpsllw $8, %ymm0, %ymm0 -; X86-NEXT: vpsraw $8, %ymm0, %ymm0 -; X86-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,1,1] +; X86-NEXT: vpsllw $8, %xmm0, %xmm0 +; X86-NEXT: vpsraw $8, %xmm0, %xmm0 +; X86-NEXT: vpsllw $8, %xmm1, %xmm1 +; X86-NEXT: vpsraw $8, %xmm1, %xmm1 +; X86-NEXT: vpunpcklqdq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2] ; X86-NEXT: vmovdqu %ymm0, (%eax) ; X86-NEXT: vzeroupper ; X86-NEXT: retl -- GitLab From ff485a0e77a55847cb50768b01c04fe45a6879ea Mon Sep 17 00:00:00 2001 From: Youngsuk Kim Date: Thu, 30 Nov 2023 13:57:12 -0600 Subject: [PATCH 030/699] [clang] Remove no-op ptr-to-ptr bitcasts (NFC) Opaque ptr cleanup effort (NFC). --- clang/lib/CodeGen/CGObjC.cpp | 10 +--------- clang/lib/CodeGen/MicrosoftCXXABI.cpp | 4 +--- 2 files changed, 2 insertions(+), 12 deletions(-) diff --git a/clang/lib/CodeGen/CGObjC.cpp b/clang/lib/CodeGen/CGObjC.cpp index fff89c8939a5..acc85165a470 100644 --- a/clang/lib/CodeGen/CGObjC.cpp +++ b/clang/lib/CodeGen/CGObjC.cpp @@ -827,11 +827,8 @@ static void emitStructGetterCall(CodeGenFunction &CGF, ObjCIvarDecl *ivar, // sizeof (Type of Ivar), isAtomic, false); CallArgList args; - llvm::Value *dest = - CGF.Builder.CreateBitCast(CGF.ReturnValue.getPointer(), CGF.VoidPtrTy); + llvm::Value *dest = CGF.ReturnValue.getPointer(); args.add(RValue::get(dest), Context.VoidPtrTy); - - src = CGF.Builder.CreateBitCast(src, CGF.VoidPtrTy); args.add(RValue::get(src), Context.VoidPtrTy); CharUnits size = CGF.getContext().getTypeSizeInChars(ivar->getType()); @@ -1098,7 +1095,6 @@ static void emitCPPObjectAtomicGetterCall(CodeGenFunction &CGF, llvm::Value *ivarAddr = CGF.EmitLValueForIvar(CGF.TypeOfSelfObject(), CGF.LoadObjCSelf(), ivar, 0) .getPointer(CGF); - ivarAddr = CGF.Builder.CreateBitCast(ivarAddr, CGF.Int8PtrTy); args.add(RValue::get(ivarAddr), CGF.getContext().VoidPtrTy); // Third argument is the helper function. @@ -1340,7 +1336,6 @@ static void emitStructSetterCall(CodeGenFunction &CGF, ObjCMethodDecl *OMD, argVar->getType().getNonReferenceType(), VK_LValue, SourceLocation()); llvm::Value *argAddr = CGF.EmitLValue(&argRef).getPointer(CGF); - argAddr = CGF.Builder.CreateBitCast(argAddr, CGF.Int8PtrTy); args.add(RValue::get(argAddr), CGF.getContext().VoidPtrTy); // The third argument is the sizeof the type. @@ -1377,7 +1372,6 @@ static void emitCPPObjectAtomicSetterCall(CodeGenFunction &CGF, llvm::Value *ivarAddr = CGF.EmitLValueForIvar(CGF.TypeOfSelfObject(), CGF.LoadObjCSelf(), ivar, 0) .getPointer(CGF); - ivarAddr = CGF.Builder.CreateBitCast(ivarAddr, CGF.Int8PtrTy); args.add(RValue::get(ivarAddr), CGF.getContext().VoidPtrTy); // The second argument is the address of the parameter variable. @@ -1386,7 +1380,6 @@ static void emitCPPObjectAtomicSetterCall(CodeGenFunction &CGF, argVar->getType().getNonReferenceType(), VK_LValue, SourceLocation()); llvm::Value *argAddr = CGF.EmitLValue(&argRef).getPointer(CGF); - argAddr = CGF.Builder.CreateBitCast(argAddr, CGF.Int8PtrTy); args.add(RValue::get(argAddr), CGF.getContext().VoidPtrTy); // Third argument is the helper function. @@ -3685,7 +3678,6 @@ void CodeGenFunction::EmitExtendGCLifetime(llvm::Value *object) { /* constraints */ "r", /* side effects */ true); - object = Builder.CreateBitCast(object, VoidPtrTy); EmitNounwindRuntimeCall(extender, object); } diff --git a/clang/lib/CodeGen/MicrosoftCXXABI.cpp b/clang/lib/CodeGen/MicrosoftCXXABI.cpp index 44b9acdee626..172c4c937b97 100644 --- a/clang/lib/CodeGen/MicrosoftCXXABI.cpp +++ b/clang/lib/CodeGen/MicrosoftCXXABI.cpp @@ -2266,7 +2266,6 @@ MicrosoftCXXABI::performReturnAdjustment(CodeGenFunction &CGF, Address Ret, if (RA.isEmpty()) return Ret.getPointer(); - auto OrigTy = Ret.getType(); Ret = Ret.withElementType(CGF.Int8Ty); llvm::Value *V = Ret.getPointer(); @@ -2283,8 +2282,7 @@ MicrosoftCXXABI::performReturnAdjustment(CodeGenFunction &CGF, Address Ret, if (RA.NonVirtual) V = CGF.Builder.CreateConstInBoundsGEP1_32(CGF.Int8Ty, V, RA.NonVirtual); - // Cast back to the original type. - return CGF.Builder.CreateBitCast(V, OrigTy); + return V; } bool MicrosoftCXXABI::requiresArrayCookie(const CXXDeleteExpr *expr, -- GitLab From c8f72856dbdd0039fc16eae51726da105ea679c0 Mon Sep 17 00:00:00 2001 From: John Harrison Date: Thu, 30 Nov 2023 12:17:12 -0800 Subject: [PATCH 031/699] [lldb-dap] Fixing a type encoding issue with dap Stopped events. (#72292) Previously the type of the breakpoint id in the Stopped event was a uint64_t, however thats the wrong type for a breakpoint id, which can cause encoding issues when internal breakpoints are hit. --- lldb/tools/lldb-dap/JSONUtils.cpp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/lldb/tools/lldb-dap/JSONUtils.cpp b/lldb/tools/lldb-dap/JSONUtils.cpp index 03a43f9da87f..3a63046d9a88 100644 --- a/lldb/tools/lldb-dap/JSONUtils.cpp +++ b/lldb/tools/lldb-dap/JSONUtils.cpp @@ -13,6 +13,7 @@ #include #include "llvm/Support/FormatAdapters.h" +#include "llvm/Support/FormatVariadic.h" #include "llvm/Support/Path.h" #include "llvm/Support/ScopedPrinter.h" @@ -959,11 +960,10 @@ llvm::json::Value CreateThreadStopped(lldb::SBThread &thread, EmplaceSafeString(body, "description", exc_bp->label); } else { body.try_emplace("reason", "breakpoint"); - char desc_str[64]; - uint64_t bp_id = thread.GetStopReasonDataAtIndex(0); - uint64_t bp_loc_id = thread.GetStopReasonDataAtIndex(1); - snprintf(desc_str, sizeof(desc_str), "breakpoint %" PRIu64 ".%" PRIu64, - bp_id, bp_loc_id); + lldb::break_id_t bp_id = thread.GetStopReasonDataAtIndex(0); + lldb::break_id_t bp_loc_id = thread.GetStopReasonDataAtIndex(1); + std::string desc_str = + llvm::formatv("breakpoint {0}.{1}", bp_id, bp_loc_id); body.try_emplace("hitBreakpointIds", llvm::json::Array{llvm::json::Value(bp_id)}); EmplaceSafeString(body, "description", desc_str); -- GitLab From f8a21dff70cc5d20db731b3af1858c5a2ae96d30 Mon Sep 17 00:00:00 2001 From: Natalie Chouinard <1953083+sudonatalie@users.noreply.github.com> Date: Thu, 30 Nov 2023 15:17:32 -0500 Subject: [PATCH 032/699] [SPIR-V] Mark currently failing tests as XFAIL (#73858) These tests are currently failing and their fix is being tracked in Issue #60133. Marking them as XFAIL for now will get the test suite to a passing state so we can work on adding a GitHub action to automatically run these tests on a PR bot to help keep the tree green. Also removed the no-longer supported -opaque-pointers=0 flag from the couple tests where it was remaining. --- llvm/test/CodeGen/SPIRV/EnqueueEmptyKernel.ll | 3 +++ llvm/test/CodeGen/SPIRV/half_no_extension.ll | 3 +++ llvm/test/CodeGen/SPIRV/linked-list.ll | 5 ++++- llvm/test/CodeGen/SPIRV/opencl/basic/vstore_private.ll | 3 +++ .../CodeGen/SPIRV/opencl/device_execution/execute_block.ll | 3 +++ llvm/test/CodeGen/SPIRV/pstruct.ll | 5 ++++- llvm/test/CodeGen/SPIRV/transcoding/BuildNDRange_2.ll | 3 +++ llvm/test/CodeGen/SPIRV/transcoding/block_w_struct_return.ll | 3 +++ llvm/test/CodeGen/SPIRV/transcoding/enqueue_kernel.ll | 3 +++ llvm/test/CodeGen/SPIRV/transcoding/extract_insert_value.ll | 5 ++++- llvm/test/CodeGen/SPIRV/transcoding/global_block.ll | 3 +++ 11 files changed, 36 insertions(+), 3 deletions(-) diff --git a/llvm/test/CodeGen/SPIRV/EnqueueEmptyKernel.ll b/llvm/test/CodeGen/SPIRV/EnqueueEmptyKernel.ll index 679f8ff7a001..a6f172a81dc7 100644 --- a/llvm/test/CodeGen/SPIRV/EnqueueEmptyKernel.ll +++ b/llvm/test/CodeGen/SPIRV/EnqueueEmptyKernel.ll @@ -1,5 +1,8 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; TODO(#60133): Requires updates following opaque pointer migration. +; XFAIL: * + ;; This test checks that Invoke parameter of OpEnueueKernel instruction meet the ;; following specification requirements in case of enqueueing empty block: ;; "Invoke must be an OpFunction whose OpTypeFunction operand has: diff --git a/llvm/test/CodeGen/SPIRV/half_no_extension.ll b/llvm/test/CodeGen/SPIRV/half_no_extension.ll index a5b0ec9c92d2..6414b62874bc 100644 --- a/llvm/test/CodeGen/SPIRV/half_no_extension.ll +++ b/llvm/test/CodeGen/SPIRV/half_no_extension.ll @@ -7,6 +7,9 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; TODO(#60133): Requires updates following opaque pointer migration. +; XFAIL: * + ; CHECK-SPIRV: OpCapability Float16Buffer ; CHECK-SPIRV-NOT: OpCapability Float16 diff --git a/llvm/test/CodeGen/SPIRV/linked-list.ll b/llvm/test/CodeGen/SPIRV/linked-list.ll index bce363385328..be7634f8a57a 100644 --- a/llvm/test/CodeGen/SPIRV/linked-list.ll +++ b/llvm/test/CodeGen/SPIRV/linked-list.ll @@ -1,4 +1,7 @@ -; RUN: llc -O0 -opaque-pointers=0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s + +; TODO(#60133): Requires updates following opaque pointer migration. +; XFAIL: * %struct.Node = type { %struct.Node.0 addrspace(1)* } ; CHECK: %[[#]] = OpTypeOpaque "struct.Node.0" diff --git a/llvm/test/CodeGen/SPIRV/opencl/basic/vstore_private.ll b/llvm/test/CodeGen/SPIRV/opencl/basic/vstore_private.ll index 2bc4b447c2ed..40f1d59e4365 100644 --- a/llvm/test/CodeGen/SPIRV/opencl/basic/vstore_private.ll +++ b/llvm/test/CodeGen/SPIRV/opencl/basic/vstore_private.ll @@ -1,5 +1,8 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; TODO(#60133): Requires updates following opaque pointer migration. +; XFAIL: * + ; CHECK: %[[#i16_ty:]] = OpTypeInt 16 0 ; CHECK: %[[#v4xi16_ty:]] = OpTypeVector %[[#i16_ty]] 4 ; CHECK: %[[#pv4xi16_ty:]] = OpTypePointer Function %[[#v4xi16_ty]] diff --git a/llvm/test/CodeGen/SPIRV/opencl/device_execution/execute_block.ll b/llvm/test/CodeGen/SPIRV/opencl/device_execution/execute_block.ll index 5b7ff169a947..b001ce09f567 100644 --- a/llvm/test/CodeGen/SPIRV/opencl/device_execution/execute_block.ll +++ b/llvm/test/CodeGen/SPIRV/opencl/device_execution/execute_block.ll @@ -1,5 +1,8 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; TODO(#60133): Requires updates following opaque pointer migration. +; XFAIL: * + ; CHECK: %[[#bool:]] = OpTypeBool ; CHECK: %[[#true:]] = OpConstantTrue %[[#bool]] ; CHECK: OpBranchConditional %[[#true]] diff --git a/llvm/test/CodeGen/SPIRV/pstruct.ll b/llvm/test/CodeGen/SPIRV/pstruct.ll index 01b05b01e70b..fd55e9b69e26 100644 --- a/llvm/test/CodeGen/SPIRV/pstruct.ll +++ b/llvm/test/CodeGen/SPIRV/pstruct.ll @@ -1,4 +1,7 @@ -; RUN: llc -O0 -opaque-pointers=0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV + +; TODO(#60133): Requires updates following opaque pointer migration. +; XFAIL: * %struct.ST = type { i32, i32, i32 } diff --git a/llvm/test/CodeGen/SPIRV/transcoding/BuildNDRange_2.ll b/llvm/test/CodeGen/SPIRV/transcoding/BuildNDRange_2.ll index 79d360324110..75aa87f958d4 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/BuildNDRange_2.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/BuildNDRange_2.ll @@ -20,6 +20,9 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; TODO(#60133): Requires updates following opaque pointer migration. +; XFAIL: * + ; CHECK-SPIRV-DAG: %[[#LEN2_ID:]] = OpConstant %[[#]] 2 ; CHECK-SPIRV-DAG: %[[#LEN3_ID:]] = OpConstant %[[#]] 3 ; CHECK-SPIRV-DAG: %[[#ARRAY_T2:]] = OpTypeArray %[[#]] %[[#LEN2_ID]] diff --git a/llvm/test/CodeGen/SPIRV/transcoding/block_w_struct_return.ll b/llvm/test/CodeGen/SPIRV/transcoding/block_w_struct_return.ll index 52b25a5913f0..5ecd7f73a52e 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/block_w_struct_return.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/block_w_struct_return.ll @@ -1,5 +1,8 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK-SPIRV,CHECK-SPIRV1_4 +; TODO(#60133): Requires updates following opaque pointer migration. +; XFAIL: * + ;; TODO: We cannot check SPIR_V 1.1 and 1.4 simultaneously, implement additional ;; run with CHECK-SPIRV1_1. diff --git a/llvm/test/CodeGen/SPIRV/transcoding/enqueue_kernel.ll b/llvm/test/CodeGen/SPIRV/transcoding/enqueue_kernel.ll index 6de03dd16518..cf124ec0a278 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/enqueue_kernel.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/enqueue_kernel.ll @@ -1,5 +1,8 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; TODO(#60133): Requires updates following opaque pointer migration. +; XFAIL: * + ; CHECK-SPIRV: OpEntryPoint Kernel %[[#BlockKer1:]] "__device_side_enqueue_block_invoke_kernel" ; CHECK-SPIRV: OpEntryPoint Kernel %[[#BlockKer2:]] "__device_side_enqueue_block_invoke_2_kernel" ; CHECK-SPIRV: OpEntryPoint Kernel %[[#BlockKer3:]] "__device_side_enqueue_block_invoke_3_kernel" diff --git a/llvm/test/CodeGen/SPIRV/transcoding/extract_insert_value.ll b/llvm/test/CodeGen/SPIRV/transcoding/extract_insert_value.ll index e0392d05cc30..fd29bc8a1ebf 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/extract_insert_value.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/extract_insert_value.ll @@ -1,4 +1,7 @@ -; RUN: llc -O0 -opaque-pointers=0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV + +; TODO(#60133): Requires updates following opaque pointer migration. +; XFAIL: * ;; Check 'LLVM ==> SPIR-V' conversion of extractvalue/insertvalue. diff --git a/llvm/test/CodeGen/SPIRV/transcoding/global_block.ll b/llvm/test/CodeGen/SPIRV/transcoding/global_block.ll index 96b275956178..2f44e1943b6a 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/global_block.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/global_block.ll @@ -1,5 +1,8 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK-SPIRV,CHECK-SPIRV1_4 +; TODO(#60133): Requires updates following opaque pointer migration. +; XFAIL: * + ;; There are no blocks in SPIR-V. Therefore they are translated into regular ;; functions. An LLVM module which uses blocks, also contains some auxiliary ;; block-specific instructions, which are redundant in SPIR-V and should be -- GitLab From e86591b37d4eb92ffca21b43b224d155ec688337 Mon Sep 17 00:00:00 2001 From: Peter Klausler <35819229+klausler@users.noreply.github.com> Date: Thu, 30 Nov 2023 12:22:04 -0800 Subject: [PATCH 033/699] =?UTF-8?q?[flang]=20Improve=20procedure=20interfa?= =?UTF-8?q?ce=20compatibility=20checking=20for=20dummy=20=E2=80=A6=20(#727?= =?UTF-8?q?04)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit …arrays When comparing dummy array extents, cope with references to symbols better (including references to other dummy arguments), and emit warnings in dubious cases that are not equivalent but not provably incompatible. --- flang/include/flang/Common/Fortran-features.h | 2 +- .../include/flang/Evaluate/characteristics.h | 14 ++- flang/include/flang/Evaluate/tools.h | 13 ++- flang/lib/Evaluate/characteristics.cpp | 60 +++++----- flang/lib/Evaluate/tools.cpp | 103 +++++++++++++++++- flang/lib/Semantics/check-call.cpp | 24 +++- flang/lib/Semantics/pointer-assignment.cpp | 8 +- flang/test/Semantics/argshape01.f90 | 91 +++++++++++++++- 8 files changed, 261 insertions(+), 54 deletions(-) diff --git a/flang/include/flang/Common/Fortran-features.h b/flang/include/flang/Common/Fortran-features.h index 7e518a210f01..a6b19e9833fc 100644 --- a/flang/include/flang/Common/Fortran-features.h +++ b/flang/include/flang/Common/Fortran-features.h @@ -53,7 +53,7 @@ ENUM_CLASS(UsageWarning, Portability, PointerToUndefinable, ShortCharacterActual, ExprPassedToVolatile, ImplicitInterfaceActual, PolymorphicTransferArg, PointerComponentTransferArg, TransferSizePresence, F202XAllocatableBreakingChange, DimMustBePresent, CommonBlockPadding, - LogicalVsCBool, BindCCharLength) + LogicalVsCBool, BindCCharLength, ProcDummyArgShapes) using LanguageFeatures = EnumSet; using UsageWarnings = EnumSet; diff --git a/flang/include/flang/Evaluate/characteristics.h b/flang/include/flang/Evaluate/characteristics.h index b07affc30262..43f8134b93c5 100644 --- a/flang/include/flang/Evaluate/characteristics.h +++ b/flang/include/flang/Evaluate/characteristics.h @@ -54,7 +54,8 @@ bool DistinguishableOpOrAssign(const common::LanguageFeatureControl &, // Shapes of function results and dummy arguments have to have // the same rank, the same deferred dimensions, and the same // values for explicit dimensions when constant. -bool ShapesAreCompatible(const Shape &, const Shape &); +bool ShapesAreCompatible( + const Shape &, const Shape &, bool *possibleWarning = nullptr); class TypeAndShape { public: @@ -222,8 +223,8 @@ struct DummyDataObject { bool operator!=(const DummyDataObject &that) const { return !(*this == that); } - bool IsCompatibleWith( - const DummyDataObject &, std::string *whyNot = nullptr) const; + bool IsCompatibleWith(const DummyDataObject &, std::string *whyNot = nullptr, + std::optional *warning = nullptr) const; static std::optional Characterize( const semantics::Symbol &, FoldingContext &); bool CanBePassedViaImplicitInterface() const; @@ -283,8 +284,8 @@ struct DummyArgument { void SetIntent(common::Intent); bool CanBePassedViaImplicitInterface() const; bool IsTypelessIntrinsicDummy() const; - bool IsCompatibleWith( - const DummyArgument &, std::string *whyNot = nullptr) const; + bool IsCompatibleWith(const DummyArgument &, std::string *whyNot = nullptr, + std::optional *warning = nullptr) const; llvm::raw_ostream &Dump(llvm::raw_ostream &) const; // name and pass are not characteristics and so do not participate in @@ -379,7 +380,8 @@ struct Procedure { bool CanBeCalledViaImplicitInterface() const; bool CanOverride(const Procedure &, std::optional passIndex) const; bool IsCompatibleWith(const Procedure &, std::string *whyNot = nullptr, - const SpecificIntrinsic * = nullptr) const; + const SpecificIntrinsic * = nullptr, + std::optional *warning = nullptr) const; llvm::raw_ostream &Dump(llvm::raw_ostream &) const; diff --git a/flang/include/flang/Evaluate/tools.h b/flang/include/flang/Evaluate/tools.h index ba065c4ee1b1..8a47a9f65166 100644 --- a/flang/include/flang/Evaluate/tools.h +++ b/flang/include/flang/Evaluate/tools.h @@ -1089,11 +1089,12 @@ bool IsExpandableScalar(const Expr &expr, FoldingContext &context, // Common handling for procedure pointer compatibility of left- and right-hand // sides. Returns nullopt if they're compatible. Otherwise, it returns a -// message that needs to be augmented by the names of the left and right sides +// message that needs to be augmented by the names of the left and right sides. std::optional CheckProcCompatibility(bool isCall, const std::optional &lhsProcedure, const characteristics::Procedure *rhsProcedure, - const SpecificIntrinsic *specificIntrinsic, std::string &whyNotCompatible); + const SpecificIntrinsic *specificIntrinsic, std::string &whyNotCompatible, + std::optional &warning); // Scalar constant expansion class ScalarConstantExpander { @@ -1185,6 +1186,12 @@ private: ConstantSubscripts &&lbounds_; }; +// Predicate: should two expressions be considered identical for the purposes +// of determining whether two procedure interfaces are compatible, modulo +// naming of corresponding dummy arguments? +std::optional AreEquivalentInInterface( + const Expr &, const Expr &); + } // namespace Fortran::evaluate namespace Fortran::semantics { @@ -1261,6 +1268,8 @@ bool AreTkCompatibleTypes(const DeclTypeSpec *x, const DeclTypeSpec *y); common::IgnoreTKRSet GetIgnoreTKR(const Symbol &); +std::optional GetDummyArgumentNumber(const Symbol *); + } // namespace Fortran::semantics #endif // FORTRAN_EVALUATE_TOOLS_H_ diff --git a/flang/lib/Evaluate/characteristics.cpp b/flang/lib/Evaluate/characteristics.cpp index 16aa08603bda..83ef5d069d3c 100644 --- a/flang/lib/Evaluate/characteristics.cpp +++ b/flang/lib/Evaluate/characteristics.cpp @@ -38,18 +38,23 @@ static void CopyAttrs(const semantics::Symbol &src, A &dst, // Shapes of function results and dummy arguments have to have // the same rank, the same deferred dimensions, and the same // values for explicit dimensions when constant. -bool ShapesAreCompatible(const Shape &x, const Shape &y) { +bool ShapesAreCompatible( + const Shape &x, const Shape &y, bool *possibleWarning) { if (x.size() != y.size()) { return false; } auto yIter{y.begin()}; for (const auto &xDim : x) { const auto &yDim{*yIter++}; - if (xDim) { - if (!yDim || ToInt64(*xDim) != ToInt64(*yDim)) { - return false; + if (xDim && yDim) { + if (auto equiv{AreEquivalentInInterface(*xDim, *yDim)}) { + if (!*equiv) { + return false; + } + } else if (possibleWarning) { + *possibleWarning = true; } - } else if (yDim) { + } else if (xDim || yDim) { return false; } } @@ -270,35 +275,19 @@ llvm::raw_ostream &TypeAndShape::Dump(llvm::raw_ostream &o) const { bool DummyDataObject::operator==(const DummyDataObject &that) const { return type == that.type && attrs == that.attrs && intent == that.intent && coshape == that.coshape && cudaDataAttr == that.cudaDataAttr; - ; -} - -static bool AreCompatibleDummyDataObjectShapes(const Shape &x, const Shape &y) { - int n{GetRank(x)}; - if (n != GetRank(y)) { - return false; - } - auto xIter{x.begin()}; - auto yIter{y.begin()}; - for (; n-- > 0; ++xIter, ++yIter) { - if (auto xVal{ToInt64(*xIter)}) { - if (auto yVal{ToInt64(*yIter)}) { - if (*xVal != *yVal) { - return false; - } - } - } - } - return true; } -bool DummyDataObject::IsCompatibleWith( - const DummyDataObject &actual, std::string *whyNot) const { - if (!AreCompatibleDummyDataObjectShapes(type.shape(), actual.type.shape())) { +bool DummyDataObject::IsCompatibleWith(const DummyDataObject &actual, + std::string *whyNot, std::optional *warning) const { + bool possibleWarning{false}; + if (!ShapesAreCompatible( + type.shape(), actual.type.shape(), &possibleWarning)) { if (whyNot) { *whyNot = "incompatible dummy data object shapes"; } return false; + } else if (warning && possibleWarning) { + *warning = "distinct dummy data object shapes"; } // Treat deduced dummy character type as if it were assumed-length character // to avoid useless "implicit interfaces have distinct type" warnings from @@ -748,11 +737,11 @@ bool DummyArgument::operator==(const DummyArgument &that) const { return u == that.u; // name and passed-object usage are not characteristics } -bool DummyArgument::IsCompatibleWith( - const DummyArgument &actual, std::string *whyNot) const { +bool DummyArgument::IsCompatibleWith(const DummyArgument &actual, + std::string *whyNot, std::optional *warning) const { if (const auto *ifaceData{std::get_if(&u)}) { if (const auto *actualData{std::get_if(&actual.u)}) { - return ifaceData->IsCompatibleWith(*actualData, whyNot); + return ifaceData->IsCompatibleWith(*actualData, whyNot, warning); } if (whyNot) { *whyNot = "one dummy argument is an object, the other is not"; @@ -1181,7 +1170,8 @@ bool Procedure::operator==(const Procedure &that) const { } bool Procedure::IsCompatibleWith(const Procedure &actual, std::string *whyNot, - const SpecificIntrinsic *specificIntrinsic) const { + const SpecificIntrinsic *specificIntrinsic, + std::optional *warning) const { // 15.5.2.9(1): if dummy is not pure, actual need not be. // Ditto with elemental. Attrs actualAttrs{actual.attrs}; @@ -1226,13 +1216,17 @@ bool Procedure::IsCompatibleWith(const Procedure &actual, std::string *whyNot, // subroutine s1(base); subroutine s2(extended) // procedure(s1), pointer :: p // p => s2 ! an error, s2 is more restricted, can't handle "base" + std::optional gotWarning; if (!actual.dummyArguments[j].IsCompatibleWith( - dummyArguments[j], whyNot)) { + dummyArguments[j], whyNot, warning ? &gotWarning : nullptr)) { if (whyNot) { *whyNot = "incompatible dummy argument #"s + std::to_string(j + 1) + ": "s + *whyNot; } return false; + } else if (warning && !*warning && gotWarning) { + *warning = "possibly incompatible dummy argument #"s + + std::to_string(j + 1) + ": "s + std::move(*gotWarning); } } return true; diff --git a/flang/lib/Evaluate/tools.cpp b/flang/lib/Evaluate/tools.cpp index 9d5164965253..8c755da4a2d8 100644 --- a/flang/lib/Evaluate/tools.cpp +++ b/flang/lib/Evaluate/tools.cpp @@ -1082,7 +1082,8 @@ std::optional FindImpureCall( std::optional CheckProcCompatibility(bool isCall, const std::optional &lhsProcedure, const characteristics::Procedure *rhsProcedure, - const SpecificIntrinsic *specificIntrinsic, std::string &whyNotCompatible) { + const SpecificIntrinsic *specificIntrinsic, std::string &whyNotCompatible, + std::optional &warning) { std::optional msg; if (!lhsProcedure) { msg = "In assignment to object %s, the target '%s' is a procedure" @@ -1096,8 +1097,8 @@ std::optional CheckProcCompatibility(bool isCall, *rhsProcedure->functionResult, &whyNotCompatible)) { msg = "Function %s associated with incompatible function designator '%s': %s"_err_en_US; - } else if (lhsProcedure->IsCompatibleWith( - *rhsProcedure, &whyNotCompatible, specificIntrinsic)) { + } else if (lhsProcedure->IsCompatibleWith(*rhsProcedure, &whyNotCompatible, + specificIntrinsic, &warning)) { // OK } else if (isCall) { msg = "Procedure %s associated with result of reference to function '%s'" @@ -1275,6 +1276,83 @@ std::optional> HollerithToBOZ(FoldingContext &context, } } +// Extracts a whole symbol being used as a bound of a dummy argument, +// possibly wrapped with parentheses or MAX(0, ...). +template +static const Symbol *GetBoundSymbol( + const Expr> &expr) { + using T = Type; + return common::visit( + common::visitors{ + [](const Extremum &max) -> const Symbol * { + if (max.ordering == Ordering::Greater) { + if (auto zero{ToInt64(max.left())}; zero && *zero == 0) { + return GetBoundSymbol(max.right()); + } + } + return nullptr; + }, + [](const Parentheses &x) { return GetBoundSymbol(x.left()); }, + [](const Designator &x) -> const Symbol * { + if (const auto *ref{std::get_if(&x.u)}) { + return &**ref; + } + return nullptr; + }, + [](const Convert &x) { + return common::visit( + [](const auto &y) -> const Symbol * { + using yType = std::decay_t; + using yResult = typename yType::Result; + if constexpr (yResult::kind <= KIND) { + return GetBoundSymbol(y); + } else { + return nullptr; + } + }, + x.left().u); + }, + [](const auto &) -> const Symbol * { return nullptr; }, + }, + expr.u); +} + +std::optional AreEquivalentInInterface( + const Expr &x, const Expr &y) { + auto xVal{ToInt64(x)}; + auto yVal{ToInt64(y)}; + if (xVal && yVal) { + return *xVal == *yVal; + } else if (xVal || yVal) { + return false; + } + const Symbol *xSym{GetBoundSymbol(x)}; + const Symbol *ySym{GetBoundSymbol(y)}; + if (xSym && ySym) { + if (&xSym->GetUltimate() == &ySym->GetUltimate()) { + return true; // USE/host associated same symbol + } + auto xNum{semantics::GetDummyArgumentNumber(xSym)}; + auto yNum{semantics::GetDummyArgumentNumber(ySym)}; + if (xNum && yNum) { + if (*xNum == *yNum) { + auto xType{DynamicType::From(*xSym)}; + auto yType{DynamicType::From(*ySym)}; + return xType && yType && xType->IsEquivalentTo(*yType); + } + } + return false; + } else if (xSym || ySym) { + return false; + } + // Neither expression is an integer constant or a whole symbol. + if (x == y) { + return true; + } else { + return std::nullopt; // not sure + } +} + } // namespace Fortran::evaluate namespace Fortran::semantics { @@ -1788,4 +1866,23 @@ common::IgnoreTKRSet GetIgnoreTKR(const Symbol &symbol) { return result; } +std::optional GetDummyArgumentNumber(const Symbol *symbol) { + if (symbol) { + if (IsDummy(*symbol)) { + if (const Symbol * subpSym{symbol->owner().symbol()}) { + if (const auto *subp{subpSym->detailsIf()}) { + int j{0}; + for (const Symbol *dummy : subp->dummyArgs()) { + if (dummy == symbol) { + return j; + } + ++j; + } + } + } + } + } + return std::nullopt; +} + } // namespace Fortran::semantics diff --git a/flang/lib/Semantics/check-call.cpp b/flang/lib/Semantics/check-call.cpp index f28a44e27ad6..ca9fffaeeaf2 100644 --- a/flang/lib/Semantics/check-call.cpp +++ b/flang/lib/Semantics/check-call.cpp @@ -971,7 +971,9 @@ static void CheckProcedureArg(evaluate::ActualArgument &arg, } if (interface.HasExplicitInterface()) { std::string whyNot; - if (!interface.IsCompatibleWith(argInterface, &whyNot)) { + std::optional warning; + if (!interface.IsCompatibleWith(argInterface, &whyNot, + /*specificIntrinsic=*/nullptr, &warning)) { // 15.5.2.9(1): Explicit interfaces must match if (argInterface.HasExplicitInterface()) { messages.Say( @@ -988,6 +990,11 @@ static void CheckProcedureArg(evaluate::ActualArgument &arg, "Actual procedure argument has an implicit interface which is not known to be compatible with %s which has an explicit interface"_warn_en_US, dummyName); } + } else if (warning && + context.ShouldWarn(common::UsageWarning::ProcDummyArgShapes)) { + messages.Say( + "Actual procedure argument has possible interface incompatibility with %s: %s"_warn_en_US, + dummyName, std::move(*warning)); } } else { // 15.5.2.9(2,3) if (interface.IsSubroutine() && argInterface.IsFunction()) { @@ -1351,6 +1358,7 @@ static void CheckAssociated(evaluate::ActualArguments &arguments, *targetExpr, foldingContext)}) { bool isCall{!!UnwrapProcedureRef(*targetExpr)}; std::string whyNot; + std::optional warning; const auto *targetProcDesignator{ evaluate::UnwrapExpr( *targetExpr)}; @@ -1358,9 +1366,17 @@ static void CheckAssociated(evaluate::ActualArguments &arguments, targetProcDesignator ? targetProcDesignator->GetSpecificIntrinsic() : nullptr}; - if (std::optional msg{ - CheckProcCompatibility(isCall, pointerProc, - &*targetProc, specificIntrinsic, whyNot)}) { + std::optional msg{ + CheckProcCompatibility(isCall, pointerProc, &*targetProc, + specificIntrinsic, whyNot, warning)}; + if (!msg && warning && + semanticsContext.ShouldWarn( + common::UsageWarning::ProcDummyArgShapes)) { + msg = + "Procedures '%s' and '%s' may not be completely compatible: %s"_warn_en_US; + whyNot = std::move(*warning); + } + if (msg) { msg->set_severity(parser::Severity::Warning); messages.Say(std::move(*msg), "pointer '" + pointerExpr->AsFortran() + "'", diff --git a/flang/lib/Semantics/pointer-assignment.cpp b/flang/lib/Semantics/pointer-assignment.cpp index 0dcaa4e3f2a3..4c293e85cf9d 100644 --- a/flang/lib/Semantics/pointer-assignment.cpp +++ b/flang/lib/Semantics/pointer-assignment.cpp @@ -359,12 +359,18 @@ bool PointerAssignmentChecker::Check(parser::CharBlock rhsName, bool isCall, const Procedure *rhsProcedure, const evaluate::SpecificIntrinsic *specific) { std::string whyNot; + std::optional warning; CharacterizeProcedure(); if (std::optional msg{evaluate::CheckProcCompatibility( - isCall, procedure_, rhsProcedure, specific, whyNot)}) { + isCall, procedure_, rhsProcedure, specific, whyNot, warning)}) { Say(std::move(*msg), description_, rhsName, whyNot); return false; } + if (context_.ShouldWarn(common::UsageWarning::ProcDummyArgShapes) && + warning) { + Say("%s and %s may not be completely compatible procedures: %s"_warn_en_US, + description_, rhsName, std::move(*warning)); + } return true; } diff --git a/flang/test/Semantics/argshape01.f90 b/flang/test/Semantics/argshape01.f90 index b57641a1b898..19cca1ca4620 100644 --- a/flang/test/Semantics/argshape01.f90 +++ b/flang/test/Semantics/argshape01.f90 @@ -1,6 +1,7 @@ -! RUN: %python %S/test_errors.py %s %flang_fc1 +! RUN: %python %S/test_errors.py %s %flang_fc1 -pedantic ! Detect incompatible argument shapes module m + integer :: ha = 1 contains subroutine s1(a) real, intent(in) :: a(2,3) @@ -17,6 +18,32 @@ module m subroutine s5(a) real, intent(in) :: a(..) end + subroutine s6(a,n,m) + integer, intent(in) :: n, m + real, intent(in) :: a(n, m) + end + subroutine s6b(a,nn,mm) + integer, intent(in) :: nn, mm + real, intent(in) :: a(nn, mm) + end + subroutine s7(a,n,m) + integer, intent(in) :: n, m + real, intent(in) :: a(m, n) + end + subroutine s8(a,n,m) + integer, intent(in) :: n, m + real, intent(in) :: a(n+1,m+1) + end + subroutine s8b(a,n,m) + integer, intent(in) :: n, m + real, intent(in) :: a(n-1,m+2) + end + subroutine s9(a) + real, intent(in) :: a(ha,ha) + end + subroutine s9b(a) + real, intent(in) :: a(ha,ha) + end subroutine s1c(s) procedure(s1) :: s end @@ -32,6 +59,18 @@ module m subroutine s5c(s) procedure(s5) :: s end + subroutine s6c(s) + procedure(s6) :: s + end + subroutine s7c(s) + procedure(s7) :: s + end + subroutine s8c(s) + procedure(s8) :: s + end + subroutine s9c(s) + procedure(s9) :: s + end end program main @@ -41,27 +80,54 @@ program main procedure(s3), pointer :: ps3 procedure(s4), pointer :: ps4 procedure(s5), pointer :: ps5 + procedure(s6), pointer :: ps6 + procedure(s7), pointer :: ps7 + procedure(s8), pointer :: ps8 + procedure(s9), pointer :: ps9 call s1c(s1) !ERROR: Actual procedure argument has interface incompatible with dummy argument 's=': incompatible dummy argument #1: incompatible dummy data object shapes call s1c(s2) !ERROR: Actual procedure argument has interface incompatible with dummy argument 's=': incompatible dummy argument #1: incompatible dummy data object shapes call s1c(s3) - !ERROR: Actual procedure argument has interface incompatible with dummy argument 's=': incompatible dummy argument #1: incompatible dummy data object attributes + !ERROR: Actual procedure argument has interface incompatible with dummy argument 's=': incompatible dummy argument #1: incompatible dummy data object shapes call s1c(s4) !ERROR: Actual procedure argument has interface incompatible with dummy argument 's=': incompatible dummy argument #1: incompatible dummy data object shapes call s1c(s5) + !ERROR: Actual procedure argument has interface incompatible with dummy argument 's=': distinct numbers of dummy arguments + call s1c(s6) !ERROR: Actual procedure argument has interface incompatible with dummy argument 's=': incompatible dummy argument #1: incompatible dummy data object shapes call s2c(s1) call s2c(s2) + call s6c(s6) + call s6c(s6b) + !ERROR: Actual procedure argument has interface incompatible with dummy argument 's=': incompatible dummy argument #1: incompatible dummy data object shapes + call s6c(s7) + !WARNING: Actual procedure argument has interface incompatible with dummy argument 's=': incompatible dummy argument #1: incompatible dummy data object shapes + call s6c(s8) + !ERROR: Actual procedure argument has interface incompatible with dummy argument 's=': incompatible dummy argument #1: incompatible dummy data object shapes + call s7c(s6) + !ERROR: Actual procedure argument has interface incompatible with dummy argument 's=': incompatible dummy argument #1: incompatible dummy data object shapes + call s7c(s8) + !ERROR: Actual procedure argument has interface incompatible with dummy argument 's=': incompatible dummy argument #1: incompatible dummy data object shapes + call s8c(s6) + !ERROR: Actual procedure argument has interface incompatible with dummy argument 's=': incompatible dummy argument #1: incompatible dummy data object shapes + call s8c(s7) + call s8c(s8) + !WARNING: Actual procedure argument has possible interface incompatibility with dummy argument 's=': possibly incompatible dummy argument #1: distinct dummy data object shapes + call s8c(s8b) + call s9c(s9) + call s9c(s9b) ps1 => s1 !ERROR: Procedure pointer 'ps1' associated with incompatible procedure designator 's2': incompatible dummy argument #1: incompatible dummy data object shapes ps1 => s2 !ERROR: Procedure pointer 'ps1' associated with incompatible procedure designator 's3': incompatible dummy argument #1: incompatible dummy data object shapes ps1 => s3 - !ERROR: Procedure pointer 'ps1' associated with incompatible procedure designator 's4': incompatible dummy argument #1: incompatible dummy data object attributes + !ERROR: Procedure pointer 'ps1' associated with incompatible procedure designator 's4': incompatible dummy argument #1: incompatible dummy data object shapes ps1 => s4 !ERROR: Procedure pointer 'ps1' associated with incompatible procedure designator 's5': incompatible dummy argument #1: incompatible dummy data object shapes ps1 => s5 + !ERROR: Procedure pointer 'ps1' associated with incompatible procedure designator 's6': distinct numbers of dummy arguments + ps1 => s6 !ERROR: Procedure pointer 'ps2' associated with incompatible procedure designator 's1': incompatible dummy argument #1: incompatible dummy data object shapes ps2 => s1 ps2 => s2 @@ -70,11 +136,28 @@ program main call s1c(ps2) !ERROR: Actual procedure argument has interface incompatible with dummy argument 's=': incompatible dummy argument #1: incompatible dummy data object shapes call s1c(ps3) - !ERROR: Actual procedure argument has interface incompatible with dummy argument 's=': incompatible dummy argument #1: incompatible dummy data object attributes + !ERROR: Actual procedure argument has interface incompatible with dummy argument 's=': incompatible dummy argument #1: incompatible dummy data object shapes call s1c(ps4) !ERROR: Actual procedure argument has interface incompatible with dummy argument 's=': incompatible dummy argument #1: incompatible dummy data object shapes call s1c(ps5) !ERROR: Actual procedure argument has interface incompatible with dummy argument 's=': incompatible dummy argument #1: incompatible dummy data object shapes call s2c(ps1) call s2c(ps2) + ps6 => s6 + ps6 => s6b + !ERROR: Procedure pointer 'ps6' associated with incompatible procedure designator 's7': incompatible dummy argument #1: incompatible dummy data object shapes + ps6 => s7 + !ERROR: Procedure pointer 'ps6' associated with incompatible procedure designator 's8': incompatible dummy argument #1: incompatible dummy data object shapes + ps6 => s8 + !ERROR: Procedure pointer 'ps7' associated with incompatible procedure designator 's6': incompatible dummy argument #1: incompatible dummy data object shapes + ps7 => s6 + !ERROR: Procedure pointer 'ps7' associated with incompatible procedure designator 's8': incompatible dummy argument #1: incompatible dummy data object shapes + ps7 => s8 + ps8 => s8 + !WARNING: pointer 'ps8' and s8b may not be completely compatible procedures: possibly incompatible dummy argument #1: distinct dummy data object shapes + ps8 => s8b + !ERROR: Procedure pointer 'ps8' associated with incompatible procedure designator 's6': incompatible dummy argument #1: incompatible dummy data object shapes + ps8 => s6 + !WARNING: Procedure pointer 'ps8' associated with incompatible procedure designator 's7': incompatible dummy argument #1: incompatible dummy data object shapes + ps8 => s7 end -- GitLab From 248446980317dccadd5ecdf7d2831942baaff4ab Mon Sep 17 00:00:00 2001 From: Eduard Zingerman Date: Thu, 30 Nov 2023 22:14:52 +0200 Subject: [PATCH 034/699] Revert "[BPF] Attribute preserve_static_offset for structs" This reverts commit cb13e9286b6d4e384b5d4203e853d44e2eff0f0f. Buildbot reports MSAN failures in tests added in this commit: https://lab.llvm.org/buildbot/#/builders/5/builds/38806 Failing tests: LLVM :: CodeGen/BPF/preserve-static-offset/load-arr-pai.ll LLVM :: CodeGen/BPF/preserve-static-offset/load-ptr-pai.ll LLVM :: CodeGen/BPF/preserve-static-offset/load-struct-pai.ll LLVM :: CodeGen/BPF/preserve-static-offset/load-union-pai.ll LLVM :: CodeGen/BPF/preserve-static-offset/store-pai.ll --- clang/include/clang/Basic/Attr.td | 8 - clang/include/clang/Basic/AttrDocs.td | 37 - clang/lib/CodeGen/CGExpr.cpp | 34 - clang/lib/Sema/SemaDeclAttr.cpp | 3 - .../CodeGen/bpf-preserve-static-offset-arr.c | 33 - .../bpf-preserve-static-offset-bitfield.c | 31 - .../bpf-preserve-static-offset-lvalue.c | 28 - .../bpf-preserve-static-offset-non-bpf.c | 18 - .../CodeGen/bpf-preserve-static-offset-pai.c | 29 - ...a-attribute-supported-attributes-list.test | 1 - ...attr-preserve-static-offset-warns-nonbpf.c | 6 - .../bpf-attr-preserve-static-offset-warns.c | 23 - .../Sema/bpf-attr-preserve-static-offset.c | 27 - llvm/include/llvm/IR/Intrinsics.td | 4 - llvm/include/llvm/IR/IntrinsicsBPF.td | 39 - llvm/lib/Target/BPF/BPF.h | 19 - .../Target/BPF/BPFAbstractMemberAccess.cpp | 77 +- llvm/lib/Target/BPF/BPFCORE.h | 4 - llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp | 56 -- .../Target/BPF/BPFPreserveStaticOffset.cpp | 680 ------------------ llvm/lib/Target/BPF/BPFTargetMachine.cpp | 11 - llvm/lib/Target/BPF/CMakeLists.txt | 1 - .../BPF/preserve-static-offset/load-align.ll | 66 -- .../preserve-static-offset/load-arr-pai.ll | 93 --- .../BPF/preserve-static-offset/load-atomic.ll | 66 -- .../preserve-static-offset/load-chain-2.ll | 82 --- .../preserve-static-offset/load-chain-oob.ll | 73 -- .../load-chain-u8-oob.ll | 74 -- .../load-chain-u8-type-mismatch.ll | 73 -- .../preserve-static-offset/load-chain-u8.ll | 71 -- .../BPF/preserve-static-offset/load-chain.ll | 68 -- .../BPF/preserve-static-offset/load-inline.ll | 85 --- .../preserve-static-offset/load-non-const.ll | 75 -- .../preserve-static-offset/load-ptr-pai.ll | 114 --- .../BPF/preserve-static-offset/load-simple.ll | 71 -- .../preserve-static-offset/load-struct-pai.ll | 105 --- .../preserve-static-offset/load-undo-align.ll | 67 -- .../load-undo-chain-oob.ll | 74 -- .../load-undo-chain-u8.ll | 68 -- .../preserve-static-offset/load-undo-chain.ll | 73 -- .../load-undo-simple.ll | 65 -- .../load-undo-volatile.ll | 64 -- .../preserve-static-offset/load-union-pai.ll | 110 --- .../load-unroll-inline.ll | 108 --- .../BPF/preserve-static-offset/load-unroll.ll | 95 --- .../preserve-static-offset/load-volatile.ll | 62 -- .../BPF/preserve-static-offset/load-zero.ll | 57 -- .../BPF/preserve-static-offset/store-align.ll | 59 -- .../preserve-static-offset/store-atomic.ll | 60 -- .../preserve-static-offset/store-chain-2.ll | 77 -- .../preserve-static-offset/store-chain-oob.ll | 67 -- .../store-chain-u8-oob.ll | 67 -- .../preserve-static-offset/store-chain-u8.ll | 68 -- .../BPF/preserve-static-offset/store-chain.ll | 64 -- .../BPF/preserve-static-offset/store-pai.ll | 136 ---- .../preserve-static-offset/store-simple.ll | 60 -- .../store-undo-align.ll | 62 -- .../store-undo-chain-oob.ll | 67 -- .../store-undo-chain-u8.ll | 62 -- .../store-undo-chain.ll | 68 -- .../store-undo-simple.ll | 61 -- .../store-undo-volatile.ll | 61 -- .../store-unroll-inline.ll | 104 --- .../preserve-static-offset/store-volatile.ll | 56 -- .../BPF/preserve-static-offset/store-zero.ll | 51 -- 65 files changed, 35 insertions(+), 4343 deletions(-) delete mode 100644 clang/test/CodeGen/bpf-preserve-static-offset-arr.c delete mode 100644 clang/test/CodeGen/bpf-preserve-static-offset-bitfield.c delete mode 100644 clang/test/CodeGen/bpf-preserve-static-offset-lvalue.c delete mode 100644 clang/test/CodeGen/bpf-preserve-static-offset-non-bpf.c delete mode 100644 clang/test/CodeGen/bpf-preserve-static-offset-pai.c delete mode 100644 clang/test/Sema/bpf-attr-preserve-static-offset-warns-nonbpf.c delete mode 100644 clang/test/Sema/bpf-attr-preserve-static-offset-warns.c delete mode 100644 clang/test/Sema/bpf-attr-preserve-static-offset.c delete mode 100644 llvm/lib/Target/BPF/BPFPreserveStaticOffset.cpp delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-align.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-arr-pai.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-atomic.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-2.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-oob.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8-oob.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8-type-mismatch.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-chain.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-inline.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-non-const.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-ptr-pai.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-simple.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-struct-pai.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-align.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain-oob.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain-u8.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-simple.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-volatile.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-union-pai.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-unroll-inline.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-unroll.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-volatile.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-zero.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-align.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-atomic.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-2.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-oob.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-u8-oob.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-u8.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-chain.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-pai.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-simple.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-align.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain-oob.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain-u8.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-simple.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-volatile.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-unroll-inline.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-volatile.ll delete mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-zero.ll diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td index 121ed203829c..1800f584c7e1 100644 --- a/clang/include/clang/Basic/Attr.td +++ b/clang/include/clang/Basic/Attr.td @@ -2024,14 +2024,6 @@ def BPFPreserveAccessIndex : InheritableAttr, let LangOpts = [COnly]; } -def BPFPreserveStaticOffset : InheritableAttr, - TargetSpecificAttr { - let Spellings = [Clang<"preserve_static_offset">]; - let Subjects = SubjectList<[Record], ErrorDiag>; - let Documentation = [BPFPreserveStaticOffsetDocs]; - let LangOpts = [COnly]; -} - def BTFDeclTag : InheritableAttr { let Spellings = [Clang<"btf_decl_tag">]; let Args = [StringArgument<"BTFDeclTag">]; diff --git a/clang/include/clang/Basic/AttrDocs.td b/clang/include/clang/Basic/AttrDocs.td index dafc811c5225..f2c4eb51b443 100644 --- a/clang/include/clang/Basic/AttrDocs.td +++ b/clang/include/clang/Basic/AttrDocs.td @@ -2199,43 +2199,6 @@ preserving struct or union member access debuginfo indices of this struct or union, similar to clang ``__builtin_preserve_access_index()``. }]; } - -def BPFPreserveStaticOffsetDocs : Documentation { - let Category = DocCatFunction; - let Content = [{ -Clang supports the ``__attribute__((preserve_static_offset))`` -attribute for the BPF target. This attribute may be attached to a -struct or union declaration. Reading or writing fields of types having -such annotation is guaranteed to generate LDX/ST/STX instruction with -offset corresponding to the field. - -For example: - -.. code-block:: c - - struct foo { - int a; - int b; - }; - - struct bar { - int a; - struct foo b; - } __attribute__((preserve_static_offset)); - - void buz(struct bar *g) { - g->b.a = 42; - } - -The assignment to ``g``'s field would produce an ST instruction with -offset 8: ``*(u32)(r1 + 8) = 42;``. - -Without this attribute generated instructions might be different, -depending on optimizations behavior. E.g. the example above could be -rewritten as ``r1 += 8; *(u32)(r1 + 0) = 42;``. - }]; -} - def BTFDeclTagDocs : Documentation { let Category = DocCatFunction; let Content = [{ diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp index 69cf7f76be9a..9d1f1a58f9e1 100644 --- a/clang/lib/CodeGen/CGExpr.cpp +++ b/clang/lib/CodeGen/CGExpr.cpp @@ -3833,33 +3833,6 @@ static QualType getFixedSizeElementType(const ASTContext &ctx, return eltType; } -static bool hasBPFPreserveStaticOffset(const RecordDecl *D) { - return D && D->hasAttr(); -} - -static bool hasBPFPreserveStaticOffset(const Expr *E) { - if (!E) - return false; - QualType PointeeType = E->getType()->getPointeeType(); - if (PointeeType.isNull()) - return false; - if (const auto *BaseDecl = PointeeType->getAsRecordDecl()) - return hasBPFPreserveStaticOffset(BaseDecl); - return false; -} - -// Wraps Addr with a call to llvm.preserve.static.offset intrinsic. -static Address wrapWithBPFPreserveStaticOffset(CodeGenFunction &CGF, - Address &Addr) { - if (!CGF.getTarget().getTriple().isBPF()) - return Addr; - - llvm::Function *Fn = - CGF.CGM.getIntrinsic(llvm::Intrinsic::preserve_static_offset); - llvm::CallInst *Call = CGF.Builder.CreateCall(Fn, {Addr.getPointer()}); - return Address(Call, Addr.getElementType(), Addr.getAlignment()); -} - /// Given an array base, check whether its member access belongs to a record /// with preserve_access_index attribute or not. static bool IsPreserveAIArrayBase(CodeGenFunction &CGF, const Expr *ArrayBase) { @@ -3921,9 +3894,6 @@ static Address emitArraySubscriptGEP(CodeGenFunction &CGF, Address addr, CharUnits eltAlign = getArrayElementAlign(addr.getAlignment(), indices.back(), eltSize); - if (hasBPFPreserveStaticOffset(Base)) - addr = wrapWithBPFPreserveStaticOffset(CGF, addr); - llvm::Value *eltPtr; auto LastIndex = dyn_cast(indices.back()); if (!LastIndex || @@ -4552,8 +4522,6 @@ LValue CodeGenFunction::EmitLValueForField(LValue base, Address Addr = base.getAddress(*this); unsigned Idx = RL.getLLVMFieldNo(field); const RecordDecl *rec = field->getParent(); - if (hasBPFPreserveStaticOffset(rec)) - Addr = wrapWithBPFPreserveStaticOffset(*this, Addr); if (!UseVolatile) { if (!IsInPreservedAIRegion && (!getDebugInfo() || !rec->hasAttr())) { @@ -4626,8 +4594,6 @@ LValue CodeGenFunction::EmitLValueForField(LValue base, } Address addr = base.getAddress(*this); - if (hasBPFPreserveStaticOffset(rec)) - addr = wrapWithBPFPreserveStaticOffset(*this, addr); if (auto *ClassDef = dyn_cast(rec)) { if (CGM.getCodeGenOpts().StrictVTablePointers && ClassDef->isDynamicClass()) { diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp index a345978bb870..87c78d742d0f 100644 --- a/clang/lib/Sema/SemaDeclAttr.cpp +++ b/clang/lib/Sema/SemaDeclAttr.cpp @@ -9036,9 +9036,6 @@ ProcessDeclAttribute(Sema &S, Scope *scope, Decl *D, const ParsedAttr &AL, case ParsedAttr::AT_BPFPreserveAccessIndex: handleBPFPreserveAccessIndexAttr(S, D, AL); break; - case ParsedAttr::AT_BPFPreserveStaticOffset: - handleSimpleAttribute(S, D, AL); - break; case ParsedAttr::AT_BTFDeclTag: handleBTFDeclTagAttr(S, D, AL); break; diff --git a/clang/test/CodeGen/bpf-preserve-static-offset-arr.c b/clang/test/CodeGen/bpf-preserve-static-offset-arr.c deleted file mode 100644 index 295bd2919fc6..000000000000 --- a/clang/test/CodeGen/bpf-preserve-static-offset-arr.c +++ /dev/null @@ -1,33 +0,0 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 -// REQUIRES: bpf-registered-target -// RUN: %clang -cc1 -triple bpf -disable-llvm-passes -S -emit-llvm -o - %s \ -// RUN: | FileCheck %s - -// Check that call to preserve.static.offset is generated when array -// member of a struct marked with __attribute__((preserve_static_offset)) -// is accessed. - -#define __ctx __attribute__((preserve_static_offset)) - -struct foo { - struct { - int a; - } b[7]; -} __ctx; - -// CHECK-LABEL: define dso_local i32 @arr_access -// CHECK-SAME: (ptr noundef [[P:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8 -// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 8 -// CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.preserve.static.offset(ptr [[TMP0]]) -// CHECK-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_FOO:%.*]], ptr [[TMP1]], i32 0, i32 0 -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [7 x %struct.anon], ptr [[B]], i64 0, i64 2 -// CHECK-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[ARRAYIDX]], i32 0, i32 0 -// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 -// CHECK-NEXT: ret i32 [[TMP2]] -// -int arr_access(struct foo *p) { - return p->b[2].a; -} diff --git a/clang/test/CodeGen/bpf-preserve-static-offset-bitfield.c b/clang/test/CodeGen/bpf-preserve-static-offset-bitfield.c deleted file mode 100644 index e4fd2eeeeb66..000000000000 --- a/clang/test/CodeGen/bpf-preserve-static-offset-bitfield.c +++ /dev/null @@ -1,31 +0,0 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 -// REQUIRES: bpf-registered-target -// RUN: %clang -cc1 -triple bpf -disable-llvm-passes -S -emit-llvm -o - %s \ -// RUN: | FileCheck %s - -// Check that call to preserve.static.offset is generated when bitfield -// from a struct marked with __attribute__((preserve_static_offset)) is -// accessed. - -#define __ctx __attribute__((preserve_static_offset)) - -struct foo { - unsigned a:1; -} __ctx; - -// CHECK-LABEL: define dso_local void @lvalue_bitfield -// CHECK-SAME: (ptr noundef [[P:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8 -// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 8 -// CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.preserve.static.offset(ptr [[TMP0]]) -// CHECK-NEXT: [[BF_LOAD:%.*]] = load i8, ptr [[TMP1]], align 4 -// CHECK-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -2 -// CHECK-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 1 -// CHECK-NEXT: store i8 [[BF_SET]], ptr [[TMP1]], align 4 -// CHECK-NEXT: ret void -// -void lvalue_bitfield(struct foo *p) { - p->a = 1; -} diff --git a/clang/test/CodeGen/bpf-preserve-static-offset-lvalue.c b/clang/test/CodeGen/bpf-preserve-static-offset-lvalue.c deleted file mode 100644 index 4f0c359366f5..000000000000 --- a/clang/test/CodeGen/bpf-preserve-static-offset-lvalue.c +++ /dev/null @@ -1,28 +0,0 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 -// REQUIRES: bpf-registered-target -// RUN: %clang -cc1 -triple bpf -disable-llvm-passes -S -emit-llvm -o - %s \ -// RUN: | FileCheck %s - -// Check that call to preserve.static.offset is generated when field of -// a struct marked with __attribute__((preserve_static_offset)) is accessed. - -#define __ctx __attribute__((preserve_static_offset)) - -struct foo { - int a; -} __ctx; - -// CHECK-LABEL: define dso_local void @lvalue -// CHECK-SAME: (ptr noundef [[P:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8 -// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 8 -// CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.preserve.static.offset(ptr [[TMP0]]) -// CHECK-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_FOO:%.*]], ptr [[TMP1]], i32 0, i32 0 -// CHECK-NEXT: store i32 42, ptr [[A]], align 4 -// CHECK-NEXT: ret void -// -void lvalue(struct foo *p) { - p->a = 42; -} diff --git a/clang/test/CodeGen/bpf-preserve-static-offset-non-bpf.c b/clang/test/CodeGen/bpf-preserve-static-offset-non-bpf.c deleted file mode 100644 index 3fe8d2517fe3..000000000000 --- a/clang/test/CodeGen/bpf-preserve-static-offset-non-bpf.c +++ /dev/null @@ -1,18 +0,0 @@ -// REQUIRES: x86-registered-target -// RUN: %clang -cc1 -triple x86_64 -disable-llvm-passes -S -emit-llvm -o - %s \ -// RUN: | FileCheck %s - -// Verify that __attribute__((preserve_static_offset)) -// has no effect for non-BPF target. - -#define __ctx __attribute__((preserve_static_offset)) - -struct foo { - int a; -} __ctx; - -// CHECK-NOT: @llvm_preserve_static_offset - -int bar(struct foo *p) { - return p->a; -} diff --git a/clang/test/CodeGen/bpf-preserve-static-offset-pai.c b/clang/test/CodeGen/bpf-preserve-static-offset-pai.c deleted file mode 100644 index df1f33b1a664..000000000000 --- a/clang/test/CodeGen/bpf-preserve-static-offset-pai.c +++ /dev/null @@ -1,29 +0,0 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 -// REQUIRES: bpf-registered-target -// RUN: %clang -cc1 -triple bpf -disable-llvm-passes -S -emit-llvm -o - %s \ -// RUN: | FileCheck %s - -// Verify that preserve_static_offset does not interfere with -// preserve_access_index at IR generation stage. - -#define __ctx __attribute__((preserve_static_offset)) -#define __pai __attribute__((preserve_access_index)) - -struct foo { - int a; -} __ctx __pai; - -// CHECK-LABEL: define dso_local i32 @bar -// CHECK-SAME: (ptr noundef [[P:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8 -// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 8 -// CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.preserve.static.offset(ptr [[TMP0]]) -// CHECK-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_FOO:%.*]], ptr [[TMP1]], i32 0, i32 0 -// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 -// CHECK-NEXT: ret i32 [[TMP2]] -// -int bar(struct foo *p) { - return p->a; -} diff --git a/clang/test/Misc/pragma-attribute-supported-attributes-list.test b/clang/test/Misc/pragma-attribute-supported-attributes-list.test index 707fc8875089..dd91f4f88ad6 100644 --- a/clang/test/Misc/pragma-attribute-supported-attributes-list.test +++ b/clang/test/Misc/pragma-attribute-supported-attributes-list.test @@ -23,7 +23,6 @@ // CHECK-NEXT: Availability ((SubjectMatchRule_record, SubjectMatchRule_enum, SubjectMatchRule_enum_constant, SubjectMatchRule_field, SubjectMatchRule_function, SubjectMatchRule_namespace, SubjectMatchRule_objc_category, SubjectMatchRule_objc_implementation, SubjectMatchRule_objc_interface, SubjectMatchRule_objc_method, SubjectMatchRule_objc_property, SubjectMatchRule_objc_protocol, SubjectMatchRule_record, SubjectMatchRule_type_alias, SubjectMatchRule_variable)) // CHECK-NEXT: AvailableOnlyInDefaultEvalMethod (SubjectMatchRule_type_alias) // CHECK-NEXT: BPFPreserveAccessIndex (SubjectMatchRule_record) -// CHECK-NEXT: BPFPreserveStaticOffset (SubjectMatchRule_record) // CHECK-NEXT: BTFDeclTag (SubjectMatchRule_variable, SubjectMatchRule_function, SubjectMatchRule_record, SubjectMatchRule_field, SubjectMatchRule_type_alias) // CHECK-NEXT: BuiltinAlias (SubjectMatchRule_function) // CHECK-NEXT: CFAuditedTransfer (SubjectMatchRule_function) diff --git a/clang/test/Sema/bpf-attr-preserve-static-offset-warns-nonbpf.c b/clang/test/Sema/bpf-attr-preserve-static-offset-warns-nonbpf.c deleted file mode 100644 index d543e6f99952..000000000000 --- a/clang/test/Sema/bpf-attr-preserve-static-offset-warns-nonbpf.c +++ /dev/null @@ -1,6 +0,0 @@ -// RUN: %clang_cc1 -fsyntax-only -verify %s - -#define __pso __attribute__((preserve_static_offset)) - -struct foo { int a; } __pso; // expected-warning{{unknown attribute}} -union quux { int a; } __pso; // expected-warning{{unknown attribute}} diff --git a/clang/test/Sema/bpf-attr-preserve-static-offset-warns.c b/clang/test/Sema/bpf-attr-preserve-static-offset-warns.c deleted file mode 100644 index 1067ebe8f82b..000000000000 --- a/clang/test/Sema/bpf-attr-preserve-static-offset-warns.c +++ /dev/null @@ -1,23 +0,0 @@ -// RUN: %clang_cc1 -fsyntax-only -verify -triple bpf-pc-linux-gnu %s - -#define __pso __attribute__((preserve_static_offset)) - -// These are correct usages. -struct foo { int a; } __pso; -union quux { int a; } __pso; -struct doug { int a; } __pso __attribute__((packed)); - -// Rest are incorrect usages. -typedef int bar __pso; // expected-error{{attribute only applies to}} -struct goo { - int a __pso; // expected-error{{attribute only applies to}} -}; -int g __pso; // expected-error{{attribute only applies to}} -__pso void ffunc1(void); // expected-error{{attribute only applies to}} -void ffunc2(int a __pso); // expected-error{{attribute only applies to}} -void ffunc3(void) { - int a __pso; // expected-error{{attribute only applies to}} -} - -struct buz { int a; } __attribute__((preserve_static_offset("hello"))); // \ - expected-error{{attribute takes no arguments}} diff --git a/clang/test/Sema/bpf-attr-preserve-static-offset.c b/clang/test/Sema/bpf-attr-preserve-static-offset.c deleted file mode 100644 index 5f53469869f3..000000000000 --- a/clang/test/Sema/bpf-attr-preserve-static-offset.c +++ /dev/null @@ -1,27 +0,0 @@ -// RUN: %clang_cc1 -fsyntax-only -ast-dump -triple bpf-pc-linux-gnu %s | FileCheck %s - -// The 'preserve_static_offset' attribute should be propagated to -// inline declarations (foo's 'b', 'bb', 'c' but not 'd'). -// -// CHECK: RecordDecl {{.*}} struct foo definition -// CHECK-NEXT: BPFPreserveStaticOffsetAttr -// CHECK-NEXT: FieldDecl {{.*}} a -// CHECK-NEXT: RecordDecl {{.*}} struct definition -// CHECK-NEXT: FieldDecl {{.*}} aa -// CHECK-NEXT: FieldDecl {{.*}} b -// CHECK-NEXT: RecordDecl {{.*}} union bar definition -// CHECK-NEXT: BPFPreserveStaticOffsetAttr -// CHECK-NEXT: FieldDecl {{.*}} a -// CHECK-NEXT: FieldDecl {{.*}} b - -struct foo { - int a; - struct { - int aa; - } b; -} __attribute__((preserve_static_offset)); - -union bar { - int a; - long b; -} __attribute__((preserve_static_offset)); diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td index b54c697296b2..060e964f77bf 100644 --- a/llvm/include/llvm/IR/Intrinsics.td +++ b/llvm/include/llvm/IR/Intrinsics.td @@ -2469,10 +2469,6 @@ def int_preserve_struct_access_index : DefaultAttrsIntrinsic<[llvm_anyptr_ty], [IntrNoMem, ImmArg>, ImmArg>]>; -def int_preserve_static_offset : DefaultAttrsIntrinsic<[llvm_ptr_ty], - [llvm_ptr_ty], - [IntrNoMem, IntrSpeculatable, - ReadNone >]>; //===------------ Intrinsics to perform common vector shuffles ------------===// diff --git a/llvm/include/llvm/IR/IntrinsicsBPF.td b/llvm/include/llvm/IR/IntrinsicsBPF.td index c7ec0916f1d1..8916b60d2be3 100644 --- a/llvm/include/llvm/IR/IntrinsicsBPF.td +++ b/llvm/include/llvm/IR/IntrinsicsBPF.td @@ -37,43 +37,4 @@ let TargetPrefix = "bpf" in { // All intrinsics start with "llvm.bpf." def int_bpf_compare : ClangBuiltin<"__builtin_bpf_compare">, Intrinsic<[llvm_i1_ty], [llvm_i32_ty, llvm_anyint_ty, llvm_anyint_ty], [IntrNoMem]>; - def int_bpf_getelementptr_and_load : ClangBuiltin<"__builtin_bpf_getelementptr_and_load">, - Intrinsic<[llvm_any_ty], - [llvm_ptr_ty, // base ptr for getelementptr - llvm_i1_ty, // volatile - llvm_i8_ty, // atomic order - llvm_i8_ty, // synscope id - llvm_i8_ty, // alignment - llvm_i1_ty, // inbounds - llvm_vararg_ty], // indices for getelementptr insn - [IntrNoCallback, - IntrNoFree, - IntrWillReturn, - NoCapture >, - ImmArg >, // volatile - ImmArg >, // atomic order - ImmArg >, // synscope id - ImmArg >, // alignment - ImmArg >, // inbounds - ]>; - def int_bpf_getelementptr_and_store : ClangBuiltin<"__builtin_bpf_getelementptr_and_store">, - Intrinsic<[], - [llvm_any_ty, // value to store - llvm_ptr_ty, // base ptr for getelementptr - llvm_i1_ty, // volatile - llvm_i8_ty, // atomic order - llvm_i8_ty, // syncscope id - llvm_i8_ty, // alignment - llvm_i1_ty, // inbounds - llvm_vararg_ty], // indexes for getelementptr insn - [IntrNoCallback, - IntrNoFree, - IntrWillReturn, - NoCapture >, - ImmArg >, // volatile - ImmArg >, // atomic order - ImmArg >, // syncscope id - ImmArg >, // alignment - ImmArg >, // inbounds - ]>; } diff --git a/llvm/lib/Target/BPF/BPF.h b/llvm/lib/Target/BPF/BPF.h index 436cd62c2581..1f539d3270b7 100644 --- a/llvm/lib/Target/BPF/BPF.h +++ b/llvm/lib/Target/BPF/BPF.h @@ -10,7 +10,6 @@ #define LLVM_LIB_TARGET_BPF_BPF_H #include "MCTargetDesc/BPFMCTargetDesc.h" -#include "llvm/IR/Instructions.h" #include "llvm/IR/PassManager.h" #include "llvm/Pass.h" #include "llvm/Target/TargetMachine.h" @@ -63,24 +62,6 @@ class BPFAdjustOptPass : public PassInfoMixin { public: PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM); }; - -class BPFPreserveStaticOffsetPass - : public PassInfoMixin { - bool AllowPartial; - -public: - BPFPreserveStaticOffsetPass(bool AllowPartial) : AllowPartial(AllowPartial) {} - PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); - - static bool isRequired() { return true; } - - static std::pair - reconstructLoad(CallInst *Call); - - static std::pair - reconstructStore(CallInst *Call); -}; - } // namespace llvm #endif diff --git a/llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp b/llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp index 9634c16a30dc..1895d15c1f55 100644 --- a/llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp +++ b/llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp @@ -172,6 +172,8 @@ private: bool IsValidAIChain(const MDNode *ParentMeta, uint32_t ParentAI, const MDNode *ChildMeta); bool removePreserveAccessIndexIntrinsic(Function &F); + void replaceWithGEP(std::vector &CallList, + uint32_t NumOfZerosIndex, uint32_t DIIndex); bool HasPreserveFieldInfoCall(CallInfoStack &CallStack); void GetStorageBitRange(DIDerivedType *MemberTy, Align RecordAlignment, uint32_t &StartBitOffset, uint32_t &EndBitOffset); @@ -183,6 +185,7 @@ private: std::string &AccessKey, MDNode *&BaseMeta); MDNode *computeAccessKey(CallInst *Call, CallInfo &CInfo, std::string &AccessKey, bool &IsInt32Ret); + uint64_t getConstant(const Value *IndexValue); bool transformGEPChain(CallInst *Call, CallInfo &CInfo); }; @@ -323,12 +326,6 @@ static Type *getBaseElementType(const CallInst *Call) { return Call->getParamElementType(0); } -static uint64_t getConstant(const Value *IndexValue) { - const ConstantInt *CV = dyn_cast(IndexValue); - assert(CV); - return CV->getValue().getZExtValue(); -} - /// Check whether a call is a preserve_*_access_index intrinsic call or not. bool BPFAbstractMemberAccess::IsPreserveDIAccessIndexCall(const CallInst *Call, CallInfo &CInfo) { @@ -413,36 +410,26 @@ bool BPFAbstractMemberAccess::IsPreserveDIAccessIndexCall(const CallInst *Call, return false; } -static void replaceWithGEP(CallInst *Call, uint32_t DimensionIndex, - uint32_t GEPIndex) { - uint32_t Dimension = 1; - if (DimensionIndex > 0) - Dimension = getConstant(Call->getArgOperand(DimensionIndex)); - - Constant *Zero = - ConstantInt::get(Type::getInt32Ty(Call->getParent()->getContext()), 0); - SmallVector IdxList; - for (unsigned I = 0; I < Dimension; ++I) - IdxList.push_back(Zero); - IdxList.push_back(Call->getArgOperand(GEPIndex)); - - auto *GEP = GetElementPtrInst::CreateInBounds( - getBaseElementType(Call), Call->getArgOperand(0), IdxList, "", Call); - Call->replaceAllUsesWith(GEP); - Call->eraseFromParent(); -} - -void BPFCoreSharedInfo::removeArrayAccessCall(CallInst *Call) { - replaceWithGEP(Call, 1, 2); -} - -void BPFCoreSharedInfo::removeStructAccessCall(CallInst *Call) { - replaceWithGEP(Call, 0, 1); -} - -void BPFCoreSharedInfo::removeUnionAccessCall(CallInst *Call) { - Call->replaceAllUsesWith(Call->getArgOperand(0)); - Call->eraseFromParent(); +void BPFAbstractMemberAccess::replaceWithGEP(std::vector &CallList, + uint32_t DimensionIndex, + uint32_t GEPIndex) { + for (auto *Call : CallList) { + uint32_t Dimension = 1; + if (DimensionIndex > 0) + Dimension = getConstant(Call->getArgOperand(DimensionIndex)); + + Constant *Zero = + ConstantInt::get(Type::getInt32Ty(Call->getParent()->getContext()), 0); + SmallVector IdxList; + for (unsigned I = 0; I < Dimension; ++I) + IdxList.push_back(Zero); + IdxList.push_back(Call->getArgOperand(GEPIndex)); + + auto *GEP = GetElementPtrInst::CreateInBounds( + getBaseElementType(Call), Call->getArgOperand(0), IdxList, "", Call); + Call->replaceAllUsesWith(GEP); + Call->eraseFromParent(); + } } bool BPFAbstractMemberAccess::removePreserveAccessIndexIntrinsic(Function &F) { @@ -477,12 +464,12 @@ bool BPFAbstractMemberAccess::removePreserveAccessIndexIntrinsic(Function &F) { // . addr = preserve_struct_access_index(base, gep_index, di_index) // is transformed to // addr = GEP(base, 0, gep_index) - for (CallInst *Call : PreserveArrayIndexCalls) - BPFCoreSharedInfo::removeArrayAccessCall(Call); - for (CallInst *Call : PreserveStructIndexCalls) - BPFCoreSharedInfo::removeStructAccessCall(Call); - for (CallInst *Call : PreserveUnionIndexCalls) - BPFCoreSharedInfo::removeUnionAccessCall(Call); + replaceWithGEP(PreserveArrayIndexCalls, 1, 2); + replaceWithGEP(PreserveStructIndexCalls, 0, 1); + for (auto *Call : PreserveUnionIndexCalls) { + Call->replaceAllUsesWith(Call->getArgOperand(0)); + Call->eraseFromParent(); + } return Found; } @@ -647,6 +634,12 @@ void BPFAbstractMemberAccess::collectAICallChains(Function &F) { } } +uint64_t BPFAbstractMemberAccess::getConstant(const Value *IndexValue) { + const ConstantInt *CV = dyn_cast(IndexValue); + assert(CV); + return CV->getValue().getZExtValue(); +} + /// Get the start and the end of storage offset for \p MemberTy. void BPFAbstractMemberAccess::GetStorageBitRange(DIDerivedType *MemberTy, Align RecordAlignment, diff --git a/llvm/lib/Target/BPF/BPFCORE.h b/llvm/lib/Target/BPF/BPFCORE.h index f46a8ef62a7f..9a547a775c96 100644 --- a/llvm/lib/Target/BPF/BPFCORE.h +++ b/llvm/lib/Target/BPF/BPFCORE.h @@ -10,7 +10,6 @@ #define LLVM_LIB_TARGET_BPF_BPFCORE_H #include "llvm/ADT/StringRef.h" -#include "llvm/IR/Instructions.h" namespace llvm { @@ -54,9 +53,6 @@ public: static Instruction *insertPassThrough(Module *M, BasicBlock *BB, Instruction *Input, Instruction *Before); - static void removeArrayAccessCall(CallInst *Call); - static void removeStructAccessCall(CallInst *Call); - static void removeUnionAccessCall(CallInst *Call); }; } // namespace llvm diff --git a/llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp b/llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp index 56c89f61b319..a3616ae7ebab 100644 --- a/llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp +++ b/llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp @@ -12,8 +12,6 @@ // The following are done for IR adjustment: // - remove __builtin_bpf_passthrough builtins. Target independent IR // optimizations are done and those builtins can be removed. -// - remove llvm.bpf.getelementptr.and.load builtins. -// - remove llvm.bpf.getelementptr.and.store builtins. // //===----------------------------------------------------------------------===// @@ -26,7 +24,6 @@ #include "llvm/IR/IRBuilder.h" #include "llvm/IR/Instruction.h" #include "llvm/IR/Instructions.h" -#include "llvm/IR/IntrinsicsBPF.h" #include "llvm/IR/Module.h" #include "llvm/IR/Type.h" #include "llvm/IR/User.h" @@ -54,7 +51,6 @@ private: bool removePassThroughBuiltin(Module &M); bool removeCompareBuiltin(Module &M); bool sinkMinMax(Module &M); - bool removeGEPBuiltins(Module &M); }; } // End anonymous namespace @@ -365,62 +361,10 @@ void BPFCheckAndAdjustIR::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); } -static void unrollGEPLoad(CallInst *Call) { - auto [GEP, Load] = BPFPreserveStaticOffsetPass::reconstructLoad(Call); - GEP->insertBefore(Call); - Load->insertBefore(Call); - Call->replaceAllUsesWith(Load); - Call->eraseFromParent(); -} - -static void unrollGEPStore(CallInst *Call) { - auto [GEP, Store] = BPFPreserveStaticOffsetPass::reconstructStore(Call); - GEP->insertBefore(Call); - Store->insertBefore(Call); - Call->eraseFromParent(); -} - -static bool removeGEPBuiltinsInFunc(Function &F) { - SmallVector GEPLoads; - SmallVector GEPStores; - for (auto &BB : F) - for (auto &Insn : BB) - if (auto *Call = dyn_cast(&Insn)) - if (auto *Called = Call->getCalledFunction()) - switch (Called->getIntrinsicID()) { - case Intrinsic::bpf_getelementptr_and_load: - GEPLoads.push_back(Call); - break; - case Intrinsic::bpf_getelementptr_and_store: - GEPStores.push_back(Call); - break; - } - - if (GEPLoads.empty() && GEPStores.empty()) - return false; - - for_each(GEPLoads, unrollGEPLoad); - for_each(GEPStores, unrollGEPStore); - - return true; -} - -// Rewrites the following builtins: -// - llvm.bpf.getelementptr.and.load -// - llvm.bpf.getelementptr.and.store -// As (load (getelementptr ...)) or (store (getelementptr ...)). -bool BPFCheckAndAdjustIR::removeGEPBuiltins(Module &M) { - bool Changed = false; - for (auto &F : M) - Changed = removeGEPBuiltinsInFunc(F) || Changed; - return Changed; -} - bool BPFCheckAndAdjustIR::adjustIR(Module &M) { bool Changed = removePassThroughBuiltin(M); Changed = removeCompareBuiltin(M) || Changed; Changed = sinkMinMax(M) || Changed; - Changed = removeGEPBuiltins(M) || Changed; return Changed; } diff --git a/llvm/lib/Target/BPF/BPFPreserveStaticOffset.cpp b/llvm/lib/Target/BPF/BPFPreserveStaticOffset.cpp deleted file mode 100644 index e30a10a9f267..000000000000 --- a/llvm/lib/Target/BPF/BPFPreserveStaticOffset.cpp +++ /dev/null @@ -1,680 +0,0 @@ -//===------ BPFPreserveStaticOffset.cpp -----------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// TLDR: replaces llvm.preserve.static.offset + GEP + load / store -// with llvm.bpf.getelementptr.and.load / store -// -// This file implements BPFPreserveStaticOffsetPass transformation. -// This transformation address two BPF verifier specific issues: -// -// (a) Access to the fields of some structural types is allowed only -// using load and store instructions with static immediate offsets. -// -// Examples of such types are `struct __sk_buff` and `struct -// bpf_sock_ops`. This is so because offsets of the fields of -// these structures do not match real offsets in the running -// kernel. During BPF program load LDX and STX instructions -// referring to the fields of these types are rewritten so that -// offsets match real offsets. For this rewrite to happen field -// offsets have to be encoded as immediate operands of the -// instructions. -// -// See kernel/bpf/verifier.c:convert_ctx_access function in the -// Linux kernel source tree for details. -// -// (b) Pointers to context parameters of BPF programs must not be -// modified before access. -// -// During BPF program verification a tag PTR_TO_CTX is tracked for -// register values. In case if register with such tag is modified -// BPF program is not allowed to read or write memory using this -// register. See kernel/bpf/verifier.c:check_mem_access function -// in the Linux kernel source tree for details. -// -// The following sequence of the IR instructions: -// -// %x = getelementptr %ptr, %constant_offset -// %y = load %x -// -// Is translated as a single machine instruction: -// -// LDW %ptr, %constant_offset -// -// In order for cases (a) and (b) to work the sequence %x-%y above has -// to be preserved by the IR passes. -// -// However, several optimization passes might sink `load` instruction -// or hoist `getelementptr` instruction so that the instructions are -// no longer in sequence. Examples of such passes are: -// SimplifyCFGPass, InstCombinePass, GVNPass. -// After such modification the verifier would reject the BPF program. -// -// To avoid this issue the patterns like (load/store (getelementptr ...)) -// are replaced by calls to BPF specific intrinsic functions: -// - llvm.bpf.getelementptr.and.load -// - llvm.bpf.getelementptr.and.store -// -// These calls are lowered back to (load/store (getelementptr ...)) -// by BPFCheckAndAdjustIR pass right before the translation from IR to -// machine instructions. -// -// The transformation is split into the following steps: -// - When IR is generated from AST the calls to intrinsic function -// llvm.preserve.static.offset are inserted. -// - BPFPreserveStaticOffsetPass is executed as early as possible -// with AllowPatial set to true, this handles marked GEP chains -// with constant offsets. -// - BPFPreserveStaticOffsetPass is executed at ScalarOptimizerLateEPCallback -// with AllowPatial set to false, this handles marked GEP chains -// with offsets that became constant after loop unrolling, e.g. -// to handle the following code: -// -// struct context { int x[4]; } __attribute__((preserve_static_offset)); -// -// struct context *ctx = ...; -// #pragma clang loop unroll(full) -// for (int i = 0; i < 4; ++i) -// foo(ctx->x[i]); -// -// The early BPFPreserveStaticOffsetPass run is necessary to allow -// additional GVN / CSE opportunities after functions inlining. -// The relative order of optimization applied to function: -// - early stage (1) -// - ... -// - function inlining (2) -// - ... -// - loop unrolling -// - ... -// - ScalarOptimizerLateEPCallback (3) -// -// When function A is inlined into function B all optimizations for A -// are already done, while some passes remain for B. In case if -// BPFPreserveStaticOffsetPass is done at (3) but not done at (1) -// the code after (2) would contain a mix of -// (load (gep %p)) and (get.and.load %p) usages: -// - the (load (gep %p)) would come from the calling function; -// - the (get.and.load %p) would come from the callee function. -// Thus clobbering CSE / GVN passes done after inlining. - -#include "BPF.h" -#include "BPFCORE.h" -#include "llvm/ADT/SmallPtrSet.h" -#include "llvm/ADT/SmallVector.h" -#include "llvm/IR/Argument.h" -#include "llvm/IR/Attributes.h" -#include "llvm/IR/BasicBlock.h" -#include "llvm/IR/Constants.h" -#include "llvm/IR/DebugInfoMetadata.h" -#include "llvm/IR/DiagnosticInfo.h" -#include "llvm/IR/IRBuilder.h" -#include "llvm/IR/InstIterator.h" -#include "llvm/IR/Instructions.h" -#include "llvm/IR/Intrinsics.h" -#include "llvm/IR/IntrinsicsBPF.h" -#include "llvm/Support/Debug.h" -#include "llvm/Support/ErrorHandling.h" - -#define DEBUG_TYPE "bpf-preserve-static-offset" - -using namespace llvm; - -static const unsigned GepAndLoadFirstIdxArg = 6; -static const unsigned GepAndStoreFirstIdxArg = 7; - -static bool isIntrinsicCall(Value *I, Intrinsic::ID Id) { - if (auto *Call = dyn_cast(I)) - if (Function *Func = Call->getCalledFunction()) - return Func->getIntrinsicID() == Id; - return false; -} - -static bool isPreserveStaticOffsetCall(Value *I) { - return isIntrinsicCall(I, Intrinsic::preserve_static_offset); -} - -static CallInst *isGEPAndLoad(Value *I) { - if (isIntrinsicCall(I, Intrinsic::bpf_getelementptr_and_load)) - return cast(I); - return nullptr; -} - -static CallInst *isGEPAndStore(Value *I) { - if (isIntrinsicCall(I, Intrinsic::bpf_getelementptr_and_store)) - return cast(I); - return nullptr; -} - -template -static DILocation *mergeDILocations(SmallVector &Insns) { - DILocation *Merged = (*Insns.begin())->getDebugLoc(); - for (T *I : Insns) - Merged = DILocation::getMergedLocation(Merged, I->getDebugLoc()); - return Merged; -} - -static CallInst *makeIntrinsicCall(Module *M, - Intrinsic::BPFIntrinsics Intrinsic, - ArrayRef Types, - ArrayRef Args) { - - Function *Fn = Intrinsic::getDeclaration(M, Intrinsic, Types); - return CallInst::Create(Fn, Args); -} - -static void setParamElementType(CallInst *Call, unsigned ArgNo, Type *Type) { - LLVMContext &C = Call->getContext(); - Call->addParamAttr(ArgNo, Attribute::get(C, Attribute::ElementType, Type)); -} - -static void setParamReadNone(CallInst *Call, unsigned ArgNo) { - LLVMContext &C = Call->getContext(); - Call->addParamAttr(ArgNo, Attribute::get(C, Attribute::ReadNone)); -} - -static void setParamReadOnly(CallInst *Call, unsigned ArgNo) { - LLVMContext &C = Call->getContext(); - Call->addParamAttr(ArgNo, Attribute::get(C, Attribute::ReadOnly)); -} - -static void setParamWriteOnly(CallInst *Call, unsigned ArgNo) { - LLVMContext &C = Call->getContext(); - Call->addParamAttr(ArgNo, Attribute::get(C, Attribute::WriteOnly)); -} - -namespace { -struct GEPChainInfo { - bool InBounds; - Type *SourceElementType; - SmallVector Indices; - SmallVector Members; - - GEPChainInfo() { reset(); } - - void reset() { - InBounds = true; - SourceElementType = nullptr; - Indices.clear(); - Members.clear(); - } -}; -} // Anonymous namespace - -template > -static void fillCommonArgs(LLVMContext &C, SmallVector &Args, - GEPChainInfo &GEP, T *Insn) { - Type *Int8Ty = Type::getInt8Ty(C); - Type *Int1Ty = Type::getInt1Ty(C); - // Implementation of Align guarantees that ShiftValue < 64 - unsigned AlignShiftValue = Log2_64(Insn->getAlign().value()); - Args.push_back(GEP.Members[0]->getPointerOperand()); - Args.push_back(ConstantInt::get(Int1Ty, Insn->isVolatile())); - Args.push_back(ConstantInt::get(Int8Ty, (unsigned)Insn->getOrdering())); - Args.push_back(ConstantInt::get(Int8Ty, (unsigned)Insn->getSyncScopeID())); - Args.push_back(ConstantInt::get(Int8Ty, AlignShiftValue)); - Args.push_back(ConstantInt::get(Int1Ty, GEP.InBounds)); - Args.append(GEP.Indices.begin(), GEP.Indices.end()); -} - -static Instruction *makeGEPAndLoad(Module *M, GEPChainInfo &GEP, - LoadInst *Load) { - SmallVector Args; - fillCommonArgs(M->getContext(), Args, GEP, Load); - CallInst *Call = makeIntrinsicCall(M, Intrinsic::bpf_getelementptr_and_load, - {Load->getType()}, Args); - setParamElementType(Call, 0, GEP.SourceElementType); - Call->applyMergedLocation(mergeDILocations(GEP.Members), Load->getDebugLoc()); - Call->setName((*GEP.Members.rbegin())->getName()); - if (Load->isUnordered()) { - Call->setOnlyReadsMemory(); - Call->setOnlyAccessesArgMemory(); - setParamReadOnly(Call, 0); - } - for (unsigned I = GepAndLoadFirstIdxArg; I < Args.size(); ++I) - Call->addParamAttr(I, Attribute::ImmArg); - Call->setAAMetadata(Load->getAAMetadata()); - return Call; -} - -static Instruction *makeGEPAndStore(Module *M, GEPChainInfo &GEP, - StoreInst *Store) { - SmallVector Args; - Args.push_back(Store->getValueOperand()); - fillCommonArgs(M->getContext(), Args, GEP, Store); - CallInst *Call = - makeIntrinsicCall(M, Intrinsic::bpf_getelementptr_and_store, - {Store->getValueOperand()->getType()}, Args); - setParamElementType(Call, 1, GEP.SourceElementType); - if (Store->getValueOperand()->getType()->isPointerTy()) - setParamReadNone(Call, 0); - Call->applyMergedLocation(mergeDILocations(GEP.Members), - Store->getDebugLoc()); - if (Store->isUnordered()) { - Call->setOnlyWritesMemory(); - Call->setOnlyAccessesArgMemory(); - setParamWriteOnly(Call, 1); - } - for (unsigned I = GepAndStoreFirstIdxArg; I < Args.size(); ++I) - Call->addParamAttr(I, Attribute::ImmArg); - Call->setAAMetadata(Store->getAAMetadata()); - return Call; -} - -static unsigned getOperandAsUnsigned(CallInst *Call, unsigned ArgNo) { - if (auto *Int = dyn_cast(Call->getOperand(ArgNo))) - return Int->getValue().getZExtValue(); - std::string Report; - raw_string_ostream ReportS(Report); - ReportS << "Expecting ConstantInt as argument #" << ArgNo << " of " << *Call - << "\n"; - report_fatal_error(StringRef(Report)); -} - -static GetElementPtrInst *reconstructGEP(CallInst *Call, int Delta) { - SmallVector Indices; - Indices.append(Call->data_operands_begin() + 6 + Delta, - Call->data_operands_end()); - Type *GEPPointeeType = Call->getParamElementType(Delta); - auto *GEP = - GetElementPtrInst::Create(GEPPointeeType, Call->getOperand(Delta), - ArrayRef(Indices), Call->getName()); - GEP->setIsInBounds(getOperandAsUnsigned(Call, 5 + Delta)); - return GEP; -} - -template > -static void reconstructCommon(CallInst *Call, GetElementPtrInst *GEP, T *Insn, - int Delta) { - Insn->setVolatile(getOperandAsUnsigned(Call, 1 + Delta)); - Insn->setOrdering((AtomicOrdering)getOperandAsUnsigned(Call, 2 + Delta)); - Insn->setSyncScopeID(getOperandAsUnsigned(Call, 3 + Delta)); - unsigned AlignShiftValue = getOperandAsUnsigned(Call, 4 + Delta); - Insn->setAlignment(Align(1ULL << AlignShiftValue)); - GEP->setDebugLoc(Call->getDebugLoc()); - Insn->setDebugLoc(Call->getDebugLoc()); - Insn->setAAMetadata(Call->getAAMetadata()); -} - -std::pair -BPFPreserveStaticOffsetPass::reconstructLoad(CallInst *Call) { - GetElementPtrInst *GEP = reconstructGEP(Call, 0); - Type *ReturnType = Call->getFunctionType()->getReturnType(); - auto *Load = new LoadInst(ReturnType, GEP, "", - /* These would be set in reconstructCommon */ - false, Align(1)); - reconstructCommon(Call, GEP, Load, 0); - return std::pair{GEP, Load}; -} - -std::pair -BPFPreserveStaticOffsetPass::reconstructStore(CallInst *Call) { - GetElementPtrInst *GEP = reconstructGEP(Call, 1); - auto *Store = new StoreInst(Call->getOperand(0), GEP, - /* These would be set in reconstructCommon */ - false, Align(1)); - reconstructCommon(Call, GEP, Store, 1); - return std::pair{GEP, Store}; -} - -static bool isZero(Value *V) { - auto *CI = dyn_cast(V); - return CI && CI->isZero(); -} - -// Given a chain of GEP instructions collect information necessary to -// merge this chain as a single GEP instruction of form: -// getelementptr %, ptr %p, i32 0, , , ... -static bool foldGEPChainAsStructAccess(SmallVector &GEPs, - GEPChainInfo &Info) { - if (GEPs.empty()) - return false; - - if (!all_of(GEPs, [=](GetElementPtrInst *GEP) { - return GEP->hasAllConstantIndices(); - })) - return false; - - GetElementPtrInst *First = GEPs[0]; - Info.InBounds = First->isInBounds(); - Info.SourceElementType = First->getSourceElementType(); - Type *ResultElementType = First->getResultElementType(); - Info.Indices.append(First->idx_begin(), First->idx_end()); - Info.Members.push_back(First); - - for (auto *Iter = GEPs.begin() + 1; Iter != GEPs.end(); ++Iter) { - GetElementPtrInst *GEP = *Iter; - if (!isZero(*GEP->idx_begin())) { - Info.reset(); - return false; - } - if (!GEP->getSourceElementType() || - GEP->getSourceElementType() != ResultElementType) { - Info.reset(); - return false; - } - Info.InBounds &= GEP->isInBounds(); - Info.Indices.append(GEP->idx_begin() + 1, GEP->idx_end()); - Info.Members.push_back(GEP); - ResultElementType = GEP->getResultElementType(); - } - - return true; -} - -// Given a chain of GEP instructions collect information necessary to -// merge this chain as a single GEP instruction of form: -// getelementptr i8, ptr %p, i64 %offset -static bool foldGEPChainAsU8Access(SmallVector &GEPs, - GEPChainInfo &Info) { - if (GEPs.empty()) - return false; - - GetElementPtrInst *First = GEPs[0]; - const DataLayout &DL = First->getModule()->getDataLayout(); - LLVMContext &C = First->getContext(); - Type *PtrTy = First->getType()->getScalarType(); - APInt Offset(DL.getIndexTypeSizeInBits(PtrTy), 0); - for (GetElementPtrInst *GEP : GEPs) { - if (!GEP->accumulateConstantOffset(DL, Offset)) { - Info.reset(); - return false; - } - Info.InBounds &= GEP->isInBounds(); - Info.Members.push_back(GEP); - } - Info.SourceElementType = Type::getInt8Ty(C); - Info.Indices.push_back(ConstantInt::get(C, Offset)); - - return true; -} - -static void reportNonStaticGEPChain(Instruction *Insn) { - auto Msg = DiagnosticInfoUnsupported( - *Insn->getFunction(), - Twine("Non-constant offset in access to a field of a type marked " - "with preserve_static_offset might be rejected by BPF verifier") - .concat(Insn->getDebugLoc() - ? "" - : " (pass -g option to get exact location)"), - Insn->getDebugLoc(), DS_Warning); - Insn->getContext().diagnose(Msg); -} - -static bool allZeroIndices(SmallVector &GEPs) { - return GEPs.empty() || all_of(GEPs, [=](GetElementPtrInst *GEP) { - return GEP->hasAllZeroIndices(); - }); -} - -static bool tryToReplaceWithGEPBuiltin(Instruction *LoadOrStoreTemplate, - SmallVector &GEPs, - Instruction *InsnToReplace) { - GEPChainInfo GEPChain; - if (!foldGEPChainAsStructAccess(GEPs, GEPChain) && - !foldGEPChainAsU8Access(GEPs, GEPChain)) { - return false; - } - Module *M = InsnToReplace->getModule(); - if (auto *Load = dyn_cast(LoadOrStoreTemplate)) { - Instruction *Replacement = makeGEPAndLoad(M, GEPChain, Load); - Replacement->insertBefore(InsnToReplace); - InsnToReplace->replaceAllUsesWith(Replacement); - } - if (auto *Store = dyn_cast(LoadOrStoreTemplate)) { - Instruction *Replacement = makeGEPAndStore(M, GEPChain, Store); - Replacement->insertBefore(InsnToReplace); - } - return true; -} - -// Check if U->getPointerOperand() == I -static bool isPointerOperand(Value *I, User *U) { - if (auto *L = dyn_cast(U)) - return L->getPointerOperand() == I; - if (auto *S = dyn_cast(U)) - return S->getPointerOperand() == I; - if (auto *GEP = dyn_cast(U)) - return GEP->getPointerOperand() == I; - if (auto *Call = isGEPAndLoad(U)) - return Call->getArgOperand(0) == I; - if (auto *Call = isGEPAndStore(U)) - return Call->getArgOperand(1) == I; - return false; -} - -static bool isInlineableCall(User *U) { - if (auto *Call = dyn_cast(U)) - return Call->hasFnAttr(Attribute::InlineHint); - return false; -} - -static void rewriteAccessChain(Instruction *Insn, - SmallVector &GEPs, - SmallVector &Visited, - bool AllowPatial, bool &StillUsed); - -static void rewriteUses(Instruction *Insn, - SmallVector &GEPs, - SmallVector &Visited, bool AllowPatial, - bool &StillUsed) { - for (User *U : Insn->users()) { - auto *UI = dyn_cast(U); - if (UI && (isPointerOperand(Insn, UI) || isPreserveStaticOffsetCall(UI) || - isInlineableCall(UI))) - rewriteAccessChain(UI, GEPs, Visited, AllowPatial, StillUsed); - else - LLVM_DEBUG({ - llvm::dbgs() << "unsupported usage in BPFPreserveStaticOffsetPass:\n"; - llvm::dbgs() << " Insn: " << *Insn << "\n"; - llvm::dbgs() << " User: " << *U << "\n"; - }); - } -} - -// A DFS traversal of GEP chain trees starting from Root. -// -// Recursion descends through GEP instructions and -// llvm.preserve.static.offset calls. Recursion stops at any other -// instruction. If load or store instruction is reached it is replaced -// by a call to `llvm.bpf.getelementptr.and.load` or -// `llvm.bpf.getelementptr.and.store` intrinsic. -// If `llvm.bpf.getelementptr.and.load/store` is reached the accumulated -// GEPs are merged into the intrinsic call. -// If nested calls to `llvm.preserve.static.offset` are encountered these -// calls are marked for deletion. -// -// Parameters description: -// - Insn - current position in the tree -// - GEPs - GEP instructions for the current branch -// - Visited - a list of visited instructions in DFS order, -// order is important for unused instruction deletion. -// - AllowPartial - when true GEP chains that can't be folded are -// not reported, otherwise diagnostic message is show for such chains. -// - StillUsed - set to true if one of the GEP chains could not be -// folded, makes sense when AllowPartial is false, means that root -// preserve.static.offset call is still in use and should remain -// until the next run of this pass. -static void rewriteAccessChain(Instruction *Insn, - SmallVector &GEPs, - SmallVector &Visited, - bool AllowPatial, bool &StillUsed) { - auto MarkAndTraverseUses = [&]() { - Visited.push_back(Insn); - rewriteUses(Insn, GEPs, Visited, AllowPatial, StillUsed); - }; - auto TryToReplace = [&](Instruction *LoadOrStore) { - // Do nothing for (preserve.static.offset (load/store ..)) or for - // GEPs with zero indices. Such constructs lead to zero offset and - // are simplified by other passes. - if (allZeroIndices(GEPs)) - return; - if (tryToReplaceWithGEPBuiltin(LoadOrStore, GEPs, Insn)) { - Visited.push_back(Insn); - return; - } - if (!AllowPatial) - reportNonStaticGEPChain(Insn); - StillUsed = true; - }; - if (isa(Insn) || isa(Insn)) { - TryToReplace(Insn); - } else if (isGEPAndLoad(Insn)) { - auto [GEP, Load] = - BPFPreserveStaticOffsetPass::reconstructLoad(cast(Insn)); - GEPs.push_back(GEP); - TryToReplace(Load); - GEPs.pop_back(); - delete Load; - delete GEP; - } else if (isGEPAndStore(Insn)) { - // This case can't be merged with the above because - // `delete Load` / `delete Store` wants a concrete type, - // destructor of Instruction is protected. - auto [GEP, Store] = - BPFPreserveStaticOffsetPass::reconstructStore(cast(Insn)); - GEPs.push_back(GEP); - TryToReplace(Store); - GEPs.pop_back(); - delete Store; - delete GEP; - } else if (auto *GEP = dyn_cast(Insn)) { - GEPs.push_back(GEP); - MarkAndTraverseUses(); - GEPs.pop_back(); - } else if (isPreserveStaticOffsetCall(Insn)) { - MarkAndTraverseUses(); - } else if (isInlineableCall(Insn)) { - // Preserve preserve.static.offset call for parameters of - // functions that might be inlined. These would be removed on a - // second pass after inlining. - // Might happen when a pointer to a preserve_static_offset - // structure is passed as parameter of a function that would be - // inlined inside a loop that would be unrolled. - if (AllowPatial) - StillUsed = true; - } else { - SmallString<128> Buf; - raw_svector_ostream BufStream(Buf); - BufStream << *Insn; - report_fatal_error( - Twine("Unexpected rewriteAccessChain Insn = ").concat(Buf)); - } -} - -static void removeMarkerCall(Instruction *Marker) { - Marker->replaceAllUsesWith(Marker->getOperand(0)); - Marker->eraseFromParent(); -} - -static bool rewriteAccessChain(Instruction *Marker, bool AllowPatial, - SmallPtrSetImpl &RemovedMarkers) { - SmallVector GEPs; - SmallVector Visited; - bool StillUsed = false; - rewriteUses(Marker, GEPs, Visited, AllowPatial, StillUsed); - // Check if Visited instructions could be removed, iterate in - // reverse to unblock instructions higher in the chain. - for (auto V = Visited.rbegin(); V != Visited.rend(); ++V) { - if (isPreserveStaticOffsetCall(*V)) { - removeMarkerCall(*V); - RemovedMarkers.insert(*V); - } else if ((*V)->use_empty()) { - (*V)->eraseFromParent(); - } - } - return StillUsed; -} - -static std::vector -collectPreserveStaticOffsetCalls(Function &F) { - std::vector Calls; - for (Instruction &Insn : instructions(F)) - if (isPreserveStaticOffsetCall(&Insn)) - Calls.push_back(&Insn); - return Calls; -} - -bool isPreserveArrayIndex(Value *V) { - return isIntrinsicCall(V, Intrinsic::preserve_array_access_index); -} - -bool isPreserveStructIndex(Value *V) { - return isIntrinsicCall(V, Intrinsic::preserve_struct_access_index); -} - -bool isPreserveUnionIndex(Value *V) { - return isIntrinsicCall(V, Intrinsic::preserve_union_access_index); -} - -static void removePAICalls(Instruction *Marker) { - auto IsPointerOperand = [](Value *Op, User *U) { - if (auto *GEP = dyn_cast(U)) - return GEP->getPointerOperand() == Op; - if (isPreserveStaticOffsetCall(U) || isPreserveArrayIndex(U) || - isPreserveStructIndex(U) || isPreserveUnionIndex(U)) - return cast(U)->getArgOperand(0) == Op; - return false; - }; - - SmallVector WorkList; - WorkList.push_back(Marker); - do { - Value *V = WorkList.pop_back_val(); - for (User *U : V->users()) - if (IsPointerOperand(V, U)) - WorkList.push_back(U); - auto *Call = dyn_cast(V); - if (!Call) - continue; - if (isPreserveArrayIndex(V)) - BPFCoreSharedInfo::removeArrayAccessCall(Call); - if (isPreserveStructIndex(V)) - BPFCoreSharedInfo::removeStructAccessCall(Call); - if (isPreserveUnionIndex(V)) - BPFCoreSharedInfo::removeUnionAccessCall(Call); - } while (!WorkList.empty()); -} - -// Look for sequences: -// - llvm.preserve.static.offset -> getelementptr... -> load -// - llvm.preserve.static.offset -> getelementptr... -> store -// And replace those with calls to intrinsics: -// - llvm.bpf.getelementptr.and.load -// - llvm.bpf.getelementptr.and.store -static bool rewriteFunction(Function &F, bool AllowPartial) { - LLVM_DEBUG(dbgs() << "********** BPFPreserveStaticOffsetPass (AllowPartial=" - << AllowPartial << ") ************\n"); - - auto MarkerCalls = collectPreserveStaticOffsetCalls(F); - SmallPtrSet RemovedMarkers; - - LLVM_DEBUG(dbgs() << "There are " << MarkerCalls.size() - << " preserve.static.offset calls\n"); - - if (MarkerCalls.empty()) - return false; - - for (auto *Call : MarkerCalls) - removePAICalls(Call); - - for (auto *Call : MarkerCalls) { - if (RemovedMarkers.contains(Call)) - continue; - bool StillUsed = rewriteAccessChain(Call, AllowPartial, RemovedMarkers); - if (!StillUsed || !AllowPartial) - removeMarkerCall(Call); - } - - return true; -} - -PreservedAnalyses -llvm::BPFPreserveStaticOffsetPass::run(Function &F, - FunctionAnalysisManager &AM) { - return rewriteFunction(F, AllowPartial) ? PreservedAnalyses::none() - : PreservedAnalyses::all(); -} diff --git a/llvm/lib/Target/BPF/BPFTargetMachine.cpp b/llvm/lib/Target/BPF/BPFTargetMachine.cpp index 65286c822c4b..983a4ff6aa5c 100644 --- a/llvm/lib/Target/BPF/BPFTargetMachine.cpp +++ b/llvm/lib/Target/BPF/BPFTargetMachine.cpp @@ -105,16 +105,11 @@ void BPFTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) { FPM.addPass(BPFIRPeepholePass()); return true; } - if (PassName == "bpf-preserve-static-offset") { - FPM.addPass(BPFPreserveStaticOffsetPass(false)); - return true; - } return false; }); PB.registerPipelineStartEPCallback( [=](ModulePassManager &MPM, OptimizationLevel) { FunctionPassManager FPM; - FPM.addPass(BPFPreserveStaticOffsetPass(true)); FPM.addPass(BPFAbstractMemberAccessPass(this)); FPM.addPass(BPFPreserveDITypePass()); FPM.addPass(BPFIRPeepholePass()); @@ -124,12 +119,6 @@ void BPFTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) { OptimizationLevel Level) { FPM.addPass(SimplifyCFGPass(SimplifyCFGOptions().hoistCommonInsts(true))); }); - PB.registerScalarOptimizerLateEPCallback( - [=](FunctionPassManager &FPM, OptimizationLevel Level) { - // Run this after loop unrolling but before - // SimplifyCFGPass(... .sinkCommonInsts(true)) - FPM.addPass(BPFPreserveStaticOffsetPass(false)); - }); PB.registerPipelineEarlySimplificationEPCallback( [=](ModulePassManager &MPM, OptimizationLevel) { MPM.addPass(BPFAdjustOptPass()); diff --git a/llvm/lib/Target/BPF/CMakeLists.txt b/llvm/lib/Target/BPF/CMakeLists.txt index 6a96394a6aee..f4a8fa3674cd 100644 --- a/llvm/lib/Target/BPF/CMakeLists.txt +++ b/llvm/lib/Target/BPF/CMakeLists.txt @@ -26,7 +26,6 @@ add_llvm_target(BPFCodeGen BPFISelLowering.cpp BPFMCInstLower.cpp BPFPreserveDIType.cpp - BPFPreserveStaticOffset.cpp BPFRegisterInfo.cpp BPFSelectionDAGInfo.cpp BPFSubtarget.cpp diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-align.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-align.ll deleted file mode 100644 index 0a0f3c22e374..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/load-align.ll +++ /dev/null @@ -1,66 +0,0 @@ -; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check handling of a load instruction for a field with non-standard -; alignment by bpf-preserve-static-offset. -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; -; typedef int aligned_int __attribute__((aligned(128))); -; -; struct foo { -; int _; -; aligned_int a; -; } __ctx; -; -; extern void consume(int); -; -; void bar(struct foo *p) { -; consume(p->a); -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=function(sroa) -S -o - - -%struct.foo = type { i32, [124 x i8], i32, [124 x i8] } - -; Function Attrs: nounwind -define dso_local void @bar(ptr noundef %p) #0 { -entry: - %0 = call ptr @llvm.preserve.static.offset(ptr %p) - %a = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 2 - %1 = load i32, ptr %a, align 128, !tbaa !2 - call void @consume(i32 noundef %1) - ret void -} - -; CHECK: %[[a1:.*]] = call i32 (ptr, i1, i8, i8, i8, i1, ...) -; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 -; CHECK-SAME: (ptr readonly elementtype(%struct.foo) %{{[^,]+}}, -; CHECK-SAME: i1 false, i8 0, i8 1, i8 7, i1 true, i32 immarg 0, i32 immarg 2) -; ^^^^ -; alignment 2**7 -; CHECK-SAME: #[[v2:.*]], !tbaa -; CHECK-NEXT: call void @consume(i32 noundef %[[a1]]) -; CHECK: attributes #[[v2]] = { memory(argmem: read) } - -declare void @consume(i32 noundef) #1 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #2 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !4, i64 128} -!3 = !{!"foo", !4, i64 0, !4, i64 128} -!4 = !{!"int", !5, i64 0} -!5 = !{!"omnipotent char", !6, i64 0} -!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-arr-pai.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-arr-pai.ll deleted file mode 100644 index d6b1f30fa386..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/load-arr-pai.ll +++ /dev/null @@ -1,93 +0,0 @@ -; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; #define __pai __attribute__((preserve_access_index)) -; -; struct bar { -; int a[7]; -; } __pai __ctx; -; -; int buz(struct bar *p) { -; return p->a[5]; -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -debug-info-kind=limited -o - \ -; | opt -passes=function(sroa) -S -o - - -%struct.bar = type { [7 x i32] } - -; Function Attrs: nounwind -define dso_local i32 @buz(ptr noundef %p) #0 !dbg !10 { -entry: - call void @llvm.dbg.value(metadata ptr %p, metadata !18, metadata !DIExpression()), !dbg !19 - %0 = call ptr @llvm.preserve.static.offset(ptr %p), !dbg !20 - %1 = call ptr @llvm.preserve.struct.access.index.p0.p0(ptr elementtype(%struct.bar) %0, i32 0, i32 0), !dbg !20, !llvm.preserve.access.index !14 - %2 = call ptr @llvm.preserve.array.access.index.p0.p0(ptr elementtype([7 x i32]) %1, i32 1, i32 5), !dbg !21, !llvm.preserve.access.index !3 - %3 = load i32, ptr %2, align 4, !dbg !21, !tbaa !22 - ret i32 %3, !dbg !26 -} - -; CHECK: define dso_local i32 @buz(ptr noundef %[[p:.*]]) {{.*}} { -; CHECK-NEXT: entry: -; CHECK-NEXT: call void @llvm.dbg.value -; CHECK-NEXT: %[[v5:.*]] = call i32 (ptr, i1, i8, i8, i8, i1, ...) -; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 -; CHECK-SAME: (ptr readonly elementtype(%struct.bar) %[[p]], -; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 0, i32 immarg 5) -; CHECK-SAME: #[[v6:.*]], !tbaa -; CHECK-NEXT: ret i32 %[[v5]] -; CHECK-NEXT: } -; CHECK: attributes #[[v6]] = { memory(argmem: read) } - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #1 - -; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) -declare ptr @llvm.preserve.struct.access.index.p0.p0(ptr, i32 immarg, i32 immarg) #2 - -; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) -declare ptr @llvm.preserve.array.access.index.p0.p0(ptr, i32 immarg, i32 immarg) #2 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare void @llvm.dbg.value(metadata, metadata, metadata) #1 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } - -!llvm.dbg.cu = !{!0} -!llvm.module.flags = !{!7, !8} -!llvm.ident = !{!9} - -!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, retainedTypes: !2, splitDebugInlining: false, nameTableKind: None) -!1 = !DIFile(filename: "some-file.c", directory: "/some/dir/") -!2 = !{!3} -!3 = !DICompositeType(tag: DW_TAG_array_type, baseType: !4, size: 224, elements: !5) -!4 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) -!5 = !{!6} -!6 = !DISubrange(count: 7) -!7 = !{i32 2, !"Debug Info Version", i32 3} -!8 = !{i32 1, !"wchar_size", i32 4} -!9 = !{!"clang"} -!10 = distinct !DISubprogram(name: "buz", scope: !1, file: !1, line: 8, type: !11, scopeLine: 8, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !17) -!11 = !DISubroutineType(types: !12) -!12 = !{!4, !13} -!13 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !14, size: 64) -!14 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "bar", file: !1, line: 4, size: 224, elements: !15) -!15 = !{!16} -!16 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !14, file: !1, line: 5, baseType: !3, size: 224) -!17 = !{!18} -!18 = !DILocalVariable(name: "p", arg: 1, scope: !10, file: !1, line: 8, type: !13) -!19 = !DILocation(line: 0, scope: !10) -!20 = !DILocation(line: 9, column: 13, scope: !10) -!21 = !DILocation(line: 9, column: 10, scope: !10) -!22 = !{!23, !23, i64 0} -!23 = !{!"int", !24, i64 0} -!24 = !{!"omnipotent char", !25, i64 0} -!25 = !{!"Simple C/C++ TBAA"} -!26 = !DILocation(line: 9, column: 3, scope: !10) diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-atomic.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-atomic.ll deleted file mode 100644 index 0a0c8ce9af5f..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/load-atomic.ll +++ /dev/null @@ -1,66 +0,0 @@ -; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check handling of atomic load instruction by bpf-preserve-static-offset. -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct foo { -; int _; -; int a; -; } __ctx; -; -; extern void consume(int); -; -; void bar(struct foo *p) { -; int r; -; __atomic_load(&p->a, &r, 2); -; consume(r); -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=function(sroa) -S -o - - -%struct.foo = type { i32, i32 } - -; Function Attrs: nounwind -define dso_local void @bar(ptr noundef %p) #0 { -entry: - %0 = call ptr @llvm.preserve.static.offset(ptr %p) - %a = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 - %1 = load atomic i32, ptr %a acquire, align 4 - call void @consume(i32 noundef %1) - ret void -} - -; CHECK: %[[a1:.*]] = call i32 (ptr, i1, i8, i8, i8, i1, ...) -; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 -; CHECK-SAME: (ptr elementtype(%struct.foo) %[[p:.*]], -; i1 false, i8 4, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1) -; ^^^^ -; atomic order -; CHECK-NOT: #{{[0-9]+}} -; CHECK-NEXT: call void @consume(i32 noundef %[[a1]]) - -; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) -declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #2 - -declare void @consume(i32 noundef) #3 - -; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) -declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } -attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-2.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-2.ll deleted file mode 100644 index 4832fb2a50c0..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-2.ll +++ /dev/null @@ -1,82 +0,0 @@ -; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check that bpf-preserve-static-offset folds GEP chains that end by -; getelementptr.and.load. -; -; Source (modified by hand): -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct bar { -; int aa; -; int bb; -; }; -; -; struct foo { -; int a; -; struct bar b; -; } __ctx; -; -; extern void consume(int); -; -; void bar(struct foo *p) { -; consume(p->b.bb); -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=function(sroa) -S -o - -; -; And modified to fold last getelementptr/load as a single -; getelementptr.and.load. - -%struct.foo = type { i32, %struct.bar } -%struct.bar = type { i32, i32 } - -; Function Attrs: nounwind -define dso_local void @bar(ptr noundef %p) #0 { -entry: - %0 = call ptr @llvm.preserve.static.offset(ptr %p) - %b = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 - %bb1 = call i32 (ptr, i1, i8, i8, i8, i1, ...) - @llvm.bpf.getelementptr.and.load.i32 - (ptr readonly elementtype(%struct.bar) %b, - i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1) - #4, !tbaa !2 - call void @consume(i32 noundef %bb1) - ret void -} - -; CHECK: define dso_local void @bar(ptr noundef %[[p:.*]]) -; CHECK: %[[bb1:.*]] = call i32 (ptr, i1, i8, i8, i8, i1, ...) -; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 -; CHECK-SAME: (ptr readonly elementtype(%struct.foo) %[[p]], -; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1, i32 immarg 1) -; CHECK-SAME: #[[v2:.*]], !tbaa -; CHECK-NEXT: call void @consume(i32 noundef %[[bb1]]) -; CHECK: attributes #[[v2]] = { memory(argmem: read) } - -declare void @consume(i32 noundef) #1 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #2 - -; Function Attrs: nocallback nofree nounwind willreturn -declare i32 @llvm.bpf.getelementptr.and.load.i32(ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #3 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -attributes #3 = { nocallback nofree nounwind willreturn } -attributes #4 = { memory(argmem: read) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !4, i64 8} -!3 = !{!"foo", !4, i64 0, !7, i64 4} -!4 = !{!"int", !5, i64 0} -!5 = !{!"omnipotent char", !6, i64 0} -!6 = !{!"Simple C/C++ TBAA"} -!7 = !{!"bar", !4, i64 0, !4, i64 4} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-oob.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-oob.ll deleted file mode 100644 index c4a92481a0b1..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-oob.ll +++ /dev/null @@ -1,73 +0,0 @@ -; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check that bpf-preserve-static-offset keeps track of 'inbounds' flags while -; folding chain of GEP instructions. -; -; Source (IR modified by hand): -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct foo { -; int a[2]; -; }; -; -; struct bar { -; int a; -; struct foo b; -; } __ctx; -; -; extern void consume(int); -; -; void buz(struct bar *p) { -; consume(p->b.a[1]); -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=function(sroa) -S -o - -; -; Modified to remove one of the 'inbounds' from one of the GEP instructions. - -%struct.bar = type { i32, %struct.foo } -%struct.foo = type { [2 x i32] } - -; Function Attrs: nounwind -define dso_local void @buz(ptr noundef %p) #0 { -entry: - %0 = call ptr @llvm.preserve.static.offset(ptr %p) - %b = getelementptr inbounds %struct.bar, ptr %0, i32 0, i32 1 - %a = getelementptr %struct.foo, ptr %b, i32 0, i32 0 - %arrayidx = getelementptr inbounds [2 x i32], ptr %a, i64 0, i64 1 - %1 = load i32, ptr %arrayidx, align 4, !tbaa !2 - call void @consume(i32 noundef %1) - ret void -} - -; CHECK: %[[v1:.*]] = call i32 (ptr, i1, i8, i8, i8, i1, ...) -; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 -; CHECK-SAME: (ptr readonly elementtype(%struct.bar) %{{[^,]+}}, -; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 false, -; ^^^^^^^^ -; not inbounds -; CHECK-SAME: i32 immarg 0, i32 immarg 1, i32 immarg 0, i64 immarg 1) -; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -; folded gep chain -; CHECK-NEXT: call void @consume(i32 noundef %[[v1]]) - -declare void @consume(i32 noundef) #1 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #2 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !3, i64 0} -!3 = !{!"int", !4, i64 0} -!4 = !{!"omnipotent char", !5, i64 0} -!5 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8-oob.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8-oob.ll deleted file mode 100644 index da3e01a455a5..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8-oob.ll +++ /dev/null @@ -1,74 +0,0 @@ -; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check that bpf-preserve-static-offset folds chain of GEP instructions. -; The GEP chain in this example has unexpected shape and thus is -; folded as i8 access. -; -; Source (IR modified by hand): -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct foo { -; char a[2]; -; }; -; -; struct bar { -; char a; -; struct foo b; -; } __ctx; -; -; extern void consume(char); -; -; void buz(struct bar *p) { -; consume((&p->b)[1].a[1]); -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=function(sroa) -S -o - -; -; Modified to remove 'inbounds' from one of the GEP instructions. - -%struct.bar = type { i8, %struct.foo } -%struct.foo = type { [2 x i8] } - -; Function Attrs: nounwind -define dso_local void @buz(ptr noundef %p) #0 { -entry: - %0 = call ptr @llvm.preserve.static.offset(ptr %p) - %b = getelementptr inbounds %struct.bar, ptr %0, i32 0, i32 1 - %arrayidx = getelementptr inbounds %struct.foo, ptr %b, i64 1 -; ^^^^^ -; folded as i8 access because of this index - %a = getelementptr %struct.foo, ptr %arrayidx, i32 0, i32 0 - %arrayidx1 = getelementptr inbounds [2 x i8], ptr %a, i64 0, i64 1 - %1 = load i8, ptr %arrayidx1, align 1, !tbaa !2 - call void @consume(i8 noundef signext %1) - ret void -} - -; CHECK: %[[v1:.*]] = call i8 (ptr, i1, i8, i8, i8, i1, ...) -; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i8 -; CHECK-SAME: (ptr readonly elementtype(i8) %{{[^,]+}}, -; CHECK-SAME: i1 false, i8 0, i8 1, i8 0, i1 false, i64 immarg 4) -; ^^^^^^^^ ^^^^^^^^^^^^ -; not inbounds ---' | -; offset from 'struct bar' start -------------' -; CHECK-NEXT: call void @consume(i8 noundef signext %[[v1]]) - -declare void @consume(i8 noundef signext) #1 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #2 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !3, i64 0} -!3 = !{!"omnipotent char", !4, i64 0} -!4 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8-type-mismatch.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8-type-mismatch.ll deleted file mode 100644 index 757e06c507c6..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8-type-mismatch.ll +++ /dev/null @@ -1,73 +0,0 @@ -; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check that bpf-preserve-static-offset folds chain of GEP instructions. -; The GEP chain in this example has unexpected shape and thus is -; folded as i8 access. -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct foo { -; char aa; -; char bb; -; }; -; -; struct bar { -; char a; -; struct foo b; -; } __ctx; -; -; extern void consume(char); -; -; void buz(struct bar *p) { -; consume(((struct foo *)(((char*)&p->b) + 1))->bb); -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=function(sroa) -S -o - - -%struct.bar = type { i8, %struct.foo } -%struct.foo = type { i8, i8 } - -; Function Attrs: nounwind -define dso_local void @buz(ptr noundef %p) #0 { -entry: - %0 = call ptr @llvm.preserve.static.offset(ptr %p) - %b = getelementptr inbounds %struct.bar, ptr %0, i32 0, i32 1 - %add.ptr = getelementptr inbounds i8, ptr %b, i64 1 -; ~~ -; these types do not match, thus GEP chain is folded as an offset -; ~~~~~~~~~~~ - %bb = getelementptr inbounds %struct.foo, ptr %add.ptr, i32 0, i32 1 - %1 = load i8, ptr %bb, align 1, !tbaa !2 - call void @consume(i8 noundef signext %1) - ret void -} - -; CHECK: %[[bb1:.*]] = call i8 (ptr, i1, i8, i8, i8, i1, ...) -; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i8 -; CHECK-SAME: (ptr readonly elementtype(i8) %{{[^,]+}}, -; CHECK-SAME: i1 false, i8 0, i8 1, i8 0, i1 true, i64 immarg 3) -; ^^^^^^^^^^^^ -; offset from 'struct bar' start -; CHECK-NEXT: call void @consume(i8 noundef signext %[[bb1]]) - -declare void @consume(i8 noundef signext) #1 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #2 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !4, i64 1} -!3 = !{!"foo", !4, i64 0, !4, i64 1} -!4 = !{!"omnipotent char", !5, i64 0} -!5 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8.ll deleted file mode 100644 index e91aa93775e1..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8.ll +++ /dev/null @@ -1,71 +0,0 @@ -; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check that bpf-preserve-static-offset folds chain of GEP instructions. -; The GEP chain in this example has unexpected shape and thus is -; folded as i8 access. -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct foo { -; char a[2]; -; }; -; -; struct bar { -; char a; -; struct foo b; -; } __ctx; -; -; extern void consume(char); -; -; void buz(struct bar *p) { -; consume((&p->b)[1].a[1]); -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=function(sroa) -S -o - - -%struct.bar = type { i8, %struct.foo } -%struct.foo = type { [2 x i8] } - -; Function Attrs: nounwind -define dso_local void @buz(ptr noundef %p) #0 { -entry: - %0 = call ptr @llvm.preserve.static.offset(ptr %p) - %b = getelementptr inbounds %struct.bar, ptr %0, i32 0, i32 1 - %arrayidx = getelementptr inbounds %struct.foo, ptr %b, i64 1 -; ^^^^^ -; folded as i8 access because of this index - %a = getelementptr inbounds %struct.foo, ptr %arrayidx, i32 0, i32 0 - %arrayidx1 = getelementptr inbounds [2 x i8], ptr %a, i64 0, i64 1 - %1 = load i8, ptr %arrayidx1, align 1, !tbaa !2 - call void @consume(i8 noundef signext %1) - ret void -} - -; CHECK: %[[v1:.*]] = call i8 (ptr, i1, i8, i8, i8, i1, ...) -; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i8 -; CHECK-SAME: (ptr readonly elementtype(i8) %{{[^,]+}}, -; CHECK-SAME: i1 false, i8 0, i8 1, i8 0, i1 true, i64 immarg 4) -; ^^^^^^^^^^^^ -; offset from 'struct bar' start -; CHECK-NEXT: call void @consume(i8 noundef signext %[[v1]]) - -declare void @consume(i8 noundef signext) #1 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #2 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !3, i64 0} -!3 = !{!"omnipotent char", !4, i64 0} -!4 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain.ll deleted file mode 100644 index ac08fed70c8a..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain.ll +++ /dev/null @@ -1,68 +0,0 @@ -; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check that bpf-preserve-static-offset folds chain of GEP instructions. -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct foo { -; int a[2]; -; }; -; -; struct bar { -; int a; -; struct foo b; -; } __ctx; -; -; extern void consume(int); -; -; void buz(struct bar *p) { -; consume(p->b.a[1]); -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=function(sroa) -S -o - - -%struct.bar = type { i32, %struct.foo } -%struct.foo = type { [2 x i32] } - -; Function Attrs: nounwind -define dso_local void @buz(ptr noundef %p) #0 { -entry: - %0 = call ptr @llvm.preserve.static.offset(ptr %p) - %b = getelementptr inbounds %struct.bar, ptr %0, i32 0, i32 1 - %a = getelementptr inbounds %struct.foo, ptr %b, i32 0, i32 0 - %arrayidx = getelementptr inbounds [2 x i32], ptr %a, i64 0, i64 1 - %1 = load i32, ptr %arrayidx, align 4, !tbaa !2 - call void @consume(i32 noundef %1) - ret void -} - -; CHECK: %[[v1:.*]] = call i32 (ptr, i1, i8, i8, i8, i1, ...) -; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 -; CHECK-SAME: (ptr readonly elementtype(%struct.bar) %{{[^,]+}}, -; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, -; CHECK-SAME: i32 immarg 0, i32 immarg 1, i32 immarg 0, i64 immarg 1) -; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -; folded gep chain -; CHECK-NEXT: call void @consume(i32 noundef %[[v1]]) - -declare void @consume(i32 noundef) #1 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #2 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !3, i64 0} -!3 = !{!"int", !4, i64 0} -!4 = !{!"omnipotent char", !5, i64 0} -!5 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-inline.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-inline.ll deleted file mode 100644 index 9149b350dd89..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/load-inline.ll +++ /dev/null @@ -1,85 +0,0 @@ -; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check position of bpf-preserve-static-offset pass in the pipeline: -; - preserve.static.offset call is preserved if address is passed as -; a parameter to an inline-able function; -; - second bpf-preserve-static-offset pass (after inlining) should introduce -; getelementptr.and.load call using the preserved marker. -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct bar { -; int aa; -; int bb; -; }; -; -; struct foo { -; int a; -; struct bar b; -; } __ctx; -; -; extern void consume(int); -; -; static inline void bar(struct bar *p){ -; consume(p->bb); -; } -; -; void quux(struct foo *p) { -; bar(&p->b); -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=function(sroa) -S -o - - -%struct.foo = type { i32, %struct.bar } -%struct.bar = type { i32, i32 } - -; Function Attrs: nounwind -define dso_local void @quux(ptr noundef %p) #0 { -entry: - %0 = call ptr @llvm.preserve.static.offset(ptr %p) - %b = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 - call void @bar(ptr noundef %b) - ret void -} - -; Function Attrs: inlinehint nounwind -define internal void @bar(ptr noundef %p) #1 { -entry: - %bb = getelementptr inbounds %struct.bar, ptr %p, i32 0, i32 1 - %0 = load i32, ptr %bb, align 4, !tbaa !2 - call void @consume(i32 noundef %0) - ret void -} - -; CHECK: define dso_local void @quux(ptr nocapture noundef readonly %[[p:.*]]) -; CHECK: %[[bb_i1:.*]] = tail call i32 (ptr, i1, i8, i8, i8, i1, ...) -; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 -; CHECK-SAME: (ptr readonly elementtype(%struct.foo) %[[p]], -; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i64 immarg 0, i32 immarg 1, i32 immarg 1) -; CHECK-SAME: #[[v2:.*]], !tbaa -; CHECK-NEXT: tail call void @consume(i32 noundef %[[bb_i1]]) -; CHECK: attributes #[[v2]] = { memory(argmem: read) } - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #2 - -declare void @consume(i32 noundef) #3 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { inlinehint nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !4, i64 4} -!3 = !{!"bar", !4, i64 0, !4, i64 4} -!4 = !{!"int", !5, i64 0} -!5 = !{!"omnipotent char", !6, i64 0} -!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-non-const.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-non-const.ll deleted file mode 100644 index 2dd6edf4c4b8..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/load-non-const.ll +++ /dev/null @@ -1,75 +0,0 @@ -; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s 2>&1 | FileCheck %s -; -; If load offset is not a constant bpf-preserve-static-offset should report a -; warning and remove preserve.static.offset call. -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct foo { -; int a[7]; -; } __ctx; -; -; extern void consume(int); -; -; void bar(struct foo *p, unsigned long i) { -; consume(p->a[i]); -; } -; -; Compilation flag: -; clang -cc1 -O2 -debug-info-kind=line-tables-only -triple bpf \ -; -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=function(sroa) -S -o - - -; CHECK: warning: some-file.c:10:11: in function bar void (ptr, i64): -; CHECK-SAME: Non-constant offset in access to a field of a type marked with -; CHECK-SAME: preserve_static_offset might be rejected by BPF verifier - -%struct.foo = type { [7 x i32] } - -; Function Attrs: nounwind -define dso_local void @bar(ptr noundef %p, i64 noundef %i) #0 !dbg !5 { -entry: - %0 = call ptr @llvm.preserve.static.offset(ptr %p), !dbg !8 - %a = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 0, !dbg !8 - %arrayidx = getelementptr inbounds [7 x i32], ptr %a, i64 0, i64 %i, !dbg !9 - %1 = load i32, ptr %arrayidx, align 4, !dbg !9, !tbaa !10 - call void @consume(i32 noundef %1), !dbg !14 - ret void, !dbg !15 -} - -; CHECK: define dso_local void @bar(ptr noundef %[[p:.*]], i64 noundef %[[i:.*]]) -; CHECK: %[[a:.*]] = getelementptr inbounds %struct.foo, ptr %[[p]], i32 0, i32 0, !dbg -; CHECK-NEXT: %[[arrayidx:.*]] = getelementptr inbounds [7 x i32], ptr %[[a]], i64 0, i64 %[[i]], !dbg -; CHECK-NEXT: %[[v5:.*]] = load i32, ptr %[[arrayidx]], align 4, !dbg {{.*}}, !tbaa -; CHECK-NEXT: call void @consume(i32 noundef %[[v5]]), !dbg - -declare void @consume(i32 noundef) #1 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #2 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } - -!llvm.dbg.cu = !{!0} -!llvm.module.flags = !{!2, !3} -!llvm.ident = !{!4} - -!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly, splitDebugInlining: false, nameTableKind: None) -!1 = !DIFile(filename: "some-file.c", directory: "/some/dir/") -!2 = !{i32 2, !"Debug Info Version", i32 3} -!3 = !{i32 1, !"wchar_size", i32 4} -!4 = !{!"clang"} -!5 = distinct !DISubprogram(name: "bar", scope: !1, file: !1, line: 9, type: !6, scopeLine: 9, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0) -!6 = !DISubroutineType(types: !7) -!7 = !{} -!8 = !DILocation(line: 10, column: 14, scope: !5) -!9 = !DILocation(line: 10, column: 11, scope: !5) -!10 = !{!11, !11, i64 0} -!11 = !{!"int", !12, i64 0} -!12 = !{!"omnipotent char", !13, i64 0} -!13 = !{!"Simple C/C++ TBAA"} -!14 = !DILocation(line: 10, column: 3, scope: !5) -!15 = !DILocation(line: 11, column: 1, scope: !5) diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-ptr-pai.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-ptr-pai.ll deleted file mode 100644 index 6ec59c6b2c02..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/load-ptr-pai.ll +++ /dev/null @@ -1,114 +0,0 @@ -; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; #define __pai __attribute__((preserve_access_index)) -; -; struct bar { -; int a; -; int b; -; } __pai; -; -; struct buz { -; int _1; -; struct bar *b; -; } __pai __ctx; -; -; void foo(struct buz *p) { -; p->b->b = 42; -; } -; -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes \ -; -debug-info-kind=limited -o - \ -; | opt -passes=function(sroa) -S -o - - -%struct.buz = type { i32, ptr } -%struct.bar = type { i32, i32 } - -; Function Attrs: nounwind -define dso_local void @foo(ptr noundef %p) #0 !dbg !5 { -entry: - call void @llvm.dbg.value(metadata ptr %p, metadata !20, metadata !DIExpression()), !dbg !21 - %0 = call ptr @llvm.preserve.static.offset(ptr %p), !dbg !22 - %1 = call ptr @llvm.preserve.struct.access.index.p0.p0(ptr elementtype(%struct.buz) %0, i32 1, i32 1), !dbg !22, !llvm.preserve.access.index !9 - %2 = load ptr, ptr %1, align 8, !dbg !22, !tbaa !23 - %3 = call ptr @llvm.preserve.struct.access.index.p0.p0(ptr elementtype(%struct.bar) %2, i32 1, i32 1), !dbg !29, !llvm.preserve.access.index !15 - store i32 42, ptr %3, align 4, !dbg !30, !tbaa !31 - ret void, !dbg !33 -} - -; CHECK: define dso_local void @foo(ptr noundef %[[p:.*]]) {{.*}} { -; CHECK-NEXT: entry: -; CHECK-NEXT: call void @llvm.dbg.value -; CHECK-NEXT: %[[v5:.*]] = call ptr (ptr, i1, i8, i8, i8, i1, ...) -; CHECK-SAME: @llvm.bpf.getelementptr.and.load.p0 -; CHECK-SAME: (ptr readonly elementtype(%struct.buz) %[[p]], -; CHECK-SAME: i1 false, i8 0, i8 1, i8 3, i1 true, i32 immarg 0, i32 immarg 1) -; CHECK-SAME: #[[v6:.*]], !tbaa -; CHECK-NEXT: %[[v8:.*]] = -; CHECK-SAME: call ptr @llvm.preserve.struct.access.index.p0.p0 -; CHECK-SAME: (ptr elementtype(%struct.bar) %[[v5]], i32 1, i32 1), -; CHECK-SAME: !dbg ![[#]], !llvm.preserve.access.index ![[#]] -; CHECK-NEXT: store i32 42, ptr %[[v8]], align 4, !dbg ![[#]], !tbaa -; CHECK-NEXT: ret void, !dbg -; CHECK-NEXT: } - -; CHECK : attributes #[[v6]] = { memory(argmem: read) } - - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #1 - -; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) -declare ptr @llvm.preserve.struct.access.index.p0.p0(ptr, i32 immarg, i32 immarg) #2 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare void @llvm.dbg.value(metadata, metadata, metadata) #1 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } - -!llvm.dbg.cu = !{!0} -!llvm.module.flags = !{!2, !3} -!llvm.ident = !{!4} - -!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) -!1 = !DIFile(filename: "some-file.c", directory: "/some/dir/") -!2 = !{i32 2, !"Debug Info Version", i32 3} -!3 = !{i32 1, !"wchar_size", i32 4} -!4 = !{!"clang"} -!5 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 14, type: !6, scopeLine: 14, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !19) -!6 = !DISubroutineType(types: !7) -!7 = !{null, !8} -!8 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !9, size: 64) -!9 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "buz", file: !1, line: 9, size: 128, elements: !10) -!10 = !{!11, !13} -!11 = !DIDerivedType(tag: DW_TAG_member, name: "_1", scope: !9, file: !1, line: 10, baseType: !12, size: 32) -!12 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) -!13 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !9, file: !1, line: 11, baseType: !14, size: 64, offset: 64) -!14 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !15, size: 64) -!15 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "bar", file: !1, line: 4, size: 64, elements: !16) -!16 = !{!17, !18} -!17 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !15, file: !1, line: 5, baseType: !12, size: 32) -!18 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !15, file: !1, line: 6, baseType: !12, size: 32, offset: 32) -!19 = !{!20} -!20 = !DILocalVariable(name: "p", arg: 1, scope: !5, file: !1, line: 14, type: !8) -!21 = !DILocation(line: 0, scope: !5) -!22 = !DILocation(line: 15, column: 6, scope: !5) -!23 = !{!24, !28, i64 8} -!24 = !{!"buz", !25, i64 0, !28, i64 8} -!25 = !{!"int", !26, i64 0} -!26 = !{!"omnipotent char", !27, i64 0} -!27 = !{!"Simple C/C++ TBAA"} -!28 = !{!"any pointer", !26, i64 0} -!29 = !DILocation(line: 15, column: 9, scope: !5) -!30 = !DILocation(line: 15, column: 11, scope: !5) -!31 = !{!32, !25, i64 4} -!32 = !{!"bar", !25, i64 0, !25, i64 4} -!33 = !DILocation(line: 16, column: 1, scope: !5) diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-simple.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-simple.ll deleted file mode 100644 index 03ae7f3272dc..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/load-simple.ll +++ /dev/null @@ -1,71 +0,0 @@ -; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check handling of a simple load instruction by bpf-preserve-static-offset. -; Verify: -; - presence of gep.and.load intrinsic call -; - correct attributes for intrinsic call -; - presence of tbaa annotations -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct foo { -; int _; -; int a; -; } __ctx; -; -; extern void consume(int); -; -; void bar(struct foo *p) { -; consume(p->a); -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=function(sroa) -S -o - - -%struct.foo = type { i32, i32 } - -; Function Attrs: nounwind -define dso_local void @bar(ptr noundef %p) #0 { -entry: - %0 = call ptr @llvm.preserve.static.offset(ptr %p) - %a = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 - %1 = load i32, ptr %a, align 4, !tbaa !2 - call void @consume(i32 noundef %1) - ret void -} - -; CHECK: define dso_local void @bar(ptr noundef %[[p:.*]]) -; CHECK: %[[a1:.*]] = call i32 (ptr, i1, i8, i8, i8, i1, ...) -; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 -; CHECK-SAME: (ptr readonly elementtype(%struct.foo) %[[p]], -; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1) -; CHECK-SAME: #[[v1:.*]], !tbaa -; CHECK-NEXT: call void @consume(i32 noundef %[[a1]]) - -; CHECK: declare i32 -; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32(ptr nocapture, {{.*}}) #[[v2:.*]] - -; CHECK: attributes #[[v2]] = { nocallback nofree nounwind willreturn } -; CHECK: attributes #[[v1]] = { memory(argmem: read) } - -declare void @consume(i32 noundef) #1 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #2 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !4, i64 4} -!3 = !{!"foo", !4, i64 0, !4, i64 4} -!4 = !{!"int", !5, i64 0} -!5 = !{!"omnipotent char", !6, i64 0} -!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-struct-pai.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-struct-pai.ll deleted file mode 100644 index 5baa7ad0242c..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/load-struct-pai.ll +++ /dev/null @@ -1,105 +0,0 @@ -; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; #define __pai __attribute__((preserve_access_index)) -; -; struct foo { -; int a; -; int b; -; }; -; -; struct bar { -; int _1; -; int _2; -; struct foo c; -; } __pai __ctx; -; -; int buz(struct bar *p) { -; return p->c.b; -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes \ -; -debug-info-kind=limited -o - \ -; | opt -passes=function(sroa) -S -o - - -%struct.bar = type { i32, i32, %struct.foo } -%struct.foo = type { i32, i32 } - -; Function Attrs: nounwind -define dso_local i32 @buz(ptr noundef %p) #0 !dbg !5 { -entry: - call void @llvm.dbg.value(metadata ptr %p, metadata !20, metadata !DIExpression()), !dbg !21 - %0 = call ptr @llvm.preserve.static.offset(ptr %p), !dbg !22 - %1 = call ptr @llvm.preserve.struct.access.index.p0.p0(ptr elementtype(%struct.bar) %0, i32 2, i32 2), !dbg !22, !llvm.preserve.access.index !10 - %b = getelementptr inbounds %struct.foo, ptr %1, i32 0, i32 1, !dbg !23 - %2 = load i32, ptr %b, align 4, !dbg !23, !tbaa !24 - ret i32 %2, !dbg !30 -} - -; CHECK: define dso_local i32 @buz(ptr noundef %[[p:.*]]) {{.*}} { -; CHECK-NEXT: entry: -; CHECK-NEXT: call void @llvm.dbg.value -; CHECK-NEXT: %[[b1:.*]] = call i32 (ptr, i1, i8, i8, i8, i1, ...) -; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 -; CHECK-SAME: (ptr readonly elementtype(%struct.bar) %[[p]], -; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 2, i32 immarg 1) -; CHECK-SAME: #[[v5:.*]], !tbaa -; CHECK-NEXT: ret i32 %[[b1]] -; CHECK-NEXT: } - -; CHECK: attributes #[[v5]] = { memory(argmem: read) } - - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #1 - -; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) -declare ptr @llvm.preserve.struct.access.index.p0.p0(ptr, i32 immarg, i32 immarg) #2 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare void @llvm.dbg.value(metadata, metadata, metadata) #1 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } - -!llvm.dbg.cu = !{!0} -!llvm.module.flags = !{!2, !3} -!llvm.ident = !{!4} - -!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) -!1 = !DIFile(filename: "some-file.c", directory: "/some/dir/") -!2 = !{i32 2, !"Debug Info Version", i32 3} -!3 = !{i32 1, !"wchar_size", i32 4} -!4 = !{!"clang"} -!5 = distinct !DISubprogram(name: "buz", scope: !1, file: !1, line: 15, type: !6, scopeLine: 15, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !19) -!6 = !DISubroutineType(types: !7) -!7 = !{!8, !9} -!8 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) -!9 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !10, size: 64) -!10 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "bar", file: !1, line: 9, size: 128, elements: !11) -!11 = !{!12, !13, !14} -!12 = !DIDerivedType(tag: DW_TAG_member, name: "_1", scope: !10, file: !1, line: 10, baseType: !8, size: 32) -!13 = !DIDerivedType(tag: DW_TAG_member, name: "_2", scope: !10, file: !1, line: 11, baseType: !8, size: 32, offset: 32) -!14 = !DIDerivedType(tag: DW_TAG_member, name: "c", scope: !10, file: !1, line: 12, baseType: !15, size: 64, offset: 64) -!15 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "foo", file: !1, line: 4, size: 64, elements: !16) -!16 = !{!17, !18} -!17 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !15, file: !1, line: 5, baseType: !8, size: 32) -!18 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !15, file: !1, line: 6, baseType: !8, size: 32, offset: 32) -!19 = !{!20} -!20 = !DILocalVariable(name: "p", arg: 1, scope: !5, file: !1, line: 15, type: !9) -!21 = !DILocation(line: 0, scope: !5) -!22 = !DILocation(line: 16, column: 13, scope: !5) -!23 = !DILocation(line: 16, column: 15, scope: !5) -!24 = !{!25, !26, i64 12} -!25 = !{!"bar", !26, i64 0, !26, i64 4, !29, i64 8} -!26 = !{!"int", !27, i64 0} -!27 = !{!"omnipotent char", !28, i64 0} -!28 = !{!"Simple C/C++ TBAA"} -!29 = !{!"foo", !26, i64 0, !26, i64 4} -!30 = !DILocation(line: 16, column: 3, scope: !5) diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-align.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-align.ll deleted file mode 100644 index 019c93c424b1..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-align.ll +++ /dev/null @@ -1,67 +0,0 @@ -; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check that getelementptr.and.load unroll restores alignment spec. -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; -; typedef int aligned_int __attribute__((aligned(128))); -; -; struct foo { -; int _; -; aligned_int a; -; } __ctx; -; -; extern void consume(int); -; -; void bar(struct foo *p) { -; consume(p->a); -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=sroa,bpf-preserve-static-offset -S -o - - -%struct.foo = type { i32, [124 x i8], i32, [124 x i8] } - -; Function Attrs: nounwind -define dso_local void @bar(ptr noundef %p) #0 { -entry: - %a1 = call i32 (ptr, i1, i8, i8, i8, i1, ...) - @llvm.bpf.getelementptr.and.load.i32 - (ptr readonly elementtype(%struct.foo) %p, - i1 false, i8 0, i8 1, i8 7, i1 true, i32 immarg 0, i32 immarg 2) - #4, !tbaa !2 - call void @consume(i32 noundef %a1) - ret void -} - -; CHECK: define dso_local void @bar(ptr noundef %[[p:.*]]) -; CHECK: %[[a11:.*]] = getelementptr inbounds %struct.foo, ptr %[[p]], i32 0, i32 2 -; CHECK: %[[v2:.*]] = load i32, ptr %[[a11]], align 128 -; CHECK: call void @consume(i32 noundef %[[v2]]) - -declare void @consume(i32 noundef) #1 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #2 - -; Function Attrs: nocallback nofree nounwind willreturn -declare i32 @llvm.bpf.getelementptr.and.load.i32(ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #3 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -attributes #3 = { nocallback nofree nounwind willreturn } -attributes #4 = { memory(argmem: read) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !4, i64 128} -!3 = !{!"foo", !4, i64 0, !4, i64 128} -!4 = !{!"int", !5, i64 0} -!5 = !{!"omnipotent char", !6, i64 0} -!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain-oob.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain-oob.ll deleted file mode 100644 index d8fa3482b6cc..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain-oob.ll +++ /dev/null @@ -1,74 +0,0 @@ -; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check that getelementptr.and.load unroll can skip 'inbounds' flag. -; -; Source (IR modified by hand): -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct bar { -; int aa; -; int bb; -; }; -; -; struct foo { -; int a; -; struct bar b; -; } __ctx; -; -; extern void consume(int); -; -; void buz(struct foo *p) { -; consume(p->b.bb); -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=sroa,bpf-preserve-static-offset -S -o - -; -; Modified to set 'inbounds' flag to false. - -%struct.foo = type { i32, %struct.bar } -%struct.bar = type { i32, i32 } - -; Function Attrs: nounwind -define dso_local void @buz(ptr noundef %p) #0 { -entry: - %bb1 = call i32 (ptr, i1, i8, i8, i8, i1, ...) - @llvm.bpf.getelementptr.and.load.i32 - (ptr readonly elementtype(%struct.foo) %p, - i1 false, i8 0, i8 1, i8 2, i1 false, i32 immarg 0, i32 immarg 1, i32 immarg 1) - #4, !tbaa !2 - call void @consume(i32 noundef %bb1) - ret void -} - -; CHECK: define dso_local void @buz(ptr noundef %[[p:.*]]) -; CHECK: %[[bb11:.*]] = getelementptr %struct.foo, ptr %[[p]], i32 0, i32 1, i32 1 -; CHECK: %[[v2:.*]] = load i32, ptr %[[bb11]], align 4 -; CHECK: call void @consume(i32 noundef %[[v2]]) - -declare void @consume(i32 noundef) #1 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #2 - -; Function Attrs: nocallback nofree nounwind willreturn -declare i32 @llvm.bpf.getelementptr.and.load.i32(ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #3 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -attributes #3 = { nocallback nofree nounwind willreturn } -attributes #4 = { memory(argmem: read) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !4, i64 8} -!3 = !{!"foo", !4, i64 0, !7, i64 4} -!4 = !{!"int", !5, i64 0} -!5 = !{!"omnipotent char", !6, i64 0} -!6 = !{!"Simple C/C++ TBAA"} -!7 = !{!"bar", !4, i64 0, !4, i64 4} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain-u8.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain-u8.ll deleted file mode 100644 index ac6f830bf5d4..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain-u8.ll +++ /dev/null @@ -1,68 +0,0 @@ -; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check unroll of getelementptr.and.load when direct memory offset is -; used instead of field indexes. -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct foo { -; char aa; -; char bb; -; }; -; -; struct bar { -; char a; -; struct foo b; -; } __ctx; -; -; extern void consume(char); -; -; void buz(struct bar *p) { -; consume(((struct foo *)(((char*)&p->b) + 1))->bb); -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=sroa,bpf-preserve-static-offset -S -o - - -; Function Attrs: nounwind -define dso_local void @buz(ptr noundef %p) #0 { -entry: - %bb1 = call i8 (ptr, i1, i8, i8, i8, i1, ...) - @llvm.bpf.getelementptr.and.load.i8 - (ptr readonly elementtype(i8) %p, - i1 false, i8 0, i8 1, i8 0, i1 true, i64 immarg 3) - #4, !tbaa !2 - call void @consume(i8 noundef signext %bb1) - ret void -} - -; CHECK: define dso_local void @buz(ptr noundef %[[p:.*]]) -; CHECK: %[[bb11:.*]] = getelementptr inbounds i8, ptr %[[p]], i64 3 -; CHECK: %[[v2:.*]] = load i8, ptr %[[bb11]], align 1 -; CHECK: call void @consume(i8 noundef signext %[[v2]]) - -declare void @consume(i8 noundef signext) #1 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #2 - -; Function Attrs: nocallback nofree nounwind willreturn -declare i8 @llvm.bpf.getelementptr.and.load.i8(ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #3 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -attributes #3 = { nocallback nofree nounwind willreturn } -attributes #4 = { memory(argmem: read) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !4, i64 1} -!3 = !{!"foo", !4, i64 0, !4, i64 1} -!4 = !{!"omnipotent char", !5, i64 0} -!5 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain.ll deleted file mode 100644 index d6ffb270529a..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain.ll +++ /dev/null @@ -1,73 +0,0 @@ -; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check unroll of getelementptr.and.load when several field indexes -; are specified in a chain. -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct bar { -; int aa; -; int bb; -; }; -; -; struct foo { -; int a; -; struct bar b; -; } __ctx; -; -; extern void consume(int); -; -; void buz(struct foo *p) { -; consume(p->b.bb); -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=sroa,bpf-preserve-static-offset -S -o - - -%struct.foo = type { i32, %struct.bar } -%struct.bar = type { i32, i32 } - -; Function Attrs: nounwind -define dso_local void @buz(ptr noundef %p) #0 { -entry: - %bb1 = call i32 (ptr, i1, i8, i8, i8, i1, ...) - @llvm.bpf.getelementptr.and.load.i32 - (ptr readonly elementtype(%struct.foo) %p, - i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1, i32 immarg 1) - #4, !tbaa !2 - call void @consume(i32 noundef %bb1) - ret void -} - -; CHECK: define dso_local void @buz(ptr noundef %[[p:.*]]) -; CHECK: %[[bb11:.*]] = getelementptr inbounds %struct.foo, ptr %[[p]], i32 0, i32 1, i32 1 -; CHECK: %[[v2:.*]] = load i32, ptr %[[bb11]], align 4 -; CHECK: call void @consume(i32 noundef %[[v2]]) - -declare void @consume(i32 noundef) #1 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #2 - -; Function Attrs: nocallback nofree nounwind willreturn -declare i32 @llvm.bpf.getelementptr.and.load.i32(ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #3 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -attributes #3 = { nocallback nofree nounwind willreturn } -attributes #4 = { memory(argmem: read) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !4, i64 8} -!3 = !{!"foo", !4, i64 0, !7, i64 4} -!4 = !{!"int", !5, i64 0} -!5 = !{!"omnipotent char", !6, i64 0} -!6 = !{!"Simple C/C++ TBAA"} -!7 = !{!"bar", !4, i64 0, !4, i64 4} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-simple.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-simple.ll deleted file mode 100644 index ae19dd7ad98d..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-simple.ll +++ /dev/null @@ -1,65 +0,0 @@ -; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check unroll of getelementptr.and.load. -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct foo { -; int a; -; int b; -; } __ctx; -; -; extern void consume(int); -; -; void bar(struct foo *p){ -; consume(p->b); -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=sroa,bpf-preserve-static-offset -S -o - - -%struct.foo = type { i32, i32 } - -; Function Attrs: nounwind -define dso_local void @bar(ptr noundef %p) #0 { -entry: - %b1 = call i32 (ptr, i1, i8, i8, i8, i1, ...) - @llvm.bpf.getelementptr.and.load.i32 - (ptr readonly elementtype(%struct.foo) %p, - i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1) - #4, !tbaa !2 - call void @consume(i32 noundef %b1) - ret void -} - -; CHECK: define dso_local void @bar(ptr noundef %[[p:.*]]) #[[v1:.*]] { -; CHECK: %[[b11:.*]] = getelementptr inbounds %struct.foo, ptr %[[p]], i32 0, i32 1 -; CHECK-NEXT: %[[v2:.*]] = load i32, ptr %[[b11]], align 4 -; CHECK-NEXT: call void @consume(i32 noundef %[[v2]]) - -declare void @consume(i32 noundef) #1 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #2 - -; Function Attrs: nocallback nofree nounwind willreturn -declare i32 @llvm.bpf.getelementptr.and.load.i32(ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #3 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -attributes #3 = { nocallback nofree nounwind willreturn } -attributes #4 = { memory(argmem: read) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !4, i64 4} -!3 = !{!"foo", !4, i64 0, !4, i64 4} -!4 = !{!"int", !5, i64 0} -!5 = !{!"omnipotent char", !6, i64 0} -!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-volatile.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-volatile.ll deleted file mode 100644 index d9634a3fc3a9..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-volatile.ll +++ /dev/null @@ -1,64 +0,0 @@ -; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check that unroll of getelementptr.and.load restores volatile. -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct foo { -; int a; -; volatile int b; -; } __ctx; -; -; extern void consume(int); -; -; void bar(struct foo *p){ -; consume(p->b); -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=sroa,bpf-preserve-static-offset -S -o - - -%struct.foo = type { i32, i32 } - -; Function Attrs: nounwind -define dso_local void @bar(ptr noundef %p) #0 { -entry: - %b1 = call i32 (ptr, i1, i8, i8, i8, i1, ...) - @llvm.bpf.getelementptr.and.load.i32 - (ptr elementtype(%struct.foo) %p, - i1 true, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1), - !tbaa !2 - call void @consume(i32 noundef %b1) - ret void -} - -; CHECK: define dso_local void @bar(ptr noundef %[[p:.*]]) -; CHECK: %[[b11:.*]] = getelementptr inbounds %struct.foo, ptr %[[p]], i32 0, i32 1 -; CHECK: %[[v2:.*]] = load volatile i32, ptr %[[b11]], align 4 -; CHECK: call void @consume(i32 noundef %[[v2]]) - -declare void @consume(i32 noundef) #1 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #2 - -; Function Attrs: nocallback nofree nounwind willreturn -declare i32 @llvm.bpf.getelementptr.and.load.i32(ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #3 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -attributes #3 = { nocallback nofree nounwind willreturn } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !4, i64 4} -!3 = !{!"foo", !4, i64 0, !4, i64 4} -!4 = !{!"int", !5, i64 0} -!5 = !{!"omnipotent char", !6, i64 0} -!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-union-pai.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-union-pai.ll deleted file mode 100644 index f90e3c54b072..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/load-union-pai.ll +++ /dev/null @@ -1,110 +0,0 @@ -; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; #define __pai __attribute__((preserve_access_index)) -; -; struct foo { -; char a[10]; -; } __pai; -; -; struct bar { -; int a; -; int b; -; } __pai; -; -; union buz { -; struct foo a; -; struct bar b; -; } __pai __ctx; -; -; int quux(union buz *p) { -; return p->b.b; -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -debug-info-kind=limited -o - \ -; | opt -passes=function(sroa) -S -o - - -%struct.bar = type { i32, i32 } - -; Function Attrs: nounwind -define dso_local i32 @quux(ptr noundef %p) #0 !dbg !5 { -entry: - call void @llvm.dbg.value(metadata ptr %p, metadata !26, metadata !DIExpression()), !dbg !27 - %0 = call ptr @llvm.preserve.static.offset(ptr %p), !dbg !28 - %1 = call ptr @llvm.preserve.union.access.index.p0.p0(ptr %0, i32 1), !dbg !28, !llvm.preserve.access.index !10 - %2 = call ptr @llvm.preserve.struct.access.index.p0.p0(ptr elementtype(%struct.bar) %1, i32 1, i32 1), !dbg !29, !llvm.preserve.access.index !21 - %3 = load i32, ptr %2, align 4, !dbg !29, !tbaa !30 - ret i32 %3, !dbg !33 -} - -; CHECK: define dso_local i32 @quux(ptr noundef %[[p:.*]]) {{.*}} { -; CHECK-NEXT: entry: -; CHECK-NEXT: call void @llvm.dbg.value -; CHECK-NEXT: %[[v5:.*]] = call i32 (ptr, i1, i8, i8, i8, i1, ...) -; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 -; CHECK-SAME: (ptr readonly elementtype(%struct.bar) %[[p]], -; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1) -; CHECK-SAME: #[[v6:.*]], !tbaa -; CHECK-NEXT: ret i32 %[[v5]] -; CHECK-NEXT: } -; CHECK: attributes #[[v6]] = { memory(argmem: read) } - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #1 - -; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) -declare ptr @llvm.preserve.union.access.index.p0.p0(ptr, i32 immarg) #2 - -; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) -declare ptr @llvm.preserve.struct.access.index.p0.p0(ptr, i32 immarg, i32 immarg) #2 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare void @llvm.dbg.value(metadata, metadata, metadata) #1 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } - -!llvm.dbg.cu = !{!0} -!llvm.module.flags = !{!2, !3} -!llvm.ident = !{!4} - -!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) -!1 = !DIFile(filename: "some-file.c", directory: "/some/dir/") -!2 = !{i32 2, !"Debug Info Version", i32 3} -!3 = !{i32 1, !"wchar_size", i32 4} -!4 = !{!"clang"} -!5 = distinct !DISubprogram(name: "quux", scope: !1, file: !1, line: 18, type: !6, scopeLine: 18, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !25) -!6 = !DISubroutineType(types: !7) -!7 = !{!8, !9} -!8 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) -!9 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !10, size: 64) -!10 = distinct !DICompositeType(tag: DW_TAG_union_type, name: "buz", file: !1, line: 13, size: 96, elements: !11) -!11 = !{!12, !20} -!12 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !10, file: !1, line: 14, baseType: !13, size: 80) -!13 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "foo", file: !1, line: 4, size: 80, elements: !14) -!14 = !{!15} -!15 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !13, file: !1, line: 5, baseType: !16, size: 80) -!16 = !DICompositeType(tag: DW_TAG_array_type, baseType: !17, size: 80, elements: !18) -!17 = !DIBasicType(name: "char", size: 8, encoding: DW_ATE_signed_char) -!18 = !{!19} -!19 = !DISubrange(count: 10) -!20 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !10, file: !1, line: 15, baseType: !21, size: 64) -!21 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "bar", file: !1, line: 8, size: 64, elements: !22) -!22 = !{!23, !24} -!23 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !21, file: !1, line: 9, baseType: !8, size: 32) -!24 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !21, file: !1, line: 10, baseType: !8, size: 32, offset: 32) -!25 = !{!26} -!26 = !DILocalVariable(name: "p", arg: 1, scope: !5, file: !1, line: 18, type: !9) -!27 = !DILocation(line: 0, scope: !5) -!28 = !DILocation(line: 19, column: 13, scope: !5) -!29 = !DILocation(line: 19, column: 15, scope: !5) -!30 = !{!31, !31, i64 0} -!31 = !{!"omnipotent char", !32, i64 0} -!32 = !{!"Simple C/C++ TBAA"} -!33 = !DILocation(line: 19, column: 3, scope: !5) diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-unroll-inline.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-unroll-inline.ll deleted file mode 100644 index 78172cd17dca..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/load-unroll-inline.ll +++ /dev/null @@ -1,108 +0,0 @@ -; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check position of bpf-preserve-static-offset pass in the pipeline: -; - preserve.static.offset call is preserved if address is passed as -; a parameter to an inline-able function; -; - second bpf-preserve-static-offset pass (after inlining) should introduce -; getelementptr.and.load call using the preserved marker after loops -; unrolling; -; - readonly and tbaa attributes should allow replacement of -; getelementptr.and.load calls by CSE transformation. -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct foo { -; int a; -; int b[4]; -; } __ctx; -; -; extern void consume(int); -; -; static inline void bar(int * restrict p) { -; consume(p[1]); -; } -; -; void quux(struct foo *p){ -; unsigned long i = 0; -; #pragma clang loop unroll(full) -; while (i < 2) { -; bar(p->b); -; ++i; -; } -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=function(sroa) -S -o - - -%struct.foo = type { i32, [4 x i32] } - -; Function Attrs: nounwind -define dso_local void @quux(ptr noundef %p) #0 { -entry: - br label %while.cond - -while.cond: ; preds = %while.body, %entry - %i.0 = phi i64 [ 0, %entry ], [ %inc, %while.body ] - %cmp = icmp ult i64 %i.0, 2 - br i1 %cmp, label %while.body, label %while.end - -while.body: ; preds = %while.cond - %0 = call ptr @llvm.preserve.static.offset(ptr %p) - %b = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 - %arraydecay = getelementptr inbounds [4 x i32], ptr %b, i64 0, i64 0 - call void @bar(ptr noundef %arraydecay) - %inc = add i64 %i.0, 1 - br label %while.cond, !llvm.loop !2 - -while.end: ; preds = %while.cond - ret void -} - -; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) -declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1 - -; Function Attrs: inlinehint nounwind -define internal void @bar(ptr noalias noundef %p) #2 { -entry: - %arrayidx = getelementptr inbounds i32, ptr %p, i64 1 - %0 = load i32, ptr %arrayidx, align 4, !tbaa !5 - call void @consume(i32 noundef %0) - ret void -} - -; CHECK: define dso_local void @quux(ptr nocapture noundef readonly %[[p:.*]]) -; CHECK: %[[v1:.*]] = tail call i32 (ptr, i1, i8, i8, i8, i1, ...) -; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 -; CHECK-SAME: (ptr readonly elementtype(%struct.foo) %[[p]], -; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i64 immarg 0, i32 immarg 1, i64 immarg 1) -; CHECK: tail call void @consume(i32 noundef %[[v1]]) -; CHECK: tail call void @consume(i32 noundef %[[v1]]) - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #3 - -; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) -declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1 - -declare void @consume(i32 noundef) #4 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } -attributes #2 = { inlinehint nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -attributes #4 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = distinct !{!2, !3, !4} -!3 = !{!"llvm.loop.mustprogress"} -!4 = !{!"llvm.loop.unroll.full"} -!5 = !{!6, !6, i64 0} -!6 = !{!"int", !7, i64 0} -!7 = !{!"omnipotent char", !8, i64 0} -!8 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-unroll.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-unroll.ll deleted file mode 100644 index 7c3303342bb6..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/load-unroll.ll +++ /dev/null @@ -1,95 +0,0 @@ -; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check position of bpf-preserve-static-offset pass in the pipeline: -; preserve.static.offset call should be preserved long enough to allow -; introduction of getelementptr.and.load after loops unrolling. -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct foo { -; int a; -; int b[4]; -; } __ctx; -; -; extern void consume(int); -; -; void bar(struct foo *p){ -; unsigned long i = 0; -; #pragma clang loop unroll(full) -; while (i < 2) -; consume(p->b[i++]); -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=function(sroa) -S -o - - -%struct.foo = type { i32, [4 x i32] } - -; Function Attrs: nounwind -define dso_local void @bar(ptr noundef %p) #0 { -entry: - br label %while.cond - -while.cond: ; preds = %while.body, %entry - %i.0 = phi i64 [ 0, %entry ], [ %inc, %while.body ] - %cmp = icmp ult i64 %i.0, 2 - br i1 %cmp, label %while.body, label %while.end - -while.body: ; preds = %while.cond - %0 = call ptr @llvm.preserve.static.offset(ptr %p) - %b = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 - %inc = add i64 %i.0, 1 - %arrayidx = getelementptr inbounds [4 x i32], ptr %b, i64 0, i64 %i.0 - %1 = load i32, ptr %arrayidx, align 4, !tbaa !2 - call void @consume(i32 noundef %1) - br label %while.cond, !llvm.loop !6 - -while.end: ; preds = %while.cond - ret void -} - -; CHECK: define dso_local void @bar(ptr nocapture noundef readonly %[[p:.*]]) -; CHECK: %[[v1:.*]] = tail call i32 (ptr, i1, i8, i8, i8, i1, ...) -; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 -; CHECK-SAME: (ptr readonly elementtype(%struct.foo) %[[p]], -; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i64 immarg 0, i32 immarg 1, i64 immarg 0) -; CHECK-SAME: #[[attrs:.*]], !tbaa -; CHECK-NEXT: tail call void @consume(i32 noundef %[[v1]]) -; CHECK-NEXT: %[[v2:.*]] = tail call i32 (ptr, i1, i8, i8, i8, i1, ...) -; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 -; CHECK-SAME: (ptr readonly elementtype(%struct.foo) %[[p]], -; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i64 immarg 0, i32 immarg 1, i64 immarg 1) -; CHECK-SAME: #[[attrs]], !tbaa -; CHECK-NEXT: tail call void @consume(i32 noundef %[[v2]]) -; CHECK: attributes #[[attrs]] = { memory(argmem: read) } - -; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) -declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1 - -declare void @consume(i32 noundef) #2 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #3 - -; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) -declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } -attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !3, i64 0} -!3 = !{!"int", !4, i64 0} -!4 = !{!"omnipotent char", !5, i64 0} -!5 = !{!"Simple C/C++ TBAA"} -!6 = distinct !{!6, !7, !8} -!7 = !{!"llvm.loop.mustprogress"} -!8 = !{!"llvm.loop.unroll.full"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-volatile.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-volatile.ll deleted file mode 100644 index 819a4b31fb23..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/load-volatile.ll +++ /dev/null @@ -1,62 +0,0 @@ -; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check handling of a volatile load instruction by bpf-preserve-static-offset. -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct foo { -; int _; -; volatile int a; -; } __ctx; -; -; extern void consume(int); -; -; void bar(struct foo *p) { -; consume(p->a); -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=function(sroa) -S -o - - -%struct.foo = type { i32, i32 } - -; Function Attrs: nounwind -define dso_local void @bar(ptr noundef %p) #0 { -entry: - %0 = call ptr @llvm.preserve.static.offset(ptr %p) - %a = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 - %1 = load volatile i32, ptr %a, align 4, !tbaa !2 - call void @consume(i32 noundef %1) - ret void -} - -; CHECK: %[[a1:.*]] = call i32 (ptr, i1, i8, i8, i8, i1, ...) -; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 -; CHECK-SAME: (ptr elementtype(%struct.foo) %{{[^,]+}}, -; CHECK-SAME: i1 true, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1) -; ^^^^^^^^ -; volatile -; CHECK-NOT: #{{[0-9]+}} -; CHECK-NEXT: call void @consume(i32 noundef %[[a1]]) - -declare void @consume(i32 noundef) #1 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #2 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !4, i64 4} -!3 = !{!"foo", !4, i64 0, !4, i64 4} -!4 = !{!"int", !5, i64 0} -!5 = !{!"omnipotent char", !6, i64 0} -!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-zero.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-zero.ll deleted file mode 100644 index 681c9640cbb8..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/load-zero.ll +++ /dev/null @@ -1,57 +0,0 @@ -; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check that loads from zero offset are not modified by bpf-preserve-static-offset. -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct foo { -; int a; -; } __ctx; -; -; extern void consume(int); -; -; void bar(struct foo *p) { -; consume(p->a); -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=function(sroa) -S -o - - -%struct.foo = type { i32 } - -; Function Attrs: nounwind -define dso_local void @bar(ptr noundef %p) #0 { -entry: - %0 = call ptr @llvm.preserve.static.offset(ptr %p) - %a = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 0 - %1 = load i32, ptr %a, align 4, !tbaa !2 - call void @consume(i32 noundef %1) - ret void -} - -; CHECK: entry: -; CHECK-NEXT: %[[a:.*]] = getelementptr inbounds %struct.foo, ptr %[[p:.*]], i32 0, i32 0 -; CHECK-NEXT: %[[v2:.*]] = load i32, ptr %[[a]], align 4, !tbaa -; CHECK-NEXT: call void @consume(i32 noundef %[[v2]]) - -declare void @consume(i32 noundef) #1 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #2 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !4, i64 0} -!3 = !{!"foo", !4, i64 0} -!4 = !{!"int", !5, i64 0} -!5 = !{!"omnipotent char", !6, i64 0} -!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-align.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-align.ll deleted file mode 100644 index 667f8f5a8d8b..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/store-align.ll +++ /dev/null @@ -1,59 +0,0 @@ -; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check handling of a store instruction for a field with non-standard -; alignment by bpf-preserve-static-offset. -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; -; typedef int aligned_int __attribute__((aligned(128))); -; -; struct foo { -; int _; -; aligned_int a; -; } __ctx; -; -; void bar(struct foo *p) { -; p->a = 7; -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=function(sroa) -S -o - - -%struct.foo = type { i32, [124 x i8], i32, [124 x i8] } - -; Function Attrs: nounwind -define dso_local void @bar(ptr noundef %p) #0 { -entry: - %0 = call ptr @llvm.preserve.static.offset(ptr %p) - %a = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 2 - store i32 7, ptr %a, align 128, !tbaa !2 - ret void -} - -; CHECK: define dso_local void @bar(ptr nocapture noundef writeonly %[[p:.*]]) -; CHECK: tail call void (i32, ptr, i1, i8, i8, i8, i1, ...) -; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i32 -; CHECK-SAME: (i32 7, -; CHECK-SAME: ptr writeonly elementtype(%struct.foo) %[[p]], -; CHECK-SAME: i1 false, i8 0, i8 1, i8 7, i1 true, i32 immarg 0, i32 immarg 2) -; CHECK-SAME: #[[v2:.*]], !tbaa -; CHECK: attributes #[[v2]] = { memory(argmem: write) } - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #1 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !4, i64 128} -!3 = !{!"foo", !4, i64 0, !4, i64 128} -!4 = !{!"int", !5, i64 0} -!5 = !{!"omnipotent char", !6, i64 0} -!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-atomic.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-atomic.ll deleted file mode 100644 index 443966337b9d..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/store-atomic.ll +++ /dev/null @@ -1,60 +0,0 @@ -; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check handling of atomic store instruction by bpf-preserve-static-offset. -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct foo { -; int _; -; int a; -; } __ctx; -; -; void bar(struct foo *p) { -; int r; -; r = 7; -; __atomic_store(&p->a, &r, 3); -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=function(sroa) -S -o - - -%struct.foo = type { i32, i32 } - -; Function Attrs: nounwind -define dso_local void @bar(ptr noundef %p) #0 { -entry: - %0 = call ptr @llvm.preserve.static.offset(ptr %p) - %a = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 - store atomic i32 7, ptr %a release, align 4 - ret void -} - -; CHECK: define dso_local void @bar(ptr nocapture noundef %[[p:.*]]) -; CHECK: tail call void (i32, ptr, i1, i8, i8, i8, i1, ...) -; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i32 -; CHECK-SAME: (i32 7, -; CHECK-SAME: ptr elementtype(%struct.foo) %[[p]], -; CHECK-SAME: i1 false, i8 5, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1) -; CHECK-NOT: #{{[0-9]+}} -; CHECK-NEXT: ret void - -; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) -declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #2 - -; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) -declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } -attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-2.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-2.ll deleted file mode 100644 index 49f3fa5b8383..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-2.ll +++ /dev/null @@ -1,77 +0,0 @@ -; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check that bpf-preserve-static-offset folds GEP chains that end by -; getelementptr.and.store. -; -; Source (modified by hand): -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct bar { -; int aa; -; int bb; -; }; -; -; struct foo { -; int a; -; struct bar b; -; } __ctx; -; -; void buz(struct foo *p) { -; p->b.bb = 42; -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=function(sroa) -S -o - -; -; And modified to fold last getelementptr/store as a single -; getelementptr.and.store. - -%struct.foo = type { i32, %struct.bar } -%struct.bar = type { i32, i32 } - -; Function Attrs: nounwind -define dso_local void @buz(ptr noundef %p) #0 { -entry: - %0 = call ptr @llvm.preserve.static.offset(ptr %p) - %b = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 - call void (i32, ptr, i1, i8, i8, i8, i1, ...) - @llvm.bpf.getelementptr.and.store.i32 - (i32 42, - ptr writeonly elementtype(%struct.bar) %b, - i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1) - #3, !tbaa !2 - ret void -} - -; CHECK: define dso_local void @buz(ptr noundef %[[p:.*]]) -; CHECK: call void (i32, ptr, i1, i8, i8, i8, i1, ...) -; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i32 -; CHECK-SAME: (i32 42, -; CHECK-SAME: ptr writeonly elementtype(%struct.foo) %[[p]], -; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1, i32 immarg 1) -; CHECK-SAME: #[[v2:.*]], !tbaa -; CHECK: attributes #[[v2]] = { memory(argmem: write) } - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #1 - -; Function Attrs: nocallback nofree nounwind willreturn -declare void @llvm.bpf.getelementptr.and.store.i32(i32, ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #2 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -attributes #2 = { nocallback nofree nounwind willreturn } -attributes #3 = { memory(argmem: write) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !4, i64 8} -!3 = !{!"foo", !4, i64 0, !7, i64 4} -!4 = !{!"int", !5, i64 0} -!5 = !{!"omnipotent char", !6, i64 0} -!6 = !{!"Simple C/C++ TBAA"} -!7 = !{!"bar", !4, i64 0, !4, i64 4} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-oob.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-oob.ll deleted file mode 100644 index e2878f091303..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-oob.ll +++ /dev/null @@ -1,67 +0,0 @@ -; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check that bpf-preserve-static-offset keeps track of 'inbounds' flags while -; folding chain of GEP instructions. -; -; Source (IR modified by hand): -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct bar { -; int aa; -; int bb; -; }; -; -; struct foo { -; int a; -; struct bar b; -; } __ctx; -; -; void buz(struct foo *p) { -; p->b.bb = 42; -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=function(sroa) -S -o - -; -; Modified to remove one of the 'inbounds' from one of the GEP instructions. - -%struct.foo = type { i32, %struct.bar } -%struct.bar = type { i32, i32 } - -; Function Attrs: nounwind -define dso_local void @buz(ptr noundef %p) #0 { -entry: - %0 = call ptr @llvm.preserve.static.offset(ptr %p) - %b = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 - %bb = getelementptr %struct.bar, ptr %b, i32 0, i32 1 - store i32 42, ptr %bb, align 4, !tbaa !2 - ret void -} - -; CHECK: define dso_local void @buz(ptr nocapture noundef writeonly %[[p:.*]]) -; CHECK: tail call void (i32, ptr, i1, i8, i8, i8, i1, ...) -; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i32 -; CHECK-SAME: (i32 42, -; CHECK-SAME: ptr writeonly elementtype(%struct.foo) %[[p]], -; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 false, i32 immarg 0, i32 immarg 1, i32 immarg 1) -; CHECK-SAME: #[[v2:.*]], !tbaa -; CHECK: attributes #[[v2]] = { memory(argmem: write) } - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #1 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !4, i64 8} -!3 = !{!"foo", !4, i64 0, !7, i64 4} -!4 = !{!"int", !5, i64 0} -!5 = !{!"omnipotent char", !6, i64 0} -!6 = !{!"Simple C/C++ TBAA"} -!7 = !{!"bar", !4, i64 0, !4, i64 4} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-u8-oob.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-u8-oob.ll deleted file mode 100644 index a33732546677..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-u8-oob.ll +++ /dev/null @@ -1,67 +0,0 @@ -; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check that bpf-preserve-static-offset folds chain of GEP instructions. -; The GEP chain in this example has type mismatch and thus is -; folded as i8 access. -; -; Source (modified by hand): -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct foo { -; char aa; -; char bb; -; }; -; -; struct bar { -; char a; -; struct foo b; -; } __ctx; -; -; void buz(struct bar *p) { -; ((struct foo *)(((char*)&p->b) + 1))->bb = 42; -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=function(sroa) -S -o - -; -; Modified to remove one of the 'inbounds' from one of the getelementptr. - -%struct.bar = type { i8, %struct.foo } -%struct.foo = type { i8, i8 } - -; Function Attrs: nounwind -define dso_local void @buz(ptr noundef %p) #0 { -entry: - %0 = call ptr @llvm.preserve.static.offset(ptr %p) - %b = getelementptr inbounds %struct.bar, ptr %0, i32 0, i32 1 - %add.ptr = getelementptr i8, ptr %b, i64 1 - %bb = getelementptr inbounds %struct.foo, ptr %add.ptr, i32 0, i32 1 - store i8 42, ptr %bb, align 1, !tbaa !2 - ret void -} - -; CHECK: define dso_local void @buz(ptr nocapture noundef writeonly %[[p:.*]]) -; CHECK: tail call void (i8, ptr, i1, i8, i8, i8, i1, ...) -; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i8 -; CHECK-SAME: (i8 42, -; CHECK-SAME: ptr writeonly elementtype(i8) %[[p]], -; CHECK-SAME: i1 false, i8 0, i8 1, i8 0, i1 false, i64 immarg 3) -; CHECK-SAME: #[[v2:.*]], !tbaa ![[v3:.*]] -; CHECK: attributes #[[v2]] = { memory(argmem: write) } - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #1 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !4, i64 1} -!3 = !{!"foo", !4, i64 0, !4, i64 1} -!4 = !{!"omnipotent char", !5, i64 0} -!5 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-u8.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-u8.ll deleted file mode 100644 index 92740603ae69..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-u8.ll +++ /dev/null @@ -1,68 +0,0 @@ -; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check that bpf-preserve-static-offset folds chain of GEP instructions. -; The GEP chain in this example has type mismatch and thus is -; folded as i8 access. -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct foo { -; char aa; -; char bb; -; }; -; -; struct bar { -; char a; -; struct foo b; -; } __ctx; -; -; void buz(struct bar *p) { -; ((struct foo *)(((char*)&p->b) + 1))->bb = 42; -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=function(sroa) -S -o - - -%struct.bar = type { i8, %struct.foo } -%struct.foo = type { i8, i8 } - -; Function Attrs: nounwind -define dso_local void @buz(ptr noundef %p) #0 { -entry: - %0 = call ptr @llvm.preserve.static.offset(ptr %p) - %b = getelementptr inbounds %struct.bar, ptr %0, i32 0, i32 1 - %add.ptr = getelementptr inbounds i8, ptr %b, i64 1 -; ~~ -; these types do not match, thus GEP chain is folded as an offset -; ~~~~~~~~~~~ - %bb = getelementptr inbounds %struct.foo, ptr %add.ptr, i32 0, i32 1 - store i8 42, ptr %bb, align 1, !tbaa !2 - ret void -} - -; CHECK: define dso_local void @buz(ptr nocapture noundef writeonly %[[p:.*]]) -; CHECK: tail call void (i8, ptr, i1, i8, i8, i8, i1, ...) -; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i8 -; CHECK-SAME: (i8 42, -; CHECK-SAME: ptr writeonly elementtype(i8) %[[p]], -; CHECK-SAME: i1 false, i8 0, i8 1, i8 0, i1 true, i64 immarg 3) -; CHECK-SAME: #[[v2:.*]], !tbaa ![[v3:.*]] -; CHECK: attributes #[[v2]] = { memory(argmem: write) } - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #1 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !4, i64 1} -!3 = !{!"foo", !4, i64 0, !4, i64 1} -!4 = !{!"omnipotent char", !5, i64 0} -!5 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain.ll deleted file mode 100644 index d4c90616bf5c..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain.ll +++ /dev/null @@ -1,64 +0,0 @@ -; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check that bpf-preserve-static-offset folds chain of GEP instructions. -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct bar { -; int aa; -; int bb; -; }; -; -; struct foo { -; int a; -; struct bar b; -; } __ctx; -; -; void buz(struct foo *p) { -; p->b.bb = 42; -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=function(sroa) -S -o - - -%struct.foo = type { i32, %struct.bar } -%struct.bar = type { i32, i32 } - -; Function Attrs: nounwind -define dso_local void @buz(ptr noundef %p) #0 { -entry: - %0 = call ptr @llvm.preserve.static.offset(ptr %p) - %b = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 - %bb = getelementptr inbounds %struct.bar, ptr %b, i32 0, i32 1 - store i32 42, ptr %bb, align 4, !tbaa !2 - ret void -} - -; CHECK: define dso_local void @buz(ptr nocapture noundef writeonly %[[p:.*]]) -; CHECK: tail call void (i32, ptr, i1, i8, i8, i8, i1, ...) -; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i32 -; CHECK-SAME: (i32 42, -; CHECK-SAME: ptr writeonly elementtype(%struct.foo) %[[p]], -; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1, i32 immarg 1) -; CHECK-SAME: #[[v2:.*]], !tbaa -; CHECK: attributes #[[v2]] = { memory(argmem: write) } - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #1 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !4, i64 8} -!3 = !{!"foo", !4, i64 0, !7, i64 4} -!4 = !{!"int", !5, i64 0} -!5 = !{!"omnipotent char", !6, i64 0} -!6 = !{!"Simple C/C++ TBAA"} -!7 = !{!"bar", !4, i64 0, !4, i64 4} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-pai.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-pai.ll deleted file mode 100644 index b22b26836826..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/store-pai.ll +++ /dev/null @@ -1,136 +0,0 @@ -; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; #define __pai __attribute__((preserve_access_index)) -; -; struct foo { -; char a[10]; -; } __pai; -; -; struct bar { -; int a; -; int b; -; } __pai; -; -; struct buz { -; int _1; -; int _2; -; int _3; -; union { -; struct foo a; -; struct bar b[7]; -; }; -; } __pai __ctx; -; -; void quux(struct buz *p) { -; p->b[5].b = 42; -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes \ -; -debug-info-kind=limited -o - \ -; | opt -passes=function(sroa) -S -o - - -%struct.buz = type { i32, i32, i32, %union.anon } -%union.anon = type { [7 x %struct.bar] } -%struct.bar = type { i32, i32 } - -; Function Attrs: nounwind -define dso_local void @quux(ptr noundef %p) #0 !dbg !31 { -entry: - call void @llvm.dbg.value(metadata ptr %p, metadata !36, metadata !DIExpression()), !dbg !37 - %0 = call ptr @llvm.preserve.static.offset(ptr %p), !dbg !38 - %1 = call ptr @llvm.preserve.struct.access.index.p0.p0(ptr elementtype(%struct.buz) %0, i32 3, i32 3), !dbg !38, !llvm.preserve.access.index !4 - %2 = call ptr @llvm.preserve.union.access.index.p0.p0(ptr %1, i32 1), !dbg !38, !llvm.preserve.access.index !3 - %3 = call ptr @llvm.preserve.array.access.index.p0.p0(ptr elementtype([7 x %struct.bar]) %2, i32 1, i32 5), !dbg !39, !llvm.preserve.access.index !21 - %4 = call ptr @llvm.preserve.struct.access.index.p0.p0(ptr elementtype(%struct.bar) %3, i32 1, i32 1), !dbg !40, !llvm.preserve.access.index !22 - store i32 42, ptr %4, align 4, !dbg !41, !tbaa !42 - ret void, !dbg !45 -} - -; CHECK: define dso_local void @quux(ptr noundef %[[p:.*]]) {{.*}} { -; CHECK-NEXT: entry: -; CHECK-NEXT: call void @llvm.dbg.value -; CHECK-NEXT: call void (i32, ptr, i1, i8, i8, i8, i1, ...) -; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i32 -; CHECK-SAME: (i32 42, -; CHECK-SAME: ptr writeonly elementtype(i8) %[[p]], -; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i64 immarg 56) -; CHECK-SAME: #[[v5:.*]], !tbaa -; CHECK-NEXT: ret void, !dbg -; CHECK-NEXT: } -; CHECK: attributes #[[v5]] = { memory(argmem: write) } - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #1 - -; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) -declare ptr @llvm.preserve.struct.access.index.p0.p0(ptr, i32 immarg, i32 immarg) #2 - -; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) -declare ptr @llvm.preserve.union.access.index.p0.p0(ptr, i32 immarg) #2 - -; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) -declare ptr @llvm.preserve.array.access.index.p0.p0(ptr, i32 immarg, i32 immarg) #2 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare void @llvm.dbg.value(metadata, metadata, metadata) #1 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } - -!llvm.dbg.cu = !{!0} -!llvm.module.flags = !{!28, !29} -!llvm.ident = !{!30} - -!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, retainedTypes: !2, splitDebugInlining: false, nameTableKind: None) -!1 = !DIFile(filename: "some-file.c", directory: "/some/dir/") -!2 = !{!3, !21} -!3 = distinct !DICompositeType(tag: DW_TAG_union_type, scope: !4, file: !1, line: 17, size: 448, elements: !11) -!4 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "buz", file: !1, line: 13, size: 544, elements: !5) -!5 = !{!6, !8, !9, !10} -!6 = !DIDerivedType(tag: DW_TAG_member, name: "_1", scope: !4, file: !1, line: 14, baseType: !7, size: 32) -!7 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) -!8 = !DIDerivedType(tag: DW_TAG_member, name: "_2", scope: !4, file: !1, line: 15, baseType: !7, size: 32, offset: 32) -!9 = !DIDerivedType(tag: DW_TAG_member, name: "_3", scope: !4, file: !1, line: 16, baseType: !7, size: 32, offset: 64) -!10 = !DIDerivedType(tag: DW_TAG_member, scope: !4, file: !1, line: 17, baseType: !3, size: 448, offset: 96) -!11 = !{!12, !20} -!12 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !3, file: !1, line: 18, baseType: !13, size: 80) -!13 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "foo", file: !1, line: 4, size: 80, elements: !14) -!14 = !{!15} -!15 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !13, file: !1, line: 5, baseType: !16, size: 80) -!16 = !DICompositeType(tag: DW_TAG_array_type, baseType: !17, size: 80, elements: !18) -!17 = !DIBasicType(name: "char", size: 8, encoding: DW_ATE_signed_char) -!18 = !{!19} -!19 = !DISubrange(count: 10) -!20 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !3, file: !1, line: 19, baseType: !21, size: 448) -!21 = !DICompositeType(tag: DW_TAG_array_type, baseType: !22, size: 448, elements: !26) -!22 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "bar", file: !1, line: 8, size: 64, elements: !23) -!23 = !{!24, !25} -!24 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !22, file: !1, line: 9, baseType: !7, size: 32) -!25 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !22, file: !1, line: 10, baseType: !7, size: 32, offset: 32) -!26 = !{!27} -!27 = !DISubrange(count: 7) -!28 = !{i32 2, !"Debug Info Version", i32 3} -!29 = !{i32 1, !"wchar_size", i32 4} -!30 = !{!"clang"} -!31 = distinct !DISubprogram(name: "quux", scope: !1, file: !1, line: 23, type: !32, scopeLine: 23, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !35) -!32 = !DISubroutineType(types: !33) -!33 = !{null, !34} -!34 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !4, size: 64) -!35 = !{!36} -!36 = !DILocalVariable(name: "p", arg: 1, scope: !31, file: !1, line: 23, type: !34) -!37 = !DILocation(line: 0, scope: !31) -!38 = !DILocation(line: 24, column: 6, scope: !31) -!39 = !DILocation(line: 24, column: 3, scope: !31) -!40 = !DILocation(line: 24, column: 11, scope: !31) -!41 = !DILocation(line: 24, column: 13, scope: !31) -!42 = !{!43, !43, i64 0} -!43 = !{!"omnipotent char", !44, i64 0} -!44 = !{!"Simple C/C++ TBAA"} -!45 = !DILocation(line: 25, column: 1, scope: !31) diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-simple.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-simple.ll deleted file mode 100644 index a603ad866739..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/store-simple.ll +++ /dev/null @@ -1,60 +0,0 @@ -; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check handling of a simple store instruction by bpf-preserve-static-offset. -; Verify: -; - presence of gep.and.store intrinsic call -; - correct attributes for intrinsic call -; - presence of tbaa annotations -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct foo { -; int _; -; int a; -; } __ctx; -; -; void bar(struct foo *p) { -; p->a = 7; -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=function(sroa) -S -o - - -%struct.foo = type { i32, i32 } - -; Function Attrs: nounwind -define dso_local void @bar(ptr noundef %p) #0 { -entry: - %0 = call ptr @llvm.preserve.static.offset(ptr %p) - %a = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 - store i32 7, ptr %a, align 4, !tbaa !2 - ret void -} - -; CHECK: define dso_local void @bar(ptr nocapture noundef writeonly %[[p:.*]]) -; CHECK: tail call void (i32, ptr, i1, i8, i8, i8, i1, ...) -; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i32 -; CHECK-SAME: (i32 7, -; CHECK-SAME: ptr writeonly elementtype(%struct.foo) %[[p]], -; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1) -; CHECK-SAME: #[[v2:.*]], !tbaa -; CHECK: attributes #[[v2]] = { memory(argmem: write) } - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #1 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !4, i64 4} -!3 = !{!"foo", !4, i64 0, !4, i64 4} -!4 = !{!"int", !5, i64 0} -!5 = !{!"omnipotent char", !6, i64 0} -!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-align.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-align.ll deleted file mode 100644 index 7996fe0d1bb2..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-align.ll +++ /dev/null @@ -1,62 +0,0 @@ -; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check that getelementptr.and.store unroll restores alignment spec. -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; -; typedef int aligned_int __attribute__((aligned(128))); -; -; struct foo { -; int _; -; aligned_int a; -; } __ctx; -; -; void bar(struct foo *p) { -; p->a = 42; -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=sroa,bpf-preserve-static-offset -S -o - - -%struct.foo = type { i32, [124 x i8], i32, [124 x i8] } - -; Function Attrs: nounwind -define dso_local void @bar(ptr noundef %p) #0 { -entry: - call void (i32, ptr, i1, i8, i8, i8, i1, ...) - @llvm.bpf.getelementptr.and.store.i32 - (i32 42, - ptr writeonly elementtype(%struct.foo) %p, - i1 false, i8 0, i8 1, i8 7, i1 true, i32 immarg 0, i32 immarg 2) - #3, !tbaa !2 - ret void -} - -; CHECK: define dso_local void @bar(ptr noundef %[[p:.*]]) -; CHECK: %[[v2:.*]] = getelementptr inbounds %struct.foo, ptr %[[p]], i32 0, i32 2 -; CHECK: store i32 42, ptr %[[v2]], align 128 -; CHECK: ret void - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #1 - -; Function Attrs: nocallback nofree nounwind willreturn -declare void @llvm.bpf.getelementptr.and.store.i32(i32, ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #2 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -attributes #2 = { nocallback nofree nounwind willreturn } -attributes #3 = { memory(argmem: write) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !4, i64 128} -!3 = !{!"foo", !4, i64 0, !4, i64 128} -!4 = !{!"int", !5, i64 0} -!5 = !{!"omnipotent char", !6, i64 0} -!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain-oob.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain-oob.ll deleted file mode 100644 index d2731d32ed4c..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain-oob.ll +++ /dev/null @@ -1,67 +0,0 @@ -; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check that getelementptr.and.load unroll can skip 'inbounds' flag. -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct bar { -; int aa; -; int bb; -; }; -; -; struct foo { -; int a; -; struct bar b; -; } __ctx; -; -; void buz(struct foo *p) { -; p->b.bb = 42; -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=sroa,bpf-preserve-static-offset -S -o - - -%struct.foo = type { i32, %struct.bar } -%struct.bar = type { i32, i32 } - -; Function Attrs: nounwind -define dso_local void @buz(ptr noundef %p) #0 { -entry: - call void (i32, ptr, i1, i8, i8, i8, i1, ...) - @llvm.bpf.getelementptr.and.store.i32 - (i32 42, - ptr writeonly elementtype(%struct.foo) %p, - i1 false, i8 0, i8 1, i8 2, i1 false, i32 immarg 0, i32 immarg 1, i32 immarg 1) - #3, !tbaa !2 - ret void -} - -; CHECK: define dso_local void @buz(ptr noundef %[[p:.*]]) -; CHECK: %[[v2:.*]] = getelementptr %struct.foo, ptr %[[p]], i32 0, i32 1, i32 1 -; CHECK: store i32 42, ptr %[[v2]], align 4 -; CHECK: ret void - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #1 - -; Function Attrs: nocallback nofree nounwind willreturn -declare void @llvm.bpf.getelementptr.and.store.i32(i32, ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #2 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -attributes #2 = { nocallback nofree nounwind willreturn } -attributes #3 = { memory(argmem: write) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !4, i64 8} -!3 = !{!"foo", !4, i64 0, !7, i64 4} -!4 = !{!"int", !5, i64 0} -!5 = !{!"omnipotent char", !6, i64 0} -!6 = !{!"Simple C/C++ TBAA"} -!7 = !{!"bar", !4, i64 0, !4, i64 4} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain-u8.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain-u8.ll deleted file mode 100644 index 184c5c334905..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain-u8.ll +++ /dev/null @@ -1,62 +0,0 @@ -; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check unroll of getelementptr.and.store when direct memory offset is -; used instead of field indexes. -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct foo { -; char aa; -; char bb; -; }; -; -; struct bar { -; char a; -; struct foo b; -; } __ctx; -; -; void buz(struct bar *p) { -; ((struct foo *)(((char*)&p->b) + 1))->bb = 42; -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=sroa,bpf-preserve-static-offset -S -o - - -; Function Attrs: nounwind -define dso_local void @buz(ptr noundef %p) #0 { -entry: - call void (i8, ptr, i1, i8, i8, i8, i1, ...) - @llvm.bpf.getelementptr.and.store.i8 - (i8 42, - ptr writeonly elementtype(i8) %p, - i1 false, i8 0, i8 1, i8 0, i1 true, i64 immarg 3) - #3, !tbaa !2 - ret void -} - -; CHECK: define dso_local void @buz(ptr noundef %[[p:.*]]) -; CHECK: %[[v2:.*]] = getelementptr inbounds i8, ptr %[[p]], i64 3 -; CHECK: store i8 42, ptr %[[v2]], align 1 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #1 - -; Function Attrs: nocallback nofree nounwind willreturn -declare void @llvm.bpf.getelementptr.and.store.i8(i8, ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #2 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -attributes #2 = { nocallback nofree nounwind willreturn } -attributes #3 = { memory(argmem: write) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !4, i64 1} -!3 = !{!"foo", !4, i64 0, !4, i64 1} -!4 = !{!"omnipotent char", !5, i64 0} -!5 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain.ll deleted file mode 100644 index 2899ab03f50d..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain.ll +++ /dev/null @@ -1,68 +0,0 @@ -; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check unroll of getelementptr.and.store when several field indexes -; are specified in a chain. -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct bar { -; int aa; -; int bb; -; }; -; -; struct foo { -; int a; -; struct bar b; -; } __ctx; -; -; void buz(struct foo *p) { -; p->b.bb = 42; -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=sroa,bpf-preserve-static-offset -S -o - - -%struct.foo = type { i32, %struct.bar } -%struct.bar = type { i32, i32 } - -; Function Attrs: nounwind -define dso_local void @buz(ptr noundef %p) #0 { -entry: - call void (i32, ptr, i1, i8, i8, i8, i1, ...) - @llvm.bpf.getelementptr.and.store.i32 - (i32 42, - ptr writeonly elementtype(%struct.foo) %p, - i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1, i32 immarg 1) - #3, !tbaa !2 - ret void -} - -; CHECK: define dso_local void @buz(ptr noundef %[[p:.*]]) -; CHECK: %[[v2:.*]] = getelementptr inbounds %struct.foo, ptr %[[p]], i32 0, i32 1, i32 1 -; CHECK: store i32 42, ptr %[[v2]], align 4 -; CHECK: ret void - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #1 - -; Function Attrs: nocallback nofree nounwind willreturn -declare void @llvm.bpf.getelementptr.and.store.i32(i32, ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #2 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -attributes #2 = { nocallback nofree nounwind willreturn } -attributes #3 = { memory(argmem: write) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !4, i64 8} -!3 = !{!"foo", !4, i64 0, !7, i64 4} -!4 = !{!"int", !5, i64 0} -!5 = !{!"omnipotent char", !6, i64 0} -!6 = !{!"Simple C/C++ TBAA"} -!7 = !{!"bar", !4, i64 0, !4, i64 4} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-simple.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-simple.ll deleted file mode 100644 index 8ad5eae98475..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-simple.ll +++ /dev/null @@ -1,61 +0,0 @@ -; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check unroll of getelementptr.and.store. -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct foo { -; int a; -; int b; -; } __ctx; -; -; extern void consume(int); -; -; void bar(struct foo *p){ -; p->b = 42; -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=sroa,bpf-preserve-static-offset -S -o - - -%struct.foo = type { i32, i32 } - -; Function Attrs: nounwind -define dso_local void @bar(ptr noundef %p) #0 { -entry: - call void (i32, ptr, i1, i8, i8, i8, i1, ...) - @llvm.bpf.getelementptr.and.store.i32 - (i32 42, - ptr writeonly elementtype(%struct.foo) %p, - i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1) - #3, !tbaa !2 - ret void -} - -; CHECK: define dso_local void @bar(ptr noundef %[[p:.*]]) -; CHECK: %[[v2:.*]] = getelementptr inbounds %struct.foo, ptr %[[p]], i32 0, i32 1 -; CHECK: store i32 42, ptr %[[v2]], align 4 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #1 - -; Function Attrs: nocallback nofree nounwind willreturn -declare void @llvm.bpf.getelementptr.and.store.i32(i32, ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #2 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -attributes #2 = { nocallback nofree nounwind willreturn } -attributes #3 = { memory(argmem: write) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !4, i64 4} -!3 = !{!"foo", !4, i64 0, !4, i64 4} -!4 = !{!"int", !5, i64 0} -!5 = !{!"omnipotent char", !6, i64 0} -!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-volatile.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-volatile.ll deleted file mode 100644 index 79495732f972..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-volatile.ll +++ /dev/null @@ -1,61 +0,0 @@ -; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check that unroll of getelementptr.and.store restores volatile. -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct foo { -; int a; -; volatile int b; -; } __ctx; -; -; extern void consume(int); -; -; void bar(struct foo *p){ -; p->b = 42; -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=sroa,bpf-preserve-static-offset -S -o - - -%struct.foo = type { i32, i32 } - -; Function Attrs: nounwind -define dso_local void @bar(ptr noundef %p) #0 { -entry: - call void (i32, ptr, i1, i8, i8, i8, i1, ...) - @llvm.bpf.getelementptr.and.store.i32 - (i32 42, - ptr elementtype(%struct.foo) %p, - i1 true, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1), - !tbaa !2 - ret void -} - -; CHECK: define dso_local void @bar(ptr noundef %[[p:.*]]) -; CHECK: entry: -; CHECK: %[[v2:.*]] = getelementptr inbounds %struct.foo, ptr %[[p]], i32 0, i32 1 -; CHECK: store volatile i32 42, ptr %[[v2]], align 4 - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #1 - -; Function Attrs: nocallback nofree nounwind willreturn -declare void @llvm.bpf.getelementptr.and.store.i32(i32, ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #2 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -attributes #2 = { nocallback nofree nounwind willreturn } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !4, i64 4} -!3 = !{!"foo", !4, i64 0, !4, i64 4} -!4 = !{!"int", !5, i64 0} -!5 = !{!"omnipotent char", !6, i64 0} -!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-unroll-inline.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-unroll-inline.ll deleted file mode 100644 index 161aded79eac..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/store-unroll-inline.ll +++ /dev/null @@ -1,104 +0,0 @@ -; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check position of bpf-preserve-static-offset pass in the pipeline: -; - preserve.static.offset call is preserved if address is passed as -; a parameter to an inline-able function; -; - second bpf-preserve-static-offset pass (after inlining) should introduce -; getelementptr.and.store call using the preserved marker after loops -; unrolling; -; - memory(argmem: readwrite) and tbaa attributes should allow -; removing one getelementptr.and.store call. -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct foo { -; int a; -; int b[4]; -; } __ctx; -; -; static inline void bar(int * restrict p, unsigned long i) { -; p[0] = i; -; } -; -; void quux(struct foo *p){ -; unsigned long i = 0; -; #pragma clang loop unroll(full) -; while (i < 2) { -; bar(p->b, i); -; ++i; -; } -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=function(sroa) -S -o - - -%struct.foo = type { i32, [4 x i32] } - -; Function Attrs: nounwind -define dso_local void @quux(ptr noundef %p) #0 { -entry: - br label %while.cond - -while.cond: ; preds = %while.body, %entry - %i.0 = phi i64 [ 0, %entry ], [ %inc, %while.body ] - %cmp = icmp ult i64 %i.0, 2 - br i1 %cmp, label %while.body, label %while.end - -while.body: ; preds = %while.cond - %0 = call ptr @llvm.preserve.static.offset(ptr %p) - %b = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 - %arraydecay = getelementptr inbounds [4 x i32], ptr %b, i64 0, i64 0 - call void @bar(ptr noundef %arraydecay, i64 noundef %i.0) - %inc = add i64 %i.0, 1 - br label %while.cond, !llvm.loop !2 - -while.end: ; preds = %while.cond - ret void -} - -; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) -declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1 - -; Function Attrs: inlinehint nounwind -define internal void @bar(ptr noalias noundef %p, i64 noundef %i) #2 { -entry: - %conv = trunc i64 %i to i32 - %arrayidx = getelementptr inbounds i32, ptr %p, i64 0 - store i32 %conv, ptr %arrayidx, align 4, !tbaa !5 - ret void -} - -; CHECK: define dso_local void @quux(ptr nocapture noundef writeonly %[[p:.*]]) -; CHECK-NEXT: entry: -; CHECK-NEXT: tail call void (i32, ptr, i1, i8, i8, i8, i1, ...) -; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i32 -; CHECK-SAME: (i32 1, -; CHECK-SAME: ptr writeonly elementtype(%struct.foo) %[[p]], -; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i64 immarg 0, i32 immarg 1) -; CHECK-NEXT: ret void - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #3 - -; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) -declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } -attributes #2 = { inlinehint nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = distinct !{!2, !3, !4} -!3 = !{!"llvm.loop.mustprogress"} -!4 = !{!"llvm.loop.unroll.full"} -!5 = !{!6, !6, i64 0} -!6 = !{!"int", !7, i64 0} -!7 = !{!"omnipotent char", !8, i64 0} -!8 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-volatile.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-volatile.ll deleted file mode 100644 index 8b0493a38efa..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/store-volatile.ll +++ /dev/null @@ -1,56 +0,0 @@ -; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check handling of a volatile store instruction by bpf-preserve-static-offset. -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct foo { -; int a; -; volatile int b; -; } __ctx; -; -; void bar(struct foo *p) { -; p->b = 42; -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=function(sroa) -S -o - - -%struct.foo = type { i32, i32 } - -; Function Attrs: nounwind -define dso_local void @bar(ptr noundef %p) #0 { -entry: - %0 = call ptr @llvm.preserve.static.offset(ptr %p) - %b = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 - store volatile i32 42, ptr %b, align 4, !tbaa !2 - ret void -} - -; CHECK: define dso_local void @bar(ptr nocapture noundef %[[p:.*]]) -; CHECK: tail call void (i32, ptr, i1, i8, i8, i8, i1, ...) -; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i32 -; CHECK-SAME: (i32 42, -; CHECK-SAME: ptr elementtype(%struct.foo) %[[p]], -; CHECK-SAME: i1 true, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1), -; CHECK-NOT: #{{[0-9]+}} -; CHECK-SAME: !tbaa - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #1 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !4, i64 4} -!3 = !{!"foo", !4, i64 0, !4, i64 4} -!4 = !{!"int", !5, i64 0} -!5 = !{!"omnipotent char", !6, i64 0} -!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-zero.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-zero.ll deleted file mode 100644 index 7f2a06af8d10..000000000000 --- a/llvm/test/CodeGen/BPF/preserve-static-offset/store-zero.ll +++ /dev/null @@ -1,51 +0,0 @@ -; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s -; -; Check that stores from zero offset are not modified by bpf-preserve-static-offset. -; -; Source: -; #define __ctx __attribute__((preserve_static_offset)) -; -; struct foo { -; int a; -; } __ctx; -; -; void bar(struct foo *p) { -; p->a = 0; -; } -; -; Compilation flag: -; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ -; | opt -passes=function(sroa) -S -o - - -%struct.foo = type { i32 } - -; Function Attrs: nounwind -define dso_local void @bar(ptr noundef %p) #0 { -entry: - %0 = call ptr @llvm.preserve.static.offset(ptr %p) - %a = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 0 - store i32 0, ptr %a, align 4, !tbaa !2 - ret void -} - -; CHECK: define dso_local void @bar(ptr nocapture noundef writeonly %[[p:.*]]) -; CHECK-NEXT: entry: -; CHECK-NEXT: store i32 0, ptr %[[p]], align 4, !tbaa -; CHECK-NEXT: ret void - -; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) -declare ptr @llvm.preserve.static.offset(ptr readnone) #1 - -attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang"} -!2 = !{!3, !4, i64 0} -!3 = !{!"foo", !4, i64 0} -!4 = !{!"int", !5, i64 0} -!5 = !{!"omnipotent char", !6, i64 0} -!6 = !{!"Simple C/C++ TBAA"} -- GitLab From bddf5d20105e24cf708ff8c6ff49aa65af4e89b0 Mon Sep 17 00:00:00 2001 From: Peter Klausler <35819229+klausler@users.noreply.github.com> Date: Thu, 30 Nov 2023 12:34:42 -0800 Subject: [PATCH 035/699] [flang][runtime] Fix BACKSPACE-WRITE on variable-length unformatted file (#72732) A subtle bug in buffer management is being caused by a WRITE on an unformatted file with variable-length records after one or more BACKSPACEs and some READs. An attempt at a minor optimization in BACKSPACE kept the footer of the previous record in the unit's buffer, in case more BACKSPACEs were to follow. If a later WRITE takes place instead, the buffer's frame would still cover that footer, but its content would be lost when the buffer became dirty on its first modification, and the footer in the file would be overwritten with stale buffer contents. As WriteFrame() implies the intent to define all the bytes in the identified range, the trick being used in BACKSPACE with its adjustment to frameOffsetInFile_ breaks any later WRITE... and so we just can't do it. Fixes https://github.com/llvm/llvm-project/issues/72599. --- flang/runtime/unit.cpp | 4 ---- 1 file changed, 4 deletions(-) diff --git a/flang/runtime/unit.cpp b/flang/runtime/unit.cpp index dec8d8032f61..995656b9480c 100644 --- a/flang/runtime/unit.cpp +++ b/flang/runtime/unit.cpp @@ -825,10 +825,6 @@ void ExternalFileUnit::BackspaceVariableUnformattedRecord( return; } frameOffsetInFile_ -= *recordLength + 2 * headerBytes; - if (frameOffsetInFile_ >= headerBytes) { - frameOffsetInFile_ -= headerBytes; - recordOffsetInFrame_ = headerBytes; - } auto need{static_cast( recordOffsetInFrame_ + sizeof header + *recordLength)}; got = ReadFrame(frameOffsetInFile_, need, handler); -- GitLab From cc84a1419723fcc240c3c6832bdb990afef37f4b Mon Sep 17 00:00:00 2001 From: Nick Desaulniers Date: Thu, 30 Nov 2023 12:38:00 -0800 Subject: [PATCH 036/699] [libc] fix getchar_unlocked (#73874) A typo was leading to getc_unlocked.cpp.o being included into libc.a twice. I only noticed because I was trying to convert libc.a to a shared object via $ ld.lld -o libc.so --whole-archive libc.a which errored since getc_unlocked was being defined twice. --- libc/src/stdio/generic/CMakeLists.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libc/src/stdio/generic/CMakeLists.txt b/libc/src/stdio/generic/CMakeLists.txt index 2ecef879eb4b..4e4a709e9406 100644 --- a/libc/src/stdio/generic/CMakeLists.txt +++ b/libc/src/stdio/generic/CMakeLists.txt @@ -319,9 +319,9 @@ add_entrypoint_object( add_entrypoint_object( getchar_unlocked SRCS - getc_unlocked.cpp + getchar_unlocked.cpp HDRS - ../getc_unlocked.h + ../getchar_unlocked.h DEPENDS libc.src.errno.errno libc.include.stdio -- GitLab From 7fbdee057db4dbc299d998d390fd478ddc76d20b Mon Sep 17 00:00:00 2001 From: LLVM GN Syncbot Date: Thu, 30 Nov 2023 20:40:10 +0000 Subject: [PATCH 037/699] [gn build] Port 248446980317 --- llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn | 1 - 1 file changed, 1 deletion(-) diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn index 2e5b7e03bd65..7881905228a4 100644 --- a/llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn @@ -74,7 +74,6 @@ static_library("LLVMBPFCodeGen") { "BPFMIPeephole.cpp", "BPFMISimplifyPatchable.cpp", "BPFPreserveDIType.cpp", - "BPFPreserveStaticOffset.cpp", "BPFRegisterInfo.cpp", "BPFSelectionDAGInfo.cpp", "BPFSubtarget.cpp", -- GitLab From 13386c608e6d571d2d91eea5f7c8fb6911d6dcfb Mon Sep 17 00:00:00 2001 From: Michael Spencer Date: Thu, 30 Nov 2023 12:47:27 -0800 Subject: [PATCH 038/699] [clang][DependencyScanner] Include the working directory in the context hash (#73719) The working directory is included in the PCM, but is not currently part of the context hash. This causes problems because different builds of a PCM with exactly the same command line can end up with different binary content for a PCM. If a build system tracks tasks by both working directory and command line, it may build a given PCM multiple times, causing a "module file out of date" error when loading the PCM due to different sizes. --- .../DependencyScanning/ModuleDepCollector.cpp | 9 +- clang/test/ClangScanDeps/working-dir.m | 107 ++++++++++++++++++ 2 files changed, 114 insertions(+), 2 deletions(-) create mode 100644 clang/test/ClangScanDeps/working-dir.m diff --git a/clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp b/clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp index 9099c18391e4..1058ddb8254c 100644 --- a/clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp +++ b/clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp @@ -316,7 +316,8 @@ void ModuleDepCollector::applyDiscoveredDependencies(CompilerInvocation &CI) { static std::string getModuleContextHash(const ModuleDeps &MD, const CowCompilerInvocation &CI, - bool EagerLoadModules) { + bool EagerLoadModules, + llvm::vfs::FileSystem &VFS) { llvm::HashBuilder, llvm::endianness::native> HashBuilder; SmallString<32> Scratch; @@ -325,6 +326,9 @@ static std::string getModuleContextHash(const ModuleDeps &MD, // will be readable. HashBuilder.add(getClangFullRepositoryVersion()); HashBuilder.add(serialization::VERSION_MAJOR, serialization::VERSION_MINOR); + llvm::ErrorOr CWD = VFS.getCurrentWorkingDirectory(); + if (CWD) + HashBuilder.add(*CWD); // Hash the BuildInvocation without any input files. SmallString<0> ArgVec; @@ -356,7 +360,8 @@ static std::string getModuleContextHash(const ModuleDeps &MD, void ModuleDepCollector::associateWithContextHash( const CowCompilerInvocation &CI, ModuleDeps &Deps) { - Deps.ID.ContextHash = getModuleContextHash(Deps, CI, EagerLoadModules); + Deps.ID.ContextHash = getModuleContextHash( + Deps, CI, EagerLoadModules, ScanInstance.getVirtualFileSystem()); bool Inserted = ModuleDepsByID.insert({Deps.ID, &Deps}).second; (void)Inserted; assert(Inserted && "duplicate module mapping"); diff --git a/clang/test/ClangScanDeps/working-dir.m b/clang/test/ClangScanDeps/working-dir.m new file mode 100644 index 000000000000..a43df2351f67 --- /dev/null +++ b/clang/test/ClangScanDeps/working-dir.m @@ -0,0 +1,107 @@ +// RUN: rm -rf %t +// RUN: split-file %s %t +// RUN: sed -e "s|DIR|%/t|g" %t/build/compile-commands.json.in > %t/build/compile-commands.json +// RUN: clang-scan-deps -compilation-database %t/build/compile-commands.json \ +// RUN: -j 1 -format experimental-full --optimize-args=all > %t/deps.db +// RUN: cat %t/deps.db | sed 's:\\\\\?:/:g' | FileCheck %s -DPREFIX=%/t + +// Check that there are two separate modules hashes. One for each working dir. + +// CHECK: { +// CHECK-NEXT: "modules": [ +// CHECK-NEXT: { +// CHECK-NEXT: "clang-module-deps": +// CHECK-NEXT: "clang-modulemap-file": +// CHECK-NEXT: "command-line": [ +// CHECK: ], +// CHECK-NEXT: "context-hash": "{{.*}}", +// CHECK-NEXT: "file-deps": [ +// CHECK: ], +// CHECK-NEXT: "name": "A" +// CHECK-NEXT: }, +// CHECK-NEXT: { +// CHECK-NEXT: "clang-module-deps": +// CHECK-NEXT: "clang-modulemap-file": +// CHECK-NEXT: "command-line": [ +// CHECK: ], +// CHECK-NEXT: "context-hash": "{{.*}}", +// CHECK-NEXT: "file-deps": [ +// CHECK: ], +// CHECK-NEXT: "name": "A" +// CHECK-NEXT: }, +// CHECK-NEXT: { +// CHECK-NEXT: "clang-module-deps": +// CHECK: ], +// CHECK-NEXT: "clang-modulemap-file": +// CHECK-NEXT: "command-line": [ +// CHECK: ], +// CHECK-NEXT: "context-hash": "{{.*}}", +// CHECK-NEXT: "file-deps": [ +// CHECK: ], +// CHECK-NEXT: "name": "B" +// CHECK-NEXT: }, +// CHECK-NEXT: { +// CHECK-NEXT: "clang-module-deps": +// CHECK: ], +// CHECK-NEXT: "clang-modulemap-file": +// CHECK-NEXT: "command-line": [ +// CHECK: ], +// CHECK-NEXT: "context-hash": "{{.*}}", +// CHECK-NEXT: "file-deps": [ +// CHECK: ], +// CHECK-NEXT: "name": "B" +// CHECK-NEXT: } +// CHECK-NEXT: ], +// CHECK-NEXT: "translation-units": [ +// CHECK: ] +// CHECK: } + +//--- build/compile-commands.json.in + +[ +{ + "directory": "DIR/build", + "command": "clang -c DIR/A.m -IDIR/modules/A -IDIR/modules/B -fmodules -fmodules-cache-path=DIR/module-cache -fimplicit-module-maps", + "file": "DIR/A.m" +}, +{ + "directory": "DIR", + "command": "clang -c DIR/B.m -IDIR/modules/A -IDIR/modules/B -fmodules -fmodules-cache-path=DIR/module-cache -fimplicit-module-maps", + "file": "DIR/B.m" +} +] + + +//--- modules/A/module.modulemap + +module A { + umbrella header "A.h" +} + +//--- modules/A/A.h + +typedef int A_t; + +//--- modules/B/module.modulemap + +module B { + umbrella header "B.h" +} + +//--- modules/B/B.h + +#include + +typedef int B_t; + +//--- A.m + +#include + +A_t a = 0; + +//--- B.m + +#include + +B_t b = 0; -- GitLab From c13f7e17409b6fed29696c2bbe59efc3af3a408b Mon Sep 17 00:00:00 2001 From: Peter Klausler <35819229+klausler@users.noreply.github.com> Date: Thu, 30 Nov 2023 12:51:56 -0800 Subject: [PATCH 039/699] [flang][runtime] Allow already-documented missing 'w' on edit descriptor (#72901) As already documented in flang/docs/Extensions.md and implemented in the compilation-time format validator, we want to support at execution time the Intel (and presumably also Fujitsu) extension of allowing a missing width on an edit descriptor in a formatted I/O statement. Fixes https://github.com/llvm/llvm-project/issues/72597. --- flang/runtime/format-implementation.h | 73 ++++++++++++++------------- flang/unittests/Runtime/Format.cpp | 3 +- 2 files changed, 39 insertions(+), 37 deletions(-) diff --git a/flang/runtime/format-implementation.h b/flang/runtime/format-implementation.h index 57c176ea8d77..c54ac062c7be 100644 --- a/flang/runtime/format-implementation.h +++ b/flang/runtime/format-implementation.h @@ -416,14 +416,16 @@ std::optional FormatControl::GetNextDataEdit( int repeat{CueUpNextDataEdit(context)}; auto start{offset_}; DataEdit edit; + edit.modes = context.mutableModes(); + // Handle repeated nonparenthesized edit descriptors + edit.repeat = std::min(repeat, maxRepeat); // 0 if maxRepeat==0 + if (repeat > maxRepeat) { + stack_[height_].start = start; // after repeat count + stack_[height_].remaining = repeat - edit.repeat; + ++height_; + } edit.descriptor = static_cast(Capitalize(GetNextChar(context))); - if (edit.descriptor == 'E') { - if (auto next{static_cast(Capitalize(PeekNext()))}; - next == 'N' || next == 'S' || next == 'X') { - edit.variation = next; - ++offset_; - } - } else if (edit.descriptor == 'D' && Capitalize(PeekNext()) == 'T') { + if (edit.descriptor == 'D' && Capitalize(PeekNext()) == 'T') { // DT['iotype'][(v_list)] defined I/O edit.descriptor = DataEdit::DefinedDerivedType; ++offset_; @@ -479,38 +481,37 @@ std::optional FormatControl::GetNextDataEdit( return std::nullopt; } } - } - if (edit.descriptor == 'A' || edit.descriptor == 'L') { - // width is optional for A[w] or L[w] - auto ch{PeekNext()}; - if (ch >= '0' && ch <= '9') { - edit.width = GetIntField(context); - } - } else if (edit.descriptor != DataEdit::DefinedDerivedType) { - edit.width = GetIntField(context); - } - if constexpr (std::is_base_of_v) { - if (edit.width.value_or(-1) == 0) { - ReportBadFormat(context, "Input field width is zero", start); + } else { // not DT'iotype' + if (edit.descriptor == 'E') { + if (auto next{static_cast(Capitalize(PeekNext()))}; + next == 'N' || next == 'S' || next == 'X') { + edit.variation = next; + ++offset_; + } } - } - if (edit.descriptor != DataEdit::DefinedDerivedType && PeekNext() == '.') { - ++offset_; - edit.digits = GetIntField(context); - CharType ch{PeekNext()}; - if (ch == 'e' || ch == 'E' || ch == 'd' || ch == 'D') { - ++offset_; - edit.expoDigits = GetIntField(context); + // Width is optional for A[w] in the standard and optional + // for Lw in most compilers. + // Intel & (presumably, from bug report) Fujitsu allow + // a missing 'w' & 'd'/'m' for other edit descriptors -- but not + // 'd'/'m' with a missing 'w' -- and so interpret "(E)" as "(E0)". + if (CharType ch{PeekNext()}; (ch >= '0' && ch <= '9') || ch == '.') { + edit.width = GetIntField(context); + if constexpr (std::is_base_of_v) { + if (edit.width.value_or(-1) == 0) { + ReportBadFormat(context, "Input field width is zero", start); + } + } + if (PeekNext() == '.') { + ++offset_; + edit.digits = GetIntField(context); + if (CharType ch{PeekNext()}; + ch == 'e' || ch == 'E' || ch == 'd' || ch == 'D') { + ++offset_; + edit.expoDigits = GetIntField(context); + } + } } } - edit.modes = context.mutableModes(); - // Handle repeated nonparenthesized edit descriptors - edit.repeat = std::min(repeat, maxRepeat); // 0 if maxRepeat==0 - if (repeat > maxRepeat) { - stack_[height_].start = start; // after repeat count - stack_[height_].remaining = repeat - edit.repeat; - ++height_; - } return edit; } diff --git a/flang/unittests/Runtime/Format.cpp b/flang/unittests/Runtime/Format.cpp index e9004b7798f3..01803c628de2 100644 --- a/flang/unittests/Runtime/Format.cpp +++ b/flang/unittests/Runtime/Format.cpp @@ -111,6 +111,7 @@ TEST(FormatTests, FormatStringTraversal) { ResultsTy{"I4", "E10.1", "E10.1", "/", "I4", "E10.1", "E10.1", "/", "I4", "E10.1", "E10.1"}, 1}, + {1, "(F)", ResultsTy{"F"}, 1}, // missing 'w' }; for (const auto &[n, format, expect, repeat] : params) { @@ -170,7 +171,7 @@ TEST(InvalidFormatFailure, MissingPrecision) { R"(Invalid FORMAT: integer expected at '\)')"); } -TEST(InvalidFormatFailure, MissingFormatWidth) { +TEST(InvalidFormatFailure, MissingFormatWidthWithDigits) { static constexpr const char *format{"(F.9)"}; static constexpr int repeat{1}; -- GitLab From 33b54f01fe32030ff60d661a7a951e33360f82ee Mon Sep 17 00:00:00 2001 From: Peter Klausler <35819229+klausler@users.noreply.github.com> Date: Thu, 30 Nov 2023 12:59:06 -0800 Subject: [PATCH 040/699] =?UTF-8?q?[flang]=20Move=20internal=20Fortran::IS?= =?UTF-8?q?O=20namespace=20out=20of=20user-facing=20ISO=5FF=E2=80=A6=20(#7?= =?UTF-8?q?2909)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit …ortran_binding.h ... and into the ISO_Fortran_binding_wrapper.h header, through which the compiler and runtime access its contents. This change ensures that user code that #includes ISO_Fortran_binding.h within 'extern "C" {' doesn't encounter mysterious namespace errors. --- flang/include/flang/ISO_Fortran_binding.h | 19 +++++++++---------- .../flang/ISO_Fortran_binding_wrapper.h | 10 ++++++++++ flang/lib/Optimizer/CodeGen/DescriptorModel.h | 2 +- 3 files changed, 20 insertions(+), 11 deletions(-) diff --git a/flang/include/flang/ISO_Fortran_binding.h b/flang/include/flang/ISO_Fortran_binding.h index 51d6219427cc..dd384c516263 100644 --- a/flang/include/flang/ISO_Fortran_binding.h +++ b/flang/include/flang/ISO_Fortran_binding.h @@ -10,7 +10,14 @@ #ifndef CFI_ISO_FORTRAN_BINDING_H_ #define CFI_ISO_FORTRAN_BINDING_H_ +/* When this header is included into the compiler and runtime implementations, + * it does so by means of a wrapper header that establishes namespaces and + * a macro for extra function attributes (RT_API_ATTRS). + */ +#ifndef FORTRAN_ISO_FORTRAN_BINDING_WRAPPER_H_ #include +#define FORTRAN_ISO_NAMESPACE_ +#endif /* Standard interface to Fortran from C and C++. * These interfaces are named in subclause 18.5 of the Fortran 2018 @@ -22,12 +29,6 @@ #define RT_API_ATTRS #endif -#ifdef __cplusplus -namespace Fortran { -namespace ISO { -inline namespace Fortran_2018 { -#endif - /* 18.5.4 */ #define CFI_VERSION 20180515 @@ -169,7 +170,8 @@ template struct CdescStorage : public CFI_cdesc_t { template <> struct CdescStorage<1> : public CFI_cdesc_t {}; template <> struct CdescStorage<0> : public CFI_cdesc_t {}; } // namespace cfi_internal -#define CFI_CDESC_T(rank) ::Fortran::ISO::cfi_internal::CdescStorage +#define CFI_CDESC_T(rank) \ + FORTRAN_ISO_NAMESPACE_::cfi_internal::CdescStorage #else #define CFI_CDESC_T(_RANK) \ struct { \ @@ -199,9 +201,6 @@ RT_API_ATTRS int CFI_setpointer( CFI_cdesc_t *, const CFI_cdesc_t *source, const CFI_index_t lower_bounds[]); #ifdef __cplusplus } // extern "C" -} // inline namespace Fortran_2018 -} // namespace ISO -} // namespace Fortran #endif #endif /* CFI_ISO_FORTRAN_BINDING_H_ */ diff --git a/flang/include/flang/ISO_Fortran_binding_wrapper.h b/flang/include/flang/ISO_Fortran_binding_wrapper.h index c810ebccdbca..83c974365e34 100644 --- a/flang/include/flang/ISO_Fortran_binding_wrapper.h +++ b/flang/include/flang/ISO_Fortran_binding_wrapper.h @@ -22,8 +22,18 @@ */ /* clang-format off */ +#include #include "Runtime/api-attrs.h" +#ifdef __cplusplus +namespace Fortran { +namespace ISO { +#define FORTRAN_ISO_NAMESPACE_ ::Fortran::ISO +#endif /* __cplusplus */ #include "ISO_Fortran_binding.h" +#ifdef __cplusplus +} // namespace ISO +} // namespace Fortran +#endif /* __cplusplus */ /* clang-format on */ #endif /* FORTRAN_ISO_FORTRAN_BINDING_WRAPPER_H_ */ diff --git a/flang/lib/Optimizer/CodeGen/DescriptorModel.h b/flang/lib/Optimizer/CodeGen/DescriptorModel.h index 39427a42f0f4..ed35caef9301 100644 --- a/flang/lib/Optimizer/CodeGen/DescriptorModel.h +++ b/flang/lib/Optimizer/CodeGen/DescriptorModel.h @@ -113,7 +113,7 @@ getModel>() { /// Get the type model of the field number `Field` in an ISO CFI descriptor. template static constexpr TypeBuilderFunc getDescFieldTypeModel() { - Fortran::ISO::Fortran_2018::CFI_cdesc_t dummyDesc{}; + Fortran::ISO::CFI_cdesc_t dummyDesc{}; // check that the descriptor is exactly 8 fields as specified in CFI_cdesc_t // in flang/include/flang/ISO_Fortran_binding.h. auto [a, b, c, d, e, f, g, h] = dummyDesc; -- GitLab From fddadd293952ffddd2455f567373424bf8faa003 Mon Sep 17 00:00:00 2001 From: Peter Klausler <35819229+klausler@users.noreply.github.com> Date: Thu, 30 Nov 2023 13:07:49 -0800 Subject: [PATCH 041/699] [flang] Address case of under-processed array symbol (#73169) Array element references are frequently parsed as function references due to the ambiguous syntax of Fortran, and the parse tree is repaired by semantics once the relevant symbol table entries are in hand. This patch fixes a case in which the correction takes a path that leaves the type of a symbol undetermined, leading to later spurious errors in expression analysis. Fixes https://github.com/llvm/llvm-project/issues/68652. --- flang/lib/Semantics/resolve-names.cpp | 5 +---- flang/test/Semantics/symbol33.f90 | 11 +++++++++++ 2 files changed, 12 insertions(+), 4 deletions(-) create mode 100644 flang/test/Semantics/symbol33.f90 diff --git a/flang/lib/Semantics/resolve-names.cpp b/flang/lib/Semantics/resolve-names.cpp index 0f69c1ccd285..5e2a9be41b90 100644 --- a/flang/lib/Semantics/resolve-names.cpp +++ b/flang/lib/Semantics/resolve-names.cpp @@ -7731,7 +7731,6 @@ void ResolveNamesVisitor::HandleProcedureName( } else if (CheckUseError(name)) { // error was reported } else { - auto &nonUltimateSymbol{*symbol}; symbol = &Resolve(name, symbol)->GetUltimate(); CheckEntryDummyUse(name.source, symbol); bool convertedToProcEntity{ConvertToProcEntity(*symbol)}; @@ -7756,9 +7755,7 @@ void ResolveNamesVisitor::HandleProcedureName( // is created for the current scope. // Operate on non ultimate symbol so that HostAssocDetails are also // created for symbols used associated in the host procedure. - if (IsUplevelReference(nonUltimateSymbol)) { - MakeHostAssocSymbol(name, nonUltimateSymbol); - } + ResolveName(name); } else if (symbol->test(Symbol::Flag::Implicit)) { Say(name, "Use of '%s' as a procedure conflicts with its implicit definition"_err_en_US); diff --git a/flang/test/Semantics/symbol33.f90 b/flang/test/Semantics/symbol33.f90 new file mode 100644 index 000000000000..fbb5321b8854 --- /dev/null +++ b/flang/test/Semantics/symbol33.f90 @@ -0,0 +1,11 @@ +! RUN: %python %S/test_symbols.py %s %flang_fc1 +! Ensure that a misparsed function reference that turns out to be an +! array element reference still applies implicit typing, &c. +!DEF: /subr (Subroutine) Subprogram +subroutine subr + !DEF: /subr/moo (Implicit) ObjectEntity INTEGER(4) + common //moo(1) + !DEF: /subr/a ObjectEntity REAL(4) + !REF: /subr/moo + real a(moo(1)) +end subroutine -- GitLab From 828bfbef173e82943e56aee5901641c70fc1ea14 Mon Sep 17 00:00:00 2001 From: Peter Klausler <35819229+klausler@users.noreply.github.com> Date: Thu, 30 Nov 2023 13:15:42 -0800 Subject: [PATCH 042/699] =?UTF-8?q?[flang]=20Suppress=20error=20meant=20to?= =?UTF-8?q?=20prevent=20discontiguous=20association=20whe=E2=80=A6=20(#731?= =?UTF-8?q?75)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit …n actual argument is contiguous When an element of a contiguous pointer array or assumed-shape array is associated as an actual argument with an assumed-size dummy array, don't flag the usage as an error. --- flang/lib/Semantics/check-call.cpp | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/flang/lib/Semantics/check-call.cpp b/flang/lib/Semantics/check-call.cpp index ca9fffaeeaf2..ec8f99ca6bf4 100644 --- a/flang/lib/Semantics/check-call.cpp +++ b/flang/lib/Semantics/check-call.cpp @@ -529,17 +529,18 @@ static void CheckExplicitDataArg(const characteristics::DummyDataObject &dummy, dummyName); } if (actualIsArrayElement && actualLastSymbol && - IsPointer(*actualLastSymbol)) { - basicError = true; - messages.Say( - "Element of pointer array may not be associated with a %s array"_err_en_US, - dummyName); - } - if (actualLastSymbol && IsAssumedShape(*actualLastSymbol)) { - basicError = true; - messages.Say( - "Element of assumed-shape array may not be associated with a %s array"_err_en_US, - dummyName); + !evaluate::IsContiguous(*actualLastSymbol, foldingContext)) { + if (IsPointer(*actualLastSymbol)) { + basicError = true; + messages.Say( + "Element of pointer array may not be associated with a %s array"_err_en_US, + dummyName); + } else if (IsAssumedShape(*actualLastSymbol)) { + basicError = true; + messages.Say( + "Element of assumed-shape array may not be associated with a %s array"_err_en_US, + dummyName); + } } } } -- GitLab From 5f864ba1957e42283b9680ee47811d12e69d92bd Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Thu, 30 Nov 2023 16:15:35 -0500 Subject: [PATCH 043/699] Revert "[OpenMP] Use simple VLA implementation to replace uses of actual VLA" This reverts commit 97e16da450e94c92456fa5a74768ec1b22fe6b63 because it causes build error on i386 system. --- openmp/runtime/src/kmp_gsupport.cpp | 7 ++-- openmp/runtime/src/kmp_runtime.cpp | 3 +- openmp/runtime/src/kmp_utils.h | 58 ----------------------------- 3 files changed, 4 insertions(+), 64 deletions(-) delete mode 100644 openmp/runtime/src/kmp_utils.h diff --git a/openmp/runtime/src/kmp_gsupport.cpp b/openmp/runtime/src/kmp_gsupport.cpp index f38a0ddfc62a..d77d4809a7e9 100644 --- a/openmp/runtime/src/kmp_gsupport.cpp +++ b/openmp/runtime/src/kmp_gsupport.cpp @@ -12,7 +12,6 @@ #include "kmp.h" #include "kmp_atomic.h" -#include "kmp_utils.h" #if OMPT_SUPPORT #include "ompt-specific.h" @@ -1281,7 +1280,7 @@ void KMP_EXPAND_NAME(KMP_API_NAME_GOMP_TASK)(void (*func)(void *), void *data, KMP_ASSERT(depend); kmp_gomp_depends_info_t gomp_depends(depend); kmp_int32 ndeps = gomp_depends.get_num_deps(); - SimpleVLA dep_list(ndeps); + kmp_depend_info_t dep_list[ndeps]; for (kmp_int32 i = 0; i < ndeps; i++) dep_list[i] = gomp_depends.get_kmp_depend(i); kmp_int32 ndeps_cnv; @@ -1310,7 +1309,7 @@ void KMP_EXPAND_NAME(KMP_API_NAME_GOMP_TASK)(void (*func)(void *), void *data, KMP_ASSERT(depend); kmp_gomp_depends_info_t gomp_depends(depend); kmp_int32 ndeps = gomp_depends.get_num_deps(); - SimpleVLA dep_list(ndeps); + kmp_depend_info_t dep_list[ndeps]; for (kmp_int32 i = 0; i < ndeps; i++) dep_list[i] = gomp_depends.get_kmp_depend(i); __kmpc_omp_wait_deps(&loc, gtid, ndeps, dep_list, 0, NULL); @@ -1994,7 +1993,7 @@ void KMP_EXPAND_NAME(KMP_API_NAME_GOMP_TASKWAIT_DEPEND)(void **depend) { KA_TRACE(20, ("GOMP_taskwait_depend: T#%d\n", gtid)); kmp_gomp_depends_info_t gomp_depends(depend); kmp_int32 ndeps = gomp_depends.get_num_deps(); - SimpleVLA dep_list(ndeps); + kmp_depend_info_t dep_list[ndeps]; for (kmp_int32 i = 0; i < ndeps; i++) dep_list[i] = gomp_depends.get_kmp_depend(i); #if OMPT_SUPPORT diff --git a/openmp/runtime/src/kmp_runtime.cpp b/openmp/runtime/src/kmp_runtime.cpp index 4ac694ace874..25136691bc72 100644 --- a/openmp/runtime/src/kmp_runtime.cpp +++ b/openmp/runtime/src/kmp_runtime.cpp @@ -24,7 +24,6 @@ #include "kmp_wait_release.h" #include "kmp_wrapper_getpid.h" #include "kmp_dispatch.h" -#include "kmp_utils.h" #if KMP_USE_HIER_SCHED #include "kmp_dispatch_hier.h" #endif @@ -1653,7 +1652,7 @@ __kmp_serial_fork_call(ident_t *loc, int gtid, enum fork_context_e call_context, /* josh todo: hypothetical question: what do we do for OS X*? */ #if KMP_OS_LINUX && \ (KMP_ARCH_X86 || KMP_ARCH_X86_64 || KMP_ARCH_ARM || KMP_ARCH_AARCH64) - SimpleVLA args(argc); + void *args[argc]; #else void **args = (void **)KMP_ALLOCA(argc * sizeof(void *)); #endif /* KMP_OS_LINUX && ( KMP_ARCH_X86 || KMP_ARCH_X86_64 || KMP_ARCH_ARM || \ diff --git a/openmp/runtime/src/kmp_utils.h b/openmp/runtime/src/kmp_utils.h deleted file mode 100644 index 009334792c45..000000000000 --- a/openmp/runtime/src/kmp_utils.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * kmp_utils.h -- Utilities that used internally - */ - -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -#ifndef __KMP_UTILS_H__ -#define __KMP_UTILS_H__ - -#include - -#include "kmp.h" - -/// A simple pure header implementation of VLA that aims to replace uses of -/// actual VLA, which can cause compile warning. This class by default creates a -/// stack buffer that can accomodate \p N elements. If the number of elements is -/// greater than \p N, then a heap buffer will be allocated and used to -/// accomodate the elements. Similar to the actual VLA, we don't check boundary -/// (for now), so we will not store the number of elements. We can always revise -/// it later. -template class SimpleVLA final { - T StackBuffer[N]; - T *HeapBuffer = nullptr; - T *Ptr = StackBuffer; - -public: - SimpleVLA() = delete; - SimpleVLA(const SimpleVLA &) = delete; - SimpleVLA(SimpleVLA &&) = delete; - SimpleVLA &operator=(const SimpleVLA &) = delete; - SimpleVLA &operator=(SimpleVLA &&) = delete; - - explicit SimpleVLA(unsigned NumOfElements) noexcept { - if (NumOfElements > N) { - HeapBuffer = - reinterpret_cast(__kmp_allocate(NumOfElements * sizeof(T))); - Ptr = HeapBuffer; - } - } - - ~SimpleVLA() { - if (HeapBuffer) - __kmp_free(HeapBuffer); - } - - const T &operator[](std::size_t Idx) const noexcept { return Ptr[Idx]; } - T &operator[](std::size_t Idx) noexcept { return Ptr[Idx]; } - - operator T *() noexcept { return Ptr; } - operator const T *() const noexcept { return Ptr; } -}; - -#endif -- GitLab From a1db874d35cb60d536d460a194f8c40c9eeb8dff Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Valentin=20Clement=20=28=E3=83=90=E3=83=AC=E3=83=B3?= =?UTF-8?q?=E3=82=BF=E3=82=A4=E3=83=B3=20=E3=82=AF=E3=83=AC=E3=83=A1?= =?UTF-8?q?=E3=83=B3=29?= Date: Thu, 30 Nov 2023 13:16:53 -0800 Subject: [PATCH 044/699] [flang][openacc] Allow multiple clauses when in preceded by device_type (#73976) Some clauses can be repeated on the compute construct when they are placed after `device_type`. The semantic check was reporting an error for these cases. This patch fixes this. --- flang/lib/Semantics/check-acc-structure.cpp | 6 ++++ .../lib/Semantics/check-directive-structure.h | 25 ++++++++++++++ flang/test/Semantics/OpenACC/acc-parallel.f90 | 33 +++++++++++++++++++ llvm/include/llvm/Frontend/OpenACC/ACC.td | 12 +++---- 4 files changed, 70 insertions(+), 6 deletions(-) diff --git a/flang/lib/Semantics/check-acc-structure.cpp b/flang/lib/Semantics/check-acc-structure.cpp index abda9409efd3..932d5776a046 100644 --- a/flang/lib/Semantics/check-acc-structure.cpp +++ b/flang/lib/Semantics/check-acc-structure.cpp @@ -561,6 +561,8 @@ void AccStructureChecker::Enter(const parser::AccClause::NumGangs &n) { /*warnInsteadOfError=*/GetContext().directive == llvm::acc::Directive::ACCD_serial || GetContext().directive == llvm::acc::Directive::ACCD_serial_loop); + CheckAllowedOncePerGroup( + llvm::acc::Clause::ACCC_num_gangs, llvm::acc::Clause::ACCC_device_type); if (n.v.size() > 3) context_.Say(GetContext().clauseSource, @@ -572,6 +574,8 @@ void AccStructureChecker::Enter(const parser::AccClause::NumWorkers &n) { /*warnInsteadOfError=*/GetContext().directive == llvm::acc::Directive::ACCD_serial || GetContext().directive == llvm::acc::Directive::ACCD_serial_loop); + CheckAllowedOncePerGroup( + llvm::acc::Clause::ACCC_num_workers, llvm::acc::Clause::ACCC_device_type); } void AccStructureChecker::Enter(const parser::AccClause::VectorLength &n) { @@ -579,6 +583,8 @@ void AccStructureChecker::Enter(const parser::AccClause::VectorLength &n) { /*warnInsteadOfError=*/GetContext().directive == llvm::acc::Directive::ACCD_serial || GetContext().directive == llvm::acc::Directive::ACCD_serial_loop); + CheckAllowedOncePerGroup(llvm::acc::Clause::ACCC_vector_length, + llvm::acc::Clause::ACCC_device_type); } void AccStructureChecker::Enter(const parser::AccClause::Reduction &reduction) { diff --git a/flang/lib/Semantics/check-directive-structure.h b/flang/lib/Semantics/check-directive-structure.h index 84240b87f47e..f7a6233a32ed 100644 --- a/flang/lib/Semantics/check-directive-structure.h +++ b/flang/lib/Semantics/check-directive-structure.h @@ -349,6 +349,10 @@ protected: void CheckAllowed(C clause, bool warnInsteadOfError = false); + // Check that the clause appears only once. The counter is reset when the + // separator clause appears. + void CheckAllowedOncePerGroup(C clause, C separator); + void CheckAtLeastOneClause(); void CheckNotAllowedIfClause( @@ -545,6 +549,27 @@ void DirectiveStructureChecker +void DirectiveStructureChecker::CheckAllowedOncePerGroup(C clause, C separator) { + bool clauseIsPresent = false; + for (auto cl : GetContext().actualClauses) { + if (cl == clause) { + if (clauseIsPresent) { + context_.Say(GetContext().clauseSource, + "At most one %s clause can appear on the %s directive or in group separated by the %s clause"_err_en_US, + parser::ToUpperCaseLetters(getClauseName(clause).str()), + parser::ToUpperCaseLetters(GetContext().directiveSource.ToString()), + parser::ToUpperCaseLetters(getClauseName(separator).str())); + } else { + clauseIsPresent = true; + } + } + if (cl == separator) + clauseIsPresent = false; + } +} + // Check the value of the clause is a constant positive integer. template void DirectiveStructureChecker { def ACC_Parallel : Directive<"parallel"> { let allowedClauses = [ VersionedClause, + VersionedClause, VersionedClause, VersionedClause, VersionedClause, @@ -342,20 +343,19 @@ def ACC_Parallel : Directive<"parallel"> { VersionedClause, VersionedClause, VersionedClause, + VersionedClause, + VersionedClause, VersionedClause, VersionedClause, VersionedClause, VersionedClause, - VersionedClause + VersionedClause, + VersionedClause ]; let allowedOnceClauses = [ - VersionedClause, VersionedClause, VersionedClause, - VersionedClause, - VersionedClause, - VersionedClause, - VersionedClause + VersionedClause ]; } -- GitLab From d3e5c20ab846303874a2a25e5877c72271fc798b Mon Sep 17 00:00:00 2001 From: Peter Klausler <35819229+klausler@users.noreply.github.com> Date: Thu, 30 Nov 2023 13:23:14 -0800 Subject: [PATCH 045/699] [flang] Handle preprocessor macro expansion edge case (#73835) When a reference to a function-like macro begins during the rescanning of the expansion of another macro but is not completed by the end of that expansion, it is necessary to abort that rescanning of that expansion and try again when more tokens can be acquired. (See the new unclosed-FLM.F90 test case.) All other Fortran preprocessors to which I have access can handle this situation. --- flang/lib/Parser/preprocessor.cpp | 232 +++++++++++++--------- flang/lib/Parser/preprocessor.h | 15 +- flang/test/Preprocessing/unclosed-FLM.F90 | 7 + 3 files changed, 152 insertions(+), 102 deletions(-) create mode 100644 flang/test/Preprocessing/unclosed-FLM.F90 diff --git a/flang/lib/Parser/preprocessor.cpp b/flang/lib/Parser/preprocessor.cpp index 88efcf71445c..8c993e7ced0e 100644 --- a/flang/lib/Parser/preprocessor.cpp +++ b/flang/lib/Parser/preprocessor.cpp @@ -259,14 +259,15 @@ void Preprocessor::Define(std::string macro, std::string value) { void Preprocessor::Undefine(std::string macro) { definitions_.erase(macro); } std::optional Preprocessor::MacroReplacement( - const TokenSequence &input, Prescanner &prescanner) { + const TokenSequence &input, Prescanner &prescanner, + std::optional *partialFunctionLikeMacro) { // Do quick scan for any use of a defined name. if (definitions_.empty()) { return std::nullopt; } std::size_t tokens{input.SizeInTokens()}; - std::size_t j; - for (j = 0; j < tokens; ++j) { + std::size_t j{0}; + for (; j < tokens; ++j) { CharBlock token{input.TokenAt(j)}; if (!token.empty() && IsLegalIdentifierStart(token[0]) && IsNameDefined(token)) { @@ -277,6 +278,38 @@ std::optional Preprocessor::MacroReplacement( return std::nullopt; // input contains nothing that would be replaced } TokenSequence result{input, 0, j}; + + // After rescanning after macro replacement has failed due to an unclosed + // function-like macro call (no left parenthesis yet, or no closing + // parenthesis), if tokens remain in the input, append them to the + // replacement text and attempt to proceed. Otherwise, return, so that + // the caller may try again with remaining tokens in its input. + auto CompleteFunctionLikeMacro{ + [this, &input, &prescanner, &result, &partialFunctionLikeMacro]( + std::size_t after, const TokenSequence &replacement, + std::size_t pFLMOffset) { + if (after < input.SizeInTokens()) { + result.Put(replacement, 0, pFLMOffset); + TokenSequence suffix; + suffix.Put( + replacement, pFLMOffset, replacement.SizeInTokens() - pFLMOffset); + suffix.Put(input, after, input.SizeInTokens() - after); + auto further{ + ReplaceMacros(suffix, prescanner, partialFunctionLikeMacro)}; + if (partialFunctionLikeMacro && *partialFunctionLikeMacro) { + // still not closed + **partialFunctionLikeMacro += result.SizeInTokens(); + } + result.Put(further); + return true; + } else { + if (partialFunctionLikeMacro) { + *partialFunctionLikeMacro = pFLMOffset + result.SizeInTokens(); + } + return false; + } + }}; + for (; j < tokens; ++j) { CharBlock token{input.TokenAt(j)}; if (token.IsBlank() || !IsLegalIdentifierStart(token[0])) { @@ -294,20 +327,17 @@ std::optional Preprocessor::MacroReplacement( continue; } if (!def->isFunctionLike()) { - bool isRenaming{false}; - if (def->isPredefined()) { + if (def->isPredefined() && !def->replacement().empty()) { std::string repl; - if (!def->replacement().empty()) { - std::string name{def->replacement().TokenAt(0).ToString()}; - if (name == "__FILE__") { - repl = "\""s + - allSources_.GetPath(prescanner.GetCurrentProvenance()) + '"'; - } else if (name == "__LINE__") { - std::string buf; - llvm::raw_string_ostream ss{buf}; - ss << allSources_.GetLineNumber(prescanner.GetCurrentProvenance()); - repl = ss.str(); - } + std::string name{def->replacement().TokenAt(0).ToString()}; + if (name == "__FILE__") { + repl = "\""s + + allSources_.GetPath(prescanner.GetCurrentProvenance()) + '"'; + } else if (name == "__LINE__") { + std::string buf; + llvm::raw_string_ostream ss{buf}; + ss << allSources_.GetLineNumber(prescanner.GetCurrentProvenance()); + repl = ss.str(); } if (!repl.empty()) { ProvenanceRange insert{allSources_.AddCompilerInsertion(repl)}; @@ -317,105 +347,109 @@ std::optional Preprocessor::MacroReplacement( continue; } } + std::optional partialFLM; def->set_isDisabled(true); - TokenSequence replaced{ - TokenPasting(ReplaceMacros(def->replacement(), prescanner))}; + TokenSequence replaced{TokenPasting( + ReplaceMacros(def->replacement(), prescanner, &partialFLM))}; def->set_isDisabled(false); - // Allow a keyword-like macro replacement to be the name of - // a function-like macro, possibly surrounded by blanks. - std::size_t k{0}, repTokens{replaced.SizeInTokens()}; - for (; k < repTokens && replaced.TokenAt(k).IsBlank(); ++k) { + if (partialFLM && + CompleteFunctionLikeMacro(j + 1, replaced, *partialFLM)) { + return result; + } + if (!replaced.empty()) { + ProvenanceRange from{def->replacement().GetProvenanceRange()}; + ProvenanceRange use{input.GetTokenProvenanceRange(j)}; + ProvenanceRange newRange{ + allSources_.AddMacroCall(from, use, replaced.ToString())}; + result.Put(replaced, newRange); + } + } else { + // Possible function-like macro call. Skip spaces and newlines to see + // whether '(' is next. + std::size_t k{j}; + bool leftParen{false}; + while (++k < tokens) { + const CharBlock &lookAhead{input.TokenAt(k)}; + if (!lookAhead.IsBlank() && lookAhead[0] != '\n') { + leftParen = lookAhead[0] == '(' && lookAhead.size() == 1; + break; + } } - if (k < repTokens) { - token = replaced.TokenAt(k); - for (++k; k < repTokens && replaced.TokenAt(k).IsBlank(); ++k) { + if (!leftParen) { + if (partialFunctionLikeMacro) { + *partialFunctionLikeMacro = result.SizeInTokens(); + result.Put(input, j, tokens - j); + return result; + } else { + result.Put(input, j); + continue; } - if (k == repTokens && IsLegalIdentifierStart(token[0])) { - auto it{definitions_.find(token)}; - if (it != definitions_.end() && !it->second.isDisabled() && - it->second.isFunctionLike()) { - def = &it->second; - isRenaming = true; + } + std::vector argStart{++k}; + for (int nesting{0}; k < tokens; ++k) { + CharBlock token{input.TokenAt(k)}; + char ch{token.OnlyNonBlank()}; + if (ch == '(') { + ++nesting; + } else if (ch == ')') { + if (nesting == 0) { + break; } + --nesting; + } else if (ch == ',' && nesting == 0) { + argStart.push_back(k + 1); } } - if (!isRenaming) { - if (!replaced.empty()) { - ProvenanceRange from{def->replacement().GetProvenanceRange()}; - ProvenanceRange use{input.GetTokenProvenanceRange(j)}; - ProvenanceRange newRange{ - allSources_.AddMacroCall(from, use, replaced.ToString())}; - result.Put(replaced, newRange); - } + if (argStart.size() == 1 && k == argStart[0] && + def->argumentCount() == 0) { + // Subtle: () is zero arguments, not one empty argument, + // unless one argument was expected. + argStart.clear(); + } + if (k >= tokens && partialFunctionLikeMacro) { + *partialFunctionLikeMacro = result.SizeInTokens(); + result.Put(input, j, tokens - j); + return result; + } else if (k >= tokens || argStart.size() < def->argumentCount() || + (argStart.size() > def->argumentCount() && !def->isVariadic())) { + result.Put(input, j); continue; } - } - // Possible function-like macro call. Skip spaces and newlines to see - // whether '(' is next. - std::size_t k{j}; - bool leftParen{false}; - while (++k < tokens) { - const CharBlock &lookAhead{input.TokenAt(k)}; - if (!lookAhead.IsBlank() && lookAhead[0] != '\n') { - leftParen = lookAhead[0] == '(' && lookAhead.size() == 1; - break; + std::vector args; + for (std::size_t n{0}; n < argStart.size(); ++n) { + std::size_t at{argStart[n]}; + std::size_t count{ + (n + 1 == argStart.size() ? k : argStart[n + 1] - 1) - at}; + args.emplace_back(TokenSequence(input, at, count)); } - } - if (!leftParen) { - result.Put(input, j); - continue; - } - std::vector argStart{++k}; - for (int nesting{0}; k < tokens; ++k) { - CharBlock token{input.TokenAt(k)}; - char ch{token.OnlyNonBlank()}; - if (ch == '(') { - ++nesting; - } else if (ch == ')') { - if (nesting == 0) { - break; - } - --nesting; - } else if (ch == ',' && nesting == 0) { - argStart.push_back(k + 1); + TokenSequence applied{def->Apply(args, prescanner)}; + std::optional partialFLM; + def->set_isDisabled(true); + TokenSequence replaced{ + ReplaceMacros(std::move(applied), prescanner, &partialFLM)}; + def->set_isDisabled(false); + if (partialFLM && + CompleteFunctionLikeMacro(k + 1, replaced, *partialFLM)) { + return result; } + if (!replaced.empty()) { + ProvenanceRange from{def->replacement().GetProvenanceRange()}; + ProvenanceRange use{input.GetIntervalProvenanceRange(j, k - j)}; + ProvenanceRange newRange{ + allSources_.AddMacroCall(from, use, replaced.ToString())}; + result.Put(replaced, newRange); + } + j = k; // advance to the terminal ')' } - if (argStart.size() == 1 && k == argStart[0] && def->argumentCount() == 0) { - // Subtle: () is zero arguments, not one empty argument, - // unless one argument was expected. - argStart.clear(); - } - if (k >= tokens || argStart.size() < def->argumentCount() || - (argStart.size() > def->argumentCount() && !def->isVariadic())) { - result.Put(input, j); - continue; - } - std::vector args; - for (std::size_t n{0}; n < argStart.size(); ++n) { - std::size_t at{argStart[n]}; - std::size_t count{ - (n + 1 == argStart.size() ? k : argStart[n + 1] - 1) - at}; - args.emplace_back(TokenSequence(input, at, count)); - } - TokenSequence applied{def->Apply(args, prescanner)}; - def->set_isDisabled(true); - TokenSequence replaced{ReplaceMacros(std::move(applied), prescanner)}; - def->set_isDisabled(false); - if (!replaced.empty()) { - ProvenanceRange from{def->replacement().GetProvenanceRange()}; - ProvenanceRange use{input.GetIntervalProvenanceRange(j, k - j)}; - ProvenanceRange newRange{ - allSources_.AddMacroCall(from, use, replaced.ToString())}; - result.Put(replaced, newRange); - } - j = k; // advance to the terminal ')' } return result; } -TokenSequence Preprocessor::ReplaceMacros( - const TokenSequence &tokens, Prescanner &prescanner) { - if (std::optional repl{MacroReplacement(tokens, prescanner)}) { +TokenSequence Preprocessor::ReplaceMacros(const TokenSequence &tokens, + Prescanner &prescanner, + std::optional *partialFunctionLikeMacro) { + if (std::optional repl{ + MacroReplacement(tokens, prescanner, partialFunctionLikeMacro)}) { return std::move(*repl); } return tokens; diff --git a/flang/lib/Parser/preprocessor.h b/flang/lib/Parser/preprocessor.h index e0617a490957..3b456364944c 100644 --- a/flang/lib/Parser/preprocessor.h +++ b/flang/lib/Parser/preprocessor.h @@ -75,8 +75,16 @@ public: bool IsNameDefined(const CharBlock &); bool IsFunctionLikeDefinition(const CharBlock &); - std::optional MacroReplacement( - const TokenSequence &, Prescanner &); + // When called with partialFunctionLikeMacro not null, MacroReplacement() + // and ReplaceMacros() handle an unclosed function-like macro reference + // by terminating macro replacement at the name of the FLM and returning + // its index in the result. This allows the recursive call sites in + // MacroReplacement to append any remaining tokens in their inputs to + // that result and try again. All other Fortran preprocessors share this + // behavior. + std::optional MacroReplacement(const TokenSequence &, + Prescanner &, + std::optional *partialFunctionLikeMacro = nullptr); // Implements a preprocessor directive. void Directive(const TokenSequence &, Prescanner &); @@ -86,7 +94,8 @@ private: enum class CanDeadElseAppear { No, Yes }; CharBlock SaveTokenAsName(const CharBlock &); - TokenSequence ReplaceMacros(const TokenSequence &, Prescanner &); + TokenSequence ReplaceMacros(const TokenSequence &, Prescanner &, + std::optional *partialFunctionLikeMacro = nullptr); void SkipDisabledConditionalCode( const std::string &, IsElseActive, Prescanner &, ProvenanceRange); bool IsIfPredicateTrue(const TokenSequence &expr, std::size_t first, diff --git a/flang/test/Preprocessing/unclosed-FLM.F90 b/flang/test/Preprocessing/unclosed-FLM.F90 new file mode 100644 index 000000000000..ed8bdbed2f44 --- /dev/null +++ b/flang/test/Preprocessing/unclosed-FLM.F90 @@ -0,0 +1,7 @@ +! RUN: %flang -E %s | FileCheck %s +#define A B(c) +#define B(d) d); call E(d +#define E(f) G(f) +!CHECK: call I(c); call G(c) +call I(A) +end -- GitLab From a4745ff99bec927efdc726fa902e30d589e70761 Mon Sep 17 00:00:00 2001 From: Peter Klausler <35819229+klausler@users.noreply.github.com> Date: Thu, 30 Nov 2023 13:35:07 -0800 Subject: [PATCH 046/699] =?UTF-8?q?[flang]=20Detect=20more=20misparsed=20s?= =?UTF-8?q?tatement=20functions=20(same=20name=20as=20funct=E2=80=A6=20(#7?= =?UTF-8?q?3852)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit …ion result) A function can't return a statement function, so an apparent attempt to define a statement function with the same name as the function's result must be a misparsed assignment statement. --- flang/lib/Semantics/check-declarations.cpp | 3 +++ flang/lib/Semantics/resolve-names.cpp | 3 ++- flang/test/Semantics/stmt-func01.f90 | 30 ++++++++++++++++++++++ flang/test/Semantics/stmt-func02.f90 | 19 ++++++++++++++ 4 files changed, 54 insertions(+), 1 deletion(-) diff --git a/flang/lib/Semantics/check-declarations.cpp b/flang/lib/Semantics/check-declarations.cpp index 71292d3211f9..777e6a9f23fb 100644 --- a/flang/lib/Semantics/check-declarations.cpp +++ b/flang/lib/Semantics/check-declarations.cpp @@ -1357,6 +1357,9 @@ void CheckHelper::CheckSubprogram( if (auto msg{evaluate::CheckStatementFunction( symbol, *stmtFunction, context_.foldingContext())}) { SayWithDeclaration(symbol, std::move(*msg)); + } else if (IsPointer(symbol)) { + SayWithDeclaration(symbol, + "A statement function must not have the POINTER attribute"_err_en_US); } else if (details.result().flags().test(Symbol::Flag::Implicit)) { // 15.6.4 p2 weird requirement if (const Symbol * diff --git a/flang/lib/Semantics/resolve-names.cpp b/flang/lib/Semantics/resolve-names.cpp index 5e2a9be41b90..e1cd34ddf65b 100644 --- a/flang/lib/Semantics/resolve-names.cpp +++ b/flang/lib/Semantics/resolve-names.cpp @@ -3531,7 +3531,8 @@ bool SubprogramVisitor::HandleStmtFunction(const parser::StmtFunctionStmt &x) { Symbol &ultimate{symbol->GetUltimate()}; if (ultimate.has() || ultimate.has() || - CouldBeDataPointerValuedFunction(&ultimate)) { + CouldBeDataPointerValuedFunction(&ultimate) || + (&symbol->owner() == &currScope() && IsFunctionResult(*symbol))) { misparsedStmtFuncFound_ = true; return false; } diff --git a/flang/test/Semantics/stmt-func01.f90 b/flang/test/Semantics/stmt-func01.f90 index fd9b33a52a57..733a7a56dfdb 100644 --- a/flang/test/Semantics/stmt-func01.f90 +++ b/flang/test/Semantics/stmt-func01.f90 @@ -53,3 +53,33 @@ program main sf13(x) = 2.*x end subroutine end + +subroutine s0 + allocatable :: sf + !ERROR: 'sf' is not a callable procedure + sf(x) = 1. +end + +subroutine s1 + asynchronous :: sf + !ERROR: An entity may not have the ASYNCHRONOUS attribute unless it is a variable + sf(x) = 1. +end + +subroutine s2 + pointer :: sf + !ERROR: A statement function must not have the POINTER attribute + sf(x) = 1. +end + +subroutine s3 + save :: sf + !ERROR: The entity 'sf' with an explicit SAVE attribute must be a variable, procedure pointer, or COMMON block + sf(x) = 1. +end + +subroutine s4 + volatile :: sf + !ERROR: VOLATILE attribute may apply only to a variable + sf(x) = 1. +end diff --git a/flang/test/Semantics/stmt-func02.f90 b/flang/test/Semantics/stmt-func02.f90 index 90a89e93530c..0f4e8c034f65 100644 --- a/flang/test/Semantics/stmt-func02.f90 +++ b/flang/test/Semantics/stmt-func02.f90 @@ -25,4 +25,23 @@ module m !ERROR: 'sf' has not been declared as an array or pointer-valued function sf(x) = 4. end + function f() + !ERROR: Recursive call to 'f' requires a distinct RESULT in its declaration + !ERROR: Left-hand side of assignment is not definable + !BECAUSE: 'f()' is not a variable or pointer + f() = 1. ! statement function of same name as function + end + function g() result(r) + !WARNING: Name 'g' from host scope should have a type declaration before its local statement function definition + !ERROR: 'g' is already declared in this scoping unit + g() = 1. ! statement function of same name as function + end + function h1() result(r) + !ERROR: 'r' is not a callable procedure + r() = 1. ! statement function of same name as function result + end + function h2() result(r) + procedure(real), pointer :: r + r() = 1. ! not a statement function + end end -- GitLab From e1395c7bdbe74b632ba7fbd90e2be2b4d82ee09e Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Thu, 30 Nov 2023 15:35:33 -0600 Subject: [PATCH 047/699] [libc] Explicitly pin memory for the client symbol lookup (#73988) Summary: Previously, we determined that coarse grained memory cannot be used in the general case. That removed the buffer used to transfer the memory, however we still had this lookup. Though we do not access the symbol directly, it still conflicts with the agents apparently. Pin this as well. This resolves the problems @lntue was having with the `libc` GPU build. --- libc/utils/gpu/loader/amdgpu/Loader.cpp | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/libc/utils/gpu/loader/amdgpu/Loader.cpp b/libc/utils/gpu/loader/amdgpu/Loader.cpp index 5c28607b2f29..a9a687656efc 100644 --- a/libc/utils/gpu/loader/amdgpu/Loader.cpp +++ b/libc/utils/gpu/loader/amdgpu/Loader.cpp @@ -464,18 +464,20 @@ int load(int argc, char **argv, char **envp, void *image, size_t size, executable, rpc_client_symbol_name, &dev_agent, &rpc_client_sym)) handle_error(err); - void *rpc_client_host; - if (hsa_status_t err = - hsa_amd_memory_pool_allocate(coarsegrained_pool, sizeof(void *), - /*flags=*/0, &rpc_client_host)) - handle_error(err); - void *rpc_client_dev; if (hsa_status_t err = hsa_executable_symbol_get_info( rpc_client_sym, HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_ADDRESS, &rpc_client_dev)) handle_error(err); + // Pin some memory we can use to obtain the address of the rpc client. + void *rpc_client_storage = nullptr; + void *rpc_client_host = nullptr; + if (hsa_status_t err = + hsa_amd_memory_lock(&rpc_client_storage, sizeof(void *), + /*agents=*/nullptr, 0, &rpc_client_host)) + handle_error(err); + // Copy the address of the client buffer from the device to the host. if (hsa_status_t err = hsa_memcpy(rpc_client_host, host_agent, rpc_client_dev, dev_agent, sizeof(void *))) @@ -497,7 +499,7 @@ int load(int argc, char **argv, char **envp, void *image, size_t size, if (hsa_status_t err = hsa_amd_memory_unlock( const_cast(rpc_get_client_buffer(device_id)))) handle_error(err); - if (hsa_status_t err = hsa_amd_memory_pool_free(rpc_client_host)) + if (hsa_status_t err = hsa_amd_memory_unlock(rpc_client_host)) handle_error(err); // Obtain the GPU's fixed-frequency clock rate and copy it to the GPU. -- GitLab From 83aa7250fbc6cc5fe253f4bb7ae7b8561adeff5a Mon Sep 17 00:00:00 2001 From: Teresa Johnson Date: Thu, 30 Nov 2023 13:36:14 -0800 Subject: [PATCH 048/699] [MemProf][NFC] Simplify test case (#73979) Removes some unnecessary testing of dump and dot file formats, to simplify updates to this test. --- .../X86/memprof-duplicate-context-ids.ll | 142 +----------------- 1 file changed, 6 insertions(+), 136 deletions(-) diff --git a/llvm/test/ThinLTO/X86/memprof-duplicate-context-ids.ll b/llvm/test/ThinLTO/X86/memprof-duplicate-context-ids.ll index 5bc2f3005f46..f7ba0d27dca7 100644 --- a/llvm/test/ThinLTO/X86/memprof-duplicate-context-ids.ll +++ b/llvm/test/ThinLTO/X86/memprof-duplicate-context-ids.ll @@ -64,16 +64,10 @@ ; RUN: -r=%t.o,sleep, \ ; RUN: -r=%t.o,_Znam, \ ; RUN: -memprof-verify-ccg -memprof-verify-nodes -memprof-dump-ccg \ -; RUN: -memprof-export-to-dot -memprof-dot-file-path-prefix=%t. \ ; RUN: -stats -pass-remarks=memprof-context-disambiguation -save-temps \ ; RUN: -o %t.out 2>&1 | FileCheck %s --check-prefix=DUMP \ ; RUN: --check-prefix=STATS --check-prefix=STATS-BE --check-prefix=REMARKS -; RUN: cat %t.ccg.prestackupdate.dot | FileCheck %s --check-prefix=DOTPRE -; RUN: cat %t.ccg.postbuild.dot | FileCheck %s --check-prefix=DOTPOST -;; We should clone D once for the cold allocations via C. -; RUN: cat %t.ccg.cloned.dot | FileCheck %s --check-prefix=DOTCLONED - ; RUN: llvm-dis %t.out.1.4.opt.bc -o - | FileCheck %s --check-prefix=IR @@ -86,15 +80,10 @@ ; RUN: -r=%t.o,sleep, \ ; RUN: -r=%t.o,_Znam, \ ; RUN: -memprof-verify-ccg -memprof-verify-nodes -memprof-dump-ccg \ -; RUN: -memprof-export-to-dot -memprof-dot-file-path-prefix=%t2. \ ; RUN: -stats -pass-remarks=memprof-context-disambiguation \ ; RUN: -o %t2.out 2>&1 | FileCheck %s --check-prefix=DUMP \ ; RUN: --check-prefix=STATS -; RUN: cat %t.ccg.prestackupdate.dot | FileCheck %s --check-prefix=DOTPRE -; RUN: cat %t.ccg.postbuild.dot | FileCheck %s --check-prefix=DOTPOST -;; We should clone D once for the cold allocations via C. -; RUN: cat %t.ccg.cloned.dot | FileCheck %s --check-prefix=DOTCLONED ;; Check distributed index ; RUN: llvm-dis %t.o.thinlto.bc -o - | FileCheck %s --check-prefix=DISTRIB @@ -184,22 +173,6 @@ attributes #0 = { noinline optnone} ; DUMP: Edge from Callee [[D]] to Caller: [[C:0x[a-z0-9]+]] AllocTypes: Cold ContextIds: 1 ; DUMP: Edge from Callee [[D]] to Caller: [[F:0x[a-z0-9]+]] AllocTypes: NotCold ContextIds: 2 -; DUMP: Node [[C]] -; DUMP: null Call -; DUMP: AllocTypes: Cold -; DUMP: ContextIds: 1 -; DUMP: CalleeEdges: -; DUMP: Edge from Callee [[D]] to Caller: [[C]] AllocTypes: Cold ContextIds: 1 -; DUMP: CallerEdges: - -; DUMP: Node [[F]] -; DUMP: null Call -; DUMP: AllocTypes: NotCold -; DUMP: ContextIds: 2 -; DUMP: CalleeEdges: -; DUMP: Edge from Callee [[D]] to Caller: [[F]] AllocTypes: NotCold ContextIds: 2 -; DUMP: CallerEdges: - ;; After updating for callsite metadata, we should have generated context ids 3 and 4, ;; along with 2 new nodes for those callsites. All have the same allocation type ;; behavior as the original C node. @@ -216,42 +189,9 @@ attributes #0 = { noinline optnone} ; DUMP: CalleeEdges: ; DUMP: CallerEdges: ; DUMP: Edge from Callee [[D]] to Caller: [[F]] AllocTypes: NotCold ContextIds: 2 -; DUMP: Edge from Callee [[D]] to Caller: [[C2:0x[a-z0-9]+]] AllocTypes: Cold ContextIds: 3 -; DUMP: Edge from Callee [[D]] to Caller: [[B:0x[a-z0-9]+]] AllocTypes: Cold ContextIds: 4 -; DUMP: Edge from Callee [[D]] to Caller: [[E:0x[a-z0-9]+]] AllocTypes: Cold ContextIds: 1 - -; DUMP: Node [[F]] -; DUMP: Callee: 4881081444663423788 (_Z1Dv) Clones: 0 StackIds: 1 (clone 0) -; DUMP: AllocTypes: NotCold -; DUMP: ContextIds: 2 -; DUMP: CalleeEdges: -; DUMP: Edge from Callee [[D]] to Caller: [[F]] AllocTypes: NotCold ContextIds: 2 -; DUMP: CallerEdges: - -; DUMP: Node [[C2]] -; DUMP: Callee: 4881081444663423788 (_Z1Dv) Clones: 0 StackIds: 0 (clone 0) -; DUMP: AllocTypes: Cold -; DUMP: ContextIds: 3 -; DUMP: CalleeEdges: -; DUMP: Edge from Callee [[D]] to Caller: [[C2]] AllocTypes: Cold ContextIds: 3 -; DUMP: CallerEdges: - -; DUMP: Node [[B]] -; DUMP: Callee: 4881081444663423788 (_Z1Dv) Clones: 0 StackIds: 0, 2 (clone 0) -; DUMP: AllocTypes: Cold -; DUMP: ContextIds: 4 -; DUMP: CalleeEdges: -; DUMP: Edge from Callee [[D]] to Caller: [[B]] AllocTypes: Cold ContextIds: 4 -; DUMP: CallerEdges: - -; DUMP: Node [[E]] -; DUMP: Callee: 4881081444663423788 (_Z1Dv) Clones: 0 StackIds: 0, 3 (clone 0) -; DUMP: AllocTypes: Cold -; DUMP: ContextIds: 1 -; DUMP: CalleeEdges: -; DUMP: Edge from Callee [[D]] to Caller: [[E]] AllocTypes: Cold ContextIds: 1 -; DUMP: CallerEdges: - +; DUMP: Edge from Callee [[D]] to Caller: [[C1:0x[a-z0-9]+]] AllocTypes: Cold ContextIds: 3 +; DUMP: Edge from Callee [[D]] to Caller: [[C2:0x[a-z0-9]+]] AllocTypes: Cold ContextIds: 4 +; DUMP: Edge from Callee [[D]] to Caller: [[C0:0x[a-z0-9]+]] AllocTypes: Cold ContextIds: 1 ; DUMP: CCG after cloning: ; DUMP: Callsite Context Graph: @@ -267,38 +207,6 @@ attributes #0 = { noinline optnone} ; DUMP: Edge from Callee [[D]] to Caller: [[F]] AllocTypes: NotCold ContextIds: 2 ; DUMP: Clones: [[D2:0x[a-z0-9]+]] -; DUMP: Node [[F]] -; DUMP: Callee: 4881081444663423788 (_Z1Dv) Clones: 0 StackIds: 1 (clone 0) -; DUMP: AllocTypes: NotCold -; DUMP: ContextIds: 2 -; DUMP: CalleeEdges: -; DUMP: Edge from Callee [[D]] to Caller: [[F]] AllocTypes: NotCold ContextIds: 2 -; DUMP: CallerEdges: - -; DUMP: Node [[C2]] -; DUMP: Callee: 4881081444663423788 (_Z1Dv) Clones: 0 StackIds: 0 (clone 0) -; DUMP: AllocTypes: Cold -; DUMP: ContextIds: 3 -; DUMP: CalleeEdges: -; DUMP: Edge from Callee [[D2]] to Caller: [[C2]] AllocTypes: Cold ContextIds: 3 -; DUMP: CallerEdges: - -; DUMP: Node [[B]] -; DUMP: Callee: 4881081444663423788 (_Z1Dv) Clones: 0 StackIds: 0, 2 (clone 0) -; DUMP: AllocTypes: Cold -; DUMP: ContextIds: 4 -; DUMP: CalleeEdges: -; DUMP: Edge from Callee [[D2]] to Caller: [[B]] AllocTypes: Cold ContextIds: 4 -; DUMP: CallerEdges: - -; DUMP: Node [[E]] -; DUMP: Callee: 4881081444663423788 (_Z1Dv) Clones: 0 StackIds: 0, 3 (clone 0) -; DUMP: AllocTypes: Cold -; DUMP: ContextIds: 1 -; DUMP: CalleeEdges: -; DUMP: Edge from Callee [[D2]] to Caller: [[E]] AllocTypes: Cold ContextIds: 1 -; DUMP: CallerEdges: - ; DUMP: Node [[D2]] ; DUMP: Versions: 1 MIB: ; DUMP: AllocType 2 StackIds: 0 @@ -308,9 +216,9 @@ attributes #0 = { noinline optnone} ; DUMP: ContextIds: 1 3 4 ; DUMP: CalleeEdges: ; DUMP: CallerEdges: -; DUMP: Edge from Callee [[D2]] to Caller: [[E:0x[a-z0-9]+]] AllocTypes: Cold ContextIds: 1 -; DUMP: Edge from Callee [[D2]] to Caller: [[C2:0x[a-z0-9]+]] AllocTypes: Cold ContextIds: 3 -; DUMP: Edge from Callee [[D2]] to Caller: [[B:0x[a-z0-9]+]] AllocTypes: Cold ContextIds: 4 +; DUMP: Edge from Callee [[D2]] to Caller: [[C0]] AllocTypes: Cold ContextIds: 1 +; DUMP: Edge from Callee [[D2]] to Caller: [[C1]] AllocTypes: Cold ContextIds: 3 +; DUMP: Edge from Callee [[D2]] to Caller: [[C2]] AllocTypes: Cold ContextIds: 4 ; DUMP: Clone of [[D]] ; REMARKS: created clone _Z1Dv.memprof.1 @@ -352,44 +260,6 @@ attributes #0 = { noinline optnone} ; STATS-BE: 1 memprof-context-disambiguation - Number of original (not cloned) allocations with memprof profiles during ThinLTO backend -; DOTPRE: digraph "prestackupdate" { -; DOTPRE: label="prestackupdate"; -; DOTPRE: Node[[D:0x[a-z0-9]+]] [shape=record,tooltip="N[[D]] ContextIds: 1 2",fillcolor="mediumorchid1",style="filled",style="filled",label="{OrigId: Alloc0\n_Z1Dv -\> alloc}"]; -; DOTPRE: Node[[C:0x[a-z0-9]+]] [shape=record,tooltip="N[[C]] ContextIds: 1",fillcolor="cyan",style="filled",style="filled",label="{OrigId: 12176601099670543485\nnull call (external)}"]; -; DOTPRE: Node[[C]] -> Node[[D]][tooltip="ContextIds: 1",fillcolor="cyan"]; -; DOTPRE: Node[[F:0x[a-z0-9]+]] [shape=record,tooltip="N[[F]] ContextIds: 2",fillcolor="brown1",style="filled",style="filled",label="{OrigId: 13543580133643026784\nnull call (external)}"]; -; DOTPRE: Node[[F]] -> Node[[D]][tooltip="ContextIds: 2",fillcolor="brown1"]; -; DOTPRE: } - - -; DOTPOST:digraph "postbuild" { -; DOTPOST: label="postbuild"; -; DOTPOST: Node[[D:0x[a-z0-9]+]] [shape=record,tooltip="N[[D]] ContextIds: 1 2 3 4",fillcolor="mediumorchid1",style="filled",style="filled",label="{OrigId: Alloc0\n_Z1Dv -\> alloc}"]; -; DOTPOST: Node[[F:0x[a-z0-9]+]] [shape=record,tooltip="N[[F]] ContextIds: 2",fillcolor="brown1",style="filled",style="filled",label="{OrigId: 13543580133643026784\n_Z1Fv -\> _Z1Dv}"]; -; DOTPOST: Node[[F]] -> Node[[D]][tooltip="ContextIds: 2",fillcolor="brown1"]; -; DOTPOST: Node[[C:0x[a-z0-9]+]] [shape=record,tooltip="N[[C]] ContextIds: 3",fillcolor="cyan",style="filled",style="filled",label="{OrigId: 0\n_Z1Cv -\> _Z1Dv}"]; -; DOTPOST: Node[[C]] -> Node[[D]][tooltip="ContextIds: 3",fillcolor="cyan"]; -; DOTPOST: Node[[B:0x[a-z0-9]+]] [shape=record,tooltip="N[[B]] ContextIds: 4",fillcolor="cyan",style="filled",style="filled",label="{OrigId: 0\n_Z1Bv -\> _Z1Dv}"]; -; DOTPOST: Node[[B]] -> Node[[D]][tooltip="ContextIds: 4",fillcolor="cyan"]; -; DOTPOST: Node[[E:0x[a-z0-9]+]] [shape=record,tooltip="N[[E]] ContextIds: 1",fillcolor="cyan",style="filled",style="filled",label="{OrigId: 0\n_Z1Ev -\> _Z1Dv}"]; -; DOTPOST: Node[[E]] -> Node[[D]][tooltip="ContextIds: 1",fillcolor="cyan"]; -; DOTPOST:} - - -; DOTCLONED: digraph "cloned" { -; DOTCLONED: label="cloned"; -; DOTCLONED: Node[[D:0x[a-z0-9]+]] [shape=record,tooltip="N[[D]] ContextIds: 2",fillcolor="brown1",style="filled",style="filled",label="{OrigId: Alloc0\n_Z1Dv -\> alloc}"]; -; DOTCLONED: Node[[F:0x[a-z0-9]+]] [shape=record,tooltip="N[[F]] ContextIds: 2",fillcolor="brown1",style="filled",style="filled",label="{OrigId: 13543580133643026784\n_Z1Fv -\> _Z1Dv}"]; -; DOTCLONED: Node[[F]] -> Node[[D]][tooltip="ContextIds: 2",fillcolor="brown1"]; -; DOTCLONED: Node[[C:0x[a-z0-9]+]] [shape=record,tooltip="N[[C]] ContextIds: 3",fillcolor="cyan",style="filled",style="filled",label="{OrigId: 0\n_Z1Cv -\> _Z1Dv}"]; -; DOTCLONED: Node[[C]] -> Node[[D2:0x[a-z0-9]+]][tooltip="ContextIds: 3",fillcolor="cyan"]; -; DOTCLONED: Node[[B:0x[a-z0-9]+]] [shape=record,tooltip="N[[B]] ContextIds: 4",fillcolor="cyan",style="filled",style="filled",label="{OrigId: 0\n_Z1Bv -\> _Z1Dv}"]; -; DOTCLONED: Node[[B]] -> Node[[D2]][tooltip="ContextIds: 4",fillcolor="cyan"]; -; DOTCLONED: Node[[E:0x[a-z0-9]+]] [shape=record,tooltip="N[[E]] ContextIds: 1",fillcolor="cyan",style="filled",style="filled",label="{OrigId: 0\n_Z1Ev -\> _Z1Dv}"]; -; DOTCLONED: Node[[E]] -> Node[[D2]][tooltip="ContextIds: 1",fillcolor="cyan"]; -; DOTCLONED: Node[[D2]] [shape=record,tooltip="N[[D2]] ContextIds: 1 3 4",fillcolor="cyan",style="filled",color="blue",style="filled,bold,dashed",label="{OrigId: Alloc0\n_Z1Dv -\> alloc}"]; -; DOTCLONED: } - ; DISTRIB: ^[[C:[0-9]+]] = gv: (guid: 1643923691937891493, {{.*}} callsites: ((callee: ^[[D:[0-9]+]], clones: (1) ; DISTRIB: ^[[D]] = gv: (guid: 4881081444663423788, {{.*}} allocs: ((versions: (notcold, cold) ; DISTRIB: ^[[B:[0-9]+]] = gv: (guid: 14590037969532473829, {{.*}} callsites: ((callee: ^[[D]], clones: (1) -- GitLab From 1b02f594b337618e2e5808a33620eeac19d10e06 Mon Sep 17 00:00:00 2001 From: Jeffrey Byrnes Date: Thu, 30 Nov 2023 13:38:05 -0800 Subject: [PATCH 049/699] [AMDGPU] Rework dot4 signedness checks (#68757) Using the known/unknown value of the sign bit, reason about the signedness version of the dot4 instruction. --- llvm/include/llvm/CodeGen/ByteProvider.h | 16 - llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 171 ++++----- llvm/test/CodeGen/AMDGPU/idot4u.ll | 428 ++++++++++++++++++++++ 3 files changed, 516 insertions(+), 99 deletions(-) diff --git a/llvm/include/llvm/CodeGen/ByteProvider.h b/llvm/include/llvm/CodeGen/ByteProvider.h index adfa59f14b1d..3187b4e68c56 100644 --- a/llvm/include/llvm/CodeGen/ByteProvider.h +++ b/llvm/include/llvm/CodeGen/ByteProvider.h @@ -32,11 +32,6 @@ private: ByteProvider(std::optional Src, int64_t DestOffset, int64_t SrcOffset) : Src(Src), DestOffset(DestOffset), SrcOffset(SrcOffset) {} - ByteProvider(std::optional Src, int64_t DestOffset, int64_t SrcOffset, - std::optional IsSigned) - : Src(Src), DestOffset(DestOffset), SrcOffset(SrcOffset), - IsSigned(IsSigned) {} - // TODO -- use constraint in c++20 // Does this type correspond with an operation in selection DAG template class is_op { @@ -66,9 +61,6 @@ public: // DestOffset int64_t SrcOffset = 0; - // Whether or not the path to this Src involved signed extensions - std::optional IsSigned; - ByteProvider() = default; static ByteProvider getSrc(std::optional Val, int64_t ByteOffset, @@ -78,14 +70,6 @@ public: return ByteProvider(Val, ByteOffset, VectorOffset); } - static ByteProvider getSrc(std::optional Val, int64_t ByteOffset, - int64_t VectorOffset, - std::optional IsSigned) { - static_assert(is_op().value, - "ByteProviders must contain an operation in selection DAG."); - return ByteProvider(Val, ByteOffset, VectorOffset, IsSigned); - } - static ByteProvider getConstantZero() { return ByteProvider(std::nullopt, 0, 0); } diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index d6a768a64ff3..53ab5da01353 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -10940,7 +10940,6 @@ SDValue SITargetLowering::performAndCombine(SDNode *N, // performed. static const std::optional> calculateSrcByte(const SDValue Op, uint64_t DestByte, uint64_t SrcIndex = 0, - std::optional IsSigned = std::nullopt, unsigned Depth = 0) { // We may need to recursively traverse a series of SRLs if (Depth >= 6) @@ -10952,16 +10951,12 @@ calculateSrcByte(const SDValue Op, uint64_t DestByte, uint64_t SrcIndex = 0, switch (Op->getOpcode()) { case ISD::TRUNCATE: { - return calculateSrcByte(Op->getOperand(0), DestByte, SrcIndex, IsSigned, - Depth + 1); + return calculateSrcByte(Op->getOperand(0), DestByte, SrcIndex, Depth + 1); } case ISD::SIGN_EXTEND: case ISD::ZERO_EXTEND: case ISD::SIGN_EXTEND_INREG: { - IsSigned = IsSigned.value_or(false) || - Op->getOpcode() == ISD::SIGN_EXTEND || - Op->getOpcode() == ISD::SIGN_EXTEND_INREG; SDValue NarrowOp = Op->getOperand(0); auto NarrowVT = NarrowOp.getValueType(); if (Op->getOpcode() == ISD::SIGN_EXTEND_INREG) { @@ -10974,8 +10969,7 @@ calculateSrcByte(const SDValue Op, uint64_t DestByte, uint64_t SrcIndex = 0, if (SrcIndex >= NarrowByteWidth) return std::nullopt; - return calculateSrcByte(Op->getOperand(0), DestByte, SrcIndex, IsSigned, - Depth + 1); + return calculateSrcByte(Op->getOperand(0), DestByte, SrcIndex, Depth + 1); } case ISD::SRA: @@ -10991,24 +10985,11 @@ calculateSrcByte(const SDValue Op, uint64_t DestByte, uint64_t SrcIndex = 0, SrcIndex += BitShift / 8; - return calculateSrcByte(Op->getOperand(0), DestByte, SrcIndex, IsSigned, - Depth + 1); + return calculateSrcByte(Op->getOperand(0), DestByte, SrcIndex, Depth + 1); } default: { - if (isa(Op) || Op->isMemIntrinsic()) { - // If this causes us to throw away signedness info, then fail. - if (IsSigned) - return std::nullopt; - return ByteProvider::getSrc(Op, DestByte, SrcIndex); - } - - if (auto L = dyn_cast(Op)) - if (L->getExtensionType() != ISD::NON_EXTLOAD) - IsSigned = - IsSigned.value_or(false) || L->getExtensionType() == ISD::SEXTLOAD; - - return ByteProvider::getSrc(Op, DestByte, SrcIndex, IsSigned); + return ByteProvider::getSrc(Op, DestByte, SrcIndex); } } llvm_unreachable("fully handled switch"); @@ -11022,8 +11003,7 @@ calculateSrcByte(const SDValue Op, uint64_t DestByte, uint64_t SrcIndex = 0, // performed. \p StartingIndex is the originally requested byte of the Or static const std::optional> calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth, - unsigned StartingIndex = 0, - std::optional IsSigned = std::nullopt) { + unsigned StartingIndex = 0) { // Finding Src tree of RHS of or typically requires at least 1 additional // depth if (Depth > 6) @@ -11038,11 +11018,11 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth, switch (Op.getOpcode()) { case ISD::OR: { auto RHS = calculateByteProvider(Op.getOperand(1), Index, Depth + 1, - StartingIndex, IsSigned); + StartingIndex); if (!RHS) return std::nullopt; auto LHS = calculateByteProvider(Op.getOperand(0), Index, Depth + 1, - StartingIndex, IsSigned); + StartingIndex); if (!LHS) return std::nullopt; // A well formed Or will have two ByteProviders for each byte, one of which @@ -11073,7 +11053,7 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth, return ByteProvider::getConstantZero(); } - return calculateSrcByte(Op->getOperand(0), StartingIndex, Index, IsSigned); + return calculateSrcByte(Op->getOperand(0), StartingIndex, Index); } case ISD::FSHR: { @@ -11122,7 +11102,7 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth, // the SRL is Index + ByteShift return BytesProvided - ByteShift > Index ? calculateSrcByte(Op->getOperand(0), StartingIndex, - Index + ByteShift, IsSigned) + Index + ByteShift) : ByteProvider::getConstantZero(); } @@ -11143,7 +11123,7 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth, return Index < ByteShift ? ByteProvider::getConstantZero() : calculateByteProvider(Op.getOperand(0), Index - ByteShift, - Depth + 1, StartingIndex, IsSigned); + Depth + 1, StartingIndex); } case ISD::ANY_EXTEND: case ISD::SIGN_EXTEND: @@ -11163,21 +11143,12 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth, return std::nullopt; uint64_t NarrowByteWidth = NarrowBitWidth / 8; - IsSigned = - Op->getOpcode() != ISD::ANY_EXTEND - ? std::optional(IsSigned.value_or(false) || - Op->getOpcode() == ISD::SIGN_EXTEND || - Op->getOpcode() == ISD::SIGN_EXTEND_INREG || - Op->getOpcode() == ISD::AssertSext) - : IsSigned; - if (Index >= NarrowByteWidth) return Op.getOpcode() == ISD::ZERO_EXTEND ? std::optional>( ByteProvider::getConstantZero()) : std::nullopt; - return calculateByteProvider(NarrowOp, Index, Depth + 1, StartingIndex, - IsSigned); + return calculateByteProvider(NarrowOp, Index, Depth + 1, StartingIndex); } case ISD::TRUNCATE: { @@ -11185,7 +11156,7 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth, if (NarrowByteWidth >= Index) { return calculateByteProvider(Op.getOperand(0), Index, Depth + 1, - StartingIndex, IsSigned); + StartingIndex); } return std::nullopt; @@ -11193,7 +11164,7 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth, case ISD::CopyFromReg: { if (BitWidth / 8 > Index) - return calculateSrcByte(Op, StartingIndex, Index, IsSigned); + return calculateSrcByte(Op, StartingIndex, Index); return std::nullopt; } @@ -11201,10 +11172,6 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth, case ISD::LOAD: { auto L = cast(Op.getNode()); - // Only set IsSigned if the load is extended. - if (L->getExtensionType() != ISD::NON_EXTLOAD) - IsSigned = - IsSigned.value_or(false) || L->getExtensionType() == ISD::SEXTLOAD; unsigned NarrowBitWidth = L->getMemoryVT().getSizeInBits(); if (NarrowBitWidth % 8 != 0) return std::nullopt; @@ -11221,7 +11188,7 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth, } if (NarrowByteWidth > Index) { - return calculateSrcByte(Op, StartingIndex, Index, IsSigned); + return calculateSrcByte(Op, StartingIndex, Index); } return std::nullopt; @@ -11229,7 +11196,7 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth, case ISD::BSWAP: return calculateByteProvider(Op->getOperand(0), BitWidth / 8 - Index - 1, - Depth + 1, StartingIndex, IsSigned); + Depth + 1, StartingIndex); case ISD::EXTRACT_VECTOR_ELT: { auto IdxOp = dyn_cast(Op->getOperand(1)); @@ -11244,7 +11211,7 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth, } return calculateSrcByte(ScalarSize == 32 ? Op : Op.getOperand(0), - StartingIndex, Index, IsSigned); + StartingIndex, Index); } case AMDGPUISD::PERM: { @@ -11260,10 +11227,9 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth, auto NextOp = Op.getOperand(IdxMask > 0x03 ? 0 : 1); auto NextIndex = IdxMask > 0x03 ? IdxMask % 4 : IdxMask; - return IdxMask != 0x0c - ? calculateSrcByte(NextOp, StartingIndex, NextIndex, IsSigned) - : ByteProvider( - ByteProvider::getConstantZero()); + return IdxMask != 0x0c ? calculateSrcByte(NextOp, StartingIndex, NextIndex) + : ByteProvider( + ByteProvider::getConstantZero()); } default: { @@ -13064,32 +13030,67 @@ static bool isMul(const SDValue Op) { Opcode == AMDGPUISD::MUL_I24); } -static std::optional checkSignedness(const SDValue &N, - ByteProvider &Src0, - ByteProvider &Src1) { - auto MulOpcode = N.getOpcode(); - std::optional IterIsSigned; - // Both sides of the tree must have the same signedness semantics. - if ((Src0.IsSigned != Src1.IsSigned) || - (Src0.IsSigned.value_or(false) != Src1.IsSigned.value_or(false))) - return IterIsSigned; - // If we have a MUL_U24 op with signed semantics, then fail. - if (Src0.IsSigned.value_or(false) && MulOpcode == AMDGPUISD::MUL_U24) - return IterIsSigned; - // If we have a MUL_I24 op with unsigned semantics, then fail. - if (!Src0.IsSigned.value_or(true) && MulOpcode == AMDGPUISD::MUL_I24) - return IterIsSigned; - - bool TopLevelSignedness = - MulOpcode == AMDGPUISD::MUL_I24 || - (MulOpcode == ISD::MUL && N.getNode()->getFlags().hasNoSignedWrap() && - !N.getNode()->getFlags().hasNoUnsignedWrap()); - - // In cases where we are accumulating into an i8 (for v_dot4), the - // ByteProvider will not have signedness info since the MSBs are dont-cares. - // In this case, we simply use the TopLevelSignedness of the instruction. - IterIsSigned = Src0.IsSigned.value_or(TopLevelSignedness); - return IterIsSigned; +static std::optional +checkDot4MulSignedness(const SDValue &N, ByteProvider &Src0, + ByteProvider &Src1, const SDValue &S0Op, + const SDValue &S1Op, const SelectionDAG &DAG) { + // If we both ops are i8s (pre legalize-dag), then the signedness semantics + // of the dot4 is irrelevant. + if (S0Op.getValueSizeInBits() == 8 && S1Op.getValueSizeInBits() == 8) + return false; + + auto Known0 = DAG.computeKnownBits(S0Op, 0); + bool S0IsUnsigned = Known0.countMinLeadingZeros() > 0; + bool S0IsSigned = Known0.countMinLeadingOnes() > 0; + auto Known1 = DAG.computeKnownBits(S1Op, 0); + bool S1IsUnsigned = Known1.countMinLeadingZeros() > 0; + bool S1IsSigned = Known1.countMinLeadingOnes() > 0; + + assert(!(S0IsUnsigned && S0IsSigned)); + assert(!(S1IsUnsigned && S1IsSigned)); + + // There are 9 possible permutations of + // {S0IsUnsigned, S0IsSigned, S1IsUnsigned, S1IsSigned} + + // In two permutations, the sign bits are known to be the same for both Ops, + // so simply return Signed / Unsigned corresponding to the MSB + + if ((S0IsUnsigned && S1IsUnsigned) || (S0IsSigned && S1IsSigned)) + return S0IsSigned; + + // In another two permutations, the sign bits are known to be opposite. In + // this case return std::nullopt to indicate a bad match. + + if ((S0IsUnsigned && S1IsSigned) || (S0IsSigned && S1IsUnsigned)) + return std::nullopt; + + // In the remaining five permutations, we don't know the value of the sign + // bit for at least one Op. Since we have a valid ByteProvider, we know that + // the upper bits must be extension bits. Thus, the only ways for the sign + // bit to be unknown is if it was sign extended from unknown value, or if it + // was any extended. In either case, it is correct to use the signed + // version of the signedness semantics of dot4 + + // In two of such permutations, we known the sign bit is set for + // one op, and the other is unknown. It is okay to used signed version of + // dot4. + if ((S0IsSigned && !(S1IsSigned || S1IsUnsigned)) || + ((S1IsSigned && !(S0IsSigned || S0IsUnsigned)))) + return true; + + // In one such permutation, we don't know either of the sign bits. It is okay + // to used the signed version of dot4. + if ((!(S1IsSigned || S1IsUnsigned) && !(S0IsSigned || S0IsUnsigned))) + return true; + + // In two of such permutations, we known the sign bit is unset for + // one op, and the other is unknown. Return std::nullopt to indicate a + // bad match. + if ((S0IsUnsigned && !(S1IsSigned || S1IsUnsigned)) || + ((S1IsUnsigned && !(S0IsSigned || S0IsUnsigned)))) + return std::nullopt; + + llvm_unreachable("Fully covered condition"); } SDValue SITargetLowering::performAddCombine(SDNode *N, @@ -13132,8 +13133,10 @@ SDValue SITargetLowering::performAddCombine(SDNode *N, if (!Src1) break; - auto IterIsSigned = - checkSignedness(TempNode->getOperand(MulIdx), *Src0, *Src1); + auto IterIsSigned = checkDot4MulSignedness( + TempNode->getOperand(MulIdx), *Src0, *Src1, + TempNode->getOperand(MulIdx)->getOperand(0), + TempNode->getOperand(MulIdx)->getOperand(1), DAG); if (!IterIsSigned) break; if (!IsSigned) @@ -13154,8 +13157,10 @@ SDValue SITargetLowering::performAddCombine(SDNode *N, handleMulOperand(TempNode->getOperand(AddIdx)->getOperand(1)); if (!Src1) break; - auto IterIsSigned = - checkSignedness(TempNode->getOperand(AddIdx), *Src0, *Src1); + auto IterIsSigned = checkDot4MulSignedness( + TempNode->getOperand(AddIdx), *Src0, *Src1, + TempNode->getOperand(AddIdx)->getOperand(0), + TempNode->getOperand(AddIdx)->getOperand(1), DAG); if (!IterIsSigned) break; assert(IsSigned); diff --git a/llvm/test/CodeGen/AMDGPU/idot4u.ll b/llvm/test/CodeGen/AMDGPU/idot4u.ll index a82c5215f3b2..ba9ccb4c636f 100644 --- a/llvm/test/CodeGen/AMDGPU/idot4u.ll +++ b/llvm/test/CodeGen/AMDGPU/idot4u.ll @@ -1735,6 +1735,268 @@ entry: ret void } + +define amdgpu_kernel void @notdot4_mixedtypes2(ptr addrspace(1) %src1, +; GFX7-LABEL: notdot4_mixedtypes2: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: s_mov_b32 s10, 0 +; GFX7-NEXT: s_mov_b32 s11, s3 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_mov_b64 s[8:9], s[4:5] +; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX7-NEXT: v_mov_b32_e32 v1, 0 +; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 +; GFX7-NEXT: s_mov_b64 s[8:9], s[6:7] +; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: buffer_load_ushort v1, off, s[0:3], 0 +; GFX7-NEXT: s_waitcnt vmcnt(2) +; GFX7-NEXT: v_bfe_i32 v3, v2, 0, 8 +; GFX7-NEXT: v_bfe_u32 v4, v2, 8, 8 +; GFX7-NEXT: s_waitcnt vmcnt(1) +; GFX7-NEXT: v_bfe_i32 v7, v0, 8, 8 +; GFX7-NEXT: v_and_b32_e32 v7, 0xffff, v7 +; GFX7-NEXT: v_bfe_i32 v5, v2, 16, 8 +; GFX7-NEXT: v_and_b32_e32 v3, 0xffff, v3 +; GFX7-NEXT: v_and_b32_e32 v6, 0xff, v0 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_mad_u32_u24 v1, v4, v7, v1 +; GFX7-NEXT: v_and_b32_e32 v5, 0xffff, v5 +; GFX7-NEXT: v_bfe_u32 v8, v0, 16, 8 +; GFX7-NEXT: v_ashrrev_i32_e32 v0, 24, v0 +; GFX7-NEXT: v_mad_u32_u24 v1, v3, v6, v1 +; GFX7-NEXT: v_lshrrev_b32_e32 v2, 24, v2 +; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX7-NEXT: v_mad_u32_u24 v1, v5, v8, v1 +; GFX7-NEXT: v_mad_u32_u24 v0, v2, v0, v1 +; GFX7-NEXT: buffer_store_short v0, off, s[0:3], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: notdot4_mixedtypes2: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GFX8-NEXT: v_mov_b32_e32 v5, 0xff +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v1, s5 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_dword v3, v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v1, s7 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s6, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_dword v2, v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ushort v4, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(2) +; GFX8-NEXT: v_lshrrev_b32_e32 v9, 8, v3 +; GFX8-NEXT: v_and_b32_e32 v9, 0xff, v9 +; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v3 +; GFX8-NEXT: v_bfe_i32 v7, v3, 0, 8 +; GFX8-NEXT: v_bfe_i32 v6, v6, 0, 8 +; GFX8-NEXT: v_lshrrev_b32_e32 v3, 24, v3 +; GFX8-NEXT: s_waitcnt vmcnt(1) +; GFX8-NEXT: v_lshrrev_b32_e32 v10, 8, v2 +; GFX8-NEXT: v_bfe_i32 v10, v10, 0, 8 +; GFX8-NEXT: v_and_b32_e32 v8, 0xff, v2 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_mad_u16 v4, v9, v10, v4 +; GFX8-NEXT: v_and_b32_sdwa v5, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX8-NEXT: v_lshrrev_b32_e32 v2, 24, v2 +; GFX8-NEXT: v_mad_u16 v4, v7, v8, v4 +; GFX8-NEXT: v_bfe_i32 v2, v2, 0, 8 +; GFX8-NEXT: v_mad_u16 v4, v6, v5, v4 +; GFX8-NEXT: v_mad_u16 v2, v3, v2, v4 +; GFX8-NEXT: flat_store_short v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-NODL-LABEL: notdot4_mixedtypes2: +; GFX9-NODL: ; %bb.0: ; %entry +; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NODL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 +; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-NODL-NEXT: s_movk_i32 s0, 0xff +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: global_load_dword v1, v0, s[4:5] +; GFX9-NODL-NEXT: global_load_dword v2, v0, s[6:7] +; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NODL-NEXT: global_load_ushort v3, v0, s[2:3] +; GFX9-NODL-NEXT: s_waitcnt vmcnt(2) +; GFX9-NODL-NEXT: v_lshrrev_b32_e32 v7, 8, v1 +; GFX9-NODL-NEXT: s_waitcnt vmcnt(1) +; GFX9-NODL-NEXT: v_lshrrev_b32_e32 v8, 8, v2 +; GFX9-NODL-NEXT: v_and_b32_e32 v7, 0xff, v7 +; GFX9-NODL-NEXT: v_bfe_i32 v8, v8, 0, 8 +; GFX9-NODL-NEXT: v_lshrrev_b32_e32 v4, 16, v1 +; GFX9-NODL-NEXT: v_bfe_i32 v5, v1, 0, 8 +; GFX9-NODL-NEXT: v_and_b32_e32 v6, 0xff, v2 +; GFX9-NODL-NEXT: s_waitcnt vmcnt(0) +; GFX9-NODL-NEXT: v_mad_legacy_u16 v3, v7, v8, v3 +; GFX9-NODL-NEXT: v_and_b32_sdwa v9, v2, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX9-NODL-NEXT: v_lshrrev_b32_e32 v2, 24, v2 +; GFX9-NODL-NEXT: v_bfe_i32 v4, v4, 0, 8 +; GFX9-NODL-NEXT: v_mad_legacy_u16 v3, v5, v6, v3 +; GFX9-NODL-NEXT: v_lshrrev_b32_e32 v1, 24, v1 +; GFX9-NODL-NEXT: v_bfe_i32 v2, v2, 0, 8 +; GFX9-NODL-NEXT: v_mad_legacy_u16 v3, v4, v9, v3 +; GFX9-NODL-NEXT: v_mad_legacy_u16 v1, v1, v2, v3 +; GFX9-NODL-NEXT: global_store_short v0, v1, s[2:3] +; GFX9-NODL-NEXT: s_endpgm +; +; GFX9-DL-LABEL: notdot4_mixedtypes2: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 +; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-DL-NEXT: s_movk_i32 s0, 0xff +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: global_load_dword v1, v0, s[4:5] +; GFX9-DL-NEXT: global_load_dword v2, v0, s[6:7] +; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-DL-NEXT: global_load_ushort v3, v0, s[2:3] +; GFX9-DL-NEXT: s_waitcnt vmcnt(2) +; GFX9-DL-NEXT: v_lshrrev_b32_e32 v7, 8, v1 +; GFX9-DL-NEXT: s_waitcnt vmcnt(1) +; GFX9-DL-NEXT: v_lshrrev_b32_e32 v8, 8, v2 +; GFX9-DL-NEXT: v_and_b32_e32 v7, 0xff, v7 +; GFX9-DL-NEXT: v_bfe_i32 v8, v8, 0, 8 +; GFX9-DL-NEXT: v_lshrrev_b32_e32 v4, 16, v1 +; GFX9-DL-NEXT: v_bfe_i32 v5, v1, 0, 8 +; GFX9-DL-NEXT: v_and_b32_e32 v6, 0xff, v2 +; GFX9-DL-NEXT: s_waitcnt vmcnt(0) +; GFX9-DL-NEXT: v_mad_legacy_u16 v3, v7, v8, v3 +; GFX9-DL-NEXT: v_and_b32_sdwa v9, v2, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX9-DL-NEXT: v_lshrrev_b32_e32 v2, 24, v2 +; GFX9-DL-NEXT: v_bfe_i32 v4, v4, 0, 8 +; GFX9-DL-NEXT: v_mad_legacy_u16 v3, v5, v6, v3 +; GFX9-DL-NEXT: v_lshrrev_b32_e32 v1, 24, v1 +; GFX9-DL-NEXT: v_bfe_i32 v2, v2, 0, 8 +; GFX9-DL-NEXT: v_mad_legacy_u16 v3, v4, v9, v3 +; GFX9-DL-NEXT: v_mad_legacy_u16 v1, v1, v2, v3 +; GFX9-DL-NEXT: global_store_short v0, v1, s[2:3] +; GFX9-DL-NEXT: s_endpgm +; +; GFX10-DL-LABEL: notdot4_mixedtypes2: +; GFX10-DL: ; %bb.0: ; %entry +; GFX10-DL-NEXT: s_clause 0x1 +; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 +; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX10-DL-NEXT: v_mov_b32_e32 v8, 0xff +; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-DL-NEXT: s_clause 0x1 +; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5] +; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7] +; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-DL-NEXT: global_load_ushort v3, v0, s[2:3] +; GFX10-DL-NEXT: s_waitcnt vmcnt(2) +; GFX10-DL-NEXT: v_lshrrev_b32_e32 v4, 8, v1 +; GFX10-DL-NEXT: s_waitcnt vmcnt(1) +; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v2 +; GFX10-DL-NEXT: v_lshrrev_b32_e32 v6, 16, v1 +; GFX10-DL-NEXT: v_bfe_i32 v7, v1, 0, 8 +; GFX10-DL-NEXT: v_and_b32_e32 v9, 0xff, v2 +; GFX10-DL-NEXT: v_and_b32_e32 v4, 0xff, v4 +; GFX10-DL-NEXT: v_bfe_i32 v5, v5, 0, 8 +; GFX10-DL-NEXT: v_lshrrev_b32_e32 v1, 24, v1 +; GFX10-DL-NEXT: s_waitcnt vmcnt(0) +; GFX10-DL-NEXT: v_mad_u16 v3, v4, v5, v3 +; GFX10-DL-NEXT: v_bfe_i32 v4, v6, 0, 8 +; GFX10-DL-NEXT: v_and_b32_sdwa v5, v2, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 24, v2 +; GFX10-DL-NEXT: v_mad_u16 v3, v7, v9, v3 +; GFX10-DL-NEXT: v_bfe_i32 v2, v2, 0, 8 +; GFX10-DL-NEXT: v_mad_u16 v3, v4, v5, v3 +; GFX10-DL-NEXT: v_mad_u16 v1, v1, v2, v3 +; GFX10-DL-NEXT: global_store_short v0, v1, s[2:3] +; GFX10-DL-NEXT: s_endpgm +; +; GFX11-DL-LABEL: notdot4_mixedtypes2: +; GFX11-DL: ; %bb.0: ; %entry +; GFX11-DL-NEXT: s_clause 0x1 +; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 +; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 +; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-DL-NEXT: s_clause 0x1 +; GFX11-DL-NEXT: global_load_b32 v1, v0, s[4:5] +; GFX11-DL-NEXT: global_load_b32 v0, v0, s[6:7] +; GFX11-DL-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-DL-NEXT: s_waitcnt vmcnt(1) +; GFX11-DL-NEXT: v_lshrrev_b32_e32 v4, 8, v1 +; GFX11-DL-NEXT: s_waitcnt vmcnt(0) +; GFX11-DL-NEXT: v_and_b32_e32 v9, 0xff, v0 +; GFX11-DL-NEXT: global_load_u16 v3, v2, s[0:1] +; GFX11-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v0 +; GFX11-DL-NEXT: v_lshrrev_b32_e32 v6, 16, v1 +; GFX11-DL-NEXT: v_and_b32_e32 v4, 0xff, v4 +; GFX11-DL-NEXT: v_lshrrev_b32_e32 v7, 16, v0 +; GFX11-DL-NEXT: v_bfe_i32 v8, v1, 0, 8 +; GFX11-DL-NEXT: v_bfe_i32 v5, v5, 0, 8 +; GFX11-DL-NEXT: v_lshrrev_b32_e32 v0, 24, v0 +; GFX11-DL-NEXT: v_lshrrev_b32_e32 v1, 24, v1 +; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3) +; GFX11-DL-NEXT: v_bfe_i32 v0, v0, 0, 8 +; GFX11-DL-NEXT: s_waitcnt vmcnt(0) +; GFX11-DL-NEXT: v_mad_u16 v3, v4, v5, v3 +; GFX11-DL-NEXT: v_bfe_i32 v4, v6, 0, 8 +; GFX11-DL-NEXT: v_and_b32_e32 v5, 0xff, v7 +; GFX11-DL-NEXT: v_mad_u16 v3, v8, v9, v3 +; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-DL-NEXT: v_mad_u16 v3, v4, v5, v3 +; GFX11-DL-NEXT: v_mad_u16 v0, v1, v0, v3 +; GFX11-DL-NEXT: global_store_b16 v2, v0, s[0:1] +; GFX11-DL-NEXT: s_nop 0 +; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-DL-NEXT: s_endpgm + ptr addrspace(1) %src2, + ptr addrspace(1) nocapture %dst) { +entry: + %idx = call i32 @llvm.amdgcn.workitem.id.x() + %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx + %vec1 = load <4 x i8>, ptr addrspace(1) %gep1 + %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx + %vec2 = load <4 x i8>, ptr addrspace(1) %gep2 + + %v1e0 = extractelement <4 x i8> %vec1, i64 0 + %cv1e0 = sext i8 %v1e0 to i16 + %v2e0 = extractelement <4 x i8> %vec2, i64 0 + %cv2e0 = zext i8 %v2e0 to i16 + %mul1 = mul nuw nsw i16 %cv1e0, %cv2e0 + + %v1e1 = extractelement <4 x i8> %vec1, i64 1 + %cv1e1 = zext i8 %v1e1 to i16 + %v2e1 = extractelement <4 x i8> %vec2, i64 1 + %cv2e1 = sext i8 %v2e1 to i16 + %mul2 = mul nuw nsw i16 %cv1e1, %cv2e1 + + %v1e2 = extractelement <4 x i8> %vec1, i64 2 + %cv1e2 = sext i8 %v1e2 to i16 + %v2e2 = extractelement <4 x i8> %vec2, i64 2 + %cv2e2 = zext i8 %v2e2 to i16 + %mul3 = mul nuw nsw i16 %cv1e2, %cv2e2 + + %v1e3 = extractelement <4 x i8> %vec1, i64 3 + %cv1e3 = zext i8 %v1e3 to i16 + %v2e3 = extractelement <4 x i8> %vec2, i64 3 + %cv2e3 = sext i8 %v2e3 to i16 + %mul4 = mul nuw nsw i16 %cv1e3, %cv2e3 + + %acc = load i16, ptr addrspace(1) %dst, align 2 + %add1 = add i16 %mul2, %acc + %add2 = add i16 %add1, %mul1 + %add3 = add i16 %add2, %mul3 + %add4 = add i16 %add3, %mul4 + + store i16 %add4, ptr addrspace(1) %dst, align 2 + ret void +} + ; TODO: cleanup s_lshr_b32 define amdgpu_kernel void @udot4_acc32_vecMul(ptr addrspace(1) %src1, ; GFX7-LABEL: udot4_acc32_vecMul: @@ -4622,4 +4884,170 @@ entry: ret void } +define amdgpu_kernel void @idot4_acc32_anyext(ptr addrspace(1) %src1, +; GFX7-LABEL: idot4_acc32_anyext: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: s_mov_b32 s10, 0 +; GFX7-NEXT: s_mov_b32 s11, s3 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_mov_b64 s[8:9], s[4:5] +; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX7-NEXT: v_mov_b32_e32 v1, 0 +; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 +; GFX7-NEXT: s_mov_b64 s[8:9], s[6:7] +; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64 +; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_waitcnt vmcnt(1) +; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v2 +; GFX7-NEXT: v_bfe_u32 v2, v2, 8, 8 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_bfe_u32 v0, v0, 8, 8 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: v_mad_u32_u24 v1, v1, v1, s4 +; GFX7-NEXT: v_mad_u32_u24 v0, v2, v0, v1 +; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: idot4_acc32_anyext: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v1, s5 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_dword v3, v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v1, s7 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s6, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_dword v0, v[0:1] +; GFX8-NEXT: s_load_dword s2, s[0:1], 0x0 +; GFX8-NEXT: s_waitcnt vmcnt(1) +; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v3 +; GFX8-NEXT: v_bfe_u32 v2, v3, 8, 8 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mad_u32_u24 v1, v1, v1, s2 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_bfe_u32 v0, v0, 8, 8 +; GFX8-NEXT: v_mad_u32_u24 v2, v2, v0, v1 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-NODL-LABEL: idot4_acc32_anyext: +; GFX9-NODL: ; %bb.0: ; %entry +; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NODL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 +; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: global_load_dword v1, v0, s[4:5] +; GFX9-NODL-NEXT: global_load_dword v2, v0, s[6:7] +; GFX9-NODL-NEXT: s_load_dword s0, s[2:3], 0x0 +; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NODL-NEXT: s_waitcnt vmcnt(1) +; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v3, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 +; GFX9-NODL-NEXT: s_waitcnt vmcnt(0) +; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1 +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: v_add3_u32 v1, v3, s0, v1 +; GFX9-NODL-NEXT: global_store_dword v0, v1, s[2:3] +; GFX9-NODL-NEXT: s_endpgm +; +; GFX9-DL-LABEL: idot4_acc32_anyext: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 +; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-DL-NEXT: s_mov_b32 s1, 0xc0c0500 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: global_load_dword v1, v0, s[4:5] +; GFX9-DL-NEXT: global_load_dword v2, v0, s[6:7] +; GFX9-DL-NEXT: s_load_dword s0, s[2:3], 0x0 +; GFX9-DL-NEXT: s_mov_b32 s4, 0xc0c0100 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-DL-NEXT: s_waitcnt vmcnt(0) +; GFX9-DL-NEXT: v_perm_b32 v2, v2, v1, s1 +; GFX9-DL-NEXT: v_perm_b32 v1, v1, v1, s4 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: v_dot4_u32_u8 v1, v1, v2, s0 +; GFX9-DL-NEXT: global_store_dword v0, v1, s[2:3] +; GFX9-DL-NEXT: s_endpgm +; +; GFX10-DL-LABEL: idot4_acc32_anyext: +; GFX10-DL: ; %bb.0: ; %entry +; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-DL-NEXT: s_clause 0x1 +; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5] +; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7] +; GFX10-DL-NEXT: s_load_dword s2, s[0:1], 0x0 +; GFX10-DL-NEXT: s_waitcnt vmcnt(0) +; GFX10-DL-NEXT: v_perm_b32 v0, v2, v1, 0xc0c0500 +; GFX10-DL-NEXT: v_perm_b32 v1, v1, v1, 0xc0c0100 +; GFX10-DL-NEXT: v_mov_b32_e32 v2, 0 +; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-DL-NEXT: v_dot4_u32_u8 v0, v1, v0, s2 +; GFX10-DL-NEXT: global_store_dword v2, v0, s[0:1] +; GFX10-DL-NEXT: s_endpgm +; +; GFX11-DL-LABEL: idot4_acc32_anyext: +; GFX11-DL: ; %bb.0: ; %entry +; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 +; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 +; GFX11-DL-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-DL-NEXT: s_clause 0x1 +; GFX11-DL-NEXT: global_load_b32 v1, v0, s[4:5] +; GFX11-DL-NEXT: global_load_b32 v0, v0, s[6:7] +; GFX11-DL-NEXT: s_load_b32 s2, s[0:1], 0x0 +; GFX11-DL-NEXT: s_waitcnt vmcnt(0) +; GFX11-DL-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0500 +; GFX11-DL-NEXT: v_perm_b32 v1, v1, v1, 0xc0c0100 +; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-DL-NEXT: v_dot4_u32_u8 v0, v1, v0, s2 +; GFX11-DL-NEXT: global_store_b32 v2, v0, s[0:1] +; GFX11-DL-NEXT: s_nop 0 +; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-DL-NEXT: s_endpgm + ptr addrspace(1) %src2, + ptr addrspace(1) nocapture %dst) { +entry: + %idx = call i32 @llvm.amdgcn.workitem.id.x() + %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx + %vec1 = load <4 x i8>, ptr addrspace(1) %gep1 + %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx + %vec2 = load <4 x i8>, ptr addrspace(1) %gep2 + + %v1e0 = extractelement <4 x i8> %vec1, i64 0 + %cv1e0t = sext i8 %v1e0 to i32 + %cv1e0 = and i32 %cv1e0t, 255 + %v2e0 = extractelement <4 x i8> %vec2, i64 0 + %cv2e0t = sext i8 %v2e0 to i32 + %cv2e0 = and i32 %cv1e0t, 255 + %mul1 = mul nuw nsw i32 %cv1e0, %cv2e0 + + %v1e1 = extractelement <4 x i8> %vec1, i64 1 + %cv1e1 = zext i8 %v1e1 to i32 + %v2e1 = extractelement <4 x i8> %vec2, i64 1 + %cv2e1t = sext i8 %v2e1 to i32 + %cv2e1 = and i32 %cv2e1t, 255 + %mul2 = mul nuw nsw i32 %cv1e1, %cv2e1 + + %acc = load i32, ptr addrspace(1) %dst, align 4 + %add1 = add i32 %mul1, %acc + %add2 = add i32 %add1, %mul2 + store i32 %add2, ptr addrspace(1) %dst, align 4 + ret void +} + declare i32 @llvm.amdgcn.workitem.id.x() -- GitLab From fce4c0acd6db4bd8598db7eb471ccca60dc05406 Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Thu, 30 Nov 2023 13:47:47 -0800 Subject: [PATCH 050/699] [OpenMP] Start organizing PluginManager, PluginAdaptors (#73875) --- openmp/libomptarget/include/PluginManager.h | 226 ++++++++++++++++++ openmp/libomptarget/include/device.h | 67 +----- openmp/libomptarget/include/rtl.h | 150 ------------ openmp/libomptarget/src/CMakeLists.txt | 1 + openmp/libomptarget/src/OpenMP/InteropAPI.cpp | 1 + openmp/libomptarget/src/PluginManager.cpp | 15 ++ openmp/libomptarget/src/api.cpp | 1 + openmp/libomptarget/src/device.cpp | 3 +- openmp/libomptarget/src/interface.cpp | 1 + openmp/libomptarget/src/omptarget.cpp | 1 + openmp/libomptarget/src/rtl.cpp | 27 +-- 11 files changed, 264 insertions(+), 229 deletions(-) create mode 100644 openmp/libomptarget/include/PluginManager.h create mode 100644 openmp/libomptarget/src/PluginManager.cpp diff --git a/openmp/libomptarget/include/PluginManager.h b/openmp/libomptarget/include/PluginManager.h new file mode 100644 index 000000000000..6a91e245453c --- /dev/null +++ b/openmp/libomptarget/include/PluginManager.h @@ -0,0 +1,226 @@ +//===-- PluginManager.h - Plugin loading and communication API --*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Declarations for managing devices that are handled by RTL plugins. +// +//===----------------------------------------------------------------------===// + +#ifndef OMPTARGET_PLUGIN_MANAGER_H +#define OMPTARGET_PLUGIN_MANAGER_H + +#include "Shared/APITypes.h" + +#include "device.h" + +#include "llvm/ADT/DenseSet.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/Support/DynamicLibrary.h" + +#include +#include + +struct PluginAdaptorTy { + typedef int32_t(init_plugin_ty)(); + typedef int32_t(is_valid_binary_ty)(void *); + typedef int32_t(is_valid_binary_info_ty)(void *, void *); + typedef int32_t(is_data_exchangable_ty)(int32_t, int32_t); + typedef int32_t(number_of_devices_ty)(); + typedef int32_t(init_device_ty)(int32_t); + typedef __tgt_target_table *(load_binary_ty)(int32_t, void *); + typedef void *(data_alloc_ty)(int32_t, int64_t, void *, int32_t); + typedef int32_t(data_submit_ty)(int32_t, void *, void *, int64_t); + typedef int32_t(data_submit_async_ty)(int32_t, void *, void *, int64_t, + __tgt_async_info *); + typedef int32_t(data_retrieve_ty)(int32_t, void *, void *, int64_t); + typedef int32_t(data_retrieve_async_ty)(int32_t, void *, void *, int64_t, + __tgt_async_info *); + typedef int32_t(data_exchange_ty)(int32_t, void *, int32_t, void *, int64_t); + typedef int32_t(data_exchange_async_ty)(int32_t, void *, int32_t, void *, + int64_t, __tgt_async_info *); + typedef int32_t(data_delete_ty)(int32_t, void *, int32_t); + typedef int32_t(launch_kernel_ty)(int32_t, void *, void **, ptrdiff_t *, + const KernelArgsTy *, __tgt_async_info *); + typedef int64_t(init_requires_ty)(int64_t); + typedef int32_t(synchronize_ty)(int32_t, __tgt_async_info *); + typedef int32_t(query_async_ty)(int32_t, __tgt_async_info *); + typedef int32_t(supports_empty_images_ty)(); + typedef void(print_device_info_ty)(int32_t); + typedef void(set_info_flag_ty)(uint32_t); + typedef int32_t(create_event_ty)(int32_t, void **); + typedef int32_t(record_event_ty)(int32_t, void *, __tgt_async_info *); + typedef int32_t(wait_event_ty)(int32_t, void *, __tgt_async_info *); + typedef int32_t(sync_event_ty)(int32_t, void *); + typedef int32_t(destroy_event_ty)(int32_t, void *); + typedef int32_t(release_async_info_ty)(int32_t, __tgt_async_info *); + typedef int32_t(init_async_info_ty)(int32_t, __tgt_async_info **); + typedef int64_t(init_device_into_ty)(int64_t, __tgt_device_info *, + const char **); + typedef int32_t(data_lock_ty)(int32_t, void *, int64_t, void **); + typedef int32_t(data_unlock_ty)(int32_t, void *); + typedef int32_t(data_notify_mapped_ty)(int32_t, void *, int64_t); + typedef int32_t(data_notify_unmapped_ty)(int32_t, void *); + typedef int32_t(set_device_offset_ty)(int32_t); + typedef int32_t(activate_record_replay_ty)(int32_t, uint64_t, void *, bool, + bool, uint64_t &); + + int32_t Idx = -1; // RTL index, index is the number of devices + // of other RTLs that were registered before, + // i.e. the OpenMP index of the first device + // to be registered with this RTL. + int32_t NumberOfDevices = -1; // Number of devices this RTL deals with. + + std::unique_ptr LibraryHandler; + +#ifdef OMPTARGET_DEBUG + std::string RTLName; +#endif + + // Functions implemented in the RTL. + init_plugin_ty *init_plugin = nullptr; + is_valid_binary_ty *is_valid_binary = nullptr; + is_valid_binary_info_ty *is_valid_binary_info = nullptr; + is_data_exchangable_ty *is_data_exchangable = nullptr; + number_of_devices_ty *number_of_devices = nullptr; + init_device_ty *init_device = nullptr; + load_binary_ty *load_binary = nullptr; + data_alloc_ty *data_alloc = nullptr; + data_submit_ty *data_submit = nullptr; + data_submit_async_ty *data_submit_async = nullptr; + data_retrieve_ty *data_retrieve = nullptr; + data_retrieve_async_ty *data_retrieve_async = nullptr; + data_exchange_ty *data_exchange = nullptr; + data_exchange_async_ty *data_exchange_async = nullptr; + data_delete_ty *data_delete = nullptr; + launch_kernel_ty *launch_kernel = nullptr; + init_requires_ty *init_requires = nullptr; + synchronize_ty *synchronize = nullptr; + query_async_ty *query_async = nullptr; + supports_empty_images_ty *supports_empty_images = nullptr; + set_info_flag_ty *set_info_flag = nullptr; + print_device_info_ty *print_device_info = nullptr; + create_event_ty *create_event = nullptr; + record_event_ty *record_event = nullptr; + wait_event_ty *wait_event = nullptr; + sync_event_ty *sync_event = nullptr; + destroy_event_ty *destroy_event = nullptr; + init_async_info_ty *init_async_info = nullptr; + init_device_into_ty *init_device_info = nullptr; + release_async_info_ty *release_async_info = nullptr; + data_lock_ty *data_lock = nullptr; + data_unlock_ty *data_unlock = nullptr; + data_notify_mapped_ty *data_notify_mapped = nullptr; + data_notify_unmapped_ty *data_notify_unmapped = nullptr; + set_device_offset_ty *set_device_offset = nullptr; + activate_record_replay_ty *activate_record_replay = nullptr; + + // Are there images associated with this RTL. + bool IsUsed = false; + + llvm::DenseSet UsedImages; + + // Mutex for thread-safety when calling RTL interface functions. + // It is easier to enforce thread-safety at the libomptarget level, + // so that developers of new RTLs do not have to worry about it. + std::mutex Mtx; +}; + +/// RTLs identified in the system. +struct PluginAdaptorManagerTy { + // List of the detected runtime libraries. + std::list AllRTLs; + + // Array of pointers to the detected runtime libraries that have compatible + // binaries. + llvm::SmallVector UsedRTLs; + + int64_t RequiresFlags = OMP_REQ_UNDEFINED; + + explicit PluginAdaptorManagerTy() = default; + + // Register the clauses of the requires directive. + void registerRequires(int64_t Flags); + + // Initialize RTL if it has not been initialized + void initRTLonce(PluginAdaptorTy &RTL); + + // Initialize all RTLs + void initAllRTLs(); + + // Register a shared library with all (compatible) RTLs. + void registerLib(__tgt_bin_desc *Desc); + + // Unregister a shared library from all RTLs. + void unregisterLib(__tgt_bin_desc *Desc); + + // not thread-safe, called from global constructor (i.e. once) + void loadRTLs(); + +private: + static bool attemptLoadRTL(const std::string &RTLName, PluginAdaptorTy &RTL); +}; + +/// Struct for the data required to handle plugins +struct PluginManager { + PluginManager(bool UseEventsForAtomicTransfers) + : UseEventsForAtomicTransfers(UseEventsForAtomicTransfers) {} + + /// RTLs identified on the host + PluginAdaptorManagerTy RTLs; + + /// Executable images and information extracted from the input images passed + /// to the runtime. + std::list> Images; + + /// Devices associated with RTLs + llvm::SmallVector> Devices; + std::mutex RTLsMtx; ///< For RTLs and Devices + + /// Translation table retreived from the binary + HostEntriesBeginToTransTableTy HostEntriesBeginToTransTable; + std::mutex TrlTblMtx; ///< For Translation Table + /// Host offload entries in order of image registration + llvm::SmallVector<__tgt_offload_entry *> HostEntriesBeginRegistrationOrder; + + /// Map from ptrs on the host to an entry in the Translation Table + HostPtrToTableMapTy HostPtrToTableMap; + std::mutex TblMapMtx; ///< For HostPtrToTableMap + + // Store target policy (disabled, mandatory, default) + kmp_target_offload_kind_t TargetOffloadPolicy = tgt_default; + std::mutex TargetOffloadMtx; ///< For TargetOffloadPolicy + + /// Flag to indicate if we use events to ensure the atomicity of + /// map clauses or not. Can be modified with an environment variable. + const bool UseEventsForAtomicTransfers; + + // Work around for plugins that call dlopen on shared libraries that call + // tgt_register_lib during their initialisation. Stash the pointers in a + // vector until the plugins are all initialised and then register them. + bool delayRegisterLib(__tgt_bin_desc *Desc) { + if (RTLsLoaded) + return false; + DelayedBinDesc.push_back(Desc); + return true; + } + + void registerDelayedLibraries() { + // Only called by libomptarget constructor + RTLsLoaded = true; + for (auto *Desc : DelayedBinDesc) + __tgt_register_lib(Desc); + DelayedBinDesc.clear(); + } + +private: + bool RTLsLoaded = false; + llvm::SmallVector<__tgt_bin_desc *> DelayedBinDesc; +}; + +extern PluginManager *PM; + +#endif // OMPTARGET_PLUGIN_MANAGER_H diff --git a/openmp/libomptarget/include/device.h b/openmp/libomptarget/include/device.h index 9cea6e6c9393..5e58879bd738 100644 --- a/openmp/libomptarget/include/device.h +++ b/openmp/libomptarget/include/device.h @@ -28,10 +28,8 @@ #include "OpenMP/Mapping.h" -#include "llvm/ADT/SmallVector.h" - // Forward declarations. -struct RTLInfoTy; +struct PluginAdaptorTy; struct __tgt_bin_desc; struct __tgt_target_table; @@ -53,7 +51,7 @@ typedef std::map<__tgt_bin_desc *, PendingCtorDtorListsTy> struct DeviceTy { int32_t DeviceID; - RTLInfoTy *RTL; + PluginAdaptorTy *RTL; int32_t RTLDeviceID; bool IsInit; @@ -77,7 +75,7 @@ struct DeviceTy { std::mutex PendingGlobalsMtx; - DeviceTy(RTLInfoTy *RTL); + DeviceTy(PluginAdaptorTy *RTL); // DeviceTy is not copyable DeviceTy(const DeviceTy &D) = delete; DeviceTy &operator=(const DeviceTy &D) = delete; @@ -243,63 +241,4 @@ private: extern bool deviceIsReady(int DeviceNum); -/// Struct for the data required to handle plugins -struct PluginManager { - PluginManager(bool UseEventsForAtomicTransfers) - : UseEventsForAtomicTransfers(UseEventsForAtomicTransfers) {} - - /// RTLs identified on the host - RTLsTy RTLs; - - /// Executable images and information extracted from the input images passed - /// to the runtime. - std::list> Images; - - /// Devices associated with RTLs - llvm::SmallVector> Devices; - std::mutex RTLsMtx; ///< For RTLs and Devices - - /// Translation table retreived from the binary - HostEntriesBeginToTransTableTy HostEntriesBeginToTransTable; - std::mutex TrlTblMtx; ///< For Translation Table - /// Host offload entries in order of image registration - llvm::SmallVector<__tgt_offload_entry *> HostEntriesBeginRegistrationOrder; - - /// Map from ptrs on the host to an entry in the Translation Table - HostPtrToTableMapTy HostPtrToTableMap; - std::mutex TblMapMtx; ///< For HostPtrToTableMap - - // Store target policy (disabled, mandatory, default) - kmp_target_offload_kind_t TargetOffloadPolicy = tgt_default; - std::mutex TargetOffloadMtx; ///< For TargetOffloadPolicy - - /// Flag to indicate if we use events to ensure the atomicity of - /// map clauses or not. Can be modified with an environment variable. - const bool UseEventsForAtomicTransfers; - - // Work around for plugins that call dlopen on shared libraries that call - // tgt_register_lib during their initialisation. Stash the pointers in a - // vector until the plugins are all initialised and then register them. - bool delayRegisterLib(__tgt_bin_desc *Desc) { - if (RTLsLoaded) - return false; - DelayedBinDesc.push_back(Desc); - return true; - } - - void registerDelayedLibraries() { - // Only called by libomptarget constructor - RTLsLoaded = true; - for (auto *Desc : DelayedBinDesc) - __tgt_register_lib(Desc); - DelayedBinDesc.clear(); - } - -private: - bool RTLsLoaded = false; - llvm::SmallVector<__tgt_bin_desc *> DelayedBinDesc; -}; - -extern PluginManager *PM; - #endif diff --git a/openmp/libomptarget/include/rtl.h b/openmp/libomptarget/include/rtl.h index 49a62685dcdb..d110e89de5f1 100644 --- a/openmp/libomptarget/include/rtl.h +++ b/openmp/libomptarget/include/rtl.h @@ -13,162 +13,12 @@ #ifndef _OMPTARGET_RTL_H #define _OMPTARGET_RTL_H -#include "omptarget.h" -#include "llvm/ADT/DenseSet.h" #include "llvm/ADT/SmallVector.h" -#include "llvm/Support/DynamicLibrary.h" #include "omptarget.h" #include -#include #include -#include -#include - -// Forward declarations. -struct DeviceTy; -struct __tgt_bin_desc; - -struct RTLInfoTy { - typedef int32_t(init_plugin_ty)(); - typedef int32_t(is_valid_binary_ty)(void *); - typedef int32_t(is_valid_binary_info_ty)(void *, void *); - typedef int32_t(is_data_exchangable_ty)(int32_t, int32_t); - typedef int32_t(number_of_devices_ty)(); - typedef int32_t(init_device_ty)(int32_t); - typedef __tgt_target_table *(load_binary_ty)(int32_t, void *); - typedef void *(data_alloc_ty)(int32_t, int64_t, void *, int32_t); - typedef int32_t(data_submit_ty)(int32_t, void *, void *, int64_t); - typedef int32_t(data_submit_async_ty)(int32_t, void *, void *, int64_t, - __tgt_async_info *); - typedef int32_t(data_retrieve_ty)(int32_t, void *, void *, int64_t); - typedef int32_t(data_retrieve_async_ty)(int32_t, void *, void *, int64_t, - __tgt_async_info *); - typedef int32_t(data_exchange_ty)(int32_t, void *, int32_t, void *, int64_t); - typedef int32_t(data_exchange_async_ty)(int32_t, void *, int32_t, void *, - int64_t, __tgt_async_info *); - typedef int32_t(data_delete_ty)(int32_t, void *, int32_t); - typedef int32_t(launch_kernel_ty)(int32_t, void *, void **, ptrdiff_t *, - const KernelArgsTy *, __tgt_async_info *); - typedef int64_t(init_requires_ty)(int64_t); - typedef int32_t(synchronize_ty)(int32_t, __tgt_async_info *); - typedef int32_t(query_async_ty)(int32_t, __tgt_async_info *); - typedef int32_t(supports_empty_images_ty)(); - typedef void(print_device_info_ty)(int32_t); - typedef void(set_info_flag_ty)(uint32_t); - typedef int32_t(create_event_ty)(int32_t, void **); - typedef int32_t(record_event_ty)(int32_t, void *, __tgt_async_info *); - typedef int32_t(wait_event_ty)(int32_t, void *, __tgt_async_info *); - typedef int32_t(sync_event_ty)(int32_t, void *); - typedef int32_t(destroy_event_ty)(int32_t, void *); - typedef int32_t(release_async_info_ty)(int32_t, __tgt_async_info *); - typedef int32_t(init_async_info_ty)(int32_t, __tgt_async_info **); - typedef int64_t(init_device_into_ty)(int64_t, __tgt_device_info *, - const char **); - typedef int32_t(data_lock_ty)(int32_t, void *, int64_t, void **); - typedef int32_t(data_unlock_ty)(int32_t, void *); - typedef int32_t(data_notify_mapped_ty)(int32_t, void *, int64_t); - typedef int32_t(data_notify_unmapped_ty)(int32_t, void *); - typedef int32_t(set_device_offset_ty)(int32_t); - typedef int32_t(activate_record_replay_ty)(int32_t, uint64_t, void *, bool, - bool, uint64_t &); - - int32_t Idx = -1; // RTL index, index is the number of devices - // of other RTLs that were registered before, - // i.e. the OpenMP index of the first device - // to be registered with this RTL. - int32_t NumberOfDevices = -1; // Number of devices this RTL deals with. - - std::unique_ptr LibraryHandler; - -#ifdef OMPTARGET_DEBUG - std::string RTLName; -#endif - - // Functions implemented in the RTL. - init_plugin_ty *init_plugin = nullptr; - is_valid_binary_ty *is_valid_binary = nullptr; - is_valid_binary_info_ty *is_valid_binary_info = nullptr; - is_data_exchangable_ty *is_data_exchangable = nullptr; - number_of_devices_ty *number_of_devices = nullptr; - init_device_ty *init_device = nullptr; - load_binary_ty *load_binary = nullptr; - data_alloc_ty *data_alloc = nullptr; - data_submit_ty *data_submit = nullptr; - data_submit_async_ty *data_submit_async = nullptr; - data_retrieve_ty *data_retrieve = nullptr; - data_retrieve_async_ty *data_retrieve_async = nullptr; - data_exchange_ty *data_exchange = nullptr; - data_exchange_async_ty *data_exchange_async = nullptr; - data_delete_ty *data_delete = nullptr; - launch_kernel_ty *launch_kernel = nullptr; - init_requires_ty *init_requires = nullptr; - synchronize_ty *synchronize = nullptr; - query_async_ty *query_async = nullptr; - supports_empty_images_ty *supports_empty_images = nullptr; - set_info_flag_ty *set_info_flag = nullptr; - print_device_info_ty *print_device_info = nullptr; - create_event_ty *create_event = nullptr; - record_event_ty *record_event = nullptr; - wait_event_ty *wait_event = nullptr; - sync_event_ty *sync_event = nullptr; - destroy_event_ty *destroy_event = nullptr; - init_async_info_ty *init_async_info = nullptr; - init_device_into_ty *init_device_info = nullptr; - release_async_info_ty *release_async_info = nullptr; - data_lock_ty *data_lock = nullptr; - data_unlock_ty *data_unlock = nullptr; - data_notify_mapped_ty *data_notify_mapped = nullptr; - data_notify_unmapped_ty *data_notify_unmapped = nullptr; - set_device_offset_ty *set_device_offset = nullptr; - activate_record_replay_ty *activate_record_replay = nullptr; - - // Are there images associated with this RTL. - bool IsUsed = false; - - llvm::DenseSet UsedImages; - - // Mutex for thread-safety when calling RTL interface functions. - // It is easier to enforce thread-safety at the libomptarget level, - // so that developers of new RTLs do not have to worry about it. - std::mutex Mtx; -}; - -/// RTLs identified in the system. -struct RTLsTy { - // List of the detected runtime libraries. - std::list AllRTLs; - - // Array of pointers to the detected runtime libraries that have compatible - // binaries. - llvm::SmallVector UsedRTLs; - - int64_t RequiresFlags = OMP_REQ_UNDEFINED; - - explicit RTLsTy() = default; - - // Register the clauses of the requires directive. - void registerRequires(int64_t Flags); - - // Initialize RTL if it has not been initialized - void initRTLonce(RTLInfoTy &RTL); - - // Initialize all RTLs - void initAllRTLs(); - - // Register a shared library with all (compatible) RTLs. - void registerLib(__tgt_bin_desc *Desc); - - // Unregister a shared library from all RTLs. - void unregisterLib(__tgt_bin_desc *Desc); - - // not thread-safe, called from global constructor (i.e. once) - void loadRTLs(); - -private: - static bool attemptLoadRTL(const std::string &RTLName, RTLInfoTy &RTL); -}; /// Map between the host entry begin and the translation table. Each /// registered library gets one TranslationTable. Use the map from diff --git a/openmp/libomptarget/src/CMakeLists.txt b/openmp/libomptarget/src/CMakeLists.txt index 8daa448a57e9..ca40ace45645 100644 --- a/openmp/libomptarget/src/CMakeLists.txt +++ b/openmp/libomptarget/src/CMakeLists.txt @@ -21,6 +21,7 @@ add_llvm_library(omptarget omptarget.cpp rtl.cpp LegacyAPI.cpp + PluginManager.cpp OpenMP/Mapping.cpp OpenMP/InteropAPI.cpp diff --git a/openmp/libomptarget/src/OpenMP/InteropAPI.cpp b/openmp/libomptarget/src/OpenMP/InteropAPI.cpp index ace0fecd0a43..6a40dbca87af 100644 --- a/openmp/libomptarget/src/OpenMP/InteropAPI.cpp +++ b/openmp/libomptarget/src/OpenMP/InteropAPI.cpp @@ -10,6 +10,7 @@ #include "OpenMP/InternalTypes.h" #include "OpenMP/omp.h" +#include "PluginManager.h" #include "device.h" #include "omptarget.h" diff --git a/openmp/libomptarget/src/PluginManager.cpp b/openmp/libomptarget/src/PluginManager.cpp new file mode 100644 index 000000000000..260aecd47659 --- /dev/null +++ b/openmp/libomptarget/src/PluginManager.cpp @@ -0,0 +1,15 @@ +//===-- PluginManager.cpp - Plugin loading and communication API ---------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Functionality for handling plugins. +// +//===----------------------------------------------------------------------===// + +#include "PluginManager.h" + +PluginManager *PM; diff --git a/openmp/libomptarget/src/api.cpp b/openmp/libomptarget/src/api.cpp index 42379f42d43b..e44421428ada 100644 --- a/openmp/libomptarget/src/api.cpp +++ b/openmp/libomptarget/src/api.cpp @@ -10,6 +10,7 @@ // //===----------------------------------------------------------------------===// +#include "PluginManager.h" #include "device.h" #include "omptarget.h" #include "private.h" diff --git a/openmp/libomptarget/src/device.cpp b/openmp/libomptarget/src/device.cpp index 742ab156da31..8e292eb7b4fd 100644 --- a/openmp/libomptarget/src/device.cpp +++ b/openmp/libomptarget/src/device.cpp @@ -13,6 +13,7 @@ #include "device.h" #include "OpenMP/OMPT/Callback.h" #include "OpenMP/OMPT/Interface.h" +#include "PluginManager.h" #include "omptarget.h" #include "private.h" #include "rtl.h" @@ -58,7 +59,7 @@ int HostDataToTargetTy::addEventIfNecessary(DeviceTy &Device, return OFFLOAD_SUCCESS; } -DeviceTy::DeviceTy(RTLInfoTy *RTL) +DeviceTy::DeviceTy(PluginAdaptorTy *RTL) : DeviceID(-1), RTL(RTL), RTLDeviceID(-1), IsInit(false), InitFlag(), HasPendingGlobals(false), PendingCtorsDtors(), PendingGlobalsMtx() {} diff --git a/openmp/libomptarget/src/interface.cpp b/openmp/libomptarget/src/interface.cpp index 3dda2e28e7cb..97cada94527f 100644 --- a/openmp/libomptarget/src/interface.cpp +++ b/openmp/libomptarget/src/interface.cpp @@ -13,6 +13,7 @@ #include "OpenMP/OMPT/Interface.h" #include "OpenMP/OMPT/Callback.h" +#include "PluginManager.h" #include "device.h" #include "omptarget.h" #include "private.h" diff --git a/openmp/libomptarget/src/omptarget.cpp b/openmp/libomptarget/src/omptarget.cpp index f549afe24f1a..5b43c7e67eaf 100644 --- a/openmp/libomptarget/src/omptarget.cpp +++ b/openmp/libomptarget/src/omptarget.cpp @@ -14,6 +14,7 @@ #include "omptarget.h" #include "OpenMP/OMPT/Callback.h" #include "OpenMP/OMPT/Interface.h" +#include "PluginManager.h" #include "device.h" #include "private.h" #include "rtl.h" diff --git a/openmp/libomptarget/src/rtl.cpp b/openmp/libomptarget/src/rtl.cpp index 2a89eebcc0ad..6248acff686d 100644 --- a/openmp/libomptarget/src/rtl.cpp +++ b/openmp/libomptarget/src/rtl.cpp @@ -13,6 +13,7 @@ #include "llvm/Object/OffloadBinary.h" #include "OpenMP/OMPT/Callback.h" +#include "PluginManager.h" #include "device.h" #include "private.h" #include "rtl.h" @@ -39,8 +40,6 @@ static const char *RTLNames[] = { /* AMDGPU target */ "libomptarget.rtl.amdgpu", }; -PluginManager *PM; - static char *ProfileTraceFile = nullptr; #ifdef OMPT_SUPPORT @@ -91,7 +90,7 @@ __attribute__((destructor(101))) void deinit() { } } -void RTLsTy::loadRTLs() { +void PluginAdaptorManagerTy::loadRTLs() { // Parse environment variable OMP_TARGET_OFFLOAD (if set) PM->TargetOffloadPolicy = (kmp_target_offload_kind_t)__kmpc_get_target_offload(); @@ -106,7 +105,7 @@ void RTLsTy::loadRTLs() { for (const char *Name : RTLNames) { AllRTLs.emplace_back(); - RTLInfoTy &RTL = AllRTLs.back(); + PluginAdaptorTy &RTL = AllRTLs.back(); const std::string BaseRTLName(Name); if (!attemptLoadRTL(BaseRTLName + ".so", RTL)) @@ -116,7 +115,7 @@ void RTLsTy::loadRTLs() { DP("RTLs loaded!\n"); } -bool RTLsTy::attemptLoadRTL(const std::string &RTLName, RTLInfoTy &RTL) { +bool PluginAdaptorManagerTy::attemptLoadRTL(const std::string &RTLName, PluginAdaptorTy &RTL) { const char *Name = RTLName.c_str(); DP("Loading library '%s'...\n", Name); @@ -259,7 +258,7 @@ bool RTLsTy::attemptLoadRTL(const std::string &RTLName, RTLInfoTy &RTL) { // Functionality for registering libs static void registerImageIntoTranslationTable(TranslationTable &TT, - RTLInfoTy &RTL, + PluginAdaptorTy &RTL, __tgt_device_image *Image) { // same size, as when we increase one, we also increase the other. @@ -290,7 +289,7 @@ static void registerImageIntoTranslationTable(TranslationTable &TT, static void registerGlobalCtorsDtorsForImage(__tgt_bin_desc *Desc, __tgt_device_image *Img, - RTLInfoTy *RTL) { + PluginAdaptorTy *RTL) { for (int32_t I = 0; I < RTL->NumberOfDevices; ++I) { DeviceTy &Device = *PM->Devices[RTL->Idx + I]; @@ -361,7 +360,7 @@ static __tgt_image_info getImageInfo(__tgt_device_image *Image) { return __tgt_image_info{(*BinaryOrErr)->getArch().data()}; } -void RTLsTy::registerRequires(int64_t Flags) { +void PluginAdaptorManagerTy::registerRequires(int64_t Flags) { // TODO: add more elaborate check. // Minimal check: only set requires flags if previous value // is undefined. This ensures that only the first call to this @@ -402,7 +401,7 @@ void RTLsTy::registerRequires(int64_t Flags) { Flags, RequiresFlags); } -void RTLsTy::initRTLonce(RTLInfoTy &R) { +void PluginAdaptorManagerTy::initRTLonce(PluginAdaptorTy &R) { // If this RTL is not already in use, initialize it. if (R.IsUsed || !R.NumberOfDevices) return; @@ -430,12 +429,12 @@ void RTLsTy::initRTLonce(RTLInfoTy &R) { DP("RTL " DPxMOD " has index %d!\n", DPxPTR(R.LibraryHandler.get()), R.Idx); } -void RTLsTy::initAllRTLs() { +void PluginAdaptorManagerTy::initAllRTLs() { for (auto &R : AllRTLs) initRTLonce(R); } -void RTLsTy::registerLib(__tgt_bin_desc *Desc) { +void PluginAdaptorManagerTy::registerLib(__tgt_bin_desc *Desc) { PM->RTLsMtx.lock(); // Extract the exectuable image and extra information if availible. @@ -449,7 +448,7 @@ void RTLsTy::registerLib(__tgt_bin_desc *Desc) { __tgt_device_image *Img = &ImageAndInfo.first; __tgt_image_info *Info = &ImageAndInfo.second; - RTLInfoTy *FoundRTL = nullptr; + PluginAdaptorTy *FoundRTL = nullptr; // Scan the RTLs that have associated images until we find one that supports // the current image. @@ -509,7 +508,7 @@ void RTLsTy::registerLib(__tgt_bin_desc *Desc) { DP("Done registering entries!\n"); } -void RTLsTy::unregisterLib(__tgt_bin_desc *Desc) { +void PluginAdaptorManagerTy::unregisterLib(__tgt_bin_desc *Desc) { DP("Unloading target library!\n"); PM->RTLsMtx.lock(); @@ -518,7 +517,7 @@ void RTLsTy::unregisterLib(__tgt_bin_desc *Desc) { // Obtain the image and information that was previously extracted. __tgt_device_image *Img = &ImageAndInfo.first; - RTLInfoTy *FoundRTL = NULL; + PluginAdaptorTy *FoundRTL = NULL; // Scan the RTLs that have associated images until we find one that supports // the current image. We only need to scan RTLs that are already being used. -- GitLab From 0ec4b82cfddbe0c7c7eb4b3486f55139f56d5f16 Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Thu, 30 Nov 2023 15:48:39 -0600 Subject: [PATCH 051/699] [Libomptarget] Output the DeviceRTL alongside the other libraries (#73705) Summary: Currently, the `libomp.so` and `libomptarget.so` are emitted in the `./lib` build directory generally. This logic is internal to the `add_llvm_library` function we use to build `libomptarget`. The DeviceRTl static library however is in the middle of the OpenMP runtime build, which can vary depending on if this is a runtimes or projects build. This patch changes this to install the DeviceRTL static library alongside the other OpenMP libraries so they are easier to find. --- openmp/libomptarget/CMakeLists.txt | 8 ++++++++ openmp/libomptarget/DeviceRTL/CMakeLists.txt | 5 ++++- openmp/libomptarget/test/lit.cfg | 4 ++-- openmp/libomptarget/test/lit.site.cfg.in | 1 + 4 files changed, 15 insertions(+), 3 deletions(-) diff --git a/openmp/libomptarget/CMakeLists.txt b/openmp/libomptarget/CMakeLists.txt index 5f592f46c8ff..972b887c7c95 100644 --- a/openmp/libomptarget/CMakeLists.txt +++ b/openmp/libomptarget/CMakeLists.txt @@ -24,6 +24,12 @@ set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${LIBOMPTARGET_LIBRARY_DIR}) set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${LIBOMPTARGET_LIBRARY_DIR}) set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${LIBOMPTARGET_LIBRARY_DIR}) +if(LLVM_LIBRARY_OUTPUT_INTDIR) + set(LIBOMPTARGET_INTDIR ${LIBOMPTARGET_LIBRARY_DIR}) +else() + set(LIBOMPTARGET_INTDIR ${LLVM_LIBRARY_OUTPUT_INTDIR}) +endif() + # Message utilities. include(LibomptargetUtils) @@ -115,6 +121,8 @@ set(LIBOMPTARGET_OPENMP_HOST_RTL_FOLDER "${LIBOMP_LIBRARY_DIR}" CACHE STRING "Path to folder containing libomp.so, and libLLVMSupport.so with profiling enabled") set(LIBOMPTARGET_LLVM_LIBRARY_DIR "${LLVM_LIBRARY_DIR}" CACHE STRING "Path to folder containing llvm library libomptarget.so") +set(LIBOMPTARGET_LLVM_LIBRARY_INTDIR "${LIBOMPTARGET_INTDIR}" CACHE STRING + "Path to folder where intermediate libraries will be output") # Build offloading plugins and device RTLs if they are available. add_subdirectory(plugins-nextgen) diff --git a/openmp/libomptarget/DeviceRTL/CMakeLists.txt b/openmp/libomptarget/DeviceRTL/CMakeLists.txt index df8e4a5126fd..104b65020daf 100644 --- a/openmp/libomptarget/DeviceRTL/CMakeLists.txt +++ b/openmp/libomptarget/DeviceRTL/CMakeLists.txt @@ -301,7 +301,10 @@ endforeach() # Archive all the object files generated above into a static library add_library(omptarget.devicertl STATIC) -set_target_properties(omptarget.devicertl PROPERTIES LINKER_LANGUAGE CXX) +set_target_properties(omptarget.devicertl PROPERTIES + ARCHIVE_OUTPUT_DIRECTORY ${LIBOMPTARGET_LLVM_LIBRARY_INTDIR} + LINKER_LANGUAGE CXX +) target_link_libraries(omptarget.devicertl PRIVATE omptarget.devicertl.all_objs) install(TARGETS omptarget.devicertl ARCHIVE DESTINATION ${OPENMP_INSTALL_LIBDIR}) diff --git a/openmp/libomptarget/test/lit.cfg b/openmp/libomptarget/test/lit.cfg index 6dab31bd35a9..adbdd7cc35cc 100644 --- a/openmp/libomptarget/test/lit.cfg +++ b/openmp/libomptarget/test/lit.cfg @@ -156,8 +156,8 @@ def remove_suffix_if_present(name): def add_libraries(source): if config.libomptarget_has_libc: return source + " " + config.llvm_library_dir + "/libcgpu.a " + \ - config.library_dir + "/libomptarget.devicertl.a" - return source + " " + config.library_dir + "/libomptarget.devicertl.a" + config.llvm_library_intdir + "/libomptarget.devicertl.a" + return source + " " + config.llvm_library_intdir + "/libomptarget.devicertl.a" # substitutions # - for targets that exist in the system create the actual command. diff --git a/openmp/libomptarget/test/lit.site.cfg.in b/openmp/libomptarget/test/lit.site.cfg.in index 2c6b90ad4601..2d6381188387 100644 --- a/openmp/libomptarget/test/lit.site.cfg.in +++ b/openmp/libomptarget/test/lit.site.cfg.in @@ -13,6 +13,7 @@ config.cuda_test_arch = "@LIBOMPTARGET_DEP_CUDA_ARCH@" config.libomptarget_obj_root = "@CMAKE_CURRENT_BINARY_DIR@/@CURRENT_TARGET@" config.library_dir = "@LIBOMPTARGET_LIBRARY_DIR@" config.llvm_library_dir = "@LIBOMPTARGET_LLVM_LIBRARY_DIR@" +config.llvm_library_intdir = "@LIBOMPTARGET_LLVM_LIBRARY_INTDIR@" config.omp_header_directory = "@LIBOMPTARGET_OPENMP_HEADER_FOLDER@" config.omp_host_rtl_directory = "@LIBOMPTARGET_OPENMP_HOST_RTL_FOLDER@" config.llvm_lib_directory = "@LIBOMPTARGET_LLVM_LIBRARY_DIR@" -- GitLab From 4e2216e184a2ba4b9e7e40b3cfa11e0c516a6ed6 Mon Sep 17 00:00:00 2001 From: "Stephan T. Lavavej" Date: Thu, 30 Nov 2023 13:54:52 -0800 Subject: [PATCH 052/699] [libc++][test] `ADDITIONAL_COMPILE_FLAGS` should be a space-separated list (#73541) Found while running libc++'s test suite with MSVC's STL. `ADDITIONAL_COMPILE_FLAGS` is a `ParserKind.LIST`: https://github.com/llvm/llvm-project/blob/3c23ed156f0151923b168bdff0c34ec73fb37f38/libcxx/utils/libcxx/test/format.py#L104-L108 With a comma-separated example: https://github.com/llvm/llvm-project/blob/3c23ed156f0151923b168bdff0c34ec73fb37f38/libcxx/utils/libcxx/test/format.py#L223-L228 And comma-separated test coverage: https://github.com/llvm/llvm-project/blob/dd3184c30ff531b8aecea280e65233337dd02815/libcxx/test/libcxx/selftest/additional_compile_flags/substitutes-in-run.sh.cpp#L12-L15 Because the machinery splits on commas: https://github.com/llvm/llvm-project/blob/dd09221a29506031415cad8a1308998358633d48/llvm/utils/lit/lit/TestRunner.py#L1882-L1883 https://github.com/llvm/llvm-project/blob/dd09221a29506031415cad8a1308998358633d48/llvm/utils/lit/lit/TestRunner.py#L1951-L1956 However, most (although not all) usage of `ADDITIONAL_COMPILE_FLAGS` is treating it as space-separated. That apparently works in the normal Clang environment, but in my exotic configuration it causes `"-DMEOW -DWOOF"` to be passed as a single argument to MSVC, which then emits "warning C5102: ignoring invalid command-line macro definition `'_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT'`", causing test failures due to warnings-as-errors. This PR changes `ADDITIONAL_COMPILE_FLAGS` to actually be parsed as a space-separated list, and changes the few uses/examples that had commas. --- .../substitutes-in-compile-flags.sh.cpp | 2 +- .../substitutes-in-run.sh.cpp | 2 +- .../sized_delete_fsizeddeallocation.pass.cpp | 2 +- libcxx/utils/libcxx/test/format.py | 6 ++-- llvm/utils/lit/lit/TestRunner.py | 26 +++++++++++++---- .../Inputs/testrunner-custom-parsers/test.txt | 6 ++++ llvm/utils/lit/tests/unit/TestRunner.py | 29 +++++++++++++++++++ 7 files changed, 61 insertions(+), 12 deletions(-) diff --git a/libcxx/test/libcxx/selftest/additional_compile_flags/substitutes-in-compile-flags.sh.cpp b/libcxx/test/libcxx/selftest/additional_compile_flags/substitutes-in-compile-flags.sh.cpp index 499d8da97cea..561d77c56947 100644 --- a/libcxx/test/libcxx/selftest/additional_compile_flags/substitutes-in-compile-flags.sh.cpp +++ b/libcxx/test/libcxx/selftest/additional_compile_flags/substitutes-in-compile-flags.sh.cpp @@ -13,6 +13,6 @@ // Make sure that substitutions are performed inside additional compiler flags. // ADDITIONAL_COMPILE_FLAGS: -I %t.1 -// ADDITIONAL_COMPILE_FLAGS: -isystem %t.2 , -isysroot %t.3 +// ADDITIONAL_COMPILE_FLAGS: -isystem %t.2 -isysroot %t.3 // RUN: echo "-I %t.1 -isystem %t.2 -isysroot %t.3" | sed "s/\\\/\\\\\\\/g" > %t.escaped.grep // RUN: echo "%{compile_flags}" | grep -e -f %t.escaped.grep diff --git a/libcxx/test/libcxx/selftest/additional_compile_flags/substitutes-in-run.sh.cpp b/libcxx/test/libcxx/selftest/additional_compile_flags/substitutes-in-run.sh.cpp index 387b1a1c3440..c8ddddcef0a7 100644 --- a/libcxx/test/libcxx/selftest/additional_compile_flags/substitutes-in-run.sh.cpp +++ b/libcxx/test/libcxx/selftest/additional_compile_flags/substitutes-in-run.sh.cpp @@ -11,5 +11,5 @@ // ADDITIONAL_COMPILE_FLAGS: -foo // ADDITIONAL_COMPILE_FLAGS: -bar -// ADDITIONAL_COMPILE_FLAGS: -baz, -foom +// ADDITIONAL_COMPILE_FLAGS: -baz -foom // RUN: echo "%{compile_flags}" | grep -e '-foo -bar -baz -foom' diff --git a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete_fsizeddeallocation.pass.cpp b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete_fsizeddeallocation.pass.cpp index d9907779466f..df8b96447262 100644 --- a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete_fsizeddeallocation.pass.cpp +++ b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete_fsizeddeallocation.pass.cpp @@ -15,7 +15,7 @@ // XFAIL: stdlib=apple-libc++ && target={{.+}}-apple-macosx10.{{9|10|11}} // REQUIRES: -fsized-deallocation -// ADDITIONAL_COMPILE_FLAGS: -fsized-deallocation, -O3 +// ADDITIONAL_COMPILE_FLAGS: -fsized-deallocation -O3 #if !defined(__cpp_sized_deallocation) # error __cpp_sized_deallocation should be defined diff --git a/libcxx/utils/libcxx/test/format.py b/libcxx/utils/libcxx/test/format.py index 5eb17d417489..e58e404bfcd2 100644 --- a/libcxx/utils/libcxx/test/format.py +++ b/libcxx/utils/libcxx/test/format.py @@ -99,7 +99,7 @@ def parseScript(test, preamble): ), lit.TestRunner.IntegratedTestKeywordParser( "ADDITIONAL_COMPILE_FLAGS:", - lit.TestRunner.ParserKind.LIST, + lit.TestRunner.ParserKind.SPACE_LIST, initial_value=additionalCompileFlags, ), ] @@ -110,7 +110,7 @@ def parseScript(test, preamble): for feature in test.config.available_features: parser = lit.TestRunner.IntegratedTestKeywordParser( "ADDITIONAL_COMPILE_FLAGS({}):".format(feature), - lit.TestRunner.ParserKind.LIST, + lit.TestRunner.ParserKind.SPACE_LIST, initial_value=additionalCompileFlags, ) parsers.append(parser) @@ -216,7 +216,7 @@ class CxxStandardLibraryTest(lit.formats.FileBasedTest): all the inputs necessary to run the test, such that e.g. execution on a remote host can be done by simply copying %T to the host. - // ADDITIONAL_COMPILE_FLAGS: flag1, flag2, flag3 + // ADDITIONAL_COMPILE_FLAGS: flag1 flag2 flag3 This directive will cause the provided flags to be added to the %{compile_flags} substitution for the test that contains it. This diff --git a/llvm/utils/lit/lit/TestRunner.py b/llvm/utils/lit/lit/TestRunner.py index 788152846efe..da7fa86fd391 100644 --- a/llvm/utils/lit/lit/TestRunner.py +++ b/llvm/utils/lit/lit/TestRunner.py @@ -1352,7 +1352,7 @@ def getDefaultSubstitutions(test, tmpDir, tmpBase, normalize_slashes=False): substitutions.append(("%{pathsep}", os.pathsep)) substitutions.append(("%basename_t", baseName)) - + substitutions.extend( [ ("%{fs-src-root}", pathlib.Path(sourcedir).anchor), @@ -1795,6 +1795,7 @@ class ParserKind(object): TAG: A keyword taking no value. Ex 'END.' COMMAND: A keyword taking a list of shell commands. Ex 'RUN:' LIST: A keyword taking a comma-separated list of values. + SPACE_LIST: A keyword taking a space-separated list of values. BOOLEAN_EXPR: A keyword taking a comma-separated list of boolean expressions. Ex 'XFAIL:' INTEGER: A keyword taking a single integer. Ex 'ALLOW_RETRIES:' @@ -1808,11 +1809,12 @@ class ParserKind(object): TAG = 0 COMMAND = 1 LIST = 2 - BOOLEAN_EXPR = 3 - INTEGER = 4 - CUSTOM = 5 - DEFINE = 6 - REDEFINE = 7 + SPACE_LIST = 3 + BOOLEAN_EXPR = 4 + INTEGER = 5 + CUSTOM = 6 + DEFINE = 7 + REDEFINE = 8 @staticmethod def allowedKeywordSuffixes(value): @@ -1820,6 +1822,7 @@ class ParserKind(object): ParserKind.TAG: ["."], ParserKind.COMMAND: [":"], ParserKind.LIST: [":"], + ParserKind.SPACE_LIST: [":"], ParserKind.BOOLEAN_EXPR: [":"], ParserKind.INTEGER: [":"], ParserKind.CUSTOM: [":", "."], @@ -1833,6 +1836,7 @@ class ParserKind(object): ParserKind.TAG: "TAG", ParserKind.COMMAND: "COMMAND", ParserKind.LIST: "LIST", + ParserKind.SPACE_LIST: "SPACE_LIST", ParserKind.BOOLEAN_EXPR: "BOOLEAN_EXPR", ParserKind.INTEGER: "INTEGER", ParserKind.CUSTOM: "CUSTOM", @@ -1881,6 +1885,8 @@ class IntegratedTestKeywordParser(object): ) elif kind == ParserKind.LIST: self.parser = self._handleList + elif kind == ParserKind.SPACE_LIST: + self.parser = self._handleSpaceList elif kind == ParserKind.BOOLEAN_EXPR: self.parser = self._handleBooleanExpr elif kind == ParserKind.INTEGER: @@ -1955,6 +1961,14 @@ class IntegratedTestKeywordParser(object): output.extend([s.strip() for s in line.split(",")]) return output + @staticmethod + def _handleSpaceList(line_number, line, output): + """A parser for SPACE_LIST type keywords""" + if output is None: + output = [] + output.extend([s.strip() for s in line.split(" ") if s.strip() != ""]) + return output + @staticmethod def _handleSingleInteger(line_number, line, output): """A parser for INTEGER type keywords""" diff --git a/llvm/utils/lit/tests/Inputs/testrunner-custom-parsers/test.txt b/llvm/utils/lit/tests/Inputs/testrunner-custom-parsers/test.txt index 31e835d9bd4d..a0410adb5552 100644 --- a/llvm/utils/lit/tests/Inputs/testrunner-custom-parsers/test.txt +++ b/llvm/utils/lit/tests/Inputs/testrunner-custom-parsers/test.txt @@ -4,6 +4,11 @@ // MY_RUN: baz // MY_LIST: one, two // MY_LIST: three, four +// MY_SPACE_LIST: orange +// MY_SPACE_LIST: tabby tortie tuxedo +// MY_SPACE_LIST: void +// MY_SPACE_LIST: multiple spaces +// MY_SPACE_LIST: cute, fluffy, kittens // MY_RUN: foo \ // MY_RUN: bar // @@ -25,3 +30,4 @@ // // END. // MY_LIST: five +// MY_SPACE_LIST: zebra diff --git a/llvm/utils/lit/tests/unit/TestRunner.py b/llvm/utils/lit/tests/unit/TestRunner.py index e9888d685d38..f1baf51c02f3 100644 --- a/llvm/utils/lit/tests/unit/TestRunner.py +++ b/llvm/utils/lit/tests/unit/TestRunner.py @@ -61,6 +61,7 @@ class TestIntegratedTestKeywordParser(unittest.TestCase): IntegratedTestKeywordParser("MY_TAG.", ParserKind.TAG), IntegratedTestKeywordParser("MY_DNE_TAG.", ParserKind.TAG), IntegratedTestKeywordParser("MY_LIST:", ParserKind.LIST), + IntegratedTestKeywordParser("MY_SPACE_LIST:", ParserKind.SPACE_LIST), IntegratedTestKeywordParser("MY_BOOL:", ParserKind.BOOLEAN_EXPR), IntegratedTestKeywordParser("MY_INT:", ParserKind.INTEGER), IntegratedTestKeywordParser("MY_RUN:", ParserKind.COMMAND), @@ -104,6 +105,26 @@ class TestIntegratedTestKeywordParser(unittest.TestCase): list_parser = self.get_parser(parsers, "MY_LIST:") self.assertEqual(list_parser.getValue(), ["one", "two", "three", "four"]) + def test_space_lists(self): + parsers = self.make_parsers() + self.parse_test(parsers) + space_list_parser = self.get_parser(parsers, "MY_SPACE_LIST:") + self.assertEqual( + space_list_parser.getValue(), + [ + "orange", + "tabby", + "tortie", + "tuxedo", + "void", + "multiple", + "spaces", + "cute,", + "fluffy,", + "kittens", + ], + ) + def test_commands(self): parsers = self.make_parsers() self.parse_test(parsers) @@ -222,6 +243,14 @@ class TestIntegratedTestKeywordParser(unittest.TestCase): except BaseException as e: self.fail("LIST_WITH_DOT. raised the wrong exception: %r" % e) + try: + IntegratedTestKeywordParser("SPACE_LIST_WITH_DOT.", ParserKind.SPACE_LIST), + self.fail("SPACE_LIST_WITH_DOT. failed to raise an exception") + except ValueError as e: + pass + except BaseException as e: + self.fail("SPACE_LIST_WITH_DOT. raised the wrong exception: %r" % e) + try: IntegratedTestKeywordParser( "CUSTOM_NO_SUFFIX", ParserKind.CUSTOM, custom_parse -- GitLab From b80b5f180ba64c2d6d9753ce8b310f1759eb2884 Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Thu, 30 Nov 2023 14:16:34 -0800 Subject: [PATCH 053/699] [OpenMP] Replace copy and paste code with instantiation (#73991) --- openmp/libomptarget/include/PluginManager.h | 87 ++------------ openmp/libomptarget/include/Shared/APITypes.h | 26 ++++ .../libomptarget/include/Shared/PluginAPI.h | 10 ++ .../libomptarget/include/Shared/PluginAPI.inc | 50 ++++++++ openmp/libomptarget/include/device.h | 4 +- openmp/libomptarget/include/omptarget.h | 23 ---- openmp/libomptarget/src/device.cpp | 9 +- openmp/libomptarget/src/omptarget.cpp | 6 +- openmp/libomptarget/src/rtl.cpp | 112 +++--------------- 9 files changed, 116 insertions(+), 211 deletions(-) create mode 100644 openmp/libomptarget/include/Shared/PluginAPI.inc diff --git a/openmp/libomptarget/include/PluginManager.h b/openmp/libomptarget/include/PluginManager.h index 6a91e245453c..3a1c97fc52c9 100644 --- a/openmp/libomptarget/include/PluginManager.h +++ b/openmp/libomptarget/include/PluginManager.h @@ -14,6 +14,7 @@ #define OMPTARGET_PLUGIN_MANAGER_H #include "Shared/APITypes.h" +#include "Shared/PluginAPI.h" #include "device.h" @@ -25,49 +26,6 @@ #include struct PluginAdaptorTy { - typedef int32_t(init_plugin_ty)(); - typedef int32_t(is_valid_binary_ty)(void *); - typedef int32_t(is_valid_binary_info_ty)(void *, void *); - typedef int32_t(is_data_exchangable_ty)(int32_t, int32_t); - typedef int32_t(number_of_devices_ty)(); - typedef int32_t(init_device_ty)(int32_t); - typedef __tgt_target_table *(load_binary_ty)(int32_t, void *); - typedef void *(data_alloc_ty)(int32_t, int64_t, void *, int32_t); - typedef int32_t(data_submit_ty)(int32_t, void *, void *, int64_t); - typedef int32_t(data_submit_async_ty)(int32_t, void *, void *, int64_t, - __tgt_async_info *); - typedef int32_t(data_retrieve_ty)(int32_t, void *, void *, int64_t); - typedef int32_t(data_retrieve_async_ty)(int32_t, void *, void *, int64_t, - __tgt_async_info *); - typedef int32_t(data_exchange_ty)(int32_t, void *, int32_t, void *, int64_t); - typedef int32_t(data_exchange_async_ty)(int32_t, void *, int32_t, void *, - int64_t, __tgt_async_info *); - typedef int32_t(data_delete_ty)(int32_t, void *, int32_t); - typedef int32_t(launch_kernel_ty)(int32_t, void *, void **, ptrdiff_t *, - const KernelArgsTy *, __tgt_async_info *); - typedef int64_t(init_requires_ty)(int64_t); - typedef int32_t(synchronize_ty)(int32_t, __tgt_async_info *); - typedef int32_t(query_async_ty)(int32_t, __tgt_async_info *); - typedef int32_t(supports_empty_images_ty)(); - typedef void(print_device_info_ty)(int32_t); - typedef void(set_info_flag_ty)(uint32_t); - typedef int32_t(create_event_ty)(int32_t, void **); - typedef int32_t(record_event_ty)(int32_t, void *, __tgt_async_info *); - typedef int32_t(wait_event_ty)(int32_t, void *, __tgt_async_info *); - typedef int32_t(sync_event_ty)(int32_t, void *); - typedef int32_t(destroy_event_ty)(int32_t, void *); - typedef int32_t(release_async_info_ty)(int32_t, __tgt_async_info *); - typedef int32_t(init_async_info_ty)(int32_t, __tgt_async_info **); - typedef int64_t(init_device_into_ty)(int64_t, __tgt_device_info *, - const char **); - typedef int32_t(data_lock_ty)(int32_t, void *, int64_t, void **); - typedef int32_t(data_unlock_ty)(int32_t, void *); - typedef int32_t(data_notify_mapped_ty)(int32_t, void *, int64_t); - typedef int32_t(data_notify_unmapped_ty)(int32_t, void *); - typedef int32_t(set_device_offset_ty)(int32_t); - typedef int32_t(activate_record_replay_ty)(int32_t, uint64_t, void *, bool, - bool, uint64_t &); - int32_t Idx = -1; // RTL index, index is the number of devices // of other RTLs that were registered before, // i.e. the OpenMP index of the first device @@ -80,43 +38,12 @@ struct PluginAdaptorTy { std::string RTLName; #endif - // Functions implemented in the RTL. - init_plugin_ty *init_plugin = nullptr; - is_valid_binary_ty *is_valid_binary = nullptr; - is_valid_binary_info_ty *is_valid_binary_info = nullptr; - is_data_exchangable_ty *is_data_exchangable = nullptr; - number_of_devices_ty *number_of_devices = nullptr; - init_device_ty *init_device = nullptr; - load_binary_ty *load_binary = nullptr; - data_alloc_ty *data_alloc = nullptr; - data_submit_ty *data_submit = nullptr; - data_submit_async_ty *data_submit_async = nullptr; - data_retrieve_ty *data_retrieve = nullptr; - data_retrieve_async_ty *data_retrieve_async = nullptr; - data_exchange_ty *data_exchange = nullptr; - data_exchange_async_ty *data_exchange_async = nullptr; - data_delete_ty *data_delete = nullptr; - launch_kernel_ty *launch_kernel = nullptr; - init_requires_ty *init_requires = nullptr; - synchronize_ty *synchronize = nullptr; - query_async_ty *query_async = nullptr; - supports_empty_images_ty *supports_empty_images = nullptr; - set_info_flag_ty *set_info_flag = nullptr; - print_device_info_ty *print_device_info = nullptr; - create_event_ty *create_event = nullptr; - record_event_ty *record_event = nullptr; - wait_event_ty *wait_event = nullptr; - sync_event_ty *sync_event = nullptr; - destroy_event_ty *destroy_event = nullptr; - init_async_info_ty *init_async_info = nullptr; - init_device_into_ty *init_device_info = nullptr; - release_async_info_ty *release_async_info = nullptr; - data_lock_ty *data_lock = nullptr; - data_unlock_ty *data_unlock = nullptr; - data_notify_mapped_ty *data_notify_mapped = nullptr; - data_notify_unmapped_ty *data_notify_unmapped = nullptr; - set_device_offset_ty *set_device_offset = nullptr; - activate_record_replay_ty *activate_record_replay = nullptr; +#define PLUGIN_API_HANDLE(NAME, MANDATORY) \ + using NAME##_ty = decltype(__tgt_rtl_##NAME); \ + NAME##_ty *NAME = nullptr; + +#include "Shared/PluginAPI.inc" +#undef PLUGIN_API_HANDLE // Are there images associated with this RTL. bool IsUsed = false; diff --git a/openmp/libomptarget/include/Shared/APITypes.h b/openmp/libomptarget/include/Shared/APITypes.h index fc494cd5f586..8e2aee2deb29 100644 --- a/openmp/libomptarget/include/Shared/APITypes.h +++ b/openmp/libomptarget/include/Shared/APITypes.h @@ -86,6 +86,32 @@ struct __tgt_async_info { /// happening. KernelLaunchEnvironmentTy KernelLaunchEnvironment; }; + +/// This struct contains all of the arguments to a target kernel region launch. +struct KernelArgsTy { + uint32_t Version; // Version of this struct for ABI compatibility. + uint32_t NumArgs; // Number of arguments in each input pointer. + void **ArgBasePtrs; // Base pointer of each argument (e.g. a struct). + void **ArgPtrs; // Pointer to the argument data. + int64_t *ArgSizes; // Size of the argument data in bytes. + int64_t *ArgTypes; // Type of the data (e.g. to / from). + void **ArgNames; // Name of the data for debugging, possibly null. + void **ArgMappers; // User-defined mappers, possibly null. + uint64_t Tripcount; // Tripcount for the teams / distribute loop, 0 otherwise. + struct { + uint64_t NoWait : 1; // Was this kernel spawned with a `nowait` clause. + uint64_t Unused : 63; + } Flags; + uint32_t NumTeams[3]; // The number of teams (for x,y,z dimension). + uint32_t ThreadLimit[3]; // The number of threads (for x,y,z dimension). + uint32_t DynCGroupMem; // Amount of dynamic cgroup memory requested. +}; +static_assert(sizeof(KernelArgsTy().Flags) == sizeof(uint64_t), + "Invalid struct size"); +static_assert(sizeof(KernelArgsTy) == + (8 * sizeof(int32_t) + 3 * sizeof(int64_t) + + 4 * sizeof(void **) + 2 * sizeof(int64_t *)), + "Invalid struct size"); } #endif // OMPTARGET_SHARED_API_TYPES_H diff --git a/openmp/libomptarget/include/Shared/PluginAPI.h b/openmp/libomptarget/include/Shared/PluginAPI.h index 94beab2dcea1..41d1908da215 100644 --- a/openmp/libomptarget/include/Shared/PluginAPI.h +++ b/openmp/libomptarget/include/Shared/PluginAPI.h @@ -215,6 +215,16 @@ int32_t __tgt_rtl_data_notify_unmapped(int32_t ID, void *HstPtr); // Set the global device identifier offset, such that the plugin may determine a // unique device number. int32_t __tgt_rtl_set_device_offset(int32_t DeviceIdOffset); + +int32_t __tgt_rtl_launch_kernel(int32_t DeviceId, void *TgtEntryPtr, + void **TgtArgs, ptrdiff_t *TgtOffsets, + KernelArgsTy *KernelArgs, + __tgt_async_info *AsyncInfoPtr); + +int32_t __tgt_rtl_initialize_record_replay(int32_t DeviceId, int64_t MemorySize, + void *VAddr, bool isRecord, + bool SaveOutput, + uint64_t &ReqPtrArgOffset); } #endif // OMPTARGET_SHARED_PLUGIN_API_H diff --git a/openmp/libomptarget/include/Shared/PluginAPI.inc b/openmp/libomptarget/include/Shared/PluginAPI.inc new file mode 100644 index 000000000000..0949e4e593dd --- /dev/null +++ b/openmp/libomptarget/include/Shared/PluginAPI.inc @@ -0,0 +1,50 @@ +//===-- Shared/PluginAPI.inc - Target independent plugin API ----*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines the names of the interface functions between target +// independent offload runtime library and target dependent plugins. +// +//===----------------------------------------------------------------------===// + +// No include guards! + +PLUGIN_API_HANDLE(init_plugin, true); +PLUGIN_API_HANDLE(is_valid_binary, true); +PLUGIN_API_HANDLE(is_valid_binary_info, false); +PLUGIN_API_HANDLE(is_data_exchangable, false); +PLUGIN_API_HANDLE(number_of_devices, true); +PLUGIN_API_HANDLE(init_device, true); +PLUGIN_API_HANDLE(load_binary, true); +PLUGIN_API_HANDLE(data_alloc, true); +PLUGIN_API_HANDLE(data_submit, true); +PLUGIN_API_HANDLE(data_submit_async, false); +PLUGIN_API_HANDLE(data_retrieve, true); +PLUGIN_API_HANDLE(data_retrieve_async, false); +PLUGIN_API_HANDLE(data_exchange, false); +PLUGIN_API_HANDLE(data_exchange_async, false); +PLUGIN_API_HANDLE(data_delete, true); +PLUGIN_API_HANDLE(launch_kernel, true); +PLUGIN_API_HANDLE(init_requires, false); +PLUGIN_API_HANDLE(synchronize, false); +PLUGIN_API_HANDLE(query_async, false); +PLUGIN_API_HANDLE(supports_empty_images, false); +PLUGIN_API_HANDLE(set_info_flag, false); +PLUGIN_API_HANDLE(print_device_info, false); +PLUGIN_API_HANDLE(create_event, false); +PLUGIN_API_HANDLE(record_event, false); +PLUGIN_API_HANDLE(wait_event, false); +PLUGIN_API_HANDLE(sync_event, false); +PLUGIN_API_HANDLE(destroy_event, false); +PLUGIN_API_HANDLE(init_async_info, false); +PLUGIN_API_HANDLE(init_device_info, false); +PLUGIN_API_HANDLE(data_lock, false); +PLUGIN_API_HANDLE(data_unlock, false); +PLUGIN_API_HANDLE(data_notify_mapped, false); +PLUGIN_API_HANDLE(data_notify_unmapped, false); +PLUGIN_API_HANDLE(set_device_offset, false); +PLUGIN_API_HANDLE(initialize_record_replay, false); diff --git a/openmp/libomptarget/include/device.h b/openmp/libomptarget/include/device.h index 5e58879bd738..8d253df19215 100644 --- a/openmp/libomptarget/include/device.h +++ b/openmp/libomptarget/include/device.h @@ -150,7 +150,7 @@ struct DeviceTy { // calls to RTL int32_t initOnce(); - __tgt_target_table *loadBinary(void *Img); + __tgt_target_table *loadBinary(__tgt_device_image *Img); // device memory allocation/deallocation routines /// Allocates \p Size bytes on the device, host or shared memory space @@ -192,7 +192,7 @@ struct DeviceTy { // Launch the kernel identified by \p TgtEntryPtr with the given arguments. int32_t launchKernel(void *TgtEntryPtr, void **TgtVarsPtr, - ptrdiff_t *TgtOffsets, const KernelArgsTy &KernelArgs, + ptrdiff_t *TgtOffsets, KernelArgsTy &KernelArgs, AsyncInfoTy &AsyncInfo); /// Synchronize device/queue/event based on \p AsyncInfo and return diff --git a/openmp/libomptarget/include/omptarget.h b/openmp/libomptarget/include/omptarget.h index 45fb40c397af..829e000f4fb3 100644 --- a/openmp/libomptarget/include/omptarget.h +++ b/openmp/libomptarget/include/omptarget.h @@ -121,29 +121,6 @@ enum TargetAllocTy : int32_t { TARGET_ALLOC_DEFAULT }; -/// This struct contains all of the arguments to a target kernel region launch. -struct KernelArgsTy { - uint32_t Version; // Version of this struct for ABI compatibility. - uint32_t NumArgs; // Number of arguments in each input pointer. - void **ArgBasePtrs; // Base pointer of each argument (e.g. a struct). - void **ArgPtrs; // Pointer to the argument data. - int64_t *ArgSizes; // Size of the argument data in bytes. - int64_t *ArgTypes; // Type of the data (e.g. to / from). - void **ArgNames; // Name of the data for debugging, possibly null. - void **ArgMappers; // User-defined mappers, possibly null. - uint64_t Tripcount; // Tripcount for the teams / distribute loop, 0 otherwise. - struct { - uint64_t NoWait : 1; // Was this kernel spawned with a `nowait` clause. - uint64_t Unused : 63; - } Flags; - uint32_t NumTeams[3]; // The number of teams (for x,y,z dimension). - uint32_t ThreadLimit[3]; // The number of threads (for x,y,z dimension). - uint32_t DynCGroupMem; // Amount of dynamic cgroup memory requested. -}; -static_assert(sizeof(KernelArgsTy().Flags) == sizeof(uint64_t), - "Invalid struct size"); -static_assert(sizeof(KernelArgsTy) == (8 * sizeof(int32_t) + 3 * sizeof(int64_t) + 4 * sizeof(void**) + 2 * sizeof(int64_t*)), - "Invalid struct size"); inline KernelArgsTy CTorDTorKernelArgs = {1, 0, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, 0, {0,0}, {1, 0, 0}, {1, 0, 0}, 0}; diff --git a/openmp/libomptarget/src/device.cpp b/openmp/libomptarget/src/device.cpp index 8e292eb7b4fd..2431d7c07335 100644 --- a/openmp/libomptarget/src/device.cpp +++ b/openmp/libomptarget/src/device.cpp @@ -542,8 +542,8 @@ void DeviceTy::init() { "LIBOMPTARGET_RR_SAVE_OUTPUT", false); uint64_t ReqPtrArgOffset; - RTL->activate_record_replay(RTLDeviceID, 0, nullptr, true, - OMPX_ReplaySaveOutput, ReqPtrArgOffset); + RTL->initialize_record_replay(RTLDeviceID, 0, nullptr, true, + OMPX_ReplaySaveOutput, ReqPtrArgOffset); } IsInit = true; @@ -565,7 +565,7 @@ int32_t DeviceTy::initOnce() { } // Load binary to device. -__tgt_target_table *DeviceTy::loadBinary(void *Img) { +__tgt_target_table *DeviceTy::loadBinary(__tgt_device_image *Img) { std::lock_guardMtx)> LG(RTL->Mtx); return RTL->load_binary(RTLDeviceID, Img); } @@ -702,8 +702,7 @@ int32_t DeviceTy::notifyDataUnmapped(void *HstPtr) { // Run region on device int32_t DeviceTy::launchKernel(void *TgtEntryPtr, void **TgtVarsPtr, - ptrdiff_t *TgtOffsets, - const KernelArgsTy &KernelArgs, + ptrdiff_t *TgtOffsets, KernelArgsTy &KernelArgs, AsyncInfoTy &AsyncInfo) { return RTL->launch_kernel(RTLDeviceID, TgtEntryPtr, TgtVarsPtr, TgtOffsets, &KernelArgs, AsyncInfo); diff --git a/openmp/libomptarget/src/omptarget.cpp b/openmp/libomptarget/src/omptarget.cpp index 5b43c7e67eaf..9d75fd360108 100644 --- a/openmp/libomptarget/src/omptarget.cpp +++ b/openmp/libomptarget/src/omptarget.cpp @@ -1733,9 +1733,9 @@ int target(ident_t *Loc, DeviceTy &Device, void *HostPtr, int target_activate_rr(DeviceTy &Device, uint64_t MemorySize, void *VAddr, bool IsRecord, bool SaveOutput, uint64_t &ReqPtrArgOffset) { - return Device.RTL->activate_record_replay(Device.DeviceID, MemorySize, VAddr, - IsRecord, SaveOutput, - ReqPtrArgOffset); + return Device.RTL->initialize_record_replay(Device.DeviceID, MemorySize, + VAddr, IsRecord, SaveOutput, + ReqPtrArgOffset); } /// Executes a kernel using pre-recorded information for loading to diff --git a/openmp/libomptarget/src/rtl.cpp b/openmp/libomptarget/src/rtl.cpp index 6248acff686d..e80d6e09c484 100644 --- a/openmp/libomptarget/src/rtl.cpp +++ b/openmp/libomptarget/src/rtl.cpp @@ -14,6 +14,7 @@ #include "OpenMP/OMPT/Callback.h" #include "PluginManager.h" +#include "Shared/Debug.h" #include "device.h" #include "private.h" #include "rtl.h" @@ -132,50 +133,21 @@ bool PluginAdaptorManagerTy::attemptLoadRTL(const std::string &RTLName, PluginAd DP("Successfully loaded library '%s'!\n", Name); - // Remove plugin on failure to call optional init_plugin - *((void **)&RTL.init_plugin) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_init_plugin"); - if (RTL.init_plugin) { - int32_t Rc = RTL.init_plugin(); - if (Rc != OFFLOAD_SUCCESS) { - DP("Unable to initialize library '%s': %u!\n", Name, Rc); - return false; - } +#define PLUGIN_API_HANDLE(NAME, MANDATORY) \ + *((void **)&RTL.NAME) = \ + DynLibrary->getAddressOfSymbol(GETNAME(__tgt_rtl_##NAME)); \ + if (MANDATORY && !RTL.NAME) { \ + DP("Invalid plugin as necessary interface is not found.\n"); \ + return false; \ } - bool ValidPlugin = true; - - if (!(*((void **)&RTL.is_valid_binary) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_is_valid_binary"))) - ValidPlugin = false; - if (!(*((void **)&RTL.number_of_devices) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_number_of_devices"))) - ValidPlugin = false; - if (!(*((void **)&RTL.init_device) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_init_device"))) - ValidPlugin = false; - if (!(*((void **)&RTL.load_binary) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_load_binary"))) - ValidPlugin = false; - if (!(*((void **)&RTL.data_alloc) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_data_alloc"))) - ValidPlugin = false; - if (!(*((void **)&RTL.data_submit) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_data_submit"))) - ValidPlugin = false; - if (!(*((void **)&RTL.data_retrieve) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_data_retrieve"))) - ValidPlugin = false; - if (!(*((void **)&RTL.data_delete) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_data_delete"))) - ValidPlugin = false; - if (!(*((void **)&RTL.launch_kernel) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_launch_kernel"))) - ValidPlugin = false; - - // Invalid plugin - if (!ValidPlugin) { - DP("Invalid plugin as necessary interface is not found.\n"); +#include "Shared/PluginAPI.inc" +#undef PLUGIN_API_HANDLE + + // Remove plugin on failure to call optional init_plugin + int32_t Rc = RTL.init_plugin(); + if (Rc != OFFLOAD_SUCCESS) { + DP("Unable to initialize library '%s': %u!\n", Name, Rc); return false; } @@ -192,62 +164,6 @@ bool PluginAdaptorManagerTy::attemptLoadRTL(const std::string &RTLName, PluginAd DP("Registering RTL %s supporting %d devices!\n", Name, RTL.NumberOfDevices); - // Optional functions - *((void **)&RTL.is_valid_binary_info) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_is_valid_binary_info"); - *((void **)&RTL.init_requires) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_init_requires"); - *((void **)&RTL.data_submit_async) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_data_submit_async"); - *((void **)&RTL.data_retrieve_async) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_data_retrieve_async"); - *((void **)&RTL.synchronize) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_synchronize"); - *((void **)&RTL.query_async) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_query_async"); - *((void **)&RTL.data_exchange) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_data_exchange"); - *((void **)&RTL.data_exchange_async) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_data_exchange_async"); - *((void **)&RTL.is_data_exchangable) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_is_data_exchangable"); - *((void **)&RTL.supports_empty_images) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_supports_empty_images"); - *((void **)&RTL.set_info_flag) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_set_info_flag"); - *((void **)&RTL.print_device_info) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_print_device_info"); - *((void **)&RTL.create_event) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_create_event"); - *((void **)&RTL.record_event) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_record_event"); - *((void **)&RTL.wait_event) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_wait_event"); - *((void **)&RTL.sync_event) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_sync_event"); - *((void **)&RTL.destroy_event) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_destroy_event"); - *((void **)&RTL.release_async_info) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_release_async_info"); - *((void **)&RTL.init_async_info) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_init_async_info"); - *((void **)&RTL.init_device_info) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_init_device_info"); - *((void **)&RTL.data_lock) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_data_lock"); - *((void **)&RTL.data_unlock) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_data_unlock"); - *((void **)&RTL.data_notify_mapped) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_data_notify_mapped"); - *((void **)&RTL.data_notify_unmapped) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_data_notify_unmapped"); - *((void **)&RTL.set_device_offset) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_set_device_offset"); - - // Record Replay RTL - *((void **)&RTL.activate_record_replay) = - DynLibrary->getAddressOfSymbol("__tgt_rtl_initialize_record_replay"); - RTL.LibraryHandler = std::move(DynLibrary); // Successfully loaded -- GitLab From 6fb7c2d713587a061cd281eda917746750559380 Mon Sep 17 00:00:00 2001 From: Aart Bik <39774503+aartbik@users.noreply.github.com> Date: Thu, 30 Nov 2023 14:19:02 -0800 Subject: [PATCH 054/699] [mlir][sparse] bug fix on all-dense lex insertion (#73987) Fixes a bug that appended values after insertion completed. Also slight optimization by avoiding all-Dense computation for every lexInsert call --- .../ExecutionEngine/SparseTensor/Storage.h | 20 ++++++++----------- .../ExecutionEngine/SparseTensor/Storage.cpp | 14 ++++++++++--- 2 files changed, 19 insertions(+), 15 deletions(-) diff --git a/mlir/include/mlir/ExecutionEngine/SparseTensor/Storage.h b/mlir/include/mlir/ExecutionEngine/SparseTensor/Storage.h index 19c49e6c487d..01c5f2382ffe 100644 --- a/mlir/include/mlir/ExecutionEngine/SparseTensor/Storage.h +++ b/mlir/include/mlir/ExecutionEngine/SparseTensor/Storage.h @@ -186,6 +186,7 @@ private: protected: const MapRef map; // non-owning pointers into dim2lvl/lvl2dim vectors + const bool allDense; }; /// A memory-resident sparse tensor using a storage scheme based on @@ -293,8 +294,6 @@ public: /// Partially specialize lexicographical insertions based on template types. void lexInsert(const uint64_t *lvlCoords, V val) final { assert(lvlCoords); - bool allDense = std::all_of(getLvlTypes().begin(), getLvlTypes().end(), - [](LevelType lt) { return isDenseLT(lt); }); if (allDense) { uint64_t lvlRank = getLvlRank(); uint64_t valIdx = 0; @@ -363,10 +362,12 @@ public: /// Finalizes lexicographic insertions. void endLexInsert() final { - if (values.empty()) - finalizeSegment(0); - else - endPath(0); + if (!allDense) { + if (values.empty()) + finalizeSegment(0); + else + endPath(0); + } } /// Allocates a new COO object and initializes it with the contents. @@ -705,7 +706,6 @@ SparseTensorStorage::SparseTensorStorage( // we reserve position/coordinate space based on all previous dense // levels, which works well up to first sparse level; but we should // really use nnz and dense/sparse distribution. - bool allDense = true; uint64_t sz = 1; for (uint64_t l = 0; l < lvlRank; l++) { if (isCompressedLvl(l)) { @@ -713,23 +713,19 @@ SparseTensorStorage::SparseTensorStorage( positions[l].push_back(0); coordinates[l].reserve(sz); sz = 1; - allDense = false; } else if (isLooseCompressedLvl(l)) { positions[l].reserve(2 * sz + 1); // last one unused positions[l].push_back(0); coordinates[l].reserve(sz); sz = 1; - allDense = false; } else if (isSingletonLvl(l)) { coordinates[l].reserve(sz); sz = 1; - allDense = false; } else if (is2OutOf4Lvl(l)) { - assert(allDense && l == lvlRank - 1 && "unexpected 2:4 usage"); + assert(l == lvlRank - 1 && "unexpected 2:4 usage"); sz = detail::checkedMul(sz, lvlSizes[l]) / 2; coordinates[l].reserve(sz); values.reserve(sz); - allDense = false; } else { // Dense level. assert(isDenseLvl(l)); sz = detail::checkedMul(sz, lvlSizes[l]); diff --git a/mlir/lib/ExecutionEngine/SparseTensor/Storage.cpp b/mlir/lib/ExecutionEngine/SparseTensor/Storage.cpp index 7f8f76f8ec18..0c7b3a228a65 100644 --- a/mlir/lib/ExecutionEngine/SparseTensor/Storage.cpp +++ b/mlir/lib/ExecutionEngine/SparseTensor/Storage.cpp @@ -17,6 +17,13 @@ using namespace mlir::sparse_tensor; +static inline bool isAllDense(uint64_t lvlRank, const LevelType *lvlTypes) { + for (uint64_t l = 0; l < lvlRank; l++) + if (!isDenseLT(lvlTypes[l])) + return false; + return true; +} + SparseTensorStorageBase::SparseTensorStorageBase( // NOLINT uint64_t dimRank, const uint64_t *dimSizes, uint64_t lvlRank, const uint64_t *lvlSizes, const LevelType *lvlTypes, @@ -26,15 +33,16 @@ SparseTensorStorageBase::SparseTensorStorageBase( // NOLINT lvlTypes(lvlTypes, lvlTypes + lvlRank), dim2lvlVec(dim2lvl, dim2lvl + lvlRank), lvl2dimVec(lvl2dim, lvl2dim + dimRank), - map(dimRank, lvlRank, dim2lvlVec.data(), lvl2dimVec.data()) { + map(dimRank, lvlRank, dim2lvlVec.data(), lvl2dimVec.data()), + allDense(isAllDense(lvlRank, lvlTypes)) { assert(dimSizes && lvlSizes && lvlTypes && dim2lvl && lvl2dim); // Validate dim-indexed parameters. assert(dimRank > 0 && "Trivial shape is unsupported"); - for (uint64_t d = 0; d < dimRank; ++d) + for (uint64_t d = 0; d < dimRank; d++) assert(dimSizes[d] > 0 && "Dimension size zero has trivial storage"); // Validate lvl-indexed parameters. assert(lvlRank > 0 && "Trivial shape is unsupported"); - for (uint64_t l = 0; l < lvlRank; ++l) { + for (uint64_t l = 0; l < lvlRank; l++) { assert(lvlSizes[l] > 0 && "Level size zero has trivial storage"); assert(isDenseLvl(l) || isCompressedLvl(l) || isLooseCompressedLvl(l) || isSingletonLvl(l) || is2OutOf4Lvl(l)); -- GitLab From a9a5af82704d772509ccef87991384f47b65884d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Valentin=20Clement=20=28=E3=83=90=E3=83=AC=E3=83=B3?= =?UTF-8?q?=E3=82=BF=E3=82=A4=E3=83=B3=20=E3=82=AF=E3=83=AC=E3=83=A1?= =?UTF-8?q?=E3=83=B3=29?= Date: Thu, 30 Nov 2023 14:25:03 -0800 Subject: [PATCH 055/699] [flang][openacc] Support early return in acc.loop (#73841) Early return is accepted in OpenACC loop not directly nested in a compute construct. Since acc.loop operation has a region, the `func.return` operation cannot be directly used inside the region. An early return is materialized by an `acc.yield` operation returning a `true` value. The standard end of the `acc.loop` region yield a `false` value in this case. A conditional branch operation on the `acc.loop` result will branch to the `finalBlock` or just to the continue block whether an early exit was produce in the acc.loop. --- flang/include/flang/Lower/OpenACC.h | 13 ++- flang/lib/Lower/Bridge.cpp | 23 +++++- flang/lib/Lower/OpenACC.cpp | 94 ++++++++++++++++++---- flang/test/Lower/OpenACC/acc-loop-exit.f90 | 37 +++++++++ 4 files changed, 148 insertions(+), 19 deletions(-) create mode 100644 flang/test/Lower/OpenACC/acc-loop-exit.f90 diff --git a/flang/include/flang/Lower/OpenACC.h b/flang/include/flang/Lower/OpenACC.h index 409956f0ecb3..f23e4726f33e 100644 --- a/flang/include/flang/Lower/OpenACC.h +++ b/flang/include/flang/Lower/OpenACC.h @@ -64,9 +64,10 @@ static constexpr llvm::StringRef declarePreDeallocSuffix = static constexpr llvm::StringRef declarePostDeallocSuffix = "_acc_declare_update_desc_post_dealloc"; -void genOpenACCConstruct(AbstractConverter &, - Fortran::semantics::SemanticsContext &, - pft::Evaluation &, const parser::OpenACCConstruct &); +mlir::Value genOpenACCConstruct(AbstractConverter &, + Fortran::semantics::SemanticsContext &, + pft::Evaluation &, + const parser::OpenACCConstruct &); void genOpenACCDeclarativeConstruct(AbstractConverter &, Fortran::semantics::SemanticsContext &, StatementContext &, @@ -112,6 +113,12 @@ void attachDeclarePostDeallocAction(AbstractConverter &, fir::FirOpBuilder &, void genOpenACCTerminator(fir::FirOpBuilder &, mlir::Operation *, mlir::Location); +bool isInOpenACCLoop(fir::FirOpBuilder &); + +void setInsertionPointAfterOpenACCLoopIfInside(fir::FirOpBuilder &); + +void genEarlyReturnInOpenACCLoop(fir::FirOpBuilder &, mlir::Location); + } // namespace lower } // namespace Fortran diff --git a/flang/lib/Lower/Bridge.cpp b/flang/lib/Lower/Bridge.cpp index 0090c2f12121..61c02c896017 100644 --- a/flang/lib/Lower/Bridge.cpp +++ b/flang/lib/Lower/Bridge.cpp @@ -2382,11 +2382,25 @@ private: void genFIR(const Fortran::parser::OpenACCConstruct &acc) { mlir::OpBuilder::InsertPoint insertPt = builder->saveInsertionPoint(); localSymbols.pushScope(); - genOpenACCConstruct(*this, bridge.getSemanticsContext(), getEval(), acc); + mlir::Value exitCond = genOpenACCConstruct( + *this, bridge.getSemanticsContext(), getEval(), acc); for (Fortran::lower::pft::Evaluation &e : getEval().getNestedEvaluations()) genFIR(e); localSymbols.popScope(); builder->restoreInsertionPoint(insertPt); + + const Fortran::parser::OpenACCLoopConstruct *accLoop = + std::get_if(&acc.u); + if (accLoop && exitCond) { + Fortran::lower::pft::FunctionLikeUnit *funit = + getEval().getOwningProcedure(); + assert(funit && "not inside main program, function or subroutine"); + mlir::Block *continueBlock = + builder->getBlock()->splitBlock(builder->getBlock()->end()); + builder->create(toLocation(), exitCond, + funit->finalBlock, continueBlock); + builder->setInsertionPointToEnd(continueBlock); + } } void genFIR(const Fortran::parser::OpenACCDeclarativeConstruct &accDecl) { @@ -4091,10 +4105,15 @@ private: // Branch to the last block of the SUBROUTINE, which has the actual return. if (!funit->finalBlock) { mlir::OpBuilder::InsertPoint insPt = builder->saveInsertionPoint(); + Fortran::lower::setInsertionPointAfterOpenACCLoopIfInside(*builder); funit->finalBlock = builder->createBlock(&builder->getRegion()); builder->restoreInsertionPoint(insPt); } - builder->create(loc, funit->finalBlock); + + if (Fortran::lower::isInOpenACCLoop(*builder)) + Fortran::lower::genEarlyReturnInOpenACCLoop(*builder, loc); + else + builder->create(loc, funit->finalBlock); } void genFIR(const Fortran::parser::CycleStmt &) { diff --git a/flang/lib/Lower/OpenACC.cpp b/flang/lib/Lower/OpenACC.cpp index 8c6c22210cf0..e2abed1b9f4f 100644 --- a/flang/lib/Lower/OpenACC.cpp +++ b/flang/lib/Lower/OpenACC.cpp @@ -25,10 +25,12 @@ #include "flang/Optimizer/Builder/HLFIRTools.h" #include "flang/Optimizer/Builder/IntrinsicCall.h" #include "flang/Optimizer/Builder/Todo.h" +#include "flang/Parser/parse-tree-visitor.h" #include "flang/Parser/parse-tree.h" #include "flang/Semantics/expression.h" #include "flang/Semantics/scope.h" #include "flang/Semantics/tools.h" +#include "mlir/Dialect/ControlFlow/IR/ControlFlowOps.h" #include "llvm/Frontend/OpenACC/ACC.h.inc" // Special value for * passed in device_type or gang clauses. @@ -1381,9 +1383,10 @@ static Op createRegionOp(fir::FirOpBuilder &builder, mlir::Location loc, Fortran::lower::pft::Evaluation &eval, const llvm::SmallVectorImpl &operands, const llvm::SmallVectorImpl &operandSegments, - bool outerCombined = false) { - llvm::ArrayRef argTy; - Op op = builder.create(loc, argTy, operands); + bool outerCombined = false, + llvm::SmallVector retTy = {}, + mlir::Value yieldValue = {}) { + Op op = builder.create(loc, retTy, operands); builder.createBlock(&op.getRegion()); mlir::Block &block = op.getRegion().back(); builder.setInsertionPointToStart(&block); @@ -1401,7 +1404,16 @@ static Op createRegionOp(fir::FirOpBuilder &builder, mlir::Location loc, mlir::acc::YieldOp>( builder, eval.getNestedEvaluations()); - builder.create(loc); + if (yieldValue) { + if constexpr (std::is_same_v) { + Terminator yieldOp = builder.create(loc, yieldValue); + yieldValue.getDefiningOp()->moveBefore(yieldOp); + } else { + builder.create(loc); + } + } else { + builder.create(loc); + } builder.setInsertionPointToStart(&block); return op; } @@ -1494,7 +1506,8 @@ createLoopOp(Fortran::lower::AbstractConverter &converter, Fortran::lower::pft::Evaluation &eval, Fortran::semantics::SemanticsContext &semanticsContext, Fortran::lower::StatementContext &stmtCtx, - const Fortran::parser::AccClauseList &accClauseList) { + const Fortran::parser::AccClauseList &accClauseList, + bool needEarlyReturnHandling = false) { fir::FirOpBuilder &builder = converter.getFirOpBuilder(); mlir::Value workerNum; @@ -1599,8 +1612,17 @@ createLoopOp(Fortran::lower::AbstractConverter &converter, addOperands(operands, operandSegments, privateOperands); addOperands(operands, operandSegments, reductionOperands); + llvm::SmallVector retTy; + mlir::Value yieldValue; + if (needEarlyReturnHandling) { + mlir::Type i1Ty = builder.getI1Type(); + yieldValue = builder.createIntegerConstant(currentLocation, i1Ty, 0); + retTy.push_back(i1Ty); + } + auto loopOp = createRegionOp( - builder, currentLocation, eval, operands, operandSegments); + builder, currentLocation, eval, operands, operandSegments, + /*outerCombined=*/false, retTy, yieldValue); if (hasGang) loopOp.setHasGangAttr(builder.getUnitAttr()); @@ -1647,16 +1669,34 @@ createLoopOp(Fortran::lower::AbstractConverter &converter, return loopOp; } -static void genACC(Fortran::lower::AbstractConverter &converter, - Fortran::semantics::SemanticsContext &semanticsContext, - Fortran::lower::pft::Evaluation &eval, - const Fortran::parser::OpenACCLoopConstruct &loopConstruct) { +static bool hasEarlyReturn(Fortran::lower::pft::Evaluation &eval) { + bool hasReturnStmt = false; + for (auto &e : eval.getNestedEvaluations()) { + e.visit(Fortran::common::visitors{ + [&](const Fortran::parser::ReturnStmt &) { hasReturnStmt = true; }, + [&](const auto &s) {}, + }); + if (e.hasNestedEvaluations()) + hasReturnStmt = hasEarlyReturn(e); + } + return hasReturnStmt; +} + +static mlir::Value +genACC(Fortran::lower::AbstractConverter &converter, + Fortran::semantics::SemanticsContext &semanticsContext, + Fortran::lower::pft::Evaluation &eval, + const Fortran::parser::OpenACCLoopConstruct &loopConstruct) { const auto &beginLoopDirective = std::get(loopConstruct.t); const auto &loopDirective = std::get(beginLoopDirective.t); + bool needEarlyExitHandling = false; + if (eval.lowerAsUnstructured()) + needEarlyExitHandling = hasEarlyReturn(eval); + mlir::Location currentLocation = converter.genLocation(beginLoopDirective.source); Fortran::lower::StatementContext stmtCtx; @@ -1664,9 +1704,13 @@ static void genACC(Fortran::lower::AbstractConverter &converter, if (loopDirective.v == llvm::acc::ACCD_loop) { const auto &accClauseList = std::get(beginLoopDirective.t); - createLoopOp(converter, currentLocation, eval, semanticsContext, stmtCtx, - accClauseList); + auto loopOp = + createLoopOp(converter, currentLocation, eval, semanticsContext, + stmtCtx, accClauseList, needEarlyExitHandling); + if (needEarlyExitHandling) + return loopOp.getResult(0); } + return mlir::Value{}; } template @@ -3431,12 +3475,13 @@ genACC(Fortran::lower::AbstractConverter &converter, builder.restoreInsertionPoint(crtPos); } -void Fortran::lower::genOpenACCConstruct( +mlir::Value Fortran::lower::genOpenACCConstruct( Fortran::lower::AbstractConverter &converter, Fortran::semantics::SemanticsContext &semanticsContext, Fortran::lower::pft::Evaluation &eval, const Fortran::parser::OpenACCConstruct &accConstruct) { + mlir::Value exitCond; std::visit( common::visitors{ [&](const Fortran::parser::OpenACCBlockConstruct &blockConstruct) { @@ -3447,7 +3492,7 @@ void Fortran::lower::genOpenACCConstruct( genACC(converter, semanticsContext, eval, combinedConstruct); }, [&](const Fortran::parser::OpenACCLoopConstruct &loopConstruct) { - genACC(converter, semanticsContext, eval, loopConstruct); + exitCond = genACC(converter, semanticsContext, eval, loopConstruct); }, [&](const Fortran::parser::OpenACCStandaloneConstruct &standaloneConstruct) { @@ -3467,6 +3512,7 @@ void Fortran::lower::genOpenACCConstruct( }, }, accConstruct.u); + return exitCond; } void Fortran::lower::genOpenACCDeclarativeConstruct( @@ -3560,3 +3606,23 @@ void Fortran::lower::genOpenACCTerminator(fir::FirOpBuilder &builder, else builder.create(loc); } + +bool Fortran::lower::isInOpenACCLoop(fir::FirOpBuilder &builder) { + if (builder.getBlock()->getParent()->getParentOfType()) + return true; + return false; +} + +void Fortran::lower::setInsertionPointAfterOpenACCLoopIfInside( + fir::FirOpBuilder &builder) { + if (auto loopOp = + builder.getBlock()->getParent()->getParentOfType()) + builder.setInsertionPointAfter(loopOp); +} + +void Fortran::lower::genEarlyReturnInOpenACCLoop(fir::FirOpBuilder &builder, + mlir::Location loc) { + mlir::Value yieldValue = + builder.createIntegerConstant(loc, builder.getI1Type(), 1); + builder.create(loc, yieldValue); +} diff --git a/flang/test/Lower/OpenACC/acc-loop-exit.f90 b/flang/test/Lower/OpenACC/acc-loop-exit.f90 new file mode 100644 index 000000000000..75f1c3073327 --- /dev/null +++ b/flang/test/Lower/OpenACC/acc-loop-exit.f90 @@ -0,0 +1,37 @@ +! RUN: bbc -fopenacc -emit-hlfir %s -o - | FileCheck %s + +subroutine sub1(x, a) + real :: x(200) + integer :: a + + !$acc loop + do i = 100, 200 + x(i) = 1.0 + if (i == a) return + end do + + i = 2 +end + +! CHECK-LABEL: func.func @_QPsub1 +! CHECK: %[[A:.*]]:2 = hlfir.declare %arg1 {uniq_name = "_QFsub1Ea"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[EXIT_COND:.*]] = acc.loop { +! CHECK: ^bb{{.*}}: +! CHECK: ^bb{{.*}}: +! CHECK: %[[LOAD_A:.*]] = fir.load %[[A]]#0 : !fir.ref +! CHECK: %[[CMP:.*]] = arith.cmpi eq, %15, %[[LOAD_A]] : i32 +! CHECK: cf.cond_br %[[CMP]], ^[[EARLY_RET:.*]], ^[[NO_RET:.*]] +! CHECK: ^[[EARLY_RET]]: +! CHECK: acc.yield %true : i1 +! CHECK: ^[[NO_RET]]: +! CHECK: cf.br ^bb{{.*}} +! CHECK: ^bb{{.*}}: +! CHECK: acc.yield %false : i1 +! CHECK: }(i1) +! CHECK: cf.cond_br %[[EXIT_COND]], ^[[EXIT_BLOCK:.*]], ^[[CONTINUE_BLOCK:.*]] +! CHECK: ^[[CONTINUE_BLOCK]]: +! CHECK: hlfir.assign +! CHECK: cf.br ^[[EXIT_BLOCK]] +! CHECK: ^[[EXIT_BLOCK]]: +! CHECK: return +! CHECK: } -- GitLab From 4f3081296f37a244010dfd493a07e95c06ef22ff Mon Sep 17 00:00:00 2001 From: Maksim Panchenko Date: Thu, 30 Nov 2023 14:31:38 -0800 Subject: [PATCH 056/699] [BOLT][NFC] Fix comment (#73983) Fix off-by-one error in comment. --- bolt/lib/Core/BinaryFunction.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bolt/lib/Core/BinaryFunction.cpp b/bolt/lib/Core/BinaryFunction.cpp index 76bac2f62441..be033cf07668 100644 --- a/bolt/lib/Core/BinaryFunction.cpp +++ b/bolt/lib/Core/BinaryFunction.cpp @@ -3352,9 +3352,9 @@ void BinaryFunction::fixBranches() { // We are going to generate two branches. Check if their targets are in // the same fragment as this block. If only one target is in the same // fragment, make it the destination of the conditional branch. There - // is a chance it will be a short branch which takes 5 bytes fewer than + // is a chance it will be a short branch which takes 4 bytes fewer than // a long conditional branch. For unconditional branch, the difference - // is 4 bytes. + // is 3 bytes. if (BB->getFragmentNum() != TSuccessor->getFragmentNum() && BB->getFragmentNum() == FSuccessor->getFragmentNum()) swapSuccessors(); -- GitLab From 9a485b02f9e3184ae34e64dbadc2a17b787db007 Mon Sep 17 00:00:00 2001 From: madanial0 <118996571+madanial0@users.noreply.github.com> Date: Thu, 30 Nov 2023 17:45:21 -0500 Subject: [PATCH 057/699] [Flang] Testcase changes to switch directories before rm (NFC) (#73602) In AIX, the following testcase fails in attempt to delete the current directory, exiting current directory before removing --------- Co-authored-by: Mark Danial --- flang/test/Driver/write-module.f90 | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/flang/test/Driver/write-module.f90 b/flang/test/Driver/write-module.f90 index 0be5c5817ba9..c4dbaddd4b27 100644 --- a/flang/test/Driver/write-module.f90 +++ b/flang/test/Driver/write-module.f90 @@ -9,6 +9,7 @@ ! RUN: rm -rf %t && mkdir -p %t/dir-flang ! RUN: cd %t && %flang -fsyntax-only -module-dir %t/dir-flang %s ! RUN: ls %t/dir-flang/testmodule.mod && not ls %t/testmodule.mod +! RUN: cd - !-------------------------- ! -module-dir @@ -16,6 +17,7 @@ ! RUN: rm -rf %t && mkdir -p %t/dir-flang ! RUN: cd %t && %flang -fsyntax-only -module-dir%t/dir-flang %s ! RUN: ls %t/dir-flang/testmodule.mod && not ls %t/testmodule.mod +! RUN: cd - !--------------------------- ! -J @@ -23,6 +25,7 @@ ! RUN: rm -rf %t && mkdir -p %t/dir-flang ! RUN: cd %t && %flang -fsyntax-only -J %t/dir-flang %s ! RUN: ls %t/dir-flang/testmodule.mod && not ls %t/testmodule.mod +! RUN: cd - !------------------------------ ! -J @@ -30,6 +33,7 @@ ! RUN: rm -rf %t && mkdir -p %t/dir-flang ! RUN: cd %t && %flang -fsyntax-only -J%t/dir-flang %s ! RUN: ls %t/dir-flang/testmodule.mod && not ls %t/testmodule.mod +! RUN: cd - module testmodule type::t2 -- GitLab From 812dad536ed50abe94d6e2b2519f351791c24c59 Mon Sep 17 00:00:00 2001 From: Brad Smith Date: Thu, 30 Nov 2023 17:58:09 -0500 Subject: [PATCH 058/699] [Driver] Remove support for FreeBSD 11.x (#73392) Now that FreeBSD 14.0 has been released make the 12.x branch the oldest supported releases. -fuse-init-array defaults to on. DWARF 4 is now the default. --- clang/lib/Driver/ToolChains/FreeBSD.cpp | 17 ----------------- clang/lib/Driver/ToolChains/FreeBSD.h | 6 +----- clang/test/Driver/clang-g-opts.c | 8 ++++---- clang/test/Driver/constructors.c | 4 ---- clang/test/Driver/debug-options.c | 13 +------------ 5 files changed, 6 insertions(+), 42 deletions(-) diff --git a/clang/lib/Driver/ToolChains/FreeBSD.cpp b/clang/lib/Driver/ToolChains/FreeBSD.cpp index d46feb3459a6..b7c9e0e51cdb 100644 --- a/clang/lib/Driver/ToolChains/FreeBSD.cpp +++ b/clang/lib/Driver/ToolChains/FreeBSD.cpp @@ -400,13 +400,6 @@ FreeBSD::FreeBSD(const Driver &D, const llvm::Triple &Triple, getFilePaths().push_back(concat(getDriver().SysRoot, "/usr/lib")); } -unsigned FreeBSD::GetDefaultDwarfVersion() const { - unsigned Major = getTriple().getOSMajorVersion(); - if (Major >= 12 || Major == 0) - return 4; - return 2; -} - void FreeBSD::AddClangSystemIncludeArgs( const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args) const { @@ -510,13 +503,3 @@ SanitizerMask FreeBSD::getSupportedSanitizers() const { } return Res; } - -void FreeBSD::addClangTargetOptions(const ArgList &DriverArgs, - ArgStringList &CC1Args, - Action::OffloadKind) const { - unsigned Major = getTriple().getOSMajorVersion(); - if (!DriverArgs.hasFlag(options::OPT_fuse_init_array, - options::OPT_fno_use_init_array, - (Major >= 12 || Major == 0))) - CC1Args.push_back("-fno-use-init-array"); -} diff --git a/clang/lib/Driver/ToolChains/FreeBSD.h b/clang/lib/Driver/ToolChains/FreeBSD.h index 959cbf78ddc7..7ab63905ed4f 100644 --- a/clang/lib/Driver/ToolChains/FreeBSD.h +++ b/clang/lib/Driver/ToolChains/FreeBSD.h @@ -82,14 +82,10 @@ public: getDefaultUnwindTableLevel(const llvm::opt::ArgList &Args) const override; bool isPIEDefault(const llvm::opt::ArgList &Args) const override; SanitizerMask getSupportedSanitizers() const override; - unsigned GetDefaultDwarfVersion() const override; + unsigned GetDefaultDwarfVersion() const override { return 4; } // Until dtrace (via CTF) and LLDB can deal with distributed debug info, // FreeBSD defaults to standalone/full debug info. bool GetDefaultStandaloneDebug() const override { return true; } - void - addClangTargetOptions(const llvm::opt::ArgList &DriverArgs, - llvm::opt::ArgStringList &CC1Args, - Action::OffloadKind DeviceOffloadKind) const override; protected: Tool *buildAssembler() const override; diff --git a/clang/test/Driver/clang-g-opts.c b/clang/test/Driver/clang-g-opts.c index b1cdf411925a..b73602a155b0 100644 --- a/clang/test/Driver/clang-g-opts.c +++ b/clang/test/Driver/clang-g-opts.c @@ -7,8 +7,8 @@ // RUN: | FileCheck --check-prefix=CHECK-WITH-G-DWARF2 %s // RUN: %clang -### -S %s -g -target i686-pc-openbsd 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-WITH-G-DWARF2 %s -// RUN: %clang -### -S %s -g -target x86_64-pc-freebsd10.0 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-WITH-G-DWARF2 %s +// RUN: %clang -### -S %s -g -target x86_64-pc-freebsd 2>&1 \ +// RUN: | FileCheck --check-prefix=CHECK-WITH-G-DWARF4 %s // RUN: %clang -### -S %s -g --target=x86_64-unknown-haiku 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-WITH-G-DWARF4 %s @@ -27,8 +27,8 @@ // RUN: | FileCheck --check-prefix=CHECK-WITH-G-STANDALONE %s // RUN: %clang -### -S %s -g0 -g -target i686-pc-openbsd 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-WITH-G-DWARF2 %s -// RUN: %clang -### -S %s -g0 -g -target x86_64-pc-freebsd10.0 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-WITH-G-DWARF2 %s +// RUN: %clang -### -S %s -g0 -g -target x86_64-pc-freebsd 2>&1 \ +// RUN: | FileCheck --check-prefix=CHECK-WITH-G-DWARF4 %s // RUN: %clang -### -S %s -g0 -g --target=x86_64-unknown-haiku 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-WITH-G-DWARF4 %s // RUN: %clang -### -S %s -g0 -g --target=i386-pc-solaris 2>&1 \ diff --git a/clang/test/Driver/constructors.c b/clang/test/Driver/constructors.c index 45d6dd6cb171..1cb3aec840c2 100644 --- a/clang/test/Driver/constructors.c +++ b/clang/test/Driver/constructors.c @@ -75,10 +75,6 @@ // RUN: --target=arm64-none-none-eabi \ // RUN: | FileCheck --check-prefix=CHECK-INIT-ARRAY %s -// RUN: %clang -### %s -fsyntax-only 2>&1 \ -// RUN: --target=i386-unknown-freebsd11 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-INIT-ARRAY %s -// // RUN: %clang -### %s -fsyntax-only 2>&1 \ // RUN: --target=i386-unknown-freebsd \ // RUN: | FileCheck --check-prefix=CHECK-INIT-ARRAY %s diff --git a/clang/test/Driver/debug-options.c b/clang/test/Driver/debug-options.c index 6c472f047528..e4809511ac91 100644 --- a/clang/test/Driver/debug-options.c +++ b/clang/test/Driver/debug-options.c @@ -76,10 +76,7 @@ // RUN: | FileCheck -check-prefix=G_STANDALONE %s // FreeBSD. -// RUN: %clang -### -c -g %s -target x86_64-pc-freebsd11.0 2>&1 \ -// RUN: | FileCheck -check-prefix=G_GDB \ -// RUN: -check-prefix=G_DWARF2 %s -// RUN: %clang -### -c -g %s -target x86_64-pc-freebsd12.0 2>&1 \ +// RUN: %clang -### -c -g %s -target x86_64-pc-freebsd 2>&1 \ // RUN: | FileCheck -check-prefix=G_GDB \ // RUN: -check-prefix=G_DWARF4 %s @@ -188,16 +185,12 @@ // RUN: | FileCheck -check-prefix=GLTO_ONLY %s // RUN: %clang -### -c -gline-tables-only %s -target i686-pc-openbsd 2>&1 \ // RUN: | FileCheck -check-prefix=GLTO_ONLY_DWARF2 %s -// RUN: %clang -### -c -gline-tables-only %s -target x86_64-pc-freebsd10.0 2>&1 \ -// RUN: | FileCheck -check-prefix=GLTO_ONLY_DWARF2 %s // RUN: %clang -### -c -gline-tables-only -g %s -target x86_64-linux-gnu 2>&1 \ // RUN: | FileCheck -check-prefix=G_ONLY %s // RUN: %clang -### -c -gline-tables-only -g %s -target x86_64-apple-darwin16 2>&1 \ // RUN: | FileCheck -check-prefix=G_STANDALONE -check-prefix=G_DWARF4 %s // RUN: %clang -### -c -gline-tables-only -g %s -target i686-pc-openbsd 2>&1 \ // RUN: | FileCheck -check-prefix=G_ONLY_DWARF2 %s -// RUN: %clang -### -c -gline-tables-only -g %s -target x86_64-pc-freebsd10.0 2>&1 \ -// RUN: | FileCheck -check-prefix=G_ONLY_DWARF2 %s // RUN: %clang -### -c -gline-tables-only -g %s --target=i386-pc-solaris 2>&1 \ // RUN: | FileCheck -check-prefix=G_ONLY %s // RUN: %clang -### -c -gline-tables-only -g0 %s 2>&1 \ @@ -207,16 +200,12 @@ // RUN: | FileCheck -check-prefix=GLIO_ONLY %s // RUN: %clang -### -c -gline-directives-only %s -target i686-pc-openbsd 2>&1 \ // RUN: | FileCheck -check-prefix=GLIO_ONLY_DWARF2 %s -// RUN: %clang -### -c -gline-directives-only %s -target x86_64-pc-freebsd10.0 2>&1 \ -// RUN: | FileCheck -check-prefix=GLIO_ONLY_DWARF2 %s // RUN: %clang -### -c -gline-directives-only -g %s -target x86_64-linux-gnu 2>&1 \ // RUN: | FileCheck -check-prefix=G_ONLY %s // RUN: %clang -### -c -gline-directives-only -g %s -target x86_64-apple-darwin16 2>&1 \ // RUN: | FileCheck -check-prefix=G_STANDALONE -check-prefix=G_DWARF4 %s // RUN: %clang -### -c -gline-directives-only -g %s -target i686-pc-openbsd 2>&1 \ // RUN: | FileCheck -check-prefix=G_ONLY_DWARF2 %s -// RUN: %clang -### -c -gline-directives-only -g %s -target x86_64-pc-freebsd10.0 2>&1 \ -// RUN: | FileCheck -check-prefix=G_ONLY_DWARF2 %s // RUN: %clang -### -c -gline-directives-only -g %s --target=i386-pc-solaris 2>&1 \ // RUN: | FileCheck -check-prefix=G_ONLY %s // RUN: %clang -### -c -gline-directives-only -g0 %s 2>&1 \ -- GitLab From c73a3f16f81aaa427c61f69020a82b5b09570ffb Mon Sep 17 00:00:00 2001 From: Jason Molenda Date: Mon, 27 Nov 2023 13:28:59 -0800 Subject: [PATCH 059/699] [lldb] [mostly NFC] Large WP foundation: WatchpointResources (#68845) This patch is rearranging code a bit to add WatchpointResources to Process. A WatchpointResource is meant to represent a hardware watchpoint register in the inferior process. It has an address, a size, a type, and a list of Watchpoints that are using this WatchpointResource. This current patch doesn't add any of the features of WatchpointResources that make them interesting -- a user asking to watch a 24 byte object could watch this with three 8 byte WatchpointResources. Or a Watchpoint on 1 byte at 0x1002 and a second watchpoint on 1 byte at 0x1003, these must both be served by a single WatchpointResource on that doubleword at 0x1000 on a 64-bit target, if two hardware watchpoint registers were used to track these separately, one of them may not be hit. Or if you have one Watchpoint on a variable with a condition set, and another Watchpoint on that same variable with a command defined or different condition, or ignorecount, both of those Watchpoints need to evaluate their criteria/commands when their WatchpointResource has been hit. There's a bit of code movement to rearrange things in the direction I'll need for implementing this feature, so I want to start with reviewing & landing this mostly NFC patch and we can focus on the algorithmic choices about how WatchpointResources are shared and handled as they're triggeed, separately. This patch also stops printing "Watchpoint hit: old value: , new vlaue: " for Read watchpoints. I could make an argument for print "Watchpoint hit: current value " but the current output doesn't make any sense, and the user can print the value if they are particularly interested. Read watchpoints are used primarily to understand what code is reading a variable. This patch adds more fallbacks for how to print the objects being watched if we have types, instead of assuming they are all integral values, so a struct will print its elements. As large watchpoints are added, we'll be doing a lot more of those. To track the WatchpointSP in the WatchpointResources, I changed the internal API which took a WatchpointSP and devolved it to a Watchpoint*, which meant touching several different Process files. I removed the watchpoint code in ProcessKDP which only reported that watchpoints aren't supported, the base class does that already. I haven't yet changed how we receive a watchpoint to identify the WatchpointResource responsible for the trigger, and identify all Watchpoints that are using this Resource to evaluate their conditions etc. This is the same work that a BreakpointSite needs to do when it has been tiggered, where multiple Breakpoints may be at the same address. There is not yet any printing of the Resources that a Watchpoint is implemented in terms of ("watchpoint list", or SBWatchpoint::GetDescription). "watchpoint set var" and "watchpoint set expression" take a size argument which was previously 1, 2, 4, or 8 (an enum). I've changed this to an unsigned int. Most hardware implementations can only watch 1, 2, 4, 8 byte ranges, but with Resources we'll allow a user to ask for different sized watchpoints and set them in hardware-expressble terms soon. I've annotated areas where I know there is work still needed with LWP_TODO that I'll be working on once this is landed. I've tested this on aarch64 macOS, aarch64 Linux, and Intel macOS. https://discourse.llvm.org/t/rfc-large-watchpoint-support-in-lldb/72116 (cherry picked from commit fc6b72523f3d73b921690a713e97a433c96066c6) --- lldb/include/lldb/Breakpoint/BreakpointSite.h | 68 ++-- .../lldb/Breakpoint/BreakpointSiteList.h | 173 ---------- .../lldb/Breakpoint/StopPointSiteList.h | 310 ++++++++++++++++++ lldb/include/lldb/Breakpoint/Watchpoint.h | 2 +- .../lldb/Breakpoint/WatchpointResource.h | 169 ++++++++++ .../lldb/Breakpoint/WatchpointResourceList.h | 145 ++++++++ .../lldb/Interpreter/OptionGroupWatchpoint.h | 5 +- lldb/include/lldb/Target/Process.h | 43 ++- lldb/include/lldb/lldb-defines.h | 4 + lldb/include/lldb/lldb-forward.h | 4 +- lldb/include/lldb/lldb-types.h | 1 + lldb/source/API/SBThread.cpp | 4 +- lldb/source/API/SBWatchpoint.cpp | 4 +- lldb/source/Breakpoint/BreakpointLocation.cpp | 6 +- lldb/source/Breakpoint/BreakpointSite.cpp | 84 +++-- lldb/source/Breakpoint/BreakpointSiteList.cpp | 193 ----------- lldb/source/Breakpoint/CMakeLists.txt | 4 +- lldb/source/Breakpoint/StopPointSiteList.cpp | 37 +++ lldb/source/Breakpoint/Watchpoint.cpp | 76 +++-- lldb/source/Breakpoint/WatchpointResource.cpp | 122 +++++++ .../Breakpoint/WatchpointResourceList.cpp | 114 +++++++ lldb/source/Commands/CommandObjectProcess.cpp | 4 +- .../Commands/CommandObjectWatchpoint.cpp | 8 +- .../Interpreter/OptionGroupWatchpoint.cpp | 43 +-- .../ItaniumABI/ItaniumABILanguageRuntime.cpp | 2 +- .../AppleObjCRuntime/AppleObjCRuntime.cpp | 2 +- ...pleThreadPlanStepThroughObjCTrampoline.cpp | 2 +- .../Platform/MacOSX/PlatformDarwin.cpp | 2 +- .../Process/MacOSX-Kernel/ProcessKDP.cpp | 14 - .../Process/MacOSX-Kernel/ProcessKDP.h | 7 - .../Process/Utility/StopInfoMachException.cpp | 9 + .../Process/Windows/Common/ProcessWindows.cpp | 38 +-- .../Process/Windows/Common/ProcessWindows.h | 6 +- .../Process/gdb-remote/ProcessGDBRemote.cpp | 270 +++++++++------ .../Process/gdb-remote/ProcessGDBRemote.h | 6 +- lldb/source/Target/Platform.cpp | 2 +- lldb/source/Target/Process.cpp | 60 ++-- lldb/source/Target/StackFrameList.cpp | 5 +- lldb/source/Target/StopInfo.cpp | 68 ++-- lldb/source/Target/Target.cpp | 31 +- lldb/source/Target/ThreadPlanCallFunction.cpp | 4 +- lldb/source/Target/ThreadPlanStepOut.cpp | 2 +- lldb/source/Target/ThreadPlanStepRange.cpp | 14 +- lldb/source/Target/ThreadPlanStepUntil.cpp | 4 +- .../watchlocation/TestTargetWatchAddress.py | 2 +- lldb/test/Shell/Watchpoint/Inputs/val.c | 3 + .../LocalVariableWatchpointDisabler.test | 7 + lldb/test/Shell/Watchpoint/SetErrorCases.test | 2 +- 48 files changed, 1426 insertions(+), 759 deletions(-) delete mode 100644 lldb/include/lldb/Breakpoint/BreakpointSiteList.h create mode 100644 lldb/include/lldb/Breakpoint/StopPointSiteList.h create mode 100644 lldb/include/lldb/Breakpoint/WatchpointResource.h create mode 100644 lldb/include/lldb/Breakpoint/WatchpointResourceList.h delete mode 100644 lldb/source/Breakpoint/BreakpointSiteList.cpp create mode 100644 lldb/source/Breakpoint/StopPointSiteList.cpp create mode 100644 lldb/source/Breakpoint/WatchpointResource.cpp create mode 100644 lldb/source/Breakpoint/WatchpointResourceList.cpp diff --git a/lldb/include/lldb/Breakpoint/BreakpointSite.h b/lldb/include/lldb/Breakpoint/BreakpointSite.h index e4c850206fd8..17b76d51c1ae 100644 --- a/lldb/include/lldb/Breakpoint/BreakpointSite.h +++ b/lldb/include/lldb/Breakpoint/BreakpointSite.h @@ -45,6 +45,9 @@ public: // display any breakpoint opcodes. }; + typedef lldb::break_id_t SiteID; + typedef lldb::break_id_t ConstituentID; + ~BreakpointSite() override; // This section manages the breakpoint traps @@ -77,8 +80,8 @@ public: /// Tells whether the current breakpoint site is enabled or not /// /// This is a low-level enable bit for the breakpoint sites. If a - /// breakpoint site has no enabled owners, it should just get removed. This - /// enable/disable is for the low-level target code to enable and disable + /// breakpoint site has no enabled constituents, it should just get removed. + /// This enable/disable is for the low-level target code to enable and disable /// breakpoint sites when single stepping, etc. bool IsEnabled() const; @@ -101,44 +104,46 @@ public: /// Standard Dump method void Dump(Stream *s) const override; - /// The "Owners" are the breakpoint locations that share this breakpoint - /// site. The method adds the \a owner to this breakpoint site's owner list. + /// The "Constituents" are the breakpoint locations that share this breakpoint + /// site. The method adds the \a constituent to this breakpoint site's + /// constituent list. /// - /// \param[in] owner - /// \a owner is the Breakpoint Location to add. - void AddOwner(const lldb::BreakpointLocationSP &owner); + /// \param[in] constituent + /// \a constituent is the Breakpoint Location to add. + void AddConstituent(const lldb::BreakpointLocationSP &constituent); /// This method returns the number of breakpoint locations currently located /// at this breakpoint site. /// /// \return - /// The number of owners. - size_t GetNumberOfOwners(); + /// The number of constituents. + size_t GetNumberOfConstituents(); /// This method returns the breakpoint location at index \a index located at - /// this breakpoint site. The owners are listed ordinally from 0 to - /// GetNumberOfOwners() - 1 so you can use this method to iterate over the - /// owners + /// this breakpoint site. The constituents are listed ordinally from 0 to + /// GetNumberOfConstituents() - 1 so you can use this method to iterate over + /// the constituents /// /// \param[in] idx - /// The index in the list of owners for which you wish the owner location. + /// The index in the list of constituents for which you wish the + /// constituent location. /// /// \return /// A shared pointer to the breakpoint location at that index. - lldb::BreakpointLocationSP GetOwnerAtIndex(size_t idx); + lldb::BreakpointLocationSP GetConstituentAtIndex(size_t idx); - /// This method copies the breakpoint site's owners into a new collection. - /// It does this while the owners mutex is locked. + /// This method copies the breakpoint site's constituents into a new + /// collection. It does this while the constituents mutex is locked. /// /// \param[out] out_collection - /// The BreakpointLocationCollection into which to put the owners + /// The BreakpointLocationCollection into which to put the constituents /// of this breakpoint site. /// /// \return /// The number of elements copied into out_collection. - size_t CopyOwnersList(BreakpointLocationCollection &out_collection); + size_t CopyConstituentsList(BreakpointLocationCollection &out_collection); - /// Check whether the owners of this breakpoint site have any thread + /// Check whether the constituents of this breakpoint site have any thread /// specifiers, and if yes, is \a thread contained in any of these /// specifiers. /// @@ -151,7 +156,7 @@ public: bool ValidForThisThread(Thread &thread); /// Print a description of this breakpoint site to the stream \a s. - /// GetDescription tells you about the breakpoint site's owners. Use + /// GetDescription tells you about the breakpoint site's constituents. Use /// BreakpointSite::Dump(Stream *) to get information about the breakpoint /// site itself. /// @@ -203,9 +208,10 @@ private: void BumpHitCounts(); - /// The method removes the owner at \a break_loc_id from this breakpoint + /// The method removes the constituent at \a break_loc_id from this breakpoint /// list. - size_t RemoveOwner(lldb::break_id_t break_id, lldb::break_id_t break_loc_id); + size_t RemoveConstituent(lldb::break_id_t break_id, + lldb::break_id_t break_loc_id); BreakpointSite::Type m_type; ///< The type of this breakpoint site. uint8_t m_saved_opcode[8]; ///< The saved opcode bytes if this breakpoint site @@ -215,20 +221,20 @@ private: bool m_enabled; ///< Boolean indicating if this breakpoint site enabled or not. - // Consider adding an optimization where if there is only one owner, we don't - // store a list. The usual case will be only one owner... - BreakpointLocationCollection m_owners; ///< This has the BreakpointLocations - ///that share this breakpoint site. - std::recursive_mutex - m_owners_mutex; ///< This mutex protects the owners collection. + // Consider adding an optimization where if there is only one constituent, we + // don't store a list. The usual case will be only one constituent... + BreakpointLocationCollection + m_constituents; ///< This has the BreakpointLocations + /// that share this breakpoint site. + std::recursive_mutex m_constituents_mutex; ///< This mutex protects the + ///< constituents collection. static lldb::break_id_t GetNextID(); // Only the Process can create breakpoint sites in // Process::CreateBreakpointSite (lldb::BreakpointLocationSP &, bool). - BreakpointSite(BreakpointSiteList *list, - const lldb::BreakpointLocationSP &owner, lldb::addr_t m_addr, - bool use_hardware); + BreakpointSite(const lldb::BreakpointLocationSP &constituent, + lldb::addr_t m_addr, bool use_hardware); BreakpointSite(const BreakpointSite &) = delete; const BreakpointSite &operator=(const BreakpointSite &) = delete; diff --git a/lldb/include/lldb/Breakpoint/BreakpointSiteList.h b/lldb/include/lldb/Breakpoint/BreakpointSiteList.h deleted file mode 100644 index 98091bbaeb05..000000000000 --- a/lldb/include/lldb/Breakpoint/BreakpointSiteList.h +++ /dev/null @@ -1,173 +0,0 @@ -//===-- BreakpointSiteList.h ------------------------------------*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifndef LLDB_BREAKPOINT_BREAKPOINTSITELIST_H -#define LLDB_BREAKPOINT_BREAKPOINTSITELIST_H - -#include -#include -#include - -#include "lldb/Breakpoint/BreakpointSite.h" - -namespace lldb_private { - -/// \class BreakpointSiteList BreakpointSiteList.h -/// "lldb/Breakpoint/BreakpointSiteList.h" Class that manages lists of -/// BreakpointSite shared pointers. -class BreakpointSiteList { - // At present Process directly accesses the map of BreakpointSites so it can - // do quick lookups into the map (using GetMap). - // FIXME: Find a better interface for this. - friend class Process; - -public: - /// Default constructor makes an empty list. - BreakpointSiteList(); - - /// Destructor, currently does nothing. - ~BreakpointSiteList(); - - /// Add a BreakpointSite to the list. - /// - /// \param[in] bp_site_sp - /// A shared pointer to a breakpoint site being added to the list. - /// - /// \return - /// The ID of the BreakpointSite in the list. - lldb::break_id_t Add(const lldb::BreakpointSiteSP &bp_site_sp); - - /// Standard Dump routine, doesn't do anything at present. \param[in] s - /// Stream into which to dump the description. - void Dump(Stream *s) const; - - /// Returns a shared pointer to the breakpoint site at address \a addr. - /// - /// \param[in] addr - /// The address to look for. - /// - /// \result - /// A shared pointer to the breakpoint site. May contain a NULL - /// pointer if no breakpoint site exists with a matching address. - lldb::BreakpointSiteSP FindByAddress(lldb::addr_t addr); - - /// Returns a shared pointer to the breakpoint site with id \a breakID. - /// - /// \param[in] breakID - /// The breakpoint site ID to seek for. - /// - /// \result - /// A shared pointer to the breakpoint site. May contain a NULL pointer if - /// the - /// breakpoint doesn't exist. - lldb::BreakpointSiteSP FindByID(lldb::break_id_t breakID); - - /// Returns a shared pointer to the breakpoint site with id \a breakID - - /// const version. - /// - /// \param[in] breakID - /// The breakpoint site ID to seek for. - /// - /// \result - /// A shared pointer to the breakpoint site. May contain a NULL pointer if - /// the - /// breakpoint doesn't exist. - const lldb::BreakpointSiteSP FindByID(lldb::break_id_t breakID) const; - - /// Returns the breakpoint site id to the breakpoint site at address \a - /// addr. - /// - /// \param[in] addr - /// The address to match. - /// - /// \result - /// The ID of the breakpoint site, or LLDB_INVALID_BREAK_ID. - lldb::break_id_t FindIDByAddress(lldb::addr_t addr); - - /// Returns whether the breakpoint site \a bp_site_id has \a bp_id - // as one of its owners. - /// - /// \param[in] bp_site_id - /// The breakpoint site id to query. - /// - /// \param[in] bp_id - /// The breakpoint id to look for in \a bp_site_id. - /// - /// \result - /// True if \a bp_site_id exists in the site list AND \a bp_id is one of the - /// owners of that site. - bool BreakpointSiteContainsBreakpoint(lldb::break_id_t bp_site_id, - lldb::break_id_t bp_id); - - void ForEach(std::function const &callback); - - /// Removes the breakpoint site given by \b breakID from this list. - /// - /// \param[in] breakID - /// The breakpoint site index to remove. - /// - /// \result - /// \b true if the breakpoint site \a breakID was in the list. - bool Remove(lldb::break_id_t breakID); - - /// Removes the breakpoint site at address \a addr from this list. - /// - /// \param[in] addr - /// The address from which to remove a breakpoint site. - /// - /// \result - /// \b true if \a addr had a breakpoint site to remove from the list. - bool RemoveByAddress(lldb::addr_t addr); - - bool FindInRange(lldb::addr_t lower_bound, lldb::addr_t upper_bound, - BreakpointSiteList &bp_site_list) const; - - typedef void (*BreakpointSiteSPMapFunc)(lldb::BreakpointSiteSP &bp, - void *baton); - - /// Enquires of the breakpoint site on in this list with ID \a breakID - /// whether we should stop for the breakpoint or not. - /// - /// \param[in] context - /// This contains the information about this stop. - /// - /// \param[in] breakID - /// This break ID that we hit. - /// - /// \return - /// \b true if we should stop, \b false otherwise. - bool ShouldStop(StoppointCallbackContext *context, lldb::break_id_t breakID); - - /// Returns the number of elements in the list. - /// - /// \result - /// The number of elements. - size_t GetSize() const { - std::lock_guard guard(m_mutex); - return m_bp_site_list.size(); - } - - bool IsEmpty() const { - std::lock_guard guard(m_mutex); - return m_bp_site_list.empty(); - } - -protected: - typedef std::map collection; - - collection::iterator GetIDIterator(lldb::break_id_t breakID); - - collection::const_iterator GetIDConstIterator(lldb::break_id_t breakID) const; - - mutable std::recursive_mutex m_mutex; - collection m_bp_site_list; // The breakpoint site list. -}; - -} // namespace lldb_private - -#endif // LLDB_BREAKPOINT_BREAKPOINTSITELIST_H diff --git a/lldb/include/lldb/Breakpoint/StopPointSiteList.h b/lldb/include/lldb/Breakpoint/StopPointSiteList.h new file mode 100644 index 000000000000..9ff151fd01b6 --- /dev/null +++ b/lldb/include/lldb/Breakpoint/StopPointSiteList.h @@ -0,0 +1,310 @@ +//===-- StopPointSiteList.h -------------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLDB_BREAKPOINT_STOPPOINTSITELIST_H +#define LLDB_BREAKPOINT_STOPPOINTSITELIST_H + +#include +#include +#include + +#include +#include +#include + +namespace lldb_private { + +template class StopPointSiteList { + // At present Process directly accesses the map of StopPointSites so it can + // do quick lookups into the map (using GetMap). + // FIXME: Find a better interface for this. + friend class Process; + +public: + using StopPointSiteSP = std::shared_ptr; + + /// Add a site to the list. + /// + /// \param[in] site_sp + /// A shared pointer to a site being added to the list. + /// + /// \return + /// The ID of the site in the list. + typename StopPointSite::SiteID Add(const StopPointSiteSP &site_sp) { + lldb::addr_t site_load_addr = site_sp->GetLoadAddress(); + std::lock_guard guard(m_mutex); + typename collection::iterator iter = m_site_list.find(site_load_addr); + + // Add site to the list. However, if the element already exists in + // the list, then we don't add it, and return InvalidSiteID. + if (iter == m_site_list.end()) { + m_site_list[site_load_addr] = site_sp; + return site_sp->GetID(); + } else { + return UINT32_MAX; + } + } + + /// Standard Dump routine, doesn't do anything at present. + /// \param[in] s + /// Stream into which to dump the description. + void Dump(Stream *s) const { + s->Printf("%p: ", static_cast(this)); + s->Printf("StopPointSiteList with %u ConstituentSites:\n", + (uint32_t)m_site_list.size()); + s->IndentMore(); + typename collection::const_iterator pos; + typename collection::const_iterator end = m_site_list.end(); + for (pos = m_site_list.begin(); pos != end; ++pos) + pos->second->Dump(s); + s->IndentLess(); + } + + /// Returns a shared pointer to the site at address \a addr. + /// + /// \param[in] addr + /// The address to look for. + /// + /// \result + /// A shared pointer to the site. Nullptr if no site contains + /// the address. + StopPointSiteSP FindByAddress(lldb::addr_t addr) { + StopPointSiteSP found_sp; + std::lock_guard guard(m_mutex); + typename collection::iterator iter = m_site_list.find(addr); + if (iter != m_site_list.end()) + found_sp = iter->second; + return found_sp; + } + + /// Returns a shared pointer to the site with id \a site_id. + /// + /// \param[in] site_id + /// The site ID to seek for. + /// + /// \result + /// A shared pointer to the site. Nullptr if no matching site. + StopPointSiteSP FindByID(typename StopPointSite::SiteID site_id) { + std::lock_guard guard(m_mutex); + StopPointSiteSP stop_sp; + typename collection::iterator pos = GetIDIterator(site_id); + if (pos != m_site_list.end()) + stop_sp = pos->second; + + return stop_sp; + } + + /// Returns a shared pointer to the site with id \a site_id - + /// const version. + /// + /// \param[in] site_id + /// The site ID to seek for. + /// + /// \result + /// A shared pointer to the site. Nullptr if no matching site. + const StopPointSiteSP FindByID(typename StopPointSite::SiteID site_id) const { + std::lock_guard guard(m_mutex); + StopPointSiteSP stop_sp; + typename collection::const_iterator pos = GetIDConstIterator(site_id); + if (pos != m_site_list.end()) + stop_sp = pos->second; + + return stop_sp; + } + + /// Returns the site id to the site at address \a addr. + /// + /// \param[in] addr + /// The address to match. + /// + /// \result + /// The ID of the site, or LLDB_INVALID_SITE_ID. + typename StopPointSite::SiteID FindIDByAddress(lldb::addr_t addr) { + if (StopPointSiteSP site = FindByAddress(addr)) + return site->GetID(); + return UINT32_MAX; + } + + /// Returns whether the BreakpointSite \a site_id has a BreakpointLocation + /// that is part of Breakpoint \a bp_id. + /// + /// NB this is only defined when StopPointSiteList is specialized for + /// BreakpointSite's. + /// + /// \param[in] site_id + /// The site id to query. + /// + /// \param[in] bp_id + /// The breakpoint id to look for in \a site_id's BreakpointLocations. + /// + /// \result + /// True if \a site_id exists in the site list AND \a bp_id + /// is the breakpoint for one of the BreakpointLocations. + bool StopPointSiteContainsBreakpoint(typename StopPointSite::SiteID, + lldb::break_id_t bp_id); + + void ForEach(std::function const &callback) { + std::lock_guard guard(m_mutex); + for (auto pair : m_site_list) + callback(pair.second.get()); + } + + /// Removes the site given by \a site_id from this list. + /// + /// \param[in] site_id + /// The site ID to remove. + /// + /// \result + /// \b true if the site \a site_id was in the list. + bool Remove(typename StopPointSite::SiteID site_id) { + std::lock_guard guard(m_mutex); + typename collection::iterator pos = GetIDIterator(site_id); // Predicate + if (pos != m_site_list.end()) { + m_site_list.erase(pos); + return true; + } + return false; + } + + /// Removes the site at address \a addr from this list. + /// + /// \param[in] addr + /// The address from which to remove a site. + /// + /// \result + /// \b true if \a addr had a site to remove from the list. + bool RemoveByAddress(lldb::addr_t addr) { + std::lock_guard guard(m_mutex); + typename collection::iterator pos = m_site_list.find(addr); + if (pos != m_site_list.end()) { + m_site_list.erase(pos); + return true; + } + return false; + } + + bool FindInRange(lldb::addr_t lower_bound, lldb::addr_t upper_bound, + StopPointSiteList &bp_site_list) const { + if (lower_bound > upper_bound) + return false; + + std::lock_guard guard(m_mutex); + typename collection::const_iterator lower, upper, pos; + lower = m_site_list.lower_bound(lower_bound); + if (lower == m_site_list.end() || (*lower).first >= upper_bound) + return false; + + // This is one tricky bit. The site might overlap the bottom end of + // the range. So we grab the site prior to the lower bound, and check + // that that + its byte size isn't in our range. + if (lower != m_site_list.begin()) { + typename collection::const_iterator prev_pos = lower; + prev_pos--; + const StopPointSiteSP &prev_site = (*prev_pos).second; + if (prev_site->GetLoadAddress() + prev_site->GetByteSize() > lower_bound) + bp_site_list.Add(prev_site); + } + + upper = m_site_list.upper_bound(upper_bound); + + for (pos = lower; pos != upper; pos++) + bp_site_list.Add((*pos).second); + return true; + } + + typedef void (*StopPointSiteSPMapFunc)(StopPointSite &site, void *baton); + + /// Enquires of the site on in this list with ID \a site_id + /// whether we should stop for the constituent or not. + /// + /// \param[in] context + /// This contains the information about this stop. + /// + /// \param[in] site_id + /// This site ID that we hit. + /// + /// \return + /// \b true if we should stop, \b false otherwise. + bool ShouldStop(StoppointCallbackContext *context, + typename StopPointSite::SiteID site_id) { + if (StopPointSiteSP site_sp = FindByID(site_id)) { + // Let the site decide if it should stop here (could not have + // reached it's target hit count yet, or it could have a callback that + // decided it shouldn't stop (shared library loads/unloads). + return site_sp->ShouldStop(context); + } + // We should stop here since this site isn't valid anymore or it + // doesn't exist. + return true; + } + + /// Returns the number of elements in the list. + /// + /// \result + /// The number of elements. + size_t GetSize() const { + std::lock_guard guard(m_mutex); + return m_site_list.size(); + } + + bool IsEmpty() const { + std::lock_guard guard(m_mutex); + return m_site_list.empty(); + } + + std::vector Sites() { + std::vector sites; + std::lock_guard guard(m_mutex); + typename collection::iterator iter = m_site_list.begin(); + while (iter != m_site_list.end()) { + sites.push_back(iter->second); + ++iter; + } + + return sites; + } + + void Clear() { + std::lock_guard guard(m_mutex); + m_site_list.clear(); + } + +protected: + typedef std::map collection; + + typename collection::iterator + GetIDIterator(typename StopPointSite::SiteID site_id) { + std::lock_guard guard(m_mutex); + auto id_matches = + [site_id](const std::pair s) { + return site_id == s.second->GetID(); + }; + return std::find_if(m_site_list.begin(), + m_site_list.end(), // Search full range + id_matches); + } + + typename collection::const_iterator + GetIDConstIterator(typename StopPointSite::SiteID site_id) const { + std::lock_guard guard(m_mutex); + auto id_matches = + [site_id](const std::pair s) { + return site_id == s.second->GetID(); + }; + return std::find_if(m_site_list.begin(), + m_site_list.end(), // Search full range + id_matches); + } + + mutable std::recursive_mutex m_mutex; + collection m_site_list; // The site list. +}; + +} // namespace lldb_private + +#endif // LLDB_BREAKPOINT_STOPPOINTSITELIST_H diff --git a/lldb/include/lldb/Breakpoint/Watchpoint.h b/lldb/include/lldb/Breakpoint/Watchpoint.h index c86d66663c7f..851162af24c7 100644 --- a/lldb/include/lldb/Breakpoint/Watchpoint.h +++ b/lldb/include/lldb/Breakpoint/Watchpoint.h @@ -126,7 +126,7 @@ public: void GetDescription(Stream *s, lldb::DescriptionLevel level); void Dump(Stream *s) const override; - void DumpSnapshots(Stream *s, const char *prefix = nullptr) const; + bool DumpSnapshots(Stream *s, const char *prefix = nullptr) const; void DumpWithLevel(Stream *s, lldb::DescriptionLevel description_level) const; Target &GetTarget() { return m_target; } const Status &GetError() { return m_error; } diff --git a/lldb/include/lldb/Breakpoint/WatchpointResource.h b/lldb/include/lldb/Breakpoint/WatchpointResource.h new file mode 100644 index 000000000000..e83ba0bbe8c6 --- /dev/null +++ b/lldb/include/lldb/Breakpoint/WatchpointResource.h @@ -0,0 +1,169 @@ +//===-- WatchpointResource.h ------------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLDB_BREAKPOINT_WATCHPOINTRESOURCE_H +#define LLDB_BREAKPOINT_WATCHPOINTRESOURCE_H + +#include "lldb/Utility/Iterable.h" +#include "lldb/lldb-public.h" + +#include +#include + +namespace lldb_private { + +class WatchpointResource + : public std::enable_shared_from_this { + +public: + WatchpointResource(lldb::addr_t addr, size_t size, bool read, bool write); + + ~WatchpointResource(); + + typedef lldb::wp_resource_id_t SiteID; + typedef lldb::watch_id_t ConstituentID; + + lldb::addr_t GetLoadAddress() const; + + size_t GetByteSize() const; + + bool WatchpointResourceRead() const; + + bool WatchpointResourceWrite() const; + + void SetType(bool read, bool write); + + typedef std::vector WatchpointCollection; + typedef LockingAdaptedIterable + WatchpointIterable; + + /// Iterate over the watchpoint constituents for this resource + /// + /// \return + /// An Iterable object which can be used to loop over the watchpoints + /// that are constituents of this resource. + WatchpointIterable Constituents() { + return WatchpointIterable(m_constituents, m_constituents_mutex); + } + + /// Enquires of the atchpoints that produced this watchpoint resource + /// whether we should stop at this location. + /// + /// \param[in] context + /// This contains the information about this stop. + /// + /// \return + /// \b true if we should stop, \b false otherwise. + bool ShouldStop(StoppointCallbackContext *context); + + /// Standard Dump method + void Dump(Stream *s) const; + + /// The "Constituents" are the watchpoints that share this resource. + /// The method adds the \a constituent to this resource's constituent list. + /// + /// \param[in] constituent + /// \a constituent is the Wachpoint to add. + void AddConstituent(const lldb::WatchpointSP &constituent); + + /// The method removes the constituent at \a constituent from this watchpoint + /// resource. + void RemoveConstituent(lldb::WatchpointSP &constituent); + + /// This method returns the number of Watchpoints currently using + /// watchpoint resource. + /// + /// \return + /// The number of constituents. + size_t GetNumberOfConstituents(); + + /// This method returns the Watchpoint at index \a index using this + /// Resource. The constituents are listed ordinally from 0 to + /// GetNumberOfConstituents() - 1 so you can use this method to iterate over + /// the constituents. + /// + /// \param[in] idx + /// The index in the list of constituents for which you wish the + /// constituent location. + /// + /// \return + /// The Watchpoint at that index. + lldb::WatchpointSP GetConstituentAtIndex(size_t idx); + + /// Check if the constituents includes a watchpoint. + /// + /// \param[in] wp_sp + /// The WatchpointSP to search for. + /// + /// \result + /// true if this resource's constituents includes the watchpoint. + bool ConstituentsContains(const lldb::WatchpointSP &wp_sp); + + /// Check if the constituents includes a watchpoint. + /// + /// \param[in] wp + /// The Watchpoint to search for. + /// + /// \result + /// true if this resource's constituents includes the watchpoint. + bool ConstituentsContains(const lldb_private::Watchpoint *wp); + + /// This method copies the watchpoint resource's constituents into a new + /// collection. It does this while the constituents mutex is locked. + /// + /// \return + /// A copy of the Watchpoints which own this resource. + WatchpointCollection CopyConstituentsList(); + + // The ID of the WatchpointResource is set by the WatchpointResourceList + // when the Resource has been set in the inferior and is being added + // to the List, in an attempt to match the hardware watchpoint register + // ordering. If a Process can correctly identify the hardware watchpoint + // register index when it has created the Resource, it may initialize it + // before it is inserted in the WatchpointResourceList. + void SetID(lldb::wp_resource_id_t); + + lldb::wp_resource_id_t GetID() const; + + bool Contains(lldb::addr_t addr); + +protected: + // The StopInfoWatchpoint knows when it is processing a hit for a thread for + // a site, so let it be the one to manage setting the location hit count once + // and only once. + friend class StopInfoWatchpoint; + + void BumpHitCounts(); + +private: + static lldb::wp_resource_id_t GetNextID(); + + lldb::wp_resource_id_t m_id; + + // Start address & size aligned & expanded to be a valid watchpoint + // memory granule on this target. + lldb::addr_t m_addr; + size_t m_size; + + bool m_watch_read; + bool m_watch_write; + + /// The Watchpoints which own this resource. + WatchpointCollection m_constituents; + + /// This mutex protects the constituents collection. + std::mutex m_constituents_mutex; + + WatchpointResource(const WatchpointResource &) = delete; + const WatchpointResource &operator=(const WatchpointResource &) = delete; +}; + +} // namespace lldb_private + +#endif // LLDB_BREAKPOINT_WATCHPOINTRESOURCE_H diff --git a/lldb/include/lldb/Breakpoint/WatchpointResourceList.h b/lldb/include/lldb/Breakpoint/WatchpointResourceList.h new file mode 100644 index 000000000000..0e6c5fab8778 --- /dev/null +++ b/lldb/include/lldb/Breakpoint/WatchpointResourceList.h @@ -0,0 +1,145 @@ +//===-- WatchpointResourceList.h --------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLDB_BREAKPOINT_WATCHPOINTRESOURCELIST_H +#define LLDB_BREAKPOINT_WATCHPOINTRESOURCELIST_H + +#include "lldb/Utility/Iterable.h" +#include "lldb/lldb-private.h" +#include "lldb/lldb-public.h" + +#include +#include + +namespace lldb_private { + +class WatchpointResourceList { + +public: + WatchpointResourceList(); + + ~WatchpointResourceList(); + + /// Add a WatchpointResource to the list. + /// + /// \param[in] wp_res_sp + /// A shared pointer to a breakpoint site being added to the list. + /// + /// \return + /// The ID of the BreakpointSite in the list. + lldb::wp_resource_id_t Add(const lldb::WatchpointResourceSP &wp_res_sp); + + /// Removes the watchpoint resource given by \a id from this list. + /// + /// \param[in] id + /// The watchpoint resource to remove. + /// + /// \result + /// \b true if the watchpoint resource \a id was in the list. + bool Remove(lldb::wp_resource_id_t id); + + /// Removes the watchpoint resource containing address \a addr from this list. + /// + /// \param[in] addr + /// The address from which to remove a watchpoint resource. + /// + /// \result + /// \b true if \a addr had a watchpoint resource to remove from the list. + bool RemoveByAddress(lldb::addr_t addr); + + /// Returns a shared pointer to the watchpoint resource which contains + /// \a addr. + /// + /// \param[in] addr + /// The address to look for. + /// + /// \result + /// A shared pointer to the watchpoint resource. May contain a nullptr + /// pointer if no watchpoint site exists with a matching address. + lldb::WatchpointResourceSP FindByAddress(lldb::addr_t addr); + + /// Returns a shared pointer to the watchpoint resource which is owned + /// by \a wp_sp. + /// + /// \param[in] wp_sp + /// The WatchpointSP to look for. + /// + /// \result + /// A shared pointer to the watchpoint resource. May contain a nullptr + /// pointer if no watchpoint site exists + lldb::WatchpointResourceSP FindByWatchpointSP(lldb::WatchpointSP &wp_sp); + + /// Returns a shared pointer to the watchpoint resource which is owned + /// by \a wp. + /// + /// \param[in] wp + /// The Watchpoint to look for. + /// + /// \result + /// A shared pointer to the watchpoint resource. May contain a nullptr + /// pointer if no watchpoint site exists + lldb::WatchpointResourceSP + FindByWatchpoint(const lldb_private::Watchpoint *wp); + + /// Returns a shared pointer to the watchpoint resource which has hardware + /// index \a id. Some Process plugins may not have access to the actual + /// hardware watchpoint register number used for a WatchpointResource, so + /// the wp_resource_id_t may not be correctly tracking the target's wp + /// register target. + /// + /// \param[in] id + /// The hardware resource index to search for. + /// + /// \result + /// A shared pointer to the watchpoint resource. May contain a nullptr + /// pointer if no watchpoint site exists with a matching id. + lldb::WatchpointResourceSP FindByID(lldb::wp_resource_id_t id); + + /// + /// Get the number of WatchpointResources that are available. + /// + /// \return + /// The number of WatchpointResources that are stored in the + /// WatchpointResourceList. + uint32_t GetSize(); + + /// Get the WatchpointResource at a given index. + /// + /// \param [in] idx + /// The index of the resource. + /// \return + /// The WatchpointResource at that index number. + lldb::WatchpointResourceSP GetResourceAtIndex(uint32_t idx); + + typedef std::vector collection; + typedef LockingAdaptedIterable + WatchpointResourceIterable; + + /// Iterate over the list of WatchpointResources. + /// + /// \return + /// An Iterable object which can be used to loop over the resources + /// that exist. + WatchpointResourceIterable Resources() { + return WatchpointResourceIterable(m_resources, m_mutex); + } + + /// Clear out the list of resources from the WatchpointResourceList + void Clear(); + + std::mutex &GetMutex(); + +private: + collection m_resources; + std::mutex m_mutex; +}; + +} // namespace lldb_private + +#endif // LLDB_BREAKPOINT_WATCHPOINTRESOURCELIST_H diff --git a/lldb/include/lldb/Interpreter/OptionGroupWatchpoint.h b/lldb/include/lldb/Interpreter/OptionGroupWatchpoint.h index f009fa145f30..527a2612b189 100644 --- a/lldb/include/lldb/Interpreter/OptionGroupWatchpoint.h +++ b/lldb/include/lldb/Interpreter/OptionGroupWatchpoint.h @@ -9,6 +9,7 @@ #ifndef LLDB_INTERPRETER_OPTIONGROUPWATCHPOINT_H #define LLDB_INTERPRETER_OPTIONGROUPWATCHPOINT_H +#include "lldb/Interpreter/OptionValueUInt64.h" #include "lldb/Interpreter/Options.h" namespace lldb_private { @@ -21,8 +22,6 @@ public: ~OptionGroupWatchpoint() override = default; - static bool IsWatchSizeSupported(uint32_t watch_size); - llvm::ArrayRef GetDefinitions() override; Status SetOptionValue(uint32_t option_idx, llvm::StringRef option_value, @@ -43,7 +42,7 @@ public: }; WatchType watch_type; - uint32_t watch_size; + OptionValueUInt64 watch_size; bool watch_type_specified; lldb::LanguageType language_type; diff --git a/lldb/include/lldb/Target/Process.h b/lldb/include/lldb/Target/Process.h index 08e3c60f7c32..4646e3070cf1 100644 --- a/lldb/include/lldb/Target/Process.h +++ b/lldb/include/lldb/Target/Process.h @@ -22,7 +22,9 @@ #include #include -#include "lldb/Breakpoint/BreakpointSiteList.h" +#include "lldb/Breakpoint/BreakpointSite.h" +#include "lldb/Breakpoint/StopPointSiteList.h" +#include "lldb/Breakpoint/WatchpointResource.h" #include "lldb/Core/LoadedModuleInfoList.h" #include "lldb/Core/PluginInterface.h" #include "lldb/Core/SourceManager.h" @@ -2139,9 +2141,10 @@ public: // doesn't work for a specific process plug-in. virtual Status DisableSoftwareBreakpoint(BreakpointSite *bp_site); - BreakpointSiteList &GetBreakpointSiteList(); + StopPointSiteList &GetBreakpointSiteList(); - const BreakpointSiteList &GetBreakpointSiteList() const; + const StopPointSiteList & + GetBreakpointSiteList() const; void DisableAllBreakpointSites(); @@ -2154,16 +2157,17 @@ public: Status EnableBreakpointSiteByID(lldb::user_id_t break_id); - // BreakpointLocations use RemoveOwnerFromBreakpointSite to remove themselves - // from the owner's list of this breakpoint sites. - void RemoveOwnerFromBreakpointSite(lldb::user_id_t owner_id, - lldb::user_id_t owner_loc_id, - lldb::BreakpointSiteSP &bp_site_sp); + // BreakpointLocations use RemoveConstituentFromBreakpointSite to remove + // themselves from the constituent's list of this breakpoint sites. + void RemoveConstituentFromBreakpointSite(lldb::user_id_t site_id, + lldb::user_id_t constituent_id, + lldb::BreakpointSiteSP &bp_site_sp); // Process Watchpoints (optional) - virtual Status EnableWatchpoint(Watchpoint *wp, bool notify = true); + virtual Status EnableWatchpoint(lldb::WatchpointSP wp_sp, bool notify = true); - virtual Status DisableWatchpoint(Watchpoint *wp, bool notify = true); + virtual Status DisableWatchpoint(lldb::WatchpointSP wp_sp, + bool notify = true); // Thread Queries @@ -2182,6 +2186,11 @@ public: ThreadList &GetThreadList() { return m_thread_list; } + StopPointSiteList & + GetWatchpointResourceList() { + return m_watchpoint_resource_list; + } + // When ExtendedBacktraces are requested, the HistoryThreads that are created // need an owner -- they're saved here in the Process. The threads in this // list are not iterated over - driver programs need to request the extended @@ -3009,20 +3018,24 @@ protected: /// threads in m_thread_list, as well as /// threads we knew existed, but haven't /// determined that they have died yet. - ThreadList m_extended_thread_list; ///< Owner for extended threads that may be - ///generated, cleared on natural stops + ThreadList + m_extended_thread_list; ///< Constituent for extended threads that may be + /// generated, cleared on natural stops uint32_t m_extended_thread_stop_id; ///< The natural stop id when ///extended_thread_list was last updated QueueList m_queue_list; ///< The list of libdispatch queues at a given stop point uint32_t m_queue_list_stop_id; ///< The natural stop id when queue list was ///last fetched + StopPointSiteList + m_watchpoint_resource_list; ///< Watchpoint resources currently in use. std::vector m_notifications; ///< The list of notifications ///that this process can deliver. std::vector m_image_tokens; - BreakpointSiteList m_breakpoint_site_list; ///< This is the list of breakpoint - ///locations we intend to insert in - ///the target. + StopPointSiteList + m_breakpoint_site_list; ///< This is the list of breakpoint + /// locations we intend to insert in + /// the target. lldb::DynamicLoaderUP m_dyld_up; lldb::JITLoaderListUP m_jit_loaders_up; lldb::DynamicCheckerFunctionsUP m_dynamic_checkers_up; ///< The functions used diff --git a/lldb/include/lldb/lldb-defines.h b/lldb/include/lldb/lldb-defines.h index 6950a4f3a496..469be92eabec 100644 --- a/lldb/include/lldb/lldb-defines.h +++ b/lldb/include/lldb/lldb-defines.h @@ -49,6 +49,9 @@ ((type & LLDB_WATCH_TYPE_READ) || (type & LLDB_WATCH_TYPE_WRITE) || \ (type & LLDB_WATCH_TYPE_MODIFY)) +// StopPointSites +#define LLDB_INVALID_SITE_ID UINT32_MAX + // Generic Register Numbers #define LLDB_REGNUM_GENERIC_PC 0 // Program Counter #define LLDB_REGNUM_GENERIC_SP 1 // Stack Pointer @@ -92,6 +95,7 @@ #define LLDB_INVALID_COLUMN_NUMBER 0 #define LLDB_INVALID_QUEUE_ID 0 #define LLDB_INVALID_CPU_ID UINT32_MAX +#define LLDB_INVALID_WATCHPOINT_RESOURCE_ID UINT32_MAX /// CPU Type definitions #define LLDB_ARCH_DEFAULT "systemArch" diff --git a/lldb/include/lldb/lldb-forward.h b/lldb/include/lldb/lldb-forward.h index d38985f5c1f9..068fce4976ed 100644 --- a/lldb/include/lldb/lldb-forward.h +++ b/lldb/include/lldb/lldb-forward.h @@ -39,7 +39,6 @@ class BreakpointOptions; class BreakpointPrecondition; class BreakpointResolver; class BreakpointSite; -class BreakpointSiteList; class BroadcastEventSpec; class Broadcaster; class BroadcasterManager; @@ -289,6 +288,8 @@ class VariableList; class Watchpoint; class WatchpointList; class WatchpointOptions; +class WatchpointResource; +class WatchpointResourceCollection; class WatchpointSetOptions; struct CompilerContext; struct LineEntry; @@ -469,6 +470,7 @@ typedef std::shared_ptr VariableSP; typedef std::shared_ptr VariableListSP; typedef std::shared_ptr ValueObjectListSP; typedef std::shared_ptr WatchpointSP; +typedef std::shared_ptr WatchpointResourceSP; } // namespace lldb diff --git a/lldb/include/lldb/lldb-types.h b/lldb/include/lldb/lldb-types.h index d9c2a21c2daa..d60686e33142 100644 --- a/lldb/include/lldb/lldb-types.h +++ b/lldb/include/lldb/lldb-types.h @@ -83,6 +83,7 @@ typedef uint64_t tid_t; typedef uint64_t offset_t; typedef int32_t break_id_t; typedef int32_t watch_id_t; +typedef uint32_t wp_resource_id_t; typedef void *opaque_compiler_type_t; typedef uint64_t queue_id_t; typedef uint32_t cpu_id_t; // CPU core id diff --git a/lldb/source/API/SBThread.cpp b/lldb/source/API/SBThread.cpp index 18c086bb04c6..fa4c80e59d97 100644 --- a/lldb/source/API/SBThread.cpp +++ b/lldb/source/API/SBThread.cpp @@ -181,7 +181,7 @@ size_t SBThread::GetStopReasonDataCount() { exe_ctx.GetProcessPtr()->GetBreakpointSiteList().FindByID( site_id)); if (bp_site_sp) - return bp_site_sp->GetNumberOfOwners() * 2; + return bp_site_sp->GetNumberOfConstituents() * 2; else return 0; // Breakpoint must have cleared itself... } break; @@ -241,7 +241,7 @@ uint64_t SBThread::GetStopReasonDataAtIndex(uint32_t idx) { if (bp_site_sp) { uint32_t bp_index = idx / 2; BreakpointLocationSP bp_loc_sp( - bp_site_sp->GetOwnerAtIndex(bp_index)); + bp_site_sp->GetConstituentAtIndex(bp_index)); if (bp_loc_sp) { if (idx & 1) { // Odd idx, return the breakpoint location ID diff --git a/lldb/source/API/SBWatchpoint.cpp b/lldb/source/API/SBWatchpoint.cpp index 8e60e6d5bb73..9664bbe61860 100644 --- a/lldb/source/API/SBWatchpoint.cpp +++ b/lldb/source/API/SBWatchpoint.cpp @@ -142,9 +142,9 @@ void SBWatchpoint::SetEnabled(bool enabled) { const bool notify = true; if (process_sp) { if (enabled) - process_sp->EnableWatchpoint(watchpoint_sp.get(), notify); + process_sp->EnableWatchpoint(watchpoint_sp, notify); else - process_sp->DisableWatchpoint(watchpoint_sp.get(), notify); + process_sp->DisableWatchpoint(watchpoint_sp, notify); } else { watchpoint_sp->SetEnabled(enabled, notify); } diff --git a/lldb/source/Breakpoint/BreakpointLocation.cpp b/lldb/source/Breakpoint/BreakpointLocation.cpp index 931e1ad4b2d9..99f94d04bb31 100644 --- a/lldb/source/Breakpoint/BreakpointLocation.cpp +++ b/lldb/source/Breakpoint/BreakpointLocation.cpp @@ -473,10 +473,10 @@ bool BreakpointLocation::ClearBreakpointSite() { // physical implementation of the breakpoint as well if there are no more // owners. Otherwise just remove this owner. if (process_sp) - process_sp->RemoveOwnerFromBreakpointSite(GetBreakpoint().GetID(), - GetID(), m_bp_site_sp); + process_sp->RemoveConstituentFromBreakpointSite(GetBreakpoint().GetID(), + GetID(), m_bp_site_sp); else - m_bp_site_sp->RemoveOwner(GetBreakpoint().GetID(), GetID()); + m_bp_site_sp->RemoveConstituent(GetBreakpoint().GetID(), GetID()); m_bp_site_sp.reset(); return true; diff --git a/lldb/source/Breakpoint/BreakpointSite.cpp b/lldb/source/Breakpoint/BreakpointSite.cpp index 5187bc560ba2..3ca93f908e30 100644 --- a/lldb/source/Breakpoint/BreakpointSite.cpp +++ b/lldb/source/Breakpoint/BreakpointSite.cpp @@ -12,14 +12,12 @@ #include "lldb/Breakpoint/Breakpoint.h" #include "lldb/Breakpoint/BreakpointLocation.h" -#include "lldb/Breakpoint/BreakpointSiteList.h" #include "lldb/Utility/Stream.h" using namespace lldb; using namespace lldb_private; -BreakpointSite::BreakpointSite(BreakpointSiteList *list, - const BreakpointLocationSP &owner, +BreakpointSite::BreakpointSite(const BreakpointLocationSP &constituent, lldb::addr_t addr, bool use_hardware) : StoppointSite(GetNextID(), addr, 0, use_hardware), m_type(eSoftware), // Process subclasses need to set this correctly using @@ -28,14 +26,14 @@ BreakpointSite::BreakpointSite(BreakpointSiteList *list, m_enabled(false) // Need to create it disabled, so the first enable turns // it on. { - m_owners.Add(owner); + m_constituents.Add(constituent); } BreakpointSite::~BreakpointSite() { BreakpointLocationSP bp_loc_sp; - const size_t owner_count = m_owners.GetSize(); - for (size_t i = 0; i < owner_count; i++) { - m_owners.GetByIndex(i)->ClearBreakpointSite(); + const size_t constituent_count = m_constituents.GetSize(); + for (size_t i = 0; i < constituent_count; i++) { + m_constituents.GetByIndex(i)->ClearBreakpointSite(); } } @@ -50,22 +48,22 @@ break_id_t BreakpointSite::GetNextID() { bool BreakpointSite::ShouldStop(StoppointCallbackContext *context) { m_hit_counter.Increment(); // ShouldStop can do a lot of work, and might even come back and hit - // this breakpoint site again. So don't hold the m_owners_mutex the whole - // while. Instead make a local copy of the collection and call ShouldStop on - // the copy. - BreakpointLocationCollection owners_copy; + // this breakpoint site again. So don't hold the m_constituents_mutex the + // whole while. Instead make a local copy of the collection and call + // ShouldStop on the copy. + BreakpointLocationCollection constituents_copy; { - std::lock_guard guard(m_owners_mutex); - owners_copy = m_owners; + std::lock_guard guard(m_constituents_mutex); + constituents_copy = m_constituents; } - return owners_copy.ShouldStop(context); + return constituents_copy.ShouldStop(context); } bool BreakpointSite::IsBreakpointAtThisSite(lldb::break_id_t bp_id) { - std::lock_guard guard(m_owners_mutex); - const size_t owner_count = m_owners.GetSize(); - for (size_t i = 0; i < owner_count; i++) { - if (m_owners.GetByIndex(i)->GetBreakpoint().GetID() == bp_id) + std::lock_guard guard(m_constituents_mutex); + const size_t constituent_count = m_constituents.GetSize(); + for (size_t i = 0; i < constituent_count; i++) { + if (m_constituents.GetByIndex(i)->GetBreakpoint().GetID() == bp_id) return true; } return false; @@ -82,14 +80,14 @@ void BreakpointSite::Dump(Stream *s) const { } void BreakpointSite::GetDescription(Stream *s, lldb::DescriptionLevel level) { - std::lock_guard guard(m_owners_mutex); + std::lock_guard guard(m_constituents_mutex); if (level != lldb::eDescriptionLevelBrief) s->Printf("breakpoint site: %d at 0x%8.8" PRIx64, GetID(), GetLoadAddress()); - m_owners.GetDescription(s, level); + m_constituents.GetDescription(s, level); } -bool BreakpointSite::IsInternal() const { return m_owners.IsInternal(); } +bool BreakpointSite::IsInternal() const { return m_constituents.IsInternal(); } uint8_t *BreakpointSite::GetTrapOpcodeBytes() { return &m_trap_opcode[0]; } @@ -122,36 +120,36 @@ bool BreakpointSite::IsEnabled() const { return m_enabled; } void BreakpointSite::SetEnabled(bool enabled) { m_enabled = enabled; } -void BreakpointSite::AddOwner(const BreakpointLocationSP &owner) { - std::lock_guard guard(m_owners_mutex); - m_owners.Add(owner); +void BreakpointSite::AddConstituent(const BreakpointLocationSP &constituent) { + std::lock_guard guard(m_constituents_mutex); + m_constituents.Add(constituent); } -size_t BreakpointSite::RemoveOwner(lldb::break_id_t break_id, - lldb::break_id_t break_loc_id) { - std::lock_guard guard(m_owners_mutex); - m_owners.Remove(break_id, break_loc_id); - return m_owners.GetSize(); +size_t BreakpointSite::RemoveConstituent(lldb::break_id_t break_id, + lldb::break_id_t break_loc_id) { + std::lock_guard guard(m_constituents_mutex); + m_constituents.Remove(break_id, break_loc_id); + return m_constituents.GetSize(); } -size_t BreakpointSite::GetNumberOfOwners() { - std::lock_guard guard(m_owners_mutex); - return m_owners.GetSize(); +size_t BreakpointSite::GetNumberOfConstituents() { + std::lock_guard guard(m_constituents_mutex); + return m_constituents.GetSize(); } -BreakpointLocationSP BreakpointSite::GetOwnerAtIndex(size_t index) { - std::lock_guard guard(m_owners_mutex); - return m_owners.GetByIndex(index); +BreakpointLocationSP BreakpointSite::GetConstituentAtIndex(size_t index) { + std::lock_guard guard(m_constituents_mutex); + return m_constituents.GetByIndex(index); } bool BreakpointSite::ValidForThisThread(Thread &thread) { - std::lock_guard guard(m_owners_mutex); - return m_owners.ValidForThisThread(thread); + std::lock_guard guard(m_constituents_mutex); + return m_constituents.ValidForThisThread(thread); } void BreakpointSite::BumpHitCounts() { - std::lock_guard guard(m_owners_mutex); - for (BreakpointLocationSP loc_sp : m_owners.BreakpointLocations()) { + std::lock_guard guard(m_constituents_mutex); + for (BreakpointLocationSP loc_sp : m_constituents.BreakpointLocations()) { loc_sp->BumpHitCount(); } } @@ -198,10 +196,10 @@ bool BreakpointSite::IntersectsRange(lldb::addr_t addr, size_t size, return true; } -size_t -BreakpointSite::CopyOwnersList(BreakpointLocationCollection &out_collection) { - std::lock_guard guard(m_owners_mutex); - for (BreakpointLocationSP loc_sp : m_owners.BreakpointLocations()) { +size_t BreakpointSite::CopyConstituentsList( + BreakpointLocationCollection &out_collection) { + std::lock_guard guard(m_constituents_mutex); + for (BreakpointLocationSP loc_sp : m_constituents.BreakpointLocations()) { out_collection.Add(loc_sp); } return out_collection.GetSize(); diff --git a/lldb/source/Breakpoint/BreakpointSiteList.cpp b/lldb/source/Breakpoint/BreakpointSiteList.cpp deleted file mode 100644 index ab15da82ea45..000000000000 --- a/lldb/source/Breakpoint/BreakpointSiteList.cpp +++ /dev/null @@ -1,193 +0,0 @@ -//===-- BreakpointSiteList.cpp --------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "lldb/Breakpoint/BreakpointSiteList.h" - -#include "lldb/Utility/Stream.h" -#include - -using namespace lldb; -using namespace lldb_private; - -BreakpointSiteList::BreakpointSiteList() = default; - -BreakpointSiteList::~BreakpointSiteList() = default; - -// Add breakpoint site to the list. However, if the element already exists in -// the list, then we don't add it, and return LLDB_INVALID_BREAK_ID. - -lldb::break_id_t BreakpointSiteList::Add(const BreakpointSiteSP &bp) { - lldb::addr_t bp_site_load_addr = bp->GetLoadAddress(); - std::lock_guard guard(m_mutex); - collection::iterator iter = m_bp_site_list.find(bp_site_load_addr); - - if (iter == m_bp_site_list.end()) { - m_bp_site_list.insert(iter, collection::value_type(bp_site_load_addr, bp)); - return bp->GetID(); - } else { - return LLDB_INVALID_BREAK_ID; - } -} - -bool BreakpointSiteList::ShouldStop(StoppointCallbackContext *context, - lldb::break_id_t site_id) { - BreakpointSiteSP site_sp(FindByID(site_id)); - if (site_sp) { - // Let the BreakpointSite decide if it should stop here (could not have - // reached it's target hit count yet, or it could have a callback that - // decided it shouldn't stop (shared library loads/unloads). - return site_sp->ShouldStop(context); - } - // We should stop here since this BreakpointSite isn't valid anymore or it - // doesn't exist. - return true; -} -lldb::break_id_t BreakpointSiteList::FindIDByAddress(lldb::addr_t addr) { - if (BreakpointSiteSP bp = FindByAddress(addr)) - return bp.get()->GetID(); - return LLDB_INVALID_BREAK_ID; -} - -bool BreakpointSiteList::Remove(lldb::break_id_t break_id) { - std::lock_guard guard(m_mutex); - collection::iterator pos = GetIDIterator(break_id); // Predicate - if (pos != m_bp_site_list.end()) { - m_bp_site_list.erase(pos); - return true; - } - return false; -} - -bool BreakpointSiteList::RemoveByAddress(lldb::addr_t address) { - std::lock_guard guard(m_mutex); - collection::iterator pos = m_bp_site_list.find(address); - if (pos != m_bp_site_list.end()) { - m_bp_site_list.erase(pos); - return true; - } - return false; -} - -class BreakpointSiteIDMatches { -public: - BreakpointSiteIDMatches(lldb::break_id_t break_id) : m_break_id(break_id) {} - - bool operator()(std::pair val_pair) const { - return m_break_id == val_pair.second->GetID(); - } - -private: - const lldb::break_id_t m_break_id; -}; - -BreakpointSiteList::collection::iterator -BreakpointSiteList::GetIDIterator(lldb::break_id_t break_id) { - std::lock_guard guard(m_mutex); - return std::find_if(m_bp_site_list.begin(), - m_bp_site_list.end(), // Search full range - BreakpointSiteIDMatches(break_id)); // Predicate -} - -BreakpointSiteList::collection::const_iterator -BreakpointSiteList::GetIDConstIterator(lldb::break_id_t break_id) const { - std::lock_guard guard(m_mutex); - return std::find_if(m_bp_site_list.begin(), - m_bp_site_list.end(), // Search full range - BreakpointSiteIDMatches(break_id)); // Predicate -} - -BreakpointSiteSP BreakpointSiteList::FindByID(lldb::break_id_t break_id) { - std::lock_guard guard(m_mutex); - BreakpointSiteSP stop_sp; - collection::iterator pos = GetIDIterator(break_id); - if (pos != m_bp_site_list.end()) - stop_sp = pos->second; - - return stop_sp; -} - -const BreakpointSiteSP -BreakpointSiteList::FindByID(lldb::break_id_t break_id) const { - std::lock_guard guard(m_mutex); - BreakpointSiteSP stop_sp; - collection::const_iterator pos = GetIDConstIterator(break_id); - if (pos != m_bp_site_list.end()) - stop_sp = pos->second; - - return stop_sp; -} - -BreakpointSiteSP BreakpointSiteList::FindByAddress(lldb::addr_t addr) { - BreakpointSiteSP found_sp; - std::lock_guard guard(m_mutex); - collection::iterator iter = m_bp_site_list.find(addr); - if (iter != m_bp_site_list.end()) - found_sp = iter->second; - return found_sp; -} - -bool BreakpointSiteList::BreakpointSiteContainsBreakpoint( - lldb::break_id_t bp_site_id, lldb::break_id_t bp_id) { - std::lock_guard guard(m_mutex); - collection::const_iterator pos = GetIDConstIterator(bp_site_id); - if (pos != m_bp_site_list.end()) - return pos->second->IsBreakpointAtThisSite(bp_id); - - return false; -} - -void BreakpointSiteList::Dump(Stream *s) const { - s->Printf("%p: ", static_cast(this)); - // s->Indent(); - s->Printf("BreakpointSiteList with %u BreakpointSites:\n", - (uint32_t)m_bp_site_list.size()); - s->IndentMore(); - collection::const_iterator pos; - collection::const_iterator end = m_bp_site_list.end(); - for (pos = m_bp_site_list.begin(); pos != end; ++pos) - pos->second->Dump(s); - s->IndentLess(); -} - -void BreakpointSiteList::ForEach( - std::function const &callback) { - std::lock_guard guard(m_mutex); - for (auto pair : m_bp_site_list) - callback(pair.second.get()); -} - -bool BreakpointSiteList::FindInRange(lldb::addr_t lower_bound, - lldb::addr_t upper_bound, - BreakpointSiteList &bp_site_list) const { - if (lower_bound > upper_bound) - return false; - - std::lock_guard guard(m_mutex); - collection::const_iterator lower, upper, pos; - lower = m_bp_site_list.lower_bound(lower_bound); - if (lower == m_bp_site_list.end() || (*lower).first >= upper_bound) - return false; - - // This is one tricky bit. The breakpoint might overlap the bottom end of - // the range. So we grab the breakpoint prior to the lower bound, and check - // that that + its byte size isn't in our range. - if (lower != m_bp_site_list.begin()) { - collection::const_iterator prev_pos = lower; - prev_pos--; - const BreakpointSiteSP &prev_bp = (*prev_pos).second; - if (prev_bp->GetLoadAddress() + prev_bp->GetByteSize() > lower_bound) - bp_site_list.Add(prev_bp); - } - - upper = m_bp_site_list.upper_bound(upper_bound); - - for (pos = lower; pos != upper; pos++) { - bp_site_list.Add((*pos).second); - } - return true; -} diff --git a/lldb/source/Breakpoint/CMakeLists.txt b/lldb/source/Breakpoint/CMakeLists.txt index 5c2802322ed5..42ac338c315b 100644 --- a/lldb/source/Breakpoint/CMakeLists.txt +++ b/lldb/source/Breakpoint/CMakeLists.txt @@ -16,13 +16,15 @@ add_lldb_library(lldbBreakpoint NO_PLUGIN_DEPENDENCIES BreakpointResolverName.cpp BreakpointResolverScripted.cpp BreakpointSite.cpp - BreakpointSiteList.cpp Stoppoint.cpp StoppointCallbackContext.cpp StoppointSite.cpp + StopPointSiteList.cpp Watchpoint.cpp WatchpointList.cpp WatchpointOptions.cpp + WatchpointResource.cpp + WatchpointResourceList.cpp LINK_LIBS lldbCore diff --git a/lldb/source/Breakpoint/StopPointSiteList.cpp b/lldb/source/Breakpoint/StopPointSiteList.cpp new file mode 100644 index 000000000000..275d0fbf265a --- /dev/null +++ b/lldb/source/Breakpoint/StopPointSiteList.cpp @@ -0,0 +1,37 @@ +//===-- StopPointSiteList.cpp ---------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "lldb/Breakpoint/StopPointSiteList.h" +#include "lldb/Breakpoint/BreakpointSite.h" +#include "lldb/Breakpoint/WatchpointResource.h" + +#include "lldb/Utility/Stream.h" +#include + +using namespace lldb; +using namespace lldb_private; + +// This method is only defined when we're specializing for +// BreakpointSite / BreakpointLocation / Breakpoint. +// Watchpoints don't have a similar structure, they are +// WatchpointResource / Watchpoint + +template <> +bool StopPointSiteList::StopPointSiteContainsBreakpoint( + typename BreakpointSite::SiteID site_id, lldb::break_id_t bp_id) { + std::lock_guard guard(m_mutex); + typename collection::const_iterator pos = GetIDConstIterator(site_id); + if (pos != m_site_list.end()) + return pos->second->IsBreakpointAtThisSite(bp_id); + + return false; +} + +namespace lldb_private { +template class StopPointSiteList; +} // namespace lldb_private diff --git a/lldb/source/Breakpoint/Watchpoint.cpp b/lldb/source/Breakpoint/Watchpoint.cpp index b58455f73030..4602ce4213b9 100644 --- a/lldb/source/Breakpoint/Watchpoint.cpp +++ b/lldb/source/Breakpoint/Watchpoint.cpp @@ -9,9 +9,11 @@ #include "lldb/Breakpoint/Watchpoint.h" #include "lldb/Breakpoint/StoppointCallbackContext.h" +#include "lldb/Breakpoint/WatchpointResource.h" #include "lldb/Core/Value.h" #include "lldb/Core/ValueObject.h" #include "lldb/Core/ValueObjectMemory.h" +#include "lldb/DataFormatters/DumpValueObjectOptions.h" #include "lldb/Expression/UserExpression.h" #include "lldb/Symbol/TypeSystem.h" #include "lldb/Target/Process.h" @@ -161,7 +163,7 @@ bool Watchpoint::VariableWatchpointDisabler(void *baton, "callback for watchpoint %" PRId32 " matched internal breakpoint execution context", watch_sp->GetID()); - process_sp->DisableWatchpoint(watch_sp.get()); + process_sp->DisableWatchpoint(watch_sp); return false; } LLDB_LOGF(log, @@ -266,33 +268,69 @@ void Watchpoint::Dump(Stream *s) const { // If prefix is nullptr, we display the watch id and ignore the prefix // altogether. -void Watchpoint::DumpSnapshots(Stream *s, const char *prefix) const { - if (!prefix) { - s->Printf("\nWatchpoint %u hit:", GetID()); - prefix = ""; - } +bool Watchpoint::DumpSnapshots(Stream *s, const char *prefix) const { + bool printed_anything = false; + + // For read watchpoints, don't display any before/after value changes. + if (m_watch_read && !m_watch_modify && !m_watch_write) + return printed_anything; + + s->Printf("\n"); + s->Printf("Watchpoint %u hit:\n", GetID()); + + StreamString values_ss; + if (prefix) + values_ss.Indent(prefix); if (m_old_value_sp) { - const char *old_value_cstr = m_old_value_sp->GetValueAsCString(); - if (old_value_cstr && old_value_cstr[0]) - s->Printf("\n%sold value: %s", prefix, old_value_cstr); - else { - const char *old_summary_cstr = m_old_value_sp->GetSummaryAsCString(); - if (old_summary_cstr && old_summary_cstr[0]) - s->Printf("\n%sold value: %s", prefix, old_summary_cstr); + if (auto *old_value_cstr = m_old_value_sp->GetValueAsCString()) { + values_ss.Printf("old value: %s", old_value_cstr); + } else { + if (auto *old_summary_cstr = m_old_value_sp->GetSummaryAsCString()) + values_ss.Printf("old value: %s", old_summary_cstr); + else { + StreamString strm; + DumpValueObjectOptions options; + options.SetUseDynamicType(eNoDynamicValues) + .SetHideRootType(true) + .SetHideRootName(true) + .SetHideName(true); + m_old_value_sp->Dump(strm, options); + if (strm.GetData()) + values_ss.Printf("old value: %s", strm.GetData()); + } } } if (m_new_value_sp) { - const char *new_value_cstr = m_new_value_sp->GetValueAsCString(); - if (new_value_cstr && new_value_cstr[0]) - s->Printf("\n%snew value: %s", prefix, new_value_cstr); + if (values_ss.GetSize()) + values_ss.Printf("\n"); + + if (auto *new_value_cstr = m_new_value_sp->GetValueAsCString()) + values_ss.Printf("new value: %s", new_value_cstr); else { - const char *new_summary_cstr = m_new_value_sp->GetSummaryAsCString(); - if (new_summary_cstr && new_summary_cstr[0]) - s->Printf("\n%snew value: %s", prefix, new_summary_cstr); + if (auto *new_summary_cstr = m_new_value_sp->GetSummaryAsCString()) + values_ss.Printf("new value: %s", new_summary_cstr); + else { + StreamString strm; + DumpValueObjectOptions options; + options.SetUseDynamicType(eNoDynamicValues) + .SetHideRootType(true) + .SetHideRootName(true) + .SetHideName(true); + m_new_value_sp->Dump(strm, options); + if (strm.GetData()) + values_ss.Printf("new value: %s", strm.GetData()); + } } } + + if (values_ss.GetSize()) { + s->Printf("%s", values_ss.GetData()); + printed_anything = true; + } + + return printed_anything; } void Watchpoint::DumpWithLevel(Stream *s, diff --git a/lldb/source/Breakpoint/WatchpointResource.cpp b/lldb/source/Breakpoint/WatchpointResource.cpp new file mode 100644 index 000000000000..4b8fbe42c865 --- /dev/null +++ b/lldb/source/Breakpoint/WatchpointResource.cpp @@ -0,0 +1,122 @@ +//===-- WatchpointResource.cpp --------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include "lldb/Breakpoint/WatchpointResource.h" + +using namespace lldb; +using namespace lldb_private; + +WatchpointResource::WatchpointResource(lldb::addr_t addr, size_t size, + bool read, bool write) + : m_id(GetNextID()), m_addr(addr), m_size(size), + m_watch_read(read), m_watch_write(write) {} + +WatchpointResource::~WatchpointResource() { + std::lock_guard guard(m_constituents_mutex); + m_constituents.clear(); +} + +addr_t WatchpointResource::GetLoadAddress() const { return m_addr; } + +size_t WatchpointResource::GetByteSize() const { return m_size; } + +bool WatchpointResource::WatchpointResourceRead() const { return m_watch_read; } + +bool WatchpointResource::WatchpointResourceWrite() const { + return m_watch_write; +} + +void WatchpointResource::SetType(bool read, bool write) { + m_watch_read = read; + m_watch_write = write; +} + +wp_resource_id_t WatchpointResource::GetID() const { return m_id; } + +void WatchpointResource::SetID(wp_resource_id_t id) { m_id = id; } + +bool WatchpointResource::Contains(addr_t addr) { + if (addr >= m_addr && addr < m_addr + m_size) + return true; + return false; +} + +void WatchpointResource::AddConstituent(const WatchpointSP &wp_sp) { + std::lock_guard guard(m_constituents_mutex); + m_constituents.push_back(wp_sp); +} + +void WatchpointResource::RemoveConstituent(WatchpointSP &wp_sp) { + std::lock_guard guard(m_constituents_mutex); + const auto &it = + std::find(m_constituents.begin(), m_constituents.end(), wp_sp); + if (it != m_constituents.end()) + m_constituents.erase(it); +} + +size_t WatchpointResource::GetNumberOfConstituents() { + std::lock_guard guard(m_constituents_mutex); + return m_constituents.size(); +} + +bool WatchpointResource::ConstituentsContains(const WatchpointSP &wp_sp) { + return ConstituentsContains(wp_sp.get()); +} + +bool WatchpointResource::ConstituentsContains(const Watchpoint *wp) { + std::lock_guard guard(m_constituents_mutex); + WatchpointCollection::const_iterator match = + std::find_if(m_constituents.begin(), m_constituents.end(), + [&wp](const WatchpointSP &x) { return x.get() == wp; }); + return match != m_constituents.end(); +} + +WatchpointSP WatchpointResource::GetConstituentAtIndex(size_t idx) { + std::lock_guard guard(m_constituents_mutex); + assert(idx < m_constituents.size()); + if (idx >= m_constituents.size()) + return {}; + + return m_constituents[idx]; +} + +WatchpointResource::WatchpointCollection +WatchpointResource::CopyConstituentsList() { + std::lock_guard guard(m_constituents_mutex); + return m_constituents; +} + +bool WatchpointResource::ShouldStop(StoppointCallbackContext *context) { + // LWP_TODO: Need to poll all Watchpoint constituents and see if + // we should stop, like BreakpointSites do. +#if 0 + m_hit_counter.Increment(); + // ShouldStop can do a lot of work, and might even come back and hit + // this breakpoint site again. So don't hold the m_constituents_mutex the + // whole while. Instead make a local copy of the collection and call + // ShouldStop on the copy. + WatchpointResourceCollection constituents_copy; + { + std::lock_guard guard(m_constituents_mutex); + constituents_copy = m_constituents; + } + return constituents_copy.ShouldStop(context); +#endif + return true; +} + +void WatchpointResource::Dump(Stream *s) const { + return; // LWP_TODO +} + +wp_resource_id_t WatchpointResource::GetNextID() { + static wp_resource_id_t g_next_id = 0; + return ++g_next_id; +} diff --git a/lldb/source/Breakpoint/WatchpointResourceList.cpp b/lldb/source/Breakpoint/WatchpointResourceList.cpp new file mode 100644 index 000000000000..d1d364832098 --- /dev/null +++ b/lldb/source/Breakpoint/WatchpointResourceList.cpp @@ -0,0 +1,114 @@ +//===-- WatchpointResourceList.cpp ----------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "lldb/Breakpoint/WatchpointResourceList.h" +#include "lldb/Breakpoint/WatchpointResource.h" +#include "lldb/Utility/LLDBLog.h" +#include "lldb/Utility/Log.h" + +using namespace lldb; +using namespace lldb_private; + +WatchpointResourceList::WatchpointResourceList() : m_resources(), m_mutex() {} + +WatchpointResourceList::~WatchpointResourceList() { Clear(); } + +wp_resource_id_t +WatchpointResourceList::Add(const WatchpointResourceSP &wp_res_sp) { + Log *log = GetLog(LLDBLog::Watchpoints); + std::lock_guard guard(m_mutex); + LLDB_LOGF(log, "WatchpointResourceList::Add(addr 0x%" PRIx64 " size %zu)", + wp_res_sp->GetLoadAddress(), wp_res_sp->GetByteSize()); + + m_resources.push_back(wp_res_sp); + return wp_res_sp->GetID(); +} + +bool WatchpointResourceList::Remove(wp_resource_id_t id) { + std::lock_guard guard(m_mutex); + Log *log = GetLog(LLDBLog::Watchpoints); + for (collection::iterator pos = m_resources.begin(); pos != m_resources.end(); + ++pos) { + if ((*pos)->GetID() == id) { + LLDB_LOGF(log, + "WatchpointResourceList::Remove(addr 0x%" PRIx64 " size %zu)", + (*pos)->GetLoadAddress(), (*pos)->GetByteSize()); + m_resources.erase(pos); + return true; + } + } + return false; +} + +bool WatchpointResourceList::RemoveByAddress(addr_t addr) { + std::lock_guard guard(m_mutex); + Log *log = GetLog(LLDBLog::Watchpoints); + for (collection::iterator pos = m_resources.begin(); pos != m_resources.end(); + ++pos) { + if ((*pos)->Contains(addr)) { + LLDB_LOGF(log, + "WatchpointResourceList::RemoveByAddress(addr 0x%" PRIx64 + " size %zu)", + (*pos)->GetLoadAddress(), (*pos)->GetByteSize()); + m_resources.erase(pos); + return true; + } + } + return false; +} + +WatchpointResourceSP WatchpointResourceList::FindByAddress(addr_t addr) { + std::lock_guard guard(m_mutex); + for (WatchpointResourceSP wp_res_sp : m_resources) + if (wp_res_sp->Contains(addr)) + return wp_res_sp; + return {}; +} + +WatchpointResourceSP +WatchpointResourceList::FindByWatchpointSP(WatchpointSP &wp_sp) { + return FindByWatchpoint(wp_sp.get()); +} + +WatchpointResourceSP +WatchpointResourceList::FindByWatchpoint(const Watchpoint *wp) { + std::lock_guard guard(m_mutex); + for (WatchpointResourceSP wp_res_sp : m_resources) + if (wp_res_sp->ConstituentsContains(wp)) + return wp_res_sp; + return {}; +} + +WatchpointResourceSP WatchpointResourceList::FindByID(wp_resource_id_t id) { + std::lock_guard guard(m_mutex); + for (WatchpointResourceSP wp_res_sp : m_resources) + if (wp_res_sp->GetID() == id) + return wp_res_sp; + return {}; +} + +uint32_t WatchpointResourceList::GetSize() { + std::lock_guard guard(m_mutex); + return m_resources.size(); +} + +lldb::WatchpointResourceSP +WatchpointResourceList::GetResourceAtIndex(uint32_t idx) { + std::lock_guard guard(m_mutex); + if (idx < m_resources.size()) + return m_resources[idx]; + + return {}; +} + +void WatchpointResourceList::Clear() { + std::lock_guard guard(m_mutex); + m_resources.clear(); +} + +std::mutex &WatchpointResourceList::GetMutex() { return m_mutex; } diff --git a/lldb/source/Commands/CommandObjectProcess.cpp b/lldb/source/Commands/CommandObjectProcess.cpp index e42d637535eb..6dc7648f872d 100644 --- a/lldb/source/Commands/CommandObjectProcess.cpp +++ b/lldb/source/Commands/CommandObjectProcess.cpp @@ -519,10 +519,10 @@ protected: BreakpointSiteSP bp_site_sp( process->GetBreakpointSiteList().FindByID(bp_site_id)); if (bp_site_sp) { - const size_t num_owners = bp_site_sp->GetNumberOfOwners(); + const size_t num_owners = bp_site_sp->GetNumberOfConstituents(); for (size_t i = 0; i < num_owners; i++) { Breakpoint &bp_ref = - bp_site_sp->GetOwnerAtIndex(i)->GetBreakpoint(); + bp_site_sp->GetConstituentAtIndex(i)->GetBreakpoint(); if (!bp_ref.IsInternal()) { bp_ref.SetIgnoreCount(m_options.m_ignore); } diff --git a/lldb/source/Commands/CommandObjectWatchpoint.cpp b/lldb/source/Commands/CommandObjectWatchpoint.cpp index cd1d226988f2..c80868d33905 100644 --- a/lldb/source/Commands/CommandObjectWatchpoint.cpp +++ b/lldb/source/Commands/CommandObjectWatchpoint.cpp @@ -918,9 +918,9 @@ protected: if (addr_type == eAddressTypeLoad) { // We're in business. // Find out the size of this variable. - size = m_option_watchpoint.watch_size == 0 + size = m_option_watchpoint.watch_size.GetCurrentValue() == 0 ? valobj_sp->GetByteSize().value_or(0) - : m_option_watchpoint.watch_size; + : m_option_watchpoint.watch_size.GetCurrentValue(); } compiler_type = valobj_sp->GetCompilerType(); } else { @@ -1113,8 +1113,8 @@ protected: return; } - if (m_option_watchpoint.watch_size != 0) - size = m_option_watchpoint.watch_size; + if (m_option_watchpoint.watch_size.GetCurrentValue() != 0) + size = m_option_watchpoint.watch_size.GetCurrentValue(); else size = target->GetArchitecture().GetAddressByteSize(); diff --git a/lldb/source/Interpreter/OptionGroupWatchpoint.cpp b/lldb/source/Interpreter/OptionGroupWatchpoint.cpp index c3708e7a1e80..d1ae916cd74b 100644 --- a/lldb/source/Interpreter/OptionGroupWatchpoint.cpp +++ b/lldb/source/Interpreter/OptionGroupWatchpoint.cpp @@ -39,35 +39,12 @@ static constexpr OptionEnumValueElement g_watch_type[] = { }, }; -static constexpr OptionEnumValueElement g_watch_size[] = { - { - 1, - "1", - "Watch for byte size of 1", - }, - { - 2, - "2", - "Watch for byte size of 2", - }, - { - 4, - "4", - "Watch for byte size of 4", - }, - { - 8, - "8", - "Watch for byte size of 8", - }, -}; - static constexpr OptionDefinition g_option_table[] = { {LLDB_OPT_SET_1, false, "watch", 'w', OptionParser::eRequiredArgument, nullptr, OptionEnumValues(g_watch_type), 0, eArgTypeWatchType, "Specify the type of watching to perform."}, {LLDB_OPT_SET_1, false, "size", 's', OptionParser::eRequiredArgument, - nullptr, OptionEnumValues(g_watch_size), 0, eArgTypeByteSize, + nullptr, {}, 0, eArgTypeByteSize, "Number of bytes to use to watch a region."}, {LLDB_OPT_SET_2, false, @@ -80,16 +57,6 @@ static constexpr OptionDefinition g_option_table[] = { eArgTypeLanguage, "Language of expression to run"}}; -bool OptionGroupWatchpoint::IsWatchSizeSupported(uint32_t watch_size) { - for (const auto& size : g_watch_size) { - if (0 == size.value) - break; - if (watch_size == size.value) - return true; - } - return false; -} - Status OptionGroupWatchpoint::SetOptionValue(uint32_t option_idx, llvm::StringRef option_arg, @@ -120,8 +87,10 @@ OptionGroupWatchpoint::SetOptionValue(uint32_t option_idx, break; } case 's': - watch_size = (uint32_t)OptionArgParser::ToOptionEnum( - option_arg, g_option_table[option_idx].enum_values, 0, error); + error = watch_size.SetValueFromString(option_arg); + if (watch_size.GetCurrentValue() == 0) + error.SetErrorStringWithFormat("invalid --size option value '%s'", + option_arg.str().c_str()); break; default: @@ -135,7 +104,7 @@ void OptionGroupWatchpoint::OptionParsingStarting( ExecutionContext *execution_context) { watch_type_specified = false; watch_type = eWatchInvalid; - watch_size = 0; + watch_size.Clear(); language_type = eLanguageTypeUnknown; } diff --git a/lldb/source/Plugins/LanguageRuntime/CPlusPlus/ItaniumABI/ItaniumABILanguageRuntime.cpp b/lldb/source/Plugins/LanguageRuntime/CPlusPlus/ItaniumABI/ItaniumABILanguageRuntime.cpp index 6c763ea1558f..a5c9ead55f4c 100644 --- a/lldb/source/Plugins/LanguageRuntime/CPlusPlus/ItaniumABI/ItaniumABILanguageRuntime.cpp +++ b/lldb/source/Plugins/LanguageRuntime/CPlusPlus/ItaniumABI/ItaniumABILanguageRuntime.cpp @@ -607,7 +607,7 @@ bool ItaniumABILanguageRuntime::ExceptionBreakpointsExplainStop( return false; uint64_t break_site_id = stop_reason->GetValue(); - return m_process->GetBreakpointSiteList().BreakpointSiteContainsBreakpoint( + return m_process->GetBreakpointSiteList().StopPointSiteContainsBreakpoint( break_site_id, m_cxx_exception_bp_sp->GetID()); } diff --git a/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntime.cpp b/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntime.cpp index 80c7bd071d6b..f08f9f0f815d 100644 --- a/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntime.cpp +++ b/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntime.cpp @@ -445,7 +445,7 @@ bool AppleObjCRuntime::ExceptionBreakpointsExplainStop( return false; uint64_t break_site_id = stop_reason->GetValue(); - return m_process->GetBreakpointSiteList().BreakpointSiteContainsBreakpoint( + return m_process->GetBreakpointSiteList().StopPointSiteContainsBreakpoint( break_site_id, m_objc_exception_bp_sp->GetID()); } diff --git a/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleThreadPlanStepThroughObjCTrampoline.cpp b/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleThreadPlanStepThroughObjCTrampoline.cpp index 547a1f6db976..4093cbdd955f 100644 --- a/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleThreadPlanStepThroughObjCTrampoline.cpp +++ b/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleThreadPlanStepThroughObjCTrampoline.cpp @@ -333,7 +333,7 @@ AppleThreadPlanStepThroughDirectDispatch::DoPlanExplainsStop(Event *event_ptr) { if (site_sp->IsBreakpointAtThisSite(break_sp->GetID())) { // If we aren't the only one with a breakpoint on this site, then we // should just stop and return control to the user. - if (site_sp->GetNumberOfOwners() > 1) { + if (site_sp->GetNumberOfConstituents() > 1) { SetPlanComplete(true); return false; } diff --git a/lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp b/lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp index ae36d3f9730b..ca7ff5a99f90 100644 --- a/lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp +++ b/lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp @@ -432,7 +432,7 @@ PlatformDarwin::GetSoftwareBreakpointTrapOpcode(Target &target, // Auto detect arm/thumb if it wasn't explicitly specified if (!bp_is_thumb) { - lldb::BreakpointLocationSP bp_loc_sp(bp_site->GetOwnerAtIndex(0)); + lldb::BreakpointLocationSP bp_loc_sp(bp_site->GetConstituentAtIndex(0)); if (bp_loc_sp) bp_is_thumb = bp_loc_sp->GetAddress().GetAddressClass() == AddressClass::eCodeAlternateISA; diff --git a/lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDP.cpp b/lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDP.cpp index e0956b49ae1f..70bb9aa7a833 100644 --- a/lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDP.cpp +++ b/lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDP.cpp @@ -671,20 +671,6 @@ Status ProcessKDP::DisableBreakpointSite(BreakpointSite *bp_site) { return DisableSoftwareBreakpoint(bp_site); } -Status ProcessKDP::EnableWatchpoint(Watchpoint *wp, bool notify) { - Status error; - error.SetErrorString( - "watchpoints are not supported in kdp remote debugging"); - return error; -} - -Status ProcessKDP::DisableWatchpoint(Watchpoint *wp, bool notify) { - Status error; - error.SetErrorString( - "watchpoints are not supported in kdp remote debugging"); - return error; -} - void ProcessKDP::Clear() { m_thread_list.Clear(); } Status ProcessKDP::DoSignal(int signo) { diff --git a/lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDP.h b/lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDP.h index 3c12fd407449..e5ec5914f960 100644 --- a/lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDP.h +++ b/lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDP.h @@ -124,13 +124,6 @@ public: lldb_private::Status DisableBreakpointSite(lldb_private::BreakpointSite *bp_site) override; - // Process Watchpoints - lldb_private::Status EnableWatchpoint(lldb_private::Watchpoint *wp, - bool notify = true) override; - - lldb_private::Status DisableWatchpoint(lldb_private::Watchpoint *wp, - bool notify = true) override; - CommunicationKDP &GetCommunication() { return m_comm; } protected: diff --git a/lldb/source/Plugins/Process/Utility/StopInfoMachException.cpp b/lldb/source/Plugins/Process/Utility/StopInfoMachException.cpp index 5c947bbc8d9c..565941d3168f 100644 --- a/lldb/source/Plugins/Process/Utility/StopInfoMachException.cpp +++ b/lldb/source/Plugins/Process/Utility/StopInfoMachException.cpp @@ -491,6 +491,9 @@ static StopInfoSP GetStopInfoForHardwareBP(Thread &thread, Target *target, uint64_t exc_sub_sub_code) { // Try hardware watchpoint. if (target) { + // LWP_TODO: We need to find the WatchpointResource that matches + // the address, and evaluate its Watchpoints. + // The exc_sub_code indicates the data break address. lldb::WatchpointSP wp_sp = target->GetWatchpointList().FindByAddress((lldb::addr_t)exc_sub_code); @@ -666,6 +669,9 @@ StopInfoSP StopInfoMachException::CreateStopReasonWithMachException( case llvm::Triple::thumb: if (exc_code == 0x102) // EXC_ARM_DA_DEBUG { + // LWP_TODO: We need to find the WatchpointResource that matches + // the address, and evaluate its Watchpoints. + // It's a watchpoint, then, if the exc_sub_code indicates a // known/enabled data break address from our watchpoint list. lldb::WatchpointSP wp_sp; @@ -742,6 +748,9 @@ StopInfoSP StopInfoMachException::CreateStopReasonWithMachException( } if (exc_code == 0x102) // EXC_ARM_DA_DEBUG { + // LWP_TODO: We need to find the WatchpointResource that matches + // the address, and evaluate its Watchpoints. + // It's a watchpoint, then, if the exc_sub_code indicates a // known/enabled data break address from our watchpoint list. lldb::WatchpointSP wp_sp; diff --git a/lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp b/lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp index 91b3216a57c3..eb0834b1159f 100644 --- a/lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp +++ b/lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp @@ -835,11 +835,11 @@ std::optional ProcessWindows::GetWatchpointSlotCount() { return RegisterContextWindows::GetNumHardwareBreakpointSlots(); } -Status ProcessWindows::EnableWatchpoint(Watchpoint *wp, bool notify) { +Status ProcessWindows::EnableWatchpoint(WatchpointSP wp_sp, bool notify) { Status error; - if (wp->IsEnabled()) { - wp->SetEnabled(true, notify); + if (wp_sp->IsEnabled()) { + wp_sp->SetEnabled(true, notify); return error; } @@ -851,13 +851,13 @@ Status ProcessWindows::EnableWatchpoint(Watchpoint *wp, bool notify) { break; if (info.slot_id == RegisterContextWindows::GetNumHardwareBreakpointSlots()) { error.SetErrorStringWithFormat("Can't find free slot for watchpoint %i", - wp->GetID()); + wp_sp->GetID()); return error; } - info.address = wp->GetLoadAddress(); - info.size = wp->GetByteSize(); - info.read = wp->WatchpointRead(); - info.write = wp->WatchpointWrite(); + info.address = wp_sp->GetLoadAddress(); + info.size = wp_sp->GetByteSize(); + info.read = wp_sp->WatchpointRead(); + info.write = wp_sp->WatchpointWrite(); for (unsigned i = 0U; i < m_thread_list.GetSize(); i++) { Thread *thread = m_thread_list.GetThreadAtIndex(i).get(); @@ -866,7 +866,7 @@ Status ProcessWindows::EnableWatchpoint(Watchpoint *wp, bool notify) { if (!reg_ctx->AddHardwareBreakpoint(info.slot_id, info.address, info.size, info.read, info.write)) { error.SetErrorStringWithFormat( - "Can't enable watchpoint %i on thread 0x%llx", wp->GetID(), + "Can't enable watchpoint %i on thread 0x%llx", wp_sp->GetID(), thread->GetID()); break; } @@ -881,26 +881,26 @@ Status ProcessWindows::EnableWatchpoint(Watchpoint *wp, bool notify) { return error; } - m_watchpoints[wp->GetID()] = info; - m_watchpoint_ids[info.slot_id] = wp->GetID(); + m_watchpoints[wp_sp->GetID()] = info; + m_watchpoint_ids[info.slot_id] = wp_sp->GetID(); - wp->SetEnabled(true, notify); + wp_sp->SetEnabled(true, notify); return error; } -Status ProcessWindows::DisableWatchpoint(Watchpoint *wp, bool notify) { +Status ProcessWindows::DisableWatchpoint(WatchpointSP wp_sp, bool notify) { Status error; - if (!wp->IsEnabled()) { - wp->SetEnabled(false, notify); + if (!wp_sp->IsEnabled()) { + wp_sp->SetEnabled(false, notify); return error; } - auto it = m_watchpoints.find(wp->GetID()); + auto it = m_watchpoints.find(wp_sp->GetID()); if (it == m_watchpoints.end()) { error.SetErrorStringWithFormat("Info about watchpoint %i is not found", - wp->GetID()); + wp_sp->GetID()); return error; } @@ -910,7 +910,7 @@ Status ProcessWindows::DisableWatchpoint(Watchpoint *wp, bool notify) { thread->GetRegisterContext().get()); if (!reg_ctx->RemoveHardwareBreakpoint(it->second.slot_id)) { error.SetErrorStringWithFormat( - "Can't disable watchpoint %i on thread 0x%llx", wp->GetID(), + "Can't disable watchpoint %i on thread 0x%llx", wp_sp->GetID(), thread->GetID()); break; } @@ -921,7 +921,7 @@ Status ProcessWindows::DisableWatchpoint(Watchpoint *wp, bool notify) { m_watchpoint_ids[it->second.slot_id] = LLDB_INVALID_BREAK_ID; m_watchpoints.erase(it); - wp->SetEnabled(false, notify); + wp_sp->SetEnabled(false, notify); return error; } diff --git a/lldb/source/Plugins/Process/Windows/Common/ProcessWindows.h b/lldb/source/Plugins/Process/Windows/Common/ProcessWindows.h index ed083b9e78b4..e97cfb790248 100644 --- a/lldb/source/Plugins/Process/Windows/Common/ProcessWindows.h +++ b/lldb/source/Plugins/Process/Windows/Common/ProcessWindows.h @@ -96,8 +96,10 @@ public: void OnDebuggerError(const Status &error, uint32_t type) override; std::optional GetWatchpointSlotCount() override; - Status EnableWatchpoint(Watchpoint *wp, bool notify = true) override; - Status DisableWatchpoint(Watchpoint *wp, bool notify = true) override; + Status EnableWatchpoint(lldb::WatchpointSP wp_sp, + bool notify = true) override; + Status DisableWatchpoint(lldb::WatchpointSP wp_sp, + bool notify = true) override; protected: ProcessWindows(lldb::TargetSP target_sp, lldb::ListenerSP listener_sp); diff --git a/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp b/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp index 9648f1fd52cf..fb6715140492 100644 --- a/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp +++ b/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp @@ -24,6 +24,7 @@ #include #include "lldb/Breakpoint/Watchpoint.h" +#include "lldb/Breakpoint/WatchpointResource.h" #include "lldb/Core/Debugger.h" #include "lldb/Core/Module.h" #include "lldb/Core/ModuleSpec.h" @@ -1798,24 +1799,29 @@ ThreadSP ProcessGDBRemote::SetThreadStopInfo( addr_t wp_hit_addr = desc_extractor.GetU64(LLDB_INVALID_ADDRESS); watch_id_t watch_id = LLDB_INVALID_WATCH_ID; bool silently_continue = false; - WatchpointSP wp_sp; + WatchpointResourceSP wp_resource_sp; if (wp_hit_addr != LLDB_INVALID_ADDRESS) { - wp_sp = GetTarget().GetWatchpointList().FindByAddress(wp_hit_addr); + wp_resource_sp = + m_watchpoint_resource_list.FindByAddress(wp_hit_addr); // On MIPS, \a wp_hit_addr outside the range of a watched // region means we should silently continue, it is a false hit. ArchSpec::Core core = GetTarget().GetArchitecture().GetCore(); - if (!wp_sp && core >= ArchSpec::kCore_mips_first && + if (!wp_resource_sp && core >= ArchSpec::kCore_mips_first && core <= ArchSpec::kCore_mips_last) silently_continue = true; } - if (!wp_sp && wp_addr != LLDB_INVALID_ADDRESS) - wp_sp = GetTarget().GetWatchpointList().FindByAddress(wp_addr); - if (wp_sp) { - watch_id = wp_sp->GetID(); - } - if (watch_id == LLDB_INVALID_WATCH_ID) { + if (!wp_resource_sp && wp_addr != LLDB_INVALID_ADDRESS) + wp_resource_sp = m_watchpoint_resource_list.FindByAddress(wp_addr); + if (!wp_resource_sp) { Log *log(GetLog(GDBRLog::Watchpoints)); LLDB_LOGF(log, "failed to find watchpoint"); + watch_id = LLDB_INVALID_SITE_ID; + } else { + // LWP_TODO: This is hardcoding a single Watchpoint in a + // Resource, need to add + // StopInfo::CreateStopReasonWithWatchpointResource which + // represents all watchpoints that were tripped at this stop. + watch_id = wp_resource_sp->GetConstituentAtIndex(0)->GetID(); } thread_sp->SetStopInfo(StopInfo::CreateStopReasonWithWatchpointID( *thread_sp, watch_id, silently_continue)); @@ -2239,8 +2245,8 @@ StateType ProcessGDBRemote::SetThreadStopInfo(StringExtractor &stop_packet) { lldb::addr_t wp_addr = LLDB_INVALID_ADDRESS; value.getAsInteger(16, wp_addr); - WatchpointSP wp_sp = - GetTarget().GetWatchpointList().FindByAddress(wp_addr); + WatchpointResourceSP wp_resource_sp = + m_watchpoint_resource_list.FindByAddress(wp_addr); // Rewrite gdb standard watch/rwatch/awatch to // "reason:watchpoint" + "description:ADDR", @@ -3109,102 +3115,182 @@ Status ProcessGDBRemote::DisableBreakpointSite(BreakpointSite *bp_site) { } // Pre-requisite: wp != NULL. -static GDBStoppointType GetGDBStoppointType(Watchpoint *wp) { - assert(wp); - bool watch_read = wp->WatchpointRead(); - bool watch_write = wp->WatchpointWrite(); - bool watch_modify = wp->WatchpointModify(); - - // watch_read, watch_write, watch_modify cannot all be false. - assert((watch_read || watch_write || watch_modify) && - "watch_read, watch_write, watch_modify cannot all be false."); - if (watch_read && (watch_write || watch_modify)) +static GDBStoppointType +GetGDBStoppointType(const WatchpointResourceSP &wp_res_sp) { + assert(wp_res_sp); + bool read = wp_res_sp->WatchpointResourceRead(); + bool write = wp_res_sp->WatchpointResourceWrite(); + + assert((read || write) && + "WatchpointResource type is neither read nor write"); + if (read && write) return eWatchpointReadWrite; - else if (watch_read) + else if (read) return eWatchpointRead; - else // Must be watch_write or watch_modify, then. + else return eWatchpointWrite; } -Status ProcessGDBRemote::EnableWatchpoint(Watchpoint *wp, bool notify) { +Status ProcessGDBRemote::EnableWatchpoint(WatchpointSP wp_sp, bool notify) { Status error; - if (wp) { - user_id_t watchID = wp->GetID(); - addr_t addr = wp->GetLoadAddress(); - Log *log(GetLog(GDBRLog::Watchpoints)); - LLDB_LOGF(log, "ProcessGDBRemote::EnableWatchpoint(watchID = %" PRIu64 ")", - watchID); - if (wp->IsEnabled()) { - LLDB_LOGF(log, - "ProcessGDBRemote::EnableWatchpoint(watchID = %" PRIu64 - ") addr = 0x%8.8" PRIx64 ": watchpoint already enabled.", - watchID, (uint64_t)addr); - return error; - } + if (!wp_sp) { + error.SetErrorString("No watchpoint specified"); + return error; + } + user_id_t watchID = wp_sp->GetID(); + addr_t addr = wp_sp->GetLoadAddress(); + Log *log(GetLog(GDBRLog::Watchpoints)); + LLDB_LOGF(log, "ProcessGDBRemote::EnableWatchpoint(watchID = %" PRIu64 ")", + watchID); + if (wp_sp->IsEnabled()) { + LLDB_LOGF(log, + "ProcessGDBRemote::EnableWatchpoint(watchID = %" PRIu64 + ") addr = 0x%8.8" PRIx64 ": watchpoint already enabled.", + watchID, (uint64_t)addr); + return error; + } - GDBStoppointType type = GetGDBStoppointType(wp); - // Pass down an appropriate z/Z packet... - if (m_gdb_comm.SupportsGDBStoppointPacket(type)) { - if (m_gdb_comm.SendGDBStoppointTypePacket(type, true, addr, - wp->GetByteSize(), - GetInterruptTimeout()) == 0) { - wp->SetEnabled(true, notify); - return error; - } else - error.SetErrorString("sending gdb watchpoint packet failed"); - } else - error.SetErrorString("watchpoints not supported"); + bool read = wp_sp->WatchpointRead(); + bool write = wp_sp->WatchpointWrite() || wp_sp->WatchpointModify(); + size_t size = wp_sp->GetByteSize(); + + // New WatchpointResources needed to implement this Watchpoint. + std::vector resources; + + // LWP_TODO: Break up the user's request into pieces that can be watched + // given the capabilities of the target cpu / stub software. + // As a default, breaking the watched region up into target-pointer-sized, + // aligned, groups. + // + // Beyond the default, a stub can / should inform us of its capabilities, + // e.g. a stub that can do AArch64 power-of-2 MASK watchpoints. + // + // And the cpu may have unique capabilities. AArch64 BAS watchpoints + // can watch any sequential bytes in a doubleword, but Intel watchpoints + // can only watch 1, 2, 4, 8 bytes within a doubleword. + WatchpointResourceSP wp_res_sp = + std::make_shared(addr, size, read, write); + resources.push_back(wp_res_sp); + + // LWP_TODO: Now that we know the WP Resources needed to implement this + // Watchpoint, we need to look at currently allocated Resources in the + // Process and if they match, or are within the same memory granule, or + // overlapping memory ranges, then we need to combine them. e.g. one + // Watchpoint watching 1 byte at 0x1002 and a second watchpoint watching 1 + // byte at 0x1003, they must use the same hardware watchpoint register + // (Resource) to watch them. + + // This may mean that an existing resource changes its type (read to + // read+write) or address range it is watching, in which case the old + // watchpoint needs to be disabled and the new Resource addr/size/type + // watchpoint enabled. + + // If we modify a shared Resource to accomodate this newly added Watchpoint, + // and we are unable to set all of the Resources for it in the inferior, we + // will return an error for this Watchpoint and the shared Resource should + // be restored. e.g. this Watchpoint requires three Resources, one which + // is shared with another Watchpoint. We extend the shared Resouce to + // handle both Watchpoints and we try to set two new ones. But if we don't + // have sufficient watchpoint register for all 3, we need to show an error + // for creating this Watchpoint and we should reset the shared Resource to + // its original configuration because it is no longer shared. + + bool set_all_resources = true; + std::vector succesfully_set_resources; + for (const auto &wp_res_sp : resources) { + addr_t addr = wp_res_sp->GetLoadAddress(); + size_t size = wp_res_sp->GetByteSize(); + GDBStoppointType type = GetGDBStoppointType(wp_res_sp); + if (!m_gdb_comm.SupportsGDBStoppointPacket(type) || + m_gdb_comm.SendGDBStoppointTypePacket(type, true, addr, size, + GetInterruptTimeout())) { + set_all_resources = false; + break; + } else { + succesfully_set_resources.push_back(wp_res_sp); + } + } + if (set_all_resources) { + wp_sp->SetEnabled(true, notify); + for (const auto &wp_res_sp : resources) { + // LWP_TODO: If we expanded/reused an existing Resource, + // it's already in the WatchpointResourceList. + wp_res_sp->AddConstituent(wp_sp); + m_watchpoint_resource_list.Add(wp_res_sp); + } + return error; } else { - error.SetErrorString("Watchpoint argument was NULL."); + // We failed to allocate one of the resources. Unset all + // of the new resources we did successfully set in the + // process. + for (const auto &wp_res_sp : succesfully_set_resources) { + addr_t addr = wp_res_sp->GetLoadAddress(); + size_t size = wp_res_sp->GetByteSize(); + GDBStoppointType type = GetGDBStoppointType(wp_res_sp); + m_gdb_comm.SendGDBStoppointTypePacket(type, false, addr, size, + GetInterruptTimeout()); + } + error.SetErrorString("Setting one of the watchpoint resources failed"); } - if (error.Success()) - error.SetErrorToGenericError(); return error; } -Status ProcessGDBRemote::DisableWatchpoint(Watchpoint *wp, bool notify) { +Status ProcessGDBRemote::DisableWatchpoint(WatchpointSP wp_sp, bool notify) { Status error; - if (wp) { - user_id_t watchID = wp->GetID(); + if (!wp_sp) { + error.SetErrorString("Watchpoint argument was NULL."); + return error; + } + + user_id_t watchID = wp_sp->GetID(); - Log *log(GetLog(GDBRLog::Watchpoints)); + Log *log(GetLog(GDBRLog::Watchpoints)); - addr_t addr = wp->GetLoadAddress(); + addr_t addr = wp_sp->GetLoadAddress(); + + LLDB_LOGF(log, + "ProcessGDBRemote::DisableWatchpoint (watchID = %" PRIu64 + ") addr = 0x%8.8" PRIx64, + watchID, (uint64_t)addr); + if (!wp_sp->IsEnabled()) { LLDB_LOGF(log, "ProcessGDBRemote::DisableWatchpoint (watchID = %" PRIu64 - ") addr = 0x%8.8" PRIx64, + ") addr = 0x%8.8" PRIx64 " -- SUCCESS (already disabled)", watchID, (uint64_t)addr); + // See also 'class WatchpointSentry' within StopInfo.cpp. This disabling + // attempt might come from the user-supplied actions, we'll route it in + // order for the watchpoint object to intelligently process this action. + wp_sp->SetEnabled(false, notify); + return error; + } - if (!wp->IsEnabled()) { - LLDB_LOGF(log, - "ProcessGDBRemote::DisableWatchpoint (watchID = %" PRIu64 - ") addr = 0x%8.8" PRIx64 " -- SUCCESS (already disabled)", - watchID, (uint64_t)addr); - // See also 'class WatchpointSentry' within StopInfo.cpp. This disabling - // attempt might come from the user-supplied actions, we'll route it in - // order for the watchpoint object to intelligently process this action. - wp->SetEnabled(false, notify); - return error; - } + if (wp_sp->IsHardware()) { + bool disabled_all = true; - if (wp->IsHardware()) { - GDBStoppointType type = GetGDBStoppointType(wp); - // Pass down an appropriate z/Z packet... - if (m_gdb_comm.SendGDBStoppointTypePacket(type, false, addr, - wp->GetByteSize(), - GetInterruptTimeout()) == 0) { - wp->SetEnabled(false, notify); - return error; - } else - error.SetErrorString("sending gdb watchpoint packet failed"); + std::vector unused_resources; + for (const auto &wp_res_sp : m_watchpoint_resource_list.Sites()) { + if (wp_res_sp->ConstituentsContains(wp_sp)) { + GDBStoppointType type = GetGDBStoppointType(wp_res_sp); + addr_t addr = wp_res_sp->GetLoadAddress(); + size_t size = wp_res_sp->GetByteSize(); + if (m_gdb_comm.SendGDBStoppointTypePacket(type, false, addr, size, + GetInterruptTimeout())) { + disabled_all = false; + } else { + wp_res_sp->RemoveConstituent(wp_sp); + if (wp_res_sp->GetNumberOfConstituents() == 0) + unused_resources.push_back(wp_res_sp); + } + } } - // TODO: clear software watchpoints if we implement them - } else { - error.SetErrorString("Watchpoint argument was NULL."); + for (auto &wp_res_sp : unused_resources) + m_watchpoint_resource_list.Remove(wp_res_sp->GetID()); + + wp_sp->SetEnabled(false, notify); + if (!disabled_all) + error.SetErrorString("Failure disabling one of the watchpoint locations"); } - if (error.Success()) - error.SetErrorToGenericError(); return error; } @@ -5456,16 +5542,12 @@ void ProcessGDBRemote::DidForkSwitchHardwareTraps(bool enable) { }); } - WatchpointList &wps = GetTarget().GetWatchpointList(); - size_t wp_count = wps.GetSize(); - for (size_t i = 0; i < wp_count; ++i) { - WatchpointSP wp = wps.GetByIndex(i); - if (wp->IsEnabled()) { - GDBStoppointType type = GetGDBStoppointType(wp.get()); - m_gdb_comm.SendGDBStoppointTypePacket(type, enable, wp->GetLoadAddress(), - wp->GetByteSize(), - GetInterruptTimeout()); - } + for (const auto &wp_res_sp : m_watchpoint_resource_list.Sites()) { + addr_t addr = wp_res_sp->GetLoadAddress(); + size_t size = wp_res_sp->GetByteSize(); + GDBStoppointType type = GetGDBStoppointType(wp_res_sp); + m_gdb_comm.SendGDBStoppointTypePacket(type, true, addr, size, + GetInterruptTimeout()); } } diff --git a/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.h b/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.h index f3787e716904..c1ea1cc79055 100644 --- a/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.h +++ b/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.h @@ -158,9 +158,11 @@ public: Status DisableBreakpointSite(BreakpointSite *bp_site) override; // Process Watchpoints - Status EnableWatchpoint(Watchpoint *wp, bool notify = true) override; + Status EnableWatchpoint(lldb::WatchpointSP wp_sp, + bool notify = true) override; - Status DisableWatchpoint(Watchpoint *wp, bool notify = true) override; + Status DisableWatchpoint(lldb::WatchpointSP wp_sp, + bool notify = true) override; std::optional GetWatchpointSlotCount() override; diff --git a/lldb/source/Target/Platform.cpp b/lldb/source/Target/Platform.cpp index c345e3313607..4ce290dfbe03 100644 --- a/lldb/source/Target/Platform.cpp +++ b/lldb/source/Target/Platform.cpp @@ -2014,7 +2014,7 @@ size_t Platform::GetSoftwareBreakpointTrapOpcode(Target &target, static const uint8_t g_arm_breakpoint_opcode[] = {0xf0, 0x01, 0xf0, 0xe7}; static const uint8_t g_thumb_breakpoint_opcode[] = {0x01, 0xde}; - lldb::BreakpointLocationSP bp_loc_sp(bp_site->GetOwnerAtIndex(0)); + lldb::BreakpointLocationSP bp_loc_sp(bp_site->GetConstituentAtIndex(0)); AddressClass addr_class = AddressClass::eUnknown; if (bp_loc_sp) { diff --git a/lldb/source/Target/Process.cpp b/lldb/source/Target/Process.cpp index f3da2839e262..2d77144a9b28 100644 --- a/lldb/source/Target/Process.cpp +++ b/lldb/source/Target/Process.cpp @@ -436,7 +436,7 @@ Process::Process(lldb::TargetSP target_sp, ListenerSP listener_sp, m_exit_status_mutex(), m_thread_mutex(), m_thread_list_real(this), m_thread_list(this), m_thread_plans(*this), m_extended_thread_list(this), m_extended_thread_stop_id(0), m_queue_list(this), m_queue_list_stop_id(0), - m_notifications(), m_image_tokens(), + m_watchpoint_resource_list(), m_notifications(), m_image_tokens(), m_breakpoint_site_list(), m_dynamic_checkers_up(), m_unix_signals_sp(unix_signals_sp), m_abi_sp(), m_process_input_reader(), m_stdio_communication("process.stdio"), m_stdio_communication_mutex(), @@ -547,6 +547,7 @@ void Process::Finalize() { m_extended_thread_list.Destroy(); m_queue_list.Clear(); m_queue_list_stop_id = 0; + m_watchpoint_resource_list.Clear(); std::vector empty_notifications; m_notifications.swap(empty_notifications); m_image_tokens.clear(); @@ -1563,11 +1564,12 @@ void Process::SetDynamicCheckers(DynamicCheckerFunctions *dynamic_checkers) { m_dynamic_checkers_up.reset(dynamic_checkers); } -BreakpointSiteList &Process::GetBreakpointSiteList() { +StopPointSiteList &Process::GetBreakpointSiteList() { return m_breakpoint_site_list; } -const BreakpointSiteList &Process::GetBreakpointSiteList() const { +const StopPointSiteList & +Process::GetBreakpointSiteList() const { return m_breakpoint_site_list; } @@ -1615,7 +1617,7 @@ Status Process::EnableBreakpointSiteByID(lldb::user_id_t break_id) { } lldb::break_id_t -Process::CreateBreakpointSite(const BreakpointLocationSP &owner, +Process::CreateBreakpointSite(const BreakpointLocationSP &constituent, bool use_hardware) { addr_t load_addr = LLDB_INVALID_ADDRESS; @@ -1642,10 +1644,10 @@ Process::CreateBreakpointSite(const BreakpointLocationSP &owner, // Reset the IsIndirect flag here, in case the location changes from pointing // to a indirect symbol to a regular symbol. - owner->SetIsIndirect(false); + constituent->SetIsIndirect(false); - if (owner->ShouldResolveIndirectFunctions()) { - Symbol *symbol = owner->GetAddress().CalculateSymbolContextSymbol(); + if (constituent->ShouldResolveIndirectFunctions()) { + Symbol *symbol = constituent->GetAddress().CalculateSymbolContextSymbol(); if (symbol && symbol->IsIndirect()) { Status error; Address symbol_address = symbol->GetAddress(); @@ -1655,37 +1657,37 @@ Process::CreateBreakpointSite(const BreakpointLocationSP &owner, "warning: failed to resolve indirect function at 0x%" PRIx64 " for breakpoint %i.%i: %s\n", symbol->GetLoadAddress(&GetTarget()), - owner->GetBreakpoint().GetID(), owner->GetID(), + constituent->GetBreakpoint().GetID(), constituent->GetID(), error.AsCString() ? error.AsCString() : "unknown error"); return LLDB_INVALID_BREAK_ID; } Address resolved_address(load_addr); load_addr = resolved_address.GetOpcodeLoadAddress(&GetTarget()); - owner->SetIsIndirect(true); + constituent->SetIsIndirect(true); } else - load_addr = owner->GetAddress().GetOpcodeLoadAddress(&GetTarget()); + load_addr = constituent->GetAddress().GetOpcodeLoadAddress(&GetTarget()); } else - load_addr = owner->GetAddress().GetOpcodeLoadAddress(&GetTarget()); + load_addr = constituent->GetAddress().GetOpcodeLoadAddress(&GetTarget()); if (load_addr != LLDB_INVALID_ADDRESS) { BreakpointSiteSP bp_site_sp; - // Look up this breakpoint site. If it exists, then add this new owner, - // otherwise create a new breakpoint site and add it. + // Look up this breakpoint site. If it exists, then add this new + // constituent, otherwise create a new breakpoint site and add it. bp_site_sp = m_breakpoint_site_list.FindByAddress(load_addr); if (bp_site_sp) { - bp_site_sp->AddOwner(owner); - owner->SetBreakpointSite(bp_site_sp); + bp_site_sp->AddConstituent(constituent); + constituent->SetBreakpointSite(bp_site_sp); return bp_site_sp->GetID(); } else { - bp_site_sp.reset(new BreakpointSite(&m_breakpoint_site_list, owner, - load_addr, use_hardware)); + bp_site_sp.reset( + new BreakpointSite(constituent, load_addr, use_hardware)); if (bp_site_sp) { Status error = EnableBreakpointSite(bp_site_sp.get()); if (error.Success()) { - owner->SetBreakpointSite(bp_site_sp); + constituent->SetBreakpointSite(bp_site_sp); return m_breakpoint_site_list.Add(bp_site_sp); } else { if (show_error || use_hardware) { @@ -1693,7 +1695,8 @@ Process::CreateBreakpointSite(const BreakpointLocationSP &owner, GetTarget().GetDebugger().GetErrorStream().Printf( "warning: failed to set breakpoint site at 0x%" PRIx64 " for breakpoint %i.%i: %s\n", - load_addr, owner->GetBreakpoint().GetID(), owner->GetID(), + load_addr, constituent->GetBreakpoint().GetID(), + constituent->GetID(), error.AsCString() ? error.AsCString() : "unknown error"); } } @@ -1704,11 +1707,12 @@ Process::CreateBreakpointSite(const BreakpointLocationSP &owner, return LLDB_INVALID_BREAK_ID; } -void Process::RemoveOwnerFromBreakpointSite(lldb::user_id_t owner_id, - lldb::user_id_t owner_loc_id, - BreakpointSiteSP &bp_site_sp) { - uint32_t num_owners = bp_site_sp->RemoveOwner(owner_id, owner_loc_id); - if (num_owners == 0) { +void Process::RemoveConstituentFromBreakpointSite( + lldb::user_id_t constituent_id, lldb::user_id_t constituent_loc_id, + BreakpointSiteSP &bp_site_sp) { + uint32_t num_constituents = + bp_site_sp->RemoveConstituent(constituent_id, constituent_loc_id); + if (num_constituents == 0) { // Don't try to disable the site if we don't have a live process anymore. if (IsAlive()) DisableBreakpointSite(bp_site_sp.get()); @@ -1719,7 +1723,7 @@ void Process::RemoveOwnerFromBreakpointSite(lldb::user_id_t owner_id, size_t Process::RemoveBreakpointOpcodesFromBuffer(addr_t bp_addr, size_t size, uint8_t *buf) const { size_t bytes_removed = 0; - BreakpointSiteList bp_sites_in_range; + StopPointSiteList bp_sites_in_range; if (m_breakpoint_site_list.FindInRange(bp_addr, bp_addr + size, bp_sites_in_range)) { @@ -2140,7 +2144,7 @@ size_t Process::WriteMemory(addr_t addr, const void *buf, size_t size, // (enabled software breakpoints) any software traps (breakpoints) that we // may have placed in our tasks memory. - BreakpointSiteList bp_sites_in_range; + StopPointSiteList bp_sites_in_range; if (!m_breakpoint_site_list.FindInRange(addr, addr + size, bp_sites_in_range)) return WriteMemoryPrivate(addr, buf, size, error); @@ -2408,13 +2412,13 @@ bool Process::GetLoadAddressPermissions(lldb::addr_t load_addr, return true; } -Status Process::EnableWatchpoint(Watchpoint *watchpoint, bool notify) { +Status Process::EnableWatchpoint(WatchpointSP wp_sp, bool notify) { Status error; error.SetErrorString("watchpoints are not supported"); return error; } -Status Process::DisableWatchpoint(Watchpoint *watchpoint, bool notify) { +Status Process::DisableWatchpoint(WatchpointSP wp_sp, bool notify) { Status error; error.SetErrorString("watchpoints are not supported"); return error; diff --git a/lldb/source/Target/StackFrameList.cpp b/lldb/source/Target/StackFrameList.cpp index 88cc518d0ea0..2273e52e2e04 100644 --- a/lldb/source/Target/StackFrameList.cpp +++ b/lldb/source/Target/StackFrameList.cpp @@ -156,9 +156,10 @@ void StackFrameList::ResetCurrentInlinedDepth() { m_thread.GetProcess()->GetBreakpointSiteList().FindByID(bp_site_id)); bool all_internal = true; if (bp_site_sp) { - uint32_t num_owners = bp_site_sp->GetNumberOfOwners(); + uint32_t num_owners = bp_site_sp->GetNumberOfConstituents(); for (uint32_t i = 0; i < num_owners; i++) { - Breakpoint &bp_ref = bp_site_sp->GetOwnerAtIndex(i)->GetBreakpoint(); + Breakpoint &bp_ref = + bp_site_sp->GetConstituentAtIndex(i)->GetBreakpoint(); if (!bp_ref.IsInternal()) { all_internal = false; } diff --git a/lldb/source/Target/StopInfo.cpp b/lldb/source/Target/StopInfo.cpp index 0b858454782b..3b65d661c1ab 100644 --- a/lldb/source/Target/StopInfo.cpp +++ b/lldb/source/Target/StopInfo.cpp @@ -12,6 +12,7 @@ #include "lldb/Breakpoint/BreakpointLocation.h" #include "lldb/Breakpoint/StoppointCallbackContext.h" #include "lldb/Breakpoint/Watchpoint.h" +#include "lldb/Breakpoint/WatchpointResource.h" #include "lldb/Core/Debugger.h" #include "lldb/Core/ValueObject.h" #include "lldb/Expression/UserExpression.h" @@ -109,9 +110,9 @@ public: BreakpointSiteSP bp_site_sp( thread_sp->GetProcess()->GetBreakpointSiteList().FindByID(m_value)); if (bp_site_sp) { - uint32_t num_owners = bp_site_sp->GetNumberOfOwners(); - if (num_owners == 1) { - BreakpointLocationSP bp_loc_sp = bp_site_sp->GetOwnerAtIndex(0); + uint32_t num_constituents = bp_site_sp->GetNumberOfConstituents(); + if (num_constituents == 1) { + BreakpointLocationSP bp_loc_sp = bp_site_sp->GetConstituentAtIndex(0); if (bp_loc_sp) { Breakpoint & bkpt = bp_loc_sp->GetBreakpoint(); m_break_id = bkpt.GetID(); @@ -120,8 +121,10 @@ public: } } else { m_was_all_internal = true; - for (uint32_t i = 0; i < num_owners; i++) { - if (!bp_site_sp->GetOwnerAtIndex(i)->GetBreakpoint().IsInternal()) { + for (uint32_t i = 0; i < num_constituents; i++) { + if (!bp_site_sp->GetConstituentAtIndex(i) + ->GetBreakpoint() + .IsInternal()) { m_was_all_internal = false; break; } @@ -189,9 +192,9 @@ public: // If we have just hit an internal breakpoint, and it has a kind // description, print that instead of the full breakpoint printing: if (bp_site_sp->IsInternal()) { - size_t num_owners = bp_site_sp->GetNumberOfOwners(); - for (size_t idx = 0; idx < num_owners; idx++) { - const char *kind = bp_site_sp->GetOwnerAtIndex(idx) + size_t num_constituents = bp_site_sp->GetNumberOfConstituents(); + for (size_t idx = 0; idx < num_constituents; idx++) { + const char *kind = bp_site_sp->GetConstituentAtIndex(idx) ->GetBreakpoint() .GetBreakpointKind(); if (kind != nullptr) { @@ -284,13 +287,14 @@ protected: // Use this variable to tell us if that is true. bool actually_hit_any_locations = false; if (bp_site_sp) { - // Let's copy the owners list out of the site and store them in a local - // list. That way if one of the breakpoint actions changes the site, - // then we won't be operating on a bad list. + // Let's copy the constituents list out of the site and store them in a + // local list. That way if one of the breakpoint actions changes the + // site, then we won't be operating on a bad list. BreakpointLocationCollection site_locations; - size_t num_owners = bp_site_sp->CopyOwnersList(site_locations); + size_t num_constituents = + bp_site_sp->CopyConstituentsList(site_locations); - if (num_owners == 0) { + if (num_constituents == 0) { m_should_stop = true; actually_hit_any_locations = true; // We're going to stop, don't // change the stop info. @@ -382,20 +386,21 @@ protected: StoppointCallbackContext context(event_ptr, exe_ctx, false); // For safety's sake let's also grab an extra reference to the - // breakpoint owners of the locations we're going to examine, since - // the locations are going to have to get back to their breakpoints, - // and the locations don't keep their owners alive. I'm just - // sticking the BreakpointSP's in a vector since I'm only using it to - // locally increment their retain counts. + // breakpoint constituents of the locations we're going to examine, + // since the locations are going to have to get back to their + // breakpoints, and the locations don't keep their constituents alive. + // I'm just sticking the BreakpointSP's in a vector since I'm only + // using it to locally increment their retain counts. - std::vector location_owners; + std::vector location_constituents; - for (size_t j = 0; j < num_owners; j++) { + for (size_t j = 0; j < num_constituents; j++) { BreakpointLocationSP loc(site_locations.GetByIndex(j)); - location_owners.push_back(loc->GetBreakpoint().shared_from_this()); + location_constituents.push_back( + loc->GetBreakpoint().shared_from_this()); } - for (size_t j = 0; j < num_owners; j++) { + for (size_t j = 0; j < num_constituents; j++) { lldb::BreakpointLocationSP bp_loc_sp = site_locations.GetByIndex(j); StreamString loc_desc; if (log) { @@ -631,7 +636,7 @@ public: if (process_sp && watchpoint_sp) { const bool notify = false; watchpoint_sp->TurnOnEphemeralMode(); - process_sp->DisableWatchpoint(watchpoint_sp.get(), notify); + process_sp->DisableWatchpoint(watchpoint_sp, notify); process_sp->AddPreResumeAction(SentryPreResumeAction, this); } } @@ -642,9 +647,9 @@ public: watchpoint_sp->TurnOffEphemeralMode(); const bool notify = false; if (was_disabled) { - process_sp->DisableWatchpoint(watchpoint_sp.get(), notify); + process_sp->DisableWatchpoint(watchpoint_sp, notify); } else { - process_sp->EnableWatchpoint(watchpoint_sp.get(), notify); + process_sp->EnableWatchpoint(watchpoint_sp, notify); } } } @@ -707,7 +712,7 @@ protected: return true; if (!m_did_disable_wp) { - GetThread().GetProcess()->DisableWatchpoint(m_watch_sp.get(), false); + GetThread().GetProcess()->DisableWatchpoint(m_watch_sp, false); m_did_disable_wp = true; } return true; @@ -751,7 +756,7 @@ protected: if (!m_did_disable_wp) return; m_did_disable_wp = true; - GetThread().GetProcess()->EnableWatchpoint(m_watch_sp.get(), true); + GetThread().GetProcess()->EnableWatchpoint(m_watch_sp, true); } private: @@ -991,9 +996,10 @@ protected: Debugger &debugger = exe_ctx.GetTargetRef().GetDebugger(); StreamSP output_sp = debugger.GetAsyncOutputStream(); - wp_sp->DumpSnapshots(output_sp.get()); - output_sp->EOL(); - output_sp->Flush(); + if (wp_sp->DumpSnapshots(output_sp.get())) { + output_sp->EOL(); + output_sp->Flush(); + } } } else { @@ -1366,6 +1372,8 @@ StopInfoSP StopInfo::CreateStopReasonWithBreakpointSiteID(Thread &thread, return StopInfoSP(new StopInfoBreakpoint(thread, break_id, should_stop)); } +// LWP_TODO: We'll need a CreateStopReasonWithWatchpointResourceID akin +// to CreateStopReasonWithBreakpointSiteID StopInfoSP StopInfo::CreateStopReasonWithWatchpointID(Thread &thread, break_id_t watch_id, bool silently_continue) { diff --git a/lldb/source/Target/Target.cpp b/lldb/source/Target/Target.cpp index a6d7148c84e2..2e8d1dfdaa17 100644 --- a/lldb/source/Target/Target.cpp +++ b/lldb/source/Target/Target.cpp @@ -892,6 +892,18 @@ WatchpointSP Target::CreateWatchpoint(lldb::addr_t addr, size_t size, if (ABISP abi = m_process_sp->GetABI()) addr = abi->FixDataAddress(addr); + // LWP_TODO this sequence is looking for an existing watchpoint + // at the exact same user-specified address, disables the new one + // if addr/size/type match. If type/size differ, disable old one. + // This isn't correct, we need both watchpoints to use a shared + // WatchpointResource in the target, and expand the WatchpointResource + // to handle the needs of both Watchpoints. + // Also, even if the addresses don't match, they may need to be + // supported by the same WatchpointResource, e.g. a watchpoint + // watching 1 byte at 0x102 and a watchpoint watching 1 byte at 0x103. + // They're in the same word and must be watched by a single hardware + // watchpoint register. + std::unique_lock lock; this->GetWatchpointList().GetListMutex(lock); WatchpointSP matched_sp = m_watchpoint_list.FindByAddress(addr); @@ -907,7 +919,7 @@ WatchpointSP Target::CreateWatchpoint(lldb::addr_t addr, size_t size, wp_sp->SetEnabled(false, notify); } else { // Nil the matched watchpoint; we will be creating a new one. - m_process_sp->DisableWatchpoint(matched_sp.get(), notify); + m_process_sp->DisableWatchpoint(matched_sp, notify); m_watchpoint_list.Remove(matched_sp->GetID(), true); } } @@ -918,7 +930,7 @@ WatchpointSP Target::CreateWatchpoint(lldb::addr_t addr, size_t size, m_watchpoint_list.Add(wp_sp, true); } - error = m_process_sp->EnableWatchpoint(wp_sp.get(), notify); + error = m_process_sp->EnableWatchpoint(wp_sp, notify); LLDB_LOGF(log, "Target::%s (creation of watchpoint %s with id = %u)\n", __FUNCTION__, error.Success() ? "succeeded" : "failed", wp_sp->GetID()); @@ -927,11 +939,6 @@ WatchpointSP Target::CreateWatchpoint(lldb::addr_t addr, size_t size, // Enabling the watchpoint on the device side failed. Remove the said // watchpoint from the list maintained by the target instance. m_watchpoint_list.Remove(wp_sp->GetID(), true); - // See if we could provide more helpful error message. - if (!OptionGroupWatchpoint::IsWatchSizeSupported(size)) - error.SetErrorStringWithFormat( - "watch size of %" PRIu64 " is not supported", (uint64_t)size); - wp_sp.reset(); } else m_last_created_watchpoint = wp_sp; @@ -1231,7 +1238,7 @@ bool Target::RemoveAllWatchpoints(bool end_to_end) { if (!wp_sp) return false; - Status rc = m_process_sp->DisableWatchpoint(wp_sp.get()); + Status rc = m_process_sp->DisableWatchpoint(wp_sp); if (rc.Fail()) return false; } @@ -1260,7 +1267,7 @@ bool Target::DisableAllWatchpoints(bool end_to_end) { if (!wp_sp) return false; - Status rc = m_process_sp->DisableWatchpoint(wp_sp.get()); + Status rc = m_process_sp->DisableWatchpoint(wp_sp); if (rc.Fail()) return false; } @@ -1287,7 +1294,7 @@ bool Target::EnableAllWatchpoints(bool end_to_end) { if (!wp_sp) return false; - Status rc = m_process_sp->EnableWatchpoint(wp_sp.get()); + Status rc = m_process_sp->EnableWatchpoint(wp_sp); if (rc.Fail()) return false; } @@ -1350,7 +1357,7 @@ bool Target::DisableWatchpointByID(lldb::watch_id_t watch_id) { WatchpointSP wp_sp = m_watchpoint_list.FindByID(watch_id); if (wp_sp) { - Status rc = m_process_sp->DisableWatchpoint(wp_sp.get()); + Status rc = m_process_sp->DisableWatchpoint(wp_sp); if (rc.Success()) return true; @@ -1369,7 +1376,7 @@ bool Target::EnableWatchpointByID(lldb::watch_id_t watch_id) { WatchpointSP wp_sp = m_watchpoint_list.FindByID(watch_id); if (wp_sp) { - Status rc = m_process_sp->EnableWatchpoint(wp_sp.get()); + Status rc = m_process_sp->EnableWatchpoint(wp_sp); if (rc.Success()) return true; diff --git a/lldb/source/Target/ThreadPlanCallFunction.cpp b/lldb/source/Target/ThreadPlanCallFunction.cpp index 31027cd9e011..50dcb66b9719 100644 --- a/lldb/source/Target/ThreadPlanCallFunction.cpp +++ b/lldb/source/Target/ThreadPlanCallFunction.cpp @@ -291,10 +291,10 @@ bool ThreadPlanCallFunction::DoPlanExplainsStop(Event *event_ptr) { BreakpointSiteSP bp_site_sp; bp_site_sp = m_process.GetBreakpointSiteList().FindByID(break_site_id); if (bp_site_sp) { - uint32_t num_owners = bp_site_sp->GetNumberOfOwners(); + uint32_t num_owners = bp_site_sp->GetNumberOfConstituents(); bool is_internal = true; for (uint32_t i = 0; i < num_owners; i++) { - Breakpoint &bp = bp_site_sp->GetOwnerAtIndex(i)->GetBreakpoint(); + Breakpoint &bp = bp_site_sp->GetConstituentAtIndex(i)->GetBreakpoint(); LLDB_LOGF(log, "ThreadPlanCallFunction::PlanExplainsStop: hit " "breakpoint %d while calling function", diff --git a/lldb/source/Target/ThreadPlanStepOut.cpp b/lldb/source/Target/ThreadPlanStepOut.cpp index 7bf1d2a8b579..0a1e2ae605ef 100644 --- a/lldb/source/Target/ThreadPlanStepOut.cpp +++ b/lldb/source/Target/ThreadPlanStepOut.cpp @@ -322,7 +322,7 @@ bool ThreadPlanStepOut::DoPlanExplainsStop(Event *event_ptr) { // important to report the user breakpoint than the step out // completion. - if (site_sp->GetNumberOfOwners() == 1) + if (site_sp->GetNumberOfConstituents() == 1) return true; } return false; diff --git a/lldb/source/Target/ThreadPlanStepRange.cpp b/lldb/source/Target/ThreadPlanStepRange.cpp index 0d5144d7a46b..bb92adcae78b 100644 --- a/lldb/source/Target/ThreadPlanStepRange.cpp +++ b/lldb/source/Target/ThreadPlanStepRange.cpp @@ -400,14 +400,14 @@ bool ThreadPlanStepRange::NextRangeBreakpointExplainsStop( return false; else { // If we've hit the next branch breakpoint, then clear it. - size_t num_owners = bp_site_sp->GetNumberOfOwners(); + size_t num_constituents = bp_site_sp->GetNumberOfConstituents(); bool explains_stop = true; - // If all the owners are internal, then we are probably just stepping over - // this range from multiple threads, or multiple frames, so we want to + // If all the constituents are internal, then we are probably just stepping + // over this range from multiple threads, or multiple frames, so we want to // continue. If one is not internal, then we should not explain the stop, // and let the user breakpoint handle the stop. - for (size_t i = 0; i < num_owners; i++) { - if (!bp_site_sp->GetOwnerAtIndex(i)->GetBreakpoint().IsInternal()) { + for (size_t i = 0; i < num_constituents; i++) { + if (!bp_site_sp->GetConstituentAtIndex(i)->GetBreakpoint().IsInternal()) { explains_stop = false; break; } @@ -415,8 +415,8 @@ bool ThreadPlanStepRange::NextRangeBreakpointExplainsStop( LLDB_LOGF(log, "ThreadPlanStepRange::NextRangeBreakpointExplainsStop - Hit " "next range breakpoint which has %" PRIu64 - " owners - explains stop: %u.", - (uint64_t)num_owners, explains_stop); + " constituents - explains stop: %u.", + (uint64_t)num_constituents, explains_stop); ClearNextBranchBreakpoint(); return explains_stop; } diff --git a/lldb/source/Target/ThreadPlanStepUntil.cpp b/lldb/source/Target/ThreadPlanStepUntil.cpp index f63e97d3c402..ee0f803510e6 100644 --- a/lldb/source/Target/ThreadPlanStepUntil.cpp +++ b/lldb/source/Target/ThreadPlanStepUntil.cpp @@ -182,7 +182,7 @@ void ThreadPlanStepUntil::AnalyzeStop() { } else m_should_stop = false; - if (this_site->GetNumberOfOwners() == 1) + if (this_site->GetNumberOfConstituents() == 1) m_explains_stop = true; else m_explains_stop = false; @@ -228,7 +228,7 @@ void ThreadPlanStepUntil::AnalyzeStop() { // only breakpoint here, then we do explain the stop, and we'll // continue. If not then we should let higher plans handle this // stop. - if (this_site->GetNumberOfOwners() == 1) + if (this_site->GetNumberOfConstituents() == 1) m_explains_stop = true; else { m_should_stop = true; diff --git a/lldb/test/API/python_api/watchpoint/watchlocation/TestTargetWatchAddress.py b/lldb/test/API/python_api/watchpoint/watchlocation/TestTargetWatchAddress.py index bf31819d4070..cbab3c6382e4 100644 --- a/lldb/test/API/python_api/watchpoint/watchlocation/TestTargetWatchAddress.py +++ b/lldb/test/API/python_api/watchpoint/watchlocation/TestTargetWatchAddress.py @@ -135,5 +135,5 @@ class TargetWatchpointCreateByAddressPITestCase(TestBase): self.expect( error.GetCString(), exe=False, - substrs=["watch size of %d is not supported" % 365], + substrs=["Setting one of the watchpoint resources failed"], ) diff --git a/lldb/test/Shell/Watchpoint/Inputs/val.c b/lldb/test/Shell/Watchpoint/Inputs/val.c index 5c70375c9d0f..4a23ae5b1aa9 100644 --- a/lldb/test/Shell/Watchpoint/Inputs/val.c +++ b/lldb/test/Shell/Watchpoint/Inputs/val.c @@ -1,6 +1,9 @@ int main() { int val = 0; // Break here + val = 5; + val = 10; + val = 1; val++; val++; return 0; diff --git a/lldb/test/Shell/Watchpoint/LocalVariableWatchpointDisabler.test b/lldb/test/Shell/Watchpoint/LocalVariableWatchpointDisabler.test index dc2b6687964f..396b4a922fd8 100644 --- a/lldb/test/Shell/Watchpoint/LocalVariableWatchpointDisabler.test +++ b/lldb/test/Shell/Watchpoint/LocalVariableWatchpointDisabler.test @@ -1,3 +1,10 @@ # REQUIRES: system-darwin +# TODO: This test is breaking with my output +# reformatting done for Large Watchpoint support, +# but the lines being output by lldb are identical, +# by visual inspection. +# FileCheck is seeing some difference between them, +# which I need to get to the bottom of. +# UNSUPPORTED: system-darwin # RUN: %clang_host -x c %S/Inputs/val.c -g -o %t # RUN: %lldb -b -s %S/Inputs/watchpoint.in %t 2>&1 | FileCheck %S/Inputs/watchpoint.in diff --git a/lldb/test/Shell/Watchpoint/SetErrorCases.test b/lldb/test/Shell/Watchpoint/SetErrorCases.test index cc67d0adfc3f..6020186b9e3f 100644 --- a/lldb/test/Shell/Watchpoint/SetErrorCases.test +++ b/lldb/test/Shell/Watchpoint/SetErrorCases.test @@ -25,4 +25,4 @@ watchpoint set expression MyAggregateDataType # CHECK: error: expression did not evaluate to an address watchpoint set variable -s -128 -# CHECK: error: invalid enumeration value +# CHECK: error: invalid --size option value -- GitLab From 162e4b8c494459ea7509f598d15addd6ffc3dc9c Mon Sep 17 00:00:00 2001 From: Jason Molenda Date: Mon, 27 Nov 2023 13:39:24 -0800 Subject: [PATCH 060/699] Include in WatchpointResource.h On macOS was already included via another header file, but this failed on the CI bots. I'd tested on linux earlier in this patch's life when the headers were differently arranged. (cherry picked from commit a0a1ff3ab40e347589b4e27d8fd350c600526735) --- lldb/include/lldb/Breakpoint/WatchpointResource.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lldb/include/lldb/Breakpoint/WatchpointResource.h b/lldb/include/lldb/Breakpoint/WatchpointResource.h index e83ba0bbe8c6..4b1d733850f1 100644 --- a/lldb/include/lldb/Breakpoint/WatchpointResource.h +++ b/lldb/include/lldb/Breakpoint/WatchpointResource.h @@ -13,7 +13,7 @@ #include "lldb/lldb-public.h" #include -#include +#include namespace lldb_private { -- GitLab From 22f72642fe6cd8f049bc905e0f0a69243b650f89 Mon Sep 17 00:00:00 2001 From: Nico Weber Date: Tue, 28 Nov 2023 08:52:23 +0900 Subject: [PATCH 061/699] [lldb] try to fix build on linux after fc6b72523f3d7 Tries to fix: ../../lldb/source/Breakpoint/WatchpointResource.cpp:59:12: error: no member named 'find' in namespace 'std'; did you mean 'fill'? std::find(m_constituents.begin(), m_constituents.end(), wp_sp); ~~~~~^~~~ fill (cherry picked from commit a6c62bf1a4717accc852463b664cd1012237d334) --- lldb/source/Breakpoint/WatchpointResource.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/lldb/source/Breakpoint/WatchpointResource.cpp b/lldb/source/Breakpoint/WatchpointResource.cpp index 4b8fbe42c865..d0f8dc346f3c 100644 --- a/lldb/source/Breakpoint/WatchpointResource.cpp +++ b/lldb/source/Breakpoint/WatchpointResource.cpp @@ -10,6 +10,8 @@ #include "lldb/Breakpoint/WatchpointResource.h" +#include + using namespace lldb; using namespace lldb_private; -- GitLab From 9e77d666d88d407a7705caa623f7bfc8dc90287d Mon Sep 17 00:00:00 2001 From: Jason Molenda Date: Thu, 30 Nov 2023 14:35:31 -0800 Subject: [PATCH 062/699] Correctly disable hardware watchpoints after a fork event Fix a failure on Linux system where follow-fork-mode exists, which caused the large watchpoint NFC patch to be reverted earlier this week. --- lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp b/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp index fb6715140492..b04319703b94 100644 --- a/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp +++ b/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp @@ -5546,7 +5546,7 @@ void ProcessGDBRemote::DidForkSwitchHardwareTraps(bool enable) { addr_t addr = wp_res_sp->GetLoadAddress(); size_t size = wp_res_sp->GetByteSize(); GDBStoppointType type = GetGDBStoppointType(wp_res_sp); - m_gdb_comm.SendGDBStoppointTypePacket(type, true, addr, size, + m_gdb_comm.SendGDBStoppointTypePacket(type, enable, addr, size, GetInterruptTimeout()); } } -- GitLab From dd1e72c38f3f9fc457d12940b9bc594e43683c7c Mon Sep 17 00:00:00 2001 From: LLVM GN Syncbot Date: Thu, 30 Nov 2023 23:04:47 +0000 Subject: [PATCH 063/699] [gn build] Port c73a3f16f81a --- llvm/utils/gn/secondary/lldb/source/Breakpoint/BUILD.gn | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/llvm/utils/gn/secondary/lldb/source/Breakpoint/BUILD.gn b/llvm/utils/gn/secondary/lldb/source/Breakpoint/BUILD.gn index b8a06582e985..84163e47b2b6 100644 --- a/llvm/utils/gn/secondary/lldb/source/Breakpoint/BUILD.gn +++ b/llvm/utils/gn/secondary/lldb/source/Breakpoint/BUILD.gn @@ -29,12 +29,14 @@ static_library("Breakpoint") { "BreakpointResolverName.cpp", "BreakpointResolverScripted.cpp", "BreakpointSite.cpp", - "BreakpointSiteList.cpp", + "StopPointSiteList.cpp", "Stoppoint.cpp", "StoppointCallbackContext.cpp", "StoppointSite.cpp", "Watchpoint.cpp", "WatchpointList.cpp", "WatchpointOptions.cpp", + "WatchpointResource.cpp", + "WatchpointResourceList.cpp", ] } -- GitLab From 2ee8763fecad644c1b25bfdb06a884d291633009 Mon Sep 17 00:00:00 2001 From: "Stephan T. Lavavej" Date: Thu, 30 Nov 2023 15:06:24 -0800 Subject: [PATCH 064/699] [test] Fix expected line number in `TestRunner.py` (#73996) My #73541 added lines to `llvm/utils/lit/tests/Inputs/testrunner-custom-parsers/test.txt` so what was previously on line 7 is now on line 12. Before: https://github.com/llvm/llvm-project/blob/28412d1800e391c5ba8e7607bb15c74b106d581b/llvm/utils/lit/tests/Inputs/testrunner-custom-parsers/test.txt#L7-L8 After: https://github.com/llvm/llvm-project/blob/6fb7c2d713587a061cd281eda917746750559380/llvm/utils/lit/tests/Inputs/testrunner-custom-parsers/test.txt#L12-L13 This didn't show up in the PR checks, but caused a buildbot failure after merging, https://lab.llvm.org/buildbot/#/builders/139/builds/54597 : ``` # | ====================================================================== # | FAIL: test_commands (__main__.TestIntegratedTestKeywordParser) # | ---------------------------------------------------------------------- # | Traceback (most recent call last): # | File "/home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/build/utils/lit/tests/unit/TestRunner.py", line 135, in test_commands # | self.assertEqual(value[1].command.strip(), "%dbg(MY_RUN: at line 7) foo bar") # | AssertionError: '%dbg(MY_RUN: at line 12) foo bar' != '%dbg(MY_RUN: at line 7) foo bar' # | - %dbg(MY_RUN: at line 12) foo bar # | ? ^^ # | + %dbg(MY_RUN: at line 7) foo bar # | ? ^ ``` Apologies for the build break :scream_cat: --- llvm/utils/lit/tests/unit/TestRunner.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/utils/lit/tests/unit/TestRunner.py b/llvm/utils/lit/tests/unit/TestRunner.py index f1baf51c02f3..09470c7b9386 100644 --- a/llvm/utils/lit/tests/unit/TestRunner.py +++ b/llvm/utils/lit/tests/unit/TestRunner.py @@ -132,7 +132,7 @@ class TestIntegratedTestKeywordParser(unittest.TestCase): value = cmd_parser.getValue() self.assertEqual(len(value), 2) # there are only two run lines self.assertEqual(value[0].command.strip(), "%dbg(MY_RUN: at line 4) baz") - self.assertEqual(value[1].command.strip(), "%dbg(MY_RUN: at line 7) foo bar") + self.assertEqual(value[1].command.strip(), "%dbg(MY_RUN: at line 12) foo bar") def test_boolean(self): parsers = self.make_parsers() -- GitLab From 4e724c2a214cc62fd024237f0bdf903ed8fbf45b Mon Sep 17 00:00:00 2001 From: Adrian Prantl Date: Wed, 29 Nov 2023 14:38:39 -0800 Subject: [PATCH 065/699] Revert "[DWARFv5] Verify all-or-nothing constraint on DIFile source" This reverts commit 4ed5195712fd1f3f43e23678d8f666c47d1aa7d5. --- llvm/lib/IR/Verifier.cpp | 18 -------- .../Assembler/debug-info-source-invalid.ll | 27 ------------ llvm/test/Assembler/debug-info-source.ll | 41 ------------------- 3 files changed, 86 deletions(-) delete mode 100644 llvm/test/Assembler/debug-info-source-invalid.ll delete mode 100644 llvm/test/Assembler/debug-info-source.ll diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp index 5560c037aa3e..5f466581ea98 100644 --- a/llvm/lib/IR/Verifier.cpp +++ b/llvm/lib/IR/Verifier.cpp @@ -329,9 +329,6 @@ class Verifier : public InstVisitor, VerifierSupport { /// The current source language. dwarf::SourceLanguage CurrentSourceLang = dwarf::DW_LANG_lo_user; - /// Whether source was present on the first DIFile encountered in each CU. - DenseMap HasSourceDebugInfo; - /// Stores the count of how many objects were passed to llvm.localescape for a /// given function and the largest index passed to llvm.localrecover. DenseMap> FrameEscapeInfo; @@ -620,9 +617,6 @@ private: void verifyAttachedCallBundle(const CallBase &Call, const OperandBundleUse &BU); - /// Verify all-or-nothing property of DIFile source attribute within a CU. - void verifySourceDebugInfo(const DICompileUnit &U, const DIFile &F); - /// Verify the llvm.experimental.noalias.scope.decl declarations void verifyNoAliasScopeDecl(); }; @@ -1352,8 +1346,6 @@ void Verifier::visitDICompileUnit(const DICompileUnit &N) { CurrentSourceLang = (dwarf::SourceLanguage)N.getSourceLanguage(); - verifySourceDebugInfo(N, *N.getFile()); - CheckDI((N.getEmissionKind() <= DICompileUnit::LastEmissionKind), "invalid emission kind", &N); @@ -1442,8 +1434,6 @@ void Verifier::visitDISubprogram(const DISubprogram &N) { "definition subprograms cannot be nested within DICompositeType " "when enabling ODR", &N); - if (N.getFile()) - verifySourceDebugInfo(*N.getUnit(), *N.getFile()); } else { // Subprogram declarations (part of the type hierarchy). CheckDI(!Unit, "subprogram declarations must not have a compile unit", &N); @@ -6590,14 +6580,6 @@ void Verifier::verifyAttachedCallBundle(const CallBase &Call, } } -void Verifier::verifySourceDebugInfo(const DICompileUnit &U, const DIFile &F) { - bool HasSource = F.getSource().has_value(); - if (!HasSourceDebugInfo.count(&U)) - HasSourceDebugInfo[&U] = HasSource; - CheckDI(HasSource == HasSourceDebugInfo[&U], - "inconsistent use of embedded source"); -} - void Verifier::verifyNoAliasScopeDecl() { if (NoAliasScopeDecls.empty()) return; diff --git a/llvm/test/Assembler/debug-info-source-invalid.ll b/llvm/test/Assembler/debug-info-source-invalid.ll deleted file mode 100644 index d746e9e25fc3..000000000000 --- a/llvm/test/Assembler/debug-info-source-invalid.ll +++ /dev/null @@ -1,27 +0,0 @@ -; RUN: llvm-as < %s 2>&1 >/dev/null | FileCheck %s - -; Ensure we reject debug info where the DIFiles of a DICompileUnit mix source -; and no-source. - -define dso_local void @foo() !dbg !5 { - ret void -} - -define dso_local void @bar() !dbg !6 { - ret void -} - -!llvm.dbg.cu = !{!4} -!llvm.module.flags = !{!0, !1} - -!0 = !{i32 2, !"Dwarf Version", i32 5} -!1 = !{i32 2, !"Debug Info Version", i32 3} - -!2 = !DIFile(filename: "foo.c", directory: "dir", source: "void foo() { }\0A") -; CHECK: inconsistent use of embedded source -; CHECK: warning: ignoring invalid debug info -!3 = !DIFile(filename: "bar.h", directory: "dir") - -!4 = distinct !DICompileUnit(language: DW_LANG_C99, file: !2) -!5 = distinct !DISubprogram(name: "foo", file: !2, unit: !4) -!6 = distinct !DISubprogram(name: "bar", file: !3, unit: !4) diff --git a/llvm/test/Assembler/debug-info-source.ll b/llvm/test/Assembler/debug-info-source.ll deleted file mode 100644 index 381603ef35c3..000000000000 --- a/llvm/test/Assembler/debug-info-source.ll +++ /dev/null @@ -1,41 +0,0 @@ -; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s -; RUN: verify-uselistorder %s - -; Ensure we accept debug info where DIFiles within a DICompileUnit either all -; have source, or none have source. - -define dso_local void @foo() !dbg !6 { - ret void -} - -define dso_local void @bar() !dbg !7 { - ret void -} - -define dso_local void @baz() !dbg !9 { - ret void -} - -define dso_local void @qux() !dbg !11 { - ret void -} - -!llvm.dbg.cu = !{!0, !2} -!llvm.module.flags = !{!4, !5} - -!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1) -; CHECK: !1 = !DIFile(filename: "foo.c", directory: "dir", source: "void foo() { }\0A") -!1 = !DIFile(filename: "foo.c", directory: "dir", source: "void foo() { }\0A") -!2 = distinct !DICompileUnit(language: DW_LANG_C99, file: !3) -; CHECK: !3 = !DIFile(filename: "qux.h", directory: "dir") -!3 = !DIFile(filename: "qux.h", directory: "dir") -!4 = !{i32 2, !"Dwarf Version", i32 5} -!5 = !{i32 2, !"Debug Info Version", i32 3} -!6 = distinct !DISubprogram(name: "foo", file: !1, unit: !0) -!7 = distinct !DISubprogram(name: "bar", file: !8, unit: !0) -; CHECK: !8 = !DIFile(filename: "bar.h", directory: "dir", source: "void bar() { }\0A") -!8 = !DIFile(filename: "bar.h", directory: "dir", source: "void bar() { }\0A") -!9 = distinct !DISubprogram(name: "baz", file: !10, unit: !2) -; CHECK: !10 = !DIFile(filename: "baz.c", directory: "dir") -!10 = !DIFile(filename: "baz.c", directory: "dir") -!11 = distinct !DISubprogram(name: "qux", file: !3, unit: !2) -- GitLab From 87e22bdd2bd6d77d782f9d64b3e3ae5bdcd5080d Mon Sep 17 00:00:00 2001 From: Adrian Prantl Date: Wed, 29 Nov 2023 16:01:37 -0800 Subject: [PATCH 066/699] Allow for mixing source/no-source DIFiles in one CU The DWARF proposal that the DW_LNCT_LLVM_source extension is based on (https://dwarfstd.org/issues/180201.1.html) allows to mix source and non-source files in the same CU by storing an empty string as a sentinel value. This patch implements this feature. Review in https://github.com/llvm/llvm-project/pull/73877 --- llvm/include/llvm/MC/MCDwarf.h | 9 ++--- llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp | 11 ++++-- llvm/lib/MC/MCDwarf.cpp | 23 +++++-------- llvm/test/DebugInfo/Generic/mixed-source.ll | 37 +++++++++++++++++++++ 4 files changed, 59 insertions(+), 21 deletions(-) create mode 100644 llvm/test/DebugInfo/Generic/mixed-source.ll diff --git a/llvm/include/llvm/MC/MCDwarf.h b/llvm/include/llvm/MC/MCDwarf.h index 715714f8e55d..18056c5fdf81 100644 --- a/llvm/include/llvm/MC/MCDwarf.h +++ b/llvm/include/llvm/MC/MCDwarf.h @@ -265,7 +265,8 @@ struct MCDwarfLineTableHeader { StringMap SourceIdMap; std::string CompilationDir; MCDwarfFile RootFile; - bool HasSource = false; + bool HasAnySource = false; + private: bool HasAllMD5 = true; bool HasAnyMD5 = false; @@ -305,7 +306,7 @@ public: RootFile.Checksum = Checksum; RootFile.Source = Source; trackMD5Usage(Checksum.has_value()); - HasSource = Source.has_value(); + HasAnySource |= Source.has_value(); } void resetFileTable() { @@ -313,7 +314,7 @@ public: MCDwarfFiles.clear(); RootFile.Name.clear(); resetMD5Usage(); - HasSource = false; + HasAnySource = false; } private: @@ -385,7 +386,7 @@ public: Header.RootFile.Checksum = Checksum; Header.RootFile.Source = Source; Header.trackMD5Usage(Checksum.has_value()); - Header.HasSource = Source.has_value(); + Header.HasAnySource |= Source.has_value(); } void resetFileTable() { Header.resetFileTable(); } diff --git a/llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp b/llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp index 6f2afe5d50e9..78792cf83891 100644 --- a/llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp +++ b/llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp @@ -170,9 +170,14 @@ void DWARFDebugLine::Prologue::dump(raw_ostream &OS, if (ContentTypes.HasLength) OS << format(" length: 0x%8.8" PRIx64 "\n", FileEntry.Length); if (ContentTypes.HasSource) { - OS << " source: "; - FileEntry.Source.dump(OS, DumpOptions); - OS << '\n'; + auto Source = FileEntry.Source.getAsCString(); + if (!Source) + consumeError(Source.takeError()); + else if ((*Source)[0]) { + OS << " source: "; + FileEntry.Source.dump(OS, DumpOptions); + OS << '\n'; + } } } } diff --git a/llvm/lib/MC/MCDwarf.cpp b/llvm/lib/MC/MCDwarf.cpp index 7925fba876f8..f94fc48a033d 100644 --- a/llvm/lib/MC/MCDwarf.cpp +++ b/llvm/lib/MC/MCDwarf.cpp @@ -386,7 +386,7 @@ void MCDwarfLineTableHeader::emitV2FileDirTables(MCStreamer *MCOS) const { } static void emitOneV5FileEntry(MCStreamer *MCOS, const MCDwarfFile &DwarfFile, - bool EmitMD5, bool HasSource, + bool EmitMD5, bool HasAnySource, std::optional &LineStr) { assert(!DwarfFile.Name.empty()); if (LineStr) @@ -401,7 +401,7 @@ static void emitOneV5FileEntry(MCStreamer *MCOS, const MCDwarfFile &DwarfFile, MCOS->emitBinaryData( StringRef(reinterpret_cast(Cksum.data()), Cksum.size())); } - if (HasSource) { + if (HasAnySource) { if (LineStr) LineStr->emitRef(MCOS, DwarfFile.Source.value_or(StringRef())); else { @@ -452,7 +452,7 @@ void MCDwarfLineTableHeader::emitV5FileDirTables( uint64_t Entries = 2; if (HasAllMD5) Entries += 1; - if (HasSource) + if (HasAnySource) Entries += 1; MCOS->emitInt8(Entries); MCOS->emitULEB128IntValue(dwarf::DW_LNCT_path); @@ -464,7 +464,7 @@ void MCDwarfLineTableHeader::emitV5FileDirTables( MCOS->emitULEB128IntValue(dwarf::DW_LNCT_MD5); MCOS->emitULEB128IntValue(dwarf::DW_FORM_data16); } - if (HasSource) { + if (HasAnySource) { MCOS->emitULEB128IntValue(dwarf::DW_LNCT_LLVM_source); MCOS->emitULEB128IntValue(LineStr ? dwarf::DW_FORM_line_strp : dwarf::DW_FORM_string); @@ -479,9 +479,9 @@ void MCDwarfLineTableHeader::emitV5FileDirTables( assert((!RootFile.Name.empty() || MCDwarfFiles.size() >= 1) && "No root file and no .file directives"); emitOneV5FileEntry(MCOS, RootFile.Name.empty() ? MCDwarfFiles[1] : RootFile, - HasAllMD5, HasSource, LineStr); + HasAllMD5, HasAnySource, LineStr); for (unsigned i = 1; i < MCDwarfFiles.size(); ++i) - emitOneV5FileEntry(MCOS, MCDwarfFiles[i], HasAllMD5, HasSource, LineStr); + emitOneV5FileEntry(MCOS, MCDwarfFiles[i], HasAllMD5, HasAnySource, LineStr); } std::pair @@ -598,7 +598,7 @@ MCDwarfLineTableHeader::tryGetFile(StringRef &Directory, StringRef &FileName, // If any files have embedded source, they all must. if (MCDwarfFiles.empty()) { trackMD5Usage(Checksum.has_value()); - HasSource = (Source != std::nullopt); + HasAnySource |= Source.has_value(); } if (DwarfVersion >= 5 && isRootFile(RootFile, Directory, FileName, Checksum)) return 0; @@ -625,11 +625,6 @@ MCDwarfLineTableHeader::tryGetFile(StringRef &Directory, StringRef &FileName, return make_error("file number already allocated", inconvertibleErrorCode()); - // If any files have embedded source, they all must. - if (HasSource != (Source != std::nullopt)) - return make_error("inconsistent use of embedded source", - inconvertibleErrorCode()); - if (Directory.empty()) { // Separate the directory part from the basename of the FileName. StringRef tFileName = sys::path::filename(FileName); @@ -662,8 +657,8 @@ MCDwarfLineTableHeader::tryGetFile(StringRef &Directory, StringRef &FileName, File.Checksum = Checksum; trackMD5Usage(Checksum.has_value()); File.Source = Source; - if (Source) - HasSource = true; + if (Source.has_value()) + HasAnySource = true; // return the allocated FileNumber. return FileNumber; diff --git a/llvm/test/DebugInfo/Generic/mixed-source.ll b/llvm/test/DebugInfo/Generic/mixed-source.ll new file mode 100644 index 000000000000..46ea05c975f1 --- /dev/null +++ b/llvm/test/DebugInfo/Generic/mixed-source.ll @@ -0,0 +1,37 @@ +; RUN: %llc_dwarf -O0 -filetype=obj -o - < %s | llvm-dwarfdump -debug-line - | FileCheck %s + +; CHECK: include_directories[ 0] = "dir" +; CHECK-NEXT: file_names[ 0]: +; CHECK-NEXT: name: "foo.c" +; CHECK-NEXT: dir_index: 0 +; CHECK-NEXT: source: "void foo() { }\n" +; CHECK-NEXT: file_names[ 1]: +; CHECK-NEXT: name: "bar.h" +; CHECK-NEXT: dir_index: 0 +; CHECK-NOT: source: + +; Test that DIFiles mixing source and no-source within a DICompileUnit works. + +define dso_local void @foo() !dbg !5 { + ret void, !dbg !7 +} + +define dso_local void @bar() !dbg !6 { + ret void, !dbg !8 +} + +!llvm.dbg.cu = !{!4} +!llvm.module.flags = !{!0, !1} + +!0 = !{i32 2, !"Dwarf Version", i32 5} +!1 = !{i32 2, !"Debug Info Version", i32 3} + +!2 = !DIFile(filename: "foo.c", directory: "dir", source: "void foo() { }\0A") +!3 = !DIFile(filename: "bar.h", directory: "dir") + +!4 = distinct !DICompileUnit(language: DW_LANG_C99, emissionKind: FullDebug, file: !2) +!5 = distinct !DISubprogram(name: "foo", file: !2, line: 1, type: !9, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !4) +!6 = distinct !DISubprogram(name: "bar", file: !3, line: 1, type: !9, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !4) +!7 = !DILocation(line: 1, scope: !5) +!8 = !DILocation(line: 1, scope: !6) +!9 = !DISubroutineType(types: !{}) -- GitLab From 4bf8a688956a759b7b6b8d94f42d25c13c7af130 Mon Sep 17 00:00:00 2001 From: Arthur Eubanks Date: Tue, 28 Nov 2023 12:55:17 -0800 Subject: [PATCH 067/699] Reland [X86] With large code model, put functions into .ltext with large section flag (#73037) So that when mixing small and large text, large text stays out of the way of the rest of the binary. This is useful for mixing precompiled small code model object files and built-from-source large code model binaries so that the the text sections don't get merged. The reland fixes an issue where a function in the large code model would reference small data without GOTOFF. --- llvm/include/llvm/Target/TargetMachine.h | 2 +- .../CodeGen/TargetLoweringObjectFileImpl.cpp | 15 ++------ llvm/lib/Target/TargetMachine.cpp | 12 +++++- llvm/lib/Target/X86/X86Subtarget.cpp | 38 +++++++------------ .../X86/code-model-elf-text-sections.ll | 25 ++++++++++++ llvm/test/CodeGen/X86/code-model-elf.ll | 1 + llvm/test/CodeGen/X86/pcsections.ll | 22 +++++------ .../OrcLazy/debug-objects-elf-minimal.ll | 2 +- 8 files changed, 66 insertions(+), 51 deletions(-) create mode 100644 llvm/test/CodeGen/X86/code-model-elf-text-sections.ll diff --git a/llvm/include/llvm/Target/TargetMachine.h b/llvm/include/llvm/Target/TargetMachine.h index c1d05b25ea21..4830ecbe1cd6 100644 --- a/llvm/include/llvm/Target/TargetMachine.h +++ b/llvm/include/llvm/Target/TargetMachine.h @@ -239,7 +239,7 @@ public: void setCodeModel(CodeModel::Model CM) { CMModel = CM; } void setLargeDataThreshold(uint64_t LDT) { LargeDataThreshold = LDT; } - bool isLargeData(const GlobalVariable *GV) const; + bool isLargeGlobalObject(const GlobalObject *GO) const; bool isPositionIndependent() const; diff --git a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp index f3ba38081890..143a4951c136 100644 --- a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp +++ b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp @@ -616,7 +616,7 @@ static unsigned getEntrySizeForKind(SectionKind Kind) { /// DataSections. static StringRef getSectionPrefixForGlobal(SectionKind Kind, bool IsLarge) { if (Kind.isText()) - return ".text"; + return IsLarge ? ".ltext" : ".text"; if (Kind.isReadOnly()) return IsLarge ? ".lrodata" : ".rodata"; if (Kind.isBSS()) @@ -650,10 +650,7 @@ getELFSectionNameForGlobal(const GlobalObject *GO, SectionKind Kind, Name = ".rodata.cst"; Name += utostr(EntrySize); } else { - bool IsLarge = false; - if (auto *GV = dyn_cast(GO)) - IsLarge = TM.isLargeData(GV); - Name = getSectionPrefixForGlobal(Kind, IsLarge); + Name = getSectionPrefixForGlobal(Kind, TM.isLargeGlobalObject(GO)); } bool HasPrefix = false; @@ -773,12 +770,8 @@ getGlobalObjectInfo(const GlobalObject *GO, const TargetMachine &TM) { Group = C->getName(); IsComdat = C->getSelectionKind() == Comdat::Any; } - if (auto *GV = dyn_cast(GO)) { - if (TM.isLargeData(GV)) { - assert(TM.getTargetTriple().getArch() == Triple::x86_64); - Flags |= ELF::SHF_X86_64_LARGE; - } - } + if (TM.isLargeGlobalObject(GO)) + Flags |= ELF::SHF_X86_64_LARGE; return {Group, IsComdat, Flags}; } diff --git a/llvm/lib/Target/TargetMachine.cpp b/llvm/lib/Target/TargetMachine.cpp index 1cba8cf8004b..f7096b708b39 100644 --- a/llvm/lib/Target/TargetMachine.cpp +++ b/llvm/lib/Target/TargetMachine.cpp @@ -39,13 +39,21 @@ TargetMachine::TargetMachine(const Target &T, StringRef DataLayoutString, TargetMachine::~TargetMachine() = default; -bool TargetMachine::isLargeData(const GlobalVariable *GV) const { - if (getTargetTriple().getArch() != Triple::x86_64 || GV->isThreadLocal()) +bool TargetMachine::isLargeGlobalObject(const GlobalObject *GO) const { + if (getTargetTriple().getArch() != Triple::x86_64) return false; if (getCodeModel() != CodeModel::Medium && getCodeModel() != CodeModel::Large) return false; + if (isa(GO)) + return getCodeModel() == CodeModel::Large; + + auto *GV = cast(GO); + + if (GV->isThreadLocal()) + return false; + // Allowing large metadata sections in the presence of an explicit section is // useful, even if GCC does not allow them. However, we should not mark // certain well-known prefixes as large, because it would make the whole diff --git a/llvm/lib/Target/X86/X86Subtarget.cpp b/llvm/lib/Target/X86/X86Subtarget.cpp index 085fdafa6b9f..328608363a8f 100644 --- a/llvm/lib/Target/X86/X86Subtarget.cpp +++ b/llvm/lib/Target/X86/X86Subtarget.cpp @@ -83,32 +83,20 @@ X86Subtarget::classifyLocalReference(const GlobalValue *GV) const { if (is64Bit()) { // 64-bit ELF PIC local references may use GOTOFF relocations. if (isTargetELF()) { - switch (TM.getCodeModel()) { - // 64-bit small code model is simple: All rip-relative. - case CodeModel::Tiny: - llvm_unreachable("Tiny codesize model not supported on X86"); - case CodeModel::Small: - case CodeModel::Kernel: - return X86II::MO_NO_FLAG; - - // The large PIC code model uses GOTOFF. - case CodeModel::Large: + CodeModel::Model CM = TM.getCodeModel(); + assert(CM != CodeModel::Tiny && + "Tiny codesize model not supported on X86"); + // In the large code model, even referencing a global under the large data + // threshold which is considered "small", we need to use GOTOFF. + if (CM == CodeModel::Large) return X86II::MO_GOTOFF; - - // Medium is a hybrid: RIP-rel for code and non-large data, GOTOFF for - // remaining DSO local data. - case CodeModel::Medium: - // Constant pool and jump table handling pass a nullptr to this - // function so we need to use isa_and_nonnull. - if (isa_and_nonnull(GV)) - return X86II::MO_NO_FLAG; // All code is RIP-relative - if (auto *GVar = dyn_cast_or_null(GV)) { - if (TM.isLargeData(GVar)) - return X86II::MO_GOTOFF; - } - return X86II::MO_NO_FLAG; // Local symbols use GOTOFF. - } - llvm_unreachable("invalid code model"); + // Large objects use GOTOFF, otherwise use RIP-rel access. + if (auto *GO = dyn_cast_or_null(GV)) + return TM.isLargeGlobalObject(GO) ? X86II::MO_GOTOFF + : X86II::MO_NO_FLAG; + // For non-GlobalObjects, the small and medium code models treat them as + // accessible with a RIP-rel access. + return X86II::MO_NO_FLAG; } // Otherwise, this is either a RIP-relative reference or a 64-bit movabsq, diff --git a/llvm/test/CodeGen/X86/code-model-elf-text-sections.ll b/llvm/test/CodeGen/X86/code-model-elf-text-sections.ll new file mode 100644 index 000000000000..016c9a4d7b83 --- /dev/null +++ b/llvm/test/CodeGen/X86/code-model-elf-text-sections.ll @@ -0,0 +1,25 @@ +; RUN: llc < %s -relocation-model=pic -filetype=obj -code-model=small -o %t +; RUN: llvm-readelf -S %t | FileCheck %s --check-prefix=SMALL +; RUN: llc < %s -relocation-model=pic -filetype=obj -code-model=medium -o %t +; RUN: llvm-readelf -S %t | FileCheck %s --check-prefix=SMALL +; RUN: llc < %s -relocation-model=pic -filetype=obj -code-model=large -o %t +; RUN: llvm-readelf -S %t | FileCheck %s --check-prefix=LARGE + +; RUN: llc < %s -relocation-model=pic -filetype=obj -code-model=small -function-sections -o %t +; RUN: llvm-readelf -S %t | FileCheck %s --check-prefix=SMALL-DS +; RUN: llc < %s -relocation-model=pic -filetype=obj -code-model=medium -function-sections -o %t +; RUN: llvm-readelf -S %t | FileCheck %s --check-prefix=SMALL-DS +; RUN: llc < %s -relocation-model=pic -filetype=obj -code-model=large -function-sections -o %t +; RUN: llvm-readelf -S %t | FileCheck %s --check-prefix=LARGE-DS + +; SMALL: .text {{.*}} AX {{.*}} +; SMALL-DS: .text.func {{.*}} AX {{.*}} +; LARGE: .ltext {{.*}} AXl {{.*}} +; LARGE-DS: .ltext.func {{.*}} AXl {{.*}} + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64--linux" + +define void @func() { + ret void +} diff --git a/llvm/test/CodeGen/X86/code-model-elf.ll b/llvm/test/CodeGen/X86/code-model-elf.ll index 901a62d26f77..483ffd87ac69 100644 --- a/llvm/test/CodeGen/X86/code-model-elf.ll +++ b/llvm/test/CodeGen/X86/code-model-elf.ll @@ -9,6 +9,7 @@ ; RUN: llc -verify-machineinstrs < %s -relocation-model=pic -code-model=medium -large-data-threshold=1000 | FileCheck %s --check-prefix=CHECK --check-prefix=MEDIUM-SMALL-DATA-PIC ; RUN: llc -verify-machineinstrs < %s -relocation-model=pic -code-model=medium | FileCheck %s --check-prefix=CHECK --check-prefix=MEDIUM-PIC ; RUN: llc -verify-machineinstrs < %s -relocation-model=pic -code-model=large | FileCheck %s --check-prefix=CHECK --check-prefix=LARGE-PIC +; RUN: llc -verify-machineinstrs < %s -relocation-model=pic -code-model=large -large-data-threshold=1000 | FileCheck %s --check-prefix=CHECK --check-prefix=LARGE-PIC ; Generated from this C source: ; diff --git a/llvm/test/CodeGen/X86/pcsections.ll b/llvm/test/CodeGen/X86/pcsections.ll index 00c1aba18cb4..4fe70d93cf34 100644 --- a/llvm/test/CodeGen/X86/pcsections.ll +++ b/llvm/test/CodeGen/X86/pcsections.ll @@ -19,12 +19,12 @@ define void @empty_no_aux() !pcsections !0 { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: retq ; CHECK-NEXT: .Lfunc_end0: -; CHECK: .section section_no_aux,"awo",@progbits,.text +; CHECK: .section section_no_aux,"awo",@progbits,.{{l?}}text ; CHECK-NEXT: .Lpcsection_base0: ; DEFCM-NEXT: .long .Lfunc_begin0-.Lpcsection_base0 ; LARGE-NEXT: .quad .Lfunc_begin0-.Lpcsection_base0 ; CHECK-NEXT: .long .Lfunc_end0-.Lfunc_begin0 -; CHECK-NEXT: .text +; CHECK-NEXT: .{{l?}}text entry: ret void } @@ -35,7 +35,7 @@ define void @empty_aux() !pcsections !1 { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: retq ; CHECK-NEXT: .Lfunc_end1: -; CHECK: .section section_aux,"awo",@progbits,.text +; CHECK: .section section_aux,"awo",@progbits,.{{l?}}text ; CHECK-NEXT: .Lpcsection_base1: ; DEFCM-NEXT: .long .Lfunc_begin1-.Lpcsection_base1 ; LARGE-NEXT: .quad .Lfunc_begin1-.Lpcsection_base1 @@ -43,7 +43,7 @@ define void @empty_aux() !pcsections !1 { ; CHECK-NEXT: .long 10 ; CHECK-NEXT: .long 20 ; CHECK-NEXT: .long 30 -; CHECK-NEXT: .text +; CHECK-NEXT: .{{l?}}text entry: ret void } @@ -56,22 +56,22 @@ define i64 @multiple() !pcsections !0 { ; CHECK-NEXT: movq ; CHECK-NEXT: retq ; CHECK-NEXT: .Lfunc_end2: -; CHECK: .section section_no_aux,"awo",@progbits,.text +; CHECK: .section section_no_aux,"awo",@progbits,.{{l?}}text ; CHECK-NEXT: .Lpcsection_base2: ; DEFCM-NEXT: .long .Lfunc_begin2-.Lpcsection_base2 ; LARGE-NEXT: .quad .Lfunc_begin2-.Lpcsection_base2 ; CHECK-NEXT: .long .Lfunc_end2-.Lfunc_begin2 -; CHECK-NEXT: .section section_aux_42,"awo",@progbits,.text +; CHECK-NEXT: .section section_aux_42,"awo",@progbits,.{{l?}}text ; CHECK-NEXT: .Lpcsection_base3: ; DEFCM-NEXT: .long .Lpcsection0-.Lpcsection_base3 ; LARGE-NEXT: .quad .Lpcsection0-.Lpcsection_base3 ; CHECK-NEXT: .long 42 -; CHECK-NEXT: .section section_aux_21264,"awo",@progbits,.text +; CHECK-NEXT: .section section_aux_21264,"awo",@progbits,.{{l?}}text ; CHECK-NEXT: .Lpcsection_base4: ; DEFCM-NEXT: .long .Lpcsection0-.Lpcsection_base4 ; LARGE-NEXT: .quad .Lpcsection0-.Lpcsection_base4 ; CHECK-NEXT: .long 21264 -; CHECK-NEXT: .text +; CHECK-NEXT: .{{l?}}text entry: %0 = load i64, ptr @bar, align 8, !pcsections !2 ret i64 %0 @@ -79,7 +79,7 @@ entry: define void @multiple_uleb128() !pcsections !6 { ; CHECK-LABEL: multiple_uleb128: -; CHECK: .section section_aux,"awo",@progbits,.text +; CHECK: .section section_aux,"awo",@progbits,.{{l?}}text ; CHECK-NEXT: .Lpcsection_base5: ; DEFCM-NEXT: .long .Lfunc_begin3-.Lpcsection_base5 ; LARGE-NEXT: .quad .Lfunc_begin3-.Lpcsection_base5 @@ -87,13 +87,13 @@ define void @multiple_uleb128() !pcsections !6 { ; CHECK-NEXT: .byte 42 ; CHECK-NEXT: .ascii "\345\216&" ; CHECK-NEXT: .byte 255 -; CHECK-NEXT: .section section_aux_21264,"awo",@progbits,.text +; CHECK-NEXT: .section section_aux_21264,"awo",@progbits,.{{l?}}text ; CHECK-NEXT: .Lpcsection_base6: ; DEFCM-NEXT: .long .Lfunc_begin3-.Lpcsection_base6 ; LARGE-NEXT: .quad .Lfunc_begin3-.Lpcsection_base6 ; CHECK-NEXT: .long .Lfunc_end3-.Lfunc_begin3 ; CHECK-NEXT: .long 21264 -; CHECK-NEXT: .text +; CHECK-NEXT: .{{l?}}text entry: ret void } diff --git a/llvm/test/ExecutionEngine/OrcLazy/debug-objects-elf-minimal.ll b/llvm/test/ExecutionEngine/OrcLazy/debug-objects-elf-minimal.ll index 0d5aba376080..d7bc2dc117b7 100644 --- a/llvm/test/ExecutionEngine/OrcLazy/debug-objects-elf-minimal.ll +++ b/llvm/test/ExecutionEngine/OrcLazy/debug-objects-elf-minimal.ll @@ -44,7 +44,7 @@ ; RUN: --generate=__dump_jit_debug_objects %s | llvm-objdump --section-headers - | \ ; RUN: FileCheck --check-prefix=CHECK_LOAD_ADDR %s ; -; CHECK_LOAD_ADDR-NOT: {{[0-9]*}} .text {{.*}} 0000000000000000 TEXT +; CHECK_LOAD_ADDR-NOT: {{[0-9]*}} .ltext {{.*}} 0000000000000000 TEXT target triple = "x86_64-unknown-unknown-elf" -- GitLab From 148dec9fa43b3a16b08169df8bdf3bbae24aa9b0 Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Thu, 30 Nov 2023 15:23:34 -0800 Subject: [PATCH 068/699] [OpenMP][NFC] Separate Envar (environment variable) handling (#73994) --- .../include/Shared/EnvironmentVar.h | 194 ++++++++++++++++++ openmp/libomptarget/include/Shared/Utils.h | 177 ---------------- .../plugins-nextgen/common/include/JIT.h | 23 +-- .../common/include/MemoryManager.h | 2 +- .../common/include/PluginInterface.h | 1 + openmp/libomptarget/src/device.cpp | 7 +- openmp/libomptarget/src/interface.cpp | 2 +- openmp/libomptarget/src/rtl.cpp | 2 +- 8 files changed, 212 insertions(+), 196 deletions(-) create mode 100644 openmp/libomptarget/include/Shared/EnvironmentVar.h diff --git a/openmp/libomptarget/include/Shared/EnvironmentVar.h b/openmp/libomptarget/include/Shared/EnvironmentVar.h new file mode 100644 index 000000000000..4cbdad695a0e --- /dev/null +++ b/openmp/libomptarget/include/Shared/EnvironmentVar.h @@ -0,0 +1,194 @@ +//===-- Shared/EnvironmentVar.h - Environment variable handling -*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +//===----------------------------------------------------------------------===// + +#ifndef OMPTARGET_SHARED_ENVIRONMENT_VAR_H +#define OMPTARGET_SHARED_ENVIRONMENT_VAR_H + +#include "Debug.h" + +#include "llvm/ADT/StringRef.h" +#include "llvm/Support/Error.h" + +#include +#include + +/// Utility class for parsing strings to other types. +struct StringParser { + /// Parse a string to another type. + template static bool parse(const char *Value, Ty &Result); +}; + +/// Class for reading and checking environment variables. Currently working with +/// integer, floats, std::string and bool types. +template class Envar { + Ty Data; + bool IsPresent; + bool Initialized; + +public: + /// Auxiliary function to safely create envars. This static function safely + /// creates envars using fallible constructors. See the constructors to know + /// more details about the creation parameters. + template + static llvm::Expected create(ArgsTy &&...Args) { + llvm::Error Err = llvm::Error::success(); + Envar Envar(std::forward(Args)..., Err); + if (Err) + return std::move(Err); + return std::move(Envar); + } + + /// Create an empty envar. Cannot be consulted. This constructor is merely + /// for convenience. This constructor is not fallible. + Envar() : Data(Ty()), IsPresent(false), Initialized(false) {} + + /// Create an envar with a name and an optional default. The Envar object will + /// take the value read from the environment variable, or the default if it + /// was not set or not correct. This constructor is not fallible. + Envar(llvm::StringRef Name, Ty Default = Ty()) + : Data(Default), IsPresent(false), Initialized(true) { + + if (const char *EnvStr = getenv(Name.data())) { + // Check whether the envar is defined and valid. + IsPresent = StringParser::parse(EnvStr, Data); + + if (!IsPresent) { + DP("Ignoring invalid value %s for envar %s\n", EnvStr, Name.data()); + Data = Default; + } + } + } + + Envar &operator=(const Ty &V) { + Data = V; + Initialized = true; + return *this; + } + + /// Get the definitive value. + const Ty &get() const { + // Throw a runtime error in case this envar is not initialized. + if (!Initialized) + FATAL_MESSAGE0(1, "Consulting envar before initialization"); + + return Data; + } + + /// Get the definitive value. + operator Ty() const { return get(); } + + /// Indicate whether the environment variable was defined and valid. + bool isPresent() const { return IsPresent; } + +private: + /// This constructor should never fail but we provide it for convenience. This + /// way, the constructor can be used by the Envar::create() static function + /// to safely create this kind of envars. + Envar(llvm::StringRef Name, Ty Default, llvm::Error &Err) + : Envar(Name, Default) { + llvm::ErrorAsOutParameter EAO(&Err); + Err = llvm::Error::success(); + } + + /// Create an envar with a name, getter function and a setter function. The + /// Envar object will take the value read from the environment variable if + /// this value is accepted by the setter function. Otherwise, the getter + /// function will be executed to get the default value. The getter should be + /// of the form Error GetterFunctionTy(Ty &Value) and the setter should + /// be of the form Error SetterFunctionTy(Ty Value). This constructor has a + /// private visibility because is a fallible constructor. Please use the + /// Envar::create() static function to safely create this object instead. + template + Envar(llvm::StringRef Name, GetterFunctor Getter, SetterFunctor Setter, + llvm::Error &Err) + : Data(Ty()), IsPresent(false), Initialized(true) { + llvm::ErrorAsOutParameter EAO(&Err); + Err = init(Name, Getter, Setter); + } + + template + llvm::Error init(llvm::StringRef Name, GetterFunctor Getter, + SetterFunctor Setter); +}; + +/// Define some common envar types. +using IntEnvar = Envar; +using Int32Envar = Envar; +using Int64Envar = Envar; +using UInt32Envar = Envar; +using UInt64Envar = Envar; +using StringEnvar = Envar; +using BoolEnvar = Envar; + +template <> +inline bool StringParser::parse(const char *ValueStr, bool &Result) { + std::string Value(ValueStr); + + // Convert the string to lowercase. + std::transform(Value.begin(), Value.end(), Value.begin(), + [](unsigned char c) { return std::tolower(c); }); + + // May be implemented with fancier C++ features, but let's keep it simple. + if (Value == "true" || Value == "yes" || Value == "on" || Value == "1") + Result = true; + else if (Value == "false" || Value == "no" || Value == "off" || Value == "0") + Result = false; + else + return false; + + // Parsed correctly. + return true; +} + +template +inline bool StringParser::parse(const char *Value, Ty &Result) { + assert(Value && "Parsed value cannot be null"); + + std::istringstream Stream(Value); + Stream >> Result; + + return !Stream.fail(); +} + +template +template +inline llvm::Error Envar::init(llvm::StringRef Name, GetterFunctor Getter, + SetterFunctor Setter) { + // Get the default value. + Ty Default; + if (llvm::Error Err = Getter(Default)) + return Err; + + if (const char *EnvStr = getenv(Name.data())) { + IsPresent = StringParser::parse(EnvStr, Data); + if (IsPresent) { + // Check whether the envar value is actually valid. + llvm::Error Err = Setter(Data); + if (Err) { + // The setter reported an invalid value. Mark the user-defined value as + // not present and reset to the getter value (default). + IsPresent = false; + Data = Default; + DP("Setter of envar %s failed, resetting to %s\n", Name.data(), + std::to_string(Data).data()); + consumeError(std::move(Err)); + } + } else { + DP("Ignoring invalid value %s for envar %s\n", EnvStr, Name.data()); + Data = Default; + } + } else { + Data = Default; + } + + return llvm::Error::success(); +} + +#endif // OMPTARGET_SHARED_ENVIRONMENT_VAR_H diff --git a/openmp/libomptarget/include/Shared/Utils.h b/openmp/libomptarget/include/Shared/Utils.h index b6bb97ce5949..fce14b54edb9 100644 --- a/openmp/libomptarget/include/Shared/Utils.h +++ b/openmp/libomptarget/include/Shared/Utils.h @@ -15,131 +15,18 @@ #define OMPTARGET_SHARED_UTILS_H #include "llvm/ADT/StringRef.h" -#include "llvm/Support/Error.h" #include "Debug.h" -#include #include #include -#include -#include -#include -#include #include #include -#include -#include namespace llvm { namespace omp { namespace target { -/// Utility class for parsing strings to other types. -struct StringParser { - /// Parse a string to another type. - template static bool parse(const char *Value, Ty &Result); -}; - -/// Class for reading and checking environment variables. Currently working with -/// integer, floats, std::string and bool types. -template class Envar { - Ty Data; - bool IsPresent; - bool Initialized; - -public: - /// Auxiliary function to safely create envars. This static function safely - /// creates envars using fallible constructors. See the constructors to know - /// more details about the creation parameters. - template - static Expected create(ArgsTy &&...Args) { - Error Err = Error::success(); - Envar Envar(std::forward(Args)..., Err); - if (Err) - return std::move(Err); - return std::move(Envar); - } - - /// Create an empty envar. Cannot be consulted. This constructor is merely - /// for convenience. This constructor is not fallible. - Envar() : Data(Ty()), IsPresent(false), Initialized(false) {} - - /// Create an envar with a name and an optional default. The Envar object will - /// take the value read from the environment variable, or the default if it - /// was not set or not correct. This constructor is not fallible. - Envar(StringRef Name, Ty Default = Ty()) - : Data(Default), IsPresent(false), Initialized(true) { - - if (const char *EnvStr = getenv(Name.data())) { - // Check whether the envar is defined and valid. - IsPresent = StringParser::parse(EnvStr, Data); - - if (!IsPresent) { - DP("Ignoring invalid value %s for envar %s\n", EnvStr, Name.data()); - Data = Default; - } - } - } - - Envar &operator=(const Ty &V) { - Data = V; - Initialized = true; - return *this; - } - - /// Get the definitive value. - const Ty &get() const { - // Throw a runtime error in case this envar is not initialized. - if (!Initialized) - FATAL_MESSAGE0(1, "Consulting envar before initialization"); - - return Data; - } - - /// Get the definitive value. - operator Ty() const { return get(); } - - /// Indicate whether the environment variable was defined and valid. - bool isPresent() const { return IsPresent; } - -private: - /// This constructor should never fail but we provide it for convenience. This - /// way, the constructor can be used by the Envar::create() static function - /// to safely create this kind of envars. - Envar(StringRef Name, Ty Default, Error &Err) : Envar(Name, Default) { - ErrorAsOutParameter EAO(&Err); - Err = Error::success(); - } - - /// Create an envar with a name, getter function and a setter function. The - /// Envar object will take the value read from the environment variable if - /// this value is accepted by the setter function. Otherwise, the getter - /// function will be executed to get the default value. The getter should be - /// of the form Error GetterFunctionTy(Ty &Value) and the setter should - /// be of the form Error SetterFunctionTy(Ty Value). This constructor has a - /// private visibility because is a fallible constructor. Please use the - /// Envar::create() static function to safely create this object instead. - template - Envar(StringRef Name, GetterFunctor Getter, SetterFunctor Setter, Error &Err) - : Data(Ty()), IsPresent(false), Initialized(true) { - ErrorAsOutParameter EAO(&Err); - Err = init(Name, Getter, Setter); - } - - template - Error init(StringRef Name, GetterFunctor Getter, SetterFunctor Setter); -}; - -/// Define some common envar types. -using IntEnvar = Envar; -using Int32Envar = Envar; -using Int64Envar = Envar; -using UInt32Envar = Envar; -using UInt64Envar = Envar; -using StringEnvar = Envar; -using BoolEnvar = Envar; - /// Utility class for thread-safe reference counting. Any class that needs /// objects' reference counting can inherit from this entity or have it as a /// class data member. @@ -170,70 +57,6 @@ private: std::atomic Refs; }; -template <> -inline bool StringParser::parse(const char *ValueStr, bool &Result) { - std::string Value(ValueStr); - - // Convert the string to lowercase. - std::transform(Value.begin(), Value.end(), Value.begin(), - [](unsigned char c) { return std::tolower(c); }); - - // May be implemented with fancier C++ features, but let's keep it simple. - if (Value == "true" || Value == "yes" || Value == "on" || Value == "1") - Result = true; - else if (Value == "false" || Value == "no" || Value == "off" || Value == "0") - Result = false; - else - return false; - - // Parsed correctly. - return true; -} - -template -inline bool StringParser::parse(const char *Value, Ty &Result) { - assert(Value && "Parsed value cannot be null"); - - std::istringstream Stream(Value); - Stream >> Result; - - return !Stream.fail(); -} - -template -template -inline Error Envar::init(StringRef Name, GetterFunctor Getter, - SetterFunctor Setter) { - // Get the default value. - Ty Default; - if (Error Err = Getter(Default)) - return Err; - - if (const char *EnvStr = getenv(Name.data())) { - IsPresent = StringParser::parse(EnvStr, Data); - if (IsPresent) { - // Check whether the envar value is actually valid. - Error Err = Setter(Data); - if (Err) { - // The setter reported an invalid value. Mark the user-defined value as - // not present and reset to the getter value (default). - IsPresent = false; - Data = Default; - DP("Setter of envar %s failed, resetting to %s\n", Name.data(), - std::to_string(Data).data()); - consumeError(std::move(Err)); - } - } else { - DP("Ignoring invalid value %s for envar %s\n", EnvStr, Name.data()); - Data = Default; - } - } else { - Data = Default; - } - - return Error::success(); -} - /// Return the difference (in bytes) between \p Begin and \p End. template ptrdiff_t getPtrDiff(const void *End, const void *Begin) { diff --git a/openmp/libomptarget/plugins-nextgen/common/include/JIT.h b/openmp/libomptarget/plugins-nextgen/common/include/JIT.h index 1a5e56b2ea73..7252519a8c2e 100644 --- a/openmp/libomptarget/plugins-nextgen/common/include/JIT.h +++ b/openmp/libomptarget/plugins-nextgen/common/include/JIT.h @@ -11,6 +11,7 @@ #ifndef OPENMP_LIBOMPTARGET_PLUGINS_NEXTGEN_COMMON_JIT_H #define OPENMP_LIBOMPTARGET_PLUGINS_NEXTGEN_COMMON_JIT_H +#include "Shared/EnvironmentVar.h" #include "Shared/Utils.h" #include "llvm/ADT/StringMap.h" @@ -106,18 +107,16 @@ private: std::mutex ComputeUnitMapMutex; /// Control environment variables. - target::StringEnvar ReplacementObjectFileName = - target::StringEnvar("LIBOMPTARGET_JIT_REPLACEMENT_OBJECT"); - target::StringEnvar ReplacementModuleFileName = - target::StringEnvar("LIBOMPTARGET_JIT_REPLACEMENT_MODULE"); - target::StringEnvar PreOptIRModuleFileName = - target::StringEnvar("LIBOMPTARGET_JIT_PRE_OPT_IR_MODULE"); - target::StringEnvar PostOptIRModuleFileName = - target::StringEnvar("LIBOMPTARGET_JIT_POST_OPT_IR_MODULE"); - target::UInt32Envar JITOptLevel = - target::UInt32Envar("LIBOMPTARGET_JIT_OPT_LEVEL", 3); - target::BoolEnvar JITSkipOpt = - target::BoolEnvar("LIBOMPTARGET_JIT_SKIP_OPT", false); + StringEnvar ReplacementObjectFileName = + StringEnvar("LIBOMPTARGET_JIT_REPLACEMENT_OBJECT"); + StringEnvar ReplacementModuleFileName = + StringEnvar("LIBOMPTARGET_JIT_REPLACEMENT_MODULE"); + StringEnvar PreOptIRModuleFileName = + StringEnvar("LIBOMPTARGET_JIT_PRE_OPT_IR_MODULE"); + StringEnvar PostOptIRModuleFileName = + StringEnvar("LIBOMPTARGET_JIT_POST_OPT_IR_MODULE"); + UInt32Envar JITOptLevel = UInt32Envar("LIBOMPTARGET_JIT_OPT_LEVEL", 3); + BoolEnvar JITSkipOpt = BoolEnvar("LIBOMPTARGET_JIT_SKIP_OPT", false); }; } // namespace target diff --git a/openmp/libomptarget/plugins-nextgen/common/include/MemoryManager.h b/openmp/libomptarget/plugins-nextgen/common/include/MemoryManager.h index 95491b4be6fa..fe1989930b76 100644 --- a/openmp/libomptarget/plugins-nextgen/common/include/MemoryManager.h +++ b/openmp/libomptarget/plugins-nextgen/common/include/MemoryManager.h @@ -324,7 +324,7 @@ public: /// manager explicitly by setting the var to 0. If user doesn't specify /// anything, returns <0, true>. static std::pair getSizeThresholdFromEnv() { - static llvm::omp::target::UInt32Envar MemoryManagerThreshold( + static UInt32Envar MemoryManagerThreshold( "LIBOMPTARGET_MEMORY_MANAGER_THRESHOLD", 0); size_t Threshold = MemoryManagerThreshold.get(); diff --git a/openmp/libomptarget/plugins-nextgen/common/include/PluginInterface.h b/openmp/libomptarget/plugins-nextgen/common/include/PluginInterface.h index 6abd1b6829ab..dd601e6b4231 100644 --- a/openmp/libomptarget/plugins-nextgen/common/include/PluginInterface.h +++ b/openmp/libomptarget/plugins-nextgen/common/include/PluginInterface.h @@ -21,6 +21,7 @@ #include "Shared/Debug.h" #include "Shared/Environment.h" +#include "Shared/EnvironmentVar.h" #include "Shared/Utils.h" #include "GlobalHandler.h" diff --git a/openmp/libomptarget/src/device.cpp b/openmp/libomptarget/src/device.cpp index 2431d7c07335..da7d33b3f40c 100644 --- a/openmp/libomptarget/src/device.cpp +++ b/openmp/libomptarget/src/device.cpp @@ -18,7 +18,7 @@ #include "private.h" #include "rtl.h" -#include "Shared/Utils.h" +#include "Shared/EnvironmentVar.h" #include #include @@ -535,11 +535,10 @@ void DeviceTy::init() { return; // Enables recording kernels if set. - llvm::omp::target::BoolEnvar OMPX_RecordKernel("LIBOMPTARGET_RECORD", false); + BoolEnvar OMPX_RecordKernel("LIBOMPTARGET_RECORD", false); if (OMPX_RecordKernel) { // Enables saving the device memory kernel output post execution if set. - llvm::omp::target::BoolEnvar OMPX_ReplaySaveOutput( - "LIBOMPTARGET_RR_SAVE_OUTPUT", false); + BoolEnvar OMPX_ReplaySaveOutput("LIBOMPTARGET_RR_SAVE_OUTPUT", false); uint64_t ReqPtrArgOffset; RTL->initialize_record_replay(RTLDeviceID, 0, nullptr, true, diff --git a/openmp/libomptarget/src/interface.cpp b/openmp/libomptarget/src/interface.cpp index 97cada94527f..a2f713459e1d 100644 --- a/openmp/libomptarget/src/interface.cpp +++ b/openmp/libomptarget/src/interface.cpp @@ -19,8 +19,8 @@ #include "private.h" #include "rtl.h" +#include "Shared/EnvironmentVar.h" #include "Shared/Profile.h" -#include "Shared/Utils.h" #include "Utils/ExponentialBackoff.h" diff --git a/openmp/libomptarget/src/rtl.cpp b/openmp/libomptarget/src/rtl.cpp index e80d6e09c484..09084be12a76 100644 --- a/openmp/libomptarget/src/rtl.cpp +++ b/openmp/libomptarget/src/rtl.cpp @@ -14,11 +14,11 @@ #include "OpenMP/OMPT/Callback.h" #include "PluginManager.h" -#include "Shared/Debug.h" #include "device.h" #include "private.h" #include "rtl.h" +#include "Shared/Debug.h" #include "Shared/Profile.h" #include "Shared/Utils.h" -- GitLab From 668865789620f390fbad4d7093ed8ca6eb932c31 Mon Sep 17 00:00:00 2001 From: Aiden Grossman Date: Thu, 30 Nov 2023 14:06:01 -0800 Subject: [PATCH 069/699] Reland "[llvm-exegesis] Set stack pointer register after starting perf counter (#72489)" This reverts commit 52b4b357268ac114f7972e37da1e5954f322df09. This commit was causing build failures on bots without libpfm installed as the CHECK requires were not set correctly. The test added should only run on machines with libpfm enabled due to the limitations currently imposed by the subprocess execution mode. --- .../X86/latency/subprocess-rsp.s | 18 +++++++++++++++ llvm/tools/llvm-exegesis/lib/Assembler.cpp | 23 +++++++++++++++++++ 2 files changed, 41 insertions(+) create mode 100644 llvm/test/tools/llvm-exegesis/X86/latency/subprocess-rsp.s diff --git a/llvm/test/tools/llvm-exegesis/X86/latency/subprocess-rsp.s b/llvm/test/tools/llvm-exegesis/X86/latency/subprocess-rsp.s new file mode 100644 index 000000000000..cc23cdee3296 --- /dev/null +++ b/llvm/test/tools/llvm-exegesis/X86/latency/subprocess-rsp.s @@ -0,0 +1,18 @@ +# REQUIRES: exegesis-can-measure-latency, x86_64-linux + +# RUN: llvm-exegesis -mtriple=x86_64-unknown-unknown -mode=latency -snippets-file=%s -execution-mode=subprocess | FileCheck %s + +# Check that we can set the value of RSP in subprocess mode without +# segfaulting as we need to restore it after the rest of the setup is +# complete to prevent loading from the stack where we set it instead +# of where the stack actuall is. + +# LLVM-EXEGESIS-MEM-DEF test1 4096 2147483647 +# LLVM-EXEGESIS-MEM-MAP test1 1048576 +# LLVM-EXEGESIS-DEFREG RAX 100000 +# LLVM-EXEGESIS-DEFREG R14 100000 +# LLVM-EXEGESIS-DEFREG RSP 100000 + +movq %r14, (%rax) + +# CHECK-NOT: error: 'The benchmarking subprocess sent unexpected signal: Segmentation fault' diff --git a/llvm/tools/llvm-exegesis/lib/Assembler.cpp b/llvm/tools/llvm-exegesis/lib/Assembler.cpp index e64f4e64ebb4..e17d239faa47 100644 --- a/llvm/tools/llvm-exegesis/lib/Assembler.cpp +++ b/llvm/tools/llvm-exegesis/lib/Assembler.cpp @@ -19,6 +19,7 @@ #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/TargetInstrInfo.h" +#include "llvm/CodeGen/TargetLowering.h" #include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/CodeGen/TargetSubtargetInfo.h" #include "llvm/ExecutionEngine/Orc/LLJIT.h" @@ -60,7 +61,17 @@ static bool generateSnippetSetupCode( } BBF.addInstructions(ET.setStackRegisterToAuxMem()); } + Register StackPointerRegister = BBF.MF.getSubtarget() + .getTargetLowering() + ->getStackPointerRegisterToSaveRestore(); for (const RegisterValue &RV : RegisterInitialValues) { + if (GenerateMemoryInstructions) { + // If we're generating memory instructions, don't load in the value for + // the register with the stack pointer as it will be used later to finish + // the setup. + if (RV.Register == StackPointerRegister) + continue; + } // Load a constant in the register. const auto SetRegisterCode = ET.setRegTo(*MSI, RV.Register, RV.Value); if (SetRegisterCode.empty()) @@ -71,6 +82,18 @@ static bool generateSnippetSetupCode( #ifdef HAVE_LIBPFM BBF.addInstructions(ET.configurePerfCounter(PERF_EVENT_IOC_RESET, true)); #endif // HAVE_LIBPFM + for (const RegisterValue &RV : RegisterInitialValues) { + // Load in the stack register now as we're done using it elsewhere + // and need to set the value in preparation for executing the + // snippet. + if (RV.Register == StackPointerRegister) + continue; + const auto SetRegisterCode = ET.setRegTo(*MSI, RV.Register, RV.Value); + if (SetRegisterCode.empty()) + IsSnippetSetupComplete = false; + BBF.addInstructions(SetRegisterCode); + break; + } } return IsSnippetSetupComplete; } -- GitLab From 3dbac2c007c114a720300d2a4d79abe9ca1351e7 Mon Sep 17 00:00:00 2001 From: Fehr Mathieu Date: Fri, 1 Dec 2023 00:39:34 +0100 Subject: [PATCH 070/699] [mlir] Expose type and attribute names in the MLIRContext and abstract type/attr classes (#72189) This patch expose the type and attribute names in C++ as methods in the `AbstractType` and `AbstractAttribute` classes, and keep a map of names to `AbstractType` and `AbstractAttribute` in the `MLIRContext`. Type and attribute names should be unique. It adds support in ODS to generate the `getName` methods in `AbstractType` and `AbstractAttribute`, through the use of two new variables, `typeName` and `attrName`. It also adds names to C++-defined type and attributes. --- .../include/flang/Optimizer/Dialect/FIRAttr.h | 8 ++ mlir/examples/toy/Ch7/include/toy/Dialect.h | 3 + mlir/include/mlir/Dialect/DLTI/DLTI.h | 4 + mlir/include/mlir/Dialect/GPU/IR/GPUDialect.h | 35 ++++++-- mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h | 17 ++-- mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td | 4 + mlir/include/mlir/Dialect/Quant/QuantTypes.h | 8 ++ .../mlir/Dialect/SPIRV/IR/SPIRVAttributes.h | 6 ++ .../mlir/Dialect/SPIRV/IR/SPIRVTypes.h | 20 +++++ mlir/include/mlir/IR/AttrTypeBase.td | 12 ++- mlir/include/mlir/IR/AttributeSupport.h | 22 +++-- mlir/include/mlir/IR/BuiltinAttributes.h | 2 + mlir/include/mlir/IR/BuiltinAttributes.td | 43 ++++----- .../mlir/IR/BuiltinLocationAttributes.td | 6 ++ mlir/include/mlir/IR/BuiltinTypes.td | 55 ++++++------ mlir/include/mlir/IR/TypeSupport.h | 23 +++-- mlir/include/mlir/TableGen/AttrOrTypeDef.h | 8 ++ mlir/lib/IR/ExtensibleDialect.cpp | 16 +++- mlir/lib/IR/MLIRContext.cpp | 45 +++++++++- mlir/lib/TableGen/AttrOrTypeDef.cpp | 16 ++++ mlir/test/lib/Dialect/Test/TestTypes.h | 4 +- mlir/test/mlir-tblgen/attrdefs.td | 5 ++ mlir/test/mlir-tblgen/op-attribute.td | 1 + mlir/test/mlir-tblgen/op-decl-and-defs.td | 4 +- mlir/test/mlir-tblgen/typedefs.td | 2 + mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp | 17 ++++ mlir/unittests/IR/CMakeLists.txt | 1 + mlir/unittests/IR/TypeAttrNamesTest.cpp | 90 +++++++++++++++++++ mlir/unittests/IR/TypeTest.cpp | 5 ++ .../Interfaces/DataLayoutInterfacesTest.cpp | 7 ++ 30 files changed, 409 insertions(+), 80 deletions(-) create mode 100644 mlir/unittests/IR/TypeAttrNamesTest.cpp diff --git a/flang/include/flang/Optimizer/Dialect/FIRAttr.h b/flang/include/flang/Optimizer/Dialect/FIRAttr.h index 2b14e15c906c..c427a6576b5d 100644 --- a/flang/include/flang/Optimizer/Dialect/FIRAttr.h +++ b/flang/include/flang/Optimizer/Dialect/FIRAttr.h @@ -38,6 +38,7 @@ public: using Base::Base; using ValueType = mlir::Type; + static constexpr llvm::StringLiteral name = "fir.type_is"; static constexpr llvm::StringRef getAttrName() { return "type_is"; } static ExactTypeAttr get(mlir::Type value); @@ -51,6 +52,7 @@ public: using Base::Base; using ValueType = mlir::Type; + static constexpr llvm::StringLiteral name = "fir.class_is"; static constexpr llvm::StringRef getAttrName() { return "class_is"; } static SubclassAttr get(mlir::Type value); @@ -63,6 +65,7 @@ class MustBeHeapAttr : public mlir::BoolAttr { public: using BoolAttr::BoolAttr; + static constexpr llvm::StringLiteral name = "fir.must_be_heap"; static constexpr llvm::StringRef getAttrName() { return "fir.must_be_heap"; } }; @@ -78,6 +81,7 @@ class ClosedIntervalAttr public: using Base::Base; + static constexpr llvm::StringLiteral name = "fir.interval"; static constexpr llvm::StringRef getAttrName() { return "interval"; } static ClosedIntervalAttr get(mlir::MLIRContext *ctxt); }; @@ -92,6 +96,7 @@ class UpperBoundAttr public: using Base::Base; + static constexpr llvm::StringLiteral name = "fir.upper"; static constexpr llvm::StringRef getAttrName() { return "upper"; } static UpperBoundAttr get(mlir::MLIRContext *ctxt); }; @@ -106,6 +111,7 @@ class LowerBoundAttr public: using Base::Base; + static constexpr llvm::StringLiteral name = "fir.lower"; static constexpr llvm::StringRef getAttrName() { return "lower"; } static LowerBoundAttr get(mlir::MLIRContext *ctxt); }; @@ -120,6 +126,7 @@ class PointIntervalAttr public: using Base::Base; + static constexpr llvm::StringLiteral name = "fir.point"; static constexpr llvm::StringRef getAttrName() { return "point"; } static PointIntervalAttr get(mlir::MLIRContext *ctxt); }; @@ -135,6 +142,7 @@ public: using Base::Base; using ValueType = std::pair; + static constexpr llvm::StringLiteral name = "fir.real"; static constexpr llvm::StringRef getAttrName() { return "real"; } static RealAttr get(mlir::MLIRContext *ctxt, const ValueType &key); diff --git a/mlir/examples/toy/Ch7/include/toy/Dialect.h b/mlir/examples/toy/Ch7/include/toy/Dialect.h index bbcc6cd7f0b1..64094c351591 100644 --- a/mlir/examples/toy/Ch7/include/toy/Dialect.h +++ b/mlir/examples/toy/Ch7/include/toy/Dialect.h @@ -72,6 +72,9 @@ public: /// Returns the number of element type held by this struct. size_t getNumElementTypes() { return getElementTypes().size(); } + + /// The name of this struct type. + static constexpr StringLiteral name = "toy.struct"; }; } // namespace toy } // namespace mlir diff --git a/mlir/include/mlir/Dialect/DLTI/DLTI.h b/mlir/include/mlir/Dialect/DLTI/DLTI.h index cf78b2312c24..b9a8763eb449 100644 --- a/mlir/include/mlir/Dialect/DLTI/DLTI.h +++ b/mlir/include/mlir/Dialect/DLTI/DLTI.h @@ -55,6 +55,8 @@ public: /// Prints this attribute. void print(AsmPrinter &os) const; + + static constexpr StringLiteral name = "builtin.data_layout_entry"; }; //===----------------------------------------------------------------------===// @@ -109,6 +111,8 @@ public: /// Prints this attribute. void print(AsmPrinter &os) const; + + static constexpr StringLiteral name = "builtin.data_layout_spec"; }; } // namespace mlir diff --git a/mlir/include/mlir/Dialect/GPU/IR/GPUDialect.h b/mlir/include/mlir/Dialect/GPU/IR/GPUDialect.h index 14a1fac5fd25..58c0719c6a41 100644 --- a/mlir/include/mlir/Dialect/GPU/IR/GPUDialect.h +++ b/mlir/include/mlir/Dialect/GPU/IR/GPUDialect.h @@ -45,6 +45,8 @@ class AsyncTokenType public: // Used for generic hooks in TypeBase. using Base::Base; + + static constexpr StringLiteral name = "gpu.async_token"; }; /// MMAMatrixType storage and uniquing. Array is uniqued based on its shape @@ -128,6 +130,8 @@ class MMAMatrixType public: using Base::Base; + static constexpr StringLiteral name = "gpu.mma_matrix"; + /// Get MMAMatrixType and verify construction Invariants. static MMAMatrixType get(ArrayRef shape, Type elementType, StringRef operand); @@ -168,18 +172,35 @@ void addAsyncDependency(Operation *op, Value token); // Handle types for sparse. enum class SparseHandleKind { SpMat, DnTensor, SpGEMMOp }; -template -class SparseHandleType - : public Type::TypeBase, Type, TypeStorage> { +class SparseDnTensorHandleType + : public Type::TypeBase { +public: + using Base = typename Type::TypeBase::Base; + using Base::Base; + + static constexpr StringLiteral name = "gpu.sparse.dntensor_handle"; +}; + +class SparseSpMatHandleType + : public Type::TypeBase { public: using Base = - typename Type::TypeBase, Type, TypeStorage>::Base; + typename Type::TypeBase::Base; using Base::Base; + + static constexpr StringLiteral name = "gpu.sparse.spmat_handle"; }; -using SparseDnTensorHandleType = SparseHandleType; -using SparseSpMatHandleType = SparseHandleType; -using SparseSpGEMMOpHandleType = SparseHandleType; +class SparseSpGEMMOpHandleType + : public Type::TypeBase { +public: + using Base = typename Type::TypeBase::Base; + using Base::Base; + + static constexpr StringLiteral name = "gpu.sparse.spgemmop_handle"; +}; } // namespace gpu } // namespace mlir diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h b/mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h index 06a41c7c1a72..93733ccd4929 100644 --- a/mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h +++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h @@ -58,18 +58,19 @@ namespace LLVM { //===----------------------------------------------------------------------===// // Batch-define trivial types. -#define DEFINE_TRIVIAL_LLVM_TYPE(ClassName) \ +#define DEFINE_TRIVIAL_LLVM_TYPE(ClassName, TypeName) \ class ClassName : public Type::TypeBase { \ public: \ using Base::Base; \ + static constexpr StringLiteral name = TypeName; \ } -DEFINE_TRIVIAL_LLVM_TYPE(LLVMVoidType); -DEFINE_TRIVIAL_LLVM_TYPE(LLVMPPCFP128Type); -DEFINE_TRIVIAL_LLVM_TYPE(LLVMX86MMXType); -DEFINE_TRIVIAL_LLVM_TYPE(LLVMTokenType); -DEFINE_TRIVIAL_LLVM_TYPE(LLVMLabelType); -DEFINE_TRIVIAL_LLVM_TYPE(LLVMMetadataType); +DEFINE_TRIVIAL_LLVM_TYPE(LLVMVoidType, "llvm.void"); +DEFINE_TRIVIAL_LLVM_TYPE(LLVMPPCFP128Type, "llvm.ppc_fp128"); +DEFINE_TRIVIAL_LLVM_TYPE(LLVMX86MMXType, "llvm.x86_mmx"); +DEFINE_TRIVIAL_LLVM_TYPE(LLVMTokenType, "llvm.token"); +DEFINE_TRIVIAL_LLVM_TYPE(LLVMLabelType, "llvm.label"); +DEFINE_TRIVIAL_LLVM_TYPE(LLVMMetadataType, "llvm.metadata"); #undef DEFINE_TRIVIAL_LLVM_TYPE @@ -110,6 +111,8 @@ public: /// Inherit base constructors. using Base::Base; + static constexpr StringLiteral name = "llvm.struct"; + /// Checks if the given type can be contained in a structure type. static bool isValidElementType(Type type); diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td b/mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td index 0bd068c1be7c..96cdbf01b4bd 100644 --- a/mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td +++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td @@ -162,6 +162,8 @@ def LLVMFixedVectorType : LLVMType<"LLVMFixedVector", "vec"> { elements can be processed as one in SIMD context. }]; + let typeName = "llvm.fixed_vec"; + let parameters = (ins "Type":$elementType, "unsigned":$numElements); let assemblyFormat = [{ `<` $numElements `x` custom($elementType) `>` @@ -192,6 +194,8 @@ def LLVMScalableVectorType : LLVMType<"LLVMScalableVector", "vec"> { elements can be processed as one in SIMD context. }]; + let typeName = "llvm.scalable_vec"; + let parameters = (ins "Type":$elementType, "unsigned":$minNumElements); let assemblyFormat = [{ `<` `?` `x` $minNumElements `x` ` ` custom($elementType) `>` diff --git a/mlir/include/mlir/Dialect/Quant/QuantTypes.h b/mlir/include/mlir/Dialect/Quant/QuantTypes.h index 2776b3e6e17b..de5aed0a91a2 100644 --- a/mlir/include/mlir/Dialect/Quant/QuantTypes.h +++ b/mlir/include/mlir/Dialect/Quant/QuantTypes.h @@ -198,6 +198,8 @@ public: using Base::Base; using Base::getChecked; + static constexpr StringLiteral name = "quant.any"; + /// Gets an instance of the type with all parameters specified but not /// checked. static AnyQuantizedType get(unsigned flags, Type storageType, @@ -257,6 +259,8 @@ public: using Base::Base; using Base::getChecked; + static constexpr StringLiteral name = "quant.uniform"; + /// Gets an instance of the type with all parameters specified but not /// checked. static UniformQuantizedType get(unsigned flags, Type storageType, @@ -315,6 +319,8 @@ public: using Base::Base; using Base::getChecked; + static constexpr StringLiteral name = "quant.uniform_per_axis"; + /// Gets an instance of the type with all parameters specified but not /// checked. static UniformQuantizedPerAxisType @@ -383,6 +389,8 @@ public: using Base::Base; using Base::getChecked; + static constexpr StringLiteral name = "quant.calibrated"; + /// Gets an instance of the type with all parameters specified but not /// checked. static CalibratedQuantizedType get(Type expressedType, double min, diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAttributes.h b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAttributes.h index 3b914dc4cc82..5ebfa9ca5ec2 100644 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAttributes.h +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAttributes.h @@ -79,6 +79,8 @@ public: static LogicalResult verify(function_ref emitError, IntegerAttr descriptorSet, IntegerAttr binding, IntegerAttr storageClass); + + static constexpr StringLiteral name = "spirv.interface_var_abi"; }; /// An attribute that specifies the SPIR-V (version, capabilities, extensions) @@ -129,6 +131,8 @@ public: static LogicalResult verify(function_ref emitError, IntegerAttr version, ArrayAttr capabilities, ArrayAttr extensions); + + static constexpr StringLiteral name = "spirv.ver_cap_ext"; }; /// An attribute that specifies the target version, allowed extensions and @@ -183,6 +187,8 @@ public: /// Returns the target resource limits. ResourceLimitsAttr getResourceLimits() const; + + static constexpr StringLiteral name = "spirv.target_env"; }; } // namespace spirv } // namespace mlir diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTypes.h b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTypes.h index 4be2582f8fd6..d946d936d4e6 100644 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTypes.h +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTypes.h @@ -132,6 +132,8 @@ class ArrayType : public Type::TypeBase emitError, diff --git a/mlir/include/mlir/IR/AttrTypeBase.td b/mlir/include/mlir/IR/AttrTypeBase.td index 42a611ee8e42..91c9283de8bd 100644 --- a/mlir/include/mlir/IR/AttrTypeBase.td +++ b/mlir/include/mlir/IR/AttrTypeBase.td @@ -264,6 +264,9 @@ class AttrDef traits = [], // Make it possible to use such attributes as parameters for other attributes. string cppType = dialect.cppNamespace # "::" # cppClassName; + // The unique attribute name. + string attrName = dialect.name # "." # mnemonic; + // The call expression to convert from the storage type to the return // type. For example, an enum can be stored as an int but returned as an // enum class. @@ -289,6 +292,9 @@ class TypeDef traits = [], // Make it possible to use such type as parameters for other types. string cppType = dialect.cppNamespace # "::" # cppClassName; + // The unique type name. + string typeName = dialect.name # "." # mnemonic; + // A constant builder provided when the type has no parameters. let builderCall = !if(!empty(parameters), "$_builder.getType<" # dialect.cppNamespace # @@ -431,15 +437,15 @@ class AttributeSelfTypeParameter traits = []> - : AttrDef { + : AttrDef { let parameters = (ins OptionalArrayRefParameter:$value); let mnemonic = attrMnemonic; let assemblyFormat = "`[` (`]`) : ($value^ `]`)?"; let returnType = "::llvm::ArrayRef<" # eltName # ">"; - let constBuilderCall = "$_builder.getAttr<" # attrName # "Attr>($0)"; + let constBuilderCall = "$_builder.getAttr<" # name # "Attr>($0)"; let convertFromStorage = "$_self.getValue()"; let extraClassDeclaration = [{ diff --git a/mlir/include/mlir/IR/AttributeSupport.h b/mlir/include/mlir/IR/AttributeSupport.h index 75ea1ce24753..9f36ee4aae27 100644 --- a/mlir/include/mlir/IR/AttributeSupport.h +++ b/mlir/include/mlir/IR/AttributeSupport.h @@ -38,6 +38,11 @@ public: /// reference to it. static const AbstractAttribute &lookup(TypeID typeID, MLIRContext *context); + /// Look up the specified abstract attribute in the MLIRContext and return a + /// reference to it if it exists. + static std::optional> + lookup(StringRef name, MLIRContext *context); + /// This method is used by Dialect objects when they register the list of /// attributes they contain. template @@ -45,7 +50,7 @@ public: return AbstractAttribute(dialect, T::getInterfaceMap(), T::getHasTraitFn(), T::getWalkImmediateSubElementsFn(), T::getReplaceImmediateSubElementsFn(), - T::getTypeID()); + T::getTypeID(), T::name); } /// This method is used by Dialect objects to register attributes with @@ -57,10 +62,10 @@ public: HasTraitFn &&hasTrait, WalkImmediateSubElementsFn walkImmediateSubElementsFn, ReplaceImmediateSubElementsFn replaceImmediateSubElementsFn, - TypeID typeID) { + TypeID typeID, StringRef name) { return AbstractAttribute(dialect, std::move(interfaceMap), std::move(hasTrait), walkImmediateSubElementsFn, - replaceImmediateSubElementsFn, typeID); + replaceImmediateSubElementsFn, typeID, name); } /// Return the dialect this attribute was registered to. @@ -102,17 +107,20 @@ public: /// Return the unique identifier representing the concrete attribute class. TypeID getTypeID() const { return typeID; } + /// Return the unique name representing the type. + StringRef getName() const { return name; } + private: AbstractAttribute(Dialect &dialect, detail::InterfaceMap &&interfaceMap, HasTraitFn &&hasTraitFn, WalkImmediateSubElementsFn walkImmediateSubElementsFn, ReplaceImmediateSubElementsFn replaceImmediateSubElementsFn, - TypeID typeID) + TypeID typeID, StringRef name) : dialect(dialect), interfaceMap(std::move(interfaceMap)), hasTraitFn(std::move(hasTraitFn)), walkImmediateSubElementsFn(walkImmediateSubElementsFn), replaceImmediateSubElementsFn(replaceImmediateSubElementsFn), - typeID(typeID) {} + typeID(typeID), name(name) {} /// Give StorageUserBase access to the mutable lookup. template traits = [], +class Builtin_Attr traits = [], string baseCppClass = "::mlir::Attribute"> : AttrDef { let mnemonic = ?; + let attrName = "builtin." # attrMnemonic; } //===----------------------------------------------------------------------===// // AffineMapAttr //===----------------------------------------------------------------------===// -def Builtin_AffineMapAttr : Builtin_Attr<"AffineMap", [ +def Builtin_AffineMapAttr : Builtin_Attr<"AffineMap", "affine_map", [ MemRefLayoutAttrInterface ]> { let summary = "An Attribute containing an AffineMap object"; @@ -70,7 +71,7 @@ def Builtin_AffineMapAttr : Builtin_Attr<"AffineMap", [ // ArrayAttr //===----------------------------------------------------------------------===// -def Builtin_ArrayAttr : Builtin_Attr<"Array"> { +def Builtin_ArrayAttr : Builtin_Attr<"Array", "array"> { let summary = "A collection of other Attribute values"; let description = [{ Syntax: @@ -152,7 +153,7 @@ def Builtin_DenseArrayRawDataParameter : ArrayRefParameter< }]; } -def Builtin_DenseArray : Builtin_Attr<"DenseArray"> { +def Builtin_DenseArray : Builtin_Attr<"DenseArray", "dense_array"> { let summary = "A dense array of integer or floating point elements."; let description = [{ A dense array attribute is an attribute that represents a dense array of @@ -218,7 +219,7 @@ def Builtin_DenseArray : Builtin_Attr<"DenseArray"> { //===----------------------------------------------------------------------===// def Builtin_DenseIntOrFPElementsAttr : Builtin_Attr< - "DenseIntOrFPElements", [ElementsAttrInterface], + "DenseIntOrFPElements", "dense_int_or_fp_elements", [ElementsAttrInterface], "DenseElementsAttr" > { let summary = "An Attribute containing a dense multi-dimensional array of " @@ -359,7 +360,7 @@ def Builtin_DenseIntOrFPElementsAttr : Builtin_Attr< //===----------------------------------------------------------------------===// def Builtin_DenseStringElementsAttr : Builtin_Attr< - "DenseStringElements", [ElementsAttrInterface], + "DenseStringElements", "dense_string_elements", [ElementsAttrInterface], "DenseElementsAttr" > { let summary = "An Attribute containing a dense multi-dimensional array of " @@ -429,9 +430,8 @@ def Builtin_DenseStringElementsAttr : Builtin_Attr< // DenseResourceElementsAttr //===----------------------------------------------------------------------===// -def Builtin_DenseResourceElementsAttr : Builtin_Attr<"DenseResourceElements", [ - ElementsAttrInterface - ]> { +def Builtin_DenseResourceElementsAttr : Builtin_Attr<"DenseResourceElements", + "dense_resource_elements", [ElementsAttrInterface]> { let summary = "An Attribute containing a dense multi-dimensional array " "backed by a resource"; let description = [{ @@ -487,7 +487,7 @@ def Builtin_DenseResourceElementsAttr : Builtin_Attr<"DenseResourceElements", [ // DictionaryAttr //===----------------------------------------------------------------------===// -def Builtin_DictionaryAttr : Builtin_Attr<"Dictionary"> { +def Builtin_DictionaryAttr : Builtin_Attr<"Dictionary", "dictionary"> { let summary = "An dictionary of named Attribute values"; let description = [{ Syntax: @@ -585,7 +585,7 @@ def Builtin_DictionaryAttr : Builtin_Attr<"Dictionary"> { // FloatAttr //===----------------------------------------------------------------------===// -def Builtin_FloatAttr : Builtin_Attr<"Float", [TypedAttrInterface]> { +def Builtin_FloatAttr : Builtin_Attr<"Float", "float", [TypedAttrInterface]> { let summary = "An Attribute containing a floating-point value"; let description = [{ Syntax: @@ -648,7 +648,8 @@ def Builtin_FloatAttr : Builtin_Attr<"Float", [TypedAttrInterface]> { // IntegerAttr //===----------------------------------------------------------------------===// -def Builtin_IntegerAttr : Builtin_Attr<"Integer", [TypedAttrInterface]> { +def Builtin_IntegerAttr : Builtin_Attr<"Integer", "integer", + [TypedAttrInterface]> { let summary = "An Attribute containing a integer value"; let description = [{ Syntax: @@ -736,7 +737,7 @@ def Builtin_IntegerAttr : Builtin_Attr<"Integer", [TypedAttrInterface]> { // IntegerSetAttr //===----------------------------------------------------------------------===// -def Builtin_IntegerSetAttr : Builtin_Attr<"IntegerSet"> { +def Builtin_IntegerSetAttr : Builtin_Attr<"IntegerSet", "integer_set"> { let summary = "An Attribute containing an IntegerSet object"; let description = [{ Syntax: @@ -765,7 +766,8 @@ def Builtin_IntegerSetAttr : Builtin_Attr<"IntegerSet"> { // OpaqueAttr //===----------------------------------------------------------------------===// -def Builtin_OpaqueAttr : Builtin_Attr<"Opaque", [TypedAttrInterface]> { +def Builtin_OpaqueAttr : Builtin_Attr<"Opaque", "opaque", + [TypedAttrInterface]> { let summary = "An opaque representation of another Attribute"; let description = [{ Syntax: @@ -803,7 +805,7 @@ def Builtin_OpaqueAttr : Builtin_Attr<"Opaque", [TypedAttrInterface]> { //===----------------------------------------------------------------------===// def Builtin_SparseElementsAttr : Builtin_Attr< - "SparseElements", [ElementsAttrInterface] + "SparseElements", "sparse_elements", [ElementsAttrInterface] > { let summary = "An opaque representation of a multi-dimensional array"; let description = [{ @@ -958,7 +960,7 @@ def Builtin_SparseElementsAttr : Builtin_Attr< // StridedLayoutAttr //===----------------------------------------------------------------------===// -def StridedLayoutAttr : Builtin_Attr<"StridedLayout", +def StridedLayoutAttr : Builtin_Attr<"StridedLayout", "strided_layout", [DeclareAttrInterfaceMethods]> { let summary = "An Attribute representing a strided layout of a shaped type"; @@ -1012,7 +1014,8 @@ def StridedLayoutAttr : Builtin_Attr<"StridedLayout", // StringAttr //===----------------------------------------------------------------------===// -def Builtin_StringAttr : Builtin_Attr<"String", [TypedAttrInterface]> { +def Builtin_StringAttr : Builtin_Attr<"String", "string", + [TypedAttrInterface]> { let summary = "An Attribute containing a string"; let description = [{ Syntax: @@ -1093,7 +1096,7 @@ def Builtin_StringAttr : Builtin_Attr<"String", [TypedAttrInterface]> { // SymbolRefAttr //===----------------------------------------------------------------------===// -def Builtin_SymbolRefAttr : Builtin_Attr<"SymbolRef"> { +def Builtin_SymbolRefAttr : Builtin_Attr<"SymbolRef", "symbol_ref"> { let summary = "An Attribute containing a symbolic reference to an Operation"; let description = [{ Syntax: @@ -1159,7 +1162,7 @@ def Builtin_SymbolRefAttr : Builtin_Attr<"SymbolRef"> { // TypeAttr //===----------------------------------------------------------------------===// -def Builtin_TypeAttr : Builtin_Attr<"Type"> { +def Builtin_TypeAttr : Builtin_Attr<"Type", "type"> { let summary = "An Attribute containing a Type"; let description = [{ Syntax: @@ -1192,7 +1195,7 @@ def Builtin_TypeAttr : Builtin_Attr<"Type"> { // UnitAttr //===----------------------------------------------------------------------===// -def Builtin_UnitAttr : Builtin_Attr<"Unit"> { +def Builtin_UnitAttr : Builtin_Attr<"Unit", "unit"> { let summary = "An Attribute value of `unit` type"; let description = [{ Syntax: diff --git a/mlir/include/mlir/IR/BuiltinLocationAttributes.td b/mlir/include/mlir/IR/BuiltinLocationAttributes.td index 3c9d2c57f4d1..e1656f268795 100644 --- a/mlir/include/mlir/IR/BuiltinLocationAttributes.td +++ b/mlir/include/mlir/IR/BuiltinLocationAttributes.td @@ -56,6 +56,7 @@ def CallSiteLoc : Builtin_LocationAttr<"CallSiteLoc"> { "ArrayRef":$frames)> ]; let skipDefaultBuilders = 1; + let attrName = "builtin.call_site_loc"; } //===----------------------------------------------------------------------===// @@ -98,6 +99,7 @@ def FileLineColLoc : Builtin_LocationAttr<"FileLineColLoc"> { }]> ]; let skipDefaultBuilders = 1; + let attrName = "builtin.file_line_loc"; } //===----------------------------------------------------------------------===// @@ -137,6 +139,7 @@ def FusedLoc : Builtin_LocationAttr<"FusedLoc"> { return get(locs, Attribute(), context); } }]; + let attrName = "builtin.fused_loc"; } //===----------------------------------------------------------------------===// @@ -174,6 +177,7 @@ def NameLoc : Builtin_LocationAttr<"NameLoc"> { }]> ]; let skipDefaultBuilders = 1; + let attrName = "builtin.name_loc"; } //===----------------------------------------------------------------------===// @@ -239,6 +243,7 @@ def OpaqueLoc : Builtin_LocationAttr<"OpaqueLoc"> { } }]; let skipDefaultBuilders = 1; + let attrName = "builtin.opaque_loc"; } //===----------------------------------------------------------------------===// @@ -268,6 +273,7 @@ def UnknownLoc : Builtin_LocationAttr<"UnknownLoc"> { let extraClassDeclaration = [{ static UnknownLoc get(MLIRContext *context); }]; + let attrName = "builtin.unknown_loc"; } #endif // BUILTIN_LOCATION_ATTRIBUTES_TD diff --git a/mlir/include/mlir/IR/BuiltinTypes.td b/mlir/include/mlir/IR/BuiltinTypes.td index 5ec986ac26de..1d7772810ae6 100644 --- a/mlir/include/mlir/IR/BuiltinTypes.td +++ b/mlir/include/mlir/IR/BuiltinTypes.td @@ -23,17 +23,18 @@ include "mlir/IR/BuiltinTypeInterfaces.td" // remove the definitions in OpBase.td, and repoint users to this file instead. // Base class for Builtin dialect types. -class Builtin_Type traits = [], +class Builtin_Type traits = [], string baseCppClass = "::mlir::Type"> : TypeDef { let mnemonic = ?; + let typeName = "builtin." # typeMnemonic; } //===----------------------------------------------------------------------===// // ComplexType //===----------------------------------------------------------------------===// -def Builtin_Complex : Builtin_Type<"Complex"> { +def Builtin_Complex : Builtin_Type<"Complex", "complex"> { let summary = "Complex number with a parameterized element type"; let description = [{ Syntax: @@ -68,8 +69,8 @@ def Builtin_Complex : Builtin_Type<"Complex"> { //===----------------------------------------------------------------------===// // Base class for Builtin dialect float types. -class Builtin_FloatType - : Builtin_Type { +class Builtin_FloatType + : Builtin_Type { let extraClassDeclaration = [{ static }] # name # [{Type get(MLIRContext *context); }]; @@ -78,7 +79,7 @@ class Builtin_FloatType //===----------------------------------------------------------------------===// // Float8E5M2Type -def Builtin_Float8E5M2 : Builtin_FloatType<"Float8E5M2"> { +def Builtin_Float8E5M2 : Builtin_FloatType<"Float8E5M2", "f8E5M2"> { let summary = "8-bit floating point with 2 bit mantissa"; let description = [{ An 8-bit floating point type with 1 sign bit, 5 bits exponent and 2 bits @@ -99,7 +100,7 @@ def Builtin_Float8E5M2 : Builtin_FloatType<"Float8E5M2"> { //===----------------------------------------------------------------------===// // Float8E4M3FNType -def Builtin_Float8E4M3FN : Builtin_FloatType<"Float8E4M3FN"> { +def Builtin_Float8E4M3FN : Builtin_FloatType<"Float8E4M3FN", "f8E4M3FN"> { let summary = "8-bit floating point with 3 bit mantissa"; let description = [{ An 8-bit floating point type with 1 sign bit, 4 bits exponent and 3 bits @@ -121,7 +122,7 @@ def Builtin_Float8E4M3FN : Builtin_FloatType<"Float8E4M3FN"> { //===----------------------------------------------------------------------===// // Float8E5M2FNUZType -def Builtin_Float8E5M2FNUZ : Builtin_FloatType<"Float8E5M2FNUZ"> { +def Builtin_Float8E5M2FNUZ : Builtin_FloatType<"Float8E5M2FNUZ", "f8E5M2FNUZ"> { let summary = "8-bit floating point with 2 bit mantissa"; let description = [{ An 8-bit floating point type with 1 sign bit, 5 bits exponent and 2 bits @@ -143,7 +144,7 @@ def Builtin_Float8E5M2FNUZ : Builtin_FloatType<"Float8E5M2FNUZ"> { //===----------------------------------------------------------------------===// // Float8E4M3FNUZType -def Builtin_Float8E4M3FNUZ : Builtin_FloatType<"Float8E4M3FNUZ"> { +def Builtin_Float8E4M3FNUZ : Builtin_FloatType<"Float8E4M3FNUZ", "f8E4M3FNUZ"> { let summary = "8-bit floating point with 3 bit mantissa"; let description = [{ An 8-bit floating point type with 1 sign bit, 4 bits exponent and 3 bits @@ -165,7 +166,7 @@ def Builtin_Float8E4M3FNUZ : Builtin_FloatType<"Float8E4M3FNUZ"> { //===----------------------------------------------------------------------===// // Float8E4M3B11FNUZType -def Builtin_Float8E4M3B11FNUZ : Builtin_FloatType<"Float8E4M3B11FNUZ"> { +def Builtin_Float8E4M3B11FNUZ : Builtin_FloatType<"Float8E4M3B11FNUZ", "f8E4M3B11FNUZ"> { let summary = "8-bit floating point with 3 bit mantissa"; let description = [{ An 8-bit floating point type with 1 sign bit, 4 bits exponent and 3 bits @@ -187,49 +188,49 @@ def Builtin_Float8E4M3B11FNUZ : Builtin_FloatType<"Float8E4M3B11FNUZ"> { //===----------------------------------------------------------------------===// // BFloat16Type -def Builtin_BFloat16 : Builtin_FloatType<"BFloat16"> { +def Builtin_BFloat16 : Builtin_FloatType<"BFloat16", "bf16"> { let summary = "bfloat16 floating-point type"; } //===----------------------------------------------------------------------===// // Float16Type -def Builtin_Float16 : Builtin_FloatType<"Float16"> { +def Builtin_Float16 : Builtin_FloatType<"Float16", "f16"> { let summary = "16-bit floating-point type"; } //===----------------------------------------------------------------------===// // FloatTF32Type -def Builtin_FloatTF32 : Builtin_FloatType<"FloatTF32"> { +def Builtin_FloatTF32 : Builtin_FloatType<"FloatTF32", "tf32"> { let summary = "TF32 floating-point type"; } //===----------------------------------------------------------------------===// // Float32Type -def Builtin_Float32 : Builtin_FloatType<"Float32"> { +def Builtin_Float32 : Builtin_FloatType<"Float32", "f32"> { let summary = "32-bit floating-point type"; } //===----------------------------------------------------------------------===// // Float64Type -def Builtin_Float64 : Builtin_FloatType<"Float64"> { +def Builtin_Float64 : Builtin_FloatType<"Float64", "f64"> { let summary = "64-bit floating-point type"; } //===----------------------------------------------------------------------===// // Float80Type -def Builtin_Float80 : Builtin_FloatType<"Float80"> { +def Builtin_Float80 : Builtin_FloatType<"Float80", "f80"> { let summary = "80-bit floating-point type"; } //===----------------------------------------------------------------------===// // Float128Type -def Builtin_Float128 : Builtin_FloatType<"Float128"> { +def Builtin_Float128 : Builtin_FloatType<"Float128", "f128"> { let summary = "128-bit floating-point type"; } @@ -237,7 +238,7 @@ def Builtin_Float128 : Builtin_FloatType<"Float128"> { // FunctionType //===----------------------------------------------------------------------===// -def Builtin_Function : Builtin_Type<"Function"> { +def Builtin_Function : Builtin_Type<"Function", "function"> { let summary = "Map from a list of inputs to a list of results"; let description = [{ Syntax: @@ -289,7 +290,7 @@ def Builtin_Function : Builtin_Type<"Function"> { // IndexType //===----------------------------------------------------------------------===// -def Builtin_Index : Builtin_Type<"Index"> { +def Builtin_Index : Builtin_Type<"Index", "index"> { let summary = "Integer-like type with unknown platform-dependent bit width"; let description = [{ Syntax: @@ -319,7 +320,7 @@ def Builtin_Index : Builtin_Type<"Index"> { // IntegerType //===----------------------------------------------------------------------===// -def Builtin_Integer : Builtin_Type<"Integer"> { +def Builtin_Integer : Builtin_Type<"Integer", "integer"> { let summary = "Integer type with arbitrary precision up to a fixed limit"; let description = [{ Syntax: @@ -383,7 +384,7 @@ def Builtin_Integer : Builtin_Type<"Integer"> { // MemRefType //===----------------------------------------------------------------------===// -def Builtin_MemRef : Builtin_Type<"MemRef", [ +def Builtin_MemRef : Builtin_Type<"MemRef", "memref", [ ShapedTypeInterface ], "BaseMemRefType"> { let summary = "Shaped reference to a region of memory"; @@ -663,7 +664,7 @@ def Builtin_MemRef : Builtin_Type<"MemRef", [ // NoneType //===----------------------------------------------------------------------===// -def Builtin_None : Builtin_Type<"None"> { +def Builtin_None : Builtin_Type<"None", "none"> { let summary = "A unit type"; let description = [{ NoneType is a unit type, i.e. a type with exactly one possible value, where @@ -678,7 +679,7 @@ def Builtin_None : Builtin_Type<"None"> { // OpaqueType //===----------------------------------------------------------------------===// -def Builtin_Opaque : Builtin_Type<"Opaque"> { +def Builtin_Opaque : Builtin_Type<"Opaque", "opaque"> { let summary = "Type of a non-registered dialect"; let description = [{ Syntax: @@ -718,7 +719,7 @@ def Builtin_Opaque : Builtin_Type<"Opaque"> { // RankedTensorType //===----------------------------------------------------------------------===// -def Builtin_RankedTensor : Builtin_Type<"RankedTensor", [ +def Builtin_RankedTensor : Builtin_Type<"RankedTensor", "tensor", [ ShapedTypeInterface ], "TensorType"> { let summary = "Multi-dimensional array with a fixed number of dimensions"; @@ -829,7 +830,7 @@ def Builtin_RankedTensor : Builtin_Type<"RankedTensor", [ // TupleType //===----------------------------------------------------------------------===// -def Builtin_Tuple : Builtin_Type<"Tuple"> { +def Builtin_Tuple : Builtin_Type<"Tuple", "tuple"> { let summary = "Fixed-sized collection of other types"; let description = [{ Syntax: @@ -896,7 +897,7 @@ def Builtin_Tuple : Builtin_Type<"Tuple"> { // UnrankedMemRefType //===----------------------------------------------------------------------===// -def Builtin_UnrankedMemRef : Builtin_Type<"UnrankedMemRef", [ +def Builtin_UnrankedMemRef : Builtin_Type<"UnrankedMemRef", "unranked_memref", [ ShapedTypeInterface ], "BaseMemRefType"> { let summary = "Shaped reference, with unknown rank, to a region of memory"; @@ -974,7 +975,7 @@ def Builtin_UnrankedMemRef : Builtin_Type<"UnrankedMemRef", [ // UnrankedTensorType //===----------------------------------------------------------------------===// -def Builtin_UnrankedTensor : Builtin_Type<"UnrankedTensor", [ +def Builtin_UnrankedTensor : Builtin_Type<"UnrankedTensor", "unranked_tensor", [ ShapedTypeInterface ], "TensorType"> { let summary = "Multi-dimensional array with unknown dimensions"; @@ -1023,7 +1024,7 @@ def Builtin_UnrankedTensor : Builtin_Type<"UnrankedTensor", [ // VectorType //===----------------------------------------------------------------------===// -def Builtin_Vector : Builtin_Type<"Vector", [ShapedTypeInterface], "Type"> { +def Builtin_Vector : Builtin_Type<"Vector", "vector", [ShapedTypeInterface], "Type"> { let summary = "Multi-dimensional SIMD vector type"; let description = [{ Syntax: diff --git a/mlir/include/mlir/IR/TypeSupport.h b/mlir/include/mlir/IR/TypeSupport.h index 2aa6b1a59e86..36ef696ba4f6 100644 --- a/mlir/include/mlir/IR/TypeSupport.h +++ b/mlir/include/mlir/IR/TypeSupport.h @@ -39,13 +39,19 @@ public: /// reference to it. static const AbstractType &lookup(TypeID typeID, MLIRContext *context); + /// Look up the specified abstract type in the MLIRContext and return a + /// reference to it if it exists. + static std::optional> + lookup(StringRef name, MLIRContext *context); + /// This method is used by Dialect objects when they register the list of /// types they contain. template static AbstractType get(Dialect &dialect) { return AbstractType(dialect, T::getInterfaceMap(), T::getHasTraitFn(), T::getWalkImmediateSubElementsFn(), - T::getReplaceImmediateSubElementsFn(), T::getTypeID()); + T::getReplaceImmediateSubElementsFn(), T::getTypeID(), + T::name); } /// This method is used by Dialect objects to register types with @@ -57,10 +63,10 @@ public: HasTraitFn &&hasTrait, WalkImmediateSubElementsFn walkImmediateSubElementsFn, ReplaceImmediateSubElementsFn replaceImmediateSubElementsFn, - TypeID typeID) { + TypeID typeID, StringRef name) { return AbstractType(dialect, std::move(interfaceMap), std::move(hasTrait), walkImmediateSubElementsFn, - replaceImmediateSubElementsFn, typeID); + replaceImmediateSubElementsFn, typeID, name); } /// Return the dialect this type was registered to. @@ -100,17 +106,20 @@ public: /// Return the unique identifier representing the concrete type class. TypeID getTypeID() const { return typeID; } + /// Return the unique name representing the type. + StringRef getName() const { return name; } + private: AbstractType(Dialect &dialect, detail::InterfaceMap &&interfaceMap, HasTraitFn &&hasTrait, WalkImmediateSubElementsFn walkImmediateSubElementsFn, ReplaceImmediateSubElementsFn replaceImmediateSubElementsFn, - TypeID typeID) + TypeID typeID, StringRef name) : dialect(dialect), interfaceMap(std::move(interfaceMap)), hasTraitFn(std::move(hasTrait)), walkImmediateSubElementsFn(walkImmediateSubElementsFn), replaceImmediateSubElementsFn(replaceImmediateSubElementsFn), - typeID(typeID) {} + typeID(typeID), name(name) {} /// Give StorageUserBase access to the mutable lookup. template getTypeBuilder() const; static bool classof(const AttrOrTypeDef *def); + + /// Get the unique attribute name "dialect.attrname". + StringRef getAttrName() const; }; //===----------------------------------------------------------------------===// @@ -267,6 +270,11 @@ public: class TypeDef : public AttrOrTypeDef { public: using AttrOrTypeDef::AttrOrTypeDef; + + static bool classof(const AttrOrTypeDef *def); + + /// Get the unique type name "dialect.typename". + StringRef getTypeName() const; }; } // namespace tblgen diff --git a/mlir/lib/IR/ExtensibleDialect.cpp b/mlir/lib/IR/ExtensibleDialect.cpp index 2225a8f2d1b9..ca7b0e1cbb6b 100644 --- a/mlir/lib/IR/ExtensibleDialect.cpp +++ b/mlir/lib/IR/ExtensibleDialect.cpp @@ -407,10 +407,16 @@ void ExtensibleDialect::registerDynamicType( assert(registered && "Trying to create a new dynamic type with an existing name"); + // The StringAttr allocates the type name StringRef for the duration of the + // MLIR context. + MLIRContext *ctx = getContext(); + auto nameAttr = + StringAttr::get(ctx, getNamespace() + "." + typePtr->getName()); + auto abstractType = AbstractType::get( *dialect, DynamicAttr::getInterfaceMap(), DynamicType::getHasTraitFn(), DynamicType::getWalkImmediateSubElementsFn(), - DynamicType::getReplaceImmediateSubElementsFn(), typeID); + DynamicType::getReplaceImmediateSubElementsFn(), typeID, nameAttr); /// Add the type to the dialect and the type uniquer. addType(typeID, std::move(abstractType)); @@ -437,10 +443,16 @@ void ExtensibleDialect::registerDynamicAttr( assert(registered && "Trying to create a new dynamic attribute with an existing name"); + // The StringAttr allocates the attribute name StringRef for the duration of + // the MLIR context. + MLIRContext *ctx = getContext(); + auto nameAttr = + StringAttr::get(ctx, getNamespace() + "." + attrPtr->getName()); + auto abstractAttr = AbstractAttribute::get( *dialect, DynamicAttr::getInterfaceMap(), DynamicAttr::getHasTraitFn(), DynamicAttr::getWalkImmediateSubElementsFn(), - DynamicAttr::getReplaceImmediateSubElementsFn(), typeID); + DynamicAttr::getReplaceImmediateSubElementsFn(), typeID, nameAttr); /// Add the type to the dialect and the type uniquer. addAttribute(typeID, std::move(abstractAttr)); diff --git a/mlir/lib/IR/MLIRContext.cpp b/mlir/lib/IR/MLIRContext.cpp index e5a397c9d65c..2fd9cac6df3d 100644 --- a/mlir/lib/IR/MLIRContext.cpp +++ b/mlir/lib/IR/MLIRContext.cpp @@ -212,6 +212,13 @@ public: DenseMap registeredTypes; StorageUniquer typeUniquer; + /// This is a mapping from type name to the abstract type describing it. + /// It is used by `AbstractType::lookup` to get an `AbstractType` from a name. + /// As this map needs to be populated before `StringAttr` is loaded, we + /// cannot use `StringAttr` as the key. The context does not take ownership + /// of the key, so the `StringRef` must outlive the context. + llvm::DenseMap nameToType; + /// Cached Type Instances. Float8E5M2Type f8E5M2Ty; Float8E4M3FNType f8E4M3FNTy; @@ -236,6 +243,14 @@ public: DenseMap registeredAttributes; StorageUniquer attributeUniquer; + /// This is a mapping from attribute name to the abstract attribute describing + /// it. It is used by `AbstractType::lookup` to get an `AbstractType` from a + /// name. + /// As this map needs to be populated before `StringAttr` is loaded, we + /// cannot use `StringAttr` as the key. The context does not take ownership + /// of the key, so the `StringRef` must outlive the context. + llvm::DenseMap nameToAttribute; + /// Cached Attribute Instances. BoolAttr falseAttr, trueAttr; UnitAttr unitAttr; @@ -697,6 +712,9 @@ void Dialect::addType(TypeID typeID, AbstractType &&typeInfo) { AbstractType(std::move(typeInfo)); if (!impl.registeredTypes.insert({typeID, newInfo}).second) llvm::report_fatal_error("Dialect Type already registered."); + if (!impl.nameToType.insert({newInfo->getName(), newInfo}).second) + llvm::report_fatal_error("Dialect Type with name " + newInfo->getName() + + " is already registered."); } void Dialect::addAttribute(TypeID typeID, AbstractAttribute &&attrInfo) { @@ -709,6 +727,9 @@ void Dialect::addAttribute(TypeID typeID, AbstractAttribute &&attrInfo) { AbstractAttribute(std::move(attrInfo)); if (!impl.registeredAttributes.insert({typeID, newInfo}).second) llvm::report_fatal_error("Dialect Attribute already registered."); + if (!impl.nameToAttribute.insert({newInfo->getName(), newInfo}).second) + llvm::report_fatal_error("Dialect Attribute with name " + + newInfo->getName() + " is already registered."); } //===----------------------------------------------------------------------===// @@ -731,6 +752,16 @@ AbstractAttribute *AbstractAttribute::lookupMutable(TypeID typeID, return impl.registeredAttributes.lookup(typeID); } +std::optional> +AbstractAttribute::lookup(StringRef name, MLIRContext *context) { + MLIRContextImpl &impl = context->getImpl(); + const AbstractAttribute *type = impl.nameToAttribute.lookup(name); + + if (!type) + return std::nullopt; + return {*type}; +} + //===----------------------------------------------------------------------===// // OperationName //===----------------------------------------------------------------------===// @@ -864,8 +895,8 @@ void OperationName::UnregisteredOpModel::copyProperties(OpaqueProperties lhs, OpaqueProperties rhs) { *lhs.as() = *rhs.as(); } -bool OperationName::UnregisteredOpModel::compareProperties(OpaqueProperties lhs, - OpaqueProperties rhs) { +bool OperationName::UnregisteredOpModel::compareProperties( + OpaqueProperties lhs, OpaqueProperties rhs) { return *lhs.as() == *rhs.as(); } llvm::hash_code @@ -945,6 +976,16 @@ AbstractType *AbstractType::lookupMutable(TypeID typeID, MLIRContext *context) { return impl.registeredTypes.lookup(typeID); } +std::optional> +AbstractType::lookup(StringRef name, MLIRContext *context) { + MLIRContextImpl &impl = context->getImpl(); + const AbstractType *type = impl.nameToType.lookup(name); + + if (!type) + return std::nullopt; + return {*type}; +} + //===----------------------------------------------------------------------===// // Type uniquing //===----------------------------------------------------------------------===// diff --git a/mlir/lib/TableGen/AttrOrTypeDef.cpp b/mlir/lib/TableGen/AttrOrTypeDef.cpp index 56c96ffd159c..c9dbb3bc76b1 100644 --- a/mlir/lib/TableGen/AttrOrTypeDef.cpp +++ b/mlir/lib/TableGen/AttrOrTypeDef.cpp @@ -220,6 +220,22 @@ bool AttrDef::classof(const AttrOrTypeDef *def) { return def->getDef()->isSubClassOf("AttrDef"); } +StringRef AttrDef::getAttrName() const { + return def->getValueAsString("attrName"); +} + +//===----------------------------------------------------------------------===// +// TypeDef +//===----------------------------------------------------------------------===// + +bool TypeDef::classof(const AttrOrTypeDef *def) { + return def->getDef()->isSubClassOf("TypeDef"); +} + +StringRef TypeDef::getTypeName() const { + return def->getValueAsString("typeName"); +} + //===----------------------------------------------------------------------===// // AttrOrTypeParameter //===----------------------------------------------------------------------===// diff --git a/mlir/test/lib/Dialect/Test/TestTypes.h b/mlir/test/lib/Dialect/Test/TestTypes.h index 0ce86dd70ab9..b1b5921d8fad 100644 --- a/mlir/test/lib/Dialect/Test/TestTypes.h +++ b/mlir/test/lib/Dialect/Test/TestTypes.h @@ -14,8 +14,8 @@ #ifndef MLIR_TESTTYPES_H #define MLIR_TESTTYPES_H -#include #include +#include #include "TestTraits.h" #include "mlir/IR/Diagnostics.h" @@ -132,6 +132,8 @@ class TestRecursiveType public: using Base::Base; + static constexpr ::mlir::StringLiteral name = "test.recursive"; + static TestRecursiveType get(::mlir::MLIRContext *ctx, ::llvm::StringRef name) { return Base::get(ctx, name); diff --git a/mlir/test/mlir-tblgen/attrdefs.td b/mlir/test/mlir-tblgen/attrdefs.td index 0fb6958799b2..5683f343c6bb 100644 --- a/mlir/test/mlir-tblgen/attrdefs.td +++ b/mlir/test/mlir-tblgen/attrdefs.td @@ -63,6 +63,7 @@ def C_IndexAttr : TestAttr<"Index"> { } def A_SimpleAttrA : TestAttr<"SimpleA"> { + let attrName = "test.simple"; // DECL: class SimpleAAttr : public ::mlir::Attribute } @@ -123,6 +124,7 @@ def D_SingleParameterAttr : TestAttr<"SingleParameter"> { ins "int": $num ); + let attrName = "test.single_parameter"; // DECL-LABEL: struct SingleParameterAttrStorage; // DECL-LABEL: class SingleParameterAttr // DECL-SAME: detail::SingleParameterAttrStorage @@ -130,6 +132,7 @@ def D_SingleParameterAttr : TestAttr<"SingleParameter"> { def F_ParamWithAccessorTypeAttr : TestAttr<"ParamWithAccessorType"> { let parameters = (ins AttrParameter<"std::string", "", "StringRef">:$param); + let attrName = "test.param_with_accessor_type"; } // DECL-LABEL: class ParamWithAccessorTypeAttr @@ -142,6 +145,7 @@ def G_BuilderWithReturnTypeAttr : TestAttr<"BuilderWithReturnType"> { let parameters = (ins "int":$a); let genVerifyDecl = 1; let builders = [AttrBuilder<(ins), [{ return {}; }], "::mlir::Attribute">]; + let attrName = "test.builder_with_return_type"; } // DECL-LABEL: class BuilderWithReturnTypeAttr @@ -158,6 +162,7 @@ def H_TestExtraClassAttr : TestAttr<"TestExtraClass"> { return i+1; } }]; + let attrName = "test.test_extra_class"; } // DECL-LABEL: TestExtraClassAttr : public ::mlir::Attribute diff --git a/mlir/test/mlir-tblgen/op-attribute.td b/mlir/test/mlir-tblgen/op-attribute.td index f81fc3df857e..07636f53c1e1 100644 --- a/mlir/test/mlir-tblgen/op-attribute.td +++ b/mlir/test/mlir-tblgen/op-attribute.td @@ -22,6 +22,7 @@ def SomeAttr : Attr, "some attribute kind"> { } def SomeAttrDef : AttrDef { + let attrName = "test.some_attr"; } diff --git a/mlir/test/mlir-tblgen/op-decl-and-defs.td b/mlir/test/mlir-tblgen/op-decl-and-defs.td index 85d68cc42ccb..ca133fafdcb5 100644 --- a/mlir/test/mlir-tblgen/op-decl-and-defs.td +++ b/mlir/test/mlir-tblgen/op-decl-and-defs.td @@ -358,7 +358,9 @@ def Test_Dialect2 : Dialect { let name = "test"; let cppNamespace = "::mlir::dialect2"; } -def TestDialect2Type : TypeDef; +def TestDialect2Type : TypeDef { + let typeName = "test.type"; +} def NS_ResultWithDialectTypeOp : NS_Op<"op_with_dialect_type", []> { let results = (outs TestDialect2Type); diff --git a/mlir/test/mlir-tblgen/typedefs.td b/mlir/test/mlir-tblgen/typedefs.td index 51006635a75a..705da4e41b78 100644 --- a/mlir/test/mlir-tblgen/typedefs.td +++ b/mlir/test/mlir-tblgen/typedefs.td @@ -45,6 +45,7 @@ class TestType : TypeDef { } def A_SimpleTypeA : TestType<"SimpleA"> { // DECL: class SimpleAType : public ::mlir::Type + let typeName = "test.simple_a"; } def RTLValueType : Type, "Type"> { @@ -97,6 +98,7 @@ def C_IndexType : TestType<"Index"> { } def D_SingleParameterType : TestType<"SingleParameter"> { + let typeName = "test.d_single_parameter"; let parameters = (ins "int": $num ); diff --git a/mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp b/mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp index 8889dff7a587..b9a72119790e 100644 --- a/mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp +++ b/mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp @@ -87,6 +87,8 @@ private: /// Emit top-level declarations: using declarations and any extra class /// declarations. void emitTopLevelDeclarations(); + /// Emit the function that returns the type or attribute name. + void emitName(); /// Emit attribute or type builders. void emitBuilders(); /// Emit a verifier for the def. @@ -180,6 +182,8 @@ DefGen::DefGen(const AttrOrTypeDef &def) // Emit builders for defs with parameters if (storageCls) emitBuilders(); + // Emit the type name. + emitName(); // Emit the verifier. if (storageCls && def.genVerifyDecl()) emitVerifier(); @@ -264,6 +268,19 @@ void DefGen::emitTopLevelDeclarations() { std::move(extraDef)); } +void DefGen::emitName() { + StringRef name; + if (auto *attrDef = dyn_cast(&def)) { + name = attrDef->getAttrName(); + } else { + auto *typeDef = cast(&def); + name = typeDef->getTypeName(); + } + std::string nameDecl = + strfmt("static constexpr ::llvm::StringLiteral name = \"{0}\";\n", name); + defCls.declare(std::move(nameDecl)); +} + void DefGen::emitBuilders() { if (!def.skipDefaultBuilders()) { emitDefaultBuilder(); diff --git a/mlir/unittests/IR/CMakeLists.txt b/mlir/unittests/IR/CMakeLists.txt index 6d05af193dfa..1ed46869c2c8 100644 --- a/mlir/unittests/IR/CMakeLists.txt +++ b/mlir/unittests/IR/CMakeLists.txt @@ -10,6 +10,7 @@ add_mlir_unittest(MLIRIRTests ShapedTypeTest.cpp SymbolTableTest.cpp TypeTest.cpp + TypeAttrNamesTest.cpp OpPropertiesTest.cpp DEPENDS diff --git a/mlir/unittests/IR/TypeAttrNamesTest.cpp b/mlir/unittests/IR/TypeAttrNamesTest.cpp new file mode 100644 index 000000000000..488c164b23b4 --- /dev/null +++ b/mlir/unittests/IR/TypeAttrNamesTest.cpp @@ -0,0 +1,90 @@ +//===- TypeAttrNamesTest.cpp - Type API unit tests ------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file test the lookup of AbstractType / AbstractAttribute by name. +// +//===----------------------------------------------------------------------===// + +#include "mlir/IR/Attributes.h" +#include "mlir/IR/BuiltinTypes.h" +#include "mlir/IR/Dialect.h" +#include "mlir/IR/Types.h" +#include "mlir/IR/Value.h" +#include "mlir/Support/TypeID.h" +#include "gtest/gtest.h" + +using namespace mlir; + +namespace { +struct FooType : Type::TypeBase { + using Base::Base; + + static constexpr StringLiteral name = "fake.foo"; + + MLIR_DEFINE_EXPLICIT_INTERNAL_INLINE_TYPE_ID(FooType) +}; + +struct BarAttr : Attribute::AttrBase { + using Base::Base; + + static constexpr StringLiteral name = "fake.bar"; + + MLIR_DEFINE_EXPLICIT_INTERNAL_INLINE_TYPE_ID(BarAttr) +}; + +struct FakeDialect : Dialect { + FakeDialect(MLIRContext *context) + : Dialect(getDialectNamespace(), context, TypeID::get()) { + addTypes(); + addAttributes(); + } + + static constexpr ::llvm::StringLiteral getDialectNamespace() { + return ::llvm::StringLiteral("fake"); + } + + MLIR_DEFINE_EXPLICIT_INTERNAL_INLINE_TYPE_ID(FakeDialect) +}; +} // namespace + +TEST(AbstractType, LookupWithString) { + MLIRContext ctx; + ctx.loadDialect(); + + // Check that we can lookup an abstract type by name. + auto fooAbstractType = AbstractType::lookup("fake.foo", &ctx); + EXPECT_TRUE(fooAbstractType.has_value()); + EXPECT_TRUE(fooAbstractType->get().getName() == "fake.foo"); + + // Check that the abstract type is the same as the one used by the type. + auto fooType = FooType::get(&ctx); + EXPECT_TRUE(&fooType.getAbstractType() == &fooAbstractType->get()); + + // Check that lookups of non-existing types returns nullopt. + // Even if an attribute with the same name exists. + EXPECT_FALSE(AbstractType::lookup("fake.bar", &ctx).has_value()); +} + +TEST(AbstractAttribute, LookupWithString) { + MLIRContext ctx; + ctx.loadDialect(); + + // Check that we can lookup an abstract type by name. + auto barAbstractAttr = AbstractAttribute::lookup("fake.bar", &ctx); + EXPECT_TRUE(barAbstractAttr.has_value()); + EXPECT_TRUE(barAbstractAttr->get().getName() == "fake.bar"); + + // Check that the abstract Attribute is the same as the one used by the + // Attribute. + auto barAttr = BarAttr::get(&ctx); + EXPECT_TRUE(&barAttr.getAbstractAttribute() == &barAbstractAttr->get()); + + // Check that lookups of non-existing Attributes returns nullopt. + // Even if an attribute with the same name exists. + EXPECT_FALSE(AbstractAttribute::lookup("fake.foo", &ctx).has_value()); +} diff --git a/mlir/unittests/IR/TypeTest.cpp b/mlir/unittests/IR/TypeTest.cpp index 1bb9d077d8ed..30f6642a9ca7 100644 --- a/mlir/unittests/IR/TypeTest.cpp +++ b/mlir/unittests/IR/TypeTest.cpp @@ -19,6 +19,9 @@ struct LeafType; struct MiddleType : Type::TypeBase { using Base::Base; + + static constexpr StringLiteral name = "test.middle"; + static bool classof(Type ty) { return ty.getTypeID() == TypeID::get() || Base::classof(ty); } @@ -26,6 +29,8 @@ struct MiddleType : Type::TypeBase { struct LeafType : Type::TypeBase { using Base::Base; + + static constexpr StringLiteral name = "test.leaf"; }; struct FakeDialect : Dialect { diff --git a/mlir/unittests/Interfaces/DataLayoutInterfacesTest.cpp b/mlir/unittests/Interfaces/DataLayoutInterfacesTest.cpp index 21b9e7b5ac2c..79599b8c4850 100644 --- a/mlir/unittests/Interfaces/DataLayoutInterfacesTest.cpp +++ b/mlir/unittests/Interfaces/DataLayoutInterfacesTest.cpp @@ -56,6 +56,9 @@ struct CustomDataLayoutSpec MLIR_DEFINE_EXPLICIT_INTERNAL_INLINE_TYPE_ID(CustomDataLayoutSpec) using Base::Base; + + static constexpr StringLiteral name = "test.custom_data_layout_spec"; + static CustomDataLayoutSpec get(MLIRContext *ctx, ArrayRef entries) { return Base::get(ctx, entries); @@ -83,6 +86,8 @@ struct SingleQueryType using Base::Base; + static constexpr StringLiteral name = "test.single_query"; + static SingleQueryType get(MLIRContext *ctx) { return Base::get(ctx); } llvm::TypeSize getTypeSizeInBits(const DataLayout &layout, @@ -131,6 +136,8 @@ struct TypeNoLayout : public Type::TypeBase { using Base::Base; + static constexpr StringLiteral name = "test.no_layout"; + static TypeNoLayout get(MLIRContext *ctx) { return Base::get(ctx); } }; -- GitLab From b8b2a279d002f4d424d9b089bc32a0e5d6989dbb Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Thu, 30 Nov 2023 15:52:02 -0800 Subject: [PATCH 071/699] [OpenMP][NFC] Encapsulate profiling logic (#74003) This simply puts the profiling logic into the `Profiler` class and allows non-RAII profiling via `beginSection` and `endSection`. --- openmp/docs/design/Runtimes.rst | 7 +++ openmp/libomptarget/include/Shared/Profile.h | 64 ++++++++++++++++++++ openmp/libomptarget/src/rtl.cpp | 16 +---- 3 files changed, 72 insertions(+), 15 deletions(-) diff --git a/openmp/docs/design/Runtimes.rst b/openmp/docs/design/Runtimes.rst index e7371b34e035..9002fa62348f 100644 --- a/openmp/docs/design/Runtimes.rst +++ b/openmp/docs/design/Runtimes.rst @@ -708,6 +708,7 @@ variables is defined below. * ``LIBOMPTARGET_DEBUG=`` * ``LIBOMPTARGET_PROFILE=`` + * ``LIBOMPTARGET_PROFILE_GRANULARITY= (default 500, in us)`` * ``LIBOMPTARGET_MEMORY_MANAGER_THRESHOLD=`` * ``LIBOMPTARGET_INFO=`` * ``LIBOMPTARGET_HEAP_SIZE=`` @@ -749,6 +750,12 @@ for time trace output. Note that this will turn ``libomp`` into a C++ library. .. _`LLVM Support Library`: https://llvm.org/docs/SupportLibrary.html +LIBOMPTARGET_PROFILE_GRANULARITY +"""""""""""""""""""""""""""""""" + +``LIBOMPTARGET_PROFILE_GRANULARITY`` allows to change the time profile +granularity measured in `us`. Default is 500 (`us`). + LIBOMPTARGET_MEMORY_MANAGER_THRESHOLD """"""""""""""""""""""""""""""""""""" diff --git a/openmp/libomptarget/include/Shared/Profile.h b/openmp/libomptarget/include/Shared/Profile.h index bbdefea06d90..316b0c3086d0 100644 --- a/openmp/libomptarget/include/Shared/Profile.h +++ b/openmp/libomptarget/include/Shared/Profile.h @@ -10,8 +10,70 @@ // //===----------------------------------------------------------------------===// +#ifndef OMPTARGET_SHARED_PROFILE_H +#define OMPTARGET_SHARED_PROFILE_H + +#include "Shared/Debug.h" +#include "Shared/EnvironmentVar.h" + +#include "llvm/ADT/StringRef.h" +#include "llvm/Support/Error.h" #include "llvm/Support/TimeProfiler.h" +/// Class that holds the singleton profiler and allows to start/end events. +class Profiler { + + Profiler() { + if (!ProfileTraceFile.isPresent()) + return; + + // TODO: Add an alias without LIBOMPTARGET + // Flag to modify the profile granularity (in us). + Int32Envar ProfileGranularity = + Int32Envar("LIBOMPTARGET_PROFILE_GRANULARITY", 500); + + llvm::timeTraceProfilerInitialize(ProfileGranularity /* us */, + "libomptarget"); + } + + ~Profiler() { + if (!ProfileTraceFile.isPresent()) + return; + + if (auto Err = llvm::timeTraceProfilerWrite(ProfileTraceFile.get(), "-")) + REPORT("Error writing out the time trace: %s\n", + llvm::toString(std::move(Err)).c_str()); + + llvm::timeTraceProfilerCleanup(); + } + + // TODO: Add an alias without LIBOMPTARGET + /// Flag to enable profiling which also specifies the file profile information + /// is stored in. + StringEnvar ProfileTraceFile = StringEnvar("LIBOMPTARGET_PROFILE"); + +public: + static Profiler &get() { + static Profiler P; + return P; + } + + /// Manually begin a time section, with the given \p Name and \p Detail. + /// Profiler copies the string data, so the pointers can be given into + /// temporaries. Time sections can be hierarchical; every Begin must have a + /// matching End pair but they can nest. + void beginSection(llvm::StringRef Name, llvm::StringRef Detail) { + llvm::timeTraceProfilerBegin(Name, Detail); + } + void beginSection(llvm::StringRef Name, + llvm::function_ref Detail) { + llvm::timeTraceProfilerBegin(Name, Detail); + } + + /// Manually end the last time section. + void endSection() { llvm::timeTraceProfilerEnd(); } +}; + /// Time spend in the current scope, assigned to the function name. #define TIMESCOPE() llvm::TimeTraceScope TimeScope(__FUNCTION__) @@ -34,3 +96,5 @@ std::string ProfileLocation = SI.getProfileLocation(); \ std::string RTM = RegionTypeMsg; \ llvm::TimeTraceScope TimeScope(__FUNCTION__, ProfileLocation + RTM) + +#endif // OMPTARGET_SHARED_PROFILE_H diff --git a/openmp/libomptarget/src/rtl.cpp b/openmp/libomptarget/src/rtl.cpp index 09084be12a76..42d147d1c145 100644 --- a/openmp/libomptarget/src/rtl.cpp +++ b/openmp/libomptarget/src/rtl.cpp @@ -41,8 +41,6 @@ static const char *RTLNames[] = { /* AMDGPU target */ "libomptarget.rtl.amdgpu", }; -static char *ProfileTraceFile = nullptr; - #ifdef OMPT_SUPPORT extern void ompt::connectLibrary(); #endif @@ -64,16 +62,12 @@ __attribute__((constructor(101))) void init() { PM = new PluginManager(UseEventsForAtomicTransfers); - ProfileTraceFile = getenv("LIBOMPTARGET_PROFILE"); - // TODO: add a configuration option for time granularity - if (ProfileTraceFile) - timeTraceProfilerInitialize(500 /* us */, "libomptarget"); - #ifdef OMPT_SUPPORT // Initialize OMPT first ompt::connectLibrary(); #endif + Profiler::get(); PM->RTLs.loadRTLs(); PM->registerDelayedLibraries(); } @@ -81,14 +75,6 @@ __attribute__((constructor(101))) void init() { __attribute__((destructor(101))) void deinit() { DP("Deinit target library!\n"); delete PM; - - if (ProfileTraceFile) { - // TODO: add env var for file output - if (auto E = timeTraceProfilerWrite(ProfileTraceFile, "-")) - fprintf(stderr, "Error writing out the time trace\n"); - - timeTraceProfilerCleanup(); - } } void PluginAdaptorManagerTy::loadRTLs() { -- GitLab From 7ae1b76ed7271b2e86a3cda72d9e1fc63f4e5c48 Mon Sep 17 00:00:00 2001 From: Kirill Stoimenov Date: Fri, 1 Dec 2023 00:32:26 +0000 Subject: [PATCH 072/699] Fix ARM Sanitizer build Example: https://lab.llvm.org/buildbot/#/builders/239/builds/4709 --- clang/test/Index/initializer-memory.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/test/Index/initializer-memory.cpp b/clang/test/Index/initializer-memory.cpp index da7344412576..06e26d6fac73 100644 --- a/clang/test/Index/initializer-memory.cpp +++ b/clang/test/Index/initializer-memory.cpp @@ -13,4 +13,4 @@ struct S { S data2[1000000] = {0}; S data_empty_init2[1000000] = {}; -// CHECK: TOTAL = {{.*}} (0.{{.*}} MBytes) +// CHECK: TOTAL = {{.*}} ({{0|1}}.{{.*}} MBytes) -- GitLab From b6cad75e077e1c68449b18ffeb6e93f18463464f Mon Sep 17 00:00:00 2001 From: Peiming Liu <36770114+PeimingLiu@users.noreply.github.com> Date: Thu, 30 Nov 2023 16:40:11 -0800 Subject: [PATCH 073/699] [mlir][sparse] refactoring: using util functions to query the index to load from position array for slice-driven loop. (#73986) --- .../SparseTensor/Transforms/LoopEmitter.cpp | 167 ++++--- .../SparsificationAndBufferizationPass.cpp | 2 +- .../sparse_conv_2d_slice_based.mlir | 413 +++++++++--------- 3 files changed, 308 insertions(+), 274 deletions(-) diff --git a/mlir/lib/Dialect/SparseTensor/Transforms/LoopEmitter.cpp b/mlir/lib/Dialect/SparseTensor/Transforms/LoopEmitter.cpp index 26f015ce6ec6..9c6dc320467c 100644 --- a/mlir/lib/Dialect/SparseTensor/Transforms/LoopEmitter.cpp +++ b/mlir/lib/Dialect/SparseTensor/Transforms/LoopEmitter.cpp @@ -148,23 +148,60 @@ static Value genSparseReducedAffineCond(OpBuilder &builder, Location loc, // Helper functions that load/store into the position buffer for slice-driven // loops. // The sliced pointer buffer is orgnized as: -// [size, curPtr] (two metadata) + [[pLo, pHi, pNext], ...] (list of tuples) +// [size, curPtr] (two metadata) + [[pLo0, pLo1, pLo2, ...], +// [pHi0, pHi1, pHi2, ...], +// [pNx0, pNx1, pNx2, ...]] +static Value allocSlicePosBuf(OpBuilder &builder, Location loc, + Value tupleCnt) { + Value bufSz = MULI(tupleCnt, C_IDX(kSliceIterWidth)); + // Additional two metadata {memSize, idx} at head. + bufSz = ADDI(bufSz, C_IDX(2)); + return genAlloca(builder, loc, bufSz, builder.getIndexType()); +} +// TODO: We should use SSA value for it. +// Gets and sets metadata. static Value loadSlicePosPtr(OpBuilder &builder, Location loc, Value sPosBuf) { - // Load curPtr. - // TODO: We should use SSA value for it. return genIndexLoad(builder, loc, sPosBuf, C_IDX(1)); } static void updateSlicePosPtr(OpBuilder &builder, Location loc, Value sPosBuf, Value pPtr) { - // Set curPtr. - // TODO: We should use SSA value for it. builder.create(loc, pPtr, sPosBuf, C_IDX(1)); } -static Value loadSliceNextPosPtrStart(OpBuilder &builder, Location loc, - Value sPosBuf, Value tupleIdx) { - // load the pNext in the current tuple specified by `tupleIdx`. - // 4 = 2 (two metadata) + 2 (pNext == tuple[2]) - return genIndexLoad(builder, loc, sPosBuf, ADDI(tupleIdx, C_IDX(4))); +static Value loadSlicePosTupleNum(OpBuilder &builder, Location loc, + Value sPosBuf) { + return genIndexLoad(builder, loc, sPosBuf, C_IDX(0)); +} +static void updateSlicePosTupleNum(OpBuilder &builder, Location loc, Value num, + Value sPosBuf) { + builder.create(loc, num, sPosBuf, C_IDX(0)); +} + +// Gets and sets position values for slice-driven loops. +enum class SlicePosKind { kLo, kHi, kNext }; +static Value getSlicePosIdx(OpBuilder &builder, Location loc, Value posBuf, + Value tupleIdx, SlicePosKind posKind) { + Value dim = builder.create(loc, posBuf, C_IDX(0)); + Value tupleCnt = DIVUI(SUBI(dim, C_IDX(2)), C_IDX(kSliceIterWidth)); + switch (posKind) { + case SlicePosKind::kLo: + return ADDI(tupleIdx, C_IDX(2)); + case SlicePosKind::kHi: + return ADDI(tupleIdx, ADDI(tupleCnt, C_IDX(2))); + case SlicePosKind::kNext: + return ADDI(tupleIdx, ADDI(tupleCnt, ADDI(tupleCnt, C_IDX(2)))); + } + llvm_unreachable("unexpected kind"); +} +static Value loadSlicePos(OpBuilder &builder, Location loc, Value sPosBuf, + Value tupleIdx, SlicePosKind posKind) { + return genIndexLoad(builder, loc, sPosBuf, + getSlicePosIdx(builder, loc, sPosBuf, tupleIdx, posKind)); +} +static void updateSlicePos(OpBuilder &builder, Location loc, Value sPosBuf, + Value pos, Value tupleIdx, SlicePosKind posKind) { + builder.create( + loc, pos, sPosBuf, + getSlicePosIdx(builder, loc, sPosBuf, tupleIdx, posKind)); } std::pair @@ -1445,13 +1482,13 @@ void LoopEmitter::forwardsReducedSliceLevelTreeIt(OpBuilder &builder, // The first compressed level, setting up the position pointer for it. Value sPosBuf = slicePosBuffer[tid][curLvl].back(); // One step forwards in the parent level result in forwarding one `segment` - // (kSliceIterWidth) in the child sparse level. - Value fPosPtr = MULI(fcnt, C_IDX(kSliceIterWidth)); // forward ptr + // in the child sparse level. Value pPosPtr = loadSlicePosPtr(builder, loc, sPosBuf); // previous ptr - Value cPosPtr = ADDI(fPosPtr, pPosPtr); // current ptr + Value cPosPtr = ADDI(fcnt, pPosPtr); // current ptr updateSlicePosPtr(builder, loc, sPosBuf, cPosPtr); // Loads the position pointer start for next level. - nxPosPtr = loadSliceNextPosPtrStart(builder, loc, sPosBuf, cPosPtr); + nxPosPtr = + loadSlicePos(builder, loc, sPosBuf, cPosPtr, SlicePosKind::kNext); curLvl++; } @@ -1463,10 +1500,10 @@ void LoopEmitter::forwardsReducedSliceLevelTreeIt(OpBuilder &builder, for (; curLvl < leafLvl; curLvl++) { assert(nxPosPtr); if (!isDenseLT(lvlTypes[tid][curLvl])) { - nxPosPtr = MULI(nxPosPtr, C_IDX(kSliceIterWidth)); Value sPosBuf = slicePosBuffer[tid][curLvl].back(); updateSlicePosPtr(builder, loc, sPosBuf, nxPosPtr); - nxPosPtr = loadSliceNextPosPtrStart(builder, loc, sPosBuf, nxPosPtr); + nxPosPtr = + loadSlicePos(builder, loc, sPosBuf, nxPosPtr, SlicePosKind::kNext); } } } @@ -1736,7 +1773,7 @@ ValueRange LoopEmitter::genUnResolvedSliceTreeTraverse( std::optional> firstResLvl, ValueRange userReduc, LoopBodyBuilder bodyBuilder) { - Value c0 = C_IDX(0), c1 = C_IDX(1), c2 = C_IDX(2); + Value c0 = C_IDX(0), c1 = C_IDX(1); Value pos = c0; OpBuilder::InsertPoint ip; SmallVector innerArgs(userReduc.begin(), userReduc.end()); @@ -1769,20 +1806,22 @@ ValueRange LoopEmitter::genUnResolvedSliceTreeTraverse( unsigned depth = frontSlice.depth - 1; Value offset = frontSlice.offset; Value sPtrBuf = slicePosBuffer[tid][firstLvl][depth]; - Value mSz = genIndexLoad(builder, loc, sPtrBuf, c0); // memSize + Value mSz = loadSlicePosTupleNum(builder, loc, sPtrBuf); outerMost = builder.create( - loc, c2, mSz, C_IDX(kSliceIterWidth), innerArgs, - [this, c1, c2, tid, firstLvl, offset, sPtrBuf, &ip, &pos, + loc, c0, mSz, c1, innerArgs, + [this, tid, firstLvl, offset, sPtrBuf, &ip, &pos, &innerArgs](OpBuilder &builder, Location loc, Value iv, ValueRange iterArgs) { // generate traversal for each level. - Value loopLo = genIndexLoad(builder, loc, sPtrBuf, iv); - Value loopHi = genIndexLoad(builder, loc, sPtrBuf, ADDI(iv, c1)); + Value loopLo = + loadSlicePos(builder, loc, sPtrBuf, iv, SlicePosKind::kLo); + Value loopHi = + loadSlicePos(builder, loc, sPtrBuf, iv, SlicePosKind::kHi); // We need to remember the starting index for next level's // position, because slice-driven loop breaks the level into // non-consecutive segments. - builder.create(loc, iterArgs.back(), sPtrBuf, - ADDI(iv, c2).getResult()); + updateSlicePos(builder, loc, sPtrBuf, iterArgs.back(), iv, + SlicePosKind::kNext); auto [size, stride] = sliceMeta[tid][firstLvl].back(); assert(stride == 1 && "Not yet implemented"); @@ -1873,8 +1912,7 @@ ValueRange LoopEmitter::genUnResolvedSliceTreeTraverse( void LoopEmitter::genResolvedSliceBegin(OpBuilder &builder, Location loc, TensorId tid, Level lvl) { - Value c0 = C_IDX(0), c1 = C_IDX(1), c2 = C_IDX(2), c3 = C_IDX(3), - c4 = C_IDX(4); + Value c0 = C_IDX(0), c1 = C_IDX(1); if (isDenseLT(lvlTypes[tid][lvl])) { // Dense slice begin is trivial. sliceStack[tid].emplace_back(/*minCoord=*/c0, /*offset=*/c0, @@ -1896,10 +1934,10 @@ void LoopEmitter::genResolvedSliceBegin(OpBuilder &builder, Location loc, ADDI(posits[tid][lvl - 1], c1)); } // Fills out pIdxBuffer[tid][lvl][0] with [/*memSize =*/4, 0, pLo, pHi] - builder.create(loc, c4, sPtrBuf, c0); // memSize = 4 - builder.create(loc, c0, sPtrBuf, c1); // index = 0 - builder.create(loc, pLo, sPtrBuf, c2); // pLo - builder.create(loc, pHi, sPtrBuf, c3); // pHi + updateSlicePosTupleNum(builder, loc, c1, sPtrBuf); + updateSlicePosPtr(builder, loc, sPtrBuf, c0); + updateSlicePos(builder, loc, sPtrBuf, pLo, c0, SlicePosKind::kLo); + updateSlicePos(builder, loc, sPtrBuf, pHi, c0, SlicePosKind::kHi); // This is an non empty tensor if pLo < pHi. Value isNonEmpty = CMPI(ult, pLo, pHi); @@ -1938,7 +1976,7 @@ void LoopEmitter::genResolvedSliceBegin(OpBuilder &builder, Location loc, // } void LoopEmitter::genUnResolvedSliceBegin(OpBuilder &builder, Location loc, TensorId tid, Level lvl) { - Value c0 = C_IDX(0), c1 = C_IDX(1), c2 = C_IDX(2); + Value c0 = C_IDX(0), c1 = C_IDX(1); unsigned depth = levelReducedDep[tid][lvl]; // The remaining slice size after reduction. Value remSz = sliceMeta[tid][lvl][depth + 1].first; @@ -1983,7 +2021,7 @@ void LoopEmitter::genUnResolvedSliceBegin(OpBuilder &builder, Location loc, SmallVector reduc = { constantI1(builder, loc, false), // isNonEmpty lvlSizes[tid][lvl], // minCoord - c2, // memSize + c0, // memSize }; ValueRange result = genUnResolvedSliceTreeTraverse( @@ -1992,7 +2030,7 @@ void LoopEmitter::genUnResolvedSliceBegin(OpBuilder &builder, Location loc, MutableArrayRef reduc) { Value &nonEmpty = reduc[0]; Value &minCrd = reduc[1]; - Value &curMemSz = reduc[2]; + Value &curTupleCnt = reduc[2]; Value pHi = ADDI(iv, c1); Value sPLo = genIndexLoad(builder, loc, positionsBuffers[tid][lvl], iv); @@ -2024,19 +2062,19 @@ void LoopEmitter::genUnResolvedSliceBegin(OpBuilder &builder, Location loc, YIELD(minCrd); } minCrd = ifNonEmpty.getResult(0); - builder.create(loc, sPLo, sPtrBuf, curMemSz); - Value nxtMemSize = ADDI(curMemSz, c1); - builder.create(loc, sPHi, sPtrBuf, nxtMemSize); - // curMemSize += kSliceIterWidth - curMemSz = ADDI(curMemSz, C_IDX(kSliceIterWidth)); + updateSlicePos(builder, loc, sPtrBuf, sPLo, curTupleCnt, + SlicePosKind::kLo); + updateSlicePos(builder, loc, sPtrBuf, sPHi, curTupleCnt, + SlicePosKind::kHi); + curTupleCnt = ADDI(curTupleCnt, C_IDX(1)); }); Value isNonEmpty = result[0]; Value minCrd = result[1]; // Two metadata [memSize, idx]. // TODO: Can use an SSA value for these two metadata - builder.create(loc, result[2], sPtrBuf, c0); - builder.create(loc, c0, sPtrBuf, c1); + updateSlicePosTupleNum(builder, loc, result[2], sPtrBuf); + updateSlicePosPtr(builder, loc, sPtrBuf, c0); // FIXME: we need the relative offset related to the base slice. Value absOffset = offsetFromMinCoord(builder, loc, minCrd, remSz, isNonEmpty); sliceStack[tid].emplace_back(minCrd, absOffset, isNonEmpty, lvl, depth + 1); @@ -2044,8 +2082,6 @@ void LoopEmitter::genUnResolvedSliceBegin(OpBuilder &builder, Location loc, bool LoopEmitter::genSliceBegin(OpBuilder &builder, Location loc, TensorId tid, Level lvl) { - Value c1 = C_IDX(1), c2 = C_IDX(2); - if (depFullyReduced(tid, lvl)) { // Do not need to prepare for slice driven loop on dense level after it is // fully reduced. @@ -2054,14 +2090,12 @@ bool LoopEmitter::genSliceBegin(OpBuilder &builder, Location loc, TensorId tid, // If constraints on the tensor is fully resolved. We do not need to // generates slice begin any more, instead we fall back to TACO-based // algorithm to (co)iterates over the slice. - Value pLoPtr = - loadSlicePosPtr(builder, loc, slicePosBuffer[tid][lvl].back()); - pLoPtr = ADDI(pLoPtr, c2); - Value pHiPtr = ADDI(pLoPtr, c1); + Value sPosBuf = slicePosBuffer[tid][lvl].back(); + Value tupleIdx = loadSlicePosPtr(builder, loc, sPosBuf); posits[tid][lvl] = - genIndexLoad(builder, loc, slicePosBuffer[tid][lvl].back(), pLoPtr); + loadSlicePos(builder, loc, sPosBuf, tupleIdx, SlicePosKind::kLo); highs[tid][lvl] = - genIndexLoad(builder, loc, slicePosBuffer[tid][lvl].back(), pHiPtr); + loadSlicePos(builder, loc, sPosBuf, tupleIdx, SlicePosKind::kHi); return true; } @@ -2090,8 +2124,7 @@ bool LoopEmitter::genSliceBegin(OpBuilder &builder, Location loc, TensorId tid, // The buffer can be reused, and the size is loop invariant: it only // depends on the iteration graph's toposort. builder.setInsertionPointAfter(localInsertPos); - Value bufSize = C_IDX(1); - Value c2 = C_IDX(2); + Value tupleCnt = C_IDX(1); // Accumlates the size required to cache the pLo for the slice. // E.g., if we want to cache the pIdx for slice on the second // level. We at most need to a memref. @@ -2108,16 +2141,10 @@ bool LoopEmitter::genSliceBegin(OpBuilder &builder, Location loc, TensorId tid, assert(!sliceMeta[tid][curLevel - 1].empty()); auto [sz, stride] = sliceMeta[tid][curLevel - 1].back(); assert(stride == 1 && "Not yet implemented"); - bufSize = MULI(bufSize, sz); + tupleCnt = MULI(tupleCnt, sz); } - // For a triple of [pLo, pHi, pPtr]. Note that we can not compress pHi - // because slice creates segments in the index buffer so that the pHi for - // the current level is no longer the pLo for the next level. - bufSize = MULI(bufSize, C_IDX(kSliceIterWidth)); - // Additional two metadata {memSize, idx} at head. - bufSize = ADDI(bufSize, c2); for (Value &cache : slicePosBuffer[tid][lvl]) - cache = genAlloca(builder, loc, bufSize, builder.getIndexType()); + cache = allocSlicePosBuf(builder, loc, tupleCnt); } if (sliceInfo.isInitialTensor() || @@ -2147,7 +2174,7 @@ LoopEmitter::genSliceNextInduction(OpBuilder &builder, Location loc, llvm_unreachable("TODO"); // else generate code to compute next non empty slice. - Value c0 = C_IDX(0), c1 = C_IDX(1), c2 = C_IDX(2); + Value c0 = C_IDX(0), c1 = C_IDX(1); SliceInfo &info = sliceStack[tid].back(); assert(info.slicedOnLvl == lvl); @@ -2194,14 +2221,13 @@ LoopEmitter::genSliceNextInduction(OpBuilder &builder, Location loc, // offset = minCrd - size + 1; // } builder.setInsertionPointToStart(&ifOp.getElseRegion().front()); - reduc[2] = absOffset; // restore value. - Value pSt = c2; // pointer starting index - Value mSz = genIndexLoad(builder, loc, sPtrBuf, c0); // memSize - reduc[0] = lvlSizes[tid][lvl]; // next min coord - reduc[1] = constantI1(builder, loc, false); // isNonEmpty + reduc[2] = absOffset; // restore value. + Value mSz = loadSlicePosTupleNum(builder, loc, sPtrBuf); // memSize + reduc[0] = lvlSizes[tid][lvl]; // next min coord + reduc[1] = constantI1(builder, loc, false); // isNonEmpty auto loopArgs = static_cast(reduc).drop_back(); auto forOp = scf::buildLoopNest( - builder, loc, pSt, mSz, C_IDX(kSliceIterWidth), loopArgs, + builder, loc, c0, mSz, c1, loopArgs, [this, tid, lvl, c1, sPtrBuf, &info](OpBuilder &builder, Location loc, ValueRange ivs, ValueRange iterArgs) -> scf::ValueVector { @@ -2209,9 +2235,10 @@ LoopEmitter::genSliceNextInduction(OpBuilder &builder, Location loc, Value isNonEmpty = iterArgs[1]; Type idxTp = builder.getIndexType(); - Value pLo = genIndexLoad(builder, loc, sPtrBuf, ivs.front()); - Value pHi = - genIndexLoad(builder, loc, sPtrBuf, ADDI(ivs.front(), c1)); + Value pLo = loadSlicePos(builder, loc, sPtrBuf, ivs.front(), + SlicePosKind::kLo); + Value pHi = loadSlicePos(builder, loc, sPtrBuf, ivs.front(), + SlicePosKind::kHi); // // if (pLo < pHi) // Only loads when inbound. // coord = load[pLo] @@ -2235,8 +2262,8 @@ LoopEmitter::genSliceNextInduction(OpBuilder &builder, Location loc, &ifEqual.getThenRegion().front()); Value newPlo = ADDI(pLo, c1); // Updates the cache. - builder.create(loc, newPlo, sPtrBuf, - ivs.front()); + updateSlicePos(builder, loc, sPtrBuf, newPlo, ivs.front(), + SlicePosKind::kLo); YIELD(newPlo); } /* else coord != minCrd */ { diff --git a/mlir/lib/Dialect/SparseTensor/Transforms/SparsificationAndBufferizationPass.cpp b/mlir/lib/Dialect/SparseTensor/Transforms/SparsificationAndBufferizationPass.cpp index 94b25a358e80..6266c63064ff 100644 --- a/mlir/lib/Dialect/SparseTensor/Transforms/SparsificationAndBufferizationPass.cpp +++ b/mlir/lib/Dialect/SparseTensor/Transforms/SparsificationAndBufferizationPass.cpp @@ -150,8 +150,8 @@ public: pm.addPass( createSparseReinterpretMapPass(ReinterpretMapScope::kExceptGeneric)); pm.addNestedPass(createLowerForeachToSCFPass()); + pm.addPass(mlir::createLoopInvariantCodeMotionPass()); if (vectorLength > 0) { - pm.addPass(mlir::createLoopInvariantCodeMotionPass()); pm.addPass(createSparseVectorizationPass( vectorLength, enableVLAVectorization, enableSIMDIndex32)); } diff --git a/mlir/test/Dialect/SparseTensor/sparse_conv_2d_slice_based.mlir b/mlir/test/Dialect/SparseTensor/sparse_conv_2d_slice_based.mlir index 0cd57ac64b50..0f99a0206e4c 100644 --- a/mlir/test/Dialect/SparseTensor/sparse_conv_2d_slice_based.mlir +++ b/mlir/test/Dialect/SparseTensor/sparse_conv_2d_slice_based.mlir @@ -6,258 +6,265 @@ #DCSR = #sparse_tensor.encoding<{ map = (d0, d1) -> (d0 : compressed, d1 : compressed) }> + // CHECK-LABEL: func.func @conv2d_all_sparse_CSR( // CHECK-SAME: %[[VAL_0:.*]]: tensor<8x8xi32, #sparse{{[0-9]*}}>, -// CHECK-SAME: %[[VAL_1:.*]]: tensor<3x3xi32>) -> tensor<6x6xi32, #sparse{{[0-9]*}}> { +// CHECK-SAME: %[[VAL_1:.*]]: tensor<3x3xi32>) -> tensor<6x6xi32, #sparse{{[0-9]*}}> // CHECK-DAG: %[[VAL_2:.*]] = arith.constant true // CHECK-DAG: %[[VAL_3:.*]] = arith.constant -2 : index -// CHECK-DAG: %[[VAL_4:.*]] = arith.constant 8 : index -// CHECK-DAG: %[[VAL_5:.*]] = arith.constant 3 : index -// CHECK-DAG: %[[VAL_6:.*]] = arith.constant 0 : index +// CHECK-DAG: %[[VAL_4:.*]] = arith.constant 4 : index +// CHECK-DAG: %[[VAL_5:.*]] = arith.constant 8 : index +// CHECK-DAG: %[[VAL_6:.*]] = arith.constant 3 : index // CHECK-DAG: %[[VAL_7:.*]] = arith.constant 1 : index -// CHECK-DAG: %[[VAL_8:.*]] = arith.constant 2 : index -// CHECK-DAG: %[[VAL_9:.*]] = arith.constant 4 : index -// CHECK-DAG: %[[VAL_10:.*]] = arith.constant 0 : i32 -// CHECK-DAG: %[[VAL_11:.*]] = arith.constant false -// CHECK-DAG: %[[VAL_12:.*]] = tensor.empty() : tensor<6x6xi32, #sparse{{[0-9]*}}> -// CHECK-DAG: %[[VAL_13:.*]] = sparse_tensor.positions %[[VAL_0]] {level = 0 : index} : tensor<8x8xi32, #sparse{{[0-9]*}}> to memref -// CHECK-DAG: %[[VAL_14:.*]] = sparse_tensor.coordinates %[[VAL_0]] {level = 0 : index} : tensor<8x8xi32, #sparse{{[0-9]*}}> to memref -// CHECK-DAG: %[[VAL_15:.*]] = sparse_tensor.positions %[[VAL_0]] {level = 1 : index} : tensor<8x8xi32, #sparse{{[0-9]*}}> to memref -// CHECK-DAG: %[[VAL_16:.*]] = sparse_tensor.coordinates %[[VAL_0]] {level = 1 : index} : tensor<8x8xi32, #sparse{{[0-9]*}}> to memref -// CHECK-DAG: %[[VAL_17:.*]] = sparse_tensor.values %[[VAL_0]] : tensor<8x8xi32, #sparse{{[0-9]*}}> to memref -// CHECK-DAG: %[[VAL_18:.*]] = memref.alloca() : memref<11xindex> -// CHECK-DAG: %[[VAL_19:.*]] = memref.alloca() : memref<5xindex> -// CHECK-DAG: %[[VAL_20:.*]] = memref.load %[[VAL_13]]{{\[}}%[[VAL_7]]] : memref -// CHECK: memref.store %[[VAL_9]], %[[VAL_19]]{{\[}}%[[VAL_6]]] : memref<5xindex> -// CHECK: memref.store %[[VAL_6]], %[[VAL_19]]{{\[}}%[[VAL_7]]] : memref<5xindex> -// CHECK: memref.store %[[VAL_6]], %[[VAL_19]]{{\[}}%[[VAL_8]]] : memref<5xindex> -// CHECK: memref.store %[[VAL_20]], %[[VAL_19]]{{\[}}%[[VAL_5]]] : memref<5xindex> -// CHECK: %[[VAL_21:.*]] = arith.cmpi ugt, %[[VAL_20]], %[[VAL_6]] : index -// CHECK: %[[VAL_22:.*]] = memref.load %[[VAL_14]]{{\[}}%[[VAL_6]]] : memref -// CHECK: %[[VAL_23:.*]] = arith.cmpi uge, %[[VAL_22]], %[[VAL_5]] : index -// CHECK: %[[VAL_24:.*]] = arith.andi %[[VAL_21]], %[[VAL_23]] : i1 -// CHECK: %[[VAL_25:.*]] = arith.addi %[[VAL_22]], %[[VAL_3]] : index -// CHECK: %[[VAL_26:.*]] = arith.select %[[VAL_24]], %[[VAL_25]], %[[VAL_6]] : index -// CHECK: %[[VAL_27:.*]]:3 = scf.while (%[[VAL_28:.*]] = %[[VAL_21]], %[[VAL_29:.*]] = %[[VAL_22]], %[[VAL_30:.*]] = %[[VAL_26]], %[[VAL_31:.*]] = %[[VAL_12]]) : (i1, index, index, tensor<6x6xi32, #sparse{{[0-9]*}}>) -> (index, index, tensor<6x6xi32, #sparse{{[0-9]*}}>) { -// CHECK: scf.condition(%[[VAL_28]]) %[[VAL_29]], %[[VAL_30]], %[[VAL_31]] : index, index, tensor<6x6xi32, #sparse{{[0-9]*}}> +// CHECK-DAG: %[[VAL_8:.*]] = arith.constant 5 : index +// CHECK-DAG: %[[VAL_9:.*]] = arith.constant 2 : index +// CHECK-DAG: %[[VAL_10:.*]] = arith.constant 0 : index +// CHECK-DAG: %[[VAL_11:.*]] = arith.constant 0 : i32 +// CHECK-DAG: %[[VAL_12:.*]] = arith.constant false +// CHECK-DAG: %[[VAL_13:.*]] = tensor.empty() : tensor<6x6xi32, #sparse{{[0-9]*}}> +// CHECK-DAG: %[[VAL_14:.*]] = sparse_tensor.positions %[[VAL_0]] {level = 0 : index} : tensor<8x8xi32, #sparse{{[0-9]*}}> to memref +// CHECK-DAG: %[[VAL_15:.*]] = sparse_tensor.coordinates %[[VAL_0]] {level = 0 : index} : tensor<8x8xi32, #sparse{{[0-9]*}}> to memref +// CHECK-DAG: %[[VAL_16:.*]] = sparse_tensor.positions %[[VAL_0]] {level = 1 : index} : tensor<8x8xi32, #sparse{{[0-9]*}}> to memref +// CHECK-DAG: %[[VAL_17:.*]] = sparse_tensor.coordinates %[[VAL_0]] {level = 1 : index} : tensor<8x8xi32, #sparse{{[0-9]*}}> to memref +// CHECK-DAG: %[[VAL_18:.*]] = sparse_tensor.values %[[VAL_0]] : tensor<8x8xi32, #sparse{{[0-9]*}}> to memref +// CHECK-DAG: %[[VAL_19:.*]] = memref.alloca() : memref<11xindex> +// CHECK-DAG: %[[VAL_20:.*]] = memref.alloca() : memref<5xindex> +// CHECK-DAG: %[[VAL_21:.*]] = memref.load %[[VAL_14]]{{\[}}%[[VAL_7]]] : memref +// CHECK-DAG: memref.store %[[VAL_7]], %[[VAL_20]]{{\[}}%[[VAL_10]]] : memref<5xindex> +// CHECK-DAG: memref.store %[[VAL_10]], %[[VAL_20]]{{\[}}%[[VAL_7]]] : memref<5xindex> +// CHECK-DAG: memref.store %[[VAL_10]], %[[VAL_20]]{{\[}}%[[VAL_9]]] : memref<5xindex> +// CHECK-DAG: memref.store %[[VAL_21]], %[[VAL_20]]{{\[}}%[[VAL_6]]] : memref<5xindex> +// CHECK: %[[VAL_22:.*]] = arith.cmpi ugt, %[[VAL_21]], %[[VAL_10]] : index +// CHECK: %[[VAL_23:.*]] = memref.load %[[VAL_15]]{{\[}}%[[VAL_10]]] : memref +// CHECK: %[[VAL_24:.*]] = arith.cmpi uge, %[[VAL_23]], %[[VAL_6]] : index +// CHECK: %[[VAL_25:.*]] = arith.andi %[[VAL_22]], %[[VAL_24]] : i1 +// CHECK: %[[VAL_26:.*]] = arith.addi %[[VAL_23]], %[[VAL_3]] : index +// CHECK: %[[VAL_27:.*]] = arith.select %[[VAL_25]], %[[VAL_26]], %[[VAL_10]] : index +// CHECK: %[[VAL_28:.*]]:3 = scf.while (%[[VAL_29:.*]] = %[[VAL_22]], %[[VAL_30:.*]] = %[[VAL_23]], %[[VAL_31:.*]] = %[[VAL_27]], %[[VAL_32:.*]] = %[[VAL_13]]) : (i1, index, index, tensor<6x6xi32, #sparse{{[0-9]*}}>) -> (index, index, tensor<6x6xi32, #sparse{{[0-9]*}}>) { +// CHECK: scf.condition(%[[VAL_29]]) %[[VAL_30]], %[[VAL_31]], %[[VAL_32]] : index, index, tensor<6x6xi32, #sparse{{[0-9]*}}> // CHECK: } do { -// CHECK: ^bb0(%[[VAL_32:.*]]: index, %[[VAL_33:.*]]: index, %[[VAL_34:.*]]: tensor<6x6xi32, #sparse{{[0-9]*}}>): -// CHECK: %[[VAL_35:.*]] = memref.load %[[VAL_19]]{{\[}}%[[VAL_6]]] : memref<5xindex> -// CHECK: %[[VAL_36:.*]]:4 = scf.for %[[VAL_37:.*]] = %[[VAL_8]] to %[[VAL_35]] step %[[VAL_5]] iter_args(%[[VAL_38:.*]] = %[[VAL_11]], %[[VAL_39:.*]] = %[[VAL_4]], %[[VAL_40:.*]] = %[[VAL_8]], %[[VAL_41:.*]] = %[[VAL_6]]) -> (i1, index, index, index) { -// CHECK: %[[VAL_42:.*]] = memref.load %[[VAL_19]]{{\[}}%[[VAL_37]]] : memref<5xindex> -// CHECK: %[[VAL_43:.*]] = arith.addi %[[VAL_37]], %[[VAL_7]] : index -// CHECK: %[[VAL_44:.*]] = memref.load %[[VAL_19]]{{\[}}%[[VAL_43]]] : memref<5xindex> -// CHECK: %[[VAL_45:.*]] = arith.addi %[[VAL_37]], %[[VAL_8]] : index -// CHECK: memref.store %[[VAL_41]], %[[VAL_19]]{{\[}}%[[VAL_45]]] : memref<5xindex> -// CHECK: %[[VAL_46:.*]] = arith.addi %[[VAL_33]], %[[VAL_5]] : index -// CHECK: %[[VAL_47:.*]]:5 = scf.while (%[[VAL_48:.*]] = %[[VAL_42]], %[[VAL_49:.*]] = %[[VAL_38]], %[[VAL_50:.*]] = %[[VAL_39]], %[[VAL_51:.*]] = %[[VAL_40]], %[[VAL_52:.*]] = %[[VAL_41]]) : (index, i1, index, index, index) -> (index, i1, index, index, index) { -// CHECK: %[[VAL_53:.*]] = arith.cmpi ult, %[[VAL_48]], %[[VAL_44]] : index -// CHECK: %[[VAL_54:.*]] = scf.if %[[VAL_53]] -> (i1) { -// CHECK: %[[VAL_55:.*]] = memref.load %[[VAL_14]]{{\[}}%[[VAL_48]]] : memref -// CHECK: %[[VAL_56:.*]] = arith.cmpi ult, %[[VAL_55]], %[[VAL_46]] : index -// CHECK: scf.yield %[[VAL_56]] : i1 +// CHECK: ^bb0(%[[VAL_33:.*]]: index, %[[VAL_34:.*]]: index, %[[VAL_35:.*]]: tensor<6x6xi32, #sparse{{[0-9]*}}>): +// CHECK: %[[VAL_36:.*]] = memref.load %[[VAL_20]]{{\[}}%[[VAL_10]]] : memref<5xindex> +// CHECK: %[[VAL_37:.*]]:4 = scf.for %[[VAL_38:.*]] = %[[VAL_10]] to %[[VAL_36]] step %[[VAL_7]] iter_args(%[[VAL_39:.*]] = %[[VAL_12]], %[[VAL_40:.*]] = %[[VAL_5]], %[[VAL_41:.*]] = %[[VAL_10]], %[[VAL_42:.*]] = %[[VAL_10]]) -> (i1, index, index, index) { +// CHECK: %[[VAL_43:.*]] = arith.addi %[[VAL_38]], %[[VAL_9]] : index +// CHECK: %[[VAL_44:.*]] = memref.load %[[VAL_20]]{{\[}}%[[VAL_43]]] : memref<5xindex> +// CHECK: %[[VAL_45:.*]] = arith.addi %[[VAL_38]], %[[VAL_6]] : index +// CHECK: %[[VAL_46:.*]] = memref.load %[[VAL_20]]{{\[}}%[[VAL_45]]] : memref<5xindex> +// CHECK: %[[VAL_47:.*]] = arith.addi %[[VAL_38]], %[[VAL_4]] : index +// CHECK: memref.store %[[VAL_42]], %[[VAL_20]]{{\[}}%[[VAL_47]]] : memref<5xindex> +// CHECK: %[[VAL_48:.*]] = arith.addi %[[VAL_34]], %[[VAL_6]] : index +// CHECK: %[[VAL_49:.*]]:5 = scf.while (%[[VAL_50:.*]] = %[[VAL_44]], %[[VAL_51:.*]] = %[[VAL_39]], %[[VAL_52:.*]] = %[[VAL_40]], %[[VAL_53:.*]] = %[[VAL_41]], %[[VAL_54:.*]] = %[[VAL_42]]) : (index, i1, index, index, index) -> (index, i1, index, index, index) { +// CHECK: %[[VAL_55:.*]] = arith.cmpi ult, %[[VAL_50]], %[[VAL_46]] : index +// CHECK: %[[VAL_56:.*]] = scf.if %[[VAL_55]] -> (i1) { +// CHECK: %[[VAL_57:.*]] = memref.load %[[VAL_15]]{{\[}}%[[VAL_50]]] : memref +// CHECK: %[[VAL_58:.*]] = arith.cmpi ult, %[[VAL_57]], %[[VAL_48]] : index +// CHECK: scf.yield %[[VAL_58]] : i1 // CHECK: } else { -// CHECK: scf.yield %[[VAL_11]] : i1 +// CHECK: scf.yield %[[VAL_12]] : i1 // CHECK: } -// CHECK: scf.condition(%[[VAL_57:.*]]) %[[VAL_48]], %[[VAL_49]], %[[VAL_50]], %[[VAL_51]], %[[VAL_52]] : index, i1, index, index, index +// CHECK: scf.condition(%[[VAL_56]]) %[[VAL_50]], %[[VAL_51]], %[[VAL_52]], %[[VAL_53]], %[[VAL_54]] : index, i1, index, index, index // CHECK: } do { -// CHECK: ^bb0(%[[VAL_58:.*]]: index, %[[VAL_59:.*]]: i1, %[[VAL_60:.*]]: index, %[[VAL_61:.*]]: index, %[[VAL_62:.*]]: index): -// CHECK: %[[VAL_63:.*]] = arith.addi %[[VAL_58]], %[[VAL_7]] : index -// CHECK: %[[VAL_64:.*]] = memref.load %[[VAL_15]]{{\[}}%[[VAL_58]]] : memref -// CHECK: %[[VAL_65:.*]] = memref.load %[[VAL_15]]{{\[}}%[[VAL_63]]] : memref -// CHECK: %[[VAL_66:.*]] = arith.cmpi ult, %[[VAL_64]], %[[VAL_65]] : index -// CHECK: %[[VAL_67:.*]] = arith.ori %[[VAL_66]], %[[VAL_59]] : i1 -// CHECK: %[[VAL_68:.*]] = scf.if %[[VAL_66]] -> (index) { -// CHECK: %[[VAL_69:.*]] = memref.load %[[VAL_16]]{{\[}}%[[VAL_64]]] : memref -// CHECK: %[[VAL_70:.*]] = arith.cmpi ult, %[[VAL_69]], %[[VAL_60]] : index -// CHECK: %[[VAL_71:.*]] = arith.select %[[VAL_70]], %[[VAL_69]], %[[VAL_60]] : index -// CHECK: scf.yield %[[VAL_71]] : index +// CHECK: ^bb0(%[[VAL_59:.*]]: index, %[[VAL_60:.*]]: i1, %[[VAL_61:.*]]: index, %[[VAL_62:.*]]: index, %[[VAL_63:.*]]: index): +// CHECK: %[[VAL_64:.*]] = arith.addi %[[VAL_59]], %[[VAL_7]] : index +// CHECK: %[[VAL_65:.*]] = memref.load %[[VAL_16]]{{\[}}%[[VAL_59]]] : memref +// CHECK: %[[VAL_66:.*]] = memref.load %[[VAL_16]]{{\[}}%[[VAL_64]]] : memref +// CHECK: %[[VAL_67:.*]] = arith.cmpi ult, %[[VAL_65]], %[[VAL_66]] : index +// CHECK: %[[VAL_68:.*]] = arith.ori %[[VAL_67]], %[[VAL_60]] : i1 +// CHECK: %[[VAL_69:.*]] = scf.if %[[VAL_67]] -> (index) { +// CHECK: %[[VAL_70:.*]] = memref.load %[[VAL_17]]{{\[}}%[[VAL_65]]] : memref +// CHECK: %[[VAL_71:.*]] = arith.cmpi ult, %[[VAL_70]], %[[VAL_61]] : index +// CHECK: %[[VAL_72:.*]] = arith.select %[[VAL_71]], %[[VAL_70]], %[[VAL_61]] : index +// CHECK: scf.yield %[[VAL_72]] : index // CHECK: } else { -// CHECK: scf.yield %[[VAL_60]] : index +// CHECK: scf.yield %[[VAL_61]] : index // CHECK: } -// CHECK: memref.store %[[VAL_64]], %[[VAL_18]]{{\[}}%[[VAL_61]]] : memref<11xindex> -// CHECK: %[[VAL_72:.*]] = arith.addi %[[VAL_61]], %[[VAL_7]] : index -// CHECK: memref.store %[[VAL_65]], %[[VAL_18]]{{\[}}%[[VAL_72]]] : memref<11xindex> -// CHECK: %[[VAL_73:.*]] = arith.addi %[[VAL_61]], %[[VAL_5]] : index -// CHECK: %[[VAL_74:.*]] = arith.addi %[[VAL_62]], %[[VAL_7]] : index -// CHECK: scf.yield %[[VAL_63]], %[[VAL_67]], %[[VAL_75:.*]], %[[VAL_73]], %[[VAL_74]] : index, i1, index, index, index +// CHECK: %[[VAL_73:.*]] = arith.addi %[[VAL_62]], %[[VAL_9]] : index +// CHECK: memref.store %[[VAL_65]], %[[VAL_19]]{{\[}}%[[VAL_73]]] : memref<11xindex> +// CHECK: %[[VAL_74:.*]] = arith.addi %[[VAL_62]], %[[VAL_8]] : index +// CHECK: memref.store %[[VAL_66]], %[[VAL_19]]{{\[}}%[[VAL_74]]] : memref<11xindex> +// CHECK: %[[VAL_75:.*]] = arith.addi %[[VAL_62]], %[[VAL_7]] : index +// CHECK: %[[VAL_76:.*]] = arith.addi %[[VAL_63]], %[[VAL_7]] : index +// CHECK: scf.yield %[[VAL_64]], %[[VAL_68]], %[[VAL_69]], %[[VAL_75]], %[[VAL_76]] : index, i1, index, index, index // CHECK: } -// CHECK: scf.yield %[[VAL_76:.*]]#1, %[[VAL_76]]#2, %[[VAL_76]]#3, %[[VAL_76]]#4 : i1, index, index, index +// CHECK: scf.yield %[[VAL_77:.*]]#1, %[[VAL_77]]#2, %[[VAL_77]]#3, %[[VAL_77]]#4 : i1, index, index, index // CHECK: } -// CHECK: memref.store %[[VAL_77:.*]]#2, %[[VAL_18]]{{\[}}%[[VAL_6]]] : memref<11xindex> -// CHECK: memref.store %[[VAL_6]], %[[VAL_18]]{{\[}}%[[VAL_7]]] : memref<11xindex> -// CHECK: %[[VAL_78:.*]] = arith.cmpi uge, %[[VAL_77]]#1, %[[VAL_5]] : index -// CHECK: %[[VAL_79:.*]] = arith.andi %[[VAL_77]]#0, %[[VAL_78]] : i1 -// CHECK: %[[VAL_80:.*]] = arith.addi %[[VAL_77]]#1, %[[VAL_3]] : index -// CHECK: %[[VAL_81:.*]] = arith.select %[[VAL_79]], %[[VAL_80]], %[[VAL_6]] : index -// CHECK: %[[VAL_82:.*]]:3 = scf.while (%[[VAL_83:.*]] = %[[VAL_77]]#0, %[[VAL_84:.*]] = %[[VAL_77]]#1, %[[VAL_85:.*]] = %[[VAL_81]], %[[VAL_86:.*]] = %[[VAL_34]]) : (i1, index, index, tensor<6x6xi32, #sparse{{[0-9]*}}>) -> (index, index, tensor<6x6xi32, #sparse{{[0-9]*}}>) { -// CHECK: scf.condition(%[[VAL_83]]) %[[VAL_84]], %[[VAL_85]], %[[VAL_86]] : index, index, tensor<6x6xi32, #sparse{{[0-9]*}}> +// CHECK: memref.store %[[VAL_78:.*]]#2, %[[VAL_19]]{{\[}}%[[VAL_10]]] : memref<11xindex> +// CHECK: memref.store %[[VAL_10]], %[[VAL_19]]{{\[}}%[[VAL_7]]] : memref<11xindex> +// CHECK: %[[VAL_79:.*]] = arith.cmpi uge, %[[VAL_78]]#1, %[[VAL_6]] : index +// CHECK: %[[VAL_80:.*]] = arith.andi %[[VAL_78]]#0, %[[VAL_79]] : i1 +// CHECK: %[[VAL_81:.*]] = arith.addi %[[VAL_78]]#1, %[[VAL_3]] : index +// CHECK: %[[VAL_82:.*]] = arith.select %[[VAL_80]], %[[VAL_81]], %[[VAL_10]] : index +// CHECK: %[[VAL_83:.*]]:3 = scf.while (%[[VAL_84:.*]] = %[[VAL_78]]#0, %[[VAL_85:.*]] = %[[VAL_78]]#1, %[[VAL_86:.*]] = %[[VAL_82]], %[[VAL_87:.*]] = %[[VAL_35]]) : (i1, index, index, tensor<6x6xi32, #sparse{{[0-9]*}}>) -> (index, index, tensor<6x6xi32, #sparse{{[0-9]*}}>) { +// CHECK: scf.condition(%[[VAL_84]]) %[[VAL_85]], %[[VAL_86]], %[[VAL_87]] : index, index, tensor<6x6xi32, #sparse{{[0-9]*}}> // CHECK: } do { -// CHECK: ^bb0(%[[VAL_87:.*]]: index, %[[VAL_88:.*]]: index, %[[VAL_89:.*]]: tensor<6x6xi32, #sparse{{[0-9]*}}>): -// CHECK: %[[VAL_90:.*]] = memref.load %[[VAL_19]]{{\[}}%[[VAL_7]]] : memref<5xindex> -// CHECK: %[[VAL_91:.*]] = arith.addi %[[VAL_90]], %[[VAL_8]] : index -// CHECK: %[[VAL_92:.*]] = arith.addi %[[VAL_90]], %[[VAL_5]] : index -// CHECK: %[[VAL_93:.*]] = memref.load %[[VAL_19]]{{\[}}%[[VAL_91]]] : memref<5xindex> -// CHECK: %[[VAL_94:.*]] = memref.load %[[VAL_19]]{{\[}}%[[VAL_92]]] : memref<5xindex> -// CHECK: %[[VAL_95:.*]] = arith.addi %[[VAL_33]], %[[VAL_5]] : index -// CHECK: %[[VAL_96:.*]]:3 = scf.while (%[[VAL_97:.*]] = %[[VAL_93]], %[[VAL_98:.*]] = %[[VAL_10]], %[[VAL_99:.*]] = %[[VAL_11]]) : (index, i32, i1) -> (index, i32, i1) { -// CHECK: %[[VAL_100:.*]] = arith.cmpi ult, %[[VAL_97]], %[[VAL_94]] : index -// CHECK: %[[VAL_101:.*]] = scf.if %[[VAL_100]] -> (i1) { -// CHECK: %[[VAL_102:.*]] = memref.load %[[VAL_14]]{{\[}}%[[VAL_97]]] : memref -// CHECK: %[[VAL_103:.*]] = arith.cmpi ult, %[[VAL_102]], %[[VAL_95]] : index -// CHECK: scf.yield %[[VAL_103]] : i1 +// CHECK: ^bb0(%[[VAL_88:.*]]: index, %[[VAL_89:.*]]: index, %[[VAL_90:.*]]: tensor<6x6xi32, #sparse{{[0-9]*}}>): +// CHECK: %[[VAL_91:.*]] = memref.load %[[VAL_20]]{{\[}}%[[VAL_7]]] : memref<5xindex> +// CHECK: %[[VAL_92:.*]] = arith.addi %[[VAL_91]], %[[VAL_9]] : index +// CHECK: %[[VAL_93:.*]] = memref.load %[[VAL_20]]{{\[}}%[[VAL_92]]] : memref<5xindex> +// CHECK: %[[VAL_94:.*]] = arith.addi %[[VAL_91]], %[[VAL_6]] : index +// CHECK: %[[VAL_95:.*]] = memref.load %[[VAL_20]]{{\[}}%[[VAL_94]]] : memref<5xindex> +// CHECK: %[[VAL_96:.*]] = arith.addi %[[VAL_34]], %[[VAL_6]] : index +// CHECK: %[[VAL_97:.*]]:3 = scf.while (%[[VAL_98:.*]] = %[[VAL_93]], %[[VAL_99:.*]] = %[[VAL_11]], %[[VAL_100:.*]] = %[[VAL_12]]) : (index, i32, i1) -> (index, i32, i1) { +// CHECK: %[[VAL_101:.*]] = arith.cmpi ult, %[[VAL_98]], %[[VAL_95]] : index +// CHECK: %[[VAL_102:.*]] = scf.if %[[VAL_101]] -> (i1) { +// CHECK: %[[VAL_103:.*]] = memref.load %[[VAL_15]]{{\[}}%[[VAL_98]]] : memref +// CHECK: %[[VAL_104:.*]] = arith.cmpi ult, %[[VAL_103]], %[[VAL_96]] : index +// CHECK: scf.yield %[[VAL_104]] : i1 // CHECK: } else { -// CHECK: scf.yield %[[VAL_11]] : i1 +// CHECK: scf.yield %[[VAL_12]] : i1 // CHECK: } -// CHECK: scf.condition(%[[VAL_104:.*]]) %[[VAL_97]], %[[VAL_98]], %[[VAL_99]] : index, i32, i1 +// CHECK: scf.condition(%[[VAL_102]]) %[[VAL_98]], %[[VAL_99]], %[[VAL_100]] : index, i32, i1 // CHECK: } do { // CHECK: ^bb0(%[[VAL_105:.*]]: index, %[[VAL_106:.*]]: i32, %[[VAL_107:.*]]: i1): -// CHECK: %[[VAL_108:.*]] = memref.load %[[VAL_14]]{{\[}}%[[VAL_105]]] : memref -// CHECK: %[[VAL_109:.*]] = arith.subi %[[VAL_108]], %[[VAL_33]] : index -// CHECK: %[[VAL_110:.*]] = memref.load %[[VAL_18]]{{\[}}%[[VAL_7]]] : memref<11xindex> -// CHECK: %[[VAL_111:.*]] = arith.addi %[[VAL_110]], %[[VAL_8]] : index -// CHECK: %[[VAL_112:.*]] = arith.addi %[[VAL_110]], %[[VAL_5]] : index -// CHECK: %[[VAL_113:.*]] = memref.load %[[VAL_18]]{{\[}}%[[VAL_111]]] : memref<11xindex> -// CHECK: %[[VAL_114:.*]] = memref.load %[[VAL_18]]{{\[}}%[[VAL_112]]] : memref<11xindex> -// CHECK: %[[VAL_115:.*]] = arith.addi %[[VAL_88]], %[[VAL_5]] : index -// CHECK: %[[VAL_116:.*]]:2 = scf.while (%[[VAL_117:.*]] = %[[VAL_113]], %[[VAL_118:.*]] = %[[VAL_106]]) : (index, i32) -> (index, i32) { +// CHECK: %[[VAL_108:.*]] = memref.load %[[VAL_15]]{{\[}}%[[VAL_105]]] : memref +// CHECK: %[[VAL_109:.*]] = arith.subi %[[VAL_108]], %[[VAL_34]] : index +// CHECK: %[[VAL_110:.*]] = memref.load %[[VAL_19]]{{\[}}%[[VAL_7]]] : memref<11xindex> +// CHECK: %[[VAL_111:.*]] = arith.addi %[[VAL_110]], %[[VAL_9]] : index +// CHECK: %[[VAL_112:.*]] = memref.load %[[VAL_19]]{{\[}}%[[VAL_111]]] : memref<11xindex> +// CHECK: %[[VAL_113:.*]] = arith.addi %[[VAL_110]], %[[VAL_8]] : index +// CHECK: %[[VAL_114:.*]] = memref.load %[[VAL_19]]{{\[}}%[[VAL_113]]] : memref<11xindex> +// CHECK: %[[VAL_115:.*]] = arith.addi %[[VAL_89]], %[[VAL_6]] : index +// CHECK: %[[VAL_116:.*]]:2 = scf.while (%[[VAL_117:.*]] = %[[VAL_112]], %[[VAL_118:.*]] = %[[VAL_106]]) : (index, i32) -> (index, i32) { // CHECK: %[[VAL_119:.*]] = arith.cmpi ult, %[[VAL_117]], %[[VAL_114]] : index // CHECK: %[[VAL_120:.*]] = scf.if %[[VAL_119]] -> (i1) { -// CHECK: %[[VAL_121:.*]] = memref.load %[[VAL_16]]{{\[}}%[[VAL_117]]] : memref +// CHECK: %[[VAL_121:.*]] = memref.load %[[VAL_17]]{{\[}}%[[VAL_117]]] : memref // CHECK: %[[VAL_122:.*]] = arith.cmpi ult, %[[VAL_121]], %[[VAL_115]] : index // CHECK: scf.yield %[[VAL_122]] : i1 // CHECK: } else { -// CHECK: scf.yield %[[VAL_11]] : i1 +// CHECK: scf.yield %[[VAL_12]] : i1 // CHECK: } -// CHECK: scf.condition(%[[VAL_123:.*]]) %[[VAL_117]], %[[VAL_118]] : index, i32 +// CHECK: scf.condition(%[[VAL_120]]) %[[VAL_117]], %[[VAL_118]] : index, i32 // CHECK: } do { -// CHECK: ^bb0(%[[VAL_124:.*]]: index, %[[VAL_125:.*]]: i32): -// CHECK: %[[VAL_126:.*]] = memref.load %[[VAL_16]]{{\[}}%[[VAL_124]]] : memref -// CHECK: %[[VAL_127:.*]] = arith.subi %[[VAL_126]], %[[VAL_88]] : index -// CHECK: %[[VAL_128:.*]] = memref.load %[[VAL_17]]{{\[}}%[[VAL_124]]] : memref -// CHECK: %[[VAL_129:.*]] = tensor.extract %[[VAL_1]]{{\[}}%[[VAL_109]], %[[VAL_127]]] : tensor<3x3xi32> -// CHECK: %[[VAL_130:.*]] = arith.muli %[[VAL_128]], %[[VAL_129]] : i32 -// CHECK: %[[VAL_131:.*]] = arith.addi %[[VAL_125]], %[[VAL_130]] : i32 -// CHECK: %[[VAL_132:.*]] = arith.addi %[[VAL_124]], %[[VAL_7]] : index -// CHECK: scf.yield %[[VAL_132]], %[[VAL_131]] : index, i32 +// CHECK: ^bb0(%[[VAL_123:.*]]: index, %[[VAL_124:.*]]: i32): +// CHECK: %[[VAL_125:.*]] = memref.load %[[VAL_17]]{{\[}}%[[VAL_123]]] : memref +// CHECK: %[[VAL_126:.*]] = arith.subi %[[VAL_125]], %[[VAL_89]] : index +// CHECK: %[[VAL_127:.*]] = memref.load %[[VAL_18]]{{\[}}%[[VAL_123]]] : memref +// CHECK: %[[VAL_128:.*]] = tensor.extract %[[VAL_1]]{{\[}}%[[VAL_109]], %[[VAL_126]]] : tensor<3x3xi32> +// CHECK: %[[VAL_129:.*]] = arith.muli %[[VAL_127]], %[[VAL_128]] : i32 +// CHECK: %[[VAL_130:.*]] = arith.addi %[[VAL_124]], %[[VAL_129]] : i32 +// CHECK: %[[VAL_131:.*]] = arith.addi %[[VAL_123]], %[[VAL_7]] : index +// CHECK: scf.yield %[[VAL_131]], %[[VAL_130]] : index, i32 // CHECK: } -// CHECK: %[[VAL_133:.*]] = arith.addi %[[VAL_105]], %[[VAL_7]] : index -// CHECK: memref.store %[[VAL_112]], %[[VAL_18]]{{\[}}%[[VAL_7]]] : memref<11xindex> -// CHECK: scf.yield %[[VAL_133]], %[[VAL_136:.*]]#1, %[[VAL_2]] : index, i32, i1 +// CHECK: %[[VAL_132:.*]] = arith.addi %[[VAL_105]], %[[VAL_7]] : index +// CHECK: %[[VAL_133:.*]] = arith.addi %[[VAL_110]], %[[VAL_7]] : index +// CHECK: memref.store %[[VAL_133]], %[[VAL_19]]{{\[}}%[[VAL_7]]] : memref<11xindex> +// CHECK: scf.yield %[[VAL_132]], %[[VAL_134:.*]]#1, %[[VAL_2]] : index, i32, i1 // CHECK: } -// CHECK: %[[VAL_137:.*]] = scf.if %[[VAL_138:.*]]#2 -> (tensor<6x6xi32, #sparse{{[0-9]*}}>) { -// CHECK: %[[VAL_139:.*]] = sparse_tensor.insert %[[VAL_138]]#1 into %[[VAL_89]]{{\[}}%[[VAL_33]], %[[VAL_88]]] : tensor<6x6xi32, #sparse{{[0-9]*}}> -// CHECK: scf.yield %[[VAL_139]] : tensor<6x6xi32, #sparse{{[0-9]*}}> +// CHECK: %[[VAL_135:.*]] = scf.if %[[VAL_136:.*]]#2 -> (tensor<6x6xi32, #sparse{{[0-9]*}}>) { +// CHECK: %[[VAL_137:.*]] = sparse_tensor.insert %[[VAL_136]]#1 into %[[VAL_90]]{{\[}}%[[VAL_34]], %[[VAL_89]]] : tensor<6x6xi32, #sparse{{[0-9]*}}> +// CHECK: scf.yield %[[VAL_137]] : tensor<6x6xi32, #sparse{{[0-9]*}}> // CHECK: } else { -// CHECK: scf.yield %[[VAL_89]] : tensor<6x6xi32, #sparse{{[0-9]*}}> +// CHECK: scf.yield %[[VAL_90]] : tensor<6x6xi32, #sparse{{[0-9]*}}> // CHECK: } -// CHECK: memref.store %[[VAL_6]], %[[VAL_19]]{{\[}}%[[VAL_7]]] : memref<5xindex> -// CHECK: memref.store %[[VAL_6]], %[[VAL_18]]{{\[}}%[[VAL_7]]] : memref<11xindex> -// CHECK: %[[VAL_140:.*]] = arith.cmpi ugt, %[[VAL_87]], %[[VAL_88]] : index -// CHECK: %[[VAL_141:.*]]:3 = scf.if %[[VAL_140]] -> (index, i1, index) { -// CHECK: %[[VAL_142:.*]] = arith.addi %[[VAL_88]], %[[VAL_7]] : index -// CHECK: scf.yield %[[VAL_87]], %[[VAL_2]], %[[VAL_142]] : index, i1, index +// CHECK: memref.store %[[VAL_10]], %[[VAL_20]]{{\[}}%[[VAL_7]]] : memref<5xindex> +// CHECK: memref.store %[[VAL_10]], %[[VAL_19]]{{\[}}%[[VAL_7]]] : memref<11xindex> +// CHECK: %[[VAL_138:.*]] = arith.cmpi ugt, %[[VAL_88]], %[[VAL_89]] : index +// CHECK: %[[VAL_139:.*]]:3 = scf.if %[[VAL_138]] -> (index, i1, index) { +// CHECK: %[[VAL_140:.*]] = arith.addi %[[VAL_89]], %[[VAL_7]] : index +// CHECK: scf.yield %[[VAL_88]], %[[VAL_2]], %[[VAL_140]] : index, i1, index // CHECK: } else { -// CHECK: %[[VAL_143:.*]] = memref.load %[[VAL_18]]{{\[}}%[[VAL_6]]] : memref<11xindex> -// CHECK: %[[VAL_144:.*]]:2 = scf.for %[[VAL_145:.*]] = %[[VAL_8]] to %[[VAL_143]] step %[[VAL_5]] iter_args(%[[VAL_146:.*]] = %[[VAL_4]], %[[VAL_147:.*]] = %[[VAL_11]]) -> (index, i1) { -// CHECK: %[[VAL_148:.*]] = memref.load %[[VAL_18]]{{\[}}%[[VAL_145]]] : memref<11xindex> -// CHECK: %[[VAL_149:.*]] = arith.addi %[[VAL_145]], %[[VAL_7]] : index -// CHECK: %[[VAL_150:.*]] = memref.load %[[VAL_18]]{{\[}}%[[VAL_149]]] : memref<11xindex> -// CHECK: %[[VAL_151:.*]] = arith.cmpi ult, %[[VAL_148]], %[[VAL_150]] : index -// CHECK: %[[VAL_152:.*]] = scf.if %[[VAL_151]] -> (index) { -// CHECK: %[[VAL_153:.*]] = memref.load %[[VAL_16]]{{\[}}%[[VAL_148]]] : memref -// CHECK: %[[VAL_154:.*]] = arith.cmpi eq, %[[VAL_153]], %[[VAL_87]] : index -// CHECK: %[[VAL_155:.*]] = scf.if %[[VAL_154]] -> (index) { -// CHECK: %[[VAL_156:.*]] = arith.addi %[[VAL_148]], %[[VAL_7]] : index -// CHECK: memref.store %[[VAL_156]], %[[VAL_18]]{{\[}}%[[VAL_145]]] : memref<11xindex> -// CHECK: scf.yield %[[VAL_156]] : index +// CHECK: %[[VAL_141:.*]] = memref.load %[[VAL_19]]{{\[}}%[[VAL_10]]] : memref<11xindex> +// CHECK: %[[VAL_142:.*]]:2 = scf.for %[[VAL_143:.*]] = %[[VAL_10]] to %[[VAL_141]] step %[[VAL_7]] iter_args(%[[VAL_144:.*]] = %[[VAL_5]], %[[VAL_145:.*]] = %[[VAL_12]]) -> (index, i1) { +// CHECK: %[[VAL_146:.*]] = arith.addi %[[VAL_143]], %[[VAL_9]] : index +// CHECK: %[[VAL_147:.*]] = memref.load %[[VAL_19]]{{\[}}%[[VAL_146]]] : memref<11xindex> +// CHECK: %[[VAL_148:.*]] = arith.addi %[[VAL_143]], %[[VAL_8]] : index +// CHECK: %[[VAL_149:.*]] = memref.load %[[VAL_19]]{{\[}}%[[VAL_148]]] : memref<11xindex> +// CHECK: %[[VAL_150:.*]] = arith.cmpi ult, %[[VAL_147]], %[[VAL_149]] : index +// CHECK: %[[VAL_151:.*]] = scf.if %[[VAL_150]] -> (index) { +// CHECK: %[[VAL_152:.*]] = memref.load %[[VAL_17]]{{\[}}%[[VAL_147]]] : memref +// CHECK: %[[VAL_153:.*]] = arith.cmpi eq, %[[VAL_152]], %[[VAL_88]] : index +// CHECK: %[[VAL_154:.*]] = scf.if %[[VAL_153]] -> (index) { +// CHECK: %[[VAL_155:.*]] = arith.addi %[[VAL_147]], %[[VAL_7]] : index +// CHECK: memref.store %[[VAL_155]], %[[VAL_19]]{{\[}}%[[VAL_146]]] : memref<11xindex> +// CHECK: scf.yield %[[VAL_155]] : index // CHECK: } else { -// CHECK: scf.yield %[[VAL_148]] : index +// CHECK: scf.yield %[[VAL_147]] : index // CHECK: } -// CHECK: scf.yield %[[VAL_157:.*]] : index +// CHECK: scf.yield %[[VAL_154]] : index // CHECK: } else { -// CHECK: scf.yield %[[VAL_148]] : index +// CHECK: scf.yield %[[VAL_147]] : index // CHECK: } -// CHECK: %[[VAL_158:.*]] = arith.cmpi ult, %[[VAL_159:.*]], %[[VAL_150]] : index -// CHECK: %[[VAL_160:.*]] = scf.if %[[VAL_158]] -> (index) { -// CHECK: %[[VAL_161:.*]] = memref.load %[[VAL_16]]{{\[}}%[[VAL_159]]] : memref -// CHECK: scf.yield %[[VAL_161]] : index +// CHECK: %[[VAL_156:.*]] = arith.cmpi ult, %[[VAL_151]], %[[VAL_149]] : index +// CHECK: %[[VAL_157:.*]] = scf.if %[[VAL_156]] -> (index) { +// CHECK: %[[VAL_158:.*]] = memref.load %[[VAL_17]]{{\[}}%[[VAL_151]]] : memref +// CHECK: scf.yield %[[VAL_158]] : index // CHECK: } else { -// CHECK: scf.yield %[[VAL_146]] : index +// CHECK: scf.yield %[[VAL_144]] : index // CHECK: } -// CHECK: %[[VAL_162:.*]] = arith.ori %[[VAL_158]], %[[VAL_147]] : i1 -// CHECK: %[[VAL_163:.*]] = arith.cmpi ult, %[[VAL_164:.*]], %[[VAL_146]] : index -// CHECK: %[[VAL_165:.*]] = arith.select %[[VAL_163]], %[[VAL_164]], %[[VAL_146]] : index -// CHECK: scf.yield %[[VAL_165]], %[[VAL_162]] : index, i1 +// CHECK: %[[VAL_159:.*]] = arith.ori %[[VAL_156]], %[[VAL_145]] : i1 +// CHECK: %[[VAL_160:.*]] = arith.cmpi ult, %[[VAL_157]], %[[VAL_144]] : index +// CHECK: %[[VAL_161:.*]] = arith.select %[[VAL_160]], %[[VAL_157]], %[[VAL_144]] : index +// CHECK: scf.yield %[[VAL_161]], %[[VAL_159]] : index, i1 // CHECK: } -// CHECK: %[[VAL_166:.*]] = arith.addi %[[VAL_167:.*]]#0, %[[VAL_7]] : index -// CHECK: %[[VAL_168:.*]] = arith.addi %[[VAL_167]]#0, %[[VAL_3]] : index -// CHECK: %[[VAL_169:.*]] = arith.cmpi uge, %[[VAL_166]], %[[VAL_5]] : index -// CHECK: %[[VAL_170:.*]] = arith.select %[[VAL_169]], %[[VAL_168]], %[[VAL_6]] : index -// CHECK: scf.yield %[[VAL_167]]#0, %[[VAL_167]]#1, %[[VAL_170]] : index, i1, index +// CHECK: %[[VAL_162:.*]] = arith.addi %[[VAL_163:.*]]#0, %[[VAL_7]] : index +// CHECK: %[[VAL_164:.*]] = arith.addi %[[VAL_163]]#0, %[[VAL_3]] : index +// CHECK: %[[VAL_165:.*]] = arith.cmpi uge, %[[VAL_162]], %[[VAL_6]] : index +// CHECK: %[[VAL_166:.*]] = arith.select %[[VAL_165]], %[[VAL_164]], %[[VAL_10]] : index +// CHECK: scf.yield %[[VAL_163]]#0, %[[VAL_163]]#1, %[[VAL_166]] : index, i1, index // CHECK: } -// CHECK: %[[VAL_171:.*]] = arith.addi %[[VAL_88]], %[[VAL_7]] : index -// CHECK: %[[VAL_172:.*]] = arith.cmpi ugt, %[[VAL_173:.*]]#2, %[[VAL_171]] : index -// CHECK: %[[VAL_174:.*]] = arith.select %[[VAL_172]], %[[VAL_173]]#2, %[[VAL_171]] : index -// CHECK: %[[VAL_175:.*]] = arith.addi %[[VAL_174]], %[[VAL_5]] : index -// CHECK: %[[VAL_176:.*]] = arith.cmpi ule, %[[VAL_175]], %[[VAL_4]] : index -// CHECK: %[[VAL_177:.*]] = arith.andi %[[VAL_173]]#1, %[[VAL_176]] : i1 -// CHECK: scf.yield %[[VAL_177]], %[[VAL_173]]#0, %[[VAL_174]], %[[VAL_178:.*]] : i1, index, index, tensor<6x6xi32, #sparse{{[0-9]*}}> +// CHECK: %[[VAL_167:.*]] = arith.addi %[[VAL_89]], %[[VAL_7]] : index +// CHECK: %[[VAL_168:.*]] = arith.cmpi ugt, %[[VAL_169:.*]]#2, %[[VAL_167]] : index +// CHECK: %[[VAL_170:.*]] = arith.select %[[VAL_168]], %[[VAL_169]]#2, %[[VAL_167]] : index +// CHECK: %[[VAL_171:.*]] = arith.addi %[[VAL_170]], %[[VAL_6]] : index +// CHECK: %[[VAL_172:.*]] = arith.cmpi ule, %[[VAL_171]], %[[VAL_5]] : index +// CHECK: %[[VAL_173:.*]] = arith.andi %[[VAL_169]]#1, %[[VAL_172]] : i1 +// CHECK: scf.yield %[[VAL_173]], %[[VAL_169]]#0, %[[VAL_170]], %[[VAL_135]] : i1, index, index, tensor<6x6xi32, #sparse{{[0-9]*}}> // CHECK: } -// CHECK: memref.store %[[VAL_6]], %[[VAL_19]]{{\[}}%[[VAL_7]]] : memref<5xindex> -// CHECK: %[[VAL_179:.*]] = arith.cmpi ugt, %[[VAL_32]], %[[VAL_33]] : index -// CHECK: %[[VAL_180:.*]]:3 = scf.if %[[VAL_179]] -> (index, i1, index) { -// CHECK: %[[VAL_181:.*]] = arith.addi %[[VAL_33]], %[[VAL_7]] : index -// CHECK: scf.yield %[[VAL_32]], %[[VAL_2]], %[[VAL_181]] : index, i1, index +// CHECK: memref.store %[[VAL_10]], %[[VAL_20]]{{\[}}%[[VAL_7]]] : memref<5xindex> +// CHECK: %[[VAL_174:.*]] = arith.cmpi ugt, %[[VAL_33]], %[[VAL_34]] : index +// CHECK: %[[VAL_175:.*]]:3 = scf.if %[[VAL_174]] -> (index, i1, index) { +// CHECK: %[[VAL_176:.*]] = arith.addi %[[VAL_34]], %[[VAL_7]] : index +// CHECK: scf.yield %[[VAL_33]], %[[VAL_2]], %[[VAL_176]] : index, i1, index // CHECK: } else { -// CHECK: %[[VAL_182:.*]] = memref.load %[[VAL_19]]{{\[}}%[[VAL_6]]] : memref<5xindex> -// CHECK: %[[VAL_183:.*]]:2 = scf.for %[[VAL_184:.*]] = %[[VAL_8]] to %[[VAL_182]] step %[[VAL_5]] iter_args(%[[VAL_185:.*]] = %[[VAL_4]], %[[VAL_186:.*]] = %[[VAL_11]]) -> (index, i1) { -// CHECK: %[[VAL_187:.*]] = memref.load %[[VAL_19]]{{\[}}%[[VAL_184]]] : memref<5xindex> -// CHECK: %[[VAL_188:.*]] = arith.addi %[[VAL_184]], %[[VAL_7]] : index -// CHECK: %[[VAL_189:.*]] = memref.load %[[VAL_19]]{{\[}}%[[VAL_188]]] : memref<5xindex> -// CHECK: %[[VAL_190:.*]] = arith.cmpi ult, %[[VAL_187]], %[[VAL_189]] : index -// CHECK: %[[VAL_191:.*]] = scf.if %[[VAL_190]] -> (index) { -// CHECK: %[[VAL_192:.*]] = memref.load %[[VAL_14]]{{\[}}%[[VAL_187]]] : memref -// CHECK: %[[VAL_193:.*]] = arith.cmpi eq, %[[VAL_192]], %[[VAL_32]] : index -// CHECK: %[[VAL_194:.*]] = scf.if %[[VAL_193]] -> (index) { -// CHECK: %[[VAL_195:.*]] = arith.addi %[[VAL_187]], %[[VAL_7]] : index -// CHECK: memref.store %[[VAL_195]], %[[VAL_19]]{{\[}}%[[VAL_184]]] : memref<5xindex> -// CHECK: scf.yield %[[VAL_195]] : index +// CHECK: %[[VAL_177:.*]] = memref.load %[[VAL_20]]{{\[}}%[[VAL_10]]] : memref<5xindex> +// CHECK: %[[VAL_178:.*]]:2 = scf.for %[[VAL_179:.*]] = %[[VAL_10]] to %[[VAL_177]] step %[[VAL_7]] iter_args(%[[VAL_180:.*]] = %[[VAL_5]], %[[VAL_181:.*]] = %[[VAL_12]]) -> (index, i1) { +// CHECK: %[[VAL_182:.*]] = arith.addi %[[VAL_179]], %[[VAL_9]] : index +// CHECK: %[[VAL_183:.*]] = memref.load %[[VAL_20]]{{\[}}%[[VAL_182]]] : memref<5xindex> +// CHECK: %[[VAL_184:.*]] = arith.addi %[[VAL_179]], %[[VAL_6]] : index +// CHECK: %[[VAL_185:.*]] = memref.load %[[VAL_20]]{{\[}}%[[VAL_184]]] : memref<5xindex> +// CHECK: %[[VAL_186:.*]] = arith.cmpi ult, %[[VAL_183]], %[[VAL_185]] : index +// CHECK: %[[VAL_187:.*]] = scf.if %[[VAL_186]] -> (index) { +// CHECK: %[[VAL_188:.*]] = memref.load %[[VAL_15]]{{\[}}%[[VAL_183]]] : memref +// CHECK: %[[VAL_189:.*]] = arith.cmpi eq, %[[VAL_188]], %[[VAL_33]] : index +// CHECK: %[[VAL_190:.*]] = scf.if %[[VAL_189]] -> (index) { +// CHECK: %[[VAL_191:.*]] = arith.addi %[[VAL_183]], %[[VAL_7]] : index +// CHECK: memref.store %[[VAL_191]], %[[VAL_20]]{{\[}}%[[VAL_182]]] : memref<5xindex> +// CHECK: scf.yield %[[VAL_191]] : index // CHECK: } else { -// CHECK: scf.yield %[[VAL_187]] : index +// CHECK: scf.yield %[[VAL_183]] : index // CHECK: } -// CHECK: scf.yield %[[VAL_196:.*]] : index +// CHECK: scf.yield %[[VAL_190]] : index // CHECK: } else { -// CHECK: scf.yield %[[VAL_187]] : index +// CHECK: scf.yield %[[VAL_183]] : index // CHECK: } -// CHECK: %[[VAL_197:.*]] = arith.cmpi ult, %[[VAL_198:.*]], %[[VAL_189]] : index -// CHECK: %[[VAL_199:.*]] = scf.if %[[VAL_197]] -> (index) { -// CHECK: %[[VAL_200:.*]] = memref.load %[[VAL_14]]{{\[}}%[[VAL_198]]] : memref -// CHECK: scf.yield %[[VAL_200]] : index +// CHECK: %[[VAL_192:.*]] = arith.cmpi ult, %[[VAL_187]], %[[VAL_185]] : index +// CHECK: %[[VAL_193:.*]] = scf.if %[[VAL_192]] -> (index) { +// CHECK: %[[VAL_194:.*]] = memref.load %[[VAL_15]]{{\[}}%[[VAL_187]]] : memref +// CHECK: scf.yield %[[VAL_194]] : index // CHECK: } else { -// CHECK: scf.yield %[[VAL_185]] : index +// CHECK: scf.yield %[[VAL_180]] : index // CHECK: } -// CHECK: %[[VAL_201:.*]] = arith.ori %[[VAL_197]], %[[VAL_186]] : i1 -// CHECK: %[[VAL_202:.*]] = arith.cmpi ult, %[[VAL_203:.*]], %[[VAL_185]] : index -// CHECK: %[[VAL_204:.*]] = arith.select %[[VAL_202]], %[[VAL_203]], %[[VAL_185]] : index -// CHECK: scf.yield %[[VAL_204]], %[[VAL_201]] : index, i1 +// CHECK: %[[VAL_195:.*]] = arith.ori %[[VAL_192]], %[[VAL_181]] : i1 +// CHECK: %[[VAL_196:.*]] = arith.cmpi ult, %[[VAL_193]], %[[VAL_180]] : index +// CHECK: %[[VAL_197:.*]] = arith.select %[[VAL_196]], %[[VAL_193]], %[[VAL_180]] : index +// CHECK: scf.yield %[[VAL_197]], %[[VAL_195]] : index, i1 // CHECK: } -// CHECK: %[[VAL_205:.*]] = arith.addi %[[VAL_206:.*]]#0, %[[VAL_7]] : index -// CHECK: %[[VAL_207:.*]] = arith.addi %[[VAL_206]]#0, %[[VAL_3]] : index -// CHECK: %[[VAL_208:.*]] = arith.cmpi uge, %[[VAL_205]], %[[VAL_5]] : index -// CHECK: %[[VAL_209:.*]] = arith.select %[[VAL_208]], %[[VAL_207]], %[[VAL_6]] : index -// CHECK: scf.yield %[[VAL_206]]#0, %[[VAL_206]]#1, %[[VAL_209]] : index, i1, index +// CHECK: %[[VAL_198:.*]] = arith.addi %[[VAL_199:.*]]#0, %[[VAL_7]] : index +// CHECK: %[[VAL_200:.*]] = arith.addi %[[VAL_199]]#0, %[[VAL_3]] : index +// CHECK: %[[VAL_201:.*]] = arith.cmpi uge, %[[VAL_198]], %[[VAL_6]] : index +// CHECK: %[[VAL_202:.*]] = arith.select %[[VAL_201]], %[[VAL_200]], %[[VAL_10]] : index +// CHECK: scf.yield %[[VAL_199]]#0, %[[VAL_199]]#1, %[[VAL_202]] : index, i1, index // CHECK: } -// CHECK: %[[VAL_210:.*]] = arith.addi %[[VAL_33]], %[[VAL_7]] : index -// CHECK: %[[VAL_211:.*]] = arith.cmpi ugt, %[[VAL_212:.*]]#2, %[[VAL_210]] : index -// CHECK: %[[VAL_213:.*]] = arith.select %[[VAL_211]], %[[VAL_212]]#2, %[[VAL_210]] : index -// CHECK: %[[VAL_214:.*]] = arith.addi %[[VAL_213]], %[[VAL_5]] : index -// CHECK: %[[VAL_215:.*]] = arith.cmpi ule, %[[VAL_214]], %[[VAL_4]] : index -// CHECK: %[[VAL_216:.*]] = arith.andi %[[VAL_212]]#1, %[[VAL_215]] : i1 -// CHECK: scf.yield %[[VAL_216]], %[[VAL_212]]#0, %[[VAL_213]], %[[VAL_217:.*]]#2 : i1, index, index, tensor<6x6xi32, #sparse{{[0-9]*}}> +// CHECK: %[[VAL_203:.*]] = arith.addi %[[VAL_34]], %[[VAL_7]] : index +// CHECK: %[[VAL_204:.*]] = arith.cmpi ugt, %[[VAL_205:.*]]#2, %[[VAL_203]] : index +// CHECK: %[[VAL_206:.*]] = arith.select %[[VAL_204]], %[[VAL_205]]#2, %[[VAL_203]] : index +// CHECK: %[[VAL_207:.*]] = arith.addi %[[VAL_206]], %[[VAL_6]] : index +// CHECK: %[[VAL_208:.*]] = arith.cmpi ule, %[[VAL_207]], %[[VAL_5]] : index +// CHECK: %[[VAL_209:.*]] = arith.andi %[[VAL_205]]#1, %[[VAL_208]] : i1 +// CHECK: scf.yield %[[VAL_209]], %[[VAL_205]]#0, %[[VAL_206]], %[[VAL_210:.*]]#2 : i1, index, index, tensor<6x6xi32, #sparse{{[0-9]*}}> // CHECK: } -// CHECK: %[[VAL_218:.*]] = sparse_tensor.load %[[VAL_219:.*]]#2 hasInserts : tensor<6x6xi32, #sparse{{[0-9]*}}> -// CHECK: return %[[VAL_218]] : tensor<6x6xi32, #sparse{{[0-9]*}}> +// CHECK: %[[VAL_211:.*]] = sparse_tensor.load %[[VAL_212:.*]]#2 hasInserts : tensor<6x6xi32, #sparse{{[0-9]*}}> +// CHECK: return %[[VAL_211]] : tensor<6x6xi32, #sparse{{[0-9]*}}> // CHECK: } func.func @conv2d_all_sparse_CSR(%arg0: tensor<8x8xi32, #DCSR>, %arg1: tensor<3x3xi32>) -> tensor<6x6xi32, #DCSR> { -- GitLab From 1035cc7029180243de371384eee91f4e1e87d199 Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Thu, 30 Nov 2023 16:44:47 -0800 Subject: [PATCH 074/699] [OpenMP][NFC] Encapsulate Devices.size() (#74010) --- openmp/libomptarget/include/PluginManager.h | 5 +++++ openmp/libomptarget/src/api.cpp | 24 +++++++-------------- 2 files changed, 13 insertions(+), 16 deletions(-) diff --git a/openmp/libomptarget/include/PluginManager.h b/openmp/libomptarget/include/PluginManager.h index 3a1c97fc52c9..e9b5169510fc 100644 --- a/openmp/libomptarget/include/PluginManager.h +++ b/openmp/libomptarget/include/PluginManager.h @@ -143,6 +143,11 @@ struct PluginManager { DelayedBinDesc.clear(); } + int getNumDevices() { + std::lock_guard Lock(RTLsMtx); + return Devices.size(); + } + private: bool RTLsLoaded = false; llvm::SmallVector<__tgt_bin_desc *> DelayedBinDesc; diff --git a/openmp/libomptarget/src/api.cpp b/openmp/libomptarget/src/api.cpp index e44421428ada..cc4cca286df5 100644 --- a/openmp/libomptarget/src/api.cpp +++ b/openmp/libomptarget/src/api.cpp @@ -28,13 +28,11 @@ EXTERN int omp_get_num_devices(void) { TIMESCOPE(); - PM->RTLsMtx.lock(); - size_t DevicesSize = PM->Devices.size(); - PM->RTLsMtx.unlock(); + size_t NumDevices = PM->getNumDevices(); - DP("Call to omp_get_num_devices returning %zd\n", DevicesSize); + DP("Call to omp_get_num_devices returning %zd\n", NumDevices); - return DevicesSize; + return NumDevices; } EXTERN int omp_get_device_num(void) { @@ -112,10 +110,8 @@ EXTERN int omp_target_is_present(const void *Ptr, int DeviceNum) { return true; } - PM->RTLsMtx.lock(); - size_t DevicesSize = PM->Devices.size(); - PM->RTLsMtx.unlock(); - if (DevicesSize <= (size_t)DeviceNum) { + size_t NumDevices = PM->getNumDevices(); + if (NumDevices <= (size_t)DeviceNum) { DP("Call to omp_target_is_present with invalid device ID, returning " "false\n"); return false; @@ -562,18 +558,14 @@ EXTERN void *omp_get_mapped_ptr(const void *Ptr, int DeviceNum) { return nullptr; } - if (DeviceNum == omp_get_initial_device()) { + size_t NumDevices = omp_get_initial_device(); + if (DeviceNum == NumDevices) { REPORT("Device %d is initial device, returning Ptr " DPxMOD ".\n", DeviceNum, DPxPTR(Ptr)); return const_cast(Ptr); } - int DevicesSize = omp_get_initial_device(); - { - std::lock_guard LG(PM->RTLsMtx); - DevicesSize = PM->Devices.size(); - } - if (DevicesSize <= DeviceNum) { + if (NumDevices <= DeviceNum) { DP("DeviceNum %d is invalid, returning nullptr.\n", DeviceNum); return nullptr; } -- GitLab From 071855dc2c4939c0b7c51da63e84bd956e49c74a Mon Sep 17 00:00:00 2001 From: Teresa Johnson Date: Thu, 30 Nov 2023 16:59:13 -0800 Subject: [PATCH 075/699] [ThinLTO] Fix assembly dumping of vtable type ids (#73997) With RTTI, a C++ class type info will get two entries in the summary index: a gv and a typeidCompatibleVTable, both sharing the same GUID. Ensure we use different namespaces to generate the entry slot numbers for these two different summary entries. --- llvm/lib/IR/AsmWriter.cpp | 31 +++++++++++++++--- .../test/Assembler/thinlto-vtable-summary2.ll | 32 +++++++++++++++++++ 2 files changed, 59 insertions(+), 4 deletions(-) create mode 100644 llvm/test/Assembler/thinlto-vtable-summary2.ll diff --git a/llvm/lib/IR/AsmWriter.cpp b/llvm/lib/IR/AsmWriter.cpp index 601b636f306a..fabc79adbd33 100644 --- a/llvm/lib/IR/AsmWriter.cpp +++ b/llvm/lib/IR/AsmWriter.cpp @@ -736,6 +736,11 @@ private: StringMap TypeIdMap; unsigned TypeIdNext = 0; + /// TypeIdCompatibleVtableMap - The slot map for type compatible vtable ids + /// used in the summary index. + StringMap TypeIdCompatibleVtableMap; + unsigned TypeIdCompatibleVtableNext = 0; + public: /// Construct from a module. /// @@ -779,6 +784,7 @@ public: int getModulePathSlot(StringRef Path); int getGUIDSlot(GlobalValue::GUID GUID); int getTypeIdSlot(StringRef Id); + int getTypeIdCompatibleVtableSlot(StringRef Id); /// If you'd like to deal with a function instead of just a module, use /// this method to get its data into the SlotTracker. @@ -834,6 +840,7 @@ private: inline void CreateModulePathSlot(StringRef Path); void CreateGUIDSlot(GlobalValue::GUID GUID); void CreateTypeIdSlot(StringRef Id); + void CreateTypeIdCompatibleVtableSlot(StringRef Id); /// Add all of the module level global variables (and their initializers) /// and function declarations, but not the contents of those functions. @@ -1095,11 +1102,13 @@ int SlotTracker::processIndex() { for (auto &GlobalList : *TheIndex) CreateGUIDSlot(GlobalList.first); + // Start numbering the TypeIdCompatibleVtables after the GUIDs. + TypeIdCompatibleVtableNext = GUIDNext; for (auto &TId : TheIndex->typeIdCompatibleVtableMap()) - CreateGUIDSlot(GlobalValue::getGUID(TId.first)); + CreateTypeIdCompatibleVtableSlot(TId.first); - // Start numbering the TypeIds after the GUIDs. - TypeIdNext = GUIDNext; + // Start numbering the TypeIds after the TypeIdCompatibleVtables. + TypeIdNext = TypeIdCompatibleVtableNext; for (const auto &TID : TheIndex->typeIds()) CreateTypeIdSlot(TID.second.first); @@ -1232,6 +1241,15 @@ int SlotTracker::getTypeIdSlot(StringRef Id) { return I == TypeIdMap.end() ? -1 : (int)I->second; } +int SlotTracker::getTypeIdCompatibleVtableSlot(StringRef Id) { + // Check for uninitialized state and do lazy initialization. + initializeIndexIfNeeded(); + + // Find the TypeIdCompatibleVtable string in the map + auto I = TypeIdCompatibleVtableMap.find(Id); + return I == TypeIdCompatibleVtableMap.end() ? -1 : (int)I->second; +} + /// CreateModuleSlot - Insert the specified GlobalValue* into the slot table. void SlotTracker::CreateModuleSlot(const GlobalValue *V) { assert(V && "Can't insert a null Value into SlotTracker!"); @@ -1307,6 +1325,11 @@ void SlotTracker::CreateTypeIdSlot(StringRef Id) { TypeIdMap[Id] = TypeIdNext++; } +/// Create a new slot for the specified Id +void SlotTracker::CreateTypeIdCompatibleVtableSlot(StringRef Id) { + TypeIdCompatibleVtableMap[Id] = TypeIdCompatibleVtableNext++; +} + namespace { /// Common instances used by most of the printer functions. struct AsmWriterContext { @@ -2955,7 +2978,7 @@ void AssemblyWriter::printModuleSummaryIndex() { // Print the TypeIdCompatibleVtableMap entries. for (auto &TId : TheIndex->typeIdCompatibleVtableMap()) { auto GUID = GlobalValue::getGUID(TId.first); - Out << "^" << Machine.getGUIDSlot(GUID) + Out << "^" << Machine.getTypeIdCompatibleVtableSlot(TId.first) << " = typeidCompatibleVTable: (name: \"" << TId.first << "\""; printTypeIdCompatibleVtableSummary(TId.second); Out << ") ; guid = " << GUID << "\n"; diff --git a/llvm/test/Assembler/thinlto-vtable-summary2.ll b/llvm/test/Assembler/thinlto-vtable-summary2.ll new file mode 100644 index 000000000000..862b7abfcd3c --- /dev/null +++ b/llvm/test/Assembler/thinlto-vtable-summary2.ll @@ -0,0 +1,32 @@ +;; Test to ensure that the summary is correctly printed when there is both a +;; global variable summary and a vtable typeid summary entry for the same +;; symbol. + +; RUN: opt %s -S -module-summary | FileCheck %s +;; Make sure it round trips correctly. +; RUN: opt %s -S -module-summary -o - | llvm-as -o - | llvm-dis -o - | FileCheck %s + +;; These summary entries should get numbered differently. +; CHECK: ^2 = gv: (name: "_ZTS1A" +; CHECK: ^6 = typeidCompatibleVTable: (name: "_ZTS1A" + +; ModuleID = 'thinlto-vtable-summary2.cc' +source_filename = "thinlto-vtable-summary2.cc" +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +@_ZTV1A = dso_local unnamed_addr constant { [3 x ptr] } { [3 x ptr] [ptr null, ptr @_ZTI1A, ptr @_ZN1A3fooEv] }, align 8, !type !0, !type !1 +@_ZTVN10__cxxabiv117__class_type_infoE = external global [0 x ptr] +@_ZTS1A = dso_local constant [3 x i8] c"1A\00", align 1 +@_ZTI1A = dso_local constant { ptr, ptr } { ptr getelementptr inbounds (ptr, ptr @_ZTVN10__cxxabiv117__class_type_infoE, i64 2), ptr @_ZTS1A }, align 8 + +define dso_local noundef i32 @_ZN1A3fooEv(ptr noundef nonnull align 8 dereferenceable(8) %this) unnamed_addr align 2 { +entry: + %this.addr = alloca ptr, align 8 + store ptr %this, ptr %this.addr, align 8 + %this1 = load ptr, ptr %this.addr, align 8 + ret i32 1 +} + +!0 = !{i64 16, !"_ZTS1A"} +!1 = !{i64 16, !"_ZTSM1AFivE.virtual"} -- GitLab From 51fc8544c7a267e5621eadfebf758f46b015ebd4 Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Thu, 30 Nov 2023 17:08:41 -0800 Subject: [PATCH 076/699] [OpenMP][NFC] Move mapping related logic into Mapping.h (#74009) --- openmp/libomptarget/include/OpenMP/Mapping.h | 19 +++++++++++++++++++ openmp/libomptarget/include/PluginManager.h | 7 ------- openmp/libomptarget/src/device.cpp | 2 +- openmp/libomptarget/src/rtl.cpp | 14 +------------- 4 files changed, 21 insertions(+), 21 deletions(-) diff --git a/openmp/libomptarget/include/OpenMP/Mapping.h b/openmp/libomptarget/include/OpenMP/Mapping.h index b01831c61f6c..9a1ecb808792 100644 --- a/openmp/libomptarget/include/OpenMP/Mapping.h +++ b/openmp/libomptarget/include/OpenMP/Mapping.h @@ -13,6 +13,7 @@ #ifndef OMPTARGET_OPENMP_MAPPING_H #define OMPTARGET_OPENMP_MAPPING_H +#include "Shared/EnvironmentVar.h" #include "omptarget.h" #include @@ -26,6 +27,24 @@ class AsyncInfoTy; using map_var_info_t = void *; +class MappingConfig { + + MappingConfig() { + BoolEnvar ForceAtomic = BoolEnvar("LIBOMPTARGET_MAP_FORCE_ATOMIC", true); + UseEventsForAtomicTransfers = ForceAtomic; + } + +public: + static const MappingConfig &get() { + static MappingConfig MP; + return MP; + }; + + /// Flag to indicate if we use events to ensure the atomicity of + /// map clauses or not. Can be modified with an environment variable. + bool UseEventsForAtomicTransfers = true; +}; + /// Information about shadow pointers. struct ShadowPtrInfoTy { void **HstPtrAddr = nullptr; diff --git a/openmp/libomptarget/include/PluginManager.h b/openmp/libomptarget/include/PluginManager.h index e9b5169510fc..c92884d8e27d 100644 --- a/openmp/libomptarget/include/PluginManager.h +++ b/openmp/libomptarget/include/PluginManager.h @@ -93,9 +93,6 @@ private: /// Struct for the data required to handle plugins struct PluginManager { - PluginManager(bool UseEventsForAtomicTransfers) - : UseEventsForAtomicTransfers(UseEventsForAtomicTransfers) {} - /// RTLs identified on the host PluginAdaptorManagerTy RTLs; @@ -121,10 +118,6 @@ struct PluginManager { kmp_target_offload_kind_t TargetOffloadPolicy = tgt_default; std::mutex TargetOffloadMtx; ///< For TargetOffloadPolicy - /// Flag to indicate if we use events to ensure the atomicity of - /// map clauses or not. Can be modified with an environment variable. - const bool UseEventsForAtomicTransfers; - // Work around for plugins that call dlopen on shared libraries that call // tgt_register_lib during their initialisation. Stash the pointers in a // vector until the plugins are all initialised and then register them. diff --git a/openmp/libomptarget/src/device.cpp b/openmp/libomptarget/src/device.cpp index da7d33b3f40c..31499cbf9317 100644 --- a/openmp/libomptarget/src/device.cpp +++ b/openmp/libomptarget/src/device.cpp @@ -35,7 +35,7 @@ using namespace llvm::omp::target::ompt; int HostDataToTargetTy::addEventIfNecessary(DeviceTy &Device, AsyncInfoTy &AsyncInfo) const { // First, check if the user disabled atomic map transfer/malloc/dealloc. - if (!PM->UseEventsForAtomicTransfers) + if (!MappingConfig::get().UseEventsForAtomicTransfers) return OFFLOAD_SUCCESS; void *Event = getEvent(); diff --git a/openmp/libomptarget/src/rtl.cpp b/openmp/libomptarget/src/rtl.cpp index 42d147d1c145..3cc7ac381640 100644 --- a/openmp/libomptarget/src/rtl.cpp +++ b/openmp/libomptarget/src/rtl.cpp @@ -48,19 +48,7 @@ extern void ompt::connectLibrary(); __attribute__((constructor(101))) void init() { DP("Init target library!\n"); - bool UseEventsForAtomicTransfers = true; - if (const char *ForceAtomicMap = getenv("LIBOMPTARGET_MAP_FORCE_ATOMIC")) { - std::string ForceAtomicMapStr(ForceAtomicMap); - if (ForceAtomicMapStr == "false" || ForceAtomicMapStr == "FALSE") - UseEventsForAtomicTransfers = false; - else if (ForceAtomicMapStr != "true" && ForceAtomicMapStr != "TRUE") - fprintf(stderr, - "Warning: 'LIBOMPTARGET_MAP_FORCE_ATOMIC' accepts only " - "'true'/'TRUE' or 'false'/'FALSE' as options, '%s' ignored\n", - ForceAtomicMap); - } - - PM = new PluginManager(UseEventsForAtomicTransfers); + PM = new PluginManager(); #ifdef OMPT_SUPPORT // Initialize OMPT first -- GitLab From cfe1ece833d643921da2735cd80e32b32ef170fb Mon Sep 17 00:00:00 2001 From: Paul Kirth Date: Thu, 30 Nov 2023 17:09:34 -0800 Subject: [PATCH 077/699] [clang][llvm][fatlto] Avoid cloning modules in FatLTO (#72180) https://github.com/llvm/llvm-project/issues/70703 pointed out that cloning LLVM modules could lead to miscompiles when using FatLTO. This is due to an existing issue when cloning modules with labels (see #55991 and #47769). Since this can lead to miscompilation, we can avoid cloning the LLVM modules, which was desirable anyway. This patch modifies the EmbedBitcodePass to no longer clone the module or run an input pipeline over it. Further, it make FatLTO always perform UnifiedLTO, so we can still defer the Thin/Full LTO decision to link-time. Lastly, it removes dead/obsolete code related to now defunct options that do not work with the EmbedBitcodePass implementation any longer. --- clang/lib/CodeGen/BackendUtil.cpp | 9 ++-- clang/lib/Driver/ToolChains/Clang.cpp | 4 +- clang/lib/Frontend/CompilerInvocation.cpp | 14 ++++++ clang/test/CodeGen/fat-lto-objects.c | 48 +++++++++---------- clang/test/Driver/fat-lto-objects.c | 12 +++++ llvm/docs/FatLTO.rst | 35 +++++++------- llvm/include/llvm/Passes/PassBuilder.h | 3 +- .../llvm/Transforms/IPO/EmbedBitcodePass.h | 17 +------ llvm/lib/Passes/PassBuilder.cpp | 20 -------- llvm/lib/Passes/PassBuilderPipelines.cpp | 22 ++++++--- llvm/lib/Passes/PassRegistry.def | 5 +- llvm/lib/Transforms/IPO/EmbedBitcodePass.cpp | 16 +------ llvm/test/CodeGen/X86/fat-lto-section.ll | 2 +- llvm/test/Transforms/EmbedBitcode/embed.ll | 3 -- 14 files changed, 94 insertions(+), 116 deletions(-) diff --git a/clang/lib/CodeGen/BackendUtil.cpp b/clang/lib/CodeGen/BackendUtil.cpp index f01a6514f6ef..8c666e2cb463 100644 --- a/clang/lib/CodeGen/BackendUtil.cpp +++ b/clang/lib/CodeGen/BackendUtil.cpp @@ -996,9 +996,8 @@ void EmitAssemblyHelper::RunOptimizationPipeline( } if (CodeGenOpts.FatLTO) { - MPM.addPass(PB.buildFatLTODefaultPipeline( - Level, PrepareForThinLTO, - PrepareForThinLTO || shouldEmitRegularLTOSummary())); + assert(CodeGenOpts.UnifiedLTO && "FatLTO requires UnifiedLTO"); + MPM.addPass(PB.buildFatLTODefaultPipeline(Level)); } else if (PrepareForThinLTO) { MPM.addPass(PB.buildThinLTOPreLinkDefaultPipeline(Level)); } else if (PrepareForLTO) { @@ -1042,7 +1041,6 @@ void EmitAssemblyHelper::RunOptimizationPipeline( MPM.addPass(PrintModulePass(*OS, "", CodeGenOpts.EmitLLVMUseLists, /*EmitLTOSummary=*/true)); } - } else { // Emit a module summary by default for Regular LTO except for ld64 // targets @@ -1073,7 +1071,8 @@ void EmitAssemblyHelper::RunOptimizationPipeline( if (!TheModule->getModuleFlag("EnableSplitLTOUnit")) TheModule->addModuleFlag(llvm::Module::Error, "EnableSplitLTOUnit", uint32_t(CodeGenOpts.EnableSplitLTOUnit)); - if (CodeGenOpts.UnifiedLTO && !TheModule->getModuleFlag("UnifiedLTO")) + // FatLTO always means UnifiedLTO + if (!TheModule->getModuleFlag("UnifiedLTO")) TheModule->addModuleFlag(llvm::Module::Error, "UnifiedLTO", uint32_t(1)); } diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index 3c8df8a9037d..b1ce95be38f8 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -4862,7 +4862,9 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, bool UnifiedLTO = false; if (IsUsingLTO) { UnifiedLTO = Args.hasFlag(options::OPT_funified_lto, - options::OPT_fno_unified_lto, Triple.isPS()); + options::OPT_fno_unified_lto, Triple.isPS()) || + Args.hasFlag(options::OPT_ffat_lto_objects, + options::OPT_fno_fat_lto_objects, false); if (UnifiedLTO) CmdArgs.push_back("-funified-lto"); } diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp index 5a8e4cf9843d..a6188cb45e17 100644 --- a/clang/lib/Frontend/CompilerInvocation.cpp +++ b/clang/lib/Frontend/CompilerInvocation.cpp @@ -1861,6 +1861,20 @@ bool CompilerInvocation::ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, if (Args.hasArg(OPT_funified_lto)) Opts.PrepareForThinLTO = true; } + if (Arg *A = Args.getLastArg(options::OPT_ffat_lto_objects, + options::OPT_fno_fat_lto_objects)) { + if (A->getOption().matches(options::OPT_ffat_lto_objects)) { + if (Arg *Uni = Args.getLastArg(options::OPT_funified_lto, + options::OPT_fno_unified_lto)) { + if (Uni->getOption().matches(options::OPT_fno_unified_lto)) + Diags.Report(diag::err_drv_incompatible_options) + << A->getAsString(Args) << "-fno-unified-lto"; + } else + Diags.Report(diag::err_drv_argument_only_allowed_with) + << A->getAsString(Args) << "-funified-lto"; + } + } + if (Arg *A = Args.getLastArg(OPT_fthinlto_index_EQ)) { if (IK.getLanguage() != Language::LLVM_IR) Diags.Report(diag::err_drv_argument_only_allowed_with) diff --git a/clang/test/CodeGen/fat-lto-objects.c b/clang/test/CodeGen/fat-lto-objects.c index 2c3a4ef9c615..95207e77c244 100644 --- a/clang/test/CodeGen/fat-lto-objects.c +++ b/clang/test/CodeGen/fat-lto-objects.c @@ -1,49 +1,47 @@ // REQUIRES: x86-registered-target -// RUN: %clang -cc1 -triple x86_64-unknown-linux-gnu -flto=full -ffat-lto-objects -fsplit-lto-unit -emit-llvm < %s | FileCheck %s --check-prefixes=FULL,SPLIT -// RUN: %clang -cc1 -triple x86_64-unknown-linux-gnu -flto=full -ffat-lto-objects -emit-llvm < %s | FileCheck %s --check-prefixes=FULL,SPLIT +// RUN: not %clang -cc1 -triple x86_64-unknown-linux-gnu -flto=full -ffat-lto-objects -fsplit-lto-unit -emit-llvm < %s 2>&1 | FileCheck %s --check-prefixes=NO-UNIFIED -// RUN: %clang -cc1 -triple x86_64-unknown-linux-gnu -flto=thin -fsplit-lto-unit -ffat-lto-objects -emit-llvm < %s | FileCheck %s --check-prefixes=THIN,SPLIT -// RUN: %clang -cc1 -triple x86_64-unknown-linux-gnu -flto=thin -ffat-lto-objects -emit-llvm < %s | FileCheck %s --check-prefixes=THIN,NOSPLIT +// RUN: %clang -cc1 -triple x86_64-unknown-linux-gnu -flto=full -funified-lto -ffat-lto-objects -fsplit-lto-unit -emit-llvm < %s | FileCheck %s --check-prefixes=FULL,SPLIT,UNIFIED +// RUN: %clang -cc1 -triple x86_64-unknown-linux-gnu -flto=full -funified-lto -ffat-lto-objects -emit-llvm < %s | FileCheck %s --check-prefixes=FULL,NOSPLIT,UNIFIED -// RUN: %clang -cc1 -triple x86_64-unknown-linux-gnu -flto=full -ffat-lto-objects -fsplit-lto-unit -emit-obj < %s -o %t.full.split.o +// RUN: %clang -cc1 -triple x86_64-unknown-linux-gnu -flto=thin -funified-lto -fsplit-lto-unit -ffat-lto-objects -emit-llvm < %s | FileCheck %s --check-prefixes=THIN,SPLIT,UNIFIED +// RUN: %clang -cc1 -triple x86_64-unknown-linux-gnu -flto=thin -funified-lto -ffat-lto-objects -emit-llvm < %s | FileCheck %s --check-prefixes=THIN,NOSPLIT,UNIFIED + +// RUN: %clang -cc1 -triple x86_64-unknown-linux-gnu -flto=full -funified-lto -ffat-lto-objects -fsplit-lto-unit -emit-obj < %s -o %t.full.split.o // RUN: llvm-readelf -S %t.full.split.o | FileCheck %s --check-prefixes=ELF // RUN: llvm-objcopy --dump-section=.llvm.lto=%t.full.split.bc %t.full.split.o -// RUN: llvm-dis %t.full.split.bc -o - | FileCheck %s --check-prefixes=FULL,SPLIT,NOUNIFIED +// RUN: llvm-dis %t.full.split.bc -o - | FileCheck %s --check-prefixes=THIN,SPLIT,UNIFIED -// RUN: %clang -cc1 -triple x86_64-unknown-linux-gnu -flto=full -ffat-lto-objects -emit-obj < %s -o %t.full.nosplit.o +// RUN: %clang -cc1 -triple x86_64-unknown-linux-gnu -flto=full -funified-lto -ffat-lto-objects -emit-obj < %s -o %t.full.nosplit.o // RUN: llvm-readelf -S %t.full.nosplit.o | FileCheck %s --check-prefixes=ELF // RUN: llvm-objcopy --dump-section=.llvm.lto=%t.full.nosplit.bc %t.full.nosplit.o -// RUN: llvm-dis %t.full.nosplit.bc -o - | FileCheck %s --check-prefixes=FULL,NOSPLIT,NOUNIFIED +// RUN: llvm-dis %t.full.nosplit.bc -o - | FileCheck %s --check-prefixes=THIN,NOSPLIT,UNIFIED -// RUN: %clang -cc1 -triple x86_64-unknown-linux-gnu -flto=thin -fsplit-lto-unit -ffat-lto-objects -emit-obj < %s -o %t.thin.split.o +// RUN: %clang -cc1 -triple x86_64-unknown-linux-gnu -flto=thin -funified-lto -fsplit-lto-unit -ffat-lto-objects -emit-obj < %s -o %t.thin.split.o // RUN: llvm-readelf -S %t.thin.split.o | FileCheck %s --check-prefixes=ELF // RUN: llvm-objcopy --dump-section=.llvm.lto=%t.thin.split.bc %t.thin.split.o -// RUN: llvm-dis %t.thin.split.bc -o - | FileCheck %s --check-prefixes=THIN,SPLIT,NOUNIFIED +// RUN: llvm-dis %t.thin.split.bc -o - | FileCheck %s --check-prefixes=THIN,SPLIT,UNIFIED -// RUN: %clang -cc1 -triple x86_64-unknown-linux-gnu -flto=thin -ffat-lto-objects -emit-obj < %s -o %t.thin.nosplit.o +// RUN: %clang -cc1 -triple x86_64-unknown-linux-gnu -flto=thin -funified-lto -ffat-lto-objects -emit-obj < %s -o %t.thin.nosplit.o // RUN: llvm-readelf -S %t.thin.nosplit.o | FileCheck %s --check-prefixes=ELF // RUN: llvm-objcopy --dump-section=.llvm.lto=%t.thin.nosplit.bc %t.thin.nosplit.o -// RUN: llvm-dis %t.thin.nosplit.bc -o - | FileCheck %s --check-prefixes=THIN,NOSPLIT,NOUNIFIED - -// RUN: %clang -cc1 -triple x86_64-unknown-linux-gnu -flto=thin -funified-lto -ffat-lto-objects -emit-obj < %s -o %t.unified.o -// RUN: llvm-readelf -S %t.unified.o | FileCheck %s --check-prefixes=ELF -// RUN: llvm-objcopy --dump-section=.llvm.lto=%t.unified.bc %t.unified.o -// RUN: llvm-dis %t.unified.bc -o - | FileCheck %s --check-prefixes=THIN,NOSPLIT,UNIFIED +// RUN: llvm-dis %t.thin.nosplit.bc -o - | FileCheck %s --check-prefixes=THIN,NOSPLIT,UNIFIED -// RUN: %clang -cc1 -triple x86_64-unknown-linux-gnu -flto=full -ffat-lto-objects -fsplit-lto-unit -S < %s -o - \ +// RUN: %clang -cc1 -triple x86_64-unknown-linux-gnu -flto=full -funified-lto -ffat-lto-objects -fsplit-lto-unit -S < %s -o - \ // RUN: | FileCheck %s --check-prefixes=ASM -/// Check that the ThinLTO metadata is only set false for full LTO. -// FULL: ![[#]] = !{i32 1, !"ThinLTO", i32 0} -// THIN-NOT: ![[#]] = !{i32 1, !"ThinLTO", i32 0} - /// Be sure we enable split LTO units correctly under -ffat-lto-objects. -// SPLIT: ![[#]] = !{i32 1, !"EnableSplitLTOUnit", i32 1} +// SPLIT: ![[#]] = !{i32 1, !"EnableSplitLTOUnit", i32 1} // NOSPLIT: ![[#]] = !{i32 1, !"EnableSplitLTOUnit", i32 0} -// UNIFIED: ![[#]] = !{i32 1, !"UnifiedLTO", i32 1} -// NOUNIFIED-NOT: ![[#]] = !{i32 1, !"UnifiedLTO", i32 1} +/// Check that the ThinLTO metadata is set true for both full and thin LTO, since FatLTO is based on UnifiedLTO. +// FULL: ![[#]] = !{i32 1, !"ThinLTO", i32 1} +// THIN-NOT: ![[#]] = !{i32 1, !"ThinLTO", i32 0} + +/// FatLTO always uses UnifiedLTO. It's an error if they aren't set together +// UNIFIED: ![[#]] = !{i32 1, !"UnifiedLTO", i32 1} +// NO-UNIFIED: error: invalid argument '-ffat-lto-objects' only allowed with '-funified-lto' // ELF: .llvm.lto diff --git a/clang/test/Driver/fat-lto-objects.c b/clang/test/Driver/fat-lto-objects.c index 887c33fa76d7..e02359db3f0a 100644 --- a/clang/test/Driver/fat-lto-objects.c +++ b/clang/test/Driver/fat-lto-objects.c @@ -1,5 +1,6 @@ // RUN: %clang --target=x86_64-unknown-linux-gnu -flto -ffat-lto-objects -### %s -c 2>&1 | FileCheck %s -check-prefix=CHECK-CC // CHECK-CC: -cc1 +// CHECK-CC-SAME: -funified-lto // CHECK-CC-SAME: -emit-obj // CHECK-CC-SAME: -ffat-lto-objects @@ -15,6 +16,7 @@ // RUN: %clang --target=x86_64-unknown-linux-gnu -flto -ffat-lto-objects -### %s -S 2>&1 | FileCheck %s -check-prefix=CHECK-CC-S-LTO // RUN: %clang --target=x86_64-unknown-linux-gnu -flto -ffat-lto-objects -### %s -S -emit-llvm 2>&1 | FileCheck %s -check-prefix=CHECK-CC-S-LTO // CHECK-CC-S-LTO: -cc1 +// CHECK-CC-S-LTO-SAME: -funified-lto // CHECK-CC-S-LTO-SAME: -emit-llvm // CHECK-CC-S-LTO-SAME: -ffat-lto-objects @@ -32,3 +34,13 @@ // RUN: -fuse-ld=lld -fno-lto -ffat-lto-objects -### 2>&1 | FileCheck --check-prefix=NOLTO %s // LTO: "--fat-lto-objects" // NOLTO-NOT: "--fat-lto-objects" + +/// Make sure that incompatible options emit the correct diagnostics, since -ffat-lto-objects requires -funified-lto +// RUN: %clang -cc1 -triple=x86_64-unknown-linux-gnu -flto -ffat-lto-objects -funified-lto -emit-llvm-only %s 2>&1 | FileCheck %s -check-prefix=UNIFIED --allow-empty +// UNIFIED-NOT: error: + +// RUN: not %clang -cc1 -triple=x86_64-unknown-linux-gnu -flto -ffat-lto-objects -emit-llvm-only %s 2>&1 | FileCheck %s -check-prefix=MISSING_UNIFIED +// MISSING_UNIFIED: error: invalid argument '-ffat-lto-objects' only allowed with '-funified-lto' + +// RUN: not %clang -cc1 -triple=x86_64-unknown-linux-gnu -flto -fno-unified-lto -ffat-lto-objects -emit-llvm-only %s 2>&1 | FileCheck %s -check-prefix=NO-UNIFIED +// NO-UNIFIED: error: the combination of '-ffat-lto-objects' and '-fno-unified-lto' is incompatible diff --git a/llvm/docs/FatLTO.rst b/llvm/docs/FatLTO.rst index b505bb2a96fe..21da24504bcd 100644 --- a/llvm/docs/FatLTO.rst +++ b/llvm/docs/FatLTO.rst @@ -29,30 +29,31 @@ Overview Within LLVM, FatLTO is supported by choosing the ``FatLTODefaultPipeline``. This pipeline will: -#) Clone the IR module. -#) Run the pre-link (Thin)LTO pipeline using the cloned module. +#) Run the pre-link UnifiedLTO pipeline on the current module. #) Embed the pre-link bitcode in a special ``.llvm.lto`` section. -#) Optimize the unmodified copy of the module using the normal compilation pipeline. +#) Finish optimizing the module using the post-link ThinLTO pipeline. #) Emit the object file, including the new ``.llvm.lto`` section. .. NOTE - At the time of writing, we conservatively run independent pipelines to - generate the bitcode section and the object code, which happen to be - identical to those used outside of FatLTO. This results in compiled - artifacts that are identical to those produced by the default and (Thin)LTO - pipelines. However, this is not a guarantee, and we reserve the right to - change this at any time. Explicitly, users should not rely on the produced - bitcode or object code to mach their non-LTO counterparts precisely. They - will exhibit similar performance characteristics, but may not be bit-for-bit - the same. + Previously, we conservatively ran independent pipelines on separate copies + of the LLVM module to generate the bitcode section and the object code, + which happen to be identical to those used outside of FatLTO. While that + resulted in compiled artifacts that were identical to those produced by the + default and (Thin)LTO pipelines, module cloning led to some cases of + miscompilation, and we have moved away from trying to keep bitcode + generation and optimization completely disjoint. + + Bit-for-bit compatibility is not (and never was) a guarantee, and we reserve + the right to change this at any time. Explicitly, users should not rely on + the produced bitcode or object code to match their non-LTO counterparts + precisely. They will exhibit similar performance characteristics, but may + not be bit-for-bit the same. Internally, the ``.llvm.lto`` section is created by running the -``EmbedBitcodePass`` at the start of the ``PerModuleDefaultPipeline``. This -pass is responsible for cloning and optimizing the module with the appropriate -LTO pipeline and emitting the ``.llvm.lto`` section. Afterwards, the -``PerModuleDefaultPipeline`` runs normally and the compiler can emit the fat -object file. +``EmbedBitcodePass`` after the ``ThinLTOPreLinkDefaultPipeline``. This pass is +responsible for emitting the ``.llvm.lto`` section. Afterwards, the +``ThinLTODefaultPipeline`` runs and the compiler can emit the fat object file. Limitations =========== diff --git a/llvm/include/llvm/Passes/PassBuilder.h b/llvm/include/llvm/Passes/PassBuilder.h index 23bc891a8f1e..19ac90842bcb 100644 --- a/llvm/include/llvm/Passes/PassBuilder.h +++ b/llvm/include/llvm/Passes/PassBuilder.h @@ -246,8 +246,7 @@ public: /// separately to avoid any inconsistencies with an ad-hoc pipeline that tries /// to approximate the PerModuleDefaultPipeline from the pre-link LTO /// pipelines. - ModulePassManager buildFatLTODefaultPipeline(OptimizationLevel Level, - bool ThinLTO, bool EmitSummary); + ModulePassManager buildFatLTODefaultPipeline(OptimizationLevel Level); /// Build a pre-link, ThinLTO-targeting default optimization pipeline to /// a pass manager. diff --git a/llvm/include/llvm/Transforms/IPO/EmbedBitcodePass.h b/llvm/include/llvm/Transforms/IPO/EmbedBitcodePass.h index f323c61483fd..c35048c91aba 100644 --- a/llvm/include/llvm/Transforms/IPO/EmbedBitcodePass.h +++ b/llvm/include/llvm/Transforms/IPO/EmbedBitcodePass.h @@ -25,28 +25,13 @@ class Module; class ModulePass; class Pass; -struct EmbedBitcodeOptions { - EmbedBitcodeOptions() : EmbedBitcodeOptions(false, false) {} - EmbedBitcodeOptions(bool IsThinLTO, bool EmitLTOSummary) - : IsThinLTO(IsThinLTO), EmitLTOSummary(EmitLTOSummary) {} - bool IsThinLTO; - bool EmitLTOSummary; -}; - /// Pass embeds a copy of the module optimized with the provided pass pipeline /// into a global variable. class EmbedBitcodePass : public PassInfoMixin { - bool IsThinLTO; - bool EmitLTOSummary; ModulePassManager MPM; public: - EmbedBitcodePass(EmbedBitcodeOptions Opts) - : EmbedBitcodePass(Opts.IsThinLTO, Opts.EmitLTOSummary, - ModulePassManager()) {} - EmbedBitcodePass(bool IsThinLTO, bool EmitLTOSummary, ModulePassManager &&MPM) - : IsThinLTO(IsThinLTO), EmitLTOSummary(EmitLTOSummary), - MPM(std::move(MPM)) {} + EmbedBitcodePass() {} PreservedAnalyses run(Module &M, ModuleAnalysisManager &); diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp index aeb9726a186b..98a679177c23 100644 --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -759,26 +759,6 @@ Expected parseHWASanPassOptions(StringRef Params) { return Result; } -Expected parseEmbedBitcodePassOptions(StringRef Params) { - EmbedBitcodeOptions Result; - while (!Params.empty()) { - StringRef ParamName; - std::tie(ParamName, Params) = Params.split(';'); - - if (ParamName == "thinlto") { - Result.IsThinLTO = true; - } else if (ParamName == "emit-summary") { - Result.EmitLTOSummary = true; - } else { - return make_error( - formatv("invalid EmbedBitcode pass parameter '{0}' ", ParamName) - .str(), - inconvertibleErrorCode()); - } - } - return Result; -} - Expected parseMSanPassOptions(StringRef Params) { MemorySanitizerOptions Result; while (!Params.empty()) { diff --git a/llvm/lib/Passes/PassBuilderPipelines.cpp b/llvm/lib/Passes/PassBuilderPipelines.cpp index f3d280316e04..e7f88680655c 100644 --- a/llvm/lib/Passes/PassBuilderPipelines.cpp +++ b/llvm/lib/Passes/PassBuilderPipelines.cpp @@ -1530,14 +1530,22 @@ PassBuilder::buildPerModuleDefaultPipeline(OptimizationLevel Level, } ModulePassManager -PassBuilder::buildFatLTODefaultPipeline(OptimizationLevel Level, bool ThinLTO, - bool EmitSummary) { +PassBuilder::buildFatLTODefaultPipeline(OptimizationLevel Level) { ModulePassManager MPM; - MPM.addPass(EmbedBitcodePass(ThinLTO, EmitSummary, - ThinLTO - ? buildThinLTOPreLinkDefaultPipeline(Level) - : buildLTOPreLinkDefaultPipeline(Level))); - MPM.addPass(buildPerModuleDefaultPipeline(Level)); + // FatLTO always uses UnifiedLTO, so use the ThinLTOPreLink pipeline + MPM.addPass(buildThinLTOPreLinkDefaultPipeline(Level)); + MPM.addPass(EmbedBitcodePass()); + + // Use the ThinLTO post-link pipeline with sample profiling, other + if (PGOOpt && PGOOpt->Action == PGOOptions::SampleUse) + MPM.addPass(buildThinLTODefaultPipeline(Level, /*ImportSummary=*/nullptr)); + else { + // otherwise, just use module optimization + MPM.addPass( + buildModuleOptimizationPipeline(Level, ThinOrFullLTOPhase::None)); + // Emit annotation remarks. + addAnnotationRemarksPass(MPM); + } return MPM; } diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def index 1f1bc3222468..2abc2920264a 100644 --- a/llvm/lib/Passes/PassRegistry.def +++ b/llvm/lib/Passes/PassRegistry.def @@ -58,6 +58,7 @@ MODULE_PASS("dfsan", DataFlowSanitizerPass()) MODULE_PASS("dot-callgraph", CallGraphDOTPrinterPass()) MODULE_PASS("dxil-upgrade", DXILUpgradePass()) MODULE_PASS("elim-avail-extern", EliminateAvailableExternallyPass()) +MODULE_PASS("embed-bitcode", EmbedBitcodePass()) MODULE_PASS("extract-blocks", BlockExtractorPass({}, false)) MODULE_PASS("forceattrs", ForceFunctionAttrsPass()) MODULE_PASS("function-import", FunctionImportPass()) @@ -145,10 +146,6 @@ MODULE_PASS_WITH_PARAMS( "asan", "AddressSanitizerPass", [](AddressSanitizerOptions Opts) { return AddressSanitizerPass(Opts); }, parseASanPassOptions, "kernel") -MODULE_PASS_WITH_PARAMS( - "embed-bitcode", "EmbedBitcodePass", - [](EmbedBitcodeOptions Opts) { return EmbedBitcodePass(Opts); }, - parseEmbedBitcodePassOptions, "thinlto;emit-summary") MODULE_PASS_WITH_PARAMS( "globaldce", "GlobalDCEPass", [](bool InLTOPostLink) { return GlobalDCEPass(InLTOPostLink); }, diff --git a/llvm/lib/Transforms/IPO/EmbedBitcodePass.cpp b/llvm/lib/Transforms/IPO/EmbedBitcodePass.cpp index fa56a5b564ae..48ef0772e800 100644 --- a/llvm/lib/Transforms/IPO/EmbedBitcodePass.cpp +++ b/llvm/lib/Transforms/IPO/EmbedBitcodePass.cpp @@ -7,8 +7,6 @@ //===----------------------------------------------------------------------===// #include "llvm/Transforms/IPO/EmbedBitcodePass.h" -#include "llvm/Bitcode/BitcodeWriter.h" -#include "llvm/Bitcode/BitcodeWriterPass.h" #include "llvm/IR/PassManager.h" #include "llvm/Pass.h" #include "llvm/Support/ErrorHandling.h" @@ -16,10 +14,8 @@ #include "llvm/Support/raw_ostream.h" #include "llvm/TargetParser/Triple.h" #include "llvm/Transforms/IPO/ThinLTOBitcodeWriter.h" -#include "llvm/Transforms/Utils/Cloning.h" #include "llvm/Transforms/Utils/ModuleUtils.h" -#include #include using namespace llvm; @@ -34,19 +30,9 @@ PreservedAnalyses EmbedBitcodePass::run(Module &M, ModuleAnalysisManager &AM) { report_fatal_error( "EmbedBitcode pass currently only supports ELF object format", /*gen_crash_diag=*/false); - - std::unique_ptr NewModule = CloneModule(M); - MPM.run(*NewModule, AM); - std::string Data; raw_string_ostream OS(Data); - if (IsThinLTO) - ThinLTOBitcodeWriterPass(OS, /*ThinLinkOS=*/nullptr).run(*NewModule, AM); - else - BitcodeWriterPass(OS, /*ShouldPreserveUseListOrder=*/false, EmitLTOSummary) - .run(*NewModule, AM); - + ThinLTOBitcodeWriterPass(OS, /*ThinLinkOS=*/nullptr).run(M, AM); embedBufferInModule(M, MemoryBufferRef(Data, "ModuleData"), ".llvm.lto"); - return PreservedAnalyses::all(); } diff --git a/llvm/test/CodeGen/X86/fat-lto-section.ll b/llvm/test/CodeGen/X86/fat-lto-section.ll index 30c56229a0e2..9a4359bab6b5 100644 --- a/llvm/test/CodeGen/X86/fat-lto-section.ll +++ b/llvm/test/CodeGen/X86/fat-lto-section.ll @@ -1,5 +1,5 @@ ;; Ensure that the .llvm.lto section has SHT_EXCLUDE set. -; RUN: opt --mtriple x86_64-unknown-linux-gnu < %s -passes="embed-bitcode" -S \ +; RUN: opt --mtriple x86_64-unknown-linux-gnu < %s -passes="embed-bitcode" -S \ ; RUN: | llc --mtriple x86_64-unknown-linux-gnu -filetype=obj \ ; RUN: | llvm-readelf - --sections \ ; RUN: | FileCheck %s --check-prefix=EXCLUDE diff --git a/llvm/test/Transforms/EmbedBitcode/embed.ll b/llvm/test/Transforms/EmbedBitcode/embed.ll index dffb5cf75547..734bf5274a5f 100644 --- a/llvm/test/Transforms/EmbedBitcode/embed.ll +++ b/llvm/test/Transforms/EmbedBitcode/embed.ll @@ -1,7 +1,4 @@ ; RUN: opt --mtriple x86_64-unknown-linux-gnu < %s -passes="embed-bitcode" -S | FileCheck %s -; RUN: opt --mtriple x86_64-unknown-linux-gnu < %s -passes="embed-bitcode" -S | FileCheck %s -; RUN: opt --mtriple x86_64-unknown-linux-gnu < %s -passes="embed-bitcode" -S | FileCheck %s -; RUN: opt --mtriple x86_64-unknown-linux-gnu < %s -passes="embed-bitcode" -S | FileCheck %s @a = global i32 1 -- GitLab From f2cbd1fdf702afe31d0198c9185e08dc2b104252 Mon Sep 17 00:00:00 2001 From: wanglei Date: Thu, 16 Nov 2023 20:05:01 +0800 Subject: [PATCH 078/699] [LoongArch] Add codegen support for insertelement --- .../LoongArch/LoongArchISelLowering.cpp | 82 +++++- .../Target/LoongArch/LoongArchISelLowering.h | 1 + .../LoongArch/LoongArchLASXInstrInfo.td | 18 ++ .../Target/LoongArch/LoongArchLSXInstrInfo.td | 5 + .../lasx/ir-instruction/insertelement.ll | 270 ++++++++++++++++++ .../lsx/ir-instruction/insertelement.ll | 196 +++++++++++++ 6 files changed, 570 insertions(+), 2 deletions(-) create mode 100644 llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insertelement.ll create mode 100644 llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insertelement.ll diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp index f59beca523cb..670620823440 100644 --- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp @@ -246,7 +246,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM, // FIXME: For BUILD_VECTOR, it is temporarily set to `Legal` here, and it // will be `Custom` handled in the future. setOperationAction(ISD::BUILD_VECTOR, VT, Legal); - setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Legal); + setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Legal); } for (MVT VT : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) { @@ -276,7 +276,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM, // FIXME: Same as above. setOperationAction(ISD::BUILD_VECTOR, VT, Legal); - setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Legal); + setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Legal); } for (MVT VT : {MVT::v4i64, MVT::v8i32, MVT::v16i16, MVT::v32i8}) { @@ -380,10 +380,20 @@ SDValue LoongArchTargetLowering::LowerOperation(SDValue Op, return lowerRETURNADDR(Op, DAG); case ISD::WRITE_REGISTER: return lowerWRITE_REGISTER(Op, DAG); + case ISD::INSERT_VECTOR_ELT: + return lowerINSERT_VECTOR_ELT(Op, DAG); } return SDValue(); } +SDValue +LoongArchTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op, + SelectionDAG &DAG) const { + if (isa(Op->getOperand(2))) + return Op; + return SDValue(); +} + SDValue LoongArchTargetLowering::lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const { SDLoc DL(Op); @@ -3067,6 +3077,71 @@ emitVecCondBranchPseudo(MachineInstr &MI, MachineBasicBlock *BB, return SinkBB; } +static MachineBasicBlock * +emitPseudoXVINSGR2VR(MachineInstr &MI, MachineBasicBlock *BB, + const LoongArchSubtarget &Subtarget) { + unsigned InsOp; + unsigned HalfSize; + switch (MI.getOpcode()) { + default: + llvm_unreachable("Unexpected opcode"); + case LoongArch::PseudoXVINSGR2VR_B: + HalfSize = 16; + InsOp = LoongArch::VINSGR2VR_B; + break; + case LoongArch::PseudoXVINSGR2VR_H: + HalfSize = 8; + InsOp = LoongArch::VINSGR2VR_H; + break; + } + const TargetInstrInfo *TII = Subtarget.getInstrInfo(); + const TargetRegisterClass *RC = &LoongArch::LASX256RegClass; + const TargetRegisterClass *SubRC = &LoongArch::LSX128RegClass; + DebugLoc DL = MI.getDebugLoc(); + MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); + // XDst = vector_insert XSrc, Elt, Idx + Register XDst = MI.getOperand(0).getReg(); + Register XSrc = MI.getOperand(1).getReg(); + Register Elt = MI.getOperand(2).getReg(); + unsigned Idx = MI.getOperand(3).getImm(); + + Register ScratchReg1 = XSrc; + if (Idx >= HalfSize) { + ScratchReg1 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII->get(LoongArch::XVPERMI_Q), ScratchReg1) + .addReg(XSrc) + .addReg(XSrc) + .addImm(1); + } + + Register ScratchSubReg1 = MRI.createVirtualRegister(SubRC); + Register ScratchSubReg2 = MRI.createVirtualRegister(SubRC); + BuildMI(*BB, MI, DL, TII->get(LoongArch::COPY), ScratchSubReg1) + .addReg(ScratchReg1, 0, LoongArch::sub_128); + BuildMI(*BB, MI, DL, TII->get(InsOp), ScratchSubReg2) + .addReg(ScratchSubReg1) + .addReg(Elt) + .addImm(Idx >= HalfSize ? Idx - HalfSize : Idx); + + Register ScratchReg2 = XDst; + if (Idx >= HalfSize) + ScratchReg2 = MRI.createVirtualRegister(RC); + + BuildMI(*BB, MI, DL, TII->get(LoongArch::SUBREG_TO_REG), ScratchReg2) + .addImm(0) + .addReg(ScratchSubReg2) + .addImm(LoongArch::sub_128); + + if (Idx >= HalfSize) + BuildMI(*BB, MI, DL, TII->get(LoongArch::XVPERMI_Q), XDst) + .addReg(XSrc) + .addReg(ScratchReg2) + .addImm(2); + + MI.eraseFromParent(); + return BB; +} + MachineBasicBlock *LoongArchTargetLowering::EmitInstrWithCustomInserter( MachineInstr &MI, MachineBasicBlock *BB) const { const TargetInstrInfo *TII = Subtarget.getInstrInfo(); @@ -3122,6 +3197,9 @@ MachineBasicBlock *LoongArchTargetLowering::EmitInstrWithCustomInserter( case LoongArch::PseudoXVBNZ_W: case LoongArch::PseudoXVBNZ_D: return emitVecCondBranchPseudo(MI, BB, Subtarget); + case LoongArch::PseudoXVINSGR2VR_B: + case LoongArch::PseudoXVINSGR2VR_H: + return emitPseudoXVINSGR2VR(MI, BB, Subtarget); } } diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h index 314128667105..aa63cf0acabb 100644 --- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h +++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h @@ -276,6 +276,7 @@ private: SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; SDValue lowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override; diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td index 380206ddcf10..475565db15c9 100644 --- a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td @@ -1065,6 +1065,13 @@ def PseudoXVBZ_W : VecCond; def PseudoXVBZ_D : VecCond; def PseudoXVBZ : VecCond; +let usesCustomInserter = 1, Constraints = "$xd = $dst" in { +def PseudoXVINSGR2VR_B + : Pseudo<(outs LASX256:$dst), (ins LASX256:$xd, GPR:$rj, uimm5:$imm)>; +def PseudoXVINSGR2VR_H + : Pseudo<(outs LASX256:$dst), (ins LASX256:$xd, GPR:$rj, uimm4:$imm)>; +} // usesCustomInserter = 1, Constraints = "$xd = $dst" + } // Predicates = [HasExtLASX] multiclass PatXr { @@ -1365,12 +1372,23 @@ def : Pat<(fma v8f32:$xj, v8f32:$xk, v8f32:$xa), def : Pat<(fma v4f64:$xj, v4f64:$xk, v4f64:$xa), (XVFMADD_D v4f64:$xj, v4f64:$xk, v4f64:$xa)>; +// PseudoXVINSGR2VR_{B/H} +def : Pat<(vector_insert v32i8:$xd, GRLenVT:$rj, uimm5:$imm), + (PseudoXVINSGR2VR_B v32i8:$xd, GRLenVT:$rj, uimm5:$imm)>; +def : Pat<(vector_insert v16i16:$xd, GRLenVT:$rj, uimm4:$imm), + (PseudoXVINSGR2VR_H v16i16:$xd, GRLenVT:$rj, uimm4:$imm)>; + // XVINSGR2VR_{W/D} def : Pat<(vector_insert v8i32:$xd, GRLenVT:$rj, uimm3:$imm), (XVINSGR2VR_W v8i32:$xd, GRLenVT:$rj, uimm3:$imm)>; def : Pat<(vector_insert v4i64:$xd, GRLenVT:$rj, uimm2:$imm), (XVINSGR2VR_D v4i64:$xd, GRLenVT:$rj, uimm2:$imm)>; +def : Pat<(vector_insert v8f32:$vd, FPR32:$fj, uimm3:$imm), + (XVINSGR2VR_W $vd, (COPY_TO_REGCLASS FPR32:$fj, GPR), uimm3:$imm)>; +def : Pat<(vector_insert v4f64:$vd, FPR64:$fj, uimm2:$imm), + (XVINSGR2VR_D $vd, (COPY_TO_REGCLASS FPR64:$fj, GPR), uimm2:$imm)>; + // XVPICKVE2GR_W[U] def : Pat<(loongarch_vpick_sext_elt v8i32:$xd, uimm3:$imm, i32), (XVPICKVE2GR_W v8i32:$xd, uimm3:$imm)>; diff --git a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td index 980870e34503..d8fd132a1c59 100644 --- a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td @@ -1462,6 +1462,11 @@ def : Pat<(vector_insert v4i32:$vd, GRLenVT:$rj, uimm2:$imm), def : Pat<(vector_insert v2i64:$vd, GRLenVT:$rj, uimm1:$imm), (VINSGR2VR_D v2i64:$vd, GRLenVT:$rj, uimm1:$imm)>; +def : Pat<(vector_insert v4f32:$vd, FPR32:$fj, uimm2:$imm), + (VINSGR2VR_W $vd, (COPY_TO_REGCLASS FPR32:$fj, GPR), uimm2:$imm)>; +def : Pat<(vector_insert v2f64:$vd, FPR64:$fj, uimm1:$imm), + (VINSGR2VR_D $vd, (COPY_TO_REGCLASS FPR64:$fj, GPR), uimm1:$imm)>; + // VPICKVE2GR_{B/H/W}[U] def : Pat<(loongarch_vpick_sext_elt v16i8:$vd, uimm4:$imm, i8), (VPICKVE2GR_B v16i8:$vd, uimm4:$imm)>; diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insertelement.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insertelement.ll new file mode 100644 index 000000000000..ceaf40027ffc --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insertelement.ll @@ -0,0 +1,270 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s + +define void @insert_32xi8(ptr %src, ptr %dst, i8 %in) nounwind { +; CHECK-LABEL: insert_32xi8: +; CHECK: # %bb.0: +; CHECK-NEXT: xvld $xr0, $a0, 0 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a2, 1 +; CHECK-NEXT: xvst $xr0, $a1, 0 +; CHECK-NEXT: ret + %v = load volatile <32 x i8>, ptr %src + %v_new = insertelement <32 x i8> %v, i8 %in, i32 1 + store <32 x i8> %v_new, ptr %dst + ret void +} + +define void @insert_32xi8_upper(ptr %src, ptr %dst, i8 %in) nounwind { +; CHECK-LABEL: insert_32xi8_upper: +; CHECK: # %bb.0: +; CHECK-NEXT: xvld $xr0, $a0, 0 +; CHECK-NEXT: xvori.b $xr1, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a2, 0 +; CHECK-NEXT: xvpermi.q $xr0, $xr1, 2 +; CHECK-NEXT: xvst $xr0, $a1, 0 +; CHECK-NEXT: ret + %v = load volatile <32 x i8>, ptr %src + %v_new = insertelement <32 x i8> %v, i8 %in, i32 16 + store <32 x i8> %v_new, ptr %dst + ret void +} + +define void @insert_16xi16(ptr %src, ptr %dst, i16 %in) nounwind { +; CHECK-LABEL: insert_16xi16: +; CHECK: # %bb.0: +; CHECK-NEXT: xvld $xr0, $a0, 0 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a2, 1 +; CHECK-NEXT: xvst $xr0, $a1, 0 +; CHECK-NEXT: ret + %v = load volatile <16 x i16>, ptr %src + %v_new = insertelement <16 x i16> %v, i16 %in, i32 1 + store <16 x i16> %v_new, ptr %dst + ret void +} + +define void @insert_16xi16_upper(ptr %src, ptr %dst, i16 %in) nounwind { +; CHECK-LABEL: insert_16xi16_upper: +; CHECK: # %bb.0: +; CHECK-NEXT: xvld $xr0, $a0, 0 +; CHECK-NEXT: xvori.b $xr1, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a2, 0 +; CHECK-NEXT: xvpermi.q $xr0, $xr1, 2 +; CHECK-NEXT: xvst $xr0, $a1, 0 +; CHECK-NEXT: ret + %v = load volatile <16 x i16>, ptr %src + %v_new = insertelement <16 x i16> %v, i16 %in, i32 8 + store <16 x i16> %v_new, ptr %dst + ret void +} + +define void @insert_8xi32(ptr %src, ptr %dst, i32 %in) nounwind { +; CHECK-LABEL: insert_8xi32: +; CHECK: # %bb.0: +; CHECK-NEXT: xvld $xr0, $a0, 0 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a2, 1 +; CHECK-NEXT: xvst $xr0, $a1, 0 +; CHECK-NEXT: ret + %v = load volatile <8 x i32>, ptr %src + %v_new = insertelement <8 x i32> %v, i32 %in, i32 1 + store <8 x i32> %v_new, ptr %dst + ret void +} + +define void @insert_4xi64(ptr %src, ptr %dst, i64 %in) nounwind { +; CHECK-LABEL: insert_4xi64: +; CHECK: # %bb.0: +; CHECK-NEXT: xvld $xr0, $a0, 0 +; CHECK-NEXT: xvinsgr2vr.d $xr0, $a2, 1 +; CHECK-NEXT: xvst $xr0, $a1, 0 +; CHECK-NEXT: ret + %v = load volatile <4 x i64>, ptr %src + %v_new = insertelement <4 x i64> %v, i64 %in, i32 1 + store <4 x i64> %v_new, ptr %dst + ret void +} + +define void @insert_8xfloat(ptr %src, ptr %dst, float %in) nounwind { +; CHECK-LABEL: insert_8xfloat: +; CHECK: # %bb.0: +; CHECK-NEXT: movfr2gr.s $a2, $fa0 +; CHECK-NEXT: xvld $xr0, $a0, 0 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a2, 1 +; CHECK-NEXT: xvst $xr0, $a1, 0 +; CHECK-NEXT: ret + %v = load volatile <8 x float>, ptr %src + %v_new = insertelement <8 x float> %v, float %in, i32 1 + store <8 x float> %v_new, ptr %dst + ret void +} + +define void @insert_4xdouble(ptr %src, ptr %dst, double %in) nounwind { +; CHECK-LABEL: insert_4xdouble: +; CHECK: # %bb.0: +; CHECK-NEXT: movfr2gr.d $a2, $fa0 +; CHECK-NEXT: xvld $xr0, $a0, 0 +; CHECK-NEXT: xvinsgr2vr.d $xr0, $a2, 1 +; CHECK-NEXT: xvst $xr0, $a1, 0 +; CHECK-NEXT: ret + %v = load volatile <4 x double>, ptr %src + %v_new = insertelement <4 x double> %v, double %in, i32 1 + store <4 x double> %v_new, ptr %dst + ret void +} + +define void @insert_32xi8_idx(ptr %src, ptr %dst, i8 %in, i32 %idx) nounwind { +; CHECK-LABEL: insert_32xi8_idx: +; CHECK: # %bb.0: +; CHECK-NEXT: addi.d $sp, $sp, -64 +; CHECK-NEXT: st.d $ra, $sp, 56 # 8-byte Folded Spill +; CHECK-NEXT: st.d $fp, $sp, 48 # 8-byte Folded Spill +; CHECK-NEXT: addi.d $fp, $sp, 64 +; CHECK-NEXT: bstrins.d $sp, $zero, 4, 0 +; CHECK-NEXT: xvld $xr0, $a0, 0 +; CHECK-NEXT: xvst $xr0, $sp, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a3, 4, 0 +; CHECK-NEXT: st.b $a2, $a0, 0 +; CHECK-NEXT: xvld $xr0, $sp, 0 +; CHECK-NEXT: xvst $xr0, $a1, 0 +; CHECK-NEXT: addi.d $sp, $fp, -64 +; CHECK-NEXT: ld.d $fp, $sp, 48 # 8-byte Folded Reload +; CHECK-NEXT: ld.d $ra, $sp, 56 # 8-byte Folded Reload +; CHECK-NEXT: addi.d $sp, $sp, 64 +; CHECK-NEXT: ret + %v = load volatile <32 x i8>, ptr %src + %v_new = insertelement <32 x i8> %v, i8 %in, i32 %idx + store <32 x i8> %v_new, ptr %dst + ret void +} + +define void @insert_16xi16_idx(ptr %src, ptr %dst, i16 %in, i32 %idx) nounwind { +; CHECK-LABEL: insert_16xi16_idx: +; CHECK: # %bb.0: +; CHECK-NEXT: addi.d $sp, $sp, -64 +; CHECK-NEXT: st.d $ra, $sp, 56 # 8-byte Folded Spill +; CHECK-NEXT: st.d $fp, $sp, 48 # 8-byte Folded Spill +; CHECK-NEXT: addi.d $fp, $sp, 64 +; CHECK-NEXT: bstrins.d $sp, $zero, 4, 0 +; CHECK-NEXT: xvld $xr0, $a0, 0 +; CHECK-NEXT: xvst $xr0, $sp, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a3, 4, 1 +; CHECK-NEXT: st.h $a2, $a0, 0 +; CHECK-NEXT: xvld $xr0, $sp, 0 +; CHECK-NEXT: xvst $xr0, $a1, 0 +; CHECK-NEXT: addi.d $sp, $fp, -64 +; CHECK-NEXT: ld.d $fp, $sp, 48 # 8-byte Folded Reload +; CHECK-NEXT: ld.d $ra, $sp, 56 # 8-byte Folded Reload +; CHECK-NEXT: addi.d $sp, $sp, 64 +; CHECK-NEXT: ret + %v = load volatile <16 x i16>, ptr %src + %v_new = insertelement <16 x i16> %v, i16 %in, i32 %idx + store <16 x i16> %v_new, ptr %dst + ret void +} + +define void @insert_8xi32_idx(ptr %src, ptr %dst, i32 %in, i32 %idx) nounwind { +; CHECK-LABEL: insert_8xi32_idx: +; CHECK: # %bb.0: +; CHECK-NEXT: addi.d $sp, $sp, -64 +; CHECK-NEXT: st.d $ra, $sp, 56 # 8-byte Folded Spill +; CHECK-NEXT: st.d $fp, $sp, 48 # 8-byte Folded Spill +; CHECK-NEXT: addi.d $fp, $sp, 64 +; CHECK-NEXT: bstrins.d $sp, $zero, 4, 0 +; CHECK-NEXT: xvld $xr0, $a0, 0 +; CHECK-NEXT: xvst $xr0, $sp, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a3, 4, 2 +; CHECK-NEXT: st.w $a2, $a0, 0 +; CHECK-NEXT: xvld $xr0, $sp, 0 +; CHECK-NEXT: xvst $xr0, $a1, 0 +; CHECK-NEXT: addi.d $sp, $fp, -64 +; CHECK-NEXT: ld.d $fp, $sp, 48 # 8-byte Folded Reload +; CHECK-NEXT: ld.d $ra, $sp, 56 # 8-byte Folded Reload +; CHECK-NEXT: addi.d $sp, $sp, 64 +; CHECK-NEXT: ret + %v = load volatile <8 x i32>, ptr %src + %v_new = insertelement <8 x i32> %v, i32 %in, i32 %idx + store <8 x i32> %v_new, ptr %dst + ret void +} + +define void @insert_4xi64_idx(ptr %src, ptr %dst, i64 %in, i32 %idx) nounwind { +; CHECK-LABEL: insert_4xi64_idx: +; CHECK: # %bb.0: +; CHECK-NEXT: addi.d $sp, $sp, -64 +; CHECK-NEXT: st.d $ra, $sp, 56 # 8-byte Folded Spill +; CHECK-NEXT: st.d $fp, $sp, 48 # 8-byte Folded Spill +; CHECK-NEXT: addi.d $fp, $sp, 64 +; CHECK-NEXT: bstrins.d $sp, $zero, 4, 0 +; CHECK-NEXT: xvld $xr0, $a0, 0 +; CHECK-NEXT: xvst $xr0, $sp, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a3, 4, 3 +; CHECK-NEXT: st.d $a2, $a0, 0 +; CHECK-NEXT: xvld $xr0, $sp, 0 +; CHECK-NEXT: xvst $xr0, $a1, 0 +; CHECK-NEXT: addi.d $sp, $fp, -64 +; CHECK-NEXT: ld.d $fp, $sp, 48 # 8-byte Folded Reload +; CHECK-NEXT: ld.d $ra, $sp, 56 # 8-byte Folded Reload +; CHECK-NEXT: addi.d $sp, $sp, 64 +; CHECK-NEXT: ret + %v = load volatile <4 x i64>, ptr %src + %v_new = insertelement <4 x i64> %v, i64 %in, i32 %idx + store <4 x i64> %v_new, ptr %dst + ret void +} + +define void @insert_8xfloat_idx(ptr %src, ptr %dst, float %in, i32 %idx) nounwind { +; CHECK-LABEL: insert_8xfloat_idx: +; CHECK: # %bb.0: +; CHECK-NEXT: addi.d $sp, $sp, -64 +; CHECK-NEXT: st.d $ra, $sp, 56 # 8-byte Folded Spill +; CHECK-NEXT: st.d $fp, $sp, 48 # 8-byte Folded Spill +; CHECK-NEXT: addi.d $fp, $sp, 64 +; CHECK-NEXT: bstrins.d $sp, $zero, 4, 0 +; CHECK-NEXT: xvld $xr1, $a0, 0 +; CHECK-NEXT: xvst $xr1, $sp, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a2, 4, 2 +; CHECK-NEXT: fst.s $fa0, $a0, 0 +; CHECK-NEXT: xvld $xr0, $sp, 0 +; CHECK-NEXT: xvst $xr0, $a1, 0 +; CHECK-NEXT: addi.d $sp, $fp, -64 +; CHECK-NEXT: ld.d $fp, $sp, 48 # 8-byte Folded Reload +; CHECK-NEXT: ld.d $ra, $sp, 56 # 8-byte Folded Reload +; CHECK-NEXT: addi.d $sp, $sp, 64 +; CHECK-NEXT: ret + %v = load volatile <8 x float>, ptr %src + %v_new = insertelement <8 x float> %v, float %in, i32 %idx + store <8 x float> %v_new, ptr %dst + ret void +} + +define void @insert_4xdouble_idx(ptr %src, ptr %dst, double %in, i32 %idx) nounwind { +; CHECK-LABEL: insert_4xdouble_idx: +; CHECK: # %bb.0: +; CHECK-NEXT: addi.d $sp, $sp, -64 +; CHECK-NEXT: st.d $ra, $sp, 56 # 8-byte Folded Spill +; CHECK-NEXT: st.d $fp, $sp, 48 # 8-byte Folded Spill +; CHECK-NEXT: addi.d $fp, $sp, 64 +; CHECK-NEXT: bstrins.d $sp, $zero, 4, 0 +; CHECK-NEXT: xvld $xr1, $a0, 0 +; CHECK-NEXT: xvst $xr1, $sp, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a2, 4, 3 +; CHECK-NEXT: fst.d $fa0, $a0, 0 +; CHECK-NEXT: xvld $xr0, $sp, 0 +; CHECK-NEXT: xvst $xr0, $a1, 0 +; CHECK-NEXT: addi.d $sp, $fp, -64 +; CHECK-NEXT: ld.d $fp, $sp, 48 # 8-byte Folded Reload +; CHECK-NEXT: ld.d $ra, $sp, 56 # 8-byte Folded Reload +; CHECK-NEXT: addi.d $sp, $sp, 64 +; CHECK-NEXT: ret + %v = load volatile <4 x double>, ptr %src + %v_new = insertelement <4 x double> %v, double %in, i32 %idx + store <4 x double> %v_new, ptr %dst + ret void +} diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insertelement.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insertelement.ll new file mode 100644 index 000000000000..a9834591aa0e --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insertelement.ll @@ -0,0 +1,196 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s + +define void @insert_16xi8(ptr %src, ptr %dst, i8 %ins) nounwind { +; CHECK-LABEL: insert_16xi8: +; CHECK: # %bb.0: +; CHECK-NEXT: vld $vr0, $a0, 0 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a2, 1 +; CHECK-NEXT: vst $vr0, $a1, 0 +; CHECK-NEXT: ret + %v = load volatile <16 x i8>, ptr %src + %v_new = insertelement <16 x i8> %v, i8 %ins, i32 1 + store <16 x i8> %v_new, ptr %dst + ret void +} + +define void @insert_8xi16(ptr %src, ptr %dst, i16 %ins) nounwind { +; CHECK-LABEL: insert_8xi16: +; CHECK: # %bb.0: +; CHECK-NEXT: vld $vr0, $a0, 0 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a2, 1 +; CHECK-NEXT: vst $vr0, $a1, 0 +; CHECK-NEXT: ret + %v = load volatile <8 x i16>, ptr %src + %v_new = insertelement <8 x i16> %v, i16 %ins, i32 1 + store <8 x i16> %v_new, ptr %dst + ret void +} + +define void @insert_4xi32(ptr %src, ptr %dst, i32 %ins) nounwind { +; CHECK-LABEL: insert_4xi32: +; CHECK: # %bb.0: +; CHECK-NEXT: vld $vr0, $a0, 0 +; CHECK-NEXT: vinsgr2vr.w $vr0, $a2, 1 +; CHECK-NEXT: vst $vr0, $a1, 0 +; CHECK-NEXT: ret + %v = load volatile <4 x i32>, ptr %src + %v_new = insertelement <4 x i32> %v, i32 %ins, i32 1 + store <4 x i32> %v_new, ptr %dst + ret void +} + +define void @insert_2xi64(ptr %src, ptr %dst, i64 %ins) nounwind { +; CHECK-LABEL: insert_2xi64: +; CHECK: # %bb.0: +; CHECK-NEXT: vld $vr0, $a0, 0 +; CHECK-NEXT: vinsgr2vr.d $vr0, $a2, 1 +; CHECK-NEXT: vst $vr0, $a1, 0 +; CHECK-NEXT: ret + %v = load volatile <2 x i64>, ptr %src + %v_new = insertelement <2 x i64> %v, i64 %ins, i32 1 + store <2 x i64> %v_new, ptr %dst + ret void +} + +define void @insert_4xfloat(ptr %src, ptr %dst, float %ins) nounwind { +; CHECK-LABEL: insert_4xfloat: +; CHECK: # %bb.0: +; CHECK-NEXT: movfr2gr.s $a2, $fa0 +; CHECK-NEXT: vld $vr0, $a0, 0 +; CHECK-NEXT: vinsgr2vr.w $vr0, $a2, 1 +; CHECK-NEXT: vst $vr0, $a1, 0 +; CHECK-NEXT: ret + %v = load volatile <4 x float>, ptr %src + %v_new = insertelement <4 x float> %v, float %ins, i32 1 + store <4 x float> %v_new, ptr %dst + ret void +} + +define void @insert_2xdouble(ptr %src, ptr %dst, double %ins) nounwind { +; CHECK-LABEL: insert_2xdouble: +; CHECK: # %bb.0: +; CHECK-NEXT: movfr2gr.d $a2, $fa0 +; CHECK-NEXT: vld $vr0, $a0, 0 +; CHECK-NEXT: vinsgr2vr.d $vr0, $a2, 1 +; CHECK-NEXT: vst $vr0, $a1, 0 +; CHECK-NEXT: ret + %v = load volatile <2 x double>, ptr %src + %v_new = insertelement <2 x double> %v, double %ins, i32 1 + store <2 x double> %v_new, ptr %dst + ret void +} + +define void @insert_16xi8_idx(ptr %src, ptr %dst, i8 %ins, i32 %idx) nounwind { +; CHECK-LABEL: insert_16xi8_idx: +; CHECK: # %bb.0: +; CHECK-NEXT: addi.d $sp, $sp, -16 +; CHECK-NEXT: vld $vr0, $a0, 0 +; CHECK-NEXT: vst $vr0, $sp, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a3, 3, 0 +; CHECK-NEXT: st.b $a2, $a0, 0 +; CHECK-NEXT: vld $vr0, $sp, 0 +; CHECK-NEXT: vst $vr0, $a1, 0 +; CHECK-NEXT: addi.d $sp, $sp, 16 +; CHECK-NEXT: ret + %v = load volatile <16 x i8>, ptr %src + %v_new = insertelement <16 x i8> %v, i8 %ins, i32 %idx + store <16 x i8> %v_new, ptr %dst + ret void +} + +define void @insert_8xi16_idx(ptr %src, ptr %dst, i16 %ins, i32 %idx) nounwind { +; CHECK-LABEL: insert_8xi16_idx: +; CHECK: # %bb.0: +; CHECK-NEXT: addi.d $sp, $sp, -16 +; CHECK-NEXT: vld $vr0, $a0, 0 +; CHECK-NEXT: vst $vr0, $sp, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a3, 3, 1 +; CHECK-NEXT: st.h $a2, $a0, 0 +; CHECK-NEXT: vld $vr0, $sp, 0 +; CHECK-NEXT: vst $vr0, $a1, 0 +; CHECK-NEXT: addi.d $sp, $sp, 16 +; CHECK-NEXT: ret + %v = load volatile <8 x i16>, ptr %src + %v_new = insertelement <8 x i16> %v, i16 %ins, i32 %idx + store <8 x i16> %v_new, ptr %dst + ret void +} + +define void @insert_4xi32_idx(ptr %src, ptr %dst, i32 %ins, i32 %idx) nounwind { +; CHECK-LABEL: insert_4xi32_idx: +; CHECK: # %bb.0: +; CHECK-NEXT: addi.d $sp, $sp, -16 +; CHECK-NEXT: vld $vr0, $a0, 0 +; CHECK-NEXT: vst $vr0, $sp, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a3, 3, 2 +; CHECK-NEXT: st.w $a2, $a0, 0 +; CHECK-NEXT: vld $vr0, $sp, 0 +; CHECK-NEXT: vst $vr0, $a1, 0 +; CHECK-NEXT: addi.d $sp, $sp, 16 +; CHECK-NEXT: ret + %v = load volatile <4 x i32>, ptr %src + %v_new = insertelement <4 x i32> %v, i32 %ins, i32 %idx + store <4 x i32> %v_new, ptr %dst + ret void +} + +define void @insert_2xi64_idx(ptr %src, ptr %dst, i64 %ins, i32 %idx) nounwind { +; CHECK-LABEL: insert_2xi64_idx: +; CHECK: # %bb.0: +; CHECK-NEXT: addi.d $sp, $sp, -16 +; CHECK-NEXT: vld $vr0, $a0, 0 +; CHECK-NEXT: vst $vr0, $sp, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a3, 3, 3 +; CHECK-NEXT: st.d $a2, $a0, 0 +; CHECK-NEXT: vld $vr0, $sp, 0 +; CHECK-NEXT: vst $vr0, $a1, 0 +; CHECK-NEXT: addi.d $sp, $sp, 16 +; CHECK-NEXT: ret + %v = load volatile <2 x i64>, ptr %src + %v_new = insertelement <2 x i64> %v, i64 %ins, i32 %idx + store <2 x i64> %v_new, ptr %dst + ret void +} + +define void @insert_4xfloat_idx(ptr %src, ptr %dst, float %ins, i32 %idx) nounwind { +; CHECK-LABEL: insert_4xfloat_idx: +; CHECK: # %bb.0: +; CHECK-NEXT: addi.d $sp, $sp, -16 +; CHECK-NEXT: vld $vr1, $a0, 0 +; CHECK-NEXT: vst $vr1, $sp, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a2, 3, 2 +; CHECK-NEXT: fst.s $fa0, $a0, 0 +; CHECK-NEXT: vld $vr0, $sp, 0 +; CHECK-NEXT: vst $vr0, $a1, 0 +; CHECK-NEXT: addi.d $sp, $sp, 16 +; CHECK-NEXT: ret + %v = load volatile <4 x float>, ptr %src + %v_new = insertelement <4 x float> %v, float %ins, i32 %idx + store <4 x float> %v_new, ptr %dst + ret void +} + +define void @insert_2xdouble_idx(ptr %src, ptr %dst, double %ins, i32 %idx) nounwind { +; CHECK-LABEL: insert_2xdouble_idx: +; CHECK: # %bb.0: +; CHECK-NEXT: addi.d $sp, $sp, -16 +; CHECK-NEXT: vld $vr1, $a0, 0 +; CHECK-NEXT: vst $vr1, $sp, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a2, 3, 3 +; CHECK-NEXT: fst.d $fa0, $a0, 0 +; CHECK-NEXT: vld $vr0, $sp, 0 +; CHECK-NEXT: vst $vr0, $a1, 0 +; CHECK-NEXT: addi.d $sp, $sp, 16 +; CHECK-NEXT: ret + %v = load volatile <2 x double>, ptr %src + %v_new = insertelement <2 x double> %v, double %ins, i32 %idx + store <2 x double> %v_new, ptr %dst + ret void +} -- GitLab From add224c0a094d20389d3659f7b6e496df461a976 Mon Sep 17 00:00:00 2001 From: wanglei Date: Wed, 25 Oct 2023 17:00:32 +0800 Subject: [PATCH 079/699] [LoongArch] Custom lowering `ISD::BUILD_VECTOR` --- .../LoongArch/LoongArchISelDAGToDAG.cpp | 52 +- .../LoongArch/LoongArchISelLowering.cpp | 102 +++- .../Target/LoongArch/LoongArchISelLowering.h | 1 + .../LoongArch/LoongArchLASXInstrInfo.td | 13 + .../Target/LoongArch/LoongArchLSXInstrInfo.td | 12 +- .../CodeGen/LoongArch/lasx/build-vector.ll | 551 ++++++++++++++++++ .../CodeGen/LoongArch/lsx/build-vector.ll | 376 ++++++++++++ .../LoongArch/lsx/ir-instruction/mul.ll | 28 +- 8 files changed, 1112 insertions(+), 23 deletions(-) create mode 100644 llvm/test/CodeGen/LoongArch/lasx/build-vector.ll create mode 100644 llvm/test/CodeGen/LoongArch/lsx/build-vector.ll diff --git a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp index 0cfee6025218..726856bda5dc 100644 --- a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp @@ -77,13 +77,63 @@ void LoongArchDAGToDAGISel::Select(SDNode *Node) { return; } case ISD::BITCAST: { - if (VT.is128BitVector() || VT.is512BitVector()) { + if (VT.is128BitVector() || VT.is256BitVector()) { ReplaceUses(SDValue(Node, 0), Node->getOperand(0)); CurDAG->RemoveDeadNode(Node); return; } break; } + case ISD::BUILD_VECTOR: { + // Select appropriate [x]vrepli.[bhwd] instructions for constant splats of + // 128/256-bit when LSX/LASX is enabled. + BuildVectorSDNode *BVN = cast(Node); + APInt SplatValue, SplatUndef; + unsigned SplatBitSize; + bool HasAnyUndefs; + unsigned Op; + EVT ViaVecTy; + bool Is128Vec = BVN->getValueType(0).is128BitVector(); + bool Is256Vec = BVN->getValueType(0).is256BitVector(); + + if (!Subtarget->hasExtLSX() || (!Is128Vec && !Is256Vec)) + break; + if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, + HasAnyUndefs, 8)) + break; + + switch (SplatBitSize) { + default: + break; + case 8: + Op = Is256Vec ? LoongArch::PseudoXVREPLI_B : LoongArch::PseudoVREPLI_B; + ViaVecTy = Is256Vec ? MVT::v32i8 : MVT::v16i8; + break; + case 16: + Op = Is256Vec ? LoongArch::PseudoXVREPLI_H : LoongArch::PseudoVREPLI_H; + ViaVecTy = Is256Vec ? MVT::v16i16 : MVT::v8i16; + break; + case 32: + Op = Is256Vec ? LoongArch::PseudoXVREPLI_W : LoongArch::PseudoVREPLI_W; + ViaVecTy = Is256Vec ? MVT::v8i32 : MVT::v4i32; + break; + case 64: + Op = Is256Vec ? LoongArch::PseudoXVREPLI_D : LoongArch::PseudoVREPLI_D; + ViaVecTy = Is256Vec ? MVT::v4i64 : MVT::v2i64; + break; + } + + SDNode *Res; + // If we have a signed 10 bit integer, we can splat it directly. + if (SplatValue.isSignedIntN(10)) { + SDValue Imm = CurDAG->getTargetConstant(SplatValue, DL, + ViaVecTy.getVectorElementType()); + Res = CurDAG->getMachineNode(Op, DL, ViaVecTy, Imm); + ReplaceNode(Node, Res); + return; + } + break; + } } // Select the default instruction. diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp index 670620823440..0a22f3c9930d 100644 --- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp @@ -243,11 +243,9 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM, setOperationAction(ISD::BITCAST, VT, Legal); setOperationAction(ISD::UNDEF, VT, Legal); - // FIXME: For BUILD_VECTOR, it is temporarily set to `Legal` here, and it - // will be `Custom` handled in the future. - setOperationAction(ISD::BUILD_VECTOR, VT, Legal); setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Legal); + setOperationAction(ISD::BUILD_VECTOR, VT, Custom); } for (MVT VT : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) { setOperationAction({ISD::ADD, ISD::SUB}, VT, Legal); @@ -274,10 +272,9 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM, setOperationAction(ISD::BITCAST, VT, Legal); setOperationAction(ISD::UNDEF, VT, Legal); - // FIXME: Same as above. - setOperationAction(ISD::BUILD_VECTOR, VT, Legal); setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Legal); + setOperationAction(ISD::BUILD_VECTOR, VT, Custom); } for (MVT VT : {MVT::v4i64, MVT::v8i32, MVT::v16i16, MVT::v32i8}) { setOperationAction({ISD::ADD, ISD::SUB}, VT, Legal); @@ -382,10 +379,105 @@ SDValue LoongArchTargetLowering::LowerOperation(SDValue Op, return lowerWRITE_REGISTER(Op, DAG); case ISD::INSERT_VECTOR_ELT: return lowerINSERT_VECTOR_ELT(Op, DAG); + case ISD::BUILD_VECTOR: + return lowerBUILD_VECTOR(Op, DAG); } return SDValue(); } +static bool isConstantOrUndef(const SDValue Op) { + if (Op->isUndef()) + return true; + if (isa(Op)) + return true; + if (isa(Op)) + return true; + return false; +} + +static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op) { + for (unsigned i = 0; i < Op->getNumOperands(); ++i) + if (isConstantOrUndef(Op->getOperand(i))) + return true; + return false; +} + +SDValue LoongArchTargetLowering::lowerBUILD_VECTOR(SDValue Op, + SelectionDAG &DAG) const { + BuildVectorSDNode *Node = cast(Op); + EVT ResTy = Op->getValueType(0); + SDLoc DL(Op); + APInt SplatValue, SplatUndef; + unsigned SplatBitSize; + bool HasAnyUndefs; + bool Is128Vec = ResTy.is128BitVector(); + bool Is256Vec = ResTy.is256BitVector(); + + if ((!Subtarget.hasExtLSX() || !Is128Vec) && + (!Subtarget.hasExtLASX() || !Is256Vec)) + return SDValue(); + + if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs, + /*MinSplatBits=*/8) && + SplatBitSize <= 64) { + // We can only cope with 8, 16, 32, or 64-bit elements. + if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 && + SplatBitSize != 64) + return SDValue(); + + EVT ViaVecTy; + + switch (SplatBitSize) { + default: + return SDValue(); + case 8: + ViaVecTy = Is128Vec ? MVT::v16i8 : MVT::v32i8; + break; + case 16: + ViaVecTy = Is128Vec ? MVT::v8i16 : MVT::v16i16; + break; + case 32: + ViaVecTy = Is128Vec ? MVT::v4i32 : MVT::v8i32; + break; + case 64: + ViaVecTy = Is128Vec ? MVT::v2i64 : MVT::v4i64; + break; + } + + // SelectionDAG::getConstant will promote SplatValue appropriately. + SDValue Result = DAG.getConstant(SplatValue, DL, ViaVecTy); + + // Bitcast to the type we originally wanted. + if (ViaVecTy != ResTy) + Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result); + + return Result; + } + + if (DAG.isSplatValue(Op, /*AllowUndefs=*/false)) + return Op; + + if (!isConstantOrUndefBUILD_VECTOR(Node)) { + // Use INSERT_VECTOR_ELT operations rather than expand to stores. + // The resulting code is the same length as the expansion, but it doesn't + // use memory operations. + EVT ResTy = Node->getValueType(0); + + assert(ResTy.isVector()); + + unsigned NumElts = ResTy.getVectorNumElements(); + SDValue Vector = DAG.getUNDEF(ResTy); + for (unsigned i = 0; i < NumElts; ++i) { + Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector, + Node->getOperand(i), + DAG.getConstant(i, DL, Subtarget.getGRLenVT())); + } + return Vector; + } + + return SDValue(); +} + SDValue LoongArchTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h index aa63cf0acabb..3a81c0e827af 100644 --- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h +++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h @@ -277,6 +277,7 @@ private: SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; SDValue lowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) const; SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override; diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td index 475565db15c9..4487152fb42b 100644 --- a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td @@ -33,6 +33,13 @@ def lasxsplati32 def lasxsplati64 : PatFrag<(ops node:$e0), (v4i64 (build_vector node:$e0, node:$e0, node:$e0, node:$e0))>; +def lasxsplatf32 + : PatFrag<(ops node:$e0), + (v8f32 (build_vector node:$e0, node:$e0, node:$e0, node:$e0, + node:$e0, node:$e0, node:$e0, node:$e0))>; +def lasxsplatf64 + : PatFrag<(ops node:$e0), + (v4f64 (build_vector node:$e0, node:$e0, node:$e0, node:$e0))>; //===----------------------------------------------------------------------===// // Instruction class templates @@ -1411,6 +1418,12 @@ def : Pat<(loongarch_vreplve v8i32:$xj, GRLenVT:$rk), def : Pat<(loongarch_vreplve v4i64:$xj, GRLenVT:$rk), (XVREPLVE_D v4i64:$xj, GRLenVT:$rk)>; +// XVREPL128VEI_{W/D} +def : Pat<(lasxsplatf32 FPR32:$fj), + (XVREPL128VEI_W (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32), 0)>; +def : Pat<(lasxsplatf64 FPR64:$fj), + (XVREPL128VEI_D (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), 0)>; + // Loads/Stores foreach vt = [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64] in { defm : LdPat; diff --git a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td index d8fd132a1c59..deac5015882d 100644 --- a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td @@ -141,9 +141,13 @@ def lsxsplati16 : PatFrag<(ops node:$e0), def lsxsplati32 : PatFrag<(ops node:$e0), (v4i32 (build_vector node:$e0, node:$e0, node:$e0, node:$e0))>; - def lsxsplati64 : PatFrag<(ops node:$e0), (v2i64 (build_vector node:$e0, node:$e0))>; +def lsxsplatf32 : PatFrag<(ops node:$e0), + (v4f32 (build_vector node:$e0, node:$e0, + node:$e0, node:$e0))>; +def lsxsplatf64 : PatFrag<(ops node:$e0), + (v2f64 (build_vector node:$e0, node:$e0))>; def to_valid_timm : SDNodeXForm(N); @@ -1498,6 +1502,12 @@ def : Pat<(loongarch_vreplve v4i32:$vj, GRLenVT:$rk), def : Pat<(loongarch_vreplve v2i64:$vj, GRLenVT:$rk), (VREPLVE_D v2i64:$vj, GRLenVT:$rk)>; +// VREPLVEI_{W/D} +def : Pat<(lsxsplatf32 FPR32:$fj), + (VREPLVEI_W (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32), 0)>; +def : Pat<(lsxsplatf64 FPR64:$fj), + (VREPLVEI_D (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), 0)>; + // Loads/Stores foreach vt = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in { defm : LdPat; diff --git a/llvm/test/CodeGen/LoongArch/lasx/build-vector.ll b/llvm/test/CodeGen/LoongArch/lasx/build-vector.ll new file mode 100644 index 000000000000..6824ab5cda8d --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lasx/build-vector.ll @@ -0,0 +1,551 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s + +define void @buildvector_v32i8_splat(ptr %dst, i8 %a0) nounwind { +; CHECK-LABEL: buildvector_v32i8_splat: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvreplgr2vr.b $xr0, $a1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %insert = insertelement <32 x i8> undef, i8 %a0, i8 0 + %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer + store <32 x i8> %splat, ptr %dst + ret void +} + +define void @buildvector_v16i16_splat(ptr %dst, i16 %a0) nounwind { +; CHECK-LABEL: buildvector_v16i16_splat: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvreplgr2vr.h $xr0, $a1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %insert = insertelement <16 x i16> undef, i16 %a0, i8 0 + %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer + store <16 x i16> %splat, ptr %dst + ret void +} + +define void @buildvector_v8i32_splat(ptr %dst, i32 %a0) nounwind { +; CHECK-LABEL: buildvector_v8i32_splat: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvreplgr2vr.w $xr0, $a1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %insert = insertelement <8 x i32> undef, i32 %a0, i8 0 + %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer + store <8 x i32> %splat, ptr %dst + ret void +} + +define void @buildvector_v4i64_splat(ptr %dst, i64 %a0) nounwind { +; CHECK-LABEL: buildvector_v4i64_splat: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvreplgr2vr.d $xr0, $a1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %insert = insertelement <4 x i64> undef, i64 %a0, i8 0 + %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer + store <4 x i64> %splat, ptr %dst + ret void +} + +define void @buildvector_v8f32_splat(ptr %dst, float %a0) nounwind { +; CHECK-LABEL: buildvector_v8f32_splat: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: # kill: def $f0 killed $f0 def $xr0 +; CHECK-NEXT: xvrepl128vei.w $xr0, $xr0, 0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %insert = insertelement <8 x float> undef, float %a0, i8 0 + %splat = shufflevector <8 x float> %insert, <8 x float> undef, <8 x i32> zeroinitializer + store <8 x float> %splat, ptr %dst + ret void +} + +define void @buildvector_v4f64_splat(ptr %dst, double %a0) nounwind { +; CHECK-LABEL: buildvector_v4f64_splat: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: # kill: def $f0_64 killed $f0_64 def $xr0 +; CHECK-NEXT: xvrepl128vei.d $xr0, $xr0, 0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %insert = insertelement <4 x double> undef, double %a0, i8 0 + %splat = shufflevector <4 x double> %insert, <4 x double> undef, <4 x i32> zeroinitializer + store <4 x double> %splat, ptr %dst + ret void +} + +define void @buildvector_v32i8_const_splat(ptr %dst) nounwind { +; CHECK-LABEL: buildvector_v32i8_const_splat: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvrepli.b $xr0, 1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + store <32 x i8> , ptr %dst + ret void +} + +define void @buildvector_v16i16_const_splat(ptr %dst) nounwind { +; CHECK-LABEL: buildvector_v16i16_const_splat: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvrepli.h $xr0, 1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + store <16 x i16> , ptr %dst + ret void +} + +define void @buildvector_v8i32_const_splat(ptr %dst) nounwind { +; CHECK-LABEL: buildvector_v8i32_const_splat: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvrepli.w $xr0, 1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + store <8 x i32> , ptr %dst + ret void +} + +define void @buildvector_v4i64_const_splat(ptr %dst) nounwind { +; CHECK-LABEL: buildvector_v4i64_const_splat: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvrepli.d $xr0, 1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + store <4 x i64> , ptr %dst + ret void +} + +define void @buildvector_v2f32_const_splat(ptr %dst) nounwind { +; CHECK-LABEL: buildvector_v2f32_const_splat: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lu12i.w $a1, 260096 +; CHECK-NEXT: xvreplgr2vr.w $xr0, $a1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + store <8 x float> , ptr %dst + ret void +} + +define void @buildvector_v4f64_const_splat(ptr %dst) nounwind { +; CHECK-LABEL: buildvector_v4f64_const_splat: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lu52i.d $a1, $zero, 1023 +; CHECK-NEXT: xvreplgr2vr.d $xr0, $a1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + store <4 x double> , ptr %dst + ret void +} + +define void @buildvector_v32i8_const(ptr %dst) nounwind { +; CHECK-LABEL: buildvector_v32i8_const: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI12_0) +; CHECK-NEXT: addi.d $a1, $a1, %pc_lo12(.LCPI12_0) +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + store <32 x i8> , ptr %dst + ret void +} + +define void @buildvector_v16i16_const(ptr %dst) nounwind { +; CHECK-LABEL: buildvector_v16i16_const: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI13_0) +; CHECK-NEXT: addi.d $a1, $a1, %pc_lo12(.LCPI13_0) +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + store <16 x i16> , ptr %dst + ret void +} + +define void @buildvector_v8i32_const(ptr %dst) nounwind { +; CHECK-LABEL: buildvector_v8i32_const: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI14_0) +; CHECK-NEXT: addi.d $a1, $a1, %pc_lo12(.LCPI14_0) +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + store <8 x i32> , ptr %dst + ret void +} + +define void @buildvector_v4i64_const(ptr %dst) nounwind { +; CHECK-LABEL: buildvector_v4i64_const: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI15_0) +; CHECK-NEXT: addi.d $a1, $a1, %pc_lo12(.LCPI15_0) +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + store <4 x i64> , ptr %dst + ret void +} + +define void @buildvector_v2f32_const(ptr %dst) nounwind { +; CHECK-LABEL: buildvector_v2f32_const: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI16_0) +; CHECK-NEXT: addi.d $a1, $a1, %pc_lo12(.LCPI16_0) +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + store <8 x float> , ptr %dst + ret void +} + +define void @buildvector_v4f64_const(ptr %dst) nounwind { +; CHECK-LABEL: buildvector_v4f64_const: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI17_0) +; CHECK-NEXT: addi.d $a1, $a1, %pc_lo12(.LCPI17_0) +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + store <4 x double> , ptr %dst + ret void +} + +define void @buildvector_v32i8(ptr %dst, i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4, i8 %a5, i8 %a6, i8 %a7, i8 %a8, i8 %a9, i8 %a10, i8 %a11, i8 %a12, i8 %a13, i8 %a14, i8 %a15, i8 %a16, i8 %a17, i8 %a18, i8 %a19, i8 %a20, i8 %a21, i8 %a22, i8 %a23, i8 %a24, i8 %a25, i8 %a26, i8 %a27, i8 %a28, i8 %a29, i8 %a30, i8 %a31) nounwind { +; CHECK-LABEL: buildvector_v32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 0 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a2, 1 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a3, 2 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a4, 3 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a5, 4 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a6, 5 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a7, 6 +; CHECK-NEXT: ld.b $a1, $sp, 0 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 7 +; CHECK-NEXT: ld.b $a1, $sp, 8 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 8 +; CHECK-NEXT: ld.b $a1, $sp, 16 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 9 +; CHECK-NEXT: ld.b $a1, $sp, 24 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 10 +; CHECK-NEXT: ld.b $a1, $sp, 32 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 11 +; CHECK-NEXT: ld.b $a1, $sp, 40 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 12 +; CHECK-NEXT: ld.b $a1, $sp, 48 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 13 +; CHECK-NEXT: ld.b $a1, $sp, 56 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 14 +; CHECK-NEXT: ld.b $a1, $sp, 64 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 15 +; CHECK-NEXT: ld.b $a1, $sp, 72 +; CHECK-NEXT: xvori.b $xr1, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 0 +; CHECK-NEXT: xvpermi.q $xr0, $xr1, 2 +; CHECK-NEXT: ld.b $a1, $sp, 80 +; CHECK-NEXT: xvori.b $xr1, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 1 +; CHECK-NEXT: xvpermi.q $xr0, $xr1, 2 +; CHECK-NEXT: ld.b $a1, $sp, 88 +; CHECK-NEXT: xvori.b $xr1, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 2 +; CHECK-NEXT: xvpermi.q $xr0, $xr1, 2 +; CHECK-NEXT: ld.b $a1, $sp, 96 +; CHECK-NEXT: xvori.b $xr1, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 3 +; CHECK-NEXT: xvpermi.q $xr0, $xr1, 2 +; CHECK-NEXT: ld.b $a1, $sp, 104 +; CHECK-NEXT: xvori.b $xr1, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 4 +; CHECK-NEXT: xvpermi.q $xr0, $xr1, 2 +; CHECK-NEXT: ld.b $a1, $sp, 112 +; CHECK-NEXT: xvori.b $xr1, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 5 +; CHECK-NEXT: xvpermi.q $xr0, $xr1, 2 +; CHECK-NEXT: ld.b $a1, $sp, 120 +; CHECK-NEXT: xvori.b $xr1, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 6 +; CHECK-NEXT: xvpermi.q $xr0, $xr1, 2 +; CHECK-NEXT: ld.b $a1, $sp, 128 +; CHECK-NEXT: xvori.b $xr1, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 7 +; CHECK-NEXT: xvpermi.q $xr0, $xr1, 2 +; CHECK-NEXT: ld.b $a1, $sp, 136 +; CHECK-NEXT: xvori.b $xr1, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 8 +; CHECK-NEXT: xvpermi.q $xr0, $xr1, 2 +; CHECK-NEXT: ld.b $a1, $sp, 144 +; CHECK-NEXT: xvori.b $xr1, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 9 +; CHECK-NEXT: xvpermi.q $xr0, $xr1, 2 +; CHECK-NEXT: ld.b $a1, $sp, 152 +; CHECK-NEXT: xvori.b $xr1, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 10 +; CHECK-NEXT: xvpermi.q $xr0, $xr1, 2 +; CHECK-NEXT: ld.b $a1, $sp, 160 +; CHECK-NEXT: xvori.b $xr1, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 11 +; CHECK-NEXT: xvpermi.q $xr0, $xr1, 2 +; CHECK-NEXT: ld.b $a1, $sp, 168 +; CHECK-NEXT: xvori.b $xr1, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 12 +; CHECK-NEXT: xvpermi.q $xr0, $xr1, 2 +; CHECK-NEXT: ld.b $a1, $sp, 176 +; CHECK-NEXT: xvori.b $xr1, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 13 +; CHECK-NEXT: xvpermi.q $xr0, $xr1, 2 +; CHECK-NEXT: ld.b $a1, $sp, 184 +; CHECK-NEXT: xvori.b $xr1, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 14 +; CHECK-NEXT: xvpermi.q $xr0, $xr1, 2 +; CHECK-NEXT: ld.b $a1, $sp, 192 +; CHECK-NEXT: xvori.b $xr1, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 15 +; CHECK-NEXT: xvpermi.q $xr0, $xr1, 2 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %ins0 = insertelement <32 x i8> undef, i8 %a0, i32 0 + %ins1 = insertelement <32 x i8> %ins0, i8 %a1, i32 1 + %ins2 = insertelement <32 x i8> %ins1, i8 %a2, i32 2 + %ins3 = insertelement <32 x i8> %ins2, i8 %a3, i32 3 + %ins4 = insertelement <32 x i8> %ins3, i8 %a4, i32 4 + %ins5 = insertelement <32 x i8> %ins4, i8 %a5, i32 5 + %ins6 = insertelement <32 x i8> %ins5, i8 %a6, i32 6 + %ins7 = insertelement <32 x i8> %ins6, i8 %a7, i32 7 + %ins8 = insertelement <32 x i8> %ins7, i8 %a8, i32 8 + %ins9 = insertelement <32 x i8> %ins8, i8 %a9, i32 9 + %ins10 = insertelement <32 x i8> %ins9, i8 %a10, i32 10 + %ins11 = insertelement <32 x i8> %ins10, i8 %a11, i32 11 + %ins12 = insertelement <32 x i8> %ins11, i8 %a12, i32 12 + %ins13 = insertelement <32 x i8> %ins12, i8 %a13, i32 13 + %ins14 = insertelement <32 x i8> %ins13, i8 %a14, i32 14 + %ins15 = insertelement <32 x i8> %ins14, i8 %a15, i32 15 + %ins16 = insertelement <32 x i8> %ins15, i8 %a16, i32 16 + %ins17 = insertelement <32 x i8> %ins16, i8 %a17, i32 17 + %ins18 = insertelement <32 x i8> %ins17, i8 %a18, i32 18 + %ins19 = insertelement <32 x i8> %ins18, i8 %a19, i32 19 + %ins20 = insertelement <32 x i8> %ins19, i8 %a20, i32 20 + %ins21 = insertelement <32 x i8> %ins20, i8 %a21, i32 21 + %ins22 = insertelement <32 x i8> %ins21, i8 %a22, i32 22 + %ins23 = insertelement <32 x i8> %ins22, i8 %a23, i32 23 + %ins24 = insertelement <32 x i8> %ins23, i8 %a24, i32 24 + %ins25 = insertelement <32 x i8> %ins24, i8 %a25, i32 25 + %ins26 = insertelement <32 x i8> %ins25, i8 %a26, i32 26 + %ins27 = insertelement <32 x i8> %ins26, i8 %a27, i32 27 + %ins28 = insertelement <32 x i8> %ins27, i8 %a28, i32 28 + %ins29 = insertelement <32 x i8> %ins28, i8 %a29, i32 29 + %ins30 = insertelement <32 x i8> %ins29, i8 %a30, i32 30 + %ins31 = insertelement <32 x i8> %ins30, i8 %a31, i32 31 + store <32 x i8> %ins31, ptr %dst + ret void +} + +define void @buildvector_v16i16(ptr %dst, i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7, i16 %a8, i16 %a9, i16 %a10, i16 %a11, i16 %a12, i16 %a13, i16 %a14, i16 %a15) nounwind { +; CHECK-LABEL: buildvector_v16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vinsgr2vr.h $vr0, $a1, 0 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a2, 1 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a3, 2 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a4, 3 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a5, 4 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a6, 5 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a7, 6 +; CHECK-NEXT: ld.h $a1, $sp, 0 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a1, 7 +; CHECK-NEXT: ld.h $a1, $sp, 8 +; CHECK-NEXT: xvori.b $xr1, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 0 +; CHECK-NEXT: xvpermi.q $xr0, $xr1, 2 +; CHECK-NEXT: ld.h $a1, $sp, 16 +; CHECK-NEXT: xvori.b $xr1, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 1 +; CHECK-NEXT: xvpermi.q $xr0, $xr1, 2 +; CHECK-NEXT: ld.h $a1, $sp, 24 +; CHECK-NEXT: xvori.b $xr1, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 2 +; CHECK-NEXT: xvpermi.q $xr0, $xr1, 2 +; CHECK-NEXT: ld.h $a1, $sp, 32 +; CHECK-NEXT: xvori.b $xr1, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 3 +; CHECK-NEXT: xvpermi.q $xr0, $xr1, 2 +; CHECK-NEXT: ld.h $a1, $sp, 40 +; CHECK-NEXT: xvori.b $xr1, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 4 +; CHECK-NEXT: xvpermi.q $xr0, $xr1, 2 +; CHECK-NEXT: ld.h $a1, $sp, 48 +; CHECK-NEXT: xvori.b $xr1, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 5 +; CHECK-NEXT: xvpermi.q $xr0, $xr1, 2 +; CHECK-NEXT: ld.h $a1, $sp, 56 +; CHECK-NEXT: xvori.b $xr1, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 6 +; CHECK-NEXT: xvpermi.q $xr0, $xr1, 2 +; CHECK-NEXT: ld.h $a1, $sp, 64 +; CHECK-NEXT: xvori.b $xr1, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 7 +; CHECK-NEXT: xvpermi.q $xr0, $xr1, 2 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %ins0 = insertelement <16 x i16> undef, i16 %a0, i32 0 + %ins1 = insertelement <16 x i16> %ins0, i16 %a1, i32 1 + %ins2 = insertelement <16 x i16> %ins1, i16 %a2, i32 2 + %ins3 = insertelement <16 x i16> %ins2, i16 %a3, i32 3 + %ins4 = insertelement <16 x i16> %ins3, i16 %a4, i32 4 + %ins5 = insertelement <16 x i16> %ins4, i16 %a5, i32 5 + %ins6 = insertelement <16 x i16> %ins5, i16 %a6, i32 6 + %ins7 = insertelement <16 x i16> %ins6, i16 %a7, i32 7 + %ins8 = insertelement <16 x i16> %ins7, i16 %a8, i32 8 + %ins9 = insertelement <16 x i16> %ins8, i16 %a9, i32 9 + %ins10 = insertelement <16 x i16> %ins9, i16 %a10, i32 10 + %ins11 = insertelement <16 x i16> %ins10, i16 %a11, i32 11 + %ins12 = insertelement <16 x i16> %ins11, i16 %a12, i32 12 + %ins13 = insertelement <16 x i16> %ins12, i16 %a13, i32 13 + %ins14 = insertelement <16 x i16> %ins13, i16 %a14, i32 14 + %ins15 = insertelement <16 x i16> %ins14, i16 %a15, i32 15 + store <16 x i16> %ins15, ptr %dst + ret void +} + +define void @buildvector_v8i32(ptr %dst, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7) nounwind { +; CHECK-LABEL: buildvector_v8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a1, 0 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a2, 1 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a3, 2 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a4, 3 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a5, 4 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a6, 5 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a7, 6 +; CHECK-NEXT: ld.w $a1, $sp, 0 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a1, 7 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %ins0 = insertelement <8 x i32> undef, i32 %a0, i32 0 + %ins1 = insertelement <8 x i32> %ins0, i32 %a1, i32 1 + %ins2 = insertelement <8 x i32> %ins1, i32 %a2, i32 2 + %ins3 = insertelement <8 x i32> %ins2, i32 %a3, i32 3 + %ins4 = insertelement <8 x i32> %ins3, i32 %a4, i32 4 + %ins5 = insertelement <8 x i32> %ins4, i32 %a5, i32 5 + %ins6 = insertelement <8 x i32> %ins5, i32 %a6, i32 6 + %ins7 = insertelement <8 x i32> %ins6, i32 %a7, i32 7 + store <8 x i32> %ins7, ptr %dst + ret void +} + +define void @buildvector_v4i64(ptr %dst, i64 %a0, i64 %a1, i64 %a2, i64 %a3) nounwind { +; CHECK-LABEL: buildvector_v4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvinsgr2vr.d $xr0, $a1, 0 +; CHECK-NEXT: xvinsgr2vr.d $xr0, $a2, 1 +; CHECK-NEXT: xvinsgr2vr.d $xr0, $a3, 2 +; CHECK-NEXT: xvinsgr2vr.d $xr0, $a4, 3 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %ins0 = insertelement <4 x i64> undef, i64 %a0, i32 0 + %ins1 = insertelement <4 x i64> %ins0, i64 %a1, i32 1 + %ins2 = insertelement <4 x i64> %ins1, i64 %a2, i32 2 + %ins3 = insertelement <4 x i64> %ins2, i64 %a3, i32 3 + store <4 x i64> %ins3, ptr %dst + ret void +} + +define void @buildvector_v8f32(ptr %dst, float %a0, float %a1, float %a2, float %a3, float %a4, float %a5, float %a6, float %a7) nounwind { +; CHECK-LABEL: buildvector_v8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: movfr2gr.s $a1, $fa0 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a1, 0 +; CHECK-NEXT: movfr2gr.s $a1, $fa1 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a1, 1 +; CHECK-NEXT: movfr2gr.s $a1, $fa2 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a1, 2 +; CHECK-NEXT: movfr2gr.s $a1, $fa3 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a1, 3 +; CHECK-NEXT: movfr2gr.s $a1, $fa4 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a1, 4 +; CHECK-NEXT: movfr2gr.s $a1, $fa5 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a1, 5 +; CHECK-NEXT: movfr2gr.s $a1, $fa6 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a1, 6 +; CHECK-NEXT: movfr2gr.s $a1, $fa7 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a1, 7 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %ins0 = insertelement <8 x float> undef, float %a0, i32 0 + %ins1 = insertelement <8 x float> %ins0, float %a1, i32 1 + %ins2 = insertelement <8 x float> %ins1, float %a2, i32 2 + %ins3 = insertelement <8 x float> %ins2, float %a3, i32 3 + %ins4 = insertelement <8 x float> %ins3, float %a4, i32 4 + %ins5 = insertelement <8 x float> %ins4, float %a5, i32 5 + %ins6 = insertelement <8 x float> %ins5, float %a6, i32 6 + %ins7 = insertelement <8 x float> %ins6, float %a7, i32 7 + store <8 x float> %ins7, ptr %dst + ret void +} + +define void @buildvector_v4f64(ptr %dst, double %a0, double %a1, double %a2, double %a3) nounwind { +; CHECK-LABEL: buildvector_v4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: movfr2gr.d $a1, $fa0 +; CHECK-NEXT: xvinsgr2vr.d $xr0, $a1, 0 +; CHECK-NEXT: movfr2gr.d $a1, $fa1 +; CHECK-NEXT: xvinsgr2vr.d $xr0, $a1, 1 +; CHECK-NEXT: movfr2gr.d $a1, $fa2 +; CHECK-NEXT: xvinsgr2vr.d $xr0, $a1, 2 +; CHECK-NEXT: movfr2gr.d $a1, $fa3 +; CHECK-NEXT: xvinsgr2vr.d $xr0, $a1, 3 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %ins0 = insertelement <4 x double> undef, double %a0, i32 0 + %ins1 = insertelement <4 x double> %ins0, double %a1, i32 1 + %ins2 = insertelement <4 x double> %ins1, double %a2, i32 2 + %ins3 = insertelement <4 x double> %ins2, double %a3, i32 3 + store <4 x double> %ins3, ptr %dst + ret void +} diff --git a/llvm/test/CodeGen/LoongArch/lsx/build-vector.ll b/llvm/test/CodeGen/LoongArch/lsx/build-vector.ll new file mode 100644 index 000000000000..3a74db5e1acb --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lsx/build-vector.ll @@ -0,0 +1,376 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s + +define void @buildvector_v16i8_splat(ptr %dst, i8 %a0) nounwind { +; CHECK-LABEL: buildvector_v16i8_splat: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vreplgr2vr.b $vr0, $a1 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %insert = insertelement <16 x i8> undef, i8 %a0, i8 0 + %splat = shufflevector <16 x i8> %insert, <16 x i8> undef, <16 x i32> zeroinitializer + store <16 x i8> %splat, ptr %dst + ret void +} + +define void @buildvector_v8i16_splat(ptr %dst, i16 %a0) nounwind { +; CHECK-LABEL: buildvector_v8i16_splat: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vreplgr2vr.h $vr0, $a1 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %insert = insertelement <8 x i16> undef, i16 %a0, i8 0 + %splat = shufflevector <8 x i16> %insert, <8 x i16> undef, <8 x i32> zeroinitializer + store <8 x i16> %splat, ptr %dst + ret void +} + +define void @buildvector_v4i32_splat(ptr %dst, i32 %a0) nounwind { +; CHECK-LABEL: buildvector_v4i32_splat: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vreplgr2vr.w $vr0, $a1 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %insert = insertelement <4 x i32> undef, i32 %a0, i8 0 + %splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer + store <4 x i32> %splat, ptr %dst + ret void +} + +define void @buildvector_v2i64_splat(ptr %dst, i64 %a0) nounwind { +; CHECK-LABEL: buildvector_v2i64_splat: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vreplgr2vr.d $vr0, $a1 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %insert = insertelement <2 x i64> undef, i64 %a0, i8 0 + %splat = shufflevector <2 x i64> %insert, <2 x i64> undef, <2 x i32> zeroinitializer + store <2 x i64> %splat, ptr %dst + ret void +} + +define void @buildvector_v4f32_splat(ptr %dst, float %a0) nounwind { +; CHECK-LABEL: buildvector_v4f32_splat: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: # kill: def $f0 killed $f0 def $vr0 +; CHECK-NEXT: vreplvei.w $vr0, $vr0, 0 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %insert = insertelement <4 x float> undef, float %a0, i8 0 + %splat = shufflevector <4 x float> %insert, <4 x float> undef, <4 x i32> zeroinitializer + store <4 x float> %splat, ptr %dst + ret void +} + +define void @buildvector_v2f64_splat(ptr %dst, double %a0) nounwind { +; CHECK-LABEL: buildvector_v2f64_splat: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: # kill: def $f0_64 killed $f0_64 def $vr0 +; CHECK-NEXT: vreplvei.d $vr0, $vr0, 0 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %insert = insertelement <2 x double> undef, double %a0, i8 0 + %splat = shufflevector <2 x double> %insert, <2 x double> undef, <2 x i32> zeroinitializer + store <2 x double> %splat, ptr %dst + ret void +} + +define void @buildvector_v16i8_const_splat(ptr %dst) nounwind { +; CHECK-LABEL: buildvector_v16i8_const_splat: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vrepli.b $vr0, 1 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + store <16 x i8> , ptr %dst + ret void +} + +define void @buildvector_v8i16_const_splat(ptr %dst) nounwind { +; CHECK-LABEL: buildvector_v8i16_const_splat: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vrepli.h $vr0, 1 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + store <8 x i16> , ptr %dst + ret void +} + +define void @buildvector_v4i32_const_splat(ptr %dst) nounwind { +; CHECK-LABEL: buildvector_v4i32_const_splat: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vrepli.w $vr0, 1 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + store <4 x i32> , ptr %dst + ret void +} + +define void @buildvector_v2i64_const_splat(ptr %dst) nounwind { +; CHECK-LABEL: buildvector_v2i64_const_splat: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vrepli.d $vr0, 1 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + store <2 x i64> , ptr %dst + ret void +} + +define void @buildvector_v2f32_const_splat(ptr %dst) nounwind { +; CHECK-LABEL: buildvector_v2f32_const_splat: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lu12i.w $a1, 260096 +; CHECK-NEXT: vreplgr2vr.w $vr0, $a1 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + store <4 x float> , ptr %dst + ret void +} + +define void @buildvector_v2f64_const_splat(ptr %dst) nounwind { +; CHECK-LABEL: buildvector_v2f64_const_splat: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lu52i.d $a1, $zero, 1023 +; CHECK-NEXT: vreplgr2vr.d $vr0, $a1 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + store <2 x double> , ptr %dst + ret void +} + +define void @buildvector_v16i8_const(ptr %dst) nounwind { +; CHECK-LABEL: buildvector_v16i8_const: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI12_0) +; CHECK-NEXT: addi.d $a1, $a1, %pc_lo12(.LCPI12_0) +; CHECK-NEXT: vld $vr0, $a1, 0 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + store <16 x i8> , ptr %dst + ret void +} + +define void @buildvector_v8i16_const(ptr %dst) nounwind { +; CHECK-LABEL: buildvector_v8i16_const: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI13_0) +; CHECK-NEXT: addi.d $a1, $a1, %pc_lo12(.LCPI13_0) +; CHECK-NEXT: vld $vr0, $a1, 0 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + store <8 x i16> , ptr %dst + ret void +} + +define void @buildvector_v4i32_const(ptr %dst) nounwind { +; CHECK-LABEL: buildvector_v4i32_const: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI14_0) +; CHECK-NEXT: addi.d $a1, $a1, %pc_lo12(.LCPI14_0) +; CHECK-NEXT: vld $vr0, $a1, 0 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + store <4 x i32> , ptr %dst + ret void +} + +define void @buildvector_v2i64_const(ptr %dst) nounwind { +; CHECK-LABEL: buildvector_v2i64_const: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI15_0) +; CHECK-NEXT: addi.d $a1, $a1, %pc_lo12(.LCPI15_0) +; CHECK-NEXT: vld $vr0, $a1, 0 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + store <2 x i64> , ptr %dst + ret void +} + +define void @buildvector_v2f32_const(ptr %dst) nounwind { +; CHECK-LABEL: buildvector_v2f32_const: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI16_0) +; CHECK-NEXT: addi.d $a1, $a1, %pc_lo12(.LCPI16_0) +; CHECK-NEXT: vld $vr0, $a1, 0 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + store <4 x float> , ptr %dst + ret void +} + +define void @buildvector_v2f64_const(ptr %dst) nounwind { +; CHECK-LABEL: buildvector_v2f64_const: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI17_0) +; CHECK-NEXT: addi.d $a1, $a1, %pc_lo12(.LCPI17_0) +; CHECK-NEXT: vld $vr0, $a1, 0 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + store <2 x double> , ptr %dst + ret void +} + +define void @buildvector_v16i8(ptr %dst, i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4, i8 %a5, i8 %a6, i8 %a7, i8 %a8, i8 %a9, i8 %a10, i8 %a11, i8 %a12, i8 %a13, i8 %a14, i8 %a15) nounwind { +; CHECK-LABEL: buildvector_v16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 0 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a2, 1 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a3, 2 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a4, 3 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a5, 4 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a6, 5 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a7, 6 +; CHECK-NEXT: ld.b $a1, $sp, 0 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 7 +; CHECK-NEXT: ld.b $a1, $sp, 8 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 8 +; CHECK-NEXT: ld.b $a1, $sp, 16 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 9 +; CHECK-NEXT: ld.b $a1, $sp, 24 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 10 +; CHECK-NEXT: ld.b $a1, $sp, 32 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 11 +; CHECK-NEXT: ld.b $a1, $sp, 40 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 12 +; CHECK-NEXT: ld.b $a1, $sp, 48 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 13 +; CHECK-NEXT: ld.b $a1, $sp, 56 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 14 +; CHECK-NEXT: ld.b $a1, $sp, 64 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 15 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %ins0 = insertelement <16 x i8> undef, i8 %a0, i32 0 + %ins1 = insertelement <16 x i8> %ins0, i8 %a1, i32 1 + %ins2 = insertelement <16 x i8> %ins1, i8 %a2, i32 2 + %ins3 = insertelement <16 x i8> %ins2, i8 %a3, i32 3 + %ins4 = insertelement <16 x i8> %ins3, i8 %a4, i32 4 + %ins5 = insertelement <16 x i8> %ins4, i8 %a5, i32 5 + %ins6 = insertelement <16 x i8> %ins5, i8 %a6, i32 6 + %ins7 = insertelement <16 x i8> %ins6, i8 %a7, i32 7 + %ins8 = insertelement <16 x i8> %ins7, i8 %a8, i32 8 + %ins9 = insertelement <16 x i8> %ins8, i8 %a9, i32 9 + %ins10 = insertelement <16 x i8> %ins9, i8 %a10, i32 10 + %ins11 = insertelement <16 x i8> %ins10, i8 %a11, i32 11 + %ins12 = insertelement <16 x i8> %ins11, i8 %a12, i32 12 + %ins13 = insertelement <16 x i8> %ins12, i8 %a13, i32 13 + %ins14 = insertelement <16 x i8> %ins13, i8 %a14, i32 14 + %ins15 = insertelement <16 x i8> %ins14, i8 %a15, i32 15 + store <16 x i8> %ins15, ptr %dst + ret void +} + +define void @buildvector_v8i16(ptr %dst, i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7) nounwind { +; CHECK-LABEL: buildvector_v8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vinsgr2vr.h $vr0, $a1, 0 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a2, 1 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a3, 2 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a4, 3 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a5, 4 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a6, 5 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a7, 6 +; CHECK-NEXT: ld.h $a1, $sp, 0 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a1, 7 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %ins0 = insertelement <8 x i16> undef, i16 %a0, i32 0 + %ins1 = insertelement <8 x i16> %ins0, i16 %a1, i32 1 + %ins2 = insertelement <8 x i16> %ins1, i16 %a2, i32 2 + %ins3 = insertelement <8 x i16> %ins2, i16 %a3, i32 3 + %ins4 = insertelement <8 x i16> %ins3, i16 %a4, i32 4 + %ins5 = insertelement <8 x i16> %ins4, i16 %a5, i32 5 + %ins6 = insertelement <8 x i16> %ins5, i16 %a6, i32 6 + %ins7 = insertelement <8 x i16> %ins6, i16 %a7, i32 7 + store <8 x i16> %ins7, ptr %dst + ret void +} + +define void @buildvector_v4i32(ptr %dst, i32 %a0, i32 %a1, i32 %a2, i32 %a3) nounwind { +; CHECK-LABEL: buildvector_v4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vinsgr2vr.w $vr0, $a1, 0 +; CHECK-NEXT: vinsgr2vr.w $vr0, $a2, 1 +; CHECK-NEXT: vinsgr2vr.w $vr0, $a3, 2 +; CHECK-NEXT: vinsgr2vr.w $vr0, $a4, 3 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %ins0 = insertelement <4 x i32> undef, i32 %a0, i32 0 + %ins1 = insertelement <4 x i32> %ins0, i32 %a1, i32 1 + %ins2 = insertelement <4 x i32> %ins1, i32 %a2, i32 2 + %ins3 = insertelement <4 x i32> %ins2, i32 %a3, i32 3 + store <4 x i32> %ins3, ptr %dst + ret void +} + +define void @buildvector_v2i64(ptr %dst, i64 %a0, i64 %a1) nounwind { +; CHECK-LABEL: buildvector_v2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vinsgr2vr.d $vr0, $a1, 0 +; CHECK-NEXT: vinsgr2vr.d $vr0, $a2, 1 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %ins0 = insertelement <2 x i64> undef, i64 %a0, i32 0 + %ins1 = insertelement <2 x i64> %ins0, i64 %a1, i32 1 + store <2 x i64> %ins1, ptr %dst + ret void +} + +define void @buildvector_v4f32(ptr %dst, float %a0, float %a1, float %a2, float %a3) nounwind { +; CHECK-LABEL: buildvector_v4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: movfr2gr.s $a1, $fa0 +; CHECK-NEXT: vinsgr2vr.w $vr0, $a1, 0 +; CHECK-NEXT: movfr2gr.s $a1, $fa1 +; CHECK-NEXT: vinsgr2vr.w $vr0, $a1, 1 +; CHECK-NEXT: movfr2gr.s $a1, $fa2 +; CHECK-NEXT: vinsgr2vr.w $vr0, $a1, 2 +; CHECK-NEXT: movfr2gr.s $a1, $fa3 +; CHECK-NEXT: vinsgr2vr.w $vr0, $a1, 3 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %ins0 = insertelement <4 x float> undef, float %a0, i32 0 + %ins1 = insertelement <4 x float> %ins0, float %a1, i32 1 + %ins2 = insertelement <4 x float> %ins1, float %a2, i32 2 + %ins3 = insertelement <4 x float> %ins2, float %a3, i32 3 + store <4 x float> %ins3, ptr %dst + ret void +} + +define void @buildvector_v2f64(ptr %dst, double %a0, double %a1) nounwind { +; CHECK-LABEL: buildvector_v2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: movfr2gr.d $a1, $fa0 +; CHECK-NEXT: vinsgr2vr.d $vr0, $a1, 0 +; CHECK-NEXT: movfr2gr.d $a1, $fa1 +; CHECK-NEXT: vinsgr2vr.d $vr0, $a1, 1 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %ins0 = insertelement <2 x double> undef, double %a0, i32 0 + %ins1 = insertelement <2 x double> %ins0, double %a1, i32 1 + store <2 x double> %ins1, ptr %dst + ret void +} diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/mul.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/mul.ll index 5060240cd8b1..d0be9cb7e3c8 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/mul.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/mul.ll @@ -180,10 +180,9 @@ entry: define void @mul_v16i8_17(ptr %res, ptr %a0) nounwind { ; CHECK-LABEL: mul_v16i8_17: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: ori $a2, $zero, 17 -; CHECK-NEXT: vreplgr2vr.b $vr0, $a2 -; CHECK-NEXT: vld $vr1, $a1, 0 -; CHECK-NEXT: vmul.b $vr0, $vr1, $vr0 +; CHECK-NEXT: vld $vr0, $a1, 0 +; CHECK-NEXT: vrepli.b $vr1, 17 +; CHECK-NEXT: vmul.b $vr0, $vr0, $vr1 ; CHECK-NEXT: vst $vr0, $a0, 0 ; CHECK-NEXT: ret entry: @@ -196,10 +195,9 @@ entry: define void @mul_v8i16_17(ptr %res, ptr %a0) nounwind { ; CHECK-LABEL: mul_v8i16_17: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: ori $a2, $zero, 17 -; CHECK-NEXT: vreplgr2vr.h $vr0, $a2 -; CHECK-NEXT: vld $vr1, $a1, 0 -; CHECK-NEXT: vmul.h $vr0, $vr1, $vr0 +; CHECK-NEXT: vld $vr0, $a1, 0 +; CHECK-NEXT: vrepli.h $vr1, 17 +; CHECK-NEXT: vmul.h $vr0, $vr0, $vr1 ; CHECK-NEXT: vst $vr0, $a0, 0 ; CHECK-NEXT: ret entry: @@ -212,10 +210,9 @@ entry: define void @mul_v4i32_17(ptr %res, ptr %a0) nounwind { ; CHECK-LABEL: mul_v4i32_17: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: ori $a2, $zero, 17 -; CHECK-NEXT: vreplgr2vr.w $vr0, $a2 -; CHECK-NEXT: vld $vr1, $a1, 0 -; CHECK-NEXT: vmul.w $vr0, $vr1, $vr0 +; CHECK-NEXT: vld $vr0, $a1, 0 +; CHECK-NEXT: vrepli.w $vr1, 17 +; CHECK-NEXT: vmul.w $vr0, $vr0, $vr1 ; CHECK-NEXT: vst $vr0, $a0, 0 ; CHECK-NEXT: ret entry: @@ -228,10 +225,9 @@ entry: define void @mul_v2i64_17(ptr %res, ptr %a0) nounwind { ; CHECK-LABEL: mul_v2i64_17: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: ori $a2, $zero, 17 -; CHECK-NEXT: vreplgr2vr.d $vr0, $a2 -; CHECK-NEXT: vld $vr1, $a1, 0 -; CHECK-NEXT: vmul.d $vr0, $vr1, $vr0 +; CHECK-NEXT: vld $vr0, $a1, 0 +; CHECK-NEXT: vrepli.d $vr1, 17 +; CHECK-NEXT: vmul.d $vr0, $vr0, $vr1 ; CHECK-NEXT: vst $vr0, $a0, 0 ; CHECK-NEXT: ret entry: -- GitLab From 668a4a238045e7f300b771f7e4cfa723d8bde237 Mon Sep 17 00:00:00 2001 From: Brad Smith Date: Thu, 30 Nov 2023 20:19:36 -0500 Subject: [PATCH 080/699] [lldb] pipe2(2) is also supported by OpenBSD (#74012) --- lldb/source/Host/posix/PipePosix.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lldb/source/Host/posix/PipePosix.cpp b/lldb/source/Host/posix/PipePosix.cpp index c02869cbf4d7..6fc4646953b4 100644 --- a/lldb/source/Host/posix/PipePosix.cpp +++ b/lldb/source/Host/posix/PipePosix.cpp @@ -32,7 +32,7 @@ enum PIPES { READ, WRITE }; // Constants 0 and 1 for READ and WRITE // pipe2 is supported by a limited set of platforms // TODO: Add more platforms that support pipe2. #if defined(__linux__) || (defined(__FreeBSD__) && __FreeBSD__ >= 10) || \ - defined(__NetBSD__) + defined(__NetBSD__) || defined(__OpenBSD__) #define PIPE2_SUPPORTED 1 #else #define PIPE2_SUPPORTED 0 -- GitLab From 8123fd961ceca20966744f43a562ccd9c1139913 Mon Sep 17 00:00:00 2001 From: Valery Pykhtin Date: Fri, 1 Dec 2023 02:35:01 +0100 Subject: [PATCH 081/699] [ASAN][AMDGPU] NFC. Improve instrumentation tests. (#73919) * Added 128 bit wide operation tests (fast path check). * Added test for recovery mode. Upcoming patch https://github.com/llvm/llvm-project/pull/72247. --- .../asan_instrument_constant_address_space.ll | 74 ++++++- .../asan_instrument_generic_address_space.ll | 187 ++++++++++++++++++ .../asan_instrument_global_address_space.ll | 131 ++++++++++++ 3 files changed, 390 insertions(+), 2 deletions(-) diff --git a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_constant_address_space.ll b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_constant_address_space.ll index 911e8021a736..47b289ba32b8 100644 --- a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_constant_address_space.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_constant_address_space.ll @@ -1,9 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3 ; RUN: opt < %s -passes=asan -S | FileCheck %s +; RUN: opt < %s -passes=asan -asan-recover -S | FileCheck %s --check-prefix=RECOV target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8" target triple = "amdgcn-amd-amdhsa" @x = addrspace(4) global [2 x i32] zeroinitializer, align 4 +@x8 = addrspace(4) global [2 x i64] zeroinitializer, align 8 define protected amdgpu_kernel void @constant_load(i64 %i) sanitize_address { ; CHECK-LABEL: define protected amdgpu_kernel void @constant_load( @@ -16,7 +18,7 @@ define protected amdgpu_kernel void @constant_load(i64 %i) sanitize_address { ; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr ; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0 -; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP12:%.*]], !prof [[PROF1:![0-9]+]] +; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP12:%.*]], !prof [[PROF2:![0-9]+]] ; CHECK: 6: ; CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP0]], 7 ; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP7]], 3 @@ -30,9 +32,77 @@ define protected amdgpu_kernel void @constant_load(i64 %i) sanitize_address { ; CHECK-NEXT: [[Q:%.*]] = load i32, ptr addrspace(4) [[A]], align 4 ; CHECK-NEXT: ret void ; +; RECOV-LABEL: define protected amdgpu_kernel void @constant_load( +; RECOV-SAME: i64 [[I:%.*]]) #[[ATTR0:[0-9]+]] { +; RECOV-NEXT: entry: +; RECOV-NEXT: [[A:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(4) @x, i64 0, i64 [[I]] +; RECOV-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(4) [[A]] to i64 +; RECOV-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3 +; RECOV-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880 +; RECOV-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr +; RECOV-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1 +; RECOV-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0 +; RECOV-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP13:%.*]], !prof [[PROF2:![0-9]+]] +; RECOV: 6: +; RECOV-NEXT: [[TMP7:%.*]] = and i64 [[TMP0]], 7 +; RECOV-NEXT: [[TMP8:%.*]] = add i64 [[TMP7]], 3 +; RECOV-NEXT: [[TMP9:%.*]] = trunc i64 [[TMP8]] to i8 +; RECOV-NEXT: [[TMP10:%.*]] = icmp sge i8 [[TMP9]], [[TMP4]] +; RECOV-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP12:%.*]] +; RECOV: 11: +; RECOV-NEXT: call void @__asan_report_load4_noabort(i64 [[TMP0]]) #[[ATTR3:[0-9]+]] +; RECOV-NEXT: br label [[TMP12]] +; RECOV: 12: +; RECOV-NEXT: br label [[TMP13]] +; RECOV: 13: +; RECOV-NEXT: [[Q:%.*]] = load i32, ptr addrspace(4) [[A]], align 4 +; RECOV-NEXT: ret void +; entry: - %a = getelementptr inbounds [2 x i32], ptr addrspace(4) @x, i64 0, i64 %i %q = load i32, ptr addrspace(4) %a, align 4 ret void } + +define protected amdgpu_kernel void @constant_load_8(i64 %i) sanitize_address { +; CHECK-LABEL: define protected amdgpu_kernel void @constant_load_8( +; CHECK-SAME: i64 [[I:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[A:%.*]] = getelementptr inbounds [2 x i64], ptr addrspace(4) @x8, i64 0, i64 [[I]] +; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(4) [[A]] to i64 +; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3 +; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880 +; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr +; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1 +; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0 +; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP7:%.*]] +; CHECK: 6: +; CHECK-NEXT: call void @__asan_report_load8(i64 [[TMP0]]) #[[ATTR3]] +; CHECK-NEXT: unreachable +; CHECK: 7: +; CHECK-NEXT: [[Q:%.*]] = load i64, ptr addrspace(4) [[A]], align 8 +; CHECK-NEXT: ret void +; +; RECOV-LABEL: define protected amdgpu_kernel void @constant_load_8( +; RECOV-SAME: i64 [[I:%.*]]) #[[ATTR0]] { +; RECOV-NEXT: entry: +; RECOV-NEXT: [[A:%.*]] = getelementptr inbounds [2 x i64], ptr addrspace(4) @x8, i64 0, i64 [[I]] +; RECOV-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(4) [[A]] to i64 +; RECOV-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3 +; RECOV-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880 +; RECOV-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr +; RECOV-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1 +; RECOV-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0 +; RECOV-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP7:%.*]] +; RECOV: 6: +; RECOV-NEXT: call void @__asan_report_load8_noabort(i64 [[TMP0]]) #[[ATTR3]] +; RECOV-NEXT: br label [[TMP7]] +; RECOV: 7: +; RECOV-NEXT: [[Q:%.*]] = load i64, ptr addrspace(4) [[A]], align 8 +; RECOV-NEXT: ret void +; +entry: + %a = getelementptr inbounds [2 x i64], ptr addrspace(4) @x8, i64 0, i64 %i + %q = load i64, ptr addrspace(4) %a, align 8 + ret void +} diff --git a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_generic_address_space.ll b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_generic_address_space.ll index 34b7f04592e2..58af1eafa180 100644 --- a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_generic_address_space.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_generic_address_space.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3 ; RUN: opt < %s -passes=asan -S | FileCheck %s +; RUN: opt < %s -passes=asan -asan-recover -S | FileCheck %s --check-prefix=RECOV target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8" target triple = "amdgcn-amd-amdhsa" @@ -36,6 +37,40 @@ define protected amdgpu_kernel void @generic_store(ptr addrspace(1) %p, i32 %i) ; CHECK-NEXT: store i32 0, ptr [[Q]], align 4 ; CHECK-NEXT: ret void ; +; RECOV-LABEL: define protected amdgpu_kernel void @generic_store( +; RECOV-SAME: ptr addrspace(1) [[P:%.*]], i32 [[I:%.*]]) #[[ATTR0:[0-9]+]] { +; RECOV-NEXT: entry: +; RECOV-NEXT: [[Q:%.*]] = addrspacecast ptr addrspace(1) [[P]] to ptr +; RECOV-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[Q]]) +; RECOV-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[Q]]) +; RECOV-NEXT: [[TMP2:%.*]] = or i1 [[TMP0]], [[TMP1]] +; RECOV-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true +; RECOV-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP19:%.*]] +; RECOV: 4: +; RECOV-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[Q]] to i64 +; RECOV-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 3 +; RECOV-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 2147450880 +; RECOV-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr +; RECOV-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1 +; RECOV-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP9]], 0 +; RECOV-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP18:%.*]], !prof [[PROF0:![0-9]+]] +; RECOV: 11: +; RECOV-NEXT: [[TMP12:%.*]] = and i64 [[TMP5]], 7 +; RECOV-NEXT: [[TMP13:%.*]] = add i64 [[TMP12]], 3 +; RECOV-NEXT: [[TMP14:%.*]] = trunc i64 [[TMP13]] to i8 +; RECOV-NEXT: [[TMP15:%.*]] = icmp sge i8 [[TMP14]], [[TMP9]] +; RECOV-NEXT: br i1 [[TMP15]], label [[TMP16:%.*]], label [[TMP17:%.*]] +; RECOV: 16: +; RECOV-NEXT: call void @__asan_report_store4_noabort(i64 [[TMP5]]) #[[ATTR3:[0-9]+]] +; RECOV-NEXT: br label [[TMP17]] +; RECOV: 17: +; RECOV-NEXT: br label [[TMP18]] +; RECOV: 18: +; RECOV-NEXT: br label [[TMP19]] +; RECOV: 19: +; RECOV-NEXT: store i32 0, ptr [[Q]], align 4 +; RECOV-NEXT: ret void +; entry: %q = addrspacecast ptr addrspace(1) %p to ptr @@ -76,9 +111,161 @@ define protected amdgpu_kernel void @generic_load(ptr addrspace(1) %p, i32 %i) s ; CHECK-NEXT: [[R:%.*]] = load i32, ptr [[Q]], align 4 ; CHECK-NEXT: ret void ; +; RECOV-LABEL: define protected amdgpu_kernel void @generic_load( +; RECOV-SAME: ptr addrspace(1) [[P:%.*]], i32 [[I:%.*]]) #[[ATTR0]] { +; RECOV-NEXT: entry: +; RECOV-NEXT: [[Q:%.*]] = addrspacecast ptr addrspace(1) [[P]] to ptr +; RECOV-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[Q]]) +; RECOV-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[Q]]) +; RECOV-NEXT: [[TMP2:%.*]] = or i1 [[TMP0]], [[TMP1]] +; RECOV-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true +; RECOV-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP19:%.*]] +; RECOV: 4: +; RECOV-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[Q]] to i64 +; RECOV-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 3 +; RECOV-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 2147450880 +; RECOV-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr +; RECOV-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1 +; RECOV-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP9]], 0 +; RECOV-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP18:%.*]], !prof [[PROF0]] +; RECOV: 11: +; RECOV-NEXT: [[TMP12:%.*]] = and i64 [[TMP5]], 7 +; RECOV-NEXT: [[TMP13:%.*]] = add i64 [[TMP12]], 3 +; RECOV-NEXT: [[TMP14:%.*]] = trunc i64 [[TMP13]] to i8 +; RECOV-NEXT: [[TMP15:%.*]] = icmp sge i8 [[TMP14]], [[TMP9]] +; RECOV-NEXT: br i1 [[TMP15]], label [[TMP16:%.*]], label [[TMP17:%.*]] +; RECOV: 16: +; RECOV-NEXT: call void @__asan_report_load4_noabort(i64 [[TMP5]]) #[[ATTR3]] +; RECOV-NEXT: br label [[TMP17]] +; RECOV: 17: +; RECOV-NEXT: br label [[TMP18]] +; RECOV: 18: +; RECOV-NEXT: br label [[TMP19]] +; RECOV: 19: +; RECOV-NEXT: [[R:%.*]] = load i32, ptr [[Q]], align 4 +; RECOV-NEXT: ret void +; entry: %q = addrspacecast ptr addrspace(1) %p to ptr %r = load i32, ptr %q, align 4 ret void } + +define protected amdgpu_kernel void @generic_store_8(ptr addrspace(1) %p) sanitize_address { +; CHECK-LABEL: define protected amdgpu_kernel void @generic_store_8( +; CHECK-SAME: ptr addrspace(1) [[P:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[Q:%.*]] = addrspacecast ptr addrspace(1) [[P]] to ptr +; CHECK-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[Q]]) +; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[Q]]) +; CHECK-NEXT: [[TMP2:%.*]] = or i1 [[TMP0]], [[TMP1]] +; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true +; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP13:%.*]] +; CHECK: 4: +; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[Q]] to i64 +; CHECK-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 3 +; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 2147450880 +; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr +; CHECK-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1 +; CHECK-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP9]], 0 +; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP12:%.*]] +; CHECK: 11: +; CHECK-NEXT: call void @__asan_report_store8(i64 [[TMP5]]) #[[ATTR3]] +; CHECK-NEXT: unreachable +; CHECK: 12: +; CHECK-NEXT: br label [[TMP13]] +; CHECK: 13: +; CHECK-NEXT: store i64 0, ptr [[Q]], align 8 +; CHECK-NEXT: ret void +; +; RECOV-LABEL: define protected amdgpu_kernel void @generic_store_8( +; RECOV-SAME: ptr addrspace(1) [[P:%.*]]) #[[ATTR0]] { +; RECOV-NEXT: entry: +; RECOV-NEXT: [[Q:%.*]] = addrspacecast ptr addrspace(1) [[P]] to ptr +; RECOV-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[Q]]) +; RECOV-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[Q]]) +; RECOV-NEXT: [[TMP2:%.*]] = or i1 [[TMP0]], [[TMP1]] +; RECOV-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true +; RECOV-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP13:%.*]] +; RECOV: 4: +; RECOV-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[Q]] to i64 +; RECOV-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 3 +; RECOV-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 2147450880 +; RECOV-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr +; RECOV-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1 +; RECOV-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP9]], 0 +; RECOV-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP12:%.*]] +; RECOV: 11: +; RECOV-NEXT: call void @__asan_report_store8_noabort(i64 [[TMP5]]) #[[ATTR3]] +; RECOV-NEXT: br label [[TMP12]] +; RECOV: 12: +; RECOV-NEXT: br label [[TMP13]] +; RECOV: 13: +; RECOV-NEXT: store i64 0, ptr [[Q]], align 8 +; RECOV-NEXT: ret void +; +entry: + %q = addrspacecast ptr addrspace(1) %p to ptr + store i64 0, ptr %q, align 8 + ret void +} + +define protected amdgpu_kernel void @generic_load_8(ptr addrspace(1) %p) sanitize_address { +; CHECK-LABEL: define protected amdgpu_kernel void @generic_load_8( +; CHECK-SAME: ptr addrspace(1) [[P:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[Q:%.*]] = addrspacecast ptr addrspace(1) [[P]] to ptr +; CHECK-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[Q]]) +; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[Q]]) +; CHECK-NEXT: [[TMP2:%.*]] = or i1 [[TMP0]], [[TMP1]] +; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true +; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP13:%.*]] +; CHECK: 4: +; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[Q]] to i64 +; CHECK-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 3 +; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 2147450880 +; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr +; CHECK-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1 +; CHECK-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP9]], 0 +; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP12:%.*]] +; CHECK: 11: +; CHECK-NEXT: call void @__asan_report_load8(i64 [[TMP5]]) #[[ATTR3]] +; CHECK-NEXT: unreachable +; CHECK: 12: +; CHECK-NEXT: br label [[TMP13]] +; CHECK: 13: +; CHECK-NEXT: [[R:%.*]] = load i64, ptr [[Q]], align 8 +; CHECK-NEXT: ret void +; +; RECOV-LABEL: define protected amdgpu_kernel void @generic_load_8( +; RECOV-SAME: ptr addrspace(1) [[P:%.*]]) #[[ATTR0]] { +; RECOV-NEXT: entry: +; RECOV-NEXT: [[Q:%.*]] = addrspacecast ptr addrspace(1) [[P]] to ptr +; RECOV-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[Q]]) +; RECOV-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[Q]]) +; RECOV-NEXT: [[TMP2:%.*]] = or i1 [[TMP0]], [[TMP1]] +; RECOV-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true +; RECOV-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP13:%.*]] +; RECOV: 4: +; RECOV-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[Q]] to i64 +; RECOV-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 3 +; RECOV-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 2147450880 +; RECOV-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr +; RECOV-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1 +; RECOV-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP9]], 0 +; RECOV-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP12:%.*]] +; RECOV: 11: +; RECOV-NEXT: call void @__asan_report_load8_noabort(i64 [[TMP5]]) #[[ATTR3]] +; RECOV-NEXT: br label [[TMP12]] +; RECOV: 12: +; RECOV-NEXT: br label [[TMP13]] +; RECOV: 13: +; RECOV-NEXT: [[R:%.*]] = load i64, ptr [[Q]], align 8 +; RECOV-NEXT: ret void +; +entry: + %q = addrspacecast ptr addrspace(1) %p to ptr + %r = load i64, ptr %q, align 8 + ret void +} diff --git a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_global_address_space.ll b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_global_address_space.ll index d8708e744835..e792c453a723 100644 --- a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_global_address_space.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_global_address_space.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3 ; RUN: opt < %s -passes=asan -S | FileCheck %s +; RUN: opt < %s -passes=asan -asan-recover -S | FileCheck %s --check-prefix=RECOV target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8" target triple = "amdgcn-amd-amdhsa" @@ -27,6 +28,31 @@ define protected amdgpu_kernel void @global_store(ptr addrspace(1) %p, i32 %i) s ; CHECK-NEXT: store i32 0, ptr addrspace(1) [[P]], align 4 ; CHECK-NEXT: ret void ; +; RECOV-LABEL: define protected amdgpu_kernel void @global_store( +; RECOV-SAME: ptr addrspace(1) [[P:%.*]], i32 [[I:%.*]]) #[[ATTR0:[0-9]+]] { +; RECOV-NEXT: entry: +; RECOV-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(1) [[P]] to i64 +; RECOV-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3 +; RECOV-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880 +; RECOV-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr +; RECOV-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1 +; RECOV-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0 +; RECOV-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP13:%.*]], !prof [[PROF0:![0-9]+]] +; RECOV: 6: +; RECOV-NEXT: [[TMP7:%.*]] = and i64 [[TMP0]], 7 +; RECOV-NEXT: [[TMP8:%.*]] = add i64 [[TMP7]], 3 +; RECOV-NEXT: [[TMP9:%.*]] = trunc i64 [[TMP8]] to i8 +; RECOV-NEXT: [[TMP10:%.*]] = icmp sge i8 [[TMP9]], [[TMP4]] +; RECOV-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP12:%.*]] +; RECOV: 11: +; RECOV-NEXT: call void @__asan_report_store4_noabort(i64 [[TMP0]]) #[[ATTR3:[0-9]+]] +; RECOV-NEXT: br label [[TMP12]] +; RECOV: 12: +; RECOV-NEXT: br label [[TMP13]] +; RECOV: 13: +; RECOV-NEXT: store i32 0, ptr addrspace(1) [[P]], align 4 +; RECOV-NEXT: ret void +; entry: store i32 0, ptr addrspace(1) %p, align 4 @@ -57,8 +83,113 @@ define protected amdgpu_kernel void @global_load(ptr addrspace(1) %p, i32 %i) sa ; CHECK-NEXT: [[Q:%.*]] = load i32, ptr addrspace(1) [[P]], align 4 ; CHECK-NEXT: ret void ; +; RECOV-LABEL: define protected amdgpu_kernel void @global_load( +; RECOV-SAME: ptr addrspace(1) [[P:%.*]], i32 [[I:%.*]]) #[[ATTR0]] { +; RECOV-NEXT: entry: +; RECOV-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(1) [[P]] to i64 +; RECOV-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3 +; RECOV-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880 +; RECOV-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr +; RECOV-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1 +; RECOV-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0 +; RECOV-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP13:%.*]], !prof [[PROF0]] +; RECOV: 6: +; RECOV-NEXT: [[TMP7:%.*]] = and i64 [[TMP0]], 7 +; RECOV-NEXT: [[TMP8:%.*]] = add i64 [[TMP7]], 3 +; RECOV-NEXT: [[TMP9:%.*]] = trunc i64 [[TMP8]] to i8 +; RECOV-NEXT: [[TMP10:%.*]] = icmp sge i8 [[TMP9]], [[TMP4]] +; RECOV-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP12:%.*]] +; RECOV: 11: +; RECOV-NEXT: call void @__asan_report_load4_noabort(i64 [[TMP0]]) #[[ATTR3]] +; RECOV-NEXT: br label [[TMP12]] +; RECOV: 12: +; RECOV-NEXT: br label [[TMP13]] +; RECOV: 13: +; RECOV-NEXT: [[Q:%.*]] = load i32, ptr addrspace(1) [[P]], align 4 +; RECOV-NEXT: ret void +; entry: %q = load i32, ptr addrspace(1) %p, align 4 ret void } + +define protected amdgpu_kernel void @global_store_8(ptr addrspace(1) %p) sanitize_address { +; CHECK-LABEL: define protected amdgpu_kernel void @global_store_8( +; CHECK-SAME: ptr addrspace(1) [[P:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(1) [[P]] to i64 +; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3 +; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880 +; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr +; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1 +; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0 +; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP7:%.*]] +; CHECK: 6: +; CHECK-NEXT: call void @__asan_report_store8(i64 [[TMP0]]) #[[ATTR3]] +; CHECK-NEXT: unreachable +; CHECK: 7: +; CHECK-NEXT: store i64 0, ptr addrspace(1) [[P]], align 8 +; CHECK-NEXT: ret void +; +; RECOV-LABEL: define protected amdgpu_kernel void @global_store_8( +; RECOV-SAME: ptr addrspace(1) [[P:%.*]]) #[[ATTR0]] { +; RECOV-NEXT: entry: +; RECOV-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(1) [[P]] to i64 +; RECOV-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3 +; RECOV-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880 +; RECOV-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr +; RECOV-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1 +; RECOV-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0 +; RECOV-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP7:%.*]] +; RECOV: 6: +; RECOV-NEXT: call void @__asan_report_store8_noabort(i64 [[TMP0]]) #[[ATTR3]] +; RECOV-NEXT: br label [[TMP7]] +; RECOV: 7: +; RECOV-NEXT: store i64 0, ptr addrspace(1) [[P]], align 8 +; RECOV-NEXT: ret void +; +entry: + store i64 0, ptr addrspace(1) %p, align 8 + ret void +} + +define protected amdgpu_kernel void @global_load_8(ptr addrspace(1) %p) sanitize_address { +; CHECK-LABEL: define protected amdgpu_kernel void @global_load_8( +; CHECK-SAME: ptr addrspace(1) [[P:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(1) [[P]] to i64 +; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3 +; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880 +; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr +; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1 +; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0 +; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP7:%.*]] +; CHECK: 6: +; CHECK-NEXT: call void @__asan_report_load8(i64 [[TMP0]]) #[[ATTR3]] +; CHECK-NEXT: unreachable +; CHECK: 7: +; CHECK-NEXT: [[Q:%.*]] = load i64, ptr addrspace(1) [[P]], align 8 +; CHECK-NEXT: ret void +; +; RECOV-LABEL: define protected amdgpu_kernel void @global_load_8( +; RECOV-SAME: ptr addrspace(1) [[P:%.*]]) #[[ATTR0]] { +; RECOV-NEXT: entry: +; RECOV-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(1) [[P]] to i64 +; RECOV-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3 +; RECOV-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880 +; RECOV-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr +; RECOV-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1 +; RECOV-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0 +; RECOV-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP7:%.*]] +; RECOV: 6: +; RECOV-NEXT: call void @__asan_report_load8_noabort(i64 [[TMP0]]) #[[ATTR3]] +; RECOV-NEXT: br label [[TMP7]] +; RECOV: 7: +; RECOV-NEXT: [[Q:%.*]] = load i64, ptr addrspace(1) [[P]], align 8 +; RECOV-NEXT: ret void +; +entry: + %q = load i64, ptr addrspace(1) %p, align 8 + ret void +} -- GitLab From 985c0d1903c173b896674b30480992e2414b8aa0 Mon Sep 17 00:00:00 2001 From: Schrodinger ZHU Yifan Date: Thu, 30 Nov 2023 20:36:28 -0500 Subject: [PATCH 082/699] [libc][mincore] use correct page_size for test (#73984) --- libc/test/src/sys/mman/linux/CMakeLists.txt | 1 + libc/test/src/sys/mman/linux/mincore_test.cpp | 78 ++++++++++++------- 2 files changed, 49 insertions(+), 30 deletions(-) diff --git a/libc/test/src/sys/mman/linux/CMakeLists.txt b/libc/test/src/sys/mman/linux/CMakeLists.txt index 5402ae030b34..c60377eb2cc1 100644 --- a/libc/test/src/sys/mman/linux/CMakeLists.txt +++ b/libc/test/src/sys/mman/linux/CMakeLists.txt @@ -76,5 +76,6 @@ add_libc_unittest( libc.src.sys.mman.munmap libc.src.sys.mman.madvise libc.src.sys.mman.mincore + libc.src.unistd.sysconf libc.test.UnitTest.ErrnoSetterMatcher ) diff --git a/libc/test/src/sys/mman/linux/mincore_test.cpp b/libc/test/src/sys/mman/linux/mincore_test.cpp index 7c8ca3b4ffa4..655fd8631af8 100644 --- a/libc/test/src/sys/mman/linux/mincore_test.cpp +++ b/libc/test/src/sys/mman/linux/mincore_test.cpp @@ -11,12 +11,13 @@ #include "src/sys/mman/mincore.h" #include "src/sys/mman/mmap.h" #include "src/sys/mman/munmap.h" +#include "src/unistd/sysconf.h" #include "test/UnitTest/ErrnoSetterMatcher.h" #include "test/UnitTest/LibcTest.h" #include "test/UnitTest/Test.h" -#include // For EXEC_PAGESIZE #include +#include // For sysconf. using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; @@ -28,73 +29,90 @@ TEST(LlvmLibcMincoreTest, UnMappedMemory) { EXPECT_THAT(res, Fails(ENOMEM, -1)); } +// It is always possible to find an aligned boundary if we allocate page sized +// memory. +static char *aligned_addr(void *addr, size_t alignment) { + char *byte_addr = static_cast(addr); + uintptr_t addr_val = reinterpret_cast(addr); + uintptr_t offset = + addr_val % alignment == 0 ? 0 : alignment - (addr_val % alignment); + return byte_addr + offset; +} + TEST(LlvmLibcMincoreTest, InvalidVec) { - void *addr = LIBC_NAMESPACE::mmap(nullptr, 4 * EXEC_PAGESIZE, PROT_READ, + size_t page_size = static_cast(LIBC_NAMESPACE::sysconf(_SC_PAGESIZE)); + void *addr = LIBC_NAMESPACE::mmap(nullptr, 5 * page_size, PROT_READ, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); EXPECT_NE(addr, MAP_FAILED); - EXPECT_EQ(reinterpret_cast(addr) % EXEC_PAGESIZE, 0ul); + // Since we allocated 5 pages, we can find an aligned boundary after which + // there are at least 4 pages + char *aligned = aligned_addr(addr, page_size); libc_errno = 0; - int res = LIBC_NAMESPACE::mincore(addr, 1, nullptr); + int res = LIBC_NAMESPACE::mincore(aligned, 1, nullptr); EXPECT_THAT(res, Fails(EFAULT, -1)); - void *area = - LIBC_NAMESPACE::mmap(nullptr, EXEC_PAGESIZE, PROT_READ | PROT_WRITE, - MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); + void *area = LIBC_NAMESPACE::mmap(nullptr, page_size, PROT_READ | PROT_WRITE, + MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); EXPECT_NE(area, MAP_FAILED); - unsigned char *ptr = static_cast(area) + EXEC_PAGESIZE - 3; - res = LIBC_NAMESPACE::mincore(addr, 4 * EXEC_PAGESIZE, ptr); + unsigned char *ptr = static_cast(area) + page_size - 3; + res = LIBC_NAMESPACE::mincore(aligned, 4 * page_size, ptr); EXPECT_THAT(res, Fails(EFAULT, -1)); - EXPECT_THAT(LIBC_NAMESPACE::munmap(addr, EXEC_PAGESIZE), Succeeds()); - EXPECT_THAT(LIBC_NAMESPACE::munmap(area, 2), Succeeds()); + EXPECT_THAT(LIBC_NAMESPACE::munmap(addr, 5 * page_size), Succeeds()); + EXPECT_THAT(LIBC_NAMESPACE::munmap(area, page_size), Succeeds()); } TEST(LlvmLibcMincoreTest, UnalignedAddr) { - void *addr = LIBC_NAMESPACE::mmap(nullptr, EXEC_PAGESIZE, PROT_READ, + size_t page_size = static_cast(LIBC_NAMESPACE::sysconf(_SC_PAGESIZE)); + void *addr = LIBC_NAMESPACE::mmap(nullptr, page_size, PROT_READ, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); EXPECT_NE(addr, MAP_FAILED); - EXPECT_EQ(reinterpret_cast(addr) % EXEC_PAGESIZE, 0ul); + char *aligned = aligned_addr(addr, page_size); libc_errno = 0; - int res = LIBC_NAMESPACE::mincore(static_cast(addr) + 1, 1, nullptr); + int res = LIBC_NAMESPACE::mincore(aligned + 1, 1, nullptr); EXPECT_THAT(res, Fails(EINVAL, -1)); - EXPECT_THAT(LIBC_NAMESPACE::munmap(addr, EXEC_PAGESIZE), Succeeds()); + EXPECT_THAT(LIBC_NAMESPACE::munmap(addr, page_size), Succeeds()); } TEST(LlvmLibcMincoreTest, NoError) { - void *addr = LIBC_NAMESPACE::mmap(nullptr, EXEC_PAGESIZE, PROT_READ, + size_t page_size = static_cast(LIBC_NAMESPACE::sysconf(_SC_PAGESIZE)); + void *addr = LIBC_NAMESPACE::mmap(nullptr, page_size, PROT_READ, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); EXPECT_NE(addr, MAP_FAILED); - EXPECT_EQ(reinterpret_cast(addr) % EXEC_PAGESIZE, 0ul); + char *aligned = aligned_addr(addr, page_size); unsigned char vec; libc_errno = 0; - int res = LIBC_NAMESPACE::mincore(addr, 1, &vec); + int res = LIBC_NAMESPACE::mincore(aligned, 1, &vec); EXPECT_THAT(res, Succeeds()); - EXPECT_THAT(LIBC_NAMESPACE::munmap(addr, EXEC_PAGESIZE), Succeeds()); + EXPECT_THAT(LIBC_NAMESPACE::munmap(addr, page_size), Succeeds()); } TEST(LlvmLibcMincoreTest, NegativeLength) { - void *addr = LIBC_NAMESPACE::mmap(nullptr, EXEC_PAGESIZE, PROT_READ, + size_t page_size = static_cast(LIBC_NAMESPACE::sysconf(_SC_PAGESIZE)); + void *addr = LIBC_NAMESPACE::mmap(nullptr, page_size, PROT_READ, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); EXPECT_NE(addr, MAP_FAILED); - EXPECT_EQ(reinterpret_cast(addr) % EXEC_PAGESIZE, 0ul); + char *aligned = aligned_addr(addr, page_size); unsigned char vec; libc_errno = 0; - int res = LIBC_NAMESPACE::mincore(addr, -1, &vec); + int res = LIBC_NAMESPACE::mincore(aligned, -1, &vec); EXPECT_THAT(res, Fails(ENOMEM, -1)); - EXPECT_THAT(LIBC_NAMESPACE::munmap(addr, EXEC_PAGESIZE), Succeeds()); + EXPECT_THAT(LIBC_NAMESPACE::munmap(addr, page_size), Succeeds()); } TEST(LlvmLibcMincoreTest, PageOut) { unsigned char vec; + size_t page_size = static_cast(LIBC_NAMESPACE::sysconf(_SC_PAGESIZE)); + // allocate 2 pages since we need to page out page_size bytes void *addr = - LIBC_NAMESPACE::mmap(nullptr, EXEC_PAGESIZE, PROT_READ | PROT_WRITE, + LIBC_NAMESPACE::mmap(nullptr, 2 * page_size, PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); EXPECT_NE(addr, MAP_FAILED); - EXPECT_EQ(reinterpret_cast(addr) % EXEC_PAGESIZE, 0ul); + char *aligned = aligned_addr(addr, page_size); // touch the page { - static_cast(addr)[0] = 0; + aligned[0] = 0; libc_errno = 0; - int res = LIBC_NAMESPACE::mincore(addr, 1, &vec); + int res = LIBC_NAMESPACE::mincore(aligned, 1, &vec); EXPECT_EQ(vec & 1u, 1u); EXPECT_THAT(res, Succeeds()); } @@ -102,14 +120,14 @@ TEST(LlvmLibcMincoreTest, PageOut) { // page out the memory { libc_errno = 0; - EXPECT_THAT(LIBC_NAMESPACE::madvise(addr, EXEC_PAGESIZE, MADV_DONTNEED), + EXPECT_THAT(LIBC_NAMESPACE::madvise(aligned, page_size, MADV_DONTNEED), Succeeds()); libc_errno = 0; - int res = LIBC_NAMESPACE::mincore(addr, EXEC_PAGESIZE, &vec); + int res = LIBC_NAMESPACE::mincore(aligned, 1, &vec); EXPECT_EQ(vec & 1u, 0u); EXPECT_THAT(res, Succeeds()); } - EXPECT_THAT(LIBC_NAMESPACE::munmap(addr, EXEC_PAGESIZE), Succeeds()); + EXPECT_THAT(LIBC_NAMESPACE::munmap(addr, 2 * page_size), Succeeds()); } -- GitLab From 2441e237a2d6ad44eedb26bde4406e274e32c4a4 Mon Sep 17 00:00:00 2001 From: Wenju He Date: Fri, 1 Dec 2023 09:46:24 +0800 Subject: [PATCH 083/699] [NFC][indvars] Remove unused code in WidenIV::widenLoopCompare (#73506) --- llvm/lib/Transforms/Utils/SimplifyIndVar.cpp | 4 ---- 1 file changed, 4 deletions(-) diff --git a/llvm/lib/Transforms/Utils/SimplifyIndVar.cpp b/llvm/lib/Transforms/Utils/SimplifyIndVar.cpp index c2ca97d9ef9f..722ed03db3de 100644 --- a/llvm/lib/Transforms/Utils/SimplifyIndVar.cpp +++ b/llvm/lib/Transforms/Utils/SimplifyIndVar.cpp @@ -1511,10 +1511,6 @@ bool WidenIV::widenLoopCompare(WidenIV::NarrowIVDefUse DU) { assert(CastWidth <= IVWidth && "Unexpected width while widening compare."); // Widen the compare instruction. - auto *InsertPt = getInsertPointForUses(DU.NarrowUse, DU.NarrowDef, DT, LI); - if (!InsertPt) - return false; - IRBuilder<> Builder(InsertPt); DU.NarrowUse->replaceUsesOfWith(DU.NarrowDef, DU.WideDef); // Widen the other operand of the compare, if necessary. -- GitLab From 56bbf8135eb8b7d133d5d5fc7604d66f5011c57b Mon Sep 17 00:00:00 2001 From: ShatianWang <38512325+ShatianWang@users.noreply.github.com> Date: Thu, 30 Nov 2023 20:55:36 -0500 Subject: [PATCH 084/699] [BOLT] CDSplit main logic part 1/2 (#73895) This diff defines and initializes auxiliary variables used by CDSplit and implements two important helper functions. The first helper function approximates the block level size increase if a function is hot-warm split at a given split index (X86 specific). The second helper function finds all calls in the form of X->Y or Y->X for each BF given function order [... X ... BF ... Y ...]. These calls are referred to as "cover calls". Their distance will decrease if BF's hot fragment size is further reduced by hot-warm splitting. NFC. --- bolt/lib/Core/FunctionLayout.cpp | 4 - bolt/lib/Passes/SplitFunctions.cpp | 231 ++++++++++++++++++++++++++++- 2 files changed, 230 insertions(+), 5 deletions(-) diff --git a/bolt/lib/Core/FunctionLayout.cpp b/bolt/lib/Core/FunctionLayout.cpp index 37b07bd28f26..27e40de94be6 100644 --- a/bolt/lib/Core/FunctionLayout.cpp +++ b/bolt/lib/Core/FunctionLayout.cpp @@ -188,10 +188,6 @@ bool FunctionLayout::update(const ArrayRef NewLayout) { for (BinaryBasicBlock *const BB : NewLayout) { FragmentNum Num = BB->getFragmentNum(); - assert(Num >= Fragments.back()->getFragmentNum() && - "Blocks must be arranged such that fragments are monotonically " - "increasing."); - // Add empty fragments if necessary while (Fragments.back()->getFragmentNum() < Num) addFragment(); diff --git a/bolt/lib/Passes/SplitFunctions.cpp b/bolt/lib/Passes/SplitFunctions.cpp index 79da4cc3b04b..f8c5360495be 100644 --- a/bolt/lib/Passes/SplitFunctions.cpp +++ b/bolt/lib/Passes/SplitFunctions.cpp @@ -109,6 +109,11 @@ static cl::opt SplitStrategy( "fragment contains exactly a single basic block")), cl::desc("strategy used to partition blocks into fragments"), cl::cat(BoltOptCategory)); + +static cl::opt CallScale( + "call-scale", + cl::desc("Call score scale coefficient (when --split-strategy=cdsplit)"), + cl::init(0.95), cl::ReallyHidden, cl::cat(BoltOptCategory)); } // namespace opts namespace { @@ -140,12 +145,18 @@ struct SplitProfile2 final : public SplitStrategy { }; struct SplitCacheDirected final : public SplitStrategy { + BinaryContext &BC; using BasicBlockOrder = BinaryFunction::BasicBlockOrderType; bool canSplit(const BinaryFunction &BF) override { return BF.hasValidProfile() && hasFullProfile(BF) && !allBlocksCold(BF); } + explicit SplitCacheDirected(BinaryContext &BC) : BC(BC) { + initializeAuxiliaryVariables(); + buildCallGraph(); + } + // When some functions are hot-warm split and others are hot-warm-cold split, // we do not want to change the fragment numbers of the blocks in the hot-warm // split functions. @@ -173,6 +184,224 @@ struct SplitCacheDirected final : public SplitStrategy { } private: + struct JumpInfo { + bool HasUncondBranch = false; + BinaryBasicBlock *CondSuccessor = nullptr; + BinaryBasicBlock *UncondSuccessor = nullptr; + }; + + struct CallInfo { + size_t Length; + size_t Count; + }; + + // Auxiliary variables used by the algorithm. + size_t TotalNumBlocks{0}; + size_t OrigHotSectionSize{0}; + DenseMap GlobalIndices; + DenseMap BBSizes; + DenseMap BBOffsets; + DenseMap JumpInfos; + + // Call graph. + std::vector> Callers; + std::vector> Callees; + + bool shouldConsiderForCallGraph(const BinaryFunction &BF) { + // Only a subset of the functions in the binary will be considered + // for initializing auxiliary variables and building call graph. + return BF.hasValidIndex() && BF.hasValidProfile() && !BF.empty(); + } + + void initializeAuxiliaryVariables() { + // Gather information about conditional and unconditional successors of + // each basic block; this information will be used to estimate block size + // increase due to hot-warm splitting. + auto analyzeBranches = [&](BinaryBasicBlock &BB) { + JumpInfo BBJumpInfo; + const MCSymbol *TBB = nullptr; + const MCSymbol *FBB = nullptr; + MCInst *CondBranch = nullptr; + MCInst *UncondBranch = nullptr; + if (BB.analyzeBranch(TBB, FBB, CondBranch, UncondBranch)) { + BBJumpInfo.HasUncondBranch = UncondBranch != nullptr; + if (BB.succ_size() == 1) { + BBJumpInfo.UncondSuccessor = BB.getSuccessor(); + } else if (BB.succ_size() == 2) { + BBJumpInfo.CondSuccessor = BB.getConditionalSuccessor(true); + BBJumpInfo.UncondSuccessor = BB.getConditionalSuccessor(false); + } + } + return BBJumpInfo; + }; + + for (BinaryFunction *BF : BC.getSortedFunctions()) { + if (!shouldConsiderForCallGraph(*BF)) + continue; + + // Calculate the size of each BB after hot-cold splitting. + // This populates BinaryBasicBlock::OutputAddressRange which + // can be used to compute the size of each BB. + BC.calculateEmittedSize(*BF, /*FixBranches=*/true); + + for (BinaryBasicBlock *BB : BF->getLayout().blocks()) { + // Unique global index. + GlobalIndices[BB] = TotalNumBlocks; + TotalNumBlocks++; + + // Block size after hot-cold splitting. + BBSizes[BB] = BB->getOutputSize(); + + // Hot block offset after hot-cold splitting. + BBOffsets[BB] = OrigHotSectionSize; + if (!BB->isSplit()) + OrigHotSectionSize += BBSizes[BB]; + + // (Un)Conditional branch instruction information. + JumpInfos[BB] = analyzeBranches(*BB); + } + } + } + + void buildCallGraph() { + Callers.resize(TotalNumBlocks); + Callees.resize(TotalNumBlocks); + for (const BinaryFunction *SrcFunction : BC.getSortedFunctions()) { + if (!shouldConsiderForCallGraph(*SrcFunction)) + continue; + + for (BinaryBasicBlock &SrcBB : SrcFunction->blocks()) { + // Skip blocks that are not executed + if (SrcBB.getKnownExecutionCount() == 0) + continue; + + // Find call instructions and extract target symbols from each one + for (const MCInst &Inst : SrcBB) { + if (!BC.MIB->isCall(Inst)) + continue; + + // Call info + const MCSymbol *DstSym = BC.MIB->getTargetSymbol(Inst); + // Ignore calls w/o information + if (!DstSym) + continue; + + const BinaryFunction *DstFunction = BC.getFunctionForSymbol(DstSym); + // Ignore calls that do not have a valid target, but do not ignore + // recursive calls, because caller block could be moved to warm. + if (!DstFunction || DstFunction->getLayout().block_empty()) + continue; + + const BinaryBasicBlock *DstBB = &(DstFunction->front()); + + // Record the call only if DstBB is also in functions to consider for + // call graph. + if (GlobalIndices.contains(DstBB)) { + Callers[GlobalIndices[DstBB]].push_back(&SrcBB); + Callees[GlobalIndices[&SrcBB]].push_back(DstBB); + } + } + } + } + } + + /// Populate BinaryBasicBlock::OutputAddressRange with estimated basic block + /// start and end addresses for hot and warm basic blocks, assuming hot-warm + /// splitting happens at \p SplitIndex. Also return estimated end addresses + /// of the hot fragment before and after splitting. + /// The estimations take into account the potential addition of branch + /// instructions due to split fall through branches as well as the need to + /// use longer branch instructions for split (un)conditional branches. + std::pair + estimatePostSplitBBAddress(const BasicBlockOrder &BlockOrder, + const size_t SplitIndex) { + assert(SplitIndex < BlockOrder.size() && "Invalid split index"); + + // Update function layout assuming hot-warm splitting at SplitIndex + for (size_t Index = 0; Index < BlockOrder.size(); Index++) { + BinaryBasicBlock *BB = BlockOrder[Index]; + if (BB->getFragmentNum() == FragmentNum::cold()) + break; + BB->setFragmentNum(Index <= SplitIndex ? FragmentNum::main() + : FragmentNum::warm()); + } + BinaryFunction *BF = BlockOrder[0]->getFunction(); + BF->getLayout().update(BlockOrder); + // Populate BB.OutputAddressRange under the updated layout. + BC.calculateEmittedSize(*BF); + + // Populate BB.OutputAddressRange with estimated new start and end addresses + // and compute the old end address of the hot section and the new end + // address of the hot section. + size_t OldHotEndAddr; + size_t NewHotEndAddr; + size_t CurrentAddr = BBOffsets[BlockOrder[0]]; + for (BinaryBasicBlock *BB : BlockOrder) { + // We only care about new addresses of blocks in hot/warm. + if (BB->getFragmentNum() == FragmentNum::cold()) + break; + BB->setOutputStartAddress(CurrentAddr); + CurrentAddr += BB->getOutputSize(); + BB->setOutputEndAddress(CurrentAddr); + if (BB->getLayoutIndex() == SplitIndex) { + NewHotEndAddr = CurrentAddr; + // Approximate the start address of the warm fragment of the current + // function using the original hot section size. + CurrentAddr = OrigHotSectionSize; + } + OldHotEndAddr = BBOffsets[BB] + BBSizes[BB]; + } + return std::make_pair(OldHotEndAddr, NewHotEndAddr); + } + + /// Get a collection of "shortenable" calls, that is, calls of type X->Y + /// when the function order is [... X ... BF ... Y ...]. + /// If the hot fragment size of BF is reduced, then such calls are guaranteed + /// to get shorter by the reduced hot fragment size. + std::vector extractCoverCalls(const BinaryFunction &BF) { + // Record the length and the count of the calls that can be shortened + std::vector CoverCalls; + if (opts::CallScale == 0) + return CoverCalls; + + const BinaryFunction *ThisBF = &BF; + const BinaryBasicBlock *ThisBB = &(ThisBF->front()); + const size_t ThisGI = GlobalIndices[ThisBB]; + + for (const BinaryFunction *DstBF : BC.getSortedFunctions()) { + if (!shouldConsiderForCallGraph(*DstBF)) + continue; + + const BinaryBasicBlock *DstBB = &(DstBF->front()); + if (DstBB->getKnownExecutionCount() == 0) + continue; + + const size_t DstGI = GlobalIndices[DstBB]; + for (const BinaryBasicBlock *SrcBB : Callers[DstGI]) { + const BinaryFunction *SrcBF = SrcBB->getFunction(); + if (ThisBF == SrcBF) + continue; + + const size_t CallCount = SrcBB->getKnownExecutionCount(); + + const size_t SrcGI = GlobalIndices[SrcBB]; + + const bool IsCoverCall = (SrcGI < ThisGI && ThisGI < DstGI) || + (DstGI <= ThisGI && ThisGI < SrcGI); + if (!IsCoverCall) + continue; + + const size_t SrcBBEndAddr = BBOffsets[SrcBB] + BBSizes[SrcBB]; + const size_t DstBBStartAddr = BBOffsets[DstBB]; + const size_t CallLength = + AbsoluteDifference(SrcBBEndAddr, DstBBStartAddr); + const CallInfo CI{CallLength, CallCount}; + CoverCalls.emplace_back(CI); + } + } + return CoverCalls; + } + /// Find the best index for splitting. The returned value is the index of the /// last hot basic block. Hence, "no splitting" is equivalent to returning the /// value which is one less than the size of the function. @@ -308,7 +537,7 @@ void SplitFunctions::runOnFunctions(BinaryContext &BC) { // before function reordering and hot-warm-cold splitting // (SplitCacheDirected) after function reordering. if (BC.HasFinalizedFunctionOrder) - Strategy = std::make_unique(); + Strategy = std::make_unique(BC); else Strategy = std::make_unique(); opts::AggressiveSplitting = true; -- GitLab From ca66df3b021017fedf08f0779f5bfc7898dbdd29 Mon Sep 17 00:00:00 2001 From: wanglei Date: Tue, 14 Nov 2023 17:58:52 +0800 Subject: [PATCH 085/699] [LoongArch] Add more and/or/xor patterns for vector types --- .../LoongArch/LoongArchLASXInstrInfo.td | 21 +-- .../Target/LoongArch/LoongArchLSXInstrInfo.td | 21 +-- .../LoongArch/lasx/ir-instruction/and.ll | 125 ++++++++++++++++++ .../LoongArch/lasx/ir-instruction/or.ll | 125 ++++++++++++++++++ .../LoongArch/lasx/ir-instruction/xor.ll | 125 ++++++++++++++++++ .../LoongArch/lsx/ir-instruction/and.ll | 125 ++++++++++++++++++ .../LoongArch/lsx/ir-instruction/or.ll | 125 ++++++++++++++++++ .../LoongArch/lsx/ir-instruction/xor.ll | 125 ++++++++++++++++++ 8 files changed, 774 insertions(+), 18 deletions(-) create mode 100644 llvm/test/CodeGen/LoongArch/lasx/ir-instruction/and.ll create mode 100644 llvm/test/CodeGen/LoongArch/lasx/ir-instruction/or.ll create mode 100644 llvm/test/CodeGen/LoongArch/lasx/ir-instruction/xor.ll create mode 100644 llvm/test/CodeGen/LoongArch/lsx/ir-instruction/and.ll create mode 100644 llvm/test/CodeGen/LoongArch/lsx/ir-instruction/or.ll create mode 100644 llvm/test/CodeGen/LoongArch/lsx/ir-instruction/xor.ll diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td index 4487152fb42b..a5652472481a 100644 --- a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td @@ -1184,10 +1184,6 @@ multiclass PatShiftXrUimm { (!cast(Inst#"_D") LASX256:$xj, uimm6:$imm)>; } -class PatXrXrB - : Pat<(OpNode (v32i8 LASX256:$xj), (v32i8 LASX256:$xk)), - (Inst LASX256:$xj, LASX256:$xk)>; - let Predicates = [HasExtLASX] in { // XVADD_{B/H/W/D} @@ -1235,13 +1231,20 @@ defm : PatXrXr; defm : PatXrXrU; // XVAND_V -def : PatXrXrB; -// XVNOR_V -def : PatXrXrB; +foreach vt = [v32i8, v16i16, v8i32, v4i64] in +def : Pat<(and (vt LASX256:$xj), (vt LASX256:$xk)), + (XVAND_V LASX256:$xj, LASX256:$xk)>; +// XVOR_V +foreach vt = [v32i8, v16i16, v8i32, v4i64] in +def : Pat<(or (vt LASX256:$xj), (vt LASX256:$xk)), + (XVOR_V LASX256:$xj, LASX256:$xk)>; // XVXOR_V -def : PatXrXrB; +foreach vt = [v32i8, v16i16, v8i32, v4i64] in +def : Pat<(xor (vt LASX256:$xj), (vt LASX256:$xk)), + (XVXOR_V LASX256:$xj, LASX256:$xk)>; // XVNOR_V -def : Pat<(vnot (or (v32i8 LASX256:$xj), (v32i8 LASX256:$xk))), +foreach vt = [v32i8, v16i16, v8i32, v4i64] in +def : Pat<(vnot (or (vt LASX256:$xj), (vt LASX256:$xk))), (XVNOR_V LASX256:$xj, LASX256:$xk)>; // XVANDI_B diff --git a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td index deac5015882d..5645ce51194a 100644 --- a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td @@ -1261,10 +1261,6 @@ multiclass PatShiftVrUimm { (!cast(Inst#"_D") LSX128:$vj, uimm6:$imm)>; } -class PatVrVrB - : Pat<(OpNode (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)), - (Inst LSX128:$vj, LSX128:$vk)>; - let Predicates = [HasExtLSX] in { // VADD_{B/H/W/D} @@ -1312,13 +1308,20 @@ defm : PatVrVr; defm : PatVrVrU; // VAND_V -def : PatVrVrB; -// VNOR_V -def : PatVrVrB; +foreach vt = [v16i8, v8i16, v4i32, v2i64] in +def : Pat<(and (vt LSX128:$vj), (vt LSX128:$vk)), + (VAND_V LSX128:$vj, LSX128:$vk)>; +// VOR_V +foreach vt = [v16i8, v8i16, v4i32, v2i64] in +def : Pat<(or (vt LSX128:$vj), (vt LSX128:$vk)), + (VOR_V LSX128:$vj, LSX128:$vk)>; // VXOR_V -def : PatVrVrB; +foreach vt = [v16i8, v8i16, v4i32, v2i64] in +def : Pat<(xor (vt LSX128:$vj), (vt LSX128:$vk)), + (VXOR_V LSX128:$vj, LSX128:$vk)>; // VNOR_V -def : Pat<(vnot (or (v16i8 LSX128:$vj), (v16i8 LSX128:$vk))), +foreach vt = [v16i8, v8i16, v4i32, v2i64] in +def : Pat<(vnot (or (vt LSX128:$vj), (vt LSX128:$vk))), (VNOR_V LSX128:$vj, LSX128:$vk)>; // VANDI_B diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/and.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/and.ll new file mode 100644 index 000000000000..98c87cadeeb5 --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/and.ll @@ -0,0 +1,125 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s + +define void @and_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: and_v32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvand.v $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <32 x i8>, ptr %a0 + %v1 = load <32 x i8>, ptr %a1 + %v2 = and <32 x i8> %v0, %v1 + store <32 x i8> %v2, ptr %res + ret void +} + +define void @and_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: and_v16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvand.v $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i16>, ptr %a0 + %v1 = load <16 x i16>, ptr %a1 + %v2 = and <16 x i16> %v0, %v1 + store <16 x i16> %v2, ptr %res + ret void +} + +define void @and_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: and_v8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvand.v $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i32>, ptr %a0 + %v1 = load <8 x i32>, ptr %a1 + %v2 = and <8 x i32> %v0, %v1 + store <8 x i32> %v2, ptr %res + ret void +} + +define void @and_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: and_v4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvand.v $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i64>, ptr %a0 + %v1 = load <4 x i64>, ptr %a1 + %v2 = and <4 x i64> %v0, %v1 + store <4 x i64> %v2, ptr %res + ret void +} + +define void @and_u_v32i8(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: and_u_v32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvandi.b $xr0, $xr0, 31 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <32 x i8>, ptr %a0 + %v1 = and <32 x i8> %v0, + store <32 x i8> %v1, ptr %res + ret void +} + +define void @and_u_v16i16(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: and_u_v16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvrepli.h $xr1, 31 +; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i16>, ptr %a0 + %v1 = and <16 x i16> %v0, + store <16 x i16> %v1, ptr %res + ret void +} + +define void @and_u_v8i32(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: and_u_v8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvrepli.w $xr1, 31 +; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i32>, ptr %a0 + %v1 = and <8 x i32> %v0, + store <8 x i32> %v1, ptr %res + ret void +} + +define void @and_u_v4i64(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: and_u_v4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvrepli.d $xr1, 31 +; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i64>, ptr %a0 + %v1 = and <4 x i64> %v0, + store <4 x i64> %v1, ptr %res + ret void +} diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/or.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/or.ll new file mode 100644 index 000000000000..f37cbf1cefed --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/or.ll @@ -0,0 +1,125 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s + +define void @or_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: or_v32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvor.v $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <32 x i8>, ptr %a0 + %v1 = load <32 x i8>, ptr %a1 + %v2 = or <32 x i8> %v0, %v1 + store <32 x i8> %v2, ptr %res + ret void +} + +define void @or_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: or_v16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvor.v $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i16>, ptr %a0 + %v1 = load <16 x i16>, ptr %a1 + %v2 = or <16 x i16> %v0, %v1 + store <16 x i16> %v2, ptr %res + ret void +} + +define void @or_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: or_v8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvor.v $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i32>, ptr %a0 + %v1 = load <8 x i32>, ptr %a1 + %v2 = or <8 x i32> %v0, %v1 + store <8 x i32> %v2, ptr %res + ret void +} + +define void @or_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: or_v4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvor.v $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i64>, ptr %a0 + %v1 = load <4 x i64>, ptr %a1 + %v2 = or <4 x i64> %v0, %v1 + store <4 x i64> %v2, ptr %res + ret void +} + +define void @or_u_v32i8(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: or_u_v32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvori.b $xr0, $xr0, 31 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <32 x i8>, ptr %a0 + %v1 = or <32 x i8> %v0, + store <32 x i8> %v1, ptr %res + ret void +} + +define void @or_u_v16i16(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: or_u_v16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvrepli.h $xr1, 31 +; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i16>, ptr %a0 + %v1 = or <16 x i16> %v0, + store <16 x i16> %v1, ptr %res + ret void +} + +define void @or_u_v8i32(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: or_u_v8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvrepli.w $xr1, 31 +; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i32>, ptr %a0 + %v1 = or <8 x i32> %v0, + store <8 x i32> %v1, ptr %res + ret void +} + +define void @or_u_v4i64(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: or_u_v4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvrepli.d $xr1, 31 +; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i64>, ptr %a0 + %v1 = or <4 x i64> %v0, + store <4 x i64> %v1, ptr %res + ret void +} diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/xor.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/xor.ll new file mode 100644 index 000000000000..c2fb1462b7a2 --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/xor.ll @@ -0,0 +1,125 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s + +define void @xor_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: xor_v32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvxor.v $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <32 x i8>, ptr %a0 + %v1 = load <32 x i8>, ptr %a1 + %v2 = xor <32 x i8> %v0, %v1 + store <32 x i8> %v2, ptr %res + ret void +} + +define void @xor_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: xor_v16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvxor.v $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i16>, ptr %a0 + %v1 = load <16 x i16>, ptr %a1 + %v2 = xor <16 x i16> %v0, %v1 + store <16 x i16> %v2, ptr %res + ret void +} + +define void @xor_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: xor_v8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvxor.v $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i32>, ptr %a0 + %v1 = load <8 x i32>, ptr %a1 + %v2 = xor <8 x i32> %v0, %v1 + store <8 x i32> %v2, ptr %res + ret void +} + +define void @xor_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: xor_v4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvxor.v $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i64>, ptr %a0 + %v1 = load <4 x i64>, ptr %a1 + %v2 = xor <4 x i64> %v0, %v1 + store <4 x i64> %v2, ptr %res + ret void +} + +define void @xor_u_v32i8(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: xor_u_v32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvxori.b $xr0, $xr0, 31 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <32 x i8>, ptr %a0 + %v1 = xor <32 x i8> %v0, + store <32 x i8> %v1, ptr %res + ret void +} + +define void @xor_u_v16i16(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: xor_u_v16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvrepli.h $xr1, 31 +; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i16>, ptr %a0 + %v1 = xor <16 x i16> %v0, + store <16 x i16> %v1, ptr %res + ret void +} + +define void @xor_u_v8i32(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: xor_u_v8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvrepli.w $xr1, 31 +; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i32>, ptr %a0 + %v1 = xor <8 x i32> %v0, + store <8 x i32> %v1, ptr %res + ret void +} + +define void @xor_u_v4i64(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: xor_u_v4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvrepli.d $xr1, 31 +; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i64>, ptr %a0 + %v1 = xor <4 x i64> %v0, + store <4 x i64> %v1, ptr %res + ret void +} diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/and.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/and.ll new file mode 100644 index 000000000000..523255159a81 --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/and.ll @@ -0,0 +1,125 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s + +define void @and_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: and_v16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vld $vr0, $a2, 0 +; CHECK-NEXT: vld $vr1, $a1, 0 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i8>, ptr %a0 + %v1 = load <16 x i8>, ptr %a1 + %v2 = and <16 x i8> %v0, %v1 + store <16 x i8> %v2, ptr %res + ret void +} + +define void @and_v8i16(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: and_v8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vld $vr0, $a2, 0 +; CHECK-NEXT: vld $vr1, $a1, 0 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i16>, ptr %a0 + %v1 = load <8 x i16>, ptr %a1 + %v2 = and <8 x i16> %v0, %v1 + store <8 x i16> %v2, ptr %res + ret void +} + +define void @and_v4i32(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: and_v4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vld $vr0, $a2, 0 +; CHECK-NEXT: vld $vr1, $a1, 0 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i32>, ptr %a0 + %v1 = load <4 x i32>, ptr %a1 + %v2 = and <4 x i32> %v0, %v1 + store <4 x i32> %v2, ptr %res + ret void +} + +define void @and_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: and_v2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vld $vr0, $a2, 0 +; CHECK-NEXT: vld $vr1, $a1, 0 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <2 x i64>, ptr %a0 + %v1 = load <2 x i64>, ptr %a1 + %v2 = and <2 x i64> %v0, %v1 + store <2 x i64> %v2, ptr %res + ret void +} + +define void @and_u_v16i8(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: and_u_v16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vld $vr0, $a1, 0 +; CHECK-NEXT: vandi.b $vr0, $vr0, 31 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i8>, ptr %a0 + %v1 = and <16 x i8> %v0, + store <16 x i8> %v1, ptr %res + ret void +} + +define void @and_u_v8i16(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: and_u_v8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vld $vr0, $a1, 0 +; CHECK-NEXT: vrepli.h $vr1, 31 +; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i16>, ptr %a0 + %v1 = and <8 x i16> %v0, + store <8 x i16> %v1, ptr %res + ret void +} + +define void @and_u_v4i32(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: and_u_v4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vld $vr0, $a1, 0 +; CHECK-NEXT: vrepli.w $vr1, 31 +; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i32>, ptr %a0 + %v1 = and <4 x i32> %v0, + store <4 x i32> %v1, ptr %res + ret void +} + +define void @and_u_v2i64(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: and_u_v2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vld $vr0, $a1, 0 +; CHECK-NEXT: vrepli.d $vr1, 31 +; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <2 x i64>, ptr %a0 + %v1 = and <2 x i64> %v0, + store <2 x i64> %v1, ptr %res + ret void +} diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/or.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/or.ll new file mode 100644 index 000000000000..f124512acce7 --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/or.ll @@ -0,0 +1,125 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s + +define void @or_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: or_v16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vld $vr0, $a2, 0 +; CHECK-NEXT: vld $vr1, $a1, 0 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i8>, ptr %a0 + %v1 = load <16 x i8>, ptr %a1 + %v2 = or <16 x i8> %v0, %v1 + store <16 x i8> %v2, ptr %res + ret void +} + +define void @or_v8i16(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: or_v8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vld $vr0, $a2, 0 +; CHECK-NEXT: vld $vr1, $a1, 0 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i16>, ptr %a0 + %v1 = load <8 x i16>, ptr %a1 + %v2 = or <8 x i16> %v0, %v1 + store <8 x i16> %v2, ptr %res + ret void +} + +define void @or_v4i32(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: or_v4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vld $vr0, $a2, 0 +; CHECK-NEXT: vld $vr1, $a1, 0 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i32>, ptr %a0 + %v1 = load <4 x i32>, ptr %a1 + %v2 = or <4 x i32> %v0, %v1 + store <4 x i32> %v2, ptr %res + ret void +} + +define void @or_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: or_v2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vld $vr0, $a2, 0 +; CHECK-NEXT: vld $vr1, $a1, 0 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <2 x i64>, ptr %a0 + %v1 = load <2 x i64>, ptr %a1 + %v2 = or <2 x i64> %v0, %v1 + store <2 x i64> %v2, ptr %res + ret void +} + +define void @or_u_v16i8(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: or_u_v16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vld $vr0, $a1, 0 +; CHECK-NEXT: vori.b $vr0, $vr0, 31 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i8>, ptr %a0 + %v1 = or <16 x i8> %v0, + store <16 x i8> %v1, ptr %res + ret void +} + +define void @or_u_v8i16(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: or_u_v8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vld $vr0, $a1, 0 +; CHECK-NEXT: vrepli.h $vr1, 31 +; CHECK-NEXT: vor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i16>, ptr %a0 + %v1 = or <8 x i16> %v0, + store <8 x i16> %v1, ptr %res + ret void +} + +define void @or_u_v4i32(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: or_u_v4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vld $vr0, $a1, 0 +; CHECK-NEXT: vrepli.w $vr1, 31 +; CHECK-NEXT: vor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i32>, ptr %a0 + %v1 = or <4 x i32> %v0, + store <4 x i32> %v1, ptr %res + ret void +} + +define void @or_u_v2i64(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: or_u_v2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vld $vr0, $a1, 0 +; CHECK-NEXT: vrepli.d $vr1, 31 +; CHECK-NEXT: vor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <2 x i64>, ptr %a0 + %v1 = or <2 x i64> %v0, + store <2 x i64> %v1, ptr %res + ret void +} diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/xor.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/xor.ll new file mode 100644 index 000000000000..ce3e49c990ff --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/xor.ll @@ -0,0 +1,125 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s + +define void @xor_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: xor_v16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vld $vr0, $a2, 0 +; CHECK-NEXT: vld $vr1, $a1, 0 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i8>, ptr %a0 + %v1 = load <16 x i8>, ptr %a1 + %v2 = xor <16 x i8> %v0, %v1 + store <16 x i8> %v2, ptr %res + ret void +} + +define void @xor_v8i16(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: xor_v8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vld $vr0, $a2, 0 +; CHECK-NEXT: vld $vr1, $a1, 0 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i16>, ptr %a0 + %v1 = load <8 x i16>, ptr %a1 + %v2 = xor <8 x i16> %v0, %v1 + store <8 x i16> %v2, ptr %res + ret void +} + +define void @xor_v4i32(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: xor_v4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vld $vr0, $a2, 0 +; CHECK-NEXT: vld $vr1, $a1, 0 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i32>, ptr %a0 + %v1 = load <4 x i32>, ptr %a1 + %v2 = xor <4 x i32> %v0, %v1 + store <4 x i32> %v2, ptr %res + ret void +} + +define void @xor_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: xor_v2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vld $vr0, $a2, 0 +; CHECK-NEXT: vld $vr1, $a1, 0 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <2 x i64>, ptr %a0 + %v1 = load <2 x i64>, ptr %a1 + %v2 = xor <2 x i64> %v0, %v1 + store <2 x i64> %v2, ptr %res + ret void +} + +define void @xor_u_v16i8(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: xor_u_v16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vld $vr0, $a1, 0 +; CHECK-NEXT: vxori.b $vr0, $vr0, 31 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i8>, ptr %a0 + %v1 = xor <16 x i8> %v0, + store <16 x i8> %v1, ptr %res + ret void +} + +define void @xor_u_v8i16(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: xor_u_v8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vld $vr0, $a1, 0 +; CHECK-NEXT: vrepli.h $vr1, 31 +; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i16>, ptr %a0 + %v1 = xor <8 x i16> %v0, + store <8 x i16> %v1, ptr %res + ret void +} + +define void @xor_u_v4i32(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: xor_u_v4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vld $vr0, $a1, 0 +; CHECK-NEXT: vrepli.w $vr1, 31 +; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i32>, ptr %a0 + %v1 = xor <4 x i32> %v0, + store <4 x i32> %v1, ptr %res + ret void +} + +define void @xor_u_v2i64(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: xor_u_v2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vld $vr0, $a1, 0 +; CHECK-NEXT: vrepli.d $vr1, 31 +; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <2 x i64>, ptr %a0 + %v1 = xor <2 x i64> %v0, + store <2 x i64> %v1, ptr %res + ret void +} -- GitLab From d0a39e617ba301a76d28e2d82e1f657999c9dcfb Mon Sep 17 00:00:00 2001 From: Piyou Chen Date: Thu, 30 Nov 2023 21:12:46 -0600 Subject: [PATCH 086/699] [RISCV] default enable splitting regalloc between RVV and other (#72950) This patch make riscv-split-regalloc as true by default. It will not affect the codegen result if it vector register allocation doesn't exist. If there is the vector register allocation, it may affect the non-rvv register LiveInterval's segment/weight. It will make the allocation in a different order. --- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 2 +- llvm/test/CodeGen/RISCV/O0-pipeline.ll | 1 + llvm/test/CodeGen/RISCV/O3-pipeline.ll | 4 + llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll | 32 +++---- llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll | 88 +++++++++---------- .../CodeGen/RISCV/rvv/regalloc-fast-crash.ll | 1 - llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll | 8 +- 7 files changed, 70 insertions(+), 66 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp index b6c194f03f54..ba13f8d2f448 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -93,7 +93,7 @@ static cl::opt static cl::opt EnableSplitRegAlloc("riscv-split-regalloc", cl::Hidden, cl::desc("Enable Split RegisterAlloc for RVV"), - cl::init(false)); + cl::init(true)); static cl::opt EnableMISchedLoadClustering( "riscv-misched-load-clustering", cl::Hidden, diff --git a/llvm/test/CodeGen/RISCV/O0-pipeline.ll b/llvm/test/CodeGen/RISCV/O0-pipeline.ll index e01d2d452634..e90fa24761bc 100644 --- a/llvm/test/CodeGen/RISCV/O0-pipeline.ll +++ b/llvm/test/CodeGen/RISCV/O0-pipeline.ll @@ -47,6 +47,7 @@ ; CHECK-NEXT: Eliminate PHI nodes for register allocation ; CHECK-NEXT: Two-Address instruction pass ; CHECK-NEXT: Fast Register Allocator +; CHECK-NEXT: Fast Register Allocator ; CHECK-NEXT: Remove Redundant DEBUG_VALUE analysis ; CHECK-NEXT: Fixup Statepoint Caller Saved ; CHECK-NEXT: Lazy Machine Block Frequency Analysis diff --git a/llvm/test/CodeGen/RISCV/O3-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-pipeline.ll index 5926c595979e..e7db8ef9d5af 100644 --- a/llvm/test/CodeGen/RISCV/O3-pipeline.ll +++ b/llvm/test/CodeGen/RISCV/O3-pipeline.ll @@ -142,6 +142,10 @@ ; CHECK-NEXT: Machine Optimization Remark Emitter ; CHECK-NEXT: Greedy Register Allocator ; CHECK-NEXT: Virtual Register Rewriter +; CHECK-NEXT: Virtual Register Map +; CHECK-NEXT: Live Register Matrix +; CHECK-NEXT: Greedy Register Allocator +; CHECK-NEXT: Virtual Register Rewriter ; CHECK-NEXT: Register Allocation Pass Scoring ; CHECK-NEXT: Stack Slot Coloring ; CHECK-NEXT: Machine Copy Propagation Pass diff --git a/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll b/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll index f41a2a06c69b..27fd9693b674 100644 --- a/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll @@ -3062,24 +3062,24 @@ define @vp_bitreverse_nxv64i16( %va, @vp_bitreverse_nxv64i16( %va, @vp_bitreverse_nxv64i16( %va, @fshr_v16i64( %a, @fshr_v16i64( %a, @fshr_v16i64( %a, @fshr_v16i64( %a, @fshr_v16i64( %a, @fshl_v16i64( %a, @fshl_v16i64( %a, @fshl_v16i64( %a, @fshl_v16i64( %a, @fshl_v16i64( %a, , %val, ptr %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll index 734fb59e2d88..243dc19a2558 100644 --- a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll @@ -3512,7 +3512,7 @@ define @fcmp_oeq_vv_nxv32f64( %va, @fcmp_oeq_vv_nxv32f64( %va, @fcmp_oeq_vv_nxv32f64( %va, Date: Fri, 1 Dec 2023 11:30:05 +0800 Subject: [PATCH 087/699] [mlir] Fix the link of libcuda.so in MLIRGPUTransforms to not use fully qualified path (#74018) At the moment we find libcuda.so in a path like: /usr/local/cuda/targets/x86_64-linux/lib/stubs/libcuda.so and directly add this to `target_link_libraries`. The problem is that our installed MLIR package will include the full path to the library, and a user downstream when including our cmake installed package will inherit this full path. We're changing this to instead -L /usr/local/cuda/targets/x86_64-linux/lib/stubs/ -lcuda --- mlir/lib/Dialect/GPU/CMakeLists.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/mlir/lib/Dialect/GPU/CMakeLists.txt b/mlir/lib/Dialect/GPU/CMakeLists.txt index b76d18e81246..e8b69879ad6a 100644 --- a/mlir/lib/Dialect/GPU/CMakeLists.txt +++ b/mlir/lib/Dialect/GPU/CMakeLists.txt @@ -135,11 +135,15 @@ if(MLIR_ENABLE_CUDA_RUNNER) ${CMAKE_CUDA_TOOLKIT_INCLUDE_DIRECTORIES} ) + # Add link path for the cuda driver library. find_library(CUDA_DRIVER_LIBRARY cuda HINTS ${CMAKE_CUDA_IMPLICIT_LINK_DIRECTORIES} REQUIRED) + get_filename_component(CUDA_DRIVER_LIBRARY_PATH "${CUDA_DRIVER_LIBRARY}" DIRECTORY) + target_link_directories(MLIRGPUTransforms PRIVATE ${CUDA_DRIVER_LIBRARY_PATH}) + target_link_libraries(MLIRGPUTransforms PRIVATE MLIRNVVMToLLVMIRTranslation - ${CUDA_DRIVER_LIBRARY} + cuda ) endif() -- GitLab From 755c28a9401536d89601ae3582f44be1746fadb6 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 30 Nov 2023 19:55:23 -0800 Subject: [PATCH 088/699] [GISel][Mips] Infer alignment when creating memory operand for G_VASTART. (#74004) --- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 5 +++-- llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 3753b6d540f1..14a4e72152e7 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -81,6 +81,7 @@ #include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetIntrinsicInfo.h" #include "llvm/Target/TargetMachine.h" +#include "llvm/Transforms/Utils/Local.h" #include "llvm/Transforms/Utils/MemoryOpRemark.h" #include #include @@ -2067,12 +2068,12 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID, auto &TLI = *MF->getSubtarget().getTargetLowering(); Value *Ptr = CI.getArgOperand(0); unsigned ListSize = TLI.getVaListSizeInBits(*DL) / 8; + Align Alignment = getKnownAlignment(Ptr, *DL); - // FIXME: Get alignment MIRBuilder.buildInstr(TargetOpcode::G_VASTART, {}, {getOrCreateVReg(*Ptr)}) .addMemOperand(MF->getMachineMemOperand(MachinePointerInfo(Ptr), MachineMemOperand::MOStore, - ListSize, Align(1))); + ListSize, Alignment)); return true; } case Intrinsic::dbg_value: { diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll index 90032372bd46..3e7eb15a22a2 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll @@ -27,7 +27,7 @@ define void @testVaCopyArg(ptr %fmt, ...) { ; MIPS32-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.2.aq ; MIPS32-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.3.s ; MIPS32-NEXT: G_STORE [[COPY]](p0), [[FRAME_INDEX3]](p0) :: (store (p0) into %ir.fmt.addr) - ; MIPS32-NEXT: G_VASTART [[FRAME_INDEX4]](p0) :: (store (s32) into %ir.ap, align 1) + ; MIPS32-NEXT: G_VASTART [[FRAME_INDEX4]](p0) :: (store (s32) into %ir.ap) ; MIPS32-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.va_copy), [[FRAME_INDEX5]](p0), [[FRAME_INDEX4]](p0) ; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX5]](p0) :: (dereferenceable load (p0) from %ir.aq) ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 -- GitLab From a37c69ec315b9526a3532022be3ebe1af9ca356a Mon Sep 17 00:00:00 2001 From: Brad Smith Date: Thu, 30 Nov 2023 23:14:46 -0500 Subject: [PATCH 089/699] [lldb] Remove pre GCC 4.8 workaround (#73981) The minimum GCC version was bumped up from 4.8 to 5.1 and then even newer awhile ago so garbage collect the pre 4.8 workaround. https://reviews.llvm.org/D66188 --- lldb/source/Host/common/Host.cpp | 4 ---- 1 file changed, 4 deletions(-) diff --git a/lldb/source/Host/common/Host.cpp b/lldb/source/Host/common/Host.cpp index 49eac0b0fa7b..8314d3581f6a 100644 --- a/lldb/source/Host/common/Host.cpp +++ b/lldb/source/Host/common/Host.cpp @@ -133,11 +133,7 @@ private: #endif // __linux__ #ifdef __linux__ -#if defined(__GNUC__) && (__GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 8)) -static __thread volatile sig_atomic_t g_usr1_called; -#else static thread_local volatile sig_atomic_t g_usr1_called; -#endif static void SigUsr1Handler(int) { g_usr1_called = 1; } #endif // __linux__ -- GitLab From 4483cf2d8b294aa8718b5488f2033675895369da Mon Sep 17 00:00:00 2001 From: ShatianWang <38512325+ShatianWang@users.noreply.github.com> Date: Thu, 30 Nov 2023 23:17:11 -0500 Subject: [PATCH 090/699] [BOLT] CDSplit main logic part 2/2 (#74032) This diff implements the main splitting logic of CDSplit. CDSplit processes functions in a binary in parallel. For each function BF, it assumes that all other functions are hot-cold split. For each possible hot-warm split point of BF, it computes its corresponding SplitScore, and chooses the split point with the best SplitScore. The SplitScore of each split point is computed in the following way: each call edge or jump edge has an edge score that is proportional to its execution count, and inversely proportional to its distance. The SplitScore of a split point is a sum of edge scores over a fixed set of edges whose distance can change due to hot-warm splitting BF. This set contains all cover calls in the form of X->Y or Y->X given function order [... X ... BF ... Y ...]; we refer to the sum of edge scores over the set of cover calls as CoverCallScore. This set also contains all jump edges (branches) within BF as well as all call edges originated from BF; we refer to the sum of edge scores over this set of edges as LocalScore. CDSplit finds the split index maximizing CoverCallScore + LocalScore. --- bolt/lib/Passes/SplitFunctions.cpp | 203 ++++++++++++++++++++++++++- bolt/test/X86/cdsplit-call-scale.s | 137 ++++++++++++++++++ bolt/test/X86/cdsplit-symbol-names.s | 147 +++++++++++++++++++ 3 files changed, 484 insertions(+), 3 deletions(-) create mode 100644 bolt/test/X86/cdsplit-call-scale.s create mode 100644 bolt/test/X86/cdsplit-symbol-names.s diff --git a/bolt/lib/Passes/SplitFunctions.cpp b/bolt/lib/Passes/SplitFunctions.cpp index f8c5360495be..836f19de8c87 100644 --- a/bolt/lib/Passes/SplitFunctions.cpp +++ b/bolt/lib/Passes/SplitFunctions.cpp @@ -114,6 +114,16 @@ static cl::opt CallScale( "call-scale", cl::desc("Call score scale coefficient (when --split-strategy=cdsplit)"), cl::init(0.95), cl::ReallyHidden, cl::cat(BoltOptCategory)); + +static cl::opt + CallPower("call-power", + cl::desc("Call score power (when --split-strategy=cdsplit)"), + cl::init(0.05), cl::ReallyHidden, cl::cat(BoltOptCategory)); + +static cl::opt + JumpPower("jump-power", + cl::desc("Jump score power (when --split-strategy=cdsplit)"), + cl::init(0.15), cl::ReallyHidden, cl::cat(BoltOptCategory)); } // namespace opts namespace { @@ -195,6 +205,13 @@ private: size_t Count; }; + struct SplitScore { + size_t SplitIndex; + size_t HotSizeReduction = 0; + double LocalScore = 0; + double CoverCallScore = 0; + }; + // Auxiliary variables used by the algorithm. size_t TotalNumBlocks{0}; size_t OrigHotSectionSize{0}; @@ -340,8 +357,9 @@ private: // We only care about new addresses of blocks in hot/warm. if (BB->getFragmentNum() == FragmentNum::cold()) break; + const size_t NewSize = BB->getOutputSize(); BB->setOutputStartAddress(CurrentAddr); - CurrentAddr += BB->getOutputSize(); + CurrentAddr += NewSize; BB->setOutputEndAddress(CurrentAddr); if (BB->getLayoutIndex() == SplitIndex) { NewHotEndAddr = CurrentAddr; @@ -402,13 +420,192 @@ private: return CoverCalls; } + /// Compute the edge score of a call edge. + double computeCallScore(uint64_t CallCount, size_t CallLength) { + // Increase call lengths by 1 to avoid raising 0 to a negative power. + return opts::CallScale * static_cast(CallCount) / + std::pow(static_cast(CallLength + 1), opts::CallPower); + } + + /// Compute the edge score of a jump (branch) edge. + double computeJumpScore(uint64_t JumpCount, size_t JumpLength) { + // Increase jump lengths by 1 to avoid raising 0 to a negative power. + return static_cast(JumpCount) / + std::pow(static_cast(JumpLength + 1), opts::JumpPower); + } + + /// Compute sum of scores over jumps within \p BlockOrder given \p SplitIndex. + /// Increament Score.LocalScore in place by the sum. + void computeJumpScore(const BasicBlockOrder &BlockOrder, + const size_t SplitIndex, SplitScore &Score) { + + for (const BinaryBasicBlock *SrcBB : BlockOrder) { + if (SrcBB->getKnownExecutionCount() == 0) + continue; + + const size_t SrcBBEndAddr = SrcBB->getOutputAddressRange().second; + + for (const auto Pair : zip(SrcBB->successors(), SrcBB->branch_info())) { + const BinaryBasicBlock *DstBB = std::get<0>(Pair); + const BinaryBasicBlock::BinaryBranchInfo &Branch = std::get<1>(Pair); + const size_t JumpCount = Branch.Count; + + if (JumpCount == 0) + continue; + + const size_t DstBBStartAddr = DstBB->getOutputAddressRange().first; + const size_t NewJumpLength = + AbsoluteDifference(SrcBBEndAddr, DstBBStartAddr); + Score.LocalScore += computeJumpScore(JumpCount, NewJumpLength); + } + } + } + + /// Compute sum of scores over calls originated in the current function + /// given \p SplitIndex. Increament Score.LocalScore in place by the sum. + void computeLocalCallScore(const BasicBlockOrder &BlockOrder, + const size_t SplitIndex, SplitScore &Score) { + if (opts::CallScale == 0) + return; + + // Global index of the last block in the current function. + // This is later used to determine whether a call originated in the current + // function is to a function that comes after the current function. + const size_t LastGlobalIndex = GlobalIndices[BlockOrder.back()]; + + // The length of calls originated in the input function can increase / + // decrease depending on the splitting decision. + for (const BinaryBasicBlock *SrcBB : BlockOrder) { + const size_t CallCount = SrcBB->getKnownExecutionCount(); + // If SrcBB does not call any functions, skip it. + if (CallCount == 0) + continue; + + // Obtain an estimate on the end address of the src basic block + // after splitting at SplitIndex. + const size_t SrcBBEndAddr = SrcBB->getOutputAddressRange().second; + + for (const BinaryBasicBlock *DstBB : Callees[GlobalIndices[SrcBB]]) { + // Obtain an estimate on the start address of the dst basic block + // after splitting at SplitIndex. If DstBB is in a function before + // the current function, then its start address remains unchanged. + size_t DstBBStartAddr = BBOffsets[DstBB]; + // If DstBB is in a function after the current function, then its + // start address should be adjusted based on the reduction in hot size. + if (GlobalIndices[DstBB] > LastGlobalIndex) { + assert(DstBBStartAddr >= Score.HotSizeReduction); + DstBBStartAddr -= Score.HotSizeReduction; + } + const size_t NewCallLength = + AbsoluteDifference(SrcBBEndAddr, DstBBStartAddr); + Score.LocalScore += computeCallScore(CallCount, NewCallLength); + } + } + } + + /// Compute sum of splitting scores for cover calls of the input function. + /// Increament Score.CoverCallScore in place by the sum. + void computeCoverCallScore(const BasicBlockOrder &BlockOrder, + const size_t SplitIndex, + const std::vector &CoverCalls, + SplitScore &Score) { + if (opts::CallScale == 0) + return; + + for (const CallInfo CI : CoverCalls) { + assert(CI.Length >= Score.HotSizeReduction && + "Length of cover calls must exceed reduced size of hot fragment."); + // Compute the new length of the call, which is shorter than the original + // one by the size of the splitted fragment minus the total size increase. + const size_t NewCallLength = CI.Length - Score.HotSizeReduction; + Score.CoverCallScore += computeCallScore(CI.Count, NewCallLength); + } + } + + /// Compute the split score of splitting a function at a given index. + /// The split score consists of local score and cover score. Cover call score + /// is expensive to compute. As a result, we pass in a \p ReferenceScore and + /// compute cover score only when the local score exceeds that in the + /// ReferenceScore or that the size reduction of the hot fragment is larger + /// than that achieved by the split index of the ReferenceScore. This function + /// returns \p Score of SplitScore type. It contains the local score and cover + /// score (if computed) of the current splitting index. For easier book + /// keeping and comparison, it also stores the split index and the resulting + /// reduction in hot fragment size. + SplitScore computeSplitScore(const BinaryFunction &BF, + const BasicBlockOrder &BlockOrder, + const size_t SplitIndex, + const std::vector &CoverCalls, + const SplitScore &ReferenceScore) { + // Populate BinaryBasicBlock::OutputAddressRange with estimated + // new start and end addresses after hot-warm splitting at SplitIndex. + size_t OldHotEnd; + size_t NewHotEnd; + std::tie(OldHotEnd, NewHotEnd) = + estimatePostSplitBBAddress(BlockOrder, SplitIndex); + + SplitScore Score; + Score.SplitIndex = SplitIndex; + + // It's not worth splitting if OldHotEnd < NewHotEnd. + if (OldHotEnd < NewHotEnd) + return Score; + + // Hot fragment size reduction due to splitting. + Score.HotSizeReduction = OldHotEnd - NewHotEnd; + + // First part of LocalScore is the sum over call edges originated in the + // input function. These edges can get shorter or longer depending on + // SplitIndex. Score.LocalScore is increamented in place. + computeLocalCallScore(BlockOrder, SplitIndex, Score); + + // Second part of LocalScore is the sum over jump edges with src basic block + // and dst basic block in the current function. Score.LocalScore is + // increamented in place. + computeJumpScore(BlockOrder, SplitIndex, Score); + + // There is no need to compute CoverCallScore if we have already found + // another split index with a bigger LocalScore and bigger HotSizeReduction. + if (Score.LocalScore <= ReferenceScore.LocalScore && + Score.HotSizeReduction <= ReferenceScore.HotSizeReduction) + return Score; + + // Compute CoverCallScore and store in Score in place. + computeCoverCallScore(BlockOrder, SplitIndex, CoverCalls, Score); + return Score; + } + /// Find the best index for splitting. The returned value is the index of the /// last hot basic block. Hence, "no splitting" is equivalent to returning the /// value which is one less than the size of the function. size_t findSplitIndex(const BinaryFunction &BF, const BasicBlockOrder &BlockOrder) { - // Placeholder: hot-warm split after entry block. - return 0; + // Find all function calls that can be shortened if we move blocks of the + // current function to warm/cold + const std::vector CoverCalls = extractCoverCalls(BF); + + // Try all possible split indices (blocks with Index <= SplitIndex are in + // hot) and find the one maximizing the splitting score. + SplitScore BestScore; + double BestScoreSum = -1.0; + SplitScore ReferenceScore; + for (size_t Index = 0; Index < BlockOrder.size(); Index++) { + const BinaryBasicBlock *LastHotBB = BlockOrder[Index]; + // No need to keep cold blocks in the hot section. + if (LastHotBB->getFragmentNum() == FragmentNum::cold()) + break; + const SplitScore Score = + computeSplitScore(BF, BlockOrder, Index, CoverCalls, ReferenceScore); + double ScoreSum = Score.LocalScore + Score.CoverCallScore; + if (ScoreSum > BestScoreSum) { + BestScoreSum = ScoreSum; + BestScore = Score; + } + if (Score.LocalScore > ReferenceScore.LocalScore) + ReferenceScore = Score; + } + + return BestScore.SplitIndex; } }; diff --git a/bolt/test/X86/cdsplit-call-scale.s b/bolt/test/X86/cdsplit-call-scale.s new file mode 100644 index 000000000000..5b4f92832624 --- /dev/null +++ b/bolt/test/X86/cdsplit-call-scale.s @@ -0,0 +1,137 @@ +# Test the control of aggressiveness of 3-way splitting by -call-scale. +# When -call-scale=0.0, the tested function is 2-way splitted. +# When -call-scale=1.0, the tested function is 3-way splitted with 5 blocks +# in warm because of the increased benefit of shortening the call edges. +# When -call-scale=1000.0, the tested function is 3-way splitted with 7 blocks +# in warm because of the strong benefit of shortening the call edges. + +# RUN: llvm-mc --filetype=obj --triple x86_64-unknown-unknown %s -o %t.o +# RUN: link_fdata %s %t.o %t.fdata +# RUN: llvm-strip --strip-unneeded %t.o +# RUN: %clang %cflags %t.o -o %t.exe -Wl,-q +# RUN: llvm-bolt %t.exe -o %t.bolt --split-functions --split-strategy=cdsplit \ +# RUN: --call-scale=0.0 --print-split --print-only=chain \ +# RUN: --data=%t.fdata --reorder-blocks=ext-tsp \ +# RUN: 2>&1 | FileCheck --check-prefix=LOWINCENTIVE %s +# RUN: llvm-bolt %t.exe -o %t.bolt --split-functions --split-strategy=cdsplit \ +# RUN: --call-scale=1.0 --print-split --print-only=chain \ +# RUN: --data=%t.fdata --reorder-blocks=ext-tsp \ +# RUN: 2>&1 | FileCheck --check-prefix=MEDINCENTIVE %s +# RUN: llvm-bolt %t.exe -o %t.bolt --split-functions --split-strategy=cdsplit \ +# RUN: --call-scale=1000.0 --print-split --print-only=chain \ +# RUN: --data=%t.fdata --reorder-blocks=ext-tsp \ +# RUN: 2>&1 | FileCheck --check-prefix=HIGHINCENTIVE %s + +# LOWINCENTIVE: Binary Function "chain" after split-functions +# LOWINCENTIVE: {{^\.Ltmp5}} +# LOWINCENTIVE: ------- HOT-COLD SPLIT POINT ------- +# LOWINCENTIVE: {{^\.LFT1}} + +# MEDINCENTIVE: Binary Function "chain" after split-functions +# MEDINCENTIVE: {{^\.Ltmp1}} +# MEDINCENTIVE: ------- HOT-COLD SPLIT POINT ------- +# MEDINCENTIVE: {{^\.LFT1}} +# MEDINCENTIVE: ------- HOT-COLD SPLIT POINT ------- +# MEDINCENTIVE: {{^\.Ltmp0}} +# MEDINCENTIVE: {{^\.Ltmp2}} +# MEDINCENTIVE: {{^\.Ltmp3}} +# MEDINCENTIVE: {{^\.Ltmp4}} +# MEDINCENTIVE: {{^\.Ltmp5}} + +# HIGHINCENTIVE: Binary Function "chain" after split-functions +# HIGHINCENTIVE: {{^\.LBB00}} +# HIGHINCENTIVE: ------- HOT-COLD SPLIT POINT ------- +# HIGHINCENTIVE: {{^\.LFT1}} +# HIGHINCENTIVE: ------- HOT-COLD SPLIT POINT ------- +# HIGHINCENTIVE: {{^\.LFT0}} +# HIGHINCENTIVE: {{^\.Ltmp1}} +# HIGHINCENTIVE: {{^\.Ltmp0}} +# HIGHINCENTIVE: {{^\.Ltmp2}} +# HIGHINCENTIVE: {{^\.Ltmp3}} +# HIGHINCENTIVE: {{^\.Ltmp4}} +# HIGHINCENTIVE: {{^\.Ltmp5}} + + + + .text + .globl chain + .type chain, @function +chain: + pushq %rbp + movq %rsp, %rbp + cmpl $2, %edi +LLentry_LLchain_start: + jge LLchain_start +# FDATA: 1 chain #LLentry_LLchain_start# 1 chain #LLchain_start# 0 10 +# FDATA: 1 chain #LLentry_LLchain_start# 1 chain #LLfast# 0 500 +LLfast: + movl $5, %eax +LLfast_LLexit: + jmp LLexit +# FDATA: 1 chain #LLfast_LLexit# 1 chain #LLexit# 0 500 +LLchain_start: + movl $10, %eax +LLchain_start_LLchain1: + jge LLchain1 +# FDATA: 1 chain #LLchain_start_LLchain1# 1 chain #LLchain1# 0 10 +# FDATA: 1 chain #LLchain_start_LLchain1# 1 chain #LLcold# 0 0 +LLcold: + addl $1, %eax + addl $1, %eax + addl $1, %eax + addl $1, %eax + addl $1, %eax + addl $1, %eax +LLchain1: + addl $1, %eax +LLchain1_LLchain2: + jmp LLchain2 +# FDATA: 1 chain #LLchain1_LLchain2# 1 chain #LLchain2# 0 10 +LLchain2: + addl $1, %eax +LLchain2_LLchain3: + jmp LLchain3 +# FDATA: 1 chain #LLchain2_LLchain3# 1 chain #LLchain3# 0 10 +LLchain3: + addl $1, %eax + addl $1, %eax + addl $1, %eax + addl $1, %eax + addl $1, %eax +LLchain3_LLchain4: + jmp LLchain4 +# FDATA: 1 chain #LLchain3_LLchain4# 1 chain #LLchain4# 0 10 +LLchain4: + addl $1, %eax + addl $1, %eax + addl $1, %eax + addl $1, %eax + addl $1, %eax +LLchain4_LLexit: + jmp LLexit +# FDATA: 1 chain #LLchain4_LLexit# 1 chain #LLexit# 0 10 +LLexit: + popq %rbp + ret +LLchain_end: + .size chain, LLchain_end-chain + + + .globl main + .type main, @function +main: + pushq %rbp + movq %rsp, %rbp + movl $1, %edi +LLmain_chain1: + call chain +# FDATA: 1 main #LLmain_chain1# 1 chain 0 0 500 + movl $4, %edi +LLmain_chain2: + call chain +# FDATA: 1 main #LLmain_chain2# 1 chain 0 0 10 + xorl %eax, %eax + popq %rbp + retq +.Lmain_end: + .size main, .Lmain_end-main diff --git a/bolt/test/X86/cdsplit-symbol-names.s b/bolt/test/X86/cdsplit-symbol-names.s new file mode 100644 index 000000000000..e2259276e255 --- /dev/null +++ b/bolt/test/X86/cdsplit-symbol-names.s @@ -0,0 +1,147 @@ +# Test the correctness of section names and function symbol names post cdsplit. +# Warm section should have name .text.warm and warm function fragments should +# have symbol names ending in warm. + +# RUN: llvm-mc --filetype=obj --triple x86_64-unknown-unknown %s -o %t.o +# RUN: link_fdata %s %t.o %t.fdata +# RUN: llvm-strip --strip-unneeded %t.o +# RUN: %clang %cflags %t.o -o %t.exe -Wl,-q +# RUN: llvm-bolt %t.exe -o %t.bolt --split-functions --split-strategy=cdsplit \ +# RUN: --call-scale=2 --data=%t.fdata --reorder-blocks=ext-tsp +# RUN: llvm-objdump --syms %t.bolt | FileCheck %s --check-prefix=CHECK-SYMS-WARM + +# CHECK-SYMS-WARM: .text.warm +# CHECK-SYMS-WARM-SAME: chain.warm +# CHECK-SYMS-WARM: .text.cold +# CHECK-SYMS-WARM-SAME: dummy.cold + + .text + .globl chain + .type chain, @function +chain: + pushq %rbp + movq %rsp, %rbp + cmpl $2, %edi +LLentry_LLchain_start: + jge LLchain_start +# FDATA: 1 chain #LLentry_LLchain_start# 1 chain #LLchain_start# 0 100 +# FDATA: 1 chain #LLentry_LLchain_start# 1 chain #LLfast# 0 500 +LLfast: + movl $5, %eax +LLfast_LLexit: + jmp LLexit +# FDATA: 1 chain #LLfast_LLexit# 1 chain #LLexit# 0 500 +LLchain_start: + movl $10, %eax +LLchain_start_LLchain1: + jge LLchain1 +# FDATA: 1 chain #LLchain_start_LLchain1# 1 chain #LLchain1# 0 99 +# FDATA: 1 chain #LLchain_start_LLchain1# 1 chain #LLloop_entry# 0 1 +LLloop_entry: + addl $1, %eax + addl $1, %eax + addl $1, %eax + addl $1, %eax + xorl %eax, %eax // Initialize result + movl $1000000, %ecx // Set loop counter to a large value +LLloop_entry_LLloop_start: + jmp LLloop_start +# FDATA: 1 chain #LLloop_entry_LLloop_start# 1 chain #LLloop_start# 0 1 +LLloop_start: + addl $1, %eax // Increment result + subl $1, %ecx // Decrement loop counter +LLloop_start_LLloop_start: + jg LLloop_start // Jump if loop counter is greater than 0 +# FDATA: 1 chain #LLloop_start_LLloop_start# 1 chain #LLloop_start# 0 1000000 +# FDATA: 1 chain #LLloop_start_LLloop_start# 1 chain #LLchain1# 0 1 +LLchain1: + addl $1, %eax +LLchain1_LLchain2: + jmp LLchain2 +# FDATA: 1 chain #LLchain1_LLchain2# 1 chain #LLchain2# 0 100 +LLchain2: + addl $1, %eax +LLchain2_LLchain3: + jmp LLchain3 +# FDATA: 1 chain #LLchain2_LLchain3# 1 chain #LLchain3# 0 100 +LLchain3: + addl $1, %eax + addl $1, %eax + addl $1, %eax + addl $1, %eax + addl $1, %eax +LLchain3_LLchain4: + jmp LLchain4 +# FDATA: 1 chain #LLchain3_LLchain4# 1 chain #LLchain4# 0 100 +LLchain4: + addl $1, %eax + addl $1, %eax + addl $1, %eax + addl $1, %eax + addl $1, %eax +LLchain4_LLexit: + jmp LLexit +# FDATA: 1 chain #LLchain4_LLexit# 1 chain #LLexit# 0 100 +LLexit: + popq %rbp + ret +LLchain_end: + .size chain, LLchain_end-chain + + .text + .globl dummy + .type dummy, @function +dummy: + pushq %rbp + movq %rsp, %rbp + cmpl $2, %edi +dummy_dummy_block1: + jg dummy_block1 +# FDATA: 1 dummy #dummy_dummy_block1# 1 dummy #dummy_block1# 0 0 +# FDATA: 1 dummy #dummy_dummy_block1# 1 dummy #dummy_next# 0 100 +dummy_next: + addl $1, %eax + addl $1, %eax +dummy_next_dummy_exit: + jmp dummy_exit +# FDATA: 1 dummy #dummy_next_dummy_exit# 1 dummy #dummy_exit# 0 100 +dummy_block1: + addl $1, %eax + addl $1, %eax + addl $1, %eax + addl $1, %eax + addl $1, %eax +dummy_block1_dummy_block2: + jmp dummy_block2 +# FDATA: 1 dummy #dummy_block1_dummy_block2# 1 dummy #dummy_block2# 0 0 +dummy_block2: + addl $1, %eax + addl $1, %eax + addl $1, %eax + addl $1, %eax + addl $1, %eax +dummy_block2_dummy_exit: + jmp dummy_exit +# FDATA: 1 dummy #dummy_block2_dummy_exit# 1 dummy #dummy_exit# 0 0 +dummy_exit: + popq %rbp + ret + + .globl main + .type main, @function +main: + pushq %rbp + movq %rsp, %rbp + movl $1, %edi +LLmain_chain1: + call chain +# FDATA: 1 main #LLmain_chain1# 1 chain 0 0 600 + movl $4, %edi +LLmain_dummy: + call dummy +# FDATA: 1 main #LLmain_dummy# 1 dummy 0 0 100 + xorl %eax, %eax + popq %rbp + retq +.Lmain_end: + .size main, .Lmain_end-main -- GitLab From 5c60e2ce78e79c2d15152e08d9e28fcf3a1d4e51 Mon Sep 17 00:00:00 2001 From: Owen Pan Date: Thu, 30 Nov 2023 20:07:27 -0800 Subject: [PATCH 091/699] [clang-format][NFC] Reformat source code with clang-format style --- clang/include/clang/Format/.clang-format | 6 +----- clang/lib/Format/.clang-format | 6 +----- clang/lib/Format/UnwrappedLineParser.cpp | 3 +-- clang/tools/clang-format/.clang-format | 6 +----- clang/tools/clang-format/ClangFormat.cpp | 3 +-- clang/unittests/Format/.clang-format | 6 +----- 6 files changed, 6 insertions(+), 24 deletions(-) diff --git a/clang/include/clang/Format/.clang-format b/clang/include/clang/Format/.clang-format index 63d45e0307a3..d7331b3c8cf0 100644 --- a/clang/include/clang/Format/.clang-format +++ b/clang/include/clang/Format/.clang-format @@ -1,5 +1 @@ -BasedOnStyle: LLVM -InsertBraces: true -InsertNewlineAtEOF: true -LineEnding: LF -RemoveBracesLLVM: true +BasedOnStyle: clang-format diff --git a/clang/lib/Format/.clang-format b/clang/lib/Format/.clang-format index 63d45e0307a3..d7331b3c8cf0 100644 --- a/clang/lib/Format/.clang-format +++ b/clang/lib/Format/.clang-format @@ -1,5 +1 @@ -BasedOnStyle: LLVM -InsertBraces: true -InsertNewlineAtEOF: true -LineEnding: LF -RemoveBracesLLVM: true +BasedOnStyle: clang-format diff --git a/clang/lib/Format/UnwrappedLineParser.cpp b/clang/lib/Format/UnwrappedLineParser.cpp index 9a9a16a3caac..57126b8dfeac 100644 --- a/clang/lib/Format/UnwrappedLineParser.cpp +++ b/clang/lib/Format/UnwrappedLineParser.cpp @@ -47,8 +47,7 @@ void printLine(llvm::raw_ostream &OS, const UnwrappedLine &Line, OS << Prefix; NewLine = false; } - OS << I->Tok->Tok.getName() << "[" - << "T=" << (unsigned)I->Tok->getType() + OS << I->Tok->Tok.getName() << "[" << "T=" << (unsigned)I->Tok->getType() << ", OC=" << I->Tok->OriginalColumn << ", \"" << I->Tok->TokenText << "\"] "; for (SmallVectorImpl::const_iterator diff --git a/clang/tools/clang-format/.clang-format b/clang/tools/clang-format/.clang-format index 63d45e0307a3..d7331b3c8cf0 100644 --- a/clang/tools/clang-format/.clang-format +++ b/clang/tools/clang-format/.clang-format @@ -1,5 +1 @@ -BasedOnStyle: LLVM -InsertBraces: true -InsertNewlineAtEOF: true -LineEnding: LF -RemoveBracesLLVM: true +BasedOnStyle: clang-format diff --git a/clang/tools/clang-format/ClangFormat.cpp b/clang/tools/clang-format/ClangFormat.cpp index cb6e7460a66e..829f85b93bc7 100644 --- a/clang/tools/clang-format/ClangFormat.cpp +++ b/clang/tools/clang-format/ClangFormat.cpp @@ -330,8 +330,7 @@ static void outputReplacementXML(StringRef Text) { static void outputReplacementsXML(const Replacements &Replaces) { for (const auto &R : Replaces) { - outs() << ""; outputReplacementXML(R.getReplacementText()); outs() << "\n"; diff --git a/clang/unittests/Format/.clang-format b/clang/unittests/Format/.clang-format index 63d45e0307a3..d7331b3c8cf0 100644 --- a/clang/unittests/Format/.clang-format +++ b/clang/unittests/Format/.clang-format @@ -1,5 +1 @@ -BasedOnStyle: LLVM -InsertBraces: true -InsertNewlineAtEOF: true -LineEnding: LF -RemoveBracesLLVM: true +BasedOnStyle: clang-format -- GitLab From 54878b80f3e332f3420132f8b4c74412fc29ef6b Mon Sep 17 00:00:00 2001 From: Schrodinger ZHU Yifan Date: Thu, 30 Nov 2023 23:35:35 -0500 Subject: [PATCH 092/699] [libc] remove fragile test from mincore (#74026) --- libc/test/src/sys/mman/linux/mincore_test.cpp | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/libc/test/src/sys/mman/linux/mincore_test.cpp b/libc/test/src/sys/mman/linux/mincore_test.cpp index 655fd8631af8..1b0ed157483e 100644 --- a/libc/test/src/sys/mman/linux/mincore_test.cpp +++ b/libc/test/src/sys/mman/linux/mincore_test.cpp @@ -41,23 +41,13 @@ static char *aligned_addr(void *addr, size_t alignment) { TEST(LlvmLibcMincoreTest, InvalidVec) { size_t page_size = static_cast(LIBC_NAMESPACE::sysconf(_SC_PAGESIZE)); - void *addr = LIBC_NAMESPACE::mmap(nullptr, 5 * page_size, PROT_READ, + void *addr = LIBC_NAMESPACE::mmap(nullptr, page_size, PROT_READ, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); EXPECT_NE(addr, MAP_FAILED); - // Since we allocated 5 pages, we can find an aligned boundary after which - // there are at least 4 pages char *aligned = aligned_addr(addr, page_size); - libc_errno = 0; int res = LIBC_NAMESPACE::mincore(aligned, 1, nullptr); EXPECT_THAT(res, Fails(EFAULT, -1)); - void *area = LIBC_NAMESPACE::mmap(nullptr, page_size, PROT_READ | PROT_WRITE, - MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); - EXPECT_NE(area, MAP_FAILED); - unsigned char *ptr = static_cast(area) + page_size - 3; - res = LIBC_NAMESPACE::mincore(aligned, 4 * page_size, ptr); - EXPECT_THAT(res, Fails(EFAULT, -1)); - EXPECT_THAT(LIBC_NAMESPACE::munmap(addr, 5 * page_size), Succeeds()); - EXPECT_THAT(LIBC_NAMESPACE::munmap(area, page_size), Succeeds()); + EXPECT_THAT(LIBC_NAMESPACE::munmap(addr, page_size), Succeeds()); } TEST(LlvmLibcMincoreTest, UnalignedAddr) { -- GitLab From 3bd517205799a152689434ceddf9493765f1e883 Mon Sep 17 00:00:00 2001 From: paperchalice Date: Fri, 1 Dec 2023 12:55:05 +0800 Subject: [PATCH 093/699] Reland "[CodeGen] Port SafeStack to new pass manager (#74027) Forgot to update related code in `CodeGenPassBuilder.h`, also update it for `CallBrPreparePass`. Fix build when `LLVM_ENABLE_MODULES:BOOL=ON`. --- .../include/llvm/CodeGen/CodeGenPassBuilder.h | 6 ++- .../llvm/CodeGen/MachinePassRegistry.def | 4 +- llvm/include/llvm/CodeGen/SafeStack.h | 28 ++++++++++++++ llvm/lib/CodeGen/SafeStack.cpp | 37 +++++++++++++++++++ llvm/lib/Passes/PassBuilder.cpp | 1 + llvm/lib/Passes/PassRegistry.def | 1 + llvm/test/Transforms/SafeStack/AArch64/abi.ll | 1 + .../Transforms/SafeStack/AArch64/abi_ssp.ll | 2 + .../SafeStack/AArch64/unreachable.ll | 1 + llvm/test/Transforms/SafeStack/ARM/abi.ll | 1 + llvm/test/Transforms/SafeStack/ARM/debug.ll | 1 + llvm/test/Transforms/SafeStack/ARM/setjmp.ll | 1 + llvm/test/Transforms/SafeStack/X86/abi.ll | 4 ++ llvm/test/Transforms/SafeStack/X86/abi_ssp.ll | 11 ++++++ .../Transforms/SafeStack/X86/addr-taken.ll | 2 + .../Transforms/SafeStack/X86/array-aligned.ll | 2 + llvm/test/Transforms/SafeStack/X86/array.ll | 2 + llvm/test/Transforms/SafeStack/X86/byval.ll | 2 + llvm/test/Transforms/SafeStack/X86/call.ll | 2 + llvm/test/Transforms/SafeStack/X86/cast.ll | 2 + .../Transforms/SafeStack/X86/coloring-ssp.ll | 1 + .../test/Transforms/SafeStack/X86/coloring.ll | 2 + .../Transforms/SafeStack/X86/coloring2.ll | 2 + .../SafeStack/X86/constant-gep-call.ll | 2 + .../Transforms/SafeStack/X86/constant-gep.ll | 2 + .../Transforms/SafeStack/X86/constant-geps.ll | 2 + .../SafeStack/X86/debug-loc-dynamic.ll | 2 + .../Transforms/SafeStack/X86/debug-loc.ll | 2 + .../Transforms/SafeStack/X86/debug-loc2.ll | 2 + .../SafeStack/X86/dynamic-alloca.ll | 2 + .../SafeStack/X86/escape-addr-pointer.ll | 2 + .../SafeStack/X86/escape-bitcast-store.ll | 2 + .../SafeStack/X86/escape-bitcast-store2.ll | 2 + .../Transforms/SafeStack/X86/escape-call.ll | 2 + .../SafeStack/X86/escape-casted-pointer.ll | 2 + .../SafeStack/X86/escape-gep-call.ll | 2 + .../SafeStack/X86/escape-gep-invoke.ll | 2 + .../SafeStack/X86/escape-gep-negative.ll | 2 + .../SafeStack/X86/escape-gep-ptrtoint.ll | 2 + .../SafeStack/X86/escape-gep-store.ll | 2 + .../SafeStack/X86/escape-phi-call.ll | 2 + .../SafeStack/X86/escape-select-call.ll | 2 + .../Transforms/SafeStack/X86/escape-vector.ll | 2 + llvm/test/Transforms/SafeStack/X86/invoke.ll | 2 + .../Transforms/SafeStack/X86/layout-frag.ll | 1 + .../SafeStack/X86/layout-region-split.ll | 1 + .../SafeStack/X86/memintrinsic-oob-read.ll | 2 + .../test/Transforms/SafeStack/X86/musttail.ll | 1 + llvm/test/Transforms/SafeStack/X86/no-attr.ll | 2 + .../SafeStack/X86/no-crash-on-lifetime.ll | 1 + .../Transforms/SafeStack/X86/phi-cycle.ll | 2 + llvm/test/Transforms/SafeStack/X86/phi.ll | 2 + llvm/test/Transforms/SafeStack/X86/pr54784.ll | 1 + llvm/test/Transforms/SafeStack/X86/ret.ll | 2 + llvm/test/Transforms/SafeStack/X86/setjmp.ll | 2 + llvm/test/Transforms/SafeStack/X86/setjmp2.ll | 2 + .../Transforms/SafeStack/X86/sink-to-use.ll | 2 + llvm/test/Transforms/SafeStack/X86/ssp.ll | 1 + llvm/test/Transforms/SafeStack/X86/store.ll | 2 + llvm/test/Transforms/SafeStack/X86/struct.ll | 2 + 60 files changed, 180 insertions(+), 4 deletions(-) create mode 100644 llvm/include/llvm/CodeGen/SafeStack.h diff --git a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h index d7739e8bb597..0a12f4210998 100644 --- a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h +++ b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h @@ -22,10 +22,12 @@ #include "llvm/Analysis/ScopedNoAliasAA.h" #include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/Analysis/TypeBasedAliasAnalysis.h" +#include "llvm/CodeGen/CallBrPrepare.h" #include "llvm/CodeGen/ExpandReductions.h" #include "llvm/CodeGen/MachinePassManager.h" #include "llvm/CodeGen/PreISelIntrinsicLowering.h" #include "llvm/CodeGen/ReplaceWithVeclib.h" +#include "llvm/CodeGen/SafeStack.h" #include "llvm/CodeGen/UnreachableBlockElim.h" #include "llvm/IR/PassManager.h" #include "llvm/IR/Verifier.h" @@ -715,10 +717,10 @@ template void CodeGenPassBuilder::addISelPrepare(AddIRPass &addPass) const { derived().addPreISel(addPass); - addPass(CallBrPrepare()); + addPass(CallBrPreparePass()); // Add both the safe stack and the stack protection passes: each of them will // only protect functions that have corresponding attributes. - addPass(SafeStackPass()); + addPass(SafeStackPass(&TM)); addPass(StackProtectorPass()); if (Opt.PrintISelInput) diff --git a/llvm/include/llvm/CodeGen/MachinePassRegistry.def b/llvm/include/llvm/CodeGen/MachinePassRegistry.def index a29269644ea1..47dd8f2cc464 100644 --- a/llvm/include/llvm/CodeGen/MachinePassRegistry.def +++ b/llvm/include/llvm/CodeGen/MachinePassRegistry.def @@ -35,6 +35,8 @@ FUNCTION_ANALYSIS("targetir", TargetIRAnalysis, (std::move(TM.getTargetIRAnalysi #ifndef FUNCTION_PASS #define FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) #endif +FUNCTION_PASS("callbrprepare", CallBrPreparePass, ()) +FUNCTION_PASS("safe-stack", SafeStackPass, (TM)) FUNCTION_PASS("mergeicmps", MergeICmpsPass, ()) FUNCTION_PASS("lower-constant-intrinsics", LowerConstantIntrinsicsPass, ()) FUNCTION_PASS("unreachableblockelim", UnreachableBlockElimPass, ()) @@ -114,7 +116,6 @@ DUMMY_FUNCTION_PASS("dwarfehprepare", DwarfEHPass, ()) DUMMY_FUNCTION_PASS("winehprepare", WinEHPass, ()) DUMMY_FUNCTION_PASS("wasmehprepare", WasmEHPass, ()) DUMMY_FUNCTION_PASS("codegenprepare", CodeGenPreparePass, ()) -DUMMY_FUNCTION_PASS("safe-stack", SafeStackPass, ()) DUMMY_FUNCTION_PASS("stack-protector", StackProtectorPass, ()) DUMMY_FUNCTION_PASS("atomic-expand", AtomicExpandPass, ()) DUMMY_FUNCTION_PASS("interleaved-access", InterleavedAccessPass, ()) @@ -123,7 +124,6 @@ DUMMY_FUNCTION_PASS("cfguard-dispatch", CFGuardDispatchPass, ()) DUMMY_FUNCTION_PASS("cfguard-check", CFGuardCheckPass, ()) DUMMY_FUNCTION_PASS("gc-info-printer", GCInfoPrinterPass, ()) DUMMY_FUNCTION_PASS("select-optimize", SelectOptimizePass, ()) -DUMMY_FUNCTION_PASS("callbrprepare", CallBrPrepare, ()) #undef DUMMY_FUNCTION_PASS #ifndef DUMMY_MODULE_PASS diff --git a/llvm/include/llvm/CodeGen/SafeStack.h b/llvm/include/llvm/CodeGen/SafeStack.h new file mode 100644 index 000000000000..e8f0d141457b --- /dev/null +++ b/llvm/include/llvm/CodeGen/SafeStack.h @@ -0,0 +1,28 @@ +//===--------------------- llvm/CodeGen/SafeStack.h -------------*- C++-*--===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_SAFESTACK_H +#define LLVM_CODEGEN_SAFESTACK_H + +#include "llvm/IR/PassManager.h" + +namespace llvm { + +class TargetMachine; + +class SafeStackPass : public PassInfoMixin { + const TargetMachine *TM; + +public: + explicit SafeStackPass(const TargetMachine *TM_) : TM(TM_) {} + PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM); +}; + +} // namespace llvm + +#endif // LLVM_CODEGEN_SAFESTACK_H diff --git a/llvm/lib/CodeGen/SafeStack.cpp b/llvm/lib/CodeGen/SafeStack.cpp index ef293faa1d06..88db57ad46b9 100644 --- a/llvm/lib/CodeGen/SafeStack.cpp +++ b/llvm/lib/CodeGen/SafeStack.cpp @@ -14,6 +14,7 @@ // //===----------------------------------------------------------------------===// +#include "llvm/CodeGen/SafeStack.h" #include "SafeStackLayout.h" #include "llvm/ADT/APInt.h" #include "llvm/ADT/ArrayRef.h" @@ -927,6 +928,42 @@ public: } // end anonymous namespace +PreservedAnalyses SafeStackPass::run(Function &F, + FunctionAnalysisManager &FAM) { + LLVM_DEBUG(dbgs() << "[SafeStack] Function: " << F.getName() << "\n"); + + if (!F.hasFnAttribute(Attribute::SafeStack)) { + LLVM_DEBUG(dbgs() << "[SafeStack] safestack is not requested" + " for this function\n"); + return PreservedAnalyses::all(); + } + + if (F.isDeclaration()) { + LLVM_DEBUG(dbgs() << "[SafeStack] function definition" + " is not available\n"); + return PreservedAnalyses::all(); + } + + auto *TL = TM->getSubtargetImpl(F)->getTargetLowering(); + if (!TL) + report_fatal_error("TargetLowering instance is required"); + + auto &DL = F.getParent()->getDataLayout(); + + // preserve DominatorTree + auto &DT = FAM.getResult(F); + auto &SE = FAM.getResult(F); + DomTreeUpdater DTU(DT, DomTreeUpdater::UpdateStrategy::Lazy); + + bool Changed = SafeStack(F, *TL, DL, &DTU, SE).run(); + + if (!Changed) + return PreservedAnalyses::all(); + PreservedAnalyses PA; + PA.preserve(); + return PA; +} + char SafeStackLegacyPass::ID = 0; INITIALIZE_PASS_BEGIN(SafeStackLegacyPass, DEBUG_TYPE, diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp index 98a679177c23..dad7a74693cb 100644 --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -77,6 +77,7 @@ #include "llvm/CodeGen/ExpandLargeDivRem.h" #include "llvm/CodeGen/ExpandLargeFpConvert.h" #include "llvm/CodeGen/HardwareLoops.h" +#include "llvm/CodeGen/SafeStack.h" #include "llvm/CodeGen/TypePromotion.h" #include "llvm/IR/DebugInfo.h" #include "llvm/IR/Dominators.h" diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def index 2abc2920264a..e23863a235a1 100644 --- a/llvm/lib/Passes/PassRegistry.def +++ b/llvm/lib/Passes/PassRegistry.def @@ -390,6 +390,7 @@ FUNCTION_PASS("print", UniformityInfoPrinterPass(dbgs())) FUNCTION_PASS("reassociate", ReassociatePass()) FUNCTION_PASS("redundant-dbg-inst-elim", RedundantDbgInstEliminationPass()) FUNCTION_PASS("reg2mem", RegToMemPass()) +FUNCTION_PASS("safe-stack", SafeStackPass(TM)) FUNCTION_PASS("scalarize-masked-mem-intrin", ScalarizeMaskedMemIntrinPass()) FUNCTION_PASS("scalarizer", ScalarizerPass()) FUNCTION_PASS("sccp", SCCPPass()) diff --git a/llvm/test/Transforms/SafeStack/AArch64/abi.ll b/llvm/test/Transforms/SafeStack/AArch64/abi.ll index 18cf49920ace..6d4ca0309682 100644 --- a/llvm/test/Transforms/SafeStack/AArch64/abi.ll +++ b/llvm/test/Transforms/SafeStack/AArch64/abi.ll @@ -1,4 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=aarch64-linux-android < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=aarch64-linux-android < %s -o - | FileCheck %s define void @foo() nounwind uwtable safestack { diff --git a/llvm/test/Transforms/SafeStack/AArch64/abi_ssp.ll b/llvm/test/Transforms/SafeStack/AArch64/abi_ssp.ll index aab2d5dd4a78..282d8c4390b6 100644 --- a/llvm/test/Transforms/SafeStack/AArch64/abi_ssp.ll +++ b/llvm/test/Transforms/SafeStack/AArch64/abi_ssp.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=aarch64-linux-android < %s -o - | FileCheck --check-prefixes=TLS,ANDROID %s ; RUN: opt -safe-stack -S -mtriple=aarch64-unknown-fuchsia < %s -o - | FileCheck --check-prefixes=TLS,FUCHSIA %s +; RUN: opt -passes=safe-stack -S -mtriple=aarch64-linux-android < %s -o - | FileCheck --check-prefixes=TLS,ANDROID %s +; RUN: opt -passes=safe-stack -S -mtriple=aarch64-unknown-fuchsia < %s -o - | FileCheck --check-prefixes=TLS,FUCHSIA %s define void @foo() nounwind uwtable safestack sspreq { entry: diff --git a/llvm/test/Transforms/SafeStack/AArch64/unreachable.ll b/llvm/test/Transforms/SafeStack/AArch64/unreachable.ll index 430c4aa7ae45..23fd3bf9d8f2 100644 --- a/llvm/test/Transforms/SafeStack/AArch64/unreachable.ll +++ b/llvm/test/Transforms/SafeStack/AArch64/unreachable.ll @@ -1,4 +1,5 @@ ; RUN: opt -safe-stack -safe-stack-coloring -S -mtriple=aarch64-linux-android < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -safe-stack-coloring -S -mtriple=aarch64-linux-android < %s -o - | FileCheck %s define void @foo() nounwind uwtable safestack { entry: diff --git a/llvm/test/Transforms/SafeStack/ARM/abi.ll b/llvm/test/Transforms/SafeStack/ARM/abi.ll index be4e2e35f976..5584dedf697e 100644 --- a/llvm/test/Transforms/SafeStack/ARM/abi.ll +++ b/llvm/test/Transforms/SafeStack/ARM/abi.ll @@ -1,4 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=arm-linux-android < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=arm-linux-android < %s -o - | FileCheck %s define void @foo() nounwind uwtable safestack { diff --git a/llvm/test/Transforms/SafeStack/ARM/debug.ll b/llvm/test/Transforms/SafeStack/ARM/debug.ll index 9a61b78d2d96..c38ee62fa6aa 100644 --- a/llvm/test/Transforms/SafeStack/ARM/debug.ll +++ b/llvm/test/Transforms/SafeStack/ARM/debug.ll @@ -1,4 +1,5 @@ ; RUN: opt -safe-stack -safestack-use-pointer-address < %s -S | FileCheck %s +; RUN: opt -passes=safe-stack -safestack-use-pointer-address < %s -S | FileCheck %s target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "armv7-pc-linux-android" diff --git a/llvm/test/Transforms/SafeStack/ARM/setjmp.ll b/llvm/test/Transforms/SafeStack/ARM/setjmp.ll index b86e778aabb1..8da5f3549a4c 100644 --- a/llvm/test/Transforms/SafeStack/ARM/setjmp.ll +++ b/llvm/test/Transforms/SafeStack/ARM/setjmp.ll @@ -1,5 +1,6 @@ ; Test stack pointer restore after setjmp() with the function-call safestack ABI. ; RUN: opt -safe-stack -S -mtriple=arm-linux-androideabi < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=arm-linux-androideabi < %s -o - | FileCheck %s @env = global [64 x i32] zeroinitializer, align 4 diff --git a/llvm/test/Transforms/SafeStack/X86/abi.ll b/llvm/test/Transforms/SafeStack/X86/abi.ll index 37d8ea6a67f5..2afee3b2f342 100644 --- a/llvm/test/Transforms/SafeStack/X86/abi.ll +++ b/llvm/test/Transforms/SafeStack/X86/abi.ll @@ -2,6 +2,10 @@ ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s --check-prefix=TLS ; RUN: opt -safe-stack -S -mtriple=i686-linux-android < %s -o - | FileCheck %s --check-prefix=DIRECT-TLS32 ; RUN: opt -safe-stack -S -mtriple=x86_64-linux-android < %s -o - | FileCheck %s --check-prefix=DIRECT-TLS64 +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s --check-prefix=TLS +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s --check-prefix=TLS +; RUN: opt -passes=safe-stack -S -mtriple=i686-linux-android < %s -o - | FileCheck %s --check-prefix=DIRECT-TLS32 +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-linux-android < %s -o - | FileCheck %s --check-prefix=DIRECT-TLS64 define void @foo() nounwind uwtable safestack { diff --git a/llvm/test/Transforms/SafeStack/X86/abi_ssp.ll b/llvm/test/Transforms/SafeStack/X86/abi_ssp.ll index 7cb754999c65..e66127533d38 100644 --- a/llvm/test/Transforms/SafeStack/X86/abi_ssp.ll +++ b/llvm/test/Transforms/SafeStack/X86/abi_ssp.ll @@ -8,6 +8,17 @@ ; RUN: opt -safe-stack -S -mtriple=x86_64-unknown-fuchsia < %s -o - | FileCheck --check-prefixes=COMMON,FUCHSIA64 %s +; RUN: opt -passes=safe-stack -S -mtriple=i686-pc-linux-gnu < %s -o - | FileCheck --check-prefixes=COMMON,TLS32 %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck --check-prefixes=COMMON,TLS64 %s + +; RUN: opt -passes=safe-stack -S -mtriple=i686-linux-android < %s -o - | FileCheck --check-prefixes=COMMON,GLOBAL32 %s +; RUN: opt -passes=safe-stack -S -mtriple=i686-linux-android24 < %s -o - | FileCheck --check-prefixes=COMMON,TLS32 %s + +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-linux-android < %s -o - | FileCheck --check-prefixes=COMMON,TLS64 %s + +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-unknown-fuchsia < %s -o - | FileCheck --check-prefixes=COMMON,FUCHSIA64 %s + + define void @foo() safestack sspreq { entry: ; TLS32: %[[StackGuard:.*]] = load ptr, ptr addrspace(256) inttoptr (i32 20 to ptr addrspace(256)) diff --git a/llvm/test/Transforms/SafeStack/X86/addr-taken.ll b/llvm/test/Transforms/SafeStack/X86/addr-taken.ll index cd9f76217a45..7bbe9f4743d1 100644 --- a/llvm/test/Transforms/SafeStack/X86/addr-taken.ll +++ b/llvm/test/Transforms/SafeStack/X86/addr-taken.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/array-aligned.ll b/llvm/test/Transforms/SafeStack/X86/array-aligned.ll index ed05d387b511..509e50072b99 100644 --- a/llvm/test/Transforms/SafeStack/X86/array-aligned.ll +++ b/llvm/test/Transforms/SafeStack/X86/array-aligned.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/array.ll b/llvm/test/Transforms/SafeStack/X86/array.ll index 2bc57be3dd6a..e773e375529d 100644 --- a/llvm/test/Transforms/SafeStack/X86/array.ll +++ b/llvm/test/Transforms/SafeStack/X86/array.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s ; array [4 x i8] ; Requires protector. diff --git a/llvm/test/Transforms/SafeStack/X86/byval.ll b/llvm/test/Transforms/SafeStack/X86/byval.ll index 761265e279d4..29c6e22b7a27 100644 --- a/llvm/test/Transforms/SafeStack/X86/byval.ll +++ b/llvm/test/Transforms/SafeStack/X86/byval.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/SafeStack/X86/call.ll b/llvm/test/Transforms/SafeStack/X86/call.ll index bb1b46275e1c..9592b33b620b 100644 --- a/llvm/test/Transforms/SafeStack/X86/call.ll +++ b/llvm/test/Transforms/SafeStack/X86/call.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/SafeStack/X86/cast.ll b/llvm/test/Transforms/SafeStack/X86/cast.ll index 41f01c3b576a..629cd61993d3 100644 --- a/llvm/test/Transforms/SafeStack/X86/cast.ll +++ b/llvm/test/Transforms/SafeStack/X86/cast.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/coloring-ssp.ll b/llvm/test/Transforms/SafeStack/X86/coloring-ssp.ll index 032ffd199477..8ff369ef063e 100644 --- a/llvm/test/Transforms/SafeStack/X86/coloring-ssp.ll +++ b/llvm/test/Transforms/SafeStack/X86/coloring-ssp.ll @@ -1,4 +1,5 @@ ; RUN: opt -safe-stack -safe-stack-coloring=1 -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -safe-stack-coloring=1 -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s ; %x and %y share a stack slot between them, but not with the stack guard. define void @f() safestack sspreq { diff --git a/llvm/test/Transforms/SafeStack/X86/coloring.ll b/llvm/test/Transforms/SafeStack/X86/coloring.ll index 37bdccffd0c3..22e1487bdcfc 100644 --- a/llvm/test/Transforms/SafeStack/X86/coloring.ll +++ b/llvm/test/Transforms/SafeStack/X86/coloring.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -safe-stack-coloring=1 -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -safe-stack-coloring=1 -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -safe-stack-coloring=1 -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -safe-stack-coloring=1 -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s define void @f() safestack { entry: diff --git a/llvm/test/Transforms/SafeStack/X86/coloring2.ll b/llvm/test/Transforms/SafeStack/X86/coloring2.ll index b2f59906b603..2e02ea66f9c7 100644 --- a/llvm/test/Transforms/SafeStack/X86/coloring2.ll +++ b/llvm/test/Transforms/SafeStack/X86/coloring2.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -safe-stack-coloring=1 -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -safe-stack-coloring=1 -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -safe-stack-coloring=1 -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -safe-stack-coloring=1 -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s ; x and y share the stack slot. define void @f() safestack { diff --git a/llvm/test/Transforms/SafeStack/X86/constant-gep-call.ll b/llvm/test/Transforms/SafeStack/X86/constant-gep-call.ll index 880471a8a63d..074977b27f66 100644 --- a/llvm/test/Transforms/SafeStack/X86/constant-gep-call.ll +++ b/llvm/test/Transforms/SafeStack/X86/constant-gep-call.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s %struct.nest = type { %struct.pair, %struct.pair } %struct.pair = type { i32, i32 } diff --git a/llvm/test/Transforms/SafeStack/X86/constant-gep.ll b/llvm/test/Transforms/SafeStack/X86/constant-gep.ll index 935c3624e387..88429ca5304e 100644 --- a/llvm/test/Transforms/SafeStack/X86/constant-gep.ll +++ b/llvm/test/Transforms/SafeStack/X86/constant-gep.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s %class.A = type { [2 x i8] } diff --git a/llvm/test/Transforms/SafeStack/X86/constant-geps.ll b/llvm/test/Transforms/SafeStack/X86/constant-geps.ll index fd099db5f943..fe05d0ed17f3 100644 --- a/llvm/test/Transforms/SafeStack/X86/constant-geps.ll +++ b/llvm/test/Transforms/SafeStack/X86/constant-geps.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s %struct.deep = type { %union.anon } %union.anon = type { %struct.anon } diff --git a/llvm/test/Transforms/SafeStack/X86/debug-loc-dynamic.ll b/llvm/test/Transforms/SafeStack/X86/debug-loc-dynamic.ll index b5d862b03b62..42d2aa91307f 100644 --- a/llvm/test/Transforms/SafeStack/X86/debug-loc-dynamic.ll +++ b/llvm/test/Transforms/SafeStack/X86/debug-loc-dynamic.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - --try-experimental-debuginfo-iterators | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - --try-experimental-debuginfo-iterators | FileCheck %s ; Test llvm.dbg.value for dynamic allocas moved onto the unsafe stack. ; In the dynamic alloca case, the dbg.value does not change with the exception diff --git a/llvm/test/Transforms/SafeStack/X86/debug-loc.ll b/llvm/test/Transforms/SafeStack/X86/debug-loc.ll index 41240f7d7a91..9a4df89f37b0 100644 --- a/llvm/test/Transforms/SafeStack/X86/debug-loc.ll +++ b/llvm/test/Transforms/SafeStack/X86/debug-loc.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - --try-experimental-debuginfo-iterators | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - --try-experimental-debuginfo-iterators | FileCheck %s ; Test debug location for the local variables moved onto the unsafe stack. diff --git a/llvm/test/Transforms/SafeStack/X86/debug-loc2.ll b/llvm/test/Transforms/SafeStack/X86/debug-loc2.ll index a7164ef0f45c..915126bc3bbe 100644 --- a/llvm/test/Transforms/SafeStack/X86/debug-loc2.ll +++ b/llvm/test/Transforms/SafeStack/X86/debug-loc2.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - --try-experimental-debuginfo-iterators | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - --try-experimental-debuginfo-iterators | FileCheck %s ; Test llvm.dbg.value for the local variables moved onto the unsafe stack. ; SafeStack rewrites them relative to the unsafe stack pointer (base address of diff --git a/llvm/test/Transforms/SafeStack/X86/dynamic-alloca.ll b/llvm/test/Transforms/SafeStack/X86/dynamic-alloca.ll index d8377781bb6e..a8dec20973ba 100644 --- a/llvm/test/Transforms/SafeStack/X86/dynamic-alloca.ll +++ b/llvm/test/Transforms/SafeStack/X86/dynamic-alloca.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/escape-addr-pointer.ll b/llvm/test/Transforms/SafeStack/X86/escape-addr-pointer.ll index a650ee9661f0..42448fb62024 100644 --- a/llvm/test/Transforms/SafeStack/X86/escape-addr-pointer.ll +++ b/llvm/test/Transforms/SafeStack/X86/escape-addr-pointer.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/escape-bitcast-store.ll b/llvm/test/Transforms/SafeStack/X86/escape-bitcast-store.ll index bde9c3a21964..23a8edf4afce 100644 --- a/llvm/test/Transforms/SafeStack/X86/escape-bitcast-store.ll +++ b/llvm/test/Transforms/SafeStack/X86/escape-bitcast-store.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/escape-bitcast-store2.ll b/llvm/test/Transforms/SafeStack/X86/escape-bitcast-store2.ll index 8dd1233cd023..1a3c8ac215e0 100644 --- a/llvm/test/Transforms/SafeStack/X86/escape-bitcast-store2.ll +++ b/llvm/test/Transforms/SafeStack/X86/escape-bitcast-store2.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/escape-call.ll b/llvm/test/Transforms/SafeStack/X86/escape-call.ll index 9af891e3f62e..1d87cae52683 100644 --- a/llvm/test/Transforms/SafeStack/X86/escape-call.ll +++ b/llvm/test/Transforms/SafeStack/X86/escape-call.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/escape-casted-pointer.ll b/llvm/test/Transforms/SafeStack/X86/escape-casted-pointer.ll index d482f0c8263f..9ca0fd39fbab 100644 --- a/llvm/test/Transforms/SafeStack/X86/escape-casted-pointer.ll +++ b/llvm/test/Transforms/SafeStack/X86/escape-casted-pointer.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/escape-gep-call.ll b/llvm/test/Transforms/SafeStack/X86/escape-gep-call.ll index 759dc5d1cb1a..60e4f91ed61e 100644 --- a/llvm/test/Transforms/SafeStack/X86/escape-gep-call.ll +++ b/llvm/test/Transforms/SafeStack/X86/escape-gep-call.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s %struct.pair = type { i32, i32 } diff --git a/llvm/test/Transforms/SafeStack/X86/escape-gep-invoke.ll b/llvm/test/Transforms/SafeStack/X86/escape-gep-invoke.ll index d09a3d85d39e..db69fbfd38f6 100644 --- a/llvm/test/Transforms/SafeStack/X86/escape-gep-invoke.ll +++ b/llvm/test/Transforms/SafeStack/X86/escape-gep-invoke.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s %struct.pair = type { i32, i32 } diff --git a/llvm/test/Transforms/SafeStack/X86/escape-gep-negative.ll b/llvm/test/Transforms/SafeStack/X86/escape-gep-negative.ll index 896cae962105..96625c5aaad8 100644 --- a/llvm/test/Transforms/SafeStack/X86/escape-gep-negative.ll +++ b/llvm/test/Transforms/SafeStack/X86/escape-gep-negative.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/escape-gep-ptrtoint.ll b/llvm/test/Transforms/SafeStack/X86/escape-gep-ptrtoint.ll index 60783b8d657a..8a38781981af 100644 --- a/llvm/test/Transforms/SafeStack/X86/escape-gep-ptrtoint.ll +++ b/llvm/test/Transforms/SafeStack/X86/escape-gep-ptrtoint.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s %struct.pair = type { i32, i32 } diff --git a/llvm/test/Transforms/SafeStack/X86/escape-gep-store.ll b/llvm/test/Transforms/SafeStack/X86/escape-gep-store.ll index b7dad0eb34ba..a2693ca76702 100644 --- a/llvm/test/Transforms/SafeStack/X86/escape-gep-store.ll +++ b/llvm/test/Transforms/SafeStack/X86/escape-gep-store.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s %struct.pair = type { i32, i32 } diff --git a/llvm/test/Transforms/SafeStack/X86/escape-phi-call.ll b/llvm/test/Transforms/SafeStack/X86/escape-phi-call.ll index 1dd5d6e0d927..57e116834ab0 100644 --- a/llvm/test/Transforms/SafeStack/X86/escape-phi-call.ll +++ b/llvm/test/Transforms/SafeStack/X86/escape-phi-call.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/escape-select-call.ll b/llvm/test/Transforms/SafeStack/X86/escape-select-call.ll index 5d1046ca9660..67b284aa1d1d 100644 --- a/llvm/test/Transforms/SafeStack/X86/escape-select-call.ll +++ b/llvm/test/Transforms/SafeStack/X86/escape-select-call.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/escape-vector.ll b/llvm/test/Transforms/SafeStack/X86/escape-vector.ll index c725ba922cf0..055f558c966e 100644 --- a/llvm/test/Transforms/SafeStack/X86/escape-vector.ll +++ b/llvm/test/Transforms/SafeStack/X86/escape-vector.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s %struct.vec = type { <4 x i32> } diff --git a/llvm/test/Transforms/SafeStack/X86/invoke.ll b/llvm/test/Transforms/SafeStack/X86/invoke.ll index 5385169950cc..23d935eb06ac 100644 --- a/llvm/test/Transforms/SafeStack/X86/invoke.ll +++ b/llvm/test/Transforms/SafeStack/X86/invoke.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/layout-frag.ll b/llvm/test/Transforms/SafeStack/X86/layout-frag.ll index 19c3855bc1cb..b858fd613153 100644 --- a/llvm/test/Transforms/SafeStack/X86/layout-frag.ll +++ b/llvm/test/Transforms/SafeStack/X86/layout-frag.ll @@ -1,5 +1,6 @@ ; Test that safestack layout reuses a region w/o fragmentation. ; RUN: opt -safe-stack -safe-stack-coloring=1 -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -safe-stack-coloring=1 -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s define void @f() safestack { ; CHECK-LABEL: define void @f diff --git a/llvm/test/Transforms/SafeStack/X86/layout-region-split.ll b/llvm/test/Transforms/SafeStack/X86/layout-region-split.ll index 3bee85527f82..b126fdff204f 100644 --- a/llvm/test/Transforms/SafeStack/X86/layout-region-split.ll +++ b/llvm/test/Transforms/SafeStack/X86/layout-region-split.ll @@ -1,5 +1,6 @@ ; Regression test for safestack layout. Used to fail with asan. ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s define void @f() safestack { ; CHECK-LABEL: define void @f diff --git a/llvm/test/Transforms/SafeStack/X86/memintrinsic-oob-read.ll b/llvm/test/Transforms/SafeStack/X86/memintrinsic-oob-read.ll index 9bc247ed6c50..75e40ad6921d 100644 --- a/llvm/test/Transforms/SafeStack/X86/memintrinsic-oob-read.ll +++ b/llvm/test/Transforms/SafeStack/X86/memintrinsic-oob-read.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/SafeStack/X86/musttail.ll b/llvm/test/Transforms/SafeStack/X86/musttail.ll index 32bc6674a2a2..a6e127924bf5 100644 --- a/llvm/test/Transforms/SafeStack/X86/musttail.ll +++ b/llvm/test/Transforms/SafeStack/X86/musttail.ll @@ -1,6 +1,7 @@ ; To test that safestack does not break the musttail call contract. ; ; RUN: opt < %s --safe-stack -S | FileCheck %s +; RUN: opt < %s -passes=safe-stack -S | FileCheck %s target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/SafeStack/X86/no-attr.ll b/llvm/test/Transforms/SafeStack/X86/no-attr.ll index 7715ca59f168..1a292b5a84b3 100644 --- a/llvm/test/Transforms/SafeStack/X86/no-attr.ll +++ b/llvm/test/Transforms/SafeStack/X86/no-attr.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/no-crash-on-lifetime.ll b/llvm/test/Transforms/SafeStack/X86/no-crash-on-lifetime.ll index 45e9fa3c2e3f..76c638ebbd21 100644 --- a/llvm/test/Transforms/SafeStack/X86/no-crash-on-lifetime.ll +++ b/llvm/test/Transforms/SafeStack/X86/no-crash-on-lifetime.ll @@ -1,5 +1,6 @@ ; Check that the pass does not crash on the code. ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu %s -o /dev/null +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu %s -o /dev/null %class.F = type { %class.o, i8, [7 x i8] } %class.o = type <{ ptr, i32, [4 x i8] }> diff --git a/llvm/test/Transforms/SafeStack/X86/phi-cycle.ll b/llvm/test/Transforms/SafeStack/X86/phi-cycle.ll index 18e6a7d50fe4..cca87af96ccf 100644 --- a/llvm/test/Transforms/SafeStack/X86/phi-cycle.ll +++ b/llvm/test/Transforms/SafeStack/X86/phi-cycle.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s %struct.small = type { i8 } diff --git a/llvm/test/Transforms/SafeStack/X86/phi.ll b/llvm/test/Transforms/SafeStack/X86/phi.ll index 18380431f639..8f0023edd54a 100644 --- a/llvm/test/Transforms/SafeStack/X86/phi.ll +++ b/llvm/test/Transforms/SafeStack/X86/phi.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s define void @f(i1 %d1, i1 %d2) safestack { entry: diff --git a/llvm/test/Transforms/SafeStack/X86/pr54784.ll b/llvm/test/Transforms/SafeStack/X86/pr54784.ll index 940f56004e81..398a53848063 100644 --- a/llvm/test/Transforms/SafeStack/X86/pr54784.ll +++ b/llvm/test/Transforms/SafeStack/X86/pr54784.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -S -safe-stack < %s | FileCheck %s +; RUN: opt -S -passes=safe-stack < %s | FileCheck %s target triple = "x86_64-unknown-unknown" diff --git a/llvm/test/Transforms/SafeStack/X86/ret.ll b/llvm/test/Transforms/SafeStack/X86/ret.ll index b8a3e0569d49..40ed6f50d4d2 100644 --- a/llvm/test/Transforms/SafeStack/X86/ret.ll +++ b/llvm/test/Transforms/SafeStack/X86/ret.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/setjmp.ll b/llvm/test/Transforms/SafeStack/X86/setjmp.ll index 64a39e081631..e3003ccd9b86 100644 --- a/llvm/test/Transforms/SafeStack/X86/setjmp.ll +++ b/llvm/test/Transforms/SafeStack/X86/setjmp.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s %struct.__jmp_buf_tag = type { [8 x i64], i32, %struct.__sigset_t } %struct.__sigset_t = type { [16 x i64] } diff --git a/llvm/test/Transforms/SafeStack/X86/setjmp2.ll b/llvm/test/Transforms/SafeStack/X86/setjmp2.ll index d5bd7c67109a..dbb9a08dc5a1 100644 --- a/llvm/test/Transforms/SafeStack/X86/setjmp2.ll +++ b/llvm/test/Transforms/SafeStack/X86/setjmp2.ll @@ -1,6 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3 ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s --check-prefix=I386 ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s --check-prefix=X86-64 +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s --check-prefix=I386 +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s --check-prefix=X86-64 %struct.__jmp_buf_tag = type { [8 x i64], i32, %struct.__sigset_t } %struct.__sigset_t = type { [16 x i64] } diff --git a/llvm/test/Transforms/SafeStack/X86/sink-to-use.ll b/llvm/test/Transforms/SafeStack/X86/sink-to-use.ll index 1a7984a7c04a..e6a95c3be82b 100644 --- a/llvm/test/Transforms/SafeStack/X86/sink-to-use.ll +++ b/llvm/test/Transforms/SafeStack/X86/sink-to-use.ll @@ -1,6 +1,8 @@ ; Test that unsafe alloca address calculation is done immediately before each use. ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s define void @f() safestack { entry: diff --git a/llvm/test/Transforms/SafeStack/X86/ssp.ll b/llvm/test/Transforms/SafeStack/X86/ssp.ll index 56e1ac69d1d7..c40abc65ca37 100644 --- a/llvm/test/Transforms/SafeStack/X86/ssp.ll +++ b/llvm/test/Transforms/SafeStack/X86/ssp.ll @@ -1,4 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=x86_64-unknown < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-unknown < %s -o - | FileCheck %s define void @foo() safestack sspreq { entry: diff --git a/llvm/test/Transforms/SafeStack/X86/store.ll b/llvm/test/Transforms/SafeStack/X86/store.ll index 6fc08760a72c..1e737f1551d7 100644 --- a/llvm/test/Transforms/SafeStack/X86/store.ll +++ b/llvm/test/Transforms/SafeStack/X86/store.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 diff --git a/llvm/test/Transforms/SafeStack/X86/struct.ll b/llvm/test/Transforms/SafeStack/X86/struct.ll index 8bce24bb5380..0c841c12025b 100644 --- a/llvm/test/Transforms/SafeStack/X86/struct.ll +++ b/llvm/test/Transforms/SafeStack/X86/struct.ll @@ -1,5 +1,7 @@ ; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s ; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s +; RUN: opt -passes=safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s %struct.foo = type { [16 x i8] } -- GitLab From 36239f9418d3ea19142e13d1bb05bd043ccf3d23 Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Fri, 1 Dec 2023 13:11:45 +0800 Subject: [PATCH 094/699] [RISCV] Move AVL coalescing logic upwards into computeInfoForInstr. NFC (#73909) There is an optimisation in transferBefore where if a VSETVLIInfo uses the AVL of a defining vsetvli, it uses that vsetvli's AVL provided VLMAX is the same. This patch moves it out of transferBefore and up into computeInfoForInstr to show how it isn't affected by the other optimisations in transferBefore, and to simplify the control flow by removing an early return. This should make #72352 easier to reason about. --- llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 74 +++++++++----------- 1 file changed, 35 insertions(+), 39 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp index 3bb648359e39..a174d762bf8c 100644 --- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp +++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp @@ -781,6 +781,25 @@ char RISCVInsertVSETVLI::ID = 0; INITIALIZE_PASS(RISCVInsertVSETVLI, DEBUG_TYPE, RISCV_INSERT_VSETVLI_NAME, false, false) +// Return a VSETVLIInfo representing the changes made by this VSETVLI or +// VSETIVLI instruction. +static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI) { + VSETVLIInfo NewInfo; + if (MI.getOpcode() == RISCV::PseudoVSETIVLI) { + NewInfo.setAVLImm(MI.getOperand(1).getImm()); + } else { + assert(MI.getOpcode() == RISCV::PseudoVSETVLI || + MI.getOpcode() == RISCV::PseudoVSETVLIX0); + Register AVLReg = MI.getOperand(1).getReg(); + assert((AVLReg != RISCV::X0 || MI.getOperand(0).getReg() != RISCV::X0) && + "Can't handle X0, X0 vsetvli yet"); + NewInfo.setAVLReg(AVLReg); + } + NewInfo.setVTYPE(MI.getOperand(2).getImm()); + + return NewInfo; +} + static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags, const MachineRegisterInfo *MRI) { VSETVLIInfo InstrInfo; @@ -841,6 +860,21 @@ static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags, #endif InstrInfo.setVTYPE(VLMul, SEW, TailAgnostic, MaskAgnostic); + // If AVL is defined by a vsetvli with the same VLMAX, we can replace the + // AVL operand with the AVL of the defining vsetvli. We avoid general + // register AVLs to avoid extending live ranges without being sure we can + // kill the original source reg entirely. + if (InstrInfo.hasAVLReg() && InstrInfo.getAVLReg().isVirtual()) { + MachineInstr *DefMI = MRI->getVRegDef(InstrInfo.getAVLReg()); + if (DefMI && isVectorConfigInstr(*DefMI)) { + VSETVLIInfo DefInstrInfo = getInfoForVSETVLI(*DefMI); + if (DefInstrInfo.hasSameVLMAX(InstrInfo) && + (DefInstrInfo.hasAVLImm() || DefInstrInfo.getAVLReg() == RISCV::X0)) { + InstrInfo.setAVL(DefInstrInfo); + } + } + } + return InstrInfo; } @@ -851,25 +885,6 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB, MachineInstr &MI, insertVSETVLI(MBB, MachineBasicBlock::iterator(&MI), DL, Info, PrevInfo); } -// Return a VSETVLIInfo representing the changes made by this VSETVLI or -// VSETIVLI instruction. -static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI) { - VSETVLIInfo NewInfo; - if (MI.getOpcode() == RISCV::PseudoVSETIVLI) { - NewInfo.setAVLImm(MI.getOperand(1).getImm()); - } else { - assert(MI.getOpcode() == RISCV::PseudoVSETVLI || - MI.getOpcode() == RISCV::PseudoVSETVLIX0); - Register AVLReg = MI.getOperand(1).getReg(); - assert((AVLReg != RISCV::X0 || MI.getOperand(0).getReg() != RISCV::X0) && - "Can't handle X0, X0 vsetvli yet"); - NewInfo.setAVLReg(AVLReg); - } - NewInfo.setVTYPE(MI.getOperand(2).getImm()); - - return NewInfo; -} - void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertPt, DebugLoc DL, const VSETVLIInfo &Info, const VSETVLIInfo &PrevInfo) { @@ -1065,27 +1080,8 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info, // to prevent extending live range of an avl register operand. // TODO: We can probably relax this for immediates. if (Demanded.VLZeroness && !Demanded.VLAny && PrevInfo.isValid() && - PrevInfo.hasEquallyZeroAVL(Info, *MRI) && Info.hasSameVLMAX(PrevInfo)) { + PrevInfo.hasEquallyZeroAVL(Info, *MRI) && Info.hasSameVLMAX(PrevInfo)) Info.setAVL(PrevInfo); - return; - } - - // If AVL is defined by a vsetvli with the same VLMAX, we can - // replace the AVL operand with the AVL of the defining vsetvli. - // We avoid general register AVLs to avoid extending live ranges - // without being sure we can kill the original source reg entirely. - if (!Info.hasAVLReg() || !Info.getAVLReg().isVirtual()) - return; - MachineInstr *DefMI = MRI->getVRegDef(Info.getAVLReg()); - if (!DefMI || !isVectorConfigInstr(*DefMI)) - return; - - VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI); - if (DefInfo.hasSameVLMAX(Info) && - (DefInfo.hasAVLImm() || DefInfo.getAVLReg() == RISCV::X0)) { - Info.setAVL(DefInfo); - return; - } } // Given a state with which we evaluated MI (see transferBefore above for why -- GitLab From dbbc7c31c8e55d72dc243b244e386a25132e7215 Mon Sep 17 00:00:00 2001 From: leecheechen Date: Fri, 1 Dec 2023 13:14:11 +0800 Subject: [PATCH 095/699] [LoongArch] Add some binary IR instructions testcases for LASX (#74031) The IR instructions include: - Binary Operations: add fadd sub fsub mul fmul udiv sdiv fdiv - Bitwise Binary Operations: shl lshr ashr --- .../LoongArch/lasx/ir-instruction/add.ll | 122 +++++++++ .../LoongArch/lasx/ir-instruction/ashr.ll | 178 +++++++++++++ .../LoongArch/lasx/ir-instruction/fadd.ll | 34 +++ .../LoongArch/lasx/ir-instruction/fdiv.ll | 34 +++ .../LoongArch/lasx/ir-instruction/fmul.ll | 34 +++ .../LoongArch/lasx/ir-instruction/fsub.ll | 34 +++ .../LoongArch/lasx/ir-instruction/lshr.ll | 178 +++++++++++++ .../LoongArch/lasx/ir-instruction/mul.ll | 238 ++++++++++++++++++ .../LoongArch/lasx/ir-instruction/sdiv.ll | 134 ++++++++++ .../LoongArch/lasx/ir-instruction/shl.ll | 178 +++++++++++++ .../LoongArch/lasx/ir-instruction/sub.ll | 122 +++++++++ .../LoongArch/lasx/ir-instruction/udiv.ll | 122 +++++++++ 12 files changed, 1408 insertions(+) create mode 100644 llvm/test/CodeGen/LoongArch/lasx/ir-instruction/add.ll create mode 100644 llvm/test/CodeGen/LoongArch/lasx/ir-instruction/ashr.ll create mode 100644 llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fadd.ll create mode 100644 llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fdiv.ll create mode 100644 llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fmul.ll create mode 100644 llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fsub.ll create mode 100644 llvm/test/CodeGen/LoongArch/lasx/ir-instruction/lshr.ll create mode 100644 llvm/test/CodeGen/LoongArch/lasx/ir-instruction/mul.ll create mode 100644 llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sdiv.ll create mode 100644 llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shl.ll create mode 100644 llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll create mode 100644 llvm/test/CodeGen/LoongArch/lasx/ir-instruction/udiv.ll diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/add.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/add.ll new file mode 100644 index 000000000000..8e4d0dc6f1c3 --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/add.ll @@ -0,0 +1,122 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s + +define void @add_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: add_v32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvadd.b $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <32 x i8>, ptr %a0 + %v1 = load <32 x i8>, ptr %a1 + %v2 = add <32 x i8> %v0, %v1 + store <32 x i8> %v2, ptr %res + ret void +} + +define void @add_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: add_v16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvadd.h $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i16>, ptr %a0 + %v1 = load <16 x i16>, ptr %a1 + %v2 = add <16 x i16> %v0, %v1 + store <16 x i16> %v2, ptr %res + ret void +} + +define void @add_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: add_v8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvadd.w $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i32>, ptr %a0 + %v1 = load <8 x i32>, ptr %a1 + %v2 = add <8 x i32> %v0, %v1 + store <8 x i32> %v2, ptr %res + ret void +} + +define void @add_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: add_v4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvadd.d $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i64>, ptr %a0 + %v1 = load <4 x i64>, ptr %a1 + %v2 = add <4 x i64> %v0, %v1 + store <4 x i64> %v2, ptr %res + ret void +} + +define void @add_v32i8_31(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: add_v32i8_31: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvaddi.bu $xr0, $xr0, 31 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <32 x i8>, ptr %a0 + %v1 = add <32 x i8> %v0, + store <32 x i8> %v1, ptr %res + ret void +} + +define void @add_v16i16_31(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: add_v16i16_31: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvaddi.hu $xr0, $xr0, 31 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i16>, ptr %a0 + %v1 = add <16 x i16> %v0, + store <16 x i16> %v1, ptr %res + ret void +} + +define void @add_v8i32_31(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: add_v8i32_31: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvaddi.wu $xr0, $xr0, 31 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i32>, ptr %a0 + %v1 = add <8 x i32> %v0, + store <8 x i32> %v1, ptr %res + ret void +} + +define void @add_v4i64_31(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: add_v4i64_31: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvaddi.du $xr0, $xr0, 31 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i64>, ptr %a0 + %v1 = add <4 x i64> %v0, + store <4 x i64> %v1, ptr %res + ret void +} diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/ashr.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/ashr.ll new file mode 100644 index 000000000000..fcbf0f1400fe --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/ashr.ll @@ -0,0 +1,178 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s + +define void @ashr_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: ashr_v32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvsra.b $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <32 x i8>, ptr %a0 + %v1 = load <32 x i8>, ptr %a1 + %v2 = ashr <32 x i8> %v0, %v1 + store <32 x i8> %v2, ptr %res + ret void +} + +define void @ashr_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: ashr_v16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvsra.h $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i16>, ptr %a0 + %v1 = load <16 x i16>, ptr %a1 + %v2 = ashr <16 x i16> %v0, %v1 + store <16 x i16> %v2, ptr %res + ret void +} + +define void @ashr_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: ashr_v8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvsra.w $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i32>, ptr %a0 + %v1 = load <8 x i32>, ptr %a1 + %v2 = ashr <8 x i32> %v0, %v1 + store <8 x i32> %v2, ptr %res + ret void +} + +define void @ashr_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: ashr_v4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvsra.d $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i64>, ptr %a0 + %v1 = load <4 x i64>, ptr %a1 + %v2 = ashr <4 x i64> %v0, %v1 + store <4 x i64> %v2, ptr %res + ret void +} + +define void @ashr_v32i8_1(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: ashr_v32i8_1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvsrai.b $xr0, $xr0, 1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <32 x i8>, ptr %a0 + %v1 = ashr <32 x i8> %v0, + store <32 x i8> %v1, ptr %res + ret void +} + +define void @ashr_v32i8_7(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: ashr_v32i8_7: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvsrai.b $xr0, $xr0, 7 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <32 x i8>, ptr %a0 + %v1 = ashr <32 x i8> %v0, + store <32 x i8> %v1, ptr %res + ret void +} + +define void @ashr_v16i16_1(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: ashr_v16i16_1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvsrai.h $xr0, $xr0, 1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i16>, ptr %a0 + %v1 = ashr <16 x i16> %v0, + store <16 x i16> %v1, ptr %res + ret void +} + +define void @ashr_v16i16_15(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: ashr_v16i16_15: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvsrai.h $xr0, $xr0, 15 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i16>, ptr %a0 + %v1 = ashr <16 x i16> %v0, + store <16 x i16> %v1, ptr %res + ret void +} + +define void @ashr_v8i32_1(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: ashr_v8i32_1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvsrai.w $xr0, $xr0, 1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i32>, ptr %a0 + %v1 = ashr <8 x i32> %v0, + store <8 x i32> %v1, ptr %res + ret void +} + +define void @ashr_v8i32_31(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: ashr_v8i32_31: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvsrai.w $xr0, $xr0, 31 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i32>, ptr %a0 + %v1 = ashr <8 x i32> %v0, + store <8 x i32> %v1, ptr %res + ret void +} + +define void @ashr_v4i64_1(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: ashr_v4i64_1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvsrai.d $xr0, $xr0, 1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i64>, ptr %a0 + %v1 = ashr <4 x i64> %v0, + store <4 x i64> %v1, ptr %res + ret void +} + +define void @ashr_v4i64_63(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: ashr_v4i64_63: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvsrai.d $xr0, $xr0, 63 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i64>, ptr %a0 + %v1 = ashr <4 x i64> %v0, + store <4 x i64> %v1, ptr %res + ret void +} diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fadd.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fadd.ll new file mode 100644 index 000000000000..365bb305fc5a --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fadd.ll @@ -0,0 +1,34 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s + +define void @fadd_v8f32(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: fadd_v8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvfadd.s $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x float>, ptr %a0 + %v1 = load <8 x float>, ptr %a1 + %v2 = fadd <8 x float> %v0, %v1 + store <8 x float> %v2, ptr %res + ret void +} + +define void @fadd_v4f64(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: fadd_v4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvfadd.d $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x double>, ptr %a0 + %v1 = load <4 x double>, ptr %a1 + %v2 = fadd <4 x double> %v0, %v1 + store <4 x double> %v2, ptr %res + ret void +} diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fdiv.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fdiv.ll new file mode 100644 index 000000000000..284121a79a49 --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fdiv.ll @@ -0,0 +1,34 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s + +define void @fdiv_v8f32(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: fdiv_v8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvfdiv.s $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x float>, ptr %a0 + %v1 = load <8 x float>, ptr %a1 + %v2 = fdiv <8 x float> %v0, %v1 + store <8 x float> %v2, ptr %res + ret void +} + +define void @fdiv_v4f64(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: fdiv_v4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvfdiv.d $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x double>, ptr %a0 + %v1 = load <4 x double>, ptr %a1 + %v2 = fdiv <4 x double> %v0, %v1 + store <4 x double> %v2, ptr %res + ret void +} diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fmul.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fmul.ll new file mode 100644 index 000000000000..a48dca8d2847 --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fmul.ll @@ -0,0 +1,34 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s + +define void @fmul_v8f32(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: fmul_v8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvfmul.s $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x float>, ptr %a0 + %v1 = load <8 x float>, ptr %a1 + %v2 = fmul <8 x float> %v0, %v1 + store <8 x float> %v2, ptr %res + ret void +} + +define void @fmul_v4f64(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: fmul_v4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvfmul.d $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x double>, ptr %a0 + %v1 = load <4 x double>, ptr %a1 + %v2 = fmul <4 x double> %v0, %v1 + store <4 x double> %v2, ptr %res + ret void +} diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fsub.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fsub.ll new file mode 100644 index 000000000000..6164aa5a55c7 --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fsub.ll @@ -0,0 +1,34 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s + +define void @fsub_v8f32(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: fsub_v8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvfsub.s $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x float>, ptr %a0 + %v1 = load <8 x float>, ptr %a1 + %v2 = fsub <8 x float> %v0, %v1 + store <8 x float> %v2, ptr %res + ret void +} + +define void @fsub_v4f64(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: fsub_v4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvfsub.d $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x double>, ptr %a0 + %v1 = load <4 x double>, ptr %a1 + %v2 = fsub <4 x double> %v0, %v1 + store <4 x double> %v2, ptr %res + ret void +} diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/lshr.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/lshr.ll new file mode 100644 index 000000000000..24be69d8032a --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/lshr.ll @@ -0,0 +1,178 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s + +define void @lshr_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: lshr_v32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvsrl.b $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <32 x i8>, ptr %a0 + %v1 = load <32 x i8>, ptr %a1 + %v2 = lshr <32 x i8> %v0, %v1 + store <32 x i8> %v2, ptr %res + ret void +} + +define void @lshr_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: lshr_v16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvsrl.h $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i16>, ptr %a0 + %v1 = load <16 x i16>, ptr %a1 + %v2 = lshr <16 x i16> %v0, %v1 + store <16 x i16> %v2, ptr %res + ret void +} + +define void @lshr_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: lshr_v8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvsrl.w $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i32>, ptr %a0 + %v1 = load <8 x i32>, ptr %a1 + %v2 = lshr <8 x i32> %v0, %v1 + store <8 x i32> %v2, ptr %res + ret void +} + +define void @lshr_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: lshr_v4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvsrl.d $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i64>, ptr %a0 + %v1 = load <4 x i64>, ptr %a1 + %v2 = lshr <4 x i64> %v0, %v1 + store <4 x i64> %v2, ptr %res + ret void +} + +define void @lshr_v32i8_1(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: lshr_v32i8_1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvsrli.b $xr0, $xr0, 1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <32 x i8>, ptr %a0 + %v1 = lshr <32 x i8> %v0, + store <32 x i8> %v1, ptr %res + ret void +} + +define void @lshr_v32i8_7(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: lshr_v32i8_7: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvsrli.b $xr0, $xr0, 7 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <32 x i8>, ptr %a0 + %v1 = lshr <32 x i8> %v0, + store <32 x i8> %v1, ptr %res + ret void +} + +define void @lshr_v16i16_1(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: lshr_v16i16_1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvsrli.h $xr0, $xr0, 1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i16>, ptr %a0 + %v1 = lshr <16 x i16> %v0, + store <16 x i16> %v1, ptr %res + ret void +} + +define void @lshr_v16i16_15(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: lshr_v16i16_15: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvsrli.h $xr0, $xr0, 15 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i16>, ptr %a0 + %v1 = lshr <16 x i16> %v0, + store <16 x i16> %v1, ptr %res + ret void +} + +define void @lshr_v8i32_1(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: lshr_v8i32_1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvsrli.w $xr0, $xr0, 1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i32>, ptr %a0 + %v1 = lshr <8 x i32> %v0, + store <8 x i32> %v1, ptr %res + ret void +} + +define void @lshr_v8i32_31(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: lshr_v8i32_31: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvsrli.w $xr0, $xr0, 31 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i32>, ptr %a0 + %v1 = lshr <8 x i32> %v0, + store <8 x i32> %v1, ptr %res + ret void +} + +define void @lshr_v4i64_1(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: lshr_v4i64_1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvsrli.d $xr0, $xr0, 1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i64>, ptr %a0 + %v1 = lshr <4 x i64> %v0, + store <4 x i64> %v1, ptr %res + ret void +} + +define void @lshr_v4i64_63(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: lshr_v4i64_63: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvsrli.d $xr0, $xr0, 63 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i64>, ptr %a0 + %v1 = lshr <4 x i64> %v0, + store <4 x i64> %v1, ptr %res + ret void +} diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/mul.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/mul.ll new file mode 100644 index 000000000000..dcb893caa255 --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/mul.ll @@ -0,0 +1,238 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s + +define void @mul_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: mul_v32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvmul.b $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <32 x i8>, ptr %a0 + %v1 = load <32 x i8>, ptr %a1 + %v2 = mul <32 x i8> %v0, %v1 + store <32 x i8> %v2, ptr %res + ret void +} + +define void @mul_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: mul_v16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvmul.h $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i16>, ptr %a0 + %v1 = load <16 x i16>, ptr %a1 + %v2 = mul <16 x i16> %v0, %v1 + store <16 x i16> %v2, ptr %res + ret void +} + +define void @mul_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: mul_v8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvmul.w $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i32>, ptr %a0 + %v1 = load <8 x i32>, ptr %a1 + %v2 = mul <8 x i32> %v0, %v1 + store <8 x i32> %v2, ptr %res + ret void +} + +define void @mul_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: mul_v4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvmul.d $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i64>, ptr %a0 + %v1 = load <4 x i64>, ptr %a1 + %v2 = mul <4 x i64> %v0, %v1 + store <4 x i64> %v2, ptr %res + ret void +} + +define void @mul_square_v32i8(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: mul_square_v32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvmul.b $xr0, $xr0, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <32 x i8>, ptr %a0 + %v1 = mul <32 x i8> %v0, %v0 + store <32 x i8> %v1, ptr %res + ret void +} + +define void @mul_square_v16i16(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: mul_square_v16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvmul.h $xr0, $xr0, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i16>, ptr %a0 + %v1 = mul <16 x i16> %v0, %v0 + store <16 x i16> %v1, ptr %res + ret void +} + +define void @mul_square_v8i32(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: mul_square_v8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvmul.w $xr0, $xr0, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i32>, ptr %a0 + %v1 = mul <8 x i32> %v0, %v0 + store <8 x i32> %v1, ptr %res + ret void +} + +define void @mul_square_v4i64(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: mul_square_v4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvmul.d $xr0, $xr0, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i64>, ptr %a0 + %v1 = mul <4 x i64> %v0, %v0 + store <4 x i64> %v1, ptr %res + ret void +} + +define void @mul_v32i8_8(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: mul_v32i8_8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvslli.b $xr0, $xr0, 3 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <32 x i8>, ptr %a0 + %v1 = mul <32 x i8> %v0, + store <32 x i8> %v1, ptr %res + ret void +} + +define void @mul_v16i16_8(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: mul_v16i16_8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvslli.h $xr0, $xr0, 3 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i16>, ptr %a0 + %v1 = mul <16 x i16> %v0, + store <16 x i16> %v1, ptr %res + ret void +} + +define void @mul_v8i32_8(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: mul_v8i32_8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvslli.w $xr0, $xr0, 3 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i32>, ptr %a0 + %v1 = mul <8 x i32> %v0, + store <8 x i32> %v1, ptr %res + ret void +} + +define void @mul_v4i64_8(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: mul_v4i64_8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvslli.d $xr0, $xr0, 3 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i64>, ptr %a0 + %v1 = mul <4 x i64> %v0, + store <4 x i64> %v1, ptr %res + ret void +} + +define void @mul_v32i8_17(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: mul_v32i8_17: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvrepli.b $xr1, 17 +; CHECK-NEXT: xvmul.b $xr0, $xr0, $xr1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <32 x i8>, ptr %a0 + %v1 = mul <32 x i8> %v0, + store <32 x i8> %v1, ptr %res + ret void +} + +define void @mul_v16i16_17(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: mul_v16i16_17: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvrepli.h $xr1, 17 +; CHECK-NEXT: xvmul.h $xr0, $xr0, $xr1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i16>, ptr %a0 + %v1 = mul <16 x i16> %v0, + store <16 x i16> %v1, ptr %res + ret void +} + +define void @mul_v8i32_17(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: mul_v8i32_17: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvrepli.w $xr1, 17 +; CHECK-NEXT: xvmul.w $xr0, $xr0, $xr1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i32>, ptr %a0 + %v1 = mul <8 x i32> %v0, + store <8 x i32> %v1, ptr %res + ret void +} + +define void @mul_v4i64_17(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: mul_v4i64_17: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvrepli.d $xr1, 17 +; CHECK-NEXT: xvmul.d $xr0, $xr0, $xr1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i64>, ptr %a0 + %v1 = mul <4 x i64> %v0, + store <4 x i64> %v1, ptr %res + ret void +} diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sdiv.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sdiv.ll new file mode 100644 index 000000000000..e3635a5f14a2 --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sdiv.ll @@ -0,0 +1,134 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s + +define void @sdiv_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: sdiv_v32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvdiv.b $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <32 x i8>, ptr %a0 + %v1 = load <32 x i8>, ptr %a1 + %v2 = sdiv <32 x i8> %v0, %v1 + store <32 x i8> %v2, ptr %res + ret void +} + +define void @sdiv_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: sdiv_v16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvdiv.h $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i16>, ptr %a0 + %v1 = load <16 x i16>, ptr %a1 + %v2 = sdiv <16 x i16> %v0, %v1 + store <16 x i16> %v2, ptr %res + ret void +} + +define void @sdiv_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: sdiv_v8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvdiv.w $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i32>, ptr %a0 + %v1 = load <8 x i32>, ptr %a1 + %v2 = sdiv <8 x i32> %v0, %v1 + store <8 x i32> %v2, ptr %res + ret void +} + +define void @sdiv_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: sdiv_v4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvdiv.d $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i64>, ptr %a0 + %v1 = load <4 x i64>, ptr %a1 + %v2 = sdiv <4 x i64> %v0, %v1 + store <4 x i64> %v2, ptr %res + ret void +} + +define void @sdiv_v32i8_8(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: sdiv_v32i8_8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvsrai.b $xr1, $xr0, 7 +; CHECK-NEXT: xvsrli.b $xr1, $xr1, 5 +; CHECK-NEXT: xvadd.b $xr0, $xr0, $xr1 +; CHECK-NEXT: xvsrai.b $xr0, $xr0, 3 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <32 x i8>, ptr %a0 + %v1 = sdiv <32 x i8> %v0, + store <32 x i8> %v1, ptr %res + ret void +} + +define void @sdiv_v16i16_8(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: sdiv_v16i16_8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvsrai.h $xr1, $xr0, 15 +; CHECK-NEXT: xvsrli.h $xr1, $xr1, 13 +; CHECK-NEXT: xvadd.h $xr0, $xr0, $xr1 +; CHECK-NEXT: xvsrai.h $xr0, $xr0, 3 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i16>, ptr %a0 + %v1 = sdiv <16 x i16> %v0, + store <16 x i16> %v1, ptr %res + ret void +} + +define void @sdiv_v8i32_8(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: sdiv_v8i32_8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvsrai.w $xr1, $xr0, 31 +; CHECK-NEXT: xvsrli.w $xr1, $xr1, 29 +; CHECK-NEXT: xvadd.w $xr0, $xr0, $xr1 +; CHECK-NEXT: xvsrai.w $xr0, $xr0, 3 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i32>, ptr %a0 + %v1 = sdiv <8 x i32> %v0, + store <8 x i32> %v1, ptr %res + ret void +} + +define void @sdiv_v4i64_8(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: sdiv_v4i64_8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvsrai.d $xr1, $xr0, 63 +; CHECK-NEXT: xvsrli.d $xr1, $xr1, 61 +; CHECK-NEXT: xvadd.d $xr0, $xr0, $xr1 +; CHECK-NEXT: xvsrai.d $xr0, $xr0, 3 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i64>, ptr %a0 + %v1 = sdiv <4 x i64> %v0, + store <4 x i64> %v1, ptr %res + ret void +} diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shl.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shl.ll new file mode 100644 index 000000000000..8a02c7e3ac97 --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shl.ll @@ -0,0 +1,178 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s + +define void @shl_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: shl_v32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvsll.b $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <32 x i8>, ptr %a0 + %v1 = load <32 x i8>, ptr %a1 + %v2 = shl <32 x i8> %v0, %v1 + store <32 x i8> %v2, ptr %res + ret void +} + +define void @shl_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: shl_v16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvsll.h $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i16>, ptr %a0 + %v1 = load <16 x i16>, ptr %a1 + %v2 = shl <16 x i16> %v0, %v1 + store <16 x i16> %v2, ptr %res + ret void +} + +define void @shl_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: shl_v8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvsll.w $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i32>, ptr %a0 + %v1 = load <8 x i32>, ptr %a1 + %v2 = shl <8 x i32> %v0, %v1 + store <8 x i32> %v2, ptr %res + ret void +} + +define void @shl_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: shl_v4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvsll.d $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i64>, ptr %a0 + %v1 = load <4 x i64>, ptr %a1 + %v2 = shl <4 x i64> %v0, %v1 + store <4 x i64> %v2, ptr %res + ret void +} + +define void @shl_v32i8_1(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: shl_v32i8_1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvslli.b $xr0, $xr0, 1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <32 x i8>, ptr %a0 + %v1 = shl <32 x i8> %v0, + store <32 x i8> %v1, ptr %res + ret void +} + +define void @shl_v32i8_7(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: shl_v32i8_7: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvslli.b $xr0, $xr0, 7 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <32 x i8>, ptr %a0 + %v1 = shl <32 x i8> %v0, + store <32 x i8> %v1, ptr %res + ret void +} + +define void @shl_v16i16_1(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: shl_v16i16_1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvslli.h $xr0, $xr0, 1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i16>, ptr %a0 + %v1 = shl <16 x i16> %v0, + store <16 x i16> %v1, ptr %res + ret void +} + +define void @shl_v16i16_15(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: shl_v16i16_15: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvslli.h $xr0, $xr0, 15 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i16>, ptr %a0 + %v1 = shl <16 x i16> %v0, + store <16 x i16> %v1, ptr %res + ret void +} + +define void @shl_v8i32_1(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: shl_v8i32_1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvslli.w $xr0, $xr0, 1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i32>, ptr %a0 + %v1 = shl <8 x i32> %v0, + store <8 x i32> %v1, ptr %res + ret void +} + +define void @shl_v8i32_31(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: shl_v8i32_31: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvslli.w $xr0, $xr0, 31 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i32>, ptr %a0 + %v1 = shl <8 x i32> %v0, + store <8 x i32> %v1, ptr %res + ret void +} + +define void @shl_v4i64_1(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: shl_v4i64_1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvslli.d $xr0, $xr0, 1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i64>, ptr %a0 + %v1 = shl <4 x i64> %v0, + store <4 x i64> %v1, ptr %res + ret void +} + +define void @shl_v4i64_63(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: shl_v4i64_63: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvslli.d $xr0, $xr0, 63 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i64>, ptr %a0 + %v1 = shl <4 x i64> %v0, + store <4 x i64> %v1, ptr %res + ret void +} diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll new file mode 100644 index 000000000000..bcfff1651477 --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll @@ -0,0 +1,122 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s + +define void @sub_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: sub_v32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvsub.b $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <32 x i8>, ptr %a0 + %v1 = load <32 x i8>, ptr %a1 + %v2 = sub <32 x i8> %v0, %v1 + store <32 x i8> %v2, ptr %res + ret void +} + +define void @sub_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: sub_v16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvsub.h $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i16>, ptr %a0 + %v1 = load <16 x i16>, ptr %a1 + %v2 = sub <16 x i16> %v0, %v1 + store <16 x i16> %v2, ptr %res + ret void +} + +define void @sub_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: sub_v8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvsub.w $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i32>, ptr %a0 + %v1 = load <8 x i32>, ptr %a1 + %v2 = sub <8 x i32> %v0, %v1 + store <8 x i32> %v2, ptr %res + ret void +} + +define void @sub_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: sub_v4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvsub.d $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i64>, ptr %a0 + %v1 = load <4 x i64>, ptr %a1 + %v2 = sub <4 x i64> %v0, %v1 + store <4 x i64> %v2, ptr %res + ret void +} + +define void @sub_v32i8_31(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: sub_v32i8_31: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvsubi.bu $xr0, $xr0, 31 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <32 x i8>, ptr %a0 + %v1 = sub <32 x i8> %v0, + store <32 x i8> %v1, ptr %res + ret void +} + +define void @sub_v16i16_31(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: sub_v16i16_31: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvsubi.hu $xr0, $xr0, 31 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i16>, ptr %a0 + %v1 = sub <16 x i16> %v0, + store <16 x i16> %v1, ptr %res + ret void +} + +define void @sub_v8i32_31(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: sub_v8i32_31: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvsubi.wu $xr0, $xr0, 31 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i32>, ptr %a0 + %v1 = sub <8 x i32> %v0, + store <8 x i32> %v1, ptr %res + ret void +} + +define void @sub_v4i64_31(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: sub_v4i64_31: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvsubi.du $xr0, $xr0, 31 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i64>, ptr %a0 + %v1 = sub <4 x i64> %v0, + store <4 x i64> %v1, ptr %res + ret void +} diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/udiv.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/udiv.ll new file mode 100644 index 000000000000..e78084c7186d --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/udiv.ll @@ -0,0 +1,122 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s + +define void @udiv_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: udiv_v32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvdiv.bu $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <32 x i8>, ptr %a0 + %v1 = load <32 x i8>, ptr %a1 + %v2 = udiv <32 x i8> %v0, %v1 + store <32 x i8> %v2, ptr %res + ret void +} + +define void @udiv_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: udiv_v16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvdiv.hu $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i16>, ptr %a0 + %v1 = load <16 x i16>, ptr %a1 + %v2 = udiv <16 x i16> %v0, %v1 + store <16 x i16> %v2, ptr %res + ret void +} + +define void @udiv_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: udiv_v8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvdiv.wu $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i32>, ptr %a0 + %v1 = load <8 x i32>, ptr %a1 + %v2 = udiv <8 x i32> %v0, %v1 + store <8 x i32> %v2, ptr %res + ret void +} + +define void @udiv_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: udiv_v4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvdiv.du $xr0, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i64>, ptr %a0 + %v1 = load <4 x i64>, ptr %a1 + %v2 = udiv <4 x i64> %v0, %v1 + store <4 x i64> %v2, ptr %res + ret void +} + +define void @udiv_v32i8_8(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: udiv_v32i8_8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvsrli.b $xr0, $xr0, 3 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <32 x i8>, ptr %a0 + %v1 = udiv <32 x i8> %v0, + store <32 x i8> %v1, ptr %res + ret void +} + +define void @udiv_v16i16_8(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: udiv_v16i16_8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvsrli.h $xr0, $xr0, 3 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <16 x i16>, ptr %a0 + %v1 = udiv <16 x i16> %v0, + store <16 x i16> %v1, ptr %res + ret void +} + +define void @udiv_v8i32_8(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: udiv_v8i32_8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvsrli.w $xr0, $xr0, 3 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <8 x i32>, ptr %a0 + %v1 = udiv <8 x i32> %v0, + store <8 x i32> %v1, ptr %res + ret void +} + +define void @udiv_v4i64_8(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: udiv_v4i64_8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvsrli.d $xr0, $xr0, 3 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %v0 = load <4 x i64>, ptr %a0 + %v1 = udiv <4 x i64> %v0, + store <4 x i64> %v1, ptr %res + ret void +} -- GitLab From 173fcf7da592acd284dc50749558fd36928861f0 Mon Sep 17 00:00:00 2001 From: Uday Bondhugula Date: Fri, 1 Dec 2023 11:00:01 +0530 Subject: [PATCH 096/699] [NVPTX] Lower 16xi8 and 8xi8 stores efficiently (#73646) Lower 16xi8 vector stores in NVPTX ISel efficiently using st.v4.b32 instead of multiple st.v4.u8 along the lines of vector loads and 8xf16. Similarly, 8xi8 using st.v2.u32. --- llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp | 53 ++++++++++++++++++-- llvm/test/CodeGen/NVPTX/i8x4-instructions.ll | 7 ++- llvm/test/CodeGen/NVPTX/vector-stores.ll | 16 ++++++ 3 files changed, 69 insertions(+), 7 deletions(-) diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp index 61285c6ba98d..b975825dae4b 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -508,6 +508,7 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM, setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i16, Expand); setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i16, Expand); + // Conversion to/from i8/i8x4 is always legal. setOperationAction(ISD::BUILD_VECTOR, MVT::v4i8, Custom); setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i8, Custom); setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i8, Custom); @@ -717,8 +718,8 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM, // We have some custom DAG combine patterns for these nodes setTargetDAGCombine({ISD::ADD, ISD::AND, ISD::EXTRACT_VECTOR_ELT, ISD::FADD, - ISD::LOAD, ISD::MUL, ISD::SHL, ISD::SREM, ISD::UREM, - ISD::VSELECT}); + ISD::LOAD, ISD::MUL, ISD::SHL, ISD::SREM, ISD::STORE, + ISD::UREM, ISD::VSELECT}); // setcc for f16x2 and bf16x2 needs special handling to prevent // legalizer's attempt to scalarize it due to v2i1 not being legal. @@ -2916,7 +2917,6 @@ NVPTXTargetLowering::LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const { DAG.getMemIntrinsicNode(Opcode, DL, DAG.getVTList(MVT::Other), Ops, MemSD->getMemoryVT(), MemSD->getMemOperand()); - // return DCI.CombineTo(N, NewSt, true); return NewSt; } @@ -5557,6 +5557,51 @@ static SDValue PerformLOADCombine(SDNode *N, DL); } +// Lower a v16i8 (or a v8i8) store into a StoreV4 (or StoreV2) operation with +// i32 results instead of letting ReplaceLoadVector split it into smaller stores +// during legalization. This is done at dag-combine1 time, so that vector +// operations with i8 elements can be optimised away instead of being needlessly +// split during legalization, which involves storing to the stack and loading it +// back. +static SDValue PerformSTORECombine(SDNode *N, + TargetLowering::DAGCombinerInfo &DCI) { + SelectionDAG &DAG = DCI.DAG; + StoreSDNode *ST = cast(N); + EVT VT = ST->getValue().getValueType(); + if (VT != MVT::v16i8 && VT != MVT::v8i8) + return SDValue(); + + // Create a v4i32 vector store operation, effectively <4 x v4i8>. + unsigned Opc = VT == MVT::v16i8 ? NVPTXISD::StoreV4 : NVPTXISD::StoreV2; + EVT NewVT = VT == MVT::v16i8 ? MVT::v4i32 : MVT::v2i32; + unsigned NumElts = NewVT.getVectorNumElements(); + + // Create a vector of the type required by the new store: v16i8 -> v4i32. + SDValue NewStoreValue = DCI.DAG.getBitcast(NewVT, ST->getValue()); + + // Operands for the store. + SmallVector Ops; + Ops.reserve(N->getNumOperands() + NumElts - 1); + // Chain value. + Ops.push_back(N->ops().front()); + + SDLoc DL(N); + SmallVector Elts(NumElts); + // Break v4i32 (or v2i32) into four (or two) elements. + for (unsigned I = 0; I < NumElts; ++I) + Elts[I] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, + NewStoreValue.getValueType().getVectorElementType(), + NewStoreValue, DAG.getIntPtrConstant(I, DL)); + Ops.append(Elts.begin(), Elts.end()); + // Any remaining operands. + Ops.append(N->op_begin() + 2, N->op_end()); + + SDValue NewStore = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other), + Ops, NewVT, ST->getMemOperand()); + // Return the new chain. + return NewStore.getValue(0); +} + SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { CodeGenOptLevel OptLevel = getTargetMachine().getOptLevel(); @@ -5578,6 +5623,8 @@ SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N, return PerformSETCCCombine(N, DCI, STI.getSmVersion()); case ISD::LOAD: return PerformLOADCombine(N, DCI); + case ISD::STORE: + return PerformSTORECombine(N, DCI); case NVPTXISD::StoreRetval: case NVPTXISD::StoreRetvalV2: case NVPTXISD::StoreRetvalV4: diff --git a/llvm/test/CodeGen/NVPTX/i8x4-instructions.ll b/llvm/test/CodeGen/NVPTX/i8x4-instructions.ll index 1ec68b4a271b..55cf6fb82576 100644 --- a/llvm/test/CodeGen/NVPTX/i8x4-instructions.ll +++ b/llvm/test/CodeGen/NVPTX/i8x4-instructions.ll @@ -790,10 +790,9 @@ define void @test_ldst_v8i8(ptr %a, ptr %b) { ; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ld.param.u64 %rd2, [test_ldst_v8i8_param_1]; ; CHECK-NEXT: ld.param.u64 %rd1, [test_ldst_v8i8_param_0]; -; CHECK-NEXT: ld.u32 %r1, [%rd1]; -; CHECK-NEXT: ld.u32 %r2, [%rd1+4]; -; CHECK-NEXT: st.u32 [%rd2+4], %r2; -; CHECK-NEXT: st.u32 [%rd2], %r1; +; CHECK-NEXT: ld.u32 %r1, [%rd1+4]; +; CHECK-NEXT: ld.u32 %r2, [%rd1]; +; CHECK-NEXT: st.v2.u32 [%rd2], {%r2, %r1}; ; CHECK-NEXT: ret; %t1 = load <8 x i8>, ptr %a store <8 x i8> %t1, ptr %b, align 16 diff --git a/llvm/test/CodeGen/NVPTX/vector-stores.ll b/llvm/test/CodeGen/NVPTX/vector-stores.ll index df14553a7720..8248bdbc1ee1 100644 --- a/llvm/test/CodeGen/NVPTX/vector-stores.ll +++ b/llvm/test/CodeGen/NVPTX/vector-stores.ll @@ -37,3 +37,19 @@ define void @v16i8(ptr %a, ptr %b) { store <16 x i8> %v, ptr %b ret void } + +; CHECK-LABEL: .visible .func v16i8_store +define void @v16i8_store(ptr %a, <16 x i8> %v) { + ; CHECK: ld.param.u64 %rd1, [v16i8_store_param_0]; + ; CHECK-NEXT: ld.param.v4.u32 {%r1, %r2, %r3, %r4}, [v16i8_store_param_1]; + ; CHECK-NEXT: st.v4.u32 [%rd1], {%r1, %r2, %r3, %r4}; + store <16 x i8> %v, ptr %a + ret void +} + +; CHECK-LABEL: .visible .func v8i8_store +define void @v8i8_store(ptr %a, <8 x i8> %v) { + ; CHECK: st.v2.u32 + store <8 x i8> %v, ptr %a + ret void +} -- GitLab From cf1a979ccfa722c3f9fce28c66c13a222990eac4 Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Fri, 1 Dec 2023 13:51:18 +0800 Subject: [PATCH 097/699] [RISCV] Minimally modify incoming state in transferBefore (#72352) transferBefore currently takes an incoming state and an instruction, computes the new state needed for the instruction, and then modifies that new state to be more similar to the incoming state. This patch reverses the approach by instead taking the incoming state and modifying only the bits that are demanded by the instruction. --- llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 51 +++++++++++++++++--- 1 file changed, 44 insertions(+), 7 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp index a174d762bf8c..323a92cfb8c8 100644 --- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp +++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp @@ -491,6 +491,8 @@ public: unsigned getSEW() const { return SEW; } RISCVII::VLMUL getVLMUL() const { return VLMul; } + bool getTailAgnostic() const { return TailAgnostic; } + bool getMaskAgnostic() const { return MaskAgnostic; } bool hasNonZeroAVL(const MachineRegisterInfo &MRI) const { if (hasAVLImm()) @@ -1040,9 +1042,13 @@ bool RISCVInsertVSETVLI::needVSETVLI(const MachineInstr &MI, return true; } -// Given an incoming state reaching MI, modifies that state so that it is minimally -// compatible with MI. The resulting state is guaranteed to be semantically legal -// for MI, but may not be the state requested by MI. +static VSETVLIInfo adjustIncoming(VSETVLIInfo PrevInfo, VSETVLIInfo NewInfo, + DemandedFields &Demanded, + const MachineRegisterInfo *MRI); + +// Given an incoming state reaching MI, minimally modifies that state so that it +// is compatible with MI. The resulting state is guaranteed to be semantically +// legal for MI, but may not be the state requested by MI. void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info, const MachineInstr &MI) const { uint64_t TSFlags = MI.getDesc().TSFlags; @@ -1055,20 +1061,47 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info, return; const VSETVLIInfo PrevInfo = Info; - Info = NewInfo; + if (Info.hasSEWLMULRatioOnly() || !Info.isValid() || Info.isUnknown()) + Info = NewInfo; - if (!RISCVII::hasVLOp(TSFlags)) + if (!RISCVII::hasVLOp(TSFlags)) { + Info = NewInfo; return; + } + + DemandedFields Demanded = getDemanded(MI, MRI, ST); + const VSETVLIInfo IncomingInfo = + adjustIncoming(PrevInfo, NewInfo, Demanded, MRI); + + if (Demanded.usedVL()) + Info.setAVL(IncomingInfo); + + Info.setVTYPE( + ((Demanded.LMUL || Demanded.SEWLMULRatio) ? IncomingInfo : Info) + .getVLMUL(), + ((Demanded.SEW || Demanded.SEWLMULRatio) ? IncomingInfo : Info).getSEW(), + // Prefer tail/mask agnostic since it can be relaxed to undisturbed later + // if needed. + (Demanded.TailPolicy ? IncomingInfo : Info).getTailAgnostic() || + IncomingInfo.getTailAgnostic(), + (Demanded.MaskPolicy ? IncomingInfo : Info).getMaskAgnostic() || + IncomingInfo.getMaskAgnostic()); +} + +static VSETVLIInfo adjustIncoming(VSETVLIInfo PrevInfo, VSETVLIInfo NewInfo, + DemandedFields &Demanded, + const MachineRegisterInfo *MRI) { + VSETVLIInfo Info = NewInfo; // If we don't use LMUL or the SEW/LMUL ratio, then adjust LMUL so that we // maintain the SEW/LMUL ratio. This allows us to eliminate VL toggles in more // places. - DemandedFields Demanded = getDemanded(MI, MRI, ST); if (!Demanded.LMUL && !Demanded.SEWLMULRatio && PrevInfo.isValid() && !PrevInfo.isUnknown()) { if (auto NewVLMul = RISCVVType::getSameRatioLMUL( PrevInfo.getSEW(), PrevInfo.getVLMUL(), Info.getSEW())) Info.setVLMul(*NewVLMul); + Demanded.LMUL = true; } // If we only demand VL zeroness (i.e. vmv.s.x and vmv.x.s), then there are @@ -1080,8 +1113,12 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info, // to prevent extending live range of an avl register operand. // TODO: We can probably relax this for immediates. if (Demanded.VLZeroness && !Demanded.VLAny && PrevInfo.isValid() && - PrevInfo.hasEquallyZeroAVL(Info, *MRI) && Info.hasSameVLMAX(PrevInfo)) + PrevInfo.hasEquallyZeroAVL(Info, *MRI) && Info.hasSameVLMAX(PrevInfo)) { Info.setAVL(PrevInfo); + Demanded.demandVL(); + } + + return Info; } // Given a state with which we evaluated MI (see transferBefore above for why -- GitLab From 58199dfb557752b1a7b782b140b033bd29d6f0e9 Mon Sep 17 00:00:00 2001 From: lifengxiang1025 <125553151+lifengxiang1025@users.noreply.github.com> Date: Fri, 1 Dec 2023 14:16:01 +0800 Subject: [PATCH 098/699] [NFC] Typo fix (#74033) Fix spelling error from `linakge` to `linkage`. Co-authored-by: lifengxiang --- llvm/include/llvm/ProfileData/SampleProf.h | 2 +- llvm/lib/MC/MCAsmStreamer.cpp | 2 +- llvm/tools/llvm-profdata/llvm-profdata.cpp | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/llvm/include/llvm/ProfileData/SampleProf.h b/llvm/include/llvm/ProfileData/SampleProf.h index a7edfecc1aa6..f001f5ee9d39 100644 --- a/llvm/include/llvm/ProfileData/SampleProf.h +++ b/llvm/include/llvm/ProfileData/SampleProf.h @@ -1561,7 +1561,7 @@ template <> struct DenseMapInfo { // Prepend "__uniq" before the hash for tools like profilers to understand // that this symbol is of internal linkage type. The "__uniq" is the // pre-determined prefix that is used to tell tools that this symbol was -// created with -funique-internal-linakge-symbols and the tools can strip or +// created with -funique-internal-linkage-symbols and the tools can strip or // keep the prefix as needed. inline std::string getUniqueInternalLinkagePostfix(const StringRef &FName) { llvm::MD5 Md5; diff --git a/llvm/lib/MC/MCAsmStreamer.cpp b/llvm/lib/MC/MCAsmStreamer.cpp index fb809f4010f7..5a157fc36d8e 100644 --- a/llvm/lib/MC/MCAsmStreamer.cpp +++ b/llvm/lib/MC/MCAsmStreamer.cpp @@ -190,7 +190,7 @@ public: void emitXCOFFLocalCommonSymbol(MCSymbol *LabelSym, uint64_t Size, MCSymbol *CsectSym, Align Alignment) override; void emitXCOFFSymbolLinkageWithVisibility(MCSymbol *Symbol, - MCSymbolAttr Linakge, + MCSymbolAttr Linkage, MCSymbolAttr Visibility) override; void emitXCOFFRenameDirective(const MCSymbol *Name, StringRef Rename) override; diff --git a/llvm/tools/llvm-profdata/llvm-profdata.cpp b/llvm/tools/llvm-profdata/llvm-profdata.cpp index b9df3f97c8fa..63e34d81f189 100644 --- a/llvm/tools/llvm-profdata/llvm-profdata.cpp +++ b/llvm/tools/llvm-profdata/llvm-profdata.cpp @@ -1006,12 +1006,12 @@ adjustInstrProfile(std::unique_ptr &WC, // If sample profile and instrumented profile do not agree on symbol // uniqification. if (SampleProfileHasFUnique != ProfileHasFUnique) { - // If instrumented profile uses -funique-internal-linakge-symbols, + // If instrumented profile uses -funique-internal-linkage-symbols, // we need to trim the name. if (ProfileHasFUnique) { NewName = NewName.substr(0, PostfixPos); } else { - // If sample profile uses -funique-internal-linakge-symbols, + // If sample profile uses -funique-internal-linkage-symbols, // we build the map. std::string NStr = NewName.str() + getUniqueInternalLinkagePostfix(FName); -- GitLab From 340cb19e153bb68981b7eb9562c74a0b2c4db214 Mon Sep 17 00:00:00 2001 From: lifengxiang1025 <125553151+lifengxiang1025@users.noreply.github.com> Date: Fri, 1 Dec 2023 14:20:19 +0800 Subject: [PATCH 099/699] [MemProf] Expand optimization scope to internal linkage function (#73236) Now MemProf can't do IR annotation right in the local linkage function and global initial function __cxx_global_var_init. In llvm-profdata which convert raw memory profile to memory profile, it uses function name in dwarf to create GUID. But when llvm consumes memory profile, it use `getIRPGOFuncName` or `getPGOFuncName` which returns local linkage function as `FileName;FunctionName` or `FileName:FunctionName` to get function name and create GUID. So profile creator's GUID is not same as profile consumer. So I think MemProf should be used with `unique-internal-linkage-names` and don't use PGOFuncName. __cxx_global_var_init is created later than where UniqueInternalLinkageNames works. So I add uniq suffix to __cxx_global_var_init additionally. Co-authored-by: lifengxiang --- .../Instrumentation/MemProfiler.cpp | 24 ++--- .../Inputs/memprof_internal_linkage.exe | Bin 0 -> 1519520 bytes .../memprof_internal_linkage.memprofraw | Bin 0 -> 1136 bytes .../Inputs/update_memprof_inputs.sh | 18 ++++ .../PGOProfile/memprof_internal_linkage.ll | 84 ++++++++++++++++++ 5 files changed, 110 insertions(+), 16 deletions(-) create mode 100755 llvm/test/Transforms/PGOProfile/Inputs/memprof_internal_linkage.exe create mode 100644 llvm/test/Transforms/PGOProfile/Inputs/memprof_internal_linkage.memprofraw create mode 100644 llvm/test/Transforms/PGOProfile/memprof_internal_linkage.ll diff --git a/llvm/lib/Transforms/Instrumentation/MemProfiler.cpp b/llvm/lib/Transforms/Instrumentation/MemProfiler.cpp index c6134ce77136..539b7441d24b 100644 --- a/llvm/lib/Transforms/Instrumentation/MemProfiler.cpp +++ b/llvm/lib/Transforms/Instrumentation/MemProfiler.cpp @@ -676,25 +676,17 @@ static void readMemprof(Module &M, Function &F, IndexedInstrProfReader *MemProfReader, const TargetLibraryInfo &TLI) { auto &Ctx = M.getContext(); - - auto FuncName = getIRPGOFuncName(F); + // Previously we used getIRPGOFuncName() here. If F is local linkage, + // getIRPGOFuncName() returns FuncName with prefix 'FileName;'. But + // llvm-profdata uses FuncName in dwarf to create GUID which doesn't + // contain FileName's prefix. It caused local linkage function can't + // find MemProfRecord. So we use getName() now. + // 'unique-internal-linkage-names' can make MemProf work better for local + // linkage function. + auto FuncName = F.getName(); auto FuncGUID = Function::getGUID(FuncName); std::optional MemProfRec; auto Err = MemProfReader->getMemProfRecord(FuncGUID).moveInto(MemProfRec); - if (Err) { - // If we don't find getIRPGOFuncName(), try getPGOFuncName() to handle - // profiles built by older compilers - Err = handleErrors(std::move(Err), [&](const InstrProfError &IE) -> Error { - if (IE.get() != instrprof_error::unknown_function) - return make_error(IE); - auto FuncName = getPGOFuncName(F); - auto FuncGUID = Function::getGUID(FuncName); - if (auto Err = - MemProfReader->getMemProfRecord(FuncGUID).moveInto(MemProfRec)) - return Err; - return Error::success(); - }); - } if (Err) { handleAllErrors(std::move(Err), [&](const InstrProfError &IPE) { auto Err = IPE.get(); diff --git a/llvm/test/Transforms/PGOProfile/Inputs/memprof_internal_linkage.exe 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binary patch literal 1136 zcmZoHO3N=Q$o?F<5M!1^N( zd;`-A4UfSzO#gz=6G}=Rm0xZ?R+;=bw`BJ0J3n1f^edbJtN+V#4Wd8bG>ZO?*jwIS zF|QK%s-tHdT-!D?r&nnviv9&B!Rme6PC@iLK=?5GUkZxMsA6>A%gS|kZ=~FgnckXT zHlyf2a00CF0j_%!a>8gJsivADB!1i};I1X|D1_&Q!KU0qN!t`(c$#Od?)@M0kT1uT!8E* zn0wG^nEyaD2*d0~w-e+J5XJ>qp%Ne(ggb;G0w5ZMk=+84f${5%G{6c&OCb3VCJrqg V81~+Slm{0-Lg-acdX@qtz5(NY06G8w literal 0 HcmV?d00001 diff --git a/llvm/test/Transforms/PGOProfile/Inputs/update_memprof_inputs.sh b/llvm/test/Transforms/PGOProfile/Inputs/update_memprof_inputs.sh index 4261c2c5fbe3..74e7e36641b4 100755 --- a/llvm/test/Transforms/PGOProfile/Inputs/update_memprof_inputs.sh +++ b/llvm/test/Transforms/PGOProfile/Inputs/update_memprof_inputs.sh @@ -127,3 +127,21 @@ ${CLANG} ${COMMON_FLAGS} -fmemory-profile -DUSE_MUSTTAIL=1 ${OUTDIR}/memprof_mis env MEMPROF_OPTIONS=log_path=stdout ${OUTDIR}/memprof_missing_leaf.exe > ${OUTDIR}/memprof_missing_leaf.memprofraw rm ${OUTDIR}/memprof_missing_leaf.cc + +cat > ${OUTDIR}/memprof_internal_linkage.cc << EOF +#include +#include +static void foo() { + int *a = new int[5]; + memset(a, 0, 5); +} +int main(int argc, char **argv) { + foo(); + return 0; +} +EOF + +${CLANG} ${COMMON_FLAGS} -fmemory-profile -funique-internal-linkage-names ${OUTDIR}/memprof_internal_linkage.cc -o ${OUTDIR}/memprof_internal_linkage.exe +env MEMPROF_OPTIONS=log_path=stdout ${OUTDIR}/memprof_internal_linkage.exe > ${OUTDIR}/memprof_internal_linkage.memprofraw + +rm ${OUTDIR}/memprof_internal_linkage.cc \ No newline at end of file diff --git a/llvm/test/Transforms/PGOProfile/memprof_internal_linkage.ll b/llvm/test/Transforms/PGOProfile/memprof_internal_linkage.ll new file mode 100644 index 000000000000..3d4b93c85ddf --- /dev/null +++ b/llvm/test/Transforms/PGOProfile/memprof_internal_linkage.ll @@ -0,0 +1,84 @@ +;; Tests memprof when contains internal linkage function. + +;; Avoid failures on big-endian systems that can't read the profile properly +; REQUIRES: x86_64-linux + +;; TODO: Use text profile inputs once that is available for memprof. +;; # To update the Inputs below, run Inputs/update_memprof_inputs.sh. +;; # To generate below LLVM IR for use in matching. +;; $ clang++ -gmlt -fdebug-info-for-profiling -S %S/Inputs/memprof_internal_linkage.cc -emit-llvm -funique-internal-linkage-names + +; RUN: llvm-profdata merge %S/Inputs/memprof_internal_linkage.memprofraw --profiled-binary %S/Inputs/memprof_internal_linkage.exe -o %t.memprofdata +; RUN: opt < %s -passes='memprof-use' -S | FileCheck %s + +; CHECK: call {{.*}} @_Znam{{.*}} #[[ATTR:[0-9]+]] +; CHECK: attributes #[[ATTR]] = { builtin allocsize(0) "memprof"="notcold" } + +; ModuleID = 'memprof_internal_linkage.cc' +source_filename = "memprof_internal_linkage.cc" +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +; Function Attrs: mustprogress noinline norecurse optnone uwtable +define dso_local noundef i32 @main(i32 noundef %argc, ptr noundef %argv) #0 !dbg !10 { +entry: + %retval = alloca i32, align 4 + %argc.addr = alloca i32, align 4 + %argv.addr = alloca ptr, align 8 + store i32 0, ptr %retval, align 4 + store i32 %argc, ptr %argc.addr, align 4 + store ptr %argv, ptr %argv.addr, align 8 + call void @_ZL3foov.__uniq.231888424933890731874095357293037629092() #4, !dbg !14 + ret i32 0, !dbg !15 +} + +; Function Attrs: mustprogress noinline optnone uwtable +define internal void @_ZL3foov.__uniq.231888424933890731874095357293037629092() #1 !dbg !16 { +entry: + %a = alloca ptr, align 8 + %call = call noalias noundef nonnull ptr @_Znam(i64 noundef 20) #5, !dbg !17 + store ptr %call, ptr %a, align 8, !dbg !18 + %0 = load ptr, ptr %a, align 8, !dbg !19 + call void @llvm.memset.p0.i64(ptr align 4 %0, i8 0, i64 5, i1 false), !dbg !20 + ret void, !dbg !21 +} + +; Function Attrs: nobuiltin allocsize(0) +declare noundef nonnull ptr @_Znam(i64 noundef) #2 + +; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write) +declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #3 + +attributes #0 = { mustprogress noinline norecurse optnone uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" } +attributes #1 = { mustprogress noinline optnone uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "sample-profile-suffix-elision-policy"="selected" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" } +attributes #2 = { nobuiltin allocsize(0) "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" } +attributes #3 = { nocallback nofree nounwind willreturn memory(argmem: write) } +attributes #4 = { "sample-profile-suffix-elision-policy"="selected" } +attributes #5 = { builtin allocsize(0) } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3, !4, !5, !6, !7, !8} +!llvm.ident = !{!9} + +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang version 18.0.0 (https://github.com/llvm/llvm-project.git a604a1112a611ea867dc4e8d164021c7b055e18a)", isOptimized: false, runtimeVersion: 0, emissionKind: LineTablesOnly, splitDebugInlining: false, debugInfoForProfiling: true, nameTableKind: None) +!1 = !DIFile(filename: "memprof_internal_linkage.cc", directory: ".", checksumkind: CSK_MD5, checksum: "de848419432086fd9ed6dda04f3bf0ac") +!2 = !{i32 7, !"Dwarf Version", i32 5} +!3 = !{i32 2, !"Debug Info Version", i32 3} +!4 = !{i32 1, !"wchar_size", i32 4} +!5 = !{i32 8, !"PIC Level", i32 2} +!6 = !{i32 7, !"PIE Level", i32 2} +!7 = !{i32 7, !"uwtable", i32 2} +!8 = !{i32 7, !"frame-pointer", i32 2} +!9 = !{!"clang version 18.0.0 (https://github.com/llvm/llvm-project.git a604a1112a611ea867dc4e8d164021c7b055e18a)"} +!10 = distinct !DISubprogram(name: "main", scope: !11, file: !11, line: 7, type: !12, scopeLine: 7, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0) +!11 = !DIFile(filename: "memprof_internal_linkage.cc", directory: ".", checksumkind: CSK_MD5, checksum: "de848419432086fd9ed6dda04f3bf0ac") +!12 = !DISubroutineType(types: !13) +!13 = !{} +!14 = !DILocation(line: 8, column: 3, scope: !10) +!15 = !DILocation(line: 9, column: 3, scope: !10) +!16 = distinct !DISubprogram(name: "foo", linkageName: "_ZL3foov.__uniq.231888424933890731874095357293037629092", scope: !11, file: !11, line: 3, type: !12, scopeLine: 3, flags: DIFlagPrototyped, spFlags: DISPFlagLocalToUnit | DISPFlagDefinition, unit: !0) +!17 = !DILocation(line: 4, column: 12, scope: !16) +!18 = !DILocation(line: 4, column: 8, scope: !16) +!19 = !DILocation(line: 5, column: 10, scope: !16) +!20 = !DILocation(line: 5, column: 3, scope: !16) +!21 = !DILocation(line: 6, column: 1, scope: !16) \ No newline at end of file -- GitLab From 71ba05b4e1ccbfdc2bc35906a985744ad785e676 Mon Sep 17 00:00:00 2001 From: Brad Smith Date: Fri, 1 Dec 2023 01:25:25 -0500 Subject: [PATCH 100/699] [ADT] Make use of the endian.h header on NetBSD and DragonFly (#74037) Move away from machine/endian.h to POSIX endian.h header. --- llvm/include/llvm/ADT/bit.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/llvm/include/llvm/ADT/bit.h b/llvm/include/llvm/ADT/bit.h index 12223facbb30..c42b5e686bdc 100644 --- a/llvm/include/llvm/ADT/bit.h +++ b/llvm/include/llvm/ADT/bit.h @@ -28,7 +28,8 @@ #endif #if defined(__linux__) || defined(__GNU__) || defined(__HAIKU__) || \ - defined(__Fuchsia__) || defined(__EMSCRIPTEN__) || defined(__OpenBSD__) + defined(__Fuchsia__) || defined(__EMSCRIPTEN__) || defined(__NetBSD__) || \ + defined(__OpenBSD__) || defined(__DragonFly__) #include #elif defined(_AIX) #include -- GitLab From 5ecb37b45aa059cadd97ab6aedc1320da609c636 Mon Sep 17 00:00:00 2001 From: Piyou Chen Date: Fri, 1 Dec 2023 01:04:42 -0600 Subject: [PATCH 101/699] [RISCV] Make InitUndef handle undef operand (#65755) Address https://github.com/llvm/llvm-project/issues/65704. If the operand is marked as undef, the InitUndef misses this case. This patch makes InitUndef pass handle the undef operand case. --- llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp | 94 +++++++++---------- .../RISCV/65704-illegal-instruction.ll | 57 +++++++++++ .../rvv/handle-noreg-with-implicit-def.mir | 7 +- .../RISCV/rvv/undef-earlyclobber-chain.mir | 4 +- 4 files changed, 106 insertions(+), 56 deletions(-) create mode 100644 llvm/test/CodeGen/RISCV/65704-illegal-instruction.ll diff --git a/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp b/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp index f519e3b2fd3b..ff7718c9ef6d 100644 --- a/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp +++ b/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp @@ -80,13 +80,13 @@ public: private: bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB, const DeadLaneDetector &DLD); - bool handleImplicitDef(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &Inst); bool isVectorRegClass(const Register R); const TargetRegisterClass * getVRLargestSuperClass(const TargetRegisterClass *RC) const; bool handleSubReg(MachineFunction &MF, MachineInstr &MI, const DeadLaneDetector &DLD); + bool fixupIllOperand(MachineInstr *MI, MachineOperand &MO); + bool handleReg(MachineInstr *MI); }; } // end anonymous namespace @@ -137,53 +137,30 @@ static bool isEarlyClobberMI(MachineInstr &MI) { }); } -bool RISCVInitUndef::handleImplicitDef(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &Inst) { - assert(Inst->getOpcode() == TargetOpcode::IMPLICIT_DEF); - - Register Reg = Inst->getOperand(0).getReg(); - if (!Reg.isVirtual()) - return false; - - bool HasOtherUse = false; - SmallVector UseMOs; - for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) { - if (isEarlyClobberMI(*MO.getParent())) { - if (MO.isUse() && !MO.isTied()) - UseMOs.push_back(&MO); - else - HasOtherUse = true; - } +static bool findImplictDefMIFromReg(Register Reg, MachineRegisterInfo *MRI) { + for (auto &DefMI : MRI->def_instructions(Reg)) { + if (DefMI.getOpcode() == TargetOpcode::IMPLICIT_DEF) + return true; } + return false; +} - if (UseMOs.empty()) - return false; - - LLVM_DEBUG( - dbgs() << "Emitting PseudoRVVInitUndef for implicit vector register " - << Reg << '\n'); - - const TargetRegisterClass *TargetRegClass = - getVRLargestSuperClass(MRI->getRegClass(Reg)); - unsigned Opcode = getUndefInitOpcode(TargetRegClass->getID()); - - Register NewDest = Reg; - if (HasOtherUse) { - NewDest = MRI->createVirtualRegister(TargetRegClass); - // We don't have a way to update dead lanes, so keep track of the - // new register so that we avoid querying it later. - NewRegs.insert(NewDest); - } - BuildMI(MBB, Inst, Inst->getDebugLoc(), TII->get(Opcode), NewDest); - - if (!HasOtherUse) - DeadInsts.push_back(&(*Inst)); +bool RISCVInitUndef::handleReg(MachineInstr *MI) { + bool Changed = false; + for (auto &UseMO : MI->uses()) { + if (!UseMO.isReg()) + continue; + if (UseMO.isTied()) + continue; + if (!UseMO.getReg().isVirtual()) + continue; + if (!isVectorRegClass(UseMO.getReg())) + continue; - for (auto MO : UseMOs) { - MO->setReg(NewDest); - MO->setIsUndef(false); + if (UseMO.isUndef() || findImplictDefMIFromReg(UseMO.getReg(), MRI)) + Changed |= fixupIllOperand(MI, UseMO); } - return true; + return Changed; } bool RISCVInitUndef::handleSubReg(MachineFunction &MF, MachineInstr &MI, @@ -248,6 +225,23 @@ bool RISCVInitUndef::handleSubReg(MachineFunction &MF, MachineInstr &MI, return Changed; } +bool RISCVInitUndef::fixupIllOperand(MachineInstr *MI, MachineOperand &MO) { + + LLVM_DEBUG( + dbgs() << "Emitting PseudoRVVInitUndef for implicit vector register " + << MO.getReg() << '\n'); + + const TargetRegisterClass *TargetRegClass = + getVRLargestSuperClass(MRI->getRegClass(MO.getReg())); + unsigned Opcode = getUndefInitOpcode(TargetRegClass->getID()); + Register NewReg = MRI->createVirtualRegister(TargetRegClass); + BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(Opcode), NewReg); + MO.setReg(NewReg); + if (MO.isUndef()) + MO.setIsUndef(false); + return true; +} + bool RISCVInitUndef::processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB, const DeadLaneDetector &DLD) { @@ -274,12 +268,10 @@ bool RISCVInitUndef::processBasicBlock(MachineFunction &MF, } } - if (ST->enableSubRegLiveness() && isEarlyClobberMI(MI)) - Changed |= handleSubReg(MF, MI, DLD); - if (MI.isImplicitDef()) { - auto DstReg = MI.getOperand(0).getReg(); - if (DstReg.isVirtual() && isVectorRegClass(DstReg)) - Changed |= handleImplicitDef(MBB, I); + if (isEarlyClobberMI(MI)) { + if (ST->enableSubRegLiveness()) + Changed |= handleSubReg(MF, MI, DLD); + Changed |= handleReg(&MI); } } return Changed; diff --git a/llvm/test/CodeGen/RISCV/65704-illegal-instruction.ll b/llvm/test/CodeGen/RISCV/65704-illegal-instruction.ll new file mode 100644 index 000000000000..3181fa60cfa2 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/65704-illegal-instruction.ll @@ -0,0 +1,57 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc -mtriple=riscv64 -mattr=+v,+f,+m,+zfh,+zvfh \ +; RUN: < %s | FileCheck %s + +declare <16 x i8> @llvm.vector.extract.v16i8.nxv8i8(, i64 immarg) +declare @llvm.vector.insert.nxv8i8.v16i8(, <16 x i8>, i64 immarg) +declare @llvm.riscv.vslideup.nxv8i8.i64(, , i64, i64, i64 immarg) +declare @llvm.vector.insert.nxv2i32.v4i32(, <4 x i32>, i64 immarg) + +define void @foo( %0) { +; CHECK-LABEL: foo: +; CHECK: # %bb.0: +; CHECK-NEXT: addi sp, sp, -32 +; CHECK-NEXT: .cfi_def_cfa_offset 32 +; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill +; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill +; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill +; CHECK-NEXT: .cfi_offset ra, -8 +; CHECK-NEXT: .cfi_offset s0, -16 +; CHECK-NEXT: .cfi_offset s1, -24 +; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vsetivli zero, 0, e8, m1, tu, ma +; CHECK-NEXT: vslideup.vi v9, v10, 0 +; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma +; CHECK-NEXT: vmv.x.s s0, v9 +; CHECK-NEXT: vsetivli zero, 0, e8, m1, tu, ma +; CHECK-NEXT: vslideup.vi v8, v9, 0 +; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma +; CHECK-NEXT: vmv.x.s s1, v8 +; CHECK-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: li a1, 0 +; CHECK-NEXT: mv a0, s0 +; CHECK-NEXT: mv a2, s1 +; CHECK-NEXT: li a3, 0 +; CHECK-NEXT: li a4, 0 +; CHECK-NEXT: li a5, 0 +; CHECK-NEXT: jalr a1 +; CHECK-NEXT: j .LBB0_1 + %2 = tail call @llvm.vector.insert.nxv8i8.v16i8( undef, <16 x i8> undef, i64 0) + %3 = tail call @llvm.vector.insert.nxv8i8.v16i8( undef, <16 x i8> poison, i64 0) + br label %4 + +4: ; preds = %4, %1 + %5 = tail call @llvm.riscv.vslideup.nxv8i8.i64( zeroinitializer, %2, i64 0, i64 0, i64 0) + %6 = tail call <16 x i8> @llvm.vector.extract.v16i8.nxv8i8( %5, i64 0) + %7 = bitcast <16 x i8> %6 to <2 x i64> + %8 = extractelement <2 x i64> %7, i64 0 + %9 = insertvalue [2 x i64] zeroinitializer, i64 %8, 0 + %10 = tail call @llvm.riscv.vslideup.nxv8i8.i64( %0, %3, i64 0, i64 0, i64 0) + %11 = tail call <16 x i8> @llvm.vector.extract.v16i8.nxv8i8( %10, i64 0) + %12 = bitcast <16 x i8> %11 to <2 x i64> + %13 = extractelement <2 x i64> %12, i64 0 + %14 = insertvalue [2 x i64] zeroinitializer, i64 %13, 0 + %15 = tail call fastcc [2 x i64] null([2 x i64] %9, [2 x i64] %14, [2 x i64] zeroinitializer) + br label %4 +} diff --git a/llvm/test/CodeGen/RISCV/rvv/handle-noreg-with-implicit-def.mir b/llvm/test/CodeGen/RISCV/rvv/handle-noreg-with-implicit-def.mir index 9ed3de951d03..4102aa8aa4d7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/handle-noreg-with-implicit-def.mir +++ b/llvm/test/CodeGen/RISCV/rvv/handle-noreg-with-implicit-def.mir @@ -7,9 +7,10 @@ tracksRegLiveness: true body: | bb.0.entry: ; MIR-LABEL: name: vrgather_all_undef - ; MIR: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1 - ; MIR-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; MIR-NEXT: early-clobber %1:vr = PseudoVRGATHER_VI_M1 [[DEF]], killed [[PseudoRVVInitUndefM1_]], 0, 0, 5 /* e32 */, 0 /* tu, mu */ + ; MIR: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; MIR-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF + ; MIR-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1 + ; MIR-NEXT: early-clobber %1:vr = PseudoVRGATHER_VI_M1 [[DEF1]], killed [[PseudoRVVInitUndefM1_]], 0, 0, 5 /* e32 */, 0 /* tu, mu */ ; MIR-NEXT: $v8 = COPY %1 ; MIR-NEXT: PseudoRET implicit $v8 %2:vr = IMPLICIT_DEF diff --git a/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir b/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir index 08ea967179eb..58b2687824aa 100644 --- a/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir +++ b/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir @@ -76,9 +76,9 @@ machineFunctionInfo: body: | bb.0.entry: ; CHECK-LABEL: name: undef_early_clobber_chain - ; CHECK: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1 - ; CHECK-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; CHECK: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1 ; CHECK-NEXT: early-clobber %1:vr = PseudoVRGATHER_VI_M1 undef [[DEF]], [[PseudoRVVInitUndefM1_]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: $v8 = COPY %1 ; CHECK-NEXT: PseudoRET implicit $v8 -- GitLab From c1ad363e6eba308fa94c47374ee98b3c79693a35 Mon Sep 17 00:00:00 2001 From: Younan Zhang Date: Fri, 1 Dec 2023 15:20:04 +0800 Subject: [PATCH 102/699] [clang] Use the materialized temporary's type while creating the APValue (#73355) See https://github.com/llvm/llvm-project/issues/72025 for the bug and its diagnosis. --- clang/docs/ReleaseNotes.rst | 3 +++ clang/lib/AST/ExprConstant.cpp | 2 +- clang/test/SemaCXX/pr72025.cpp | 9 +++++++++ 3 files changed, 13 insertions(+), 1 deletion(-) create mode 100644 clang/test/SemaCXX/pr72025.cpp diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 748e2db2f850..43ea6a3ffd6e 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -789,6 +789,9 @@ Bug Fixes to C++ Support Fixes: (`#68769 `_) +- Fixed a crash for C++98/03 while checking an ill-formed ``_Static_assert`` expression. + Fixes: (`#72025 `_) + - Clang now defers the instantiation of explicit specifier until constraint checking completes (except deduction guides). Fixes: (`#59827 `_) diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp index 2aafe5bd5289..986302e1fd22 100644 --- a/clang/lib/AST/ExprConstant.cpp +++ b/clang/lib/AST/ExprConstant.cpp @@ -8618,7 +8618,7 @@ bool LValueExprEvaluator::VisitMaterializeTemporaryExpr( Result.set(E); } else { Value = &Info.CurrentCall->createTemporary( - E, E->getType(), + E, Inner->getType(), E->getStorageDuration() == SD_FullExpression ? ScopeKind::FullExpression : ScopeKind::Block, Result); diff --git a/clang/test/SemaCXX/pr72025.cpp b/clang/test/SemaCXX/pr72025.cpp new file mode 100644 index 000000000000..9f0a4b0f4363 --- /dev/null +++ b/clang/test/SemaCXX/pr72025.cpp @@ -0,0 +1,9 @@ +// RUN: %clang_cc1 -verify -std=c++03 -fsyntax-only %s +struct V { + char c[2]; + banana V() : c("i") {} // expected-error {{unknown type name}} + // expected-error@-1 {{constructor cannot have a return type}} +}; + +_Static_assert(V().c[0], ""); // expected-error {{is not an integral constant expression}} + -- GitLab From e017169dbd0215e892570e74668f5c3289db3310 Mon Sep 17 00:00:00 2001 From: Shengchen Kan Date: Fri, 1 Dec 2023 15:09:27 +0800 Subject: [PATCH 103/699] [X86][NFC] Extract ReplaceableInstrs to a separate file and clang-format X86InstrInfo.cpp --- llvm/lib/Target/X86/X86InstrInfo.cpp | 4056 ++++++++++-------- llvm/lib/Target/X86/X86ReplaceableInstrs.def | 426 ++ 2 files changed, 2640 insertions(+), 1842 deletions(-) create mode 100644 llvm/lib/Target/X86/X86ReplaceableInstrs.def diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index b75c00effead..583f8ec73a03 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -58,26 +58,25 @@ static cl::opt cl::desc("Disable fusing of spill code into instructions"), cl::Hidden); static cl::opt -PrintFailedFusing("print-failed-fuse-candidates", - cl::desc("Print instructions that the allocator wants to" - " fuse, but the X86 backend currently can't"), - cl::Hidden); + PrintFailedFusing("print-failed-fuse-candidates", + cl::desc("Print instructions that the allocator wants to" + " fuse, but the X86 backend currently can't"), + cl::Hidden); static cl::opt -ReMatPICStubLoad("remat-pic-stub-load", - cl::desc("Re-materialize load from stub in PIC mode"), - cl::init(false), cl::Hidden); + ReMatPICStubLoad("remat-pic-stub-load", + cl::desc("Re-materialize load from stub in PIC mode"), + cl::init(false), cl::Hidden); static cl::opt -PartialRegUpdateClearance("partial-reg-update-clearance", - cl::desc("Clearance between two register writes " - "for inserting XOR to avoid partial " - "register update"), - cl::init(64), cl::Hidden); -static cl::opt -UndefRegClearance("undef-reg-clearance", - cl::desc("How many idle instructions we would like before " - "certain undef register reads"), - cl::init(128), cl::Hidden); - + PartialRegUpdateClearance("partial-reg-update-clearance", + cl::desc("Clearance between two register writes " + "for inserting XOR to avoid partial " + "register update"), + cl::init(64), cl::Hidden); +static cl::opt UndefRegClearance( + "undef-reg-clearance", + cl::desc("How many idle instructions we would like before " + "certain undef register reads"), + cl::init(128), cl::Hidden); // Pin the vtable to this file. void X86InstrInfo::anchor() {} @@ -87,10 +86,8 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI) : X86::ADJCALLSTACKDOWN32), (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 : X86::ADJCALLSTACKUP32), - X86::CATCHRET, - (STI.is64Bit() ? X86::RET64 : X86::RET32)), - Subtarget(STI), RI(STI.getTargetTriple()) { -} + X86::CATCHRET, (STI.is64Bit() ? X86::RET64 : X86::RET32)), + Subtarget(STI), RI(STI.getTargetTriple()) {} const TargetRegisterClass * X86InstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, @@ -123,12 +120,12 @@ X86InstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, } } -bool -X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI, - Register &SrcReg, Register &DstReg, - unsigned &SubIdx) const { +bool X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI, + Register &SrcReg, Register &DstReg, + unsigned &SubIdx) const { switch (MI.getOpcode()) { - default: break; + default: + break; case X86::MOVSX16rr8: case X86::MOVZX16rr8: case X86::MOVSX32rr8: @@ -149,7 +146,8 @@ X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI, SrcReg = MI.getOperand(1).getReg(); DstReg = MI.getOperand(0).getReg(); switch (MI.getOpcode()) { - default: llvm_unreachable("Unreachable!"); + default: + llvm_unreachable("Unreachable!"); case X86::MOVSX16rr8: case X86::MOVZX16rr8: case X86::MOVSX32rr8: @@ -441,8 +439,7 @@ int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const { const MachineBasicBlock *MBB = MI.getParent(); auto I = ++MachineBasicBlock::const_iterator(MI); for (auto E = MBB->end(); I != E; ++I) { - if (I->getOpcode() == getCallFrameDestroyOpcode() || - I->isCall()) + if (I->getOpcode() == getCallFrameDestroyOpcode() || I->isCall()) break; } @@ -764,7 +761,8 @@ static bool regIsPICBase(Register BaseReg, const MachineRegisterInfo &MRI) { return false; bool isPICBase = false; for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg), - E = MRI.def_instr_end(); I != E; ++I) { + E = MRI.def_instr_end(); + I != E; ++I) { MachineInstr *DefMI = &*I; if (DefMI->getOpcode() != X86::MOVPC32r) return false; @@ -952,9 +950,15 @@ void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB, // effects. int Value; switch (Orig.getOpcode()) { - case X86::MOV32r0: Value = 0; break; - case X86::MOV32r1: Value = 1; break; - case X86::MOV32r_1: Value = -1; break; + case X86::MOV32r0: + Value = 0; + break; + case X86::MOV32r1: + Value = 1; + break; + case X86::MOV32r_1: + Value = -1; + break; default: llvm_unreachable("Unexpected instruction!"); } @@ -975,8 +979,8 @@ void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB, /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead. bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const { for (const MachineOperand &MO : MI.operands()) { - if (MO.isReg() && MO.isDef() && - MO.getReg() == X86::EFLAGS && !MO.isDead()) { + if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS && + !MO.isDead()) { return true; } } @@ -1131,8 +1135,7 @@ bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src, if (AllowSP) { RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass; } else { - RC = Opc != X86::LEA32r ? - &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass; + RC = Opc != X86::LEA32r ? &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass; } Register SrcReg = Src.getReg(); isKill = MI.killsRegister(SrcReg); @@ -1195,7 +1198,8 @@ MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc, // We handle 8-bit adds and various 16-bit opcodes in the switch below. MachineBasicBlock &MBB = *MI.getParent(); MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); - assert((Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits( + assert((Is8BitOp || + RegInfo.getTargetRegisterInfo()->getRegSizeInBits( *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) && "Unexpected type for LEA transform"); @@ -1241,7 +1245,8 @@ MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc, MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), get(Opcode), OutRegLEA); switch (MIOpc) { - default: llvm_unreachable("Unreachable!"); + default: + llvm_unreachable("Unreachable!"); case X86::SHL8ri: case X86::SHL16ri: { unsigned ShAmt = MI.getOperand(2).getImm(); @@ -1399,11 +1404,13 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI, unsigned NumRegOperands = 2; unsigned MIOpc = MI.getOpcode(); switch (MIOpc) { - default: llvm_unreachable("Unreachable!"); + default: + llvm_unreachable("Unreachable!"); case X86::SHL64ri: { assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!"); unsigned ShAmt = getTruncatedShiftCount(MI, 2); - if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr; + if (!isTruncatedShiftCountForLEA(ShAmt)) + return nullptr; // LEA can't handle RSP. if (Src.getReg().isVirtual() && !MF.getRegInfo().constrainRegClass( @@ -1422,7 +1429,8 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI, case X86::SHL32ri: { assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!"); unsigned ShAmt = getTruncatedShiftCount(MI, 2); - if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr; + if (!isTruncatedShiftCountForLEA(ShAmt)) + return nullptr; unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r; @@ -1433,14 +1441,13 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI, ImplicitOp, LV, LIS)) return nullptr; - MachineInstrBuilder MIB = - BuildMI(MF, MI.getDebugLoc(), get(Opc)) - .add(Dest) - .addReg(0) - .addImm(1LL << ShAmt) - .addReg(SrcReg, getKillRegState(isKill)) - .addImm(0) - .addReg(0); + MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)) + .add(Dest) + .addReg(0) + .addImm(1LL << ShAmt) + .addReg(SrcReg, getKillRegState(isKill)) + .addImm(0) + .addReg(0); if (ImplicitOp.getReg() != 0) MIB.add(ImplicitOp); NewMI = MIB; @@ -1463,18 +1470,18 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI, case X86::INC64r: case X86::INC32r: { assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!"); - unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r : - (Is64Bit ? X86::LEA64_32r : X86::LEA32r); + unsigned Opc = MIOpc == X86::INC64r + ? X86::LEA64r + : (Is64Bit ? X86::LEA64_32r : X86::LEA32r); bool isKill; MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, SrcReg, isKill, ImplicitOp, LV, LIS)) return nullptr; - MachineInstrBuilder MIB = - BuildMI(MF, MI.getDebugLoc(), get(Opc)) - .add(Dest) - .addReg(SrcReg, getKillRegState(isKill)); + MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)) + .add(Dest) + .addReg(SrcReg, getKillRegState(isKill)); if (ImplicitOp.getReg() != 0) MIB.add(ImplicitOp); @@ -1488,8 +1495,9 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI, case X86::DEC64r: case X86::DEC32r: { assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!"); - unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r - : (Is64Bit ? X86::LEA64_32r : X86::LEA32r); + unsigned Opc = MIOpc == X86::DEC64r + ? X86::LEA64r + : (Is64Bit ? X86::LEA64_32r : X86::LEA32r); bool isKill; MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); @@ -1654,8 +1662,8 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI, assert(MI.getNumOperands() >= 3 && "Unknown sub instruction!"); - MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), - get(X86::LEA64r)).add(Dest).add(Src); + MachineInstrBuilder MIB = + BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src); NewMI = addOffset(MIB, -Imm); break; } @@ -1666,18 +1674,30 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI, case X86::VMOVDQU16Z128rmk: case X86::VMOVDQU16Z256rmk: case X86::VMOVDQU16Zrmk: - case X86::VMOVDQU32Z128rmk: case X86::VMOVDQA32Z128rmk: - case X86::VMOVDQU32Z256rmk: case X86::VMOVDQA32Z256rmk: - case X86::VMOVDQU32Zrmk: case X86::VMOVDQA32Zrmk: - case X86::VMOVDQU64Z128rmk: case X86::VMOVDQA64Z128rmk: - case X86::VMOVDQU64Z256rmk: case X86::VMOVDQA64Z256rmk: - case X86::VMOVDQU64Zrmk: case X86::VMOVDQA64Zrmk: - case X86::VMOVUPDZ128rmk: case X86::VMOVAPDZ128rmk: - case X86::VMOVUPDZ256rmk: case X86::VMOVAPDZ256rmk: - case X86::VMOVUPDZrmk: case X86::VMOVAPDZrmk: - case X86::VMOVUPSZ128rmk: case X86::VMOVAPSZ128rmk: - case X86::VMOVUPSZ256rmk: case X86::VMOVAPSZ256rmk: - case X86::VMOVUPSZrmk: case X86::VMOVAPSZrmk: + case X86::VMOVDQU32Z128rmk: + case X86::VMOVDQA32Z128rmk: + case X86::VMOVDQU32Z256rmk: + case X86::VMOVDQA32Z256rmk: + case X86::VMOVDQU32Zrmk: + case X86::VMOVDQA32Zrmk: + case X86::VMOVDQU64Z128rmk: + case X86::VMOVDQA64Z128rmk: + case X86::VMOVDQU64Z256rmk: + case X86::VMOVDQA64Z256rmk: + case X86::VMOVDQU64Zrmk: + case X86::VMOVDQA64Zrmk: + case X86::VMOVUPDZ128rmk: + case X86::VMOVAPDZ128rmk: + case X86::VMOVUPDZ256rmk: + case X86::VMOVAPDZ256rmk: + case X86::VMOVUPDZrmk: + case X86::VMOVAPDZrmk: + case X86::VMOVUPSZ128rmk: + case X86::VMOVAPSZ128rmk: + case X86::VMOVUPSZ256rmk: + case X86::VMOVAPSZ256rmk: + case X86::VMOVUPSZrmk: + case X86::VMOVAPSZrmk: case X86::VBROADCASTSDZ256rmk: case X86::VBROADCASTSDZrmk: case X86::VBROADCASTSSZ128rmk: @@ -1691,59 +1711,142 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI, case X86::VPBROADCASTQZrmk: { unsigned Opc; switch (MIOpc) { - default: llvm_unreachable("Unreachable!"); - case X86::VMOVDQU8Z128rmk: Opc = X86::VPBLENDMBZ128rmk; break; - case X86::VMOVDQU8Z256rmk: Opc = X86::VPBLENDMBZ256rmk; break; - case X86::VMOVDQU8Zrmk: Opc = X86::VPBLENDMBZrmk; break; - case X86::VMOVDQU16Z128rmk: Opc = X86::VPBLENDMWZ128rmk; break; - case X86::VMOVDQU16Z256rmk: Opc = X86::VPBLENDMWZ256rmk; break; - case X86::VMOVDQU16Zrmk: Opc = X86::VPBLENDMWZrmk; break; - case X86::VMOVDQU32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break; - case X86::VMOVDQU32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break; - case X86::VMOVDQU32Zrmk: Opc = X86::VPBLENDMDZrmk; break; - case X86::VMOVDQU64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break; - case X86::VMOVDQU64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break; - case X86::VMOVDQU64Zrmk: Opc = X86::VPBLENDMQZrmk; break; - case X86::VMOVUPDZ128rmk: Opc = X86::VBLENDMPDZ128rmk; break; - case X86::VMOVUPDZ256rmk: Opc = X86::VBLENDMPDZ256rmk; break; - case X86::VMOVUPDZrmk: Opc = X86::VBLENDMPDZrmk; break; - case X86::VMOVUPSZ128rmk: Opc = X86::VBLENDMPSZ128rmk; break; - case X86::VMOVUPSZ256rmk: Opc = X86::VBLENDMPSZ256rmk; break; - case X86::VMOVUPSZrmk: Opc = X86::VBLENDMPSZrmk; break; - case X86::VMOVDQA32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break; - case X86::VMOVDQA32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break; - case X86::VMOVDQA32Zrmk: Opc = X86::VPBLENDMDZrmk; break; - case X86::VMOVDQA64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break; - case X86::VMOVDQA64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break; - case X86::VMOVDQA64Zrmk: Opc = X86::VPBLENDMQZrmk; break; - case X86::VMOVAPDZ128rmk: Opc = X86::VBLENDMPDZ128rmk; break; - case X86::VMOVAPDZ256rmk: Opc = X86::VBLENDMPDZ256rmk; break; - case X86::VMOVAPDZrmk: Opc = X86::VBLENDMPDZrmk; break; - case X86::VMOVAPSZ128rmk: Opc = X86::VBLENDMPSZ128rmk; break; - case X86::VMOVAPSZ256rmk: Opc = X86::VBLENDMPSZ256rmk; break; - case X86::VMOVAPSZrmk: Opc = X86::VBLENDMPSZrmk; break; - case X86::VBROADCASTSDZ256rmk: Opc = X86::VBLENDMPDZ256rmbk; break; - case X86::VBROADCASTSDZrmk: Opc = X86::VBLENDMPDZrmbk; break; - case X86::VBROADCASTSSZ128rmk: Opc = X86::VBLENDMPSZ128rmbk; break; - case X86::VBROADCASTSSZ256rmk: Opc = X86::VBLENDMPSZ256rmbk; break; - case X86::VBROADCASTSSZrmk: Opc = X86::VBLENDMPSZrmbk; break; - case X86::VPBROADCASTDZ128rmk: Opc = X86::VPBLENDMDZ128rmbk; break; - case X86::VPBROADCASTDZ256rmk: Opc = X86::VPBLENDMDZ256rmbk; break; - case X86::VPBROADCASTDZrmk: Opc = X86::VPBLENDMDZrmbk; break; - case X86::VPBROADCASTQZ128rmk: Opc = X86::VPBLENDMQZ128rmbk; break; - case X86::VPBROADCASTQZ256rmk: Opc = X86::VPBLENDMQZ256rmbk; break; - case X86::VPBROADCASTQZrmk: Opc = X86::VPBLENDMQZrmbk; break; + default: + llvm_unreachable("Unreachable!"); + case X86::VMOVDQU8Z128rmk: + Opc = X86::VPBLENDMBZ128rmk; + break; + case X86::VMOVDQU8Z256rmk: + Opc = X86::VPBLENDMBZ256rmk; + break; + case X86::VMOVDQU8Zrmk: + Opc = X86::VPBLENDMBZrmk; + break; + case X86::VMOVDQU16Z128rmk: + Opc = X86::VPBLENDMWZ128rmk; + break; + case X86::VMOVDQU16Z256rmk: + Opc = X86::VPBLENDMWZ256rmk; + break; + case X86::VMOVDQU16Zrmk: + Opc = X86::VPBLENDMWZrmk; + break; + case X86::VMOVDQU32Z128rmk: + Opc = X86::VPBLENDMDZ128rmk; + break; + case X86::VMOVDQU32Z256rmk: + Opc = X86::VPBLENDMDZ256rmk; + break; + case X86::VMOVDQU32Zrmk: + Opc = X86::VPBLENDMDZrmk; + break; + case X86::VMOVDQU64Z128rmk: + Opc = X86::VPBLENDMQZ128rmk; + break; + case X86::VMOVDQU64Z256rmk: + Opc = X86::VPBLENDMQZ256rmk; + break; + case X86::VMOVDQU64Zrmk: + Opc = X86::VPBLENDMQZrmk; + break; + case X86::VMOVUPDZ128rmk: + Opc = X86::VBLENDMPDZ128rmk; + break; + case X86::VMOVUPDZ256rmk: + Opc = X86::VBLENDMPDZ256rmk; + break; + case X86::VMOVUPDZrmk: + Opc = X86::VBLENDMPDZrmk; + break; + case X86::VMOVUPSZ128rmk: + Opc = X86::VBLENDMPSZ128rmk; + break; + case X86::VMOVUPSZ256rmk: + Opc = X86::VBLENDMPSZ256rmk; + break; + case X86::VMOVUPSZrmk: + Opc = X86::VBLENDMPSZrmk; + break; + case X86::VMOVDQA32Z128rmk: + Opc = X86::VPBLENDMDZ128rmk; + break; + case X86::VMOVDQA32Z256rmk: + Opc = X86::VPBLENDMDZ256rmk; + break; + case X86::VMOVDQA32Zrmk: + Opc = X86::VPBLENDMDZrmk; + break; + case X86::VMOVDQA64Z128rmk: + Opc = X86::VPBLENDMQZ128rmk; + break; + case X86::VMOVDQA64Z256rmk: + Opc = X86::VPBLENDMQZ256rmk; + break; + case X86::VMOVDQA64Zrmk: + Opc = X86::VPBLENDMQZrmk; + break; + case X86::VMOVAPDZ128rmk: + Opc = X86::VBLENDMPDZ128rmk; + break; + case X86::VMOVAPDZ256rmk: + Opc = X86::VBLENDMPDZ256rmk; + break; + case X86::VMOVAPDZrmk: + Opc = X86::VBLENDMPDZrmk; + break; + case X86::VMOVAPSZ128rmk: + Opc = X86::VBLENDMPSZ128rmk; + break; + case X86::VMOVAPSZ256rmk: + Opc = X86::VBLENDMPSZ256rmk; + break; + case X86::VMOVAPSZrmk: + Opc = X86::VBLENDMPSZrmk; + break; + case X86::VBROADCASTSDZ256rmk: + Opc = X86::VBLENDMPDZ256rmbk; + break; + case X86::VBROADCASTSDZrmk: + Opc = X86::VBLENDMPDZrmbk; + break; + case X86::VBROADCASTSSZ128rmk: + Opc = X86::VBLENDMPSZ128rmbk; + break; + case X86::VBROADCASTSSZ256rmk: + Opc = X86::VBLENDMPSZ256rmbk; + break; + case X86::VBROADCASTSSZrmk: + Opc = X86::VBLENDMPSZrmbk; + break; + case X86::VPBROADCASTDZ128rmk: + Opc = X86::VPBLENDMDZ128rmbk; + break; + case X86::VPBROADCASTDZ256rmk: + Opc = X86::VPBLENDMDZ256rmbk; + break; + case X86::VPBROADCASTDZrmk: + Opc = X86::VPBLENDMDZrmbk; + break; + case X86::VPBROADCASTQZ128rmk: + Opc = X86::VPBLENDMQZ128rmbk; + break; + case X86::VPBROADCASTQZ256rmk: + Opc = X86::VPBLENDMQZ256rmbk; + break; + case X86::VPBROADCASTQZrmk: + Opc = X86::VPBLENDMQZrmbk; + break; } NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc)) - .add(Dest) - .add(MI.getOperand(2)) - .add(Src) - .add(MI.getOperand(3)) - .add(MI.getOperand(4)) - .add(MI.getOperand(5)) - .add(MI.getOperand(6)) - .add(MI.getOperand(7)); + .add(Dest) + .add(MI.getOperand(2)) + .add(Src) + .add(MI.getOperand(3)) + .add(MI.getOperand(4)) + .add(MI.getOperand(5)) + .add(MI.getOperand(6)) + .add(MI.getOperand(7)); NumRegOperands = 4; break; } @@ -1754,66 +1857,140 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI, case X86::VMOVDQU16Z128rrk: case X86::VMOVDQU16Z256rrk: case X86::VMOVDQU16Zrrk: - case X86::VMOVDQU32Z128rrk: case X86::VMOVDQA32Z128rrk: - case X86::VMOVDQU32Z256rrk: case X86::VMOVDQA32Z256rrk: - case X86::VMOVDQU32Zrrk: case X86::VMOVDQA32Zrrk: - case X86::VMOVDQU64Z128rrk: case X86::VMOVDQA64Z128rrk: - case X86::VMOVDQU64Z256rrk: case X86::VMOVDQA64Z256rrk: - case X86::VMOVDQU64Zrrk: case X86::VMOVDQA64Zrrk: - case X86::VMOVUPDZ128rrk: case X86::VMOVAPDZ128rrk: - case X86::VMOVUPDZ256rrk: case X86::VMOVAPDZ256rrk: - case X86::VMOVUPDZrrk: case X86::VMOVAPDZrrk: - case X86::VMOVUPSZ128rrk: case X86::VMOVAPSZ128rrk: - case X86::VMOVUPSZ256rrk: case X86::VMOVAPSZ256rrk: - case X86::VMOVUPSZrrk: case X86::VMOVAPSZrrk: { + case X86::VMOVDQU32Z128rrk: + case X86::VMOVDQA32Z128rrk: + case X86::VMOVDQU32Z256rrk: + case X86::VMOVDQA32Z256rrk: + case X86::VMOVDQU32Zrrk: + case X86::VMOVDQA32Zrrk: + case X86::VMOVDQU64Z128rrk: + case X86::VMOVDQA64Z128rrk: + case X86::VMOVDQU64Z256rrk: + case X86::VMOVDQA64Z256rrk: + case X86::VMOVDQU64Zrrk: + case X86::VMOVDQA64Zrrk: + case X86::VMOVUPDZ128rrk: + case X86::VMOVAPDZ128rrk: + case X86::VMOVUPDZ256rrk: + case X86::VMOVAPDZ256rrk: + case X86::VMOVUPDZrrk: + case X86::VMOVAPDZrrk: + case X86::VMOVUPSZ128rrk: + case X86::VMOVAPSZ128rrk: + case X86::VMOVUPSZ256rrk: + case X86::VMOVAPSZ256rrk: + case X86::VMOVUPSZrrk: + case X86::VMOVAPSZrrk: { unsigned Opc; switch (MIOpc) { - default: llvm_unreachable("Unreachable!"); - case X86::VMOVDQU8Z128rrk: Opc = X86::VPBLENDMBZ128rrk; break; - case X86::VMOVDQU8Z256rrk: Opc = X86::VPBLENDMBZ256rrk; break; - case X86::VMOVDQU8Zrrk: Opc = X86::VPBLENDMBZrrk; break; - case X86::VMOVDQU16Z128rrk: Opc = X86::VPBLENDMWZ128rrk; break; - case X86::VMOVDQU16Z256rrk: Opc = X86::VPBLENDMWZ256rrk; break; - case X86::VMOVDQU16Zrrk: Opc = X86::VPBLENDMWZrrk; break; - case X86::VMOVDQU32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break; - case X86::VMOVDQU32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break; - case X86::VMOVDQU32Zrrk: Opc = X86::VPBLENDMDZrrk; break; - case X86::VMOVDQU64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break; - case X86::VMOVDQU64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break; - case X86::VMOVDQU64Zrrk: Opc = X86::VPBLENDMQZrrk; break; - case X86::VMOVUPDZ128rrk: Opc = X86::VBLENDMPDZ128rrk; break; - case X86::VMOVUPDZ256rrk: Opc = X86::VBLENDMPDZ256rrk; break; - case X86::VMOVUPDZrrk: Opc = X86::VBLENDMPDZrrk; break; - case X86::VMOVUPSZ128rrk: Opc = X86::VBLENDMPSZ128rrk; break; - case X86::VMOVUPSZ256rrk: Opc = X86::VBLENDMPSZ256rrk; break; - case X86::VMOVUPSZrrk: Opc = X86::VBLENDMPSZrrk; break; - case X86::VMOVDQA32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break; - case X86::VMOVDQA32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break; - case X86::VMOVDQA32Zrrk: Opc = X86::VPBLENDMDZrrk; break; - case X86::VMOVDQA64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break; - case X86::VMOVDQA64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break; - case X86::VMOVDQA64Zrrk: Opc = X86::VPBLENDMQZrrk; break; - case X86::VMOVAPDZ128rrk: Opc = X86::VBLENDMPDZ128rrk; break; - case X86::VMOVAPDZ256rrk: Opc = X86::VBLENDMPDZ256rrk; break; - case X86::VMOVAPDZrrk: Opc = X86::VBLENDMPDZrrk; break; - case X86::VMOVAPSZ128rrk: Opc = X86::VBLENDMPSZ128rrk; break; - case X86::VMOVAPSZ256rrk: Opc = X86::VBLENDMPSZ256rrk; break; - case X86::VMOVAPSZrrk: Opc = X86::VBLENDMPSZrrk; break; + default: + llvm_unreachable("Unreachable!"); + case X86::VMOVDQU8Z128rrk: + Opc = X86::VPBLENDMBZ128rrk; + break; + case X86::VMOVDQU8Z256rrk: + Opc = X86::VPBLENDMBZ256rrk; + break; + case X86::VMOVDQU8Zrrk: + Opc = X86::VPBLENDMBZrrk; + break; + case X86::VMOVDQU16Z128rrk: + Opc = X86::VPBLENDMWZ128rrk; + break; + case X86::VMOVDQU16Z256rrk: + Opc = X86::VPBLENDMWZ256rrk; + break; + case X86::VMOVDQU16Zrrk: + Opc = X86::VPBLENDMWZrrk; + break; + case X86::VMOVDQU32Z128rrk: + Opc = X86::VPBLENDMDZ128rrk; + break; + case X86::VMOVDQU32Z256rrk: + Opc = X86::VPBLENDMDZ256rrk; + break; + case X86::VMOVDQU32Zrrk: + Opc = X86::VPBLENDMDZrrk; + break; + case X86::VMOVDQU64Z128rrk: + Opc = X86::VPBLENDMQZ128rrk; + break; + case X86::VMOVDQU64Z256rrk: + Opc = X86::VPBLENDMQZ256rrk; + break; + case X86::VMOVDQU64Zrrk: + Opc = X86::VPBLENDMQZrrk; + break; + case X86::VMOVUPDZ128rrk: + Opc = X86::VBLENDMPDZ128rrk; + break; + case X86::VMOVUPDZ256rrk: + Opc = X86::VBLENDMPDZ256rrk; + break; + case X86::VMOVUPDZrrk: + Opc = X86::VBLENDMPDZrrk; + break; + case X86::VMOVUPSZ128rrk: + Opc = X86::VBLENDMPSZ128rrk; + break; + case X86::VMOVUPSZ256rrk: + Opc = X86::VBLENDMPSZ256rrk; + break; + case X86::VMOVUPSZrrk: + Opc = X86::VBLENDMPSZrrk; + break; + case X86::VMOVDQA32Z128rrk: + Opc = X86::VPBLENDMDZ128rrk; + break; + case X86::VMOVDQA32Z256rrk: + Opc = X86::VPBLENDMDZ256rrk; + break; + case X86::VMOVDQA32Zrrk: + Opc = X86::VPBLENDMDZrrk; + break; + case X86::VMOVDQA64Z128rrk: + Opc = X86::VPBLENDMQZ128rrk; + break; + case X86::VMOVDQA64Z256rrk: + Opc = X86::VPBLENDMQZ256rrk; + break; + case X86::VMOVDQA64Zrrk: + Opc = X86::VPBLENDMQZrrk; + break; + case X86::VMOVAPDZ128rrk: + Opc = X86::VBLENDMPDZ128rrk; + break; + case X86::VMOVAPDZ256rrk: + Opc = X86::VBLENDMPDZ256rrk; + break; + case X86::VMOVAPDZrrk: + Opc = X86::VBLENDMPDZrrk; + break; + case X86::VMOVAPSZ128rrk: + Opc = X86::VBLENDMPSZ128rrk; + break; + case X86::VMOVAPSZ256rrk: + Opc = X86::VBLENDMPSZ256rrk; + break; + case X86::VMOVAPSZrrk: + Opc = X86::VBLENDMPSZrrk; + break; } NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc)) - .add(Dest) - .add(MI.getOperand(2)) - .add(Src) - .add(MI.getOperand(3)); + .add(Dest) + .add(MI.getOperand(2)) + .add(Src) + .add(MI.getOperand(3)); NumRegOperands = 4; break; } } - if (!NewMI) return nullptr; + if (!NewMI) + return nullptr; - if (LV) { // Update live variables + if (LV) { // Update live variables for (unsigned I = 0; I < NumRegOperands; ++I) { MachineOperand &Op = MI.getOperand(I); if (Op.isReg() && (Op.isDead() || Op.isKill())) @@ -1879,8 +2056,8 @@ unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands( "Intrinsic instructions can't commute operand 1"); // Determine which case this commute is or if it can't be done. - unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1, - SrcOpIdx2); + unsigned Case = + getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1, SrcOpIdx2); assert(Case < 3 && "Unexpected case number!"); // Define the FMA forms mapping array that helps to map input FMA form @@ -1890,22 +2067,21 @@ unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands( const unsigned Form213Index = 1; const unsigned Form231Index = 2; static const unsigned FormMapping[][3] = { - // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2; - // FMA132 A, C, b; ==> FMA231 C, A, b; - // FMA213 B, A, c; ==> FMA213 A, B, c; - // FMA231 C, A, b; ==> FMA132 A, C, b; - { Form231Index, Form213Index, Form132Index }, - // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3; - // FMA132 A, c, B; ==> FMA132 B, c, A; - // FMA213 B, a, C; ==> FMA231 C, a, B; - // FMA231 C, a, B; ==> FMA213 B, a, C; - { Form132Index, Form231Index, Form213Index }, - // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3; - // FMA132 a, C, B; ==> FMA213 a, B, C; - // FMA213 b, A, C; ==> FMA132 b, C, A; - // FMA231 c, A, B; ==> FMA231 c, B, A; - { Form213Index, Form132Index, Form231Index } - }; + // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2; + // FMA132 A, C, b; ==> FMA231 C, A, b; + // FMA213 B, A, c; ==> FMA213 A, B, c; + // FMA231 C, A, b; ==> FMA132 A, C, b; + {Form231Index, Form213Index, Form132Index}, + // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3; + // FMA132 A, c, B; ==> FMA132 B, c, A; + // FMA213 B, a, C; ==> FMA231 C, a, B; + // FMA231 C, a, B; ==> FMA213 B, a, C; + {Form132Index, Form231Index, Form213Index}, + // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3; + // FMA132 a, C, B; ==> FMA213 a, B, C; + // FMA213 b, A, C; ==> FMA132 b, C, A; + // FMA231 c, A, B; ==> FMA231 c, B, A; + {Form213Index, Form132Index, Form231Index}}; unsigned FMAForms[3]; FMAForms[0] = FMA3Group.get132Opcode(); @@ -1923,63 +2099,86 @@ unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands( static void commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2) { // Determine which case this commute is or if it can't be done. - unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1, - SrcOpIdx2); + unsigned Case = + getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1, SrcOpIdx2); assert(Case < 3 && "Unexpected case value!"); // For each case we need to swap two pairs of bits in the final immediate. static const uint8_t SwapMasks[3][4] = { - { 0x04, 0x10, 0x08, 0x20 }, // Swap bits 2/4 and 3/5. - { 0x02, 0x10, 0x08, 0x40 }, // Swap bits 1/4 and 3/6. - { 0x02, 0x04, 0x20, 0x40 }, // Swap bits 1/2 and 5/6. + {0x04, 0x10, 0x08, 0x20}, // Swap bits 2/4 and 3/5. + {0x02, 0x10, 0x08, 0x40}, // Swap bits 1/4 and 3/6. + {0x02, 0x04, 0x20, 0x40}, // Swap bits 1/2 and 5/6. }; - uint8_t Imm = MI.getOperand(MI.getNumOperands()-1).getImm(); + uint8_t Imm = MI.getOperand(MI.getNumOperands() - 1).getImm(); // Clear out the bits we are swapping. uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] | SwapMasks[Case][2] | SwapMasks[Case][3]); // If the immediate had a bit of the pair set, then set the opposite bit. - if (Imm & SwapMasks[Case][0]) NewImm |= SwapMasks[Case][1]; - if (Imm & SwapMasks[Case][1]) NewImm |= SwapMasks[Case][0]; - if (Imm & SwapMasks[Case][2]) NewImm |= SwapMasks[Case][3]; - if (Imm & SwapMasks[Case][3]) NewImm |= SwapMasks[Case][2]; - MI.getOperand(MI.getNumOperands()-1).setImm(NewImm); + if (Imm & SwapMasks[Case][0]) + NewImm |= SwapMasks[Case][1]; + if (Imm & SwapMasks[Case][1]) + NewImm |= SwapMasks[Case][0]; + if (Imm & SwapMasks[Case][2]) + NewImm |= SwapMasks[Case][3]; + if (Imm & SwapMasks[Case][3]) + NewImm |= SwapMasks[Case][2]; + MI.getOperand(MI.getNumOperands() - 1).setImm(NewImm); } // Returns true if this is a VPERMI2 or VPERMT2 instruction that can be // commuted. static bool isCommutableVPERMV3Instruction(unsigned Opcode) { -#define VPERM_CASES(Suffix) \ - case X86::VPERMI2##Suffix##128rr: case X86::VPERMT2##Suffix##128rr: \ - case X86::VPERMI2##Suffix##256rr: case X86::VPERMT2##Suffix##256rr: \ - case X86::VPERMI2##Suffix##rr: case X86::VPERMT2##Suffix##rr: \ - case X86::VPERMI2##Suffix##128rm: case X86::VPERMT2##Suffix##128rm: \ - case X86::VPERMI2##Suffix##256rm: case X86::VPERMT2##Suffix##256rm: \ - case X86::VPERMI2##Suffix##rm: case X86::VPERMT2##Suffix##rm: \ - case X86::VPERMI2##Suffix##128rrkz: case X86::VPERMT2##Suffix##128rrkz: \ - case X86::VPERMI2##Suffix##256rrkz: case X86::VPERMT2##Suffix##256rrkz: \ - case X86::VPERMI2##Suffix##rrkz: case X86::VPERMT2##Suffix##rrkz: \ - case X86::VPERMI2##Suffix##128rmkz: case X86::VPERMT2##Suffix##128rmkz: \ - case X86::VPERMI2##Suffix##256rmkz: case X86::VPERMT2##Suffix##256rmkz: \ - case X86::VPERMI2##Suffix##rmkz: case X86::VPERMT2##Suffix##rmkz: - -#define VPERM_CASES_BROADCAST(Suffix) \ - VPERM_CASES(Suffix) \ - case X86::VPERMI2##Suffix##128rmb: case X86::VPERMT2##Suffix##128rmb: \ - case X86::VPERMI2##Suffix##256rmb: case X86::VPERMT2##Suffix##256rmb: \ - case X86::VPERMI2##Suffix##rmb: case X86::VPERMT2##Suffix##rmb: \ - case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \ - case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \ - case X86::VPERMI2##Suffix##rmbkz: case X86::VPERMT2##Suffix##rmbkz: +#define VPERM_CASES(Suffix) \ + case X86::VPERMI2##Suffix##128rr: \ + case X86::VPERMT2##Suffix##128rr: \ + case X86::VPERMI2##Suffix##256rr: \ + case X86::VPERMT2##Suffix##256rr: \ + case X86::VPERMI2##Suffix##rr: \ + case X86::VPERMT2##Suffix##rr: \ + case X86::VPERMI2##Suffix##128rm: \ + case X86::VPERMT2##Suffix##128rm: \ + case X86::VPERMI2##Suffix##256rm: \ + case X86::VPERMT2##Suffix##256rm: \ + case X86::VPERMI2##Suffix##rm: \ + case X86::VPERMT2##Suffix##rm: \ + case X86::VPERMI2##Suffix##128rrkz: \ + case X86::VPERMT2##Suffix##128rrkz: \ + case X86::VPERMI2##Suffix##256rrkz: \ + case X86::VPERMT2##Suffix##256rrkz: \ + case X86::VPERMI2##Suffix##rrkz: \ + case X86::VPERMT2##Suffix##rrkz: \ + case X86::VPERMI2##Suffix##128rmkz: \ + case X86::VPERMT2##Suffix##128rmkz: \ + case X86::VPERMI2##Suffix##256rmkz: \ + case X86::VPERMT2##Suffix##256rmkz: \ + case X86::VPERMI2##Suffix##rmkz: \ + case X86::VPERMT2##Suffix##rmkz: + +#define VPERM_CASES_BROADCAST(Suffix) \ + VPERM_CASES(Suffix) \ + case X86::VPERMI2##Suffix##128rmb: \ + case X86::VPERMT2##Suffix##128rmb: \ + case X86::VPERMI2##Suffix##256rmb: \ + case X86::VPERMT2##Suffix##256rmb: \ + case X86::VPERMI2##Suffix##rmb: \ + case X86::VPERMT2##Suffix##rmb: \ + case X86::VPERMI2##Suffix##128rmbkz: \ + case X86::VPERMT2##Suffix##128rmbkz: \ + case X86::VPERMI2##Suffix##256rmbkz: \ + case X86::VPERMT2##Suffix##256rmbkz: \ + case X86::VPERMI2##Suffix##rmbkz: \ + case X86::VPERMT2##Suffix##rmbkz: switch (Opcode) { - default: return false; - VPERM_CASES(B) - VPERM_CASES_BROADCAST(D) - VPERM_CASES_BROADCAST(PD) - VPERM_CASES_BROADCAST(PS) - VPERM_CASES_BROADCAST(Q) - VPERM_CASES(W) + default: + return false; + VPERM_CASES(B) + VPERM_CASES_BROADCAST(D) + VPERM_CASES_BROADCAST(PD) + VPERM_CASES_BROADCAST(PS) + VPERM_CASES_BROADCAST(Q) + VPERM_CASES(W) return true; } #undef VPERM_CASES_BROADCAST @@ -1989,42 +2188,60 @@ static bool isCommutableVPERMV3Instruction(unsigned Opcode) { // Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching // from the I opcode to the T opcode and vice versa. static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) { -#define VPERM_CASES(Orig, New) \ - case X86::Orig##128rr: return X86::New##128rr; \ - case X86::Orig##128rrkz: return X86::New##128rrkz; \ - case X86::Orig##128rm: return X86::New##128rm; \ - case X86::Orig##128rmkz: return X86::New##128rmkz; \ - case X86::Orig##256rr: return X86::New##256rr; \ - case X86::Orig##256rrkz: return X86::New##256rrkz; \ - case X86::Orig##256rm: return X86::New##256rm; \ - case X86::Orig##256rmkz: return X86::New##256rmkz; \ - case X86::Orig##rr: return X86::New##rr; \ - case X86::Orig##rrkz: return X86::New##rrkz; \ - case X86::Orig##rm: return X86::New##rm; \ - case X86::Orig##rmkz: return X86::New##rmkz; - -#define VPERM_CASES_BROADCAST(Orig, New) \ - VPERM_CASES(Orig, New) \ - case X86::Orig##128rmb: return X86::New##128rmb; \ - case X86::Orig##128rmbkz: return X86::New##128rmbkz; \ - case X86::Orig##256rmb: return X86::New##256rmb; \ - case X86::Orig##256rmbkz: return X86::New##256rmbkz; \ - case X86::Orig##rmb: return X86::New##rmb; \ - case X86::Orig##rmbkz: return X86::New##rmbkz; +#define VPERM_CASES(Orig, New) \ + case X86::Orig##128rr: \ + return X86::New##128rr; \ + case X86::Orig##128rrkz: \ + return X86::New##128rrkz; \ + case X86::Orig##128rm: \ + return X86::New##128rm; \ + case X86::Orig##128rmkz: \ + return X86::New##128rmkz; \ + case X86::Orig##256rr: \ + return X86::New##256rr; \ + case X86::Orig##256rrkz: \ + return X86::New##256rrkz; \ + case X86::Orig##256rm: \ + return X86::New##256rm; \ + case X86::Orig##256rmkz: \ + return X86::New##256rmkz; \ + case X86::Orig##rr: \ + return X86::New##rr; \ + case X86::Orig##rrkz: \ + return X86::New##rrkz; \ + case X86::Orig##rm: \ + return X86::New##rm; \ + case X86::Orig##rmkz: \ + return X86::New##rmkz; + +#define VPERM_CASES_BROADCAST(Orig, New) \ + VPERM_CASES(Orig, New) \ + case X86::Orig##128rmb: \ + return X86::New##128rmb; \ + case X86::Orig##128rmbkz: \ + return X86::New##128rmbkz; \ + case X86::Orig##256rmb: \ + return X86::New##256rmb; \ + case X86::Orig##256rmbkz: \ + return X86::New##256rmbkz; \ + case X86::Orig##rmb: \ + return X86::New##rmb; \ + case X86::Orig##rmbkz: \ + return X86::New##rmbkz; switch (Opcode) { - VPERM_CASES(VPERMI2B, VPERMT2B) - VPERM_CASES_BROADCAST(VPERMI2D, VPERMT2D) - VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD) - VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS) - VPERM_CASES_BROADCAST(VPERMI2Q, VPERMT2Q) - VPERM_CASES(VPERMI2W, VPERMT2W) - VPERM_CASES(VPERMT2B, VPERMI2B) - VPERM_CASES_BROADCAST(VPERMT2D, VPERMI2D) - VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD) - VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS) - VPERM_CASES_BROADCAST(VPERMT2Q, VPERMI2Q) - VPERM_CASES(VPERMT2W, VPERMI2W) + VPERM_CASES(VPERMI2B, VPERMT2B) + VPERM_CASES_BROADCAST(VPERMI2D, VPERMT2D) + VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD) + VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS) + VPERM_CASES_BROADCAST(VPERMI2Q, VPERMT2Q) + VPERM_CASES(VPERMI2W, VPERMT2W) + VPERM_CASES(VPERMT2B, VPERMI2B) + VPERM_CASES_BROADCAST(VPERMT2D, VPERMI2D) + VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD) + VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS) + VPERM_CASES_BROADCAST(VPERMT2Q, VPERMI2Q) + VPERM_CASES(VPERMT2W, VPERMI2W) } llvm_unreachable("Unreachable!"); @@ -2047,17 +2264,37 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I) case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I) case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I) - case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I) + case X86::SHLD64rri8: { // A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, + // (64-I) unsigned Opc; unsigned Size; switch (MI.getOpcode()) { - default: llvm_unreachable("Unreachable!"); - case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break; - case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break; - case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break; - case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break; - case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break; - case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break; + default: + llvm_unreachable("Unreachable!"); + case X86::SHRD16rri8: + Size = 16; + Opc = X86::SHLD16rri8; + break; + case X86::SHLD16rri8: + Size = 16; + Opc = X86::SHRD16rri8; + break; + case X86::SHRD32rri8: + Size = 32; + Opc = X86::SHLD32rri8; + break; + case X86::SHLD32rri8: + Size = 32; + Opc = X86::SHRD32rri8; + break; + case X86::SHRD64rri8: + Size = 64; + Opc = X86::SHLD64rri8; + break; + case X86::SHLD64rri8: + Size = 64; + Opc = X86::SHRD64rri8; + break; } unsigned Amt = MI.getOperand(3).getImm(); auto &WorkingMI = cloneIfNew(MI); @@ -2085,19 +2322,32 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, if (MI.getParent()->getParent()->getFunction().hasOptSize()) { unsigned Mask, Opc; switch (MI.getOpcode()) { - default: llvm_unreachable("Unreachable!"); - case X86::BLENDPDrri: Opc = X86::MOVSDrr; Mask = 0x03; break; - case X86::BLENDPSrri: Opc = X86::MOVSSrr; Mask = 0x0F; break; - case X86::VBLENDPDrri: Opc = X86::VMOVSDrr; Mask = 0x03; break; - case X86::VBLENDPSrri: Opc = X86::VMOVSSrr; Mask = 0x0F; break; + default: + llvm_unreachable("Unreachable!"); + case X86::BLENDPDrri: + Opc = X86::MOVSDrr; + Mask = 0x03; + break; + case X86::BLENDPSrri: + Opc = X86::MOVSSrr; + Mask = 0x0F; + break; + case X86::VBLENDPDrri: + Opc = X86::VMOVSDrr; + Mask = 0x03; + break; + case X86::VBLENDPSrri: + Opc = X86::VMOVSSrr; + Mask = 0x0F; + break; } if ((MI.getOperand(3).getImm() ^ Mask) == 1) { auto &WorkingMI = cloneIfNew(MI); WorkingMI.setDesc(get(Opc)); WorkingMI.removeOperand(3); return TargetInstrInfo::commuteInstructionImpl(WorkingMI, - /*NewMI=*/false, - OpIdx1, OpIdx2); + /*NewMI=*/false, OpIdx1, + OpIdx2); } } [[fallthrough]]; @@ -2107,21 +2357,44 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, case X86::VPBLENDDrri: case X86::VPBLENDWrri: case X86::VPBLENDDYrri: - case X86::VPBLENDWYrri:{ + case X86::VPBLENDWYrri: { int8_t Mask; switch (MI.getOpcode()) { - default: llvm_unreachable("Unreachable!"); - case X86::BLENDPDrri: Mask = (int8_t)0x03; break; - case X86::BLENDPSrri: Mask = (int8_t)0x0F; break; - case X86::PBLENDWrri: Mask = (int8_t)0xFF; break; - case X86::VBLENDPDrri: Mask = (int8_t)0x03; break; - case X86::VBLENDPSrri: Mask = (int8_t)0x0F; break; - case X86::VBLENDPDYrri: Mask = (int8_t)0x0F; break; - case X86::VBLENDPSYrri: Mask = (int8_t)0xFF; break; - case X86::VPBLENDDrri: Mask = (int8_t)0x0F; break; - case X86::VPBLENDWrri: Mask = (int8_t)0xFF; break; - case X86::VPBLENDDYrri: Mask = (int8_t)0xFF; break; - case X86::VPBLENDWYrri: Mask = (int8_t)0xFF; break; + default: + llvm_unreachable("Unreachable!"); + case X86::BLENDPDrri: + Mask = (int8_t)0x03; + break; + case X86::BLENDPSrri: + Mask = (int8_t)0x0F; + break; + case X86::PBLENDWrri: + Mask = (int8_t)0xFF; + break; + case X86::VBLENDPDrri: + Mask = (int8_t)0x03; + break; + case X86::VBLENDPSrri: + Mask = (int8_t)0x0F; + break; + case X86::VBLENDPDYrri: + Mask = (int8_t)0x0F; + break; + case X86::VBLENDPSYrri: + Mask = (int8_t)0xFF; + break; + case X86::VPBLENDDrri: + Mask = (int8_t)0x0F; + break; + case X86::VPBLENDWrri: + Mask = (int8_t)0xFF; + break; + case X86::VPBLENDDYrri: + Mask = (int8_t)0xFF; + break; + case X86::VPBLENDWYrri: + Mask = (int8_t)0xFF; + break; } // Only the least significant bits of Imm are used. // Using int8_t to ensure it will be sign extended to the int64_t that @@ -2157,16 +2430,29 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, case X86::MOVSDrr: case X86::MOVSSrr: case X86::VMOVSDrr: - case X86::VMOVSSrr:{ + case X86::VMOVSSrr: { // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD. if (Subtarget.hasSSE41()) { unsigned Mask, Opc; switch (MI.getOpcode()) { - default: llvm_unreachable("Unreachable!"); - case X86::MOVSDrr: Opc = X86::BLENDPDrri; Mask = 0x02; break; - case X86::MOVSSrr: Opc = X86::BLENDPSrri; Mask = 0x0E; break; - case X86::VMOVSDrr: Opc = X86::VBLENDPDrri; Mask = 0x02; break; - case X86::VMOVSSrr: Opc = X86::VBLENDPSrri; Mask = 0x0E; break; + default: + llvm_unreachable("Unreachable!"); + case X86::MOVSDrr: + Opc = X86::BLENDPDrri; + Mask = 0x02; + break; + case X86::MOVSSrr: + Opc = X86::BLENDPSrri; + Mask = 0x0E; + break; + case X86::VMOVSDrr: + Opc = X86::VBLENDPDrri; + Mask = 0x02; + break; + case X86::VMOVSSrr: + Opc = X86::VBLENDPSrri; + Mask = 0x0E; + break; } auto &WorkingMI = cloneIfNew(MI); @@ -2211,30 +2497,54 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, OpIdx1, OpIdx2); } - case X86::VPCMPBZ128rri: case X86::VPCMPUBZ128rri: - case X86::VPCMPBZ256rri: case X86::VPCMPUBZ256rri: - case X86::VPCMPBZrri: case X86::VPCMPUBZrri: - case X86::VPCMPDZ128rri: case X86::VPCMPUDZ128rri: - case X86::VPCMPDZ256rri: case X86::VPCMPUDZ256rri: - case X86::VPCMPDZrri: case X86::VPCMPUDZrri: - case X86::VPCMPQZ128rri: case X86::VPCMPUQZ128rri: - case X86::VPCMPQZ256rri: case X86::VPCMPUQZ256rri: - case X86::VPCMPQZrri: case X86::VPCMPUQZrri: - case X86::VPCMPWZ128rri: case X86::VPCMPUWZ128rri: - case X86::VPCMPWZ256rri: case X86::VPCMPUWZ256rri: - case X86::VPCMPWZrri: case X86::VPCMPUWZrri: - case X86::VPCMPBZ128rrik: case X86::VPCMPUBZ128rrik: - case X86::VPCMPBZ256rrik: case X86::VPCMPUBZ256rrik: - case X86::VPCMPBZrrik: case X86::VPCMPUBZrrik: - case X86::VPCMPDZ128rrik: case X86::VPCMPUDZ128rrik: - case X86::VPCMPDZ256rrik: case X86::VPCMPUDZ256rrik: - case X86::VPCMPDZrrik: case X86::VPCMPUDZrrik: - case X86::VPCMPQZ128rrik: case X86::VPCMPUQZ128rrik: - case X86::VPCMPQZ256rrik: case X86::VPCMPUQZ256rrik: - case X86::VPCMPQZrrik: case X86::VPCMPUQZrrik: - case X86::VPCMPWZ128rrik: case X86::VPCMPUWZ128rrik: - case X86::VPCMPWZ256rrik: case X86::VPCMPUWZ256rrik: - case X86::VPCMPWZrrik: case X86::VPCMPUWZrrik: { + case X86::VPCMPBZ128rri: + case X86::VPCMPUBZ128rri: + case X86::VPCMPBZ256rri: + case X86::VPCMPUBZ256rri: + case X86::VPCMPBZrri: + case X86::VPCMPUBZrri: + case X86::VPCMPDZ128rri: + case X86::VPCMPUDZ128rri: + case X86::VPCMPDZ256rri: + case X86::VPCMPUDZ256rri: + case X86::VPCMPDZrri: + case X86::VPCMPUDZrri: + case X86::VPCMPQZ128rri: + case X86::VPCMPUQZ128rri: + case X86::VPCMPQZ256rri: + case X86::VPCMPUQZ256rri: + case X86::VPCMPQZrri: + case X86::VPCMPUQZrri: + case X86::VPCMPWZ128rri: + case X86::VPCMPUWZ128rri: + case X86::VPCMPWZ256rri: + case X86::VPCMPUWZ256rri: + case X86::VPCMPWZrri: + case X86::VPCMPUWZrri: + case X86::VPCMPBZ128rrik: + case X86::VPCMPUBZ128rrik: + case X86::VPCMPBZ256rrik: + case X86::VPCMPUBZ256rrik: + case X86::VPCMPBZrrik: + case X86::VPCMPUBZrrik: + case X86::VPCMPDZ128rrik: + case X86::VPCMPUDZ128rrik: + case X86::VPCMPDZ256rrik: + case X86::VPCMPUDZ256rrik: + case X86::VPCMPDZrrik: + case X86::VPCMPUDZrrik: + case X86::VPCMPQZ128rrik: + case X86::VPCMPUQZ128rrik: + case X86::VPCMPQZ256rrik: + case X86::VPCMPUQZ256rrik: + case X86::VPCMPQZrrik: + case X86::VPCMPUQZrrik: + case X86::VPCMPWZ128rrik: + case X86::VPCMPUWZ128rrik: + case X86::VPCMPWZ256rrik: + case X86::VPCMPUWZ256rrik: + case X86::VPCMPWZrrik: + case X86::VPCMPUWZrrik: { // Flip comparison mode immediate (if necessary). unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm() & 0x7; Imm = X86::getSwappedVPCMPImm(Imm); @@ -2243,10 +2553,14 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, OpIdx1, OpIdx2); } - case X86::VPCOMBri: case X86::VPCOMUBri: - case X86::VPCOMDri: case X86::VPCOMUDri: - case X86::VPCOMQri: case X86::VPCOMUQri: - case X86::VPCOMWri: case X86::VPCOMUWri: { + case X86::VPCOMBri: + case X86::VPCOMUBri: + case X86::VPCOMDri: + case X86::VPCOMUDri: + case X86::VPCOMQri: + case X86::VPCOMUQri: + case X86::VPCOMWri: + case X86::VPCOMUWri: { // Flip comparison mode immediate (if necessary). unsigned Imm = MI.getOperand(3).getImm() & 0x7; Imm = X86::getSwappedVPCOMImm(Imm); @@ -2274,7 +2588,7 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, case X86::VCMPPDZ256rrik: case X86::VCMPPSZ256rrik: { unsigned Imm = - MI.getOperand(MI.getNumExplicitOperands() - 1).getImm() & 0x1f; + MI.getOperand(MI.getNumExplicitOperands() - 1).getImm() & 0x1f; Imm = X86::getSwappedVCMPImm(Imm); auto &WorkingMI = cloneIfNew(MI); WorkingMI.getOperand(MI.getNumExplicitOperands() - 1).setImm(Imm); @@ -2302,20 +2616,35 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned Opc = MI.getOpcode(); switch (Opc) { - default: llvm_unreachable("Unreachable!"); - case X86::MOVHLPSrr: Opc = X86::UNPCKHPDrr; break; - case X86::UNPCKHPDrr: Opc = X86::MOVHLPSrr; break; - case X86::VMOVHLPSrr: Opc = X86::VUNPCKHPDrr; break; - case X86::VUNPCKHPDrr: Opc = X86::VMOVHLPSrr; break; - case X86::VMOVHLPSZrr: Opc = X86::VUNPCKHPDZ128rr; break; - case X86::VUNPCKHPDZ128rr: Opc = X86::VMOVHLPSZrr; break; + default: + llvm_unreachable("Unreachable!"); + case X86::MOVHLPSrr: + Opc = X86::UNPCKHPDrr; + break; + case X86::UNPCKHPDrr: + Opc = X86::MOVHLPSrr; + break; + case X86::VMOVHLPSrr: + Opc = X86::VUNPCKHPDrr; + break; + case X86::VUNPCKHPDrr: + Opc = X86::VMOVHLPSrr; + break; + case X86::VMOVHLPSZrr: + Opc = X86::VUNPCKHPDZ128rr; + break; + case X86::VUNPCKHPDZ128rr: + Opc = X86::VMOVHLPSZrr; + break; } auto &WorkingMI = cloneIfNew(MI); WorkingMI.setDesc(get(Opc)); return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, OpIdx1, OpIdx2); } - case X86::CMOV16rr: case X86::CMOV32rr: case X86::CMOV64rr: { + case X86::CMOV16rr: + case X86::CMOV32rr: + case X86::CMOV64rr: { auto &WorkingMI = cloneIfNew(MI); unsigned OpNo = MI.getDesc().getNumOperands() - 1; X86::CondCode CC = static_cast(MI.getOperand(OpNo).getImm()); @@ -2323,24 +2652,36 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, OpIdx1, OpIdx2); } - case X86::VPTERNLOGDZrri: case X86::VPTERNLOGDZrmi: - case X86::VPTERNLOGDZ128rri: case X86::VPTERNLOGDZ128rmi: - case X86::VPTERNLOGDZ256rri: case X86::VPTERNLOGDZ256rmi: - case X86::VPTERNLOGQZrri: case X86::VPTERNLOGQZrmi: - case X86::VPTERNLOGQZ128rri: case X86::VPTERNLOGQZ128rmi: - case X86::VPTERNLOGQZ256rri: case X86::VPTERNLOGQZ256rmi: + case X86::VPTERNLOGDZrri: + case X86::VPTERNLOGDZrmi: + case X86::VPTERNLOGDZ128rri: + case X86::VPTERNLOGDZ128rmi: + case X86::VPTERNLOGDZ256rri: + case X86::VPTERNLOGDZ256rmi: + case X86::VPTERNLOGQZrri: + case X86::VPTERNLOGQZrmi: + case X86::VPTERNLOGQZ128rri: + case X86::VPTERNLOGQZ128rmi: + case X86::VPTERNLOGQZ256rri: + case X86::VPTERNLOGQZ256rmi: case X86::VPTERNLOGDZrrik: case X86::VPTERNLOGDZ128rrik: case X86::VPTERNLOGDZ256rrik: case X86::VPTERNLOGQZrrik: case X86::VPTERNLOGQZ128rrik: case X86::VPTERNLOGQZ256rrik: - case X86::VPTERNLOGDZrrikz: case X86::VPTERNLOGDZrmikz: - case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz: - case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz: - case X86::VPTERNLOGQZrrikz: case X86::VPTERNLOGQZrmikz: - case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz: - case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz: + case X86::VPTERNLOGDZrrikz: + case X86::VPTERNLOGDZrmikz: + case X86::VPTERNLOGDZ128rrikz: + case X86::VPTERNLOGDZ128rmikz: + case X86::VPTERNLOGDZ256rrikz: + case X86::VPTERNLOGDZ256rmikz: + case X86::VPTERNLOGQZrrikz: + case X86::VPTERNLOGQZrmikz: + case X86::VPTERNLOGQZ128rrikz: + case X86::VPTERNLOGQZ128rmikz: + case X86::VPTERNLOGQZ256rrikz: + case X86::VPTERNLOGQZ256rmikz: case X86::VPTERNLOGDZ128rmbi: case X86::VPTERNLOGDZ256rmbi: case X86::VPTERNLOGDZrmbi: @@ -2367,11 +2708,11 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, OpIdx1, OpIdx2); } - const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(), - MI.getDesc().TSFlags); + const X86InstrFMA3Group *FMA3Group = + getFMA3Group(MI.getOpcode(), MI.getDesc().TSFlags); if (FMA3Group) { unsigned Opc = - getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group); + getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group); auto &WorkingMI = cloneIfNew(MI); WorkingMI.setDesc(get(Opc)); return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, @@ -2383,11 +2724,10 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, } } -bool -X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI, - unsigned &SrcOpIdx1, - unsigned &SrcOpIdx2, - bool IsIntrinsic) const { +bool X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI, + unsigned &SrcOpIdx1, + unsigned &SrcOpIdx2, + bool IsIntrinsic) const { uint64_t TSFlags = MI.getDesc().TSFlags; unsigned FirstCommutableVecOp = 1; @@ -2479,8 +2819,8 @@ X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI, // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2 // to return those values. - if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, - CommutableOpIdx1, CommutableOpIdx2)) + if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, CommutableOpIdx1, + CommutableOpIdx2)) return false; } @@ -2568,24 +2908,36 @@ bool X86InstrInfo::findCommutedOpIndices(const MachineInstr &MI, if (Subtarget.hasSSE2()) return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2); return false; - case X86::VPTERNLOGDZrri: case X86::VPTERNLOGDZrmi: - case X86::VPTERNLOGDZ128rri: case X86::VPTERNLOGDZ128rmi: - case X86::VPTERNLOGDZ256rri: case X86::VPTERNLOGDZ256rmi: - case X86::VPTERNLOGQZrri: case X86::VPTERNLOGQZrmi: - case X86::VPTERNLOGQZ128rri: case X86::VPTERNLOGQZ128rmi: - case X86::VPTERNLOGQZ256rri: case X86::VPTERNLOGQZ256rmi: + case X86::VPTERNLOGDZrri: + case X86::VPTERNLOGDZrmi: + case X86::VPTERNLOGDZ128rri: + case X86::VPTERNLOGDZ128rmi: + case X86::VPTERNLOGDZ256rri: + case X86::VPTERNLOGDZ256rmi: + case X86::VPTERNLOGQZrri: + case X86::VPTERNLOGQZrmi: + case X86::VPTERNLOGQZ128rri: + case X86::VPTERNLOGQZ128rmi: + case X86::VPTERNLOGQZ256rri: + case X86::VPTERNLOGQZ256rmi: case X86::VPTERNLOGDZrrik: case X86::VPTERNLOGDZ128rrik: case X86::VPTERNLOGDZ256rrik: case X86::VPTERNLOGQZrrik: case X86::VPTERNLOGQZ128rrik: case X86::VPTERNLOGQZ256rrik: - case X86::VPTERNLOGDZrrikz: case X86::VPTERNLOGDZrmikz: - case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz: - case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz: - case X86::VPTERNLOGQZrrikz: case X86::VPTERNLOGQZrmikz: - case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz: - case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz: + case X86::VPTERNLOGDZrrikz: + case X86::VPTERNLOGDZrmikz: + case X86::VPTERNLOGDZ128rrikz: + case X86::VPTERNLOGDZ128rmikz: + case X86::VPTERNLOGDZ256rrikz: + case X86::VPTERNLOGDZ256rmikz: + case X86::VPTERNLOGQZrrikz: + case X86::VPTERNLOGQZrmikz: + case X86::VPTERNLOGQZ128rrikz: + case X86::VPTERNLOGQZ128rmikz: + case X86::VPTERNLOGQZ256rrikz: + case X86::VPTERNLOGQZ256rmikz: case X86::VPTERNLOGDZ128rmbi: case X86::VPTERNLOGDZ256rmbi: case X86::VPTERNLOGDZrmbi: @@ -2674,19 +3026,18 @@ bool X86InstrInfo::findCommutedOpIndices(const MachineInstr &MI, ++CommutableOpIdx1; ++CommutableOpIdx2; } - if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, - CommutableOpIdx1, CommutableOpIdx2)) + if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, CommutableOpIdx1, + CommutableOpIdx2)) return false; - if (!MI.getOperand(SrcOpIdx1).isReg() || - !MI.getOperand(SrcOpIdx2).isReg()) + if (!MI.getOperand(SrcOpIdx1).isReg() || !MI.getOperand(SrcOpIdx2).isReg()) // No idea. return false; return true; } default: - const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(), - MI.getDesc().TSFlags); + const X86InstrFMA3Group *FMA3Group = + getFMA3Group(MI.getOpcode(), MI.getDesc().TSFlags); if (FMA3Group) return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2, FMA3Group->isIntrinsic()); @@ -2714,8 +3065,8 @@ bool X86InstrInfo::findCommutedOpIndices(const MachineInstr &MI, } } - if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, - CommutableOpIdx1, CommutableOpIdx2)) + if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, CommutableOpIdx1, + CommutableOpIdx2)) return false; if (!MI.getOperand(SrcOpIdx1).isReg() || @@ -2819,25 +3170,44 @@ X86::CondCode X86::getCondFromCMov(const MachineInstr &MI) { /// e.g. turning COND_E to COND_NE. X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { switch (CC) { - default: llvm_unreachable("Illegal condition code!"); - case X86::COND_E: return X86::COND_NE; - case X86::COND_NE: return X86::COND_E; - case X86::COND_L: return X86::COND_GE; - case X86::COND_LE: return X86::COND_G; - case X86::COND_G: return X86::COND_LE; - case X86::COND_GE: return X86::COND_L; - case X86::COND_B: return X86::COND_AE; - case X86::COND_BE: return X86::COND_A; - case X86::COND_A: return X86::COND_BE; - case X86::COND_AE: return X86::COND_B; - case X86::COND_S: return X86::COND_NS; - case X86::COND_NS: return X86::COND_S; - case X86::COND_P: return X86::COND_NP; - case X86::COND_NP: return X86::COND_P; - case X86::COND_O: return X86::COND_NO; - case X86::COND_NO: return X86::COND_O; - case X86::COND_NE_OR_P: return X86::COND_E_AND_NP; - case X86::COND_E_AND_NP: return X86::COND_NE_OR_P; + default: + llvm_unreachable("Illegal condition code!"); + case X86::COND_E: + return X86::COND_NE; + case X86::COND_NE: + return X86::COND_E; + case X86::COND_L: + return X86::COND_GE; + case X86::COND_LE: + return X86::COND_G; + case X86::COND_G: + return X86::COND_LE; + case X86::COND_GE: + return X86::COND_L; + case X86::COND_B: + return X86::COND_AE; + case X86::COND_BE: + return X86::COND_A; + case X86::COND_A: + return X86::COND_BE; + case X86::COND_AE: + return X86::COND_B; + case X86::COND_S: + return X86::COND_NS; + case X86::COND_NS: + return X86::COND_S; + case X86::COND_P: + return X86::COND_NP; + case X86::COND_NP: + return X86::COND_P; + case X86::COND_O: + return X86::COND_NO; + case X86::COND_NO: + return X86::COND_O; + case X86::COND_NE_OR_P: + return X86::COND_E_AND_NP; + case X86::COND_E_AND_NP: + return X86::COND_NE_OR_P; } } @@ -2845,17 +3215,28 @@ X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { /// modify the instructions such that flags are set by MI(b,a). static X86::CondCode getSwappedCondition(X86::CondCode CC) { switch (CC) { - default: return X86::COND_INVALID; - case X86::COND_E: return X86::COND_E; - case X86::COND_NE: return X86::COND_NE; - case X86::COND_L: return X86::COND_G; - case X86::COND_LE: return X86::COND_GE; - case X86::COND_G: return X86::COND_L; - case X86::COND_GE: return X86::COND_LE; - case X86::COND_B: return X86::COND_A; - case X86::COND_BE: return X86::COND_AE; - case X86::COND_A: return X86::COND_B; - case X86::COND_AE: return X86::COND_BE; + default: + return X86::COND_INVALID; + case X86::COND_E: + return X86::COND_E; + case X86::COND_NE: + return X86::COND_NE; + case X86::COND_L: + return X86::COND_G; + case X86::COND_LE: + return X86::COND_GE; + case X86::COND_G: + return X86::COND_L; + case X86::COND_GE: + return X86::COND_LE; + case X86::COND_B: + return X86::COND_A; + case X86::COND_BE: + return X86::COND_AE; + case X86::COND_A: + return X86::COND_B; + case X86::COND_AE: + return X86::COND_BE; } } @@ -2864,34 +3245,82 @@ X86::getX86ConditionCode(CmpInst::Predicate Predicate) { X86::CondCode CC = X86::COND_INVALID; bool NeedSwap = false; switch (Predicate) { - default: break; + default: + break; // Floating-point Predicates - case CmpInst::FCMP_UEQ: CC = X86::COND_E; break; - case CmpInst::FCMP_OLT: NeedSwap = true; [[fallthrough]]; - case CmpInst::FCMP_OGT: CC = X86::COND_A; break; - case CmpInst::FCMP_OLE: NeedSwap = true; [[fallthrough]]; - case CmpInst::FCMP_OGE: CC = X86::COND_AE; break; - case CmpInst::FCMP_UGT: NeedSwap = true; [[fallthrough]]; - case CmpInst::FCMP_ULT: CC = X86::COND_B; break; - case CmpInst::FCMP_UGE: NeedSwap = true; [[fallthrough]]; - case CmpInst::FCMP_ULE: CC = X86::COND_BE; break; - case CmpInst::FCMP_ONE: CC = X86::COND_NE; break; - case CmpInst::FCMP_UNO: CC = X86::COND_P; break; - case CmpInst::FCMP_ORD: CC = X86::COND_NP; break; - case CmpInst::FCMP_OEQ: [[fallthrough]]; - case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break; + case CmpInst::FCMP_UEQ: + CC = X86::COND_E; + break; + case CmpInst::FCMP_OLT: + NeedSwap = true; + [[fallthrough]]; + case CmpInst::FCMP_OGT: + CC = X86::COND_A; + break; + case CmpInst::FCMP_OLE: + NeedSwap = true; + [[fallthrough]]; + case CmpInst::FCMP_OGE: + CC = X86::COND_AE; + break; + case CmpInst::FCMP_UGT: + NeedSwap = true; + [[fallthrough]]; + case CmpInst::FCMP_ULT: + CC = X86::COND_B; + break; + case CmpInst::FCMP_UGE: + NeedSwap = true; + [[fallthrough]]; + case CmpInst::FCMP_ULE: + CC = X86::COND_BE; + break; + case CmpInst::FCMP_ONE: + CC = X86::COND_NE; + break; + case CmpInst::FCMP_UNO: + CC = X86::COND_P; + break; + case CmpInst::FCMP_ORD: + CC = X86::COND_NP; + break; + case CmpInst::FCMP_OEQ: + [[fallthrough]]; + case CmpInst::FCMP_UNE: + CC = X86::COND_INVALID; + break; // Integer Predicates - case CmpInst::ICMP_EQ: CC = X86::COND_E; break; - case CmpInst::ICMP_NE: CC = X86::COND_NE; break; - case CmpInst::ICMP_UGT: CC = X86::COND_A; break; - case CmpInst::ICMP_UGE: CC = X86::COND_AE; break; - case CmpInst::ICMP_ULT: CC = X86::COND_B; break; - case CmpInst::ICMP_ULE: CC = X86::COND_BE; break; - case CmpInst::ICMP_SGT: CC = X86::COND_G; break; - case CmpInst::ICMP_SGE: CC = X86::COND_GE; break; - case CmpInst::ICMP_SLT: CC = X86::COND_L; break; - case CmpInst::ICMP_SLE: CC = X86::COND_LE; break; + case CmpInst::ICMP_EQ: + CC = X86::COND_E; + break; + case CmpInst::ICMP_NE: + CC = X86::COND_NE; + break; + case CmpInst::ICMP_UGT: + CC = X86::COND_A; + break; + case CmpInst::ICMP_UGE: + CC = X86::COND_AE; + break; + case CmpInst::ICMP_ULT: + CC = X86::COND_B; + break; + case CmpInst::ICMP_ULE: + CC = X86::COND_BE; + break; + case CmpInst::ICMP_SGT: + CC = X86::COND_G; + break; + case CmpInst::ICMP_SGE: + CC = X86::COND_GE; + break; + case CmpInst::ICMP_SLT: + CC = X86::COND_L; + break; + case CmpInst::ICMP_SLE: + CC = X86::COND_LE; + break; } return std::make_pair(CC, NeedSwap); @@ -2899,39 +3328,59 @@ X86::getX86ConditionCode(CmpInst::Predicate Predicate) { /// Return a cmov opcode for the given register size in bytes, and operand type. unsigned X86::getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand) { - switch(RegBytes) { - default: llvm_unreachable("Illegal register size!"); - case 2: return HasMemoryOperand ? X86::CMOV16rm : X86::CMOV16rr; - case 4: return HasMemoryOperand ? X86::CMOV32rm : X86::CMOV32rr; - case 8: return HasMemoryOperand ? X86::CMOV64rm : X86::CMOV64rr; + switch (RegBytes) { + default: + llvm_unreachable("Illegal register size!"); + case 2: + return HasMemoryOperand ? X86::CMOV16rm : X86::CMOV16rr; + case 4: + return HasMemoryOperand ? X86::CMOV32rm : X86::CMOV32rr; + case 8: + return HasMemoryOperand ? X86::CMOV64rm : X86::CMOV64rr; } } /// Get the VPCMP immediate for the given condition. unsigned X86::getVPCMPImmForCond(ISD::CondCode CC) { switch (CC) { - default: llvm_unreachable("Unexpected SETCC condition"); - case ISD::SETNE: return 4; - case ISD::SETEQ: return 0; + default: + llvm_unreachable("Unexpected SETCC condition"); + case ISD::SETNE: + return 4; + case ISD::SETEQ: + return 0; case ISD::SETULT: - case ISD::SETLT: return 1; + case ISD::SETLT: + return 1; case ISD::SETUGT: - case ISD::SETGT: return 6; + case ISD::SETGT: + return 6; case ISD::SETUGE: - case ISD::SETGE: return 5; + case ISD::SETGE: + return 5; case ISD::SETULE: - case ISD::SETLE: return 2; + case ISD::SETLE: + return 2; } } /// Get the VPCMP immediate if the operands are swapped. unsigned X86::getSwappedVPCMPImm(unsigned Imm) { switch (Imm) { - default: llvm_unreachable("Unreachable!"); - case 0x01: Imm = 0x06; break; // LT -> NLE - case 0x02: Imm = 0x05; break; // LE -> NLT - case 0x05: Imm = 0x02; break; // NLT -> LE - case 0x06: Imm = 0x01; break; // NLE -> LT + default: + llvm_unreachable("Unreachable!"); + case 0x01: + Imm = 0x06; + break; // LT -> NLE + case 0x02: + Imm = 0x05; + break; // LE -> NLT + case 0x05: + Imm = 0x02; + break; // NLT -> LE + case 0x06: + Imm = 0x01; + break; // NLE -> LT case 0x00: // EQ case 0x03: // FALSE case 0x04: // NE @@ -2945,11 +3394,20 @@ unsigned X86::getSwappedVPCMPImm(unsigned Imm) { /// Get the VPCOM immediate if the operands are swapped. unsigned X86::getSwappedVPCOMImm(unsigned Imm) { switch (Imm) { - default: llvm_unreachable("Unreachable!"); - case 0x00: Imm = 0x02; break; // LT -> GT - case 0x01: Imm = 0x03; break; // LE -> GE - case 0x02: Imm = 0x00; break; // GT -> LT - case 0x03: Imm = 0x01; break; // GE -> LE + default: + llvm_unreachable("Unreachable!"); + case 0x00: + Imm = 0x02; + break; // LT -> GT + case 0x01: + Imm = 0x03; + break; // LE -> GE + case 0x02: + Imm = 0x00; + break; // GT -> LT + case 0x03: + Imm = 0x01; + break; // GE -> LE case 0x04: // EQ case 0x05: // NE case 0x06: // FALSE @@ -2964,11 +3422,14 @@ unsigned X86::getSwappedVPCOMImm(unsigned Imm) { unsigned X86::getSwappedVCMPImm(unsigned Imm) { // Only need the lower 2 bits to distinquish. switch (Imm & 0x3) { - default: llvm_unreachable("Unreachable!"); - case 0x00: case 0x03: + default: + llvm_unreachable("Unreachable!"); + case 0x00: + case 0x03: // EQ/NE/TRUE/FALSE/ORD/UNORD don't change immediate when commuted. break; - case 0x01: case 0x02: + case 0x01: + case 0x02: // Need to toggle bits 3:0. Bit 4 stays the same. Imm ^= 0xf; break; @@ -3078,9 +3539,9 @@ void X86InstrInfo::replaceBranchWithTailCall( auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc)); MIB->addOperand(TailCall.getOperand(0)); // Destination. - MIB.addImm(0); // Stack offset (not used). - MIB->addOperand(BranchCond[0]); // Condition. - MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters. + MIB.addImm(0); // Stack offset (not used). + MIB->addOperand(BranchCond[0]); // Condition. + MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters. // Add implicit uses and defs of all live regs potentially clobbered by the // call. This way they still appear live across the call. @@ -3173,7 +3634,7 @@ bool X86InstrInfo::AnalyzeBranchImpl( // Handle conditional branches. X86::CondCode BranchCode = X86::getCondFromBranch(*I); if (BranchCode == X86::COND_INVALID) - return true; // Can't handle indirect branch. + return true; // Can't handle indirect branch. // In practice we should never have an undef eflags operand, if we do // abort here as we are not prepared to preserve the flag. @@ -3205,8 +3666,8 @@ bool X86InstrInfo::AnalyzeBranchImpl( // we could handle more patterns here, but we shouldn't expect to see them // if instruction selection has done a reasonable job. if (TBB == NewTBB && - ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) || - (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) { + ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) || + (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) { BranchCode = X86::COND_NE_OR_P; } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) || (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) { @@ -3408,8 +3869,7 @@ unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL, - int *BytesAdded) const { + const DebugLoc &DL, int *BytesAdded) const { // Shouldn't be a fall through. assert(TBB && "insertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 1 || Cond.size() == 0) && @@ -3480,7 +3940,7 @@ bool X86InstrInfo::canInsertSelect(const MachineBasicBlock &MBB, // Check register classes. const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); const TargetRegisterClass *RC = - RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); + RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); if (!RC) return false; @@ -3532,7 +3992,8 @@ static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg, // SrcReg(MaskReg) -> DestReg(GR64) // SrcReg(MaskReg) -> DestReg(GR32) - // All KMASK RegClasses hold the same k registers, can be tested against anyone. + // All KMASK RegClasses hold the same k registers, can be tested against + // anyone. if (X86::VK16RegClass.contains(SrcReg)) { if (X86::GR64RegClass.contains(DestReg)) { assert(Subtarget.hasBWI()); @@ -3546,7 +4007,8 @@ static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg, // SrcReg(GR64) -> DestReg(MaskReg) // SrcReg(GR32) -> DestReg(MaskReg) - // All KMASK RegClasses hold the same k registers, can be tested against anyone. + // All KMASK RegClasses hold the same k registers, can be tested against + // anyone. if (X86::VK16RegClass.contains(DestReg)) { if (X86::GR64RegClass.contains(SrcReg)) { assert(Subtarget.hasBWI()); @@ -3557,7 +4019,6 @@ static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg, : (HasEGPR ? X86::KMOVWkr_EVEX : X86::KMOVWkr); } - // SrcReg(VR128) -> DestReg(GR64) // SrcReg(VR64) -> DestReg(GR64) // SrcReg(GR64) -> DestReg(VR128) @@ -3566,18 +4027,18 @@ static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg, if (X86::GR64RegClass.contains(DestReg)) { if (X86::VR128XRegClass.contains(SrcReg)) // Copy from a VR128 register to a GR64 register. - return HasAVX512 ? X86::VMOVPQIto64Zrr : - HasAVX ? X86::VMOVPQIto64rr : - X86::MOVPQIto64rr; + return HasAVX512 ? X86::VMOVPQIto64Zrr + : HasAVX ? X86::VMOVPQIto64rr + : X86::MOVPQIto64rr; if (X86::VR64RegClass.contains(SrcReg)) // Copy from a VR64 register to a GR64 register. return X86::MMX_MOVD64from64rr; } else if (X86::GR64RegClass.contains(SrcReg)) { // Copy from a GR64 register to a VR128 register. if (X86::VR128XRegClass.contains(DestReg)) - return HasAVX512 ? X86::VMOV64toPQIZrr : - HasAVX ? X86::VMOV64toPQIrr : - X86::MOV64toPQIrr; + return HasAVX512 ? X86::VMOV64toPQIZrr + : HasAVX ? X86::VMOV64toPQIrr + : X86::MOV64toPQIrr; // Copy from a GR64 register to a VR64 register. if (X86::VR64RegClass.contains(DestReg)) return X86::MMX_MOVD64to64rr; @@ -3589,16 +4050,16 @@ static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg, if (X86::GR32RegClass.contains(DestReg) && X86::VR128XRegClass.contains(SrcReg)) // Copy from a VR128 register to a GR32 register. - return HasAVX512 ? X86::VMOVPDI2DIZrr : - HasAVX ? X86::VMOVPDI2DIrr : - X86::MOVPDI2DIrr; + return HasAVX512 ? X86::VMOVPDI2DIZrr + : HasAVX ? X86::VMOVPDI2DIrr + : X86::MOVPDI2DIrr; if (X86::VR128XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg)) // Copy from a VR128 register to a VR128 register. - return HasAVX512 ? X86::VMOVDI2PDIZrr : - HasAVX ? X86::VMOVDI2PDIrr : - X86::MOVDI2PDIrr; + return HasAVX512 ? X86::VMOVDI2PDIZrr + : HasAVX ? X86::VMOVDI2PDIrr + : X86::MOVDI2PDIrr; return 0; } @@ -3619,16 +4080,14 @@ void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB, else if (X86::GR8RegClass.contains(DestReg, SrcReg)) { // Copying to or from a physical H register on x86-64 requires a NOREX // move. Otherwise use a normal move. - if ((isHReg(DestReg) || isHReg(SrcReg)) && - Subtarget.is64Bit()) { + if ((isHReg(DestReg) || isHReg(SrcReg)) && Subtarget.is64Bit()) { Opc = X86::MOV8rr_NOREX; // Both operands must be encodable without an REX prefix. assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) && "8-bit H register can not be copied outside GR8_NOREX"); } else Opc = X86::MOV8rr; - } - else if (X86::VR64RegClass.contains(DestReg, SrcReg)) + } else if (X86::VR64RegClass.contains(DestReg, SrcReg)) Opc = X86::MMX_MOVQ64rr; else if (X86::VR128XRegClass.contains(DestReg, SrcReg)) { if (HasVLX) @@ -3640,10 +4099,10 @@ void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB, // 512-bit move. Opc = X86::VMOVAPSZrr; const TargetRegisterInfo *TRI = &getRegisterInfo(); - DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm, - &X86::VR512RegClass); - SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, - &X86::VR512RegClass); + DestReg = + TRI->getMatchingSuperReg(DestReg, X86::sub_xmm, &X86::VR512RegClass); + SrcReg = + TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass); } } else if (X86::VR256XRegClass.contains(DestReg, SrcReg)) { if (HasVLX) @@ -3655,14 +4114,15 @@ void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB, // 512-bit move. Opc = X86::VMOVAPSZrr; const TargetRegisterInfo *TRI = &getRegisterInfo(); - DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm, - &X86::VR512RegClass); - SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, - &X86::VR512RegClass); + DestReg = + TRI->getMatchingSuperReg(DestReg, X86::sub_ymm, &X86::VR512RegClass); + SrcReg = + TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass); } } else if (X86::VR512RegClass.contains(DestReg, SrcReg)) Opc = X86::VMOVAPSZrr; - // All KMASK RegClasses hold the same k registers, can be tested against anyone. + // All KMASK RegClasses hold the same k registers, can be tested against + // anyone. else if (X86::VK16RegClass.contains(DestReg, SrcReg)) Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk; if (!Opc) @@ -3670,7 +4130,7 @@ void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB, if (Opc) { BuildMI(MBB, MI, DL, get(Opc), DestReg) - .addReg(SrcReg, getKillRegState(KillSrc)); + .addReg(SrcReg, getKillRegState(KillSrc)); return; } @@ -3745,13 +4205,12 @@ static unsigned getLoadStoreRegOpcode(Register Reg, if (X86::GR32RegClass.hasSubClassEq(RC)) return Load ? X86::MOV32rm : X86::MOV32mr; if (X86::FR32XRegClass.hasSubClassEq(RC)) - return Load ? - (HasAVX512 ? X86::VMOVSSZrm_alt : - HasAVX ? X86::VMOVSSrm_alt : - X86::MOVSSrm_alt) : - (HasAVX512 ? X86::VMOVSSZmr : - HasAVX ? X86::VMOVSSmr : - X86::MOVSSmr); + return Load ? (HasAVX512 ? X86::VMOVSSZrm_alt + : HasAVX ? X86::VMOVSSrm_alt + : X86::MOVSSrm_alt) + : (HasAVX512 ? X86::VMOVSSZmr + : HasAVX ? X86::VMOVSSmr + : X86::MOVSSmr); if (X86::RFP32RegClass.hasSubClassEq(RC)) return Load ? X86::LD_Fp32m : X86::ST_Fp32m; if (X86::VK32RegClass.hasSubClassEq(RC)) { @@ -3775,13 +4234,12 @@ static unsigned getLoadStoreRegOpcode(Register Reg, if (X86::GR64RegClass.hasSubClassEq(RC)) return Load ? X86::MOV64rm : X86::MOV64mr; if (X86::FR64XRegClass.hasSubClassEq(RC)) - return Load ? - (HasAVX512 ? X86::VMOVSDZrm_alt : - HasAVX ? X86::VMOVSDrm_alt : - X86::MOVSDrm_alt) : - (HasAVX512 ? X86::VMOVSDZmr : - HasAVX ? X86::VMOVSDmr : - X86::MOVSDmr); + return Load ? (HasAVX512 ? X86::VMOVSDZrm_alt + : HasAVX ? X86::VMOVSDrm_alt + : X86::MOVSDrm_alt) + : (HasAVX512 ? X86::VMOVSDZmr + : HasAVX ? X86::VMOVSDmr + : X86::MOVSDmr); if (X86::VR64RegClass.hasSubClassEq(RC)) return Load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr; if (X86::RFP64RegClass.hasSubClassEq(RC)) @@ -3799,25 +4257,23 @@ static unsigned getLoadStoreRegOpcode(Register Reg, if (X86::VR128XRegClass.hasSubClassEq(RC)) { // If stack is realigned we can use aligned stores. if (IsStackAligned) - return Load ? - (HasVLX ? X86::VMOVAPSZ128rm : - HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX : - HasAVX ? X86::VMOVAPSrm : - X86::MOVAPSrm): - (HasVLX ? X86::VMOVAPSZ128mr : - HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX : - HasAVX ? X86::VMOVAPSmr : - X86::MOVAPSmr); + return Load ? (HasVLX ? X86::VMOVAPSZ128rm + : HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX + : HasAVX ? X86::VMOVAPSrm + : X86::MOVAPSrm) + : (HasVLX ? X86::VMOVAPSZ128mr + : HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX + : HasAVX ? X86::VMOVAPSmr + : X86::MOVAPSmr); else - return Load ? - (HasVLX ? X86::VMOVUPSZ128rm : - HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX : - HasAVX ? X86::VMOVUPSrm : - X86::MOVUPSrm): - (HasVLX ? X86::VMOVUPSZ128mr : - HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX : - HasAVX ? X86::VMOVUPSmr : - X86::MOVUPSmr); + return Load ? (HasVLX ? X86::VMOVUPSZ128rm + : HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX + : HasAVX ? X86::VMOVUPSrm + : X86::MOVUPSrm) + : (HasVLX ? X86::VMOVUPSZ128mr + : HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX + : HasAVX ? X86::VMOVUPSmr + : X86::MOVUPSmr); } llvm_unreachable("Unknown 16-byte regclass"); } @@ -3825,21 +4281,19 @@ static unsigned getLoadStoreRegOpcode(Register Reg, assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass"); // If stack is realigned we can use aligned stores. if (IsStackAligned) - return Load ? - (HasVLX ? X86::VMOVAPSZ256rm : - HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX : - X86::VMOVAPSYrm) : - (HasVLX ? X86::VMOVAPSZ256mr : - HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX : - X86::VMOVAPSYmr); + return Load ? (HasVLX ? X86::VMOVAPSZ256rm + : HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX + : X86::VMOVAPSYrm) + : (HasVLX ? X86::VMOVAPSZ256mr + : HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX + : X86::VMOVAPSYmr); else - return Load ? - (HasVLX ? X86::VMOVUPSZ256rm : - HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX : - X86::VMOVUPSYrm) : - (HasVLX ? X86::VMOVUPSZ256mr : - HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX : - X86::VMOVUPSYmr); + return Load ? (HasVLX ? X86::VMOVUPSZ256rm + : HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX + : X86::VMOVUPSYrm) + : (HasVLX ? X86::VMOVUPSZ256mr + : HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX + : X86::VMOVUPSYmr); case 64: assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass"); assert(STI.hasAVX512() && "Using 512-bit register requires AVX512"); @@ -4131,7 +4585,8 @@ bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const { switch (MI.getOpcode()) { - default: break; + default: + break; case X86::CMP64ri32: case X86::CMP32ri: case X86::CMP16ri: @@ -4294,104 +4749,225 @@ inline static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag, } switch (MI.getOpcode()) { - default: return false; + default: + return false; // The shift instructions only modify ZF if their shift count is non-zero. // N.B.: The processor truncates the shift count depending on the encoding. - case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri: - case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri: - return getTruncatedShiftCount(MI, 2) != 0; + case X86::SAR8ri: + case X86::SAR16ri: + case X86::SAR32ri: + case X86::SAR64ri: + case X86::SHR8ri: + case X86::SHR16ri: + case X86::SHR32ri: + case X86::SHR64ri: + return getTruncatedShiftCount(MI, 2) != 0; // Some left shift instructions can be turned into LEA instructions but only // if their flags aren't used. Avoid transforming such instructions. - case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{ + case X86::SHL8ri: + case X86::SHL16ri: + case X86::SHL32ri: + case X86::SHL64ri: { unsigned ShAmt = getTruncatedShiftCount(MI, 2); - if (isTruncatedShiftCountForLEA(ShAmt)) return false; + if (isTruncatedShiftCountForLEA(ShAmt)) + return false; return ShAmt != 0; } - case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8: - case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8: - return getTruncatedShiftCount(MI, 3) != 0; - - case X86::SUB64ri32: case X86::SUB32ri: case X86::SUB16ri: - case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr: - case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm: - case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm: - case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r: - case X86::ADD64ri32: case X86::ADD32ri: case X86::ADD16ri: - case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr: - case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm: - case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm: - case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r: - case X86::ADC64ri32: case X86::ADC32ri: case X86::ADC16ri: - case X86::ADC8ri: case X86::ADC64rr: case X86::ADC32rr: - case X86::ADC16rr: case X86::ADC8rr: case X86::ADC64rm: - case X86::ADC32rm: case X86::ADC16rm: case X86::ADC8rm: - case X86::SBB64ri32: case X86::SBB32ri: case X86::SBB16ri: - case X86::SBB8ri: case X86::SBB64rr: case X86::SBB32rr: - case X86::SBB16rr: case X86::SBB8rr: case X86::SBB64rm: - case X86::SBB32rm: case X86::SBB16rm: case X86::SBB8rm: - case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r: - case X86::LZCNT16rr: case X86::LZCNT16rm: - case X86::LZCNT32rr: case X86::LZCNT32rm: - case X86::LZCNT64rr: case X86::LZCNT64rm: - case X86::POPCNT16rr:case X86::POPCNT16rm: - case X86::POPCNT32rr:case X86::POPCNT32rm: - case X86::POPCNT64rr:case X86::POPCNT64rm: - case X86::TZCNT16rr: case X86::TZCNT16rm: - case X86::TZCNT32rr: case X86::TZCNT32rm: - case X86::TZCNT64rr: case X86::TZCNT64rm: + case X86::SHRD16rri8: + case X86::SHRD32rri8: + case X86::SHRD64rri8: + case X86::SHLD16rri8: + case X86::SHLD32rri8: + case X86::SHLD64rri8: + return getTruncatedShiftCount(MI, 3) != 0; + + case X86::SUB64ri32: + case X86::SUB32ri: + case X86::SUB16ri: + case X86::SUB8ri: + case X86::SUB64rr: + case X86::SUB32rr: + case X86::SUB16rr: + case X86::SUB8rr: + case X86::SUB64rm: + case X86::SUB32rm: + case X86::SUB16rm: + case X86::SUB8rm: + case X86::DEC64r: + case X86::DEC32r: + case X86::DEC16r: + case X86::DEC8r: + case X86::ADD64ri32: + case X86::ADD32ri: + case X86::ADD16ri: + case X86::ADD8ri: + case X86::ADD64rr: + case X86::ADD32rr: + case X86::ADD16rr: + case X86::ADD8rr: + case X86::ADD64rm: + case X86::ADD32rm: + case X86::ADD16rm: + case X86::ADD8rm: + case X86::INC64r: + case X86::INC32r: + case X86::INC16r: + case X86::INC8r: + case X86::ADC64ri32: + case X86::ADC32ri: + case X86::ADC16ri: + case X86::ADC8ri: + case X86::ADC64rr: + case X86::ADC32rr: + case X86::ADC16rr: + case X86::ADC8rr: + case X86::ADC64rm: + case X86::ADC32rm: + case X86::ADC16rm: + case X86::ADC8rm: + case X86::SBB64ri32: + case X86::SBB32ri: + case X86::SBB16ri: + case X86::SBB8ri: + case X86::SBB64rr: + case X86::SBB32rr: + case X86::SBB16rr: + case X86::SBB8rr: + case X86::SBB64rm: + case X86::SBB32rm: + case X86::SBB16rm: + case X86::SBB8rm: + case X86::NEG8r: + case X86::NEG16r: + case X86::NEG32r: + case X86::NEG64r: + case X86::LZCNT16rr: + case X86::LZCNT16rm: + case X86::LZCNT32rr: + case X86::LZCNT32rm: + case X86::LZCNT64rr: + case X86::LZCNT64rm: + case X86::POPCNT16rr: + case X86::POPCNT16rm: + case X86::POPCNT32rr: + case X86::POPCNT32rm: + case X86::POPCNT64rr: + case X86::POPCNT64rm: + case X86::TZCNT16rr: + case X86::TZCNT16rm: + case X86::TZCNT32rr: + case X86::TZCNT32rm: + case X86::TZCNT64rr: + case X86::TZCNT64rm: return true; - case X86::AND64ri32: case X86::AND32ri: case X86::AND16ri: - case X86::AND8ri: case X86::AND64rr: case X86::AND32rr: - case X86::AND16rr: case X86::AND8rr: case X86::AND64rm: - case X86::AND32rm: case X86::AND16rm: case X86::AND8rm: - case X86::XOR64ri32: case X86::XOR32ri: case X86::XOR16ri: - case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr: - case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm: - case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm: - case X86::OR64ri32: case X86::OR32ri: case X86::OR16ri: - case X86::OR8ri: case X86::OR64rr: case X86::OR32rr: - case X86::OR16rr: case X86::OR8rr: case X86::OR64rm: - case X86::OR32rm: case X86::OR16rm: case X86::OR8rm: - case X86::ANDN32rr: case X86::ANDN32rm: - case X86::ANDN64rr: case X86::ANDN64rm: - case X86::BLSI32rr: case X86::BLSI32rm: - case X86::BLSI64rr: case X86::BLSI64rm: - case X86::BLSMSK32rr: case X86::BLSMSK32rm: - case X86::BLSMSK64rr: case X86::BLSMSK64rm: - case X86::BLSR32rr: case X86::BLSR32rm: - case X86::BLSR64rr: case X86::BLSR64rm: - case X86::BLCFILL32rr: case X86::BLCFILL32rm: - case X86::BLCFILL64rr: case X86::BLCFILL64rm: - case X86::BLCI32rr: case X86::BLCI32rm: - case X86::BLCI64rr: case X86::BLCI64rm: - case X86::BLCIC32rr: case X86::BLCIC32rm: - case X86::BLCIC64rr: case X86::BLCIC64rm: - case X86::BLCMSK32rr: case X86::BLCMSK32rm: - case X86::BLCMSK64rr: case X86::BLCMSK64rm: - case X86::BLCS32rr: case X86::BLCS32rm: - case X86::BLCS64rr: case X86::BLCS64rm: - case X86::BLSFILL32rr: case X86::BLSFILL32rm: - case X86::BLSFILL64rr: case X86::BLSFILL64rm: - case X86::BLSIC32rr: case X86::BLSIC32rm: - case X86::BLSIC64rr: case X86::BLSIC64rm: - case X86::BZHI32rr: case X86::BZHI32rm: - case X86::BZHI64rr: case X86::BZHI64rm: - case X86::T1MSKC32rr: case X86::T1MSKC32rm: - case X86::T1MSKC64rr: case X86::T1MSKC64rm: - case X86::TZMSK32rr: case X86::TZMSK32rm: - case X86::TZMSK64rr: case X86::TZMSK64rm: + case X86::AND64ri32: + case X86::AND32ri: + case X86::AND16ri: + case X86::AND8ri: + case X86::AND64rr: + case X86::AND32rr: + case X86::AND16rr: + case X86::AND8rr: + case X86::AND64rm: + case X86::AND32rm: + case X86::AND16rm: + case X86::AND8rm: + case X86::XOR64ri32: + case X86::XOR32ri: + case X86::XOR16ri: + case X86::XOR8ri: + case X86::XOR64rr: + case X86::XOR32rr: + case X86::XOR16rr: + case X86::XOR8rr: + case X86::XOR64rm: + case X86::XOR32rm: + case X86::XOR16rm: + case X86::XOR8rm: + case X86::OR64ri32: + case X86::OR32ri: + case X86::OR16ri: + case X86::OR8ri: + case X86::OR64rr: + case X86::OR32rr: + case X86::OR16rr: + case X86::OR8rr: + case X86::OR64rm: + case X86::OR32rm: + case X86::OR16rm: + case X86::OR8rm: + case X86::ANDN32rr: + case X86::ANDN32rm: + case X86::ANDN64rr: + case X86::ANDN64rm: + case X86::BLSI32rr: + case X86::BLSI32rm: + case X86::BLSI64rr: + case X86::BLSI64rm: + case X86::BLSMSK32rr: + case X86::BLSMSK32rm: + case X86::BLSMSK64rr: + case X86::BLSMSK64rm: + case X86::BLSR32rr: + case X86::BLSR32rm: + case X86::BLSR64rr: + case X86::BLSR64rm: + case X86::BLCFILL32rr: + case X86::BLCFILL32rm: + case X86::BLCFILL64rr: + case X86::BLCFILL64rm: + case X86::BLCI32rr: + case X86::BLCI32rm: + case X86::BLCI64rr: + case X86::BLCI64rm: + case X86::BLCIC32rr: + case X86::BLCIC32rm: + case X86::BLCIC64rr: + case X86::BLCIC64rm: + case X86::BLCMSK32rr: + case X86::BLCMSK32rm: + case X86::BLCMSK64rr: + case X86::BLCMSK64rm: + case X86::BLCS32rr: + case X86::BLCS32rm: + case X86::BLCS64rr: + case X86::BLCS64rm: + case X86::BLSFILL32rr: + case X86::BLSFILL32rm: + case X86::BLSFILL64rr: + case X86::BLSFILL64rm: + case X86::BLSIC32rr: + case X86::BLSIC32rm: + case X86::BLSIC64rr: + case X86::BLSIC64rm: + case X86::BZHI32rr: + case X86::BZHI32rm: + case X86::BZHI64rr: + case X86::BZHI64rm: + case X86::T1MSKC32rr: + case X86::T1MSKC32rm: + case X86::T1MSKC64rr: + case X86::T1MSKC64rm: + case X86::TZMSK32rr: + case X86::TZMSK32rm: + case X86::TZMSK64rr: + case X86::TZMSK64rm: // These instructions clear the overflow flag just like TEST. // FIXME: These are not the only instructions in this switch that clear the // overflow flag. ClearsOverflowFlag = true; return true; - case X86::BEXTR32rr: case X86::BEXTR64rr: - case X86::BEXTR32rm: case X86::BEXTR64rm: - case X86::BEXTRI32ri: case X86::BEXTRI32mi: - case X86::BEXTRI64ri: case X86::BEXTRI64mi: + case X86::BEXTR32rr: + case X86::BEXTR64rr: + case X86::BEXTR32rm: + case X86::BEXTR64rm: + case X86::BEXTRI32ri: + case X86::BEXTRI32mi: + case X86::BEXTRI64ri: + case X86::BEXTRI64mi: // BEXTR doesn't update the sign flag so we can't use it. It does clear // the overflow flag, but that's not useful without the sign flag. NoSignFlag = true; @@ -4402,7 +4978,8 @@ inline static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag, /// Check whether the use can be converted to remove a comparison against zero. static X86::CondCode isUseDefConvertible(const MachineInstr &MI) { switch (MI.getOpcode()) { - default: return X86::COND_INVALID; + default: + return X86::COND_INVALID; case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: @@ -4435,7 +5012,7 @@ static X86::CondCode isUseDefConvertible(const MachineInstr &MI) { case X86::BLSMSK32rr: case X86::BLSMSK64rr: return X86::COND_B; - // TODO: TBM instructions. + // TODO: TBM instructions. } } @@ -4448,7 +5025,8 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, const MachineRegisterInfo *MRI) const { // Check whether we can replace SUB with CMP. switch (CmpInstr.getOpcode()) { - default: break; + default: + break; case X86::SUB64ri32: case X86::SUB32ri: case X86::SUB16ri: @@ -4466,19 +5044,44 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, // There is no use of the destination register, we can replace SUB with CMP. unsigned NewOpcode = 0; switch (CmpInstr.getOpcode()) { - default: llvm_unreachable("Unreachable!"); - case X86::SUB64rm: NewOpcode = X86::CMP64rm; break; - case X86::SUB32rm: NewOpcode = X86::CMP32rm; break; - case X86::SUB16rm: NewOpcode = X86::CMP16rm; break; - case X86::SUB8rm: NewOpcode = X86::CMP8rm; break; - case X86::SUB64rr: NewOpcode = X86::CMP64rr; break; - case X86::SUB32rr: NewOpcode = X86::CMP32rr; break; - case X86::SUB16rr: NewOpcode = X86::CMP16rr; break; - case X86::SUB8rr: NewOpcode = X86::CMP8rr; break; - case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break; - case X86::SUB32ri: NewOpcode = X86::CMP32ri; break; - case X86::SUB16ri: NewOpcode = X86::CMP16ri; break; - case X86::SUB8ri: NewOpcode = X86::CMP8ri; break; + default: + llvm_unreachable("Unreachable!"); + case X86::SUB64rm: + NewOpcode = X86::CMP64rm; + break; + case X86::SUB32rm: + NewOpcode = X86::CMP32rm; + break; + case X86::SUB16rm: + NewOpcode = X86::CMP16rm; + break; + case X86::SUB8rm: + NewOpcode = X86::CMP8rm; + break; + case X86::SUB64rr: + NewOpcode = X86::CMP64rr; + break; + case X86::SUB32rr: + NewOpcode = X86::CMP32rr; + break; + case X86::SUB16rr: + NewOpcode = X86::CMP16rr; + break; + case X86::SUB8rr: + NewOpcode = X86::CMP8rr; + break; + case X86::SUB64ri32: + NewOpcode = X86::CMP64ri32; + break; + case X86::SUB32ri: + NewOpcode = X86::CMP32ri; + break; + case X86::SUB16ri: + NewOpcode = X86::CMP16ri; + break; + case X86::SUB8ri: + NewOpcode = X86::CMP8ri; + break; } CmpInstr.setDesc(get(NewOpcode)); CmpInstr.removeOperand(0); @@ -4614,7 +5217,7 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, // If we are done with the basic block, we need to check whether EFLAGS is // live-out. bool FlagsMayLiveOut = true; - SmallVector, 4> OpsToUpdate; + SmallVector, 4> OpsToUpdate; MachineBasicBlock::iterator AfterCmpInstr = std::next(MachineBasicBlock::iterator(CmpInstr)); for (MachineInstr &Instr : make_range(AfterCmpInstr, CmpMBB.end())) { @@ -4637,24 +5240,31 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, X86::CondCode ReplacementCC = X86::COND_INVALID; if (MI) { switch (OldCC) { - default: break; - case X86::COND_A: case X86::COND_AE: - case X86::COND_B: case X86::COND_BE: + default: + break; + case X86::COND_A: + case X86::COND_AE: + case X86::COND_B: + case X86::COND_BE: // CF is used, we can't perform this optimization. return false; - case X86::COND_G: case X86::COND_GE: - case X86::COND_L: case X86::COND_LE: + case X86::COND_G: + case X86::COND_GE: + case X86::COND_L: + case X86::COND_LE: // If SF is used, but the instruction doesn't update the SF, then we // can't do the optimization. if (NoSignFlag) return false; [[fallthrough]]; - case X86::COND_O: case X86::COND_NO: + case X86::COND_O: + case X86::COND_NO: // If OF is used, the instruction needs to clear it like CmpZero does. if (!ClearsOverflowFlag) return false; break; - case X86::COND_S: case X86::COND_NS: + case X86::COND_S: + case X86::COND_NS: // If SF is used, but the instruction doesn't update the SF, then we // can't do the optimization. if (NoSignFlag) @@ -4850,130 +5460,130 @@ MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI, /// ShiftRotate will be set to true if the Opcode is shift or rotate. /// If the ALUri can be further changed to COPY when the immediate is 0, set /// CanConvert2Copy to true. -static unsigned ConvertALUrr2ALUri(unsigned Opcode, bool &CanConvert2Copy, - bool &ShiftRotate) { - CanConvert2Copy = false; - ShiftRotate = false; - unsigned NewOpcode = 0; - switch (Opcode) { - case X86::ADD64rr: - NewOpcode = X86::ADD64ri32; - CanConvert2Copy = true; - break; - case X86::ADC64rr: - NewOpcode = X86::ADC64ri32; - break; - case X86::SUB64rr: - NewOpcode = X86::SUB64ri32; - CanConvert2Copy = true; - break; - case X86::SBB64rr: - NewOpcode = X86::SBB64ri32; - break; - case X86::AND64rr: - NewOpcode = X86::AND64ri32; - break; - case X86::OR64rr: - NewOpcode = X86::OR64ri32; - CanConvert2Copy = true; - break; - case X86::XOR64rr: - NewOpcode = X86::XOR64ri32; - CanConvert2Copy = true; - break; - case X86::TEST64rr: - NewOpcode = X86::TEST64ri32; - break; - case X86::CMP64rr: - NewOpcode = X86::CMP64ri32; - break; - case X86::SHR64rCL: - NewOpcode = X86::SHR64ri; - ShiftRotate = true; - break; - case X86::SHL64rCL: - NewOpcode = X86::SHL64ri; - ShiftRotate = true; - break; - case X86::SAR64rCL: - NewOpcode = X86::SAR64ri; - ShiftRotate = true; - break; - case X86::ROL64rCL: - NewOpcode = X86::ROL64ri; - ShiftRotate = true; - break; - case X86::ROR64rCL: - NewOpcode = X86::ROR64ri; - ShiftRotate = true; - break; - case X86::RCL64rCL: - NewOpcode = X86::RCL64ri; - ShiftRotate = true; - break; - case X86::RCR64rCL: - NewOpcode = X86::RCR64ri; - ShiftRotate = true; - break; - case X86::ADD32rr: - NewOpcode = X86::ADD32ri; - CanConvert2Copy = true; - break; - case X86::ADC32rr: - NewOpcode = X86::ADC32ri; - break; - case X86::SUB32rr: - NewOpcode = X86::SUB32ri; - CanConvert2Copy = true; - break; - case X86::SBB32rr: - NewOpcode = X86::SBB32ri; - break; - case X86::AND32rr: - NewOpcode = X86::AND32ri; - break; - case X86::OR32rr: - NewOpcode = X86::OR32ri; - CanConvert2Copy = true; - break; - case X86::XOR32rr: - NewOpcode = X86::XOR32ri; - CanConvert2Copy = true; - break; - case X86::TEST32rr: - NewOpcode = X86::TEST32ri; - break; - case X86::CMP32rr: - NewOpcode = X86::CMP32ri; - break; - case X86::SHR32rCL: - NewOpcode = X86::SHR32ri; - ShiftRotate = true; - break; - case X86::SHL32rCL: - NewOpcode = X86::SHL32ri; - ShiftRotate = true; - break; - case X86::SAR32rCL: - NewOpcode = X86::SAR32ri; - ShiftRotate = true; - break; - case X86::ROL32rCL: - NewOpcode = X86::ROL32ri; - ShiftRotate = true; - break; - case X86::ROR32rCL: - NewOpcode = X86::ROR32ri; - ShiftRotate = true; - break; - case X86::RCL32rCL: - NewOpcode = X86::RCL32ri; - ShiftRotate = true; - break; - case X86::RCR32rCL: - NewOpcode = X86::RCR32ri; - ShiftRotate = true; - break; +static unsigned ConvertALUrr2ALUri(unsigned Opcode, bool &CanConvert2Copy, + bool &ShiftRotate) { + CanConvert2Copy = false; + ShiftRotate = false; + unsigned NewOpcode = 0; + switch (Opcode) { + case X86::ADD64rr: + NewOpcode = X86::ADD64ri32; + CanConvert2Copy = true; + break; + case X86::ADC64rr: + NewOpcode = X86::ADC64ri32; + break; + case X86::SUB64rr: + NewOpcode = X86::SUB64ri32; + CanConvert2Copy = true; + break; + case X86::SBB64rr: + NewOpcode = X86::SBB64ri32; + break; + case X86::AND64rr: + NewOpcode = X86::AND64ri32; + break; + case X86::OR64rr: + NewOpcode = X86::OR64ri32; + CanConvert2Copy = true; + break; + case X86::XOR64rr: + NewOpcode = X86::XOR64ri32; + CanConvert2Copy = true; + break; + case X86::TEST64rr: + NewOpcode = X86::TEST64ri32; + break; + case X86::CMP64rr: + NewOpcode = X86::CMP64ri32; + break; + case X86::SHR64rCL: + NewOpcode = X86::SHR64ri; + ShiftRotate = true; + break; + case X86::SHL64rCL: + NewOpcode = X86::SHL64ri; + ShiftRotate = true; + break; + case X86::SAR64rCL: + NewOpcode = X86::SAR64ri; + ShiftRotate = true; + break; + case X86::ROL64rCL: + NewOpcode = X86::ROL64ri; + ShiftRotate = true; + break; + case X86::ROR64rCL: + NewOpcode = X86::ROR64ri; + ShiftRotate = true; + break; + case X86::RCL64rCL: + NewOpcode = X86::RCL64ri; + ShiftRotate = true; + break; + case X86::RCR64rCL: + NewOpcode = X86::RCR64ri; + ShiftRotate = true; + break; + case X86::ADD32rr: + NewOpcode = X86::ADD32ri; + CanConvert2Copy = true; + break; + case X86::ADC32rr: + NewOpcode = X86::ADC32ri; + break; + case X86::SUB32rr: + NewOpcode = X86::SUB32ri; + CanConvert2Copy = true; + break; + case X86::SBB32rr: + NewOpcode = X86::SBB32ri; + break; + case X86::AND32rr: + NewOpcode = X86::AND32ri; + break; + case X86::OR32rr: + NewOpcode = X86::OR32ri; + CanConvert2Copy = true; + break; + case X86::XOR32rr: + NewOpcode = X86::XOR32ri; + CanConvert2Copy = true; + break; + case X86::TEST32rr: + NewOpcode = X86::TEST32ri; + break; + case X86::CMP32rr: + NewOpcode = X86::CMP32ri; + break; + case X86::SHR32rCL: + NewOpcode = X86::SHR32ri; + ShiftRotate = true; + break; + case X86::SHL32rCL: + NewOpcode = X86::SHL32ri; + ShiftRotate = true; + break; + case X86::SAR32rCL: + NewOpcode = X86::SAR32ri; + ShiftRotate = true; + break; + case X86::ROL32rCL: + NewOpcode = X86::ROL32ri; + ShiftRotate = true; + break; + case X86::ROR32rCL: + NewOpcode = X86::ROR32ri; + ShiftRotate = true; + break; + case X86::RCL32rCL: + NewOpcode = X86::RCL32ri; + ShiftRotate = true; + break; + case X86::RCR32rCL: + NewOpcode = X86::RCR32ri; + ShiftRotate = true; + break; } return NewOpcode; } @@ -5042,8 +5652,8 @@ bool X86InstrInfo::FoldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI, if (ImmVal == 0) { // MOV32r0 clobbers EFLAGS. const TargetRegisterInfo *TRI = &getRegisterInfo(); - if (UseMI.getParent()->computeRegisterLiveness(TRI, X86::EFLAGS, UseMI) - != MachineBasicBlock::LQR_Dead) + if (UseMI.getParent()->computeRegisterLiveness( + TRI, X86::EFLAGS, UseMI) != MachineBasicBlock::LQR_Dead) return false; // MOV32r0 is different than other cases because it doesn't encode the @@ -5052,10 +5662,10 @@ bool X86InstrInfo::FoldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI, return true; UseMI.setDesc(get(X86::MOV32r0)); UseMI.removeOperand(UseMI.findRegisterUseOperandIdx(Reg)); - UseMI.addOperand(MachineOperand::CreateReg(X86::EFLAGS, /*isDef=*/ true, - /*isImp=*/ true, - /*isKill=*/ false, - /*isDead=*/ true)); + UseMI.addOperand(MachineOperand::CreateReg(X86::EFLAGS, /*isDef=*/true, + /*isImp=*/true, + /*isKill=*/false, + /*isDead=*/true)); Modified = true; } } else if (GR8Reg) @@ -5117,7 +5727,7 @@ bool X86InstrInfo::FoldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI, unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex; unsigned ImmOpNum = 2; if (!UseMI.getOperand(0).isDef()) { - Op1 = 0; // TEST, CMP + Op1 = 0; // TEST, CMP ImmOpNum = 1; } if (Opc == TargetOpcode::COPY) @@ -5166,8 +5776,7 @@ static bool Expand2AddrUndef(MachineInstrBuilder &MIB, // implicit operands. MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef); // But we don't trust that. - assert(MIB.getReg(1) == Reg && - MIB.getReg(2) == Reg && "Misplaced operand"); + assert(MIB.getReg(1) == Reg && MIB.getReg(2) == Reg && "Misplaced operand"); return true; } @@ -5222,8 +5831,9 @@ static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB, X86MachineFunctionInfo *X86FI = MBB.getParent()->getInfo(); if (X86FI->getUsesRedZone()) { - MIB->setDesc(TII.get(MIB->getOpcode() == - X86::MOV32ImmSExti8 ? X86::MOV32ri : X86::MOV64ri)); + MIB->setDesc(TII.get(MIB->getOpcode() == X86::MOV32ImmSExti8 + ? X86::MOV32ri + : X86::MOV64ri)); return true; } @@ -5232,8 +5842,7 @@ static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB, StackAdjustment = 8; BuildMI(MBB, I, DL, TII.get(X86::PUSH64i32)).addImm(Imm); MIB->setDesc(TII.get(X86::POP64r)); - MIB->getOperand(0) - .setReg(getX86SubSuperRegister(MIB.getReg(0), 64)); + MIB->getOperand(0).setReg(getX86SubSuperRegister(MIB.getReg(0), 64)); } else { assert(MIB->getOpcode() == X86::MOV32ImmSExti8); StackAdjustment = 4; @@ -5250,9 +5859,11 @@ static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB, bool NeedsDwarfCFI = !IsWin64Prologue && MF.needsFrameMoves(); bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI; if (EmitCFI) { - TFL->BuildCFI(MBB, I, DL, + TFL->BuildCFI( + MBB, I, DL, MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment)); - TFL->BuildCFI(MBB, std::next(I), DL, + TFL->BuildCFI( + MBB, std::next(I), DL, MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment)); } @@ -5275,8 +5886,12 @@ static void expandLoadStackGuard(MachineInstrBuilder &MIB, MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, Align(8)); MachineBasicBlock::iterator I = MIB.getInstr(); - BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1) - .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0) + BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg) + .addReg(X86::RIP) + .addImm(1) + .addReg(0) + .addGlobalAddress(GV, 0, X86II::MO_GOTPCREL) + .addReg(0) .addMemOperand(MMO); MIB->setDebugLoc(DL); MIB->setDesc(TII.get(X86::MOV64rm)); @@ -5301,8 +5916,7 @@ static bool expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) { static bool expandNOVLXLoad(MachineInstrBuilder &MIB, const TargetRegisterInfo *TRI, const MCInstrDesc &LoadDesc, - const MCInstrDesc &BroadcastDesc, - unsigned SubIdx) { + const MCInstrDesc &BroadcastDesc, unsigned SubIdx) { Register DestReg = MIB.getReg(0); // Check if DestReg is XMM16-31 or YMM16-31. if (TRI->getEncodingValue(DestReg) < 16) { @@ -5324,8 +5938,7 @@ static bool expandNOVLXLoad(MachineInstrBuilder &MIB, static bool expandNOVLXStore(MachineInstrBuilder &MIB, const TargetRegisterInfo *TRI, const MCInstrDesc &StoreDesc, - const MCInstrDesc &ExtractDesc, - unsigned SubIdx) { + const MCInstrDesc &ExtractDesc, unsigned SubIdx) { Register SrcReg = MIB.getReg(X86::AddrNumOperands); // Check if DestReg is XMM16-31 or YMM16-31. if (TRI->getEncodingValue(SrcReg) < 16) { @@ -5349,8 +5962,7 @@ static bool expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) { // Temporarily remove the immediate so we can add another source register. MIB->removeOperand(2); // Add the register. Don't copy the kill flag if there is one. - MIB.addReg(MIB.getReg(1), - getUndefRegState(MIB->getOperand(1).isUndef())); + MIB.addReg(MIB.getReg(1), getUndefRegState(MIB->getOperand(1).isUndef())); // Add back the immediate. MIB.addImm(ShiftAmt); return true; @@ -5363,9 +5975,9 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const { case X86::MOV32r0: return Expand2AddrUndef(MIB, get(X86::XOR32rr)); case X86::MOV32r1: - return expandMOV32r1(MIB, *this, /*MinusOne=*/ false); + return expandMOV32r1(MIB, *this, /*MinusOne=*/false); case X86::MOV32r_1: - return expandMOV32r1(MIB, *this, /*MinusOne=*/ true); + return expandMOV32r1(MIB, *this, /*MinusOne=*/true); case X86::MOV32ImmSExti8: case X86::MOV64ImmSExti8: return ExpandMOVImmSExti8(MIB, *this, Subtarget); @@ -5416,21 +6028,21 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const { if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) { Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm); MIB->getOperand(0).setReg(XReg); - Expand2AddrUndef(MIB, - get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr)); + Expand2AddrUndef(MIB, get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr)); MIB.addReg(SrcReg, RegState::ImplicitDefine); return true; } if (MI.getOpcode() == X86::AVX512_256_SET0) { // No VLX so we must reference a zmm. unsigned ZReg = - TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass); + TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass); MIB->getOperand(0).setReg(ZReg); } return Expand2AddrUndef(MIB, get(X86::VPXORDZrr)); } case X86::V_SETALLONES: - return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr)); + return Expand2AddrUndef(MIB, + get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr)); case X86::AVX2_SETALLONES: return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr)); case X86::AVX1_SETALLONES: { @@ -5445,8 +6057,10 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const { MIB->setDesc(get(X86::VPTERNLOGDZrri)); // VPTERNLOGD needs 3 register inputs and an immediate. // 0xff will return 1s for any input. - MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef) - .addReg(Reg, RegState::Undef).addImm(0xff); + MIB.addReg(Reg, RegState::Undef) + .addReg(Reg, RegState::Undef) + .addReg(Reg, RegState::Undef) + .addImm(0xff); return true; } case X86::AVX512_512_SEXT_MASK_32: @@ -5454,14 +6068,18 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const { Register Reg = MIB.getReg(0); Register MaskReg = MIB.getReg(1); unsigned MaskState = getRegState(MIB->getOperand(1)); - unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) ? - X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz; + unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) + ? X86::VPTERNLOGQZrrikz + : X86::VPTERNLOGDZrrikz; MI.removeOperand(1); MIB->setDesc(get(Opc)); // VPTERNLOG needs 3 register inputs and an immediate. // 0xff will return 1s for any input. - MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState) - .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff); + MIB.addReg(Reg, RegState::Undef) + .addReg(MaskReg, MaskState) + .addReg(Reg, RegState::Undef) + .addReg(Reg, RegState::Undef) + .addImm(0xff); return true; } case X86::VMOVAPSZ128rm_NOVLX: @@ -5502,10 +6120,9 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const { unsigned Is64Bit = MI.getOpcode() == X86::RDFLAGS64; MachineBasicBlock &MBB = *MIB->getParent(); - MachineInstr *NewMI = - BuildMI(MBB, MI, MIB->getDebugLoc(), - get(Is64Bit ? X86::PUSHF64 : X86::PUSHF32)) - .getInstr(); + MachineInstr *NewMI = BuildMI(MBB, MI, MIB->getDebugLoc(), + get(Is64Bit ? X86::PUSHF64 : X86::PUSHF32)) + .getInstr(); // Permit reads of the EFLAGS and DF registers without them being defined. // This intrinsic exists to read external processor state in flags, such as @@ -5543,30 +6160,56 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const { // registers, since it is not usable as a write mask. // FIXME: A more advanced approach would be to choose the best input mask // register based on context. - case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0); - case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0); - case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0); - case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0); - case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0); - case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0); + case X86::KSET0W: + return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0); + case X86::KSET0D: + return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0); + case X86::KSET0Q: + return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0); + case X86::KSET1W: + return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0); + case X86::KSET1D: + return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0); + case X86::KSET1Q: + return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0); case TargetOpcode::LOAD_STACK_GUARD: expandLoadStackGuard(MIB, *this); return true; case X86::XOR64_FP: case X86::XOR32_FP: return expandXorFP(MIB, *this); - case X86::SHLDROT32ri: return expandSHXDROT(MIB, get(X86::SHLD32rri8)); - case X86::SHLDROT64ri: return expandSHXDROT(MIB, get(X86::SHLD64rri8)); - case X86::SHRDROT32ri: return expandSHXDROT(MIB, get(X86::SHRD32rri8)); - case X86::SHRDROT64ri: return expandSHXDROT(MIB, get(X86::SHRD64rri8)); - case X86::ADD8rr_DB: MIB->setDesc(get(X86::OR8rr)); break; - case X86::ADD16rr_DB: MIB->setDesc(get(X86::OR16rr)); break; - case X86::ADD32rr_DB: MIB->setDesc(get(X86::OR32rr)); break; - case X86::ADD64rr_DB: MIB->setDesc(get(X86::OR64rr)); break; - case X86::ADD8ri_DB: MIB->setDesc(get(X86::OR8ri)); break; - case X86::ADD16ri_DB: MIB->setDesc(get(X86::OR16ri)); break; - case X86::ADD32ri_DB: MIB->setDesc(get(X86::OR32ri)); break; - case X86::ADD64ri32_DB: MIB->setDesc(get(X86::OR64ri32)); break; + case X86::SHLDROT32ri: + return expandSHXDROT(MIB, get(X86::SHLD32rri8)); + case X86::SHLDROT64ri: + return expandSHXDROT(MIB, get(X86::SHLD64rri8)); + case X86::SHRDROT32ri: + return expandSHXDROT(MIB, get(X86::SHRD32rri8)); + case X86::SHRDROT64ri: + return expandSHXDROT(MIB, get(X86::SHRD64rri8)); + case X86::ADD8rr_DB: + MIB->setDesc(get(X86::OR8rr)); + break; + case X86::ADD16rr_DB: + MIB->setDesc(get(X86::OR16rr)); + break; + case X86::ADD32rr_DB: + MIB->setDesc(get(X86::OR32rr)); + break; + case X86::ADD64rr_DB: + MIB->setDesc(get(X86::OR64rr)); + break; + case X86::ADD8ri_DB: + MIB->setDesc(get(X86::OR8ri)); + break; + case X86::ADD16ri_DB: + MIB->setDesc(get(X86::OR16ri)); + break; + case X86::ADD32ri_DB: + MIB->setDesc(get(X86::OR32ri)); + break; + case X86::ADD64ri32_DB: + MIB->setDesc(get(X86::OR64ri32)); + break; } return false; } @@ -5587,8 +6230,7 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const { /// /// FIXME: This should be turned into a TSFlags. /// -static bool hasPartialRegUpdate(unsigned Opcode, - const X86Subtarget &Subtarget, +static bool hasPartialRegUpdate(unsigned Opcode, const X86Subtarget &Subtarget, bool ForLoadFold = false) { switch (Opcode) { case X86::CVTSI2SSrr: @@ -6489,9 +7131,9 @@ MachineInstr *X86InstrInfo::foldMemoryOperandCustom( int PtrOffset = SrcIdx * 4; unsigned NewImm = (DstIdx << 4) | ZMask; unsigned NewOpCode = - (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm : - (MI.getOpcode() == X86::VINSERTPSrr) ? X86::VINSERTPSrm : - X86::INSERTPSrm; + (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm + : (MI.getOpcode() == X86::VINSERTPSrr) ? X86::VINSERTPSrm + : X86::INSERTPSrm; MachineInstr *NewMI = FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset); NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm); @@ -6511,9 +7153,9 @@ MachineInstr *X86InstrInfo::foldMemoryOperandCustom( unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8; if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment >= Align(8)) { unsigned NewOpCode = - (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm : - (MI.getOpcode() == X86::VMOVHLPSrr) ? X86::VMOVLPSrm : - X86::MOVLPSrm; + (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm + : (MI.getOpcode() == X86::VMOVHLPSrr) ? X86::VMOVLPSrm + : X86::MOVLPSrm; MachineInstr *NewMI = FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8); return NewMI; @@ -6542,7 +7184,7 @@ MachineInstr *X86InstrInfo::foldMemoryOperandCustom( static bool shouldPreventUndefRegUpdateMemFold(MachineFunction &MF, MachineInstr &MI) { - if (!hasUndefRegUpdate(MI.getOpcode(), 1, /*ForLoadFold*/true) || + if (!hasUndefRegUpdate(MI.getOpcode(), 1, /*ForLoadFold*/ true) || !MI.getOperand(1).isReg()) return false; @@ -6577,7 +7219,7 @@ MachineInstr *X86InstrInfo::foldMemoryOperandImpl( // Avoid partial and undef register update stalls unless optimizing for size. if (!MF.getFunction().hasOptSize() && - (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) || + (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/ true) || shouldPreventUndefRegUpdateMemFold(MF, MI))) return nullptr; @@ -6639,13 +7281,13 @@ MachineInstr *X86InstrInfo::foldMemoryOperandImpl( isTwoAddrFold || (OpNum == 0 && I->Flags & TB_FOLDED_LOAD) || OpNum > 0; bool FoldedStore = isTwoAddrFold || (OpNum == 0 && I->Flags & TB_FOLDED_STORE); - if (Alignment < Align(1ULL << ((I->Flags & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT))) + if (Alignment < + Align(1ULL << ((I->Flags & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT))) return nullptr; bool NarrowToMOV32rm = false; if (Size) { const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); - const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, - &RI, MF); + const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF); unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8; // Check if it's safe to fold the load. If the size of the object is // narrower than the load width, then it's not. @@ -6748,19 +7390,17 @@ MachineInstr *X86InstrInfo::foldMemoryOperandImpl( return nullptr; } -MachineInstr * -X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, - ArrayRef Ops, - MachineBasicBlock::iterator InsertPt, - int FrameIndex, LiveIntervals *LIS, - VirtRegMap *VRM) const { +MachineInstr *X86InstrInfo::foldMemoryOperandImpl( + MachineFunction &MF, MachineInstr &MI, ArrayRef Ops, + MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS, + VirtRegMap *VRM) const { // Check switch flag if (NoFusing) return nullptr; // Avoid partial and undef register update stalls unless optimizing for size. if (!MF.getFunction().hasOptSize() && - (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) || + (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/ true) || shouldPreventUndefRegUpdateMemFold(MF, MI))) return nullptr; @@ -6784,11 +7424,24 @@ X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, unsigned NewOpc = 0; unsigned RCSize = 0; switch (MI.getOpcode()) { - default: return nullptr; - case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break; - case X86::TEST16rr: NewOpc = X86::CMP16ri; RCSize = 2; break; - case X86::TEST32rr: NewOpc = X86::CMP32ri; RCSize = 4; break; - case X86::TEST64rr: NewOpc = X86::CMP64ri32; RCSize = 8; break; + default: + return nullptr; + case X86::TEST8rr: + NewOpc = X86::CMP8ri; + RCSize = 1; + break; + case X86::TEST16rr: + NewOpc = X86::CMP16ri; + RCSize = 2; + break; + case X86::TEST32rr: + NewOpc = X86::CMP32ri; + RCSize = 4; + break; + case X86::TEST64rr: + NewOpc = X86::CMP64ri32; + RCSize = 8; + break; } // Check if it's safe to fold the load. If the size of the object is // narrower than the load width, then it's not. @@ -6842,61 +7495,125 @@ static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI, case X86::VCVTSS2SDZrr_Int: case X86::VCVTSS2SDZrr_Intk: case X86::VCVTSS2SDZrr_Intkz: - case X86::CVTSS2SIrr_Int: case X86::CVTSS2SI64rr_Int: - case X86::VCVTSS2SIrr_Int: case X86::VCVTSS2SI64rr_Int: - case X86::VCVTSS2SIZrr_Int: case X86::VCVTSS2SI64Zrr_Int: - case X86::CVTTSS2SIrr_Int: case X86::CVTTSS2SI64rr_Int: - case X86::VCVTTSS2SIrr_Int: case X86::VCVTTSS2SI64rr_Int: - case X86::VCVTTSS2SIZrr_Int: case X86::VCVTTSS2SI64Zrr_Int: - case X86::VCVTSS2USIZrr_Int: case X86::VCVTSS2USI64Zrr_Int: - case X86::VCVTTSS2USIZrr_Int: case X86::VCVTTSS2USI64Zrr_Int: - case X86::RCPSSr_Int: case X86::VRCPSSr_Int: - case X86::RSQRTSSr_Int: case X86::VRSQRTSSr_Int: - case X86::ROUNDSSr_Int: case X86::VROUNDSSr_Int: - case X86::COMISSrr_Int: case X86::VCOMISSrr_Int: case X86::VCOMISSZrr_Int: - case X86::UCOMISSrr_Int:case X86::VUCOMISSrr_Int:case X86::VUCOMISSZrr_Int: - case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int: - case X86::CMPSSrr_Int: case X86::VCMPSSrr_Int: case X86::VCMPSSZrr_Int: - case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int: - case X86::MAXSSrr_Int: case X86::VMAXSSrr_Int: case X86::VMAXSSZrr_Int: - case X86::MINSSrr_Int: case X86::VMINSSrr_Int: case X86::VMINSSZrr_Int: - case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int: - case X86::SQRTSSr_Int: case X86::VSQRTSSr_Int: case X86::VSQRTSSZr_Int: - case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int: - case X86::VADDSSZrr_Intk: case X86::VADDSSZrr_Intkz: + case X86::CVTSS2SIrr_Int: + case X86::CVTSS2SI64rr_Int: + case X86::VCVTSS2SIrr_Int: + case X86::VCVTSS2SI64rr_Int: + case X86::VCVTSS2SIZrr_Int: + case X86::VCVTSS2SI64Zrr_Int: + case X86::CVTTSS2SIrr_Int: + case X86::CVTTSS2SI64rr_Int: + case X86::VCVTTSS2SIrr_Int: + case X86::VCVTTSS2SI64rr_Int: + case X86::VCVTTSS2SIZrr_Int: + case X86::VCVTTSS2SI64Zrr_Int: + case X86::VCVTSS2USIZrr_Int: + case X86::VCVTSS2USI64Zrr_Int: + case X86::VCVTTSS2USIZrr_Int: + case X86::VCVTTSS2USI64Zrr_Int: + case X86::RCPSSr_Int: + case X86::VRCPSSr_Int: + case X86::RSQRTSSr_Int: + case X86::VRSQRTSSr_Int: + case X86::ROUNDSSr_Int: + case X86::VROUNDSSr_Int: + case X86::COMISSrr_Int: + case X86::VCOMISSrr_Int: + case X86::VCOMISSZrr_Int: + case X86::UCOMISSrr_Int: + case X86::VUCOMISSrr_Int: + case X86::VUCOMISSZrr_Int: + case X86::ADDSSrr_Int: + case X86::VADDSSrr_Int: + case X86::VADDSSZrr_Int: + case X86::CMPSSrr_Int: + case X86::VCMPSSrr_Int: + case X86::VCMPSSZrr_Int: + case X86::DIVSSrr_Int: + case X86::VDIVSSrr_Int: + case X86::VDIVSSZrr_Int: + case X86::MAXSSrr_Int: + case X86::VMAXSSrr_Int: + case X86::VMAXSSZrr_Int: + case X86::MINSSrr_Int: + case X86::VMINSSrr_Int: + case X86::VMINSSZrr_Int: + case X86::MULSSrr_Int: + case X86::VMULSSrr_Int: + case X86::VMULSSZrr_Int: + case X86::SQRTSSr_Int: + case X86::VSQRTSSr_Int: + case X86::VSQRTSSZr_Int: + case X86::SUBSSrr_Int: + case X86::VSUBSSrr_Int: + case X86::VSUBSSZrr_Int: + case X86::VADDSSZrr_Intk: + case X86::VADDSSZrr_Intkz: case X86::VCMPSSZrr_Intk: - case X86::VDIVSSZrr_Intk: case X86::VDIVSSZrr_Intkz: - case X86::VMAXSSZrr_Intk: case X86::VMAXSSZrr_Intkz: - case X86::VMINSSZrr_Intk: case X86::VMINSSZrr_Intkz: - case X86::VMULSSZrr_Intk: case X86::VMULSSZrr_Intkz: - case X86::VSQRTSSZr_Intk: case X86::VSQRTSSZr_Intkz: - case X86::VSUBSSZrr_Intk: case X86::VSUBSSZrr_Intkz: - case X86::VFMADDSS4rr_Int: case X86::VFNMADDSS4rr_Int: - case X86::VFMSUBSS4rr_Int: case X86::VFNMSUBSS4rr_Int: - case X86::VFMADD132SSr_Int: case X86::VFNMADD132SSr_Int: - case X86::VFMADD213SSr_Int: case X86::VFNMADD213SSr_Int: - case X86::VFMADD231SSr_Int: case X86::VFNMADD231SSr_Int: - case X86::VFMSUB132SSr_Int: case X86::VFNMSUB132SSr_Int: - case X86::VFMSUB213SSr_Int: case X86::VFNMSUB213SSr_Int: - case X86::VFMSUB231SSr_Int: case X86::VFNMSUB231SSr_Int: - case X86::VFMADD132SSZr_Int: case X86::VFNMADD132SSZr_Int: - case X86::VFMADD213SSZr_Int: case X86::VFNMADD213SSZr_Int: - case X86::VFMADD231SSZr_Int: case X86::VFNMADD231SSZr_Int: - case X86::VFMSUB132SSZr_Int: case X86::VFNMSUB132SSZr_Int: - case X86::VFMSUB213SSZr_Int: case X86::VFNMSUB213SSZr_Int: - case X86::VFMSUB231SSZr_Int: case X86::VFNMSUB231SSZr_Int: - case X86::VFMADD132SSZr_Intk: case X86::VFNMADD132SSZr_Intk: - case X86::VFMADD213SSZr_Intk: case X86::VFNMADD213SSZr_Intk: - case X86::VFMADD231SSZr_Intk: case X86::VFNMADD231SSZr_Intk: - case X86::VFMSUB132SSZr_Intk: case X86::VFNMSUB132SSZr_Intk: - case X86::VFMSUB213SSZr_Intk: case X86::VFNMSUB213SSZr_Intk: - case X86::VFMSUB231SSZr_Intk: case X86::VFNMSUB231SSZr_Intk: - case X86::VFMADD132SSZr_Intkz: case X86::VFNMADD132SSZr_Intkz: - case X86::VFMADD213SSZr_Intkz: case X86::VFNMADD213SSZr_Intkz: - case X86::VFMADD231SSZr_Intkz: case X86::VFNMADD231SSZr_Intkz: - case X86::VFMSUB132SSZr_Intkz: case X86::VFNMSUB132SSZr_Intkz: - case X86::VFMSUB213SSZr_Intkz: case X86::VFNMSUB213SSZr_Intkz: - case X86::VFMSUB231SSZr_Intkz: case X86::VFNMSUB231SSZr_Intkz: + case X86::VDIVSSZrr_Intk: + case X86::VDIVSSZrr_Intkz: + case X86::VMAXSSZrr_Intk: + case X86::VMAXSSZrr_Intkz: + case X86::VMINSSZrr_Intk: + case X86::VMINSSZrr_Intkz: + case X86::VMULSSZrr_Intk: + case X86::VMULSSZrr_Intkz: + case X86::VSQRTSSZr_Intk: + case X86::VSQRTSSZr_Intkz: + case X86::VSUBSSZrr_Intk: + case X86::VSUBSSZrr_Intkz: + case X86::VFMADDSS4rr_Int: + case X86::VFNMADDSS4rr_Int: + case X86::VFMSUBSS4rr_Int: + case X86::VFNMSUBSS4rr_Int: + case X86::VFMADD132SSr_Int: + case X86::VFNMADD132SSr_Int: + case X86::VFMADD213SSr_Int: + case X86::VFNMADD213SSr_Int: + case X86::VFMADD231SSr_Int: + case X86::VFNMADD231SSr_Int: + case X86::VFMSUB132SSr_Int: + case X86::VFNMSUB132SSr_Int: + case X86::VFMSUB213SSr_Int: + case X86::VFNMSUB213SSr_Int: + case X86::VFMSUB231SSr_Int: + case X86::VFNMSUB231SSr_Int: + case X86::VFMADD132SSZr_Int: + case X86::VFNMADD132SSZr_Int: + case X86::VFMADD213SSZr_Int: + case X86::VFNMADD213SSZr_Int: + case X86::VFMADD231SSZr_Int: + case X86::VFNMADD231SSZr_Int: + case X86::VFMSUB132SSZr_Int: + case X86::VFNMSUB132SSZr_Int: + case X86::VFMSUB213SSZr_Int: + case X86::VFNMSUB213SSZr_Int: + case X86::VFMSUB231SSZr_Int: + case X86::VFNMSUB231SSZr_Int: + case X86::VFMADD132SSZr_Intk: + case X86::VFNMADD132SSZr_Intk: + case X86::VFMADD213SSZr_Intk: + case X86::VFNMADD213SSZr_Intk: + case X86::VFMADD231SSZr_Intk: + case X86::VFNMADD231SSZr_Intk: + case X86::VFMSUB132SSZr_Intk: + case X86::VFNMSUB132SSZr_Intk: + case X86::VFMSUB213SSZr_Intk: + case X86::VFNMSUB213SSZr_Intk: + case X86::VFMSUB231SSZr_Intk: + case X86::VFNMSUB231SSZr_Intk: + case X86::VFMADD132SSZr_Intkz: + case X86::VFNMADD132SSZr_Intkz: + case X86::VFMADD213SSZr_Intkz: + case X86::VFNMADD213SSZr_Intkz: + case X86::VFMADD231SSZr_Intkz: + case X86::VFNMADD231SSZr_Intkz: + case X86::VFMSUB132SSZr_Intkz: + case X86::VFNMSUB132SSZr_Intkz: + case X86::VFMSUB213SSZr_Intkz: + case X86::VFNMSUB213SSZr_Intkz: + case X86::VFMSUB231SSZr_Intkz: + case X86::VFNMSUB231SSZr_Intkz: case X86::VFIXUPIMMSSZrri: case X86::VFIXUPIMMSSZrrik: case X86::VFIXUPIMMSSZrrikz: @@ -6951,59 +7668,121 @@ static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI, case X86::VCVTSD2SSZrr_Int: case X86::VCVTSD2SSZrr_Intk: case X86::VCVTSD2SSZrr_Intkz: - case X86::CVTSD2SIrr_Int: case X86::CVTSD2SI64rr_Int: - case X86::VCVTSD2SIrr_Int: case X86::VCVTSD2SI64rr_Int: - case X86::VCVTSD2SIZrr_Int: case X86::VCVTSD2SI64Zrr_Int: - case X86::CVTTSD2SIrr_Int: case X86::CVTTSD2SI64rr_Int: - case X86::VCVTTSD2SIrr_Int: case X86::VCVTTSD2SI64rr_Int: - case X86::VCVTTSD2SIZrr_Int: case X86::VCVTTSD2SI64Zrr_Int: - case X86::VCVTSD2USIZrr_Int: case X86::VCVTSD2USI64Zrr_Int: - case X86::VCVTTSD2USIZrr_Int: case X86::VCVTTSD2USI64Zrr_Int: - case X86::ROUNDSDr_Int: case X86::VROUNDSDr_Int: - case X86::COMISDrr_Int: case X86::VCOMISDrr_Int: case X86::VCOMISDZrr_Int: - case X86::UCOMISDrr_Int:case X86::VUCOMISDrr_Int:case X86::VUCOMISDZrr_Int: - case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int: - case X86::CMPSDrr_Int: case X86::VCMPSDrr_Int: case X86::VCMPSDZrr_Int: - case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int: - case X86::MAXSDrr_Int: case X86::VMAXSDrr_Int: case X86::VMAXSDZrr_Int: - case X86::MINSDrr_Int: case X86::VMINSDrr_Int: case X86::VMINSDZrr_Int: - case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int: - case X86::SQRTSDr_Int: case X86::VSQRTSDr_Int: case X86::VSQRTSDZr_Int: - case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int: - case X86::VADDSDZrr_Intk: case X86::VADDSDZrr_Intkz: + case X86::CVTSD2SIrr_Int: + case X86::CVTSD2SI64rr_Int: + case X86::VCVTSD2SIrr_Int: + case X86::VCVTSD2SI64rr_Int: + case X86::VCVTSD2SIZrr_Int: + case X86::VCVTSD2SI64Zrr_Int: + case X86::CVTTSD2SIrr_Int: + case X86::CVTTSD2SI64rr_Int: + case X86::VCVTTSD2SIrr_Int: + case X86::VCVTTSD2SI64rr_Int: + case X86::VCVTTSD2SIZrr_Int: + case X86::VCVTTSD2SI64Zrr_Int: + case X86::VCVTSD2USIZrr_Int: + case X86::VCVTSD2USI64Zrr_Int: + case X86::VCVTTSD2USIZrr_Int: + case X86::VCVTTSD2USI64Zrr_Int: + case X86::ROUNDSDr_Int: + case X86::VROUNDSDr_Int: + case X86::COMISDrr_Int: + case X86::VCOMISDrr_Int: + case X86::VCOMISDZrr_Int: + case X86::UCOMISDrr_Int: + case X86::VUCOMISDrr_Int: + case X86::VUCOMISDZrr_Int: + case X86::ADDSDrr_Int: + case X86::VADDSDrr_Int: + case X86::VADDSDZrr_Int: + case X86::CMPSDrr_Int: + case X86::VCMPSDrr_Int: + case X86::VCMPSDZrr_Int: + case X86::DIVSDrr_Int: + case X86::VDIVSDrr_Int: + case X86::VDIVSDZrr_Int: + case X86::MAXSDrr_Int: + case X86::VMAXSDrr_Int: + case X86::VMAXSDZrr_Int: + case X86::MINSDrr_Int: + case X86::VMINSDrr_Int: + case X86::VMINSDZrr_Int: + case X86::MULSDrr_Int: + case X86::VMULSDrr_Int: + case X86::VMULSDZrr_Int: + case X86::SQRTSDr_Int: + case X86::VSQRTSDr_Int: + case X86::VSQRTSDZr_Int: + case X86::SUBSDrr_Int: + case X86::VSUBSDrr_Int: + case X86::VSUBSDZrr_Int: + case X86::VADDSDZrr_Intk: + case X86::VADDSDZrr_Intkz: case X86::VCMPSDZrr_Intk: - case X86::VDIVSDZrr_Intk: case X86::VDIVSDZrr_Intkz: - case X86::VMAXSDZrr_Intk: case X86::VMAXSDZrr_Intkz: - case X86::VMINSDZrr_Intk: case X86::VMINSDZrr_Intkz: - case X86::VMULSDZrr_Intk: case X86::VMULSDZrr_Intkz: - case X86::VSQRTSDZr_Intk: case X86::VSQRTSDZr_Intkz: - case X86::VSUBSDZrr_Intk: case X86::VSUBSDZrr_Intkz: - case X86::VFMADDSD4rr_Int: case X86::VFNMADDSD4rr_Int: - case X86::VFMSUBSD4rr_Int: case X86::VFNMSUBSD4rr_Int: - case X86::VFMADD132SDr_Int: case X86::VFNMADD132SDr_Int: - case X86::VFMADD213SDr_Int: case X86::VFNMADD213SDr_Int: - case X86::VFMADD231SDr_Int: case X86::VFNMADD231SDr_Int: - case X86::VFMSUB132SDr_Int: case X86::VFNMSUB132SDr_Int: - case X86::VFMSUB213SDr_Int: case X86::VFNMSUB213SDr_Int: - case X86::VFMSUB231SDr_Int: case X86::VFNMSUB231SDr_Int: - case X86::VFMADD132SDZr_Int: case X86::VFNMADD132SDZr_Int: - case X86::VFMADD213SDZr_Int: case X86::VFNMADD213SDZr_Int: - case X86::VFMADD231SDZr_Int: case X86::VFNMADD231SDZr_Int: - case X86::VFMSUB132SDZr_Int: case X86::VFNMSUB132SDZr_Int: - case X86::VFMSUB213SDZr_Int: case X86::VFNMSUB213SDZr_Int: - case X86::VFMSUB231SDZr_Int: case X86::VFNMSUB231SDZr_Int: - case X86::VFMADD132SDZr_Intk: case X86::VFNMADD132SDZr_Intk: - case X86::VFMADD213SDZr_Intk: case X86::VFNMADD213SDZr_Intk: - case X86::VFMADD231SDZr_Intk: case X86::VFNMADD231SDZr_Intk: - case X86::VFMSUB132SDZr_Intk: case X86::VFNMSUB132SDZr_Intk: - case X86::VFMSUB213SDZr_Intk: case X86::VFNMSUB213SDZr_Intk: - case X86::VFMSUB231SDZr_Intk: case X86::VFNMSUB231SDZr_Intk: - case X86::VFMADD132SDZr_Intkz: case X86::VFNMADD132SDZr_Intkz: - case X86::VFMADD213SDZr_Intkz: case X86::VFNMADD213SDZr_Intkz: - case X86::VFMADD231SDZr_Intkz: case X86::VFNMADD231SDZr_Intkz: - case X86::VFMSUB132SDZr_Intkz: case X86::VFNMSUB132SDZr_Intkz: - case X86::VFMSUB213SDZr_Intkz: case X86::VFNMSUB213SDZr_Intkz: - case X86::VFMSUB231SDZr_Intkz: case X86::VFNMSUB231SDZr_Intkz: + case X86::VDIVSDZrr_Intk: + case X86::VDIVSDZrr_Intkz: + case X86::VMAXSDZrr_Intk: + case X86::VMAXSDZrr_Intkz: + case X86::VMINSDZrr_Intk: + case X86::VMINSDZrr_Intkz: + case X86::VMULSDZrr_Intk: + case X86::VMULSDZrr_Intkz: + case X86::VSQRTSDZr_Intk: + case X86::VSQRTSDZr_Intkz: + case X86::VSUBSDZrr_Intk: + case X86::VSUBSDZrr_Intkz: + case X86::VFMADDSD4rr_Int: + case X86::VFNMADDSD4rr_Int: + case X86::VFMSUBSD4rr_Int: + case X86::VFNMSUBSD4rr_Int: + case X86::VFMADD132SDr_Int: + case X86::VFNMADD132SDr_Int: + case X86::VFMADD213SDr_Int: + case X86::VFNMADD213SDr_Int: + case X86::VFMADD231SDr_Int: + case X86::VFNMADD231SDr_Int: + case X86::VFMSUB132SDr_Int: + case X86::VFNMSUB132SDr_Int: + case X86::VFMSUB213SDr_Int: + case X86::VFNMSUB213SDr_Int: + case X86::VFMSUB231SDr_Int: + case X86::VFNMSUB231SDr_Int: + case X86::VFMADD132SDZr_Int: + case X86::VFNMADD132SDZr_Int: + case X86::VFMADD213SDZr_Int: + case X86::VFNMADD213SDZr_Int: + case X86::VFMADD231SDZr_Int: + case X86::VFNMADD231SDZr_Int: + case X86::VFMSUB132SDZr_Int: + case X86::VFNMSUB132SDZr_Int: + case X86::VFMSUB213SDZr_Int: + case X86::VFNMSUB213SDZr_Int: + case X86::VFMSUB231SDZr_Int: + case X86::VFNMSUB231SDZr_Int: + case X86::VFMADD132SDZr_Intk: + case X86::VFNMADD132SDZr_Intk: + case X86::VFMADD213SDZr_Intk: + case X86::VFNMADD213SDZr_Intk: + case X86::VFMADD231SDZr_Intk: + case X86::VFNMADD231SDZr_Intk: + case X86::VFMSUB132SDZr_Intk: + case X86::VFNMSUB132SDZr_Intk: + case X86::VFMSUB213SDZr_Intk: + case X86::VFNMSUB213SDZr_Intk: + case X86::VFMSUB231SDZr_Intk: + case X86::VFNMSUB231SDZr_Intk: + case X86::VFMADD132SDZr_Intkz: + case X86::VFNMADD132SDZr_Intkz: + case X86::VFMADD213SDZr_Intkz: + case X86::VFNMADD213SDZr_Intkz: + case X86::VFMADD231SDZr_Intkz: + case X86::VFNMADD231SDZr_Intkz: + case X86::VFMSUB132SDZr_Intkz: + case X86::VFNMSUB132SDZr_Intkz: + case X86::VFMSUB213SDZr_Intkz: + case X86::VFNMSUB213SDZr_Intkz: + case X86::VFMSUB231SDZr_Intkz: + case X86::VFNMSUB231SDZr_Intkz: case X86::VFIXUPIMMSDZrri: case X86::VFIXUPIMMSDZrrik: case X86::VFIXUPIMMSDZrrikz: @@ -7057,31 +7836,55 @@ static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI, case X86::VMINSHZrr_Int: case X86::VMULSHZrr_Int: case X86::VSUBSHZrr_Int: - case X86::VADDSHZrr_Intk: case X86::VADDSHZrr_Intkz: + case X86::VADDSHZrr_Intk: + case X86::VADDSHZrr_Intkz: case X86::VCMPSHZrr_Intk: - case X86::VDIVSHZrr_Intk: case X86::VDIVSHZrr_Intkz: - case X86::VMAXSHZrr_Intk: case X86::VMAXSHZrr_Intkz: - case X86::VMINSHZrr_Intk: case X86::VMINSHZrr_Intkz: - case X86::VMULSHZrr_Intk: case X86::VMULSHZrr_Intkz: - case X86::VSUBSHZrr_Intk: case X86::VSUBSHZrr_Intkz: - case X86::VFMADD132SHZr_Int: case X86::VFNMADD132SHZr_Int: - case X86::VFMADD213SHZr_Int: case X86::VFNMADD213SHZr_Int: - case X86::VFMADD231SHZr_Int: case X86::VFNMADD231SHZr_Int: - case X86::VFMSUB132SHZr_Int: case X86::VFNMSUB132SHZr_Int: - case X86::VFMSUB213SHZr_Int: case X86::VFNMSUB213SHZr_Int: - case X86::VFMSUB231SHZr_Int: case X86::VFNMSUB231SHZr_Int: - case X86::VFMADD132SHZr_Intk: case X86::VFNMADD132SHZr_Intk: - case X86::VFMADD213SHZr_Intk: case X86::VFNMADD213SHZr_Intk: - case X86::VFMADD231SHZr_Intk: case X86::VFNMADD231SHZr_Intk: - case X86::VFMSUB132SHZr_Intk: case X86::VFNMSUB132SHZr_Intk: - case X86::VFMSUB213SHZr_Intk: case X86::VFNMSUB213SHZr_Intk: - case X86::VFMSUB231SHZr_Intk: case X86::VFNMSUB231SHZr_Intk: - case X86::VFMADD132SHZr_Intkz: case X86::VFNMADD132SHZr_Intkz: - case X86::VFMADD213SHZr_Intkz: case X86::VFNMADD213SHZr_Intkz: - case X86::VFMADD231SHZr_Intkz: case X86::VFNMADD231SHZr_Intkz: - case X86::VFMSUB132SHZr_Intkz: case X86::VFNMSUB132SHZr_Intkz: - case X86::VFMSUB213SHZr_Intkz: case X86::VFNMSUB213SHZr_Intkz: - case X86::VFMSUB231SHZr_Intkz: case X86::VFNMSUB231SHZr_Intkz: + case X86::VDIVSHZrr_Intk: + case X86::VDIVSHZrr_Intkz: + case X86::VMAXSHZrr_Intk: + case X86::VMAXSHZrr_Intkz: + case X86::VMINSHZrr_Intk: + case X86::VMINSHZrr_Intkz: + case X86::VMULSHZrr_Intk: + case X86::VMULSHZrr_Intkz: + case X86::VSUBSHZrr_Intk: + case X86::VSUBSHZrr_Intkz: + case X86::VFMADD132SHZr_Int: + case X86::VFNMADD132SHZr_Int: + case X86::VFMADD213SHZr_Int: + case X86::VFNMADD213SHZr_Int: + case X86::VFMADD231SHZr_Int: + case X86::VFNMADD231SHZr_Int: + case X86::VFMSUB132SHZr_Int: + case X86::VFNMSUB132SHZr_Int: + case X86::VFMSUB213SHZr_Int: + case X86::VFNMSUB213SHZr_Int: + case X86::VFMSUB231SHZr_Int: + case X86::VFNMSUB231SHZr_Int: + case X86::VFMADD132SHZr_Intk: + case X86::VFNMADD132SHZr_Intk: + case X86::VFMADD213SHZr_Intk: + case X86::VFNMADD213SHZr_Intk: + case X86::VFMADD231SHZr_Intk: + case X86::VFNMADD231SHZr_Intk: + case X86::VFMSUB132SHZr_Intk: + case X86::VFNMSUB132SHZr_Intk: + case X86::VFMSUB213SHZr_Intk: + case X86::VFNMSUB213SHZr_Intk: + case X86::VFMSUB231SHZr_Intk: + case X86::VFNMSUB231SHZr_Intk: + case X86::VFMADD132SHZr_Intkz: + case X86::VFNMADD132SHZr_Intkz: + case X86::VFMADD213SHZr_Intkz: + case X86::VFNMADD213SHZr_Intkz: + case X86::VFMADD231SHZr_Intkz: + case X86::VFNMADD231SHZr_Intkz: + case X86::VFMSUB132SHZr_Intkz: + case X86::VFNMSUB132SHZr_Intkz: + case X86::VFMSUB213SHZr_Intkz: + case X86::VFNMSUB213SHZr_Intkz: + case X86::VFMSUB231SHZr_Intkz: + case X86::VFNMSUB231SHZr_Intkz: return false; default: return true; @@ -7113,11 +7916,12 @@ MachineInstr *X86InstrInfo::foldMemoryOperandImpl( } // Check switch flag - if (NoFusing) return nullptr; + if (NoFusing) + return nullptr; // Avoid partial and undef register update stalls unless optimizing for size. if (!MF.getFunction().hasOptSize() && - (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) || + (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/ true) || shouldPreventUndefRegUpdateMemFold(MF, MI))) return nullptr; @@ -7163,11 +7967,20 @@ MachineInstr *X86InstrInfo::foldMemoryOperandImpl( if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { unsigned NewOpc = 0; switch (MI.getOpcode()) { - default: return nullptr; - case X86::TEST8rr: NewOpc = X86::CMP8ri; break; - case X86::TEST16rr: NewOpc = X86::CMP16ri; break; - case X86::TEST32rr: NewOpc = X86::CMP32ri; break; - case X86::TEST64rr: NewOpc = X86::CMP64ri32; break; + default: + return nullptr; + case X86::TEST8rr: + NewOpc = X86::CMP8ri; + break; + case X86::TEST16rr: + NewOpc = X86::CMP16ri; + break; + case X86::TEST32rr: + NewOpc = X86::CMP32ri; + break; + case X86::TEST64rr: + NewOpc = X86::CMP64ri32; + break; } // Change to CMPXXri r, 0 first. MI.setDesc(get(NewOpc)); @@ -7180,7 +7993,7 @@ MachineInstr *X86InstrInfo::foldMemoryOperandImpl( if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg()) return nullptr; - SmallVector MOs; + SmallVector MOs; switch (LoadMI.getOpcode()) { case X86::MMX_SET0: case X86::V_SET0: @@ -7248,11 +8061,11 @@ MachineInstr *X86InstrInfo::foldMemoryOperandImpl( Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 4); - bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES || - Opc == X86::AVX512_512_SETALLONES || - Opc == X86::AVX1_SETALLONES); - const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) : - Constant::getNullValue(Ty); + bool IsAllOnes = + (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES || + Opc == X86::AVX512_512_SETALLONES || Opc == X86::AVX1_SETALLONES); + const Constant *C = + IsAllOnes ? Constant::getAllOnesValue(Ty) : Constant::getNullValue(Ty); unsigned CPI = MCP.getConstantPoolIndex(C, Alignment); // Create operands to load from the constant pool entry. @@ -7328,37 +8141,54 @@ static unsigned getBroadcastOpcode(const X86FoldTableEntry *I, "Can't broadcast less than 64 bytes without AVX512VL!"); switch (I->Flags & TB_BCAST_MASK) { - default: llvm_unreachable("Unexpected broadcast type!"); + default: + llvm_unreachable("Unexpected broadcast type!"); case TB_BCAST_D: switch (SpillSize) { - default: llvm_unreachable("Unknown spill size"); - case 16: return X86::VPBROADCASTDZ128rm; - case 32: return X86::VPBROADCASTDZ256rm; - case 64: return X86::VPBROADCASTDZrm; + default: + llvm_unreachable("Unknown spill size"); + case 16: + return X86::VPBROADCASTDZ128rm; + case 32: + return X86::VPBROADCASTDZ256rm; + case 64: + return X86::VPBROADCASTDZrm; } break; case TB_BCAST_Q: switch (SpillSize) { - default: llvm_unreachable("Unknown spill size"); - case 16: return X86::VPBROADCASTQZ128rm; - case 32: return X86::VPBROADCASTQZ256rm; - case 64: return X86::VPBROADCASTQZrm; + default: + llvm_unreachable("Unknown spill size"); + case 16: + return X86::VPBROADCASTQZ128rm; + case 32: + return X86::VPBROADCASTQZ256rm; + case 64: + return X86::VPBROADCASTQZrm; } break; case TB_BCAST_SS: switch (SpillSize) { - default: llvm_unreachable("Unknown spill size"); - case 16: return X86::VBROADCASTSSZ128rm; - case 32: return X86::VBROADCASTSSZ256rm; - case 64: return X86::VBROADCASTSSZrm; + default: + llvm_unreachable("Unknown spill size"); + case 16: + return X86::VBROADCASTSSZ128rm; + case 32: + return X86::VBROADCASTSSZ256rm; + case 64: + return X86::VBROADCASTSSZrm; } break; case TB_BCAST_SD: switch (SpillSize) { - default: llvm_unreachable("Unknown spill size"); - case 16: return X86::VMOVDDUPZ128rm; - case 32: return X86::VBROADCASTSDZ256rm; - case 64: return X86::VBROADCASTSDZrm; + default: + llvm_unreachable("Unknown spill size"); + case 16: + return X86::VMOVDDUPZ128rm; + case 32: + return X86::VBROADCASTSDZ256rm; + case 64: + return X86::VBROADCASTSDZrm; } break; } @@ -7394,9 +8224,9 @@ bool X86InstrInfo::unfoldMemoryOperand( // performance. return false; SmallVector AddrOps; - SmallVector BeforeOps; - SmallVector AfterOps; - SmallVector ImpOps; + SmallVector BeforeOps; + SmallVector AfterOps; + SmallVector ImpOps; for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { MachineOperand &Op = MI.getOperand(i); if (i >= Index && i < Index + X86::AddrNumOperands) @@ -7452,16 +8282,16 @@ bool X86InstrInfo::unfoldMemoryOperand( for (MachineOperand &AfterOp : AfterOps) MIB.add(AfterOp); for (MachineOperand &ImpOp : ImpOps) { - MIB.addReg(ImpOp.getReg(), - getDefRegState(ImpOp.isDef()) | - RegState::Implicit | - getKillRegState(ImpOp.isKill()) | - getDeadRegState(ImpOp.isDead()) | - getUndefRegState(ImpOp.isUndef())); + MIB.addReg(ImpOp.getReg(), getDefRegState(ImpOp.isDef()) | + RegState::Implicit | + getKillRegState(ImpOp.isKill()) | + getDeadRegState(ImpOp.isDead()) | + getUndefRegState(ImpOp.isUndef())); } // Change CMP32ri r, 0 back to TEST32rr r, r, etc. switch (DataMI->getOpcode()) { - default: break; + default: + break; case X86::CMP64ri32: case X86::CMP32ri: case X86::CMP16ri: @@ -7471,11 +8301,20 @@ bool X86InstrInfo::unfoldMemoryOperand( if (MO1.isImm() && MO1.getImm() == 0) { unsigned NewOpc; switch (DataMI->getOpcode()) { - default: llvm_unreachable("Unreachable!"); - case X86::CMP64ri32: NewOpc = X86::TEST64rr; break; - case X86::CMP32ri: NewOpc = X86::TEST32rr; break; - case X86::CMP16ri: NewOpc = X86::TEST16rr; break; - case X86::CMP8ri: NewOpc = X86::TEST8rr; break; + default: + llvm_unreachable("Unreachable!"); + case X86::CMP64ri32: + NewOpc = X86::TEST64rr; + break; + case X86::CMP32ri: + NewOpc = X86::TEST32rr; + break; + case X86::CMP16ri: + NewOpc = X86::TEST16rr; + break; + case X86::CMP8ri: + NewOpc = X86::TEST8rr; + break; } DataMI->setDesc(get(NewOpc)); MO1.ChangeToRegister(MO0.getReg(), false); @@ -7503,9 +8342,8 @@ bool X86InstrInfo::unfoldMemoryOperand( return true; } -bool -X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, - SmallVectorImpl &NewNodes) const { +bool X86InstrInfo::unfoldMemoryOperand( + SelectionDAG &DAG, SDNode *N, SmallVectorImpl &NewNodes) const { if (!N->isMachineOpcode()) return false; @@ -7527,16 +8365,16 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, std::vector AfterOps; SDLoc dl(N); unsigned NumOps = N->getNumOperands(); - for (unsigned i = 0; i != NumOps-1; ++i) { + for (unsigned i = 0; i != NumOps - 1; ++i) { SDValue Op = N->getOperand(i); - if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands) + if (i >= Index - NumDefs && i < Index - NumDefs + X86::AddrNumOperands) AddrOps.push_back(Op); - else if (i < Index-NumDefs) + else if (i < Index - NumDefs) BeforeOps.push_back(Op); - else if (i > Index-NumDefs) + else if (i > Index - NumDefs) AfterOps.push_back(Op); } - SDValue Chain = N->getOperand(NumOps-1); + SDValue Chain = N->getOperand(NumOps - 1); AddrOps.push_back(Chain); // Emit the load instruction. @@ -7584,23 +8422,33 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, llvm::append_range(BeforeOps, AfterOps); // Change CMP32ri r, 0 back to TEST32rr r, r, etc. switch (Opc) { - default: break; - case X86::CMP64ri32: - case X86::CMP32ri: - case X86::CMP16ri: - case X86::CMP8ri: - if (isNullConstant(BeforeOps[1])) { - switch (Opc) { - default: llvm_unreachable("Unreachable!"); - case X86::CMP64ri32: Opc = X86::TEST64rr; break; - case X86::CMP32ri: Opc = X86::TEST32rr; break; - case X86::CMP16ri: Opc = X86::TEST16rr; break; - case X86::CMP8ri: Opc = X86::TEST8rr; break; - } - BeforeOps[1] = BeforeOps[0]; + default: + break; + case X86::CMP64ri32: + case X86::CMP32ri: + case X86::CMP16ri: + case X86::CMP8ri: + if (isNullConstant(BeforeOps[1])) { + switch (Opc) { + default: + llvm_unreachable("Unreachable!"); + case X86::CMP64ri32: + Opc = X86::TEST64rr; + break; + case X86::CMP32ri: + Opc = X86::TEST32rr; + break; + case X86::CMP16ri: + Opc = X86::TEST16rr; + break; + case X86::CMP8ri: + Opc = X86::TEST8rr; + break; } + BeforeOps[1] = BeforeOps[0]; + } } - SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps); + SDNode *NewNode = DAG.getMachineNode(Opc, dl, VTs, BeforeOps); NewNodes.push_back(NewNode); // Emit the store instruction. @@ -7629,9 +8477,10 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, return true; } -unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, - bool UnfoldLoad, bool UnfoldStore, - unsigned *LoadRegIndex) const { +unsigned +X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, + bool UnfoldStore, + unsigned *LoadRegIndex) const { const X86FoldTableEntry *I = lookupUnfoldTable(Opc); if (I == nullptr) return 0; @@ -7646,9 +8495,9 @@ unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, return I->DstOp; } -bool -X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, - int64_t &Offset1, int64_t &Offset2) const { +bool X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, + int64_t &Offset1, + int64_t &Offset2) const { if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) return false; @@ -7782,10 +8631,11 @@ bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, unsigned Opc1 = Load1->getMachineOpcode(); unsigned Opc2 = Load2->getMachineOpcode(); if (Opc1 != Opc2) - return false; // FIXME: overly conservative? + return false; // FIXME: overly conservative? switch (Opc1) { - default: break; + default: + break; case X86::LD_Fp32m: case X86::LD_Fp64m: case X86::LD_Fp80m: @@ -7833,16 +8683,16 @@ bool X86InstrInfo::isSchedulingBoundary(const MachineInstr &MI, return TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF); } -bool X86InstrInfo:: -reverseBranchCondition(SmallVectorImpl &Cond) const { +bool X86InstrInfo::reverseBranchCondition( + SmallVectorImpl &Cond) const { assert(Cond.size() == 1 && "Invalid X86 branch condition!"); X86::CondCode CC = static_cast(Cond[0].getImm()); Cond[0].setImm(GetOppositeBranchCondition(CC)); return false; } -bool X86InstrInfo:: -isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { +bool X86InstrInfo::isSafeToMoveRegClassDefs( + const TargetRegisterClass *RC) const { // FIXME: Return false for x87 stack register classes for now. We can't // allow any loads of these registers before FpGet_ST0_80. return !(RC == &X86::CCRRegClass || RC == &X86::DFCCRRegClass || @@ -7876,515 +8726,13 @@ unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const { return GlobalBaseReg; } -// These are the replaceable SSE instructions. Some of these have Int variants -// that we don't include here. We don't want to replace instructions selected -// by intrinsics. -static const uint16_t ReplaceableInstrs[][3] = { - //PackedSingle PackedDouble PackedInt - { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr }, - { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm }, - { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr }, - { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr }, - { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm }, - { X86::MOVLPSmr, X86::MOVLPDmr, X86::MOVPQI2QImr }, - { X86::MOVSDmr, X86::MOVSDmr, X86::MOVPQI2QImr }, - { X86::MOVSSmr, X86::MOVSSmr, X86::MOVPDI2DImr }, - { X86::MOVSDrm, X86::MOVSDrm, X86::MOVQI2PQIrm }, - { X86::MOVSDrm_alt,X86::MOVSDrm_alt,X86::MOVQI2PQIrm }, - { X86::MOVSSrm, X86::MOVSSrm, X86::MOVDI2PDIrm }, - { X86::MOVSSrm_alt,X86::MOVSSrm_alt,X86::MOVDI2PDIrm }, - { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr }, - { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm }, - { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr }, - { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm }, - { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr }, - { X86::ORPSrm, X86::ORPDrm, X86::PORrm }, - { X86::ORPSrr, X86::ORPDrr, X86::PORrr }, - { X86::XORPSrm, X86::XORPDrm, X86::PXORrm }, - { X86::XORPSrr, X86::XORPDrr, X86::PXORrr }, - { X86::UNPCKLPDrm, X86::UNPCKLPDrm, X86::PUNPCKLQDQrm }, - { X86::MOVLHPSrr, X86::UNPCKLPDrr, X86::PUNPCKLQDQrr }, - { X86::UNPCKHPDrm, X86::UNPCKHPDrm, X86::PUNPCKHQDQrm }, - { X86::UNPCKHPDrr, X86::UNPCKHPDrr, X86::PUNPCKHQDQrr }, - { X86::UNPCKLPSrm, X86::UNPCKLPSrm, X86::PUNPCKLDQrm }, - { X86::UNPCKLPSrr, X86::UNPCKLPSrr, X86::PUNPCKLDQrr }, - { X86::UNPCKHPSrm, X86::UNPCKHPSrm, X86::PUNPCKHDQrm }, - { X86::UNPCKHPSrr, X86::UNPCKHPSrr, X86::PUNPCKHDQrr }, - { X86::EXTRACTPSmr, X86::EXTRACTPSmr, X86::PEXTRDmr }, - { X86::EXTRACTPSrr, X86::EXTRACTPSrr, X86::PEXTRDrr }, - // AVX 128-bit support - { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr }, - { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm }, - { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr }, - { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr }, - { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm }, - { X86::VMOVLPSmr, X86::VMOVLPDmr, X86::VMOVPQI2QImr }, - { X86::VMOVSDmr, X86::VMOVSDmr, X86::VMOVPQI2QImr }, - { X86::VMOVSSmr, X86::VMOVSSmr, X86::VMOVPDI2DImr }, - { X86::VMOVSDrm, X86::VMOVSDrm, X86::VMOVQI2PQIrm }, - { X86::VMOVSDrm_alt,X86::VMOVSDrm_alt,X86::VMOVQI2PQIrm }, - { X86::VMOVSSrm, X86::VMOVSSrm, X86::VMOVDI2PDIrm }, - { X86::VMOVSSrm_alt,X86::VMOVSSrm_alt,X86::VMOVDI2PDIrm }, - { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr }, - { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm }, - { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr }, - { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm }, - { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr }, - { X86::VORPSrm, X86::VORPDrm, X86::VPORrm }, - { X86::VORPSrr, X86::VORPDrr, X86::VPORrr }, - { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm }, - { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr }, - { X86::VUNPCKLPDrm, X86::VUNPCKLPDrm, X86::VPUNPCKLQDQrm }, - { X86::VMOVLHPSrr, X86::VUNPCKLPDrr, X86::VPUNPCKLQDQrr }, - { X86::VUNPCKHPDrm, X86::VUNPCKHPDrm, X86::VPUNPCKHQDQrm }, - { X86::VUNPCKHPDrr, X86::VUNPCKHPDrr, X86::VPUNPCKHQDQrr }, - { X86::VUNPCKLPSrm, X86::VUNPCKLPSrm, X86::VPUNPCKLDQrm }, - { X86::VUNPCKLPSrr, X86::VUNPCKLPSrr, X86::VPUNPCKLDQrr }, - { X86::VUNPCKHPSrm, X86::VUNPCKHPSrm, X86::VPUNPCKHDQrm }, - { X86::VUNPCKHPSrr, X86::VUNPCKHPSrr, X86::VPUNPCKHDQrr }, - { X86::VEXTRACTPSmr, X86::VEXTRACTPSmr, X86::VPEXTRDmr }, - { X86::VEXTRACTPSrr, X86::VEXTRACTPSrr, X86::VPEXTRDrr }, - // AVX 256-bit support - { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr }, - { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm }, - { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr }, - { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr }, - { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm }, - { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr }, - { X86::VPERMPSYrm, X86::VPERMPSYrm, X86::VPERMDYrm }, - { X86::VPERMPSYrr, X86::VPERMPSYrr, X86::VPERMDYrr }, - { X86::VPERMPDYmi, X86::VPERMPDYmi, X86::VPERMQYmi }, - { X86::VPERMPDYri, X86::VPERMPDYri, X86::VPERMQYri }, - // AVX512 support - { X86::VMOVLPSZ128mr, X86::VMOVLPDZ128mr, X86::VMOVPQI2QIZmr }, - { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr }, - { X86::VMOVNTPSZ256mr, X86::VMOVNTPDZ256mr, X86::VMOVNTDQZ256mr }, - { X86::VMOVNTPSZmr, X86::VMOVNTPDZmr, X86::VMOVNTDQZmr }, - { X86::VMOVSDZmr, X86::VMOVSDZmr, X86::VMOVPQI2QIZmr }, - { X86::VMOVSSZmr, X86::VMOVSSZmr, X86::VMOVPDI2DIZmr }, - { X86::VMOVSDZrm, X86::VMOVSDZrm, X86::VMOVQI2PQIZrm }, - { X86::VMOVSDZrm_alt, X86::VMOVSDZrm_alt, X86::VMOVQI2PQIZrm }, - { X86::VMOVSSZrm, X86::VMOVSSZrm, X86::VMOVDI2PDIZrm }, - { X86::VMOVSSZrm_alt, X86::VMOVSSZrm_alt, X86::VMOVDI2PDIZrm }, - { X86::VBROADCASTSSZ128rr,X86::VBROADCASTSSZ128rr,X86::VPBROADCASTDZ128rr }, - { X86::VBROADCASTSSZ128rm,X86::VBROADCASTSSZ128rm,X86::VPBROADCASTDZ128rm }, - { X86::VBROADCASTSSZ256rr,X86::VBROADCASTSSZ256rr,X86::VPBROADCASTDZ256rr }, - { X86::VBROADCASTSSZ256rm,X86::VBROADCASTSSZ256rm,X86::VPBROADCASTDZ256rm }, - { X86::VBROADCASTSSZrr, X86::VBROADCASTSSZrr, X86::VPBROADCASTDZrr }, - { X86::VBROADCASTSSZrm, X86::VBROADCASTSSZrm, X86::VPBROADCASTDZrm }, - { X86::VMOVDDUPZ128rr, X86::VMOVDDUPZ128rr, X86::VPBROADCASTQZ128rr }, - { X86::VMOVDDUPZ128rm, X86::VMOVDDUPZ128rm, X86::VPBROADCASTQZ128rm }, - { X86::VBROADCASTSDZ256rr,X86::VBROADCASTSDZ256rr,X86::VPBROADCASTQZ256rr }, - { X86::VBROADCASTSDZ256rm,X86::VBROADCASTSDZ256rm,X86::VPBROADCASTQZ256rm }, - { X86::VBROADCASTSDZrr, X86::VBROADCASTSDZrr, X86::VPBROADCASTQZrr }, - { X86::VBROADCASTSDZrm, X86::VBROADCASTSDZrm, X86::VPBROADCASTQZrm }, - { X86::VINSERTF32x4Zrr, X86::VINSERTF32x4Zrr, X86::VINSERTI32x4Zrr }, - { X86::VINSERTF32x4Zrm, X86::VINSERTF32x4Zrm, X86::VINSERTI32x4Zrm }, - { X86::VINSERTF32x8Zrr, X86::VINSERTF32x8Zrr, X86::VINSERTI32x8Zrr }, - { X86::VINSERTF32x8Zrm, X86::VINSERTF32x8Zrm, X86::VINSERTI32x8Zrm }, - { X86::VINSERTF64x2Zrr, X86::VINSERTF64x2Zrr, X86::VINSERTI64x2Zrr }, - { X86::VINSERTF64x2Zrm, X86::VINSERTF64x2Zrm, X86::VINSERTI64x2Zrm }, - { X86::VINSERTF64x4Zrr, X86::VINSERTF64x4Zrr, X86::VINSERTI64x4Zrr }, - { X86::VINSERTF64x4Zrm, X86::VINSERTF64x4Zrm, X86::VINSERTI64x4Zrm }, - { X86::VINSERTF32x4Z256rr,X86::VINSERTF32x4Z256rr,X86::VINSERTI32x4Z256rr }, - { X86::VINSERTF32x4Z256rm,X86::VINSERTF32x4Z256rm,X86::VINSERTI32x4Z256rm }, - { X86::VINSERTF64x2Z256rr,X86::VINSERTF64x2Z256rr,X86::VINSERTI64x2Z256rr }, - { X86::VINSERTF64x2Z256rm,X86::VINSERTF64x2Z256rm,X86::VINSERTI64x2Z256rm }, - { X86::VEXTRACTF32x4Zrr, X86::VEXTRACTF32x4Zrr, X86::VEXTRACTI32x4Zrr }, - { X86::VEXTRACTF32x4Zmr, X86::VEXTRACTF32x4Zmr, X86::VEXTRACTI32x4Zmr }, - { X86::VEXTRACTF32x8Zrr, X86::VEXTRACTF32x8Zrr, X86::VEXTRACTI32x8Zrr }, - { X86::VEXTRACTF32x8Zmr, X86::VEXTRACTF32x8Zmr, X86::VEXTRACTI32x8Zmr }, - { X86::VEXTRACTF64x2Zrr, X86::VEXTRACTF64x2Zrr, X86::VEXTRACTI64x2Zrr }, - { X86::VEXTRACTF64x2Zmr, X86::VEXTRACTF64x2Zmr, X86::VEXTRACTI64x2Zmr }, - { X86::VEXTRACTF64x4Zrr, X86::VEXTRACTF64x4Zrr, X86::VEXTRACTI64x4Zrr }, - { X86::VEXTRACTF64x4Zmr, X86::VEXTRACTF64x4Zmr, X86::VEXTRACTI64x4Zmr }, - { X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTI32x4Z256rr }, - { X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTI32x4Z256mr }, - { X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTI64x2Z256rr }, - { X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTI64x2Z256mr }, - { X86::VPERMILPSmi, X86::VPERMILPSmi, X86::VPSHUFDmi }, - { X86::VPERMILPSri, X86::VPERMILPSri, X86::VPSHUFDri }, - { X86::VPERMILPSZ128mi, X86::VPERMILPSZ128mi, X86::VPSHUFDZ128mi }, - { X86::VPERMILPSZ128ri, X86::VPERMILPSZ128ri, X86::VPSHUFDZ128ri }, - { X86::VPERMILPSZ256mi, X86::VPERMILPSZ256mi, X86::VPSHUFDZ256mi }, - { X86::VPERMILPSZ256ri, X86::VPERMILPSZ256ri, X86::VPSHUFDZ256ri }, - { X86::VPERMILPSZmi, X86::VPERMILPSZmi, X86::VPSHUFDZmi }, - { X86::VPERMILPSZri, X86::VPERMILPSZri, X86::VPSHUFDZri }, - { X86::VPERMPSZ256rm, X86::VPERMPSZ256rm, X86::VPERMDZ256rm }, - { X86::VPERMPSZ256rr, X86::VPERMPSZ256rr, X86::VPERMDZ256rr }, - { X86::VPERMPDZ256mi, X86::VPERMPDZ256mi, X86::VPERMQZ256mi }, - { X86::VPERMPDZ256ri, X86::VPERMPDZ256ri, X86::VPERMQZ256ri }, - { X86::VPERMPDZ256rm, X86::VPERMPDZ256rm, X86::VPERMQZ256rm }, - { X86::VPERMPDZ256rr, X86::VPERMPDZ256rr, X86::VPERMQZ256rr }, - { X86::VPERMPSZrm, X86::VPERMPSZrm, X86::VPERMDZrm }, - { X86::VPERMPSZrr, X86::VPERMPSZrr, X86::VPERMDZrr }, - { X86::VPERMPDZmi, X86::VPERMPDZmi, X86::VPERMQZmi }, - { X86::VPERMPDZri, X86::VPERMPDZri, X86::VPERMQZri }, - { X86::VPERMPDZrm, X86::VPERMPDZrm, X86::VPERMQZrm }, - { X86::VPERMPDZrr, X86::VPERMPDZrr, X86::VPERMQZrr }, - { X86::VUNPCKLPDZ256rm, X86::VUNPCKLPDZ256rm, X86::VPUNPCKLQDQZ256rm }, - { X86::VUNPCKLPDZ256rr, X86::VUNPCKLPDZ256rr, X86::VPUNPCKLQDQZ256rr }, - { X86::VUNPCKHPDZ256rm, X86::VUNPCKHPDZ256rm, X86::VPUNPCKHQDQZ256rm }, - { X86::VUNPCKHPDZ256rr, X86::VUNPCKHPDZ256rr, X86::VPUNPCKHQDQZ256rr }, - { X86::VUNPCKLPSZ256rm, X86::VUNPCKLPSZ256rm, X86::VPUNPCKLDQZ256rm }, - { X86::VUNPCKLPSZ256rr, X86::VUNPCKLPSZ256rr, X86::VPUNPCKLDQZ256rr }, - { X86::VUNPCKHPSZ256rm, X86::VUNPCKHPSZ256rm, X86::VPUNPCKHDQZ256rm }, - { X86::VUNPCKHPSZ256rr, X86::VUNPCKHPSZ256rr, X86::VPUNPCKHDQZ256rr }, - { X86::VUNPCKLPDZ128rm, X86::VUNPCKLPDZ128rm, X86::VPUNPCKLQDQZ128rm }, - { X86::VMOVLHPSZrr, X86::VUNPCKLPDZ128rr, X86::VPUNPCKLQDQZ128rr }, - { X86::VUNPCKHPDZ128rm, X86::VUNPCKHPDZ128rm, X86::VPUNPCKHQDQZ128rm }, - { X86::VUNPCKHPDZ128rr, X86::VUNPCKHPDZ128rr, X86::VPUNPCKHQDQZ128rr }, - { X86::VUNPCKLPSZ128rm, X86::VUNPCKLPSZ128rm, X86::VPUNPCKLDQZ128rm }, - { X86::VUNPCKLPSZ128rr, X86::VUNPCKLPSZ128rr, X86::VPUNPCKLDQZ128rr }, - { X86::VUNPCKHPSZ128rm, X86::VUNPCKHPSZ128rm, X86::VPUNPCKHDQZ128rm }, - { X86::VUNPCKHPSZ128rr, X86::VUNPCKHPSZ128rr, X86::VPUNPCKHDQZ128rr }, - { X86::VUNPCKLPDZrm, X86::VUNPCKLPDZrm, X86::VPUNPCKLQDQZrm }, - { X86::VUNPCKLPDZrr, X86::VUNPCKLPDZrr, X86::VPUNPCKLQDQZrr }, - { X86::VUNPCKHPDZrm, X86::VUNPCKHPDZrm, X86::VPUNPCKHQDQZrm }, - { X86::VUNPCKHPDZrr, X86::VUNPCKHPDZrr, X86::VPUNPCKHQDQZrr }, - { X86::VUNPCKLPSZrm, X86::VUNPCKLPSZrm, X86::VPUNPCKLDQZrm }, - { X86::VUNPCKLPSZrr, X86::VUNPCKLPSZrr, X86::VPUNPCKLDQZrr }, - { X86::VUNPCKHPSZrm, X86::VUNPCKHPSZrm, X86::VPUNPCKHDQZrm }, - { X86::VUNPCKHPSZrr, X86::VUNPCKHPSZrr, X86::VPUNPCKHDQZrr }, - { X86::VEXTRACTPSZmr, X86::VEXTRACTPSZmr, X86::VPEXTRDZmr }, - { X86::VEXTRACTPSZrr, X86::VEXTRACTPSZrr, X86::VPEXTRDZrr }, -}; - -static const uint16_t ReplaceableInstrsAVX2[][3] = { - //PackedSingle PackedDouble PackedInt - { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm }, - { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr }, - { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm }, - { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr }, - { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm }, - { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr }, - { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm }, - { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr }, - { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm }, - { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr }, - { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm}, - { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr}, - { X86::VMOVDDUPrm, X86::VMOVDDUPrm, X86::VPBROADCASTQrm}, - { X86::VMOVDDUPrr, X86::VMOVDDUPrr, X86::VPBROADCASTQrr}, - { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr}, - { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm}, - { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr}, - { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}, - { X86::VBROADCASTF128, X86::VBROADCASTF128, X86::VBROADCASTI128 }, - { X86::VBLENDPSYrri, X86::VBLENDPSYrri, X86::VPBLENDDYrri }, - { X86::VBLENDPSYrmi, X86::VBLENDPSYrmi, X86::VPBLENDDYrmi }, - { X86::VPERMILPSYmi, X86::VPERMILPSYmi, X86::VPSHUFDYmi }, - { X86::VPERMILPSYri, X86::VPERMILPSYri, X86::VPSHUFDYri }, - { X86::VUNPCKLPDYrm, X86::VUNPCKLPDYrm, X86::VPUNPCKLQDQYrm }, - { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrr, X86::VPUNPCKLQDQYrr }, - { X86::VUNPCKHPDYrm, X86::VUNPCKHPDYrm, X86::VPUNPCKHQDQYrm }, - { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrr, X86::VPUNPCKHQDQYrr }, - { X86::VUNPCKLPSYrm, X86::VUNPCKLPSYrm, X86::VPUNPCKLDQYrm }, - { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrr, X86::VPUNPCKLDQYrr }, - { X86::VUNPCKHPSYrm, X86::VUNPCKHPSYrm, X86::VPUNPCKHDQYrm }, - { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrr, X86::VPUNPCKHDQYrr }, -}; - -static const uint16_t ReplaceableInstrsFP[][3] = { - //PackedSingle PackedDouble - { X86::MOVLPSrm, X86::MOVLPDrm, X86::INSTRUCTION_LIST_END }, - { X86::MOVHPSrm, X86::MOVHPDrm, X86::INSTRUCTION_LIST_END }, - { X86::MOVHPSmr, X86::MOVHPDmr, X86::INSTRUCTION_LIST_END }, - { X86::VMOVLPSrm, X86::VMOVLPDrm, X86::INSTRUCTION_LIST_END }, - { X86::VMOVHPSrm, X86::VMOVHPDrm, X86::INSTRUCTION_LIST_END }, - { X86::VMOVHPSmr, X86::VMOVHPDmr, X86::INSTRUCTION_LIST_END }, - { X86::VMOVLPSZ128rm, X86::VMOVLPDZ128rm, X86::INSTRUCTION_LIST_END }, - { X86::VMOVHPSZ128rm, X86::VMOVHPDZ128rm, X86::INSTRUCTION_LIST_END }, - { X86::VMOVHPSZ128mr, X86::VMOVHPDZ128mr, X86::INSTRUCTION_LIST_END }, -}; - -static const uint16_t ReplaceableInstrsAVX2InsertExtract[][3] = { - //PackedSingle PackedDouble PackedInt - { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr }, - { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr }, - { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm }, - { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr }, -}; - -static const uint16_t ReplaceableInstrsAVX512[][4] = { - // Two integer columns for 64-bit and 32-bit elements. - //PackedSingle PackedDouble PackedInt PackedInt - { X86::VMOVAPSZ128mr, X86::VMOVAPDZ128mr, X86::VMOVDQA64Z128mr, X86::VMOVDQA32Z128mr }, - { X86::VMOVAPSZ128rm, X86::VMOVAPDZ128rm, X86::VMOVDQA64Z128rm, X86::VMOVDQA32Z128rm }, - { X86::VMOVAPSZ128rr, X86::VMOVAPDZ128rr, X86::VMOVDQA64Z128rr, X86::VMOVDQA32Z128rr }, - { X86::VMOVUPSZ128mr, X86::VMOVUPDZ128mr, X86::VMOVDQU64Z128mr, X86::VMOVDQU32Z128mr }, - { X86::VMOVUPSZ128rm, X86::VMOVUPDZ128rm, X86::VMOVDQU64Z128rm, X86::VMOVDQU32Z128rm }, - { X86::VMOVAPSZ256mr, X86::VMOVAPDZ256mr, X86::VMOVDQA64Z256mr, X86::VMOVDQA32Z256mr }, - { X86::VMOVAPSZ256rm, X86::VMOVAPDZ256rm, X86::VMOVDQA64Z256rm, X86::VMOVDQA32Z256rm }, - { X86::VMOVAPSZ256rr, X86::VMOVAPDZ256rr, X86::VMOVDQA64Z256rr, X86::VMOVDQA32Z256rr }, - { X86::VMOVUPSZ256mr, X86::VMOVUPDZ256mr, X86::VMOVDQU64Z256mr, X86::VMOVDQU32Z256mr }, - { X86::VMOVUPSZ256rm, X86::VMOVUPDZ256rm, X86::VMOVDQU64Z256rm, X86::VMOVDQU32Z256rm }, - { X86::VMOVAPSZmr, X86::VMOVAPDZmr, X86::VMOVDQA64Zmr, X86::VMOVDQA32Zmr }, - { X86::VMOVAPSZrm, X86::VMOVAPDZrm, X86::VMOVDQA64Zrm, X86::VMOVDQA32Zrm }, - { X86::VMOVAPSZrr, X86::VMOVAPDZrr, X86::VMOVDQA64Zrr, X86::VMOVDQA32Zrr }, - { X86::VMOVUPSZmr, X86::VMOVUPDZmr, X86::VMOVDQU64Zmr, X86::VMOVDQU32Zmr }, - { X86::VMOVUPSZrm, X86::VMOVUPDZrm, X86::VMOVDQU64Zrm, X86::VMOVDQU32Zrm }, -}; - -static const uint16_t ReplaceableInstrsAVX512DQ[][4] = { - // Two integer columns for 64-bit and 32-bit elements. - //PackedSingle PackedDouble PackedInt PackedInt - { X86::VANDNPSZ128rm, X86::VANDNPDZ128rm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm }, - { X86::VANDNPSZ128rr, X86::VANDNPDZ128rr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr }, - { X86::VANDPSZ128rm, X86::VANDPDZ128rm, X86::VPANDQZ128rm, X86::VPANDDZ128rm }, - { X86::VANDPSZ128rr, X86::VANDPDZ128rr, X86::VPANDQZ128rr, X86::VPANDDZ128rr }, - { X86::VORPSZ128rm, X86::VORPDZ128rm, X86::VPORQZ128rm, X86::VPORDZ128rm }, - { X86::VORPSZ128rr, X86::VORPDZ128rr, X86::VPORQZ128rr, X86::VPORDZ128rr }, - { X86::VXORPSZ128rm, X86::VXORPDZ128rm, X86::VPXORQZ128rm, X86::VPXORDZ128rm }, - { X86::VXORPSZ128rr, X86::VXORPDZ128rr, X86::VPXORQZ128rr, X86::VPXORDZ128rr }, - { X86::VANDNPSZ256rm, X86::VANDNPDZ256rm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm }, - { X86::VANDNPSZ256rr, X86::VANDNPDZ256rr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr }, - { X86::VANDPSZ256rm, X86::VANDPDZ256rm, X86::VPANDQZ256rm, X86::VPANDDZ256rm }, - { X86::VANDPSZ256rr, X86::VANDPDZ256rr, X86::VPANDQZ256rr, X86::VPANDDZ256rr }, - { X86::VORPSZ256rm, X86::VORPDZ256rm, X86::VPORQZ256rm, X86::VPORDZ256rm }, - { X86::VORPSZ256rr, X86::VORPDZ256rr, X86::VPORQZ256rr, X86::VPORDZ256rr }, - { X86::VXORPSZ256rm, X86::VXORPDZ256rm, X86::VPXORQZ256rm, X86::VPXORDZ256rm }, - { X86::VXORPSZ256rr, X86::VXORPDZ256rr, X86::VPXORQZ256rr, X86::VPXORDZ256rr }, - { X86::VANDNPSZrm, X86::VANDNPDZrm, X86::VPANDNQZrm, X86::VPANDNDZrm }, - { X86::VANDNPSZrr, X86::VANDNPDZrr, X86::VPANDNQZrr, X86::VPANDNDZrr }, - { X86::VANDPSZrm, X86::VANDPDZrm, X86::VPANDQZrm, X86::VPANDDZrm }, - { X86::VANDPSZrr, X86::VANDPDZrr, X86::VPANDQZrr, X86::VPANDDZrr }, - { X86::VORPSZrm, X86::VORPDZrm, X86::VPORQZrm, X86::VPORDZrm }, - { X86::VORPSZrr, X86::VORPDZrr, X86::VPORQZrr, X86::VPORDZrr }, - { X86::VXORPSZrm, X86::VXORPDZrm, X86::VPXORQZrm, X86::VPXORDZrm }, - { X86::VXORPSZrr, X86::VXORPDZrr, X86::VPXORQZrr, X86::VPXORDZrr }, -}; - -static const uint16_t ReplaceableInstrsAVX512DQMasked[][4] = { - // Two integer columns for 64-bit and 32-bit elements. - //PackedSingle PackedDouble - //PackedInt PackedInt - { X86::VANDNPSZ128rmk, X86::VANDNPDZ128rmk, - X86::VPANDNQZ128rmk, X86::VPANDNDZ128rmk }, - { X86::VANDNPSZ128rmkz, X86::VANDNPDZ128rmkz, - X86::VPANDNQZ128rmkz, X86::VPANDNDZ128rmkz }, - { X86::VANDNPSZ128rrk, X86::VANDNPDZ128rrk, - X86::VPANDNQZ128rrk, X86::VPANDNDZ128rrk }, - { X86::VANDNPSZ128rrkz, X86::VANDNPDZ128rrkz, - X86::VPANDNQZ128rrkz, X86::VPANDNDZ128rrkz }, - { X86::VANDPSZ128rmk, X86::VANDPDZ128rmk, - X86::VPANDQZ128rmk, X86::VPANDDZ128rmk }, - { X86::VANDPSZ128rmkz, X86::VANDPDZ128rmkz, - X86::VPANDQZ128rmkz, X86::VPANDDZ128rmkz }, - { X86::VANDPSZ128rrk, X86::VANDPDZ128rrk, - X86::VPANDQZ128rrk, X86::VPANDDZ128rrk }, - { X86::VANDPSZ128rrkz, X86::VANDPDZ128rrkz, - X86::VPANDQZ128rrkz, X86::VPANDDZ128rrkz }, - { X86::VORPSZ128rmk, X86::VORPDZ128rmk, - X86::VPORQZ128rmk, X86::VPORDZ128rmk }, - { X86::VORPSZ128rmkz, X86::VORPDZ128rmkz, - X86::VPORQZ128rmkz, X86::VPORDZ128rmkz }, - { X86::VORPSZ128rrk, X86::VORPDZ128rrk, - X86::VPORQZ128rrk, X86::VPORDZ128rrk }, - { X86::VORPSZ128rrkz, X86::VORPDZ128rrkz, - X86::VPORQZ128rrkz, X86::VPORDZ128rrkz }, - { X86::VXORPSZ128rmk, X86::VXORPDZ128rmk, - X86::VPXORQZ128rmk, X86::VPXORDZ128rmk }, - { X86::VXORPSZ128rmkz, X86::VXORPDZ128rmkz, - X86::VPXORQZ128rmkz, X86::VPXORDZ128rmkz }, - { X86::VXORPSZ128rrk, X86::VXORPDZ128rrk, - X86::VPXORQZ128rrk, X86::VPXORDZ128rrk }, - { X86::VXORPSZ128rrkz, X86::VXORPDZ128rrkz, - X86::VPXORQZ128rrkz, X86::VPXORDZ128rrkz }, - { X86::VANDNPSZ256rmk, X86::VANDNPDZ256rmk, - X86::VPANDNQZ256rmk, X86::VPANDNDZ256rmk }, - { X86::VANDNPSZ256rmkz, X86::VANDNPDZ256rmkz, - X86::VPANDNQZ256rmkz, X86::VPANDNDZ256rmkz }, - { X86::VANDNPSZ256rrk, X86::VANDNPDZ256rrk, - X86::VPANDNQZ256rrk, X86::VPANDNDZ256rrk }, - { X86::VANDNPSZ256rrkz, X86::VANDNPDZ256rrkz, - X86::VPANDNQZ256rrkz, X86::VPANDNDZ256rrkz }, - { X86::VANDPSZ256rmk, X86::VANDPDZ256rmk, - X86::VPANDQZ256rmk, X86::VPANDDZ256rmk }, - { X86::VANDPSZ256rmkz, X86::VANDPDZ256rmkz, - X86::VPANDQZ256rmkz, X86::VPANDDZ256rmkz }, - { X86::VANDPSZ256rrk, X86::VANDPDZ256rrk, - X86::VPANDQZ256rrk, X86::VPANDDZ256rrk }, - { X86::VANDPSZ256rrkz, X86::VANDPDZ256rrkz, - X86::VPANDQZ256rrkz, X86::VPANDDZ256rrkz }, - { X86::VORPSZ256rmk, X86::VORPDZ256rmk, - X86::VPORQZ256rmk, X86::VPORDZ256rmk }, - { X86::VORPSZ256rmkz, X86::VORPDZ256rmkz, - X86::VPORQZ256rmkz, X86::VPORDZ256rmkz }, - { X86::VORPSZ256rrk, X86::VORPDZ256rrk, - X86::VPORQZ256rrk, X86::VPORDZ256rrk }, - { X86::VORPSZ256rrkz, X86::VORPDZ256rrkz, - X86::VPORQZ256rrkz, X86::VPORDZ256rrkz }, - { X86::VXORPSZ256rmk, X86::VXORPDZ256rmk, - X86::VPXORQZ256rmk, X86::VPXORDZ256rmk }, - { X86::VXORPSZ256rmkz, X86::VXORPDZ256rmkz, - X86::VPXORQZ256rmkz, X86::VPXORDZ256rmkz }, - { X86::VXORPSZ256rrk, X86::VXORPDZ256rrk, - X86::VPXORQZ256rrk, X86::VPXORDZ256rrk }, - { X86::VXORPSZ256rrkz, X86::VXORPDZ256rrkz, - X86::VPXORQZ256rrkz, X86::VPXORDZ256rrkz }, - { X86::VANDNPSZrmk, X86::VANDNPDZrmk, - X86::VPANDNQZrmk, X86::VPANDNDZrmk }, - { X86::VANDNPSZrmkz, X86::VANDNPDZrmkz, - X86::VPANDNQZrmkz, X86::VPANDNDZrmkz }, - { X86::VANDNPSZrrk, X86::VANDNPDZrrk, - X86::VPANDNQZrrk, X86::VPANDNDZrrk }, - { X86::VANDNPSZrrkz, X86::VANDNPDZrrkz, - X86::VPANDNQZrrkz, X86::VPANDNDZrrkz }, - { X86::VANDPSZrmk, X86::VANDPDZrmk, - X86::VPANDQZrmk, X86::VPANDDZrmk }, - { X86::VANDPSZrmkz, X86::VANDPDZrmkz, - X86::VPANDQZrmkz, X86::VPANDDZrmkz }, - { X86::VANDPSZrrk, X86::VANDPDZrrk, - X86::VPANDQZrrk, X86::VPANDDZrrk }, - { X86::VANDPSZrrkz, X86::VANDPDZrrkz, - X86::VPANDQZrrkz, X86::VPANDDZrrkz }, - { X86::VORPSZrmk, X86::VORPDZrmk, - X86::VPORQZrmk, X86::VPORDZrmk }, - { X86::VORPSZrmkz, X86::VORPDZrmkz, - X86::VPORQZrmkz, X86::VPORDZrmkz }, - { X86::VORPSZrrk, X86::VORPDZrrk, - X86::VPORQZrrk, X86::VPORDZrrk }, - { X86::VORPSZrrkz, X86::VORPDZrrkz, - X86::VPORQZrrkz, X86::VPORDZrrkz }, - { X86::VXORPSZrmk, X86::VXORPDZrmk, - X86::VPXORQZrmk, X86::VPXORDZrmk }, - { X86::VXORPSZrmkz, X86::VXORPDZrmkz, - X86::VPXORQZrmkz, X86::VPXORDZrmkz }, - { X86::VXORPSZrrk, X86::VXORPDZrrk, - X86::VPXORQZrrk, X86::VPXORDZrrk }, - { X86::VXORPSZrrkz, X86::VXORPDZrrkz, - X86::VPXORQZrrkz, X86::VPXORDZrrkz }, - // Broadcast loads can be handled the same as masked operations to avoid - // changing element size. - { X86::VANDNPSZ128rmb, X86::VANDNPDZ128rmb, - X86::VPANDNQZ128rmb, X86::VPANDNDZ128rmb }, - { X86::VANDPSZ128rmb, X86::VANDPDZ128rmb, - X86::VPANDQZ128rmb, X86::VPANDDZ128rmb }, - { X86::VORPSZ128rmb, X86::VORPDZ128rmb, - X86::VPORQZ128rmb, X86::VPORDZ128rmb }, - { X86::VXORPSZ128rmb, X86::VXORPDZ128rmb, - X86::VPXORQZ128rmb, X86::VPXORDZ128rmb }, - { X86::VANDNPSZ256rmb, X86::VANDNPDZ256rmb, - X86::VPANDNQZ256rmb, X86::VPANDNDZ256rmb }, - { X86::VANDPSZ256rmb, X86::VANDPDZ256rmb, - X86::VPANDQZ256rmb, X86::VPANDDZ256rmb }, - { X86::VORPSZ256rmb, X86::VORPDZ256rmb, - X86::VPORQZ256rmb, X86::VPORDZ256rmb }, - { X86::VXORPSZ256rmb, X86::VXORPDZ256rmb, - X86::VPXORQZ256rmb, X86::VPXORDZ256rmb }, - { X86::VANDNPSZrmb, X86::VANDNPDZrmb, - X86::VPANDNQZrmb, X86::VPANDNDZrmb }, - { X86::VANDPSZrmb, X86::VANDPDZrmb, - X86::VPANDQZrmb, X86::VPANDDZrmb }, - { X86::VANDPSZrmb, X86::VANDPDZrmb, - X86::VPANDQZrmb, X86::VPANDDZrmb }, - { X86::VORPSZrmb, X86::VORPDZrmb, - X86::VPORQZrmb, X86::VPORDZrmb }, - { X86::VXORPSZrmb, X86::VXORPDZrmb, - X86::VPXORQZrmb, X86::VPXORDZrmb }, - { X86::VANDNPSZ128rmbk, X86::VANDNPDZ128rmbk, - X86::VPANDNQZ128rmbk, X86::VPANDNDZ128rmbk }, - { X86::VANDPSZ128rmbk, X86::VANDPDZ128rmbk, - X86::VPANDQZ128rmbk, X86::VPANDDZ128rmbk }, - { X86::VORPSZ128rmbk, X86::VORPDZ128rmbk, - X86::VPORQZ128rmbk, X86::VPORDZ128rmbk }, - { X86::VXORPSZ128rmbk, X86::VXORPDZ128rmbk, - X86::VPXORQZ128rmbk, X86::VPXORDZ128rmbk }, - { X86::VANDNPSZ256rmbk, X86::VANDNPDZ256rmbk, - X86::VPANDNQZ256rmbk, X86::VPANDNDZ256rmbk }, - { X86::VANDPSZ256rmbk, X86::VANDPDZ256rmbk, - X86::VPANDQZ256rmbk, X86::VPANDDZ256rmbk }, - { X86::VORPSZ256rmbk, X86::VORPDZ256rmbk, - X86::VPORQZ256rmbk, X86::VPORDZ256rmbk }, - { X86::VXORPSZ256rmbk, X86::VXORPDZ256rmbk, - X86::VPXORQZ256rmbk, X86::VPXORDZ256rmbk }, - { X86::VANDNPSZrmbk, X86::VANDNPDZrmbk, - X86::VPANDNQZrmbk, X86::VPANDNDZrmbk }, - { X86::VANDPSZrmbk, X86::VANDPDZrmbk, - X86::VPANDQZrmbk, X86::VPANDDZrmbk }, - { X86::VANDPSZrmbk, X86::VANDPDZrmbk, - X86::VPANDQZrmbk, X86::VPANDDZrmbk }, - { X86::VORPSZrmbk, X86::VORPDZrmbk, - X86::VPORQZrmbk, X86::VPORDZrmbk }, - { X86::VXORPSZrmbk, X86::VXORPDZrmbk, - X86::VPXORQZrmbk, X86::VPXORDZrmbk }, - { X86::VANDNPSZ128rmbkz,X86::VANDNPDZ128rmbkz, - X86::VPANDNQZ128rmbkz,X86::VPANDNDZ128rmbkz}, - { X86::VANDPSZ128rmbkz, X86::VANDPDZ128rmbkz, - X86::VPANDQZ128rmbkz, X86::VPANDDZ128rmbkz }, - { X86::VORPSZ128rmbkz, X86::VORPDZ128rmbkz, - X86::VPORQZ128rmbkz, X86::VPORDZ128rmbkz }, - { X86::VXORPSZ128rmbkz, X86::VXORPDZ128rmbkz, - X86::VPXORQZ128rmbkz, X86::VPXORDZ128rmbkz }, - { X86::VANDNPSZ256rmbkz,X86::VANDNPDZ256rmbkz, - X86::VPANDNQZ256rmbkz,X86::VPANDNDZ256rmbkz}, - { X86::VANDPSZ256rmbkz, X86::VANDPDZ256rmbkz, - X86::VPANDQZ256rmbkz, X86::VPANDDZ256rmbkz }, - { X86::VORPSZ256rmbkz, X86::VORPDZ256rmbkz, - X86::VPORQZ256rmbkz, X86::VPORDZ256rmbkz }, - { X86::VXORPSZ256rmbkz, X86::VXORPDZ256rmbkz, - X86::VPXORQZ256rmbkz, X86::VPXORDZ256rmbkz }, - { X86::VANDNPSZrmbkz, X86::VANDNPDZrmbkz, - X86::VPANDNQZrmbkz, X86::VPANDNDZrmbkz }, - { X86::VANDPSZrmbkz, X86::VANDPDZrmbkz, - X86::VPANDQZrmbkz, X86::VPANDDZrmbkz }, - { X86::VANDPSZrmbkz, X86::VANDPDZrmbkz, - X86::VPANDQZrmbkz, X86::VPANDDZrmbkz }, - { X86::VORPSZrmbkz, X86::VORPDZrmbkz, - X86::VPORQZrmbkz, X86::VPORDZrmbkz }, - { X86::VXORPSZrmbkz, X86::VXORPDZrmbkz, - X86::VPXORQZrmbkz, X86::VPXORDZrmbkz }, -}; - -// NOTE: These should only be used by the custom domain methods. -static const uint16_t ReplaceableBlendInstrs[][3] = { - //PackedSingle PackedDouble PackedInt - { X86::BLENDPSrmi, X86::BLENDPDrmi, X86::PBLENDWrmi }, - { X86::BLENDPSrri, X86::BLENDPDrri, X86::PBLENDWrri }, - { X86::VBLENDPSrmi, X86::VBLENDPDrmi, X86::VPBLENDWrmi }, - { X86::VBLENDPSrri, X86::VBLENDPDrri, X86::VPBLENDWrri }, - { X86::VBLENDPSYrmi, X86::VBLENDPDYrmi, X86::VPBLENDWYrmi }, - { X86::VBLENDPSYrri, X86::VBLENDPDYrri, X86::VPBLENDWYrri }, -}; -static const uint16_t ReplaceableBlendAVX2Instrs[][3] = { - //PackedSingle PackedDouble PackedInt - { X86::VBLENDPSrmi, X86::VBLENDPDrmi, X86::VPBLENDDrmi }, - { X86::VBLENDPSrri, X86::VBLENDPDrri, X86::VPBLENDDrri }, - { X86::VBLENDPSYrmi, X86::VBLENDPDYrmi, X86::VPBLENDDYrmi }, - { X86::VBLENDPSYrri, X86::VBLENDPDYrri, X86::VPBLENDDYrri }, -}; - -// Special table for changing EVEX logic instructions to VEX. -// TODO: Should we run EVEX->VEX earlier? -static const uint16_t ReplaceableCustomAVX512LogicInstrs[][4] = { - // Two integer columns for 64-bit and 32-bit elements. - //PackedSingle PackedDouble PackedInt PackedInt - { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm }, - { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr }, - { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDQZ128rm, X86::VPANDDZ128rm }, - { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDQZ128rr, X86::VPANDDZ128rr }, - { X86::VORPSrm, X86::VORPDrm, X86::VPORQZ128rm, X86::VPORDZ128rm }, - { X86::VORPSrr, X86::VORPDrr, X86::VPORQZ128rr, X86::VPORDZ128rr }, - { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORQZ128rm, X86::VPXORDZ128rm }, - { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORQZ128rr, X86::VPXORDZ128rr }, - { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm }, - { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr }, - { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDQZ256rm, X86::VPANDDZ256rm }, - { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDQZ256rr, X86::VPANDDZ256rr }, - { X86::VORPSYrm, X86::VORPDYrm, X86::VPORQZ256rm, X86::VPORDZ256rm }, - { X86::VORPSYrr, X86::VORPDYrr, X86::VPORQZ256rr, X86::VPORDZ256rr }, - { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORQZ256rm, X86::VPXORDZ256rm }, - { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORQZ256rr, X86::VPXORDZ256rr }, -}; - // FIXME: Some shuffle and unpack instructions have equivalents in different // domains, but they require a bit more work than just switching opcodes. static const uint16_t *lookup(unsigned opcode, unsigned domain, ArrayRef Table) { - for (const uint16_t (&Row)[3] : Table) - if (Row[domain-1] == opcode) + for (const uint16_t(&Row)[3] : Table) + if (Row[domain - 1] == opcode) return Row; return nullptr; } @@ -8392,8 +8740,8 @@ static const uint16_t *lookup(unsigned opcode, unsigned domain, static const uint16_t *lookupAVX512(unsigned opcode, unsigned domain, ArrayRef Table) { // If this is the integer domain make sure to check both integer columns. - for (const uint16_t (&Row)[4] : Table) - if (Row[domain-1] == opcode || (domain == 3 && Row[3] == opcode)) + for (const uint16_t(&Row)[4] : Table) + if (Row[domain - 1] == opcode || (domain == 3 && Row[3] == opcode)) return Row; return nullptr; } @@ -8477,22 +8825,38 @@ uint16_t X86InstrInfo::getExecutionDomainCustom(const MachineInstr &MI) const { case X86::VPBLENDWYrmi: case X86::VPBLENDWYrri: return GetBlendDomains(8, false); - case X86::VPANDDZ128rr: case X86::VPANDDZ128rm: - case X86::VPANDDZ256rr: case X86::VPANDDZ256rm: - case X86::VPANDQZ128rr: case X86::VPANDQZ128rm: - case X86::VPANDQZ256rr: case X86::VPANDQZ256rm: - case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm: - case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm: - case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm: - case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm: - case X86::VPORDZ128rr: case X86::VPORDZ128rm: - case X86::VPORDZ256rr: case X86::VPORDZ256rm: - case X86::VPORQZ128rr: case X86::VPORQZ128rm: - case X86::VPORQZ256rr: case X86::VPORQZ256rm: - case X86::VPXORDZ128rr: case X86::VPXORDZ128rm: - case X86::VPXORDZ256rr: case X86::VPXORDZ256rm: - case X86::VPXORQZ128rr: case X86::VPXORQZ128rm: - case X86::VPXORQZ256rr: case X86::VPXORQZ256rm: + case X86::VPANDDZ128rr: + case X86::VPANDDZ128rm: + case X86::VPANDDZ256rr: + case X86::VPANDDZ256rm: + case X86::VPANDQZ128rr: + case X86::VPANDQZ128rm: + case X86::VPANDQZ256rr: + case X86::VPANDQZ256rm: + case X86::VPANDNDZ128rr: + case X86::VPANDNDZ128rm: + case X86::VPANDNDZ256rr: + case X86::VPANDNDZ256rm: + case X86::VPANDNQZ128rr: + case X86::VPANDNQZ128rm: + case X86::VPANDNQZ256rr: + case X86::VPANDNQZ256rm: + case X86::VPORDZ128rr: + case X86::VPORDZ128rm: + case X86::VPORDZ256rr: + case X86::VPORDZ256rm: + case X86::VPORQZ128rr: + case X86::VPORQZ128rm: + case X86::VPORQZ256rr: + case X86::VPORQZ256rm: + case X86::VPXORDZ128rr: + case X86::VPXORDZ128rm: + case X86::VPXORDZ256rr: + case X86::VPXORDZ256rm: + case X86::VPXORQZ128rr: + case X86::VPXORQZ128rm: + case X86::VPXORQZ256rr: + case X86::VPXORQZ256rm: // If we don't have DQI see if we can still switch from an EVEX integer // instruction to a VEX floating point instruction. if (Subtarget.hasDQI()) @@ -8518,8 +8882,7 @@ uint16_t X86InstrInfo::getExecutionDomainCustom(const MachineInstr &MI) const { // both inputs. if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg() && MI.getOperand(0).getSubReg() == 0 && - MI.getOperand(1).getSubReg() == 0 && - MI.getOperand(2).getSubReg() == 0) + MI.getOperand(1).getSubReg() == 0 && MI.getOperand(2).getSubReg() == 0) return 0x6; return 0; case X86::SHUFPDrri: @@ -8528,6 +8891,8 @@ uint16_t X86InstrInfo::getExecutionDomainCustom(const MachineInstr &MI) const { return 0; } +#include "X86ReplaceableInstrs.def" + bool X86InstrInfo::setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const { assert(Domain > 0 && Domain < 4 && "Invalid execution domain"); @@ -8600,28 +8965,44 @@ bool X86InstrInfo::setExecutionDomainCustom(MachineInstr &MI, case X86::VPBLENDWYrmi: case X86::VPBLENDWYrri: return SetBlendDomain(16, true); - case X86::VPANDDZ128rr: case X86::VPANDDZ128rm: - case X86::VPANDDZ256rr: case X86::VPANDDZ256rm: - case X86::VPANDQZ128rr: case X86::VPANDQZ128rm: - case X86::VPANDQZ256rr: case X86::VPANDQZ256rm: - case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm: - case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm: - case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm: - case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm: - case X86::VPORDZ128rr: case X86::VPORDZ128rm: - case X86::VPORDZ256rr: case X86::VPORDZ256rm: - case X86::VPORQZ128rr: case X86::VPORQZ128rm: - case X86::VPORQZ256rr: case X86::VPORQZ256rm: - case X86::VPXORDZ128rr: case X86::VPXORDZ128rm: - case X86::VPXORDZ256rr: case X86::VPXORDZ256rm: - case X86::VPXORQZ128rr: case X86::VPXORQZ128rm: - case X86::VPXORQZ256rr: case X86::VPXORQZ256rm: { + case X86::VPANDDZ128rr: + case X86::VPANDDZ128rm: + case X86::VPANDDZ256rr: + case X86::VPANDDZ256rm: + case X86::VPANDQZ128rr: + case X86::VPANDQZ128rm: + case X86::VPANDQZ256rr: + case X86::VPANDQZ256rm: + case X86::VPANDNDZ128rr: + case X86::VPANDNDZ128rm: + case X86::VPANDNDZ256rr: + case X86::VPANDNDZ256rm: + case X86::VPANDNQZ128rr: + case X86::VPANDNQZ128rm: + case X86::VPANDNQZ256rr: + case X86::VPANDNQZ256rm: + case X86::VPORDZ128rr: + case X86::VPORDZ128rm: + case X86::VPORDZ256rr: + case X86::VPORDZ256rm: + case X86::VPORQZ128rr: + case X86::VPORQZ128rm: + case X86::VPORQZ256rr: + case X86::VPORQZ256rm: + case X86::VPXORDZ128rr: + case X86::VPXORDZ128rm: + case X86::VPXORDZ256rr: + case X86::VPXORDZ256rm: + case X86::VPXORQZ128rr: + case X86::VPXORQZ128rm: + case X86::VPXORQZ256rr: + case X86::VPXORQZ256rm: { // Without DQI, convert EVEX instructions to VEX instructions. if (Subtarget.hasDQI()) return false; - const uint16_t *table = lookupAVX512(MI.getOpcode(), dom, - ReplaceableCustomAVX512LogicInstrs); + const uint16_t *table = + lookupAVX512(MI.getOpcode(), dom, ReplaceableCustomAVX512LogicInstrs); assert(table && "Instruction not found in table?"); // Don't change integer Q instructions to D instructions and // use D intructions if we started with a PS instruction. @@ -8649,8 +9030,10 @@ bool X86InstrInfo::setExecutionDomainCustom(MachineInstr &MI, if (Domain == 1) { unsigned Imm = MI.getOperand(3).getImm(); unsigned NewImm = 0x44; - if (Imm & 1) NewImm |= 0x0a; - if (Imm & 2) NewImm |= 0xa0; + if (Imm & 1) + NewImm |= 0x0a; + if (Imm & 2) + NewImm |= 0xa0; MI.getOperand(3).setImm(NewImm); MI.setDesc(get(X86::SHUFPSrri)); } @@ -8685,12 +9068,12 @@ X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const { validDomains = 0xe; } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512)) { validDomains = 0xe; - } else if (Subtarget.hasDQI() && lookupAVX512(opcode, domain, - ReplaceableInstrsAVX512DQ)) { + } else if (Subtarget.hasDQI() && + lookupAVX512(opcode, domain, ReplaceableInstrsAVX512DQ)) { validDomains = 0xe; } else if (Subtarget.hasDQI()) { - if (const uint16_t *table = lookupAVX512(opcode, domain, - ReplaceableInstrsAVX512DQMasked)) { + if (const uint16_t *table = + lookupAVX512(opcode, domain, ReplaceableInstrsAVX512DQMasked)) { if (domain == 1 || (domain == 3 && table[3] == opcode)) validDomains = 0xa; else @@ -8702,7 +9085,7 @@ X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const { } void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const { - assert(Domain>0 && Domain<4 && "Invalid execution domain"); + assert(Domain > 0 && Domain < 4 && "Invalid execution domain"); uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3; assert(dom && "Not an SSE instruction"); @@ -8766,7 +9149,8 @@ MCInst X86InstrInfo::getNop() const { bool X86InstrInfo::isHighLatencyDef(int opc) const { switch (opc) { - default: return false; + default: + return false; case X86::DIVPDrm: case X86::DIVPDrr: case X86::DIVPSrm: @@ -9095,8 +9479,7 @@ bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst, // instructions that depend on the exact status flags (zero, sign, etc.) // that are set by using these particular operands with this operation. const MachineOperand *FlagDef = Inst.findRegisterDefOperand(X86::EFLAGS); - assert((Inst.getNumDefs() == 1 || FlagDef) && - "Implicit def isn't flags?"); + assert((Inst.getNumDefs() == 1 || FlagDef) && "Implicit def isn't flags?"); if (FlagDef && !FlagDef->isDead()) return false; @@ -9679,230 +10062,228 @@ X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const { } namespace { - /// Create Global Base Reg pass. This initializes the PIC - /// global base register for x86-32. - struct CGBR : public MachineFunctionPass { - static char ID; - CGBR() : MachineFunctionPass(ID) {} - - bool runOnMachineFunction(MachineFunction &MF) override { - const X86TargetMachine *TM = +/// Create Global Base Reg pass. This initializes the PIC +/// global base register for x86-32. +struct CGBR : public MachineFunctionPass { + static char ID; + CGBR() : MachineFunctionPass(ID) {} + + bool runOnMachineFunction(MachineFunction &MF) override { + const X86TargetMachine *TM = static_cast(&MF.getTarget()); - const X86Subtarget &STI = MF.getSubtarget(); + const X86Subtarget &STI = MF.getSubtarget(); - // Don't do anything in the 64-bit small and kernel code models. They use - // RIP-relative addressing for everything. - if (STI.is64Bit() && (TM->getCodeModel() == CodeModel::Small || - TM->getCodeModel() == CodeModel::Kernel)) - return false; + // Don't do anything in the 64-bit small and kernel code models. They use + // RIP-relative addressing for everything. + if (STI.is64Bit() && (TM->getCodeModel() == CodeModel::Small || + TM->getCodeModel() == CodeModel::Kernel)) + return false; - // Only emit a global base reg in PIC mode. - if (!TM->isPositionIndependent()) - return false; + // Only emit a global base reg in PIC mode. + if (!TM->isPositionIndependent()) + return false; - X86MachineFunctionInfo *X86FI = MF.getInfo(); - Register GlobalBaseReg = X86FI->getGlobalBaseReg(); + X86MachineFunctionInfo *X86FI = MF.getInfo(); + Register GlobalBaseReg = X86FI->getGlobalBaseReg(); - // If we didn't need a GlobalBaseReg, don't insert code. - if (GlobalBaseReg == 0) - return false; + // If we didn't need a GlobalBaseReg, don't insert code. + if (GlobalBaseReg == 0) + return false; - // Insert the set of GlobalBaseReg into the first MBB of the function - MachineBasicBlock &FirstMBB = MF.front(); - MachineBasicBlock::iterator MBBI = FirstMBB.begin(); - DebugLoc DL = FirstMBB.findDebugLoc(MBBI); - MachineRegisterInfo &RegInfo = MF.getRegInfo(); - const X86InstrInfo *TII = STI.getInstrInfo(); + // Insert the set of GlobalBaseReg into the first MBB of the function + MachineBasicBlock &FirstMBB = MF.front(); + MachineBasicBlock::iterator MBBI = FirstMBB.begin(); + DebugLoc DL = FirstMBB.findDebugLoc(MBBI); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); + const X86InstrInfo *TII = STI.getInstrInfo(); - Register PC; - if (STI.isPICStyleGOT()) - PC = RegInfo.createVirtualRegister(&X86::GR32RegClass); - else - PC = GlobalBaseReg; - - if (STI.is64Bit()) { - if (TM->getCodeModel() == CodeModel::Medium) { - // In the medium code model, use a RIP-relative LEA to materialize the - // GOT. - BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PC) - .addReg(X86::RIP) - .addImm(0) - .addReg(0) - .addExternalSymbol("_GLOBAL_OFFSET_TABLE_") - .addReg(0); - } else if (TM->getCodeModel() == CodeModel::Large) { - // In the large code model, we are aiming for this code, though the - // register allocation may vary: - // leaq .LN$pb(%rip), %rax - // movq $_GLOBAL_OFFSET_TABLE_ - .LN$pb, %rcx - // addq %rcx, %rax - // RAX now holds address of _GLOBAL_OFFSET_TABLE_. - Register PBReg = RegInfo.createVirtualRegister(&X86::GR64RegClass); - Register GOTReg = RegInfo.createVirtualRegister(&X86::GR64RegClass); - BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PBReg) - .addReg(X86::RIP) - .addImm(0) - .addReg(0) - .addSym(MF.getPICBaseSymbol()) - .addReg(0); - std::prev(MBBI)->setPreInstrSymbol(MF, MF.getPICBaseSymbol()); - BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOV64ri), GOTReg) - .addExternalSymbol("_GLOBAL_OFFSET_TABLE_", - X86II::MO_PIC_BASE_OFFSET); - BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD64rr), PC) - .addReg(PBReg, RegState::Kill) - .addReg(GOTReg, RegState::Kill); - } else { - llvm_unreachable("unexpected code model"); - } + Register PC; + if (STI.isPICStyleGOT()) + PC = RegInfo.createVirtualRegister(&X86::GR32RegClass); + else + PC = GlobalBaseReg; + + if (STI.is64Bit()) { + if (TM->getCodeModel() == CodeModel::Medium) { + // In the medium code model, use a RIP-relative LEA to materialize the + // GOT. + BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PC) + .addReg(X86::RIP) + .addImm(0) + .addReg(0) + .addExternalSymbol("_GLOBAL_OFFSET_TABLE_") + .addReg(0); + } else if (TM->getCodeModel() == CodeModel::Large) { + // In the large code model, we are aiming for this code, though the + // register allocation may vary: + // leaq .LN$pb(%rip), %rax + // movq $_GLOBAL_OFFSET_TABLE_ - .LN$pb, %rcx + // addq %rcx, %rax + // RAX now holds address of _GLOBAL_OFFSET_TABLE_. + Register PBReg = RegInfo.createVirtualRegister(&X86::GR64RegClass); + Register GOTReg = RegInfo.createVirtualRegister(&X86::GR64RegClass); + BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PBReg) + .addReg(X86::RIP) + .addImm(0) + .addReg(0) + .addSym(MF.getPICBaseSymbol()) + .addReg(0); + std::prev(MBBI)->setPreInstrSymbol(MF, MF.getPICBaseSymbol()); + BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOV64ri), GOTReg) + .addExternalSymbol("_GLOBAL_OFFSET_TABLE_", + X86II::MO_PIC_BASE_OFFSET); + BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD64rr), PC) + .addReg(PBReg, RegState::Kill) + .addReg(GOTReg, RegState::Kill); } else { - // Operand of MovePCtoStack is completely ignored by asm printer. It's - // only used in JIT code emission as displacement to pc. - BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0); - - // If we're using vanilla 'GOT' PIC style, we should use relative - // addressing not to pc, but to _GLOBAL_OFFSET_TABLE_ external. - if (STI.isPICStyleGOT()) { - // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], - // %some_register - BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg) - .addReg(PC) - .addExternalSymbol("_GLOBAL_OFFSET_TABLE_", - X86II::MO_GOT_ABSOLUTE_ADDRESS); - } + llvm_unreachable("unexpected code model"); + } + } else { + // Operand of MovePCtoStack is completely ignored by asm printer. It's + // only used in JIT code emission as displacement to pc. + BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0); + + // If we're using vanilla 'GOT' PIC style, we should use relative + // addressing not to pc, but to _GLOBAL_OFFSET_TABLE_ external. + if (STI.isPICStyleGOT()) { + // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], + // %some_register + BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg) + .addReg(PC) + .addExternalSymbol("_GLOBAL_OFFSET_TABLE_", + X86II::MO_GOT_ABSOLUTE_ADDRESS); } - - return true; } - StringRef getPassName() const override { - return "X86 PIC Global Base Reg Initialization"; - } + return true; + } - void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.setPreservesCFG(); - MachineFunctionPass::getAnalysisUsage(AU); - } - }; + StringRef getPassName() const override { + return "X86 PIC Global Base Reg Initialization"; + } + + void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.setPreservesCFG(); + MachineFunctionPass::getAnalysisUsage(AU); + } +}; } // namespace char CGBR::ID = 0; -FunctionPass* -llvm::createX86GlobalBaseRegPass() { return new CGBR(); } +FunctionPass *llvm::createX86GlobalBaseRegPass() { return new CGBR(); } namespace { - struct LDTLSCleanup : public MachineFunctionPass { - static char ID; - LDTLSCleanup() : MachineFunctionPass(ID) {} +struct LDTLSCleanup : public MachineFunctionPass { + static char ID; + LDTLSCleanup() : MachineFunctionPass(ID) {} - bool runOnMachineFunction(MachineFunction &MF) override { - if (skipFunction(MF.getFunction())) - return false; + bool runOnMachineFunction(MachineFunction &MF) override { + if (skipFunction(MF.getFunction())) + return false; - X86MachineFunctionInfo *MFI = MF.getInfo(); - if (MFI->getNumLocalDynamicTLSAccesses() < 2) { - // No point folding accesses if there isn't at least two. - return false; + X86MachineFunctionInfo *MFI = MF.getInfo(); + if (MFI->getNumLocalDynamicTLSAccesses() < 2) { + // No point folding accesses if there isn't at least two. + return false; + } + + MachineDominatorTree *DT = &getAnalysis(); + return VisitNode(DT->getRootNode(), 0); + } + + // Visit the dominator subtree rooted at Node in pre-order. + // If TLSBaseAddrReg is non-null, then use that to replace any + // TLS_base_addr instructions. Otherwise, create the register + // when the first such instruction is seen, and then use it + // as we encounter more instructions. + bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) { + MachineBasicBlock *BB = Node->getBlock(); + bool Changed = false; + + // Traverse the current block. + for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; + ++I) { + switch (I->getOpcode()) { + case X86::TLS_base_addr32: + case X86::TLS_base_addr64: + if (TLSBaseAddrReg) + I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg); + else + I = SetRegister(*I, &TLSBaseAddrReg); + Changed = true; + break; + default: + break; } + } - MachineDominatorTree *DT = &getAnalysis(); - return VisitNode(DT->getRootNode(), 0); + // Visit the children of this block in the dominator tree. + for (auto &I : *Node) { + Changed |= VisitNode(I, TLSBaseAddrReg); } - // Visit the dominator subtree rooted at Node in pre-order. - // If TLSBaseAddrReg is non-null, then use that to replace any - // TLS_base_addr instructions. Otherwise, create the register - // when the first such instruction is seen, and then use it - // as we encounter more instructions. - bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) { - MachineBasicBlock *BB = Node->getBlock(); - bool Changed = false; - - // Traverse the current block. - for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; - ++I) { - switch (I->getOpcode()) { - case X86::TLS_base_addr32: - case X86::TLS_base_addr64: - if (TLSBaseAddrReg) - I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg); - else - I = SetRegister(*I, &TLSBaseAddrReg); - Changed = true; - break; - default: - break; - } - } + return Changed; + } - // Visit the children of this block in the dominator tree. - for (auto &I : *Node) { - Changed |= VisitNode(I, TLSBaseAddrReg); - } + // Replace the TLS_base_addr instruction I with a copy from + // TLSBaseAddrReg, returning the new instruction. + MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I, + unsigned TLSBaseAddrReg) { + MachineFunction *MF = I.getParent()->getParent(); + const X86Subtarget &STI = MF->getSubtarget(); + const bool is64Bit = STI.is64Bit(); + const X86InstrInfo *TII = STI.getInstrInfo(); - return Changed; - } + // Insert a Copy from TLSBaseAddrReg to RAX/EAX. + MachineInstr *Copy = + BuildMI(*I.getParent(), I, I.getDebugLoc(), + TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX) + .addReg(TLSBaseAddrReg); - // Replace the TLS_base_addr instruction I with a copy from - // TLSBaseAddrReg, returning the new instruction. - MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I, - unsigned TLSBaseAddrReg) { - MachineFunction *MF = I.getParent()->getParent(); - const X86Subtarget &STI = MF->getSubtarget(); - const bool is64Bit = STI.is64Bit(); - const X86InstrInfo *TII = STI.getInstrInfo(); - - // Insert a Copy from TLSBaseAddrReg to RAX/EAX. - MachineInstr *Copy = - BuildMI(*I.getParent(), I, I.getDebugLoc(), - TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX) - .addReg(TLSBaseAddrReg); - - // Erase the TLS_base_addr instruction. - I.eraseFromParent(); - - return Copy; - } + // Erase the TLS_base_addr instruction. + I.eraseFromParent(); - // Create a virtual register in *TLSBaseAddrReg, and populate it by - // inserting a copy instruction after I. Returns the new instruction. - MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) { - MachineFunction *MF = I.getParent()->getParent(); - const X86Subtarget &STI = MF->getSubtarget(); - const bool is64Bit = STI.is64Bit(); - const X86InstrInfo *TII = STI.getInstrInfo(); - - // Create a virtual register for the TLS base address. - MachineRegisterInfo &RegInfo = MF->getRegInfo(); - *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit - ? &X86::GR64RegClass - : &X86::GR32RegClass); - - // Insert a copy from RAX/EAX to TLSBaseAddrReg. - MachineInstr *Next = I.getNextNode(); - MachineInstr *Copy = - BuildMI(*I.getParent(), Next, I.getDebugLoc(), - TII->get(TargetOpcode::COPY), *TLSBaseAddrReg) - .addReg(is64Bit ? X86::RAX : X86::EAX); - - return Copy; - } + return Copy; + } - StringRef getPassName() const override { - return "Local Dynamic TLS Access Clean-up"; - } + // Create a virtual register in *TLSBaseAddrReg, and populate it by + // inserting a copy instruction after I. Returns the new instruction. + MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) { + MachineFunction *MF = I.getParent()->getParent(); + const X86Subtarget &STI = MF->getSubtarget(); + const bool is64Bit = STI.is64Bit(); + const X86InstrInfo *TII = STI.getInstrInfo(); - void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.setPreservesCFG(); - AU.addRequired(); - MachineFunctionPass::getAnalysisUsage(AU); - } - }; -} + // Create a virtual register for the TLS base address. + MachineRegisterInfo &RegInfo = MF->getRegInfo(); + *TLSBaseAddrReg = RegInfo.createVirtualRegister( + is64Bit ? &X86::GR64RegClass : &X86::GR32RegClass); + + // Insert a copy from RAX/EAX to TLSBaseAddrReg. + MachineInstr *Next = I.getNextNode(); + MachineInstr *Copy = BuildMI(*I.getParent(), Next, I.getDebugLoc(), + TII->get(TargetOpcode::COPY), *TLSBaseAddrReg) + .addReg(is64Bit ? X86::RAX : X86::EAX); + + return Copy; + } + + StringRef getPassName() const override { + return "Local Dynamic TLS Access Clean-up"; + } + + void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.setPreservesCFG(); + AU.addRequired(); + MachineFunctionPass::getAnalysisUsage(AU); + } +}; +} // namespace char LDTLSCleanup::ID = 0; -FunctionPass* -llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); } +FunctionPass *llvm::createCleanupLocalDynamicTLSPass() { + return new LDTLSCleanup(); +} /// Constants defining how certain sequences should be outlined. /// @@ -9932,10 +10313,7 @@ llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); } /// * Call construction overhead: 1 (jump instruction) /// * Frame construction overhead: 0 (don't need to return) /// -enum MachineOutlinerClass { - MachineOutlinerDefault, - MachineOutlinerTailCall -}; +enum MachineOutlinerClass { MachineOutlinerDefault, MachineOutlinerTailCall }; std::optional X86InstrInfo::getOutliningCandidateInfo( @@ -9995,8 +10373,8 @@ X86InstrInfo::getOutliningCandidateInfo( MachineOutlinerDefault); } -bool X86InstrInfo::isFunctionSafeToOutlineFrom(MachineFunction &MF, - bool OutlineFromLinkOnceODRs) const { +bool X86InstrInfo::isFunctionSafeToOutlineFrom( + MachineFunction &MF, bool OutlineFromLinkOnceODRs) const { const Function &F = MF.getFunction(); // Does the function use a red zone? If it does, then we can't risk messing @@ -10011,14 +10389,15 @@ bool X86InstrInfo::isFunctionSafeToOutlineFrom(MachineFunction &MF, // If we *don't* want to outline from things that could potentially be deduped // then return false. if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage()) - return false; + return false; // This function is viable for outlining, so return true. return true; } outliner::InstrType -X86InstrInfo::getOutliningTypeImpl(MachineBasicBlock::iterator &MIT, unsigned Flags) const { +X86InstrInfo::getOutliningTypeImpl(MachineBasicBlock::iterator &MIT, + unsigned Flags) const { MachineInstr &MI = *MIT; // Is this a terminator for a basic block? @@ -10054,10 +10433,9 @@ X86InstrInfo::getOutliningTypeImpl(MachineBasicBlock::iterator &MIT, unsigned F return outliner::InstrType::Legal; } -void X86InstrInfo::buildOutlinedFrame(MachineBasicBlock &MBB, - MachineFunction &MF, - const outliner::OutlinedFunction &OF) - const { +void X86InstrInfo::buildOutlinedFrame( + MachineBasicBlock &MBB, MachineFunction &MF, + const outliner::OutlinedFunction &OF) const { // If we're a tail call, we already have a return, so don't do anything. if (OF.FrameConstructionID == MachineOutlinerTailCall) return; @@ -10068,22 +10446,18 @@ void X86InstrInfo::buildOutlinedFrame(MachineBasicBlock &MBB, MBB.insert(MBB.end(), retq); } -MachineBasicBlock::iterator -X86InstrInfo::insertOutlinedCall(Module &M, MachineBasicBlock &MBB, - MachineBasicBlock::iterator &It, - MachineFunction &MF, - outliner::Candidate &C) const { +MachineBasicBlock::iterator X86InstrInfo::insertOutlinedCall( + Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, + MachineFunction &MF, outliner::Candidate &C) const { // Is it a tail call? if (C.CallConstructionID == MachineOutlinerTailCall) { // Yes, just insert a JMP. - It = MBB.insert(It, - BuildMI(MF, DebugLoc(), get(X86::TAILJMPd64)) - .addGlobalAddress(M.getNamedValue(MF.getName()))); + It = MBB.insert(It, BuildMI(MF, DebugLoc(), get(X86::TAILJMPd64)) + .addGlobalAddress(M.getNamedValue(MF.getName()))); } else { // No, insert a call. - It = MBB.insert(It, - BuildMI(MF, DebugLoc(), get(X86::CALL64pcrel32)) - .addGlobalAddress(M.getNamedValue(MF.getName()))); + It = MBB.insert(It, BuildMI(MF, DebugLoc(), get(X86::CALL64pcrel32)) + .addGlobalAddress(M.getNamedValue(MF.getName()))); } return It; @@ -10120,8 +10494,8 @@ void X86InstrInfo::buildClearRegister(Register Reg, MachineBasicBlock &MBB, // PXOR is safe to use because it doesn't affect flags. BuildMI(MBB, Iter, DL, get(X86::PXORrr), Reg) - .addReg(Reg, RegState::Undef) - .addReg(Reg, RegState::Undef); + .addReg(Reg, RegState::Undef) + .addReg(Reg, RegState::Undef); } else if (X86::VR256RegClass.contains(Reg)) { // YMM# if (!ST.hasAVX()) @@ -10129,8 +10503,8 @@ void X86InstrInfo::buildClearRegister(Register Reg, MachineBasicBlock &MBB, // VPXOR is safe to use because it doesn't affect flags. BuildMI(MBB, Iter, DL, get(X86::VPXORrr), Reg) - .addReg(Reg, RegState::Undef) - .addReg(Reg, RegState::Undef); + .addReg(Reg, RegState::Undef) + .addReg(Reg, RegState::Undef); } else if (X86::VR512RegClass.contains(Reg)) { // ZMM# if (!ST.hasAVX512()) @@ -10138,12 +10512,10 @@ void X86InstrInfo::buildClearRegister(Register Reg, MachineBasicBlock &MBB, // VPXORY is safe to use because it doesn't affect flags. BuildMI(MBB, Iter, DL, get(X86::VPXORYrr), Reg) - .addReg(Reg, RegState::Undef) - .addReg(Reg, RegState::Undef); - } else if (X86::VK1RegClass.contains(Reg) || - X86::VK2RegClass.contains(Reg) || - X86::VK4RegClass.contains(Reg) || - X86::VK8RegClass.contains(Reg) || + .addReg(Reg, RegState::Undef) + .addReg(Reg, RegState::Undef); + } else if (X86::VK1RegClass.contains(Reg) || X86::VK2RegClass.contains(Reg) || + X86::VK4RegClass.contains(Reg) || X86::VK8RegClass.contains(Reg) || X86::VK16RegClass.contains(Reg)) { if (!ST.hasVLX()) return; diff --git a/llvm/lib/Target/X86/X86ReplaceableInstrs.def b/llvm/lib/Target/X86/X86ReplaceableInstrs.def new file mode 100644 index 000000000000..4798275c0519 --- /dev/null +++ b/llvm/lib/Target/X86/X86ReplaceableInstrs.def @@ -0,0 +1,426 @@ +//===- X86ReplaceableInstrs.def ----------------------------------*- C++ -*-==// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// These are the replaceable SSE instructions. Some of these have Int variants +// that we don't include here. We don't want to replace instructions selected +// by intrinsics. + +#define ENTRY(A, B, C) {X86::A, X86::B, X86::C}, +static const uint16_t ReplaceableInstrs[][3] = { +// PackedSingle, PackedDouble, PackedInt +ENTRY(MOVAPSmr, MOVAPDmr, MOVDQAmr) +ENTRY(MOVAPSrm, MOVAPDrm, MOVDQArm) +ENTRY(MOVAPSrr, MOVAPDrr, MOVDQArr) +ENTRY(MOVUPSmr, MOVUPDmr, MOVDQUmr) +ENTRY(MOVUPSrm, MOVUPDrm, MOVDQUrm) +ENTRY(MOVLPSmr, MOVLPDmr, MOVPQI2QImr) +ENTRY(MOVSDmr, MOVSDmr, MOVPQI2QImr) +ENTRY(MOVSSmr, MOVSSmr, MOVPDI2DImr) +ENTRY(MOVSDrm, MOVSDrm, MOVQI2PQIrm) +ENTRY(MOVSDrm_alt, MOVSDrm_alt, MOVQI2PQIrm) +ENTRY(MOVSSrm, MOVSSrm, MOVDI2PDIrm) +ENTRY(MOVSSrm_alt, MOVSSrm_alt, MOVDI2PDIrm) +ENTRY(MOVNTPSmr, MOVNTPDmr, MOVNTDQmr) +ENTRY(ANDNPSrm, ANDNPDrm, PANDNrm) +ENTRY(ANDNPSrr, ANDNPDrr, PANDNrr) +ENTRY(ANDPSrm, ANDPDrm, PANDrm) +ENTRY(ANDPSrr, ANDPDrr, PANDrr) +ENTRY(ORPSrm, ORPDrm, PORrm) +ENTRY(ORPSrr, ORPDrr, PORrr) +ENTRY(XORPSrm, XORPDrm, PXORrm) +ENTRY(XORPSrr, XORPDrr, PXORrr) +ENTRY(UNPCKLPDrm, UNPCKLPDrm, PUNPCKLQDQrm) +ENTRY(MOVLHPSrr, UNPCKLPDrr, PUNPCKLQDQrr) +ENTRY(UNPCKHPDrm, UNPCKHPDrm, PUNPCKHQDQrm) +ENTRY(UNPCKHPDrr, UNPCKHPDrr, PUNPCKHQDQrr) +ENTRY(UNPCKLPSrm, UNPCKLPSrm, PUNPCKLDQrm) +ENTRY(UNPCKLPSrr, UNPCKLPSrr, PUNPCKLDQrr) +ENTRY(UNPCKHPSrm, UNPCKHPSrm, PUNPCKHDQrm) +ENTRY(UNPCKHPSrr, UNPCKHPSrr, PUNPCKHDQrr) +ENTRY(EXTRACTPSmr, EXTRACTPSmr, PEXTRDmr) +ENTRY(EXTRACTPSrr, EXTRACTPSrr, PEXTRDrr) +// AVX 128-bit support +ENTRY(VMOVAPSmr, VMOVAPDmr, VMOVDQAmr) +ENTRY(VMOVAPSrm, VMOVAPDrm, VMOVDQArm) +ENTRY(VMOVAPSrr, VMOVAPDrr, VMOVDQArr) +ENTRY(VMOVUPSmr, VMOVUPDmr, VMOVDQUmr) +ENTRY(VMOVUPSrm, VMOVUPDrm, VMOVDQUrm) +ENTRY(VMOVLPSmr, VMOVLPDmr, VMOVPQI2QImr) +ENTRY(VMOVSDmr, VMOVSDmr, VMOVPQI2QImr) +ENTRY(VMOVSSmr, VMOVSSmr, VMOVPDI2DImr) +ENTRY(VMOVSDrm, VMOVSDrm, VMOVQI2PQIrm) +ENTRY(VMOVSDrm_alt, VMOVSDrm_alt, VMOVQI2PQIrm) +ENTRY(VMOVSSrm, VMOVSSrm, VMOVDI2PDIrm) +ENTRY(VMOVSSrm_alt, VMOVSSrm_alt, VMOVDI2PDIrm) +ENTRY(VMOVNTPSmr, VMOVNTPDmr, VMOVNTDQmr) +ENTRY(VANDNPSrm, VANDNPDrm, VPANDNrm) +ENTRY(VANDNPSrr, VANDNPDrr, VPANDNrr) +ENTRY(VANDPSrm, VANDPDrm, VPANDrm) +ENTRY(VANDPSrr, VANDPDrr, VPANDrr) +ENTRY(VORPSrm, VORPDrm, VPORrm) +ENTRY(VORPSrr, VORPDrr, VPORrr) +ENTRY(VXORPSrm, VXORPDrm, VPXORrm) +ENTRY(VXORPSrr, VXORPDrr, VPXORrr) +ENTRY(VUNPCKLPDrm, VUNPCKLPDrm, VPUNPCKLQDQrm) +ENTRY(VMOVLHPSrr, VUNPCKLPDrr, VPUNPCKLQDQrr) +ENTRY(VUNPCKHPDrm, VUNPCKHPDrm, VPUNPCKHQDQrm) +ENTRY(VUNPCKHPDrr, VUNPCKHPDrr, VPUNPCKHQDQrr) +ENTRY(VUNPCKLPSrm, VUNPCKLPSrm, VPUNPCKLDQrm) +ENTRY(VUNPCKLPSrr, VUNPCKLPSrr, VPUNPCKLDQrr) +ENTRY(VUNPCKHPSrm, VUNPCKHPSrm, VPUNPCKHDQrm) +ENTRY(VUNPCKHPSrr, VUNPCKHPSrr, VPUNPCKHDQrr) +ENTRY(VEXTRACTPSmr, VEXTRACTPSmr, VPEXTRDmr) +ENTRY(VEXTRACTPSrr, VEXTRACTPSrr, VPEXTRDrr) +// AVX 256-bit support +ENTRY(VMOVAPSYmr, VMOVAPDYmr, VMOVDQAYmr) +ENTRY(VMOVAPSYrm, VMOVAPDYrm, VMOVDQAYrm) +ENTRY(VMOVAPSYrr, VMOVAPDYrr, VMOVDQAYrr) +ENTRY(VMOVUPSYmr, VMOVUPDYmr, VMOVDQUYmr) +ENTRY(VMOVUPSYrm, VMOVUPDYrm, VMOVDQUYrm) +ENTRY(VMOVNTPSYmr, VMOVNTPDYmr, VMOVNTDQYmr) +ENTRY(VPERMPSYrm, VPERMPSYrm, VPERMDYrm) +ENTRY(VPERMPSYrr, VPERMPSYrr, VPERMDYrr) +ENTRY(VPERMPDYmi, VPERMPDYmi, VPERMQYmi) +ENTRY(VPERMPDYri, VPERMPDYri, VPERMQYri) +// AVX512 support +ENTRY(VMOVLPSZ128mr, VMOVLPDZ128mr, VMOVPQI2QIZmr) +ENTRY(VMOVNTPSZ128mr, VMOVNTPDZ128mr, VMOVNTDQZ128mr) +ENTRY(VMOVNTPSZ256mr, VMOVNTPDZ256mr, VMOVNTDQZ256mr) +ENTRY(VMOVNTPSZmr, VMOVNTPDZmr, VMOVNTDQZmr) +ENTRY(VMOVSDZmr, VMOVSDZmr, VMOVPQI2QIZmr) +ENTRY(VMOVSSZmr, VMOVSSZmr, VMOVPDI2DIZmr) +ENTRY(VMOVSDZrm, VMOVSDZrm, VMOVQI2PQIZrm) +ENTRY(VMOVSDZrm_alt, VMOVSDZrm_alt, VMOVQI2PQIZrm) +ENTRY(VMOVSSZrm, VMOVSSZrm, VMOVDI2PDIZrm) +ENTRY(VMOVSSZrm_alt, VMOVSSZrm_alt, VMOVDI2PDIZrm) +ENTRY(VBROADCASTSSZ128rr, VBROADCASTSSZ128rr, VPBROADCASTDZ128rr) +ENTRY(VBROADCASTSSZ128rm, VBROADCASTSSZ128rm, VPBROADCASTDZ128rm) +ENTRY(VBROADCASTSSZ256rr, VBROADCASTSSZ256rr, VPBROADCASTDZ256rr) +ENTRY(VBROADCASTSSZ256rm, VBROADCASTSSZ256rm, VPBROADCASTDZ256rm) +ENTRY(VBROADCASTSSZrr, VBROADCASTSSZrr, VPBROADCASTDZrr) +ENTRY(VBROADCASTSSZrm, VBROADCASTSSZrm, VPBROADCASTDZrm) +ENTRY(VMOVDDUPZ128rr, VMOVDDUPZ128rr, VPBROADCASTQZ128rr) +ENTRY(VMOVDDUPZ128rm, VMOVDDUPZ128rm, VPBROADCASTQZ128rm) +ENTRY(VBROADCASTSDZ256rr, VBROADCASTSDZ256rr, VPBROADCASTQZ256rr) +ENTRY(VBROADCASTSDZ256rm, VBROADCASTSDZ256rm, VPBROADCASTQZ256rm) +ENTRY(VBROADCASTSDZrr, VBROADCASTSDZrr, VPBROADCASTQZrr) +ENTRY(VBROADCASTSDZrm, VBROADCASTSDZrm, VPBROADCASTQZrm) +ENTRY(VINSERTF32x4Zrr, VINSERTF32x4Zrr, VINSERTI32x4Zrr) +ENTRY(VINSERTF32x4Zrm, VINSERTF32x4Zrm, VINSERTI32x4Zrm) +ENTRY(VINSERTF32x8Zrr, VINSERTF32x8Zrr, VINSERTI32x8Zrr) +ENTRY(VINSERTF32x8Zrm, VINSERTF32x8Zrm, VINSERTI32x8Zrm) +ENTRY(VINSERTF64x2Zrr, VINSERTF64x2Zrr, VINSERTI64x2Zrr) +ENTRY(VINSERTF64x2Zrm, VINSERTF64x2Zrm, VINSERTI64x2Zrm) +ENTRY(VINSERTF64x4Zrr, VINSERTF64x4Zrr, VINSERTI64x4Zrr) +ENTRY(VINSERTF64x4Zrm, VINSERTF64x4Zrm, VINSERTI64x4Zrm) +ENTRY(VINSERTF32x4Z256rr, VINSERTF32x4Z256rr, VINSERTI32x4Z256rr) +ENTRY(VINSERTF32x4Z256rm, VINSERTF32x4Z256rm, VINSERTI32x4Z256rm) +ENTRY(VINSERTF64x2Z256rr, VINSERTF64x2Z256rr, VINSERTI64x2Z256rr) +ENTRY(VINSERTF64x2Z256rm, VINSERTF64x2Z256rm, VINSERTI64x2Z256rm) +ENTRY(VEXTRACTF32x4Zrr, VEXTRACTF32x4Zrr, VEXTRACTI32x4Zrr) +ENTRY(VEXTRACTF32x4Zmr, VEXTRACTF32x4Zmr, VEXTRACTI32x4Zmr) +ENTRY(VEXTRACTF32x8Zrr, VEXTRACTF32x8Zrr, VEXTRACTI32x8Zrr) +ENTRY(VEXTRACTF32x8Zmr, VEXTRACTF32x8Zmr, VEXTRACTI32x8Zmr) +ENTRY(VEXTRACTF64x2Zrr, VEXTRACTF64x2Zrr, VEXTRACTI64x2Zrr) +ENTRY(VEXTRACTF64x2Zmr, VEXTRACTF64x2Zmr, VEXTRACTI64x2Zmr) +ENTRY(VEXTRACTF64x4Zrr, VEXTRACTF64x4Zrr, VEXTRACTI64x4Zrr) +ENTRY(VEXTRACTF64x4Zmr, VEXTRACTF64x4Zmr, VEXTRACTI64x4Zmr) +ENTRY(VEXTRACTF32x4Z256rr, VEXTRACTF32x4Z256rr, VEXTRACTI32x4Z256rr) +ENTRY(VEXTRACTF32x4Z256mr, VEXTRACTF32x4Z256mr, VEXTRACTI32x4Z256mr) +ENTRY(VEXTRACTF64x2Z256rr, VEXTRACTF64x2Z256rr, VEXTRACTI64x2Z256rr) +ENTRY(VEXTRACTF64x2Z256mr, VEXTRACTF64x2Z256mr, VEXTRACTI64x2Z256mr) +ENTRY(VPERMILPSmi, VPERMILPSmi, VPSHUFDmi) +ENTRY(VPERMILPSri, VPERMILPSri, VPSHUFDri) +ENTRY(VPERMILPSZ128mi, VPERMILPSZ128mi, VPSHUFDZ128mi) +ENTRY(VPERMILPSZ128ri, VPERMILPSZ128ri, VPSHUFDZ128ri) +ENTRY(VPERMILPSZ256mi, VPERMILPSZ256mi, VPSHUFDZ256mi) +ENTRY(VPERMILPSZ256ri, VPERMILPSZ256ri, VPSHUFDZ256ri) +ENTRY(VPERMILPSZmi, VPERMILPSZmi, VPSHUFDZmi) +ENTRY(VPERMILPSZri, VPERMILPSZri, VPSHUFDZri) +ENTRY(VPERMPSZ256rm, VPERMPSZ256rm, VPERMDZ256rm) +ENTRY(VPERMPSZ256rr, VPERMPSZ256rr, VPERMDZ256rr) +ENTRY(VPERMPDZ256mi, VPERMPDZ256mi, VPERMQZ256mi) +ENTRY(VPERMPDZ256ri, VPERMPDZ256ri, VPERMQZ256ri) +ENTRY(VPERMPDZ256rm, VPERMPDZ256rm, VPERMQZ256rm) +ENTRY(VPERMPDZ256rr, VPERMPDZ256rr, VPERMQZ256rr) +ENTRY(VPERMPSZrm, VPERMPSZrm, VPERMDZrm) +ENTRY(VPERMPSZrr, VPERMPSZrr, VPERMDZrr) +ENTRY(VPERMPDZmi, VPERMPDZmi, VPERMQZmi) +ENTRY(VPERMPDZri, VPERMPDZri, VPERMQZri) +ENTRY(VPERMPDZrm, VPERMPDZrm, VPERMQZrm) +ENTRY(VPERMPDZrr, VPERMPDZrr, VPERMQZrr) +ENTRY(VUNPCKLPDZ256rm, VUNPCKLPDZ256rm, VPUNPCKLQDQZ256rm) +ENTRY(VUNPCKLPDZ256rr, VUNPCKLPDZ256rr, VPUNPCKLQDQZ256rr) +ENTRY(VUNPCKHPDZ256rm, VUNPCKHPDZ256rm, VPUNPCKHQDQZ256rm) +ENTRY(VUNPCKHPDZ256rr, VUNPCKHPDZ256rr, VPUNPCKHQDQZ256rr) +ENTRY(VUNPCKLPSZ256rm, VUNPCKLPSZ256rm, VPUNPCKLDQZ256rm) +ENTRY(VUNPCKLPSZ256rr, VUNPCKLPSZ256rr, VPUNPCKLDQZ256rr) +ENTRY(VUNPCKHPSZ256rm, VUNPCKHPSZ256rm, VPUNPCKHDQZ256rm) +ENTRY(VUNPCKHPSZ256rr, VUNPCKHPSZ256rr, VPUNPCKHDQZ256rr) +ENTRY(VUNPCKLPDZ128rm, VUNPCKLPDZ128rm, VPUNPCKLQDQZ128rm) +ENTRY(VMOVLHPSZrr, VUNPCKLPDZ128rr, VPUNPCKLQDQZ128rr) +ENTRY(VUNPCKHPDZ128rm, VUNPCKHPDZ128rm, VPUNPCKHQDQZ128rm) +ENTRY(VUNPCKHPDZ128rr, VUNPCKHPDZ128rr, VPUNPCKHQDQZ128rr) +ENTRY(VUNPCKLPSZ128rm, VUNPCKLPSZ128rm, VPUNPCKLDQZ128rm) +ENTRY(VUNPCKLPSZ128rr, VUNPCKLPSZ128rr, VPUNPCKLDQZ128rr) +ENTRY(VUNPCKHPSZ128rm, VUNPCKHPSZ128rm, VPUNPCKHDQZ128rm) +ENTRY(VUNPCKHPSZ128rr, VUNPCKHPSZ128rr, VPUNPCKHDQZ128rr) +ENTRY(VUNPCKLPDZrm, VUNPCKLPDZrm, VPUNPCKLQDQZrm) +ENTRY(VUNPCKLPDZrr, VUNPCKLPDZrr, VPUNPCKLQDQZrr) +ENTRY(VUNPCKHPDZrm, VUNPCKHPDZrm, VPUNPCKHQDQZrm) +ENTRY(VUNPCKHPDZrr, VUNPCKHPDZrr, VPUNPCKHQDQZrr) +ENTRY(VUNPCKLPSZrm, VUNPCKLPSZrm, VPUNPCKLDQZrm) +ENTRY(VUNPCKLPSZrr, VUNPCKLPSZrr, VPUNPCKLDQZrr) +ENTRY(VUNPCKHPSZrm, VUNPCKHPSZrm, VPUNPCKHDQZrm) +ENTRY(VUNPCKHPSZrr, VUNPCKHPSZrr, VPUNPCKHDQZrr) +ENTRY(VEXTRACTPSZmr, VEXTRACTPSZmr, VPEXTRDZmr) +ENTRY(VEXTRACTPSZrr, VEXTRACTPSZrr, VPEXTRDZrr) +}; + +static const uint16_t ReplaceableInstrsAVX2[][3] = { +// PackedSingle, PackedDouble, PackedInt +ENTRY(VANDNPSYrm, VANDNPDYrm, VPANDNYrm) +ENTRY(VANDNPSYrr, VANDNPDYrr, VPANDNYrr) +ENTRY(VANDPSYrm, VANDPDYrm, VPANDYrm) +ENTRY(VANDPSYrr, VANDPDYrr, VPANDYrr) +ENTRY(VORPSYrm, VORPDYrm, VPORYrm) +ENTRY(VORPSYrr, VORPDYrr, VPORYrr) +ENTRY(VXORPSYrm, VXORPDYrm, VPXORYrm) +ENTRY(VXORPSYrr, VXORPDYrr, VPXORYrr) +ENTRY(VPERM2F128rm, VPERM2F128rm, VPERM2I128rm) +ENTRY(VPERM2F128rr, VPERM2F128rr, VPERM2I128rr) +ENTRY(VBROADCASTSSrm, VBROADCASTSSrm, VPBROADCASTDrm) +ENTRY(VBROADCASTSSrr, VBROADCASTSSrr, VPBROADCASTDrr) +ENTRY(VMOVDDUPrm, VMOVDDUPrm, VPBROADCASTQrm) +ENTRY(VMOVDDUPrr, VMOVDDUPrr, VPBROADCASTQrr) +ENTRY(VBROADCASTSSYrr, VBROADCASTSSYrr, VPBROADCASTDYrr) +ENTRY(VBROADCASTSSYrm, VBROADCASTSSYrm, VPBROADCASTDYrm) +ENTRY(VBROADCASTSDYrr, VBROADCASTSDYrr, VPBROADCASTQYrr) +ENTRY(VBROADCASTSDYrm, VBROADCASTSDYrm, VPBROADCASTQYrm) +ENTRY(VBROADCASTF128, VBROADCASTF128, VBROADCASTI128) +ENTRY(VBLENDPSYrri, VBLENDPSYrri, VPBLENDDYrri) +ENTRY(VBLENDPSYrmi, VBLENDPSYrmi, VPBLENDDYrmi) +ENTRY(VPERMILPSYmi, VPERMILPSYmi, VPSHUFDYmi) +ENTRY(VPERMILPSYri, VPERMILPSYri, VPSHUFDYri) +ENTRY(VUNPCKLPDYrm, VUNPCKLPDYrm, VPUNPCKLQDQYrm) +ENTRY(VUNPCKLPDYrr, VUNPCKLPDYrr, VPUNPCKLQDQYrr) +ENTRY(VUNPCKHPDYrm, VUNPCKHPDYrm, VPUNPCKHQDQYrm) +ENTRY(VUNPCKHPDYrr, VUNPCKHPDYrr, VPUNPCKHQDQYrr) +ENTRY(VUNPCKLPSYrm, VUNPCKLPSYrm, VPUNPCKLDQYrm) +ENTRY(VUNPCKLPSYrr, VUNPCKLPSYrr, VPUNPCKLDQYrr) +ENTRY(VUNPCKHPSYrm, VUNPCKHPSYrm, VPUNPCKHDQYrm) +ENTRY(VUNPCKHPSYrr, VUNPCKHPSYrr, VPUNPCKHDQYrr) +}; + +static const uint16_t ReplaceableInstrsFP[][3] = { +// PackedSingle, PackedDouble +ENTRY(MOVLPSrm, MOVLPDrm, INSTRUCTION_LIST_END) +ENTRY(MOVHPSrm, MOVHPDrm, INSTRUCTION_LIST_END) +ENTRY(MOVHPSmr, MOVHPDmr, INSTRUCTION_LIST_END) +ENTRY(VMOVLPSrm, VMOVLPDrm, INSTRUCTION_LIST_END) +ENTRY(VMOVHPSrm, VMOVHPDrm, INSTRUCTION_LIST_END) +ENTRY(VMOVHPSmr, VMOVHPDmr, INSTRUCTION_LIST_END) +ENTRY(VMOVLPSZ128rm, VMOVLPDZ128rm, INSTRUCTION_LIST_END) +ENTRY(VMOVHPSZ128rm, VMOVHPDZ128rm, INSTRUCTION_LIST_END) +ENTRY(VMOVHPSZ128mr, VMOVHPDZ128mr, INSTRUCTION_LIST_END) +}; + +static const uint16_t ReplaceableInstrsAVX2InsertExtract[][3] = { +// PackedSingle, PackedDouble, PackedInt +ENTRY(VEXTRACTF128mr, VEXTRACTF128mr, VEXTRACTI128mr) +ENTRY(VEXTRACTF128rr, VEXTRACTF128rr, VEXTRACTI128rr) +ENTRY(VINSERTF128rm, VINSERTF128rm, VINSERTI128rm) +ENTRY(VINSERTF128rr, VINSERTF128rr, VINSERTI128rr) +}; + +// NOTE: These should only be used by the custom domain methods. +static const uint16_t ReplaceableBlendInstrs[][3] = { +//PackedSingle, PackedDouble, PackedInt +ENTRY(BLENDPSrmi, BLENDPDrmi, PBLENDWrmi) +ENTRY(BLENDPSrri, BLENDPDrri, PBLENDWrri) +ENTRY(VBLENDPSrmi, VBLENDPDrmi, VPBLENDWrmi) +ENTRY(VBLENDPSrri, VBLENDPDrri, VPBLENDWrri) +ENTRY(VBLENDPSYrmi, VBLENDPDYrmi, VPBLENDWYrmi) +ENTRY(VBLENDPSYrri, VBLENDPDYrri, VPBLENDWYrri) +}; + +static const uint16_t ReplaceableBlendAVX2Instrs[][3] = { +// PackedSingle, PackedDouble, PackedInt +ENTRY(VBLENDPSrmi, VBLENDPDrmi, VPBLENDDrmi) +ENTRY(VBLENDPSrri, VBLENDPDrri, VPBLENDDrri) +ENTRY(VBLENDPSYrmi, VBLENDPDYrmi, VPBLENDDYrmi) +ENTRY(VBLENDPSYrri, VBLENDPDYrri, VPBLENDDYrri) +}; + +#undef ENTRY +#define ENTRY(A, B, C, D) {X86::A, X86::B, X86::C, X86::D}, +static const uint16_t ReplaceableInstrsAVX512[][4] = { +// Two integer columns for 64-bit and 32-bit elements. +//PackedSingle, PackedDouble, PackedInt, PackedInt +ENTRY(VMOVAPSZ128mr, VMOVAPDZ128mr, VMOVDQA64Z128mr, VMOVDQA32Z128mr) +ENTRY(VMOVAPSZ128rm, VMOVAPDZ128rm, VMOVDQA64Z128rm, VMOVDQA32Z128rm) +ENTRY(VMOVAPSZ128rr, VMOVAPDZ128rr, VMOVDQA64Z128rr, VMOVDQA32Z128rr) +ENTRY(VMOVUPSZ128mr, VMOVUPDZ128mr, VMOVDQU64Z128mr, VMOVDQU32Z128mr) +ENTRY(VMOVUPSZ128rm, VMOVUPDZ128rm, VMOVDQU64Z128rm, VMOVDQU32Z128rm) +ENTRY(VMOVAPSZ256mr, VMOVAPDZ256mr, VMOVDQA64Z256mr, VMOVDQA32Z256mr) +ENTRY(VMOVAPSZ256rm, VMOVAPDZ256rm, VMOVDQA64Z256rm, VMOVDQA32Z256rm) +ENTRY(VMOVAPSZ256rr, VMOVAPDZ256rr, VMOVDQA64Z256rr, VMOVDQA32Z256rr) +ENTRY(VMOVUPSZ256mr, VMOVUPDZ256mr, VMOVDQU64Z256mr, VMOVDQU32Z256mr) +ENTRY(VMOVUPSZ256rm, VMOVUPDZ256rm, VMOVDQU64Z256rm, VMOVDQU32Z256rm) +ENTRY(VMOVAPSZmr, VMOVAPDZmr, VMOVDQA64Zmr, VMOVDQA32Zmr) +ENTRY(VMOVAPSZrm, VMOVAPDZrm, VMOVDQA64Zrm, VMOVDQA32Zrm) +ENTRY(VMOVAPSZrr, VMOVAPDZrr, VMOVDQA64Zrr, VMOVDQA32Zrr) +ENTRY(VMOVUPSZmr, VMOVUPDZmr, VMOVDQU64Zmr, VMOVDQU32Zmr) +ENTRY(VMOVUPSZrm, VMOVUPDZrm, VMOVDQU64Zrm, VMOVDQU32Zrm) +}; + +static const uint16_t ReplaceableInstrsAVX512DQ[][4] = { +// Two integer columns for 64-bit and 32-bit elements. +// PackedSingle, PackedDouble, PackedInt, PackedInt +ENTRY(VANDNPSZ128rm, VANDNPDZ128rm, VPANDNQZ128rm, VPANDNDZ128rm) +ENTRY(VANDNPSZ128rr, VANDNPDZ128rr, VPANDNQZ128rr, VPANDNDZ128rr) +ENTRY(VANDPSZ128rm, VANDPDZ128rm, VPANDQZ128rm, VPANDDZ128rm) +ENTRY(VANDPSZ128rr, VANDPDZ128rr, VPANDQZ128rr, VPANDDZ128rr) +ENTRY(VORPSZ128rm, VORPDZ128rm, VPORQZ128rm, VPORDZ128rm) +ENTRY(VORPSZ128rr, VORPDZ128rr, VPORQZ128rr, VPORDZ128rr) +ENTRY(VXORPSZ128rm, VXORPDZ128rm, VPXORQZ128rm, VPXORDZ128rm) +ENTRY(VXORPSZ128rr, VXORPDZ128rr, VPXORQZ128rr, VPXORDZ128rr) +ENTRY(VANDNPSZ256rm, VANDNPDZ256rm, VPANDNQZ256rm, VPANDNDZ256rm) +ENTRY(VANDNPSZ256rr, VANDNPDZ256rr, VPANDNQZ256rr, VPANDNDZ256rr) +ENTRY(VANDPSZ256rm, VANDPDZ256rm, VPANDQZ256rm, VPANDDZ256rm) +ENTRY(VANDPSZ256rr, VANDPDZ256rr, VPANDQZ256rr, VPANDDZ256rr) +ENTRY(VORPSZ256rm, VORPDZ256rm, VPORQZ256rm, VPORDZ256rm) +ENTRY(VORPSZ256rr, VORPDZ256rr, VPORQZ256rr, VPORDZ256rr) +ENTRY(VXORPSZ256rm, VXORPDZ256rm, VPXORQZ256rm, VPXORDZ256rm) +ENTRY(VXORPSZ256rr, VXORPDZ256rr, VPXORQZ256rr, VPXORDZ256rr) +ENTRY(VANDNPSZrm, VANDNPDZrm, VPANDNQZrm, VPANDNDZrm) +ENTRY(VANDNPSZrr, VANDNPDZrr, VPANDNQZrr, VPANDNDZrr) +ENTRY(VANDPSZrm, VANDPDZrm, VPANDQZrm, VPANDDZrm) +ENTRY(VANDPSZrr, VANDPDZrr, VPANDQZrr, VPANDDZrr) +ENTRY(VORPSZrm, VORPDZrm, VPORQZrm, VPORDZrm) +ENTRY(VORPSZrr, VORPDZrr, VPORQZrr, VPORDZrr) +ENTRY(VXORPSZrm, VXORPDZrm, VPXORQZrm, VPXORDZrm) +ENTRY(VXORPSZrr, VXORPDZrr, VPXORQZrr, VPXORDZrr) +}; + +static const uint16_t ReplaceableInstrsAVX512DQMasked[][4] = { +// Two integer columns for 64-bit and 32-bit elements. +// PackedSingle, PackedDouble, PackedInt, PackedInt +ENTRY(VANDNPSZ128rmk, VANDNPDZ128rmk, VPANDNQZ128rmk, VPANDNDZ128rmk) +ENTRY(VANDNPSZ128rmkz, VANDNPDZ128rmkz, VPANDNQZ128rmkz, VPANDNDZ128rmkz) +ENTRY(VANDNPSZ128rrk, VANDNPDZ128rrk, VPANDNQZ128rrk, VPANDNDZ128rrk) +ENTRY(VANDNPSZ128rrkz, VANDNPDZ128rrkz, VPANDNQZ128rrkz, VPANDNDZ128rrkz) +ENTRY(VANDPSZ128rmk, VANDPDZ128rmk, VPANDQZ128rmk, VPANDDZ128rmk) +ENTRY(VANDPSZ128rmkz, VANDPDZ128rmkz, VPANDQZ128rmkz, VPANDDZ128rmkz) +ENTRY(VANDPSZ128rrk, VANDPDZ128rrk, VPANDQZ128rrk, VPANDDZ128rrk) +ENTRY(VANDPSZ128rrkz, VANDPDZ128rrkz, VPANDQZ128rrkz, VPANDDZ128rrkz) +ENTRY(VORPSZ128rmk, VORPDZ128rmk, VPORQZ128rmk, VPORDZ128rmk) +ENTRY(VORPSZ128rmkz, VORPDZ128rmkz, VPORQZ128rmkz, VPORDZ128rmkz) +ENTRY(VORPSZ128rrk, VORPDZ128rrk, VPORQZ128rrk, VPORDZ128rrk) +ENTRY(VORPSZ128rrkz, VORPDZ128rrkz, VPORQZ128rrkz, VPORDZ128rrkz) +ENTRY(VXORPSZ128rmk, VXORPDZ128rmk, VPXORQZ128rmk, VPXORDZ128rmk) +ENTRY(VXORPSZ128rmkz, VXORPDZ128rmkz, VPXORQZ128rmkz, VPXORDZ128rmkz) +ENTRY(VXORPSZ128rrk, VXORPDZ128rrk, VPXORQZ128rrk, VPXORDZ128rrk) +ENTRY(VXORPSZ128rrkz, VXORPDZ128rrkz, VPXORQZ128rrkz, VPXORDZ128rrkz) +ENTRY(VANDNPSZ256rmk, VANDNPDZ256rmk, VPANDNQZ256rmk, VPANDNDZ256rmk) +ENTRY(VANDNPSZ256rmkz, VANDNPDZ256rmkz, VPANDNQZ256rmkz, VPANDNDZ256rmkz) +ENTRY(VANDNPSZ256rrk, VANDNPDZ256rrk, VPANDNQZ256rrk, VPANDNDZ256rrk) +ENTRY(VANDNPSZ256rrkz, VANDNPDZ256rrkz, VPANDNQZ256rrkz, VPANDNDZ256rrkz) +ENTRY(VANDPSZ256rmk, VANDPDZ256rmk, VPANDQZ256rmk, VPANDDZ256rmk) +ENTRY(VANDPSZ256rmkz, VANDPDZ256rmkz, VPANDQZ256rmkz, VPANDDZ256rmkz) +ENTRY(VANDPSZ256rrk, VANDPDZ256rrk, VPANDQZ256rrk, VPANDDZ256rrk) +ENTRY(VANDPSZ256rrkz, VANDPDZ256rrkz, VPANDQZ256rrkz, VPANDDZ256rrkz) +ENTRY(VORPSZ256rmk, VORPDZ256rmk, VPORQZ256rmk, VPORDZ256rmk) +ENTRY(VORPSZ256rmkz, VORPDZ256rmkz, VPORQZ256rmkz, VPORDZ256rmkz) +ENTRY(VORPSZ256rrk, VORPDZ256rrk, VPORQZ256rrk, VPORDZ256rrk) +ENTRY(VORPSZ256rrkz, VORPDZ256rrkz, VPORQZ256rrkz, VPORDZ256rrkz) +ENTRY(VXORPSZ256rmk, VXORPDZ256rmk, VPXORQZ256rmk, VPXORDZ256rmk) +ENTRY(VXORPSZ256rmkz, VXORPDZ256rmkz, VPXORQZ256rmkz, VPXORDZ256rmkz) +ENTRY(VXORPSZ256rrk, VXORPDZ256rrk, VPXORQZ256rrk, VPXORDZ256rrk) +ENTRY(VXORPSZ256rrkz, VXORPDZ256rrkz, VPXORQZ256rrkz, VPXORDZ256rrkz) +ENTRY(VANDNPSZrmk, VANDNPDZrmk, VPANDNQZrmk, VPANDNDZrmk) +ENTRY(VANDNPSZrmkz, VANDNPDZrmkz, VPANDNQZrmkz, VPANDNDZrmkz) +ENTRY(VANDNPSZrrk, VANDNPDZrrk, VPANDNQZrrk, VPANDNDZrrk) +ENTRY(VANDNPSZrrkz, VANDNPDZrrkz, VPANDNQZrrkz, VPANDNDZrrkz) +ENTRY(VANDPSZrmk, VANDPDZrmk, VPANDQZrmk, VPANDDZrmk) +ENTRY(VANDPSZrmkz, VANDPDZrmkz, VPANDQZrmkz, VPANDDZrmkz) +ENTRY(VANDPSZrrk, VANDPDZrrk, VPANDQZrrk, VPANDDZrrk) +ENTRY(VANDPSZrrkz, VANDPDZrrkz, VPANDQZrrkz, VPANDDZrrkz) +ENTRY(VORPSZrmk, VORPDZrmk, VPORQZrmk, VPORDZrmk) +ENTRY(VORPSZrmkz, VORPDZrmkz, VPORQZrmkz, VPORDZrmkz) +ENTRY(VORPSZrrk, VORPDZrrk, VPORQZrrk, VPORDZrrk) +ENTRY(VORPSZrrkz, VORPDZrrkz, VPORQZrrkz, VPORDZrrkz) +ENTRY(VXORPSZrmk, VXORPDZrmk, VPXORQZrmk, VPXORDZrmk) +ENTRY(VXORPSZrmkz, VXORPDZrmkz, VPXORQZrmkz, VPXORDZrmkz) +ENTRY(VXORPSZrrk, VXORPDZrrk, VPXORQZrrk, VPXORDZrrk) +ENTRY(VXORPSZrrkz, VXORPDZrrkz, VPXORQZrrkz, VPXORDZrrkz) +// Broadcast loads can be handled the same as masked operations to avoid +// changing element size. +ENTRY(VANDNPSZ128rmb, VANDNPDZ128rmb, VPANDNQZ128rmb, VPANDNDZ128rmb) +ENTRY(VANDPSZ128rmb, VANDPDZ128rmb, VPANDQZ128rmb, VPANDDZ128rmb) +ENTRY(VORPSZ128rmb, VORPDZ128rmb, VPORQZ128rmb, VPORDZ128rmb) +ENTRY(VXORPSZ128rmb, VXORPDZ128rmb, VPXORQZ128rmb, VPXORDZ128rmb) +ENTRY(VANDNPSZ256rmb, VANDNPDZ256rmb, VPANDNQZ256rmb, VPANDNDZ256rmb) +ENTRY(VANDPSZ256rmb, VANDPDZ256rmb, VPANDQZ256rmb, VPANDDZ256rmb) +ENTRY(VORPSZ256rmb, VORPDZ256rmb, VPORQZ256rmb, VPORDZ256rmb) +ENTRY(VXORPSZ256rmb, VXORPDZ256rmb, VPXORQZ256rmb, VPXORDZ256rmb) +ENTRY(VANDNPSZrmb, VANDNPDZrmb, VPANDNQZrmb, VPANDNDZrmb) +ENTRY(VANDPSZrmb, VANDPDZrmb, VPANDQZrmb, VPANDDZrmb) +ENTRY(VANDPSZrmb, VANDPDZrmb, VPANDQZrmb, VPANDDZrmb) +ENTRY(VORPSZrmb, VORPDZrmb, VPORQZrmb, VPORDZrmb) +ENTRY(VXORPSZrmb, VXORPDZrmb, VPXORQZrmb, VPXORDZrmb) +ENTRY(VANDNPSZ128rmbk, VANDNPDZ128rmbk, VPANDNQZ128rmbk, VPANDNDZ128rmbk) +ENTRY(VANDPSZ128rmbk, VANDPDZ128rmbk, VPANDQZ128rmbk, VPANDDZ128rmbk) +ENTRY(VORPSZ128rmbk, VORPDZ128rmbk, VPORQZ128rmbk, VPORDZ128rmbk) +ENTRY(VXORPSZ128rmbk, VXORPDZ128rmbk, VPXORQZ128rmbk, VPXORDZ128rmbk) +ENTRY(VANDNPSZ256rmbk, VANDNPDZ256rmbk, VPANDNQZ256rmbk, VPANDNDZ256rmbk) +ENTRY(VANDPSZ256rmbk, VANDPDZ256rmbk, VPANDQZ256rmbk, VPANDDZ256rmbk) +ENTRY(VORPSZ256rmbk, VORPDZ256rmbk, VPORQZ256rmbk, VPORDZ256rmbk) +ENTRY(VXORPSZ256rmbk, VXORPDZ256rmbk, VPXORQZ256rmbk, VPXORDZ256rmbk) +ENTRY(VANDNPSZrmbk, VANDNPDZrmbk, VPANDNQZrmbk, VPANDNDZrmbk) +ENTRY(VANDPSZrmbk, VANDPDZrmbk, VPANDQZrmbk, VPANDDZrmbk) +ENTRY(VANDPSZrmbk, VANDPDZrmbk, VPANDQZrmbk, VPANDDZrmbk) +ENTRY(VORPSZrmbk, VORPDZrmbk, VPORQZrmbk, VPORDZrmbk) +ENTRY(VXORPSZrmbk, VXORPDZrmbk, VPXORQZrmbk, VPXORDZrmbk) +ENTRY(VANDNPSZ128rmbkz, VANDNPDZ128rmbkz, VPANDNQZ128rmbkz, VPANDNDZ128rmbkz) +ENTRY(VANDPSZ128rmbkz, VANDPDZ128rmbkz, VPANDQZ128rmbkz, VPANDDZ128rmbkz) +ENTRY(VORPSZ128rmbkz, VORPDZ128rmbkz, VPORQZ128rmbkz, VPORDZ128rmbkz) +ENTRY(VXORPSZ128rmbkz, VXORPDZ128rmbkz, VPXORQZ128rmbkz, VPXORDZ128rmbkz) +ENTRY(VANDNPSZ256rmbkz, VANDNPDZ256rmbkz, VPANDNQZ256rmbkz, VPANDNDZ256rmbkz) +ENTRY(VANDPSZ256rmbkz, VANDPDZ256rmbkz, VPANDQZ256rmbkz, VPANDDZ256rmbkz) +ENTRY(VORPSZ256rmbkz, VORPDZ256rmbkz, VPORQZ256rmbkz, VPORDZ256rmbkz) +ENTRY(VXORPSZ256rmbkz, VXORPDZ256rmbkz, VPXORQZ256rmbkz, VPXORDZ256rmbkz) +ENTRY(VANDNPSZrmbkz, VANDNPDZrmbkz, VPANDNQZrmbkz, VPANDNDZrmbkz) +ENTRY(VANDPSZrmbkz, VANDPDZrmbkz, VPANDQZrmbkz, VPANDDZrmbkz) +ENTRY(VANDPSZrmbkz, VANDPDZrmbkz, VPANDQZrmbkz, VPANDDZrmbkz) +ENTRY(VORPSZrmbkz, VORPDZrmbkz, VPORQZrmbkz, VPORDZrmbkz) +ENTRY(VXORPSZrmbkz, VXORPDZrmbkz, VPXORQZrmbkz, VPXORDZrmbkz) +}; + +// Special table for changing EVEX logic instructions to VEX. +// TODO: Should we run EVEX->VEX earlier? +static const uint16_t ReplaceableCustomAVX512LogicInstrs[][4] = { +// Two integer columns for 64-bit and 32-bit elements. +// PackedSingle, PackedDouble, PackedInt, PackedInt +ENTRY(VANDNPSrm, VANDNPDrm, VPANDNQZ128rm, VPANDNDZ128rm) +ENTRY(VANDNPSrr, VANDNPDrr, VPANDNQZ128rr, VPANDNDZ128rr) +ENTRY(VANDPSrm, VANDPDrm, VPANDQZ128rm, VPANDDZ128rm) +ENTRY(VANDPSrr, VANDPDrr, VPANDQZ128rr, VPANDDZ128rr) +ENTRY(VORPSrm, VORPDrm, VPORQZ128rm, VPORDZ128rm) +ENTRY(VORPSrr, VORPDrr, VPORQZ128rr, VPORDZ128rr) +ENTRY(VXORPSrm, VXORPDrm, VPXORQZ128rm, VPXORDZ128rm) +ENTRY(VXORPSrr, VXORPDrr, VPXORQZ128rr, VPXORDZ128rr) +ENTRY(VANDNPSYrm, VANDNPDYrm, VPANDNQZ256rm, VPANDNDZ256rm) +ENTRY(VANDNPSYrr, VANDNPDYrr, VPANDNQZ256rr, VPANDNDZ256rr) +ENTRY(VANDPSYrm, VANDPDYrm, VPANDQZ256rm, VPANDDZ256rm) +ENTRY(VANDPSYrr, VANDPDYrr, VPANDQZ256rr, VPANDDZ256rr) +ENTRY(VORPSYrm, VORPDYrm, VPORQZ256rm, VPORDZ256rm) +ENTRY(VORPSYrr, VORPDYrr, VPORQZ256rr, VPORDZ256rr) +ENTRY(VXORPSYrm, VXORPDYrm, VPXORQZ256rm, VPXORDZ256rm) +ENTRY(VXORPSYrr, VXORPDYrr, VPXORQZ256rr, VPXORDZ256rr) +}; -- GitLab From d56e0d07cc5ee8e334fd1ad403eef0b1a771384f Mon Sep 17 00:00:00 2001 From: Romaric Jodin <89833130+rjodinchr@users.noreply.github.com> Date: Fri, 1 Dec 2023 08:34:44 +0100 Subject: [PATCH 104/699] clang/OpenCL: set sqrt fp accuracy on call to Z4sqrt (#66651) This is reverting the previous implementation to avoid adding inline function in opencl headers. This was breaking clspv flow google/clspv#1231, while https://reviews.llvm.org/D156743 mentioned that just decorating the call node with `!pfmath` was enough. This PR is implementing this idea. The test has been updated with this implementation. --- clang/lib/CodeGen/CGCall.cpp | 4 + clang/lib/Headers/opencl-c-base.h | 58 ----------- clang/lib/Headers/opencl-c.h | 26 +++++ clang/lib/Sema/OpenCLBuiltins.td | 5 +- clang/test/CodeGenOpenCL/sqrt-fpmath.cl | 124 ++++++++++-------------- 5 files changed, 82 insertions(+), 135 deletions(-) diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp index 4c2577126e48..a24aeea7ae32 100644 --- a/clang/lib/CodeGen/CGCall.cpp +++ b/clang/lib/CodeGen/CGCall.cpp @@ -5608,6 +5608,10 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo &CallInfo, BundleList); EmitBlock(Cont); } + if (CI->getCalledFunction() && CI->getCalledFunction()->hasName() && + CI->getCalledFunction()->getName().startswith("_Z4sqrt")) { + SetSqrtFPAccuracy(CI); + } if (callOrInvoke) *callOrInvoke = CI; diff --git a/clang/lib/Headers/opencl-c-base.h b/clang/lib/Headers/opencl-c-base.h index d56e5ceae652..2494f6213fc5 100644 --- a/clang/lib/Headers/opencl-c-base.h +++ b/clang/lib/Headers/opencl-c-base.h @@ -819,64 +819,6 @@ int printf(__constant const char* st, ...) __attribute__((format(printf, 1, 2))) #endif // cl_intel_device_side_avc_motion_estimation -/** - * Compute square root. - * - * Provide inline implementations using the builtin so that we get appropriate - * !fpmath based on -cl-fp32-correctly-rounded-divide-sqrt, attached to - * llvm.sqrt. The implementation should still provide an external definition. - */ -#define __ovld __attribute__((overloadable)) -#define __cnfn __attribute__((const)) - -inline float __ovld __cnfn sqrt(float __x) { - return __builtin_elementwise_sqrt(__x); -} - -inline float2 __ovld __cnfn sqrt(float2 __x) { - return __builtin_elementwise_sqrt(__x); -} - -inline float3 __ovld __cnfn sqrt(float3 __x) { - return __builtin_elementwise_sqrt(__x); -} - -inline float4 __ovld __cnfn sqrt(float4 __x) { - return __builtin_elementwise_sqrt(__x); -} - -inline float8 __ovld __cnfn sqrt(float8 __x) { - return __builtin_elementwise_sqrt(__x); -} - -inline float16 __ovld __cnfn sqrt(float16 __x) { - return __builtin_elementwise_sqrt(__x); -} - -// We only really want to define the float variants here. However -// -fdeclare-opencl-builtins will not work if some overloads are already - // provided in the base header, so provide all overloads here. - -#ifdef cl_khr_fp64 -double __ovld __cnfn sqrt(double); -double2 __ovld __cnfn sqrt(double2); -double3 __ovld __cnfn sqrt(double3); -double4 __ovld __cnfn sqrt(double4); -double8 __ovld __cnfn sqrt(double8); -double16 __ovld __cnfn sqrt(double16); -#endif //cl_khr_fp64 -#ifdef cl_khr_fp16 -half __ovld __cnfn sqrt(half); -half2 __ovld __cnfn sqrt(half2); -half3 __ovld __cnfn sqrt(half3); -half4 __ovld __cnfn sqrt(half4); -half8 __ovld __cnfn sqrt(half8); -half16 __ovld __cnfn sqrt(half16); -#endif //cl_khr_fp16 - -#undef __cnfn -#undef __ovld - // Disable any extensions we may have enabled previously. #pragma OPENCL EXTENSION all : disable diff --git a/clang/lib/Headers/opencl-c.h b/clang/lib/Headers/opencl-c.h index 1efbbf8f8ee6..288bb18bc654 100644 --- a/clang/lib/Headers/opencl-c.h +++ b/clang/lib/Headers/opencl-c.h @@ -8496,6 +8496,32 @@ half8 __ovld __cnfn sinpi(half8); half16 __ovld __cnfn sinpi(half16); #endif //cl_khr_fp16 +/** + * Compute square root. + */ +float __ovld __cnfn sqrt(float); +float2 __ovld __cnfn sqrt(float2); +float3 __ovld __cnfn sqrt(float3); +float4 __ovld __cnfn sqrt(float4); +float8 __ovld __cnfn sqrt(float8); +float16 __ovld __cnfn sqrt(float16); +#ifdef cl_khr_fp64 +double __ovld __cnfn sqrt(double); +double2 __ovld __cnfn sqrt(double2); +double3 __ovld __cnfn sqrt(double3); +double4 __ovld __cnfn sqrt(double4); +double8 __ovld __cnfn sqrt(double8); +double16 __ovld __cnfn sqrt(double16); +#endif //cl_khr_fp64 +#ifdef cl_khr_fp16 +half __ovld __cnfn sqrt(half); +half2 __ovld __cnfn sqrt(half2); +half3 __ovld __cnfn sqrt(half3); +half4 __ovld __cnfn sqrt(half4); +half8 __ovld __cnfn sqrt(half8); +half16 __ovld __cnfn sqrt(half16); +#endif //cl_khr_fp16 + /** * Compute tangent. */ diff --git a/clang/lib/Sema/OpenCLBuiltins.td b/clang/lib/Sema/OpenCLBuiltins.td index 9db450281912..0cceba090bd8 100644 --- a/clang/lib/Sema/OpenCLBuiltins.td +++ b/clang/lib/Sema/OpenCLBuiltins.td @@ -563,15 +563,12 @@ foreach name = ["acos", "acosh", "acospi", "log", "log2", "log10", "log1p", "logb", "rint", "round", "rsqrt", "sin", "sinh", "sinpi", + "sqrt", "tan", "tanh", "tanpi", "tgamma", "trunc", "lgamma"] in { def : Builtin; } - -// sqrt is handled in opencl-c-base.h to handle -// -cl-fp32-correctly-rounded-divide-sqrt. - foreach name = ["nan"] in { def : Builtin; def : Builtin; diff --git a/clang/test/CodeGenOpenCL/sqrt-fpmath.cl b/clang/test/CodeGenOpenCL/sqrt-fpmath.cl index df30085cba2e..7afde7f91bdf 100644 --- a/clang/test/CodeGenOpenCL/sqrt-fpmath.cl +++ b/clang/test/CodeGenOpenCL/sqrt-fpmath.cl @@ -3,11 +3,15 @@ // depending on -cl-fp32-correctly-rounded-divide-sqrt // Test with -fdeclare-opencl-builtins -// RUN: %clang_cc1 -disable-llvm-passes -triple amdgcn-unknown-unknown -fdeclare-opencl-builtins -finclude-default-header -S -emit-llvm -o - %s | FileCheck -check-prefixes=CHECK,DEFAULT %s -// RUN: %clang_cc1 -disable-llvm-passes -triple amdgcn-unknown-unknown -fdeclare-opencl-builtins -finclude-default-header -cl-fp32-correctly-rounded-divide-sqrt -S -emit-llvm -o - %s | FileCheck -check-prefixes=CHECK,CORRECTLYROUNDED %s +// RUN: %clang_cc1 -disable-llvm-passes -triple amdgcn-unknown-unknown -fdeclare-opencl-builtins -finclude-default-header -S -emit-llvm -o %t.ll %s +// RUN: FileCheck -check-prefixes=CHECK,DEFAULT %s < %t.ll +// RUN: %clang_cc1 -disable-llvm-passes -triple amdgcn-unknown-unknown -fdeclare-opencl-builtins -finclude-default-header -cl-fp32-correctly-rounded-divide-sqrt -S -emit-llvm -o %t.ll %s +// RUN: FileCheck -check-prefixes=CHECK,CORRECTLYROUNDED %s < %t.ll -// RUN: %clang_cc1 -disable-llvm-passes -triple amdgcn-unknown-unknown -fdeclare-opencl-builtins -finclude-default-header -cl-unsafe-math-optimizations -S -emit-llvm -o - %s | FileCheck -check-prefixes=CHECK,DEFAULT-UNSAFE %s -// RUN: %clang_cc1 -disable-llvm-passes -triple amdgcn-unknown-unknown -fdeclare-opencl-builtins -finclude-default-header -cl-fp32-correctly-rounded-divide-sqrt -cl-unsafe-math-optimizations -S -emit-llvm -o - %s | FileCheck -check-prefixes=CHECK,CORRECTLYROUNDED-UNSAFE %s +// RUN: %clang_cc1 -disable-llvm-passes -triple amdgcn-unknown-unknown -fdeclare-opencl-builtins -finclude-default-header -cl-unsafe-math-optimizations -S -emit-llvm -o %t.ll %s +// RUN: FileCheck -check-prefixes=CHECK,DEFAULT-UNSAFE %s < %t.ll +// RUN: %clang_cc1 -disable-llvm-passes -triple amdgcn-unknown-unknown -fdeclare-opencl-builtins -finclude-default-header -cl-fp32-correctly-rounded-divide-sqrt -cl-unsafe-math-optimizations -S -emit-llvm -o %t.ll %s +// RUN: FileCheck -check-prefixes=CHECK,CORRECTLYROUNDED-UNSAFE %s < %t.ll // Test without -fdeclare-opencl-builtins // RUN: %clang_cc1 -disable-llvm-passes -triple amdgcn-unknown-unknown -finclude-default-header -S -emit-llvm -o - %s | FileCheck -check-prefixes=CHECK,DEFAULT %s @@ -19,183 +23,157 @@ #pragma OPENCL EXTENSION cl_khr_fp16 : enable // CHECK-LABEL: define {{.*}} float @call_sqrt_f32( -// CHECK: call {{.*}} float @_Z4sqrtf(float noundef %{{.+}}) #{{[0-9]+$}} +// DEFAULT: call float @_Z4sqrtf(float noundef %{{.+}}) #{{[0-9]+}}, !fpmath [[FPMATH:\![0-9]+]]{{$}} +// CORRECTLYROUNDED: call float @_Z4sqrtf(float noundef %{{.+}}) #{{[0-9]+}}{{$}} + +// DEFAULT-UNSAFE: call reassoc nsz arcp contract afn float @_Z4sqrtf(float noundef %{{.+}}) #{{[0-9]+}}, !fpmath [[FPMATH:\![0-9]+]]{{$}} +// CORRECTLYROUNDED-UNSAFE: call reassoc nsz arcp contract afn float @_Z4sqrtf(float noundef %{{.+}}) #{{[0-9]+}}{{$}} float call_sqrt_f32(float x) { return sqrt(x); } -// CHECK-LABEL: define available_externally float @_Z4sqrtf(float noundef %__x) -// DEFAULT: call float @llvm.sqrt.f32(float %{{.+}}), !fpmath [[$FPMATH:![0-9]+]]{{$}} -// CORRECTLYROUNDED: call float @llvm.sqrt.f32(float %{{.+}}){{$}} - -// DEFAULT-UNSAFE: call reassoc nsz arcp contract afn float @llvm.sqrt.f32(float %{{.+}}), !fpmath [[$FPMATH:![0-9]+]]{{$}} -// CORRECTLYROUNDED-UNSAFE: call reassoc nsz arcp contract afn float @llvm.sqrt.f32(float %{{.+}}){{$}} - // CHECK-LABEL: define {{.*}} <2 x float> @call_sqrt_v2f32( -// CHECK: call {{.*}} <2 x float> @_Z4sqrtDv2_f(<2 x float> noundef %{{.*}}) #{{[0-9]+$}} +// DEFAULT: call <2 x float> @_Z4sqrtDv2_f(<2 x float> noundef %{{.+}}) #{{[0-9]+}}, !fpmath [[FPMATH]]{{$}} +// CORRECTLYROUNDED: call <2 x float> @_Z4sqrtDv2_f(<2 x float> noundef %{{.+}}) #{{[0-9]+}}{{$}} + +// DEFAULT-UNSAFE: call reassoc nsz arcp contract afn <2 x float> @_Z4sqrtDv2_f(<2 x float> noundef %{{.+}}) #{{[0-9]+}}, !fpmath [[FPMATH]]{{$}} +// CORRECTLY-UNSAFE: call reassoc nsz arcp contract afn <2 x float> @_Z4sqrtDv2_f(<2 x float> noundef %{{.+}}) #{{[0-9]+}}{{$}} float2 call_sqrt_v2f32(float2 x) { return sqrt(x); } -// CHECK-LABEL: define available_externally <2 x float> @_Z4sqrtDv2_f(<2 x float> noundef %__x) -// DEFAULT: call <2 x float> @llvm.sqrt.v2f32(<2 x float> %{{.+}}), !fpmath [[$FPMATH:![0-9]+]]{{$}} -// CORRECTLYROUNDED: call <2 x float> @llvm.sqrt.v2f32(<2 x float> %{{.+}}){{$}} - -// DEFAULT-UNSAFE: call reassoc nsz arcp contract afn <2 x float> @llvm.sqrt.v2f32(<2 x float> %{{.+}}), !fpmath [[$FPMATH:![0-9]+]]{{$}} -// CORRECTLYROUNDED-UNSAFE: call reassoc nsz arcp contract afn <2 x float> @llvm.sqrt.v2f32(<2 x float> %{{.+}}){{$}} // CHECK-LABEL: define {{.*}} <3 x float> @call_sqrt_v3f32( -// CHECK: call {{.*}} <3 x float> @_Z4sqrtDv3_f(<3 x float> noundef %{{.*}}) #{{[0-9]+$}} +// DEFAULT: call <3 x float> @_Z4sqrtDv3_f(<3 x float> noundef %{{.+}}) #{{[0-9]+}}, !fpmath [[FPMATH]]{{$}} +// CORRECTLYROUNDED: call <3 x float> @_Z4sqrtDv3_f(<3 x float> noundef %{{.+}}) #{{[0-9]+}}{{$}} + +// DEFAULT-UNSAFE: call reassoc nsz arcp contract afn <3 x float> @_Z4sqrtDv3_f(<3 x float> noundef %{{.+}}) #{{[0-9]+}}, !fpmath [[FPMATH]]{{$}} +// CORRECTLY-UNSAFE: call reassoc nsz arcp contract afn <3 x float> @_Z4sqrtDv3_f(<3 x float> noundef %{{.+}}) #{{[0-9]+}}{{$}} float3 call_sqrt_v3f32(float3 x) { return sqrt(x); } -// CHECK-LABEL: define available_externally <3 x float> @_Z4sqrtDv3_f(<3 x float> noundef %__x) -// DEFAULT: call <3 x float> @llvm.sqrt.v3f32(<3 x float> %{{.+}}), !fpmath [[$FPMATH:![0-9]+]]{{$}} -// CORRECTLYROUNDED: call <3 x float> @llvm.sqrt.v3f32(<3 x float> %{{.+}}){{$}} - -// DEFAULT-UNSAFE: call reassoc nsz arcp contract afn <3 x float> @llvm.sqrt.v3f32(<3 x float> %{{.+}}), !fpmath [[$FPMATH:![0-9]+]]{{$}} -// CORRECTLYROUNDED-UNSAFE: call reassoc nsz arcp contract afn <3 x float> @llvm.sqrt.v3f32(<3 x float> %{{.+}}){{$}} // CHECK-LABEL: define {{.*}} <4 x float> @call_sqrt_v4f32( -// CHECK: call {{.*}} <4 x float> @_Z4sqrtDv4_f(<4 x float> noundef %{{.*}}) #{{[0-9]+$}} +// DEFAULT: call <4 x float> @_Z4sqrtDv4_f(<4 x float> noundef %{{.+}}) #{{[0-9]+}}, !fpmath [[FPMATH]]{{$}} +// CORRECTLYROUNDED: call <4 x float> @_Z4sqrtDv4_f(<4 x float> noundef %{{.+}}) #{{[0-9]+}}{{$}} + +// DEFAULT-UNSAFE: call reassoc nsz arcp contract afn <4 x float> @_Z4sqrtDv4_f(<4 x float> noundef %{{.+}}) #{{[0-9]+}}, !fpmath [[FPMATH]]{{$}} +// CORRECTLY-UNSAFE: call reassoc nsz arcp contract afn <4 x float> @_Z4sqrtDv4_f(<4 x float> noundef %{{.+}}) #{{[0-9]+}}{{$}} float4 call_sqrt_v4f32(float4 x) { return sqrt(x); } -// CHECK-LABEL: define available_externally <4 x float> @_Z4sqrtDv4_f(<4 x float> noundef %__x) -// DEFAULT: call <4 x float> @llvm.sqrt.v4f32(<4 x float> %{{.+}}), !fpmath [[$FPMATH:![0-9]+]]{{$}} -// CORRECTLYROUNDED: call <4 x float> @llvm.sqrt.v4f32(<4 x float> %{{.+}}){{$}} - -// DEFAULT-UNSAFE: call reassoc nsz arcp contract afn <4 x float> @llvm.sqrt.v4f32(<4 x float> %{{.+}}), !fpmath [[$FPMATH:![0-9]+]]{{$}} -// CORRECTLYROUNDED-UNSAFE: call reassoc nsz arcp contract afn <4 x float> @llvm.sqrt.v4f32(<4 x float> %{{.+}}){{$}} // CHECK-LABEL: define {{.*}} <8 x float> @call_sqrt_v8f32( -// CHECK: call {{.*}} <8 x float> @_Z4sqrtDv8_f(<8 x float> noundef %{{.*}}) #{{[0-9]+$}} +// DEFAULT: call <8 x float> @_Z4sqrtDv8_f(<8 x float> noundef %{{.+}}) #{{[0-9]+}}, !fpmath [[FPMATH]]{{$}} +// CORRECTLYROUNDED: call <8 x float> @_Z4sqrtDv8_f(<8 x float> noundef %{{.+}}) #{{[0-9]+}}{{$}} + +// DEFAULT-UNSAFE: call reassoc nsz arcp contract afn <8 x float> @_Z4sqrtDv8_f(<8 x float> noundef %{{.+}}) #{{[0-9]+}}, !fpmath [[FPMATH]]{{$}} +// CORRECTLYROUNDED-UNSAFE: call reassoc nsz arcp contract afn <8 x float> @_Z4sqrtDv8_f(<8 x float> noundef %{{.+}}) #{{[0-9]+}}{{$}} float8 call_sqrt_v8f32(float8 x) { return sqrt(x); } -// CHECK-LABEL: define available_externally <8 x float> @_Z4sqrtDv8_f(<8 x float> noundef %__x) -// DEFAULT: call <8 x float> @llvm.sqrt.v8f32(<8 x float> %{{.+}}), !fpmath [[$FPMATH:![0-9]+]]{{$}} -// CORRECTLYROUNDED: call <8 x float> @llvm.sqrt.v8f32(<8 x float> %{{.+}}){{$}} - -// DEFAULT-UNSAFE: call reassoc nsz arcp contract afn <8 x float> @llvm.sqrt.v8f32(<8 x float> %{{.+}}), !fpmath [[$FPMATH:![0-9]+]]{{$}} -// CORRECTLYROUNDED-UNSAFE: call reassoc nsz arcp contract afn <8 x float> @llvm.sqrt.v8f32(<8 x float> %{{.+}}){{$}} // CHECK-LABEL: define {{.*}} <16 x float> @call_sqrt_v16f32( -// CHECK: call {{.*}} <16 x float> @_Z4sqrtDv16_f(<16 x float> noundef %{{.*}}) #{{[0-9]+$}} +// DEFAULT: call <16 x float> @_Z4sqrtDv16_f(<16 x float> noundef %{{.+}}) #{{[0-9]+}}, !fpmath [[FPMATH]]{{$}} +// CORRECTLYROUNDED: call <16 x float> @_Z4sqrtDv16_f(<16 x float> noundef %{{.+}}) #{{[0-9]+}}{{$}} + +// DEFAULT-UNSAFE: call reassoc nsz arcp contract afn <16 x float> @_Z4sqrtDv16_f(<16 x float> noundef %{{.+}}) #{{[0-9]+}}, !fpmath [[FPMATH]]{{$}} +// CORRECTLY-UNSAFE: call reassoc nsz arcp contract afn <16 x float> @_Z4sqrtDv16_f(<16 x float> noundef %{{.+}}) #{{[0-9]+}}{{$}} float16 call_sqrt_v16f32(float16 x) { return sqrt(x); } -// CHECK-LABEL: define available_externally <16 x float> @_Z4sqrtDv16_f(<16 x float> noundef %__x) -// DEFAULT: call <16 x float> @llvm.sqrt.v16f32(<16 x float> %{{.+}}), !fpmath [[$FPMATH:![0-9]+]]{{$}} -// CORRECTLYROUNDED: call <16 x float> @llvm.sqrt.v16f32(<16 x float> %{{.+}}){{$}} - -// DEFAULT-UNSAFE: call reassoc nsz arcp contract afn <16 x float> @llvm.sqrt.v16f32(<16 x float> %{{.+}}), !fpmath [[$FPMATH:![0-9]+]]{{$}} -// CORRECTLYROUNDED-UNSAFE: call reassoc nsz arcp contract afn <16 x float> @llvm.sqrt.v16f32(<16 x float> %{{.+}}){{$}} // Not for f64 // CHECK-LABEL: define {{.*}} double @call_sqrt_f64( -// CHECK: call {{.*}} double @_Z4sqrtd(double noundef %{{.+}}) #{{[0-9]+$}} +// CHECK: call {{.*}} double @_Z4sqrtd(double noundef %{{.+}}) #{{[0-9]+$}}{{$}} double call_sqrt_f64(double x) { return sqrt(x); } -// CHECK-NOT: define // Not for f64 // CHECK-LABEL: define {{.*}} <2 x double> @call_sqrt_v2f64( -// CHECK: call {{.*}} <2 x double> @_Z4sqrtDv2_d(<2 x double> noundef %{{.+}}) #{{[0-9]+$}} +// CHECK: call {{.*}} <2 x double> @_Z4sqrtDv2_d(<2 x double> noundef %{{.+}}) #{{[0-9]+$}}{{$}} double2 call_sqrt_v2f64(double2 x) { return sqrt(x); } -// CHECK-NOT: define // CHECK-LABEL: define {{.*}} <3 x double> @call_sqrt_v3f64( -// CHECK: call {{.*}} <3 x double> @_Z4sqrtDv3_d(<3 x double> noundef %{{.+}}) #{{[0-9]+$}} +// CHECK: call {{.*}} <3 x double> @_Z4sqrtDv3_d(<3 x double> noundef %{{.+}}) #{{[0-9]+$}}{{$}} double3 call_sqrt_v3f64(double3 x) { return sqrt(x); } -// CHECK-NOT: define // CHECK-LABEL: define {{.*}} <4 x double> @call_sqrt_v4f64( -// CHECK: call {{.*}} <4 x double> @_Z4sqrtDv4_d(<4 x double> noundef %{{.+}}) #{{[0-9]+$}} +// CHECK: call {{.*}} <4 x double> @_Z4sqrtDv4_d(<4 x double> noundef %{{.+}}) #{{[0-9]+$}}{{$}} double4 call_sqrt_v4f64(double4 x) { return sqrt(x); } -// CHECK-NOT: define // CHECK-LABEL: define {{.*}} <8 x double> @call_sqrt_v8f64( -// CHECK: call {{.*}} <8 x double> @_Z4sqrtDv8_d(<8 x double> noundef %{{.+}}) #{{[0-9]+$}} +// CHECK: call {{.*}} <8 x double> @_Z4sqrtDv8_d(<8 x double> noundef %{{.+}}) #{{[0-9]+$}}{{$}} double8 call_sqrt_v8f64(double8 x) { return sqrt(x); } -// CHECK-NOT: define // CHECK-LABEL: define {{.*}} <16 x double> @call_sqrt_v16f64( -// CHECK: call {{.*}} <16 x double> @_Z4sqrtDv16_d(<16 x double> noundef %{{.+}}) #{{[0-9]+$}} +// CHECK: call {{.*}} <16 x double> @_Z4sqrtDv16_d(<16 x double> noundef %{{.+}}) #{{[0-9]+$}}{{$}} double16 call_sqrt_v16f64(double16 x) { return sqrt(x); } -// CHECK-NOT: define // Not for f16 // CHECK-LABEL: define {{.*}} half @call_sqrt_f16( -// CHECK: call {{.*}} half @_Z4sqrtDh(half noundef %{{.+}}) #{{[0-9]+$}} +// CHECK: call {{.*}} half @_Z4sqrtDh(half noundef %{{.+}}) #{{[0-9]+$}}{{$}} half call_sqrt_f16(half x) { return sqrt(x); } -// CHECK-NOT: define // CHECK-LABEL: define {{.*}} <2 x half> @call_sqrt_v2f16( -// CHECK: call {{.*}} <2 x half> @_Z4sqrtDv2_Dh(<2 x half> noundef %{{.+}}) #{{[0-9]+$}} +// CHECK: call {{.*}} <2 x half> @_Z4sqrtDv2_Dh(<2 x half> noundef %{{.+}}) #{{[0-9]+$}}{{$}} half2 call_sqrt_v2f16(half2 x) { return sqrt(x); } -// CHECK-NOT: define // CHECK-LABEL: define {{.*}} <3 x half> @call_sqrt_v3f16( -// CHECK: call {{.*}} <3 x half> @_Z4sqrtDv3_Dh(<3 x half> noundef %{{.+}}) #{{[0-9]+$}} +// CHECK: call {{.*}} <3 x half> @_Z4sqrtDv3_Dh(<3 x half> noundef %{{.+}}) #{{[0-9]+$}}{{$}} half3 call_sqrt_v3f16(half3 x) { return sqrt(x); } -// CHECK-NOT: define // CHECK-LABEL: define {{.*}} <4 x half> @call_sqrt_v4f16( -// CHECK: call {{.*}} <4 x half> @_Z4sqrtDv4_Dh(<4 x half> noundef %{{.+}}) #{{[0-9]+$}} +// CHECK: call {{.*}} <4 x half> @_Z4sqrtDv4_Dh(<4 x half> noundef %{{.+}}) #{{[0-9]+$}}{{$}} half4 call_sqrt_v4f16(half4 x) { return sqrt(x); } -// CHECK-NOT: define // CHECK-LABEL: define {{.*}} <8 x half> @call_sqrt_v8f16( -// CHECK: call {{.*}} <8 x half> @_Z4sqrtDv8_Dh(<8 x half> noundef %{{.+}}) #{{[0-9]+$}} +// CHECK: call {{.*}} <8 x half> @_Z4sqrtDv8_Dh(<8 x half> noundef %{{.+}}) #{{[0-9]+$}}{{$}} half8 call_sqrt_v8f16(half8 x) { return sqrt(x); } -// CHECK-NOT: define // CHECK-LABEL: define {{.*}} <16 x half> @call_sqrt_v16f16( -// CHECK: call {{.*}} <16 x half> @_Z4sqrtDv16_Dh(<16 x half> noundef %{{.+}}) #{{[0-9]+$}} +// CHECK: call {{.*}} <16 x half> @_Z4sqrtDv16_Dh(<16 x half> noundef %{{.+}}) #{{[0-9]+$}}{{$}} half16 call_sqrt_v16f16(half16 x) { return sqrt(x); } -// CHECK-NOT: define - -// DEFAULT: [[$FPMATH]] = !{float 3.000000e+00} +// DEFAULT: [[FPMATH]] = !{float 3.000000e+00} -- GitLab From 5a9354832695d878e86f90010d2b043a9551b072 Mon Sep 17 00:00:00 2001 From: paperchalice Date: Fri, 1 Dec 2023 15:43:48 +0800 Subject: [PATCH 105/699] [CodeGen][NFC] Sort and format MachinePassRegistry.def (#74044) Same as #73762. --- .../llvm/CodeGen/MachinePassRegistry.def | 188 ++++++++++-------- 1 file changed, 105 insertions(+), 83 deletions(-) diff --git a/llvm/include/llvm/CodeGen/MachinePassRegistry.def b/llvm/include/llvm/CodeGen/MachinePassRegistry.def index 47dd8f2cc464..fc2d07fd6616 100644 --- a/llvm/include/llvm/CodeGen/MachinePassRegistry.def +++ b/llvm/include/llvm/CodeGen/MachinePassRegistry.def @@ -29,29 +29,30 @@ MODULE_PASS("pre-isel-intrinsic-lowering", PreISelIntrinsicLoweringPass, ()) #define FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) #endif FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis, (PIC)) -FUNCTION_ANALYSIS("targetir", TargetIRAnalysis, (std::move(TM.getTargetIRAnalysis()))) +FUNCTION_ANALYSIS("targetir", TargetIRAnalysis, + (std::move(TM.getTargetIRAnalysis()))) #undef FUNCTION_ANALYSIS #ifndef FUNCTION_PASS #define FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) #endif FUNCTION_PASS("callbrprepare", CallBrPreparePass, ()) -FUNCTION_PASS("safe-stack", SafeStackPass, (TM)) -FUNCTION_PASS("mergeicmps", MergeICmpsPass, ()) -FUNCTION_PASS("lower-constant-intrinsics", LowerConstantIntrinsicsPass, ()) -FUNCTION_PASS("unreachableblockelim", UnreachableBlockElimPass, ()) FUNCTION_PASS("consthoist", ConstantHoistingPass, ()) -FUNCTION_PASS("replace-with-veclib", ReplaceWithVeclib, ()) -FUNCTION_PASS("partially-inline-libcalls", PartiallyInlineLibCallsPass, ()) FUNCTION_PASS("ee-instrument", EntryExitInstrumenterPass, (false)) -FUNCTION_PASS("post-inline-ee-instrument", EntryExitInstrumenterPass, (true)) FUNCTION_PASS("expand-large-div-rem", ExpandLargeDivRemPass, ()) FUNCTION_PASS("expand-large-fp-convert", ExpandLargeFpConvertPass, ()) FUNCTION_PASS("expand-reductions", ExpandReductionsPass, ()) FUNCTION_PASS("expandvp", ExpandVectorPredicationPass, ()) +FUNCTION_PASS("lower-constant-intrinsics", LowerConstantIntrinsicsPass, ()) FUNCTION_PASS("lowerinvoke", LowerInvokePass, ()) +FUNCTION_PASS("mergeicmps", MergeICmpsPass, ()) +FUNCTION_PASS("partially-inline-libcalls", PartiallyInlineLibCallsPass, ()) +FUNCTION_PASS("post-inline-ee-instrument", EntryExitInstrumenterPass, (true)) +FUNCTION_PASS("replace-with-veclib", ReplaceWithVeclib, ()) +FUNCTION_PASS("safe-stack", SafeStackPass, (TM)) FUNCTION_PASS("scalarize-masked-mem-intrin", ScalarizeMaskedMemIntrinPass, ()) FUNCTION_PASS("tlshoist", TLSVariableHoistPass, ()) +FUNCTION_PASS("unreachableblockelim", UnreachableBlockElimPass, ()) FUNCTION_PASS("verify", VerifierPass, ()) #undef FUNCTION_PASS @@ -69,7 +70,8 @@ LOOP_PASS("loop-reduce", LoopStrengthReducePass, ()) #ifndef MACHINE_FUNCTION_ANALYSIS #define MACHINE_FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) #endif -MACHINE_FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis, (PIC)) +MACHINE_FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis, + (PIC)) // LiveVariables currently requires pure SSA form. // FIXME: Once TwoAddressInstruction pass no longer uses kill flags, // LiveVariables can be removed completely, and LiveIntervals can be directly @@ -80,18 +82,24 @@ MACHINE_FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis, ( // MACHINE_FUNCTION_ANALYSIS("live-stacks", LiveStacksPass()) // MACHINE_FUNCTION_ANALYSIS("slot-indexes", SlotIndexesAnalysis()) // MACHINE_FUNCTION_ANALYSIS("edge-bundles", EdgeBundlesAnalysis()) -// MACHINE_FUNCTION_ANALYSIS("lazy-machine-bfi", LazyMachineBlockFrequencyInfoAnalysis()) +// MACHINE_FUNCTION_ANALYSIS("lazy-machine-bfi", +// LazyMachineBlockFrequencyInfoAnalysis()) // MACHINE_FUNCTION_ANALYSIS("machine-bfi", MachineBlockFrequencyInfoAnalysis()) // MACHINE_FUNCTION_ANALYSIS("machine-loops", MachineLoopInfoAnalysis()) -// MACHINE_FUNCTION_ANALYSIS("machine-dom-frontier", MachineDominanceFrontierAnalysis()) +// MACHINE_FUNCTION_ANALYSIS("machine-dom-frontier", +// MachineDominanceFrontierAnalysis()) // MACHINE_FUNCTION_ANALYSIS("machine-dom-tree", MachineDominatorTreeAnalysis()) -// MACHINE_FUNCTION_ANALYSIS("machine-ore", MachineOptimizationRemarkEmitterPassAnalysis()) -// MACHINE_FUNCTION_ANALYSIS("machine-post-dom-tree", MachinePostDominatorTreeAnalysis()) -// MACHINE_FUNCTION_ANALYSIS("machine-region-info", MachineRegionInfoPassAnalysis()) -// MACHINE_FUNCTION_ANALYSIS("machine-trace-metrics", MachineTraceMetricsAnalysis()) -// MACHINE_FUNCTION_ANALYSIS("reaching-def", ReachingDefAnalysisAnalysis()) -// MACHINE_FUNCTION_ANALYSIS("live-reg-matrix", LiveRegMatrixAnalysis()) -// MACHINE_FUNCTION_ANALYSIS("gc-analysis", GCMachineCodeAnalysisPass()) +// MACHINE_FUNCTION_ANALYSIS("machine-ore", +// MachineOptimizationRemarkEmitterPassAnalysis()) +// MACHINE_FUNCTION_ANALYSIS("machine-post-dom-tree", +// MachinePostDominatorTreeAnalysis()) +// MACHINE_FUNCTION_ANALYSIS("machine-region-info", +// MachineRegionInfoPassAnalysis()) +// MACHINE_FUNCTION_ANALYSIS("machine-trace-metrics", +// MachineTraceMetricsAnalysis()) MACHINE_FUNCTION_ANALYSIS("reaching-def", +// ReachingDefAnalysisAnalysis()) MACHINE_FUNCTION_ANALYSIS("live-reg-matrix", +// LiveRegMatrixAnalysis()) MACHINE_FUNCTION_ANALYSIS("gc-analysis", +// GCMachineCodeAnalysisPass()) #undef MACHINE_FUNCTION_ANALYSIS #ifndef MACHINE_FUNCTION_PASS @@ -108,22 +116,22 @@ MACHINE_FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis, ( #ifndef DUMMY_FUNCTION_PASS #define DUMMY_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) #endif +DUMMY_FUNCTION_PASS("atomic-expand", AtomicExpandPass, ()) +DUMMY_FUNCTION_PASS("cfguard-check", CFGuardCheckPass, ()) +DUMMY_FUNCTION_PASS("cfguard-dispatch", CFGuardDispatchPass, ()) +DUMMY_FUNCTION_PASS("codegenprepare", CodeGenPreparePass, ()) +DUMMY_FUNCTION_PASS("dwarfehprepare", DwarfEHPass, ()) DUMMY_FUNCTION_PASS("expandmemcmp", ExpandMemCmpPass, ()) +DUMMY_FUNCTION_PASS("gc-info-printer", GCInfoPrinterPass, ()) DUMMY_FUNCTION_PASS("gc-lowering", GCLoweringPass, ()) +DUMMY_FUNCTION_PASS("indirectbr-expand", IndirectBrExpandPass, ()) +DUMMY_FUNCTION_PASS("interleaved-access", InterleavedAccessPass, ()) +DUMMY_FUNCTION_PASS("select-optimize", SelectOptimizePass, ()) DUMMY_FUNCTION_PASS("shadow-stack-gc-lowering", ShadowStackGCLoweringPass, ()) DUMMY_FUNCTION_PASS("sjljehprepare", SjLjEHPreparePass, ()) -DUMMY_FUNCTION_PASS("dwarfehprepare", DwarfEHPass, ()) -DUMMY_FUNCTION_PASS("winehprepare", WinEHPass, ()) -DUMMY_FUNCTION_PASS("wasmehprepare", WasmEHPass, ()) -DUMMY_FUNCTION_PASS("codegenprepare", CodeGenPreparePass, ()) DUMMY_FUNCTION_PASS("stack-protector", StackProtectorPass, ()) -DUMMY_FUNCTION_PASS("atomic-expand", AtomicExpandPass, ()) -DUMMY_FUNCTION_PASS("interleaved-access", InterleavedAccessPass, ()) -DUMMY_FUNCTION_PASS("indirectbr-expand", IndirectBrExpandPass, ()) -DUMMY_FUNCTION_PASS("cfguard-dispatch", CFGuardDispatchPass, ()) -DUMMY_FUNCTION_PASS("cfguard-check", CFGuardCheckPass, ()) -DUMMY_FUNCTION_PASS("gc-info-printer", GCInfoPrinterPass, ()) -DUMMY_FUNCTION_PASS("select-optimize", SelectOptimizePass, ()) +DUMMY_FUNCTION_PASS("wasmehprepare", WasmEHPass, ()) +DUMMY_FUNCTION_PASS("winehprepare", WinEHPass, ()) #undef DUMMY_FUNCTION_PASS #ifndef DUMMY_MODULE_PASS @@ -141,71 +149,85 @@ DUMMY_MACHINE_MODULE_PASS("machine-outliner", MachineOutlinerPass, ()) #ifndef DUMMY_MACHINE_FUNCTION_PASS #define DUMMY_MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) #endif -DUMMY_MACHINE_FUNCTION_PASS("mir-printer", PrintMIRPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("free-machine-function", FreeMachineFunctionPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("finalize-isel", FinalizeISelPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("localstackalloc", LocalStackSlotPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("shrink-wrap", ShrinkWrapPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("prologepilog", PrologEpilogInserterPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("postrapseudos", ExpandPostRAPseudosPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("implicit-null-checks", ImplicitNullChecksPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("postmisched", PostMachineSchedulerPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("machine-scheduler", MachineSchedulerPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("machine-cp", MachineCopyPropagationPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("machine-latecleanup", MachineLateInstrsCleanupPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("post-RA-sched", PostRASchedulerPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("block-placement", MachineBlockPlacementPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("block-placement-stats", + MachineBlockPlacementStatsPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("branch-folder", BranchFolderPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("break-false-deps", BreakFalseDepsPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("cfguard-longjmp", CFGuardLongjmpPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("cfi-instr-inserter", CFIInstrInserterPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("dead-mi-elimination", + DeadMachineInstructionElimPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("detect-dead-lanes", DetectDeadLanesPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("dot-machine-cfg", MachineCFGPrinter, ()) +DUMMY_MACHINE_FUNCTION_PASS("early-ifcvt", EarlyIfConverterPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("early-machinelicm", EarlyMachineLICMPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("early-tailduplication", EarlyTailDuplicatePass, ()) DUMMY_MACHINE_FUNCTION_PASS("fentry-insert", FEntryInserterPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("xray-instrumentation", XRayInstrumentationPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("patchable-function", PatchableFunctionPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("reg-usage-propagation", RegUsageInfoPropagationPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("reg-usage-collector", RegUsageInfoCollectorPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("finalize-isel", FinalizeISelPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("free-machine-function", FreeMachineFunctionPass, + ()) DUMMY_MACHINE_FUNCTION_PASS("funclet-layout", FuncletLayoutPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("stackmap-liveness", StackMapLivenessPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("removeredundantdebugvalues", RemoveRedundantDebugValuesPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("dot-machine-cfg", MachineCFGPrinter, ()) +DUMMY_MACHINE_FUNCTION_PASS("implicit-null-checks", ImplicitNullChecksPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("instruction-select", InstructionSelectPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("irtranslator", IRTranslatorPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("legalizer", LegalizerPass, ()) DUMMY_MACHINE_FUNCTION_PASS("livedebugvalues", LiveDebugValuesPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("early-tailduplication", EarlyTailDuplicatePass, ()) -DUMMY_MACHINE_FUNCTION_PASS("opt-phis", OptimizePHIsPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("stack-coloring", StackColoringPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("dead-mi-elimination", DeadMachineInstructionElimPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("early-machinelicm", EarlyMachineLICMPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("machinelicm", MachineLICMPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("liveintervals", LiveIntervalsPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("localstackalloc", LocalStackSlotPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("lrshrink", LiveRangeShrinkPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("machine-combiner", MachineCombinerPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("machine-cp", MachineCopyPropagationPass, ()) DUMMY_MACHINE_FUNCTION_PASS("machine-cse", MachineCSEPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("machine-latecleanup", MachineLateInstrsCleanupPass, + ()) +DUMMY_MACHINE_FUNCTION_PASS("machine-sanmd", MachineSanitizerBinaryMetadata, ()) +DUMMY_MACHINE_FUNCTION_PASS("machine-scheduler", MachineSchedulerPass, ()) DUMMY_MACHINE_FUNCTION_PASS("machine-sink", MachineSinkingPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("postra-machine-sink", PostRAMachineSinkingPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("machine-uniformity", + MachineUniformityInfoWrapperPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("machinelicm", MachineLICMPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("machineverifier", MachineVerifierPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("mir-printer", PrintMIRPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("opt-phis", OptimizePHIsPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("patchable-function", PatchableFunctionPass, ()) DUMMY_MACHINE_FUNCTION_PASS("peephole-opt", PeepholeOptimizerPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("regalloc", RegAllocPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("virtregrewriter", VirtRegRewriterPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("stack-slot-coloring", StackSlotColoringPass, ()) DUMMY_MACHINE_FUNCTION_PASS("phi-node-elimination", PHIEliminationPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("twoaddressinstruction", TwoAddressInstructionPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("detect-dead-lanes", DetectDeadLanesPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("post-RA-sched", PostRASchedulerPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("postmisched", PostMachineSchedulerPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("postra-machine-sink", PostRAMachineSinkingPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("postrapseudos", ExpandPostRAPseudosPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("print-machine-cycles", MachineCycleInfoPrinterPass, + ()) +DUMMY_MACHINE_FUNCTION_PASS("print-machine-uniformity", + MachineUniformityInfoPrinterPass, ()) DUMMY_MACHINE_FUNCTION_PASS("processimpdefs", ProcessImplicitDefsPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("liveintervals", LiveIntervalsPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("simple-register-coalescing", RegisterCoalescerPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("rename-independent-subregs", RenameIndependentSubregsPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("branch-folder", BranchFolderPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("tailduplication", TailDuplicatePass, ()) -DUMMY_MACHINE_FUNCTION_PASS("block-placement", MachineBlockPlacementPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("block-placement-stats", MachineBlockPlacementStatsPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("early-ifcvt", EarlyIfConverterPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("machine-combiner", MachineCombinerPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("lrshrink", LiveRangeShrinkPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("break-false-deps", BreakFalseDepsPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("cfi-instr-inserter", CFIInstrInserterPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("cfguard-longjmp", CFGuardLongjmpPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("prologepilog", PrologEpilogInserterPass, ()) DUMMY_MACHINE_FUNCTION_PASS("ra-basic", RABasicPass, ()) DUMMY_MACHINE_FUNCTION_PASS("ra-fast", RAFastPass, ()) DUMMY_MACHINE_FUNCTION_PASS("ra-greedy", RAGreedyPass, ()) DUMMY_MACHINE_FUNCTION_PASS("ra-pbqp", RAPBQPPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("legalizer", LegalizerPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("irtranslator", IRTranslatorPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("reg-usage-collector", RegUsageInfoCollectorPass, + ()) +DUMMY_MACHINE_FUNCTION_PASS("reg-usage-propagation", + RegUsageInfoPropagationPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("regalloc", RegAllocPass, ()) DUMMY_MACHINE_FUNCTION_PASS("regbankselect", RegBankSelectPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("instruction-select", InstructionSelectPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("reset-machine-function", ResetMachineFunctionPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("machineverifier", MachineVerifierPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("print-machine-cycles", MachineCycleInfoPrinterPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("machine-sanmd", MachineSanitizerBinaryMetadata, ()) -DUMMY_MACHINE_FUNCTION_PASS("machine-uniformity", MachineUniformityInfoWrapperPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("print-machine-uniformity", MachineUniformityInfoPrinterPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("removeredundantdebugvalues", + RemoveRedundantDebugValuesPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("rename-independent-subregs", + RenameIndependentSubregsPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("reset-machine-function", ResetMachineFunctionPass, + ()) +DUMMY_MACHINE_FUNCTION_PASS("shrink-wrap", ShrinkWrapPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("simple-register-coalescing", RegisterCoalescerPass, + ()) +DUMMY_MACHINE_FUNCTION_PASS("stack-coloring", StackColoringPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("stack-slot-coloring", StackSlotColoringPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("stackmap-liveness", StackMapLivenessPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("tailduplication", TailDuplicatePass, ()) +DUMMY_MACHINE_FUNCTION_PASS("twoaddressinstruction", TwoAddressInstructionPass, + ()) +DUMMY_MACHINE_FUNCTION_PASS("virtregrewriter", VirtRegRewriterPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("xray-instrumentation", XRayInstrumentationPass, ()) #undef DUMMY_MACHINE_FUNCTION_PASS -- GitLab From 520c3b82db7199c1dcd24520f3c0ac573c191791 Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Thu, 30 Nov 2023 23:45:12 -0800 Subject: [PATCH 106/699] [llvm] Stop including llvm/ADT/StringSet.h (NFC) Identified with clangd. --- llvm/include/llvm/Transforms/IPO/MemProfContextDisambiguation.h | 1 - llvm/lib/ExecutionEngine/Orc/Debugging/DebuggerSupportPlugin.cpp | 1 - llvm/lib/Transforms/Utils/MoveAutoInit.cpp | 1 - llvm/tools/llvm-dwarfutil/Error.h | 1 - llvm/tools/llvm-exegesis/lib/BenchmarkResult.h | 1 - llvm/tools/llvm-gsymutil/llvm-gsymutil.cpp | 1 - llvm/tools/llvm-objcopy/ObjcopyOptions.cpp | 1 - 7 files changed, 7 deletions(-) diff --git a/llvm/include/llvm/Transforms/IPO/MemProfContextDisambiguation.h b/llvm/include/llvm/Transforms/IPO/MemProfContextDisambiguation.h index 0c79aecdd245..f5dce01c34e7 100644 --- a/llvm/include/llvm/Transforms/IPO/MemProfContextDisambiguation.h +++ b/llvm/include/llvm/Transforms/IPO/MemProfContextDisambiguation.h @@ -15,7 +15,6 @@ #ifndef LLVM_TRANSFORMS_IPO_MEMPROF_CONTEXT_DISAMBIGUATION_H #define LLVM_TRANSFORMS_IPO_MEMPROF_CONTEXT_DISAMBIGUATION_H -#include "llvm/ADT/StringSet.h" #include "llvm/IR/GlobalValue.h" #include "llvm/IR/ModuleSummaryIndex.h" #include "llvm/IR/PassManager.h" diff --git a/llvm/lib/ExecutionEngine/Orc/Debugging/DebuggerSupportPlugin.cpp b/llvm/lib/ExecutionEngine/Orc/Debugging/DebuggerSupportPlugin.cpp index cdc1158ce1c4..c6ffd9f7c2e3 100644 --- a/llvm/lib/ExecutionEngine/Orc/Debugging/DebuggerSupportPlugin.cpp +++ b/llvm/lib/ExecutionEngine/Orc/Debugging/DebuggerSupportPlugin.cpp @@ -14,7 +14,6 @@ #include "llvm/ADT/SmallSet.h" #include "llvm/ADT/SmallVector.h" -#include "llvm/ADT/StringSet.h" #include "llvm/BinaryFormat/MachO.h" #include "llvm/DebugInfo/DWARF/DWARFContext.h" #include "llvm/DebugInfo/DWARF/DWARFDebugLine.h" diff --git a/llvm/lib/Transforms/Utils/MoveAutoInit.cpp b/llvm/lib/Transforms/Utils/MoveAutoInit.cpp index 6f5f34461bea..a977ad87b79f 100644 --- a/llvm/lib/Transforms/Utils/MoveAutoInit.cpp +++ b/llvm/lib/Transforms/Utils/MoveAutoInit.cpp @@ -14,7 +14,6 @@ #include "llvm/Transforms/Utils/MoveAutoInit.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/Statistic.h" -#include "llvm/ADT/StringSet.h" #include "llvm/Analysis/MemorySSA.h" #include "llvm/Analysis/MemorySSAUpdater.h" #include "llvm/Analysis/ValueTracking.h" diff --git a/llvm/tools/llvm-dwarfutil/Error.h b/llvm/tools/llvm-dwarfutil/Error.h index b92c50ca5a45..fff5978a9d1a 100644 --- a/llvm/tools/llvm-dwarfutil/Error.h +++ b/llvm/tools/llvm-dwarfutil/Error.h @@ -11,7 +11,6 @@ #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringRef.h" -#include "llvm/ADT/StringSet.h" #include "llvm/Support/Debug.h" #include "llvm/Support/Error.h" #include "llvm/Support/Format.h" diff --git a/llvm/tools/llvm-exegesis/lib/BenchmarkResult.h b/llvm/tools/llvm-exegesis/lib/BenchmarkResult.h index 8a7faa0176e3..38111519a2c8 100644 --- a/llvm/tools/llvm-exegesis/lib/BenchmarkResult.h +++ b/llvm/tools/llvm-exegesis/lib/BenchmarkResult.h @@ -18,7 +18,6 @@ #include "LlvmState.h" #include "RegisterValue.h" #include "llvm/ADT/StringRef.h" -#include "llvm/ADT/StringSet.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstBuilder.h" #include "llvm/Support/YAMLTraits.h" diff --git a/llvm/tools/llvm-gsymutil/llvm-gsymutil.cpp b/llvm/tools/llvm-gsymutil/llvm-gsymutil.cpp index 46ec4bdc2870..094dca22f77b 100644 --- a/llvm/tools/llvm-gsymutil/llvm-gsymutil.cpp +++ b/llvm/tools/llvm-gsymutil/llvm-gsymutil.cpp @@ -7,7 +7,6 @@ //===----------------------------------------------------------------------===// #include "llvm/ADT/STLExtras.h" -#include "llvm/ADT/StringSet.h" #include "llvm/DebugInfo/DIContext.h" #include "llvm/DebugInfo/DWARF/DWARFContext.h" #include "llvm/Object/Archive.h" diff --git a/llvm/tools/llvm-objcopy/ObjcopyOptions.cpp b/llvm/tools/llvm-objcopy/ObjcopyOptions.cpp index d33adb0b6a3e..571290253944 100644 --- a/llvm/tools/llvm-objcopy/ObjcopyOptions.cpp +++ b/llvm/tools/llvm-objcopy/ObjcopyOptions.cpp @@ -10,7 +10,6 @@ #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringRef.h" -#include "llvm/ADT/StringSet.h" #include "llvm/BinaryFormat/COFF.h" #include "llvm/ObjCopy/CommonConfig.h" #include "llvm/ObjCopy/ConfigManager.h" -- GitLab From bc265bd663233c4bfa222f1cc93ec472075a53ff Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Thu, 30 Nov 2023 23:52:26 -0800 Subject: [PATCH 107/699] [llvm-reduce] Stop including llvm/ADT/SetVector.h (NFC) Identified with clangd. --- llvm/tools/llvm-reduce/deltas/ReduceFunctions.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/llvm/tools/llvm-reduce/deltas/ReduceFunctions.cpp b/llvm/tools/llvm-reduce/deltas/ReduceFunctions.cpp index 05127ec7b9c8..fdac4a3bf708 100644 --- a/llvm/tools/llvm-reduce/deltas/ReduceFunctions.cpp +++ b/llvm/tools/llvm-reduce/deltas/ReduceFunctions.cpp @@ -16,7 +16,6 @@ #include "Delta.h" #include "Utils.h" #include "llvm/ADT/STLExtras.h" -#include "llvm/ADT/SetVector.h" #include "llvm/Transforms/Utils/ModuleUtils.h" #include #include -- GitLab From 604c29e9340c4a18eab1e53dd5cc4c05d46db2f7 Mon Sep 17 00:00:00 2001 From: Valery Pykhtin Date: Fri, 1 Dec 2023 09:10:29 +0100 Subject: [PATCH 108/699] [AMDGPU] NFC. Add test for debug info on CFG annotation instructions. (#73959) --- .../CodeGen/AMDGPU/si-annotate-dbg-info.ll | 163 ++++++++++++++++++ 1 file changed, 163 insertions(+) create mode 100644 llvm/test/CodeGen/AMDGPU/si-annotate-dbg-info.ll diff --git a/llvm/test/CodeGen/AMDGPU/si-annotate-dbg-info.ll b/llvm/test/CodeGen/AMDGPU/si-annotate-dbg-info.ll new file mode 100644 index 000000000000..703eeb5df86e --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/si-annotate-dbg-info.ll @@ -0,0 +1,163 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -mtriple=amdgcn-- -S -structurizecfg -si-annotate-control-flow %s | FileCheck -check-prefix=OPT %s + +define amdgpu_ps i32 @if_else(i32 %0) !dbg !5 { +; OPT-LABEL: define amdgpu_ps i32 @if_else( +; OPT-SAME: i32 [[TMP0:%.*]]) !dbg [[DBG5:![0-9]+]] { +; OPT-NEXT: [[C:%.*]] = icmp ne i32 [[TMP0]], 0, !dbg [[DBG13:![0-9]+]] +; OPT-NEXT: tail call void @llvm.dbg.value(metadata i1 [[C]], metadata [[META9:![0-9]+]], metadata !DIExpression()), !dbg [[DBG13]] +; OPT-NEXT: [[TMP2:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[C]]) +; OPT-NEXT: [[TMP3:%.*]] = extractvalue { i1, i64 } [[TMP2]], 0 +; OPT-NEXT: [[TMP4:%.*]] = extractvalue { i1, i64 } [[TMP2]], 1 +; OPT-NEXT: br i1 [[TMP3]], label [[FALSE:%.*]], label [[FLOW:%.*]], !dbg [[DBG14:![0-9]+]] +; OPT: Flow: +; OPT-NEXT: [[TMP5:%.*]] = phi i32 [ 33, [[FALSE]] ], [ undef, [[TMP1:%.*]] ] +; OPT-NEXT: [[TMP6:%.*]] = call { i1, i64 } @llvm.amdgcn.else.i64.i64(i64 [[TMP4]]) +; OPT-NEXT: [[TMP7:%.*]] = extractvalue { i1, i64 } [[TMP6]], 0 +; OPT-NEXT: [[TMP8:%.*]] = extractvalue { i1, i64 } [[TMP6]], 1 +; OPT-NEXT: br i1 [[TMP7]], label [[TRUE:%.*]], label [[EXIT:%.*]], !dbg [[DBG14]] +; OPT: true: +; OPT-NEXT: br label [[EXIT]], !dbg [[DBG15:![0-9]+]] +; OPT: false: +; OPT-NEXT: br label [[FLOW]], !dbg [[DBG16:![0-9]+]] +; OPT: exit: +; OPT-NEXT: [[RET:%.*]] = phi i32 [ [[TMP5]], [[FLOW]] ], [ 42, [[TRUE]] ], !dbg [[DBG17:![0-9]+]] +; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP8]]) +; OPT-NEXT: tail call void @llvm.dbg.value(metadata i32 [[RET]], metadata [[META11:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17]] +; OPT-NEXT: ret i32 [[RET]], !dbg [[DBG18:![0-9]+]] +; + %c = icmp eq i32 %0, 0, !dbg !13 + tail call void @llvm.dbg.value(metadata i1 %c, metadata !9, metadata !DIExpression()), !dbg !13 + br i1 %c, label %true, label %false, !dbg !14 + +true: ; preds = %1 + br label %exit, !dbg !15 + +false: ; preds = %1 + br label %exit, !dbg !16 + +exit: ; preds = %false, %true + %ret = phi i32 [ 42, %true ], [ 33, %false ], !dbg !17 + tail call void @llvm.dbg.value(metadata i32 %ret, metadata !11, metadata !DIExpression()), !dbg !17 + ret i32 %ret, !dbg !18 +} + +define amdgpu_ps void @loop_if_break(i32 %n) !dbg !19 { +; OPT-LABEL: define amdgpu_ps void @loop_if_break( +; OPT-SAME: i32 [[N:%.*]]) !dbg [[DBG19:![0-9]+]] { +; OPT-NEXT: entry: +; OPT-NEXT: br label [[LOOP:%.*]], !dbg [[DBG24:![0-9]+]] +; OPT: loop: +; OPT-NEXT: [[PHI_BROKEN:%.*]] = phi i64 [ [[TMP5:%.*]], [[FLOW:%.*]] ], [ 0, [[ENTRY:%.*]] ] +; OPT-NEXT: [[I:%.*]] = phi i32 [ [[N]], [[ENTRY]] ], [ [[TMP3:%.*]], [[FLOW]] ], !dbg [[DBG25:![0-9]+]] +; OPT-NEXT: tail call void @llvm.dbg.value(metadata i32 [[I]], metadata [[META21:![0-9]+]], metadata !DIExpression()), !dbg [[DBG25]] +; OPT-NEXT: [[C:%.*]] = icmp ugt i32 [[I]], 0, !dbg [[DBG26:![0-9]+]] +; OPT-NEXT: tail call void @llvm.dbg.value(metadata i1 [[C]], metadata [[META22:![0-9]+]], metadata !DIExpression()), !dbg [[DBG26]] +; OPT-NEXT: [[TMP0:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[C]]) +; OPT-NEXT: [[TMP1:%.*]] = extractvalue { i1, i64 } [[TMP0]], 0 +; OPT-NEXT: [[TMP2:%.*]] = extractvalue { i1, i64 } [[TMP0]], 1 +; OPT-NEXT: br i1 [[TMP1]], label [[LOOP_BODY:%.*]], label [[FLOW]], !dbg [[DBG27:![0-9]+]] +; OPT: loop_body: +; OPT-NEXT: [[I_NEXT:%.*]] = sub i32 [[I]], 1, !dbg [[DBG28:![0-9]+]] +; OPT-NEXT: tail call void @llvm.dbg.value(metadata i32 [[I_NEXT]], metadata [[META23:![0-9]+]], metadata !DIExpression()), !dbg [[DBG28]] +; OPT-NEXT: br label [[FLOW]], !dbg [[DBG29:![0-9]+]] +; OPT: Flow: +; OPT-NEXT: [[TMP3]] = phi i32 [ [[I_NEXT]], [[LOOP_BODY]] ], [ undef, [[LOOP]] ] +; OPT-NEXT: [[TMP4:%.*]] = phi i1 [ false, [[LOOP_BODY]] ], [ true, [[LOOP]] ] +; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP2]]) +; OPT-NEXT: [[TMP5]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[TMP4]], i64 [[PHI_BROKEN]]) +; OPT-NEXT: [[TMP6:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP5]]) +; OPT-NEXT: br i1 [[TMP6]], label [[EXIT:%.*]], label [[LOOP]], !dbg [[DBG27]] +; OPT: exit: +; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP5]]) +; OPT-NEXT: ret void, !dbg [[DBG30:![0-9]+]] +; +entry: + br label %loop, !dbg !24 + +loop: ; preds = %loop_body, %entry + %i = phi i32 [ %n, %entry ], [ %i.next, %loop_body ], !dbg !25 + tail call void @llvm.dbg.value(metadata i32 %i, metadata !21, metadata !DIExpression()), !dbg !25 + %c = icmp ugt i32 %i, 0, !dbg !26 + tail call void @llvm.dbg.value(metadata i1 %c, metadata !22, metadata !DIExpression()), !dbg !26 + br i1 %c, label %loop_body, label %exit, !dbg !27 + +loop_body: ; preds = %loop + %i.next = sub i32 %i, 1, !dbg !28 + tail call void @llvm.dbg.value(metadata i32 %i.next, metadata !23, metadata !DIExpression()), !dbg !28 + br label %loop, !dbg !29 + +exit: ; preds = %loop + ret void, !dbg !30 +} + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare void @llvm.dbg.value(metadata, metadata, metadata) #0 + +attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.dbg.cu = !{!0} +!llvm.debugify = !{!2, !3} +!llvm.module.flags = !{!4} + +!0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug) +!1 = !DIFile(filename: "../../../test/CodeGen/AMDGPU/si-annotate-dbg-info.ll", directory: "/") +!2 = !{i32 13} +!3 = !{i32 5} +!4 = !{i32 2, !"Debug Info Version", i32 3} +!5 = distinct !DISubprogram(name: "if_else", linkageName: "if_else", scope: null, file: !1, line: 1, type: !6, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !8) +!6 = !DISubroutineType(types: !7) +!7 = !{} +!8 = !{!9, !11} +!9 = !DILocalVariable(name: "1", scope: !5, file: !1, line: 1, type: !10) +!10 = !DIBasicType(name: "ty8", size: 8, encoding: DW_ATE_unsigned) +!11 = !DILocalVariable(name: "2", scope: !5, file: !1, line: 5, type: !12) +!12 = !DIBasicType(name: "ty32", size: 32, encoding: DW_ATE_unsigned) +!13 = !DILocation(line: 1, column: 1, scope: !5) +!14 = !DILocation(line: 2, column: 1, scope: !5) +!15 = !DILocation(line: 3, column: 1, scope: !5) +!16 = !DILocation(line: 4, column: 1, scope: !5) +!17 = !DILocation(line: 5, column: 1, scope: !5) +!18 = !DILocation(line: 6, column: 1, scope: !5) +!19 = distinct !DISubprogram(name: "loop_if_break", linkageName: "loop_if_break", scope: null, file: !1, line: 7, type: !6, scopeLine: 7, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !20) +!20 = !{!21, !22, !23} +!21 = !DILocalVariable(name: "3", scope: !19, file: !1, line: 8, type: !12) +!22 = !DILocalVariable(name: "4", scope: !19, file: !1, line: 9, type: !10) +!23 = !DILocalVariable(name: "5", scope: !19, file: !1, line: 11, type: !12) +!24 = !DILocation(line: 7, column: 1, scope: !19) +!25 = !DILocation(line: 8, column: 1, scope: !19) +!26 = !DILocation(line: 9, column: 1, scope: !19) +!27 = !DILocation(line: 10, column: 1, scope: !19) +!28 = !DILocation(line: 11, column: 1, scope: !19) +!29 = !DILocation(line: 12, column: 1, scope: !19) +!30 = !DILocation(line: 13, column: 1, scope: !19) +;. +; OPT: [[META0:![0-9]+]] = distinct !DICompileUnit(language: DW_LANG_C, file: [[META1:![0-9]+]], producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug) +; OPT: [[META1]] = !DIFile(filename: "../../../test/CodeGen/AMDGPU/si-annotate-dbg-info.ll", directory: {{.*}}) +; OPT: [[DBG5]] = distinct !DISubprogram(name: "if_else", linkageName: "if_else", scope: null, file: [[META1]], line: 1, type: [[META6:![0-9]+]], scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: [[META0]], retainedNodes: [[META8:![0-9]+]]) +; OPT: [[META6]] = !DISubroutineType(types: [[META7:![0-9]+]]) +; OPT: [[META7]] = !{} +; OPT: [[META8]] = !{[[META9]], [[META11]]} +; OPT: [[META9]] = !DILocalVariable(name: "1", scope: [[DBG5]], file: [[META1]], line: 1, type: [[META10:![0-9]+]]) +; OPT: [[META10]] = !DIBasicType(name: "ty8", size: 8, encoding: DW_ATE_unsigned) +; OPT: [[META11]] = !DILocalVariable(name: "2", scope: [[DBG5]], file: [[META1]], line: 5, type: [[META12:![0-9]+]]) +; OPT: [[META12]] = !DIBasicType(name: "ty32", size: 32, encoding: DW_ATE_unsigned) +; OPT: [[DBG13]] = !DILocation(line: 1, column: 1, scope: [[DBG5]]) +; OPT: [[DBG14]] = !DILocation(line: 2, column: 1, scope: [[DBG5]]) +; OPT: [[DBG15]] = !DILocation(line: 3, column: 1, scope: [[DBG5]]) +; OPT: [[DBG16]] = !DILocation(line: 4, column: 1, scope: [[DBG5]]) +; OPT: [[DBG17]] = !DILocation(line: 5, column: 1, scope: [[DBG5]]) +; OPT: [[DBG18]] = !DILocation(line: 6, column: 1, scope: [[DBG5]]) +; OPT: [[DBG19]] = distinct !DISubprogram(name: "loop_if_break", linkageName: "loop_if_break", scope: null, file: [[META1]], line: 7, type: [[META6]], scopeLine: 7, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: [[META0]], retainedNodes: [[META20:![0-9]+]]) +; OPT: [[META20]] = !{[[META21]], [[META22]], [[META23]]} +; OPT: [[META21]] = !DILocalVariable(name: "3", scope: [[DBG19]], file: [[META1]], line: 8, type: [[META12]]) +; OPT: [[META22]] = !DILocalVariable(name: "4", scope: [[DBG19]], file: [[META1]], line: 9, type: [[META10]]) +; OPT: [[META23]] = !DILocalVariable(name: "5", scope: [[DBG19]], file: [[META1]], line: 11, type: [[META12]]) +; OPT: [[DBG24]] = !DILocation(line: 7, column: 1, scope: [[DBG19]]) +; OPT: [[DBG25]] = !DILocation(line: 8, column: 1, scope: [[DBG19]]) +; OPT: [[DBG26]] = !DILocation(line: 9, column: 1, scope: [[DBG19]]) +; OPT: [[DBG27]] = !DILocation(line: 10, column: 1, scope: [[DBG19]]) +; OPT: [[DBG28]] = !DILocation(line: 11, column: 1, scope: [[DBG19]]) +; OPT: [[DBG29]] = !DILocation(line: 12, column: 1, scope: [[DBG19]]) +; OPT: [[DBG30]] = !DILocation(line: 13, column: 1, scope: [[DBG19]]) +;. -- GitLab From 0e163e75d44cfa024092cda5099bd41af2218215 Mon Sep 17 00:00:00 2001 From: Shengchen Kan Date: Fri, 1 Dec 2023 16:18:33 +0800 Subject: [PATCH 109/699] [X86][MC] Not emit {evex} for VEX-promoted instructions with GPR operands (#74039) To align with 1. GNU binutils's behavior for APX instructions 2. LLVM's behaviour for EVEX intructions with VEX variant --- llvm/lib/Target/X86/X86InstrAVX512.td | 7 ++--- llvm/test/MC/Disassembler/X86/apx/kmov.txt | 35 ++++++++++++---------- llvm/test/MC/X86/apx/kmov-att.s | 28 +++++++++-------- llvm/test/MC/X86/apx/kmov-intel.s | 28 +++++++++-------- 4 files changed, 52 insertions(+), 46 deletions(-) diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 0514f0d19506..77b359e84fbd 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -2855,8 +2855,8 @@ defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, 0x67, SchedWriteFCmp>, E multiclass avx512_mask_mov opc_kk, bits<8> opc_km, bits<8> opc_mk, string OpcodeStr, RegisterClass KRC, ValueType vvt, X86MemOperand x86memop, string Suffix = ""> { - let explicitOpPrefix = !if(!eq(Suffix, ""), NoExplicitOpPrefix, ExplicitEVEX) in { - let isMoveReg = 1, hasSideEffects = 0, SchedRW = [WriteMove] in + let isMoveReg = 1, hasSideEffects = 0, SchedRW = [WriteMove], + explicitOpPrefix = !if(!eq(Suffix, ""), NoExplicitOpPrefix, ExplicitEVEX) in def kk#Suffix : I, Sched<[WriteMove]>; @@ -2868,13 +2868,12 @@ multiclass avx512_mask_mov opc_kk, bits<8> opc_km, bits<8> opc_mk, !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [(store KRC:$src, addr:$dst)]>, Sched<[WriteStore]>; - } } multiclass avx512_mask_mov_gpr opc_kr, bits<8> opc_rk, string OpcodeStr, RegisterClass KRC, RegisterClass GRC, string Suffix = ""> { - let hasSideEffects = 0, explicitOpPrefix = !if(!eq(Suffix, ""), NoExplicitOpPrefix, ExplicitEVEX) in { + let hasSideEffects = 0 in { def kr#Suffix : I, Sched<[WriteMove]>; diff --git a/llvm/test/MC/Disassembler/X86/apx/kmov.txt b/llvm/test/MC/Disassembler/X86/apx/kmov.txt index d089ef192230..5d947ff39f23 100644 --- a/llvm/test/MC/Disassembler/X86/apx/kmov.txt +++ b/llvm/test/MC/Disassembler/X86/apx/kmov.txt @@ -1,6 +1,25 @@ # RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT # RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL +# ATT: {evex} kmovb %k1, %k2 +# INTEL: {evex} kmovb k2, k1 +0x62,0xf1,0x7d,0x08,0x90,0xd1 + +# ATT: {evex} kmovw %k1, %k2 +# INTEL: {evex} kmovw k2, k1 +0x62,0xf1,0x7c,0x08,0x90,0xd1 + +# ATT: {evex} kmovd %k1, %k2 +# INTEL: {evex} kmovd k2, k1 +0x62,0xf1,0xfd,0x08,0x90,0xd1 + +# ATT: {evex} kmovq %k1, %k2 +# INTEL: {evex} kmovq k2, k1 +0x62,0xf1,0xfc,0x08,0x90,0xd1 + +# ATT-NOT: {evex} +# INTEL-NOT: {evex} + # ATT: kmovb %r16d, %k1 # INTEL: kmovb k1, r16d 0x62,0xf9,0x7d,0x08,0x92,0xc8 @@ -64,19 +83,3 @@ # ATT: kmovq %k1, (%r16,%r17) # INTEL: kmovq qword ptr [r16 + r17], k1 0x62,0xf9,0xf8,0x08,0x91,0x0c,0x08 - -# ATT: {evex} kmovb %k1, %k2 -# INTEL: {evex} kmovb k2, k1 -0x62,0xf1,0x7d,0x08,0x90,0xd1 - -# ATT: {evex} kmovw %k1, %k2 -# INTEL: {evex} kmovw k2, k1 -0x62,0xf1,0x7c,0x08,0x90,0xd1 - -# ATT: {evex} kmovd %k1, %k2 -# INTEL: {evex} kmovd k2, k1 -0x62,0xf1,0xfd,0x08,0x90,0xd1 - -# ATT: {evex} kmovq %k1, %k2 -# INTEL: {evex} kmovq k2, k1 -0x62,0xf1,0xfc,0x08,0x90,0xd1 diff --git a/llvm/test/MC/X86/apx/kmov-att.s b/llvm/test/MC/X86/apx/kmov-att.s index be5042cf0a30..949ef65be98d 100644 --- a/llvm/test/MC/X86/apx/kmov-att.s +++ b/llvm/test/MC/X86/apx/kmov-att.s @@ -3,6 +3,21 @@ # ERROR-COUNT-20: error: # ERROR-NOT: error: +# CHECK: {evex} kmovb %k1, %k2 +# CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x90,0xd1] + {evex} kmovb %k1, %k2 +# CHECK: {evex} kmovw %k1, %k2 +# CHECK: encoding: [0x62,0xf1,0x7c,0x08,0x90,0xd1] + {evex} kmovw %k1, %k2 +# CHECK: {evex} kmovd %k1, %k2 +# CHECK: encoding: [0x62,0xf1,0xfd,0x08,0x90,0xd1] + {evex} kmovd %k1, %k2 +# CHECK: {evex} kmovq %k1, %k2 +# CHECK: encoding: [0x62,0xf1,0xfc,0x08,0x90,0xd1] + {evex} kmovq %k1, %k2 + +# CHECK-NOT: {evex} + # CHECK: kmovb %r16d, %k1 # CHECK: encoding: [0x62,0xf9,0x7d,0x08,0x92,0xc8] kmovb %r16d, %k1 @@ -54,16 +69,3 @@ # CHECK: kmovq %k1, (%r16,%r17) # CHECK: encoding: [0x62,0xf9,0xf8,0x08,0x91,0x0c,0x08] kmovq %k1, (%r16,%r17) - -# CHECK: {evex} kmovb %k1, %k2 -# CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x90,0xd1] - {evex} kmovb %k1, %k2 -# CHECK: {evex} kmovw %k1, %k2 -# CHECK: encoding: [0x62,0xf1,0x7c,0x08,0x90,0xd1] - {evex} kmovw %k1, %k2 -# CHECK: {evex} kmovd %k1, %k2 -# CHECK: encoding: [0x62,0xf1,0xfd,0x08,0x90,0xd1] - {evex} kmovd %k1, %k2 -# CHECK: {evex} kmovq %k1, %k2 -# CHECK: encoding: [0x62,0xf1,0xfc,0x08,0x90,0xd1] - {evex} kmovq %k1, %k2 diff --git a/llvm/test/MC/X86/apx/kmov-intel.s b/llvm/test/MC/X86/apx/kmov-intel.s index 8ceb29d32dba..0cdbd310062e 100644 --- a/llvm/test/MC/X86/apx/kmov-intel.s +++ b/llvm/test/MC/X86/apx/kmov-intel.s @@ -1,5 +1,20 @@ # RUN: llvm-mc -triple x86_64 -show-encoding -x86-asm-syntax=intel -output-asm-variant=1 %s | FileCheck %s +# CHECK: {evex} kmovb k2, k1 +# CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x90,0xd1] + {evex} kmovb k2, k1 +# CHECK: {evex} kmovw k2, k1 +# CHECK: encoding: [0x62,0xf1,0x7c,0x08,0x90,0xd1] + {evex} kmovw k2, k1 +# CHECK: {evex} kmovd k2, k1 +# CHECK: encoding: [0x62,0xf1,0xfd,0x08,0x90,0xd1] + {evex} kmovd k2, k1 +# CHECK: {evex} kmovq k2, k1 +# CHECK: encoding: [0x62,0xf1,0xfc,0x08,0x90,0xd1] + {evex} kmovq k2, k1 + +# CHECK-NOT: {evex} + # CHECK: kmovb k1, r16d # CHECK: encoding: [0x62,0xf9,0x7d,0x08,0x92,0xc8] kmovb k1, r16d @@ -51,16 +66,3 @@ # CHECK: kmovq qword ptr [r16 + r17], k1 # CHECK: encoding: [0x62,0xf9,0xf8,0x08,0x91,0x0c,0x08] kmovq qword ptr [r16 + r17], k1 - -# CHECK: {evex} kmovb k2, k1 -# CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x90,0xd1] - {evex} kmovb k2, k1 -# CHECK: {evex} kmovw k2, k1 -# CHECK: encoding: [0x62,0xf1,0x7c,0x08,0x90,0xd1] - {evex} kmovw k2, k1 -# CHECK: {evex} kmovd k2, k1 -# CHECK: encoding: [0x62,0xf1,0xfd,0x08,0x90,0xd1] - {evex} kmovd k2, k1 -# CHECK: {evex} kmovq k2, k1 -# CHECK: encoding: [0x62,0xf1,0xfc,0x08,0x90,0xd1] - {evex} kmovq k2, k1 -- GitLab From ab3fdbdfbe7edc62049c602d87be91c3ad3f5e3b Mon Sep 17 00:00:00 2001 From: Allen Date: Fri, 1 Dec 2023 16:20:38 +0800 Subject: [PATCH 110/699] [ValueTracking] Support srem/urem for isKnownNonNullFromDominatingCondition (#74021) Similar to div, the rem should also proof its second operand is non-zero, otherwise it is a UB. Fix https://github.com/llvm/llvm-project/issues/71782 --- llvm/lib/Analysis/ValueTracking.cpp | 3 +- .../ValueTracking/select-known-non-zero.ll | 56 ++++++++++++++++++- .../Transforms/InstCombine/zext-or-icmp.ll | 4 +- 3 files changed, 58 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp index 250ce739ea51..ef8fa5826deb 100644 --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -2186,7 +2186,8 @@ static bool isKnownNonNullFromDominatingCondition(const Value *V, return true; } - if (match(U, m_IDiv(m_Value(), m_Specific(V))) && + if ((match(U, m_IDiv(m_Value(), m_Specific(V))) || + match(U, m_IRem(m_Value(), m_Specific(V)))) && isValidAssumeForContext(cast(U), CtxI, DT)) return true; diff --git a/llvm/test/Analysis/ValueTracking/select-known-non-zero.ll b/llvm/test/Analysis/ValueTracking/select-known-non-zero.ll index 1dc88412041d..53ed4485c94f 100644 --- a/llvm/test/Analysis/ValueTracking/select-known-non-zero.ll +++ b/llvm/test/Analysis/ValueTracking/select-known-non-zero.ll @@ -2,6 +2,8 @@ ; RUN: opt < %s -passes=instsimplify -S | FileCheck %s declare void @llvm.assume(i1) +declare void @use(i64) +declare void @use4(i4) define i1 @select_v_ne_fail(i8 %v, i8 %C, i8 %y) { ; CHECK-LABEL: @select_v_ne_fail( @@ -446,4 +448,56 @@ define i64 @incorrect_safe_div_call_2(i64 %n, i64 %d) { ret i64 %3 } -declare void @use(i64) +; https://alive2.llvm.org/ce/z/Si_B7b +define i4 @icmp_urem(i4 %n, i4 %d) { +; CHECK-LABEL: @icmp_urem( +; CHECK-NEXT: [[TMP1:%.*]] = urem i4 [[N:%.*]], [[D:%.*]] +; CHECK-NEXT: ret i4 [[TMP1]] +; + %1 = icmp eq i4 %d, 0 + %2 = urem i4 %n, %d + %3 = select i1 %1, i4 -1, i4 %2 + ret i4 %3 +} + +define i4 @icmp_urem_clobber_by_call(i4 %n, i4 %d) { +; CHECK-LABEL: @icmp_urem_clobber_by_call( +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i4 [[D:%.*]], 0 +; CHECK-NEXT: tail call void @use4(i4 [[D]]) +; CHECK-NEXT: [[TMP2:%.*]] = urem i4 [[N:%.*]], [[D]] +; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP1]], i4 -1, i4 [[TMP2]] +; CHECK-NEXT: ret i4 [[TMP3]] +; + %1 = icmp eq i4 %d, 0 + tail call void @use4(i4 %d) + %2 = urem i4 %n, %d + %3 = select i1 %1, i4 -1, i4 %2 + ret i4 %3 +} + +; https://alive2.llvm.org/ce/z/Fn3Wac +define i4 @icmp_srem(i4 %n, i4 %d) { +; CHECK-LABEL: @icmp_srem( +; CHECK-NEXT: [[TMP1:%.*]] = srem i4 [[N:%.*]], [[D:%.*]] +; CHECK-NEXT: ret i4 [[TMP1]] +; + %1 = icmp eq i4 %d, 0 + %2 = srem i4 %n, %d + %3 = select i1 %1, i4 -1, i4 %2 + ret i4 %3 +} + +define i4 @icmp_srem_clobber_by_call(i4 %n, i4 %d) { +; CHECK-LABEL: @icmp_srem_clobber_by_call( +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i4 [[D:%.*]], 0 +; CHECK-NEXT: tail call void @use4(i4 [[D]]) +; CHECK-NEXT: [[TMP2:%.*]] = srem i4 [[N:%.*]], [[D]] +; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP1]], i4 -1, i4 [[TMP2]] +; CHECK-NEXT: ret i4 [[TMP3]] +; + %1 = icmp eq i4 %d, 0 + tail call void @use4(i4 %d) + %2 = srem i4 %n, %d + %3 = select i1 %1, i4 -1, i4 %2 + ret i4 %3 +} diff --git a/llvm/test/Transforms/InstCombine/zext-or-icmp.ll b/llvm/test/Transforms/InstCombine/zext-or-icmp.ll index bc0e4bdce29b..9ec3ddc80c57 100644 --- a/llvm/test/Transforms/InstCombine/zext-or-icmp.ll +++ b/llvm/test/Transforms/InstCombine/zext-or-icmp.ll @@ -231,9 +231,7 @@ define i1 @PR51762(ptr %i, i32 %t0, i16 %t1, ptr %p, ptr %d, ptr %f, i32 %p2, i1 ; CHECK-NEXT: [[INSERT_INSERT41:%.*]] = or i64 [[INSERT_SHIFT52]], [[INSERT_EXT39]] ; CHECK-NEXT: [[REM:%.*]] = urem i64 [[S1]], [[INSERT_INSERT41]] ; CHECK-NEXT: [[NE:%.*]] = icmp ne i64 [[REM]], 0 -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[INSERT_INSERT41]], 0 -; CHECK-NEXT: [[SPEC_SELECT57:%.*]] = or i1 [[NE]], [[CMP]] -; CHECK-NEXT: [[LOR_EXT:%.*]] = zext i1 [[SPEC_SELECT57]] to i32 +; CHECK-NEXT: [[LOR_EXT:%.*]] = zext i1 [[NE]] to i32 ; CHECK-NEXT: [[T2:%.*]] = load i32, ptr [[D:%.*]], align 4 ; CHECK-NEXT: [[CONV15:%.*]] = sext i16 [[T1]] to i32 ; CHECK-NEXT: [[CMP16:%.*]] = icmp sge i32 [[T2]], [[CONV15]] -- GitLab From d48d1edcf3ed0c1352b3c2864feb873f01d6f9da Mon Sep 17 00:00:00 2001 From: Ramkumar Ramachandra Date: Fri, 1 Dec 2023 08:22:18 +0000 Subject: [PATCH 111/699] PowerPC/aix-cc-abi: regenerate test using UTC (NFC) (#73963) Split out the parts of aix-cc-abi.ll that requires to be regenerated by utils/update_mir_test_checks.py into aix-cc-abi-mir.ll, and regenerate it using the script. Regenerate aix-cc-abi.ll using utils/update_llc_test_checks.py. --- llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll | 2068 +++++++++++ llvm/test/CodeGen/PowerPC/aix-cc-abi.ll | 3635 +++++++++---------- 2 files changed, 3811 insertions(+), 1892 deletions(-) create mode 100644 llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll b/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll new file mode 100644 index 000000000000..ccc36530c795 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll @@ -0,0 +1,2068 @@ +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -mtriple powerpc-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | \ +; RUN: FileCheck --check-prefix=32BIT %s + +; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | \ +; RUN: FileCheck --check-prefix=64BIT %s + +define void @call_test_chars() { + ; 32BIT-LABEL: name: call_test_chars + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: $r3 = LI 97 + ; 32BIT-NEXT: $r4 = LI 97 + ; 32BIT-NEXT: $r5 = LI 97 + ; 32BIT-NEXT: $r6 = LI 97 + ; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit $r2, implicit-def $r1, implicit-def dead $r3 + ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm + ; + ; 64BIT-LABEL: name: call_test_chars + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: $x3 = LI8 97 + ; 64BIT-NEXT: $x4 = LI8 97 + ; 64BIT-NEXT: $x5 = LI8 97 + ; 64BIT-NEXT: $x6 = LI8 97 + ; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit $x2, implicit-def $r1, implicit-def dead $x3 + ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm +entry: + call i8 @test_chars(i8 signext 97, i8 signext 97, i8 signext 97, i8 signext 97) + ret void +} + +define signext i8 @test_chars(i8 signext %c1, i8 signext %c2, i8 signext %c3, i8 signext %c4) { + ; 32BIT-LABEL: name: test_chars + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: liveins: $r3, $r4, $r5, $r6 + ; 32BIT-NEXT: {{ $}} + ; 32BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, killed renamable $r4 + ; 32BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, killed renamable $r5 + ; 32BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, killed renamable $r6 + ; 32BIT-NEXT: renamable $r3 = EXTSB killed renamable $r3 + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm, implicit $r3 + ; + ; 64BIT-LABEL: name: test_chars + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: liveins: $x3, $x4, $x5, $x6 + ; 64BIT-NEXT: {{ $}} + ; 64BIT-NEXT: renamable $r3 = ADD4 renamable $r3, renamable $r4, implicit killed $x4, implicit killed $x3 + ; 64BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, renamable $r5, implicit killed $x5 + ; 64BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, renamable $r6, implicit killed $x6, implicit-def $x3 + ; 64BIT-NEXT: renamable $x3 = EXTSB8 killed renamable $x3 + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3 +entry: + %conv = sext i8 %c1 to i32 + %conv1 = sext i8 %c2 to i32 + %add = add nsw i32 %conv, %conv1 + %conv2 = sext i8 %c3 to i32 + %add3 = add nsw i32 %add, %conv2 + %conv4 = sext i8 %c4 to i32 + %add5 = add nsw i32 %add3, %conv4 + %conv6 = trunc i32 %add5 to i8 + ret i8 %conv6 +} + +define void @call_test_chars_mix() { + ; 32BIT-LABEL: name: call_test_chars_mix + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: $r3 = LI 97 + ; 32BIT-NEXT: $r4 = LI 225 + ; 32BIT-NEXT: $r5 = LI 97 + ; 32BIT-NEXT: $r6 = LI -31 + ; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit $r2, implicit-def $r1, implicit-def dead $r3 + ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm + ; + ; 64BIT-LABEL: name: call_test_chars_mix + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: $x3 = LI8 97 + ; 64BIT-NEXT: $x4 = LI8 225 + ; 64BIT-NEXT: $x5 = LI8 97 + ; 64BIT-NEXT: $x6 = LI8 -31 + ; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit $x2, implicit-def $r1, implicit-def dead $x3 + ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm +entry: + call i8 @test_chars_mix(i8 signext 97, i8 zeroext -31, i8 zeroext 97, i8 signext -31) + ret void +} + +define signext i8 @test_chars_mix(i8 signext %c1, i8 zeroext %c2, i8 zeroext %c3, i8 signext %c4) { + ; 32BIT-LABEL: name: test_chars_mix + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: liveins: $r3, $r4, $r5, $r6 + ; 32BIT-NEXT: {{ $}} + ; 32BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, killed renamable $r4 + ; 32BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, killed renamable $r5 + ; 32BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, killed renamable $r6 + ; 32BIT-NEXT: renamable $r3 = EXTSB killed renamable $r3 + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm, implicit $r3 + ; + ; 64BIT-LABEL: name: test_chars_mix + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: liveins: $x3, $x4, $x5, $x6 + ; 64BIT-NEXT: {{ $}} + ; 64BIT-NEXT: renamable $r3 = ADD4 renamable $r3, renamable $r4, implicit killed $x4, implicit killed $x3 + ; 64BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, renamable $r5, implicit killed $x5 + ; 64BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, renamable $r6, implicit killed $x6, implicit-def $x3 + ; 64BIT-NEXT: renamable $x3 = EXTSB8 killed renamable $x3 + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3 +entry: + %conv = sext i8 %c1 to i32 + %conv1 = zext i8 %c2 to i32 + %add = add nsw i32 %conv, %conv1 + %conv2 = zext i8 %c3 to i32 + %add3 = add nsw i32 %add, %conv2 + %conv4 = sext i8 %c4 to i32 + %add5 = add nsw i32 %add3, %conv4 + %conv6 = trunc i32 %add5 to i8 + ret i8 %conv6 +} + +@global_i1 = global i8 0, align 1 + +define void @test_i1(i1 %b) { + ; 32BIT-LABEL: name: test_i1 + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: liveins: $r3 + ; 32BIT-NEXT: {{ $}} + ; 32BIT-NEXT: renamable $r4 = LWZtoc @global_i1, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $r3 = RLWINM killed renamable $r3, 0, 31, 31 + ; 32BIT-NEXT: STB killed renamable $r3, 0, killed renamable $r4 :: (store (s8) into @global_i1) + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm + ; + ; 64BIT-LABEL: name: test_i1 + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: liveins: $x3 + ; 64BIT-NEXT: {{ $}} + ; 64BIT-NEXT: renamable $x4 = LDtoc @global_i1, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $r3 = RLWINM renamable $r3, 0, 31, 31, implicit killed $x3 + ; 64BIT-NEXT: STB killed renamable $r3, 0, killed renamable $x4 :: (store (s8) into @global_i1) + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm + entry: + %frombool = zext i1 %b to i8 + store i8 %frombool, ptr @global_i1, align 1 + ret void +} + +define void @call_test_i1() { + ; 32BIT-LABEL: name: call_test_i1 + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: $r3 = LI 1 + ; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit $r2, implicit-def $r1 + ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm + ; + ; 64BIT-LABEL: name: call_test_i1 + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: $x3 = LI8 1 + ; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1 + ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm +entry: + call void @test_i1(i1 1) + ret void +} + +define void @test_i1zext(i1 zeroext %b) { + ; 32BIT-LABEL: name: test_i1zext + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: liveins: $r3 + ; 32BIT-NEXT: {{ $}} + ; 32BIT-NEXT: renamable $r4 = LWZtoc @global_i1, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: STB killed renamable $r3, 0, killed renamable $r4 :: (store (s8) into @global_i1) + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm + ; + ; 64BIT-LABEL: name: test_i1zext + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: liveins: $x3 + ; 64BIT-NEXT: {{ $}} + ; 64BIT-NEXT: renamable $x4 = LDtoc @global_i1, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: STB8 killed renamable $x3, 0, killed renamable $x4 :: (store (s8) into @global_i1) + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm + entry: + %frombool = zext i1 %b to i8 + store i8 %frombool, ptr @global_i1, align 1 + ret void + } + +define i32 @test_ints(i32 signext %a, i32 zeroext %b, i32 zeroext %c, i32 signext %d, i32 signext %e, i32 signext %f, i32 signext %g, i32 signext %h) { + ; 32BIT-LABEL: name: test_ints + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: liveins: $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10 + ; 32BIT-NEXT: {{ $}} + ; 32BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, killed renamable $r4 + ; 32BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, killed renamable $r5 + ; 32BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, killed renamable $r6 + ; 32BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, killed renamable $r7 + ; 32BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, killed renamable $r8 + ; 32BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, killed renamable $r9 + ; 32BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, killed renamable $r10 + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm, implicit $r3 + ; + ; 64BIT-LABEL: name: test_ints + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: liveins: $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10 + ; 64BIT-NEXT: {{ $}} + ; 64BIT-NEXT: renamable $r3 = ADD4 renamable $r3, renamable $r4, implicit killed $x4, implicit killed $x3 + ; 64BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, renamable $r5, implicit killed $x5 + ; 64BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, renamable $r6, implicit killed $x6 + ; 64BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, renamable $r7, implicit killed $x7 + ; 64BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, renamable $r8, implicit killed $x8 + ; 64BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, renamable $r9, implicit killed $x9 + ; 64BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, renamable $r10, implicit killed $x10, implicit-def $x3 + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3 +entry: + %add = add i32 %a, %b + %add1 = add i32 %add, %c + %add2 = add i32 %add1, %d + %add3 = add i32 %add2, %e + %add4 = add i32 %add3, %f + %add5 = add i32 %add4, %g + %add6 = add i32 %add5, %h + ret i32 %add6 +} + +define void @call_test_ints() { + ; 32BIT-LABEL: name: call_test_ints + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: $r3 = LI 1 + ; 32BIT-NEXT: $r4 = LI 1 + ; 32BIT-NEXT: $r5 = LIS 32768 + ; 32BIT-NEXT: $r6 = LIS 32768 + ; 32BIT-NEXT: $r7 = LI 1 + ; 32BIT-NEXT: $r8 = LI 1 + ; 32BIT-NEXT: $r9 = LI 1 + ; 32BIT-NEXT: $r10 = LI 1 + ; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit killed $r10, implicit $r2, implicit-def $r1, implicit-def dead $r3 + ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm + ; + ; 64BIT-LABEL: name: call_test_ints + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: renamable $x3 = LI8 1 + ; 64BIT-NEXT: renamable $x5 = RLDIC killed renamable $x3, 31, 32 + ; 64BIT-NEXT: $x3 = LI8 1 + ; 64BIT-NEXT: $x4 = LI8 1 + ; 64BIT-NEXT: $x6 = LIS8 32768 + ; 64BIT-NEXT: $x7 = LI8 1 + ; 64BIT-NEXT: $x8 = LI8 1 + ; 64BIT-NEXT: $x9 = LI8 1 + ; 64BIT-NEXT: $x10 = LI8 1 + ; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit killed $x10, implicit $x2, implicit-def $r1, implicit-def dead $x3 + ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm +entry: + call i32 @test_ints(i32 signext 1, i32 zeroext 1, i32 zeroext 2147483648, i32 signext -2147483648, i32 signext 1, i32 signext 1, i32 signext 1, i32 signext 1) + ret void +} + +define void @call_test_i64() { + ; 32BIT-LABEL: name: call_test_i64 + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: $r3 = LI 0 + ; 32BIT-NEXT: $r4 = LI 1 + ; 32BIT-NEXT: $r5 = LI 0 + ; 32BIT-NEXT: $r6 = LI 2 + ; 32BIT-NEXT: $r7 = LI 0 + ; 32BIT-NEXT: $r8 = LI 3 + ; 32BIT-NEXT: $r9 = LI 0 + ; 32BIT-NEXT: $r10 = LI 4 + ; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit killed $r10, implicit $r2, implicit-def $r1, implicit-def dead $r3, implicit-def dead $r4 + ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm + ; + ; 64BIT-LABEL: name: call_test_i64 + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: $x3 = LI8 1 + ; 64BIT-NEXT: $x4 = LI8 2 + ; 64BIT-NEXT: $x5 = LI8 3 + ; 64BIT-NEXT: $x6 = LI8 4 + ; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit $x2, implicit-def $r1, implicit-def dead $x3 + ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm +entry: + call i64 @test_i64(i64 1, i64 2, i64 3, i64 4) + ret void +} + +define i64 @test_i64(i64 %a, i64 %b, i64 %c, i64 %d) { + ; 32BIT-LABEL: name: test_i64 + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: liveins: $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10 + ; 32BIT-NEXT: {{ $}} + ; 32BIT-NEXT: renamable $r4 = ADDC killed renamable $r4, killed renamable $r6, implicit-def $carry + ; 32BIT-NEXT: renamable $r3 = ADDE killed renamable $r3, killed renamable $r5, implicit-def dead $carry, implicit killed $carry + ; 32BIT-NEXT: renamable $r4 = ADDC killed renamable $r4, killed renamable $r8, implicit-def $carry + ; 32BIT-NEXT: renamable $r3 = ADDE killed renamable $r3, killed renamable $r7, implicit-def dead $carry, implicit killed $carry + ; 32BIT-NEXT: renamable $r4 = ADDC killed renamable $r4, killed renamable $r10, implicit-def $carry + ; 32BIT-NEXT: renamable $r3 = ADDE killed renamable $r3, killed renamable $r9, implicit-def dead $carry, implicit killed $carry + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm, implicit $r3, implicit $r4 + ; + ; 64BIT-LABEL: name: test_i64 + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: liveins: $x3, $x4, $x5, $x6 + ; 64BIT-NEXT: {{ $}} + ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x4 + ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x5 + ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x6 + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3 +entry: + %add = add nsw i64 %a, %b + %add1 = add nsw i64 %add, %c + %add2 = add nsw i64 %add1, %d + ret i64 %add2 +} + +define void @call_test_int_ptr() { + ; 32BIT-LABEL: name: call_test_int_ptr + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: renamable $r3 = LI 0 + ; 32BIT-NEXT: STW killed renamable $r3, 0, %stack.0.b :: (store (s32) into %ir.b) + ; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: renamable $r3 = ADDI %stack.0.b, 0 + ; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1 + ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm + ; + ; 64BIT-LABEL: name: call_test_int_ptr + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: renamable $x3 = LI8 0 + ; 64BIT-NEXT: STW8 killed renamable $x3, 0, %stack.0.b :: (store (s32) into %ir.b) + ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: renamable $x3 = ADDI8 %stack.0.b, 0 + ; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 + ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm +entry: + %b = alloca i32, align 4 + store i32 0, ptr %b, align 4 + call void @test_int_ptr(ptr %b) + ret void +} + +define void @test_int_ptr(ptr %a) { + ; 32BIT-LABEL: name: test_int_ptr + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: liveins: $r3 + ; 32BIT-NEXT: {{ $}} + ; 32BIT-NEXT: STW killed renamable $r3, 0, %stack.0.a.addr :: (store (s32) into %ir.a.addr, align 8) + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm + ; + ; 64BIT-LABEL: name: test_int_ptr + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: liveins: $x3 + ; 64BIT-NEXT: {{ $}} + ; 64BIT-NEXT: STD killed renamable $x3, 0, %stack.0.a.addr :: (store (s64) into %ir.a.addr) + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm +entry: + %a.addr = alloca ptr, align 8 + store ptr %a, ptr %a.addr, align 8 + ret void +} + +define i32 @caller(i32 %i) { + ; 32BIT-LABEL: name: caller + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: liveins: $r3 + ; 32BIT-NEXT: {{ $}} + ; 32BIT-NEXT: STW renamable $r3, 0, %stack.0.i.addr :: (store (s32) into %ir.i.addr) + ; 32BIT-NEXT: renamable $r3 = CNTLZW killed renamable $r3 + ; 32BIT-NEXT: renamable $r3 = NOR killed renamable $r3, renamable $r3 + ; 32BIT-NEXT: renamable $r3 = RLWINM killed renamable $r3, 27, 31, 31 + ; 32BIT-NEXT: STB renamable $r3, 0, %stack.1.b :: (store (s8) into %ir.b) + ; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1, implicit-def $r3 + ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm, implicit $r3 + ; + ; 64BIT-LABEL: name: caller + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: liveins: $x3 + ; 64BIT-NEXT: {{ $}} + ; 64BIT-NEXT: STW renamable $r3, 0, %stack.0.i.addr :: (store (s32) into %ir.i.addr) + ; 64BIT-NEXT: renamable $r3 = CNTLZW renamable $r3, implicit killed $x3 + ; 64BIT-NEXT: renamable $r3 = RLWINM killed renamable $r3, 27, 5, 31 + ; 64BIT-NEXT: renamable $r3 = XORI killed renamable $r3, 1, implicit-def $x3 + ; 64BIT-NEXT: STB renamable $r3, 0, %stack.1.b :: (store (s8) into %ir.b) + ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1, implicit-def $x3 + ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3 +entry: + %i.addr = alloca i32, align 4 + %b = alloca i8, align 1 + store i32 %i, ptr %i.addr, align 4 + %0 = load i32, ptr %i.addr, align 4 + %cmp = icmp ne i32 %0, 0 + %frombool = zext i1 %cmp to i8 + store i8 %frombool, ptr %b, align 1 + %1 = load i8, ptr %b, align 1 + %tobool = trunc i8 %1 to i1 + %call = call i32 @call_test_bool(i1 zeroext %tobool) + ret i32 %call +} + +declare i32 @call_test_bool(i1 zeroext) + +@f1 = global float 0.000000e+00, align 4 +@d1 = global double 0.000000e+00, align 8 + +define void @call_test_floats() { + ; 32BIT-LABEL: name: call_test_floats + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: renamable $r3 = LWZtoc @f1, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f1 = LFS 0, killed renamable $r3 :: (dereferenceable load (s32) from @f1) + ; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: $f2 = COPY renamable $f1 + ; 32BIT-NEXT: $f3 = COPY renamable $f1 + ; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit $r2, implicit-def $r1, implicit-def dead $f1 + ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm + ; + ; 64BIT-LABEL: name: call_test_floats + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: renamable $x3 = LDtoc @f1, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x3 :: (dereferenceable load (s32) from @f1) + ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: $f2 = COPY renamable $f1 + ; 64BIT-NEXT: $f3 = COPY renamable $f1 + ; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit $x2, implicit-def $r1, implicit-def dead $f1 + ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm +entry: + %0 = load float, ptr @f1, align 4 + call float @test_floats(float %0, float %0, float %0) + ret void +} + +define float @test_floats(float %f1, float %f2, float %f3) { + ; 32BIT-LABEL: name: test_floats + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: liveins: $f1, $f2, $f3 + ; 32BIT-NEXT: {{ $}} + ; 32BIT-NEXT: renamable $f0 = nofpexcept FADDS killed renamable $f1, killed renamable $f2, implicit $rm + ; 32BIT-NEXT: renamable $f1 = nofpexcept FADDS killed renamable $f0, killed renamable $f3, implicit $rm + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm, implicit $f1 + ; + ; 64BIT-LABEL: name: test_floats + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: liveins: $f1, $f2, $f3 + ; 64BIT-NEXT: {{ $}} + ; 64BIT-NEXT: renamable $f0 = nofpexcept FADDS killed renamable $f1, killed renamable $f2, implicit $rm + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADDS killed renamable $f0, killed renamable $f3, implicit $rm + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $f1 +entry: + %add = fadd float %f1, %f2 + %add1 = fadd float %add, %f3 + ret float %add1 +} + +define void @call_test_fpr_max() { + ; 32BIT-LABEL: name: call_test_fpr_max + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: renamable $r3 = LWZtoc @d1, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f1 = LFD 0, killed renamable $r3 :: (dereferenceable load (s64) from @d1) + ; 32BIT-NEXT: ADJCALLSTACKDOWN 128, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: STFD renamable $f1, 120, $r1 :: (store (s64)) + ; 32BIT-NEXT: STFD renamable $f1, 112, $r1 :: (store (s64)) + ; 32BIT-NEXT: STFD renamable $f1, 104, $r1 :: (store (s64)) + ; 32BIT-NEXT: STFD renamable $f1, 96, $r1 :: (store (s64)) + ; 32BIT-NEXT: STFD renamable $f1, 88, $r1 :: (store (s64)) + ; 32BIT-NEXT: STFD renamable $f1, 80, $r1 :: (store (s64)) + ; 32BIT-NEXT: STFD renamable $f1, 72, $r1 :: (store (s64)) + ; 32BIT-NEXT: STFD renamable $f1, 64, $r1 :: (store (s64)) + ; 32BIT-NEXT: $f2 = COPY renamable $f1 + ; 32BIT-NEXT: $f3 = COPY renamable $f1 + ; 32BIT-NEXT: $f4 = COPY renamable $f1 + ; 32BIT-NEXT: $f5 = COPY renamable $f1 + ; 32BIT-NEXT: $f6 = COPY renamable $f1 + ; 32BIT-NEXT: $f7 = COPY renamable $f1 + ; 32BIT-NEXT: $f8 = COPY renamable $f1 + ; 32BIT-NEXT: $f9 = COPY renamable $f1 + ; 32BIT-NEXT: $f10 = COPY renamable $f1 + ; 32BIT-NEXT: $f11 = COPY renamable $f1 + ; 32BIT-NEXT: $f12 = COPY renamable $f1 + ; 32BIT-NEXT: $f13 = COPY renamable $f1 + ; 32BIT-NEXT: STFD renamable $f1, 56, $r1 :: (store (s64)) + ; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit killed $f4, implicit killed $f5, implicit killed $f6, implicit killed $f7, implicit killed $f8, implicit killed $f9, implicit killed $f10, implicit killed $f11, implicit killed $f12, implicit killed $f13, implicit $r2, implicit-def $r1, implicit-def dead $f1 + ; 32BIT-NEXT: ADJCALLSTACKUP 128, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm + ; + ; 64BIT-LABEL: name: call_test_fpr_max + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: renamable $x3 = LDtoc @d1, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $f1 = LFD 0, killed renamable $x3 :: (dereferenceable load (s64) from @d1) + ; 64BIT-NEXT: ADJCALLSTACKDOWN 152, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: STFD renamable $f1, 144, $x1 :: (store (s64)) + ; 64BIT-NEXT: STFD renamable $f1, 136, $x1 :: (store (s64)) + ; 64BIT-NEXT: STFD renamable $f1, 128, $x1 :: (store (s64)) + ; 64BIT-NEXT: STFD renamable $f1, 120, $x1 :: (store (s64)) + ; 64BIT-NEXT: $f2 = COPY renamable $f1 + ; 64BIT-NEXT: $f3 = COPY renamable $f1 + ; 64BIT-NEXT: $f4 = COPY renamable $f1 + ; 64BIT-NEXT: $f5 = COPY renamable $f1 + ; 64BIT-NEXT: $f6 = COPY renamable $f1 + ; 64BIT-NEXT: $f7 = COPY renamable $f1 + ; 64BIT-NEXT: $f8 = COPY renamable $f1 + ; 64BIT-NEXT: $f9 = COPY renamable $f1 + ; 64BIT-NEXT: $f10 = COPY renamable $f1 + ; 64BIT-NEXT: $f11 = COPY renamable $f1 + ; 64BIT-NEXT: $f12 = COPY renamable $f1 + ; 64BIT-NEXT: $f13 = COPY renamable $f1 + ; 64BIT-NEXT: STFD renamable $f1, 112, $x1 :: (store (s64)) + ; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit killed $f4, implicit killed $f5, implicit killed $f6, implicit killed $f7, implicit killed $f8, implicit killed $f9, implicit killed $f10, implicit killed $f11, implicit killed $f12, implicit killed $f13, implicit $x2, implicit-def $r1, implicit-def dead $f1 + ; 64BIT-NEXT: ADJCALLSTACKUP 152, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm +entry: + %0 = load double, ptr @d1, align 8 + call double @test_fpr_max(double %0, double %0, double %0, double %0, double %0, double %0, double %0, double %0, double %0, double %0, double %0, double %0, double %0) + ret void +} + +define double @test_fpr_max(double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10, double %d11, double %d12, double %d13) { + ; 32BIT-LABEL: name: test_fpr_max + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: liveins: $f1, $f2, $f3, $f4, $f5, $f6, $f7, $f8, $f9, $f10, $f11, $f12, $f13 + ; 32BIT-NEXT: {{ $}} + ; 32BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f1, killed renamable $f2, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f3, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f4, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f5, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f6, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f7, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f8, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f9, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f10, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f11, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f12, implicit $rm + ; 32BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f0, killed renamable $f13, implicit $rm + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm, implicit $f1 + ; + ; 64BIT-LABEL: name: test_fpr_max + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: liveins: $f1, $f2, $f3, $f4, $f5, $f6, $f7, $f8, $f9, $f10, $f11, $f12, $f13 + ; 64BIT-NEXT: {{ $}} + ; 64BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f1, killed renamable $f2, implicit $rm + ; 64BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f3, implicit $rm + ; 64BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f4, implicit $rm + ; 64BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f5, implicit $rm + ; 64BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f6, implicit $rm + ; 64BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f7, implicit $rm + ; 64BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f8, implicit $rm + ; 64BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f9, implicit $rm + ; 64BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f10, implicit $rm + ; 64BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f11, implicit $rm + ; 64BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f12, implicit $rm + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f0, killed renamable $f13, implicit $rm + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $f1 +entry: + %add = fadd double %d1, %d2 + %add1 = fadd double %add, %d3 + %add2 = fadd double %add1, %d4 + %add3 = fadd double %add2, %d5 + %add4 = fadd double %add3, %d6 + %add5 = fadd double %add4, %d7 + %add6 = fadd double %add5, %d8 + %add7 = fadd double %add6, %d9 + %add8 = fadd double %add7, %d10 + %add9 = fadd double %add8, %d11 + %add10 = fadd double %add9, %d12 + %add11 = fadd double %add10, %d13 + ret double %add11 +} + +define void @call_test_mix() { + ; 32BIT-LABEL: name: call_test_mix + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: renamable $r3 = LWZtoc @f1, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $r4 = LWZtoc @d1, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f1 = LFS 0, killed renamable $r3 :: (dereferenceable load (s32) from @f1) + ; 32BIT-NEXT: renamable $f2 = LFD 0, killed renamable $r4 :: (dereferenceable load (s64) from @d1) + ; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: $r4 = LI 1 + ; 32BIT-NEXT: $r7 = LI 97 + ; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit $r4, implicit $f2, implicit killed $r7, implicit $r2, implicit-def $r1, implicit-def dead $r3 + ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm + ; + ; 64BIT-LABEL: name: call_test_mix + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: renamable $x3 = LDtoc @f1, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $x4 = LDtoc @d1, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x3 :: (dereferenceable load (s32) from @f1) + ; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x4 :: (dereferenceable load (s64) from @d1) + ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: $x4 = LI8 1 + ; 64BIT-NEXT: $x6 = LI8 97 + ; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $x4, implicit $f2, implicit killed $x6, implicit $x2, implicit-def $r1, implicit-def dead $x3 + ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm +entry: + %0 = load float, ptr @f1, align 4 + %1 = load double, ptr @d1, align 8 + call i32 @test_mix(float %0, i32 1, double %1, i8 signext 97) + ret void +} + +define i32 @test_mix(float %f, i32 signext %i, double %d, i8 signext %c) { + ; 32BIT-LABEL: name: test_mix + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: liveins: $f1, $f2, $r4, $r7 + ; 32BIT-NEXT: {{ $}} + ; 32BIT-NEXT: renamable $r3 = LIS 17200 + ; 32BIT-NEXT: STW killed renamable $r3, 0, %stack.1 :: (store (s32) into %stack.1, align 8) + ; 32BIT-NEXT: renamable $r3 = RLWINM killed renamable $r7, 0, 24, 31 + ; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r4, killed renamable $r3 + ; 32BIT-NEXT: renamable $r4 = LWZtoc %const.0, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $r3 = XORIS killed renamable $r3, 32768 + ; 32BIT-NEXT: STW killed renamable $r3, 4, %stack.1 :: (store (s32) into %stack.1 + 4) + ; 32BIT-NEXT: renamable $f0 = LFS 0, killed renamable $r4 :: (load (s32) from constant-pool) + ; 32BIT-NEXT: renamable $f3 = LFD 0, %stack.1 :: (load (s64) from %stack.1) + ; 32BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f2, implicit $rm + ; 32BIT-NEXT: renamable $f1 = nofpexcept FRSP killed renamable $f1, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FSUB killed renamable $f3, killed renamable $f0, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FRSP killed renamable $f0, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FADDS killed renamable $f0, killed renamable $f1, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FCTIWZ killed renamable $f0, implicit $rm + ; 32BIT-NEXT: STFD killed renamable $f0, 0, %stack.0 :: (store (s64) into %stack.0) + ; 32BIT-NEXT: renamable $r3 = LWZ 4, %stack.0 :: (load (s32) from %stack.0 + 4, basealign 8) + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm, implicit $r3 + ; + ; 64BIT-LABEL: name: test_mix + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: liveins: $f1, $f2, $x4, $x6 + ; 64BIT-NEXT: {{ $}} + ; 64BIT-NEXT: renamable $r3 = RLWINM renamable $r6, 0, 24, 31, implicit killed $x6 + ; 64BIT-NEXT: renamable $r3 = nsw ADD4 renamable $r4, killed renamable $r3, implicit killed $x4 + ; 64BIT-NEXT: renamable $x3 = EXTSW_32_64 killed renamable $r3 + ; 64BIT-NEXT: STD killed renamable $x3, 0, %stack.1 :: (store (s64) into %stack.1) + ; 64BIT-NEXT: renamable $f0 = LFD 0, %stack.1 :: (load (s64) from %stack.1) + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f2, implicit $rm + ; 64BIT-NEXT: renamable $f1 = nofpexcept FRSP killed renamable $f1, implicit $rm + ; 64BIT-NEXT: renamable $f0 = nofpexcept FCFID killed renamable $f0, implicit $rm + ; 64BIT-NEXT: renamable $f0 = nofpexcept FRSP killed renamable $f0, implicit $rm + ; 64BIT-NEXT: renamable $f0 = nofpexcept FADDS killed renamable $f0, killed renamable $f1, implicit $rm + ; 64BIT-NEXT: renamable $f0 = nofpexcept FCTIWZ killed renamable $f0, implicit $rm + ; 64BIT-NEXT: STFD killed renamable $f0, 0, %stack.0 :: (store (s64) into %stack.0) + ; 64BIT-NEXT: renamable $x3 = LWZ8 4, %stack.0 :: (load (s32) from %stack.0 + 4, basealign 8) + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3 +entry: + %conv = fpext float %f to double + %add = fadd double %conv, %d + %conv1 = fptrunc double %add to float + %conv2 = zext i8 %c to i32 + %add3 = add nsw i32 %i, %conv2 + %conv4 = sitofp i32 %add3 to float + %add5 = fadd float %conv4, %conv1 + %conv6 = fptosi float %add5 to i32 + ret i32 %conv6 +} + +define i64 @callee_mixed_ints(i32 %a, i8 signext %b, i32 %c, i16 signext %d, i64 %e) { + ; 32BIT-LABEL: name: callee_mixed_ints + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: liveins: $r3, $r4, $r5, $r6, $r7, $r8 + ; 32BIT-NEXT: {{ $}} + ; 32BIT-NEXT: renamable $r4 = RLWINM killed renamable $r4, 0, 24, 31 + ; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r4 + ; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r5 + ; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r6 + ; 32BIT-NEXT: renamable $r5 = SRAWI renamable $r3, 31, implicit-def dead $carry + ; 32BIT-NEXT: renamable $r4 = ADDC killed renamable $r3, killed renamable $r8, implicit-def $carry + ; 32BIT-NEXT: renamable $r3 = ADDE killed renamable $r5, killed renamable $r7, implicit-def dead $carry, implicit killed $carry + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm, implicit $r3, implicit $r4 + ; + ; 64BIT-LABEL: name: callee_mixed_ints + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: liveins: $x3, $x4, $x5, $x6, $x7 + ; 64BIT-NEXT: {{ $}} + ; 64BIT-NEXT: renamable $r4 = RLWINM renamable $r4, 0, 24, 31, implicit killed $x4 + ; 64BIT-NEXT: renamable $r3 = nsw ADD4 renamable $r3, killed renamable $r4, implicit killed $x3 + ; 64BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r5, implicit killed $x5 + ; 64BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r6, implicit killed $x6 + ; 64BIT-NEXT: renamable $x3 = EXTSW_32_64 killed renamable $r3 + ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x7 + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3 +entry: + %conv = zext i8 %b to i32 + %add = add nsw i32 %a, %conv + %add1 = add nsw i32 %add, %c + %conv2 = sext i16 %d to i32 + %add3 = add nsw i32 %add1, %conv2 + %conv4 = sext i32 %add3 to i64 + %add5 = add nsw i64 %conv4, %e + ret i64 %add5 + } + +define void @call_test_vararg() { + ; 32BIT-LABEL: name: call_test_vararg + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: renamable $r3 = LWZtoc @f1, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f1 = LFS 0, killed renamable $r3 :: (dereferenceable load (s32) from @f1) + ; 32BIT-NEXT: renamable $r3 = LWZtoc @d1, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: STFD renamable $f1, 0, %stack.1 :: (store (s64) into %stack.1) + ; 32BIT-NEXT: renamable $r4 = LWZ 0, %stack.1 :: (load (s32) from %stack.1, align 8) + ; 32BIT-NEXT: renamable $f2 = LFD 0, killed renamable $r3 :: (dereferenceable load (s64) from @d1) + ; 32BIT-NEXT: renamable $r5 = LWZ 4, %stack.1 :: (load (s32) from %stack.1 + 4) + ; 32BIT-NEXT: STFD renamable $f2, 0, %stack.0 :: (store (s64) into %stack.0) + ; 32BIT-NEXT: renamable $r6 = LWZ 0, %stack.0 :: (load (s32) from %stack.0, align 8) + ; 32BIT-NEXT: renamable $r7 = LWZ 4, %stack.0 :: (load (s32) from %stack.0 + 4) + ; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: $r3 = LI 42 + ; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit $f2, implicit $r6, implicit $r7, implicit $r2, implicit-def $r1 + ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm + ; + ; 64BIT-LABEL: name: call_test_vararg + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: renamable $x3 = LDtoc @f1, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x3 :: (dereferenceable load (s32) from @f1) + ; 64BIT-NEXT: renamable $x3 = LDtoc @d1, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: STFD renamable $f1, 0, %stack.1 :: (store (s64) into %stack.1) + ; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x3 :: (dereferenceable load (s64) from @d1) + ; 64BIT-NEXT: renamable $x4 = LD 0, %stack.1 :: (load (s64) from %stack.1) + ; 64BIT-NEXT: STFD renamable $f2, 0, %stack.0 :: (store (s64) into %stack.0) + ; 64BIT-NEXT: renamable $x5 = LD 0, %stack.0 :: (load (s64) from %stack.0) + ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: $x3 = LI8 42 + ; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $f2, implicit $x5, implicit $x2, implicit-def $r1 + ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm +entry: + %0 = load float, ptr @f1, align 4 + %conv = fpext float %0 to double + %1 = load double, ptr @d1, align 8 + call void (i32, ...) @test_vararg(i32 42, double %conv, double %1) + ret void +} + +declare void @test_vararg(i32, ...) + +define void @call_test_vararg2() { + ; 32BIT-LABEL: name: call_test_vararg2 + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: renamable $r3 = LWZtoc @f1, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f1 = LFS 0, killed renamable $r3 :: (dereferenceable load (s32) from @f1) + ; 32BIT-NEXT: renamable $r3 = LWZtoc @d1, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: STFD renamable $f1, 0, %stack.1 :: (store (s64) into %stack.1) + ; 32BIT-NEXT: renamable $r4 = LWZ 0, %stack.1 :: (load (s32) from %stack.1, align 8) + ; 32BIT-NEXT: renamable $f2 = LFD 0, killed renamable $r3 :: (dereferenceable load (s64) from @d1) + ; 32BIT-NEXT: renamable $r5 = LWZ 4, %stack.1 :: (load (s32) from %stack.1 + 4) + ; 32BIT-NEXT: STFD renamable $f2, 0, %stack.0 :: (store (s64) into %stack.0) + ; 32BIT-NEXT: renamable $r7 = LWZ 0, %stack.0 :: (load (s32) from %stack.0, align 8) + ; 32BIT-NEXT: renamable $r8 = LWZ 4, %stack.0 :: (load (s32) from %stack.0 + 4) + ; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: $r3 = LI 42 + ; 32BIT-NEXT: $r6 = LI 42 + ; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit killed $r6, implicit $f2, implicit $r7, implicit $r8, implicit $r2, implicit-def $r1 + ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm + ; + ; 64BIT-LABEL: name: call_test_vararg2 + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: renamable $x3 = LDtoc @f1, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x3 :: (dereferenceable load (s32) from @f1) + ; 64BIT-NEXT: renamable $x3 = LDtoc @d1, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: STFD renamable $f1, 0, %stack.1 :: (store (s64) into %stack.1) + ; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x3 :: (dereferenceable load (s64) from @d1) + ; 64BIT-NEXT: renamable $x4 = LD 0, %stack.1 :: (load (s64) from %stack.1) + ; 64BIT-NEXT: STFD renamable $f2, 0, %stack.0 :: (store (s64) into %stack.0) + ; 64BIT-NEXT: renamable $x6 = LD 0, %stack.0 :: (load (s64) from %stack.0) + ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: $x3 = LI8 42 + ; 64BIT-NEXT: $x5 = LI8 42 + ; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1 + ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm +entry: + %0 = load float, ptr @f1, align 4 + %conv = fpext float %0 to double + %1 = load double, ptr @d1, align 8 + call void (i32, ...) @test_vararg(i32 42, double %conv, i32 42, double %1) + ret void +} + +define void @call_test_vararg3() { + ; 32BIT-LABEL: name: call_test_vararg3 + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: renamable $r3 = LWZtoc @f1, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f1 = LFS 0, killed renamable $r3 :: (dereferenceable load (s32) from @f1) + ; 32BIT-NEXT: renamable $r3 = LWZtoc @d1, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: STFD renamable $f1, 0, %stack.1 :: (store (s64) into %stack.1) + ; 32BIT-NEXT: renamable $r4 = LWZ 0, %stack.1 :: (load (s32) from %stack.1, align 8) + ; 32BIT-NEXT: renamable $f2 = LFD 0, killed renamable $r3 :: (dereferenceable load (s64) from @d1) + ; 32BIT-NEXT: renamable $r5 = LWZ 4, %stack.1 :: (load (s32) from %stack.1 + 4) + ; 32BIT-NEXT: STFD renamable $f2, 0, %stack.0 :: (store (s64) into %stack.0) + ; 32BIT-NEXT: renamable $r8 = LWZ 0, %stack.0 :: (load (s32) from %stack.0, align 8) + ; 32BIT-NEXT: renamable $r9 = LWZ 4, %stack.0 :: (load (s32) from %stack.0 + 4) + ; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: $r3 = LI 42 + ; 32BIT-NEXT: $r6 = LI 0 + ; 32BIT-NEXT: $r7 = LI 42 + ; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit killed $r6, implicit killed $r7, implicit $f2, implicit $r8, implicit $r9, implicit $r2, implicit-def $r1 + ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm + ; + ; 64BIT-LABEL: name: call_test_vararg3 + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: renamable $x3 = LDtoc @f1, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x3 :: (dereferenceable load (s32) from @f1) + ; 64BIT-NEXT: renamable $x3 = LDtoc @d1, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: STFD renamable $f1, 0, %stack.1 :: (store (s64) into %stack.1) + ; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x3 :: (dereferenceable load (s64) from @d1) + ; 64BIT-NEXT: renamable $x4 = LD 0, %stack.1 :: (load (s64) from %stack.1) + ; 64BIT-NEXT: STFD renamable $f2, 0, %stack.0 :: (store (s64) into %stack.0) + ; 64BIT-NEXT: renamable $x6 = LD 0, %stack.0 :: (load (s64) from %stack.0) + ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: $x3 = LI8 42 + ; 64BIT-NEXT: $x5 = LI8 42 + ; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1 + ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm +entry: + %0 = load float, ptr @f1, align 4 + %conv = fpext float %0 to double + %1 = load double, ptr @d1, align 8 + call void (i32, ...) @test_vararg(i32 42, double %conv, i64 42, double %1) + ret void +} + +define void @call_test_vararg4() { + ; 32BIT-LABEL: name: call_test_vararg4 + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: renamable $r3 = LWZtoc @f1, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f1 = LFS 0, killed renamable $r3 :: (dereferenceable load (s32) from @f1) + ; 32BIT-NEXT: STFS renamable $f1, 0, %stack.0 :: (store (s32) into %stack.0) + ; 32BIT-NEXT: renamable $r4 = LWZ 0, %stack.0 :: (load (s32) from %stack.0) + ; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: $r3 = LI 42 + ; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r2, implicit-def $r1 + ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm + ; + ; 64BIT-LABEL: name: call_test_vararg4 + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: renamable $x3 = LDtoc @f1, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x3 :: (dereferenceable load (s32) from @f1) + ; 64BIT-NEXT: STFS renamable $f1, 0, %stack.0 :: (store (s32) into %stack.0) + ; 64BIT-NEXT: renamable $x4 = LWZ8 0, %stack.0 :: (load (s32) from %stack.0) + ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: $x3 = LI8 42 + ; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $x2, implicit-def $r1 + ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm +entry: + %0 = load float, ptr @f1, align 4 + call void (i32, ...) @test_vararg(i32 42, float %0) + ret void +} + +@c = common global i8 0, align 1 +@si = common global i16 0, align 2 +@i = common global i32 0, align 4 +@lli = common global i64 0, align 8 +@f = common global float 0.000000e+00, align 4 +@d = common global double 0.000000e+00, align 8 + +; Basic saving of integral type arguments to the parameter save area. +define void @call_test_stackarg_int() { + ; 32BIT-LABEL: name: call_test_stackarg_int + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: renamable $r3 = LWZtoc @c, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $r4 = LWZtoc @si, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $r5 = LWZtoc @i, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $r11 = LBZ 0, killed renamable $r3 :: (dereferenceable load (s8) from @c) + ; 32BIT-NEXT: renamable $r3 = LWZtoc @lli, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $r4 = LHA 0, killed renamable $r4 :: (dereferenceable load (s16) from @si) + ; 32BIT-NEXT: renamable $r5 = LWZ 0, killed renamable $r5 :: (dereferenceable load (s32) from @i) + ; 32BIT-NEXT: renamable $r6 = LWZ 0, renamable $r3 :: (dereferenceable load (s32) from @lli, align 8) + ; 32BIT-NEXT: renamable $r3 = LWZ 4, killed renamable $r3 :: (dereferenceable load (s32) from @lli + 4, basealign 8) + ; 32BIT-NEXT: ADJCALLSTACKDOWN 80, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: STW renamable $r5, 76, $r1 :: (store (s32)) + ; 32BIT-NEXT: STW killed renamable $r3, 72, $r1 :: (store (s32)) + ; 32BIT-NEXT: STW killed renamable $r6, 68, $r1 :: (store (s32)) + ; 32BIT-NEXT: STW killed renamable $r5, 64, $r1 :: (store (s32)) + ; 32BIT-NEXT: STW killed renamable $r4, 60, $r1 :: (store (s32)) + ; 32BIT-NEXT: $r3 = LI 1 + ; 32BIT-NEXT: $r4 = LI 2 + ; 32BIT-NEXT: $r5 = LI 3 + ; 32BIT-NEXT: $r6 = LI 4 + ; 32BIT-NEXT: $r7 = LI 5 + ; 32BIT-NEXT: $r8 = LI 6 + ; 32BIT-NEXT: $r9 = LI 7 + ; 32BIT-NEXT: $r10 = LI 8 + ; 32BIT-NEXT: STW killed renamable $r11, 56, $r1 :: (store (s32)) + ; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1 + ; 32BIT-NEXT: ADJCALLSTACKUP 80, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm + ; + ; 64BIT-LABEL: name: call_test_stackarg_int + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: renamable $x3 = LDtoc @c, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $x4 = LDtoc @si, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $x5 = LDtoc @i, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $x6 = LDtoc @lli, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $x11 = LBZ8 0, killed renamable $x3 :: (dereferenceable load (s8) from @c) + ; 64BIT-NEXT: renamable $x12 = LHA8 0, killed renamable $x4 :: (dereferenceable load (s16) from @si) + ; 64BIT-NEXT: renamable $x0 = LWZ8 0, killed renamable $x5 :: (dereferenceable load (s32) from @i) + ; 64BIT-NEXT: renamable $x31 = LD 0, killed renamable $x6 :: (dereferenceable load (s64) from @lli) + ; 64BIT-NEXT: ADJCALLSTACKDOWN 152, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: $x3 = LI8 1 + ; 64BIT-NEXT: $x4 = LI8 2 + ; 64BIT-NEXT: $x5 = LI8 3 + ; 64BIT-NEXT: $x6 = LI8 4 + ; 64BIT-NEXT: $x7 = LI8 5 + ; 64BIT-NEXT: $x8 = LI8 6 + ; 64BIT-NEXT: $x9 = LI8 7 + ; 64BIT-NEXT: $x10 = LI8 8 + ; 64BIT-NEXT: STD killed renamable $x31, 136, $x1 :: (store (s64)) + ; 64BIT-NEXT: STD renamable $x0, 144, $x1 :: (store (s64)) + ; 64BIT-NEXT: STD killed renamable $x0, 128, $x1 :: (store (s64)) + ; 64BIT-NEXT: STD killed renamable $x12, 120, $x1 :: (store (s64)) + ; 64BIT-NEXT: STD killed renamable $x11, 112, $x1 :: (store (s64)) + ; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1 + ; 64BIT-NEXT: ADJCALLSTACKUP 152, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm +entry: + %0 = load i8, ptr @c, align 1 + %1 = load i16, ptr @si, align 2 + %2 = load i32, ptr @i, align 4 + %3 = load i64, ptr @lli, align 8 + %4 = load i32, ptr @i, align 4 + call void @test_stackarg_int(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i8 zeroext %0, i16 signext %1, i32 %2, i64 %3, i32 %4) + ret void +} + +declare void @test_stackarg_int(i32, i32, i32, i32, i32, i32, i32, i32, i8 zeroext, i16 signext, i32, i64, i32) + +; Basic saving of floating point type arguments to the parameter save area. +; The float and double arguments will pass in both fpr as well as parameter save area. +define void @call_test_stackarg_float() { + ; 32BIT-LABEL: name: call_test_stackarg_float + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: renamable $r3 = LWZtoc @f, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $r4 = LWZtoc @d, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f1 = LFS 0, killed renamable $r3 :: (dereferenceable load (s32) from @f) + ; 32BIT-NEXT: renamable $f2 = LFD 0, killed renamable $r4 :: (dereferenceable load (s64) from @d) + ; 32BIT-NEXT: ADJCALLSTACKDOWN 68, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: STFD renamable $f2, 60, $r1 :: (store (s64)) + ; 32BIT-NEXT: $r3 = LI 1 + ; 32BIT-NEXT: $r4 = LI 2 + ; 32BIT-NEXT: $r5 = LI 3 + ; 32BIT-NEXT: $r6 = LI 4 + ; 32BIT-NEXT: $r7 = LI 5 + ; 32BIT-NEXT: $r8 = LI 6 + ; 32BIT-NEXT: $r9 = LI 7 + ; 32BIT-NEXT: $r10 = LI 8 + ; 32BIT-NEXT: STFS renamable $f1, 56, $r1 :: (store (s32)) + ; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit killed $r10, implicit $f1, implicit $f2, implicit $r2, implicit-def $r1 + ; 32BIT-NEXT: ADJCALLSTACKUP 68, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm + ; + ; 64BIT-LABEL: name: call_test_stackarg_float + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: renamable $x3 = LDtoc @f, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $x4 = LDtoc @d, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x3 :: (dereferenceable load (s32) from @f) + ; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x4 :: (dereferenceable load (s64) from @d) + ; 64BIT-NEXT: ADJCALLSTACKDOWN 128, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: STFD renamable $f2, 120, $x1 :: (store (s64)) + ; 64BIT-NEXT: $x3 = LI8 1 + ; 64BIT-NEXT: $x4 = LI8 2 + ; 64BIT-NEXT: $x5 = LI8 3 + ; 64BIT-NEXT: $x6 = LI8 4 + ; 64BIT-NEXT: $x7 = LI8 5 + ; 64BIT-NEXT: $x8 = LI8 6 + ; 64BIT-NEXT: $x9 = LI8 7 + ; 64BIT-NEXT: $x10 = LI8 8 + ; 64BIT-NEXT: STFS renamable $f1, 112, $x1 :: (store (s32)) + ; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit killed $x10, implicit $f1, implicit $f2, implicit $x2, implicit-def $r1 + ; 64BIT-NEXT: ADJCALLSTACKUP 128, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm +entry: + %0 = load float, ptr @f, align 4 + %1 = load double, ptr @d, align 8 + call void @test_stackarg_float(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, float %0, double %1) + ret void +} + +declare void @test_stackarg_float(i32, i32, i32, i32, i32, i32, i32, i32, float, double) + +define void @call_test_stackarg_float2() { + ; 32BIT-LABEL: name: call_test_stackarg_float2 + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: renamable $r3 = LWZtoc @d, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f1 = LFD 0, killed renamable $r3 :: (dereferenceable load (s64) from @d) + ; 32BIT-NEXT: STFD renamable $f1, 0, %stack.0 :: (store (s64) into %stack.0) + ; 32BIT-NEXT: renamable $r9 = LWZ 0, %stack.0 :: (load (s32) from %stack.0, align 8) + ; 32BIT-NEXT: renamable $r10 = LWZ 4, %stack.0 :: (load (s32) from %stack.0 + 4) + ; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: $r3 = LI 1 + ; 32BIT-NEXT: $r4 = LI 2 + ; 32BIT-NEXT: $r5 = LI 3 + ; 32BIT-NEXT: $r6 = LI 4 + ; 32BIT-NEXT: $r7 = LI 5 + ; 32BIT-NEXT: $r8 = LI 6 + ; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit $f1, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1 + ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm + ; + ; 64BIT-LABEL: name: call_test_stackarg_float2 + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: renamable $x3 = LDtoc @d, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $f1 = LFD 0, killed renamable $x3 :: (dereferenceable load (s64) from @d) + ; 64BIT-NEXT: STFD renamable $f1, 0, %stack.0 :: (store (s64) into %stack.0) + ; 64BIT-NEXT: renamable $x9 = LD 0, %stack.0 :: (load (s64) from %stack.0) + ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: $x3 = LI8 1 + ; 64BIT-NEXT: $x4 = LI8 2 + ; 64BIT-NEXT: $x5 = LI8 3 + ; 64BIT-NEXT: $x6 = LI8 4 + ; 64BIT-NEXT: $x7 = LI8 5 + ; 64BIT-NEXT: $x8 = LI8 6 + ; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit $f1, implicit $x9, implicit $x2, implicit-def $r1 + ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm +entry: + %0 = load double, ptr @d, align 8 + call void (i32, i32, i32, i32, i32, i32, ...) @test_stackarg_float2(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, double %0) + ret void +} + +declare void @test_stackarg_float2(i32, i32, i32, i32, i32, i32, ...) + +; A double arg will pass on the stack in PPC32 if there is only one available GPR. +define void @call_test_stackarg_float3() { + ; 32BIT-LABEL: name: call_test_stackarg_float3 + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: renamable $r3 = LWZtoc @d, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f1 = LFD 0, killed renamable $r3 :: (dereferenceable load (s64) from @d) + ; 32BIT-NEXT: renamable $r3 = LWZtoc @f, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: STFD renamable $f1, 0, %stack.0 :: (store (s64) into %stack.0) + ; 32BIT-NEXT: renamable $r10 = LWZ 0, %stack.0 :: (load (s32) from %stack.0, align 8) + ; 32BIT-NEXT: renamable $f2 = LFS 0, killed renamable $r3 :: (dereferenceable load (s32) from @f) + ; 32BIT-NEXT: ADJCALLSTACKDOWN 64, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: STFS renamable $f2, 60, $r1 :: (store (s32)) + ; 32BIT-NEXT: $r3 = LI 1 + ; 32BIT-NEXT: $r4 = LI 2 + ; 32BIT-NEXT: $r5 = LI 3 + ; 32BIT-NEXT: $r6 = LI 4 + ; 32BIT-NEXT: $r7 = LI 5 + ; 32BIT-NEXT: $r8 = LI 6 + ; 32BIT-NEXT: $r9 = LI 7 + ; 32BIT-NEXT: STFD renamable $f1, 52, $r1 :: (store (s64)) + ; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit $f1, implicit $r10, implicit $f2, implicit $r2, implicit-def $r1 + ; 32BIT-NEXT: ADJCALLSTACKUP 64, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm + ; + ; 64BIT-LABEL: name: call_test_stackarg_float3 + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: renamable $x3 = LDtoc @d, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $f1 = LFD 0, killed renamable $x3 :: (dereferenceable load (s64) from @d) + ; 64BIT-NEXT: renamable $x3 = LDtoc @f, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: STFD renamable $f1, 0, %stack.0 :: (store (s64) into %stack.0) + ; 64BIT-NEXT: renamable $x10 = LD 0, %stack.0 :: (load (s64) from %stack.0) + ; 64BIT-NEXT: renamable $f2 = LFS 0, killed renamable $x3 :: (dereferenceable load (s32) from @f) + ; 64BIT-NEXT: ADJCALLSTACKDOWN 120, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: $x3 = LI8 1 + ; 64BIT-NEXT: $x4 = LI8 2 + ; 64BIT-NEXT: $x5 = LI8 3 + ; 64BIT-NEXT: $x6 = LI8 4 + ; 64BIT-NEXT: $x7 = LI8 5 + ; 64BIT-NEXT: $x8 = LI8 6 + ; 64BIT-NEXT: $x9 = LI8 7 + ; 64BIT-NEXT: STFS renamable $f2, 112, $x1 :: (store (s32)) + ; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit $f1, implicit $x10, implicit $f2, implicit $x2, implicit-def $r1 + ; 64BIT-NEXT: ADJCALLSTACKUP 120, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm +entry: + %0 = load double, ptr @d, align 8 + %1 = load float, ptr @f, align 4 + call void (i32, i32, i32, i32, i32, i32, i32, ...) @test_stackarg_float3(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, double %0, float %1) + ret void +} + +declare void @test_stackarg_float3(i32, i32, i32, i32, i32, i32, i32, ...) + +define i64 @test_ints_stack(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i64 %ll9, i16 signext %s10, i8 zeroext %c11, i32 %ui12, i32 %si13, i64 %ll14, i8 zeroext %uc15, i32 %i16) { + ; 32BIT-LABEL: name: test_ints_stack + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: liveins: $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10 + ; 32BIT-NEXT: {{ $}} + ; 32BIT-NEXT: renamable $r11 = LWZ 0, %fixed-stack.0 :: (load (s32) from %fixed-stack.0) + ; 32BIT-NEXT: renamable $r12 = LWZ 0, %fixed-stack.4 :: (load (s32) from %fixed-stack.4) + ; 32BIT-NEXT: renamable $r0 = LWZ 0, %fixed-stack.1 :: (load (s32) from %fixed-stack.1, align 8) + ; 32BIT-NEXT: renamable $r31 = LWZ 4, %fixed-stack.3 :: (load (s32) from %fixed-stack.3 + 4, basealign 16) + ; 32BIT-NEXT: renamable $r30 = LWZ 0, %fixed-stack.3 :: (load (s32) from %fixed-stack.3, align 16) + ; 32BIT-NEXT: renamable $r29 = LWZ 0, %fixed-stack.5 :: (load (s32) from %fixed-stack.5, align 8) + ; 32BIT-NEXT: renamable $r28 = LWZ 0, %fixed-stack.6 :: (load (s32) from %fixed-stack.6) + ; 32BIT-NEXT: renamable $r27 = LWZ 0, %fixed-stack.7 :: (load (s32) from %fixed-stack.7, align 16) + ; 32BIT-NEXT: renamable $r26 = LWZ 4, %fixed-stack.9 :: (load (s32) from %fixed-stack.9 + 4, basealign 8) + ; 32BIT-NEXT: renamable $r25 = LWZ 0, %fixed-stack.9 :: (load (s32) from %fixed-stack.9, align 8) + ; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r4 + ; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r5 + ; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r6 + ; 32BIT-NEXT: renamable $r5 = SRAWI renamable $r11, 31, implicit-def dead $carry + ; 32BIT-NEXT: renamable $r4 = SRAWI renamable $r12, 31, implicit-def dead $carry + ; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r7 + ; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r8 + ; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r9 + ; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r10 + ; 32BIT-NEXT: renamable $r6 = SRAWI renamable $r3, 31, implicit-def dead $carry + ; 32BIT-NEXT: renamable $r3 = ADDC killed renamable $r3, killed renamable $r26, implicit-def $carry + ; 32BIT-NEXT: renamable $r6 = ADDE killed renamable $r6, killed renamable $r25, implicit-def dead $carry, implicit $carry + ; 32BIT-NEXT: renamable $r7 = SRAWI renamable $r27, 31, implicit-def dead $carry + ; 32BIT-NEXT: renamable $r3 = ADDC killed renamable $r3, killed renamable $r27, implicit-def $carry + ; 32BIT-NEXT: renamable $r6 = ADDE killed renamable $r6, killed renamable $r7, implicit-def dead $carry, implicit $carry + ; 32BIT-NEXT: renamable $r3 = ADDC killed renamable $r3, killed renamable $r28, implicit-def $carry + ; 32BIT-NEXT: renamable $r6 = ADDZE killed renamable $r6, implicit-def dead $carry, implicit $carry + ; 32BIT-NEXT: renamable $r3 = ADDC killed renamable $r3, killed renamable $r29, implicit-def $carry + ; 32BIT-NEXT: renamable $r6 = ADDZE killed renamable $r6, implicit-def dead $carry, implicit $carry + ; 32BIT-NEXT: renamable $r3 = ADDC killed renamable $r3, killed renamable $r12, implicit-def $carry + ; 32BIT-NEXT: renamable $r4 = ADDE killed renamable $r6, killed renamable $r4, implicit-def dead $carry, implicit $carry + ; 32BIT-NEXT: renamable $r3 = ADDC killed renamable $r3, killed renamable $r31, implicit-def $carry + ; 32BIT-NEXT: renamable $r4 = ADDE killed renamable $r4, killed renamable $r30, implicit-def dead $carry, implicit $carry + ; 32BIT-NEXT: renamable $r3 = ADDC killed renamable $r3, killed renamable $r0, implicit-def $carry + ; 32BIT-NEXT: renamable $r6 = ADDZE killed renamable $r4, implicit-def dead $carry, implicit $carry + ; 32BIT-NEXT: renamable $r4 = ADDC killed renamable $r3, killed renamable $r11, implicit-def $carry + ; 32BIT-NEXT: renamable $r3 = ADDE killed renamable $r6, killed renamable $r5, implicit-def dead $carry, implicit $carry + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm, implicit $r3, implicit $r4 + ; + ; 64BIT-LABEL: name: test_ints_stack + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: liveins: $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10 + ; 64BIT-NEXT: {{ $}} + ; 64BIT-NEXT: renamable $r11 = LWZ 0, %fixed-stack.1, implicit-def $x11 :: (load (s32) from %fixed-stack.1) + ; 64BIT-NEXT: renamable $x12 = LWZ8 0, %fixed-stack.4 :: (load (s32) from %fixed-stack.4) + ; 64BIT-NEXT: renamable $x0 = LWA 0, %fixed-stack.0 :: (load (s32) from %fixed-stack.0) + ; 64BIT-NEXT: renamable $x31 = LD 0, %fixed-stack.2 :: (load (s64) from %fixed-stack.2) + ; 64BIT-NEXT: renamable $x30 = LWA 0, %fixed-stack.3 :: (load (s32) from %fixed-stack.3) + ; 64BIT-NEXT: renamable $r29 = LWZ 0, %fixed-stack.5, implicit-def $x29 :: (load (s32) from %fixed-stack.5) + ; 64BIT-NEXT: renamable $x28 = LWA 0, %fixed-stack.6 :: (load (s32) from %fixed-stack.6) + ; 64BIT-NEXT: renamable $x27 = LD 0, %fixed-stack.7 :: (load (s64) from %fixed-stack.7, align 16) + ; 64BIT-NEXT: renamable $r3 = nsw ADD4 renamable $r3, renamable $r4, implicit killed $x4, implicit killed $x3 + ; 64BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r5, implicit killed $x5 + ; 64BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r6, implicit killed $x6 + ; 64BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r7, implicit killed $x7 + ; 64BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r8, implicit killed $x8 + ; 64BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r9, implicit killed $x9 + ; 64BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r10, implicit killed $x10 + ; 64BIT-NEXT: renamable $x3 = EXTSW_32_64 killed renamable $r3 + ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x27 + ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x28 + ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x29 + ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x12 + ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x30 + ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x31 + ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x11 + ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x0 + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3 +entry: + %add = add nsw i32 %i1, %i2 + %add1 = add nsw i32 %add, %i3 + %add2 = add nsw i32 %add1, %i4 + %add3 = add nsw i32 %add2, %i5 + %add4 = add nsw i32 %add3, %i6 + %add5 = add nsw i32 %add4, %i7 + %add6 = add nsw i32 %add5, %i8 + %conv = sext i32 %add6 to i64 + %add7 = add nsw i64 %conv, %ll9 + %conv8 = sext i16 %s10 to i64 + %add9 = add nsw i64 %add7, %conv8 + %conv10 = zext i8 %c11 to i64 + %add11 = add nsw i64 %add9, %conv10 + %conv12 = zext i32 %ui12 to i64 + %add13 = add nsw i64 %add11, %conv12 + %conv14 = sext i32 %si13 to i64 + %add15 = add nsw i64 %add13, %conv14 + %add16 = add nsw i64 %add15, %ll14 + %conv17 = zext i8 %uc15 to i64 + %add18 = add nsw i64 %add16, %conv17 + %conv19 = sext i32 %i16 to i64 + %add20 = add nsw i64 %add18, %conv19 + ret i64 %add20 +} + +@ll1 = common global i64 0, align 8 +@si1 = common global i16 0, align 2 +@ch = common global i8 0, align 1 +@ui = common global i32 0, align 4 +@sint = common global i32 0, align 4 +@ll2 = common global i64 0, align 8 +@uc1 = common global i8 0, align 1 +@i1 = common global i32 0, align 4 + +define void @caller_ints_stack() { + ; 32BIT-LABEL: name: caller_ints_stack + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: renamable $r3 = LWZtoc @ll1, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $r4 = LWZtoc @si1, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $r11 = LWZ 0, renamable $r3 :: (dereferenceable load (s32) from @ll1, align 8) + ; 32BIT-NEXT: renamable $r5 = LWZtoc @ch, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $r3 = LWZ 4, killed renamable $r3 :: (dereferenceable load (s32) from @ll1 + 4, basealign 8) + ; 32BIT-NEXT: renamable $r6 = LWZtoc @ui, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $r4 = LHA 0, killed renamable $r4 :: (dereferenceable load (s16) from @si1) + ; 32BIT-NEXT: renamable $r7 = LWZtoc @sint, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $r5 = LBZ 0, killed renamable $r5 :: (dereferenceable load (s8) from @ch) + ; 32BIT-NEXT: renamable $r8 = LWZtoc @ll2, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $r6 = LWZ 0, killed renamable $r6 :: (dereferenceable load (s32) from @ui) + ; 32BIT-NEXT: renamable $r7 = LWZ 0, killed renamable $r7 :: (dereferenceable load (s32) from @sint) + ; 32BIT-NEXT: renamable $r9 = LWZtoc @uc1, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $r10 = LWZ 0, renamable $r8 :: (dereferenceable load (s32) from @ll2, align 8) + ; 32BIT-NEXT: renamable $r12 = LWZtoc @i1, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $r8 = LWZ 4, killed renamable $r8 :: (dereferenceable load (s32) from @ll2 + 4, basealign 8) + ; 32BIT-NEXT: renamable $r9 = LBZ 0, killed renamable $r9 :: (dereferenceable load (s8) from @uc1) + ; 32BIT-NEXT: renamable $r12 = LWZ 0, killed renamable $r12 :: (dereferenceable load (s32) from @i1) + ; 32BIT-NEXT: ADJCALLSTACKDOWN 96, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: STW killed renamable $r12, 92, $r1 :: (store (s32)) + ; 32BIT-NEXT: STW killed renamable $r9, 88, $r1 :: (store (s32)) + ; 32BIT-NEXT: STW killed renamable $r8, 84, $r1 :: (store (s32)) + ; 32BIT-NEXT: STW killed renamable $r10, 80, $r1 :: (store (s32)) + ; 32BIT-NEXT: STW killed renamable $r7, 76, $r1 :: (store (s32)) + ; 32BIT-NEXT: STW killed renamable $r6, 72, $r1 :: (store (s32)) + ; 32BIT-NEXT: STW killed renamable $r5, 68, $r1 :: (store (s32)) + ; 32BIT-NEXT: STW killed renamable $r4, 64, $r1 :: (store (s32)) + ; 32BIT-NEXT: STW killed renamable $r3, 60, $r1 :: (store (s32)) + ; 32BIT-NEXT: $r3 = LI 1 + ; 32BIT-NEXT: $r4 = LI 2 + ; 32BIT-NEXT: $r5 = LI 3 + ; 32BIT-NEXT: $r6 = LI 4 + ; 32BIT-NEXT: $r7 = LI 5 + ; 32BIT-NEXT: $r8 = LI 6 + ; 32BIT-NEXT: $r9 = LI 7 + ; 32BIT-NEXT: $r10 = LI 8 + ; 32BIT-NEXT: STW killed renamable $r11, 56, $r1 :: (store (s32)) + ; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1, implicit-def dead $r3, implicit-def dead $r4 + ; 32BIT-NEXT: ADJCALLSTACKUP 96, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm + ; + ; 64BIT-LABEL: name: caller_ints_stack + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: renamable $x3 = LDtoc @si1, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $x4 = LDtoc @ch, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $x5 = LDtoc @ui, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $x11 = LHA8 0, killed renamable $x3 :: (dereferenceable load (s16) from @si1) + ; 64BIT-NEXT: renamable $x3 = LDtoc @sint, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $x12 = LBZ8 0, killed renamable $x4 :: (dereferenceable load (s8) from @ch) + ; 64BIT-NEXT: renamable $x4 = LDtoc @uc1, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $x0 = LWZ8 0, killed renamable $x5 :: (dereferenceable load (s32) from @ui) + ; 64BIT-NEXT: renamable $x5 = LDtoc @ll1, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $x6 = LDtoc @ll2, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $x7 = LDtoc @i1, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $x31 = LWZ8 0, killed renamable $x3 :: (dereferenceable load (s32) from @sint) + ; 64BIT-NEXT: renamable $x30 = LBZ8 0, killed renamable $x4 :: (dereferenceable load (s8) from @uc1) + ; 64BIT-NEXT: renamable $x29 = LD 0, killed renamable $x5 :: (dereferenceable load (s64) from @ll1) + ; 64BIT-NEXT: renamable $x28 = LD 0, killed renamable $x6 :: (dereferenceable load (s64) from @ll2) + ; 64BIT-NEXT: renamable $x27 = LWZ8 0, killed renamable $x7 :: (dereferenceable load (s32) from @i1) + ; 64BIT-NEXT: ADJCALLSTACKDOWN 176, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: $x3 = LI8 1 + ; 64BIT-NEXT: $x4 = LI8 2 + ; 64BIT-NEXT: $x5 = LI8 3 + ; 64BIT-NEXT: $x6 = LI8 4 + ; 64BIT-NEXT: $x7 = LI8 5 + ; 64BIT-NEXT: $x8 = LI8 6 + ; 64BIT-NEXT: $x9 = LI8 7 + ; 64BIT-NEXT: $x10 = LI8 8 + ; 64BIT-NEXT: STD killed renamable $x27, 168, $x1 :: (store (s64)) + ; 64BIT-NEXT: STD killed renamable $x30, 160, $x1 :: (store (s64)) + ; 64BIT-NEXT: STD killed renamable $x28, 152, $x1 :: (store (s64)) + ; 64BIT-NEXT: STD killed renamable $x31, 144, $x1 :: (store (s64)) + ; 64BIT-NEXT: STD killed renamable $x0, 136, $x1 :: (store (s64)) + ; 64BIT-NEXT: STD killed renamable $x12, 128, $x1 :: (store (s64)) + ; 64BIT-NEXT: STD killed renamable $x11, 120, $x1 :: (store (s64)) + ; 64BIT-NEXT: STD killed renamable $x29, 112, $x1 :: (store (s64)) + ; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1, implicit-def dead $x3 + ; 64BIT-NEXT: ADJCALLSTACKUP 176, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm +entry: + %0 = load i64, ptr @ll1, align 8 + %1 = load i16, ptr @si1, align 2 + %2 = load i8, ptr @ch, align 1 + %3 = load i32, ptr @ui, align 4 + %4 = load i32, ptr @sint, align 4 + %5 = load i64, ptr @ll2, align 8 + %6 = load i8, ptr @uc1, align 1 + %7 = load i32, ptr @i1, align 4 + %call = call i64 @test_ints_stack(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i64 %0, i16 signext %1, i8 zeroext %2, i32 %3, i32 %4, i64 %5, i8 zeroext %6, i32 %7) + ret void +} + +@globali1 = global i8 0, align 1 + +define void @test_i1_stack(i32 %a, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, i1 zeroext %b) { + ; 32BIT-LABEL: name: test_i1_stack + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: renamable $r3 = LBZ 0, %fixed-stack.0 :: (load (s8) from %fixed-stack.0) + ; 32BIT-NEXT: renamable $r4 = LWZtoc @globali1, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: STB killed renamable $r3, 0, killed renamable $r4 :: (store (s8) into @globali1) + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm + ; + ; 64BIT-LABEL: name: test_i1_stack + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: renamable $r3 = LBZ 0, %fixed-stack.0 :: (load (s8) from %fixed-stack.0) + ; 64BIT-NEXT: renamable $x4 = LDtoc @globali1, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: STB killed renamable $r3, 0, killed renamable $x4 :: (store (s8) into @globali1) + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm + entry: + %frombool = zext i1 %b to i8 + store i8 %frombool, ptr @globali1, align 1 + ret void +} + +define void @call_test_i1_stack() { + ; 32BIT-LABEL: name: call_test_i1_stack + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: ADJCALLSTACKDOWN 60, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: renamable $r11 = LI 1 + ; 32BIT-NEXT: $r3 = LI 1 + ; 32BIT-NEXT: $r4 = LI 2 + ; 32BIT-NEXT: $r5 = LI 3 + ; 32BIT-NEXT: $r6 = LI 4 + ; 32BIT-NEXT: $r7 = LI 5 + ; 32BIT-NEXT: $r8 = LI 6 + ; 32BIT-NEXT: $r9 = LI 7 + ; 32BIT-NEXT: $r10 = LI 8 + ; 32BIT-NEXT: STW killed renamable $r11, 56, $r1 :: (store (s32)) + ; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1 + ; 32BIT-NEXT: ADJCALLSTACKUP 60, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm + ; + ; 64BIT-LABEL: name: call_test_i1_stack + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: ADJCALLSTACKDOWN 120, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: renamable $x11 = LI8 1 + ; 64BIT-NEXT: $x3 = LI8 1 + ; 64BIT-NEXT: $x4 = LI8 2 + ; 64BIT-NEXT: $x5 = LI8 3 + ; 64BIT-NEXT: $x6 = LI8 4 + ; 64BIT-NEXT: $x7 = LI8 5 + ; 64BIT-NEXT: $x8 = LI8 6 + ; 64BIT-NEXT: $x9 = LI8 7 + ; 64BIT-NEXT: $x10 = LI8 8 + ; 64BIT-NEXT: STD killed renamable $x11, 112, $x1 :: (store (s64)) + ; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1 + ; 64BIT-NEXT: ADJCALLSTACKUP 120, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm + entry: + call void @test_i1_stack(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i1 true) + ret void +} + +define double @test_fpr_stack(double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %s10, double %l11, double %d12, double %d13, float %f14, double %d15, float %f16) { + ; 32BIT-LABEL: name: test_fpr_stack + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: liveins: $f1, $f2, $f3, $f4, $f5, $f6, $f7, $f8, $f9, $f10, $f11, $f12, $f13 + ; 32BIT-NEXT: {{ $}} + ; 32BIT-NEXT: renamable $f0 = LFD 0, %fixed-stack.1 :: (load (s64) from %fixed-stack.1) + ; 32BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f2, implicit $rm + ; 32BIT-NEXT: renamable $f2 = LFS 0, %fixed-stack.2 :: (load (s32) from %fixed-stack.2, align 16) + ; 32BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f3, implicit $rm + ; 32BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f4, implicit $rm + ; 32BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f5, implicit $rm + ; 32BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f6, implicit $rm + ; 32BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f7, implicit $rm + ; 32BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f8, implicit $rm + ; 32BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f9, implicit $rm + ; 32BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f10, implicit $rm + ; 32BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f11, implicit $rm + ; 32BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f12, implicit $rm + ; 32BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, renamable $f13, implicit $rm + ; 32BIT-NEXT: renamable $f3 = LFS 0, %fixed-stack.0 :: (load (s32) from %fixed-stack.0) + ; 32BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f13, implicit $rm + ; 32BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f2, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f1, killed renamable $f0, implicit $rm + ; 32BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f0, killed renamable $f3, implicit $rm + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm, implicit $f1 + ; + ; 64BIT-LABEL: name: test_fpr_stack + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: liveins: $f1, $f2, $f3, $f4, $f5, $f6, $f7, $f8, $f9, $f10, $f11, $f12, $f13 + ; 64BIT-NEXT: {{ $}} + ; 64BIT-NEXT: renamable $f0 = LFD 0, %fixed-stack.1 :: (load (s64) from %fixed-stack.1, align 16) + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f2, implicit $rm + ; 64BIT-NEXT: renamable $f2 = LFS 0, %fixed-stack.2 :: (load (s32) from %fixed-stack.2, align 8) + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f3, implicit $rm + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f4, implicit $rm + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f5, implicit $rm + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f6, implicit $rm + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f7, implicit $rm + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f8, implicit $rm + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f9, implicit $rm + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f10, implicit $rm + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f11, implicit $rm + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f12, implicit $rm + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, renamable $f13, implicit $rm + ; 64BIT-NEXT: renamable $f3 = LFS 0, %fixed-stack.0 :: (load (s32) from %fixed-stack.0, align 8) + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f13, implicit $rm + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f2, implicit $rm + ; 64BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f1, killed renamable $f0, implicit $rm + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f0, killed renamable $f3, implicit $rm + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $f1 + entry: + %add = fadd double %d1, %d2 + %add1 = fadd double %add, %d3 + %add2 = fadd double %add1, %d4 + %add3 = fadd double %add2, %d5 + %add4 = fadd double %add3, %d6 + %add5 = fadd double %add4, %d7 + %add6 = fadd double %add5, %d8 + %add7 = fadd double %add6, %d9 + %add8 = fadd double %add7, %s10 + %add9 = fadd double %add8, %l11 + %add10 = fadd double %add9, %d12 + %add11 = fadd double %add10, %d13 + %add12 = fadd double %add11, %d13 + %conv = fpext float %f14 to double + %add13 = fadd double %add12, %conv + %add14 = fadd double %add13, %d15 + %conv15 = fpext float %f16 to double + %add16 = fadd double %add14, %conv15 + ret double %add16 + } + +@f14 = common global float 0.000000e+00, align 4 +@d15 = common global double 0.000000e+00, align 8 +@f16 = common global float 0.000000e+00, align 4 + +define void @caller_fpr_stack() { + ; 32BIT-LABEL: name: caller_fpr_stack + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: renamable $r3 = LWZtoc @d15, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $r4 = LWZtoc @f14, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f0 = LFD 0, killed renamable $r3 :: (dereferenceable load (s64) from @d15) + ; 32BIT-NEXT: renamable $r5 = LWZtoc @f16, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $r3 = LWZ 0, killed renamable $r4 :: (load (s32) from @f14) + ; 32BIT-NEXT: renamable $r4 = LWZ 0, killed renamable $r5 :: (load (s32) from @f16) + ; 32BIT-NEXT: ADJCALLSTACKDOWN 144, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: renamable $r5 = LI 0 + ; 32BIT-NEXT: renamable $r6 = LIS 16352 + ; 32BIT-NEXT: STW killed renamable $r5, 60, $r1 :: (store (s32) into unknown-address + 4, basealign 8) + ; 32BIT-NEXT: renamable $r5 = LIS 13107 + ; 32BIT-NEXT: STW killed renamable $r6, 56, $r1 :: (store (s32), align 8) + ; 32BIT-NEXT: renamable $r6 = LIS 16355 + ; 32BIT-NEXT: renamable $r5 = ORI killed renamable $r5, 13107 + ; 32BIT-NEXT: STW killed renamable $r5, 68, $r1 :: (store (s32) into unknown-address + 4, basealign 8) + ; 32BIT-NEXT: renamable $r5 = LIS 26214 + ; 32BIT-NEXT: renamable $r6 = ORI killed renamable $r6, 13107 + ; 32BIT-NEXT: STW killed renamable $r6, 64, $r1 :: (store (s32), align 8) + ; 32BIT-NEXT: renamable $r6 = LIS 16358 + ; 32BIT-NEXT: renamable $r5 = ORI killed renamable $r5, 26214 + ; 32BIT-NEXT: STW killed renamable $r5, 76, $r1 :: (store (s32) into unknown-address + 4, basealign 8) + ; 32BIT-NEXT: renamable $r5 = LIS 39321 + ; 32BIT-NEXT: renamable $r6 = ORI killed renamable $r6, 26214 + ; 32BIT-NEXT: STW killed renamable $r6, 72, $r1 :: (store (s32), align 8) + ; 32BIT-NEXT: renamable $r6 = LIS 16361 + ; 32BIT-NEXT: renamable $r6 = ORI killed renamable $r6, 39321 + ; 32BIT-NEXT: STW killed renamable $r6, 80, $r1 :: (store (s32), align 8) + ; 32BIT-NEXT: renamable $r6 = LIS 52428 + ; 32BIT-NEXT: renamable $r6 = ORI killed renamable $r6, 52429 + ; 32BIT-NEXT: STW killed renamable $r6, 92, $r1 :: (store (s32) into unknown-address + 4, basealign 8) + ; 32BIT-NEXT: renamable $r6 = LIS 16364 + ; 32BIT-NEXT: renamable $r5 = ORI killed renamable $r5, 39322 + ; 32BIT-NEXT: STW renamable $r5, 84, $r1 :: (store (s32) into unknown-address + 4, basealign 8) + ; 32BIT-NEXT: renamable $r6 = ORI killed renamable $r6, 52428 + ; 32BIT-NEXT: STW killed renamable $r6, 88, $r1 :: (store (s32), align 8) + ; 32BIT-NEXT: renamable $r6 = LIS 16313 + ; 32BIT-NEXT: STW killed renamable $r5, 100, $r1 :: (store (s32) into unknown-address + 4, basealign 8) + ; 32BIT-NEXT: renamable $r5 = LIS 49807 + ; 32BIT-NEXT: renamable $r6 = ORI killed renamable $r6, 39321 + ; 32BIT-NEXT: STW killed renamable $r6, 96, $r1 :: (store (s32), align 8) + ; 32BIT-NEXT: renamable $r6 = LIS 16316 + ; 32BIT-NEXT: renamable $r5 = ORI killed renamable $r5, 23593 + ; 32BIT-NEXT: STW killed renamable $r5, 108, $r1 :: (store (s32) into unknown-address + 4, basealign 8) + ; 32BIT-NEXT: renamable $r5 = LIS 60293 + ; 32BIT-NEXT: renamable $r6 = ORI killed renamable $r6, 10485 + ; 32BIT-NEXT: STW killed renamable $r6, 104, $r1 :: (store (s32), align 8) + ; 32BIT-NEXT: renamable $r6 = LIS 16318 + ; 32BIT-NEXT: renamable $r5 = ORI killed renamable $r5, 7864 + ; 32BIT-NEXT: STW killed renamable $r5, 116, $r1 :: (store (s32) into unknown-address + 4, basealign 8) + ; 32BIT-NEXT: renamable $r5 = LIS 2621 + ; 32BIT-NEXT: renamable $r6 = ORI killed renamable $r6, 47185 + ; 32BIT-NEXT: STW killed renamable $r6, 112, $r1 :: (store (s32), align 8) + ; 32BIT-NEXT: renamable $r6 = LIS 16320 + ; 32BIT-NEXT: renamable $r5 = ORI killed renamable $r5, 28836 + ; 32BIT-NEXT: STW killed renamable $r5, 124, $r1 :: (store (s32) into unknown-address + 4, basealign 8) + ; 32BIT-NEXT: renamable $r5 = LWZtoc %const.0, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $r6 = ORI killed renamable $r6, 41943 + ; 32BIT-NEXT: STW killed renamable $r6, 120, $r1 :: (store (s32), align 8) + ; 32BIT-NEXT: renamable $r6 = LWZtoc %const.1, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f2 = LFD 0, killed renamable $r5 :: (load (s64) from constant-pool) + ; 32BIT-NEXT: renamable $r5 = LWZtoc %const.2, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f3 = LFD 0, killed renamable $r6 :: (load (s64) from constant-pool) + ; 32BIT-NEXT: renamable $r6 = LWZtoc %const.3, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f4 = LFD 0, killed renamable $r5 :: (load (s64) from constant-pool) + ; 32BIT-NEXT: renamable $r5 = LWZtoc %const.4, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f6 = LFD 0, killed renamable $r6 :: (load (s64) from constant-pool) + ; 32BIT-NEXT: renamable $r6 = LWZtoc %const.5, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f7 = LFD 0, killed renamable $r5 :: (load (s64) from constant-pool) + ; 32BIT-NEXT: renamable $r5 = LWZtoc %const.6, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f8 = LFD 0, killed renamable $r6 :: (load (s64) from constant-pool) + ; 32BIT-NEXT: renamable $r6 = LWZtoc %const.7, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f9 = LFD 0, killed renamable $r5 :: (load (s64) from constant-pool) + ; 32BIT-NEXT: renamable $r5 = LWZtoc %const.8, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f1 = LFD 0, killed renamable $r6 :: (load (s64) from constant-pool) + ; 32BIT-NEXT: renamable $r6 = LWZtoc %const.9, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f11 = LFD 0, killed renamable $r5 :: (load (s64) from constant-pool) + ; 32BIT-NEXT: renamable $r5 = LWZtoc %const.10, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f12 = LFD 0, killed renamable $r6 :: (load (s64) from constant-pool) + ; 32BIT-NEXT: renamable $r6 = LWZtoc %const.11, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f13 = LFD 0, killed renamable $r5 :: (load (s64) from constant-pool) + ; 32BIT-NEXT: renamable $f5 = LFS 0, killed renamable $r6 :: (load (s32) from constant-pool) + ; 32BIT-NEXT: STW killed renamable $r4, 140, $r1 :: (store (s32)) + ; 32BIT-NEXT: STFD killed renamable $f0, 132, $r1 :: (store (s64)) + ; 32BIT-NEXT: $f10 = COPY renamable $f1 + ; 32BIT-NEXT: STW killed renamable $r3, 128, $r1 :: (store (s32)) + ; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit killed $f10, implicit $f11, implicit $f12, implicit $f13, implicit $r2, implicit-def $r1, implicit-def dead $f1 + ; 32BIT-NEXT: ADJCALLSTACKUP 144, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm + ; + ; 64BIT-LABEL: name: caller_fpr_stack + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: renamable $x3 = LDtoc @f14, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $x4 = LDtoc @d15, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $x5 = LDtoc @f16, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $r3 = LWZ 0, killed renamable $x3 :: (load (s32) from @f14) + ; 64BIT-NEXT: renamable $x4 = LD 0, killed renamable $x4 :: (load (s64) from @d15) + ; 64BIT-NEXT: renamable $r5 = LWZ 0, killed renamable $x5 :: (load (s32) from @f16) + ; 64BIT-NEXT: ADJCALLSTACKDOWN 176, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: renamable $x6 = LDtocCPT %const.0, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: STW killed renamable $r5, 168, $x1 :: (store (s32)) + ; 64BIT-NEXT: renamable $x5 = LDtocCPT %const.1, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $x7 = LDtocCPT %const.2, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x6 :: (load (s64) from constant-pool) + ; 64BIT-NEXT: renamable $x6 = LDtocCPT %const.3, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $f3 = LFD 0, killed renamable $x5 :: (load (s64) from constant-pool) + ; 64BIT-NEXT: renamable $x5 = LDtocCPT %const.4, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $f4 = LFD 0, killed renamable $x7 :: (load (s64) from constant-pool) + ; 64BIT-NEXT: renamable $x7 = LDtocCPT %const.5, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $f6 = LFD 0, killed renamable $x6 :: (load (s64) from constant-pool) + ; 64BIT-NEXT: renamable $x6 = LDtocCPT %const.6, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $f7 = LFD 0, killed renamable $x5 :: (load (s64) from constant-pool) + ; 64BIT-NEXT: STD killed renamable $x4, 160, $x1 :: (store (s64)) + ; 64BIT-NEXT: renamable $x4 = LDtocCPT %const.7, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $f8 = LFD 0, killed renamable $x7 :: (load (s64) from constant-pool) + ; 64BIT-NEXT: renamable $x5 = LIS8 16320 + ; 64BIT-NEXT: renamable $x7 = LDtocCPT %const.8, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $f9 = LFD 0, killed renamable $x6 :: (load (s64) from constant-pool) + ; 64BIT-NEXT: renamable $x6 = LIS8 16318 + ; 64BIT-NEXT: renamable $x8 = LDtocCPT %const.9, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $f1 = LFD 0, killed renamable $x4 :: (load (s64) from constant-pool) + ; 64BIT-NEXT: renamable $x4 = LIS8 16316 + ; 64BIT-NEXT: renamable $f11 = LFD 0, killed renamable $x7 :: (load (s64) from constant-pool) + ; 64BIT-NEXT: renamable $x7 = LIS8 16313 + ; 64BIT-NEXT: renamable $f12 = LFD 0, killed renamable $x8 :: (load (s64) from constant-pool) + ; 64BIT-NEXT: renamable $x8 = LDtocCPT %const.10, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $x5 = ORI8 killed renamable $x5, 41943 + ; 64BIT-NEXT: renamable $x6 = ORI8 killed renamable $x6, 47185 + ; 64BIT-NEXT: renamable $x4 = ORI8 killed renamable $x4, 10485 + ; 64BIT-NEXT: renamable $x7 = ORI8 killed renamable $x7, 39321 + ; 64BIT-NEXT: renamable $f13 = LFD 0, killed renamable $x8 :: (load (s64) from constant-pool) + ; 64BIT-NEXT: renamable $x8 = LDtocCPT %const.11, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $x5 = RLDIC killed renamable $x5, 32, 2 + ; 64BIT-NEXT: renamable $x6 = RLDIC killed renamable $x6, 32, 2 + ; 64BIT-NEXT: renamable $x4 = RLDIC killed renamable $x4, 32, 2 + ; 64BIT-NEXT: renamable $x7 = RLDIC killed renamable $x7, 32, 2 + ; 64BIT-NEXT: renamable $x5 = ORIS8 killed renamable $x5, 2621 + ; 64BIT-NEXT: renamable $x6 = ORIS8 killed renamable $x6, 60293 + ; 64BIT-NEXT: renamable $x4 = ORIS8 killed renamable $x4, 49807 + ; 64BIT-NEXT: renamable $x7 = ORIS8 killed renamable $x7, 39321 + ; 64BIT-NEXT: renamable $x5 = ORI8 killed renamable $x5, 28836 + ; 64BIT-NEXT: renamable $x6 = ORI8 killed renamable $x6, 7864 + ; 64BIT-NEXT: renamable $x4 = ORI8 killed renamable $x4, 23593 + ; 64BIT-NEXT: renamable $f5 = LFS 0, killed renamable $x8 :: (load (s32) from constant-pool) + ; 64BIT-NEXT: renamable $x8 = LIS8 4091 + ; 64BIT-NEXT: renamable $x8 = ORI8 killed renamable $x8, 13107 + ; 64BIT-NEXT: renamable $x7 = ORI8 killed renamable $x7, 39322 + ; 64BIT-NEXT: renamable $x8 = RLDIC killed renamable $x8, 34, 2 + ; 64BIT-NEXT: renamable $x8 = ORIS8 killed renamable $x8, 52428 + ; 64BIT-NEXT: renamable $x8 = ORI8 killed renamable $x8, 52429 + ; 64BIT-NEXT: $f10 = COPY renamable $f1 + ; 64BIT-NEXT: STW killed renamable $r3, 152, $x1 :: (store (s32)) + ; 64BIT-NEXT: STD killed renamable $x5, 144, $x1 :: (store (s64)) + ; 64BIT-NEXT: STD killed renamable $x6, 136, $x1 :: (store (s64)) + ; 64BIT-NEXT: STD killed renamable $x4, 128, $x1 :: (store (s64)) + ; 64BIT-NEXT: STD killed renamable $x7, 120, $x1 :: (store (s64)) + ; 64BIT-NEXT: STD killed renamable $x8, 112, $x1 :: (store (s64)) + ; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit killed $f10, implicit $f11, implicit $f12, implicit $f13, implicit $x2, implicit-def $r1, implicit-def dead $f1 + ; 64BIT-NEXT: ADJCALLSTACKUP 176, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm +entry: + %0 = load float, ptr @f14, align 4 + %1 = load double, ptr @d15, align 8 + %2 = load float, ptr @f16, align 4 + %call = call double @test_fpr_stack(double 1.000000e-01, double 2.000000e-01, double 3.000000e-01, double 4.000000e-01, double 5.000000e-01, double 6.000000e-01, double 0x3FE6666666666666, double 8.000000e-01, double 9.000000e-01, double 1.000000e-01, double 1.100000e-01, double 1.200000e-01, double 1.300000e-01, float %0, double %1, float %2) + ret void +} + +define i32 @mix_callee(double %d1, double %d2, double %d3, double %d4, i8 zeroext %c1, i16 signext %s1, i64 %ll1, i32 %i1, i32 %i2, i32 %i3) { + ; 32BIT-LABEL: name: mix_callee + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: liveins: $f1, $f2, $f3, $f4 + ; 32BIT-NEXT: {{ $}} + ; 32BIT-NEXT: renamable $r3 = LWZ 0, %fixed-stack.3 :: (load (s32) from %fixed-stack.3) + ; 32BIT-NEXT: renamable $r4 = LWZ 0, %fixed-stack.5 :: (load (s32) from %fixed-stack.5) + ; 32BIT-NEXT: renamable $r5 = LWZ 0, %fixed-stack.6 :: (load (s32) from %fixed-stack.6, align 8) + ; 32BIT-NEXT: renamable $r6 = LWZ 0, %fixed-stack.2 :: (load (s32) from %fixed-stack.2, align 8) + ; 32BIT-NEXT: renamable $r7 = LIS 17200 + ; 32BIT-NEXT: STW killed renamable $r7, 0, %stack.1 :: (store (s32) into %stack.1, align 8) + ; 32BIT-NEXT: renamable $r7 = LWZ 0, %fixed-stack.1 :: (load (s32) from %fixed-stack.1) + ; 32BIT-NEXT: renamable $r4 = nsw ADD4 killed renamable $r5, killed renamable $r4 + ; 32BIT-NEXT: renamable $r5 = LWZtoc %const.0, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $r3 = ADD4 killed renamable $r4, killed renamable $r3 + ; 32BIT-NEXT: renamable $r4 = LWZ 0, %fixed-stack.0 :: (load (s32) from %fixed-stack.0, align 16) + ; 32BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, killed renamable $r6 + ; 32BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, killed renamable $r7 + ; 32BIT-NEXT: renamable $f0 = LFS 0, killed renamable $r5 :: (load (s32) from constant-pool) + ; 32BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, killed renamable $r4 + ; 32BIT-NEXT: renamable $r3 = XORIS killed renamable $r3, 32768 + ; 32BIT-NEXT: STW killed renamable $r3, 4, %stack.1 :: (store (s32) into %stack.1 + 4) + ; 32BIT-NEXT: renamable $f5 = LFD 0, %stack.1 :: (load (s64) from %stack.1) + ; 32BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f2, implicit $rm + ; 32BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f3, implicit $rm + ; 32BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f4, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FSUB killed renamable $f5, killed renamable $f0, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FCTIWZ killed renamable $f0, implicit $rm + ; 32BIT-NEXT: STFD killed renamable $f0, 0, %stack.0 :: (store (s64) into %stack.0) + ; 32BIT-NEXT: renamable $r3 = LWZ 4, %stack.0 :: (load (s32) from %stack.0 + 4, basealign 8) + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm, implicit $r3 + ; + ; 64BIT-LABEL: name: mix_callee + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: liveins: $f1, $f2, $f3, $f4, $x7, $x8, $x9, $x10 + ; 64BIT-NEXT: {{ $}} + ; 64BIT-NEXT: renamable $x3 = LWZ8 0, %fixed-stack.1 :: (load (s32) from %fixed-stack.1) + ; 64BIT-NEXT: renamable $r4 = nsw ADD4 renamable $r7, renamable $r8, implicit killed $x8, implicit killed $x7, implicit-def $x4 + ; 64BIT-NEXT: renamable $x5 = LWZ8 0, %fixed-stack.0 :: (load (s32) from %fixed-stack.0) + ; 64BIT-NEXT: renamable $x4 = ADD8 killed renamable $x4, killed renamable $x9 + ; 64BIT-NEXT: renamable $x4 = ADD8 killed renamable $x4, killed renamable $x10 + ; 64BIT-NEXT: renamable $x3 = ADD8 killed renamable $x4, killed renamable $x3 + ; 64BIT-NEXT: renamable $x3 = ADD8 killed renamable $x3, killed renamable $x5 + ; 64BIT-NEXT: renamable $x3 = EXTSW killed renamable $x3 + ; 64BIT-NEXT: STD killed renamable $x3, 0, %stack.1 :: (store (s64) into %stack.1) + ; 64BIT-NEXT: renamable $f0 = LFD 0, %stack.1 :: (load (s64) from %stack.1) + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f2, implicit $rm + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f3, implicit $rm + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f4, implicit $rm + ; 64BIT-NEXT: renamable $f0 = nofpexcept FCFID killed renamable $f0, implicit $rm + ; 64BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implicit $rm + ; 64BIT-NEXT: renamable $f0 = nofpexcept FCTIWZ killed renamable $f0, implicit $rm + ; 64BIT-NEXT: STFD killed renamable $f0, 0, %stack.0 :: (store (s64) into %stack.0) + ; 64BIT-NEXT: renamable $x3 = LWZ8 4, %stack.0 :: (load (s32) from %stack.0 + 4, basealign 8) + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3 + entry: + %add = fadd double %d1, %d2 + %add1 = fadd double %add, %d3 + %add2 = fadd double %add1, %d4 + %conv = zext i8 %c1 to i32 + %conv3 = sext i16 %s1 to i32 + %add4 = add nsw i32 %conv, %conv3 + %conv5 = sext i32 %add4 to i64 + %add6 = add nsw i64 %conv5, %ll1 + %conv7 = sext i32 %i1 to i64 + %add8 = add nsw i64 %add6, %conv7 + %conv9 = sext i32 %i2 to i64 + %add10 = add nsw i64 %add8, %conv9 + %conv11 = sext i32 %i3 to i64 + %add12 = add nsw i64 %add10, %conv11 + %conv13 = trunc i64 %add12 to i32 + %conv14 = sitofp i32 %conv13 to double + %add15 = fadd double %conv14, %add2 + %conv16 = fptosi double %add15 to i32 + ret i32 %conv16 + } + +define void @caller_mix() { + ; 32BIT-LABEL: name: caller_mix + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: ADJCALLSTACKDOWN 84, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: renamable $r3 = LI 60 + ; 32BIT-NEXT: STW killed renamable $r3, 80, $r1 :: (store (s32)) + ; 32BIT-NEXT: renamable $r3 = LI 50 + ; 32BIT-NEXT: STW killed renamable $r3, 76, $r1 :: (store (s32)) + ; 32BIT-NEXT: renamable $r3 = LI 40 + ; 32BIT-NEXT: STW killed renamable $r3, 72, $r1 :: (store (s32)) + ; 32BIT-NEXT: renamable $r3 = LI 0 + ; 32BIT-NEXT: renamable $r4 = LWZtoc %const.0, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: STW killed renamable $r3, 64, $r1 :: (store (s32)) + ; 32BIT-NEXT: renamable $r3 = LI 2 + ; 32BIT-NEXT: STW killed renamable $r3, 60, $r1 :: (store (s32)) + ; 32BIT-NEXT: renamable $r3 = LWZtoc %const.1, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f1 = LFD 0, killed renamable $r4 :: (load (s64) from constant-pool) + ; 32BIT-NEXT: renamable $r4 = LWZtoc %const.2, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f2 = LFD 0, killed renamable $r3 :: (load (s64) from constant-pool) + ; 32BIT-NEXT: renamable $r3 = LWZtoc %const.3, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f3 = LFD 0, killed renamable $r4 :: (load (s64) from constant-pool) + ; 32BIT-NEXT: renamable $f4 = LFD 0, killed renamable $r3 :: (load (s64) from constant-pool) + ; 32BIT-NEXT: renamable $r3 = LI 1 + ; 32BIT-NEXT: STW killed renamable $r3, 56, $r1 :: (store (s32)) + ; 32BIT-NEXT: renamable $r3 = LIS 457 + ; 32BIT-NEXT: renamable $r3 = ORI killed renamable $r3, 50048 + ; 32BIT-NEXT: STW killed renamable $r3, 68, $r1 :: (store (s32)) + ; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $r2, implicit-def $r1, implicit-def dead $r3 + ; 32BIT-NEXT: ADJCALLSTACKUP 84, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm + ; + ; 64BIT-LABEL: name: caller_mix + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: ADJCALLSTACKDOWN 128, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: renamable $x3 = LDtocCPT %const.0, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $x4 = LDtocCPT %const.1, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $x5 = LDtocCPT %const.2, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $f1 = LFD 0, killed renamable $x3 :: (load (s64) from constant-pool) + ; 64BIT-NEXT: renamable $x3 = LDtocCPT %const.3, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x4 :: (load (s64) from constant-pool) + ; 64BIT-NEXT: renamable $x4 = LI8 60 + ; 64BIT-NEXT: renamable $f3 = LFD 0, killed renamable $x5 :: (load (s64) from constant-pool) + ; 64BIT-NEXT: renamable $x5 = LI8 50 + ; 64BIT-NEXT: renamable $f4 = LFD 0, killed renamable $x3 :: (load (s64) from constant-pool) + ; 64BIT-NEXT: renamable $x3 = LIS8 457 + ; 64BIT-NEXT: renamable $x9 = ORI8 killed renamable $x3, 50048 + ; 64BIT-NEXT: $x7 = LI8 1 + ; 64BIT-NEXT: $x8 = LI8 2 + ; 64BIT-NEXT: $x10 = LI8 40 + ; 64BIT-NEXT: STD killed renamable $x4, 120, $x1 :: (store (s64)) + ; 64BIT-NEXT: STD killed renamable $x5, 112, $x1 :: (store (s64)) + ; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit killed $x7, implicit killed $x8, implicit $x9, implicit killed $x10, implicit $x2, implicit-def $r1, implicit-def dead $x3 + ; 64BIT-NEXT: ADJCALLSTACKUP 128, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm + entry: +%call = call i32 @mix_callee(double 1.000000e-01, double 2.000000e-01, double 3.000000e-01, double 4.000000e-01, i8 zeroext 1, i16 signext 2, i64 30000000, i32 40, i32 50, i32 60) + ret void + } + + define i32 @mix_floats(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10, double %d11, double %d12, double %d13, double %d14) { + ; 32BIT-LABEL: name: mix_floats + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: liveins: $f1, $f2, $f3, $f4, $f5, $f6, $f7, $f8, $f9, $f10, $f11, $f12, $f13, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10 + ; 32BIT-NEXT: {{ $}} + ; 32BIT-NEXT: renamable $r11 = LIS 17200 + ; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r4 + ; 32BIT-NEXT: STW killed renamable $r11, 0, %stack.1 :: (store (s32) into %stack.1, align 8) + ; 32BIT-NEXT: renamable $r4 = LWZtoc %const.0, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r5 + ; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r6 + ; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r7 + ; 32BIT-NEXT: renamable $f0 = LFS 0, killed renamable $r4 :: (load (s32) from constant-pool) + ; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r8 + ; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r9 + ; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r10 + ; 32BIT-NEXT: renamable $r3 = XORIS killed renamable $r3, 32768 + ; 32BIT-NEXT: STW killed renamable $r3, 4, %stack.1 :: (store (s32) into %stack.1 + 4) + ; 32BIT-NEXT: renamable $f31 = LFD 0, %stack.1 :: (load (s64) from %stack.1) + ; 32BIT-NEXT: renamable $f30 = LFD 0, %fixed-stack.0 :: (load (s64) from %fixed-stack.0, align 16) + ; 32BIT-NEXT: renamable $f0 = nofpexcept FSUB killed renamable $f31, killed renamable $f0, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f2, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f3, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f4, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f5, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f6, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f7, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f8, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f9, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f10, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f11, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f12, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f13, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f30, implicit $rm + ; 32BIT-NEXT: renamable $f0 = nofpexcept FCTIWZ killed renamable $f0, implicit $rm + ; 32BIT-NEXT: STFD killed renamable $f0, 0, %stack.0 :: (store (s64) into %stack.0) + ; 32BIT-NEXT: renamable $r3 = LWZ 4, %stack.0 :: (load (s32) from %stack.0 + 4, basealign 8) + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm, implicit $r3 + ; + ; 64BIT-LABEL: name: mix_floats + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: liveins: $f1, $f2, $f3, $f4, $f5, $f6, $f7, $f8, $f9, $f10, $f11, $f12, $f13, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10 + ; 64BIT-NEXT: {{ $}} + ; 64BIT-NEXT: renamable $f0 = LFD 0, %fixed-stack.0 :: (load (s64) from %fixed-stack.0) + ; 64BIT-NEXT: renamable $r3 = nsw ADD4 renamable $r3, renamable $r4, implicit killed $x4, implicit killed $x3 + ; 64BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r5, implicit killed $x5 + ; 64BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r6, implicit killed $x6 + ; 64BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r7, implicit killed $x7 + ; 64BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r8, implicit killed $x8 + ; 64BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r9, implicit killed $x9 + ; 64BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r10, implicit killed $x10 + ; 64BIT-NEXT: renamable $x3 = EXTSW_32_64 killed renamable $r3 + ; 64BIT-NEXT: STD killed renamable $x3, 0, %stack.1 :: (store (s64) into %stack.1) + ; 64BIT-NEXT: renamable $f31 = LFD 0, %stack.1 :: (load (s64) from %stack.1) + ; 64BIT-NEXT: renamable $f31 = nofpexcept FCFID killed renamable $f31, implicit $rm + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f31, killed renamable $f1, implicit $rm + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f2, implicit $rm + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f3, implicit $rm + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f4, implicit $rm + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f5, implicit $rm + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f6, implicit $rm + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f7, implicit $rm + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f8, implicit $rm + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f9, implicit $rm + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f10, implicit $rm + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f11, implicit $rm + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f12, implicit $rm + ; 64BIT-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f13, implicit $rm + ; 64BIT-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f1, killed renamable $f0, implicit $rm + ; 64BIT-NEXT: renamable $f0 = nofpexcept FCTIWZ killed renamable $f0, implicit $rm + ; 64BIT-NEXT: STFD killed renamable $f0, 0, %stack.0 :: (store (s64) into %stack.0) + ; 64BIT-NEXT: renamable $x3 = LWZ8 4, %stack.0 :: (load (s32) from %stack.0 + 4, basealign 8) + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3 + entry: + %add = add nsw i32 %i1, %i2 + %add1 = add nsw i32 %add, %i3 + %add2 = add nsw i32 %add1, %i4 + %add3 = add nsw i32 %add2, %i5 + %add4 = add nsw i32 %add3, %i6 + %add5 = add nsw i32 %add4, %i7 + %add6 = add nsw i32 %add5, %i8 + %conv = sitofp i32 %add6 to double + %add7 = fadd double %conv, %d1 + %add8 = fadd double %add7, %d2 + %add9 = fadd double %add8, %d3 + %add10 = fadd double %add9, %d4 + %add11 = fadd double %add10, %d5 + %add12 = fadd double %add11, %d6 + %add13 = fadd double %add12, %d7 + %add14 = fadd double %add13, %d8 + %add15 = fadd double %add14, %d9 + %add16 = fadd double %add15, %d10 + %add17 = fadd double %add16, %d11 + %add18 = fadd double %add17, %d12 + %add19 = fadd double %add18, %d13 + %add20 = fadd double %add19, %d14 + %conv21 = fptosi double %add20 to i32 + ret i32 %conv21 + } + + define void @mix_floats_caller() { + ; 32BIT-LABEL: name: mix_floats_caller + ; 32BIT: bb.0.entry: + ; 32BIT-NEXT: ADJCALLSTACKDOWN 168, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: renamable $r3 = LI 0 + ; 32BIT-NEXT: renamable $r4 = LIS 16352 + ; 32BIT-NEXT: renamable $r5 = LIS 16368 + ; 32BIT-NEXT: renamable $r6 = LIS 39321 + ; 32BIT-NEXT: renamable $r7 = LIS 16313 + ; 32BIT-NEXT: renamable $r8 = LIS 16329 + ; 32BIT-NEXT: renamable $r9 = LIS 13107 + ; 32BIT-NEXT: renamable $r10 = LIS 16339 + ; 32BIT-NEXT: STW renamable $r3, 92, $r1 :: (store (s32) into unknown-address + 4, basealign 8) + ; 32BIT-NEXT: renamable $r11 = LIS 16345 + ; 32BIT-NEXT: STW killed renamable $r4, 88, $r1 :: (store (s32), align 8) + ; 32BIT-NEXT: renamable $r4 = LIS 16355 + ; 32BIT-NEXT: STW killed renamable $r3, 132, $r1 :: (store (s32) into unknown-address + 4, basealign 8) + ; 32BIT-NEXT: renamable $r3 = LIS 26214 + ; 32BIT-NEXT: STW killed renamable $r5, 128, $r1 :: (store (s32), align 8) + ; 32BIT-NEXT: renamable $r5 = ORI killed renamable $r6, 39322 + ; 32BIT-NEXT: STW renamable $r5, 60, $r1 :: (store (s32) into unknown-address + 4, basealign 8) + ; 32BIT-NEXT: renamable $r6 = ORI killed renamable $r7, 39321 + ; 32BIT-NEXT: STW killed renamable $r6, 56, $r1 :: (store (s32), align 8) + ; 32BIT-NEXT: renamable $r6 = LIS 16358 + ; 32BIT-NEXT: STW renamable $r5, 68, $r1 :: (store (s32) into unknown-address + 4, basealign 8) + ; 32BIT-NEXT: renamable $r7 = ORI killed renamable $r8, 39321 + ; 32BIT-NEXT: STW killed renamable $r7, 64, $r1 :: (store (s32), align 8) + ; 32BIT-NEXT: renamable $r7 = ORI killed renamable $r9, 13107 + ; 32BIT-NEXT: STW renamable $r7, 76, $r1 :: (store (s32) into unknown-address + 4, basealign 8) + ; 32BIT-NEXT: renamable $r8 = ORI killed renamable $r10, 13107 + ; 32BIT-NEXT: STW killed renamable $r8, 72, $r1 :: (store (s32), align 8) + ; 32BIT-NEXT: renamable $r8 = LIS 16361 + ; 32BIT-NEXT: STW renamable $r5, 84, $r1 :: (store (s32) into unknown-address + 4, basealign 8) + ; 32BIT-NEXT: renamable $r9 = ORI killed renamable $r11, 39321 + ; 32BIT-NEXT: STW killed renamable $r9, 80, $r1 :: (store (s32), align 8) + ; 32BIT-NEXT: renamable $r9 = LIS 52428 + ; 32BIT-NEXT: STW renamable $r7, 100, $r1 :: (store (s32) into unknown-address + 4, basealign 8) + ; 32BIT-NEXT: renamable $r4 = ORI killed renamable $r4, 13107 + ; 32BIT-NEXT: STW killed renamable $r4, 96, $r1 :: (store (s32), align 8) + ; 32BIT-NEXT: renamable $r3 = ORI killed renamable $r3, 26214 + ; 32BIT-NEXT: STW renamable $r3, 108, $r1 :: (store (s32) into unknown-address + 4, basealign 8) + ; 32BIT-NEXT: renamable $r4 = ORI killed renamable $r6, 26214 + ; 32BIT-NEXT: STW killed renamable $r4, 104, $r1 :: (store (s32), align 8) + ; 32BIT-NEXT: renamable $r4 = LIS 16364 + ; 32BIT-NEXT: STW renamable $r5, 116, $r1 :: (store (s32) into unknown-address + 4, basealign 8) + ; 32BIT-NEXT: renamable $r6 = ORI killed renamable $r8, 39321 + ; 32BIT-NEXT: STW killed renamable $r6, 112, $r1 :: (store (s32), align 8) + ; 32BIT-NEXT: renamable $r6 = ORI killed renamable $r9, 52429 + ; 32BIT-NEXT: STW renamable $r6, 124, $r1 :: (store (s32) into unknown-address + 4, basealign 8) + ; 32BIT-NEXT: renamable $r4 = ORI killed renamable $r4, 52428 + ; 32BIT-NEXT: STW killed renamable $r4, 120, $r1 :: (store (s32), align 8) + ; 32BIT-NEXT: renamable $r4 = LIS 16369 + ; 32BIT-NEXT: STW killed renamable $r5, 140, $r1 :: (store (s32) into unknown-address + 4, basealign 8) + ; 32BIT-NEXT: renamable $r4 = ORI killed renamable $r4, 39321 + ; 32BIT-NEXT: STW killed renamable $r4, 136, $r1 :: (store (s32), align 8) + ; 32BIT-NEXT: renamable $r4 = LIS 16371 + ; 32BIT-NEXT: STW killed renamable $r7, 148, $r1 :: (store (s32) into unknown-address + 4, basealign 8) + ; 32BIT-NEXT: renamable $r4 = ORI killed renamable $r4, 13107 + ; 32BIT-NEXT: STW killed renamable $r4, 144, $r1 :: (store (s32), align 8) + ; 32BIT-NEXT: renamable $r4 = LIS 16372 + ; 32BIT-NEXT: renamable $r5 = LWZtoc %const.0, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: STW killed renamable $r6, 156, $r1 :: (store (s32) into unknown-address + 4, basealign 8) + ; 32BIT-NEXT: renamable $r4 = ORI killed renamable $r4, 52428 + ; 32BIT-NEXT: STW killed renamable $r4, 152, $r1 :: (store (s32), align 8) + ; 32BIT-NEXT: renamable $r4 = LWZtoc %const.1, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: STW killed renamable $r3, 164, $r1 :: (store (s32) into unknown-address + 4, basealign 8) + ; 32BIT-NEXT: renamable $r3 = LWZtoc %const.2, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f1 = LFD 0, killed renamable $r5 :: (load (s64) from constant-pool) + ; 32BIT-NEXT: renamable $r5 = LWZtoc %const.3, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f2 = LFD 0, killed renamable $r4 :: (load (s64) from constant-pool) + ; 32BIT-NEXT: renamable $r4 = LWZtoc %const.4, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f3 = LFD 0, killed renamable $r3 :: (load (s64) from constant-pool) + ; 32BIT-NEXT: renamable $r3 = LWZtoc %const.5, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f4 = LFD 0, killed renamable $r5 :: (load (s64) from constant-pool) + ; 32BIT-NEXT: renamable $r5 = LWZtoc %const.6, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f6 = LFD 0, killed renamable $r4 :: (load (s64) from constant-pool) + ; 32BIT-NEXT: renamable $r4 = LWZtoc %const.7, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f7 = LFD 0, killed renamable $r3 :: (load (s64) from constant-pool) + ; 32BIT-NEXT: renamable $r3 = LWZtoc %const.8, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f8 = LFD 0, killed renamable $r5 :: (load (s64) from constant-pool) + ; 32BIT-NEXT: renamable $r5 = LWZtoc %const.9, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f9 = LFD 0, killed renamable $r4 :: (load (s64) from constant-pool) + ; 32BIT-NEXT: renamable $r4 = LWZtoc %const.10, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f11 = LFD 0, killed renamable $r3 :: (load (s64) from constant-pool) + ; 32BIT-NEXT: renamable $r3 = LWZtoc %const.11, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f12 = LFD 0, killed renamable $r5 :: (load (s64) from constant-pool) + ; 32BIT-NEXT: renamable $r5 = LWZtoc %const.12, $r2 :: (load (s32) from got) + ; 32BIT-NEXT: renamable $f13 = LFD 0, killed renamable $r4 :: (load (s64) from constant-pool) + ; 32BIT-NEXT: renamable $r4 = LIS 16374 + ; 32BIT-NEXT: renamable $f5 = LFS 0, killed renamable $r3 :: (load (s32) from constant-pool) + ; 32BIT-NEXT: renamable $r11 = ORI killed renamable $r4, 26214 + ; 32BIT-NEXT: renamable $f10 = LFS 0, killed renamable $r5 :: (load (s32) from constant-pool) + ; 32BIT-NEXT: $r3 = LI 1 + ; 32BIT-NEXT: $r4 = LI 2 + ; 32BIT-NEXT: $r5 = LI 3 + ; 32BIT-NEXT: $r6 = LI 4 + ; 32BIT-NEXT: $r7 = LI 5 + ; 32BIT-NEXT: $r8 = LI 6 + ; 32BIT-NEXT: $r9 = LI 7 + ; 32BIT-NEXT: $r10 = LI 8 + ; 32BIT-NEXT: STW killed renamable $r11, 160, $r1 :: (store (s32), align 8) + ; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit $f10, implicit $f11, implicit $f12, implicit $f13, implicit $r2, implicit-def $r1, implicit-def dead $r3 + ; 32BIT-NEXT: ADJCALLSTACKUP 168, 0, implicit-def dead $r1, implicit $r1 + ; 32BIT-NEXT: BLR implicit $lr, implicit $rm + ; + ; 64BIT-LABEL: name: mix_floats_caller + ; 64BIT: bb.0.entry: + ; 64BIT-NEXT: ADJCALLSTACKDOWN 224, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: renamable $x3 = LI8 1023 + ; 64BIT-NEXT: renamable $x4 = LI8 511 + ; 64BIT-NEXT: renamable $x5 = LIS8 16374 + ; 64BIT-NEXT: renamable $x6 = LIS8 16371 + ; 64BIT-NEXT: renamable $x7 = LIS8 16358 + ; 64BIT-NEXT: renamable $x8 = LIS8 16355 + ; 64BIT-NEXT: renamable $x9 = LIS8 16339 + ; 64BIT-NEXT: renamable $x10 = LIS8 4093 + ; 64BIT-NEXT: renamable $x11 = LDtocCPT %const.0, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $x29 = LIS8 16369 + ; 64BIT-NEXT: renamable $x28 = LIS8 4091 + ; 64BIT-NEXT: renamable $x12 = LDtocCPT %const.1, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $x27 = LIS8 16361 + ; 64BIT-NEXT: renamable $x31 = LDtocCPT %const.2, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $f1 = LFD 0, killed renamable $x11 :: (load (s64) from constant-pool) + ; 64BIT-NEXT: renamable $x26 = LIS8 16345 + ; 64BIT-NEXT: renamable $x11 = LDtocCPT %const.3, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x12 :: (load (s64) from constant-pool) + ; 64BIT-NEXT: renamable $x25 = LIS8 16329 + ; 64BIT-NEXT: renamable $f3 = LFD 0, killed renamable $x31 :: (load (s64) from constant-pool) + ; 64BIT-NEXT: renamable $x24 = LIS8 16313 + ; 64BIT-NEXT: renamable $x23 = LDtocCPT %const.4, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $x22 = LDtocCPT %const.5, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $x21 = LDtocCPT %const.6, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $x20 = LDtocCPT %const.7, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $x19 = LDtocCPT %const.8, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $x18 = LDtocCPT %const.9, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $x17 = LDtocCPT %const.10, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $f4 = LFD 0, killed renamable $x11 :: (load (s64) from constant-pool) + ; 64BIT-NEXT: renamable $x16 = LDtocCPT %const.11, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $x11 = ORI8 killed renamable $x5, 26214 + ; 64BIT-NEXT: renamable $x12 = ORI8 killed renamable $x6, 13107 + ; 64BIT-NEXT: renamable $x0 = ORI8 killed renamable $x7, 26214 + ; 64BIT-NEXT: renamable $x31 = ORI8 killed renamable $x8, 13107 + ; 64BIT-NEXT: renamable $x30 = ORI8 killed renamable $x9, 13107 + ; 64BIT-NEXT: renamable $x5 = ORI8 killed renamable $x10, 13107 + ; 64BIT-NEXT: renamable $x6 = ORI8 killed renamable $x29, 39321 + ; 64BIT-NEXT: renamable $x7 = ORI8 killed renamable $x28, 13107 + ; 64BIT-NEXT: renamable $x8 = ORI8 killed renamable $x27, 39321 + ; 64BIT-NEXT: renamable $x9 = ORI8 killed renamable $x26, 39321 + ; 64BIT-NEXT: renamable $x10 = ORI8 killed renamable $x25, 39321 + ; 64BIT-NEXT: renamable $x27 = ORI8 killed renamable $x24, 39321 + ; 64BIT-NEXT: renamable $f6 = LFD 0, killed renamable $x23 :: (load (s64) from constant-pool) + ; 64BIT-NEXT: renamable $x26 = LDtocCPT %const.12, $x2 :: (load (s64) from got) + ; 64BIT-NEXT: renamable $x29 = RLDIC killed renamable $x3, 52, 2 + ; 64BIT-NEXT: renamable $x28 = RLDIC killed renamable $x4, 53, 2 + ; 64BIT-NEXT: renamable $x11 = RLDIMI killed renamable $x11, renamable $x11, 32, 0 + ; 64BIT-NEXT: renamable $x12 = RLDIMI killed renamable $x12, renamable $x12, 32, 0 + ; 64BIT-NEXT: renamable $x0 = RLDIMI killed renamable $x0, renamable $x0, 32, 0 + ; 64BIT-NEXT: renamable $x31 = RLDIMI killed renamable $x31, renamable $x31, 32, 0 + ; 64BIT-NEXT: renamable $x30 = RLDIMI killed renamable $x30, renamable $x30, 32, 0 + ; 64BIT-NEXT: renamable $x3 = RLDIC killed renamable $x5, 34, 2 + ; 64BIT-NEXT: renamable $x4 = RLDIC killed renamable $x6, 32, 2 + ; 64BIT-NEXT: renamable $x5 = RLDIC killed renamable $x7, 34, 2 + ; 64BIT-NEXT: renamable $x6 = RLDIC killed renamable $x8, 32, 2 + ; 64BIT-NEXT: renamable $x7 = RLDIC killed renamable $x9, 32, 2 + ; 64BIT-NEXT: renamable $x8 = RLDIC killed renamable $x10, 32, 2 + ; 64BIT-NEXT: renamable $x9 = RLDIC killed renamable $x27, 32, 2 + ; 64BIT-NEXT: renamable $x11 = RLWIMI8 killed renamable $x11, renamable $x11, 16, 0, 15 + ; 64BIT-NEXT: renamable $x12 = RLWIMI8 killed renamable $x12, renamable $x12, 16, 0, 15 + ; 64BIT-NEXT: renamable $x0 = RLWIMI8 killed renamable $x0, renamable $x0, 16, 0, 15 + ; 64BIT-NEXT: renamable $x31 = RLWIMI8 killed renamable $x31, renamable $x31, 16, 0, 15 + ; 64BIT-NEXT: renamable $x30 = RLWIMI8 killed renamable $x30, renamable $x30, 16, 0, 15 + ; 64BIT-NEXT: renamable $x3 = ORIS8 killed renamable $x3, 52428 + ; 64BIT-NEXT: renamable $x4 = ORIS8 killed renamable $x4, 39321 + ; 64BIT-NEXT: renamable $x5 = ORIS8 killed renamable $x5, 52428 + ; 64BIT-NEXT: renamable $x6 = ORIS8 killed renamable $x6, 39321 + ; 64BIT-NEXT: renamable $x7 = ORIS8 killed renamable $x7, 39321 + ; 64BIT-NEXT: renamable $x8 = ORIS8 killed renamable $x8, 39321 + ; 64BIT-NEXT: renamable $x9 = ORIS8 killed renamable $x9, 39321 + ; 64BIT-NEXT: renamable $f7 = LFD 0, killed renamable $x22 :: (load (s64) from constant-pool) + ; 64BIT-NEXT: renamable $x27 = ORI8 killed renamable $x3, 52429 + ; 64BIT-NEXT: renamable $f8 = LFD 0, killed renamable $x21 :: (load (s64) from constant-pool) + ; 64BIT-NEXT: renamable $x25 = ORI8 killed renamable $x4, 39322 + ; 64BIT-NEXT: renamable $f9 = LFD 0, killed renamable $x20 :: (load (s64) from constant-pool) + ; 64BIT-NEXT: renamable $x24 = ORI8 killed renamable $x5, 52429 + ; 64BIT-NEXT: renamable $f11 = LFD 0, killed renamable $x19 :: (load (s64) from constant-pool) + ; 64BIT-NEXT: renamable $x23 = ORI8 killed renamable $x6, 39322 + ; 64BIT-NEXT: renamable $f12 = LFD 0, killed renamable $x18 :: (load (s64) from constant-pool) + ; 64BIT-NEXT: renamable $x22 = ORI8 killed renamable $x7, 39322 + ; 64BIT-NEXT: renamable $f13 = LFD 0, killed renamable $x17 :: (load (s64) from constant-pool) + ; 64BIT-NEXT: renamable $x21 = ORI8 killed renamable $x8, 39322 + ; 64BIT-NEXT: renamable $f5 = LFS 0, killed renamable $x16 :: (load (s32) from constant-pool) + ; 64BIT-NEXT: renamable $x20 = ORI8 killed renamable $x9, 39322 + ; 64BIT-NEXT: renamable $f10 = LFS 0, killed renamable $x26 :: (load (s32) from constant-pool) + ; 64BIT-NEXT: $x3 = LI8 1 + ; 64BIT-NEXT: $x4 = LI8 2 + ; 64BIT-NEXT: $x5 = LI8 3 + ; 64BIT-NEXT: $x6 = LI8 4 + ; 64BIT-NEXT: $x7 = LI8 5 + ; 64BIT-NEXT: $x8 = LI8 6 + ; 64BIT-NEXT: $x9 = LI8 7 + ; 64BIT-NEXT: $x10 = LI8 8 + ; 64BIT-NEXT: STD killed renamable $x29, 184, $x1 :: (store (s64)) + ; 64BIT-NEXT: STD killed renamable $x28, 144, $x1 :: (store (s64)) + ; 64BIT-NEXT: STD killed renamable $x11, 216, $x1 :: (store (s64)) + ; 64BIT-NEXT: STD killed renamable $x12, 200, $x1 :: (store (s64)) + ; 64BIT-NEXT: STD killed renamable $x0, 160, $x1 :: (store (s64)) + ; 64BIT-NEXT: STD killed renamable $x31, 152, $x1 :: (store (s64)) + ; 64BIT-NEXT: STD killed renamable $x30, 128, $x1 :: (store (s64)) + ; 64BIT-NEXT: STD killed renamable $x27, 208, $x1 :: (store (s64)) + ; 64BIT-NEXT: STD killed renamable $x25, 192, $x1 :: (store (s64)) + ; 64BIT-NEXT: STD killed renamable $x24, 176, $x1 :: (store (s64)) + ; 64BIT-NEXT: STD killed renamable $x23, 168, $x1 :: (store (s64)) + ; 64BIT-NEXT: STD killed renamable $x22, 136, $x1 :: (store (s64)) + ; 64BIT-NEXT: STD killed renamable $x21, 120, $x1 :: (store (s64)) + ; 64BIT-NEXT: STD killed renamable $x20, 112, $x1 :: (store (s64)) + ; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit $f10, implicit $f11, implicit $f12, implicit $f13, implicit $x2, implicit-def $r1, implicit-def dead $x3 + ; 64BIT-NEXT: ADJCALLSTACKUP 224, 0, implicit-def dead $r1, implicit $r1 + ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm + entry: + %call = call i32 @mix_floats(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, double 1.000000e-01, double 2.000000e-01, double 3.000000e-01, double 4.000000e-01, double 5.000000e-01, double 6.000000e-01, double 0x3FE6666666666666, double 8.000000e-01, double 9.000000e-01, double 1.000000e+00, double 1.100000e+00, double 1.200000e+00, double 1.300000e+00, double 1.400000e+00) + ret void + } + diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll b/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll index 02fe9943f39c..78d60f06c067 100644 --- a/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll +++ b/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll @@ -1,42 +1,57 @@ -; RUN: llc -mtriple powerpc-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | \ -; RUN: FileCheck --check-prefixes=CHECK,32BIT %s - +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \ ; RUN: -mtriple powerpc-ibm-aix-xcoff < %s | \ ; RUN: FileCheck --check-prefixes=CHECKASM,ASM32PWR4 %s -; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | \ -; RUN: FileCheck --check-prefixes=CHECK,64BIT %s - ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \ ; RUN: -mtriple powerpc64-ibm-aix-xcoff < %s | \ ; RUN: FileCheck --check-prefixes=CHECKASM,ASM64PWR4 %s define void @call_test_chars() { +; ASM32PWR4-LABEL: call_test_chars: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: mflr 0 +; ASM32PWR4-NEXT: stwu 1, -64(1) +; ASM32PWR4-NEXT: li 3, 97 +; ASM32PWR4-NEXT: li 4, 97 +; ASM32PWR4-NEXT: stw 0, 72(1) +; ASM32PWR4-NEXT: li 5, 97 +; ASM32PWR4-NEXT: li 6, 97 +; ASM32PWR4-NEXT: bl .test_chars +; ASM32PWR4-NEXT: nop +; ASM32PWR4-NEXT: addi 1, 1, 64 +; ASM32PWR4-NEXT: lwz 0, 8(1) +; ASM32PWR4-NEXT: mtlr 0 +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: call_test_chars: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: mflr 0 +; ASM64PWR4-NEXT: stdu 1, -112(1) +; ASM64PWR4-NEXT: li 3, 97 +; ASM64PWR4-NEXT: li 4, 97 +; ASM64PWR4-NEXT: std 0, 128(1) +; ASM64PWR4-NEXT: li 5, 97 +; ASM64PWR4-NEXT: li 6, 97 +; ASM64PWR4-NEXT: bl .test_chars +; ASM64PWR4-NEXT: nop +; ASM64PWR4-NEXT: addi 1, 1, 112 +; ASM64PWR4-NEXT: ld 0, 16(1) +; ASM64PWR4-NEXT: mtlr 0 +; ASM64PWR4-NEXT: blr entry: call i8 @test_chars(i8 signext 97, i8 signext 97, i8 signext 97, i8 signext 97) ret void } -; CHECK-LABEL: name: call_test_chars - -; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 -; 32BIT: $r3 = LI 97 -; 32BIT: $r4 = LI 97 -; 32BIT: $r5 = LI 97 -; 32BIT: $r6 = LI 97 -; 32BIT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit $r2, implicit-def $r1 -; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 - -; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 -; 64BIT: $x3 = LI8 97 -; 64BIT: $x4 = LI8 97 -; 64BIT: $x5 = LI8 97 -; 64BIT: $x6 = LI8 97 -; 64BIT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit $x2, implicit-def $r1 -; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 - define signext i8 @test_chars(i8 signext %c1, i8 signext %c2, i8 signext %c3, i8 signext %c4) { +; CHECKASM-LABEL: test_chars: +; CHECKASM: # %bb.0: # %entry +; CHECKASM-NEXT: add 3, 3, 4 +; CHECKASM-NEXT: add 3, 3, 5 +; CHECKASM-NEXT: add 3, 3, 6 +; CHECKASM-NEXT: extsb 3, 3 +; CHECKASM-NEXT: blr entry: %conv = sext i8 %c1 to i32 %conv1 = sext i8 %c2 to i32 @@ -49,51 +64,51 @@ entry: ret i8 %conv6 } -; CHECK-LABEL: name: test_chars - -; 32BIT: liveins: -; 32BIT-NEXT: - { reg: '$r3', virtual-reg: '' } -; 32BIT-NEXT: - { reg: '$r4', virtual-reg: '' } -; 32BIT-NEXT: - { reg: '$r5', virtual-reg: '' } -; 32BIT-NEXT: - { reg: '$r6', virtual-reg: '' } -; 32BIT: body: -; 32BIT-NEXT: bb.0.entry: -; 32BIT-NEXT: liveins: $r3, $r4, $r5, $r6 - -; 64BIT: liveins: -; 64BIT-NEXT: - { reg: '$x3', virtual-reg: '' } -; 64BIT-NEXT: - { reg: '$x4', virtual-reg: '' } -; 64BIT-NEXT: - { reg: '$x5', virtual-reg: '' } -; 64BIT-NEXT: - { reg: '$x6', virtual-reg: '' } -; 64BIT: body: -; 64BIT-NEXT: bb.0.entry: -; 64BIT-NEXT: liveins: $x3, $x4, $x5, $x6 - define void @call_test_chars_mix() { +; ASM32PWR4-LABEL: call_test_chars_mix: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: mflr 0 +; ASM32PWR4-NEXT: stwu 1, -64(1) +; ASM32PWR4-NEXT: li 3, 97 +; ASM32PWR4-NEXT: li 4, 225 +; ASM32PWR4-NEXT: stw 0, 72(1) +; ASM32PWR4-NEXT: li 5, 97 +; ASM32PWR4-NEXT: li 6, -31 +; ASM32PWR4-NEXT: bl .test_chars_mix +; ASM32PWR4-NEXT: nop +; ASM32PWR4-NEXT: addi 1, 1, 64 +; ASM32PWR4-NEXT: lwz 0, 8(1) +; ASM32PWR4-NEXT: mtlr 0 +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: call_test_chars_mix: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: mflr 0 +; ASM64PWR4-NEXT: stdu 1, -112(1) +; ASM64PWR4-NEXT: li 3, 97 +; ASM64PWR4-NEXT: li 4, 225 +; ASM64PWR4-NEXT: std 0, 128(1) +; ASM64PWR4-NEXT: li 5, 97 +; ASM64PWR4-NEXT: li 6, -31 +; ASM64PWR4-NEXT: bl .test_chars_mix +; ASM64PWR4-NEXT: nop +; ASM64PWR4-NEXT: addi 1, 1, 112 +; ASM64PWR4-NEXT: ld 0, 16(1) +; ASM64PWR4-NEXT: mtlr 0 +; ASM64PWR4-NEXT: blr entry: call i8 @test_chars_mix(i8 signext 97, i8 zeroext -31, i8 zeroext 97, i8 signext -31) ret void } -; CHECK-LABEL: name: call_test_chars_mix - -; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 -; 32BIT: $r3 = LI 97 -; 32BIT: $r4 = LI 225 -; 32BIT: $r5 = LI 97 -; 32BIT: $r6 = LI -31 -; 32BIT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit $r2, implicit-def $r1 -; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 - -; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 -; 64BIT: $x3 = LI8 97 -; 64BIT: $x4 = LI8 225 -; 64BIT: $x5 = LI8 97 -; 64BIT: $x6 = LI8 -31 -; 64BIT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit $x2, implicit-def $r1 -; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 - define signext i8 @test_chars_mix(i8 signext %c1, i8 zeroext %c2, i8 zeroext %c3, i8 signext %c4) { +; CHECKASM-LABEL: test_chars_mix: +; CHECKASM: # %bb.0: # %entry +; CHECKASM-NEXT: add 3, 3, 4 +; CHECKASM-NEXT: add 3, 3, 5 +; CHECKASM-NEXT: add 3, 3, 6 +; CHECKASM-NEXT: extsb 3, 3 +; CHECKASM-NEXT: blr entry: %conv = sext i8 %c1 to i32 %conv1 = zext i8 %c2 to i32 @@ -106,92 +121,88 @@ entry: ret i8 %conv6 } -; CHECK-LABEL: name: test_chars_mix - -; 32BIT: liveins: -; 32BIT-NEXT: - { reg: '$r3', virtual-reg: '' } -; 32BIT-NEXT: - { reg: '$r4', virtual-reg: '' } -; 32BIT-NEXT: - { reg: '$r5', virtual-reg: '' } -; 32BIT-NEXT: - { reg: '$r6', virtual-reg: '' } -; 32BIT: body: -; 32BIT-NEXT: bb.0.entry: -; 32BIT-NEXT: liveins: $r3, $r4, $r5, $r6 - -; 64BIT: liveins: -; 64BIT-NEXT: - { reg: '$x3', virtual-reg: '' } -; 64BIT-NEXT: - { reg: '$x4', virtual-reg: '' } -; 64BIT-NEXT: - { reg: '$x5', virtual-reg: '' } -; 64BIT-NEXT: - { reg: '$x6', virtual-reg: '' } -; 64BIT: body: -; 64BIT-NEXT: bb.0.entry: -; 64BIT-NEXT: liveins: $x3, $x4, $x5, $x6 - @global_i1 = global i8 0, align 1 define void @test_i1(i1 %b) { +; ASM32PWR4-LABEL: test_i1: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: lwz 4, L..C0(2) # @global_i1 +; ASM32PWR4-NEXT: clrlwi 3, 3, 31 +; ASM32PWR4-NEXT: stb 3, 0(4) +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: test_i1: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: ld 4, L..C0(2) # @global_i1 +; ASM64PWR4-NEXT: clrlwi 3, 3, 31 +; ASM64PWR4-NEXT: stb 3, 0(4) +; ASM64PWR4-NEXT: blr entry: %frombool = zext i1 %b to i8 store i8 %frombool, ptr @global_i1, align 1 ret void } -; 32BIT: liveins: -; 32BIT-NEXT: - { reg: '$r3', virtual-reg: '' } -; 32BIT: body: | -; 32BIT-NEXT: bb.0.entry: -; 32BIT-NEXT: liveins: $r3 -; 32BIT: renamable $r3 = RLWINM killed renamable $r3, 0, 31, 31 -; 32BIT-NEXT: STB killed renamable $r3, 0, killed renamable $r4 :: (store (s8) into @global_i1) - -; 64BIT: liveins: -; 64BIT-NEXT: - { reg: '$x3', virtual-reg: '' } -; 64BIT: body: | -; 64BIT-NEXT: bb.0.entry: -; 64BIT-NEXT: liveins: $x3 -; 64BIT: renamable $r[[REG1:[0-9]+]] = RLWINM renamable $r[[REG1]], 0, 31, 31, implicit killed $x3 -; 64BIT-NEXT: STB killed renamable $r[[REG1]], 0, killed renamable $x4 :: (store (s8) into @global_i1) - define void @call_test_i1() { +; ASM32PWR4-LABEL: call_test_i1: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: mflr 0 +; ASM32PWR4-NEXT: stwu 1, -64(1) +; ASM32PWR4-NEXT: li 3, 1 +; ASM32PWR4-NEXT: stw 0, 72(1) +; ASM32PWR4-NEXT: bl .test_i1 +; ASM32PWR4-NEXT: nop +; ASM32PWR4-NEXT: addi 1, 1, 64 +; ASM32PWR4-NEXT: lwz 0, 8(1) +; ASM32PWR4-NEXT: mtlr 0 +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: call_test_i1: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: mflr 0 +; ASM64PWR4-NEXT: stdu 1, -112(1) +; ASM64PWR4-NEXT: li 3, 1 +; ASM64PWR4-NEXT: std 0, 128(1) +; ASM64PWR4-NEXT: bl .test_i1 +; ASM64PWR4-NEXT: nop +; ASM64PWR4-NEXT: addi 1, 1, 112 +; ASM64PWR4-NEXT: ld 0, 16(1) +; ASM64PWR4-NEXT: mtlr 0 +; ASM64PWR4-NEXT: blr entry: call void @test_i1(i1 1) ret void } -; CHECK-LABEL: name: call_test_i1 - -; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 -; 32BIT: $r3 = LI 1 -; 32BIT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit $r2, implicit-def $r1 -; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 - -; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 -; 64BIT: $x3 = LI8 1 -; 64BIT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1 -; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 define void @test_i1zext(i1 zeroext %b) { +; ASM32PWR4-LABEL: test_i1zext: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: lwz 4, L..C0(2) # @global_i1 +; ASM32PWR4-NEXT: stb 3, 0(4) +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: test_i1zext: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: ld 4, L..C0(2) # @global_i1 +; ASM64PWR4-NEXT: stb 3, 0(4) +; ASM64PWR4-NEXT: blr entry: %frombool = zext i1 %b to i8 store i8 %frombool, ptr @global_i1, align 1 ret void } -; 32BIT: liveins: -; 32BIT-NEXT: - { reg: '$r3', virtual-reg: '' } -; 32BIT: body: | -; 32BIT-NEXT: bb.0.entry: -; 32BIT-NEXT: liveins: $r3 -; CHECK-NOT: RLWINM -; 32BIT: STB killed renamable $r3, 0, killed renamable $r4 :: (store (s8) into @global_i1) - -; 64BIT: liveins: -; 64BIT-NEXT: - { reg: '$x3', virtual-reg: '' } -; 64BIT: body: | -; 64BIT-NEXT: bb.0.entry: -; 64BIT-NEXT: liveins: $x3 -; CHECK-NOT: RLWINM -; 64BIT: STB8 killed renamable $x3, 0, killed renamable $x4 :: (store (s8) into @global_i1) - define i32 @test_ints(i32 signext %a, i32 zeroext %b, i32 zeroext %c, i32 signext %d, i32 signext %e, i32 signext %f, i32 signext %g, i32 signext %h) { +; CHECKASM-LABEL: test_ints: +; CHECKASM: # %bb.0: # %entry +; CHECKASM-NEXT: add 3, 3, 4 +; CHECKASM-NEXT: add 3, 3, 5 +; CHECKASM-NEXT: add 3, 3, 6 +; CHECKASM-NEXT: add 3, 3, 7 +; CHECKASM-NEXT: add 3, 3, 8 +; CHECKASM-NEXT: add 3, 3, 9 +; CHECKASM-NEXT: add 3, 3, 10 +; CHECKASM-NEXT: blr entry: %add = add i32 %a, %b %add1 = add i32 %add, %c @@ -203,84 +214,109 @@ entry: ret i32 %add6 } -; CHECK-LABEL: name: test_ints - -; 32BIT: liveins: -; 32BIT-NEXT: - { reg: '$r3', virtual-reg: '' } -; 32BIT-NEXT: - { reg: '$r4', virtual-reg: '' } -; 32BIT-NEXT: - { reg: '$r5', virtual-reg: '' } -; 32BIT-NEXT: - { reg: '$r6', virtual-reg: '' } -; 32BIT-NEXT: - { reg: '$r7', virtual-reg: '' } -; 32BIT-NEXT: - { reg: '$r8', virtual-reg: '' } -; 32BIT-NEXT: - { reg: '$r9', virtual-reg: '' } -; 32BIT-NEXT: - { reg: '$r10', virtual-reg: '' } -; 32BIT: body: | -; 32BIT-NEXT: bb.0.entry: -; 32BIT-NEXT: liveins: $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10 - -; 64BIT: liveins: -; 64BIT-NEXT: - { reg: '$x3', virtual-reg: '' } -; 64BIT-NEXT: - { reg: '$x4', virtual-reg: '' } -; 64BIT-NEXT: - { reg: '$x5', virtual-reg: '' } -; 64BIT-NEXT: - { reg: '$x6', virtual-reg: '' } -; 64BIT-NEXT: - { reg: '$x7', virtual-reg: '' } -; 64BIT-NEXT: - { reg: '$x8', virtual-reg: '' } -; 64BIT-NEXT: - { reg: '$x9', virtual-reg: '' } -; 64BIT-NEXT: - { reg: '$x10', virtual-reg: '' } -; 64BIT: body: | -; 64BIT-NEXT: bb.0.entry: -; 64BIT-NEXT: liveins: $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10 - define void @call_test_ints() { +; ASM32PWR4-LABEL: call_test_ints: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: mflr 0 +; ASM32PWR4-NEXT: stwu 1, -64(1) +; ASM32PWR4-NEXT: li 3, 1 +; ASM32PWR4-NEXT: li 4, 1 +; ASM32PWR4-NEXT: stw 0, 72(1) +; ASM32PWR4-NEXT: lis 5, -32768 +; ASM32PWR4-NEXT: lis 6, -32768 +; ASM32PWR4-NEXT: li 7, 1 +; ASM32PWR4-NEXT: li 8, 1 +; ASM32PWR4-NEXT: li 9, 1 +; ASM32PWR4-NEXT: li 10, 1 +; ASM32PWR4-NEXT: bl .test_ints +; ASM32PWR4-NEXT: nop +; ASM32PWR4-NEXT: addi 1, 1, 64 +; ASM32PWR4-NEXT: lwz 0, 8(1) +; ASM32PWR4-NEXT: mtlr 0 +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: call_test_ints: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: mflr 0 +; ASM64PWR4-NEXT: stdu 1, -112(1) +; ASM64PWR4-NEXT: li 3, 1 +; ASM64PWR4-NEXT: li 4, 1 +; ASM64PWR4-NEXT: std 0, 128(1) +; ASM64PWR4-NEXT: rldic 5, 3, 31, 32 +; ASM64PWR4-NEXT: lis 6, -32768 +; ASM64PWR4-NEXT: li 7, 1 +; ASM64PWR4-NEXT: li 8, 1 +; ASM64PWR4-NEXT: li 9, 1 +; ASM64PWR4-NEXT: li 10, 1 +; ASM64PWR4-NEXT: bl .test_ints +; ASM64PWR4-NEXT: nop +; ASM64PWR4-NEXT: addi 1, 1, 112 +; ASM64PWR4-NEXT: ld 0, 16(1) +; ASM64PWR4-NEXT: mtlr 0 +; ASM64PWR4-NEXT: blr entry: call i32 @test_ints(i32 signext 1, i32 zeroext 1, i32 zeroext 2147483648, i32 signext -2147483648, i32 signext 1, i32 signext 1, i32 signext 1, i32 signext 1) ret void } -; CHECK-LABEL: name: call_test_ints - -; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 -; 64BIT: renamable $x3 = LI8 1 -; 64BIT: renamable $x5 = RLDIC killed renamable $x3, 31, 32 -; 64BIT: $x3 = LI8 1 -; 64BIT: $x4 = LI8 1 -; 64BIT: $x6 = LIS8 32768 -; 64BIT: $x7 = LI8 1 -; 64BIT: $x8 = LI8 1 -; 64BIT: $x9 = LI8 1 -; 64BIT: $x10 = LI8 1 -; 64BIT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit killed $x10, implicit $x2, implicit-def $r1, implicit-def dead $x3 -; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 - define void @call_test_i64() { +; ASM32PWR4-LABEL: call_test_i64: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: mflr 0 +; ASM32PWR4-NEXT: stwu 1, -64(1) +; ASM32PWR4-NEXT: li 3, 0 +; ASM32PWR4-NEXT: li 4, 1 +; ASM32PWR4-NEXT: stw 0, 72(1) +; ASM32PWR4-NEXT: li 5, 0 +; ASM32PWR4-NEXT: li 6, 2 +; ASM32PWR4-NEXT: li 7, 0 +; ASM32PWR4-NEXT: li 8, 3 +; ASM32PWR4-NEXT: li 9, 0 +; ASM32PWR4-NEXT: li 10, 4 +; ASM32PWR4-NEXT: bl .test_i64 +; ASM32PWR4-NEXT: nop +; ASM32PWR4-NEXT: addi 1, 1, 64 +; ASM32PWR4-NEXT: lwz 0, 8(1) +; ASM32PWR4-NEXT: mtlr 0 +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: call_test_i64: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: mflr 0 +; ASM64PWR4-NEXT: stdu 1, -112(1) +; ASM64PWR4-NEXT: li 3, 1 +; ASM64PWR4-NEXT: li 4, 2 +; ASM64PWR4-NEXT: std 0, 128(1) +; ASM64PWR4-NEXT: li 5, 3 +; ASM64PWR4-NEXT: li 6, 4 +; ASM64PWR4-NEXT: bl .test_i64 +; ASM64PWR4-NEXT: nop +; ASM64PWR4-NEXT: addi 1, 1, 112 +; ASM64PWR4-NEXT: ld 0, 16(1) +; ASM64PWR4-NEXT: mtlr 0 +; ASM64PWR4-NEXT: blr entry: call i64 @test_i64(i64 1, i64 2, i64 3, i64 4) ret void } -; CHECK-LABEL: name: call_test_i64 - -; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 -; 32BIT: $r3 = LI 0 -; 32BIT: $r4 = LI 1 -; 32BIT: $r5 = LI 0 -; 32BIT: $r6 = LI 2 -; 32BIT: $r7 = LI 0 -; 32BIT: $r8 = LI 3 -; 32BIT: $r9 = LI 0 -; 32BIT: $r10 = LI 4 -; 32BIT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit killed $r10, implicit $r2, implicit-def $r1 -; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 - -; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 -; 64BIT: $x3 = LI8 1 -; 64BIT: $x4 = LI8 2 -; 64BIT: $x5 = LI8 3 -; 64BIT: $x6 = LI8 4 -; 64BIT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit $x2, implicit-def $r1 -; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 - define i64 @test_i64(i64 %a, i64 %b, i64 %c, i64 %d) { +; ASM32PWR4-LABEL: test_i64: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: addc 4, 4, 6 +; ASM32PWR4-NEXT: adde 3, 3, 5 +; ASM32PWR4-NEXT: addc 4, 4, 8 +; ASM32PWR4-NEXT: adde 3, 3, 7 +; ASM32PWR4-NEXT: addc 4, 4, 10 +; ASM32PWR4-NEXT: adde 3, 3, 9 +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: test_i64: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: add 3, 3, 4 +; ASM64PWR4-NEXT: add 3, 3, 5 +; ASM64PWR4-NEXT: add 3, 3, 6 +; ASM64PWR4-NEXT: blr entry: %add = add nsw i64 %a, %b %add1 = add nsw i64 %add, %c @@ -288,31 +324,36 @@ entry: ret i64 %add2 } -; CHECK-LABEL: name: test_i64 - -; 32BIT: liveins: -; 32BIT-NEXT: - { reg: '$r3', virtual-reg: '' } -; 32BIT-NEXT: - { reg: '$r4', virtual-reg: '' } -; 32BIT-NEXT: - { reg: '$r5', virtual-reg: '' } -; 32BIT-NEXT: - { reg: '$r6', virtual-reg: '' } -; 32BIT-NEXT: - { reg: '$r7', virtual-reg: '' } -; 32BIT-NEXT: - { reg: '$r8', virtual-reg: '' } -; 32BIT-NEXT: - { reg: '$r9', virtual-reg: '' } -; 32BIT-NEXT: - { reg: '$r10', virtual-reg: '' } -; 32BIT: body: | -; 32BIT-NEXT: bb.0.entry: -; 32BIT-NEXT: liveins: $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10 - -; 64BIT: liveins: -; 64BIT-NEXT: - { reg: '$x3', virtual-reg: '' } -; 64BIT-NEXT: - { reg: '$x4', virtual-reg: '' } -; 64BIT-NEXT: - { reg: '$x5', virtual-reg: '' } -; 64BIT-NEXT: - { reg: '$x6', virtual-reg: '' } -; 64BIT: body: | -; 64BIT-NEXT: bb.0.entry: -; 64BIT-NEXT: liveins: $x3, $x4, $x5, $x6 - define void @call_test_int_ptr() { +; ASM32PWR4-LABEL: call_test_int_ptr: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: mflr 0 +; ASM32PWR4-NEXT: stwu 1, -64(1) +; ASM32PWR4-NEXT: li 3, 0 +; ASM32PWR4-NEXT: stw 0, 72(1) +; ASM32PWR4-NEXT: stw 3, 60(1) +; ASM32PWR4-NEXT: addi 3, 1, 60 +; ASM32PWR4-NEXT: bl .test_int_ptr +; ASM32PWR4-NEXT: nop +; ASM32PWR4-NEXT: addi 1, 1, 64 +; ASM32PWR4-NEXT: lwz 0, 8(1) +; ASM32PWR4-NEXT: mtlr 0 +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: call_test_int_ptr: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: mflr 0 +; ASM64PWR4-NEXT: stdu 1, -128(1) +; ASM64PWR4-NEXT: li 3, 0 +; ASM64PWR4-NEXT: std 0, 144(1) +; ASM64PWR4-NEXT: stw 3, 124(1) +; ASM64PWR4-NEXT: addi 3, 1, 124 +; ASM64PWR4-NEXT: bl .test_int_ptr +; ASM64PWR4-NEXT: nop +; ASM64PWR4-NEXT: addi 1, 1, 128 +; ASM64PWR4-NEXT: ld 0, 16(1) +; ASM64PWR4-NEXT: mtlr 0 +; ASM64PWR4-NEXT: blr entry: %b = alloca i32, align 4 store i32 0, ptr %b, align 4 @@ -320,43 +361,56 @@ entry: ret void } -; CHECK-LABEL: name: call_test_int_ptr - -; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 -; 32BIT: renamable $r3 = ADDI %stack.0.b, 0 -; 32BIT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1 -; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 - -; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 -; 64BIT: renamable $x3 = ADDI8 %stack.0.b, 0 -; 64BIT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 -; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 - define void @test_int_ptr(ptr %a) { +; ASM32PWR4-LABEL: test_int_ptr: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: stw 3, -8(1) +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: test_int_ptr: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: std 3, -8(1) +; ASM64PWR4-NEXT: blr entry: %a.addr = alloca ptr, align 8 store ptr %a, ptr %a.addr, align 8 ret void } -; CHECK-LABEL: name: test_int_ptr - -; 32BIT: liveins: -; 32BIT-NEXT: - { reg: '$r3', virtual-reg: '' } -; 32BIT: body: | -; 32BIT-NEXT: bb.0.entry: -; 32BIT-NEXT: liveins: $r3 -; 32BIT: STW killed renamable $r3, 0, %stack.0.a.addr :: (store (s32) into %ir.a.addr, align 8) - -; 64BIT: liveins: -; 64BIT-NEXT: - { reg: '$x3', virtual-reg: '' } -; 64BIT: body: | -; 64BIT-NEXT: bb.0.entry: -; 64BIT-NEXT: liveins: $x3 -; 64BIT: STD killed renamable $x3, 0, %stack.0.a.addr :: (store (s64) into %ir.a.addr) - - define i32 @caller(i32 %i) { +; ASM32PWR4-LABEL: caller: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: mflr 0 +; ASM32PWR4-NEXT: stwu 1, -64(1) +; ASM32PWR4-NEXT: stw 0, 72(1) +; ASM32PWR4-NEXT: stw 3, 60(1) +; ASM32PWR4-NEXT: cntlzw 3, 3 +; ASM32PWR4-NEXT: not 3, 3 +; ASM32PWR4-NEXT: rlwinm 3, 3, 27, 31, 31 +; ASM32PWR4-NEXT: stb 3, 59(1) +; ASM32PWR4-NEXT: bl .call_test_bool[PR] +; ASM32PWR4-NEXT: nop +; ASM32PWR4-NEXT: addi 1, 1, 64 +; ASM32PWR4-NEXT: lwz 0, 8(1) +; ASM32PWR4-NEXT: mtlr 0 +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: caller: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: mflr 0 +; ASM64PWR4-NEXT: stdu 1, -128(1) +; ASM64PWR4-NEXT: std 0, 144(1) +; ASM64PWR4-NEXT: stw 3, 124(1) +; ASM64PWR4-NEXT: cntlzw 3, 3 +; ASM64PWR4-NEXT: srwi 3, 3, 5 +; ASM64PWR4-NEXT: xori 3, 3, 1 +; ASM64PWR4-NEXT: stb 3, 123(1) +; ASM64PWR4-NEXT: bl .call_test_bool[PR] +; ASM64PWR4-NEXT: nop +; ASM64PWR4-NEXT: addi 1, 1, 128 +; ASM64PWR4-NEXT: ld 0, 16(1) +; ASM64PWR4-NEXT: mtlr 0 +; ASM64PWR4-NEXT: blr entry: %i.addr = alloca i32, align 4 %b = alloca i8, align 1 @@ -373,187 +427,147 @@ entry: declare i32 @call_test_bool(i1 zeroext) -; CHECK-LABEL: name: caller - -; 32BIT: liveins: -; 32BIT-NEXT: - { reg: '$r3', virtual-reg: '' } -; 32BIT: body: | -; 32BIT-NEXT: bb.0.entry: -; 32BIT: liveins: $r3 -; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 -; 32BIT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1, implicit-def $r3 -; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 - -; 64BIT: liveins: -; 64BIT-NEXT: - { reg: '$x3', virtual-reg: '' } -; 64BIT: body: | -; 64BIT-NEXT: bb.0.entry: -; 64BIT-NEXT: liveins: $x3 -; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 -; 64BIT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1, implicit-def $x3 -; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 - @f1 = global float 0.000000e+00, align 4 @d1 = global double 0.000000e+00, align 8 define void @call_test_floats() { +; ASM32PWR4-LABEL: call_test_floats: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: mflr 0 +; ASM32PWR4-NEXT: stwu 1, -64(1) +; ASM32PWR4-NEXT: lwz 3, L..C1(2) # @f1 +; ASM32PWR4-NEXT: stw 0, 72(1) +; ASM32PWR4-NEXT: lfs 1, 0(3) +; ASM32PWR4-NEXT: fmr 2, 1 +; ASM32PWR4-NEXT: fmr 3, 1 +; ASM32PWR4-NEXT: bl .test_floats +; ASM32PWR4-NEXT: nop +; ASM32PWR4-NEXT: addi 1, 1, 64 +; ASM32PWR4-NEXT: lwz 0, 8(1) +; ASM32PWR4-NEXT: mtlr 0 +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: call_test_floats: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: mflr 0 +; ASM64PWR4-NEXT: stdu 1, -112(1) +; ASM64PWR4-NEXT: ld 3, L..C1(2) # @f1 +; ASM64PWR4-NEXT: std 0, 128(1) +; ASM64PWR4-NEXT: lfs 1, 0(3) +; ASM64PWR4-NEXT: fmr 2, 1 +; ASM64PWR4-NEXT: fmr 3, 1 +; ASM64PWR4-NEXT: bl .test_floats +; ASM64PWR4-NEXT: nop +; ASM64PWR4-NEXT: addi 1, 1, 112 +; ASM64PWR4-NEXT: ld 0, 16(1) +; ASM64PWR4-NEXT: mtlr 0 +; ASM64PWR4-NEXT: blr entry: %0 = load float, ptr @f1, align 4 call float @test_floats(float %0, float %0, float %0) ret void } -; CHECK-LABEL: name: call_test_floats{{.*}} - -; 32BIT: renamable $r3 = LWZtoc @f1, $r2 :: (load (s32) from got) -; 32BIT-NEXT: renamable $f1 = LFS 0, killed renamable $r3 :: (dereferenceable load (s32) from @f1) -; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 -; 32BIT-NEXT: $f2 = COPY renamable $f1 -; 32BIT-NEXT: $f3 = COPY renamable $f1 -; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit $r2, implicit-def $r1 -; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 - -; 64BIT: renamable $x3 = LDtoc @f1, $x2 :: (load (s64) from got) -; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x3 :: (dereferenceable load (s32) from @f1) -; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 -; 64BIT-NEXT: $f2 = COPY renamable $f1 -; 64BIT-NEXT: $f3 = COPY renamable $f1 -; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit $x2, implicit-def $r1 -; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 - define float @test_floats(float %f1, float %f2, float %f3) { +; CHECKASM-LABEL: test_floats: +; CHECKASM: # %bb.0: # %entry +; CHECKASM-NEXT: fadds 0, 1, 2 +; CHECKASM-NEXT: fadds 1, 0, 3 +; CHECKASM-NEXT: blr entry: %add = fadd float %f1, %f2 %add1 = fadd float %add, %f3 ret float %add1 } -; CHECK-LABEL: name: test_floats{{.*}} - -; CHECK: liveins: -; CHECK-NEXT: - { reg: '$f1', virtual-reg: '' } -; CHECK-NEXT: - { reg: '$f2', virtual-reg: '' } -; CHECK-NEXT: - { reg: '$f3', virtual-reg: '' } -; CHECK: body: | -; CHECK-NEXT: bb.0.entry: -; CHECK-NEXT: liveins: $f1, $f2, $f3 - define void @call_test_fpr_max() { +; ASM32PWR4-LABEL: call_test_fpr_max: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: mflr 0 +; ASM32PWR4-NEXT: stwu 1, -128(1) +; ASM32PWR4-NEXT: lwz 3, L..C2(2) # @d1 +; ASM32PWR4-NEXT: stw 0, 136(1) +; ASM32PWR4-NEXT: lfd 1, 0(3) +; ASM32PWR4-NEXT: fmr 2, 1 +; ASM32PWR4-NEXT: fmr 3, 1 +; ASM32PWR4-NEXT: stfd 1, 120(1) +; ASM32PWR4-NEXT: stfd 1, 112(1) +; ASM32PWR4-NEXT: fmr 4, 1 +; ASM32PWR4-NEXT: fmr 5, 1 +; ASM32PWR4-NEXT: stfd 1, 104(1) +; ASM32PWR4-NEXT: fmr 6, 1 +; ASM32PWR4-NEXT: fmr 7, 1 +; ASM32PWR4-NEXT: stfd 1, 96(1) +; ASM32PWR4-NEXT: stfd 1, 88(1) +; ASM32PWR4-NEXT: fmr 8, 1 +; ASM32PWR4-NEXT: fmr 9, 1 +; ASM32PWR4-NEXT: stfd 1, 80(1) +; ASM32PWR4-NEXT: fmr 10, 1 +; ASM32PWR4-NEXT: fmr 11, 1 +; ASM32PWR4-NEXT: stfd 1, 72(1) +; ASM32PWR4-NEXT: stfd 1, 64(1) +; ASM32PWR4-NEXT: fmr 12, 1 +; ASM32PWR4-NEXT: fmr 13, 1 +; ASM32PWR4-NEXT: stfd 1, 56(1) +; ASM32PWR4-NEXT: bl .test_fpr_max +; ASM32PWR4-NEXT: nop +; ASM32PWR4-NEXT: addi 1, 1, 128 +; ASM32PWR4-NEXT: lwz 0, 8(1) +; ASM32PWR4-NEXT: mtlr 0 +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: call_test_fpr_max: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: mflr 0 +; ASM64PWR4-NEXT: stdu 1, -160(1) +; ASM64PWR4-NEXT: ld 3, L..C2(2) # @d1 +; ASM64PWR4-NEXT: std 0, 176(1) +; ASM64PWR4-NEXT: lfd 1, 0(3) +; ASM64PWR4-NEXT: fmr 2, 1 +; ASM64PWR4-NEXT: fmr 3, 1 +; ASM64PWR4-NEXT: stfd 1, 144(1) +; ASM64PWR4-NEXT: stfd 1, 136(1) +; ASM64PWR4-NEXT: fmr 4, 1 +; ASM64PWR4-NEXT: fmr 5, 1 +; ASM64PWR4-NEXT: stfd 1, 128(1) +; ASM64PWR4-NEXT: fmr 6, 1 +; ASM64PWR4-NEXT: fmr 7, 1 +; ASM64PWR4-NEXT: stfd 1, 120(1) +; ASM64PWR4-NEXT: stfd 1, 112(1) +; ASM64PWR4-NEXT: fmr 8, 1 +; ASM64PWR4-NEXT: fmr 9, 1 +; ASM64PWR4-NEXT: fmr 10, 1 +; ASM64PWR4-NEXT: fmr 11, 1 +; ASM64PWR4-NEXT: fmr 12, 1 +; ASM64PWR4-NEXT: fmr 13, 1 +; ASM64PWR4-NEXT: bl .test_fpr_max +; ASM64PWR4-NEXT: nop +; ASM64PWR4-NEXT: addi 1, 1, 160 +; ASM64PWR4-NEXT: ld 0, 16(1) +; ASM64PWR4-NEXT: mtlr 0 +; ASM64PWR4-NEXT: blr entry: %0 = load double, ptr @d1, align 8 call double @test_fpr_max(double %0, double %0, double %0, double %0, double %0, double %0, double %0, double %0, double %0, double %0, double %0, double %0, double %0) ret void } -; CHECK-LABEL: name: call_test_fpr_max{{.*}} - -; 32BIT: renamable $r[[REG:[0-9]+]] = LWZtoc @d1, $r2 :: (load (s32) from got) -; 32BIT-NEXT: renamable $f1 = LFD 0, killed renamable $r[[REG]] :: (dereferenceable load (s64) from @d1) -; 32BIT-NEXT: ADJCALLSTACKDOWN 128, 0, implicit-def dead $r1, implicit $r1 -; 32BIT-DAG: STFD renamable $f1, 56, $r1 :: (store (s64)) -; 32BIT-DAG: STFD renamable $f1, 64, $r1 :: (store (s64)) -; 32BIT-DAG: STFD renamable $f1, 72, $r1 :: (store (s64)) -; 32BIT-DAG: STFD renamable $f1, 80, $r1 :: (store (s64)) -; 32BIT-DAG: STFD renamable $f1, 88, $r1 :: (store (s64)) -; 32BIT-DAG: STFD renamable $f1, 96, $r1 :: (store (s64)) -; 32BIT-DAG: STFD renamable $f1, 104, $r1 :: (store (s64)) -; 32BIT-DAG: STFD renamable $f1, 112, $r1 :: (store (s64)) -; 32BIT-DAG: STFD renamable $f1, 120, $r1 :: (store (s64)) -; 32BIT-DAG: $f2 = COPY renamable $f1 -; 32BIT-DAG: $f3 = COPY renamable $f1 -; 32BIT-DAG: $f4 = COPY renamable $f1 -; 32BIT-DAG: $f5 = COPY renamable $f1 -; 32BIT-DAG: $f6 = COPY renamable $f1 -; 32BIT-DAG: $f7 = COPY renamable $f1 -; 32BIT-DAG: $f8 = COPY renamable $f1 -; 32BIT-DAG: $f9 = COPY renamable $f1 -; 32BIT-DAG: $f10 = COPY renamable $f1 -; 32BIT-DAG: $f11 = COPY renamable $f1 -; 32BIT-DAG: $f12 = COPY renamable $f1 -; 32BIT-DAG: $f13 = COPY renamable $f1 -; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit killed $f4, implicit killed $f5, implicit killed $f6, implicit killed $f7, implicit killed $f8, implicit killed $f9, implicit killed $f10, implicit killed $f11, implicit killed $f12, implicit killed $f13, implicit $r2, implicit-def $r1, implicit-def dead $f1 -; 32BIT-NEXT: ADJCALLSTACKUP 128, 0, implicit-def dead $r1, implicit $r1 - -; CHECKASM-LABEL: .call_test_fpr_max: - -; ASM32PWR4: stwu 1, -128(1) -; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C2(2) -; ASM32PWR4-NEXT: stw 0, 136(1) -; ASM32PWR4-NEXT: lfd 1, 0([[REG]]) -; ASM32PWR4-DAG: stfd 1, 56(1) -; ASM32PWR4-DAG: stfd 1, 64(1) -; ASM32PWR4-DAG: stfd 1, 72(1) -; ASM32PWR4-DAG: stfd 1, 80(1) -; ASM32PWR4-DAG: stfd 1, 88(1) -; ASM32PWR4-DAG: stfd 1, 96(1) -; ASM32PWR4-DAG: stfd 1, 104(1) -; ASM32PWR4-DAG: stfd 1, 112(1) -; ASM32PWR4-DAG: stfd 1, 120(1) -; ASM32PWR4-DAG: fmr 2, 1 -; ASM32PWR4-DAG: fmr 3, 1 -; ASM32PWR4-DAG: fmr 4, 1 -; ASM32PWR4-DAG: fmr 5, 1 -; ASM32PWR4-DAG: fmr 6, 1 -; ASM32PWR4-DAG: fmr 7, 1 -; ASM32PWR4-DAG: fmr 8, 1 -; ASM32PWR4-DAG: fmr 9, 1 -; ASM32PWR4-DAG: fmr 10, 1 -; ASM32PWR4-DAG: fmr 11, 1 -; ASM32PWR4-DAG: fmr 12, 1 -; ASM32PWR4-DAG: fmr 13, 1 -; ASM32PWR4-NEXT: bl .test_fpr_max -; ASM32PWR4-NEXT: nop -; ASM32PWR4-NEXT: addi 1, 1, 128 - -; 64BIT: renamable $x[[REGD1ADDR:[0-9]+]] = LDtoc @d1, $x2 :: (load (s64) from got) -; 64BIT-NEXT: renamable $f1 = LFD 0, killed renamable $x[[REGD1ADDR:[0-9]+]] :: (dereferenceable load (s64) from @d1) -; 64BIT-NEXT: ADJCALLSTACKDOWN 152, 0, implicit-def dead $r1, implicit $r1 -; 64BIT-DAG: STFD renamable $f1, 112, $x1 :: (store (s64)) -; 64BIT-DAG: STFD renamable $f1, 120, $x1 :: (store (s64)) -; 64BIT-DAG: STFD renamable $f1, 128, $x1 :: (store (s64)) -; 64BIT-DAG: STFD renamable $f1, 136, $x1 :: (store (s64)) -; 64BIT-DAG: STFD renamable $f1, 144, $x1 :: (store (s64)) -; 64BIT-DAG: $f2 = COPY renamable $f1 -; 64BIT-DAG: $f3 = COPY renamable $f1 -; 64BIT-DAG: $f4 = COPY renamable $f1 -; 64BIT-DAG: $f5 = COPY renamable $f1 -; 64BIT-DAG: $f6 = COPY renamable $f1 -; 64BIT-DAG: $f7 = COPY renamable $f1 -; 64BIT-DAG: $f8 = COPY renamable $f1 -; 64BIT-DAG: $f9 = COPY renamable $f1 -; 64BIT-DAG: $f10 = COPY renamable $f1 -; 64BIT-DAG: $f11 = COPY renamable $f1 -; 64BIT-DAG: $f12 = COPY renamable $f1 -; 64BIT-DAG: $f13 = COPY renamable $f1 -; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit killed $f4, implicit killed $f5, implicit killed $f6, implicit killed $f7, implicit killed $f8, implicit killed $f9, implicit killed $f10, implicit killed $f11, implicit killed $f12, implicit killed $f13, implicit $x2, implicit-def $r1 -; 64BIT-NEXT: ADJCALLSTACKUP 152, 0, implicit-def dead $r1, implicit $r1 - -; ASM64PWR4: stdu 1, -160(1) -; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C2(2) -; ASM64PWR4-NEXT: std 0, 176(1) -; ASM64PWR4-NEXT: lfd 1, 0([[REG]]) -; ASM64PWR4-DAG: stfd 1, 112(1) -; ASM64PWR4-DAG: stfd 1, 120(1) -; ASM64PWR4-DAG: stfd 1, 128(1) -; ASM64PWR4-DAG: stfd 1, 136(1) -; ASM64PWR4-DAG: stfd 1, 144(1) -; ASM64PWR4-DAG: fmr 2, 1 -; ASM64PWR4-DAG: fmr 3, 1 -; ASM64PWR4-DAG: fmr 4, 1 -; ASM64PWR4-DAG: fmr 5, 1 -; ASM64PWR4-DAG: fmr 6, 1 -; ASM64PWR4-DAG: fmr 7, 1 -; ASM64PWR4-DAG: fmr 8, 1 -; ASM64PWR4-DAG: fmr 9, 1 -; ASM64PWR4-DAG: fmr 10, 1 -; ASM64PWR4-DAG: fmr 11, 1 -; ASM64PWR4-DAG: fmr 12, 1 -; ASM64PWR4-DAG: fmr 13, 1 -; ASM64PWR4-NEXT: bl .test_fpr_max -; ASM64PWR4-NEXT: nop -; ASM64PWR4-NEXT: addi 1, 1, 160 - define double @test_fpr_max(double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10, double %d11, double %d12, double %d13) { +; CHECKASM-LABEL: test_fpr_max: +; CHECKASM: # %bb.0: # %entry +; CHECKASM-NEXT: fadd 0, 1, 2 +; CHECKASM-NEXT: fadd 0, 0, 3 +; CHECKASM-NEXT: fadd 0, 0, 4 +; CHECKASM-NEXT: fadd 0, 0, 5 +; CHECKASM-NEXT: fadd 0, 0, 6 +; CHECKASM-NEXT: fadd 0, 0, 7 +; CHECKASM-NEXT: fadd 0, 0, 8 +; CHECKASM-NEXT: fadd 0, 0, 9 +; CHECKASM-NEXT: fadd 0, 0, 10 +; CHECKASM-NEXT: fadd 0, 0, 11 +; CHECKASM-NEXT: fadd 0, 0, 12 +; CHECKASM-NEXT: fadd 1, 0, 13 +; CHECKASM-NEXT: blr entry: %add = fadd double %d1, %d2 %add1 = fadd double %add, %d3 @@ -570,27 +584,42 @@ entry: ret double %add11 } -; CHECK-LABEL: name: test_fpr_max{{.*}} - -; CHECK: liveins: -; CHECK-NEXT: - { reg: '$f1', virtual-reg: '' } -; CHECK-NEXT: - { reg: '$f2', virtual-reg: '' } -; CHECK-NEXT: - { reg: '$f3', virtual-reg: '' } -; CHECK-NEXT: - { reg: '$f4', virtual-reg: '' } -; CHECK-NEXT: - { reg: '$f5', virtual-reg: '' } -; CHECK-NEXT: - { reg: '$f6', virtual-reg: '' } -; CHECK-NEXT: - { reg: '$f7', virtual-reg: '' } -; CHECK-NEXT: - { reg: '$f8', virtual-reg: '' } -; CHECK-NEXT: - { reg: '$f9', virtual-reg: '' } -; CHECK-NEXT: - { reg: '$f10', virtual-reg: '' } -; CHECK-NEXT: - { reg: '$f11', virtual-reg: '' } -; CHECK-NEXT: - { reg: '$f12', virtual-reg: '' } -; CHECK-NEXT: - { reg: '$f13', virtual-reg: '' } -; CHECK: body: | -; CHECK-NEXT: bb.0.entry: -; CHECK-NEXT: liveins: $f1, $f2, $f3, $f4, $f5, $f6, $f7, $f8, $f9, $f10, $f11, $f12, $f13 - define void @call_test_mix() { +; ASM32PWR4-LABEL: call_test_mix: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: mflr 0 +; ASM32PWR4-NEXT: stwu 1, -64(1) +; ASM32PWR4-NEXT: lwz 3, L..C1(2) # @f1 +; ASM32PWR4-NEXT: stw 0, 72(1) +; ASM32PWR4-NEXT: li 4, 1 +; ASM32PWR4-NEXT: li 7, 97 +; ASM32PWR4-NEXT: lfs 1, 0(3) +; ASM32PWR4-NEXT: lwz 3, L..C2(2) # @d1 +; ASM32PWR4-NEXT: lfd 2, 0(3) +; ASM32PWR4-NEXT: bl .test_mix +; ASM32PWR4-NEXT: nop +; ASM32PWR4-NEXT: addi 1, 1, 64 +; ASM32PWR4-NEXT: lwz 0, 8(1) +; ASM32PWR4-NEXT: mtlr 0 +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: call_test_mix: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: mflr 0 +; ASM64PWR4-NEXT: stdu 1, -112(1) +; ASM64PWR4-NEXT: ld 3, L..C1(2) # @f1 +; ASM64PWR4-NEXT: std 0, 128(1) +; ASM64PWR4-NEXT: li 4, 1 +; ASM64PWR4-NEXT: li 6, 97 +; ASM64PWR4-NEXT: lfs 1, 0(3) +; ASM64PWR4-NEXT: ld 3, L..C2(2) # @d1 +; ASM64PWR4-NEXT: lfd 2, 0(3) +; ASM64PWR4-NEXT: bl .test_mix +; ASM64PWR4-NEXT: nop +; ASM64PWR4-NEXT: addi 1, 1, 112 +; ASM64PWR4-NEXT: ld 0, 16(1) +; ASM64PWR4-NEXT: mtlr 0 +; ASM64PWR4-NEXT: blr entry: %0 = load float, ptr @f1, align 4 %1 = load double, ptr @d1, align 8 @@ -598,29 +627,46 @@ entry: ret void } -; CHECK-LABEL: name: call_test_mix{{.*}} - -; 32BIT: renamable $r[[REG1:[0-9]+]] = LWZtoc @f1, $r2 :: (load (s32) from got) -; 32BIT-NEXT: renamable $r[[REG2:[0-9]+]] = LWZtoc @d1, $r2 :: (load (s32) from got) -; 32BIT-NEXT: renamable $f1 = LFS 0, killed renamable $r[[REG1]] :: (dereferenceable load (s32) from @f1) -; 32BIT-NEXT: renamable $f2 = LFD 0, killed renamable $r[[REG2]] :: (dereferenceable load (s64) from @d1) -; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 -; 32BIT-NEXT: $r4 = LI 1 -; 32BIT-NEXT: $r7 = LI 97 -; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit $r4, implicit $f2, implicit killed $r7, implicit $r2, implicit-def $r1 -; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 - -; 64BIT: renamable $x[[REG1:[0-9]+]] = LDtoc @f1, $x2 :: (load (s64) from got) -; 64BIT-NEXT: renamable $x[[REG2:[0-9]+]] = LDtoc @d1, $x2 :: (load (s64) from got) -; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x[[REG1]] :: (dereferenceable load (s32) from @f1) -; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x[[REG2]] :: (dereferenceable load (s64) from @d1) -; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 -; 64BIT-NEXT: $x4 = LI8 1 -; 64BIT-NEXT: $x6 = LI8 97 -; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $x4, implicit $f2, implicit killed $x6, implicit $x2, implicit-def $r1 -; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 - define i32 @test_mix(float %f, i32 signext %i, double %d, i8 signext %c) { +; ASM32PWR4-LABEL: test_mix: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: lis 3, 17200 +; ASM32PWR4-NEXT: fadd 1, 1, 2 +; ASM32PWR4-NEXT: stw 3, -16(1) +; ASM32PWR4-NEXT: lwz 3, L..C3(2) # %const.0 +; ASM32PWR4-NEXT: frsp 1, 1 +; ASM32PWR4-NEXT: lfs 0, 0(3) +; ASM32PWR4-NEXT: clrlwi 3, 7, 24 +; ASM32PWR4-NEXT: add 3, 4, 3 +; ASM32PWR4-NEXT: xoris 3, 3, 32768 +; ASM32PWR4-NEXT: stw 3, -12(1) +; ASM32PWR4-NEXT: addi 3, 1, -4 +; ASM32PWR4-NEXT: lfd 2, -16(1) +; ASM32PWR4-NEXT: fsub 0, 2, 0 +; ASM32PWR4-NEXT: frsp 0, 0 +; ASM32PWR4-NEXT: fadds 0, 0, 1 +; ASM32PWR4-NEXT: fctiwz 0, 0 +; ASM32PWR4-NEXT: stfiwx 0, 0, 3 +; ASM32PWR4-NEXT: lwz 3, -4(1) +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: test_mix: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: clrlwi 5, 6, 24 +; ASM64PWR4-NEXT: fadd 0, 1, 2 +; ASM64PWR4-NEXT: addi 3, 1, -4 +; ASM64PWR4-NEXT: frsp 0, 0 +; ASM64PWR4-NEXT: add 4, 4, 5 +; ASM64PWR4-NEXT: extsw 4, 4 +; ASM64PWR4-NEXT: std 4, -16(1) +; ASM64PWR4-NEXT: lfd 1, -16(1) +; ASM64PWR4-NEXT: fcfid 1, 1 +; ASM64PWR4-NEXT: frsp 1, 1 +; ASM64PWR4-NEXT: fadds 0, 1, 0 +; ASM64PWR4-NEXT: fctiwz 0, 0 +; ASM64PWR4-NEXT: stfiwx 0, 0, 3 +; ASM64PWR4-NEXT: lwz 3, -4(1) +; ASM64PWR4-NEXT: blr entry: %conv = fpext float %f to double %add = fadd double %conv, %d @@ -633,28 +679,27 @@ entry: ret i32 %conv6 } -; CHECK-LABEL: name: test_mix{{.*}} - -; 32BIT: liveins: -; 32BIT-NEXT: - { reg: '$f1', virtual-reg: '' } -; 32BIT-NEXT: - { reg: '$r4', virtual-reg: '' } -; 32BIT-NEXT: - { reg: '$f2', virtual-reg: '' } -; 32BIT-NEXT: - { reg: '$r7', virtual-reg: '' } -; 32BIT: body: | -; 32BIT-NEXT: bb.0.entry: -; 32BIT-NEXT: liveins: $f1, $f2, $r4, $r7 - -; 64BIT: liveins: -; 64BIT-NEXT: - { reg: '$f1', virtual-reg: '' } -; 64BIT-NEXT: - { reg: '$x4', virtual-reg: '' } -; 64BIT-NEXT: - { reg: '$f2', virtual-reg: '' } -; 64BIT-NEXT: - { reg: '$x6', virtual-reg: '' } -; 64BIT: body: | -; 64BIT-NEXT: bb.0.entry: -; 64BIT-NEXT: liveins: $f1, $f2, $x4, $x6 - - define i64 @callee_mixed_ints(i32 %a, i8 signext %b, i32 %c, i16 signext %d, i64 %e) { +; ASM32PWR4-LABEL: callee_mixed_ints: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: clrlwi 4, 4, 24 +; ASM32PWR4-NEXT: add 3, 3, 4 +; ASM32PWR4-NEXT: add 3, 3, 5 +; ASM32PWR4-NEXT: add 3, 3, 6 +; ASM32PWR4-NEXT: srawi 5, 3, 31 +; ASM32PWR4-NEXT: addc 4, 3, 8 +; ASM32PWR4-NEXT: adde 3, 5, 7 +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: callee_mixed_ints: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: clrlwi 4, 4, 24 +; ASM64PWR4-NEXT: add 3, 3, 4 +; ASM64PWR4-NEXT: add 3, 3, 5 +; ASM64PWR4-NEXT: add 3, 3, 6 +; ASM64PWR4-NEXT: extsw 3, 3 +; ASM64PWR4-NEXT: add 3, 3, 7 +; ASM64PWR4-NEXT: blr entry: %conv = zext i8 %b to i32 %add = add nsw i32 %a, %conv @@ -666,30 +711,50 @@ entry: ret i64 %add5 } -; CHECK-LABEL: name: callee_mixed_ints - -; 32BIT: liveins: -; 32BIT-NEXT: - { reg: '$r3', virtual-reg: '' } -; 32BIT-NEXT: - { reg: '$r4', virtual-reg: '' } -; 32BIT-NEXT: - { reg: '$r5', virtual-reg: '' } -; 32BIT-NEXT: - { reg: '$r6', virtual-reg: '' } -; 32BIT-NEXT: - { reg: '$r7', virtual-reg: '' } -; 32BIT-NEXT: - { reg: '$r8', virtual-reg: '' } -; 32BIT: body: | -; 32BIT-NEXT: bb.0.entry: -; 32BIT-NEXT: liveins: $r3, $r4, $r5, $r6, $r7, $r8 - -; 64BIT: liveins: -; 64BIT-NEXT: - { reg: '$x3', virtual-reg: '' } -; 64BIT-NEXT: - { reg: '$x4', virtual-reg: '' } -; 64BIT-NEXT: - { reg: '$x5', virtual-reg: '' } -; 64BIT-NEXT: - { reg: '$x6', virtual-reg: '' } -; 64BIT-NEXT: - { reg: '$x7', virtual-reg: '' } -; 64BIT: body: | -; 64BIT-NEXT: bb.0.entry: -; 64BIT-NEXT: liveins: $x3, $x4, $x5, $x6, $x7 - define void @call_test_vararg() { +; ASM32PWR4-LABEL: call_test_vararg: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: mflr 0 +; ASM32PWR4-NEXT: stwu 1, -80(1) +; ASM32PWR4-NEXT: lwz 3, L..C1(2) # @f1 +; ASM32PWR4-NEXT: stw 0, 88(1) +; ASM32PWR4-NEXT: lfs 1, 0(3) +; ASM32PWR4-NEXT: lwz 3, L..C2(2) # @d1 +; ASM32PWR4-NEXT: stfd 1, 64(1) +; ASM32PWR4-NEXT: lfd 2, 0(3) +; ASM32PWR4-NEXT: li 3, 42 +; ASM32PWR4-NEXT: stfd 2, 72(1) +; ASM32PWR4-NEXT: lwz 4, 64(1) +; ASM32PWR4-NEXT: lwz 5, 68(1) +; ASM32PWR4-NEXT: lwz 6, 72(1) +; ASM32PWR4-NEXT: lwz 7, 76(1) +; ASM32PWR4-NEXT: bl .test_vararg[PR] +; ASM32PWR4-NEXT: nop +; ASM32PWR4-NEXT: addi 1, 1, 80 +; ASM32PWR4-NEXT: lwz 0, 8(1) +; ASM32PWR4-NEXT: mtlr 0 +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: call_test_vararg: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: mflr 0 +; ASM64PWR4-NEXT: stdu 1, -128(1) +; ASM64PWR4-NEXT: ld 3, L..C1(2) # @f1 +; ASM64PWR4-NEXT: std 0, 144(1) +; ASM64PWR4-NEXT: lfs 1, 0(3) +; ASM64PWR4-NEXT: ld 3, L..C2(2) # @d1 +; ASM64PWR4-NEXT: stfd 1, 112(1) +; ASM64PWR4-NEXT: lfd 2, 0(3) +; ASM64PWR4-NEXT: li 3, 42 +; ASM64PWR4-NEXT: stfd 2, 120(1) +; ASM64PWR4-NEXT: ld 4, 112(1) +; ASM64PWR4-NEXT: ld 5, 120(1) +; ASM64PWR4-NEXT: bl .test_vararg[PR] +; ASM64PWR4-NEXT: nop +; ASM64PWR4-NEXT: addi 1, 1, 128 +; ASM64PWR4-NEXT: ld 0, 16(1) +; ASM64PWR4-NEXT: mtlr 0 +; ASM64PWR4-NEXT: blr entry: %0 = load float, ptr @f1, align 4 %conv = fpext float %0 to double @@ -700,69 +765,52 @@ entry: declare void @test_vararg(i32, ...) -; CHECK-LABEL: name: call_test_vararg - -; 32BIT: renamable $r[[REG:[0-9]+]] = LWZtoc @f1, $r2 :: (load (s32) from got) -; 32BIT-NEXT: renamable $f1 = LFS 0, killed renamable $r[[REG]] :: (dereferenceable load (s32) from @f1) -; 32BIT-NEXT: renamable $r[[REG:[0-9]+]] = LWZtoc @d1, $r2 :: (load (s32) from got) -; 32BIT-NEXT: STFD renamable $f1, 0, %stack.[[SLOT1:[0-9]+]] :: (store (s64) into %stack.[[SLOT1]]) -; 32BIT-NEXT: renamable $r4 = LWZ 0, %stack.[[SLOT1]] :: (load (s32) from %stack.[[SLOT1]], align 8) -; 32BIT-NEXT: renamable $f2 = LFD 0, killed renamable $r[[REG]] :: (dereferenceable load (s64) from @d1) -; 32BIT-NEXT: renamable $r5 = LWZ 4, %stack.[[SLOT1]] :: (load (s32) from %stack.[[SLOT1]] + 4) -; 32BIT-NEXT: STFD renamable $f2, 0, %stack.[[SLOT2:[0-9]+]] :: (store (s64) into %stack.[[SLOT2]]) -; 32BIT-NEXT: renamable $r6 = LWZ 0, %stack.[[SLOT2]] :: (load (s32) from %stack.[[SLOT2]], align 8) -; 32BIT-NEXT: renamable $r7 = LWZ 4, %stack.[[SLOT2]] :: (load (s32) from %stack.[[SLOT2]] + 4) -; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 -; 32BIT-NEXT: $r3 = LI 42 -; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit $f2, implicit $r6, implicit $r7, implicit $r2, implicit-def $r1 -; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 - -; CHECKASM-LABEL: .call_test_vararg: - -; ASM32PWR4: stwu 1, -80(1) -; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C1(2) -; ASM32PWR4-NEXT: stw 0, 88(1) -; ASM32PWR4-NEXT: lfs 1, 0([[REG]]) -; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C2(2) -; ASM32PWR4-NEXT: stfd 1, 64(1) -; ASM32PWR4-NEXT: lfd 2, 0([[REG]]) -; ASM32PWR4-NEXT: li 3, 42 -; ASM32PWR4-NEXT: stfd 2, 72(1) -; ASM32PWR4-DAG: lwz 4, 64(1) -; ASM32PWR4-DAG: lwz 5, 68(1) -; ASM32PWR4-DAG: lwz 6, 72(1) -; ASM32PWR4-DAG: lwz 7, 76(1) -; ASM32PWR4-NEXT: bl .test_vararg[PR] -; ASM32PWR4-NEXT: nop - -; 64BIT: renamable $x[[REG:[0-9]+]] = LDtoc @f1, $x2 :: (load (s64) from got) -; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x[[REG]] :: (dereferenceable load (s32) from @f1) -; 64BIT-NEXT: renamable $x[[REG:[0-9]+]] = LDtoc @d1, $x2 :: (load (s64) from got) -; 64BIT-NEXT: STFD renamable $f1, 0, %stack.[[SLOT1:[0-9]+]] :: (store (s64) into %stack.[[SLOT1]]) -; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x[[REG]] :: (dereferenceable load (s64) from @d1) -; 64BIT-NEXT: renamable $x4 = LD 0, %stack.[[SLOT1]] :: (load (s64) from %stack.[[SLOT1]]) -; 64BIT-NEXT: STFD renamable $f2, 0, %stack.[[SLOT2:[0-9]+]] :: (store (s64) into %stack.[[SLOT2]]) -; 64BIT-NEXT: renamable $x5 = LD 0, %stack.[[SLOT2]] :: (load (s64) from %stack.[[SLOT2]]) -; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 -; 64BIT-NEXT: $x3 = LI8 42 -; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $f2, implicit $x5, implicit $x2, implicit-def $r1 -; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 - -; ASM64PWR4: stdu 1, -128(1) -; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2) -; ASM64PWR4-NEXT: std 0, 144(1) -; ASM64PWR4-NEXT: lfs 1, 0([[REG]]) -; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C2(2) -; ASM64PWR4-NEXT: stfd 1, 112(1) -; ASM64PWR4-NEXT: lfd 2, 0([[REG]]) -; ASM64PWR4-NEXT: li 3, 42 -; ASM64PWR4-NEXT: stfd 2, 120(1) -; ASM64PWR4-NEXT: ld 4, 112(1) -; ASM64PWR4-NEXT: ld 5, 120(1) -; ASM64PWR4-NEXT: bl .test_vararg[PR] -; ASM64PWR4-NEXT: nop - define void @call_test_vararg2() { +; ASM32PWR4-LABEL: call_test_vararg2: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: mflr 0 +; ASM32PWR4-NEXT: stwu 1, -80(1) +; ASM32PWR4-NEXT: lwz 3, L..C1(2) # @f1 +; ASM32PWR4-NEXT: stw 0, 88(1) +; ASM32PWR4-NEXT: li 6, 42 +; ASM32PWR4-NEXT: lfs 1, 0(3) +; ASM32PWR4-NEXT: lwz 3, L..C2(2) # @d1 +; ASM32PWR4-NEXT: stfd 1, 64(1) +; ASM32PWR4-NEXT: lfd 2, 0(3) +; ASM32PWR4-NEXT: li 3, 42 +; ASM32PWR4-NEXT: stfd 2, 72(1) +; ASM32PWR4-NEXT: lwz 4, 64(1) +; ASM32PWR4-NEXT: lwz 5, 68(1) +; ASM32PWR4-NEXT: lwz 7, 72(1) +; ASM32PWR4-NEXT: lwz 8, 76(1) +; ASM32PWR4-NEXT: bl .test_vararg[PR] +; ASM32PWR4-NEXT: nop +; ASM32PWR4-NEXT: addi 1, 1, 80 +; ASM32PWR4-NEXT: lwz 0, 8(1) +; ASM32PWR4-NEXT: mtlr 0 +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: call_test_vararg2: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: mflr 0 +; ASM64PWR4-NEXT: stdu 1, -128(1) +; ASM64PWR4-NEXT: ld 3, L..C1(2) # @f1 +; ASM64PWR4-NEXT: std 0, 144(1) +; ASM64PWR4-NEXT: li 5, 42 +; ASM64PWR4-NEXT: lfs 1, 0(3) +; ASM64PWR4-NEXT: ld 3, L..C2(2) # @d1 +; ASM64PWR4-NEXT: stfd 1, 112(1) +; ASM64PWR4-NEXT: lfd 2, 0(3) +; ASM64PWR4-NEXT: li 3, 42 +; ASM64PWR4-NEXT: stfd 2, 120(1) +; ASM64PWR4-NEXT: ld 4, 112(1) +; ASM64PWR4-NEXT: ld 6, 120(1) +; ASM64PWR4-NEXT: bl .test_vararg[PR] +; ASM64PWR4-NEXT: nop +; ASM64PWR4-NEXT: addi 1, 1, 128 +; ASM64PWR4-NEXT: ld 0, 16(1) +; ASM64PWR4-NEXT: mtlr 0 +; ASM64PWR4-NEXT: blr entry: %0 = load float, ptr @f1, align 4 %conv = fpext float %0 to double @@ -771,71 +819,53 @@ entry: ret void } -; CHECK-LABEL: name: call_test_vararg2 - -; 32BIT: renamable $r[[REG:[0-9]+]] = LWZtoc @f1, $r2 :: (load (s32) from got) -; 32BIT-NEXT: renamable $f1 = LFS 0, killed renamable $r[[REG]] :: (dereferenceable load (s32) from @f1) -; 32BIT-NEXT: renamable $r[[REG:[0-9]+]] = LWZtoc @d1, $r2 :: (load (s32) from got) -; 32BIT-NEXT: STFD renamable $f1, 0, %stack.[[SLOT1:[0-9]+]] :: (store (s64) into %stack.[[SLOT1]]) -; 32BIT-NEXT: renamable $r4 = LWZ 0, %stack.[[SLOT1]] :: (load (s32) from %stack.[[SLOT1]], align 8) -; 32BIT-NEXT: renamable $f2 = LFD 0, killed renamable $r[[REG]] :: (dereferenceable load (s64) from @d1) -; 32BIT-NEXT: renamable $r5 = LWZ 4, %stack.[[SLOT1]] :: (load (s32) from %stack.[[SLOT1]] + 4) -; 32BIT-NEXT: STFD renamable $f2, 0, %stack.[[SLOT2:[0-9]+]] :: (store (s64) into %stack.[[SLOT2]]) -; 32BIT-NEXT: renamable $r7 = LWZ 0, %stack.[[SLOT2]] :: (load (s32) from %stack.[[SLOT2]], align 8) -; 32BIT-NEXT: renamable $r8 = LWZ 4, %stack.[[SLOT2]] :: (load (s32) from %stack.[[SLOT2]] + 4) -; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 -; 32BIT-NEXT: $r3 = LI 42 -; 32BIT-NEXT: $r6 = LI 42 -; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit killed $r6, implicit $f2, implicit $r7, implicit $r8, implicit $r2, implicit-def $r1 -; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 - -; ASM32PWR4: stwu 1, -80(1) -; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C1(2) -; ASM32PWR4-NEXT: stw 0, 88(1) -; ASM32PWR4-NEXT: li 6, 42 -; ASM32PWR4-NEXT: lfs 1, 0([[REG]]) -; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C2(2) -; ASM32PWR4-NEXT: stfd 1, 64(1) -; ASM32PWR4-NEXT: lfd 2, 0([[REG]]) -; ASM32PWR4-NEXT: li 3, 42 -; ASM32PWR4-NEXT: stfd 2, 72(1) -; ASM32PWR4-DAG: lwz 4, 64(1) -; ASM32PWR4-DAG: lwz 5, 68(1) -; ASM32PWR4-DAG: lwz 7, 72(1) -; ASM32PWR4-DAG: lwz 8, 76(1) -; ASM32PWR4-NEXT: bl .test_vararg[PR] -; ASM32PWR4-NEXT: nop - -; 64BIT: renamable $x[[REG:[0-9]+]] = LDtoc @f1, $x2 :: (load (s64) from got) -; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x[[REG]] :: (dereferenceable load (s32) from @f1) -; 64BIT-NEXT: renamable $x[[REG:[0-9]+]] = LDtoc @d1, $x2 :: (load (s64) from got) -; 64BIT-NEXT: STFD renamable $f1, 0, %stack.[[SLOT1:[0-9]+]] :: (store (s64) into %stack.[[SLOT1]]) -; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x[[REG]] :: (dereferenceable load (s64) from @d1) -; 64BIT-NEXT: renamable $x4 = LD 0, %stack.[[SLOT1]] :: (load (s64) from %stack.[[SLOT1]]) -; 64BIT-NEXT: STFD renamable $f2, 0, %stack.[[SLOT2:[0-9]+]] :: (store (s64) into %stack.[[SLOT2]]) -; 64BIT-NEXT: renamable $x6 = LD 0, %stack.[[SLOT2]] :: (load (s64) from %stack.[[SLOT2]]) -; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 -; 64BIT-NEXT: $x3 = LI8 42 -; 64BIT-NEXT: $x5 = LI8 42 -; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1 -; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 - -; ASM64PWR4: stdu 1, -128(1) -; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2) -; ASM64PWR4-NEXT: std 0, 144(1) -; ASM64PWR4-NEXT: li 5, 42 -; ASM64PWR4-NEXT: lfs 1, 0([[REG]]) -; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C2(2) -; ASM64PWR4-NEXT: stfd 1, 112(1) -; ASM64PWR4-NEXT: lfd 2, 0([[REG]]) -; ASM64PWR4-NEXT: li 3, 42 -; ASM64PWR4-NEXT: stfd 2, 120(1) -; ASM64PWR4-NEXT: ld 4, 112(1) -; ASM64PWR4-NEXT: ld 6, 120(1) -; ASM64PWR4-NEXT: bl .test_vararg[PR] -; ASM64PWR4-NEXT: nop - define void @call_test_vararg3() { +; ASM32PWR4-LABEL: call_test_vararg3: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: mflr 0 +; ASM32PWR4-NEXT: stwu 1, -80(1) +; ASM32PWR4-NEXT: lwz 3, L..C1(2) # @f1 +; ASM32PWR4-NEXT: stw 0, 88(1) +; ASM32PWR4-NEXT: li 6, 0 +; ASM32PWR4-NEXT: li 7, 42 +; ASM32PWR4-NEXT: lfs 1, 0(3) +; ASM32PWR4-NEXT: lwz 3, L..C2(2) # @d1 +; ASM32PWR4-NEXT: stfd 1, 64(1) +; ASM32PWR4-NEXT: lfd 2, 0(3) +; ASM32PWR4-NEXT: li 3, 42 +; ASM32PWR4-NEXT: stfd 2, 72(1) +; ASM32PWR4-NEXT: lwz 4, 64(1) +; ASM32PWR4-NEXT: lwz 5, 68(1) +; ASM32PWR4-NEXT: lwz 8, 72(1) +; ASM32PWR4-NEXT: lwz 9, 76(1) +; ASM32PWR4-NEXT: bl .test_vararg[PR] +; ASM32PWR4-NEXT: nop +; ASM32PWR4-NEXT: addi 1, 1, 80 +; ASM32PWR4-NEXT: lwz 0, 8(1) +; ASM32PWR4-NEXT: mtlr 0 +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: call_test_vararg3: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: mflr 0 +; ASM64PWR4-NEXT: stdu 1, -128(1) +; ASM64PWR4-NEXT: ld 3, L..C1(2) # @f1 +; ASM64PWR4-NEXT: std 0, 144(1) +; ASM64PWR4-NEXT: li 5, 42 +; ASM64PWR4-NEXT: lfs 1, 0(3) +; ASM64PWR4-NEXT: ld 3, L..C2(2) # @d1 +; ASM64PWR4-NEXT: stfd 1, 112(1) +; ASM64PWR4-NEXT: lfd 2, 0(3) +; ASM64PWR4-NEXT: li 3, 42 +; ASM64PWR4-NEXT: stfd 2, 120(1) +; ASM64PWR4-NEXT: ld 4, 112(1) +; ASM64PWR4-NEXT: ld 6, 120(1) +; ASM64PWR4-NEXT: bl .test_vararg[PR] +; ASM64PWR4-NEXT: nop +; ASM64PWR4-NEXT: addi 1, 1, 128 +; ASM64PWR4-NEXT: ld 0, 16(1) +; ASM64PWR4-NEXT: mtlr 0 +; ASM64PWR4-NEXT: blr entry: %0 = load float, ptr @f1, align 4 %conv = fpext float %0 to double @@ -844,118 +874,46 @@ entry: ret void } -; CHECK-LABEL: name: call_test_vararg3 - -; 32BIT: renamable $r[[REG:[0-9]+]] = LWZtoc @f1, $r2 :: (load (s32) from got) -; 32BIT-NEXT: renamable $f1 = LFS 0, killed renamable $r[[REG]] :: (dereferenceable load (s32) from @f1) -; 32BIT-NEXT: renamable $r[[REG:[0-9]+]] = LWZtoc @d1, $r2 :: (load (s32) from got) -; 32BIT-NEXT: STFD renamable $f1, 0, %stack.[[SLOT1:[0-9]+]] :: (store (s64) into %stack.[[SLOT1]]) -; 32BIT-NEXT: renamable $r4 = LWZ 0, %stack.[[SLOT1]] :: (load (s32) from %stack.[[SLOT1]], align 8) -; 32BIT-NEXT: renamable $f2 = LFD 0, killed renamable $r[[REG]] :: (dereferenceable load (s64) from @d1) -; 32BIT-NEXT: renamable $r5 = LWZ 4, %stack.[[SLOT1]] :: (load (s32) from %stack.[[SLOT1]] + 4) -; 32BIT-NEXT: STFD renamable $f2, 0, %stack.[[SLOT2:[0-9]+]] :: (store (s64) into %stack.[[SLOT2]]) -; 32BIT-NEXT: renamable $r8 = LWZ 0, %stack.[[SLOT2]] :: (load (s32) from %stack.[[SLOT2]], align 8) -; 32BIT-NEXT: renamable $r9 = LWZ 4, %stack.[[SLOT2]] :: (load (s32) from %stack.[[SLOT2]] + 4) -; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 -; 32BIT-NEXT: $r3 = LI 42 -; 32BIT-NEXT: $r6 = LI 0 -; 32BIT-NEXT: $r7 = LI 42 -; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit killed $r6, implicit killed $r7, implicit $f2, implicit $r8, implicit $r9, implicit $r2, implicit-def $r1 -; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 - -; ASM32PWR4: stwu 1, -80(1) -; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C1(2) -; ASM32PWR4-DAG: li 6, 0 -; ASM32PWR4-DAG: li 7, 42 -; ASM32PWR4-NEXT: lfs 1, 0([[REG]]) -; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C2(2) -; ASM32PWR4-NEXT: stfd 1, 64(1) -; ASM32PWR4-NEXT: lfd 2, 0([[REG]]) -; ASM32PWR4-NEXT: li 3, 42 -; ASM32PWR4-NEXT: stfd 2, 72(1) -; ASM32PWR4-DAG: lwz 4, 64(1) -; ASM32PWR4-DAG: lwz 5, 68(1) -; ASM32PWR4-DAG: lwz 8, 72(1) -; ASM32PWR4-DAG: lwz 9, 76(1) -; ASM32PWR4-NEXT: bl .test_vararg[PR] -; ASM32PWR4-NEXT: nop - -; 64BIT: renamable $x[[REG:[0-9]+]] = LDtoc @f1, $x2 :: (load (s64) from got) -; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x[[REG]] :: (dereferenceable load (s32) from @f1) -; 64BIT-NEXT: renamable $x[[REG:[0-9]+]] = LDtoc @d1, $x2 :: (load (s64) from got) -; 64BIT-NEXT: STFD renamable $f1, 0, %stack.[[SLOT1:[0-9]+]] :: (store (s64) into %stack.[[SLOT1]]) -; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x[[REG]] :: (dereferenceable load (s64) from @d1) -; 64BIT-NEXT: renamable $x4 = LD 0, %stack.[[SLOT1]] :: (load (s64) from %stack.[[SLOT1]]) -; 64BIT-NEXT: STFD renamable $f2, 0, %stack.[[SLOT2:[0-9]+]] :: (store (s64) into %stack.[[SLOT2]]) -; 64BIT-NEXT: renamable $x6 = LD 0, %stack.[[SLOT2]] :: (load (s64) from %stack.[[SLOT2]]) -; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 -; 64BIT-NEXT: $x3 = LI8 42 -; 64BIT-NEXT: $x5 = LI8 42 -; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1 -; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 - -; ASM64PWR4: stdu 1, -128(1) -; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2) -; ASM64PWR4-NEXT: std 0, 144(1) -; ASM64PWR4-NEXT: li 5, 42 -; ASM64PWR4-NEXT: lfs 1, 0([[REG]]) -; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C2(2) -; ASM64PWR4-NEXT: stfd 1, 112(1) -; ASM64PWR4-NEXT: lfd 2, 0([[REG]]) -; ASM64PWR4-NEXT: li 3, 42 -; ASM64PWR4-NEXT: stfd 2, 120(1) -; ASM64PWR4-DAG: ld 4, 112(1) -; ASM64PWR4-DAG: ld 6, 120(1) -; ASM64PWR4-NEXT: bl .test_vararg[PR] -; ASM64PWR4-NEXT: nop - define void @call_test_vararg4() { +; ASM32PWR4-LABEL: call_test_vararg4: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: mflr 0 +; ASM32PWR4-NEXT: stwu 1, -64(1) +; ASM32PWR4-NEXT: lwz 3, L..C1(2) # @f1 +; ASM32PWR4-NEXT: stw 0, 72(1) +; ASM32PWR4-NEXT: lfs 1, 0(3) +; ASM32PWR4-NEXT: li 3, 42 +; ASM32PWR4-NEXT: stfs 1, 60(1) +; ASM32PWR4-NEXT: lwz 4, 60(1) +; ASM32PWR4-NEXT: bl .test_vararg[PR] +; ASM32PWR4-NEXT: nop +; ASM32PWR4-NEXT: addi 1, 1, 64 +; ASM32PWR4-NEXT: lwz 0, 8(1) +; ASM32PWR4-NEXT: mtlr 0 +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: call_test_vararg4: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: mflr 0 +; ASM64PWR4-NEXT: stdu 1, -128(1) +; ASM64PWR4-NEXT: ld 3, L..C1(2) # @f1 +; ASM64PWR4-NEXT: std 0, 144(1) +; ASM64PWR4-NEXT: lfs 1, 0(3) +; ASM64PWR4-NEXT: li 3, 42 +; ASM64PWR4-NEXT: stfs 1, 124(1) +; ASM64PWR4-NEXT: lwz 4, 124(1) +; ASM64PWR4-NEXT: bl .test_vararg[PR] +; ASM64PWR4-NEXT: nop +; ASM64PWR4-NEXT: addi 1, 1, 128 +; ASM64PWR4-NEXT: ld 0, 16(1) +; ASM64PWR4-NEXT: mtlr 0 +; ASM64PWR4-NEXT: blr entry: %0 = load float, ptr @f1, align 4 call void (i32, ...) @test_vararg(i32 42, float %0) ret void } -; CHECK-LABEL: name: call_test_vararg4 - -; 32BIT: renamable $r[[REG:[0-9]+]] = LWZtoc @f1, $r2 :: (load (s32) from got) -; 32BIT-NEXT: renamable $f1 = LFS 0, killed renamable $r[[REG]] :: (dereferenceable load (s32) from @f1) -; 32BIT-NEXT: STFS renamable $f1, 0, %stack.[[SLOT:[0-9]+]] :: (store (s32) into %stack.[[SLOT]]) -; 32BIT-NEXT: renamable $r4 = LWZ 0, %stack.[[SLOT]] :: (load (s32) from %stack.[[SLOT]]) -; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 -; 32BIT-NEXT: $r3 = LI 42 -; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r2, implicit-def $r1 -; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 - -; ASM32PWR4: stwu 1, -64(1) -; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C1(2) -; ASM32PWR4-NEXT: stw 0, 72(1) -; ASM32PWR4-NEXT: lfs 1, 0([[REG]]) -; ASM32PWR4-NEXT: li 3, 42 -; ASM32PWR4-NEXT: stfs 1, 60(1) -; ASM32PWR4-NEXT: lwz 4, 60(1) -; ASM32PWR4-NEXT: bl .test_vararg[PR] -; ASM32PWR4-NEXT: nop - -; 64BIT: renamable $x[[REG:[0-9]+]] = LDtoc @f1, $x2 :: (load (s64) from got) -; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x[[REG]] :: (dereferenceable load (s32) from @f1) -; 64BIT-NEXT: STFS renamable $f1, 0, %stack.[[SLOT:[0-9]+]] :: (store (s32) into %stack.[[SLOT]]) -; 64BIT-NEXT: renamable $x4 = LWZ8 0, %stack.[[SLOT]] :: (load (s32) from %stack.[[SLOT]]) -; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 -; 64BIT-NEXT: $x3 = LI8 42 -; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $x2, implicit-def $r1 -; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 - -; ASM64PWR4: stdu 1, -128(1) -; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2) -; ASM64PWR4-NEXT: std 0, 144(1) -; ASM64PWR4-NEXT: lfs 1, 0([[REG]]) -; ASM64PWR4-NEXT: li 3, 42 -; ASM64PWR4-NEXT: stfs 1, 124(1) -; ASM64PWR4-NEXT: lwz 4, 124(1) -; ASM64PWR4-NEXT: bl .test_vararg[PR] -; ASM64PWR4-NEXT: nop - @c = common global i8 0, align 1 @si = common global i16 0, align 2 @i = common global i32 0, align 4 @@ -965,6 +923,73 @@ entry: ; Basic saving of integral type arguments to the parameter save area. define void @call_test_stackarg_int() { +; ASM32PWR4-LABEL: call_test_stackarg_int: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: mflr 0 +; ASM32PWR4-NEXT: stwu 1, -80(1) +; ASM32PWR4-NEXT: lwz 3, L..C4(2) # @si +; ASM32PWR4-NEXT: stw 0, 88(1) +; ASM32PWR4-NEXT: lwz 4, L..C5(2) # @i +; ASM32PWR4-NEXT: li 6, 4 +; ASM32PWR4-NEXT: li 8, 6 +; ASM32PWR4-NEXT: li 9, 7 +; ASM32PWR4-NEXT: li 10, 8 +; ASM32PWR4-NEXT: lha 7, 0(3) +; ASM32PWR4-NEXT: lwz 3, L..C6(2) # @c +; ASM32PWR4-NEXT: lbz 11, 0(3) +; ASM32PWR4-NEXT: lwz 3, L..C7(2) # @lli +; ASM32PWR4-NEXT: lwz 5, 0(4) +; ASM32PWR4-NEXT: lwz 4, 0(3) +; ASM32PWR4-NEXT: lwz 3, 4(3) +; ASM32PWR4-NEXT: stw 5, 76(1) +; ASM32PWR4-NEXT: stw 3, 72(1) +; ASM32PWR4-NEXT: li 3, 1 +; ASM32PWR4-NEXT: stw 4, 68(1) +; ASM32PWR4-NEXT: li 4, 2 +; ASM32PWR4-NEXT: stw 5, 64(1) +; ASM32PWR4-NEXT: li 5, 3 +; ASM32PWR4-NEXT: stw 7, 60(1) +; ASM32PWR4-NEXT: li 7, 5 +; ASM32PWR4-NEXT: stw 11, 56(1) +; ASM32PWR4-NEXT: bl .test_stackarg_int[PR] +; ASM32PWR4-NEXT: nop +; ASM32PWR4-NEXT: addi 1, 1, 80 +; ASM32PWR4-NEXT: lwz 0, 8(1) +; ASM32PWR4-NEXT: mtlr 0 +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: call_test_stackarg_int: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: mflr 0 +; ASM64PWR4-NEXT: stdu 1, -160(1) +; ASM64PWR4-NEXT: ld 3, L..C3(2) # @si +; ASM64PWR4-NEXT: std 0, 176(1) +; ASM64PWR4-NEXT: ld 4, L..C4(2) # @i +; ASM64PWR4-NEXT: li 6, 4 +; ASM64PWR4-NEXT: li 8, 6 +; ASM64PWR4-NEXT: li 9, 7 +; ASM64PWR4-NEXT: li 10, 8 +; ASM64PWR4-NEXT: lha 7, 0(3) +; ASM64PWR4-NEXT: ld 3, L..C5(2) # @c +; ASM64PWR4-NEXT: lbz 11, 0(3) +; ASM64PWR4-NEXT: ld 3, L..C6(2) # @lli +; ASM64PWR4-NEXT: lwz 5, 0(4) +; ASM64PWR4-NEXT: li 4, 2 +; ASM64PWR4-NEXT: ld 3, 0(3) +; ASM64PWR4-NEXT: std 5, 144(1) +; ASM64PWR4-NEXT: std 3, 136(1) +; ASM64PWR4-NEXT: li 3, 1 +; ASM64PWR4-NEXT: std 5, 128(1) +; ASM64PWR4-NEXT: li 5, 3 +; ASM64PWR4-NEXT: std 7, 120(1) +; ASM64PWR4-NEXT: li 7, 5 +; ASM64PWR4-NEXT: std 11, 112(1) +; ASM64PWR4-NEXT: bl .test_stackarg_int[PR] +; ASM64PWR4-NEXT: nop +; ASM64PWR4-NEXT: addi 1, 1, 160 +; ASM64PWR4-NEXT: ld 0, 16(1) +; ASM64PWR4-NEXT: mtlr 0 +; ASM64PWR4-NEXT: blr entry: %0 = load i8, ptr @c, align 1 %1 = load i16, ptr @si, align 2 @@ -977,121 +1002,60 @@ entry: declare void @test_stackarg_int(i32, i32, i32, i32, i32, i32, i32, i32, i8 zeroext, i16 signext, i32, i64, i32) -; CHECK-LABEL: name: call_test_stackarg_int{{.*}} - -; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. -; 32BIT-DAG: ADJCALLSTACKDOWN 80, 0, implicit-def dead $r1, implicit $r1 -; 32BIT-DAG: $r3 = LI 1 -; 32BIT-DAG: $r4 = LI 2 -; 32BIT-DAG: $r5 = LI 3 -; 32BIT-DAG: $r6 = LI 4 -; 32BIT-DAG: $r7 = LI 5 -; 32BIT-DAG: $r8 = LI 6 -; 32BIT-DAG: $r9 = LI 7 -; 32BIT-DAG: $r10 = LI 8 -; 32BIT-DAG: renamable $r[[REGCADDR:[0-9]+]] = LWZtoc @c, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $r[[REGC:[0-9]+]] = LBZ 0, killed renamable $r[[REGCADDR]] :: (dereferenceable load (s8) from @c) -; 32BIT-DAG: STW killed renamable $r[[REGC]], 56, $r1 :: (store (s32)) -; 32BIT-DAG: renamable $r[[REGSIADDR:[0-9]+]] = LWZtoc @si, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $r[[REGSI:[0-9]+]] = LHA 0, killed renamable $r[[REGSIADDR]] :: (dereferenceable load (s16) from @si) -; 32BIT-DAG: STW killed renamable $r[[REGSI]], 60, $r1 :: (store (s32)) -; 32BIT-DAG: renamable $r[[REGIADDR:[0-9]+]] = LWZtoc @i, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $r[[REGI:[0-9]+]] = LWZ 0, killed renamable $r[[REGIADDR]] :: (dereferenceable load (s32) from @i) -; 32BIT-DAG: STW killed renamable $r[[REGI]], 64, $r1 :: (store (s32)) -; 32BIT-DAG: renamable $r[[REGLLIADDR:[0-9]+]] = LWZtoc @lli, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $r[[REGLLI1:[0-9]+]] = LWZ 0, renamable $r[[REGLLIADDR]] :: (dereferenceable load (s32) from @lli, align 8) -; 32BIT-DAG: STW killed renamable $r[[REGLLI1]], 68, $r1 :: (store (s32)) -; 32BIT-DAG: renamable $r[[REGLLI2:[0-9]+]] = LWZ 4, killed renamable $r[[REGLLIADDR]] :: (dereferenceable load (s32) from @lli + 4, basealign 8) -; 32BIT-DAG: STW killed renamable $r[[REGLLI2]], 72, $r1 :: (store (s32)) -; 32BIT-DAG: STW renamable $r[[REGI]], 76, $r1 :: (store (s32)) -; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1 -; 32BIT-NEXT: ADJCALLSTACKUP 80, 0, implicit-def dead $r1, implicit $r1 - -; CHECKASM-LABEL: .call_test_stackarg_int: - -; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. -; ASM32PWR4: stwu 1, -80(1) -; ASM32PWR4-DAG: li 3, 1 -; ASM32PWR4-DAG: li 4, 2 -; ASM32PWR4-DAG: li 5, 3 -; ASM32PWR4-DAG: li 6, 4 -; ASM32PWR4-DAG: li 7, 5 -; ASM32PWR4-DAG: li 8, 6 -; ASM32PWR4-DAG: li 9, 7 -; ASM32PWR4-DAG: li 10, 8 -; ASM32PWR4-DAG: lwz [[REGCADDR:[0-9]+]], L..C6(2) -; ASM32PWR4-DAG: lbz [[REGC:[0-9]+]], 0([[REGCADDR]]) -; ASM32PWR4-DAG: stw [[REGC]], 56(1) -; ASM32PWR4-DAG: lwz [[REGSIADDR:[0-9]+]], L..C4(2) -; ASM32PWR4-DAG: lha [[REGSI:[0-9]+]], 0([[REGSIADDR]]) -; ASM32PWR4-DAG: stw [[REGSI]], 60(1) -; ASM32PWR4-DAG: lwz [[REGIADDR:[0-9]+]], L..C5(2) -; ASM32PWR4-DAG: lwz [[REGI:[0-9]+]], 0([[REGIADDR]]) -; ASM32PWR4-DAG: stw [[REGI]], 64(1) -; ASM32PWR4-DAG: lwz [[REGLLIADDR:[0-9]+]], L..C7(2) -; ASM32PWR4-DAG: lwz [[REGLLI1:[0-9]+]], 0([[REGLLIADDR]]) -; ASM32PWR4-DAG: stw [[REGLLI1]], 68(1) -; ASM32PWR4-DAG: lwz [[REGLLI2:[0-9]+]], 4([[REGLLIADDR]]) -; ASM32PWR4-DAG: stw [[REGLLI2]], 72(1) -; ASM32PWR4-DAG: stw [[REGI]], 76(1) -; ASM32PWR4-NEXT: bl .test_stackarg_int[PR] -; ASM32PWR4-NEXT: nop - -; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. -; 64BIT-DAG: ADJCALLSTACKDOWN 152, 0, implicit-def dead $r1, implicit $r1 -; 64BIT-DAG: $x3 = LI8 1 -; 64BIT-DAG: $x4 = LI8 2 -; 64BIT-DAG: $x5 = LI8 3 -; 64BIT-DAG: $x6 = LI8 4 -; 64BIT-DAG: $x7 = LI8 5 -; 64BIT-DAG: $x8 = LI8 6 -; 64BIT-DAG: $x9 = LI8 7 -; 64BIT-DAG: $x10 = LI8 8 -; 64BIT-DAG: renamable $x[[REGCADDR:[0-9]+]] = LDtoc @c, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $x[[REGC:[0-9]+]] = LBZ8 0, killed renamable $x[[REGCADDR]] :: (dereferenceable load (s8) from @c) -; 64BIT-DAG: STD killed renamable $x[[REGC]], 112, $x1 :: (store (s64)) -; 64BIT-DAG: renamable $x[[REGSIADDR:[0-9]+]] = LDtoc @si, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $x[[REGSI:[0-9]+]] = LHA8 0, killed renamable $x[[REGSIADDR]] :: (dereferenceable load (s16) from @si) -; 64BIT-DAG: STD killed renamable $x[[REGSI]], 120, $x1 :: (store (s64)) -; 64BIT-DAG: renamable $x[[REGIADDR:[0-9]+]] = LDtoc @i, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $x[[REGI:[0-9]+]] = LWZ8 0, killed renamable $x[[REGIADDR]] :: (dereferenceable load (s32) from @i) -; 64BIT-DAG: STD killed renamable $x[[REGI]], 128, $x1 :: (store (s64)) -; 64BIT-DAG: renamable $x[[REGLLIADDR:[0-9]+]] = LDtoc @lli, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $x[[REGLLI:[0-9]+]] = LD 0, killed renamable $x[[REGLLIADDR]] :: (dereferenceable load (s64) from @lli) -; 64BIT-DAG: STD killed renamable $x[[REGLLI]], 136, $x1 :: (store (s64)) -; 64BIT-DAG: STD renamable $x[[REGI]], 144, $x1 :: (store (s64)) -; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1 -; 64BIT-NEXT: ADJCALLSTACKUP 152, 0, implicit-def dead $r1, implicit $r1 - -; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. -; ASM64PWR4-DAG: stdu 1, -160(1) -; ASM64PWR4-DAG: li 3, 1 -; ASM64PWR4-DAG: li 4, 2 -; ASM64PWR4-DAG: li 5, 3 -; ASM64PWR4-DAG: li 6, 4 -; ASM64PWR4-DAG: li 7, 5 -; ASM64PWR4-DAG: li 8, 6 -; ASM64PWR4-DAG: li 9, 7 -; ASM64PWR4-DAG: li 10, 8 -; ASM64PWR4-DAG: ld [[REGCADDR:[0-9]+]], L..C5(2) -; ASM64PWR4-DAG: lbz [[REGC:[0-9]+]], 0([[REGCADDR]]) -; ASM64PWR4-DAG: std [[REGC]], 112(1) -; ASM64PWR4-DAG: ld [[REGSIADDR:[0-9]+]], L..C3(2) -; ASM64PWR4-DAG: lha [[REGSI:[0-9]+]], 0([[REGSIADDR]]) -; ASM64PWR4-DAG: std [[REGSI]], 120(1) -; ASM64PWR4-DAG: ld [[REGIADDR:[0-9]+]], L..C4(2) -; ASM64PWR4-DAG: lwz [[REGI:[0-9]+]], 0([[REGIADDR]]) -; ASM64PWR4-DAG: std [[REGI]], 128(1) -; ASM64PWR4-DAG: ld [[REGLLIADDR:[0-9]+]], L..C6(2) -; ASM64PWR4-DAG: ld [[REGLLI:[0-9]+]], 0([[REGLLIADDR]]) -; ASM64PWR4-DAG: std [[REGLLI]], 136(1) -; ASM64PWR4-DAG: std [[REGI]], 144(1) -; ASM64PWR4-NEXT: bl .test_stackarg_int[PR] -; ASM64PWR4-NEXT: nop - ; Basic saving of floating point type arguments to the parameter save area. ; The float and double arguments will pass in both fpr as well as parameter save area. define void @call_test_stackarg_float() { +; ASM32PWR4-LABEL: call_test_stackarg_float: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: mflr 0 +; ASM32PWR4-NEXT: stwu 1, -80(1) +; ASM32PWR4-NEXT: lwz 3, L..C8(2) # @f +; ASM32PWR4-NEXT: stw 0, 88(1) +; ASM32PWR4-NEXT: li 4, 2 +; ASM32PWR4-NEXT: li 5, 3 +; ASM32PWR4-NEXT: li 6, 4 +; ASM32PWR4-NEXT: li 7, 5 +; ASM32PWR4-NEXT: lfs 1, 0(3) +; ASM32PWR4-NEXT: lwz 3, L..C9(2) # @d +; ASM32PWR4-NEXT: li 8, 6 +; ASM32PWR4-NEXT: li 9, 7 +; ASM32PWR4-NEXT: lfd 2, 0(3) +; ASM32PWR4-NEXT: li 3, 1 +; ASM32PWR4-NEXT: li 10, 8 +; ASM32PWR4-NEXT: stfd 2, 60(1) +; ASM32PWR4-NEXT: stfs 1, 56(1) +; ASM32PWR4-NEXT: bl .test_stackarg_float[PR] +; ASM32PWR4-NEXT: nop +; ASM32PWR4-NEXT: addi 1, 1, 80 +; ASM32PWR4-NEXT: lwz 0, 8(1) +; ASM32PWR4-NEXT: mtlr 0 +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: call_test_stackarg_float: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: mflr 0 +; ASM64PWR4-NEXT: stdu 1, -128(1) +; ASM64PWR4-NEXT: ld 3, L..C7(2) # @f +; ASM64PWR4-NEXT: std 0, 144(1) +; ASM64PWR4-NEXT: li 4, 2 +; ASM64PWR4-NEXT: li 5, 3 +; ASM64PWR4-NEXT: li 6, 4 +; ASM64PWR4-NEXT: li 7, 5 +; ASM64PWR4-NEXT: lfs 1, 0(3) +; ASM64PWR4-NEXT: ld 3, L..C8(2) # @d +; ASM64PWR4-NEXT: li 8, 6 +; ASM64PWR4-NEXT: li 9, 7 +; ASM64PWR4-NEXT: lfd 2, 0(3) +; ASM64PWR4-NEXT: li 3, 1 +; ASM64PWR4-NEXT: li 10, 8 +; ASM64PWR4-NEXT: stfd 2, 120(1) +; ASM64PWR4-NEXT: stfs 1, 112(1) +; ASM64PWR4-NEXT: bl .test_stackarg_float[PR] +; ASM64PWR4-NEXT: nop +; ASM64PWR4-NEXT: addi 1, 1, 128 +; ASM64PWR4-NEXT: ld 0, 16(1) +; ASM64PWR4-NEXT: mtlr 0 +; ASM64PWR4-NEXT: blr entry: %0 = load float, ptr @f, align 4 %1 = load double, ptr @d, align 8 @@ -1101,89 +1065,51 @@ entry: declare void @test_stackarg_float(i32, i32, i32, i32, i32, i32, i32, i32, float, double) -; CHECK-LABEL: name: call_test_stackarg_float - -; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. -; 32BIT-DAG: ADJCALLSTACKDOWN 68, 0, implicit-def dead $r1, implicit $r1 -; 32BIT-DAG: $r3 = LI 1 -; 32BIT-DAG: $r4 = LI 2 -; 32BIT-DAG: $r5 = LI 3 -; 32BIT-DAG: $r6 = LI 4 -; 32BIT-DAG: $r7 = LI 5 -; 32BIT-DAG: $r8 = LI 6 -; 32BIT-DAG: $r9 = LI 7 -; 32BIT-DAG: $r10 = LI 8 -; 32BIT-DAG: renamable $r[[REGF:[0-9]+]] = LWZtoc @f, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $f1 = LFS 0, killed renamable $r[[REGF]] :: (dereferenceable load (s32) from @f) -; 32BIT-DAG: renamable $r[[REGD:[0-9]+]] = LWZtoc @d, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $f2 = LFD 0, killed renamable $r[[REGD]] :: (dereferenceable load (s64) from @d) -; 32BIT-DAG: STFS renamable $f1, 56, $r1 :: (store (s32)) -; 32BIT-DAG: STFD renamable $f2, 60, $r1 :: (store (s64)) -; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit killed $r10, implicit $f1, implicit $f2, implicit $r2, implicit-def $r1 -; 32BIT-NEXT: ADJCALLSTACKUP 68, 0, implicit-def dead $r1, implicit $r1 - -; CHECKASM-LABEL: .call_test_stackarg_float: - -; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. -; ASM32PWR4: stwu 1, -80(1) -; ASM32PWR4-DAG: li 3, 1 -; ASM32PWR4-DAG: li 4, 2 -; ASM32PWR4-DAG: li 5, 3 -; ASM32PWR4-DAG: li 6, 4 -; ASM32PWR4-DAG: li 7, 5 -; ASM32PWR4-DAG: li 8, 6 -; ASM32PWR4-DAG: li 9, 7 -; ASM32PWR4-DAG: li 10, 8 -; ASM32PWR4-DAG: lwz [[REGF:[0-9]+]], L..C8(2) -; ASM32PWR4-DAG: lfs 1, 0([[REGF]]) -; ASM32PWR4-DAG: lwz [[REGD:[0-9]+]], L..C9(2) -; ASM32PWR4-DAG: lfd 2, 0([[REGD:[0-9]+]]) -; ASM32PWR4-DAG: stfs 1, 56(1) -; ASM32PWR4-DAG: stfd 2, 60(1) -; ASM32PWR4-NEXT: bl .test_stackarg_float[PR] -; ASM32PWR4-NEXT: nop -; ASM32PWR4-NEXT: addi 1, 1, 80 - -; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. -; 64BIT-DAG: ADJCALLSTACKDOWN 128, 0, implicit-def dead $r1, implicit $r1 -; 64BIT-DAG: $x3 = LI8 1 -; 64BIT-DAG: $x4 = LI8 2 -; 64BIT-DAG: $x5 = LI8 3 -; 64BIT-DAG: $x6 = LI8 4 -; 64BIT-DAG: $x7 = LI8 5 -; 64BIT-DAG: $x8 = LI8 6 -; 64BIT-DAG: $x9 = LI8 7 -; 64BIT-DAG: $x10 = LI8 8 -; 64BIT-DAG: renamable $x[[REGF:[0-9]+]] = LDtoc @f, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $f1 = LFS 0, killed renamable $x[[REGF]] :: (dereferenceable load (s32) from @f) -; 64BIT-DAG: renamable $x[[REGD:[0-9]+]] = LDtoc @d, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $f2 = LFD 0, killed renamable $x[[REGD]] :: (dereferenceable load (s64) from @d) -; 64BIT-DAG: STFS renamable $f1, 112, $x1 :: (store (s32)) -; 64BIT-DAG: STFD renamable $f2, 120, $x1 :: (store (s64)) -; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit killed $x10, implicit $f1, implicit $f2, implicit $x2, implicit-def $r1 -; 64BIT-NEXT: ADJCALLSTACKUP 128, 0, implicit-def dead $r1, implicit $r1 - -; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. -; ASM64PWR4: stdu 1, -128(1) -; ASM64PWR4-DAG: li 3, 1 -; ASM64PWR4-DAG: li 4, 2 -; ASM64PWR4-DAG: li 5, 3 -; ASM64PWR4-DAG: li 6, 4 -; ASM64PWR4-DAG: li 7, 5 -; ASM64PWR4-DAG: li 8, 6 -; ASM64PWR4-DAG: li 9, 7 -; ASM64PWR4-DAG: li 10, 8 -; ASM64PWR4-DAG: ld [[REGF:[0-9]+]], L..C7(2) -; ASM64PWR4-DAG: lfs 1, 0([[REGF]]) -; ASM64PWR4-DAG: ld [[REGD:[0-9]+]], L..C8(2) -; ASM64PWR4-DAG: lfd 2, 0([[REGD]]) -; ASM64PWR4-DAG: stfs 1, 112(1) -; ASM64PWR4-DAG: stfd 2, 120(1) -; ASM64PWR4-NEXT: bl .test_stackarg_float[PR] -; ASM64PWR4-NEXT: nop -; ASM64PWR4-NEXT: addi 1, 1, 128 - define void @call_test_stackarg_float2() { +; ASM32PWR4-LABEL: call_test_stackarg_float2: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: mflr 0 +; ASM32PWR4-NEXT: stwu 1, -64(1) +; ASM32PWR4-NEXT: lwz 3, L..C9(2) # @d +; ASM32PWR4-NEXT: stw 0, 72(1) +; ASM32PWR4-NEXT: li 4, 2 +; ASM32PWR4-NEXT: li 5, 3 +; ASM32PWR4-NEXT: li 6, 4 +; ASM32PWR4-NEXT: li 7, 5 +; ASM32PWR4-NEXT: lfd 1, 0(3) +; ASM32PWR4-NEXT: li 3, 1 +; ASM32PWR4-NEXT: li 8, 6 +; ASM32PWR4-NEXT: stfd 1, 56(1) +; ASM32PWR4-NEXT: lwz 9, 56(1) +; ASM32PWR4-NEXT: lwz 10, 60(1) +; ASM32PWR4-NEXT: bl .test_stackarg_float2[PR] +; ASM32PWR4-NEXT: nop +; ASM32PWR4-NEXT: addi 1, 1, 64 +; ASM32PWR4-NEXT: lwz 0, 8(1) +; ASM32PWR4-NEXT: mtlr 0 +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: call_test_stackarg_float2: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: mflr 0 +; ASM64PWR4-NEXT: stdu 1, -128(1) +; ASM64PWR4-NEXT: ld 3, L..C8(2) # @d +; ASM64PWR4-NEXT: std 0, 144(1) +; ASM64PWR4-NEXT: li 4, 2 +; ASM64PWR4-NEXT: li 5, 3 +; ASM64PWR4-NEXT: li 6, 4 +; ASM64PWR4-NEXT: li 7, 5 +; ASM64PWR4-NEXT: lfd 1, 0(3) +; ASM64PWR4-NEXT: li 3, 1 +; ASM64PWR4-NEXT: li 8, 6 +; ASM64PWR4-NEXT: stfd 1, 120(1) +; ASM64PWR4-NEXT: ld 9, 120(1) +; ASM64PWR4-NEXT: bl .test_stackarg_float2[PR] +; ASM64PWR4-NEXT: nop +; ASM64PWR4-NEXT: addi 1, 1, 128 +; ASM64PWR4-NEXT: ld 0, 16(1) +; ASM64PWR4-NEXT: mtlr 0 +; ASM64PWR4-NEXT: blr entry: %0 = load double, ptr @d, align 8 call void (i32, i32, i32, i32, i32, i32, ...) @test_stackarg_float2(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, double %0) @@ -1192,76 +1118,60 @@ entry: declare void @test_stackarg_float2(i32, i32, i32, i32, i32, i32, ...) -; CHECK-LABEL: name: call_test_stackarg_float2{{.*}} - -; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. -; 32BIT-DAG: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 -; 32BIT-DAG: $r3 = LI 1 -; 32BIT-DAG: $r4 = LI 2 -; 32BIT-DAG: $r5 = LI 3 -; 32BIT-DAG: $r6 = LI 4 -; 32BIT-DAG: $r7 = LI 5 -; 32BIT-DAG: $r8 = LI 6 -; 32BIT-DAG: renamable $r[[REG:[0-9]+]] = LWZtoc @d, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $f1 = LFD 0, killed renamable $r[[REG]] :: (dereferenceable load (s64) from @d) -; 32BIT-DAG: STFD renamable $f1, 0, %stack.0 :: (store (s64) into %stack.0) -; 32BIT-DAG: renamable $r9 = LWZ 0, %stack.0 :: (load (s32) from %stack.0, align 8) -; 32BIT-DAG: renamable $r10 = LWZ 4, %stack.0 :: (load (s32) from %stack.0 + 4) -; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit $f1, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1 -; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 - -; CHECKASM-LABEL: .call_test_stackarg_float2: - -; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. -; ASM32PWR4: stwu 1, -64(1) -; ASM32PWR4-DAG: li 3, 1 -; ASM32PWR4-DAG: li 4, 2 -; ASM32PWR4-DAG: li 5, 3 -; ASM32PWR4-DAG: li 6, 4 -; ASM32PWR4-DAG: li 7, 5 -; ASM32PWR4-DAG: li 8, 6 -; ASM32PWR4-DAG: lwz [[REG:[0-9]+]], L..C9(2) -; ASM32PWR4-DAG: lfd 1, 0([[REG]]) -; ASM32PWR4-DAG: stfd 1, 56(1) -; ASM32PWR4-DAG: lwz 9, 56(1) -; ASM32PWR4-DAG: lwz 10, 60(1) -; ASM32PWR4-NEXT: bl .test_stackarg_float2[PR] -; ASM32PWR4-NEXT: nop -; ASM32PWR4-NEXT: addi 1, 1, 64 - -; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. -; 64BIT-DAG: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 -; 64BIT-DAG: $x3 = LI8 1 -; 64BIT-DAG: $x4 = LI8 2 -; 64BIT-DAG: $x5 = LI8 3 -; 64BIT-DAG: $x6 = LI8 4 -; 64BIT-DAG: $x7 = LI8 5 -; 64BIT-DAG: $x8 = LI8 6 -; 64BIT-DAG: renamable $x[[REG:[0-9]+]] = LDtoc @d, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $f1 = LFD 0, killed renamable $x[[REG]] :: (dereferenceable load (s64) from @d) -; 64BIT-DAG: STFD renamable $f1, 0, %stack.0 :: (store (s64) into %stack.0) -; 64BIT-DAG: renamable $x9 = LD 0, %stack.0 :: (load (s64) from %stack.0) -; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit $f1, implicit $x9, implicit $x2, implicit-def $r1 -; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 - -; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. -; ASM64PWR4: stdu 1, -128(1) -; ASM64PWR4-DAG: li 3, 1 -; ASM64PWR4-DAG: li 4, 2 -; ASM64PWR4-DAG: li 5, 3 -; ASM64PWR4-DAG: li 6, 4 -; ASM64PWR4-DAG: li 7, 5 -; ASM64PWR4-DAG: li 8, 6 -; ASM64PWR4-DAG: ld [[REG:[0-9]+]], L..C8(2) -; ASM64PWR4-DAG: lfd 1, 0([[REG]]) -; ASM64PWR4-DAG: stfd 1, 120(1) -; ASM64PWR4-DAG: ld 9, 120(1) -; ASM64PWR4-NEXT: bl .test_stackarg_float2[PR] -; ASM64PWR4-NEXT: nop -; ASM64PWR4-NEXT: addi 1, 1, 128 - ; A double arg will pass on the stack in PPC32 if there is only one available GPR. define void @call_test_stackarg_float3() { +; ASM32PWR4-LABEL: call_test_stackarg_float3: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: mflr 0 +; ASM32PWR4-NEXT: stwu 1, -80(1) +; ASM32PWR4-NEXT: lwz 3, L..C9(2) # @d +; ASM32PWR4-NEXT: stw 0, 88(1) +; ASM32PWR4-NEXT: li 4, 2 +; ASM32PWR4-NEXT: li 5, 3 +; ASM32PWR4-NEXT: li 6, 4 +; ASM32PWR4-NEXT: li 7, 5 +; ASM32PWR4-NEXT: lfd 1, 0(3) +; ASM32PWR4-NEXT: lwz 3, L..C8(2) # @f +; ASM32PWR4-NEXT: li 8, 6 +; ASM32PWR4-NEXT: li 9, 7 +; ASM32PWR4-NEXT: stfd 1, 72(1) +; ASM32PWR4-NEXT: lwz 10, 72(1) +; ASM32PWR4-NEXT: lfs 2, 0(3) +; ASM32PWR4-NEXT: li 3, 1 +; ASM32PWR4-NEXT: stfs 2, 60(1) +; ASM32PWR4-NEXT: stfd 1, 52(1) +; ASM32PWR4-NEXT: bl .test_stackarg_float3[PR] +; ASM32PWR4-NEXT: nop +; ASM32PWR4-NEXT: addi 1, 1, 80 +; ASM32PWR4-NEXT: lwz 0, 8(1) +; ASM32PWR4-NEXT: mtlr 0 +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: call_test_stackarg_float3: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: mflr 0 +; ASM64PWR4-NEXT: stdu 1, -128(1) +; ASM64PWR4-NEXT: ld 3, L..C8(2) # @d +; ASM64PWR4-NEXT: std 0, 144(1) +; ASM64PWR4-NEXT: li 4, 2 +; ASM64PWR4-NEXT: li 5, 3 +; ASM64PWR4-NEXT: li 6, 4 +; ASM64PWR4-NEXT: li 7, 5 +; ASM64PWR4-NEXT: lfd 1, 0(3) +; ASM64PWR4-NEXT: ld 3, L..C7(2) # @f +; ASM64PWR4-NEXT: li 8, 6 +; ASM64PWR4-NEXT: li 9, 7 +; ASM64PWR4-NEXT: stfd 1, 120(1) +; ASM64PWR4-NEXT: ld 10, 120(1) +; ASM64PWR4-NEXT: lfs 2, 0(3) +; ASM64PWR4-NEXT: li 3, 1 +; ASM64PWR4-NEXT: stfs 2, 112(1) +; ASM64PWR4-NEXT: bl .test_stackarg_float3[PR] +; ASM64PWR4-NEXT: nop +; ASM64PWR4-NEXT: addi 1, 1, 128 +; ASM64PWR4-NEXT: ld 0, 16(1) +; ASM64PWR4-NEXT: mtlr 0 +; ASM64PWR4-NEXT: blr entry: %0 = load double, ptr @d, align 8 %1 = load float, ptr @f, align 4 @@ -1271,94 +1181,79 @@ entry: declare void @test_stackarg_float3(i32, i32, i32, i32, i32, i32, i32, ...) -; CHECK-LABEL: name: call_test_stackarg_float3{{.*}} - -; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. -; In 32-bit the double arg is written to memory because it cannot be fully stored in the last 32-bit GPR. -; 32BIT-DAG: ADJCALLSTACKDOWN 64, 0, implicit-def dead $r1, implicit $r1 -; 32BIT-DAG: $r3 = LI 1 -; 32BIT-DAG: $r4 = LI 2 -; 32BIT-DAG: $r5 = LI 3 -; 32BIT-DAG: $r6 = LI 4 -; 32BIT-DAG: $r7 = LI 5 -; 32BIT-DAG: $r8 = LI 6 -; 32BIT-DAG: $r9 = LI 7 -; 32BIT-DAG: renamable $r[[REGD:[0-9]+]] = LWZtoc @d, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $f1 = LFD 0, killed renamable $r[[REGD]] :: (dereferenceable load (s64) from @d) -; 32BIT-DAG: renamable $r[[REGF:[0-9]+]] = LWZtoc @f, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $f2 = LFS 0, killed renamable $r[[REGF]] :: (dereferenceable load (s32) from @f) -; 32BIT-DAG: STFD renamable $f1, 52, $r1 :: (store (s64)) -; 32BIT-DAG: STFS renamable $f2, 60, $r1 :: (store (s32)) -; 32BIT-DAG: STFD renamable $f1, 0, %stack.0 :: (store (s64) into %stack.0) -; 32BIT-DAG: renamable $r10 = LWZ 0, %stack.0 :: (load (s32) from %stack.0, align 8) -; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit $f1, implicit $r10, implicit $f2, implicit $r2, implicit-def $r1 -; 32BIT-NEXT: ADJCALLSTACKUP 64, 0, implicit-def dead $r1, implicit $r1 - -; CHECKASM-LABEL: .call_test_stackarg_float3: - -; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. -; ASM32PWR4: stwu 1, -80(1) -; ASM32PWR4-DAG: li 3, 1 -; ASM32PWR4-DAG: li 4, 2 -; ASM32PWR4-DAG: li 5, 3 -; ASM32PWR4-DAG: li 6, 4 -; ASM32PWR4-DAG: li 7, 5 -; ASM32PWR4-DAG: li 8, 6 -; ASM32PWR4-DAG: li 9, 7 -; ASM32PWR4-DAG: lwz [[REGD:[0-9]+]], L..C9(2) -; ASM32PWR4-DAG: lfd 1, 0([[REGD]]) -; ASM32PWR4-DAG: lwz [[REGF:[0-9]+]], L..C8(2) -; ASM32PWR4-DAG: lfs 2, 0([[REGF]]) -; ASM32PWR4-DAG: stfd 1, 52(1) -; ASM32PWR4-DAG: stfs 2, 60(1) -; ASM32PWR4-DAG: stfd 1, 72(1) -; ASM32PWR4-DAG: lwz 10, 72(1) -; ASM32PWR4-NEXT: bl .test_stackarg_float3[PR] -; ASM32PWR4-NEXT: nop -; ASM32PWR4-NEXT: addi 1, 1, 80 - -; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. -; In 64-bit the double arg is not written to memory because it is fully stored in the last 64-bit GPR. -; 64BIT-DAG: ADJCALLSTACKDOWN 120, 0, implicit-def dead $r1, implicit $r1 -; 64BIT-DAG: $x3 = LI8 1 -; 64BIT-DAG: $x4 = LI8 2 -; 64BIT-DAG: $x5 = LI8 3 -; 64BIT-DAG: $x6 = LI8 4 -; 64BIT-DAG: $x7 = LI8 5 -; 64BIT-DAG: $x8 = LI8 6 -; 64BIT-DAG: $x9 = LI8 7 -; 64BIT-DAG: renamable $x[[REGD:[0-9]+]] = LDtoc @d, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $f1 = LFD 0, killed renamable $x[[REGD]] :: (dereferenceable load (s64) from @d) -; 64BIT-DAG: renamable $x[[REGF:[0-9]+]] = LDtoc @f, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $f2 = LFS 0, killed renamable $x[[REGF]] :: (dereferenceable load (s32) from @f) -; 64BIT-DAG: STFS renamable $f2, 112, $x1 :: (store (s32)) -; 64BIT-DAG: STFD renamable $f1, 0, %stack.0 :: (store (s64) into %stack.0) -; 64BIT-DAG: renamable $x10 = LD 0, %stack.0 :: (load (s64) from %stack.0) -; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit $f1, implicit $x10, implicit $f2, implicit $x2, implicit-def $r1 - -; 64BIT-NEXT: ADJCALLSTACKUP 120, 0, implicit-def dead $r1, implicit $r1 - -; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. -; ASM64PWR4: stdu 1, -128(1) -; ASM64PWR4-DAG: li 3, 1 -; ASM64PWR4-DAG: li 4, 2 -; ASM64PWR4-DAG: li 5, 3 -; ASM64PWR4-DAG: li 6, 4 -; ASM64PWR4-DAG: li 7, 5 -; ASM64PWR4-DAG: li 8, 6 -; ASM64PWR4-DAG: li 9, 7 -; ASM64PWR4-DAG: ld [[REGD:[0-9]+]], L..C8(2) -; ASM64PWR4-DAG: lfd 1, 0([[REGD]]) -; ASM64PWR4-DAG: ld [[REGF:[0-9]+]], L..C7(2) -; ASM64PWR4-DAG: lfs 2, 0([[REGF]]) -; ASM64PWR4-DAG: stfs 2, 112(1) -; ASM64PWR4-DAG: stfd 1, 120(1) -; ASM64PWR4-DAG: ld 10, 120(1) -; ASM64PWR4-NEXT: bl .test_stackarg_float3[PR] -; ASM64PWR4-NEXT: nop -; ASM64PWR4-NEXT: addi 1, 1, 128 - define i64 @test_ints_stack(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i64 %ll9, i16 signext %s10, i8 zeroext %c11, i32 %ui12, i32 %si13, i64 %ll14, i8 zeroext %uc15, i32 %i16) { +; ASM32PWR4-LABEL: test_ints_stack: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: add 3, 3, 4 +; ASM32PWR4-NEXT: lwz 11, 92(1) +; ASM32PWR4-NEXT: add 3, 3, 5 +; ASM32PWR4-NEXT: add 3, 3, 6 +; ASM32PWR4-NEXT: add 3, 3, 7 +; ASM32PWR4-NEXT: lwz 12, 76(1) +; ASM32PWR4-NEXT: add 3, 3, 8 +; ASM32PWR4-NEXT: add 3, 3, 9 +; ASM32PWR4-NEXT: lwz 6, 60(1) +; ASM32PWR4-NEXT: add 3, 3, 10 +; ASM32PWR4-NEXT: srawi 5, 11, 31 +; ASM32PWR4-NEXT: srawi 8, 3, 31 +; ASM32PWR4-NEXT: lwz 4, 64(1) +; ASM32PWR4-NEXT: lwz 7, 56(1) +; ASM32PWR4-NEXT: stw 31, -4(1) # 4-byte Folded Spill +; ASM32PWR4-NEXT: srawi 31, 12, 31 +; ASM32PWR4-NEXT: addc 3, 3, 6 +; ASM32PWR4-NEXT: adde 7, 8, 7 +; ASM32PWR4-NEXT: lwz 6, 68(1) +; ASM32PWR4-NEXT: srawi 8, 4, 31 +; ASM32PWR4-NEXT: addc 3, 3, 4 +; ASM32PWR4-NEXT: adde 7, 7, 8 +; ASM32PWR4-NEXT: lwz 4, 72(1) +; ASM32PWR4-NEXT: addc 3, 3, 6 +; ASM32PWR4-NEXT: addze 6, 7 +; ASM32PWR4-NEXT: addc 3, 3, 4 +; ASM32PWR4-NEXT: lwz 0, 84(1) +; ASM32PWR4-NEXT: addze 4, 6 +; ASM32PWR4-NEXT: addc 3, 3, 12 +; ASM32PWR4-NEXT: lwz 7, 80(1) +; ASM32PWR4-NEXT: adde 4, 4, 31 +; ASM32PWR4-NEXT: addc 3, 3, 0 +; ASM32PWR4-NEXT: lwz 6, 88(1) +; ASM32PWR4-NEXT: adde 4, 4, 7 +; ASM32PWR4-NEXT: addc 3, 3, 6 +; ASM32PWR4-NEXT: lwz 31, -4(1) # 4-byte Folded Reload +; ASM32PWR4-NEXT: addze 6, 4 +; ASM32PWR4-NEXT: addc 4, 3, 11 +; ASM32PWR4-NEXT: adde 3, 6, 5 +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: test_ints_stack: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: add 3, 3, 4 +; ASM64PWR4-NEXT: ld 4, 112(1) +; ASM64PWR4-NEXT: add 3, 3, 5 +; ASM64PWR4-NEXT: add 3, 3, 6 +; ASM64PWR4-NEXT: add 3, 3, 7 +; ASM64PWR4-NEXT: lwa 12, 124(1) +; ASM64PWR4-NEXT: add 3, 3, 8 +; ASM64PWR4-NEXT: add 3, 3, 9 +; ASM64PWR4-NEXT: add 3, 3, 10 +; ASM64PWR4-NEXT: extsw 3, 3 +; ASM64PWR4-NEXT: lwz 5, 132(1) +; ASM64PWR4-NEXT: add 3, 3, 4 +; ASM64PWR4-NEXT: add 3, 3, 12 +; ASM64PWR4-NEXT: std 31, -8(1) # 8-byte Folded Spill +; ASM64PWR4-NEXT: add 3, 3, 5 +; ASM64PWR4-NEXT: lwz 31, 140(1) +; ASM64PWR4-NEXT: lwa 11, 148(1) +; ASM64PWR4-NEXT: add 3, 3, 31 +; ASM64PWR4-NEXT: add 3, 3, 11 +; ASM64PWR4-NEXT: ld 4, 152(1) +; ASM64PWR4-NEXT: lwz 0, 164(1) +; ASM64PWR4-NEXT: add 3, 3, 4 +; ASM64PWR4-NEXT: lwa 5, 172(1) +; ASM64PWR4-NEXT: add 3, 3, 0 +; ASM64PWR4-NEXT: add 3, 3, 5 +; ASM64PWR4-NEXT: ld 31, -8(1) # 8-byte Folded Reload +; ASM64PWR4-NEXT: blr entry: %add = add nsw i32 %i1, %i2 %add1 = add nsw i32 %add, %i3 @@ -1385,79 +1280,6 @@ entry: ret i64 %add20 } -; CHECK-LABEL: name: test_ints_stack - -; 32BIT-LABEL: liveins: -; 32BIT-DAG: - { reg: '$r3', virtual-reg: '' } -; 32BIT-DAG: - { reg: '$r4', virtual-reg: '' } -; 32BIT-DAG: - { reg: '$r5', virtual-reg: '' } -; 32BIT-DAG: - { reg: '$r6', virtual-reg: '' } -; 32BIT-DAG: - { reg: '$r7', virtual-reg: '' } -; 32BIT-DAG: - { reg: '$r8', virtual-reg: '' } -; 32BIT-DAG: - { reg: '$r9', virtual-reg: '' } -; 32BIT-DAG: - { reg: '$r10', virtual-reg: '' } - -; 32BIT-LABEL: fixedStack: -; 32BIT-DAG: - { id: 9, type: default, offset: 56, size: 4 -; 32BIT-DAG: - { id: 8, type: default, offset: 60, size: 4 -; 32BIT-DAG: - { id: 7, type: default, offset: 64, size: 4 -; 32BIT-DAG: - { id: 6, type: default, offset: 68, size: 4 -; 32BIT-DAG: - { id: 5, type: default, offset: 72, size: 4 -; 32BIT-DAG: - { id: 4, type: default, offset: 76, size: 4 -; 32BIT-DAG: - { id: 3, type: default, offset: 80, size: 4 -; 32BIT-DAG: - { id: 2, type: default, offset: 84, size: 4 -; 32BIT-DAG: - { id: 1, type: default, offset: 88, size: 4 -; 32BIT-DAG: - { id: 0, type: default, offset: 92, size: 4 - -; 32BIT-LABEL: body: | -; 32BIT-DAG: bb.0.entry: -; 32BIT-DAG: liveins: $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10 - -; 64BIT-LABEL: liveins: -; 64BIT-DAG: - { reg: '$x3', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$x4', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$x5', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$x6', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$x7', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$x8', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$x9', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$x10', virtual-reg: '' } - -; 64BIT-LABEL: fixedStack: -; 64BIT-DAG: - { id: 7, type: default, offset: 112, size: 8 -; 64BIT-DAG: - { id: 6, type: default, offset: 124, size: 4 -; 64BIT-DAG: - { id: 5, type: default, offset: 132, size: 4 -; 64BIT-DAG: - { id: 4, type: default, offset: 140, size: 4 -; 64BIT-DAG: - { id: 3, type: default, offset: 148, size: 4 -; 64BIT-DAG: - { id: 2, type: default, offset: 152, size: 8 -; 64BIT-DAG: - { id: 1, type: default, offset: 164, size: 4 -; 64BIT-DAG: - { id: 0, type: default, offset: 172, size: 4 -; 64BIT-DAG: body: | -; 64BIT-DAG: bb.0.entry: -; 64BIT-DAG: liveins: $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10 - -; CHECKASM-LABEL: .test_ints_stack: - -; ASM32PWR4-DAG: lwz [[REG1:[0-9]+]], 56(1) -; ASM32PWR4-DAG: lwz [[REG2:[0-9]+]], 60(1) -; ASM32PWR4-DAG: lwz [[REG3:[0-9]+]], 64(1) -; ASM32PWR4-DAG: lwz [[REG4:[0-9]+]], 68(1) -; ASM32PWR4-DAG: lwz [[REG5:[0-9]+]], 72(1) -; ASM32PWR4-DAG: lwz [[REG6:[0-9]+]], 76(1) -; ASM32PWR4-DAG: lwz [[REG7:[0-9]+]], 80(1) -; ASM32PWR4-DAG: lwz [[REG8:[0-9]+]], 84(1) -; ASM32PWR4-DAG: lwz [[REG9:[0-9]+]], 88(1) -; ASM32PWR4-DAG: lwz [[REG10:[0-9]+]], 92(1) - -; ASM64PWR4-DAG: ld [[REG1:[0-9]+]], 112(1) -; ASM64PWR4-DAG: lwa [[REG2:[0-9]+]], 124(1) -; ASM64PWR4-DAG: lwz [[REG3:[0-9]+]], 132(1) -; ASM64PWR4-DAG: lwz [[REG4:[0-9]+]], 140(1) -; ASM64PWR4-DAG: lwa [[REG5:[0-9]+]], 148(1) -; ASM64PWR4-DAG: ld [[REG6:[0-9]+]], 152(1) -; ASM64PWR4-DAG: lwz [[REG7:[0-9]+]], 164(1) -; ASM64PWR4-DAG: lwa [[REG8:[0-9]+]], 172(1) - @ll1 = common global i64 0, align 8 @si1 = common global i16 0, align 2 @ch = common global i8 0, align 1 @@ -1468,6 +1290,97 @@ entry: @i1 = common global i32 0, align 4 define void @caller_ints_stack() { +; ASM32PWR4-LABEL: caller_ints_stack: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: mflr 0 +; ASM32PWR4-NEXT: stwu 1, -96(1) +; ASM32PWR4-NEXT: lwz 3, L..C10(2) # @si1 +; ASM32PWR4-NEXT: stw 0, 104(1) +; ASM32PWR4-NEXT: lwz 4, L..C11(2) # @ch +; ASM32PWR4-NEXT: lwz 6, L..C12(2) # @sint +; ASM32PWR4-NEXT: lwz 8, L..C13(2) # @ll2 +; ASM32PWR4-NEXT: lwz 10, L..C14(2) # @uc1 +; ASM32PWR4-NEXT: lwz 12, L..C15(2) # @i1 +; ASM32PWR4-NEXT: lha 5, 0(3) +; ASM32PWR4-NEXT: lwz 3, L..C16(2) # @ll1 +; ASM32PWR4-NEXT: lwz 11, 0(3) +; ASM32PWR4-NEXT: lwz 7, 4(3) +; ASM32PWR4-NEXT: lwz 3, L..C17(2) # @ui +; ASM32PWR4-NEXT: lbz 4, 0(4) +; ASM32PWR4-NEXT: lwz 3, 0(3) +; ASM32PWR4-NEXT: lwz 6, 0(6) +; ASM32PWR4-NEXT: lwz 9, 0(8) +; ASM32PWR4-NEXT: lwz 8, 4(8) +; ASM32PWR4-NEXT: lbz 10, 0(10) +; ASM32PWR4-NEXT: lwz 12, 0(12) +; ASM32PWR4-NEXT: stw 10, 88(1) +; ASM32PWR4-NEXT: li 10, 8 +; ASM32PWR4-NEXT: stw 8, 84(1) +; ASM32PWR4-NEXT: li 8, 6 +; ASM32PWR4-NEXT: stw 9, 80(1) +; ASM32PWR4-NEXT: li 9, 7 +; ASM32PWR4-NEXT: stw 6, 76(1) +; ASM32PWR4-NEXT: li 6, 4 +; ASM32PWR4-NEXT: stw 3, 72(1) +; ASM32PWR4-NEXT: li 3, 1 +; ASM32PWR4-NEXT: stw 4, 68(1) +; ASM32PWR4-NEXT: li 4, 2 +; ASM32PWR4-NEXT: stw 5, 64(1) +; ASM32PWR4-NEXT: li 5, 3 +; ASM32PWR4-NEXT: stw 7, 60(1) +; ASM32PWR4-NEXT: li 7, 5 +; ASM32PWR4-NEXT: stw 12, 92(1) +; ASM32PWR4-NEXT: stw 11, 56(1) +; ASM32PWR4-NEXT: bl .test_ints_stack +; ASM32PWR4-NEXT: nop +; ASM32PWR4-NEXT: addi 1, 1, 96 +; ASM32PWR4-NEXT: lwz 0, 8(1) +; ASM32PWR4-NEXT: mtlr 0 +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: caller_ints_stack: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: mflr 0 +; ASM64PWR4-NEXT: stdu 1, -176(1) +; ASM64PWR4-NEXT: ld 3, L..C9(2) # @si1 +; ASM64PWR4-NEXT: std 0, 192(1) +; ASM64PWR4-NEXT: ld 4, L..C10(2) # @ch +; ASM64PWR4-NEXT: ld 6, L..C11(2) # @ll2 +; ASM64PWR4-NEXT: ld 8, L..C12(2) # @uc1 +; ASM64PWR4-NEXT: ld 9, L..C13(2) # @i1 +; ASM64PWR4-NEXT: li 10, 8 +; ASM64PWR4-NEXT: lha 7, 0(3) +; ASM64PWR4-NEXT: ld 3, L..C14(2) # @ll1 +; ASM64PWR4-NEXT: ld 11, 0(3) +; ASM64PWR4-NEXT: ld 3, L..C15(2) # @ui +; ASM64PWR4-NEXT: lbz 5, 0(4) +; ASM64PWR4-NEXT: ld 4, L..C16(2) # @sint +; ASM64PWR4-NEXT: lwz 3, 0(3) +; ASM64PWR4-NEXT: lwz 4, 0(4) +; ASM64PWR4-NEXT: ld 6, 0(6) +; ASM64PWR4-NEXT: lbz 8, 0(8) +; ASM64PWR4-NEXT: lwz 9, 0(9) +; ASM64PWR4-NEXT: std 9, 168(1) +; ASM64PWR4-NEXT: li 9, 7 +; ASM64PWR4-NEXT: std 8, 160(1) +; ASM64PWR4-NEXT: li 8, 6 +; ASM64PWR4-NEXT: std 6, 152(1) +; ASM64PWR4-NEXT: li 6, 4 +; ASM64PWR4-NEXT: std 4, 144(1) +; ASM64PWR4-NEXT: li 4, 2 +; ASM64PWR4-NEXT: std 3, 136(1) +; ASM64PWR4-NEXT: li 3, 1 +; ASM64PWR4-NEXT: std 5, 128(1) +; ASM64PWR4-NEXT: li 5, 3 +; ASM64PWR4-NEXT: std 7, 120(1) +; ASM64PWR4-NEXT: li 7, 5 +; ASM64PWR4-NEXT: std 11, 112(1) +; ASM64PWR4-NEXT: bl .test_ints_stack +; ASM64PWR4-NEXT: nop +; ASM64PWR4-NEXT: addi 1, 1, 176 +; ASM64PWR4-NEXT: ld 0, 16(1) +; ASM64PWR4-NEXT: mtlr 0 +; ASM64PWR4-NEXT: blr entry: %0 = load i64, ptr @ll1, align 8 %1 = load i16, ptr @si1, align 2 @@ -1481,267 +1394,123 @@ entry: ret void } -; CHECK-LABEL: name: caller_ints_stack - -; 32BIT-DAG: $r3 = LI 1 -; 32BIT-DAG: $r4 = LI 2 -; 32BIT-DAG: $r5 = LI 3 -; 32BIT-DAG: $r6 = LI 4 -; 32BIT-DAG: $r7 = LI 5 -; 32BIT-DAG: $r8 = LI 6 -; 32BIT-DAG: $r9 = LI 7 -; 32BIT-DAG: $r10 = LI 8 -; 32BIT-DAG: renamable $r[[REGLL1ADDR:[0-9]+]] = LWZtoc @ll1, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $r[[REGLL1A:[0-9]+]] = LWZ 0, renamable $r[[REGLL1ADDR]] :: (dereferenceable load (s32) from @ll1, align 8) -; 32BIT-DAG: renamable $r[[REGLL1B:[0-9]+]] = LWZ 4, killed renamable $r[[REGLL1ADDR]] :: (dereferenceable load (s32) from @ll1 + 4, basealign 8) -; 32BIT-DAG: STW killed renamable $r[[REGLL1A]], 56, $r1 :: (store (s32)) -; 32BIT-DAG: STW killed renamable $r[[REGLL1B]], 60, $r1 :: (store (s32)) -; 32BIT-DAG: renamable $r[[REGSIADDR:[0-9]+]] = LWZtoc @si1, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $r[[REGSI:[0-9]+]] = LHA 0, killed renamable $r[[REGSIADDR]] :: (dereferenceable load (s16) from @si1) -; 32BIT-DAG: STW killed renamable $r[[REGSI]], 64, $r1 :: (store (s32)) -; 32BIT-DAG: renamable $r[[REGCHADDR:[0-9]+]] = LWZtoc @ch, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $r[[REGCH:[0-9]+]] = LBZ 0, killed renamable $r[[REGCHADDR]] :: (dereferenceable load (s8) from @ch) -; 32BIT-DAG: STW killed renamable $r[[REGCH]], 68, $r1 :: (store (s32)) -; 32BIT-DAG: renamable $r[[REGUIADDR:[0-9]+]] = LWZtoc @ui, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $r[[REGUI:[0-9]+]] = LWZ 0, killed renamable $r[[REGUIADDR]] :: (dereferenceable load (s32) from @ui) -; 32BIT-DAG: STW killed renamable $r[[REGUI]], 72, $r1 :: (store (s32)) -; 32BIT-DAG: renamable $r[[REGSIADDR:[0-9]+]] = LWZtoc @sint, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $r[[REGSI:[0-9]+]] = LWZ 0, killed renamable $r[[REGSIADDR]] :: (dereferenceable load (s32) from @sint) -; 32BIT-DAG: STW killed renamable $r[[REGSI]], 76, $r1 :: (store (s32)) -; 32BIT-DAG: renamable $r[[REGLL2ADDR:[0-9]+]] = LWZtoc @ll2, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $r[[REGLL2A:[0-9]+]] = LWZ 0, renamable $r[[REGLL2ADDR]] :: (dereferenceable load (s32) from @ll2, align 8) -; 32BIT-DAG: renamable $r[[REGLL2B:[0-9]+]] = LWZ 4, killed renamable $r[[REGLL2ADDR]] :: (dereferenceable load (s32) from @ll2 + 4, basealign 8) -; 32BIT-DAG: STW killed renamable $r[[REGLL2A]], 80, $r1 :: (store (s32)) -; 32BIT-DAG: STW killed renamable $r[[REGLL2B]], 84, $r1 :: (store (s32)) -; 32BIT-DAG: renamable $r[[REGUCADDR:[0-9]+]] = LWZtoc @uc1, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $r[[REGUC:[0-9]+]] = LBZ 0, killed renamable $r[[REGUCADDR]] :: (dereferenceable load (s8) from @uc1) -; 32BIT-DAG: STW killed renamable $r[[REGUC]], 88, $r1 :: (store (s32)) -; 32BIT-DAG: renamable $r[[REGIADDR:[0-9]+]] = LWZtoc @i1, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $r[[REGI:[0-9]+]] = LWZ 0, killed renamable $r[[REGIADDR]] :: (dereferenceable load (s32) from @i1) -; 32BIT-DAG: STW killed renamable $r[[REGI]], 92, $r1 :: (store (s32)) -; 32BIT-DAG: ADJCALLSTACKDOWN 96, 0, implicit-def dead $r1, implicit $r1 -; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1, implicit-def dead $r3 -; 32BIT-NEXT: ADJCALLSTACKUP 96, 0, implicit-def dead $r1, implicit $r1 - -; 64BIT-DAG: $x3 = LI8 1 -; 64BIT-DAG: $x4 = LI8 2 -; 64BIT-DAG: $x5 = LI8 3 -; 64BIT-DAG: $x6 = LI8 4 -; 64BIT-DAG: $x7 = LI8 5 -; 64BIT-DAG: $x8 = LI8 6 -; 64BIT-DAG: $x9 = LI8 7 -; 64BIT-DAG: $x10 = LI8 8 -; 64BIT-DAG: renamable $x[[REGLL1ADDR:[0-9]+]] = LDtoc @ll1, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $x[[REGLL1:[0-9]+]] = LD 0, killed renamable $x[[REGLL1ADDR]] :: (dereferenceable load (s64) from @ll1) -; 64BIT-DAG: STD killed renamable $x[[REGLL1]], 112, $x1 :: (store (s64)) -; 64BIT-DAG: renamable $x[[REGSIADDR:[0-9]+]] = LDtoc @si1, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $x[[REGSI:[0-9]+]] = LHA8 0, killed renamable $x[[REGSIADDR]] :: (dereferenceable load (s16) from @si1) -; 64BIT-DAG: STD killed renamable $x[[REGSI]], 120, $x1 :: (store (s64)) -; 64BIT-DAG: renamable $x[[REGCHADDR:[0-9]+]] = LDtoc @ch, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $x[[REGCH:[0-9]+]] = LBZ8 0, killed renamable $x[[REGCHADDR]] :: (dereferenceable load (s8) from @ch) -; 64BIT-DAG: STD killed renamable $x[[REGCH]], 128, $x1 :: (store (s64)) -; 64BIT-DAG: renamable $x[[REGUIADDR:[0-9]+]] = LDtoc @ui, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $x[[REGUI:[0-9]+]] = LWZ8 0, killed renamable $x[[REGUIADDR]] :: (dereferenceable load (s32) from @ui) -; 64BIT-DAG: STD killed renamable $x[[REGUI]], 136, $x1 :: (store (s64)) -; 64BIT-DAG: renamable $x[[REGSIADDR:[0-9]+]] = LDtoc @sint, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $x[[REGSI:[0-9]+]] = LWZ8 0, killed renamable $x[[REGSIADDR]] :: (dereferenceable load (s32) from @sint) -; 64BIT-DAG: STD killed renamable $x[[REGSI]], 144, $x1 :: (store (s64)) -; 64BIT-DAG: renamable $x[[REGLL2ADDR:[0-9]+]] = LDtoc @ll2, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $x[[REGLL2:[0-9]+]] = LD 0, killed renamable $x[[REGLL2ADDR]] :: (dereferenceable load (s64) from @ll2) -; 64BIT-DAG: STD killed renamable $x[[REGLL2]], 152, $x1 :: (store (s64)) -; 64BIT-DAG: renamable $x[[REGUCADDR:[0-9]+]] = LDtoc @uc1, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $x[[REGUC:[0-9]+]] = LBZ8 0, killed renamable $x[[REGUCADDR]] :: (dereferenceable load (s8) from @uc1) -; 64BIT-DAG: STD killed renamable $x[[REGUC]], 160, $x1 :: (store (s64)) -; 64BIT-DAG: renamable $x[[REGIADDR:[0-9]+]] = LDtoc @i1, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $x[[REGI:[0-9]+]] = LWZ8 0, killed renamable $x[[REGIADDR]] :: (dereferenceable load (s32) from @i1) -; 64BIT-DAG: STD killed renamable $x[[REGI]], 168, $x1 :: (store (s64)) -; 64BIT-DAG: ADJCALLSTACKDOWN 176, 0, implicit-def dead $r1, implicit $r1 -; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1, implicit-def dead $x3 -; 64BIT-NEXT: ADJCALLSTACKUP 176, 0, implicit-def dead $r1, implicit $r1 -; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm - -; CHECKASM-LABEL: .caller_ints_stack: - -; ASM32PWR4: mflr 0 -; ASM32PWR4-NEXT: stwu 1, -96(1) -; ASM32PWR4-DAG: stw 0, 104(1) -; ASM32PWR4-DAG: li 3, 1 -; ASM32PWR4-DAG: li 4, 2 -; ASM32PWR4-DAG: li 5, 3 -; ASM32PWR4-DAG: li 6, 4 -; ASM32PWR4-DAG: li 7, 5 -; ASM32PWR4-DAG: li 9, 7 -; ASM32PWR4-DAG: li 8, 6 -; ASM32PWR4-DAG: li 10, 8 -; ASM32PWR4-DAG: lwz [[REG1:[0-9]+]], L..C10(2) -; ASM32PWR4-DAG: lwz [[REG2:[0-9]+]], L..C11(2) -; ASM32PWR4-DAG: lwz [[REG3:[0-9]+]], L..C12(2) -; ASM32PWR4-DAG: lwz [[REG4:[0-9]+]], L..C13(2) -; ASM32PWR4-DAG: lwz [[REG5:[0-9]+]], L..C14(2) -; ASM32PWR4-DAG: lwz [[REG6:[0-9]+]], L..C15(2) -; ASM32PWR4-DAG: lwz [[REG7:[0-9]+]], L..C16(2) -; ASM32PWR4-DAG: lwz [[REG8:[0-9]+]], L..C17(2) -; ASM32PWR4-DAG: lha 5, 0([[REG1]]) -; ASM32PWR4-DAG: lwz 11, 0([[REG7]]) -; ASM32PWR4-DAG: lwz 7, 4([[REG7]]) -; ASM32PWR4-DAG: lbz 4, 0([[REG2]]) -; ASM32PWR4-DAG: lwz 3, 0([[REG8]]) -; ASM32PWR4-DAG: lwz 6, 0([[REG3]]) -; ASM32PWR4-DAG: lwz 9, 0([[REG4]]) -; ASM32PWR4-DAG: lwz 8, 4([[REG4]]) -; ASM32PWR4-DAG: lbz 10, 0([[REG5]]) -; ASM32PWR4-DAG: lwz 12, 0([[REG6]]) -; ASM32PWR4-DAG: stw 11, 56(1) -; ASM32PWR4-DAG: stw 7, 60(1) -; ASM32PWR4-DAG: stw 5, 64(1) -; ASM32PWR4-DAG: stw 4, 68(1) -; ASM32PWR4-DAG: stw 3, 72(1) -; ASM32PWR4-DAG: stw 6, 76(1) -; ASM32PWR4-DAG: stw 9, 80(1) -; ASM32PWR4-DAG: stw 8, 84(1) -; ASM32PWR4-DAG: stw 10, 88(1) -; ASM32PWR4-DAG: stw 12, 92(1) -; ASM32PWR4-DAG: bl .test_ints_stack -; ASM32PWR4-DAG: nop -; ASM32PWR4-DAG: addi 1, 1, 96 -; ASM32PWR4-DAG: lwz 0, 8(1) -; ASM32PWR4-NEXT: mtlr 0 -; ASM32PWR4-NEXT: blr - -; ASM64PWR4: mflr 0 -; ASM64PWR4-NEXT: stdu 1, -176(1) -; ASM64PWR4-DAG: std 0, 192(1) -; ASM64PWR4-DAG: li 3, 1 -; ASM64PWR4-DAG: li 4, 2 -; ASM64PWR4-DAG: li 5, 3 -; ASM64PWR4-DAG: li 6, 4 -; ASM64PWR4-DAG: li 7, 5 -; ASM64PWR4-DAG: li 8, 6 -; ASM64PWR4-DAG: li 9, 7 -; ASM64PWR4-DAG: li 10, 8 -; ASM64PWR4-DAG: ld [[REG1:[0-9]+]], L..C9(2) -; ASM64PWR4-DAG: ld [[REG2:[0-9]+]], L..C10(2) -; ASM64PWR4-DAG: ld [[REG3:[0-9]+]], L..C11(2) -; ASM64PWR4-DAG: ld [[REG4:[0-9]+]], L..C12(2) -; ASM64PWR4-DAG: ld [[REG5:[0-9]+]], L..C13(2) -; ASM64PWR4-DAG: ld [[REG6:[0-9]+]], L..C14(2) -; ASM64PWR4-DAG: ld [[REG7:[0-9]+]], L..C15(2) -; ASM64PWR4-DAG: ld [[REG8:[0-9]+]], L..C16(2) -; ASM64PWR4-DAG: lha 7, 0([[REG1]]) -; ASM64PWR4-DAG: lbz 5, 0([[REG2]]) -; ASM64PWR4-DAG: ld 6, 0([[REG3]]) -; ASM64PWR4-DAG: lbz 8, 0([[REG4]]) -; ASM64PWR4-DAG: lwz 9, 0([[REG5]]) -; ASM64PWR4-DAG: ld 11, 0([[REG6]]) -; ASM64PWR4-DAG: lwz 3, 0([[REG7]]) -; ASM64PWR4-DAG: lwz 4, 0([[REG8]]) -; ASM64PWR4-DAG: std 11, 112(1) -; ASM64PWR4-DAG: std 7, 120(1) -; ASM64PWR4-DAG: std 5, 128(1) -; ASM64PWR4-DAG: std 3, 136(1) -; ASM64PWR4-DAG: std 4, 144(1) -; ASM64PWR4-DAG: std 6, 152(1) -; ASM64PWR4-DAG: std 8, 160(1) -; ASM64PWR4-DAG: std 9, 168(1) -; ASM64PWR4-NEXT: bl .test_ints_stack -; ASM64PWR4-NEXT: nop -; ASM64PWR4-NEXT: addi 1, 1, 176 -; ASM64PWR4-NEXT: ld 0, 16(1) -; ASM64PWR4-NEXT: mtlr 0 -; ASM64PWR4-NEXT: blr - @globali1 = global i8 0, align 1 define void @test_i1_stack(i32 %a, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, i1 zeroext %b) { +; ASM32PWR4-LABEL: test_i1_stack: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: lbz 3, 59(1) +; ASM32PWR4-NEXT: lwz 4, L..C18(2) # @globali1 +; ASM32PWR4-NEXT: stb 3, 0(4) +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: test_i1_stack: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: lbz 3, 119(1) +; ASM64PWR4-NEXT: ld 4, L..C17(2) # @globali1 +; ASM64PWR4-NEXT: stb 3, 0(4) +; ASM64PWR4-NEXT: blr entry: %frombool = zext i1 %b to i8 store i8 %frombool, ptr @globali1, align 1 ret void } -; CHECK-LABEL: name: test_i1_stack - -; 32BIT-LABEL: fixedStack: -; 32BIT-DAG: - { id: 0, type: default, offset: 59, size: 1 -; 32BIT-DAG: body: | -; 32BIT-DAG: bb.0.entry: -; 32BIT-DAG: renamable $r[[REGB:[0-9]+]] = LBZ 0, %fixed-stack.0 :: (load (s8) from %fixed-stack.0) -; 32BIT-DAG: renamable $r[[REGBTOC:[0-9]+]] = LWZtoc @globali1, $r2 :: (load (s32) from got) -; 32BIT-DAG: STB killed renamable $r[[REGB]], 0, killed renamable $r[[REGBTOC]] :: (store (s8) into @globali1) - -; 64BIT-LABEL: fixedStack: -; 64BIT-DAG: - { id: 0, type: default, offset: 119, size: 1 -; 64BIT-DAG: body: | -; 64BIT-DAG: bb.0.entry: -; 64BIT-DAG: renamable $r[[REGB:[0-9]+]] = LBZ 0, %fixed-stack.0 :: (load (s8) from %fixed-stack.0) -; 64BIT-DAG: renamable $x[[REGBTOC:[0-9]+]] = LDtoc @globali1, $x2 :: (load (s64) from got) -; 64BIT-DAG: STB killed renamable $r[[SCRATCHREG:[0-9]+]], 0, killed renamable $x[[REGBTOC]] :: (store (s8) into @globali1) -; 64BIT-DAG: BLR8 implicit $lr8, implicit $rm - -; CHECKASM-LABEL: test_i1_stack: - -; ASM32PWR4-DAG: lbz [[REGB:[0-9]+]], 59(1) -; ASM32PWR4-DAG: lwz [[REGBTOC:[0-9]+]], L..C18(2) -; ASM32PWR4-DAG: stb [[SCRATCHREG:[0-9]+]], 0([[REGBTOC]]) -; ASM32PWR4-DAG: blr - -; ASM64PWR4-DAG: lbz [[REGB:[0-9]+]], 119(1) -; ASM64PWR4-DAG: ld [[REGBTOC:[0-9]+]], L..C17(2) -; ASM64PWR4-DAG: stb [[SCRATCHREG:[0-9]+]], 0([[REGBTOC]]) -; ASM64PWR4-DAG: blr - define void @call_test_i1_stack() { +; ASM32PWR4-LABEL: call_test_i1_stack: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: mflr 0 +; ASM32PWR4-NEXT: stwu 1, -64(1) +; ASM32PWR4-NEXT: li 11, 1 +; ASM32PWR4-NEXT: li 3, 1 +; ASM32PWR4-NEXT: stw 0, 72(1) +; ASM32PWR4-NEXT: li 4, 2 +; ASM32PWR4-NEXT: li 5, 3 +; ASM32PWR4-NEXT: stw 11, 56(1) +; ASM32PWR4-NEXT: li 6, 4 +; ASM32PWR4-NEXT: li 7, 5 +; ASM32PWR4-NEXT: li 8, 6 +; ASM32PWR4-NEXT: li 9, 7 +; ASM32PWR4-NEXT: li 10, 8 +; ASM32PWR4-NEXT: bl .test_i1_stack +; ASM32PWR4-NEXT: nop +; ASM32PWR4-NEXT: addi 1, 1, 64 +; ASM32PWR4-NEXT: lwz 0, 8(1) +; ASM32PWR4-NEXT: mtlr 0 +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: call_test_i1_stack: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: mflr 0 +; ASM64PWR4-NEXT: stdu 1, -128(1) +; ASM64PWR4-NEXT: li 11, 1 +; ASM64PWR4-NEXT: li 3, 1 +; ASM64PWR4-NEXT: std 0, 144(1) +; ASM64PWR4-NEXT: li 4, 2 +; ASM64PWR4-NEXT: li 5, 3 +; ASM64PWR4-NEXT: std 11, 112(1) +; ASM64PWR4-NEXT: li 6, 4 +; ASM64PWR4-NEXT: li 7, 5 +; ASM64PWR4-NEXT: li 8, 6 +; ASM64PWR4-NEXT: li 9, 7 +; ASM64PWR4-NEXT: li 10, 8 +; ASM64PWR4-NEXT: bl .test_i1_stack +; ASM64PWR4-NEXT: nop +; ASM64PWR4-NEXT: addi 1, 1, 128 +; ASM64PWR4-NEXT: ld 0, 16(1) +; ASM64PWR4-NEXT: mtlr 0 +; ASM64PWR4-NEXT: blr entry: call void @test_i1_stack(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i1 true) ret void } -; CHECK-LABEL: name: call_test_i1_stack - -; 32BIT-DAG: ADJCALLSTACKDOWN 60, 0, implicit-def dead $r1, implicit $r1 -; 32BIT-DAG: $r3 = LI 1 -; 32BIT-DAG: $r4 = LI 2 -; 32BIT-DAG: $r5 = LI 3 -; 32BIT-DAG: $r6 = LI 4 -; 32BIT-DAG: $r7 = LI 5 -; 32BIT-DAG: $r8 = LI 6 -; 32BIT-DAG: $r9 = LI 7 -; 32BIT-DAG: $r10 = LI 8 -; 32BIT-DAG: renamable $r[[REGBOOLADDR:[0-9]+]] = LI 1 -; 32BIT-DAG: STW killed renamable $r[[REGBOOLADDR]], 56, $r1 :: (store (s32)) -; 32BIT-DAG: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1 -; 32BIT-DAG: ADJCALLSTACKUP 60, 0, implicit-def dead $r1, implicit $r1 - -; 64BIT-DAG: ADJCALLSTACKDOWN 120, 0, implicit-def dead $r1, implicit $r1 -; 64BIT-DAG: $x3 = LI8 1 -; 64BIT-DAG: $x4 = LI8 2 -; 64BIT-DAG: $x5 = LI8 3 -; 64BIT-DAG: $x6 = LI8 4 -; 64BIT-DAG: $x7 = LI8 5 -; 64BIT-DAG: $x8 = LI8 6 -; 64BIT-DAG: $x9 = LI8 7 -; 64BIT-DAG: $x10 = LI8 8 -; 64BIT-DAG: renamable $x[[REGBOOLADDR:[0-9]+]] = LI8 1 -; 64BIT-DAG: STD killed renamable $x[[REGBOOLADDR]], 112, $x1 :: (store (s64)) -; 64BIT-DAG: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1 -; 64BIT-DAG: ADJCALLSTACKUP 120, 0, implicit-def dead $r1, implicit $r1 - -; CHECKASM-LABEL: .call_test_i1_stack: - -; ASM32PWR4-DAG: mflr 0 -; ASM32PWR4-DAG: li 3, 1 -; ASM32PWR4-DAG: li 4, 2 -; ASM32PWR4-DAG: li 5, 3 -; ASM32PWR4-DAG: li 6, 4 -; ASM32PWR4-DAG: li 7, 5 -; ASM32PWR4-DAG: li 8, 6 -; ASM32PWR4-DAG: li 9, 7 -; ASM32PWR4-DAG: li 10, 8 -; ASM32PWR4-DAG: stw [[REGB:[0-9]+]], 56(1) -; ASM32PWR4-DAG: li [[REGB]], 1 -; ASM32PWR4-DAG: bl .test_i1 - define double @test_fpr_stack(double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %s10, double %l11, double %d12, double %d13, float %f14, double %d15, float %f16) { +; ASM32PWR4-LABEL: test_fpr_stack: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: fadd 0, 1, 2 +; ASM32PWR4-NEXT: lfs 1, 128(1) +; ASM32PWR4-NEXT: fadd 0, 0, 3 +; ASM32PWR4-NEXT: lfd 2, 132(1) +; ASM32PWR4-NEXT: fadd 0, 0, 4 +; ASM32PWR4-NEXT: fadd 0, 0, 5 +; ASM32PWR4-NEXT: fadd 0, 0, 6 +; ASM32PWR4-NEXT: fadd 0, 0, 7 +; ASM32PWR4-NEXT: fadd 0, 0, 8 +; ASM32PWR4-NEXT: fadd 0, 0, 9 +; ASM32PWR4-NEXT: fadd 0, 0, 10 +; ASM32PWR4-NEXT: fadd 0, 0, 11 +; ASM32PWR4-NEXT: fadd 0, 0, 12 +; ASM32PWR4-NEXT: fadd 0, 0, 13 +; ASM32PWR4-NEXT: fadd 0, 0, 13 +; ASM32PWR4-NEXT: fadd 0, 0, 1 +; ASM32PWR4-NEXT: lfs 1, 140(1) +; ASM32PWR4-NEXT: fadd 0, 0, 2 +; ASM32PWR4-NEXT: fadd 1, 0, 1 +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: test_fpr_stack: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: fadd 0, 1, 2 +; ASM64PWR4-NEXT: lfs 1, 152(1) +; ASM64PWR4-NEXT: fadd 0, 0, 3 +; ASM64PWR4-NEXT: lfd 2, 160(1) +; ASM64PWR4-NEXT: fadd 0, 0, 4 +; ASM64PWR4-NEXT: fadd 0, 0, 5 +; ASM64PWR4-NEXT: fadd 0, 0, 6 +; ASM64PWR4-NEXT: fadd 0, 0, 7 +; ASM64PWR4-NEXT: fadd 0, 0, 8 +; ASM64PWR4-NEXT: fadd 0, 0, 9 +; ASM64PWR4-NEXT: fadd 0, 0, 10 +; ASM64PWR4-NEXT: fadd 0, 0, 11 +; ASM64PWR4-NEXT: fadd 0, 0, 12 +; ASM64PWR4-NEXT: fadd 0, 0, 13 +; ASM64PWR4-NEXT: fadd 0, 0, 13 +; ASM64PWR4-NEXT: fadd 0, 0, 1 +; ASM64PWR4-NEXT: lfs 1, 168(1) +; ASM64PWR4-NEXT: fadd 0, 0, 2 +; ASM64PWR4-NEXT: fadd 1, 0, 1 +; ASM64PWR4-NEXT: blr entry: %add = fadd double %d1, %d2 %add1 = fadd double %add, %d3 @@ -1764,57 +1533,182 @@ define double @test_fpr_stack(double %d1, double %d2, double %d3, double %d4, do ret double %add16 } -; CHECK-LABEL: name: test_fpr_stack{{.*}} - -; CHECK-LABEL: liveins: -; CHECK-DAG: - { reg: '$f1', virtual-reg: '' } -; CHECK-DAG: - { reg: '$f2', virtual-reg: '' } -; CHECK-DAG: - { reg: '$f3', virtual-reg: '' } -; CHECK-DAG: - { reg: '$f4', virtual-reg: '' } -; CHECK-DAG: - { reg: '$f5', virtual-reg: '' } -; CHECK-DAG: - { reg: '$f6', virtual-reg: '' } -; CHECK-DAG: - { reg: '$f7', virtual-reg: '' } -; CHECK-DAG: - { reg: '$f8', virtual-reg: '' } -; CHECK-DAG: - { reg: '$f9', virtual-reg: '' } -; CHECK-DAG: - { reg: '$f10', virtual-reg: '' } -; CHECK-DAG: - { reg: '$f11', virtual-reg: '' } -; CHECK-DAG: - { reg: '$f12', virtual-reg: '' } -; CHECK-DAG: - { reg: '$f13', virtual-reg: '' } - -; CHECK-LABEL: fixedStack: -; 32BIT-DAG: - { id: 2, type: default, offset: 128, size: 4 -; 32BIT-DAG: - { id: 1, type: default, offset: 132, size: 8 -; 32BIT-DAG: - { id: 0, type: default, offset: 140, size: 4 - -; 64BIT-DAG: - { id: 2, type: default, offset: 152, size: 4 -; 64BIT-DAG: - { id: 1, type: default, offset: 160, size: 8 -; 64BIT-DAG: - { id: 0, type: default, offset: 168, size: 4 - -; CHECK-LABEL: body: | -; CHECK-DAG: bb.0.entry: -; CHECK-DAG: liveins: $f1, $f2, $f3, $f4, $f5, $f6, $f7, $f8, $f9, $f10, $f11, $f12, $f13 - -; CHECKASM-LABEL: .test_fpr_stack: - -; ASM32PWR4-DAG: lfs [[REG1:[0-9]+]], 128(1) -; ASM32PWR4-DAG: lfd [[REG2:[0-9]+]], 132(1) -; ASM32PWR4-DAG: lfs [[REG3:[0-9]+]], 140(1) -; ASM32PWR4-DAG: fadd 0, 0, [[REG1]] -; ASM32PWR4-DAG: fadd 0, 0, [[REG2]] -; ASM32PWR4-DAG: fadd 1, 0, [[REG3]] - -; ASM64PWR4-DAG: lfs [[REG1:[0-9]+]], 152(1) -; ASM64PWR4-DAG: lfd [[REG2:[0-9]+]], 160(1) -; ASM64PWR4-DAG: lfs [[REG3:[0-9]+]], 168(1) -; ASM64PWR4-DAG: fadd 0, 0, [[REG1]] -; ASM64PWR4-DAG: fadd 0, 0, [[REG2]] -; ASM64PWR4-DAG: fadd 1, 0, [[REG3]] - @f14 = common global float 0.000000e+00, align 4 @d15 = common global double 0.000000e+00, align 8 @f16 = common global float 0.000000e+00, align 4 define void @caller_fpr_stack() { +; ASM32PWR4-LABEL: caller_fpr_stack: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: mflr 0 +; ASM32PWR4-NEXT: stwu 1, -144(1) +; ASM32PWR4-NEXT: lwz 3, L..C19(2) # @d15 +; ASM32PWR4-NEXT: lwz 4, L..C20(2) # @f14 +; ASM32PWR4-NEXT: lwz 5, L..C21(2) # @f16 +; ASM32PWR4-NEXT: stw 0, 152(1) +; ASM32PWR4-NEXT: lis 6, 16361 +; ASM32PWR4-NEXT: ori 6, 6, 39321 +; ASM32PWR4-NEXT: lfd 0, 0(3) +; ASM32PWR4-NEXT: lwz 3, 0(4) +; ASM32PWR4-NEXT: lwz 4, 0(5) +; ASM32PWR4-NEXT: li 5, 0 +; ASM32PWR4-NEXT: stw 5, 60(1) +; ASM32PWR4-NEXT: lis 5, 16352 +; ASM32PWR4-NEXT: stw 5, 56(1) +; ASM32PWR4-NEXT: lis 5, 13107 +; ASM32PWR4-NEXT: ori 5, 5, 13107 +; ASM32PWR4-NEXT: stw 5, 68(1) +; ASM32PWR4-NEXT: lis 5, 16355 +; ASM32PWR4-NEXT: ori 5, 5, 13107 +; ASM32PWR4-NEXT: stw 5, 64(1) +; ASM32PWR4-NEXT: lis 5, 26214 +; ASM32PWR4-NEXT: ori 5, 5, 26214 +; ASM32PWR4-NEXT: stw 5, 76(1) +; ASM32PWR4-NEXT: lis 5, 16358 +; ASM32PWR4-NEXT: ori 5, 5, 26214 +; ASM32PWR4-NEXT: stw 5, 72(1) +; ASM32PWR4-NEXT: lis 5, -26215 +; ASM32PWR4-NEXT: ori 5, 5, 39322 +; ASM32PWR4-NEXT: stw 5, 84(1) +; ASM32PWR4-NEXT: stw 5, 100(1) +; ASM32PWR4-NEXT: lis 5, 16313 +; ASM32PWR4-NEXT: ori 5, 5, 39321 +; ASM32PWR4-NEXT: stw 5, 96(1) +; ASM32PWR4-NEXT: lis 5, -15729 +; ASM32PWR4-NEXT: ori 5, 5, 23593 +; ASM32PWR4-NEXT: stw 5, 108(1) +; ASM32PWR4-NEXT: lis 5, 16316 +; ASM32PWR4-NEXT: ori 5, 5, 10485 +; ASM32PWR4-NEXT: stw 5, 104(1) +; ASM32PWR4-NEXT: lis 5, -5243 +; ASM32PWR4-NEXT: ori 5, 5, 7864 +; ASM32PWR4-NEXT: stw 5, 116(1) +; ASM32PWR4-NEXT: lis 5, 16318 +; ASM32PWR4-NEXT: ori 5, 5, 47185 +; ASM32PWR4-NEXT: stw 6, 80(1) +; ASM32PWR4-NEXT: lis 6, -13108 +; ASM32PWR4-NEXT: ori 6, 6, 52429 +; ASM32PWR4-NEXT: stw 5, 112(1) +; ASM32PWR4-NEXT: lis 5, 2621 +; ASM32PWR4-NEXT: ori 5, 5, 28836 +; ASM32PWR4-NEXT: stw 6, 92(1) +; ASM32PWR4-NEXT: lis 6, 16364 +; ASM32PWR4-NEXT: ori 6, 6, 52428 +; ASM32PWR4-NEXT: stw 5, 124(1) +; ASM32PWR4-NEXT: lis 5, 16320 +; ASM32PWR4-NEXT: ori 5, 5, 41943 +; ASM32PWR4-NEXT: stw 6, 88(1) +; ASM32PWR4-NEXT: lwz 6, L..C22(2) # %const.0 +; ASM32PWR4-NEXT: stw 5, 120(1) +; ASM32PWR4-NEXT: lwz 5, L..C23(2) # %const.1 +; ASM32PWR4-NEXT: lfd 2, 0(6) +; ASM32PWR4-NEXT: lwz 6, L..C24(2) # %const.2 +; ASM32PWR4-NEXT: lfd 3, 0(5) +; ASM32PWR4-NEXT: lwz 5, L..C25(2) # %const.3 +; ASM32PWR4-NEXT: lfd 4, 0(6) +; ASM32PWR4-NEXT: lwz 6, L..C26(2) # %const.4 +; ASM32PWR4-NEXT: lfd 6, 0(5) +; ASM32PWR4-NEXT: lwz 5, L..C27(2) # %const.5 +; ASM32PWR4-NEXT: lfd 7, 0(6) +; ASM32PWR4-NEXT: lwz 6, L..C28(2) # %const.6 +; ASM32PWR4-NEXT: lfd 8, 0(5) +; ASM32PWR4-NEXT: lwz 5, L..C29(2) # %const.7 +; ASM32PWR4-NEXT: lfd 9, 0(6) +; ASM32PWR4-NEXT: lwz 6, L..C30(2) # %const.8 +; ASM32PWR4-NEXT: lfd 1, 0(5) +; ASM32PWR4-NEXT: lwz 5, L..C31(2) # %const.9 +; ASM32PWR4-NEXT: lfd 11, 0(6) +; ASM32PWR4-NEXT: lwz 6, L..C32(2) # %const.10 +; ASM32PWR4-NEXT: fmr 10, 1 +; ASM32PWR4-NEXT: lfd 12, 0(5) +; ASM32PWR4-NEXT: lwz 5, L..C33(2) # %const.11 +; ASM32PWR4-NEXT: lfd 13, 0(6) +; ASM32PWR4-NEXT: lfs 5, 0(5) +; ASM32PWR4-NEXT: stfd 0, 132(1) +; ASM32PWR4-NEXT: stw 4, 140(1) +; ASM32PWR4-NEXT: stw 3, 128(1) +; ASM32PWR4-NEXT: bl .test_fpr_stack +; ASM32PWR4-NEXT: nop +; ASM32PWR4-NEXT: addi 1, 1, 144 +; ASM32PWR4-NEXT: lwz 0, 8(1) +; ASM32PWR4-NEXT: mtlr 0 +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: caller_fpr_stack: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: mflr 0 +; ASM64PWR4-NEXT: stdu 1, -176(1) +; ASM64PWR4-NEXT: ld 3, L..C18(2) # @f14 +; ASM64PWR4-NEXT: std 0, 192(1) +; ASM64PWR4-NEXT: ld 4, L..C19(2) # @d15 +; ASM64PWR4-NEXT: ld 5, L..C20(2) # @f16 +; ASM64PWR4-NEXT: ld 6, L..C21(2) # %const.9 +; ASM64PWR4-NEXT: lis 7, 16313 +; ASM64PWR4-NEXT: lwz 3, 0(3) +; ASM64PWR4-NEXT: ld 4, 0(4) +; ASM64PWR4-NEXT: lwz 5, 0(5) +; ASM64PWR4-NEXT: stw 3, 152(1) +; ASM64PWR4-NEXT: ld 3, L..C22(2) # %const.0 +; ASM64PWR4-NEXT: std 4, 160(1) +; ASM64PWR4-NEXT: ld 4, L..C23(2) # %const.1 +; ASM64PWR4-NEXT: lfd 2, 0(3) +; ASM64PWR4-NEXT: ld 3, L..C24(2) # %const.2 +; ASM64PWR4-NEXT: lfd 3, 0(4) +; ASM64PWR4-NEXT: ld 4, L..C25(2) # %const.3 +; ASM64PWR4-NEXT: lfd 4, 0(3) +; ASM64PWR4-NEXT: ld 3, L..C26(2) # %const.4 +; ASM64PWR4-NEXT: lfd 6, 0(4) +; ASM64PWR4-NEXT: ld 4, L..C27(2) # %const.5 +; ASM64PWR4-NEXT: lfd 7, 0(3) +; ASM64PWR4-NEXT: ld 3, L..C28(2) # %const.6 +; ASM64PWR4-NEXT: lfd 8, 0(4) +; ASM64PWR4-NEXT: ld 4, L..C29(2) # %const.7 +; ASM64PWR4-NEXT: lfd 9, 0(3) +; ASM64PWR4-NEXT: ld 3, L..C30(2) # %const.8 +; ASM64PWR4-NEXT: lfd 1, 0(4) +; ASM64PWR4-NEXT: lis 4, 16320 +; ASM64PWR4-NEXT: ori 4, 4, 41943 +; ASM64PWR4-NEXT: rldic 4, 4, 32, 2 +; ASM64PWR4-NEXT: lfd 11, 0(3) +; ASM64PWR4-NEXT: lis 3, 16316 +; ASM64PWR4-NEXT: fmr 10, 1 +; ASM64PWR4-NEXT: ori 3, 3, 10485 +; ASM64PWR4-NEXT: oris 4, 4, 2621 +; ASM64PWR4-NEXT: stw 5, 168(1) +; ASM64PWR4-NEXT: lis 5, 16318 +; ASM64PWR4-NEXT: rldic 3, 3, 32, 2 +; ASM64PWR4-NEXT: ori 5, 5, 47185 +; ASM64PWR4-NEXT: ori 4, 4, 28836 +; ASM64PWR4-NEXT: lfd 12, 0(6) +; ASM64PWR4-NEXT: ld 6, L..C31(2) # %const.10 +; ASM64PWR4-NEXT: oris 3, 3, 49807 +; ASM64PWR4-NEXT: ori 3, 3, 23593 +; ASM64PWR4-NEXT: std 4, 144(1) +; ASM64PWR4-NEXT: rldic 4, 5, 32, 2 +; ASM64PWR4-NEXT: oris 4, 4, 60293 +; ASM64PWR4-NEXT: ori 4, 4, 7864 +; ASM64PWR4-NEXT: std 3, 128(1) +; ASM64PWR4-NEXT: ld 3, L..C32(2) # %const.11 +; ASM64PWR4-NEXT: ori 5, 7, 39321 +; ASM64PWR4-NEXT: rldic 5, 5, 32, 2 +; ASM64PWR4-NEXT: std 4, 136(1) +; ASM64PWR4-NEXT: lis 4, 4091 +; ASM64PWR4-NEXT: ori 4, 4, 13107 +; ASM64PWR4-NEXT: rldic 4, 4, 34, 2 +; ASM64PWR4-NEXT: lfs 5, 0(3) +; ASM64PWR4-NEXT: oris 3, 5, 39321 +; ASM64PWR4-NEXT: ori 3, 3, 39322 +; ASM64PWR4-NEXT: lfd 13, 0(6) +; ASM64PWR4-NEXT: std 3, 120(1) +; ASM64PWR4-NEXT: oris 3, 4, 52428 +; ASM64PWR4-NEXT: ori 3, 3, 52429 +; ASM64PWR4-NEXT: std 3, 112(1) +; ASM64PWR4-NEXT: bl .test_fpr_stack +; ASM64PWR4-NEXT: nop +; ASM64PWR4-NEXT: addi 1, 1, 176 +; ASM64PWR4-NEXT: ld 0, 16(1) +; ASM64PWR4-NEXT: mtlr 0 +; ASM64PWR4-NEXT: blr entry: %0 = load float, ptr @f14, align 4 %1 = load double, ptr @d15, align 8 @@ -1823,152 +1717,60 @@ entry: ret void } -; CHECK-LABEL: caller_fpr_stack - -; 32BIT-DAG: renamable $r[[SCRATCHREG:[0-9]+]] = LWZtoc %const.0, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $r[[SCRATCHREG:[0-9]+]] = LWZtoc %const.1, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $r[[SCRATCHREG:[0-9]+]] = LWZtoc %const.2, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $r[[SCRATCHREG:[0-9]+]] = LWZtoc %const.3, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $r[[SCRATCHREG:[0-9]+]] = LWZtoc %const.4, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $r[[SCRATCHREG:[0-9]+]] = LWZtoc %const.5, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $r[[SCRATCHREG:[0-9]+]] = LWZtoc %const.6, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $r[[SCRATCHREG:[0-9]+]] = LWZtoc %const.7, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $r[[SCRATCHREG:[0-9]+]] = LWZtoc %const.8, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $r[[SCRATCHREG:[0-9]+]] = LWZtoc %const.9, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $r[[SCRATCHREG:[0-9]+]] = LWZtoc %const.10, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $r[[SCRATCHREG:[0-9]+]] = LWZtoc %const.11, $r2 :: (load (s32) from got) -; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 56, $r1 :: (store (s32), align 8) -; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 60, $r1 :: (store (s32) into unknown-address + 4, basealign 8) -; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 64, $r1 :: (store (s32), align 8) -; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 68, $r1 :: (store (s32) into unknown-address + 4, basealign 8) -; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 72, $r1 :: (store (s32), align 8) -; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 76, $r1 :: (store (s32) into unknown-address + 4, basealign 8) -; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 80, $r1 :: (store (s32), align 8) -; 32BIT-DAG: STW renamable $r[[SCRATCHREG:[0-9]+]], 84, $r1 :: (store (s32) into unknown-address + 4, basealign 8) -; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 88, $r1 :: (store (s32), align 8) -; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 92, $r1 :: (store (s32) into unknown-address + 4, basealign 8) -; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 96, $r1 :: (store (s32), align 8) -; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 100, $r1 :: (store (s32) into unknown-address + 4, basealign 8) -; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 104, $r1 :: (store (s32), align 8) -; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 108, $r1 :: (store (s32) into unknown-address + 4, basealign 8) -; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 112, $r1 :: (store (s32), align 8) -; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 116, $r1 :: (store (s32) into unknown-address + 4, basealign 8) -; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 120, $r1 :: (store (s32), align 8) -; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 124, $r1 :: (store (s32) into unknown-address + 4, basealign 8) -; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 128, $r1 :: (store (s32)) -; 32BIT-DAG: renamable $r[[REGF1:[0-9]+]] = LWZtoc @f14, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REGF1]] :: (load (s32) from @f14) -; 32BIT-DAG: STFD killed renamable $f0, 132, $r1 :: (store (s64)) -; 32BIT-DAG: renamable $r[[REGD:[0-9]+]] = LWZtoc @d15, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $f0 = LFD 0, killed renamable $r[[REGD]] :: (dereferenceable load (s64) from @d15) -; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 140, $r1 :: (store (s32)) -; 32BIT-DAG: renamable $r[[REGF2:[0-9]+]] = LWZtoc @f16, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $r[[SCRATCHREG:[0-9]+]] = LWZ 0, killed renamable $r[[REGF2]] :: (load (s32) from @f16) -; 32BIT-DAG: renamable $f1 = LFD 0, killed renamable $r[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool) -; 32BIT-DAG: renamable $f2 = LFD 0, killed renamable $r[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool) -; 32BIT-DAG: renamable $f3 = LFD 0, killed renamable $r[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool) -; 32BIT-DAG: renamable $f4 = LFD 0, killed renamable $r[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool) -; 32BIT-DAG: renamable $f5 = LFS 0, killed renamable $r[[SCRATCHREG:[0-9]+]] :: (load (s32) from constant-pool) -; 32BIT-DAG: renamable $f6 = LFD 0, killed renamable $r[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool) -; 32BIT-DAG: renamable $f7 = LFD 0, killed renamable $r[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool) -; 32BIT-DAG: renamable $f8 = LFD 0, killed renamable $r[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool) -; 32BIT-DAG: renamable $f9 = LFD 0, killed renamable $r[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool) -; 32BIT-DAG: $f10 = COPY renamable $f1 -; 32BIT-DAG: renamable $f11 = LFD 0, killed renamable $r[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool) -; 32BIT-DAG: renamable $f12 = LFD 0, killed renamable $r[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool) -; 32BIT-DAG: renamable $f13 = LFD 0, killed renamable $r[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool) -; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit killed $f10, implicit $f11, implicit $f12, implicit $f13, implicit $r2, implicit-def $r1, implicit-def dead $f1 -; 32BIT-NEXT: ADJCALLSTACKUP 144, 0, implicit-def dead $r1, implicit $r1 - -; 64BIT-DAG: renamable $x[[SCRATCHREG:[0-9]+]] = LDtocCPT %const.0, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $x[[SCRATCHREG:[0-9]+]] = LDtocCPT %const.1, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $x[[SCRATCHREG:[0-9]+]] = LDtocCPT %const.2, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $x[[SCRATCHREG:[0-9]+]] = LDtocCPT %const.[[SCRATCHREG:[0-9]+]], $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $x[[SCRATCHREG:[0-9]+]] = LDtocCPT %const.4, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $x[[SCRATCHREG:[0-9]+]] = LDtocCPT %const.5, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $x[[SCRATCHREG:[0-9]+]] = LDtocCPT %const.6, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $x[[SCRATCHREG:[0-9]+]] = LDtocCPT %const.7, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $x[[SCRATCHREG:[0-9]+]] = LDtocCPT %const.8, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $x[[SCRATCHREG:[0-9]+]] = LDtocCPT %const.9, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $x[[SCRATCHREG:[0-9]+]] = LDtocCPT %const.10, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $x[[REGF1:[0-9]+]] = LDtoc @f14, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $r3 = LWZ 0, killed renamable $x[[REGF1]] :: (load (s32) from @f14) -; 64BIT-DAG: renamable $x[[REGF2:[0-9]+]] = LDtoc @f16, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $r5 = LWZ 0, killed renamable $x[[REGF2]] :: (load (s32) from @f16) -; 64BIT-DAG: renamable $x[[REGD:[0-9]+]] = LDtoc @d15, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $x4 = LD 0, killed renamable $x[[REGD]] :: (load (s64) from @d15) -; 64BIT-DAG: ADJCALLSTACKDOWN 176, 0, implicit-def dead $r1, implicit $r1 -; 64BIT-DAG: renamable $f1 = LFD 0, killed renamable $x[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool) -; 64BIT-DAG: renamable $f2 = LFD 0, killed renamable $x[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool) -; 64BIT-DAG: renamable $f[[SCRATCHREG:[0-9]+]] = LFD 0, killed renamable $x[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool) -; 64BIT-DAG: renamable $f4 = LFD 0, killed renamable $x[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool) -; 64BIT-DAG: renamable $f5 = LFS 0, killed renamable $x[[SCRATCHREG:[0-9]+]] :: (load (s32) from constant-pool) -; 64BIT-DAG: renamable $f6 = LFD 0, killed renamable $x[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool) -; 64BIT-DAG: renamable $f7 = LFD 0, killed renamable $x[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool) -; 64BIT-DAG: renamable $f8 = LFD 0, killed renamable $x[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool) -; 64BIT-DAG: renamable $f9 = LFD 0, killed renamable $x[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool) -; 64BIT-DAG: $f10 = COPY renamable $f1 -; 64BIT-DAG: renamable $f11 = LFD 0, killed renamable $x[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool) -; 64BIT-DAG: renamable $f12 = LFD 0, killed renamable $x[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool) -; 64BIT-DAG: renamable $f13 = LFD 0, killed renamable $x[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool) -; 64BIT-DAG: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit killed $f10, implicit $f11, implicit $f12, implicit $f13, implicit $x2, implicit-def $r1, implicit-def dead $f1 -; 64BIT-NEXT: ADJCALLSTACKUP 176, 0, implicit-def dead $r1, implicit $r1 -; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm - -; CHECKASM-LABEL: .caller_fpr_stack: - -; ASM32PWR4: mflr 0 -; ASM32PWR4-NEXT: stwu 1, -144(1) -; ASM32PWR4-DAG: stw 0, 152(1) -; ASM32PWR4-DAG: lwz [[REGF1ADDR:[0-9]+]], L..C20(2) -; ASM32PWR4-DAG: lwz [[REGF1:[0-9]+]], 0([[REGF1ADDR]]) -; ASM32PWR4-DAG: lwz [[REGDADDR:[0-9]+]], L..C19(2) -; ASM32PWR4-DAG: lfd [[REGD:[0-9]+]], 0([[REGDADDR]]) -; ASM32PWR4-DAG: lwz [[REGF2ADDR:[0-9]+]], L..C21(2) -; ASM32PWR4-DAG: lwz [[REGF2:[0-9]+]], 0([[REGF2ADDR]]) -; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 56(1) -; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 60(1) -; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 64(1) -; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 68(1) -; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 72(1) -; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 76(1) -; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 80(1) -; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 84(1) -; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 88(1) -; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 92(1) -; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 96(1) -; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 100(1) -; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 108(1) -; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 104(1) -; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 112(1) -; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 116(1) -; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 120(1) -; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 124(1) -; ASM32PWR4-DAG: stw [[REGF1]], 128(1) -; ASM32PWR4-DAG: stfd [[REGD]], 132(1) -; ASM32PWR4-DAG: stw [[REGF2]], 140(1) -; ASM32PWR4-NEXT: bl .test_fpr_stack - -; ASM64PWR4: mflr 0 -; ASM64PWR4-NEXT: stdu 1, -176(1) -; ASM64PWR4-DAG: std 0, 192(1) -; ASM64PWR4-DAG: ld [[REGF1ADDR:[0-9]+]], L..C18(2) -; ASM64PWR4-DAG: lwz [[REGF1:[0-9]+]], 0([[REGF1ADDR]]) -; ASM64PWR4-DAG: ld [[REGDADDR:[0-9]+]], L..C19(2) -; ASM64PWR4-DAG: ld [[REGD:[0-9]+]], 0([[REGDADDR]]) -; ASM64PWR4-DAG: ld [[REGF2ADDR:[0-9]+]], L..C20(2) -; ASM64PWR4-DAG: lwz [[REGF2:[0-9]+]], 0([[REGF2ADDR]]) -; ASM64PWR4-DAG: std [[SCRATCHREG:[0-9]+]], 112(1) -; ASM64PWR4-DAG: std [[SCRATCHREG:[0-9]+]], 120(1) -; ASM64PWR4-DAG: std [[SCRATCHREG:[0-9]+]], 128(1) -; ASM64PWR4-DAG: std [[SCRATCHREG:[0-9]+]], 136(1) -; ASM64PWR4-DAG: std [[SCRATCHREG:[0-9]+]], 144(1) -; ASM64PWR4-DAG: stw [[REGF1]], 152(1) -; ASM64PWR4-DAG: std [[REGD]], 160(1) -; ASM64PWR4-DAG: stw [[REGF2]], 168(1) -; ASM64PWR4-NEXT: bl .test_fpr_stack - define i32 @mix_callee(double %d1, double %d2, double %d3, double %d4, i8 zeroext %c1, i16 signext %s1, i64 %ll1, i32 %i1, i32 %i2, i32 %i3) { +; ASM32PWR4-LABEL: mix_callee: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: lwz 4, 60(1) +; ASM32PWR4-NEXT: lis 8, 17200 +; ASM32PWR4-NEXT: fadd 1, 1, 2 +; ASM32PWR4-NEXT: fadd 1, 1, 3 +; ASM32PWR4-NEXT: lwz 5, 56(1) +; ASM32PWR4-NEXT: lwz 3, 68(1) +; ASM32PWR4-NEXT: add 4, 5, 4 +; ASM32PWR4-NEXT: lwz 5, L..C34(2) # %const.0 +; ASM32PWR4-NEXT: fadd 1, 1, 4 +; ASM32PWR4-NEXT: lwz 6, 72(1) +; ASM32PWR4-NEXT: add 3, 4, 3 +; ASM32PWR4-NEXT: lwz 7, 76(1) +; ASM32PWR4-NEXT: add 3, 3, 6 +; ASM32PWR4-NEXT: stw 8, -16(1) +; ASM32PWR4-NEXT: add 3, 3, 7 +; ASM32PWR4-NEXT: lwz 8, 80(1) +; ASM32PWR4-NEXT: add 3, 3, 8 +; ASM32PWR4-NEXT: lfs 0, 0(5) +; ASM32PWR4-NEXT: xoris 3, 3, 32768 +; ASM32PWR4-NEXT: stw 3, -12(1) +; ASM32PWR4-NEXT: addi 3, 1, -4 +; ASM32PWR4-NEXT: lfd 2, -16(1) +; ASM32PWR4-NEXT: fsub 0, 2, 0 +; ASM32PWR4-NEXT: fadd 0, 0, 1 +; ASM32PWR4-NEXT: fctiwz 0, 0 +; ASM32PWR4-NEXT: stfiwx 0, 0, 3 +; ASM32PWR4-NEXT: lwz 3, -4(1) +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: mix_callee: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: lwz 3, 116(1) +; ASM64PWR4-NEXT: add 4, 7, 8 +; ASM64PWR4-NEXT: fadd 0, 1, 2 +; ASM64PWR4-NEXT: add 4, 4, 9 +; ASM64PWR4-NEXT: fadd 0, 0, 3 +; ASM64PWR4-NEXT: add 4, 4, 10 +; ASM64PWR4-NEXT: lwz 5, 124(1) +; ASM64PWR4-NEXT: add 3, 4, 3 +; ASM64PWR4-NEXT: add 3, 3, 5 +; ASM64PWR4-NEXT: fadd 0, 0, 4 +; ASM64PWR4-NEXT: extsw 3, 3 +; ASM64PWR4-NEXT: std 3, -16(1) +; ASM64PWR4-NEXT: addi 3, 1, -4 +; ASM64PWR4-NEXT: lfd 1, -16(1) +; ASM64PWR4-NEXT: fcfid 1, 1 +; ASM64PWR4-NEXT: fadd 0, 1, 0 +; ASM64PWR4-NEXT: fctiwz 0, 0 +; ASM64PWR4-NEXT: stfiwx 0, 0, 3 +; ASM64PWR4-NEXT: lwz 3, -4(1) +; ASM64PWR4-NEXT: blr entry: %add = fadd double %d1, %d2 %add1 = fadd double %add, %d3 @@ -1991,137 +1793,149 @@ define i32 @mix_callee(double %d1, double %d2, double %d3, double %d4, i8 zeroex ret i32 %conv16 } -; CHECK-LABEL: mix_callee - -; 32BIT-LABEL: liveins: -; 32BIT-DAG: - { reg: '$f1', virtual-reg: '' } -; 32BIT-DAG: - { reg: '$f2', virtual-reg: '' } -; 32BIT-DAG: - { reg: '$f3', virtual-reg: '' } -; 32BIT-DAG: - { reg: '$f4', virtual-reg: '' } - -; 32BIT-LABEL: fixedStack: -; 32BIT-DAG: - { id: 6, type: default, offset: 56, size: 4 -; 32BIT-DAG: - { id: 5, type: default, offset: 60, size: 4 -; 32BIT-DAG: - { id: 4, type: default, offset: 64, size: 4 -; 32BIT-DAG: - { id: 3, type: default, offset: 68, size: 4 -; 32BIT-DAG: - { id: 2, type: default, offset: 72, size: 4 -; 32BIT-DAG: - { id: 1, type: default, offset: 76, size: 4 -; 32BIT-DAG: - { id: 0, type: default, offset: 80, size: 4 - -; 32BIT-LABEL: body: | -; 32BIT-DAG: bb.0.entry: -; 32BIT-DAG: liveins: $f1, $f2, $f3, $f4 - -; 64BIT-LABEL: liveins: -; 64BIT-DAG: - { reg: '$f1', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$f2', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$f3', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$f4', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$x7', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$x8', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$x9', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$x10', virtual-reg: '' } - -; 64BIT-LABEL: fixedStack: -; 64BIT-DAG: - { id: 1, type: default, offset: 116, size: 4 -; 64BIT-DAG: - { id: 0, type: default, offset: 124, size: 4 - -; 64BIT-LABEL: body: | -; 64BIT-DAG: bb.0.entry: -; 64BIT-DAG: liveins: $f1, $f2, $f3, $f4, $x7, $x8, $x9, $x10 - -; CHECKASM-LABEL: .mix_callee - -; ASM32PWR4-DAG: lwz [[REG1:[0-9]+]], 56(1) -; ASM32PWR4-DAG: lwz [[REG2:[0-9]+]], 60(1) -; ASM32PWR4-DAG: lwz [[REG4:[0-9]+]], 68(1) -; ASM32PWR4-DAG: lwz [[REG5:[0-9]+]], 72(1) -; ASM32PWR4-DAG: lwz [[REG6:[0-9]+]], 76(1) -; ASM32PWR4-DAG: lwz [[REG7:[0-9]+]], 80(1) -; ASM32PWR4-DAG: blr - -; ASM64PWR-DAG: ld [[REG1:[0-9]+]], 112(1) -; ASM64PWR-DAG: ld [[REG2:[0-9]+]], 120(1) -; ASM64PWR-DAG: fadd 0, 0, [[REG1]] -; ASM64PWR-DAG: add 3, 3, [[REG2]] -; ASM64PWR-DAG: blr - define void @caller_mix() { +; ASM32PWR4-LABEL: caller_mix: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: mflr 0 +; ASM32PWR4-NEXT: stwu 1, -96(1) +; ASM32PWR4-NEXT: li 3, 60 +; ASM32PWR4-NEXT: stw 0, 104(1) +; ASM32PWR4-NEXT: stw 3, 80(1) +; ASM32PWR4-NEXT: li 3, 50 +; ASM32PWR4-NEXT: stw 3, 76(1) +; ASM32PWR4-NEXT: li 3, 40 +; ASM32PWR4-NEXT: stw 3, 72(1) +; ASM32PWR4-NEXT: li 3, 0 +; ASM32PWR4-NEXT: stw 3, 64(1) +; ASM32PWR4-NEXT: li 3, 2 +; ASM32PWR4-NEXT: stw 3, 60(1) +; ASM32PWR4-NEXT: lwz 3, L..C35(2) # %const.0 +; ASM32PWR4-NEXT: lfd 1, 0(3) +; ASM32PWR4-NEXT: lwz 3, L..C36(2) # %const.1 +; ASM32PWR4-NEXT: lfd 2, 0(3) +; ASM32PWR4-NEXT: lwz 3, L..C37(2) # %const.2 +; ASM32PWR4-NEXT: lfd 3, 0(3) +; ASM32PWR4-NEXT: lwz 3, L..C38(2) # %const.3 +; ASM32PWR4-NEXT: lfd 4, 0(3) +; ASM32PWR4-NEXT: li 3, 1 +; ASM32PWR4-NEXT: stw 3, 56(1) +; ASM32PWR4-NEXT: lis 3, 457 +; ASM32PWR4-NEXT: ori 3, 3, 50048 +; ASM32PWR4-NEXT: stw 3, 68(1) +; ASM32PWR4-NEXT: bl .mix_callee +; ASM32PWR4-NEXT: nop +; ASM32PWR4-NEXT: addi 1, 1, 96 +; ASM32PWR4-NEXT: lwz 0, 8(1) +; ASM32PWR4-NEXT: mtlr 0 +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: caller_mix: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: mflr 0 +; ASM64PWR4-NEXT: stdu 1, -128(1) +; ASM64PWR4-NEXT: ld 3, L..C33(2) # %const.0 +; ASM64PWR4-NEXT: ld 4, L..C34(2) # %const.1 +; ASM64PWR4-NEXT: lis 5, 457 +; ASM64PWR4-NEXT: li 7, 1 +; ASM64PWR4-NEXT: std 0, 144(1) +; ASM64PWR4-NEXT: ori 9, 5, 50048 +; ASM64PWR4-NEXT: li 8, 2 +; ASM64PWR4-NEXT: lfd 1, 0(3) +; ASM64PWR4-NEXT: ld 3, L..C35(2) # %const.2 +; ASM64PWR4-NEXT: li 10, 40 +; ASM64PWR4-NEXT: lfd 2, 0(4) +; ASM64PWR4-NEXT: ld 4, L..C36(2) # %const.3 +; ASM64PWR4-NEXT: lfd 3, 0(3) +; ASM64PWR4-NEXT: li 3, 60 +; ASM64PWR4-NEXT: lfd 4, 0(4) +; ASM64PWR4-NEXT: li 4, 50 +; ASM64PWR4-NEXT: std 3, 120(1) +; ASM64PWR4-NEXT: std 4, 112(1) +; ASM64PWR4-NEXT: bl .mix_callee +; ASM64PWR4-NEXT: nop +; ASM64PWR4-NEXT: addi 1, 1, 128 +; ASM64PWR4-NEXT: ld 0, 16(1) +; ASM64PWR4-NEXT: mtlr 0 +; ASM64PWR4-NEXT: blr entry: %call = call i32 @mix_callee(double 1.000000e-01, double 2.000000e-01, double 3.000000e-01, double 4.000000e-01, i8 zeroext 1, i16 signext 2, i64 30000000, i32 40, i32 50, i32 60) ret void } -; CHECK-LABEL: name: caller_mix - -; 32BIT-DAG: ADJCALLSTACKDOWN 84, 0, implicit-def dead $r1, implicit $r1 -; 32BIT-DAG: renamable $r[[SCRATCHREG:[0-9]+]] = LWZtoc %const.0, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $f1 = LFD 0, killed renamable $r[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool) -; 32BIT-DAG: renamable $r[[SCRATCHREG:[0-9]+]] = LWZtoc %const.1, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $f2 = LFD 0, killed renamable $r[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool) -; 32BIT-DAG: renamable $r[[SCRATCHREG:[0-9]+]] = LWZtoc %const.2, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $f3 = LFD 0, killed renamable $r[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool) -; 32BIT-DAG: renamable $r[[SCRATCHREG:[0-9]+]] = LWZtoc %const.3, $r2 :: (load (s32) from got) -; 32BIT-DAG: renamable $f4 = LFD 0, killed renamable $r[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool) -; 32BIT-DAG: renamable $r[[SCRATCHREG:[0-9]+]] = LI 1 -; 32BIT-DAG: renamable $r[[SCRATCHREG:[0-9]+]] = LI 2 -; 32BIT-DAG: renamable $r[[SCRATCHREG:[0-9]+]] = LIS 457 -; 32BIT-DAG: renamable $r[[SCRATCHREG:[0-9]+]] = LI 0 -; 32BIT-DAG: renamable $r[[SCRATCHREG:[0-9]+]] = LI 40 -; 32BIT-DAG: renamable $r[[SCRATCHREG:[0-9]+]] = LI 50 -; 32BIT-DAG: renamable $r[[SCRATCHREG:[0-9]+]] = LI 60 -; 32BIT-DAG: STW killed renamable $r[[REG1:[0-9]+]], 56, $r1 :: (store (s32)) -; 32BIT-DAG: STW killed renamable $r[[REG2:[0-9]+]], 60, $r1 :: (store (s32)) -; 32BIT-DAG: STW killed renamable $r[[REG3:[0-9]+]], 64, $r1 :: (store (s32)) -; 32BIT-DAG: STW killed renamable $r[[REG4:[0-9]+]], 68, $r1 :: (store (s32)) -; 32BIT-DAG: STW killed renamable $r[[REG5:[0-9]+]], 72, $r1 :: (store (s32)) -; 32BIT-DAG: STW killed renamable $r[[REG6:[0-9]+]], 76, $r1 :: (store (s32)) -; 32BIT-DAG: STW killed renamable $r[[REG7:[0-9]+]], 80, $r1 :: (store (s32)) -; 32BIT-DAG: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $r2, implicit-def $r1, implicit-def dead $r3 -; 32BIT-DAG: ADJCALLSTACKUP 84, 0, implicit-def dead $r1, implicit $r1 -; 32BIT-NEXT: BLR implicit $lr, implicit $rm - -; 64BIT-DAG: ADJCALLSTACKDOWN 128, 0, implicit-def dead $r1, implicit $r1 -; 64BIT-DAG: renamable $x[[SCRATCHREG:[0-9]+]] = LDtocCPT %const.0, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $x[[SCRATCHREG:[0-9]+]] = LDtocCPT %const.1, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $x[[SCRATCHREG:[0-9]+]] = LDtocCPT %const.2, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $x[[SCRATCHREG:[0-9]+]] = LDtocCPT %const.3, $x2 :: (load (s64) from got) -; 64BIT-DAG: renamable $f1 = LFD 0, killed renamable $x[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool) -; 64BIT-DAG: renamable $f2 = LFD 0, killed renamable $x[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool) -; 64BIT-DAG: renamable $f3 = LFD 0, killed renamable $x[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool) -; 64BIT-DAG: renamable $f4 = LFD 0, killed renamable $x[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool) -; 64BIT-DAG: renamable $x[[SCRATCHREG:[0-9]+]] = LI8 50 -; 64BIT-DAG: renamable $x[[SCRATCHREG:[0-9]+]] = LI8 60 -; 64BIT-DAG: renamable $x[[SCRATCHREG:[0-9]+]] = LIS8 457 -; 64BIT-DAG: $x7 = LI8 1 -; 64BIT-DAG: $x8 = LI8 2 -; 64BIT-DAG: $x10 = LI8 40 -; 64BIT-DAG: STD killed renamable $x[[REG1:[0-9]+]], 112, $x1 :: (store (s64)) -; 64BIT-DAG: STD killed renamable $x[[REG2:[0-9]+]], 120, $x1 :: (store (s64)) -; 64BIT: ADJCALLSTACKUP 128, 0, implicit-def dead $r1, implicit $r1 -; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm - -; CHEKASM-LABEL: .caller_mix - -; ASM32PWR4: mflr 0 -; ASM32PWR4-DAG: stw [[REG1:[0-9]+]], 56(1) -; ASM32PWR4-DAG: stw [[REG2:[0-9]+]], 60(1) -; ASM32PWR4-DAG: stw [[REG3:[0-9]+]], 64(1) -; ASM32PWR4-DAG: stw [[REG4:[0-9]+]], 68(1) -; ASM32PWR4-DAG: stw [[REG5:[0-9]+]], 72(1) -; ASM32PWR4-DAG: stw [[REG6:[0-9]+]], 76(1) -; ASM32PWR4-DAG: stw [[REG7:[0-9]+]], 80(1) -; ASM32PWR4-DAG: bl .mix_callee -; ASM32PWR4-DAG: blr - -; ASM64PWR4: mflr 0 -; ASM64PWR4-DAG: std [[REG1:[0-9]+]], 112(1) -; ASM64PWR4-DAG: std [[REG2:[0-9]+]], 120(1) -; ASM64PWR4-DAG: bl .mix_callee -; ASM64PWR4-DAG: blr - - define i32 @mix_floats(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10, double %d11, double %d12, double %d13, double %d14) { +; ASM32PWR4-LABEL: mix_floats: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: add 3, 3, 4 +; ASM32PWR4-NEXT: lwz 4, L..C39(2) # %const.0 +; ASM32PWR4-NEXT: lis 11, 17200 +; ASM32PWR4-NEXT: stfd 31, -8(1) # 8-byte Folded Spill +; ASM32PWR4-NEXT: add 3, 3, 5 +; ASM32PWR4-NEXT: add 3, 3, 6 +; ASM32PWR4-NEXT: add 3, 3, 7 +; ASM32PWR4-NEXT: stw 11, -24(1) +; ASM32PWR4-NEXT: add 3, 3, 8 +; ASM32PWR4-NEXT: add 3, 3, 9 +; ASM32PWR4-NEXT: add 3, 3, 10 +; ASM32PWR4-NEXT: lfs 0, 0(4) +; ASM32PWR4-NEXT: xoris 3, 3, 32768 +; ASM32PWR4-NEXT: stw 3, -20(1) +; ASM32PWR4-NEXT: addi 3, 1, -12 +; ASM32PWR4-NEXT: lfd 31, -24(1) +; ASM32PWR4-NEXT: fsub 0, 31, 0 +; ASM32PWR4-NEXT: fadd 0, 0, 1 +; ASM32PWR4-NEXT: lfd 1, 160(1) +; ASM32PWR4-NEXT: fadd 0, 0, 2 +; ASM32PWR4-NEXT: fadd 0, 0, 3 +; ASM32PWR4-NEXT: fadd 0, 0, 4 +; ASM32PWR4-NEXT: fadd 0, 0, 5 +; ASM32PWR4-NEXT: fadd 0, 0, 6 +; ASM32PWR4-NEXT: fadd 0, 0, 7 +; ASM32PWR4-NEXT: fadd 0, 0, 8 +; ASM32PWR4-NEXT: fadd 0, 0, 9 +; ASM32PWR4-NEXT: fadd 0, 0, 10 +; ASM32PWR4-NEXT: fadd 0, 0, 11 +; ASM32PWR4-NEXT: fadd 0, 0, 12 +; ASM32PWR4-NEXT: fadd 0, 0, 13 +; ASM32PWR4-NEXT: fadd 0, 0, 1 +; ASM32PWR4-NEXT: fctiwz 0, 0 +; ASM32PWR4-NEXT: stfiwx 0, 0, 3 +; ASM32PWR4-NEXT: lwz 3, -12(1) +; ASM32PWR4-NEXT: lfd 31, -8(1) # 8-byte Folded Reload +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: mix_floats: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: add 3, 3, 4 +; ASM64PWR4-NEXT: add 3, 3, 5 +; ASM64PWR4-NEXT: add 3, 3, 6 +; ASM64PWR4-NEXT: add 3, 3, 7 +; ASM64PWR4-NEXT: add 3, 3, 8 +; ASM64PWR4-NEXT: add 3, 3, 9 +; ASM64PWR4-NEXT: add 3, 3, 10 +; ASM64PWR4-NEXT: extsw 3, 3 +; ASM64PWR4-NEXT: std 3, -16(1) +; ASM64PWR4-NEXT: addi 3, 1, -4 +; ASM64PWR4-NEXT: lfd 0, -16(1) +; ASM64PWR4-NEXT: fcfid 0, 0 +; ASM64PWR4-NEXT: fadd 0, 0, 1 +; ASM64PWR4-NEXT: lfd 1, 216(1) +; ASM64PWR4-NEXT: fadd 0, 0, 2 +; ASM64PWR4-NEXT: fadd 0, 0, 3 +; ASM64PWR4-NEXT: fadd 0, 0, 4 +; ASM64PWR4-NEXT: fadd 0, 0, 5 +; ASM64PWR4-NEXT: fadd 0, 0, 6 +; ASM64PWR4-NEXT: fadd 0, 0, 7 +; ASM64PWR4-NEXT: fadd 0, 0, 8 +; ASM64PWR4-NEXT: fadd 0, 0, 9 +; ASM64PWR4-NEXT: fadd 0, 0, 10 +; ASM64PWR4-NEXT: fadd 0, 0, 11 +; ASM64PWR4-NEXT: fadd 0, 0, 12 +; ASM64PWR4-NEXT: fadd 0, 0, 13 +; ASM64PWR4-NEXT: fadd 0, 0, 1 +; ASM64PWR4-NEXT: fctiwz 0, 0 +; ASM64PWR4-NEXT: stfiwx 0, 0, 3 +; ASM64PWR4-NEXT: lwz 3, -4(1) +; ASM64PWR4-NEXT: blr entry: %add = add nsw i32 %i1, %i2 %add1 = add nsw i32 %add, %i3 @@ -2149,203 +1963,240 @@ define void @caller_mix() { ret i32 %conv21 } -; CHECK-LABEL: mix_floats - -; 32BIT-LABEL: liveins: -; 32BIT-DAG: - { reg: '$r3', virtual-reg: '' } -; 32BIT-DAG: - { reg: '$r4', virtual-reg: '' } -; 32BIT-DAG: - { reg: '$r5', virtual-reg: '' } -; 32BIT-DAG: - { reg: '$r6', virtual-reg: '' } -; 32BIT-DAG: - { reg: '$r7', virtual-reg: '' } -; 32BIT-DAG: - { reg: '$r8', virtual-reg: '' } -; 32BIT-DAG: - { reg: '$r9', virtual-reg: '' } -; 32BIT-DAG: - { reg: '$r10', virtual-reg: '' } -; 32BIT-DAG: - { reg: '$f1', virtual-reg: '' } -; 32BIT-DAG: - { reg: '$f2', virtual-reg: '' } -; 32BIT-DAG: - { reg: '$f3', virtual-reg: '' } -; 32BIT-DAG: - { reg: '$f4', virtual-reg: '' } -; 32BIT-DAG: - { reg: '$f5', virtual-reg: '' } -; 32BIT-DAG: - { reg: '$f6', virtual-reg: '' } -; 32BIT-DAG: - { reg: '$f7', virtual-reg: '' } -; 32BIT-DAG: - { reg: '$f8', virtual-reg: '' } -; 32BIT-DAG: - { reg: '$f9', virtual-reg: '' } -; 32BIT-DAG: - { reg: '$f10', virtual-reg: '' } -; 32BIT-DAG: - { reg: '$f11', virtual-reg: '' } -; 32BIT-DAG: - { reg: '$f12', virtual-reg: '' } -; 32BIT-DAG: - { reg: '$f13', virtual-reg: '' } - -; 32BIT-LABEL: fixedStack: -; 32BIT-DAG: - { id: 0, type: default, offset: 160, size: 8 - -; 32BIT-LABEL: body: | -; 32BIT-DAG: bb.0.entry: -; 32BIT-DAG: liveins: $f1, $f2, $f3, $f4, $f5, $f6, $f7, $f8, $f9, $f10, $f11, $f12, $f13, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10 - -; 64BIT-DAG: liveins: -; 64BIT-DAG: - { reg: '$x3', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$x4', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$x5', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$x6', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$x7', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$x8', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$x9', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$x10', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$f1', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$f2', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$f3', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$f4', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$f5', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$f6', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$f7', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$f8', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$f9', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$f10', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$f11', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$f12', virtual-reg: '' } -; 64BIT-DAG: - { reg: '$f13', virtual-reg: '' } - -; 64BIT-LABEL: fixedStack: -; 64BIT-DAG: - { id: 0, type: default, offset: 216, size: 8 - -; 64BIT-LABEL: body: | -; 64BIT-DAG: bb.0.entry: -; 64BIT-DAG: liveins: $f1, $f2, $f3, $f4, $f5, $f6, $f7, $f8, $f9, $f10, $f11, $f12, $f13, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10 - -; CHECKASM-LABEL: .mix_floats: - -; ASM32PWR4-DAG: lfd [[REGF:[0-9]+]], 160(1) -; ASM32PWR4-DAG: fadd 0, 0, [[REGF]] -; ASM32PWR4-DAG: blr - -; ASM64PWR4-DAG: lfd [[REG1:[0-9]+]], 216(1) -; ASM64PWR4-DAG: fadd 0, 0, [[REG1]] -; ASM64PWR4-DAG: blr - define void @mix_floats_caller() { +; ASM32PWR4-LABEL: mix_floats_caller: +; ASM32PWR4: # %bb.0: # %entry +; ASM32PWR4-NEXT: mflr 0 +; ASM32PWR4-NEXT: stwu 1, -176(1) +; ASM32PWR4-NEXT: li 3, 0 +; ASM32PWR4-NEXT: stw 0, 184(1) +; ASM32PWR4-NEXT: lis 4, 16352 +; ASM32PWR4-NEXT: lis 5, 16339 +; ASM32PWR4-NEXT: lis 6, 16364 +; ASM32PWR4-NEXT: stw 3, 92(1) +; ASM32PWR4-NEXT: ori 5, 5, 13107 +; ASM32PWR4-NEXT: ori 6, 6, 52428 +; ASM32PWR4-NEXT: stw 3, 132(1) +; ASM32PWR4-NEXT: lis 3, 16368 +; ASM32PWR4-NEXT: li 8, 6 +; ASM32PWR4-NEXT: li 9, 7 +; ASM32PWR4-NEXT: li 10, 8 +; ASM32PWR4-NEXT: stw 3, 128(1) +; ASM32PWR4-NEXT: lis 3, -26215 +; ASM32PWR4-NEXT: ori 3, 3, 39322 +; ASM32PWR4-NEXT: stw 4, 88(1) +; ASM32PWR4-NEXT: lis 4, 16313 +; ASM32PWR4-NEXT: ori 4, 4, 39321 +; ASM32PWR4-NEXT: stw 3, 60(1) +; ASM32PWR4-NEXT: stw 3, 68(1) +; ASM32PWR4-NEXT: stw 3, 84(1) +; ASM32PWR4-NEXT: stw 3, 116(1) +; ASM32PWR4-NEXT: stw 3, 140(1) +; ASM32PWR4-NEXT: lis 3, 16369 +; ASM32PWR4-NEXT: ori 3, 3, 39321 +; ASM32PWR4-NEXT: stw 4, 56(1) +; ASM32PWR4-NEXT: lis 4, 16329 +; ASM32PWR4-NEXT: ori 4, 4, 39321 +; ASM32PWR4-NEXT: stw 3, 136(1) +; ASM32PWR4-NEXT: lis 3, 16371 +; ASM32PWR4-NEXT: ori 3, 3, 13107 +; ASM32PWR4-NEXT: stw 4, 64(1) +; ASM32PWR4-NEXT: lis 4, 13107 +; ASM32PWR4-NEXT: ori 4, 4, 13107 +; ASM32PWR4-NEXT: stw 3, 144(1) +; ASM32PWR4-NEXT: lis 3, 16372 +; ASM32PWR4-NEXT: ori 3, 3, 52428 +; ASM32PWR4-NEXT: stw 4, 76(1) +; ASM32PWR4-NEXT: stw 4, 100(1) +; ASM32PWR4-NEXT: stw 4, 148(1) +; ASM32PWR4-NEXT: lwz 4, L..C40(2) # %const.0 +; ASM32PWR4-NEXT: stw 3, 152(1) +; ASM32PWR4-NEXT: lwz 3, L..C41(2) # %const.1 +; ASM32PWR4-NEXT: lfd 1, 0(4) +; ASM32PWR4-NEXT: lwz 4, L..C42(2) # %const.2 +; ASM32PWR4-NEXT: lfd 2, 0(3) +; ASM32PWR4-NEXT: lwz 3, L..C43(2) # %const.3 +; ASM32PWR4-NEXT: stw 5, 72(1) +; ASM32PWR4-NEXT: lis 5, 16345 +; ASM32PWR4-NEXT: ori 5, 5, 39321 +; ASM32PWR4-NEXT: stw 5, 80(1) +; ASM32PWR4-NEXT: lis 5, 16355 +; ASM32PWR4-NEXT: ori 5, 5, 13107 +; ASM32PWR4-NEXT: lfd 3, 0(4) +; ASM32PWR4-NEXT: lwz 4, L..C44(2) # %const.4 +; ASM32PWR4-NEXT: lfd 4, 0(3) +; ASM32PWR4-NEXT: lwz 3, L..C45(2) # %const.5 +; ASM32PWR4-NEXT: stw 5, 96(1) +; ASM32PWR4-NEXT: lis 5, 26214 +; ASM32PWR4-NEXT: ori 7, 5, 26214 +; ASM32PWR4-NEXT: lis 5, 16358 +; ASM32PWR4-NEXT: lfd 6, 0(4) +; ASM32PWR4-NEXT: lwz 4, L..C46(2) # %const.6 +; ASM32PWR4-NEXT: ori 5, 5, 26214 +; ASM32PWR4-NEXT: lfd 7, 0(3) +; ASM32PWR4-NEXT: lwz 3, L..C47(2) # %const.7 +; ASM32PWR4-NEXT: stw 5, 104(1) +; ASM32PWR4-NEXT: lis 5, 16361 +; ASM32PWR4-NEXT: ori 5, 5, 39321 +; ASM32PWR4-NEXT: lfd 8, 0(4) +; ASM32PWR4-NEXT: lwz 4, L..C48(2) # %const.8 +; ASM32PWR4-NEXT: lfd 9, 0(3) +; ASM32PWR4-NEXT: lwz 3, L..C49(2) # %const.9 +; ASM32PWR4-NEXT: stw 5, 112(1) +; ASM32PWR4-NEXT: lis 5, -13108 +; ASM32PWR4-NEXT: ori 5, 5, 52429 +; ASM32PWR4-NEXT: stw 5, 124(1) +; ASM32PWR4-NEXT: stw 5, 156(1) +; ASM32PWR4-NEXT: lwz 5, L..C50(2) # %const.12 +; ASM32PWR4-NEXT: lfd 11, 0(4) +; ASM32PWR4-NEXT: lwz 4, L..C51(2) # %const.10 +; ASM32PWR4-NEXT: lfd 12, 0(3) +; ASM32PWR4-NEXT: lwz 3, L..C52(2) # %const.11 +; ASM32PWR4-NEXT: lfd 13, 0(4) +; ASM32PWR4-NEXT: lis 4, 16374 +; ASM32PWR4-NEXT: ori 11, 4, 26214 +; ASM32PWR4-NEXT: li 4, 2 +; ASM32PWR4-NEXT: lfs 5, 0(3) +; ASM32PWR4-NEXT: li 3, 1 +; ASM32PWR4-NEXT: lfs 10, 0(5) +; ASM32PWR4-NEXT: li 5, 3 +; ASM32PWR4-NEXT: stw 7, 108(1) +; ASM32PWR4-NEXT: stw 6, 120(1) +; ASM32PWR4-NEXT: li 6, 4 +; ASM32PWR4-NEXT: stw 7, 164(1) +; ASM32PWR4-NEXT: li 7, 5 +; ASM32PWR4-NEXT: stw 11, 160(1) +; ASM32PWR4-NEXT: bl .mix_floats +; ASM32PWR4-NEXT: nop +; ASM32PWR4-NEXT: addi 1, 1, 176 +; ASM32PWR4-NEXT: lwz 0, 8(1) +; ASM32PWR4-NEXT: mtlr 0 +; ASM32PWR4-NEXT: blr +; +; ASM64PWR4-LABEL: mix_floats_caller: +; ASM64PWR4: # %bb.0: # %entry +; ASM64PWR4-NEXT: mflr 0 +; ASM64PWR4-NEXT: stdu 1, -240(1) +; ASM64PWR4-NEXT: li 3, 1023 +; ASM64PWR4-NEXT: std 0, 256(1) +; ASM64PWR4-NEXT: ld 4, L..C37(2) # %const.0 +; ASM64PWR4-NEXT: ld 8, L..C38(2) # %const.6 +; ASM64PWR4-NEXT: lis 5, 16371 +; ASM64PWR4-NEXT: ld 6, L..C39(2) # %const.3 +; ASM64PWR4-NEXT: ld 9, L..C40(2) # %const.9 +; ASM64PWR4-NEXT: ld 10, L..C41(2) # %const.11 +; ASM64PWR4-NEXT: rldic 3, 3, 52, 2 +; ASM64PWR4-NEXT: lis 11, 4091 +; ASM64PWR4-NEXT: std 3, 184(1) +; ASM64PWR4-NEXT: li 3, 511 +; ASM64PWR4-NEXT: lis 12, 16361 +; ASM64PWR4-NEXT: rldic 3, 3, 53, 2 +; ASM64PWR4-NEXT: lfd 1, 0(4) +; ASM64PWR4-NEXT: ld 4, L..C42(2) # %const.2 +; ASM64PWR4-NEXT: lis 0, 16345 +; ASM64PWR4-NEXT: std 3, 144(1) +; ASM64PWR4-NEXT: ld 3, L..C43(2) # %const.1 +; ASM64PWR4-NEXT: lfd 2, 0(3) +; ASM64PWR4-NEXT: lis 3, 16374 +; ASM64PWR4-NEXT: ori 7, 3, 26214 +; ASM64PWR4-NEXT: ori 3, 5, 13107 +; ASM64PWR4-NEXT: ld 5, L..C44(2) # %const.5 +; ASM64PWR4-NEXT: lfd 8, 0(8) +; ASM64PWR4-NEXT: ld 8, L..C45(2) # %const.8 +; ASM64PWR4-NEXT: rldimi 7, 7, 32, 0 +; ASM64PWR4-NEXT: rlwimi 7, 7, 16, 0, 15 +; ASM64PWR4-NEXT: rldimi 3, 3, 32, 0 +; ASM64PWR4-NEXT: lfd 3, 0(4) +; ASM64PWR4-NEXT: ld 4, L..C46(2) # %const.4 +; ASM64PWR4-NEXT: rlwimi 3, 3, 16, 0, 15 +; ASM64PWR4-NEXT: lfd 4, 0(6) +; ASM64PWR4-NEXT: lis 6, 16355 +; ASM64PWR4-NEXT: lfd 7, 0(5) +; ASM64PWR4-NEXT: ori 5, 6, 13107 +; ASM64PWR4-NEXT: ld 6, L..C47(2) # %const.7 +; ASM64PWR4-NEXT: rldimi 5, 5, 32, 0 +; ASM64PWR4-NEXT: rlwimi 5, 5, 16, 0, 15 +; ASM64PWR4-NEXT: lfd 11, 0(8) +; ASM64PWR4-NEXT: ld 8, L..C48(2) # %const.10 +; ASM64PWR4-NEXT: lfd 6, 0(4) +; ASM64PWR4-NEXT: lis 4, 16358 +; ASM64PWR4-NEXT: ori 4, 4, 26214 +; ASM64PWR4-NEXT: rldimi 4, 4, 32, 0 +; ASM64PWR4-NEXT: lfd 9, 0(6) +; ASM64PWR4-NEXT: lis 6, 16339 +; ASM64PWR4-NEXT: rlwimi 4, 4, 16, 0, 15 +; ASM64PWR4-NEXT: ori 6, 6, 13107 +; ASM64PWR4-NEXT: lfd 12, 0(9) +; ASM64PWR4-NEXT: lis 9, 4093 +; ASM64PWR4-NEXT: ori 9, 9, 13107 +; ASM64PWR4-NEXT: lfd 13, 0(8) +; ASM64PWR4-NEXT: lis 8, 16369 +; ASM64PWR4-NEXT: ori 8, 8, 39321 +; ASM64PWR4-NEXT: rldimi 6, 6, 32, 0 +; ASM64PWR4-NEXT: std 31, 232(1) # 8-byte Folded Spill +; ASM64PWR4-NEXT: ld 31, L..C49(2) # %const.12 +; ASM64PWR4-NEXT: rldic 9, 9, 34, 2 +; ASM64PWR4-NEXT: rlwimi 6, 6, 16, 0, 15 +; ASM64PWR4-NEXT: oris 9, 9, 52428 +; ASM64PWR4-NEXT: lfs 5, 0(10) +; ASM64PWR4-NEXT: lis 10, 16329 +; ASM64PWR4-NEXT: ori 10, 10, 39321 +; ASM64PWR4-NEXT: std 7, 216(1) +; ASM64PWR4-NEXT: ori 7, 11, 13107 +; ASM64PWR4-NEXT: ori 11, 12, 39321 +; ASM64PWR4-NEXT: ori 12, 0, 39321 +; ASM64PWR4-NEXT: std 4, 160(1) +; ASM64PWR4-NEXT: rldic 4, 8, 32, 2 +; ASM64PWR4-NEXT: rldic 7, 7, 34, 2 +; ASM64PWR4-NEXT: oris 4, 4, 39321 +; ASM64PWR4-NEXT: std 30, 224(1) # 8-byte Folded Spill +; ASM64PWR4-NEXT: lis 30, 16313 +; ASM64PWR4-NEXT: rldic 8, 11, 32, 2 +; ASM64PWR4-NEXT: rldic 11, 12, 32, 2 +; ASM64PWR4-NEXT: std 3, 200(1) +; ASM64PWR4-NEXT: ori 3, 30, 39321 +; ASM64PWR4-NEXT: ori 4, 4, 39322 +; ASM64PWR4-NEXT: rldic 3, 3, 32, 2 +; ASM64PWR4-NEXT: std 5, 152(1) +; ASM64PWR4-NEXT: rldic 5, 10, 32, 2 +; ASM64PWR4-NEXT: oris 5, 5, 39321 +; ASM64PWR4-NEXT: oris 3, 3, 39321 +; ASM64PWR4-NEXT: std 6, 128(1) +; ASM64PWR4-NEXT: oris 6, 7, 52428 +; ASM64PWR4-NEXT: ori 7, 9, 52429 +; ASM64PWR4-NEXT: li 9, 7 +; ASM64PWR4-NEXT: lfs 10, 0(31) +; ASM64PWR4-NEXT: li 10, 8 +; ASM64PWR4-NEXT: std 7, 208(1) +; ASM64PWR4-NEXT: oris 7, 8, 39321 +; ASM64PWR4-NEXT: oris 8, 11, 39321 +; ASM64PWR4-NEXT: ori 11, 3, 39322 +; ASM64PWR4-NEXT: li 3, 1 +; ASM64PWR4-NEXT: std 4, 192(1) +; ASM64PWR4-NEXT: ori 4, 6, 52429 +; ASM64PWR4-NEXT: ori 6, 8, 39322 +; ASM64PWR4-NEXT: std 4, 176(1) +; ASM64PWR4-NEXT: ori 4, 7, 39322 +; ASM64PWR4-NEXT: ori 7, 5, 39322 +; ASM64PWR4-NEXT: li 5, 3 +; ASM64PWR4-NEXT: li 8, 6 +; ASM64PWR4-NEXT: std 4, 168(1) +; ASM64PWR4-NEXT: li 4, 2 +; ASM64PWR4-NEXT: std 6, 136(1) +; ASM64PWR4-NEXT: li 6, 4 +; ASM64PWR4-NEXT: std 7, 120(1) +; ASM64PWR4-NEXT: li 7, 5 +; ASM64PWR4-NEXT: std 11, 112(1) +; ASM64PWR4-NEXT: bl .mix_floats +; ASM64PWR4-NEXT: nop +; ASM64PWR4-NEXT: ld 31, 232(1) # 8-byte Folded Reload +; ASM64PWR4-NEXT: ld 30, 224(1) # 8-byte Folded Reload +; ASM64PWR4-NEXT: addi 1, 1, 240 +; ASM64PWR4-NEXT: ld 0, 16(1) +; ASM64PWR4-NEXT: mtlr 0 +; ASM64PWR4-NEXT: blr entry: %call = call i32 @mix_floats(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, double 1.000000e-01, double 2.000000e-01, double 3.000000e-01, double 4.000000e-01, double 5.000000e-01, double 6.000000e-01, double 0x3FE6666666666666, double 8.000000e-01, double 9.000000e-01, double 1.000000e+00, double 1.100000e+00, double 1.200000e+00, double 1.300000e+00, double 1.400000e+00) ret void } -; CHECK-LABEL: mix_floats_caller - -; 32BIT-DAG: ADJCALLSTACKDOWN 168, 0, implicit-def dead $r1, implicit $r1 -; 32BIT-DAG: $r3 = LI 1 -; 32BIT-DAG: $r4 = LI 2 -; 32BIT-DAG: $r5 = LI 3 -; 32BIT-DAG: $r6 = LI 4 -; 32BIT-DAG: $r7 = LI 5 -; 32BIT-DAG: $r8 = LI 6 -; 32BIT-DAG: $r9 = LI 7 -; 32BIT-DAG: $r10 = LI 8 -; 32BIT-DAG: STW killed renamable $r[[REG1:[0-9]+]], 56, $r1 :: (store (s32), align 8) -; 32BIT-DAG: STW renamable $r[[REG2:[0-9]+]], 60, $r1 :: (store (s32) into unknown-address + 4, basealign 8) -; 32BIT-DAG: STW killed renamable $r[[REG3:[0-9]+]], 64, $r1 :: (store (s32), align 8) -; 32BIT-DAG: STW renamable $r[[REG4:[0-9]+]], 68, $r1 :: (store (s32) into unknown-address + 4, basealign 8) -; 32BIT-DAG: STW killed renamable $r[[REG5:[0-9]+]], 72, $r1 :: (store (s32), align 8) -; 32BIT-DAG: STW renamable $r[[REG6:[0-9]+]], 76, $r1 :: (store (s32) into unknown-address + 4, basealign 8) -; 32BIT-DAG: STW killed renamable $r[[REG7:[0-9]+]], 80, $r1 :: (store (s32), align 8) -; 32BIT-DAG: STW renamable $r[[REG8:[0-9]+]], 84, $r1 :: (store (s32) into unknown-address + 4, basealign 8) -; 32BIT-DAG: STW killed renamable $r[[REG9:[0-9]+]], 88, $r1 :: (store (s32), align 8) -; 32BIT-DAG: STW renamable $r[[REG10:[0-9]+]], 92, $r1 :: (store (s32) into unknown-address + 4, basealign 8) -; 32BIT-DAG: STW killed renamable $r[[REG11:[0-9]+]], 96, $r1 :: (store (s32), align 8) -; 32BIT-DAG: STW renamable $r[[REG12:[0-9]+]], 100, $r1 :: (store (s32) into unknown-address + 4, basealign 8) -; 32BIT-DAG: STW killed renamable $r[[REG13:[0-9]+]], 104, $r1 :: (store (s32), align 8) -; 32BIT-DAG: STW renamable $r[[REG14:[0-9]+]], 108, $r1 :: (store (s32) into unknown-address + 4, basealign 8) -; 32BIT-DAG: STW killed renamable $r[[REG15:[0-9]+]], 112, $r1 :: (store (s32), align 8) -; 32BIT-DAG: STW renamable $r[[REG16:[0-9]+]], 116, $r1 :: (store (s32) into unknown-address + 4, basealign 8) -; 32BIT-DAG: STW killed renamable $r[[REG17:[0-9]+]], 120, $r1 :: (store (s32), align 8) -; 32BIT-DAG: STW killed renamable $r[[REG18:[0-9]+]], 128, $r1 :: (store (s32), align 8) -; 32BIT-DAG: STW renamable $r[[REG19:[0-9]+]], 124, $r1 :: (store (s32) into unknown-address + 4, basealign 8) -; 32BIT-DAG: STW killed renamable $r[[REG20:[0-9]+]], 132, $r1 :: (store (s32) into unknown-address + 4, basealign 8) -; 32BIT-DAG: STW killed renamable $r[[REG21:[0-9]+]], 136, $r1 :: (store (s32), align 8) -; 32BIT-DAG: STW killed renamable $r[[REG22:[0-9]+]], 140, $r1 :: (store (s32) into unknown-address + 4, basealign 8) -; 32BIT-DAG: STW killed renamable $r[[REG23:[0-9]+]], 144, $r1 :: (store (s32), align 8) -; 32BIT-DAG: STW killed renamable $r[[REG24:[0-9]+]], 148, $r1 :: (store (s32) into unknown-address + 4, basealign 8) -; 32BIT-DAG: STW killed renamable $r[[REG25:[0-9]+]], 152, $r1 :: (store (s32), align 8) -; 32BIT-DAG: STW killed renamable $r[[REG26:[0-9]+]], 156, $r1 :: (store (s32) into unknown-address + 4, basealign 8) -; 32BIT-DAG: STW killed renamable $r[[REG27:[0-9]+]], 160, $r1 :: (store (s32), align 8) -; 32BIT-DAG: STW killed renamable $r[[REG28:[0-9]+]], 164, $r1 :: (store (s32) into unknown-address + 4, basealign 8) -; 32BIT-NEXT: BL_NOP , csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit $f10, implicit $f11, implicit $f12, implicit $f13, implicit $r2, implicit-def $r1, implicit-def dead $r3 -; 32BIT-NEXT: ADJCALLSTACKUP 168, 0, implicit-def dead $r1, implicit $r1 - - -; 64BIT-DAG: ADJCALLSTACKDOWN 224, 0, implicit-def dead $r1, implicit $r1 -; 64BIT-DAG: $x3 = LI8 1 -; 64BIT-DAG: $x4 = LI8 2 -; 64BIT-DAG: $x5 = LI8 3 -; 64BIT-DAG: $x6 = LI8 4 -; 64BIT-DAG: $x7 = LI8 5 -; 64BIT-DAG: $x8 = LI8 6 -; 64BIT-DAG: $x9 = LI8 7 -; 64BIT-DAG: $x10 = LI8 8 -; 64BIT-DAG: STD killed renamable $x[[REG1:[0-9]+]], 112, $x1 :: (store (s64)) -; 64BIT-DAG: STD killed renamable $x[[REG2:[0-9]+]], 120, $x1 :: (store (s64)) -; 64BIT-DAG: STD killed renamable $x[[REG3:[0-9]+]], 128, $x1 :: (store (s64)) -; 64BIT-DAG: STD killed renamable $x[[REG4:[0-9]+]], 136, $x1 :: (store (s64)) -; 64BIT-DAG: STD killed renamable $x[[REG5:[0-9]+]], 144, $x1 :: (store (s64)) -; 64BIT-DAG: STD killed renamable $x[[REG6:[0-9]+]], 152, $x1 :: (store (s64)) -; 64BIT-DAG: STD killed renamable $x[[REG7:[0-9]+]], 160, $x1 :: (store (s64)) -; 64BIT-DAG: STD killed renamable $x[[REG8:[0-9]+]], 168, $x1 :: (store (s64)) -; 64BIT-DAG: STD killed renamable $x[[REG9:[0-9]+]], 176, $x1 :: (store (s64)) -; 64BIT-DAG: STD killed renamable $x[[REG10:[0-9]+]], 184, $x1 :: (store (s64)) -; 64BIT-DAG: STD killed renamable $x[[REG12:[0-9]+]], 192, $x1 :: (store (s64)) -; 64BIT-DAG: STD killed renamable $x[[REG13:[0-9]+]], 200, $x1 :: (store (s64)) -; 64BIT-DAG: STD killed renamable $x[[REG14:[0-9]+]], 208, $x1 :: (store (s64)) -; 64BIT-DAG: STD killed renamable $x[[REG15:[0-9]+]], 216, $x1 :: (store (s64)) -; 64BIT-DAG: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit $f10, implicit $f11, implicit $f12, implicit $f13, implicit $x2, implicit-def $r1, implicit-def dead $x3 -; 64BIT-NEXT: ADJCALLSTACKUP 224, 0, implicit-def dead $r1, implicit $r1 - -; CHEKASM-LABEL: .mix_floats_caller: - -; ASM32PWR4: mflr 0 -; ASM32PWR4-NEXT: stwu 1, -176(1) -; ASM32PWR4-DAG: stw 0, 184(1) -; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 56(1) -; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 60(1) -; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 64(1) -; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 68(1) -; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 72(1) -; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 76(1) -; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 80(1) -; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 84(1) -; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 88(1) -; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 92(1) -; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 96(1) -; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 100(1) -; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 104(1) -; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 108(1) -; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 112(1) -; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 116(1) -; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 120(1) -; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 124(1) -; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 128(1) -; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 132(1) -; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 136(1) -; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 140(1) -; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 144(1) -; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 148(1) -; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 152(1) -; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 156(1) -; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 160(1) -; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 164(1) -; ASM32PWR4: bl .mix_floats - -; ASM64PWR4: mflr 0 -; ASM64PWR4-NEXT: stdu 1, -240(1) -; ASM64PWR4-DAG: std 0, 256(1) -; ASM64PWR4-DAG: std [[REG:[0-9]+]], 112(1) -; ASM64PWR4-DAG: std [[REG:[0-9]+]], 120(1) -; ASM64PWR4-DAG: std [[REG:[0-9]+]], 128(1) -; ASM64PWR4-DAG: std [[REG:[0-9]+]], 136(1) -; ASM64PWR4-DAG: std [[REG:[0-9]+]], 144(1) -; ASM64PWR4-DAG: std [[REG:[0-9]+]], 152(1) -; ASM64PWR4-DAG: std [[REG:[0-9]+]], 160(1) -; ASM64PWR4-DAG: std [[REG:[0-9]+]], 168(1) -; ASM64PWR4-DAG: std [[REG:[0-9]+]], 176(1) -; ASM64PWR4-DAG: std [[REG:[0-9]+]], 184(1) -; ASM64PWR4-DAG: std [[REG:[0-9]+]], 192(1) -; ASM64PWR4-DAG: std [[REG:[0-9]+]], 200(1) -; ASM64PWR4-DAG: std [[REG:[0-9]+]], 208(1) -; ASM64PWR4-DAG: std [[REG:[0-9]+]], 216(1) -; ASM64PWR4: bl .mix_floats -- GitLab From 9557fcca563dba3dd31769c297bb3b97d6e614f9 Mon Sep 17 00:00:00 2001 From: Guillaume Chatelet Date: Fri, 1 Dec 2023 09:32:22 +0100 Subject: [PATCH 112/699] [libc] Fix lint message (#73956) --- libc/src/__support/CMakeLists.txt | 2 ++ libc/src/__support/str_to_num_result.h | 13 ++++++++----- utils/bazel/llvm-project-overlay/libc/BUILD.bazel | 3 +-- 3 files changed, 11 insertions(+), 7 deletions(-) diff --git a/libc/src/__support/CMakeLists.txt b/libc/src/__support/CMakeLists.txt index a76b22960f5a..decd6ed2dbd2 100644 --- a/libc/src/__support/CMakeLists.txt +++ b/libc/src/__support/CMakeLists.txt @@ -79,6 +79,8 @@ add_header_library( str_to_num_result HDRS str_to_num_result.h + DEPENDS + libc.src.__support.macros.attributes ) add_header_library( diff --git a/libc/src/__support/str_to_num_result.h b/libc/src/__support/str_to_num_result.h index 9ba704c69065..b32fbdeeb580 100644 --- a/libc/src/__support/str_to_num_result.h +++ b/libc/src/__support/str_to_num_result.h @@ -9,6 +9,8 @@ #ifndef LLVM_LIBC_SRC___SUPPORT_STR_TO_NUM_RESULT_H #define LLVM_LIBC_SRC___SUPPORT_STR_TO_NUM_RESULT_H +#include "src/__support/macros/attributes.h" // LIBC_INLINE + #include namespace LIBC_NAMESPACE { @@ -18,15 +20,16 @@ template struct StrToNumResult { int error; ptrdiff_t parsed_len; - constexpr StrToNumResult(T value) : value(value), error(0), parsed_len(0) {} - constexpr StrToNumResult(T value, ptrdiff_t parsed_len) + LIBC_INLINE constexpr StrToNumResult(T value) + : value(value), error(0), parsed_len(0) {} + LIBC_INLINE constexpr StrToNumResult(T value, ptrdiff_t parsed_len) : value(value), error(0), parsed_len(parsed_len) {} - constexpr StrToNumResult(T value, ptrdiff_t parsed_len, int error) + LIBC_INLINE constexpr StrToNumResult(T value, ptrdiff_t parsed_len, int error) : value(value), error(error), parsed_len(parsed_len) {} - constexpr bool has_error() { return error != 0; } + LIBC_INLINE constexpr bool has_error() { return error != 0; } - constexpr operator T() { return value; } + LIBC_INLINE constexpr operator T() { return value; } }; } // namespace LIBC_NAMESPACE diff --git a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel index a0a6a4366ea7..fdd620a4d415 100644 --- a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel @@ -474,8 +474,7 @@ libc_support_library( libc_support_library( name = "__support_str_to_num_result", hdrs = ["src/__support/str_to_num_result.h"], - deps = [ - ], + deps = [":__support_macros_attributes"], ) libc_support_library( -- GitLab From 1726b65e4c273d55dd54838a742b03caff4abcdd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20Warzy=C5=84ski?= Date: Fri, 1 Dec 2023 08:45:13 +0000 Subject: [PATCH 113/699] [MLIR][Vector] Refactor tests for contract -> OP transforms (4/N) (#73807) This patch refactors tests for: vector.contract -> vector.outerproduct for matvec operations (b += Ax). Summary of changes: * add 2 missing cases (masked + scalable) when the operation kind is `maxf`. This is a part of a larger effort to add cases with scalable vectors to tests for the Vector dialect. Implements #72834. --- ...act-to-outerproduct-matvec-transforms.mlir | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/mlir/test/Dialect/Vector/vector-contract-to-outerproduct-matvec-transforms.mlir b/mlir/test/Dialect/Vector/vector-contract-to-outerproduct-matvec-transforms.mlir index e84a43feaff3..8fed1f8fb341 100644 --- a/mlir/test/Dialect/Vector/vector-contract-to-outerproduct-matvec-transforms.mlir +++ b/mlir/test/Dialect/Vector/vector-contract-to-outerproduct-matvec-transforms.mlir @@ -186,6 +186,52 @@ func.func @matvec_mk_k_m_max(%A: vector<2x2xf32>, return %0 : vector<2xf32> } +// CHECK-LABEL: func.func @masked_matvec_mk_k_m_max( +// CHECK-SAME: %{{.*}}: vector<2x3xf32>, +// CHECK-SAME: %{{.*}}: vector<3xf32>, +// CHECK-SAME: %{{.*}}: vector<2xf32>, +// CHECK-SAME: %[[IN_MASK:.*]]: vector<2x3xi1>) -> vector<2xf32> +// CHECK: %[[T_MASK:.*]] = vector.transpose %[[IN_MASK]], [1, 0] : vector<2x3xi1> to vector<3x2xi1> +// CHECK: %[[MASK0:.*]] = vector.extract %[[T_MASK]][0] : vector<2xi1> from vector<3x2xi1> +// CHECK: vector.mask %[[MASK0]] { vector.outerproduct {{.*}} {kind = #vector.kind} : vector<2xf32>, f32 } : vector<2xi1> -> vector<2xf32> + +// CHECK: %[[MASK1:.*]] = vector.extract %[[T_MASK]][1] : vector<2xi1> from vector<3x2xi1> +// CHECK: vector.mask %[[MASK1]] { vector.outerproduct {{.*}} {kind = #vector.kind} : vector<2xf32>, f32 } : vector<2xi1> -> vector<2xf32> + +// CHECK: %[[MASK2:.*]] = vector.extract %[[T_MASK]][2] : vector<2xi1> from vector<3x2xi1> +// CHECK: vector.mask %[[MASK2]] { vector.outerproduct {{.*}} {kind = #vector.kind} : vector<2xf32>, f32 } : vector<2xi1> -> vector<2xf32> +func.func @masked_matvec_mk_k_m_max(%A: vector<2x3xf32>, + %x: vector<3xf32>, + %b: vector<2xf32>, + %m: vector<2x3xi1>) -> vector<2xf32> { + %0 = vector.mask %m { vector.contract #matvecmax_trait %A, %x, %b + : vector<2x3xf32>, vector<3xf32> into vector<2xf32> } : vector<2x3xi1> -> vector<2xf32> + return %0 : vector<2xf32> +} + +// CHECK-LABEL: func.func @masked_matvec_mk_k_m_max_scalable_parallel_dim( +// CHECK-SAME: %{{.*}}: vector<[2]x3xf32>, +// CHECK-SAME: %{{.*}}: vector<3xf32>, +// CHECK-SAME: %{{.*}}: vector<[2]xf32>, +// CHECK-SAME: %[[IN_MASK:.*]]: vector<[2]x3xi1>) -> vector<[2]xf32> +// CHECK: %[[T_MASK:.*]] = vector.transpose %[[IN_MASK]], [1, 0] : vector<[2]x3xi1> to vector<3x[2]xi1> +// CHECK: %[[MASK0:.*]] = vector.extract %[[T_MASK]][0] : vector<[2]xi1> from vector<3x[2]xi1> +// CHECK: vector.mask %[[MASK0]] { vector.outerproduct {{.*}} {kind = #vector.kind} : vector<[2]xf32>, f32 } : vector<[2]xi1> -> vector<[2]xf32> + +// CHECK: %[[MASK1:.*]] = vector.extract %[[T_MASK]][1] : vector<[2]xi1> from vector<3x[2]xi1> +// CHECK: vector.mask %[[MASK1]] { vector.outerproduct {{.*}} {kind = #vector.kind} : vector<[2]xf32>, f32 } : vector<[2]xi1> -> vector<[2]xf32> + +// CHECK: %[[MASK2:.*]] = vector.extract %[[T_MASK]][2] : vector<[2]xi1> from vector<3x[2]xi1> +// CHECK: vector.mask %[[MASK2]] { vector.outerproduct {{.*}} {kind = #vector.kind} : vector<[2]xf32>, f32 } : vector<[2]xi1> -> vector<[2]xf32> +func.func @masked_matvec_mk_k_m_max_scalable_parallel_dim(%A: vector<[2]x3xf32>, + %x: vector<3xf32>, + %b: vector<[2]xf32>, + %m: vector<[2]x3xi1>) -> vector<[2]xf32> { + %0 = vector.mask %m { vector.contract #matvecmax_trait %A, %x, %b + : vector<[2]x3xf32>, vector<3xf32> into vector<[2]xf32> } : vector<[2]x3xi1> -> vector<[2]xf32> + return %0 : vector<[2]xf32> +} + // ============================================================================ // Matvec 2 (plain + masked + scalable) // ============================================================================ -- GitLab From 2c976a1fac5c0d6fe1cd7c3637f3d16cc378f52b Mon Sep 17 00:00:00 2001 From: Guillaume Chatelet Date: Fri, 1 Dec 2023 09:47:26 +0100 Subject: [PATCH 114/699] [libc] Fix _Float16 detection for x86 (#73947) --- libc/src/__support/macros/properties/CMakeLists.txt | 1 + libc/src/__support/macros/properties/float.h | 3 ++- utils/bazel/llvm-project-overlay/libc/BUILD.bazel | 1 + 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/libc/src/__support/macros/properties/CMakeLists.txt b/libc/src/__support/macros/properties/CMakeLists.txt index e37cdb78bfa2..ee87ce68c9da 100644 --- a/libc/src/__support/macros/properties/CMakeLists.txt +++ b/libc/src/__support/macros/properties/CMakeLists.txt @@ -31,5 +31,6 @@ add_header_library( DEPENDS .architectures .compiler + .cpu_features .os ) diff --git a/libc/src/__support/macros/properties/float.h b/libc/src/__support/macros/properties/float.h index 7e00ddc8f0cd..4bafc3777a47 100644 --- a/libc/src/__support/macros/properties/float.h +++ b/libc/src/__support/macros/properties/float.h @@ -13,6 +13,7 @@ #include "src/__support/macros/properties/architectures.h" #include "src/__support/macros/properties/compiler.h" +#include "src/__support/macros/properties/cpu_features.h" #include "src/__support/macros/properties/os.h" #include // LDBL_MANT_DIG @@ -30,7 +31,7 @@ #endif // float16 support. -#if defined(LIBC_TARGET_ARCH_IS_X86_64) +#if defined(LIBC_TARGET_ARCH_IS_X86_64) && defined(LIBC_TARGET_CPU_HAS_SSE2) #if (defined(LIBC_COMPILER_CLANG_VER) && (LIBC_COMPILER_CLANG_VER >= 1500)) || \ (defined(LIBC_COMPILER_GCC_VER) && (LIBC_COMPILER_GCC_VER >= 1201)) #define LIBC_COMPILER_HAS_C23_FLOAT16 diff --git a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel index fdd620a4d415..d53ca2021015 100644 --- a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel @@ -86,6 +86,7 @@ libc_support_library( deps = [ ":__support_macros_properties_architectures", ":__support_macros_properties_compiler", + ":__support_macros_properties_cpu_features", ":__support_macros_properties_os", ], ) -- GitLab From d55692d60d218f402ce107520daabed15f2d9ef6 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 10 Nov 2023 22:49:21 +0900 Subject: [PATCH 115/699] Reapply "ValueTracking: Identify implied fp classes by general fcmp (#66505)" This reverts commit 96a0d714d58e48c363ee6abbbcdfd7a6ce646ac1. Avoid assert with dynamic denormal-fp-math We don't recognize compares with 0 as an exact class test if we don't know the denormal mode. We could try to do better here, but it's probably not worth it. Fixes asserts reported after 1adce7d8e47e2438f99f91607760b825e5e3cc37 --- llvm/include/llvm/Analysis/ValueTracking.h | 21 + llvm/lib/Analysis/ValueTracking.cpp | 185 +++++++- .../Attributor/nofpclass-implied-by-fcmp.ll | 446 +++++++++--------- .../assume-fcmp-constant-implies-class.ll | 270 ++++------- 4 files changed, 500 insertions(+), 422 deletions(-) diff --git a/llvm/include/llvm/Analysis/ValueTracking.h b/llvm/include/llvm/Analysis/ValueTracking.h index f353eec8c89b..82c87edd6297 100644 --- a/llvm/include/llvm/Analysis/ValueTracking.h +++ b/llvm/include/llvm/Analysis/ValueTracking.h @@ -214,6 +214,27 @@ std::pair fcmpToClassTest(CmpInst::Predicate Pred, const APFloat *ConstRHS, bool LookThroughSrc = true); +/// Compute the possible floating-point classes that \p LHS could be based on an +/// fcmp returning true. Returns { TestedValue, ClassesIfTrue, ClassesIfFalse } +/// +/// If the compare returns an exact class test, ClassesIfTrue == ~ClassesIfFalse +/// +/// This is a less exact version of fcmpToClassTest (e.g. fcmpToClassTest will +/// only succeed for a test of x > 0 implies positive, but not x > 1). +/// +/// If \p LookThroughSrc is true, consider the input value when computing the +/// mask. This may look through sign bit operations. +/// +/// If \p LookThroughSrc is false, ignore the source value (i.e. the first pair +/// element will always be LHS. +/// +std::tuple +fcmpImpliesClass(CmpInst::Predicate Pred, const Function &F, Value *LHS, + const APFloat *ConstRHS, bool LookThroughSrc = true); +std::tuple +fcmpImpliesClass(CmpInst::Predicate Pred, const Function &F, Value *LHS, + Value *RHS, bool LookThroughSrc = true); + struct KnownFPClass { /// Floating-point classes the value could be one of. FPClassTest KnownFPClasses = fcAllFlags; diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp index ef8fa5826deb..9cfe7315a7a4 100644 --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -4164,6 +4164,147 @@ llvm::fcmpToClassTest(FCmpInst::Predicate Pred, const Function &F, Value *LHS, return {Src, Mask}; } +std::tuple +llvm::fcmpImpliesClass(CmpInst::Predicate Pred, const Function &F, Value *LHS, + const APFloat *ConstRHS, bool LookThroughSrc) { + auto [Val, ClassMask] = + fcmpToClassTest(Pred, F, LHS, ConstRHS, LookThroughSrc); + if (Val) + return {Val, ClassMask, ~ClassMask}; + + FPClassTest RHSClass = ConstRHS->classify(); + + // If we see a zero here, we are using dynamic denormal-fp-math, and can't + // treat comparisons to 0 as an exact class test. + // + // TODO: We could do better and still recognize non-equality cases. + if (RHSClass == fcPosZero || RHSClass == fcNegZero) + return {nullptr, fcAllFlags, fcAllFlags}; + + assert((RHSClass == fcPosNormal || RHSClass == fcNegNormal || + RHSClass == fcPosSubnormal || RHSClass == fcNegSubnormal) && + "should have been recognized as an exact class test"); + + const bool IsNegativeRHS = (RHSClass & fcNegative) == RHSClass; + const bool IsPositiveRHS = (RHSClass & fcPositive) == RHSClass; + + assert(IsNegativeRHS == ConstRHS->isNegative()); + assert(IsPositiveRHS == !ConstRHS->isNegative()); + + Value *Src = LHS; + const bool IsFabs = LookThroughSrc && match(LHS, m_FAbs(m_Value(Src))); + + if (IsFabs) + RHSClass = llvm::inverse_fabs(RHSClass); + + if (Pred == FCmpInst::FCMP_OEQ) + return {Src, RHSClass, fcAllFlags}; + + if (Pred == FCmpInst::FCMP_UEQ) { + FPClassTest Class = RHSClass | fcNan; + return {Src, Class, ~fcNan}; + } + + if (Pred == FCmpInst::FCMP_ONE) + return {Src, ~fcNan, RHSClass}; + + if (Pred == FCmpInst::FCMP_UNE) + return {Src, fcAllFlags, RHSClass}; + + if (IsNegativeRHS) { + // TODO: Handle fneg(fabs) + if (IsFabs) { + // fabs(x) o> -k -> fcmp ord x, x + // fabs(x) u> -k -> true + // fabs(x) o< -k -> false + // fabs(x) u< -k -> fcmp uno x, x + switch (Pred) { + case FCmpInst::FCMP_OGT: + case FCmpInst::FCMP_OGE: + return {Src, ~fcNan, fcNan}; + case FCmpInst::FCMP_UGT: + case FCmpInst::FCMP_UGE: + return {Src, fcAllFlags, fcNone}; + case FCmpInst::FCMP_OLT: + case FCmpInst::FCMP_OLE: + return {Src, fcNone, fcAllFlags}; + case FCmpInst::FCMP_ULT: + case FCmpInst::FCMP_ULE: + return {Src, fcNan, ~fcNan}; + default: + break; + } + + return {nullptr, fcAllFlags, fcAllFlags}; + } + + FPClassTest ClassesLE = fcNegInf | fcNegNormal; + FPClassTest ClassesGE = fcPositive | fcNegZero | fcNegSubnormal; + + if (ConstRHS->isDenormal()) + ClassesLE |= fcNegSubnormal; + else + ClassesGE |= fcNegNormal; + + switch (Pred) { + case FCmpInst::FCMP_OGT: + case FCmpInst::FCMP_OGE: + return {Src, ClassesGE, ~ClassesGE | RHSClass}; + case FCmpInst::FCMP_UGT: + case FCmpInst::FCMP_UGE: + return {Src, ClassesGE | fcNan, ~(ClassesGE | fcNan) | RHSClass}; + case FCmpInst::FCMP_OLT: + case FCmpInst::FCMP_OLE: + return {Src, ClassesLE, ~ClassesLE | RHSClass}; + case FCmpInst::FCMP_ULT: + case FCmpInst::FCMP_ULE: + return {Src, ClassesLE | fcNan, ~(ClassesLE | fcNan) | RHSClass}; + default: + break; + } + } else if (IsPositiveRHS) { + FPClassTest ClassesGE = fcPosNormal | fcPosInf; + FPClassTest ClassesLE = fcNegative | fcPosZero | fcPosNormal; + if (ConstRHS->isDenormal()) + ClassesGE |= fcPosNormal; + else + ClassesLE |= fcPosSubnormal; + + if (IsFabs) { + ClassesGE = llvm::inverse_fabs(ClassesGE); + ClassesLE = llvm::inverse_fabs(ClassesLE); + } + + switch (Pred) { + case FCmpInst::FCMP_OGT: + case FCmpInst::FCMP_OGE: + return {Src, ClassesGE, ~ClassesGE | RHSClass}; + case FCmpInst::FCMP_UGT: + case FCmpInst::FCMP_UGE: + return {Src, ClassesGE | fcNan, ~(ClassesGE | fcNan) | RHSClass}; + case FCmpInst::FCMP_OLT: + case FCmpInst::FCMP_OLE: + return {Src, ClassesLE, ~ClassesLE | RHSClass}; + case FCmpInst::FCMP_ULT: + case FCmpInst::FCMP_ULE: + return {Src, ClassesLE | fcNan, ~(ClassesLE | fcNan) | RHSClass}; + default: + break; + } + } + + return {nullptr, fcAllFlags, fcAllFlags}; +} + +std::tuple +llvm::fcmpImpliesClass(CmpInst::Predicate Pred, const Function &F, Value *LHS, + Value *RHS, bool LookThroughSrc) { + const APFloat *ConstRHS; + if (!match(RHS, m_APFloatAllowUndef(ConstRHS))) + return {nullptr, fcAllFlags, fcNone}; + return fcmpImpliesClass(Pred, F, LHS, ConstRHS, LookThroughSrc); +} + static FPClassTest computeKnownFPClassFromAssumes(const Value *V, const SimplifyQuery &Q) { FPClassTest KnownFromAssume = fcAllFlags; @@ -4188,18 +4329,21 @@ static FPClassTest computeKnownFPClassFromAssumes(const Value *V, Value *LHS, *RHS; uint64_t ClassVal = 0; if (match(I->getArgOperand(0), m_FCmp(Pred, m_Value(LHS), m_Value(RHS)))) { - auto [TestedValue, TestedMask] = - fcmpToClassTest(Pred, *F, LHS, RHS, true); - // First see if we can fold in fabs/fneg into the test. - if (TestedValue == V) - KnownFromAssume &= TestedMask; - else { - // Try again without the lookthrough if we found a different source - // value. - auto [TestedValue, TestedMask] = - fcmpToClassTest(Pred, *F, LHS, RHS, false); - if (TestedValue == V) - KnownFromAssume &= TestedMask; + const APFloat *CRHS; + if (match(RHS, m_APFloat(CRHS))) { + // First see if we can fold in fabs/fneg into the test. + auto [CmpVal, MaskIfTrue, MaskIfFalse] = + fcmpImpliesClass(Pred, *F, LHS, CRHS, true); + if (CmpVal == V) + KnownFromAssume &= MaskIfTrue; + else { + // Try again without the lookthrough if we found a different source + // value. + auto [CmpVal, MaskIfTrue, MaskIfFalse] = + fcmpImpliesClass(Pred, *F, LHS, CRHS, false); + if (CmpVal == V) + KnownFromAssume &= MaskIfTrue; + } } } else if (match(I->getArgOperand(0), m_Intrinsic( @@ -4347,7 +4491,8 @@ void computeKnownFPClass(const Value *V, const APInt &DemandedElts, FPClassTest FilterRHS = fcAllFlags; Value *TestedValue = nullptr; - FPClassTest TestedMask = fcNone; + FPClassTest MaskIfTrue = fcAllFlags; + FPClassTest MaskIfFalse = fcAllFlags; uint64_t ClassVal = 0; const Function *F = cast(Op)->getFunction(); CmpInst::Predicate Pred; @@ -4359,20 +4504,22 @@ void computeKnownFPClass(const Value *V, const APInt &DemandedElts, // TODO: In some degenerate cases we can infer something if we try again // without looking through sign operations. bool LookThroughFAbsFNeg = CmpLHS != LHS && CmpLHS != RHS; - std::tie(TestedValue, TestedMask) = - fcmpToClassTest(Pred, *F, CmpLHS, CmpRHS, LookThroughFAbsFNeg); + std::tie(TestedValue, MaskIfTrue, MaskIfFalse) = + fcmpImpliesClass(Pred, *F, CmpLHS, CmpRHS, LookThroughFAbsFNeg); } else if (match(Cond, m_Intrinsic( m_Value(TestedValue), m_ConstantInt(ClassVal)))) { - TestedMask = static_cast(ClassVal); + FPClassTest TestedMask = static_cast(ClassVal); + MaskIfTrue = TestedMask; + MaskIfFalse = ~TestedMask; } if (TestedValue == LHS) { // match !isnan(x) ? x : y - FilterLHS = TestedMask; - } else if (TestedValue == RHS) { + FilterLHS = MaskIfTrue; + } else if (TestedValue == RHS) { // && IsExactClass // match !isnan(x) ? y : x - FilterRHS = ~TestedMask; + FilterRHS = MaskIfFalse; } KnownFPClass Known2; diff --git a/llvm/test/Transforms/Attributor/nofpclass-implied-by-fcmp.ll b/llvm/test/Transforms/Attributor/nofpclass-implied-by-fcmp.ll index ea594398c580..d19b0ee3dc2d 100644 --- a/llvm/test/Transforms/Attributor/nofpclass-implied-by-fcmp.ll +++ b/llvm/test/Transforms/Attributor/nofpclass-implied-by-fcmp.ll @@ -11,8 +11,8 @@ declare void @llvm.assume(i1 noundef) ; can't be +inf define float @clamp_is_ogt_1_to_1(float %arg) { -; CHECK-LABEL: define float @clamp_is_ogt_1_to_1( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2:[0-9]+]] { +; CHECK-LABEL: define nofpclass(pinf) float @clamp_is_ogt_1_to_1( +; CHECK-SAME: float nofpclass(pinf) [[ARG:%.*]]) #[[ATTR2:[0-9]+]] { ; CHECK-NEXT: [[IS_OGT_1:%.*]] = fcmp ogt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OGT_1]], float 1.000000e+00, float [[ARG]] ; CHECK-NEXT: ret float [[SELECT]] @@ -23,8 +23,8 @@ define float @clamp_is_ogt_1_to_1(float %arg) { } define float @clamp_is_ogt_1_to_1_commute(float %arg) { -; CHECK-LABEL: define float @clamp_is_ogt_1_to_1_commute( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(pinf) float @clamp_is_ogt_1_to_1_commute( +; CHECK-SAME: float nofpclass(pinf) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_ULE_1:%.*]] = fcmp ule float [[ARG]], 1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_ULE_1]], float [[ARG]], float 1.000000e+00 ; CHECK-NEXT: ret float [[SELECT]] @@ -36,8 +36,8 @@ define float @clamp_is_ogt_1_to_1_commute(float %arg) { ; can't be +inf or nan define float @clamp_is_ugt_1_to_1(float %arg) { -; CHECK-LABEL: define float @clamp_is_ugt_1_to_1( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan pinf) float @clamp_is_ugt_1_to_1( +; CHECK-SAME: float nofpclass(nan pinf) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_UGT_1:%.*]] = fcmp ugt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_UGT_1]], float 1.000000e+00, float [[ARG]] ; CHECK-NEXT: ret float [[SELECT]] @@ -49,8 +49,8 @@ define float @clamp_is_ugt_1_to_1(float %arg) { ; can't be +inf or nan define float @clamp_is_ugt_1_to_1_commute(float %arg) { -; CHECK-LABEL: define float @clamp_is_ugt_1_to_1_commute( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan pinf) float @clamp_is_ugt_1_to_1_commute( +; CHECK-SAME: float nofpclass(nan pinf) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_OLE_1:%.*]] = fcmp ole float [[ARG]], 1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OLE_1]], float [[ARG]], float 1.000000e+00 ; CHECK-NEXT: ret float [[SELECT]] @@ -62,8 +62,8 @@ define float @clamp_is_ugt_1_to_1_commute(float %arg) { ; can't be +inf define float @clamp_is_oge_1_to_1(float %arg) { -; CHECK-LABEL: define float @clamp_is_oge_1_to_1( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(pinf) float @clamp_is_oge_1_to_1( +; CHECK-SAME: float nofpclass(pinf) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_OGE_1:%.*]] = fcmp oge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OGE_1]], float 1.000000e+00, float [[ARG]] ; CHECK-NEXT: ret float [[SELECT]] @@ -74,8 +74,8 @@ define float @clamp_is_oge_1_to_1(float %arg) { } define float @clamp_is_oge_1_to_1_commute(float %arg) { -; CHECK-LABEL: define float @clamp_is_oge_1_to_1_commute( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(pinf) float @clamp_is_oge_1_to_1_commute( +; CHECK-SAME: float nofpclass(pinf) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_ULT_1:%.*]] = fcmp ult float [[ARG]], 1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_ULT_1]], float [[ARG]], float 1.000000e+00 ; CHECK-NEXT: ret float [[SELECT]] @@ -87,8 +87,8 @@ define float @clamp_is_oge_1_to_1_commute(float %arg) { ; can't be +inf or nan define float @clamp_is_uge_1_to_1(float %arg) { -; CHECK-LABEL: define float @clamp_is_uge_1_to_1( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan pinf) float @clamp_is_uge_1_to_1( +; CHECK-SAME: float nofpclass(nan pinf) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_UGT_1:%.*]] = fcmp uge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_UGT_1]], float 1.000000e+00, float [[ARG]] ; CHECK-NEXT: ret float [[SELECT]] @@ -100,8 +100,8 @@ define float @clamp_is_uge_1_to_1(float %arg) { ; can't be negative, zero, or denormal define float @clamp_is_olt_1_to_1(float %arg) { -; CHECK-LABEL: define float @clamp_is_olt_1_to_1( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(ninf zero sub nnorm) float @clamp_is_olt_1_to_1( +; CHECK-SAME: float nofpclass(ninf zero sub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_OLT_1:%.*]] = fcmp olt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OLT_1]], float 1.000000e+00, float [[ARG]] ; CHECK-NEXT: ret float [[SELECT]] @@ -113,8 +113,8 @@ define float @clamp_is_olt_1_to_1(float %arg) { ; can't be negative, zero, or denormal define float @clamp_is_olt_1_to_1_commute(float %arg) { -; CHECK-LABEL: define float @clamp_is_olt_1_to_1_commute( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(ninf zero sub nnorm) float @clamp_is_olt_1_to_1_commute( +; CHECK-SAME: float nofpclass(ninf zero sub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_UGE_1:%.*]] = fcmp uge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_UGE_1]], float [[ARG]], float 1.000000e+00 ; CHECK-NEXT: ret float [[SELECT]] @@ -126,8 +126,8 @@ define float @clamp_is_olt_1_to_1_commute(float %arg) { ; can't be negative or zero, nan or denormal define float @clamp_is_ult_1_to_1(float %arg) { -; CHECK-LABEL: define float @clamp_is_ult_1_to_1( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan ninf zero sub nnorm) float @clamp_is_ult_1_to_1( +; CHECK-SAME: float nofpclass(nan ninf zero sub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_ULT_1:%.*]] = fcmp ult float [[ARG]], 1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_ULT_1]], float 1.000000e+00, float [[ARG]] ; CHECK-NEXT: ret float [[SELECT]] @@ -139,8 +139,8 @@ define float @clamp_is_ult_1_to_1(float %arg) { ; can't be negative or zero, nan or denormal define float @clamp_is_ult_1_to_1_commute(float %arg) { -; CHECK-LABEL: define float @clamp_is_ult_1_to_1_commute( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan ninf zero sub nnorm) float @clamp_is_ult_1_to_1_commute( +; CHECK-SAME: float nofpclass(nan ninf zero sub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_OGE_1:%.*]] = fcmp oge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OGE_1]], float [[ARG]], float 1.000000e+00 ; CHECK-NEXT: ret float [[SELECT]] @@ -152,8 +152,8 @@ define float @clamp_is_ult_1_to_1_commute(float %arg) { ; can't be negative, zero or denormal define float @clamp_is_ole_1_to_1(float %arg) { -; CHECK-LABEL: define float @clamp_is_ole_1_to_1( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(ninf zero sub nnorm) float @clamp_is_ole_1_to_1( +; CHECK-SAME: float nofpclass(ninf zero sub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_OLE_1:%.*]] = fcmp ole float [[ARG]], 1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OLE_1]], float 1.000000e+00, float [[ARG]] ; CHECK-NEXT: ret float [[SELECT]] @@ -165,8 +165,8 @@ define float @clamp_is_ole_1_to_1(float %arg) { ; can't be negative or zero, nan or denormal define float @clamp_is_ule_1_to_1(float %arg) { -; CHECK-LABEL: define float @clamp_is_ule_1_to_1( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan ninf zero sub nnorm) float @clamp_is_ule_1_to_1( +; CHECK-SAME: float nofpclass(nan ninf zero sub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_ULE_1:%.*]] = fcmp ule float [[ARG]], 1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_ULE_1]], float 1.000000e+00, float [[ARG]] ; CHECK-NEXT: ret float [[SELECT]] @@ -178,8 +178,8 @@ define float @clamp_is_ule_1_to_1(float %arg) { ; can't be negative or denormal define float @clamp_is_olt_1_to_0(float %arg) { -; CHECK-LABEL: define float @clamp_is_olt_1_to_0( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(ninf nzero sub nnorm) float @clamp_is_olt_1_to_0( +; CHECK-SAME: float nofpclass(ninf nzero sub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_OLT_1:%.*]] = fcmp olt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OLT_1]], float 0.000000e+00, float [[ARG]] ; CHECK-NEXT: ret float [[SELECT]] @@ -191,8 +191,8 @@ define float @clamp_is_olt_1_to_0(float %arg) { ; can't be negative, nan or denormal define float @clamp_is_ult_1_to_0(float %arg) { -; CHECK-LABEL: define float @clamp_is_ult_1_to_0( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(ninf nzero sub nnorm) float @clamp_is_ult_1_to_0( +; CHECK-SAME: float nofpclass(ninf nzero sub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_ULT_1:%.*]] = fcmp olt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_ULT_1]], float 0.000000e+00, float [[ARG]] ; CHECK-NEXT: ret float [[SELECT]] @@ -204,8 +204,8 @@ define float @clamp_is_ult_1_to_0(float %arg) { ; can't be negative or denormal define float @clamp_is_ole_1_to_0(float %arg) { -; CHECK-LABEL: define float @clamp_is_ole_1_to_0( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(ninf nzero sub nnorm) float @clamp_is_ole_1_to_0( +; CHECK-SAME: float nofpclass(ninf nzero sub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_OLE_1:%.*]] = fcmp ole float [[ARG]], 1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OLE_1]], float 0.000000e+00, float [[ARG]] ; CHECK-NEXT: ret float [[SELECT]] @@ -217,8 +217,8 @@ define float @clamp_is_ole_1_to_0(float %arg) { ; can't be negative or denormal define float @clamp_is_ole_1_to_0_commute(float %arg) { -; CHECK-LABEL: define float @clamp_is_ole_1_to_0_commute( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(ninf nzero sub nnorm) float @clamp_is_ole_1_to_0_commute( +; CHECK-SAME: float nofpclass(ninf nzero sub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_UGT_1:%.*]] = fcmp ugt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_UGT_1]], float [[ARG]], float 0.000000e+00 ; CHECK-NEXT: ret float [[SELECT]] @@ -230,8 +230,8 @@ define float @clamp_is_ole_1_to_0_commute(float %arg) { ; can't be negative or denormal define float @clamp_is_ule_1_to_0(float %arg) { -; CHECK-LABEL: define float @clamp_is_ule_1_to_0( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(ninf nzero sub nnorm) float @clamp_is_ule_1_to_0( +; CHECK-SAME: float nofpclass(ninf nzero sub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_ULE_1:%.*]] = fcmp ole float [[ARG]], 1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_ULE_1]], float 0.000000e+00, float [[ARG]] ; CHECK-NEXT: ret float [[SELECT]] @@ -243,8 +243,8 @@ define float @clamp_is_ule_1_to_0(float %arg) { ; can't be positive, zero or denormal define float @clamp_is_ogt_neg1_to_neg1(float %arg) { -; CHECK-LABEL: define float @clamp_is_ogt_neg1_to_neg1( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(pinf zero sub pnorm) float @clamp_is_ogt_neg1_to_neg1( +; CHECK-SAME: float nofpclass(pinf zero sub pnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_OGT_NEG1:%.*]] = fcmp ogt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OGT_NEG1]], float -1.000000e+00, float [[ARG]] ; CHECK-NEXT: ret float [[SELECT]] @@ -256,8 +256,8 @@ define float @clamp_is_ogt_neg1_to_neg1(float %arg) { ; can't be positive, zero, nan or denormal define float @clamp_is_ugt_neg1_to_neg1(float %arg) { -; CHECK-LABEL: define float @clamp_is_ugt_neg1_to_neg1( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan pinf zero sub pnorm) float @clamp_is_ugt_neg1_to_neg1( +; CHECK-SAME: float nofpclass(nan pinf zero sub pnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_UGT_NEG1:%.*]] = fcmp ugt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_UGT_NEG1]], float -1.000000e+00, float [[ARG]] ; CHECK-NEXT: ret float [[SELECT]] @@ -269,8 +269,8 @@ define float @clamp_is_ugt_neg1_to_neg1(float %arg) { ; can't be positive or denormal define float @clamp_is_ogt_neg1_to_0(float %arg) { -; CHECK-LABEL: define float @clamp_is_ogt_neg1_to_0( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(pinf nzero sub pnorm) float @clamp_is_ogt_neg1_to_0( +; CHECK-SAME: float nofpclass(pinf nzero sub pnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_OGT_NEG1:%.*]] = fcmp ogt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OGT_NEG1]], float 0.000000e+00, float [[ARG]] ; CHECK-NEXT: ret float [[SELECT]] @@ -282,8 +282,8 @@ define float @clamp_is_ogt_neg1_to_0(float %arg) { ; can't be positive, nan or denormal define float @clamp_is_ugt_neg1_to_0(float %arg) { -; CHECK-LABEL: define float @clamp_is_ugt_neg1_to_0( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan pinf nzero sub pnorm) float @clamp_is_ugt_neg1_to_0( +; CHECK-SAME: float nofpclass(nan pinf nzero sub pnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_UGT_NEG1:%.*]] = fcmp ugt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_UGT_NEG1]], float 0.000000e+00, float [[ARG]] ; CHECK-NEXT: ret float [[SELECT]] @@ -295,8 +295,8 @@ define float @clamp_is_ugt_neg1_to_0(float %arg) { ; can't be -inf define float @clamp_is_olt_neg1_to_neg1_commute(float %arg) { -; CHECK-LABEL: define float @clamp_is_olt_neg1_to_neg1_commute( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(ninf) float @clamp_is_olt_neg1_to_neg1_commute( +; CHECK-SAME: float nofpclass(ninf) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_UGE_NEG1:%.*]] = fcmp uge float [[ARG]], -1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_UGE_NEG1]], float [[ARG]], float -1.000000e+00 ; CHECK-NEXT: ret float [[SELECT]] @@ -308,8 +308,8 @@ define float @clamp_is_olt_neg1_to_neg1_commute(float %arg) { ; can't be -inf define float @clamp_is_olt_neg1_to_neg1(float %arg) { -; CHECK-LABEL: define float @clamp_is_olt_neg1_to_neg1( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(ninf) float @clamp_is_olt_neg1_to_neg1( +; CHECK-SAME: float nofpclass(ninf) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OLT_NEG1]], float -1.000000e+00, float [[ARG]] ; CHECK-NEXT: ret float [[SELECT]] @@ -321,8 +321,8 @@ define float @clamp_is_olt_neg1_to_neg1(float %arg) { ; can't be -inf or nan define float @clamp_is_ult_neg1_to_neg1(float %arg) { -; CHECK-LABEL: define float @clamp_is_ult_neg1_to_neg1( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan ninf) float @clamp_is_ult_neg1_to_neg1( +; CHECK-SAME: float nofpclass(nan ninf) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_ULT_NEG1:%.*]] = fcmp ult float [[ARG]], -1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_ULT_NEG1]], float -1.000000e+00, float [[ARG]] ; CHECK-NEXT: ret float [[SELECT]] @@ -334,8 +334,8 @@ define float @clamp_is_ult_neg1_to_neg1(float %arg) { ; can't be -inf or nan define float @clamp_is_ult_neg1_to_neg1_commute(float %arg) { -; CHECK-LABEL: define float @clamp_is_ult_neg1_to_neg1_commute( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan ninf) float @clamp_is_ult_neg1_to_neg1_commute( +; CHECK-SAME: float nofpclass(nan ninf) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_OGE_NEG1:%.*]] = fcmp oge float [[ARG]], -1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OGE_NEG1]], float [[ARG]], float -1.000000e+00 ; CHECK-NEXT: ret float [[SELECT]] @@ -351,8 +351,8 @@ define float @clamp_is_ult_neg1_to_neg1_commute(float %arg) { ; Must be 1, only posnormal define float @fcmp_oeq_1_else_1(float %arg) { -; CHECK-LABEL: define float @fcmp_oeq_1_else_1( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan inf zero sub nnorm) float @fcmp_oeq_1_else_1( +; CHECK-SAME: float nofpclass(nan inf zero sub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_OEQ_1:%.*]] = fcmp oeq float [[ARG]], 1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OEQ_1]], float [[ARG]], float 1.000000e+00 ; CHECK-NEXT: ret float [[SELECT]] @@ -364,8 +364,8 @@ define float @fcmp_oeq_1_else_1(float %arg) { ; Don't know anything define float @fcmp_one_1_else_1(float %arg) { -; CHECK-LABEL: define float @fcmp_one_1_else_1( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan) float @fcmp_one_1_else_1( +; CHECK-SAME: float nofpclass(nan) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_ONE_1:%.*]] = fcmp one float [[ARG]], 1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_ONE_1]], float [[ARG]], float 1.000000e+00 ; CHECK-NEXT: ret float [[SELECT]] @@ -377,8 +377,8 @@ define float @fcmp_one_1_else_1(float %arg) { ; must be 1 define float @fcmp_one_1_1_else_arg(float %arg) { -; CHECK-LABEL: define float @fcmp_one_1_1_else_arg( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan inf zero sub nnorm) float @fcmp_one_1_1_else_arg( +; CHECK-SAME: float nofpclass(nan inf zero sub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_ONE_1:%.*]] = fcmp one float [[ARG]], 1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_ONE_1]], float 1.000000e+00, float [[ARG]] ; CHECK-NEXT: ret float [[SELECT]] @@ -390,8 +390,8 @@ define float @fcmp_one_1_1_else_arg(float %arg) { ; must be 1 define float @fcmp_une_1_1_else_arg(float %arg) { -; CHECK-LABEL: define float @fcmp_une_1_1_else_arg( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan inf zero sub nnorm) float @fcmp_une_1_1_else_arg( +; CHECK-SAME: float nofpclass(nan inf zero sub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_UNE_1:%.*]] = fcmp une float [[ARG]], 1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_UNE_1]], float 1.000000e+00, float [[ARG]] ; CHECK-NEXT: ret float [[SELECT]] @@ -403,8 +403,8 @@ define float @fcmp_une_1_1_else_arg(float %arg) { ; Must be -1, only negnormal define float @fcmp_oeq_neg1_else_neg1(float %arg) { -; CHECK-LABEL: define float @fcmp_oeq_neg1_else_neg1( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan inf zero sub pnorm) float @fcmp_oeq_neg1_else_neg1( +; CHECK-SAME: float nofpclass(nan inf zero sub pnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_OEQ_NEG1:%.*]] = fcmp oeq float [[ARG]], -1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OEQ_NEG1]], float [[ARG]], float -1.000000e+00 ; CHECK-NEXT: ret float [[SELECT]] @@ -416,8 +416,8 @@ define float @fcmp_oeq_neg1_else_neg1(float %arg) { ; Don't know anything define float @fcmp_one_neg1_else_neg1(float %arg) { -; CHECK-LABEL: define float @fcmp_one_neg1_else_neg1( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan) float @fcmp_one_neg1_else_neg1( +; CHECK-SAME: float nofpclass(nan) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_ONE_NEG1:%.*]] = fcmp one float [[ARG]], -1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_ONE_NEG1]], float [[ARG]], float -1.000000e+00 ; CHECK-NEXT: ret float [[SELECT]] @@ -512,8 +512,8 @@ define float @if_fcmp_one_0_1_else_arg(float %arg) { } define float @if_fcmp_one_1_arg_else_0(float %arg) { -; CHECK-LABEL: define float @if_fcmp_one_1_arg_else_0( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan) float @if_fcmp_one_1_arg_else_0( +; CHECK-SAME: float nofpclass(nan) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_ONE_1:%.*]] = fcmp one float [[ARG]], 1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_ONE_1]], float [[ARG]], float 0.000000e+00 ; CHECK-NEXT: ret float [[SELECT]] @@ -524,8 +524,8 @@ define float @if_fcmp_one_1_arg_else_0(float %arg) { } define float @fcmp_fabs_oeq_1_else_1(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @fcmp_fabs_oeq_1_else_1( -; CHECK-SAME: float nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan inf zero sub nnorm) float @fcmp_fabs_oeq_1_else_1( +; CHECK-SAME: float nofpclass(nan inf zero sub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4:[0-9]+]] ; CHECK-NEXT: [[FABS_IS_OEQ_1:%.*]] = fcmp oeq float [[FABS_ARG]], 1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[FABS_IS_OEQ_1]], float [[ARG]], float 1.000000e+00 @@ -552,8 +552,8 @@ define float @fcmp_fabs_oeq_1_0_else_arg(float %arg) { } define float @fcmp_fabs_ueq_1_0_else_arg(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @fcmp_fabs_ueq_1_0_else_arg( -; CHECK-SAME: float nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan ninf nzero nsub nnorm) float @fcmp_fabs_ueq_1_0_else_arg( +; CHECK-SAME: float nofpclass(nan ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[FABS_IS_UEQ_1:%.*]] = fcmp ueq float [[FABS_ARG]], 1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[FABS_IS_UEQ_1]], float 0.000000e+00, float [[ARG]] @@ -566,8 +566,8 @@ define float @fcmp_fabs_ueq_1_0_else_arg(float %arg) { } define float @fcmp_fabs_one_1_arg_else_0(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @fcmp_fabs_one_1_arg_else_0( -; CHECK-SAME: float nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan ninf nzero nsub nnorm) float @fcmp_fabs_one_1_arg_else_0( +; CHECK-SAME: float nofpclass(nan ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[FABS_IS_ONE_1:%.*]] = fcmp one float [[FABS_ARG]], 1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[FABS_IS_ONE_1]], float [[ARG]], float 0.000000e+00 @@ -594,8 +594,8 @@ define float @fcmp_fabs_une_1_arg_else_0(float %arg) { } define float @fcmp_fabs_one_1_0_else_arg(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @fcmp_fabs_one_1_0_else_arg( -; CHECK-SAME: float nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan inf nzero sub nnorm) float @fcmp_fabs_one_1_0_else_arg( +; CHECK-SAME: float nofpclass(nan inf nzero sub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[FABS_IS_ONE_1:%.*]] = fcmp one float [[FABS_ARG]], 1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[FABS_IS_ONE_1]], float 0.000000e+00, float [[ARG]] @@ -608,8 +608,8 @@ define float @fcmp_fabs_one_1_0_else_arg(float %arg) { } define float @fcmp_fabs_une_1_0_else_arg(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @fcmp_fabs_une_1_0_else_arg( -; CHECK-SAME: float nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan inf nzero sub nnorm) float @fcmp_fabs_une_1_0_else_arg( +; CHECK-SAME: float nofpclass(nan inf nzero sub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[FABS_IS_UNE_1:%.*]] = fcmp une float [[FABS_ARG]], 1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[FABS_IS_UNE_1]], float 0.000000e+00, float [[ARG]] @@ -622,8 +622,8 @@ define float @fcmp_fabs_une_1_0_else_arg(float %arg) { } define float @fcmp_fabs_one_1_neg2_else_arg(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub) float @fcmp_fabs_one_1_neg2_else_arg( -; CHECK-SAME: float nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan inf zero sub) float @fcmp_fabs_one_1_neg2_else_arg( +; CHECK-SAME: float nofpclass(nan inf zero sub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[FABS_IS_ONE_1:%.*]] = fcmp one float [[FABS_ARG]], 1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[FABS_IS_ONE_1]], float -2.000000e+00, float [[ARG]] @@ -640,8 +640,8 @@ define float @fcmp_fabs_one_1_neg2_else_arg(float %arg) { ;--------------------------------------------------------------------- define float @clamp_olt_largest_denormal_0.0(float %arg) { -; CHECK-LABEL: define float @clamp_olt_largest_denormal_0.0( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(ninf nzero nsub norm) float @clamp_olt_largest_denormal_0.0( +; CHECK-SAME: float nofpclass(ninf nzero nsub norm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_OLT_LARGEST_DENORMAL:%.*]] = fcmp olt float [[ARG]], 0x380FFFFFC0000000 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OLT_LARGEST_DENORMAL]], float 0.000000e+00, float [[ARG]] ; CHECK-NEXT: ret float [[SELECT]] @@ -652,8 +652,8 @@ define float @clamp_olt_largest_denormal_0.0(float %arg) { } define float @clamp_ole_largest_denormal_0.0(float %arg) { -; CHECK-LABEL: define float @clamp_ole_largest_denormal_0.0( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(ninf nzero nsub norm) float @clamp_ole_largest_denormal_0.0( +; CHECK-SAME: float nofpclass(ninf nzero nsub norm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_OLE_LARGEST_DENORMAL:%.*]] = fcmp ole float [[ARG]], 0x380FFFFFC0000000 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OLE_LARGEST_DENORMAL]], float 0.000000e+00, float [[ARG]] ; CHECK-NEXT: ret float [[SELECT]] @@ -664,8 +664,8 @@ define float @clamp_ole_largest_denormal_0.0(float %arg) { } define float @clamp_ult_largest_denormal_0.0(float %arg) { -; CHECK-LABEL: define float @clamp_ult_largest_denormal_0.0( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan ninf nzero nsub norm) float @clamp_ult_largest_denormal_0.0( +; CHECK-SAME: float nofpclass(nan ninf nzero nsub norm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_ULT_LARGEST_DENORMAL:%.*]] = fcmp ult float [[ARG]], 0x380FFFFFC0000000 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_ULT_LARGEST_DENORMAL]], float 0.000000e+00, float [[ARG]] ; CHECK-NEXT: ret float [[SELECT]] @@ -676,8 +676,8 @@ define float @clamp_ult_largest_denormal_0.0(float %arg) { } define float @clamp_ule_largest_denormal_0.0(float %arg) { -; CHECK-LABEL: define float @clamp_ule_largest_denormal_0.0( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan ninf nzero nsub norm) float @clamp_ule_largest_denormal_0.0( +; CHECK-SAME: float nofpclass(nan ninf nzero nsub norm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_ULE_LARGEST_DENORMAL:%.*]] = fcmp ule float [[ARG]], 0x380FFFFFC0000000 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_ULE_LARGEST_DENORMAL]], float 0.000000e+00, float [[ARG]] ; CHECK-NEXT: ret float [[SELECT]] @@ -688,8 +688,8 @@ define float @clamp_ule_largest_denormal_0.0(float %arg) { } define float @clamp_ogt_largest_denormal_0.0(float %arg) { -; CHECK-LABEL: define float @clamp_ogt_largest_denormal_0.0( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(ninf nzero sub nnorm) float @clamp_ogt_largest_denormal_0.0( +; CHECK-SAME: float nofpclass(ninf nzero sub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_OGT_LARGEST_DENORMAL:%.*]] = fcmp ugt float [[ARG]], 0x380FFFFFC0000000 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OGT_LARGEST_DENORMAL]], float [[ARG]], float 0.000000e+00 ; CHECK-NEXT: ret float [[SELECT]] @@ -700,8 +700,8 @@ define float @clamp_ogt_largest_denormal_0.0(float %arg) { } define float @clamp_oge_largest_denormal_0.0(float %arg) { -; CHECK-LABEL: define float @clamp_oge_largest_denormal_0.0( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan ninf nzero sub nnorm) float @clamp_oge_largest_denormal_0.0( +; CHECK-SAME: float nofpclass(nan ninf nzero sub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_OGE_LARGEST_DENORMAL:%.*]] = fcmp oge float [[ARG]], 0x380FFFFFC0000000 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OGE_LARGEST_DENORMAL]], float [[ARG]], float 0.000000e+00 ; CHECK-NEXT: ret float [[SELECT]] @@ -712,8 +712,8 @@ define float @clamp_oge_largest_denormal_0.0(float %arg) { } define float @clamp_ugt_largest_denormal_0.0(float %arg) { -; CHECK-LABEL: define float @clamp_ugt_largest_denormal_0.0( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(ninf nzero sub nnorm) float @clamp_ugt_largest_denormal_0.0( +; CHECK-SAME: float nofpclass(ninf nzero sub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_UGT_LARGEST_DENORMAL:%.*]] = fcmp ugt float [[ARG]], 0x380FFFFFC0000000 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_UGT_LARGEST_DENORMAL]], float [[ARG]], float 0.000000e+00 ; CHECK-NEXT: ret float [[SELECT]] @@ -724,8 +724,8 @@ define float @clamp_ugt_largest_denormal_0.0(float %arg) { } define float @clamp_uge_largest_denormal_0.0(float %arg) { -; CHECK-LABEL: define float @clamp_uge_largest_denormal_0.0( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(ninf nzero sub nnorm) float @clamp_uge_largest_denormal_0.0( +; CHECK-SAME: float nofpclass(ninf nzero sub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_UGE_LARGEST_DENORMAL:%.*]] = fcmp uge float [[ARG]], 0x380FFFFFC0000000 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_UGE_LARGEST_DENORMAL]], float [[ARG]], float 0.000000e+00 ; CHECK-NEXT: ret float [[SELECT]] @@ -736,8 +736,8 @@ define float @clamp_uge_largest_denormal_0.0(float %arg) { } define float @fcmp_oeq_largest_denormal_arg_else_0.0(float %arg) { -; CHECK-LABEL: define float @fcmp_oeq_largest_denormal_arg_else_0.0( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan inf nzero nsub norm) float @fcmp_oeq_largest_denormal_arg_else_0.0( +; CHECK-SAME: float nofpclass(nan inf nzero nsub norm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_OEQ_LARGEST_DENORMAL:%.*]] = fcmp oeq float [[ARG]], 0x380FFFFFC0000000 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OEQ_LARGEST_DENORMAL]], float [[ARG]], float 0.000000e+00 ; CHECK-NEXT: ret float [[SELECT]] @@ -893,8 +893,8 @@ define float @clamp_fabs_value_ule_1_to_1_copysign(float %arg) { ; Can't be +inf define float @clamp_is_ogt_largest_normal_to_largest_normal(float %arg) { -; CHECK-LABEL: define float @clamp_is_ogt_largest_normal_to_largest_normal( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(pinf) float @clamp_is_ogt_largest_normal_to_largest_normal( +; CHECK-SAME: float nofpclass(pinf) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_OGT_LARGEST_NORMAL:%.*]] = fcmp ogt float [[ARG]], 0x47EFFFFFE0000000 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OGT_LARGEST_NORMAL]], float 0x47EFFFFFE0000000, float [[ARG]] ; CHECK-NEXT: ret float [[SELECT]] @@ -906,8 +906,8 @@ define float @clamp_is_ogt_largest_normal_to_largest_normal(float %arg) { ; Can't be +inf define float @clamp_is_oge_largest_normal_to_largest_normal(float %arg) { -; CHECK-LABEL: define float @clamp_is_oge_largest_normal_to_largest_normal( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(pinf) float @clamp_is_oge_largest_normal_to_largest_normal( +; CHECK-SAME: float nofpclass(pinf) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_OGE_LARGEST_NORMAL:%.*]] = fcmp oge float [[ARG]], 0x47EFFFFFE0000000 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OGE_LARGEST_NORMAL]], float 0x47EFFFFFE0000000, float [[ARG]] ; CHECK-NEXT: ret float [[SELECT]] @@ -919,8 +919,8 @@ define float @clamp_is_oge_largest_normal_to_largest_normal(float %arg) { ; Can't be +inf or nan define float @clamp_is_ugt_largest_normal_to_largest_normal(float %arg) { -; CHECK-LABEL: define float @clamp_is_ugt_largest_normal_to_largest_normal( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan pinf) float @clamp_is_ugt_largest_normal_to_largest_normal( +; CHECK-SAME: float nofpclass(nan pinf) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_UGT_LARGEST_NORMAL:%.*]] = fcmp ugt float [[ARG]], 0x47EFFFFFE0000000 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_UGT_LARGEST_NORMAL]], float 0x47EFFFFFE0000000, float [[ARG]] ; CHECK-NEXT: ret float [[SELECT]] @@ -932,8 +932,8 @@ define float @clamp_is_ugt_largest_normal_to_largest_normal(float %arg) { ; Can't be +inf or nan define float @clamp_is_uge_largest_normal_to_largest_normal(float %arg) { -; CHECK-LABEL: define float @clamp_is_uge_largest_normal_to_largest_normal( -; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan pinf) float @clamp_is_uge_largest_normal_to_largest_normal( +; CHECK-SAME: float nofpclass(nan pinf) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[IS_UGE_LARGEST_NORMAL:%.*]] = fcmp uge float [[ARG]], 0x47EFFFFFE0000000 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_UGE_LARGEST_NORMAL]], float 0x47EFFFFFE0000000, float [[ARG]] ; CHECK-NEXT: ret float [[SELECT]] @@ -945,8 +945,8 @@ define float @clamp_is_uge_largest_normal_to_largest_normal(float %arg) { ; Can't be +inf or -inf define float @clamp_fabs_is_ogt_largest_normal_to_largest_normal(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @clamp_fabs_is_ogt_largest_normal_to_largest_normal( -; CHECK-SAME: float nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(inf nzero nsub nnorm) float @clamp_fabs_is_ogt_largest_normal_to_largest_normal( +; CHECK-SAME: float nofpclass(inf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[IS_OGT_LARGEST_NORMAL:%.*]] = fcmp ogt float [[FABS_ARG]], 0x47EFFFFFE0000000 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OGT_LARGEST_NORMAL]], float 0x47EFFFFFE0000000, float [[ARG]] @@ -960,8 +960,8 @@ define float @clamp_fabs_is_ogt_largest_normal_to_largest_normal(float %arg) { ; Can't be +inf or -inf define float @clamp_fabs_is_oge_largest_normal_to_largest_normal(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @clamp_fabs_is_oge_largest_normal_to_largest_normal( -; CHECK-SAME: float nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(inf nzero nsub nnorm) float @clamp_fabs_is_oge_largest_normal_to_largest_normal( +; CHECK-SAME: float nofpclass(inf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[IS_OGE_LARGEST_NORMAL:%.*]] = fcmp oge float [[FABS_ARG]], 0x47EFFFFFE0000000 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OGE_LARGEST_NORMAL]], float 0x47EFFFFFE0000000, float [[ARG]] @@ -975,8 +975,8 @@ define float @clamp_fabs_is_oge_largest_normal_to_largest_normal(float %arg) { ; Can't be +inf or -inf or nan define float @clamp_fabs_is_ugt_largest_normal_to_largest_normal(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @clamp_fabs_is_ugt_largest_normal_to_largest_normal( -; CHECK-SAME: float nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan inf nzero nsub nnorm) float @clamp_fabs_is_ugt_largest_normal_to_largest_normal( +; CHECK-SAME: float nofpclass(nan inf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[IS_UGT_LARGEST_NORMAL:%.*]] = fcmp ugt float [[FABS_ARG]], 0x47EFFFFFE0000000 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_UGT_LARGEST_NORMAL]], float 0x47EFFFFFE0000000, float [[ARG]] @@ -990,8 +990,8 @@ define float @clamp_fabs_is_ugt_largest_normal_to_largest_normal(float %arg) { ; Can't be +inf or -inf or nan define float @clamp_fabs_is_uge_largest_normal_to_largest_normal(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @clamp_fabs_is_uge_largest_normal_to_largest_normal( -; CHECK-SAME: float nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan inf nzero nsub nnorm) float @clamp_fabs_is_uge_largest_normal_to_largest_normal( +; CHECK-SAME: float nofpclass(nan inf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[IS_UGT_LARGEST_NORMAL:%.*]] = fcmp uge float [[FABS_ARG]], 0x47EFFFFFE0000000 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_UGT_LARGEST_NORMAL]], float 0x47EFFFFFE0000000, float [[ARG]] @@ -1009,8 +1009,8 @@ define float @clamp_fabs_is_uge_largest_normal_to_largest_normal(float %arg) { ; can't be negative or positive subnormal define float @clamp_fabs_ogt_smallest_normal_to_zero(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @clamp_fabs_ogt_smallest_normal_to_zero( -; CHECK-SAME: float nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(inf nzero nsub nnorm) float @clamp_fabs_ogt_smallest_normal_to_zero( +; CHECK-SAME: float nofpclass(inf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[IS_OGT_SMALLEST_NORMAL:%.*]] = fcmp ogt float [[FABS_ARG]], 0x3810000000000000 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OGT_SMALLEST_NORMAL]], float 0.000000e+00, float [[ARG]] @@ -1055,8 +1055,8 @@ define float @clamp_fabs_olt_smallest_normal_to_zero(float %arg) { ; can't be negative or subnormal define float @clamp_fabs_ole_smallest_normal_to_zero(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @clamp_fabs_ole_smallest_normal_to_zero( -; CHECK-SAME: float nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(ninf nzero sub nnorm) float @clamp_fabs_ole_smallest_normal_to_zero( +; CHECK-SAME: float nofpclass(ninf nzero sub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[IS_OLE_SMALLEST_NORMAL:%.*]] = fcmp ole float [[FABS_ARG]], 0x3810000000000000 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OLE_SMALLEST_NORMAL]], float 0.000000e+00, float [[ARG]] @@ -1083,8 +1083,8 @@ define float @clamp_fabs_is_is_olt_smallest_normal_to_0(float %arg) { } define float @clamp_fabs_is_is_ole_smallest_normal_to_0(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @clamp_fabs_is_is_ole_smallest_normal_to_0( -; CHECK-SAME: float nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(ninf nzero sub nnorm) float @clamp_fabs_is_is_ole_smallest_normal_to_0( +; CHECK-SAME: float nofpclass(ninf nzero sub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[IS_OLE_SMALLEST_NORMAL:%.*]] = fcmp ole float [[FABS_ARG]], 0x3810000000000000 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OLE_SMALLEST_NORMAL]], float 0.000000e+00, float [[ARG]] @@ -1111,8 +1111,8 @@ define float @clamp_fabs_oeq_smallest_normal_to_zero(float %arg) { } define float @clamp_fabs_one_smallest_normal_to_zero(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @clamp_fabs_one_smallest_normal_to_zero( -; CHECK-SAME: float nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan inf nzero sub nnorm) float @clamp_fabs_one_smallest_normal_to_zero( +; CHECK-SAME: float nofpclass(nan inf nzero sub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[IS_ONE_SMALLEST_NORMAL:%.*]] = fcmp one float [[FABS_ARG]], 0x3810000000000000 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_ONE_SMALLEST_NORMAL]], float 0.000000e+00, float [[ARG]] @@ -1125,8 +1125,8 @@ define float @clamp_fabs_one_smallest_normal_to_zero(float %arg) { } define float @clamp_fabs_ueq_smallest_normal_to_zero(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @clamp_fabs_ueq_smallest_normal_to_zero( -; CHECK-SAME: float nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan ninf nzero nsub nnorm) float @clamp_fabs_ueq_smallest_normal_to_zero( +; CHECK-SAME: float nofpclass(nan ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[IS_UEQ_SMALLEST_NORMAL:%.*]] = fcmp ueq float [[FABS_ARG]], 0x3810000000000000 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_UEQ_SMALLEST_NORMAL]], float 0.000000e+00, float [[ARG]] @@ -1139,8 +1139,8 @@ define float @clamp_fabs_ueq_smallest_normal_to_zero(float %arg) { } define float @clamp_fabs_une_smallest_normal_to_zero(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @clamp_fabs_une_smallest_normal_to_zero( -; CHECK-SAME: float nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan inf nzero sub nnorm) float @clamp_fabs_une_smallest_normal_to_zero( +; CHECK-SAME: float nofpclass(nan inf nzero sub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[IS_UNE_SMALLEST_NORMAL:%.*]] = fcmp une float [[FABS_ARG]], 0x3810000000000000 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_UNE_SMALLEST_NORMAL]], float 0.000000e+00, float [[ARG]] @@ -1179,8 +1179,8 @@ define float @clamp_fabs_ole_neg1_to_neg1(float %arg) { } define float @clamp_fabs_ult_neg1_to_neg1(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub) float @clamp_fabs_ult_neg1_to_neg1( -; CHECK-SAME: float nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan ninf nzero nsub) float @clamp_fabs_ult_neg1_to_neg1( +; CHECK-SAME: float nofpclass(nan ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[FABS_IS_ULT_NEG1:%.*]] = fcmp ult float [[FABS_ARG]], -1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[FABS_IS_ULT_NEG1]], float -1.000000e+00, float [[ARG]] @@ -1193,8 +1193,8 @@ define float @clamp_fabs_ult_neg1_to_neg1(float %arg) { } define float @clamp_fabs_ule_neg1_to_neg1(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub) float @clamp_fabs_ule_neg1_to_neg1( -; CHECK-SAME: float nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan ninf nzero nsub) float @clamp_fabs_ule_neg1_to_neg1( +; CHECK-SAME: float nofpclass(nan ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[FABS_IS_ULE_NEG1:%.*]] = fcmp ule float [[FABS_ARG]], -1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[FABS_IS_ULE_NEG1]], float -1.000000e+00, float [[ARG]] @@ -1207,8 +1207,8 @@ define float @clamp_fabs_ule_neg1_to_neg1(float %arg) { } define float @clamp_fabs_ogt_neg1_to_neg1(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub) float @clamp_fabs_ogt_neg1_to_neg1( -; CHECK-SAME: float nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(inf zero sub pnorm) float @clamp_fabs_ogt_neg1_to_neg1( +; CHECK-SAME: float nofpclass(inf zero sub norm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[FABS_IS_OGT_NEG1:%.*]] = fcmp ogt float [[FABS_ARG]], -1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[FABS_IS_OGT_NEG1]], float -1.000000e+00, float [[ARG]] @@ -1221,8 +1221,8 @@ define float @clamp_fabs_ogt_neg1_to_neg1(float %arg) { } define float @clamp_fabs_oge_neg1_to_neg1(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub) float @clamp_fabs_oge_neg1_to_neg1( -; CHECK-SAME: float nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(inf zero sub pnorm) float @clamp_fabs_oge_neg1_to_neg1( +; CHECK-SAME: float nofpclass(inf zero sub norm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[FABS_IS_OGE_NEG1:%.*]] = fcmp oge float [[FABS_ARG]], -1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[FABS_IS_OGE_NEG1]], float -1.000000e+00, float [[ARG]] @@ -1236,7 +1236,7 @@ define float @clamp_fabs_oge_neg1_to_neg1(float %arg) { define float @clamp_fabs_ugt_neg1_to_neg1(float %arg) { ; CHECK-LABEL: define noundef nofpclass(nan inf zero sub pnorm) float @clamp_fabs_ugt_neg1_to_neg1( -; CHECK-SAME: float nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-SAME: float nofpclass(all) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: ret float -1.000000e+00 ; %fabs.arg = call float @llvm.fabs.f32(float %arg) @@ -1247,7 +1247,7 @@ define float @clamp_fabs_ugt_neg1_to_neg1(float %arg) { define float @clamp_fabs_uge_neg1_to_neg1(float %arg) { ; CHECK-LABEL: define noundef nofpclass(nan inf zero sub pnorm) float @clamp_fabs_uge_neg1_to_neg1( -; CHECK-SAME: float nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-SAME: float nofpclass(all) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: ret float -1.000000e+00 ; %fabs.arg = call float @llvm.fabs.f32(float %arg) @@ -1268,8 +1268,8 @@ define float @clamp_fabs_oeq_neg1_to_neg1(float %arg) { } define float @clamp_fabs_ueq_neg1_to_neg1(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub) float @clamp_fabs_ueq_neg1_to_neg1( -; CHECK-SAME: float nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan ninf nzero nsub) float @clamp_fabs_ueq_neg1_to_neg1( +; CHECK-SAME: float nofpclass(nan ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[FABS_IS_UEQ_NEG1:%.*]] = fcmp ueq float [[FABS_ARG]], -1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[FABS_IS_UEQ_NEG1]], float -1.000000e+00, float [[ARG]] @@ -1282,8 +1282,8 @@ define float @clamp_fabs_ueq_neg1_to_neg1(float %arg) { } define float @clamp_fabs_one_neg1_to_neg1(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub) float @clamp_fabs_one_neg1_to_neg1( -; CHECK-SAME: float nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-LABEL: define nofpclass(nan inf zero sub pnorm) float @clamp_fabs_one_neg1_to_neg1( +; CHECK-SAME: float nofpclass(all) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[FABS_IS_ONE_NEG1:%.*]] = fcmp one float [[FABS_ARG]], -1.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[FABS_IS_ONE_NEG1]], float -1.000000e+00, float [[ARG]] @@ -1297,7 +1297,7 @@ define float @clamp_fabs_one_neg1_to_neg1(float %arg) { define float @clamp_fabs_une_neg1_to_neg1(float %arg) { ; CHECK-LABEL: define noundef nofpclass(nan inf zero sub pnorm) float @clamp_fabs_une_neg1_to_neg1( -; CHECK-SAME: float nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR2]] { +; CHECK-SAME: float nofpclass(all) [[ARG:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: ret float -1.000000e+00 ; %fabs.arg = call float @llvm.fabs.f32(float %arg) @@ -1311,8 +1311,8 @@ define float @clamp_fabs_une_neg1_to_neg1(float %arg) { ;--------------------------------------------------------------------- define float @ret_assumed_ogt_1(float %arg) { -; CHECK-LABEL: define float @ret_assumed_ogt_1( -; CHECK-SAME: float returned [[ARG:%.*]]) #[[ATTR3:[0-9]+]] { +; CHECK-LABEL: define nofpclass(nan ninf zero sub nnorm) float @ret_assumed_ogt_1( +; CHECK-SAME: float returned nofpclass(nan ninf zero sub nnorm) [[ARG:%.*]]) #[[ATTR3:[0-9]+]] { ; CHECK-NEXT: [[OGT_1:%.*]] = fcmp ogt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[OGT_1]]) #[[ATTR5:[0-9]+]] ; CHECK-NEXT: ret float [[ARG]] @@ -1323,8 +1323,8 @@ define float @ret_assumed_ogt_1(float %arg) { } define float @ret_assumed_oge_1(float %arg) { -; CHECK-LABEL: define float @ret_assumed_oge_1( -; CHECK-SAME: float returned [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(nan ninf zero sub nnorm) float @ret_assumed_oge_1( +; CHECK-SAME: float returned nofpclass(nan ninf zero sub nnorm) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[OGE_1:%.*]] = fcmp ogt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[OGE_1]]) #[[ATTR5]] ; CHECK-NEXT: ret float [[ARG]] @@ -1335,8 +1335,8 @@ define float @ret_assumed_oge_1(float %arg) { } define float @ret_assumed_olt_1(float %arg) { -; CHECK-LABEL: define float @ret_assumed_olt_1( -; CHECK-SAME: float returned [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(nan pinf) float @ret_assumed_olt_1( +; CHECK-SAME: float returned nofpclass(nan pinf) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[OLT_1:%.*]] = fcmp olt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[OLT_1]]) #[[ATTR5]] ; CHECK-NEXT: ret float [[ARG]] @@ -1347,8 +1347,8 @@ define float @ret_assumed_olt_1(float %arg) { } define float @ret_assumed_ole_1(float %arg) { -; CHECK-LABEL: define float @ret_assumed_ole_1( -; CHECK-SAME: float returned [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(nan pinf) float @ret_assumed_ole_1( +; CHECK-SAME: float returned nofpclass(nan pinf) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[OLE_1:%.*]] = fcmp ole float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[OLE_1]]) #[[ATTR5]] ; CHECK-NEXT: ret float [[ARG]] @@ -1359,8 +1359,8 @@ define float @ret_assumed_ole_1(float %arg) { } define float @ret_assumed_ugt_1(float %arg) { -; CHECK-LABEL: define float @ret_assumed_ugt_1( -; CHECK-SAME: float returned [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(ninf zero sub nnorm) float @ret_assumed_ugt_1( +; CHECK-SAME: float returned nofpclass(ninf zero sub nnorm) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[UGT_1:%.*]] = fcmp ugt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[UGT_1]]) #[[ATTR5]] ; CHECK-NEXT: ret float [[ARG]] @@ -1371,8 +1371,8 @@ define float @ret_assumed_ugt_1(float %arg) { } define float @ret_assumed_uge_1(float %arg) { -; CHECK-LABEL: define float @ret_assumed_uge_1( -; CHECK-SAME: float returned [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(ninf zero sub nnorm) float @ret_assumed_uge_1( +; CHECK-SAME: float returned nofpclass(ninf zero sub nnorm) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[UGE_1:%.*]] = fcmp uge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[UGE_1]]) #[[ATTR5]] ; CHECK-NEXT: ret float [[ARG]] @@ -1383,8 +1383,8 @@ define float @ret_assumed_uge_1(float %arg) { } define float @ret_assumed_ult_1(float %arg) { -; CHECK-LABEL: define float @ret_assumed_ult_1( -; CHECK-SAME: float returned [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(pinf) float @ret_assumed_ult_1( +; CHECK-SAME: float returned nofpclass(pinf) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[ULT_1:%.*]] = fcmp ult float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[ULT_1]]) #[[ATTR5]] ; CHECK-NEXT: ret float [[ARG]] @@ -1395,8 +1395,8 @@ define float @ret_assumed_ult_1(float %arg) { } define float @ret_assumed_ule_1(float %arg) { -; CHECK-LABEL: define float @ret_assumed_ule_1( -; CHECK-SAME: float returned [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(pinf) float @ret_assumed_ule_1( +; CHECK-SAME: float returned nofpclass(pinf) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[ULE_1:%.*]] = fcmp ule float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[ULE_1]]) #[[ATTR5]] ; CHECK-NEXT: ret float [[ARG]] @@ -1407,8 +1407,8 @@ define float @ret_assumed_ule_1(float %arg) { } define float @ret_assumed_fabs_ogt_1(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @ret_assumed_fabs_ogt_1( -; CHECK-SAME: float returned nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(nan ninf zero sub nnorm) float @ret_assumed_fabs_ogt_1( +; CHECK-SAME: float returned nofpclass(nan ninf zero sub nnorm) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[ARG_FABS:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[OGT_1:%.*]] = fcmp ogt float [[ARG_FABS]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[OGT_1]]) #[[ATTR5]] @@ -1421,8 +1421,8 @@ define float @ret_assumed_fabs_ogt_1(float %arg) { } define float @ret_assumed_fabs_oge_1(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @ret_assumed_fabs_oge_1( -; CHECK-SAME: float returned nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(nan ninf zero sub nnorm) float @ret_assumed_fabs_oge_1( +; CHECK-SAME: float returned nofpclass(nan ninf zero sub nnorm) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[ARG_FABS:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[OGE_1:%.*]] = fcmp oge float [[ARG_FABS]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[OGE_1]]) #[[ATTR5]] @@ -1435,8 +1435,8 @@ define float @ret_assumed_fabs_oge_1(float %arg) { } define float @ret_assumed_fabs_olt_1(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @ret_assumed_fabs_olt_1( -; CHECK-SAME: float returned nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(nan inf nzero nsub nnorm) float @ret_assumed_fabs_olt_1( +; CHECK-SAME: float returned nofpclass(nan inf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[ARG_FABS:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[OLT_1:%.*]] = fcmp olt float [[ARG_FABS]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[OLT_1]]) #[[ATTR5]] @@ -1449,8 +1449,8 @@ define float @ret_assumed_fabs_olt_1(float %arg) { } define float @ret_assumed_fabs_ole_1(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @ret_assumed_fabs_ole_1( -; CHECK-SAME: float returned nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(nan inf nzero nsub nnorm) float @ret_assumed_fabs_ole_1( +; CHECK-SAME: float returned nofpclass(nan inf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[ARG_FABS:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[OLE_1:%.*]] = fcmp olt float [[ARG_FABS]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[OLE_1]]) #[[ATTR5]] @@ -1463,8 +1463,8 @@ define float @ret_assumed_fabs_ole_1(float %arg) { } define float @ret_assumed_fabs_ugt_1(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @ret_assumed_fabs_ugt_1( -; CHECK-SAME: float returned nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(ninf zero sub nnorm) float @ret_assumed_fabs_ugt_1( +; CHECK-SAME: float returned nofpclass(ninf zero sub nnorm) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[ARG_FABS:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[UGT_1:%.*]] = fcmp ugt float [[ARG_FABS]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[UGT_1]]) #[[ATTR5]] @@ -1477,8 +1477,8 @@ define float @ret_assumed_fabs_ugt_1(float %arg) { } define float @ret_assumed_fabs_uge_1(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @ret_assumed_fabs_uge_1( -; CHECK-SAME: float returned nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(ninf zero sub nnorm) float @ret_assumed_fabs_uge_1( +; CHECK-SAME: float returned nofpclass(ninf zero sub nnorm) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[ARG_FABS:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[UGE_1:%.*]] = fcmp ugt float [[ARG_FABS]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[UGE_1]]) #[[ATTR5]] @@ -1491,8 +1491,8 @@ define float @ret_assumed_fabs_uge_1(float %arg) { } define float @ret_assumed_fabs_ult_1(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @ret_assumed_fabs_ult_1( -; CHECK-SAME: float returned nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(inf nzero nsub nnorm) float @ret_assumed_fabs_ult_1( +; CHECK-SAME: float returned nofpclass(inf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[ARG_FABS:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[ULT_1:%.*]] = fcmp ult float [[ARG_FABS]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[ULT_1]]) #[[ATTR5]] @@ -1505,8 +1505,8 @@ define float @ret_assumed_fabs_ult_1(float %arg) { } define float @ret_assumed_fabs_ule_1(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @ret_assumed_fabs_ule_1( -; CHECK-SAME: float returned nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(inf nzero nsub nnorm) float @ret_assumed_fabs_ule_1( +; CHECK-SAME: float returned nofpclass(inf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[ARG_FABS:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[ULE_1:%.*]] = fcmp ule float [[ARG_FABS]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[ULE_1]]) #[[ATTR5]] @@ -1519,8 +1519,8 @@ define float @ret_assumed_fabs_ule_1(float %arg) { } define float @ret_assumed_ogt_neg1(float %arg) { -; CHECK-LABEL: define float @ret_assumed_ogt_neg1( -; CHECK-SAME: float returned [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(nan ninf) float @ret_assumed_ogt_neg1( +; CHECK-SAME: float returned nofpclass(nan ninf) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[OGT_NEG1:%.*]] = fcmp ogt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[OGT_NEG1]]) #[[ATTR5]] ; CHECK-NEXT: ret float [[ARG]] @@ -1531,8 +1531,8 @@ define float @ret_assumed_ogt_neg1(float %arg) { } define float @ret_assumed_oge_neg1(float %arg) { -; CHECK-LABEL: define float @ret_assumed_oge_neg1( -; CHECK-SAME: float returned [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(nan ninf) float @ret_assumed_oge_neg1( +; CHECK-SAME: float returned nofpclass(nan ninf) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[OGE_NEG1:%.*]] = fcmp ogt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[OGE_NEG1]]) #[[ATTR5]] ; CHECK-NEXT: ret float [[ARG]] @@ -1543,8 +1543,8 @@ define float @ret_assumed_oge_neg1(float %arg) { } define float @ret_assumed_olt_neg1(float %arg) { -; CHECK-LABEL: define float @ret_assumed_olt_neg1( -; CHECK-SAME: float returned [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(nan pinf zero sub pnorm) float @ret_assumed_olt_neg1( +; CHECK-SAME: float returned nofpclass(nan pinf zero sub pnorm) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[OLT_NEG1]]) #[[ATTR5]] ; CHECK-NEXT: ret float [[ARG]] @@ -1555,8 +1555,8 @@ define float @ret_assumed_olt_neg1(float %arg) { } define float @ret_assumed_ole_neg1(float %arg) { -; CHECK-LABEL: define float @ret_assumed_ole_neg1( -; CHECK-SAME: float returned [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(nan pinf zero sub pnorm) float @ret_assumed_ole_neg1( +; CHECK-SAME: float returned nofpclass(nan pinf zero sub pnorm) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[OLE_NEG1:%.*]] = fcmp ole float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[OLE_NEG1]]) #[[ATTR5]] ; CHECK-NEXT: ret float [[ARG]] @@ -1567,8 +1567,8 @@ define float @ret_assumed_ole_neg1(float %arg) { } define float @ret_assumed_ugt_neg1(float %arg) { -; CHECK-LABEL: define float @ret_assumed_ugt_neg1( -; CHECK-SAME: float returned [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(ninf) float @ret_assumed_ugt_neg1( +; CHECK-SAME: float returned nofpclass(ninf) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[UGT_NEG1:%.*]] = fcmp ugt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[UGT_NEG1]]) #[[ATTR5]] ; CHECK-NEXT: ret float [[ARG]] @@ -1579,8 +1579,8 @@ define float @ret_assumed_ugt_neg1(float %arg) { } define float @ret_assumed_uge_neg1(float %arg) { -; CHECK-LABEL: define float @ret_assumed_uge_neg1( -; CHECK-SAME: float returned [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(ninf) float @ret_assumed_uge_neg1( +; CHECK-SAME: float returned nofpclass(ninf) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[UGE_NEG1:%.*]] = fcmp uge float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[UGE_NEG1]]) #[[ATTR5]] ; CHECK-NEXT: ret float [[ARG]] @@ -1591,8 +1591,8 @@ define float @ret_assumed_uge_neg1(float %arg) { } define float @ret_assumed_ult_neg1(float %arg) { -; CHECK-LABEL: define float @ret_assumed_ult_neg1( -; CHECK-SAME: float returned [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(pinf zero sub pnorm) float @ret_assumed_ult_neg1( +; CHECK-SAME: float returned nofpclass(pinf zero sub pnorm) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[ULT_NEG1:%.*]] = fcmp ult float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[ULT_NEG1]]) #[[ATTR5]] ; CHECK-NEXT: ret float [[ARG]] @@ -1603,8 +1603,8 @@ define float @ret_assumed_ult_neg1(float %arg) { } define float @ret_assumed_ule_neg1(float %arg) { -; CHECK-LABEL: define float @ret_assumed_ule_neg1( -; CHECK-SAME: float returned [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(pinf zero sub pnorm) float @ret_assumed_ule_neg1( +; CHECK-SAME: float returned nofpclass(pinf zero sub pnorm) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[ULE_NEG1:%.*]] = fcmp ule float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[ULE_NEG1]]) #[[ATTR5]] ; CHECK-NEXT: ret float [[ARG]] @@ -1615,8 +1615,8 @@ define float @ret_assumed_ule_neg1(float %arg) { } define float @ret_assumed_oeq_1(float %arg) { -; CHECK-LABEL: define float @ret_assumed_oeq_1( -; CHECK-SAME: float returned [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(nan inf zero sub nnorm) float @ret_assumed_oeq_1( +; CHECK-SAME: float returned nofpclass(nan inf zero sub nnorm) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[OEQ_1:%.*]] = fcmp oeq float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[OEQ_1]]) #[[ATTR5]] ; CHECK-NEXT: ret float [[ARG]] @@ -1627,8 +1627,8 @@ define float @ret_assumed_oeq_1(float %arg) { } define float @ret_assumed_ueq_1(float %arg) { -; CHECK-LABEL: define float @ret_assumed_ueq_1( -; CHECK-SAME: float returned [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(inf zero sub nnorm) float @ret_assumed_ueq_1( +; CHECK-SAME: float returned nofpclass(inf zero sub nnorm) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[UEQ_1:%.*]] = fcmp ueq float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[UEQ_1]]) #[[ATTR5]] ; CHECK-NEXT: ret float [[ARG]] @@ -1639,8 +1639,8 @@ define float @ret_assumed_ueq_1(float %arg) { } define float @ret_assumed_one_1(float %arg) { -; CHECK-LABEL: define float @ret_assumed_one_1( -; CHECK-SAME: float returned [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(nan) float @ret_assumed_one_1( +; CHECK-SAME: float returned nofpclass(nan) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[ONE_1:%.*]] = fcmp one float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[ONE_1]]) #[[ATTR5]] ; CHECK-NEXT: ret float [[ARG]] @@ -1651,8 +1651,8 @@ define float @ret_assumed_one_1(float %arg) { } define float @ret_assumed_one_neg1(float %arg) { -; CHECK-LABEL: define float @ret_assumed_one_neg1( -; CHECK-SAME: float returned [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(nan) float @ret_assumed_one_neg1( +; CHECK-SAME: float returned nofpclass(nan) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[ONE_NEG1:%.*]] = fcmp one float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[ONE_NEG1]]) #[[ATTR5]] ; CHECK-NEXT: ret float [[ARG]] @@ -1687,8 +1687,8 @@ define float @ret_assumed_une_1(float %arg) { } define float @ret_assumed_fabs_oeq_1(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @ret_assumed_fabs_oeq_1( -; CHECK-SAME: float returned nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(nan inf zero sub nnorm) float @ret_assumed_fabs_oeq_1( +; CHECK-SAME: float returned nofpclass(nan inf zero sub nnorm) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[ARG_FABS:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[OEQ_1:%.*]] = fcmp oeq float [[ARG_FABS]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[OEQ_1]]) #[[ATTR5]] @@ -1701,8 +1701,8 @@ define float @ret_assumed_fabs_oeq_1(float %arg) { } define float @ret_assumed_fabs_ueq_1(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @ret_assumed_fabs_ueq_1( -; CHECK-SAME: float returned nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(inf zero sub nnorm) float @ret_assumed_fabs_ueq_1( +; CHECK-SAME: float returned nofpclass(inf zero sub nnorm) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[ARG_FABS:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[UEQ_1:%.*]] = fcmp ueq float [[ARG_FABS]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[UEQ_1]]) #[[ATTR5]] @@ -1715,8 +1715,8 @@ define float @ret_assumed_fabs_ueq_1(float %arg) { } define float @ret_assumed_fabs_one_1(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @ret_assumed_fabs_one_1( -; CHECK-SAME: float returned nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(nan ninf nzero nsub nnorm) float @ret_assumed_fabs_one_1( +; CHECK-SAME: float returned nofpclass(nan ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[ARG_FABS:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[ONE_1:%.*]] = fcmp one float [[ARG_FABS]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[ONE_1]]) #[[ATTR5]] @@ -1729,8 +1729,8 @@ define float @ret_assumed_fabs_one_1(float %arg) { } define float @ret_assumed_fabs_une_1(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @ret_assumed_fabs_une_1( -; CHECK-SAME: float returned nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(nan ninf nzero nsub nnorm) float @ret_assumed_fabs_une_1( +; CHECK-SAME: float returned nofpclass(nan ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[ARG_FABS:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[UNE_1:%.*]] = fcmp one float [[ARG_FABS]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[UNE_1]]) #[[ATTR5]] @@ -1743,8 +1743,8 @@ define float @ret_assumed_fabs_une_1(float %arg) { } define float @ret_assumed_fabs_oeq_neg1(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @ret_assumed_fabs_oeq_neg1( -; CHECK-SAME: float returned nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(all) float @ret_assumed_fabs_oeq_neg1( +; CHECK-SAME: float returned nofpclass(all) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: call void @llvm.assume(i1 noundef false) #[[ATTR5]] ; CHECK-NEXT: ret float [[ARG]] ; @@ -1755,8 +1755,8 @@ define float @ret_assumed_fabs_oeq_neg1(float %arg) { } define float @ret_assumed_fabs_ueq_neg1(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @ret_assumed_fabs_ueq_neg1( -; CHECK-SAME: float returned nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(inf zero sub norm) float @ret_assumed_fabs_ueq_neg1( +; CHECK-SAME: float returned nofpclass(inf zero sub norm) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[ARG_FABS:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[UEQ_NEG1:%.*]] = fcmp ueq float [[ARG_FABS]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[UEQ_NEG1]]) #[[ATTR5]] @@ -1769,8 +1769,8 @@ define float @ret_assumed_fabs_ueq_neg1(float %arg) { } define float @ret_assumed_fabs_one_neg1(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @ret_assumed_fabs_one_neg1( -; CHECK-SAME: float returned nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(nan ninf nzero nsub nnorm) float @ret_assumed_fabs_one_neg1( +; CHECK-SAME: float returned nofpclass(nan ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[ARG_FABS:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[ONE_NEG1:%.*]] = fcmp one float [[ARG_FABS]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[ONE_NEG1]]) #[[ATTR5]] @@ -2228,8 +2228,8 @@ define float @ret_assumed_uge_known_negative(float %arg, float %unknown) { ;--------------------------------------------------------------------- define float @assume_oeq_smallest_normal(float %arg) { -; CHECK-LABEL: define float @assume_oeq_smallest_normal( -; CHECK-SAME: float returned [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(nan inf zero sub nnorm) float @assume_oeq_smallest_normal( +; CHECK-SAME: float returned nofpclass(nan inf zero sub nnorm) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[IS_OEQ_SMALLEST_NORMAL:%.*]] = fcmp oeq float [[ARG]], 0x3810000000000000 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[IS_OEQ_SMALLEST_NORMAL]]) #[[ATTR5]] ; CHECK-NEXT: ret float [[ARG]] @@ -2240,8 +2240,8 @@ define float @assume_oeq_smallest_normal(float %arg) { } define float @assume_one_smallest_normal(float %arg) { -; CHECK-LABEL: define float @assume_one_smallest_normal( -; CHECK-SAME: float returned [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(nan) float @assume_one_smallest_normal( +; CHECK-SAME: float returned nofpclass(nan) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[IS_ONE_SMALLEST_NORMAL:%.*]] = fcmp one float [[ARG]], 0x3810000000000000 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[IS_ONE_SMALLEST_NORMAL]]) #[[ATTR5]] ; CHECK-NEXT: ret float [[ARG]] @@ -2252,8 +2252,8 @@ define float @assume_one_smallest_normal(float %arg) { } define float @assume_ueq_smallest_normal(float %arg) { -; CHECK-LABEL: define float @assume_ueq_smallest_normal( -; CHECK-SAME: float returned [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(inf zero sub nnorm) float @assume_ueq_smallest_normal( +; CHECK-SAME: float returned nofpclass(inf zero sub nnorm) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[IS_UEQ_SMALLEST_NORMAL:%.*]] = fcmp ueq float [[ARG]], 0x3810000000000000 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[IS_UEQ_SMALLEST_NORMAL]]) #[[ATTR5]] ; CHECK-NEXT: ret float [[ARG]] @@ -2300,8 +2300,8 @@ define float @assume_uno_smallest_normal(float %arg) { } define float @assume_fabs_oeq_smallest_normal(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @assume_fabs_oeq_smallest_normal( -; CHECK-SAME: float returned nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(nan inf zero sub nnorm) float @assume_fabs_oeq_smallest_normal( +; CHECK-SAME: float returned nofpclass(nan inf zero sub nnorm) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[IS_OEQ_SMALLEST_NORMAL:%.*]] = fcmp oeq float [[FABS_ARG]], 0x3810000000000000 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[IS_OEQ_SMALLEST_NORMAL]]) #[[ATTR5]] @@ -2314,8 +2314,8 @@ define float @assume_fabs_oeq_smallest_normal(float %arg) { } define float @assume_fabs_one_smallest_normal(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @assume_fabs_one_smallest_normal( -; CHECK-SAME: float returned nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(nan ninf nzero nsub nnorm) float @assume_fabs_one_smallest_normal( +; CHECK-SAME: float returned nofpclass(nan ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[IS_ONE_SMALLEST_NORMAL:%.*]] = fcmp one float [[FABS_ARG]], 0x3810000000000000 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[IS_ONE_SMALLEST_NORMAL]]) #[[ATTR5]] @@ -2328,8 +2328,8 @@ define float @assume_fabs_one_smallest_normal(float %arg) { } define float @assume_fabs_ueq_smallest_normal(float %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @assume_fabs_ueq_smallest_normal( -; CHECK-SAME: float returned nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(inf zero sub nnorm) float @assume_fabs_ueq_smallest_normal( +; CHECK-SAME: float returned nofpclass(inf zero sub nnorm) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR4]] ; CHECK-NEXT: [[IS_UEQ_SMALLEST_NORMAL:%.*]] = fcmp ueq float [[FABS_ARG]], 0x3810000000000000 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[IS_UEQ_SMALLEST_NORMAL]]) #[[ATTR5]] @@ -2384,8 +2384,8 @@ define float @assume_fabs_uno_smallest_normal(float %arg) { } define float @assume_oeq_smallest_normal_known_pos(float nofpclass(ninf nsub nnorm nzero) %arg) { -; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @assume_oeq_smallest_normal_known_pos( -; CHECK-SAME: float returned nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR3]] { +; CHECK-LABEL: define nofpclass(nan inf zero sub nnorm) float @assume_oeq_smallest_normal_known_pos( +; CHECK-SAME: float returned nofpclass(nan inf zero sub nnorm) [[ARG:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[IS_OEQ_SMALLEST_NORMAL:%.*]] = fcmp oeq float [[ARG]], 0x3810000000000000 ; CHECK-NEXT: call void @llvm.assume(i1 noundef [[IS_OEQ_SMALLEST_NORMAL]]) #[[ATTR5]] ; CHECK-NEXT: ret float [[ARG]] diff --git a/llvm/test/Transforms/InstSimplify/assume-fcmp-constant-implies-class.ll b/llvm/test/Transforms/InstSimplify/assume-fcmp-constant-implies-class.ll index 7970f3ce6bf0..8d5ac063108c 100644 --- a/llvm/test/Transforms/InstSimplify/assume-fcmp-constant-implies-class.ll +++ b/llvm/test/Transforms/InstSimplify/assume-fcmp-constant-implies-class.ll @@ -17,8 +17,7 @@ define i1 @assume_olt_neg1__oeq_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) @@ -31,8 +30,7 @@ define i1 @assume_olt_neg1__ogt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) @@ -45,8 +43,7 @@ define i1 @assume_olt_neg1__oge_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp oge float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) @@ -59,8 +56,7 @@ define i1 @assume_olt_neg1__olt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp olt float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) @@ -73,8 +69,7 @@ define i1 @assume_olt_neg1__ole_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ole float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) @@ -87,8 +82,7 @@ define i1 @assume_olt_neg1__one_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp one float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) @@ -101,8 +95,7 @@ define i1 @assume_olt_neg1__ord_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ord float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) @@ -115,8 +108,7 @@ define i1 @assume_olt_neg1__ueq_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ueq float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) @@ -129,8 +121,7 @@ define i1 @assume_olt_neg1__ugt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ugt float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) @@ -143,8 +134,7 @@ define i1 @assume_olt_neg1__uge_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp uge float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) @@ -157,8 +147,7 @@ define i1 @assume_olt_neg1__ult_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ult float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) @@ -171,8 +160,7 @@ define i1 @assume_olt_neg1__ule_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ule float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) @@ -185,8 +173,7 @@ define i1 @assume_olt_neg1__une_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp une float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) @@ -199,8 +186,7 @@ define i1 @assume_olt_neg1__uno_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp uno float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) @@ -217,8 +203,7 @@ define i1 @assume_ole_neg1__oeq_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_NEG1:%.*]] = fcmp ole float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %ole.neg1 = fcmp ole float %arg, -1.0 call void @llvm.assume(i1 %ole.neg1) @@ -231,8 +216,7 @@ define i1 @assume_ole_neg1__ogt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_NEG1:%.*]] = fcmp ole float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %ole.neg1 = fcmp ole float %arg, -1.0 call void @llvm.assume(i1 %ole.neg1) @@ -245,8 +229,7 @@ define i1 @assume_ole_neg1__oge_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_NEG1:%.*]] = fcmp ole float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp oge float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %ole.neg1 = fcmp ole float %arg, -1.0 call void @llvm.assume(i1 %ole.neg1) @@ -259,8 +242,7 @@ define i1 @assume_ole_neg1__olt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_NEG1:%.*]] = fcmp ole float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp olt float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %ole.neg1 = fcmp ole float %arg, -1.0 call void @llvm.assume(i1 %ole.neg1) @@ -273,8 +255,7 @@ define i1 @assume_ole_neg1__ole_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_NEG1:%.*]] = fcmp ole float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ole float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %ole.neg1 = fcmp ole float %arg, -1.0 call void @llvm.assume(i1 %ole.neg1) @@ -287,8 +268,7 @@ define i1 @assume_ole_neg1__one_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_NEG1:%.*]] = fcmp ole float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp one float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %ole.neg1 = fcmp ole float %arg, -1.0 call void @llvm.assume(i1 %ole.neg1) @@ -301,8 +281,7 @@ define i1 @assume_ole_neg1__ord_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_NEG1:%.*]] = fcmp ole float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ord float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %ole.neg1 = fcmp ole float %arg, -1.0 call void @llvm.assume(i1 %ole.neg1) @@ -315,8 +294,7 @@ define i1 @assume_ole_neg1__ueq_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_NEG1:%.*]] = fcmp ole float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ueq float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %ole.neg1 = fcmp ole float %arg, -1.0 call void @llvm.assume(i1 %ole.neg1) @@ -329,8 +307,7 @@ define i1 @assume_ole_neg1__ugt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_NEG1:%.*]] = fcmp ole float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ugt float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %ole.neg1 = fcmp ole float %arg, -1.0 call void @llvm.assume(i1 %ole.neg1) @@ -343,8 +320,7 @@ define i1 @assume_ole_neg1__uge_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_NEG1:%.*]] = fcmp ole float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp uge float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %ole.neg1 = fcmp ole float %arg, -1.0 call void @llvm.assume(i1 %ole.neg1) @@ -357,8 +333,7 @@ define i1 @assume_ole_neg1__ult_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_NEG1:%.*]] = fcmp ole float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ult float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %ole.neg1 = fcmp ole float %arg, -1.0 call void @llvm.assume(i1 %ole.neg1) @@ -371,8 +346,7 @@ define i1 @assume_ole_neg1__ule_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_NEG1:%.*]] = fcmp ole float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ule float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %ole.neg1 = fcmp ole float %arg, -1.0 call void @llvm.assume(i1 %ole.neg1) @@ -385,8 +359,7 @@ define i1 @assume_ole_neg1__une_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_NEG1:%.*]] = fcmp ole float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp une float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %ole.neg1 = fcmp ole float %arg, -1.0 call void @llvm.assume(i1 %ole.neg1) @@ -399,8 +372,7 @@ define i1 @assume_ole_neg1__uno_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_NEG1:%.*]] = fcmp ole float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp uno float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %ole.neg1 = fcmp ole float %arg, -1.0 call void @llvm.assume(i1 %ole.neg1) @@ -501,8 +473,7 @@ define i1 @assume_ogt_neg1__ord_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_NEG1:%.*]] = fcmp ogt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ord float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %ogt.neg1 = fcmp ogt float %arg, -1.0 call void @llvm.assume(i1 %ogt.neg1) @@ -599,8 +570,7 @@ define i1 @assume_ogt_neg1__uno_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_NEG1:%.*]] = fcmp ogt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp uno float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %ogt.neg1 = fcmp ogt float %arg, -1.0 call void @llvm.assume(i1 %ogt.neg1) @@ -701,8 +671,7 @@ define i1 @assume_oge_neg1__ord_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_NEG1:%.*]] = fcmp oge float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ord float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %oge.neg1 = fcmp oge float %arg, -1.0 call void @llvm.assume(i1 %oge.neg1) @@ -799,8 +768,7 @@ define i1 @assume_oge_neg1__uno_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_NEG1:%.*]] = fcmp oge float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp uno float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %oge.neg1 = fcmp oge float %arg, -1.0 call void @llvm.assume(i1 %oge.neg1) @@ -1217,8 +1185,7 @@ define i1 @assume_ule_neg1__oeq_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[ULE_NEG1:%.*]] = fcmp ule float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[ULE_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %ule.neg1 = fcmp ule float %arg, -1.0 call void @llvm.assume(i1 %ule.neg1) @@ -1231,8 +1198,7 @@ define i1 @assume_ule_neg1__ogt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[ULE_NEG1:%.*]] = fcmp ule float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[ULE_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %ule.neg1 = fcmp ule float %arg, -1.0 call void @llvm.assume(i1 %ule.neg1) @@ -1245,8 +1211,7 @@ define i1 @assume_ule_neg1__oge_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[ULE_NEG1:%.*]] = fcmp ule float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[ULE_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp oge float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %ule.neg1 = fcmp ule float %arg, -1.0 call void @llvm.assume(i1 %ule.neg1) @@ -1357,8 +1322,7 @@ define i1 @assume_ule_neg1__ult_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[ULE_NEG1:%.*]] = fcmp ule float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[ULE_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ult float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %ule.neg1 = fcmp ule float %arg, -1.0 call void @llvm.assume(i1 %ule.neg1) @@ -1371,8 +1335,7 @@ define i1 @assume_ule_neg1__ule_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[ULE_NEG1:%.*]] = fcmp ule float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[ULE_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ule float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %ule.neg1 = fcmp ule float %arg, -1.0 call void @llvm.assume(i1 %ule.neg1) @@ -1385,8 +1348,7 @@ define i1 @assume_ule_neg1__une_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[ULE_NEG1:%.*]] = fcmp ule float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[ULE_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp une float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %ule.neg1 = fcmp ule float %arg, -1.0 call void @llvm.assume(i1 %ule.neg1) @@ -1417,8 +1379,7 @@ define i1 @assume_ult_neg1__oeq_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[ULT_NEG1:%.*]] = fcmp ult float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[ULT_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %ult.neg1 = fcmp ult float %arg, -1.0 call void @llvm.assume(i1 %ult.neg1) @@ -1431,8 +1392,7 @@ define i1 @assume_ult_neg1__ogt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[ULT_NEG1:%.*]] = fcmp ult float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[ULT_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %ult.neg1 = fcmp ult float %arg, -1.0 call void @llvm.assume(i1 %ult.neg1) @@ -1445,8 +1405,7 @@ define i1 @assume_ult_neg1__oge_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[ULT_NEG1:%.*]] = fcmp ult float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[ULT_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp oge float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %ult.neg1 = fcmp ult float %arg, -1.0 call void @llvm.assume(i1 %ult.neg1) @@ -1557,8 +1516,7 @@ define i1 @assume_ult_neg1__ult_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[ULT_NEG1:%.*]] = fcmp ult float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[ULT_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ult float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %ult.neg1 = fcmp ult float %arg, -1.0 call void @llvm.assume(i1 %ult.neg1) @@ -1571,8 +1529,7 @@ define i1 @assume_ult_neg1__ule_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[ULT_NEG1:%.*]] = fcmp ult float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[ULT_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ule float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %ult.neg1 = fcmp ult float %arg, -1.0 call void @llvm.assume(i1 %ult.neg1) @@ -1585,8 +1542,7 @@ define i1 @assume_ult_neg1__une_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[ULT_NEG1:%.*]] = fcmp ult float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[ULT_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp une float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %ult.neg1 = fcmp ult float %arg, -1.0 call void @llvm.assume(i1 %ult.neg1) @@ -1824,8 +1780,7 @@ define i1 @assume_olt_pos1__ord_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_POS1:%.*]] = fcmp olt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ord float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %olt.pos1 = fcmp olt float %arg, 1.0 call void @llvm.assume(i1 %olt.pos1) @@ -1922,8 +1877,7 @@ define i1 @assume_olt_pos1__uno_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_POS1:%.*]] = fcmp olt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp uno float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %olt.pos1 = fcmp olt float %arg, 1.0 call void @llvm.assume(i1 %olt.pos1) @@ -2024,8 +1978,7 @@ define i1 @assume_ole_pos1__ord_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_POS1:%.*]] = fcmp ole float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ord float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %ole.pos1 = fcmp ole float %arg, 1.0 call void @llvm.assume(i1 %ole.pos1) @@ -2122,8 +2075,7 @@ define i1 @assume_ole_pos1__uno_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_POS1:%.*]] = fcmp ole float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp uno float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %ole.pos1 = fcmp ole float %arg, 1.0 call void @llvm.assume(i1 %ole.pos1) @@ -2140,8 +2092,7 @@ define i1 @assume_ogt_pos1__oeq_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_POS1:%.*]] = fcmp ogt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %ogt.pos1 = fcmp ogt float %arg, 1.0 call void @llvm.assume(i1 %ogt.pos1) @@ -2154,8 +2105,7 @@ define i1 @assume_ogt_pos1__ogt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_POS1:%.*]] = fcmp ogt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %ogt.pos1 = fcmp ogt float %arg, 1.0 call void @llvm.assume(i1 %ogt.pos1) @@ -2168,8 +2118,7 @@ define i1 @assume_ogt_pos1__oge_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_POS1:%.*]] = fcmp ogt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp oge float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %ogt.pos1 = fcmp ogt float %arg, 1.0 call void @llvm.assume(i1 %ogt.pos1) @@ -2182,8 +2131,7 @@ define i1 @assume_ogt_pos1__olt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_POS1:%.*]] = fcmp ogt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp olt float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %ogt.pos1 = fcmp ogt float %arg, 1.0 call void @llvm.assume(i1 %ogt.pos1) @@ -2196,8 +2144,7 @@ define i1 @assume_ogt_pos1__ole_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_POS1:%.*]] = fcmp ogt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ole float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %ogt.pos1 = fcmp ogt float %arg, 1.0 call void @llvm.assume(i1 %ogt.pos1) @@ -2210,8 +2157,7 @@ define i1 @assume_ogt_pos1__one_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_POS1:%.*]] = fcmp ogt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp one float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %ogt.pos1 = fcmp ogt float %arg, 1.0 call void @llvm.assume(i1 %ogt.pos1) @@ -2224,8 +2170,7 @@ define i1 @assume_ogt_pos1__ord_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_POS1:%.*]] = fcmp ogt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ord float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %ogt.pos1 = fcmp ogt float %arg, 1.0 call void @llvm.assume(i1 %ogt.pos1) @@ -2238,8 +2183,7 @@ define i1 @assume_ogt_pos1__ueq_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_POS1:%.*]] = fcmp ogt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ueq float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %ogt.pos1 = fcmp ogt float %arg, 1.0 call void @llvm.assume(i1 %ogt.pos1) @@ -2252,8 +2196,7 @@ define i1 @assume_ogt_pos1__ugt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_POS1:%.*]] = fcmp ogt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ugt float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %ogt.pos1 = fcmp ogt float %arg, 1.0 call void @llvm.assume(i1 %ogt.pos1) @@ -2266,8 +2209,7 @@ define i1 @assume_ogt_pos1__uge_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_POS1:%.*]] = fcmp ogt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp uge float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %ogt.pos1 = fcmp ogt float %arg, 1.0 call void @llvm.assume(i1 %ogt.pos1) @@ -2280,8 +2222,7 @@ define i1 @assume_ogt_pos1__ult_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_POS1:%.*]] = fcmp ogt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ult float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %ogt.pos1 = fcmp ogt float %arg, 1.0 call void @llvm.assume(i1 %ogt.pos1) @@ -2294,8 +2235,7 @@ define i1 @assume_ogt_pos1__ule_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_POS1:%.*]] = fcmp ogt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ule float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %ogt.pos1 = fcmp ogt float %arg, 1.0 call void @llvm.assume(i1 %ogt.pos1) @@ -2308,8 +2248,7 @@ define i1 @assume_ogt_pos1__une_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_POS1:%.*]] = fcmp ogt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp une float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %ogt.pos1 = fcmp ogt float %arg, 1.0 call void @llvm.assume(i1 %ogt.pos1) @@ -2322,8 +2261,7 @@ define i1 @assume_ogt_pos1__uno_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_POS1:%.*]] = fcmp ogt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp uno float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %ogt.pos1 = fcmp ogt float %arg, 1.0 call void @llvm.assume(i1 %ogt.pos1) @@ -2340,8 +2278,7 @@ define i1 @assume_oge_pos1__oeq_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_POS1:%.*]] = fcmp oge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %oge.pos1 = fcmp oge float %arg, 1.0 call void @llvm.assume(i1 %oge.pos1) @@ -2354,8 +2291,7 @@ define i1 @assume_oge_pos1__ogt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_POS1:%.*]] = fcmp oge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %oge.pos1 = fcmp oge float %arg, 1.0 call void @llvm.assume(i1 %oge.pos1) @@ -2368,8 +2304,7 @@ define i1 @assume_oge_pos1__oge_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_POS1:%.*]] = fcmp oge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp oge float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %oge.pos1 = fcmp oge float %arg, 1.0 call void @llvm.assume(i1 %oge.pos1) @@ -2382,8 +2317,7 @@ define i1 @assume_oge_pos1__olt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_POS1:%.*]] = fcmp oge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp olt float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %oge.pos1 = fcmp oge float %arg, 1.0 call void @llvm.assume(i1 %oge.pos1) @@ -2396,8 +2330,7 @@ define i1 @assume_oge_pos1__ole_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_POS1:%.*]] = fcmp oge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ole float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %oge.pos1 = fcmp oge float %arg, 1.0 call void @llvm.assume(i1 %oge.pos1) @@ -2410,8 +2343,7 @@ define i1 @assume_oge_pos1__one_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_POS1:%.*]] = fcmp oge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp one float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %oge.pos1 = fcmp oge float %arg, 1.0 call void @llvm.assume(i1 %oge.pos1) @@ -2424,8 +2356,7 @@ define i1 @assume_oge_pos1__ord_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_POS1:%.*]] = fcmp oge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ord float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %oge.pos1 = fcmp oge float %arg, 1.0 call void @llvm.assume(i1 %oge.pos1) @@ -2438,8 +2369,7 @@ define i1 @assume_oge_pos1__ueq_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_POS1:%.*]] = fcmp oge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ueq float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %oge.pos1 = fcmp oge float %arg, 1.0 call void @llvm.assume(i1 %oge.pos1) @@ -2452,8 +2382,7 @@ define i1 @assume_oge_pos1__ugt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_POS1:%.*]] = fcmp oge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ugt float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %oge.pos1 = fcmp oge float %arg, 1.0 call void @llvm.assume(i1 %oge.pos1) @@ -2466,8 +2395,7 @@ define i1 @assume_oge_pos1__uge_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_POS1:%.*]] = fcmp oge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp uge float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %oge.pos1 = fcmp oge float %arg, 1.0 call void @llvm.assume(i1 %oge.pos1) @@ -2480,8 +2408,7 @@ define i1 @assume_oge_pos1__ult_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_POS1:%.*]] = fcmp oge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ult float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %oge.pos1 = fcmp oge float %arg, 1.0 call void @llvm.assume(i1 %oge.pos1) @@ -2494,8 +2421,7 @@ define i1 @assume_oge_pos1__ule_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_POS1:%.*]] = fcmp oge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ule float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %oge.pos1 = fcmp oge float %arg, 1.0 call void @llvm.assume(i1 %oge.pos1) @@ -2508,8 +2434,7 @@ define i1 @assume_oge_pos1__une_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_POS1:%.*]] = fcmp oge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp une float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %oge.pos1 = fcmp oge float %arg, 1.0 call void @llvm.assume(i1 %oge.pos1) @@ -2522,8 +2447,7 @@ define i1 @assume_oge_pos1__uno_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_POS1:%.*]] = fcmp oge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp uno float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %oge.pos1 = fcmp oge float %arg, 1.0 call void @llvm.assume(i1 %oge.pos1) @@ -2540,8 +2464,7 @@ define i1 @assume_ugt_pos1__oeq_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[UGT_POS1:%.*]] = fcmp ugt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[UGT_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %ugt.pos1 = fcmp ugt float %arg, 1.0 call void @llvm.assume(i1 %ugt.pos1) @@ -2582,8 +2505,7 @@ define i1 @assume_ugt_pos1__olt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[UGT_POS1:%.*]] = fcmp ugt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[UGT_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp olt float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %ugt.pos1 = fcmp ugt float %arg, 1.0 call void @llvm.assume(i1 %ugt.pos1) @@ -2596,8 +2518,7 @@ define i1 @assume_ugt_pos1__ole_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[UGT_POS1:%.*]] = fcmp ugt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[UGT_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ole float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %ugt.pos1 = fcmp ugt float %arg, 1.0 call void @llvm.assume(i1 %ugt.pos1) @@ -2652,8 +2573,7 @@ define i1 @assume_ugt_pos1__ugt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[UGT_POS1:%.*]] = fcmp ugt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[UGT_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ugt float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %ugt.pos1 = fcmp ugt float %arg, 1.0 call void @llvm.assume(i1 %ugt.pos1) @@ -2666,8 +2586,7 @@ define i1 @assume_ugt_pos1__uge_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[UGT_POS1:%.*]] = fcmp ugt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[UGT_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp uge float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %ugt.pos1 = fcmp ugt float %arg, 1.0 call void @llvm.assume(i1 %ugt.pos1) @@ -2708,8 +2627,7 @@ define i1 @assume_ugt_pos1__une_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[UGT_POS1:%.*]] = fcmp ugt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[UGT_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp une float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %ugt.pos1 = fcmp ugt float %arg, 1.0 call void @llvm.assume(i1 %ugt.pos1) @@ -2740,8 +2658,7 @@ define i1 @assume_uge_pos1__oeq_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[UGE_POS1:%.*]] = fcmp uge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[UGE_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %uge.pos1 = fcmp uge float %arg, 1.0 call void @llvm.assume(i1 %uge.pos1) @@ -2782,8 +2699,7 @@ define i1 @assume_uge_pos1__olt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[UGE_POS1:%.*]] = fcmp uge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[UGE_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp olt float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %uge.pos1 = fcmp uge float %arg, 1.0 call void @llvm.assume(i1 %uge.pos1) @@ -2796,8 +2712,7 @@ define i1 @assume_uge_pos1__ole_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[UGE_POS1:%.*]] = fcmp uge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[UGE_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ole float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %uge.pos1 = fcmp uge float %arg, 1.0 call void @llvm.assume(i1 %uge.pos1) @@ -2852,8 +2767,7 @@ define i1 @assume_uge_pos1__ugt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[UGE_POS1:%.*]] = fcmp uge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[UGE_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp ugt float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %uge.pos1 = fcmp uge float %arg, 1.0 call void @llvm.assume(i1 %uge.pos1) @@ -2866,8 +2780,7 @@ define i1 @assume_uge_pos1__uge_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[UGE_POS1:%.*]] = fcmp uge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[UGE_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp uge float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %uge.pos1 = fcmp uge float %arg, 1.0 call void @llvm.assume(i1 %uge.pos1) @@ -2908,8 +2821,7 @@ define i1 @assume_uge_pos1__une_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[UGE_POS1:%.*]] = fcmp uge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[UGE_POS1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp une float [[ARG]], 0.000000e+00 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %uge.pos1 = fcmp uge float %arg, 1.0 call void @llvm.assume(i1 %uge.pos1) @@ -2940,8 +2852,7 @@ define i1 @assume_olt_neg1__oeq_inf(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ARG]], 0x7FF0000000000000 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 false ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) @@ -2954,8 +2865,7 @@ define i1 @assume_olt_neg1__one_inf(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: [[CMP:%.*]] = fcmp one float [[ARG]], 0x7FF0000000000000 -; CHECK-NEXT: ret i1 [[CMP]] +; CHECK-NEXT: ret i1 true ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) -- GitLab From 5a4ca51a91ff28b1d6bdde5403144c29b86e4b54 Mon Sep 17 00:00:00 2001 From: jeanPerier Date: Fri, 1 Dec 2023 10:03:02 +0100 Subject: [PATCH 116/699] [mlir] notify insertion of parent op first when cloning (#73806) When cloning an operation with a region, the builder was currently notifying about the insertion of the cloned operations inside the region before the cloned operation itself. When using cloning inside rewrite pass, this could cause issues if a pattern is expected to be applied on a cloned parent operation before trying to apply patterns on the cloned operations it contains (the patterns are attempted in order of notifications for the cloned operations). --- mlir/lib/IR/Builders.cpp | 7 ++++--- mlir/test/IR/test-clone.mlir | 23 +++++++++++++++++++---- mlir/test/lib/IR/TestClone.cpp | 8 ++++++++ 3 files changed, 31 insertions(+), 7 deletions(-) diff --git a/mlir/lib/IR/Builders.cpp b/mlir/lib/IR/Builders.cpp index ab20f4863e11..2cabfcd24d35 100644 --- a/mlir/lib/IR/Builders.cpp +++ b/mlir/lib/IR/Builders.cpp @@ -527,7 +527,8 @@ LogicalResult OpBuilder::tryFold(Operation *op, Operation *OpBuilder::clone(Operation &op, IRMapping &mapper) { Operation *newOp = op.clone(mapper); - // The `insert` call below handles the notification for inserting `newOp` + newOp = insert(newOp); + // The `insert` call above handles the notification for inserting `newOp` // itself. But if `newOp` has any regions, we need to notify the listener // about any ops that got inserted inside those regions as part of cloning. if (listener) { @@ -535,9 +536,9 @@ Operation *OpBuilder::clone(Operation &op, IRMapping &mapper) { listener->notifyOperationInserted(walkedOp); }; for (Region ®ion : newOp->getRegions()) - region.walk(walkFn); + region.walk(walkFn); } - return insert(newOp); + return newOp; } Operation *OpBuilder::clone(Operation &op) { diff --git a/mlir/test/IR/test-clone.mlir b/mlir/test/IR/test-clone.mlir index 575098b642e8..0c07593aef32 100644 --- a/mlir/test/IR/test-clone.mlir +++ b/mlir/test/IR/test-clone.mlir @@ -1,20 +1,35 @@ -// RUN: mlir-opt -allow-unregistered-dialect %s -pass-pipeline="builtin.module(func.func(test-clone))" -split-input-file +// RUN: mlir-opt -allow-unregistered-dialect %s -pass-pipeline="builtin.module(func.func(test-clone))" | FileCheck %s module { func.func @fixpoint(%arg1 : i32) -> i32 { %r = "test.use"(%arg1) ({ - "test.yield"(%arg1) : (i32) -> () + %r2 = "test.use2"(%arg1) ({ + "test.yield2"(%arg1) : (i32) -> () + }) : (i32) -> i32 + "test.yield"(%r2) : (i32) -> () }) : (i32) -> i32 return %r : i32 } } +// CHECK: notifyOperationInserted: test.use +// CHECK-NEXT: notifyOperationInserted: test.use2 +// CHECK-NEXT: notifyOperationInserted: test.yield2 +// CHECK-NEXT: notifyOperationInserted: test.yield +// CHECK-NEXT: notifyOperationInserted: func.return + // CHECK: func @fixpoint(%[[arg0:.+]]: i32) -> i32 { // CHECK-NEXT: %[[i0:.+]] = "test.use"(%[[arg0]]) ({ -// CHECK-NEXT: "test.yield"(%arg0) : (i32) -> () +// CHECK-NEXT: %[[r2:.+]] = "test.use2"(%[[arg0]]) ({ +// CHECK-NEXT: "test.yield2"(%[[arg0]]) : (i32) -> () +// CHECK-NEXT: }) : (i32) -> i32 +// CHECK-NEXT: "test.yield"(%[[r2]]) : (i32) -> () // CHECK-NEXT: }) : (i32) -> i32 // CHECK-NEXT: %[[i1:.+]] = "test.use"(%[[i0]]) ({ -// CHECK-NEXT: "test.yield"(%[[i0]]) : (i32) -> () +// CHECK-NEXT: %[[r2:.+]] = "test.use2"(%[[i0]]) ({ +// CHECK-NEXT: "test.yield2"(%[[i0]]) : (i32) -> () +// CHECK-NEXT: }) : (i32) -> i32 +// CHECK-NEXT: "test.yield"(%[[r2]]) : (i32) -> () // CHECK-NEXT: }) : (i32) -> i32 // CHECK-NEXT: return %[[i1]] : i32 // CHECK-NEXT: } diff --git a/mlir/test/lib/IR/TestClone.cpp b/mlir/test/lib/IR/TestClone.cpp index 70238608a67c..13a0cfeb402a 100644 --- a/mlir/test/lib/IR/TestClone.cpp +++ b/mlir/test/lib/IR/TestClone.cpp @@ -14,6 +14,12 @@ using namespace mlir; namespace { +struct DumpNotifications : public OpBuilder::Listener { + void notifyOperationInserted(Operation *op) override { + llvm::outs() << "notifyOperationInserted: " << op->getName() << "\n"; + } +}; + /// This is a test pass which clones the body of a function. Specifically /// this pass replaces f(x) to instead return f(f(x)) in which the cloned body /// takes the result of the first operation return as an input. @@ -50,6 +56,8 @@ struct ClonePass } OpBuilder builder(op->getContext()); + DumpNotifications dumpNotifications; + builder.setListener(&dumpNotifications); builder.setInsertionPointToEnd(®ionEntry); SmallVector toClone; for (Operation &inst : regionEntry) -- GitLab From a224ddc9b4458b1b9cf0a758c974a554f0f17dc4 Mon Sep 17 00:00:00 2001 From: Guray Ozen Date: Fri, 1 Dec 2023 10:21:50 +0100 Subject: [PATCH 117/699] [mlir][nvvm] Introduce `cp.async.bulk.commit.group` This PR introduced `cp.async.bulk.commit.group` op. --- mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td | 9 +++++++++ mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir | 8 ++++++++ 2 files changed, 17 insertions(+) diff --git a/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td b/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td index 54826f419699..ecad1a16eb6c 100644 --- a/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td +++ b/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td @@ -1420,6 +1420,15 @@ def NVVM_MmaOp : NVVM_Op<"mma.sync", [AttrSizedOperandSegments]> { // NVVM TMA Ops //===----------------------------------------------------------------------===// +def NVVM_CpAsyncBulkCommitGroupOp : NVVM_PTXBuilder_Op<"cp.async.bulk.commit.group">, + Arguments<(ins )> { + let assemblyFormat = "attr-dict"; + let extraClassDefinition = [{ + std::string $cppClass::getPtx() { return std::string("cp.async.bulk.commit_group;"); } + }]; +} + + def NVVM_CpAsyncBulkTensorGlobalToSharedClusterOp : NVVM_Op<"cp.async.bulk.tensor.shared.cluster.global", [DeclareOpInterfaceMethods, diff --git a/mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir b/mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir index 7da4e98c40e5..5482cc194192 100644 --- a/mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir +++ b/mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir @@ -621,3 +621,11 @@ func.func @set_max_register() { nvvm.setmaxregister decrease 40 func.return } + +// ----- + +func.func @cp_bulk_commit() { + //CHECK: llvm.inline_asm has_side_effects asm_dialect = att "cp.async.bulk.commit_group;" + nvvm.cp.async.bulk.commit.group + func.return +} -- GitLab From 4d1dc7770a6411b87cc488dd982c034f1b4ff7a7 Mon Sep 17 00:00:00 2001 From: Ramkumar Ramachandra Date: Fri, 1 Dec 2023 09:22:13 +0000 Subject: [PATCH 118/699] AMDGPU/load-global-i32: regenerate test using UTC (NFC) (#73962) Fix the RUN lines so that UTC runs cleanly, and regenerate the test load-global-i32.ll using utils/update_llc_test_checks.py. --- llvm/test/CodeGen/AMDGPU/load-global-i32.ll | 4935 +++++++++++++++++-- 1 file changed, 4462 insertions(+), 473 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/load-global-i32.ll b/llvm/test/CodeGen/AMDGPU/load-global-i32.ll index c4d9b4b2bb5e..55f0773f7e05 100644 --- a/llvm/test/CodeGen/AMDGPU/load-global-i32.ll +++ b/llvm/test/CodeGen/AMDGPU/load-global-i32.ll @@ -1,113 +1,825 @@ -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=SI-NOHSA -check-prefix=FUNC %s -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=GCNX3-HSA -check-prefix=FUNC %s -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=GCNX3-NOHSA -check-prefix=FUNC %s -; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=EG -check-prefix=FUNC %s -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NOHSA %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCNX3-HSA %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCNX3-NOHSA %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-HSA -check-prefix=GCN-GFX900-HSA %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-HSA -check-prefix=GCN-GFX908-HSA %s -; FUNC-LABEL: {{^}}global_load_i32: -; GCN-NOHSA: buffer_load_dword v{{[0-9]+}} -; GCN-HSA: {{flat|global}}_load_dword - -; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 define amdgpu_kernel void @global_load_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-NOHSA-LABEL: global_load_i32: +; SI-NOHSA: ; %bb.0: ; %entry +; SI-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; SI-NOHSA-NEXT: s_mov_b32 s6, -1 +; SI-NOHSA-NEXT: s_mov_b32 s10, s6 +; SI-NOHSA-NEXT: s_mov_b32 s11, s7 +; SI-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; SI-NOHSA-NEXT: s_mov_b32 s8, s2 +; SI-NOHSA-NEXT: s_mov_b32 s9, s3 +; SI-NOHSA-NEXT: buffer_load_dword v0, off, s[8:11], 0 +; SI-NOHSA-NEXT: s_mov_b32 s4, s0 +; SI-NOHSA-NEXT: s_mov_b32 s5, s1 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(0) +; SI-NOHSA-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; SI-NOHSA-NEXT: s_endpgm +; +; GCNX3-HSA-LABEL: global_load_i32: +; GCNX3-HSA: ; %bb.0: ; %entry +; GCNX3-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCNX3-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3 +; GCNX3-HSA-NEXT: flat_load_dword v2, v[0:1] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s1 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(0) +; GCNX3-HSA-NEXT: flat_store_dword v[0:1], v2 +; GCNX3-HSA-NEXT: s_endpgm +; +; GCNX3-NOHSA-LABEL: global_load_i32: +; GCNX3-NOHSA: ; %bb.0: ; %entry +; GCNX3-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GCNX3-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; GCNX3-NOHSA-NEXT: s_mov_b32 s6, -1 +; GCNX3-NOHSA-NEXT: s_mov_b32 s10, s6 +; GCNX3-NOHSA-NEXT: s_mov_b32 s11, s7 +; GCNX3-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-NOHSA-NEXT: s_mov_b32 s8, s2 +; GCNX3-NOHSA-NEXT: s_mov_b32 s9, s3 +; GCNX3-NOHSA-NEXT: buffer_load_dword v0, off, s[8:11], 0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s4, s0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s5, s1 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(0) +; GCNX3-NOHSA-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCNX3-NOHSA-NEXT: s_endpgm +; +; EG-LABEL: global_load_i32: +; EG: ; %bb.0: ; %entry +; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 0 @6 +; EG-NEXT: ALU 1, @9, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 6: +; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1 +; EG-NEXT: ALU clause starting at 8: +; EG-NEXT: MOV * T0.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 9: +; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-HSA-LABEL: global_load_i32: +; GCN-HSA: ; %bb.0: ; %entry +; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCN-HSA-NEXT: v_mov_b32_e32 v0, 0 +; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCN-HSA-NEXT: global_load_dword v1, v0, s[2:3] +; GCN-HSA-NEXT: s_waitcnt vmcnt(0) +; GCN-HSA-NEXT: global_store_dword v0, v1, s[0:1] +; GCN-HSA-NEXT: s_endpgm entry: %ld = load i32, ptr addrspace(1) %in store i32 %ld, ptr addrspace(1) %out ret void } -; FUNC-LABEL: {{^}}global_load_v2i32: -; GCN-NOHSA: buffer_load_dwordx2 -; GCN-HSA: {{flat|global}}_load_dwordx2 - -; EG: VTX_READ_64 define amdgpu_kernel void @global_load_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-NOHSA-LABEL: global_load_v2i32: +; SI-NOHSA: ; %bb.0: ; %entry +; SI-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; SI-NOHSA-NEXT: s_mov_b32 s6, -1 +; SI-NOHSA-NEXT: s_mov_b32 s10, s6 +; SI-NOHSA-NEXT: s_mov_b32 s11, s7 +; SI-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; SI-NOHSA-NEXT: s_mov_b32 s8, s2 +; SI-NOHSA-NEXT: s_mov_b32 s9, s3 +; SI-NOHSA-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0 +; SI-NOHSA-NEXT: s_mov_b32 s4, s0 +; SI-NOHSA-NEXT: s_mov_b32 s5, s1 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(0) +; SI-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; SI-NOHSA-NEXT: s_endpgm +; +; GCNX3-HSA-LABEL: global_load_v2i32: +; GCNX3-HSA: ; %bb.0: ; %entry +; GCNX3-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCNX3-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3 +; GCNX3-HSA-NEXT: flat_load_dwordx2 v[0:1], v[0:1] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, s0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v3, s1 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(0) +; GCNX3-HSA-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GCNX3-HSA-NEXT: s_endpgm +; +; GCNX3-NOHSA-LABEL: global_load_v2i32: +; GCNX3-NOHSA: ; %bb.0: ; %entry +; GCNX3-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GCNX3-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; GCNX3-NOHSA-NEXT: s_mov_b32 s6, -1 +; GCNX3-NOHSA-NEXT: s_mov_b32 s10, s6 +; GCNX3-NOHSA-NEXT: s_mov_b32 s11, s7 +; GCNX3-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-NOHSA-NEXT: s_mov_b32 s8, s2 +; GCNX3-NOHSA-NEXT: s_mov_b32 s9, s3 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s4, s0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s5, s1 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(0) +; GCNX3-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCNX3-NOHSA-NEXT: s_endpgm +; +; EG-LABEL: global_load_v2i32: +; EG: ; %bb.0: ; %entry +; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 0 @6 +; EG-NEXT: ALU 1, @9, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 6: +; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1 +; EG-NEXT: ALU clause starting at 8: +; EG-NEXT: MOV * T0.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 9: +; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-HSA-LABEL: global_load_v2i32: +; GCN-HSA: ; %bb.0: ; %entry +; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, 0 +; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCN-HSA-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3] +; GCN-HSA-NEXT: s_waitcnt vmcnt(0) +; GCN-HSA-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GCN-HSA-NEXT: s_endpgm entry: %ld = load <2 x i32>, ptr addrspace(1) %in store <2 x i32> %ld, ptr addrspace(1) %out ret void } -; FUNC-LABEL: {{^}}global_load_v3i32: -; SI-NOHSA: buffer_load_dwordx4 -; GCNX3-NOHSA: buffer_load_dwordx3 -; GCNX3-HSA: {{flat|global}}_load_dwordx3 - -; EG: VTX_READ_128 define amdgpu_kernel void @global_load_v3i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-NOHSA-LABEL: global_load_v3i32: +; SI-NOHSA: ; %bb.0: ; %entry +; SI-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; SI-NOHSA-NEXT: s_mov_b32 s6, -1 +; SI-NOHSA-NEXT: s_mov_b32 s10, s6 +; SI-NOHSA-NEXT: s_mov_b32 s11, s7 +; SI-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; SI-NOHSA-NEXT: s_mov_b32 s8, s2 +; SI-NOHSA-NEXT: s_mov_b32 s9, s3 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 +; SI-NOHSA-NEXT: s_mov_b32 s4, s0 +; SI-NOHSA-NEXT: s_mov_b32 s5, s1 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(0) +; SI-NOHSA-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:8 +; SI-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; SI-NOHSA-NEXT: s_endpgm +; +; GCNX3-HSA-LABEL: global_load_v3i32: +; GCNX3-HSA: ; %bb.0: ; %entry +; GCNX3-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCNX3-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3 +; GCNX3-HSA-NEXT: flat_load_dwordx3 v[0:2], v[0:1] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v3, s0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s1 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(0) +; GCNX3-HSA-NEXT: flat_store_dwordx3 v[3:4], v[0:2] +; GCNX3-HSA-NEXT: s_endpgm +; +; GCNX3-NOHSA-LABEL: global_load_v3i32: +; GCNX3-NOHSA: ; %bb.0: ; %entry +; GCNX3-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GCNX3-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; GCNX3-NOHSA-NEXT: s_mov_b32 s6, -1 +; GCNX3-NOHSA-NEXT: s_mov_b32 s10, s6 +; GCNX3-NOHSA-NEXT: s_mov_b32 s11, s7 +; GCNX3-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-NOHSA-NEXT: s_mov_b32 s8, s2 +; GCNX3-NOHSA-NEXT: s_mov_b32 s9, s3 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx3 v[0:2], off, s[8:11], 0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s4, s0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s5, s1 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(0) +; GCNX3-NOHSA-NEXT: buffer_store_dwordx3 v[0:2], off, s[4:7], 0 +; GCNX3-NOHSA-NEXT: s_endpgm +; +; EG-LABEL: global_load_v3i32: +; EG: ; %bb.0: ; %entry +; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 0 @6 +; EG-NEXT: ALU 6, @9, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.X, T3.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: Fetch clause starting at 6: +; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1 +; EG-NEXT: ALU clause starting at 8: +; EG-NEXT: MOV * T0.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 9: +; EG-NEXT: LSHR T1.X, KC0[2].Y, literal.x, +; EG-NEXT: MOV * T2.X, T0.Z, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: LSHR * T3.X, PV.W, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-HSA-LABEL: global_load_v3i32: +; GCN-HSA: ; %bb.0: ; %entry +; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCN-HSA-NEXT: v_mov_b32_e32 v3, 0 +; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCN-HSA-NEXT: global_load_dwordx3 v[0:2], v3, s[2:3] +; GCN-HSA-NEXT: s_waitcnt vmcnt(0) +; GCN-HSA-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1] +; GCN-HSA-NEXT: s_endpgm entry: %ld = load <3 x i32>, ptr addrspace(1) %in store <3 x i32> %ld, ptr addrspace(1) %out ret void } -; FUNC-LABEL: {{^}}global_load_v4i32: -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 - -; EG: VTX_READ_128 define amdgpu_kernel void @global_load_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-NOHSA-LABEL: global_load_v4i32: +; SI-NOHSA: ; %bb.0: ; %entry +; SI-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; SI-NOHSA-NEXT: s_mov_b32 s6, -1 +; SI-NOHSA-NEXT: s_mov_b32 s10, s6 +; SI-NOHSA-NEXT: s_mov_b32 s11, s7 +; SI-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; SI-NOHSA-NEXT: s_mov_b32 s8, s2 +; SI-NOHSA-NEXT: s_mov_b32 s9, s3 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 +; SI-NOHSA-NEXT: s_mov_b32 s4, s0 +; SI-NOHSA-NEXT: s_mov_b32 s5, s1 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(0) +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 +; SI-NOHSA-NEXT: s_endpgm +; +; GCNX3-HSA-LABEL: global_load_v4i32: +; GCNX3-HSA: ; %bb.0: ; %entry +; GCNX3-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCNX3-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s1 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(0) +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; GCNX3-HSA-NEXT: s_endpgm +; +; GCNX3-NOHSA-LABEL: global_load_v4i32: +; GCNX3-NOHSA: ; %bb.0: ; %entry +; GCNX3-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GCNX3-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; GCNX3-NOHSA-NEXT: s_mov_b32 s6, -1 +; GCNX3-NOHSA-NEXT: s_mov_b32 s10, s6 +; GCNX3-NOHSA-NEXT: s_mov_b32 s11, s7 +; GCNX3-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-NOHSA-NEXT: s_mov_b32 s8, s2 +; GCNX3-NOHSA-NEXT: s_mov_b32 s9, s3 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s4, s0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s5, s1 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(0) +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 +; GCNX3-NOHSA-NEXT: s_endpgm +; +; EG-LABEL: global_load_v4i32: +; EG: ; %bb.0: ; %entry +; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 0 @6 +; EG-NEXT: ALU 1, @9, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 6: +; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1 +; EG-NEXT: ALU clause starting at 8: +; EG-NEXT: MOV * T0.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 9: +; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-HSA-LABEL: global_load_v4i32: +; GCN-HSA: ; %bb.0: ; %entry +; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCN-HSA-NEXT: v_mov_b32_e32 v4, 0 +; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCN-HSA-NEXT: global_load_dwordx4 v[0:3], v4, s[2:3] +; GCN-HSA-NEXT: s_waitcnt vmcnt(0) +; GCN-HSA-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] +; GCN-HSA-NEXT: s_endpgm entry: %ld = load <4 x i32>, ptr addrspace(1) %in store <4 x i32> %ld, ptr addrspace(1) %out ret void } -; FUNC-LABEL: {{^}}global_load_v8i32: -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 - -; EG: VTX_READ_128 -; EG: VTX_READ_128 define amdgpu_kernel void @global_load_v8i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-NOHSA-LABEL: global_load_v8i32: +; SI-NOHSA: ; %bb.0: ; %entry +; SI-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; SI-NOHSA-NEXT: s_mov_b32 s6, -1 +; SI-NOHSA-NEXT: s_mov_b32 s10, s6 +; SI-NOHSA-NEXT: s_mov_b32 s11, s7 +; SI-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; SI-NOHSA-NEXT: s_mov_b32 s8, s2 +; SI-NOHSA-NEXT: s_mov_b32 s9, s3 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 offset:16 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 +; SI-NOHSA-NEXT: s_mov_b32 s4, s0 +; SI-NOHSA-NEXT: s_mov_b32 s5, s1 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(1) +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 offset:16 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(1) +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 +; SI-NOHSA-NEXT: s_endpgm +; +; GCNX3-HSA-LABEL: global_load_v8i32: +; GCNX3-HSA: ; %bb.0: ; %entry +; GCNX3-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCNX3-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s2, 16 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s3, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s1 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s0 +; GCNX3-HSA-NEXT: s_add_u32 s0, s0, 16 +; GCNX3-HSA-NEXT: s_addc_u32 s1, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v11, s1 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v10, s0 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(1) +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[10:11], v[0:3] +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(1) +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[8:9], v[4:7] +; GCNX3-HSA-NEXT: s_endpgm +; +; GCNX3-NOHSA-LABEL: global_load_v8i32: +; GCNX3-NOHSA: ; %bb.0: ; %entry +; GCNX3-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GCNX3-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; GCNX3-NOHSA-NEXT: s_mov_b32 s6, -1 +; GCNX3-NOHSA-NEXT: s_mov_b32 s10, s6 +; GCNX3-NOHSA-NEXT: s_mov_b32 s11, s7 +; GCNX3-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-NOHSA-NEXT: s_mov_b32 s8, s2 +; GCNX3-NOHSA-NEXT: s_mov_b32 s9, s3 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 offset:16 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s4, s0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s5, s1 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(1) +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 offset:16 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(1) +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 +; GCNX3-NOHSA-NEXT: s_endpgm +; +; EG-LABEL: global_load_v8i32: +; EG: ; %bb.0: ; %entry +; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 1 @6 +; EG-NEXT: ALU 4, @11, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T3.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T2.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: Fetch clause starting at 6: +; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 0, #1 +; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 16, #1 +; EG-NEXT: ALU clause starting at 10: +; EG-NEXT: MOV * T0.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 11: +; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T2.X, PV.W, literal.x, +; EG-NEXT: LSHR * T3.X, KC0[2].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-HSA-LABEL: global_load_v8i32: +; GCN-HSA: ; %bb.0: ; %entry +; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCN-HSA-NEXT: v_mov_b32_e32 v8, 0 +; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCN-HSA-NEXT: global_load_dwordx4 v[0:3], v8, s[2:3] offset:16 +; GCN-HSA-NEXT: global_load_dwordx4 v[4:7], v8, s[2:3] +; GCN-HSA-NEXT: s_waitcnt vmcnt(1) +; GCN-HSA-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1] offset:16 +; GCN-HSA-NEXT: s_waitcnt vmcnt(1) +; GCN-HSA-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1] +; GCN-HSA-NEXT: s_endpgm entry: %ld = load <8 x i32>, ptr addrspace(1) %in store <8 x i32> %ld, ptr addrspace(1) %out ret void } -; FUNC-LABEL: {{^}}global_load_v9i32: -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dword -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dword define amdgpu_kernel void @global_load_v9i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-NOHSA-LABEL: global_load_v9i32: +; SI-NOHSA: ; %bb.0: ; %entry +; SI-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; SI-NOHSA-NEXT: s_mov_b32 s6, -1 +; SI-NOHSA-NEXT: s_mov_b32 s10, s6 +; SI-NOHSA-NEXT: s_mov_b32 s11, s7 +; SI-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; SI-NOHSA-NEXT: s_mov_b32 s8, s2 +; SI-NOHSA-NEXT: s_mov_b32 s9, s3 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16 +; SI-NOHSA-NEXT: buffer_load_dword v8, off, s[8:11], 0 offset:32 +; SI-NOHSA-NEXT: s_mov_b32 s4, s0 +; SI-NOHSA-NEXT: s_mov_b32 s5, s1 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(2) +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(2) +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(2) +; SI-NOHSA-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:32 +; SI-NOHSA-NEXT: s_endpgm +; +; GCNX3-HSA-LABEL: global_load_v9i32: +; GCNX3-HSA: ; %bb.0: ; %entry +; GCNX3-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCNX3-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 32 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2 +; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3 +; GCNX3-HSA-NEXT: s_add_u32 s2, s2, 16 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s3, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s5 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s2 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s4 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5] +; GCNX3-HSA-NEXT: flat_load_dword v14, v[8:9] +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 16 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s1 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s0 +; GCNX3-HSA-NEXT: s_add_u32 s0, s0, 32 +; GCNX3-HSA-NEXT: s_addc_u32 s1, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v11, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v13, s1 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v10, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v12, s0 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(2) +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[8:9], v[0:3] +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(2) +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[10:11], v[4:7] +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(2) +; GCNX3-HSA-NEXT: flat_store_dword v[12:13], v14 +; GCNX3-HSA-NEXT: s_endpgm +; +; GCNX3-NOHSA-LABEL: global_load_v9i32: +; GCNX3-NOHSA: ; %bb.0: ; %entry +; GCNX3-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GCNX3-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; GCNX3-NOHSA-NEXT: s_mov_b32 s6, -1 +; GCNX3-NOHSA-NEXT: s_mov_b32 s10, s6 +; GCNX3-NOHSA-NEXT: s_mov_b32 s11, s7 +; GCNX3-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-NOHSA-NEXT: s_mov_b32 s8, s2 +; GCNX3-NOHSA-NEXT: s_mov_b32 s9, s3 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16 +; GCNX3-NOHSA-NEXT: buffer_load_dword v8, off, s[8:11], 0 offset:32 +; GCNX3-NOHSA-NEXT: s_mov_b32 s4, s0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s5, s1 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(2) +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(2) +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(2) +; GCNX3-NOHSA-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:32 +; GCNX3-NOHSA-NEXT: s_endpgm +; +; EG-LABEL: global_load_v9i32: +; EG: ; %bb.0: ; %entry +; EG-NEXT: ALU 8, @14, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 2 @8 +; EG-NEXT: ALU 1, @23, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T5.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T1.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.X, T0.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 8: +; EG-NEXT: VTX_READ_128 T4.XYZW, T2.X, 0, #1 +; EG-NEXT: VTX_READ_128 T2.XYZW, T2.X, 16, #1 +; EG-NEXT: VTX_READ_32 T3.X, T3.X, 32, #1 +; EG-NEXT: ALU clause starting at 14: +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, +; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T0.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44) +; EG-NEXT: LSHR T1.X, PV.W, literal.x, +; EG-NEXT: MOV * T2.X, KC0[2].Z, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOV * T3.X, PS, +; EG-NEXT: ALU clause starting at 23: +; EG-NEXT: LSHR * T5.X, KC0[2].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-HSA-LABEL: global_load_v9i32: +; GCN-HSA: ; %bb.0: ; %entry +; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCN-HSA-NEXT: v_mov_b32_e32 v8, 0 +; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCN-HSA-NEXT: global_load_dwordx4 v[0:3], v8, s[2:3] +; GCN-HSA-NEXT: global_load_dwordx4 v[4:7], v8, s[2:3] offset:16 +; GCN-HSA-NEXT: global_load_dword v9, v8, s[2:3] offset:32 +; GCN-HSA-NEXT: s_waitcnt vmcnt(2) +; GCN-HSA-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1] +; GCN-HSA-NEXT: s_waitcnt vmcnt(2) +; GCN-HSA-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1] offset:16 +; GCN-HSA-NEXT: s_waitcnt vmcnt(2) +; GCN-HSA-NEXT: global_store_dword v8, v9, s[0:1] offset:32 +; GCN-HSA-NEXT: s_endpgm entry: %ld = load <9 x i32>, ptr addrspace(1) %in store <9 x i32> %ld, ptr addrspace(1) %out ret void } -; FUNC-LABEL: {{^}}global_load_v10i32: -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx2 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx2 define amdgpu_kernel void @global_load_v10i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-NOHSA-LABEL: global_load_v10i32: +; SI-NOHSA: ; %bb.0: ; %entry +; SI-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; SI-NOHSA-NEXT: s_mov_b32 s6, -1 +; SI-NOHSA-NEXT: s_mov_b32 s10, s6 +; SI-NOHSA-NEXT: s_mov_b32 s11, s7 +; SI-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; SI-NOHSA-NEXT: s_mov_b32 s8, s2 +; SI-NOHSA-NEXT: s_mov_b32 s9, s3 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16 +; SI-NOHSA-NEXT: buffer_load_dwordx2 v[8:9], off, s[8:11], 0 offset:32 +; SI-NOHSA-NEXT: s_mov_b32 s4, s0 +; SI-NOHSA-NEXT: s_mov_b32 s5, s1 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(2) +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(2) +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(2) +; SI-NOHSA-NEXT: buffer_store_dwordx2 v[8:9], off, s[4:7], 0 offset:32 +; SI-NOHSA-NEXT: s_endpgm +; +; GCNX3-HSA-LABEL: global_load_v10i32: +; GCNX3-HSA: ; %bb.0: ; %entry +; GCNX3-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCNX3-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 32 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2 +; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3 +; GCNX3-HSA-NEXT: s_add_u32 s2, s2, 16 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s3, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s5 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s4 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s2 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5] +; GCNX3-HSA-NEXT: flat_load_dwordx2 v[8:9], v[8:9] +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 16 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v11, s1 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v10, s0 +; GCNX3-HSA-NEXT: s_add_u32 s0, s0, 32 +; GCNX3-HSA-NEXT: s_addc_u32 s1, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v13, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v15, s1 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v12, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v14, s0 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(2) +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[10:11], v[0:3] +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(2) +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[12:13], v[4:7] +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(2) +; GCNX3-HSA-NEXT: flat_store_dwordx2 v[14:15], v[8:9] +; GCNX3-HSA-NEXT: s_endpgm +; +; GCNX3-NOHSA-LABEL: global_load_v10i32: +; GCNX3-NOHSA: ; %bb.0: ; %entry +; GCNX3-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GCNX3-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; GCNX3-NOHSA-NEXT: s_mov_b32 s6, -1 +; GCNX3-NOHSA-NEXT: s_mov_b32 s10, s6 +; GCNX3-NOHSA-NEXT: s_mov_b32 s11, s7 +; GCNX3-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-NOHSA-NEXT: s_mov_b32 s8, s2 +; GCNX3-NOHSA-NEXT: s_mov_b32 s9, s3 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx2 v[8:9], off, s[8:11], 0 offset:32 +; GCNX3-NOHSA-NEXT: s_mov_b32 s4, s0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s5, s1 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(2) +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(2) +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(2) +; GCNX3-NOHSA-NEXT: buffer_store_dwordx2 v[8:9], off, s[4:7], 0 offset:32 +; GCNX3-NOHSA-NEXT: s_endpgm +; +; EG-LABEL: global_load_v10i32: +; EG: ; %bb.0: ; %entry +; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 2 @8 +; EG-NEXT: ALU 7, @15, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T5.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T4.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T3.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 8: +; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 0, #1 +; EG-NEXT: VTX_READ_128 T2.XYZW, T0.X, 16, #1 +; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 32, #1 +; EG-NEXT: ALU clause starting at 14: +; EG-NEXT: MOV * T0.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 15: +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, +; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T3.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44) +; EG-NEXT: LSHR T4.X, PV.W, literal.x, +; EG-NEXT: LSHR * T5.X, KC0[2].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-HSA-LABEL: global_load_v10i32: +; GCN-HSA: ; %bb.0: ; %entry +; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCN-HSA-NEXT: v_mov_b32_e32 v10, 0 +; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCN-HSA-NEXT: global_load_dwordx4 v[0:3], v10, s[2:3] +; GCN-HSA-NEXT: global_load_dwordx4 v[4:7], v10, s[2:3] offset:16 +; GCN-HSA-NEXT: global_load_dwordx2 v[8:9], v10, s[2:3] offset:32 +; GCN-HSA-NEXT: s_waitcnt vmcnt(2) +; GCN-HSA-NEXT: global_store_dwordx4 v10, v[0:3], s[0:1] +; GCN-HSA-NEXT: s_waitcnt vmcnt(2) +; GCN-HSA-NEXT: global_store_dwordx4 v10, v[4:7], s[0:1] offset:16 +; GCN-HSA-NEXT: s_waitcnt vmcnt(2) +; GCN-HSA-NEXT: global_store_dwordx2 v10, v[8:9], s[0:1] offset:32 +; GCN-HSA-NEXT: s_endpgm entry: %ld = load <10 x i32>, ptr addrspace(1) %in store <10 x i32> %ld, ptr addrspace(1) %out ret void } -; FUNC-LABEL: {{^}}global_load_v11i32: -; SI-NOHSA: buffer_load_dwordx4 -; SI-NOHSA: buffer_load_dwordx4 -; SI-NOHSA: buffer_load_dwordx4 -; GCNX3-NOHSA: buffer_load_dwordx4 -; GCNX3-NOHSA: buffer_load_dwordx4 -; GCNX3-NOHSA: buffer_load_dwordx3 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx3 define amdgpu_kernel void @global_load_v11i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-NOHSA-LABEL: global_load_v11i32: +; SI-NOHSA: ; %bb.0: ; %entry +; SI-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; SI-NOHSA-NEXT: s_mov_b32 s6, -1 +; SI-NOHSA-NEXT: s_mov_b32 s10, s6 +; SI-NOHSA-NEXT: s_mov_b32 s11, s7 +; SI-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; SI-NOHSA-NEXT: s_mov_b32 s8, s2 +; SI-NOHSA-NEXT: s_mov_b32 s9, s3 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[8:11], off, s[8:11], 0 offset:32 +; SI-NOHSA-NEXT: s_mov_b32 s4, s0 +; SI-NOHSA-NEXT: s_mov_b32 s5, s1 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(2) +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(2) +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(2) +; SI-NOHSA-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:40 +; SI-NOHSA-NEXT: buffer_store_dwordx2 v[8:9], off, s[4:7], 0 offset:32 +; SI-NOHSA-NEXT: s_endpgm +; +; GCNX3-HSA-LABEL: global_load_v11i32: +; GCNX3-HSA: ; %bb.0: ; %entry +; GCNX3-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCNX3-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 32 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2 +; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3 +; GCNX3-HSA-NEXT: s_add_u32 s2, s2, 16 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s3, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s5 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s4 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s2 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5] +; GCNX3-HSA-NEXT: flat_load_dwordx3 v[8:10], v[8:9] +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 16 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v12, s1 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v11, s0 +; GCNX3-HSA-NEXT: s_add_u32 s0, s0, 32 +; GCNX3-HSA-NEXT: s_addc_u32 s1, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v14, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, s1 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v13, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v15, s0 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(2) +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[11:12], v[0:3] +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(2) +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[13:14], v[4:7] +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(2) +; GCNX3-HSA-NEXT: flat_store_dwordx3 v[15:16], v[8:10] +; GCNX3-HSA-NEXT: s_endpgm +; +; GCNX3-NOHSA-LABEL: global_load_v11i32: +; GCNX3-NOHSA: ; %bb.0: ; %entry +; GCNX3-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GCNX3-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; GCNX3-NOHSA-NEXT: s_mov_b32 s6, -1 +; GCNX3-NOHSA-NEXT: s_mov_b32 s10, s6 +; GCNX3-NOHSA-NEXT: s_mov_b32 s11, s7 +; GCNX3-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-NOHSA-NEXT: s_mov_b32 s8, s2 +; GCNX3-NOHSA-NEXT: s_mov_b32 s9, s3 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx3 v[8:10], off, s[8:11], 0 offset:32 +; GCNX3-NOHSA-NEXT: s_mov_b32 s4, s0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s5, s1 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(2) +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(2) +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(2) +; GCNX3-NOHSA-NEXT: buffer_store_dwordx3 v[8:10], off, s[4:7], 0 offset:32 +; GCNX3-NOHSA-NEXT: s_endpgm +; +; EG-LABEL: global_load_v11i32: +; EG: ; %bb.0: ; %entry +; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 2 @8 +; EG-NEXT: ALU 12, @15, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T7.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T6.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.X, T5.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T3.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: Fetch clause starting at 8: +; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 0, #1 +; EG-NEXT: VTX_READ_128 T2.XYZW, T0.X, 16, #1 +; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 32, #1 +; EG-NEXT: ALU clause starting at 14: +; EG-NEXT: MOV * T0.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 15: +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, +; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T3.X, PV.W, literal.x, +; EG-NEXT: MOV * T4.X, T0.Z, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, +; EG-NEXT: 40(5.605194e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T5.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44) +; EG-NEXT: LSHR T6.X, PV.W, literal.x, +; EG-NEXT: LSHR * T7.X, KC0[2].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-HSA-LABEL: global_load_v11i32: +; GCN-HSA: ; %bb.0: ; %entry +; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCN-HSA-NEXT: v_mov_b32_e32 v11, 0 +; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCN-HSA-NEXT: global_load_dwordx4 v[0:3], v11, s[2:3] +; GCN-HSA-NEXT: global_load_dwordx4 v[4:7], v11, s[2:3] offset:16 +; GCN-HSA-NEXT: global_load_dwordx3 v[8:10], v11, s[2:3] offset:32 +; GCN-HSA-NEXT: s_waitcnt vmcnt(2) +; GCN-HSA-NEXT: global_store_dwordx4 v11, v[0:3], s[0:1] +; GCN-HSA-NEXT: s_waitcnt vmcnt(2) +; GCN-HSA-NEXT: global_store_dwordx4 v11, v[4:7], s[0:1] offset:16 +; GCN-HSA-NEXT: s_waitcnt vmcnt(2) +; GCN-HSA-NEXT: global_store_dwordx3 v11, v[8:10], s[0:1] offset:32 +; GCN-HSA-NEXT: s_endpgm entry: %ld = load <11 x i32>, ptr addrspace(1) %in store <11 x i32> %ld, ptr addrspace(1) %out @@ -115,533 +827,3810 @@ entry: } -; FUNC-LABEL: {{^}}global_load_v12i32: -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 define amdgpu_kernel void @global_load_v12i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-NOHSA-LABEL: global_load_v12i32: +; SI-NOHSA: ; %bb.0: ; %entry +; SI-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; SI-NOHSA-NEXT: s_mov_b32 s6, -1 +; SI-NOHSA-NEXT: s_mov_b32 s10, s6 +; SI-NOHSA-NEXT: s_mov_b32 s11, s7 +; SI-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; SI-NOHSA-NEXT: s_mov_b32 s8, s2 +; SI-NOHSA-NEXT: s_mov_b32 s9, s3 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[8:11], off, s[8:11], 0 offset:32 +; SI-NOHSA-NEXT: s_mov_b32 s4, s0 +; SI-NOHSA-NEXT: s_mov_b32 s5, s1 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(2) +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(2) +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(2) +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[8:11], off, s[4:7], 0 offset:32 +; SI-NOHSA-NEXT: s_endpgm +; +; GCNX3-HSA-LABEL: global_load_v12i32: +; GCNX3-HSA: ; %bb.0: ; %entry +; GCNX3-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCNX3-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 32 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2 +; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3 +; GCNX3-HSA-NEXT: s_add_u32 s2, s2, 16 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s3, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s5 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s4 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s2 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5] +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[8:11], v[8:9] +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 16 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v13, s1 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v12, s0 +; GCNX3-HSA-NEXT: s_add_u32 s0, s0, 32 +; GCNX3-HSA-NEXT: s_addc_u32 s1, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v15, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v17, s1 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v14, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, s0 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(2) +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[12:13], v[0:3] +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(2) +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[14:15], v[4:7] +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(2) +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[16:17], v[8:11] +; GCNX3-HSA-NEXT: s_endpgm +; +; GCNX3-NOHSA-LABEL: global_load_v12i32: +; GCNX3-NOHSA: ; %bb.0: ; %entry +; GCNX3-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GCNX3-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; GCNX3-NOHSA-NEXT: s_mov_b32 s6, -1 +; GCNX3-NOHSA-NEXT: s_mov_b32 s10, s6 +; GCNX3-NOHSA-NEXT: s_mov_b32 s11, s7 +; GCNX3-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-NOHSA-NEXT: s_mov_b32 s8, s2 +; GCNX3-NOHSA-NEXT: s_mov_b32 s9, s3 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[8:11], off, s[8:11], 0 offset:32 +; GCNX3-NOHSA-NEXT: s_mov_b32 s4, s0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s5, s1 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(2) +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(2) +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(2) +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[8:11], off, s[4:7], 0 offset:32 +; GCNX3-NOHSA-NEXT: s_endpgm +; +; EG-LABEL: global_load_v12i32: +; EG: ; %bb.0: ; %entry +; EG-NEXT: ALU 7, @14, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 2 @8 +; EG-NEXT: ALU 1, @22, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.XYZW, T5.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T1.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T0.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 8: +; EG-NEXT: VTX_READ_128 T3.XYZW, T2.X, 0, #1 +; EG-NEXT: VTX_READ_128 T4.XYZW, T2.X, 16, #1 +; EG-NEXT: VTX_READ_128 T2.XYZW, T2.X, 32, #1 +; EG-NEXT: ALU clause starting at 14: +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, +; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T0.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44) +; EG-NEXT: LSHR T1.X, PV.W, literal.x, +; EG-NEXT: MOV * T2.X, KC0[2].Z, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: ALU clause starting at 22: +; EG-NEXT: LSHR * T5.X, KC0[2].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-HSA-LABEL: global_load_v12i32: +; GCN-HSA: ; %bb.0: ; %entry +; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCN-HSA-NEXT: v_mov_b32_e32 v12, 0 +; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCN-HSA-NEXT: global_load_dwordx4 v[0:3], v12, s[2:3] +; GCN-HSA-NEXT: global_load_dwordx4 v[4:7], v12, s[2:3] offset:16 +; GCN-HSA-NEXT: global_load_dwordx4 v[8:11], v12, s[2:3] offset:32 +; GCN-HSA-NEXT: s_waitcnt vmcnt(2) +; GCN-HSA-NEXT: global_store_dwordx4 v12, v[0:3], s[0:1] +; GCN-HSA-NEXT: s_waitcnt vmcnt(2) +; GCN-HSA-NEXT: global_store_dwordx4 v12, v[4:7], s[0:1] offset:16 +; GCN-HSA-NEXT: s_waitcnt vmcnt(2) +; GCN-HSA-NEXT: global_store_dwordx4 v12, v[8:11], s[0:1] offset:32 +; GCN-HSA-NEXT: s_endpgm entry: %ld = load <12 x i32>, ptr addrspace(1) %in store <12 x i32> %ld, ptr addrspace(1) %out ret void } -; FUNC-LABEL: {{^}}global_load_v16i32: -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 - -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 - -; EG: VTX_READ_128 -; EG: VTX_READ_128 -; EG: VTX_READ_128 -; EG: VTX_READ_128 define amdgpu_kernel void @global_load_v16i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-NOHSA-LABEL: global_load_v16i32: +; SI-NOHSA: ; %bb.0: ; %entry +; SI-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; SI-NOHSA-NEXT: s_mov_b32 s6, -1 +; SI-NOHSA-NEXT: s_mov_b32 s10, s6 +; SI-NOHSA-NEXT: s_mov_b32 s11, s7 +; SI-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; SI-NOHSA-NEXT: s_mov_b32 s4, s0 +; SI-NOHSA-NEXT: s_mov_b32 s5, s1 +; SI-NOHSA-NEXT: s_mov_b32 s8, s2 +; SI-NOHSA-NEXT: s_mov_b32 s9, s3 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 offset:32 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:48 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[8:11], off, s[8:11], 0 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[12:15], off, s[8:11], 0 offset:16 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(3) +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 offset:32 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(3) +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:48 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(3) +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[8:11], off, s[4:7], 0 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(3) +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[12:15], off, s[4:7], 0 offset:16 +; SI-NOHSA-NEXT: s_endpgm +; +; GCNX3-HSA-LABEL: global_load_v16i32: +; GCNX3-HSA: ; %bb.0: ; %entry +; GCNX3-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCNX3-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 16 +; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v13, s5 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v12, s4 +; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 48 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2 +; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3 +; GCNX3-HSA-NEXT: s_add_u32 s2, s2, 32 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s3, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s4 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s5 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s2 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5] +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[8:11], v[8:9] +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[12:15], v[12:13] +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 32 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v19, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v18, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 48 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v17, s1 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, s0 +; GCNX3-HSA-NEXT: s_add_u32 s0, s0, 16 +; GCNX3-HSA-NEXT: s_addc_u32 s1, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v21, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v23, s1 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v20, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v22, s0 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(3) +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[16:17], v[0:3] +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(3) +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[20:21], v[4:7] +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(3) +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[18:19], v[8:11] +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(3) +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[22:23], v[12:15] +; GCNX3-HSA-NEXT: s_endpgm +; +; GCNX3-NOHSA-LABEL: global_load_v16i32: +; GCNX3-NOHSA: ; %bb.0: ; %entry +; GCNX3-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GCNX3-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; GCNX3-NOHSA-NEXT: s_mov_b32 s6, -1 +; GCNX3-NOHSA-NEXT: s_mov_b32 s10, s6 +; GCNX3-NOHSA-NEXT: s_mov_b32 s11, s7 +; GCNX3-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-NOHSA-NEXT: s_mov_b32 s8, s2 +; GCNX3-NOHSA-NEXT: s_mov_b32 s9, s3 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 offset:32 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:48 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[8:11], off, s[8:11], 0 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[12:15], off, s[8:11], 0 offset:16 +; GCNX3-NOHSA-NEXT: s_mov_b32 s4, s0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s5, s1 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(3) +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 offset:32 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(3) +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:48 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(3) +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[8:11], off, s[4:7], 0 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(3) +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[12:15], off, s[4:7], 0 offset:16 +; GCNX3-NOHSA-NEXT: s_endpgm +; +; EG-LABEL: global_load_v16i32: +; EG: ; %bb.0: ; %entry +; EG-NEXT: ALU 11, @16, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 3 @8 +; EG-NEXT: ALU 1, @28, KC0[], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T7.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T5.XYZW, T2.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T1.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.XYZW, T0.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: Fetch clause starting at 8: +; EG-NEXT: VTX_READ_128 T4.XYZW, T3.X, 32, #1 +; EG-NEXT: VTX_READ_128 T5.XYZW, T3.X, 48, #1 +; EG-NEXT: VTX_READ_128 T6.XYZW, T3.X, 0, #1 +; EG-NEXT: VTX_READ_128 T3.XYZW, T3.X, 16, #1 +; EG-NEXT: ALU clause starting at 16: +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T0.X, PV.W, literal.x, +; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, +; EG-NEXT: 48(6.726233e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T2.X, PV.W, literal.x, +; EG-NEXT: MOV * T3.X, KC0[2].Z, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, +; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) +; EG-NEXT: ALU clause starting at 28: +; EG-NEXT: LSHR * T7.X, T0.W, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-HSA-LABEL: global_load_v16i32: +; GCN-HSA: ; %bb.0: ; %entry +; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCN-HSA-NEXT: v_mov_b32_e32 v16, 0 +; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCN-HSA-NEXT: global_load_dwordx4 v[0:3], v16, s[2:3] offset:32 +; GCN-HSA-NEXT: global_load_dwordx4 v[4:7], v16, s[2:3] offset:48 +; GCN-HSA-NEXT: global_load_dwordx4 v[8:11], v16, s[2:3] +; GCN-HSA-NEXT: global_load_dwordx4 v[12:15], v16, s[2:3] offset:16 +; GCN-HSA-NEXT: s_waitcnt vmcnt(3) +; GCN-HSA-NEXT: global_store_dwordx4 v16, v[0:3], s[0:1] offset:32 +; GCN-HSA-NEXT: s_waitcnt vmcnt(3) +; GCN-HSA-NEXT: global_store_dwordx4 v16, v[4:7], s[0:1] offset:48 +; GCN-HSA-NEXT: s_waitcnt vmcnt(3) +; GCN-HSA-NEXT: global_store_dwordx4 v16, v[8:11], s[0:1] +; GCN-HSA-NEXT: s_waitcnt vmcnt(3) +; GCN-HSA-NEXT: global_store_dwordx4 v16, v[12:15], s[0:1] offset:16 +; GCN-HSA-NEXT: s_endpgm entry: %ld = load <16 x i32>, ptr addrspace(1) %in store <16 x i32> %ld, ptr addrspace(1) %out ret void } -; FUNC-LABEL: {{^}}global_zextload_i32_to_i64: -; GCN-NOHSA-DAG: buffer_load_dword v[[LO:[0-9]+]], -; GCN-HSA-DAG: {{flat|global}}_load_dword v[[LO:[0-9]+]], -; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} - -; GCN-NOHSA: buffer_store_dwordx2 v[[[LO]]:[[HI]]] -; GCN-HSA: {{flat|global}}_store_dwordx2 v{{.+}}, v[[[LO]]:[[HI]]] - -; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY define amdgpu_kernel void @global_zextload_i32_to_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-NOHSA-LABEL: global_zextload_i32_to_i64: +; SI-NOHSA: ; %bb.0: +; SI-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; SI-NOHSA-NEXT: s_mov_b32 s6, -1 +; SI-NOHSA-NEXT: s_mov_b32 s10, s6 +; SI-NOHSA-NEXT: s_mov_b32 s11, s7 +; SI-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; SI-NOHSA-NEXT: s_mov_b32 s8, s2 +; SI-NOHSA-NEXT: s_mov_b32 s9, s3 +; SI-NOHSA-NEXT: buffer_load_dword v0, off, s[8:11], 0 +; SI-NOHSA-NEXT: s_mov_b32 s4, s0 +; SI-NOHSA-NEXT: s_mov_b32 s5, s1 +; SI-NOHSA-NEXT: v_mov_b32_e32 v1, 0 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(0) +; SI-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; SI-NOHSA-NEXT: s_endpgm +; +; GCNX3-HSA-LABEL: global_zextload_i32_to_i64: +; GCNX3-HSA: ; %bb.0: +; GCNX3-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCNX3-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3 +; GCNX3-HSA-NEXT: flat_load_dword v0, v[0:1] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, s0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v3, s1 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, 0 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(0) +; GCNX3-HSA-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GCNX3-HSA-NEXT: s_endpgm +; +; GCNX3-NOHSA-LABEL: global_zextload_i32_to_i64: +; GCNX3-NOHSA: ; %bb.0: +; GCNX3-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GCNX3-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; GCNX3-NOHSA-NEXT: s_mov_b32 s6, -1 +; GCNX3-NOHSA-NEXT: s_mov_b32 s10, s6 +; GCNX3-NOHSA-NEXT: s_mov_b32 s11, s7 +; GCNX3-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-NOHSA-NEXT: s_mov_b32 s8, s2 +; GCNX3-NOHSA-NEXT: s_mov_b32 s9, s3 +; GCNX3-NOHSA-NEXT: buffer_load_dword v0, off, s[8:11], 0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s4, s0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s5, s1 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v1, 0 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(0) +; GCNX3-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCNX3-NOHSA-NEXT: s_endpgm +; +; EG-LABEL: global_zextload_i32_to_i64: +; EG: ; %bb.0: +; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 0 @6 +; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 6: +; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1 +; EG-NEXT: ALU clause starting at 8: +; EG-NEXT: MOV * T0.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 9: +; EG-NEXT: MOV * T0.Y, 0.0, +; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-HSA-LABEL: global_zextload_i32_to_i64: +; GCN-HSA: ; %bb.0: +; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCN-HSA-NEXT: v_mov_b32_e32 v1, 0 +; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCN-HSA-NEXT: global_load_dword v0, v1, s[2:3] +; GCN-HSA-NEXT: s_waitcnt vmcnt(0) +; GCN-HSA-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1] +; GCN-HSA-NEXT: s_endpgm %ld = load i32, ptr addrspace(1) %in %ext = zext i32 %ld to i64 store i64 %ext, ptr addrspace(1) %out ret void } -; FUNC-LABEL: {{^}}global_sextload_i32_to_i64: -; GCN-NOHSA: buffer_load_dword v[[LO:[0-9]+]] -; GCN-HSA: {{flat|global}}_load_dword v[[LO:[0-9]+]] -; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] -; GCN-NOHSA: buffer_store_dwordx2 v[[[LO]]:[[HI]]] -; GCN-HSA: {{flat|global}}_store_dwordx2 v{{.+}}, v[[[LO]]:[[HI]]] - - -; EG: MEM_RAT -; EG: VTX_READ_32 -; EG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}}, literal. -; EG: 31 define amdgpu_kernel void @global_sextload_i32_to_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-NOHSA-LABEL: global_sextload_i32_to_i64: +; SI-NOHSA: ; %bb.0: +; SI-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; SI-NOHSA-NEXT: s_mov_b32 s6, -1 +; SI-NOHSA-NEXT: s_mov_b32 s10, s6 +; SI-NOHSA-NEXT: s_mov_b32 s11, s7 +; SI-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; SI-NOHSA-NEXT: s_mov_b32 s8, s2 +; SI-NOHSA-NEXT: s_mov_b32 s9, s3 +; SI-NOHSA-NEXT: buffer_load_dword v0, off, s[8:11], 0 +; SI-NOHSA-NEXT: s_mov_b32 s4, s0 +; SI-NOHSA-NEXT: s_mov_b32 s5, s1 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(0) +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; SI-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; SI-NOHSA-NEXT: s_endpgm +; +; GCNX3-HSA-LABEL: global_sextload_i32_to_i64: +; GCNX3-HSA: ; %bb.0: +; GCNX3-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCNX3-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3 +; GCNX3-HSA-NEXT: flat_load_dword v0, v[0:1] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, s0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v3, s1 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(0) +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; GCNX3-HSA-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GCNX3-HSA-NEXT: s_endpgm +; +; GCNX3-NOHSA-LABEL: global_sextload_i32_to_i64: +; GCNX3-NOHSA: ; %bb.0: +; GCNX3-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GCNX3-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; GCNX3-NOHSA-NEXT: s_mov_b32 s6, -1 +; GCNX3-NOHSA-NEXT: s_mov_b32 s10, s6 +; GCNX3-NOHSA-NEXT: s_mov_b32 s11, s7 +; GCNX3-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-NOHSA-NEXT: s_mov_b32 s8, s2 +; GCNX3-NOHSA-NEXT: s_mov_b32 s9, s3 +; GCNX3-NOHSA-NEXT: buffer_load_dword v0, off, s[8:11], 0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s4, s0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s5, s1 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(0) +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCNX3-NOHSA-NEXT: s_endpgm +; +; EG-LABEL: global_sextload_i32_to_i64: +; EG: ; %bb.0: +; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 0 @6 +; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 6: +; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1 +; EG-NEXT: ALU clause starting at 8: +; EG-NEXT: MOV * T0.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 9: +; EG-NEXT: LSHR T1.X, KC0[2].Y, literal.x, +; EG-NEXT: ASHR * T0.Y, T0.X, literal.y, +; EG-NEXT: 2(2.802597e-45), 31(4.344025e-44) +; +; GCN-HSA-LABEL: global_sextload_i32_to_i64: +; GCN-HSA: ; %bb.0: +; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, 0 +; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCN-HSA-NEXT: global_load_dword v0, v2, s[2:3] +; GCN-HSA-NEXT: s_waitcnt vmcnt(0) +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; GCN-HSA-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GCN-HSA-NEXT: s_endpgm %ld = load i32, ptr addrspace(1) %in %ext = sext i32 %ld to i64 store i64 %ext, ptr addrspace(1) %out ret void } -; FUNC-LABEL: {{^}}global_zextload_v1i32_to_v1i64: -; GCN-NOHSA: buffer_load_dword -; GCN-NOHSA: buffer_store_dwordx2 - -; GCN-HSA: {{flat|global}}_load_dword -; GCN-HSA: {{flat|global}}_store_dwordx2 define amdgpu_kernel void @global_zextload_v1i32_to_v1i64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-NOHSA-LABEL: global_zextload_v1i32_to_v1i64: +; SI-NOHSA: ; %bb.0: +; SI-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; SI-NOHSA-NEXT: s_mov_b32 s6, -1 +; SI-NOHSA-NEXT: s_mov_b32 s10, s6 +; SI-NOHSA-NEXT: s_mov_b32 s11, s7 +; SI-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; SI-NOHSA-NEXT: s_mov_b32 s8, s2 +; SI-NOHSA-NEXT: s_mov_b32 s9, s3 +; SI-NOHSA-NEXT: buffer_load_dword v0, off, s[8:11], 0 +; SI-NOHSA-NEXT: s_mov_b32 s4, s0 +; SI-NOHSA-NEXT: s_mov_b32 s5, s1 +; SI-NOHSA-NEXT: v_mov_b32_e32 v1, 0 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(0) +; SI-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; SI-NOHSA-NEXT: s_endpgm +; +; GCNX3-HSA-LABEL: global_zextload_v1i32_to_v1i64: +; GCNX3-HSA: ; %bb.0: +; GCNX3-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCNX3-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3 +; GCNX3-HSA-NEXT: flat_load_dword v0, v[0:1] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, s0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v3, s1 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, 0 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(0) +; GCNX3-HSA-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GCNX3-HSA-NEXT: s_endpgm +; +; GCNX3-NOHSA-LABEL: global_zextload_v1i32_to_v1i64: +; GCNX3-NOHSA: ; %bb.0: +; GCNX3-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GCNX3-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; GCNX3-NOHSA-NEXT: s_mov_b32 s6, -1 +; GCNX3-NOHSA-NEXT: s_mov_b32 s10, s6 +; GCNX3-NOHSA-NEXT: s_mov_b32 s11, s7 +; GCNX3-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-NOHSA-NEXT: s_mov_b32 s8, s2 +; GCNX3-NOHSA-NEXT: s_mov_b32 s9, s3 +; GCNX3-NOHSA-NEXT: buffer_load_dword v0, off, s[8:11], 0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s4, s0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s5, s1 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v1, 0 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(0) +; GCNX3-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCNX3-NOHSA-NEXT: s_endpgm +; +; EG-LABEL: global_zextload_v1i32_to_v1i64: +; EG: ; %bb.0: +; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 0 @6 +; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 6: +; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1 +; EG-NEXT: ALU clause starting at 8: +; EG-NEXT: MOV * T0.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 9: +; EG-NEXT: MOV * T0.Y, 0.0, +; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-HSA-LABEL: global_zextload_v1i32_to_v1i64: +; GCN-HSA: ; %bb.0: +; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCN-HSA-NEXT: v_mov_b32_e32 v1, 0 +; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCN-HSA-NEXT: global_load_dword v0, v1, s[2:3] +; GCN-HSA-NEXT: s_waitcnt vmcnt(0) +; GCN-HSA-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1] +; GCN-HSA-NEXT: s_endpgm %ld = load <1 x i32>, ptr addrspace(1) %in %ext = zext <1 x i32> %ld to <1 x i64> store <1 x i64> %ext, ptr addrspace(1) %out ret void } -; FUNC-LABEL: {{^}}global_sextload_v1i32_to_v1i64: -; GCN-NOHSA: buffer_load_dword v[[LO:[0-9]+]] -; GCN-HSA: {{flat|global}}_load_dword v[[LO:[0-9]+]] -; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] -; GCN-NOHSA: buffer_store_dwordx2 v[[[LO]]:[[HI]]] -; GCN-HSA: {{flat|global}}_store_dwordx2 v{{.+}}, v[[[LO]]:[[HI]]] define amdgpu_kernel void @global_sextload_v1i32_to_v1i64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-NOHSA-LABEL: global_sextload_v1i32_to_v1i64: +; SI-NOHSA: ; %bb.0: +; SI-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; SI-NOHSA-NEXT: s_mov_b32 s6, -1 +; SI-NOHSA-NEXT: s_mov_b32 s10, s6 +; SI-NOHSA-NEXT: s_mov_b32 s11, s7 +; SI-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; SI-NOHSA-NEXT: s_mov_b32 s8, s2 +; SI-NOHSA-NEXT: s_mov_b32 s9, s3 +; SI-NOHSA-NEXT: buffer_load_dword v0, off, s[8:11], 0 +; SI-NOHSA-NEXT: s_mov_b32 s4, s0 +; SI-NOHSA-NEXT: s_mov_b32 s5, s1 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(0) +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; SI-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; SI-NOHSA-NEXT: s_endpgm +; +; GCNX3-HSA-LABEL: global_sextload_v1i32_to_v1i64: +; GCNX3-HSA: ; %bb.0: +; GCNX3-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCNX3-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3 +; GCNX3-HSA-NEXT: flat_load_dword v0, v[0:1] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, s0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v3, s1 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(0) +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; GCNX3-HSA-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GCNX3-HSA-NEXT: s_endpgm +; +; GCNX3-NOHSA-LABEL: global_sextload_v1i32_to_v1i64: +; GCNX3-NOHSA: ; %bb.0: +; GCNX3-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GCNX3-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; GCNX3-NOHSA-NEXT: s_mov_b32 s6, -1 +; GCNX3-NOHSA-NEXT: s_mov_b32 s10, s6 +; GCNX3-NOHSA-NEXT: s_mov_b32 s11, s7 +; GCNX3-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-NOHSA-NEXT: s_mov_b32 s8, s2 +; GCNX3-NOHSA-NEXT: s_mov_b32 s9, s3 +; GCNX3-NOHSA-NEXT: buffer_load_dword v0, off, s[8:11], 0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s4, s0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s5, s1 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(0) +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCNX3-NOHSA-NEXT: s_endpgm +; +; EG-LABEL: global_sextload_v1i32_to_v1i64: +; EG: ; %bb.0: +; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 0 @6 +; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 6: +; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1 +; EG-NEXT: ALU clause starting at 8: +; EG-NEXT: MOV * T0.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 9: +; EG-NEXT: LSHR T1.X, KC0[2].Y, literal.x, +; EG-NEXT: ASHR * T0.Y, T0.X, literal.y, +; EG-NEXT: 2(2.802597e-45), 31(4.344025e-44) +; +; GCN-HSA-LABEL: global_sextload_v1i32_to_v1i64: +; GCN-HSA: ; %bb.0: +; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, 0 +; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCN-HSA-NEXT: global_load_dword v0, v2, s[2:3] +; GCN-HSA-NEXT: s_waitcnt vmcnt(0) +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; GCN-HSA-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GCN-HSA-NEXT: s_endpgm %ld = load <1 x i32>, ptr addrspace(1) %in %ext = sext <1 x i32> %ld to <1 x i64> store <1 x i64> %ext, ptr addrspace(1) %out ret void } -; FUNC-LABEL: {{^}}global_zextload_v2i32_to_v2i64: -; GCN-NOHSA: buffer_load_dwordx2 -; GCN-NOHSA: buffer_store_dwordx4 - -; GCN-HSA: {{flat|global}}_load_dwordx2 -; GCN-HSA: {{flat|global}}_store_dwordx4 define amdgpu_kernel void @global_zextload_v2i32_to_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-NOHSA-LABEL: global_zextload_v2i32_to_v2i64: +; SI-NOHSA: ; %bb.0: +; SI-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; SI-NOHSA-NEXT: s_mov_b32 s6, -1 +; SI-NOHSA-NEXT: s_mov_b32 s10, s6 +; SI-NOHSA-NEXT: s_mov_b32 s11, s7 +; SI-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; SI-NOHSA-NEXT: s_mov_b32 s8, s2 +; SI-NOHSA-NEXT: s_mov_b32 s9, s3 +; SI-NOHSA-NEXT: buffer_load_dwordx2 v[4:5], off, s[8:11], 0 +; SI-NOHSA-NEXT: v_mov_b32_e32 v1, 0 +; SI-NOHSA-NEXT: v_mov_b32_e32 v3, v1 +; SI-NOHSA-NEXT: s_mov_b32 s4, s0 +; SI-NOHSA-NEXT: s_mov_b32 s5, s1 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(0) +; SI-NOHSA-NEXT: v_mov_b32_e32 v0, v4 +; SI-NOHSA-NEXT: v_mov_b32_e32 v2, v5 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 +; SI-NOHSA-NEXT: s_endpgm +; +; GCNX3-HSA-LABEL: global_zextload_v2i32_to_v2i64: +; GCNX3-HSA: ; %bb.0: +; GCNX3-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCNX3-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3 +; GCNX3-HSA-NEXT: flat_load_dwordx2 v[2:3], v[0:1] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s1 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(0) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, v2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, v3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v3, v1 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; GCNX3-HSA-NEXT: s_endpgm +; +; GCNX3-NOHSA-LABEL: global_zextload_v2i32_to_v2i64: +; GCNX3-NOHSA: ; %bb.0: +; GCNX3-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GCNX3-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; GCNX3-NOHSA-NEXT: s_mov_b32 s6, -1 +; GCNX3-NOHSA-NEXT: s_mov_b32 s10, s6 +; GCNX3-NOHSA-NEXT: s_mov_b32 s11, s7 +; GCNX3-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-NOHSA-NEXT: s_mov_b32 s8, s2 +; GCNX3-NOHSA-NEXT: s_mov_b32 s9, s3 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx2 v[2:3], off, s[8:11], 0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v1, 0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s4, s0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s5, s1 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(0) +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v0, v2 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v2, v3 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v3, v1 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 +; GCNX3-NOHSA-NEXT: s_endpgm +; +; EG-LABEL: global_zextload_v2i32_to_v2i64: +; EG: ; %bb.0: +; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 0 @6 +; EG-NEXT: ALU 5, @9, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 6: +; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1 +; EG-NEXT: ALU clause starting at 8: +; EG-NEXT: MOV * T0.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 9: +; EG-NEXT: MOV T1.X, T0.X, +; EG-NEXT: MOV T1.Y, 0.0, +; EG-NEXT: MOV T1.Z, T0.Y, +; EG-NEXT: MOV T1.W, 0.0, +; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-HSA-LABEL: global_zextload_v2i32_to_v2i64: +; GCN-HSA: ; %bb.0: +; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCN-HSA-NEXT: v_mov_b32_e32 v1, 0 +; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCN-HSA-NEXT: global_load_dwordx2 v[2:3], v1, s[2:3] +; GCN-HSA-NEXT: s_waitcnt vmcnt(0) +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v2 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v3 +; GCN-HSA-NEXT: v_mov_b32_e32 v3, v1 +; GCN-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] +; GCN-HSA-NEXT: s_endpgm %ld = load <2 x i32>, ptr addrspace(1) %in %ext = zext <2 x i32> %ld to <2 x i64> store <2 x i64> %ext, ptr addrspace(1) %out ret void } -; FUNC-LABEL: {{^}}global_sextload_v2i32_to_v2i64: -; GCN-NOHSA: buffer_load_dwordx2 -; GCN-HSA: {{flat|global}}_load_dwordx2 - -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 - -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 define amdgpu_kernel void @global_sextload_v2i32_to_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-NOHSA-LABEL: global_sextload_v2i32_to_v2i64: +; SI-NOHSA: ; %bb.0: +; SI-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; SI-NOHSA-NEXT: s_mov_b32 s6, -1 +; SI-NOHSA-NEXT: s_mov_b32 s10, s6 +; SI-NOHSA-NEXT: s_mov_b32 s11, s7 +; SI-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; SI-NOHSA-NEXT: s_mov_b32 s8, s2 +; SI-NOHSA-NEXT: s_mov_b32 s9, s3 +; SI-NOHSA-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0 +; SI-NOHSA-NEXT: s_mov_b32 s4, s0 +; SI-NOHSA-NEXT: s_mov_b32 s5, s1 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(0) +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v3, 31, v1 +; SI-NOHSA-NEXT: v_mov_b32_e32 v2, v1 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 +; SI-NOHSA-NEXT: s_endpgm +; +; GCNX3-HSA-LABEL: global_sextload_v2i32_to_v2i64: +; GCNX3-HSA: ; %bb.0: +; GCNX3-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCNX3-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3 +; GCNX3-HSA-NEXT: flat_load_dwordx2 v[0:1], v[0:1] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s1 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(0) +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v3, 31, v1 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, v1 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; GCNX3-HSA-NEXT: s_endpgm +; +; GCNX3-NOHSA-LABEL: global_sextload_v2i32_to_v2i64: +; GCNX3-NOHSA: ; %bb.0: +; GCNX3-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GCNX3-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; GCNX3-NOHSA-NEXT: s_mov_b32 s6, -1 +; GCNX3-NOHSA-NEXT: s_mov_b32 s10, s6 +; GCNX3-NOHSA-NEXT: s_mov_b32 s11, s7 +; GCNX3-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-NOHSA-NEXT: s_mov_b32 s8, s2 +; GCNX3-NOHSA-NEXT: s_mov_b32 s9, s3 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s4, s0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s5, s1 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(0) +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v3, 31, v1 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v2, v1 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 +; GCNX3-NOHSA-NEXT: s_endpgm +; +; EG-LABEL: global_sextload_v2i32_to_v2i64: +; EG: ; %bb.0: +; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 0 @6 +; EG-NEXT: ALU 7, @9, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 6: +; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1 +; EG-NEXT: ALU clause starting at 8: +; EG-NEXT: MOV * T0.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 9: +; EG-NEXT: ASHR * T1.W, T0.Y, literal.x, +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: ASHR * T1.Y, T0.X, literal.x, +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: MOV T1.X, T0.X, +; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOV * T1.Z, T0.Y, +; +; GCN-HSA-LABEL: global_sextload_v2i32_to_v2i64: +; GCN-HSA: ; %bb.0: +; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCN-HSA-NEXT: v_mov_b32_e32 v4, 0 +; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCN-HSA-NEXT: global_load_dwordx2 v[0:1], v4, s[2:3] +; GCN-HSA-NEXT: s_waitcnt vmcnt(0) +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v3, 31, v1 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v1 +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; GCN-HSA-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] +; GCN-HSA-NEXT: s_endpgm %ld = load <2 x i32>, ptr addrspace(1) %in %ext = sext <2 x i32> %ld to <2 x i64> store <2 x i64> %ext, ptr addrspace(1) %out ret void } -; FUNC-LABEL: {{^}}global_zextload_v4i32_to_v4i64: -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_store_dwordx4 -; GCN-NOHSA: buffer_store_dwordx4 - -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_store_dwordx4 -; GCN-HSA: {{flat|global}}_store_dwordx4 define amdgpu_kernel void @global_zextload_v4i32_to_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-NOHSA-LABEL: global_zextload_v4i32_to_v4i64: +; SI-NOHSA: ; %bb.0: +; SI-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; SI-NOHSA-NEXT: s_mov_b32 s6, -1 +; SI-NOHSA-NEXT: s_mov_b32 s10, s6 +; SI-NOHSA-NEXT: s_mov_b32 s11, s7 +; SI-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; SI-NOHSA-NEXT: s_mov_b32 s8, s2 +; SI-NOHSA-NEXT: s_mov_b32 s9, s3 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 +; SI-NOHSA-NEXT: v_mov_b32_e32 v5, 0 +; SI-NOHSA-NEXT: v_mov_b32_e32 v7, v5 +; SI-NOHSA-NEXT: s_mov_b32 s4, s0 +; SI-NOHSA-NEXT: s_mov_b32 s5, s1 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(0) +; SI-NOHSA-NEXT: v_mov_b32_e32 v4, v2 +; SI-NOHSA-NEXT: v_mov_b32_e32 v6, v3 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16 +; SI-NOHSA-NEXT: s_waitcnt expcnt(0) +; SI-NOHSA-NEXT: v_mov_b32_e32 v4, v0 +; SI-NOHSA-NEXT: v_mov_b32_e32 v6, v1 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 +; SI-NOHSA-NEXT: s_endpgm +; +; GCNX3-HSA-LABEL: global_zextload_v4i32_to_v4i64: +; GCNX3-HSA: ; %bb.0: +; GCNX3-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v7, v5 +; GCNX3-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 16 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s2 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(0) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, v2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v6, v3 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[8:9], v[4:7] +; GCNX3-HSA-NEXT: s_nop 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, v0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v6, v1 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s1 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7] +; GCNX3-HSA-NEXT: s_endpgm +; +; GCNX3-NOHSA-LABEL: global_zextload_v4i32_to_v4i64: +; GCNX3-NOHSA: ; %bb.0: +; GCNX3-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GCNX3-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; GCNX3-NOHSA-NEXT: s_mov_b32 s6, -1 +; GCNX3-NOHSA-NEXT: s_mov_b32 s10, s6 +; GCNX3-NOHSA-NEXT: s_mov_b32 s11, s7 +; GCNX3-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-NOHSA-NEXT: s_mov_b32 s8, s2 +; GCNX3-NOHSA-NEXT: s_mov_b32 s9, s3 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v5, 0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v7, v5 +; GCNX3-NOHSA-NEXT: s_mov_b32 s4, s0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s5, s1 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(0) +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v4, v2 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v6, v3 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16 +; GCNX3-NOHSA-NEXT: s_nop 0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v4, v0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v6, v1 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 +; GCNX3-NOHSA-NEXT: s_endpgm +; +; EG-LABEL: global_zextload_v4i32_to_v4i64: +; EG: ; %bb.0: +; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 0 @6 +; EG-NEXT: ALU 12, @9, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T3.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T0.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: Fetch clause starting at 6: +; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1 +; EG-NEXT: ALU clause starting at 8: +; EG-NEXT: MOV * T0.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 9: +; EG-NEXT: MOV T1.X, T0.Z, +; EG-NEXT: MOV T1.Y, 0.0, +; EG-NEXT: MOV * T2.X, T0.X, +; EG-NEXT: MOV T2.Y, 0.0, +; EG-NEXT: MOV T1.Z, T0.W, +; EG-NEXT: MOV T1.W, 0.0, +; EG-NEXT: MOV * T2.Z, T0.Y, +; EG-NEXT: MOV * T2.W, 0.0, +; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44) +; EG-NEXT: LSHR * T3.X, PV.W, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-HSA-LABEL: global_zextload_v4i32_to_v4i64: +; GCN-HSA: ; %bb.0: +; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCN-HSA-NEXT: v_mov_b32_e32 v1, 0 +; GCN-HSA-NEXT: v_mov_b32_e32 v3, v1 +; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCN-HSA-NEXT: global_load_dwordx4 v[4:7], v1, s[2:3] +; GCN-HSA-NEXT: s_waitcnt vmcnt(0) +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v6 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v7 +; GCN-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] offset:16 +; GCN-HSA-NEXT: s_nop 0 +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v4 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v5 +; GCN-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] +; GCN-HSA-NEXT: s_endpgm %ld = load <4 x i32>, ptr addrspace(1) %in %ext = zext <4 x i32> %ld to <4 x i64> store <4 x i64> %ext, ptr addrspace(1) %out ret void } -; FUNC-LABEL: {{^}}global_sextload_v4i32_to_v4i64: -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 - -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 - -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-NOHSA-DAG: buffer_store_dwordx4 - -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 define amdgpu_kernel void @global_sextload_v4i32_to_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-NOHSA-LABEL: global_sextload_v4i32_to_v4i64: +; SI-NOHSA: ; %bb.0: +; SI-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; SI-NOHSA-NEXT: s_mov_b32 s6, -1 +; SI-NOHSA-NEXT: s_mov_b32 s10, s6 +; SI-NOHSA-NEXT: s_mov_b32 s11, s7 +; SI-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; SI-NOHSA-NEXT: s_mov_b32 s8, s2 +; SI-NOHSA-NEXT: s_mov_b32 s9, s3 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 +; SI-NOHSA-NEXT: s_mov_b32 s4, s0 +; SI-NOHSA-NEXT: s_mov_b32 s5, s1 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(0) +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v6, 31, v1 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v4, 31, v0 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v10, 31, v3 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v8, 31, v2 +; SI-NOHSA-NEXT: v_mov_b32_e32 v7, v2 +; SI-NOHSA-NEXT: v_mov_b32_e32 v9, v3 +; SI-NOHSA-NEXT: v_mov_b32_e32 v3, v0 +; SI-NOHSA-NEXT: v_mov_b32_e32 v5, v1 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[7:10], off, s[4:7], 0 offset:16 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[3:6], off, s[4:7], 0 +; SI-NOHSA-NEXT: s_endpgm +; +; GCNX3-HSA-LABEL: global_sextload_v4i32_to_v4i64: +; GCNX3-HSA: ; %bb.0: +; GCNX3-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCNX3-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 16 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v14, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v12, s1 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v13, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v11, s0 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(0) +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v10, 31, v3 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v8, 31, v2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v7, v2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, v3 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v6, 31, v1 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v4, 31, v0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v3, v0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, v1 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[13:14], v[7:10] +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[11:12], v[3:6] +; GCNX3-HSA-NEXT: s_endpgm +; +; GCNX3-NOHSA-LABEL: global_sextload_v4i32_to_v4i64: +; GCNX3-NOHSA: ; %bb.0: +; GCNX3-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GCNX3-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; GCNX3-NOHSA-NEXT: s_mov_b32 s6, -1 +; GCNX3-NOHSA-NEXT: s_mov_b32 s10, s6 +; GCNX3-NOHSA-NEXT: s_mov_b32 s11, s7 +; GCNX3-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-NOHSA-NEXT: s_mov_b32 s8, s2 +; GCNX3-NOHSA-NEXT: s_mov_b32 s9, s3 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s4, s0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s5, s1 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(0) +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v10, 31, v3 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v8, 31, v2 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v7, v2 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v9, v3 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v6, 31, v1 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v4, 31, v0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v3, v0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v5, v1 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[7:10], off, s[4:7], 0 offset:16 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[3:6], off, s[4:7], 0 +; GCNX3-NOHSA-NEXT: s_endpgm +; +; EG-LABEL: global_sextload_v4i32_to_v4i64: +; EG: ; %bb.0: +; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 0 @6 +; EG-NEXT: ALU 15, @9, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.XYZW, T0.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T2.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: Fetch clause starting at 6: +; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1 +; EG-NEXT: ALU clause starting at 8: +; EG-NEXT: MOV * T0.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 9: +; EG-NEXT: ASHR * T1.W, T0.Y, literal.x, +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T2.X, KC0[2].Y, literal.x, +; EG-NEXT: ASHR T1.Y, T0.X, literal.y, +; EG-NEXT: ASHR T3.W, T0.W, literal.y, +; EG-NEXT: MOV * T1.X, T0.X, +; EG-NEXT: 2(2.802597e-45), 31(4.344025e-44) +; EG-NEXT: ASHR * T3.Y, T0.Z, literal.x, +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: MOV T3.X, T0.Z, +; EG-NEXT: MOV T1.Z, T0.Y, +; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T0.X, PV.W, literal.x, +; EG-NEXT: MOV * T3.Z, T0.W, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-HSA-LABEL: global_sextload_v4i32_to_v4i64: +; GCN-HSA: ; %bb.0: +; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCN-HSA-NEXT: v_mov_b32_e32 v11, 0 +; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCN-HSA-NEXT: global_load_dwordx4 v[0:3], v11, s[2:3] +; GCN-HSA-NEXT: s_waitcnt vmcnt(0) +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v10, 31, v3 +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v8, 31, v2 +; GCN-HSA-NEXT: v_mov_b32_e32 v7, v2 +; GCN-HSA-NEXT: v_mov_b32_e32 v9, v3 +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v6, 31, v1 +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v4, 31, v0 +; GCN-HSA-NEXT: v_mov_b32_e32 v3, v0 +; GCN-HSA-NEXT: v_mov_b32_e32 v5, v1 +; GCN-HSA-NEXT: global_store_dwordx4 v11, v[7:10], s[0:1] offset:16 +; GCN-HSA-NEXT: global_store_dwordx4 v11, v[3:6], s[0:1] +; GCN-HSA-NEXT: s_endpgm %ld = load <4 x i32>, ptr addrspace(1) %in %ext = sext <4 x i32> %ld to <4 x i64> store <4 x i64> %ext, ptr addrspace(1) %out ret void } -; FUNC-LABEL: {{^}}global_zextload_v8i32_to_v8i64: -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 - -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 - -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-NOHSA-DAG: buffer_store_dwordx4 - -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 define amdgpu_kernel void @global_zextload_v8i32_to_v8i64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-NOHSA-LABEL: global_zextload_v8i32_to_v8i64: +; SI-NOHSA: ; %bb.0: +; SI-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; SI-NOHSA-NEXT: s_mov_b32 s6, -1 +; SI-NOHSA-NEXT: s_mov_b32 s10, s6 +; SI-NOHSA-NEXT: s_mov_b32 s11, s7 +; SI-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; SI-NOHSA-NEXT: s_mov_b32 s8, s2 +; SI-NOHSA-NEXT: s_mov_b32 s9, s3 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 offset:16 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 +; SI-NOHSA-NEXT: v_mov_b32_e32 v9, 0 +; SI-NOHSA-NEXT: v_mov_b32_e32 v11, v9 +; SI-NOHSA-NEXT: s_mov_b32 s4, s0 +; SI-NOHSA-NEXT: s_mov_b32 s5, s1 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(1) +; SI-NOHSA-NEXT: v_mov_b32_e32 v8, v2 +; SI-NOHSA-NEXT: v_mov_b32_e32 v10, v3 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[8:11], off, s[4:7], 0 offset:48 +; SI-NOHSA-NEXT: s_waitcnt expcnt(0) +; SI-NOHSA-NEXT: v_mov_b32_e32 v8, v0 +; SI-NOHSA-NEXT: v_mov_b32_e32 v10, v1 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[8:11], off, s[4:7], 0 offset:32 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(2) expcnt(0) +; SI-NOHSA-NEXT: v_mov_b32_e32 v8, v6 +; SI-NOHSA-NEXT: v_mov_b32_e32 v10, v7 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[8:11], off, s[4:7], 0 offset:16 +; SI-NOHSA-NEXT: s_waitcnt expcnt(0) +; SI-NOHSA-NEXT: v_mov_b32_e32 v8, v4 +; SI-NOHSA-NEXT: v_mov_b32_e32 v10, v5 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[8:11], off, s[4:7], 0 +; SI-NOHSA-NEXT: s_endpgm +; +; GCNX3-HSA-LABEL: global_zextload_v8i32_to_v8i64: +; GCNX3-HSA: ; %bb.0: +; GCNX3-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v11, v9 +; GCNX3-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3 +; GCNX3-HSA-NEXT: s_add_u32 s2, s2, 16 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s3, 0 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s2 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5] +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 16 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v15, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v14, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 48 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v13, s1 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v12, s0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v17, s3 +; GCNX3-HSA-NEXT: s_add_u32 s0, s0, 32 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, s2 +; GCNX3-HSA-NEXT: s_addc_u32 s1, s1, 0 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(1) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, v2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v10, v3 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[14:15], v[8:11] +; GCNX3-HSA-NEXT: s_nop 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, v0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v10, v1 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[12:13], v[8:11] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s0 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(2) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, v6 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v10, v7 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[16:17], v[8:11] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s1 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, v4 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v10, v5 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[0:1], v[8:11] +; GCNX3-HSA-NEXT: s_endpgm +; +; GCNX3-NOHSA-LABEL: global_zextload_v8i32_to_v8i64: +; GCNX3-NOHSA: ; %bb.0: +; GCNX3-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GCNX3-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; GCNX3-NOHSA-NEXT: s_mov_b32 s6, -1 +; GCNX3-NOHSA-NEXT: s_mov_b32 s10, s6 +; GCNX3-NOHSA-NEXT: s_mov_b32 s11, s7 +; GCNX3-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-NOHSA-NEXT: s_mov_b32 s8, s2 +; GCNX3-NOHSA-NEXT: s_mov_b32 s9, s3 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 offset:16 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v9, 0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v11, v9 +; GCNX3-NOHSA-NEXT: s_mov_b32 s4, s0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s5, s1 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(1) +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v8, v2 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v10, v3 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[8:11], off, s[4:7], 0 offset:48 +; GCNX3-NOHSA-NEXT: s_nop 0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v8, v0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v10, v1 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[8:11], off, s[4:7], 0 offset:32 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(2) +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v8, v6 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v10, v7 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[8:11], off, s[4:7], 0 offset:16 +; GCNX3-NOHSA-NEXT: s_nop 0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v8, v4 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v10, v5 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[8:11], off, s[4:7], 0 +; GCNX3-NOHSA-NEXT: s_endpgm +; +; EG-LABEL: global_zextload_v8i32_to_v8i64: +; EG: ; %bb.0: +; EG-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 1 @8 +; EG-NEXT: ALU 26, @13, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T7.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.XYZW, T6.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T1.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T5.XYZW, T0.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: Fetch clause starting at 8: +; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 16, #1 +; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1 +; EG-NEXT: ALU clause starting at 12: +; EG-NEXT: MOV * T0.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 13: +; EG-NEXT: MOV T2.X, T1.Z, +; EG-NEXT: MOV T2.Y, 0.0, +; EG-NEXT: MOV * T3.X, T1.X, +; EG-NEXT: MOV * T3.Y, 0.0, +; EG-NEXT: MOV T4.X, T0.Z, +; EG-NEXT: MOV T4.Y, 0.0, +; EG-NEXT: MOV * T5.X, T0.X, +; EG-NEXT: MOV T5.Y, 0.0, +; EG-NEXT: MOV T2.Z, T1.W, +; EG-NEXT: MOV T2.W, 0.0, +; EG-NEXT: MOV * T3.Z, T1.Y, +; EG-NEXT: MOV * T3.W, 0.0, +; EG-NEXT: MOV T4.Z, T0.W, +; EG-NEXT: MOV T4.W, 0.0, +; EG-NEXT: MOV * T5.Z, T0.Y, +; EG-NEXT: MOV * T5.W, 0.0, +; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44) +; EG-NEXT: LSHR T1.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44) +; EG-NEXT: LSHR T6.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 48(6.726233e-44) +; EG-NEXT: LSHR * T7.X, PV.W, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-HSA-LABEL: global_zextload_v8i32_to_v8i64: +; GCN-HSA: ; %bb.0: +; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCN-HSA-NEXT: v_mov_b32_e32 v1, 0 +; GCN-HSA-NEXT: v_mov_b32_e32 v3, v1 +; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCN-HSA-NEXT: global_load_dwordx4 v[4:7], v1, s[2:3] offset:16 +; GCN-HSA-NEXT: global_load_dwordx4 v[8:11], v1, s[2:3] +; GCN-HSA-NEXT: s_waitcnt vmcnt(1) +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v6 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v7 +; GCN-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] offset:48 +; GCN-HSA-NEXT: s_nop 0 +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v4 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v5 +; GCN-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] offset:32 +; GCN-HSA-NEXT: s_waitcnt vmcnt(2) +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v10 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v11 +; GCN-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] offset:16 +; GCN-HSA-NEXT: s_nop 0 +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v8 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v9 +; GCN-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] +; GCN-HSA-NEXT: s_endpgm %ld = load <8 x i32>, ptr addrspace(1) %in %ext = zext <8 x i32> %ld to <8 x i64> store <8 x i64> %ext, ptr addrspace(1) %out ret void } -; FUNC-LABEL: {{^}}global_sextload_v8i32_to_v8i64: -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 - -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 - -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 - -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-NOHSA-DAG: buffer_store_dwordx4 - -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 define amdgpu_kernel void @global_sextload_v8i32_to_v8i64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-NOHSA-LABEL: global_sextload_v8i32_to_v8i64: +; SI-NOHSA: ; %bb.0: +; SI-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; SI-NOHSA-NEXT: s_mov_b32 s6, -1 +; SI-NOHSA-NEXT: s_mov_b32 s10, s6 +; SI-NOHSA-NEXT: s_mov_b32 s11, s7 +; SI-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; SI-NOHSA-NEXT: s_mov_b32 s8, s2 +; SI-NOHSA-NEXT: s_mov_b32 s9, s3 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 +; SI-NOHSA-NEXT: s_mov_b32 s4, s0 +; SI-NOHSA-NEXT: s_mov_b32 s5, s1 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(1) +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v10, 31, v1 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v8, 31, v0 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v14, 31, v3 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v12, 31, v2 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(0) +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v18, 31, v5 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v16, 31, v4 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v22, 31, v7 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v20, 31, v6 +; SI-NOHSA-NEXT: v_mov_b32_e32 v19, v6 +; SI-NOHSA-NEXT: v_mov_b32_e32 v21, v7 +; SI-NOHSA-NEXT: v_mov_b32_e32 v15, v4 +; SI-NOHSA-NEXT: v_mov_b32_e32 v17, v5 +; SI-NOHSA-NEXT: v_mov_b32_e32 v11, v2 +; SI-NOHSA-NEXT: v_mov_b32_e32 v13, v3 +; SI-NOHSA-NEXT: v_mov_b32_e32 v7, v0 +; SI-NOHSA-NEXT: v_mov_b32_e32 v9, v1 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[19:22], off, s[4:7], 0 offset:48 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[15:18], off, s[4:7], 0 offset:32 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[11:14], off, s[4:7], 0 offset:16 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[7:10], off, s[4:7], 0 +; SI-NOHSA-NEXT: s_endpgm +; +; GCNX3-HSA-LABEL: global_sextload_v8i32_to_v8i64: +; GCNX3-HSA: ; %bb.0: +; GCNX3-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCNX3-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3 +; GCNX3-HSA-NEXT: s_add_u32 s2, s2, 16 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s3, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s3 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s2 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5] +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 16 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v19, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v18, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 48 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v17, s1 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, s0 +; GCNX3-HSA-NEXT: s_add_u32 s0, s0, 32 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v21, s3 +; GCNX3-HSA-NEXT: s_addc_u32 s1, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v20, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v23, s1 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v22, s0 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(1) +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v11, 31, v1 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v9, 31, v0 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v15, 31, v3 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v13, 31, v2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v12, v2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v14, v3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, v0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v10, v1 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[18:19], v[12:15] +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[16:17], v[8:11] +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(2) +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v3, 31, v5 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v11, 31, v7 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v9, 31, v6 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, v6 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v10, v7 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v1, 31, v4 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, v4 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, v5 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[20:21], v[8:11] +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[22:23], v[0:3] +; GCNX3-HSA-NEXT: s_endpgm +; +; GCNX3-NOHSA-LABEL: global_sextload_v8i32_to_v8i64: +; GCNX3-NOHSA: ; %bb.0: +; GCNX3-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GCNX3-NOHSA-NEXT: s_mov_b32 s3, 0xf000 +; GCNX3-NOHSA-NEXT: s_mov_b32 s2, -1 +; GCNX3-NOHSA-NEXT: s_mov_b32 s10, s2 +; GCNX3-NOHSA-NEXT: s_mov_b32 s11, s3 +; GCNX3-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-NOHSA-NEXT: s_mov_b32 s8, s6 +; GCNX3-NOHSA-NEXT: s_mov_b32 s9, s7 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16 +; GCNX3-NOHSA-NEXT: s_mov_b32 s0, s4 +; GCNX3-NOHSA-NEXT: s_mov_b32 s1, s5 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(1) +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v10, 31, v1 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(0) +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v22, 31, v7 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v20, 31, v6 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v19, v6 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v21, v7 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v8, 31, v0 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v14, 31, v3 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v12, 31, v2 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v18, 31, v5 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v16, 31, v4 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v15, v4 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v17, v5 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v11, v2 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v13, v3 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v7, v0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v9, v1 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[19:22], off, s[0:3], 0 offset:48 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[15:18], off, s[0:3], 0 offset:32 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[11:14], off, s[0:3], 0 offset:16 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[7:10], off, s[0:3], 0 +; GCNX3-NOHSA-NEXT: s_endpgm +; +; EG-LABEL: global_sextload_v8i32_to_v8i64: +; EG: ; %bb.0: +; EG-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 1 @8 +; EG-NEXT: ALU 31, @13, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T8.XYZW, T0.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T7.XYZW, T5.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T3.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T2.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: Fetch clause starting at 8: +; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 16, #1 +; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1 +; EG-NEXT: ALU clause starting at 12: +; EG-NEXT: MOV * T0.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 13: +; EG-NEXT: LSHR T2.X, KC0[2].Y, literal.x, +; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44) +; EG-NEXT: LSHR T3.X, PV.W, literal.x, +; EG-NEXT: ADD_INT T2.W, KC0[2].Y, literal.y, +; EG-NEXT: ASHR * T4.W, T0.Y, literal.z, +; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44) +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T5.X, PV.W, literal.x, +; EG-NEXT: ASHR T4.Y, T0.X, literal.y, +; EG-NEXT: ASHR T6.W, T0.W, literal.y, +; EG-NEXT: MOV * T4.X, T0.X, +; EG-NEXT: 2(2.802597e-45), 31(4.344025e-44) +; EG-NEXT: ASHR T6.Y, T0.Z, literal.x, +; EG-NEXT: ASHR * T7.W, T1.Y, literal.x, +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: MOV T6.X, T0.Z, +; EG-NEXT: ASHR T7.Y, T1.X, literal.x, +; EG-NEXT: MOV T4.Z, T0.Y, +; EG-NEXT: ASHR T8.W, T1.W, literal.x, +; EG-NEXT: MOV * T7.X, T1.X, +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: ASHR T8.Y, T1.Z, literal.x, +; EG-NEXT: MOV * T6.Z, T0.W, +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: MOV T8.X, T1.Z, +; EG-NEXT: MOV T7.Z, T1.Y, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, +; EG-NEXT: 48(6.726233e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T0.X, PV.W, literal.x, +; EG-NEXT: MOV * T8.Z, T1.W, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-HSA-LABEL: global_sextload_v8i32_to_v8i64: +; GCN-HSA: ; %bb.0: +; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCN-HSA-NEXT: v_mov_b32_e32 v23, 0 +; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCN-HSA-NEXT: global_load_dwordx4 v[0:3], v23, s[2:3] +; GCN-HSA-NEXT: global_load_dwordx4 v[4:7], v23, s[2:3] offset:16 +; GCN-HSA-NEXT: s_waitcnt vmcnt(1) +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v10, 31, v1 +; GCN-HSA-NEXT: s_waitcnt vmcnt(0) +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v22, 31, v7 +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v20, 31, v6 +; GCN-HSA-NEXT: v_mov_b32_e32 v19, v6 +; GCN-HSA-NEXT: v_mov_b32_e32 v21, v7 +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v8, 31, v0 +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v14, 31, v3 +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v12, 31, v2 +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v18, 31, v5 +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v16, 31, v4 +; GCN-HSA-NEXT: v_mov_b32_e32 v15, v4 +; GCN-HSA-NEXT: v_mov_b32_e32 v17, v5 +; GCN-HSA-NEXT: v_mov_b32_e32 v11, v2 +; GCN-HSA-NEXT: v_mov_b32_e32 v13, v3 +; GCN-HSA-NEXT: v_mov_b32_e32 v7, v0 +; GCN-HSA-NEXT: v_mov_b32_e32 v9, v1 +; GCN-HSA-NEXT: global_store_dwordx4 v23, v[19:22], s[0:1] offset:48 +; GCN-HSA-NEXT: global_store_dwordx4 v23, v[15:18], s[0:1] offset:32 +; GCN-HSA-NEXT: global_store_dwordx4 v23, v[11:14], s[0:1] offset:16 +; GCN-HSA-NEXT: global_store_dwordx4 v23, v[7:10], s[0:1] +; GCN-HSA-NEXT: s_endpgm %ld = load <8 x i32>, ptr addrspace(1) %in %ext = sext <8 x i32> %ld to <8 x i64> store <8 x i64> %ext, ptr addrspace(1) %out ret void } -; FUNC-LABEL: {{^}}global_sextload_v16i32_to_v16i64: -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 - -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 - - -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 - -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 - -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 - -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 define amdgpu_kernel void @global_sextload_v16i32_to_v16i64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-NOHSA-LABEL: global_sextload_v16i32_to_v16i64: +; SI-NOHSA: ; %bb.0: +; SI-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; SI-NOHSA-NEXT: s_mov_b32 s3, 0xf000 +; SI-NOHSA-NEXT: s_mov_b32 s2, -1 +; SI-NOHSA-NEXT: s_mov_b32 s10, s2 +; SI-NOHSA-NEXT: s_mov_b32 s11, s3 +; SI-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; SI-NOHSA-NEXT: s_mov_b32 s8, s6 +; SI-NOHSA-NEXT: s_mov_b32 s9, s7 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 offset:48 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:32 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[8:11], off, s[8:11], 0 offset:16 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[12:15], off, s[8:11], 0 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(3) +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v19, 31, v3 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v17, 31, v2 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v23, 31, v1 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v21, 31, v0 +; SI-NOHSA-NEXT: v_mov_b32_e32 v20, v0 +; SI-NOHSA-NEXT: v_mov_b32_e32 v22, v1 +; SI-NOHSA-NEXT: v_mov_b32_e32 v16, v2 +; SI-NOHSA-NEXT: v_mov_b32_e32 v18, v3 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(2) +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v3, 31, v7 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v1, 31, v6 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v27, 31, v5 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v25, 31, v4 +; SI-NOHSA-NEXT: v_mov_b32_e32 v24, v4 +; SI-NOHSA-NEXT: v_mov_b32_e32 v26, v5 +; SI-NOHSA-NEXT: v_mov_b32_e32 v0, v6 +; SI-NOHSA-NEXT: v_mov_b32_e32 v2, v7 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(1) +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v7, 31, v11 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v5, 31, v10 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v31, 31, v9 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v29, 31, v8 +; SI-NOHSA-NEXT: v_mov_b32_e32 v28, v8 +; SI-NOHSA-NEXT: v_mov_b32_e32 v30, v9 +; SI-NOHSA-NEXT: v_mov_b32_e32 v4, v10 +; SI-NOHSA-NEXT: v_mov_b32_e32 v6, v11 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(0) +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v11, 31, v15 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v9, 31, v14 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v35, 31, v13 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v33, 31, v12 +; SI-NOHSA-NEXT: v_mov_b32_e32 v32, v12 +; SI-NOHSA-NEXT: v_mov_b32_e32 v34, v13 +; SI-NOHSA-NEXT: v_mov_b32_e32 v8, v14 +; SI-NOHSA-NEXT: v_mov_b32_e32 v10, v15 +; SI-NOHSA-NEXT: s_mov_b32 s0, s4 +; SI-NOHSA-NEXT: s_mov_b32 s1, s5 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[20:23], off, s[0:3], 0 offset:96 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:112 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[24:27], off, s[0:3], 0 offset:64 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:80 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[28:31], off, s[0:3], 0 offset:32 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:48 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[32:35], off, s[0:3], 0 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:16 +; SI-NOHSA-NEXT: s_endpgm +; +; GCNX3-HSA-LABEL: global_sextload_v16i32_to_v16i64: +; GCNX3-HSA: ; %bb.0: +; GCNX3-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCNX3-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[8:11], v[0:1] +; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 48 +; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s4 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s5 +; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 32 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[12:15], v[0:1] +; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s4 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s5 +; GCNX3-HSA-NEXT: s_add_u32 s2, s2, 16 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[4:7], v[0:1] +; GCNX3-HSA-NEXT: s_addc_u32 s3, s3, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 16 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v23, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v22, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0x60 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v25, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v24, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0x70 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v27, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v21, s1 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v26, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 64 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v20, s0 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(3) +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v19, 31, v9 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v17, 31, v8 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, v8 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v18, v9 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[20:21], v[16:19] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v21, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v20, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0x50 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v29, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v28, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 32 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v19, 31, v11 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v17, 31, v10 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, v10 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v18, v11 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[22:23], v[16:19] +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(4) +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v11, 31, v15 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v9, 31, v14 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v19, 31, v13 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v17, 31, v12 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, v12 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v18, v13 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, v14 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v10, v15 +; GCNX3-HSA-NEXT: s_add_u32 s0, s0, 48 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v23, s3 +; GCNX3-HSA-NEXT: s_addc_u32 s1, s1, 0 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[24:25], v[16:19] +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[26:27], v[8:11] +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(5) +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v15, 31, v5 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v11, 31, v7 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v9, 31, v6 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v13, 31, v4 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v12, v4 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v14, v5 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, v6 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v10, v7 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v22, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v31, s1 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[20:21], v[12:15] +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[28:29], v[8:11] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v30, s0 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(6) +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v11, 31, v1 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v9, 31, v0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, v0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v10, v1 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v7, 31, v3 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v5, 31, v2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, v2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v6, v3 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[22:23], v[8:11] +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[30:31], v[4:7] +; GCNX3-HSA-NEXT: s_endpgm +; +; GCNX3-NOHSA-LABEL: global_sextload_v16i32_to_v16i64: +; GCNX3-NOHSA: ; %bb.0: +; GCNX3-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GCNX3-NOHSA-NEXT: s_mov_b32 s3, 0xf000 +; GCNX3-NOHSA-NEXT: s_mov_b32 s2, -1 +; GCNX3-NOHSA-NEXT: s_mov_b32 s10, s2 +; GCNX3-NOHSA-NEXT: s_mov_b32 s11, s3 +; GCNX3-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-NOHSA-NEXT: s_mov_b32 s8, s6 +; GCNX3-NOHSA-NEXT: s_mov_b32 s9, s7 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 offset:32 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:48 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[8:11], off, s[8:11], 0 offset:16 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[12:15], off, s[8:11], 0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s0, s4 +; GCNX3-NOHSA-NEXT: s_mov_b32 s1, s5 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(3) +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v19, 31, v3 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(2) +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v27, 31, v5 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v25, 31, v4 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v24, v4 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v26, v5 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v17, 31, v2 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v23, 31, v7 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v21, 31, v6 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v20, v6 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v22, v7 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v7, 31, v1 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v5, 31, v0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v4, v0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v6, v1 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v16, v2 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v18, v3 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(1) +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v3, 31, v11 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v1, 31, v10 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v31, 31, v9 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v29, 31, v8 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v28, v8 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v30, v9 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v0, v10 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v2, v11 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(0) +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v11, 31, v15 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v9, 31, v14 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v35, 31, v13 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v33, 31, v12 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v32, v12 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v34, v13 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v8, v14 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v10, v15 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[24:27], off, s[0:3], 0 offset:96 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[20:23], off, s[0:3], 0 offset:112 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:64 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:80 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[28:31], off, s[0:3], 0 offset:32 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[32:35], off, s[0:3], 0 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:16 +; GCNX3-NOHSA-NEXT: s_endpgm +; +; EG-LABEL: global_sextload_v16i32_to_v16i64: +; EG: ; %bb.0: +; EG-NEXT: ALU 0, @20, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 3 @12 +; EG-NEXT: ALU 64, @21, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T16.XYZW, T1.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.XYZW, T11.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T15.XYZW, T9.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T8.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T14.XYZW, T7.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T13.XYZW, T6.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T12.XYZW, T5.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T10.XYZW, T4.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: Fetch clause starting at 12: +; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 48, #1 +; EG-NEXT: VTX_READ_128 T2.XYZW, T0.X, 32, #1 +; EG-NEXT: VTX_READ_128 T3.XYZW, T0.X, 16, #1 +; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1 +; EG-NEXT: ALU clause starting at 20: +; EG-NEXT: MOV * T0.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 21: +; EG-NEXT: ADD_INT * T4.W, KC0[2].Y, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T4.X, PV.W, literal.x, +; EG-NEXT: LSHR * T5.X, KC0[2].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: ADD_INT * T4.W, KC0[2].Y, literal.x, +; EG-NEXT: 48(6.726233e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T6.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T4.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44) +; EG-NEXT: LSHR T7.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T4.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 80(1.121039e-43) +; EG-NEXT: LSHR T8.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T4.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 64(8.968310e-44) +; EG-NEXT: LSHR T9.X, PV.W, literal.x, +; EG-NEXT: ADD_INT T4.W, KC0[2].Y, literal.y, +; EG-NEXT: ASHR * T10.W, T0.W, literal.z, +; EG-NEXT: 2(2.802597e-45), 112(1.569454e-43) +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T11.X, PV.W, literal.x, +; EG-NEXT: ASHR T10.Y, T0.Z, literal.y, +; EG-NEXT: ASHR T12.W, T0.Y, literal.y, +; EG-NEXT: MOV * T10.X, T0.Z, +; EG-NEXT: 2(2.802597e-45), 31(4.344025e-44) +; EG-NEXT: ASHR T12.Y, T0.X, literal.x, +; EG-NEXT: ASHR * T13.W, T3.W, literal.x, +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: MOV T12.X, T0.X, +; EG-NEXT: ASHR T13.Y, T3.Z, literal.x, +; EG-NEXT: MOV T10.Z, T0.W, +; EG-NEXT: ASHR T14.W, T3.Y, literal.x, +; EG-NEXT: MOV * T13.X, T3.Z, +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: ASHR T14.Y, T3.X, literal.x, +; EG-NEXT: MOV T12.Z, T0.Y, +; EG-NEXT: ASHR * T0.W, T2.W, literal.x, +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: MOV T14.X, T3.X, +; EG-NEXT: ASHR T0.Y, T2.Z, literal.x, +; EG-NEXT: MOV T13.Z, T3.W, +; EG-NEXT: ASHR T15.W, T2.Y, literal.x, +; EG-NEXT: MOV * T0.X, T2.Z, +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: ASHR T15.Y, T2.X, literal.x, +; EG-NEXT: MOV T14.Z, T3.Y, +; EG-NEXT: ASHR * T3.W, T1.W, literal.x, +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: MOV T15.X, T2.X, +; EG-NEXT: ASHR T3.Y, T1.Z, literal.x, +; EG-NEXT: MOV T0.Z, T2.W, +; EG-NEXT: ASHR T16.W, T1.Y, literal.x, +; EG-NEXT: MOV * T3.X, T1.Z, +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: ASHR T16.Y, T1.X, literal.x, +; EG-NEXT: MOV * T15.Z, T2.Y, +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: MOV T16.X, T1.X, +; EG-NEXT: MOV T3.Z, T1.W, +; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.x, +; EG-NEXT: 96(1.345247e-43), 0(0.000000e+00) +; EG-NEXT: LSHR T1.X, PV.W, literal.x, +; EG-NEXT: MOV * T16.Z, T1.Y, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-HSA-LABEL: global_sextload_v16i32_to_v16i64: +; GCN-HSA: ; %bb.0: +; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCN-HSA-NEXT: v_mov_b32_e32 v36, 0 +; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCN-HSA-NEXT: global_load_dwordx4 v[0:3], v36, s[2:3] offset:32 +; GCN-HSA-NEXT: global_load_dwordx4 v[4:7], v36, s[2:3] offset:48 +; GCN-HSA-NEXT: global_load_dwordx4 v[8:11], v36, s[2:3] offset:16 +; GCN-HSA-NEXT: global_load_dwordx4 v[12:15], v36, s[2:3] +; GCN-HSA-NEXT: s_waitcnt vmcnt(3) +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v19, 31, v3 +; GCN-HSA-NEXT: s_waitcnt vmcnt(2) +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v27, 31, v5 +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v25, 31, v4 +; GCN-HSA-NEXT: v_mov_b32_e32 v24, v4 +; GCN-HSA-NEXT: v_mov_b32_e32 v26, v5 +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v17, 31, v2 +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v23, 31, v7 +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v21, 31, v6 +; GCN-HSA-NEXT: v_mov_b32_e32 v20, v6 +; GCN-HSA-NEXT: v_mov_b32_e32 v22, v7 +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v7, 31, v1 +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v5, 31, v0 +; GCN-HSA-NEXT: v_mov_b32_e32 v4, v0 +; GCN-HSA-NEXT: v_mov_b32_e32 v6, v1 +; GCN-HSA-NEXT: v_mov_b32_e32 v16, v2 +; GCN-HSA-NEXT: v_mov_b32_e32 v18, v3 +; GCN-HSA-NEXT: s_waitcnt vmcnt(1) +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v3, 31, v11 +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v1, 31, v10 +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v31, 31, v9 +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v29, 31, v8 +; GCN-HSA-NEXT: v_mov_b32_e32 v28, v8 +; GCN-HSA-NEXT: v_mov_b32_e32 v30, v9 +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v10 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v11 +; GCN-HSA-NEXT: s_waitcnt vmcnt(0) +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v11, 31, v15 +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v9, 31, v14 +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v35, 31, v13 +; GCN-HSA-NEXT: v_ashrrev_i32_e32 v33, 31, v12 +; GCN-HSA-NEXT: v_mov_b32_e32 v32, v12 +; GCN-HSA-NEXT: v_mov_b32_e32 v34, v13 +; GCN-HSA-NEXT: v_mov_b32_e32 v8, v14 +; GCN-HSA-NEXT: v_mov_b32_e32 v10, v15 +; GCN-HSA-NEXT: global_store_dwordx4 v36, v[24:27], s[0:1] offset:96 +; GCN-HSA-NEXT: global_store_dwordx4 v36, v[20:23], s[0:1] offset:112 +; GCN-HSA-NEXT: global_store_dwordx4 v36, v[4:7], s[0:1] offset:64 +; GCN-HSA-NEXT: global_store_dwordx4 v36, v[16:19], s[0:1] offset:80 +; GCN-HSA-NEXT: global_store_dwordx4 v36, v[28:31], s[0:1] offset:32 +; GCN-HSA-NEXT: global_store_dwordx4 v36, v[0:3], s[0:1] offset:48 +; GCN-HSA-NEXT: global_store_dwordx4 v36, v[32:35], s[0:1] +; GCN-HSA-NEXT: global_store_dwordx4 v36, v[8:11], s[0:1] offset:16 +; GCN-HSA-NEXT: s_endpgm %ld = load <16 x i32>, ptr addrspace(1) %in %ext = sext <16 x i32> %ld to <16 x i64> store <16 x i64> %ext, ptr addrspace(1) %out ret void } -; FUNC-LABEL: {{^}}global_zextload_v16i32_to_v16i64 -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 - -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 - -; GCN-NOHSA: buffer_store_dwordx4 -; GCN-NOHSA: buffer_store_dwordx4 -; GCN-NOHSA: buffer_store_dwordx4 -; GCN-NOHSA: buffer_store_dwordx4 -; GCN-NOHSA: buffer_store_dwordx4 -; GCN-NOHSA: buffer_store_dwordx4 -; GCN-NOHSA: buffer_store_dwordx4 -; GCN-NOHSA: buffer_store_dwordx4 - -; GCN-HSA: {{flat|global}}_store_dwordx4 -; GCN-HSA: {{flat|global}}_store_dwordx4 -; GCN-HSA: {{flat|global}}_store_dwordx4 -; GCN-HSA: {{flat|global}}_store_dwordx4 -; GCN-HSA: {{flat|global}}_store_dwordx4 -; GCN-HSA: {{flat|global}}_store_dwordx4 -; GCN-HSA: {{flat|global}}_store_dwordx4 -; GCN-HSA: {{flat|global}}_store_dwordx4 define amdgpu_kernel void @global_zextload_v16i32_to_v16i64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-NOHSA-LABEL: global_zextload_v16i32_to_v16i64: +; SI-NOHSA: ; %bb.0: +; SI-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; SI-NOHSA-NEXT: s_mov_b32 s3, 0xf000 +; SI-NOHSA-NEXT: s_mov_b32 s2, -1 +; SI-NOHSA-NEXT: s_mov_b32 s10, s2 +; SI-NOHSA-NEXT: s_mov_b32 s11, s3 +; SI-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; SI-NOHSA-NEXT: s_mov_b32 s8, s6 +; SI-NOHSA-NEXT: s_mov_b32 s9, s7 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 offset:48 +; SI-NOHSA-NEXT: v_mov_b32_e32 v5, 0 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[8:11], off, s[8:11], 0 offset:32 +; SI-NOHSA-NEXT: v_mov_b32_e32 v7, v5 +; SI-NOHSA-NEXT: s_mov_b32 s0, s4 +; SI-NOHSA-NEXT: s_mov_b32 s1, s5 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[12:15], off, s[8:11], 0 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[16:19], off, s[8:11], 0 offset:16 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(3) +; SI-NOHSA-NEXT: v_mov_b32_e32 v4, v0 +; SI-NOHSA-NEXT: v_mov_b32_e32 v6, v1 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:96 +; SI-NOHSA-NEXT: s_waitcnt expcnt(0) +; SI-NOHSA-NEXT: v_mov_b32_e32 v4, v2 +; SI-NOHSA-NEXT: v_mov_b32_e32 v6, v3 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:112 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(4) expcnt(0) +; SI-NOHSA-NEXT: v_mov_b32_e32 v4, v8 +; SI-NOHSA-NEXT: v_mov_b32_e32 v6, v9 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:64 +; SI-NOHSA-NEXT: s_waitcnt expcnt(0) +; SI-NOHSA-NEXT: v_mov_b32_e32 v4, v10 +; SI-NOHSA-NEXT: v_mov_b32_e32 v6, v11 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:80 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(4) expcnt(0) +; SI-NOHSA-NEXT: v_mov_b32_e32 v4, v16 +; SI-NOHSA-NEXT: v_mov_b32_e32 v6, v17 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:32 +; SI-NOHSA-NEXT: s_waitcnt expcnt(0) +; SI-NOHSA-NEXT: v_mov_b32_e32 v4, v18 +; SI-NOHSA-NEXT: v_mov_b32_e32 v6, v19 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:48 +; SI-NOHSA-NEXT: s_waitcnt expcnt(0) +; SI-NOHSA-NEXT: v_mov_b32_e32 v4, v12 +; SI-NOHSA-NEXT: v_mov_b32_e32 v6, v13 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 +; SI-NOHSA-NEXT: s_waitcnt expcnt(0) +; SI-NOHSA-NEXT: v_mov_b32_e32 v4, v14 +; SI-NOHSA-NEXT: v_mov_b32_e32 v6, v15 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16 +; SI-NOHSA-NEXT: s_endpgm +; +; GCNX3-HSA-LABEL: global_zextload_v16i32_to_v16i64: +; GCNX3-HSA: ; %bb.0: +; GCNX3-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v17, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v19, v17 +; GCNX3-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 16 +; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0 +; GCNX3-HSA-NEXT: s_add_u32 s6, s2, 32 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2 +; GCNX3-HSA-NEXT: s_addc_u32 s7, s3, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3 +; GCNX3-HSA-NEXT: s_add_u32 s2, s2, 48 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s3, 0 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s2 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s7 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s6 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[8:11], v[8:9] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v13, s5 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v12, s4 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[12:15], v[12:13] +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 16 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v23, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v22, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0x60 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v25, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v24, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0x70 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v27, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v21, s1 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v26, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 64 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v20, s0 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(3) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, v0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v18, v1 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[20:21], v[16:19] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0x50 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, v2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v18, v3 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, s2 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[22:23], v[16:19] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v3, s3 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(4) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, v4 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v18, v5 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 32 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[24:25], v[16:19] +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, v6 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v18, v7 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[26:27], v[16:19] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v21, s3 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(5) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, v8 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v18, v9 +; GCNX3-HSA-NEXT: s_add_u32 s0, s0, 48 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[0:1], v[16:19] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v20, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, v10 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v18, v11 +; GCNX3-HSA-NEXT: s_addc_u32 s1, s1, 0 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[2:3], v[16:19] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s0 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(6) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, v12 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v18, v13 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[20:21], v[16:19] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s1 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, v14 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v18, v15 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[0:1], v[16:19] +; GCNX3-HSA-NEXT: s_endpgm +; +; GCNX3-NOHSA-LABEL: global_zextload_v16i32_to_v16i64: +; GCNX3-NOHSA: ; %bb.0: +; GCNX3-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GCNX3-NOHSA-NEXT: s_mov_b32 s3, 0xf000 +; GCNX3-NOHSA-NEXT: s_mov_b32 s2, -1 +; GCNX3-NOHSA-NEXT: s_mov_b32 s10, s2 +; GCNX3-NOHSA-NEXT: s_mov_b32 s11, s3 +; GCNX3-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-NOHSA-NEXT: s_mov_b32 s8, s6 +; GCNX3-NOHSA-NEXT: s_mov_b32 s9, s7 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 offset:48 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:32 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[8:11], off, s[8:11], 0 offset:16 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[12:15], off, s[8:11], 0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v17, 0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v19, v17 +; GCNX3-NOHSA-NEXT: s_mov_b32 s0, s4 +; GCNX3-NOHSA-NEXT: s_mov_b32 s1, s5 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(3) +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v16, v0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v18, v1 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:96 +; GCNX3-NOHSA-NEXT: s_nop 0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v16, v2 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v18, v3 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:112 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(4) +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v16, v4 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v18, v5 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:64 +; GCNX3-NOHSA-NEXT: s_nop 0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v16, v6 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v18, v7 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:80 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(5) +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v16, v8 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v18, v9 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:32 +; GCNX3-NOHSA-NEXT: s_nop 0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v16, v10 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v18, v11 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:48 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(6) +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v16, v12 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v18, v13 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 +; GCNX3-NOHSA-NEXT: s_nop 0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v16, v14 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v18, v15 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:16 +; GCNX3-NOHSA-NEXT: s_endpgm +; +; EG-LABEL: global_zextload_v16i32_to_v16i64: +; EG: ; %bb.0: +; EG-NEXT: ALU 0, @20, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 3 @12 +; EG-NEXT: ALU 55, @21, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T15.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T5.XYZW, T14.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T13.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T7.XYZW, T12.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T8.XYZW, T3.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T9.XYZW, T2.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T10.XYZW, T1.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T11.XYZW, T0.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: Fetch clause starting at 12: +; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 48, #1 +; EG-NEXT: VTX_READ_128 T2.XYZW, T0.X, 0, #1 +; EG-NEXT: VTX_READ_128 T3.XYZW, T0.X, 16, #1 +; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 32, #1 +; EG-NEXT: ALU clause starting at 20: +; EG-NEXT: MOV * T0.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 21: +; EG-NEXT: MOV T4.X, T1.X, +; EG-NEXT: MOV T4.Y, 0.0, +; EG-NEXT: MOV * T5.X, T1.Z, +; EG-NEXT: MOV * T5.Y, 0.0, +; EG-NEXT: MOV T6.X, T0.X, +; EG-NEXT: MOV T6.Y, 0.0, +; EG-NEXT: MOV * T7.X, T0.Z, +; EG-NEXT: MOV * T7.Y, 0.0, +; EG-NEXT: MOV T8.X, T3.X, +; EG-NEXT: MOV T8.Y, 0.0, +; EG-NEXT: MOV * T9.X, T3.Z, +; EG-NEXT: MOV * T9.Y, 0.0, +; EG-NEXT: MOV T10.X, T2.X, +; EG-NEXT: MOV T10.Y, 0.0, +; EG-NEXT: MOV * T11.X, T2.Z, +; EG-NEXT: MOV T11.Y, 0.0, +; EG-NEXT: MOV T4.Z, T1.Y, +; EG-NEXT: MOV T4.W, 0.0, +; EG-NEXT: MOV * T5.Z, T1.W, +; EG-NEXT: MOV * T5.W, 0.0, +; EG-NEXT: MOV T6.Z, T0.Y, +; EG-NEXT: MOV T6.W, 0.0, +; EG-NEXT: MOV * T7.Z, T0.W, +; EG-NEXT: MOV * T7.W, 0.0, +; EG-NEXT: MOV T8.Z, T3.Y, +; EG-NEXT: MOV T8.W, 0.0, +; EG-NEXT: MOV * T9.Z, T3.W, +; EG-NEXT: MOV * T9.W, 0.0, +; EG-NEXT: MOV T10.Z, T2.Y, +; EG-NEXT: MOV T10.W, 0.0, +; EG-NEXT: MOV * T11.Z, T2.W, +; EG-NEXT: MOV T11.W, 0.0, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T0.X, PS, literal.x, +; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, +; EG-NEXT: 48(6.726233e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T2.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44) +; EG-NEXT: LSHR T3.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 80(1.121039e-43) +; EG-NEXT: LSHR T12.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 64(8.968310e-44) +; EG-NEXT: LSHR T13.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 112(1.569454e-43) +; EG-NEXT: LSHR T14.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 96(1.345247e-43) +; EG-NEXT: LSHR * T15.X, PV.W, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-HSA-LABEL: global_zextload_v16i32_to_v16i64: +; GCN-HSA: ; %bb.0: +; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCN-HSA-NEXT: v_mov_b32_e32 v1, 0 +; GCN-HSA-NEXT: v_mov_b32_e32 v3, v1 +; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCN-HSA-NEXT: global_load_dwordx4 v[4:7], v1, s[2:3] offset:48 +; GCN-HSA-NEXT: global_load_dwordx4 v[8:11], v1, s[2:3] offset:32 +; GCN-HSA-NEXT: global_load_dwordx4 v[12:15], v1, s[2:3] offset:16 +; GCN-HSA-NEXT: global_load_dwordx4 v[16:19], v1, s[2:3] +; GCN-HSA-NEXT: s_waitcnt vmcnt(3) +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v4 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v5 +; GCN-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] offset:96 +; GCN-HSA-NEXT: s_nop 0 +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v6 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v7 +; GCN-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] offset:112 +; GCN-HSA-NEXT: s_waitcnt vmcnt(4) +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v8 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v9 +; GCN-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] offset:64 +; GCN-HSA-NEXT: s_nop 0 +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v10 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v11 +; GCN-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] offset:80 +; GCN-HSA-NEXT: s_waitcnt vmcnt(5) +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v12 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v13 +; GCN-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] offset:32 +; GCN-HSA-NEXT: s_nop 0 +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v14 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v15 +; GCN-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] offset:48 +; GCN-HSA-NEXT: s_waitcnt vmcnt(6) +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v16 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v17 +; GCN-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] +; GCN-HSA-NEXT: s_nop 0 +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v18 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v19 +; GCN-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] offset:16 +; GCN-HSA-NEXT: s_endpgm %ld = load <16 x i32>, ptr addrspace(1) %in %ext = zext <16 x i32> %ld to <16 x i64> store <16 x i64> %ext, ptr addrspace(1) %out ret void } -; FUNC-LABEL: {{^}}global_sextload_v32i32_to_v32i64: - -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA-DAG: buffer_load_dwordx4 - -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 - -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 -; GCN-DAG: v_ashrrev_i32 - -; GCN-NOHSA: buffer_store_dwordx4 -; GCN-NOHSA: buffer_store_dwordx4 -; GCN-NOHSA: buffer_store_dwordx4 -; GCN-NOHSA: buffer_store_dwordx4 - -; GCN-NOHSA: buffer_store_dwordx4 -; GCN-NOHSA: buffer_store_dwordx4 -; GCN-NOHSA: buffer_store_dwordx4 -; GCN-NOHSA: buffer_store_dwordx4 - -; GCN-NOHSA: buffer_store_dwordx4 -; GCN-NOHSA: buffer_store_dwordx4 -; GCN-NOHSA: buffer_store_dwordx4 -; GCN-NOHSA: buffer_store_dwordx4 - -; GCN-NOHSA: buffer_store_dwordx4 -; GCN-NOHSA: buffer_store_dwordx4 -; GCN-NOHSA: buffer_store_dwordx4 -; GCN-NOHSA: buffer_store_dwordx4 - -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 - -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 - -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 - -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 - define amdgpu_kernel void @global_sextload_v32i32_to_v32i64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-NOHSA-LABEL: global_sextload_v32i32_to_v32i64: +; SI-NOHSA: ; %bb.0: +; SI-NOHSA-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0 +; SI-NOHSA-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1 +; SI-NOHSA-NEXT: s_mov_b32 s14, -1 +; SI-NOHSA-NEXT: s_mov_b32 s15, 0xe8f000 +; SI-NOHSA-NEXT: s_add_u32 s12, s12, s3 +; SI-NOHSA-NEXT: s_addc_u32 s13, s13, 0 +; SI-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; SI-NOHSA-NEXT: s_mov_b32 s3, 0xf000 +; SI-NOHSA-NEXT: s_mov_b32 s2, -1 +; SI-NOHSA-NEXT: s_mov_b32 s10, s2 +; SI-NOHSA-NEXT: s_mov_b32 s11, s3 +; SI-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; SI-NOHSA-NEXT: s_mov_b32 s8, s6 +; SI-NOHSA-NEXT: s_mov_b32 s9, s7 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[28:31], off, s[8:11], 0 offset:96 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[12:15], off, s[8:11], 0 offset:112 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:80 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 offset:64 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[16:19], off, s[8:11], 0 offset:48 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[20:23], off, s[8:11], 0 offset:32 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[24:27], off, s[8:11], 0 offset:16 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[8:11], off, s[8:11], 0 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(7) +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v47, 31, v31 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v45, 31, v30 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(6) +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v39, 31, v15 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v37, 31, v14 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v43, 31, v13 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v41, 31, v12 +; SI-NOHSA-NEXT: v_mov_b32_e32 v40, v12 +; SI-NOHSA-NEXT: v_mov_b32_e32 v42, v13 +; SI-NOHSA-NEXT: v_mov_b32_e32 v36, v14 +; SI-NOHSA-NEXT: v_mov_b32_e32 v38, v15 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v35, 31, v29 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v33, 31, v28 +; SI-NOHSA-NEXT: v_mov_b32_e32 v32, v28 +; SI-NOHSA-NEXT: v_mov_b32_e32 v34, v29 +; SI-NOHSA-NEXT: v_mov_b32_e32 v44, v30 +; SI-NOHSA-NEXT: v_mov_b32_e32 v46, v31 +; SI-NOHSA-NEXT: buffer_store_dword v44, off, s[12:15], 0 offset:4 ; 4-byte Folded Spill +; SI-NOHSA-NEXT: s_waitcnt vmcnt(0) +; SI-NOHSA-NEXT: buffer_store_dword v45, off, s[12:15], 0 offset:8 ; 4-byte Folded Spill +; SI-NOHSA-NEXT: buffer_store_dword v46, off, s[12:15], 0 offset:12 ; 4-byte Folded Spill +; SI-NOHSA-NEXT: buffer_store_dword v47, off, s[12:15], 0 offset:16 ; 4-byte Folded Spill +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v15, 31, v7 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v13, 31, v6 +; SI-NOHSA-NEXT: s_waitcnt expcnt(0) +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v47, 31, v5 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v45, 31, v4 +; SI-NOHSA-NEXT: v_mov_b32_e32 v44, v4 +; SI-NOHSA-NEXT: v_mov_b32_e32 v46, v5 +; SI-NOHSA-NEXT: v_mov_b32_e32 v12, v6 +; SI-NOHSA-NEXT: v_mov_b32_e32 v14, v7 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v7, 31, v3 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v5, 31, v2 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v51, 31, v1 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v49, 31, v0 +; SI-NOHSA-NEXT: v_mov_b32_e32 v48, v0 +; SI-NOHSA-NEXT: v_mov_b32_e32 v50, v1 +; SI-NOHSA-NEXT: v_mov_b32_e32 v4, v2 +; SI-NOHSA-NEXT: v_mov_b32_e32 v6, v3 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v3, 31, v19 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v1, 31, v18 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v55, 31, v17 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v53, 31, v16 +; SI-NOHSA-NEXT: v_mov_b32_e32 v52, v16 +; SI-NOHSA-NEXT: v_mov_b32_e32 v54, v17 +; SI-NOHSA-NEXT: v_mov_b32_e32 v0, v18 +; SI-NOHSA-NEXT: v_mov_b32_e32 v2, v19 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v19, 31, v23 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v17, 31, v22 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v59, 31, v21 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v57, 31, v20 +; SI-NOHSA-NEXT: v_mov_b32_e32 v56, v20 +; SI-NOHSA-NEXT: v_mov_b32_e32 v58, v21 +; SI-NOHSA-NEXT: v_mov_b32_e32 v16, v22 +; SI-NOHSA-NEXT: v_mov_b32_e32 v18, v23 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v23, 31, v27 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v21, 31, v26 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v63, 31, v25 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v61, 31, v24 +; SI-NOHSA-NEXT: v_mov_b32_e32 v60, v24 +; SI-NOHSA-NEXT: v_mov_b32_e32 v62, v25 +; SI-NOHSA-NEXT: v_mov_b32_e32 v20, v26 +; SI-NOHSA-NEXT: v_mov_b32_e32 v22, v27 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v27, 31, v11 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v25, 31, v10 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v31, 31, v9 +; SI-NOHSA-NEXT: v_ashrrev_i32_e32 v29, 31, v8 +; SI-NOHSA-NEXT: v_mov_b32_e32 v28, v8 +; SI-NOHSA-NEXT: v_mov_b32_e32 v30, v9 +; SI-NOHSA-NEXT: v_mov_b32_e32 v24, v10 +; SI-NOHSA-NEXT: v_mov_b32_e32 v26, v11 +; SI-NOHSA-NEXT: s_mov_b32 s0, s4 +; SI-NOHSA-NEXT: s_mov_b32 s1, s5 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[40:43], off, s[0:3], 0 offset:224 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[36:39], off, s[0:3], 0 offset:240 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[32:35], off, s[0:3], 0 offset:192 +; SI-NOHSA-NEXT: buffer_load_dword v8, off, s[12:15], 0 offset:4 ; 4-byte Folded Reload +; SI-NOHSA-NEXT: buffer_load_dword v9, off, s[12:15], 0 offset:8 ; 4-byte Folded Reload +; SI-NOHSA-NEXT: buffer_load_dword v10, off, s[12:15], 0 offset:12 ; 4-byte Folded Reload +; SI-NOHSA-NEXT: buffer_load_dword v11, off, s[12:15], 0 offset:16 ; 4-byte Folded Reload +; SI-NOHSA-NEXT: s_waitcnt vmcnt(0) +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:208 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[44:47], off, s[0:3], 0 offset:160 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:176 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[48:51], off, s[0:3], 0 offset:128 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:144 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[52:55], off, s[0:3], 0 offset:96 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:112 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[56:59], off, s[0:3], 0 offset:64 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:80 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[60:63], off, s[0:3], 0 offset:32 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[20:23], off, s[0:3], 0 offset:48 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[28:31], off, s[0:3], 0 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[24:27], off, s[0:3], 0 offset:16 +; SI-NOHSA-NEXT: s_endpgm +; +; GCNX3-HSA-LABEL: global_sextload_v32i32_to_v32i64: +; GCNX3-HSA: ; %bb.0: +; GCNX3-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCNX3-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[28:31], v[0:1] +; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 0x70 +; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s4 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s5 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[24:27], v[0:1] +; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 0x60 +; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s4 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s5 +; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 0x50 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[20:23], v[0:1] +; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s4 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s5 +; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 64 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[12:15], v[0:1] +; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s4 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s5 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[4:7], v[0:1] +; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 48 +; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s5 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s4 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[16:19], v[8:9] +; GCNX3-HSA-NEXT: s_add_u32 s6, s2, 32 +; GCNX3-HSA-NEXT: s_addc_u32 s7, s3, 0 +; GCNX3-HSA-NEXT: s_add_u32 s2, s2, 16 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s3, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s7 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s6 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[8:11], v[8:9] +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 16 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v37, s1 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v36, s0 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(7) +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v35, 31, v29 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v33, 31, v28 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v32, v28 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v34, v29 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v29, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v28, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0xe0 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[36:37], v[32:35] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v37, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v36, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0xf0 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v35, 31, v31 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v33, 31, v30 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v32, v30 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v34, v31 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[28:29], v[32:35] +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(8) +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v31, 31, v25 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v33, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v32, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0xc0 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v35, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v34, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0xd0 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v29, 31, v24 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v28, v24 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v30, v25 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[36:37], v[28:31] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v37, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v36, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0xa0 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v31, 31, v27 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v29, 31, v26 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v28, v26 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v30, v27 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[32:33], v[28:31] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v33, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v32, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0xb0 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v39, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v38, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0x80 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(9) +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v27, 31, v21 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v25, 31, v20 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v24, v20 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v26, v21 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v31, 31, v23 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v29, 31, v22 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v28, v22 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v30, v23 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[34:35], v[24:27] +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[36:37], v[28:31] +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(10) +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v23, 31, v15 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v21, 31, v14 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v27, 31, v13 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v25, 31, v12 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v24, v12 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v26, v13 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v20, v14 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v22, v15 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(9) +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v15, 31, v5 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v13, 31, v4 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v12, v4 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v14, v5 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0x90 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[32:33], v[24:27] +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[38:39], v[20:23] +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[4:5], v[12:15] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0x60 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v26, 31, v7 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v24, 31, v6 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v23, v6 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v25, v7 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[4:5], v[23:26] +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(12) +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v5, 31, v16 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, v16 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v15, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0x70 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v7, 31, v17 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v6, v17 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[15:16], v[4:7] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v15, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 64 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v26, 31, v19 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v24, 31, v18 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v23, v18 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v25, v19 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[15:16], v[23:26] +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(12) +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v18, 31, v9 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v16, 31, v8 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v15, v8 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v17, v9 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0x50 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[8:9], v[15:18] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 32 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v14, 31, v1 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v12, 31, v0 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v7, 31, v11 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v6, v11 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v11, v0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v13, v1 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3 +; GCNX3-HSA-NEXT: s_add_u32 s0, s0, 48 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[0:1], v[11:14] +; GCNX3-HSA-NEXT: s_addc_u32 s1, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s0 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v22, 31, v3 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v20, 31, v2 +; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v5, 31, v10 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, v10 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v19, v2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v21, v3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s1 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[8:9], v[4:7] +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[0:1], v[19:22] +; GCNX3-HSA-NEXT: s_endpgm +; +; GCNX3-NOHSA-LABEL: global_sextload_v32i32_to_v32i64: +; GCNX3-NOHSA: ; %bb.0: +; GCNX3-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GCNX3-NOHSA-NEXT: s_mov_b32 s3, 0xf000 +; GCNX3-NOHSA-NEXT: s_mov_b32 s2, -1 +; GCNX3-NOHSA-NEXT: s_mov_b32 s10, s2 +; GCNX3-NOHSA-NEXT: s_mov_b32 s11, s3 +; GCNX3-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-NOHSA-NEXT: s_mov_b32 s8, s6 +; GCNX3-NOHSA-NEXT: s_mov_b32 s9, s7 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[8:11], off, s[8:11], 0 offset:96 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[12:15], off, s[8:11], 0 offset:112 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:80 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 offset:64 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[16:19], off, s[8:11], 0 offset:48 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[20:23], off, s[8:11], 0 offset:32 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[24:27], off, s[8:11], 0 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[28:31], off, s[8:11], 0 offset:16 +; GCNX3-NOHSA-NEXT: s_mov_b32 s0, s4 +; GCNX3-NOHSA-NEXT: s_mov_b32 s1, s5 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(7) +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v35, 31, v11 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v33, 31, v10 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(6) +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v39, 31, v15 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v37, 31, v14 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v43, 31, v13 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v41, 31, v12 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v40, v12 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v42, v13 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v36, v14 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v38, v15 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v15, 31, v9 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v13, 31, v8 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v12, v8 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v14, v9 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v32, v10 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v34, v11 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(5) +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v11, 31, v7 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v9, 31, v6 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v47, 31, v5 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v45, 31, v4 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v44, v4 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v46, v5 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v8, v6 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v10, v7 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(4) +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v7, 31, v3 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v5, 31, v2 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v4, v2 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v6, v3 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(3) +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v3, 31, v19 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v2, v19 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(2) +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v19, 31, v23 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v51, 31, v1 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v49, 31, v0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v48, v0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v50, v1 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v1, 31, v18 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v55, 31, v17 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v53, 31, v16 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v52, v16 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v54, v17 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v0, v18 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v17, 31, v22 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v59, 31, v21 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v57, 31, v20 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v56, v20 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v58, v21 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v16, v22 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v18, v23 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(1) +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v22, 31, v27 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v20, 31, v26 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[40:43], off, s[0:3], 0 offset:224 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[36:39], off, s[0:3], 0 offset:240 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v42, 31, v25 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v40, 31, v24 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(2) +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v38, 31, v31 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v36, 31, v30 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:192 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v37, v31 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v15, 31, v29 +; GCNX3-NOHSA-NEXT: v_ashrrev_i32_e32 v13, 31, v28 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v12, v28 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v14, v29 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[32:35], off, s[0:3], 0 offset:208 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[44:47], off, s[0:3], 0 offset:160 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:176 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[48:51], off, s[0:3], 0 offset:128 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:144 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[52:55], off, s[0:3], 0 offset:96 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:112 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[56:59], off, s[0:3], 0 offset:64 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:80 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:32 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v35, v30 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v39, v24 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v41, v25 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v19, v26 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v21, v27 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[35:38], off, s[0:3], 0 offset:48 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[39:42], off, s[0:3], 0 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[19:22], off, s[0:3], 0 offset:16 +; GCNX3-NOHSA-NEXT: s_endpgm +; +; EG-LABEL: global_sextload_v32i32_to_v32i64: +; EG: ; %bb.0: +; EG-NEXT: ALU 33, @36, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 7 @20 +; EG-NEXT: ALU 96, @70, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T32.XYZW, T12.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T14.XYZW, T23.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T31.XYZW, T21.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T15.XYZW, T20.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T30.XYZW, T19.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T16.XYZW, T10.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T29.XYZW, T9.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T17.XYZW, T8.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T28.XYZW, T7.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T18.XYZW, T6.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T27.XYZW, T5.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T11.XYZW, T4.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T26.XYZW, T3.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T25.XYZW, T2.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T24.XYZW, T1.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T22.XYZW, T0.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: Fetch clause starting at 20: +; EG-NEXT: VTX_READ_128 T12.XYZW, T11.X, 112, #1 +; EG-NEXT: VTX_READ_128 T13.XYZW, T11.X, 96, #1 +; EG-NEXT: VTX_READ_128 T14.XYZW, T11.X, 80, #1 +; EG-NEXT: VTX_READ_128 T15.XYZW, T11.X, 64, #1 +; EG-NEXT: VTX_READ_128 T16.XYZW, T11.X, 48, #1 +; EG-NEXT: VTX_READ_128 T17.XYZW, T11.X, 32, #1 +; EG-NEXT: VTX_READ_128 T18.XYZW, T11.X, 16, #1 +; EG-NEXT: VTX_READ_128 T11.XYZW, T11.X, 0, #1 +; EG-NEXT: ALU clause starting at 36: +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T0.X, PV.W, literal.x, +; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, +; EG-NEXT: 48(6.726233e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T2.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44) +; EG-NEXT: LSHR T3.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 80(1.121039e-43) +; EG-NEXT: LSHR T4.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 64(8.968310e-44) +; EG-NEXT: LSHR T5.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 112(1.569454e-43) +; EG-NEXT: LSHR T6.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 96(1.345247e-43) +; EG-NEXT: LSHR T7.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 144(2.017870e-43) +; EG-NEXT: LSHR T8.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 128(1.793662e-43) +; EG-NEXT: LSHR T9.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 176(2.466285e-43) +; EG-NEXT: LSHR T10.X, PV.W, literal.x, +; EG-NEXT: MOV * T11.X, KC0[2].Z, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: ALU clause starting at 70: +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, +; EG-NEXT: 160(2.242078e-43), 0(0.000000e+00) +; EG-NEXT: LSHR T19.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 208(2.914701e-43) +; EG-NEXT: LSHR T20.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 192(2.690493e-43) +; EG-NEXT: LSHR T21.X, PV.W, literal.x, +; EG-NEXT: ADD_INT T0.W, KC0[2].Y, literal.y, +; EG-NEXT: ASHR * T22.W, T11.W, literal.z, +; EG-NEXT: 2(2.802597e-45), 240(3.363116e-43) +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T23.X, PV.W, literal.x, +; EG-NEXT: ASHR T22.Y, T11.Z, literal.y, +; EG-NEXT: ASHR T24.W, T11.Y, literal.y, +; EG-NEXT: MOV * T22.X, T11.Z, +; EG-NEXT: 2(2.802597e-45), 31(4.344025e-44) +; EG-NEXT: ASHR T24.Y, T11.X, literal.x, +; EG-NEXT: ASHR * T25.W, T18.W, literal.x, +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: MOV T24.X, T11.X, +; EG-NEXT: ASHR T25.Y, T18.Z, literal.x, +; EG-NEXT: MOV T22.Z, T11.W, +; EG-NEXT: ASHR T26.W, T18.Y, literal.x, +; EG-NEXT: MOV * T25.X, T18.Z, +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: ASHR T26.Y, T18.X, literal.x, +; EG-NEXT: MOV T24.Z, T11.Y, +; EG-NEXT: ASHR * T11.W, T17.W, literal.x, +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: MOV T26.X, T18.X, +; EG-NEXT: ASHR T11.Y, T17.Z, literal.x, +; EG-NEXT: MOV T25.Z, T18.W, +; EG-NEXT: ASHR T27.W, T17.Y, literal.x, +; EG-NEXT: MOV * T11.X, T17.Z, +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: ASHR T27.Y, T17.X, literal.x, +; EG-NEXT: MOV T26.Z, T18.Y, +; EG-NEXT: ASHR * T18.W, T16.W, literal.x, +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: MOV T27.X, T17.X, +; EG-NEXT: ASHR T18.Y, T16.Z, literal.x, +; EG-NEXT: MOV T11.Z, T17.W, +; EG-NEXT: ASHR T28.W, T16.Y, literal.x, +; EG-NEXT: MOV * T18.X, T16.Z, +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: ASHR T28.Y, T16.X, literal.x, +; EG-NEXT: MOV T27.Z, T17.Y, +; EG-NEXT: ASHR * T17.W, T15.W, literal.x, +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: MOV T28.X, T16.X, +; EG-NEXT: ASHR T17.Y, T15.Z, literal.x, +; EG-NEXT: MOV T18.Z, T16.W, +; EG-NEXT: ASHR T29.W, T15.Y, literal.x, +; EG-NEXT: MOV * T17.X, T15.Z, +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: ASHR T29.Y, T15.X, literal.x, +; EG-NEXT: MOV T28.Z, T16.Y, +; EG-NEXT: ASHR * T16.W, T14.W, literal.x, +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: MOV T29.X, T15.X, +; EG-NEXT: ASHR T16.Y, T14.Z, literal.x, +; EG-NEXT: MOV T17.Z, T15.W, +; EG-NEXT: ASHR T30.W, T14.Y, literal.x, +; EG-NEXT: MOV * T16.X, T14.Z, +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: ASHR T30.Y, T14.X, literal.x, +; EG-NEXT: MOV T29.Z, T15.Y, +; EG-NEXT: ASHR * T15.W, T13.W, literal.x, +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: MOV T30.X, T14.X, +; EG-NEXT: ASHR T15.Y, T13.Z, literal.x, +; EG-NEXT: MOV T16.Z, T14.W, +; EG-NEXT: ASHR T31.W, T13.Y, literal.x, +; EG-NEXT: MOV * T15.X, T13.Z, +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: ASHR T31.Y, T13.X, literal.x, +; EG-NEXT: MOV T30.Z, T14.Y, +; EG-NEXT: ASHR * T14.W, T12.W, literal.x, +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: MOV T31.X, T13.X, +; EG-NEXT: ASHR T14.Y, T12.Z, literal.x, +; EG-NEXT: MOV T15.Z, T13.W, +; EG-NEXT: ASHR T32.W, T12.Y, literal.x, +; EG-NEXT: MOV * T14.X, T12.Z, +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: ASHR T32.Y, T12.X, literal.x, +; EG-NEXT: MOV * T31.Z, T13.Y, +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; EG-NEXT: MOV T32.X, T12.X, +; EG-NEXT: MOV T14.Z, T12.W, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, +; EG-NEXT: 224(3.138909e-43), 0(0.000000e+00) +; EG-NEXT: LSHR T12.X, PV.W, literal.x, +; EG-NEXT: MOV * T32.Z, T12.Y, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-GFX900-HSA-LABEL: global_sextload_v32i32_to_v32i64: +; GCN-GFX900-HSA: ; %bb.0: +; GCN-GFX900-HSA-NEXT: s_mov_b64 s[10:11], s[2:3] +; GCN-GFX900-HSA-NEXT: s_mov_b64 s[8:9], s[0:1] +; GCN-GFX900-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v8, 0 +; GCN-GFX900-HSA-NEXT: s_add_u32 s8, s8, s7 +; GCN-GFX900-HSA-NEXT: s_addc_u32 s9, s9, 0 +; GCN-GFX900-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCN-GFX900-HSA-NEXT: global_load_dwordx4 v[0:3], v8, s[2:3] offset:96 +; GCN-GFX900-HSA-NEXT: global_load_dwordx4 v[4:7], v8, s[2:3] offset:112 +; GCN-GFX900-HSA-NEXT: global_load_dwordx4 v[9:12], v8, s[2:3] offset:80 +; GCN-GFX900-HSA-NEXT: global_load_dwordx4 v[13:16], v8, s[2:3] offset:64 +; GCN-GFX900-HSA-NEXT: global_load_dwordx4 v[17:20], v8, s[2:3] offset:48 +; GCN-GFX900-HSA-NEXT: global_load_dwordx4 v[21:24], v8, s[2:3] offset:32 +; GCN-GFX900-HSA-NEXT: s_waitcnt vmcnt(5) +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v28, 31, v3 +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v26, 31, v2 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v25, v2 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v27, v3 +; GCN-GFX900-HSA-NEXT: s_waitcnt vmcnt(4) +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v32, 31, v7 +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v30, 31, v6 +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v36, 31, v5 +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v34, 31, v4 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v33, v4 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v35, v5 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v29, v6 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v31, v7 +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v7, 31, v1 +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v5, 31, v0 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v4, v0 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v6, v1 +; GCN-GFX900-HSA-NEXT: buffer_store_dword v25, off, s[8:11], 0 offset:4 ; 4-byte Folded Spill +; GCN-GFX900-HSA-NEXT: s_waitcnt vmcnt(0) +; GCN-GFX900-HSA-NEXT: buffer_store_dword v26, off, s[8:11], 0 offset:8 ; 4-byte Folded Spill +; GCN-GFX900-HSA-NEXT: buffer_store_dword v27, off, s[8:11], 0 offset:12 ; 4-byte Folded Spill +; GCN-GFX900-HSA-NEXT: buffer_store_dword v28, off, s[8:11], 0 offset:16 ; 4-byte Folded Spill +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v28, 31, v12 +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v26, 31, v11 +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v40, 31, v10 +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v38, 31, v9 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v37, v9 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v39, v10 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v25, v11 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v27, v12 +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v12, 31, v16 +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v10, 31, v15 +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v44, 31, v14 +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v42, 31, v13 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v41, v13 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v43, v14 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v9, v15 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v11, v16 +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v16, 31, v20 +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v14, 31, v19 +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v48, 31, v18 +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v46, 31, v17 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v45, v17 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v47, v18 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v13, v19 +; GCN-GFX900-HSA-NEXT: global_load_dwordx4 v[49:52], v8, s[2:3] offset:16 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v15, v20 +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v20, 31, v24 +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v18, 31, v23 +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v56, 31, v22 +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v54, 31, v21 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v53, v21 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v55, v22 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v17, v23 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v19, v24 +; GCN-GFX900-HSA-NEXT: global_load_dwordx4 v[21:24], v8, s[2:3] +; GCN-GFX900-HSA-NEXT: s_nop 0 +; GCN-GFX900-HSA-NEXT: global_store_dwordx4 v8, v[33:36], s[0:1] offset:224 +; GCN-GFX900-HSA-NEXT: global_store_dwordx4 v8, v[29:32], s[0:1] offset:240 +; GCN-GFX900-HSA-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1] offset:192 +; GCN-GFX900-HSA-NEXT: buffer_load_dword v32, off, s[8:11], 0 offset:4 ; 4-byte Folded Reload +; GCN-GFX900-HSA-NEXT: s_nop 0 +; GCN-GFX900-HSA-NEXT: buffer_load_dword v33, off, s[8:11], 0 offset:8 ; 4-byte Folded Reload +; GCN-GFX900-HSA-NEXT: buffer_load_dword v34, off, s[8:11], 0 offset:12 ; 4-byte Folded Reload +; GCN-GFX900-HSA-NEXT: buffer_load_dword v35, off, s[8:11], 0 offset:16 ; 4-byte Folded Reload +; GCN-GFX900-HSA-NEXT: s_waitcnt vmcnt(8) +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v60, 31, v52 +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v58, 31, v51 +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v3, 31, v50 +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v1, 31, v49 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v0, v49 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v2, v50 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v57, v51 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v59, v52 +; GCN-GFX900-HSA-NEXT: s_waitcnt vmcnt(7) +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v31, 31, v24 +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v29, 31, v23 +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v7, 31, v22 +; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v5, 31, v21 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v4, v21 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v6, v22 +; GCN-GFX900-HSA-NEXT: s_waitcnt vmcnt(0) +; GCN-GFX900-HSA-NEXT: global_store_dwordx4 v8, v[32:35], s[0:1] offset:208 +; GCN-GFX900-HSA-NEXT: global_store_dwordx4 v8, v[37:40], s[0:1] offset:160 +; GCN-GFX900-HSA-NEXT: global_store_dwordx4 v8, v[25:28], s[0:1] offset:176 +; GCN-GFX900-HSA-NEXT: global_store_dwordx4 v8, v[41:44], s[0:1] offset:128 +; GCN-GFX900-HSA-NEXT: global_store_dwordx4 v8, v[9:12], s[0:1] offset:144 +; GCN-GFX900-HSA-NEXT: global_store_dwordx4 v8, v[45:48], s[0:1] offset:96 +; GCN-GFX900-HSA-NEXT: global_store_dwordx4 v8, v[13:16], s[0:1] offset:112 +; GCN-GFX900-HSA-NEXT: global_store_dwordx4 v8, v[53:56], s[0:1] offset:64 +; GCN-GFX900-HSA-NEXT: global_store_dwordx4 v8, v[17:20], s[0:1] offset:80 +; GCN-GFX900-HSA-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1] offset:32 +; GCN-GFX900-HSA-NEXT: global_store_dwordx4 v8, v[57:60], s[0:1] offset:48 +; GCN-GFX900-HSA-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1] +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v28, v23 +; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v30, v24 +; GCN-GFX900-HSA-NEXT: global_store_dwordx4 v8, v[28:31], s[0:1] offset:16 +; GCN-GFX900-HSA-NEXT: s_endpgm +; +; GCN-GFX908-HSA-LABEL: global_sextload_v32i32_to_v32i64: +; GCN-GFX908-HSA: ; %bb.0: +; GCN-GFX908-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v8, 0 +; GCN-GFX908-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCN-GFX908-HSA-NEXT: global_load_dwordx4 v[0:3], v8, s[2:3] offset:96 +; GCN-GFX908-HSA-NEXT: global_load_dwordx4 v[4:7], v8, s[2:3] offset:112 +; GCN-GFX908-HSA-NEXT: global_load_dwordx4 v[9:12], v8, s[2:3] offset:80 +; GCN-GFX908-HSA-NEXT: global_load_dwordx4 v[13:16], v8, s[2:3] offset:64 +; GCN-GFX908-HSA-NEXT: global_load_dwordx4 v[17:20], v8, s[2:3] offset:48 +; GCN-GFX908-HSA-NEXT: global_load_dwordx4 v[21:24], v8, s[2:3] offset:32 +; GCN-GFX908-HSA-NEXT: global_load_dwordx4 v[49:52], v8, s[2:3] offset:16 +; GCN-GFX908-HSA-NEXT: s_waitcnt vmcnt(6) +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v25, v2 +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v28, 31, v3 +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v26, 31, v2 +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v27, v3 +; GCN-GFX908-HSA-NEXT: v_accvgpr_write_b32 a0, v25 +; GCN-GFX908-HSA-NEXT: v_accvgpr_write_b32 a1, v26 +; GCN-GFX908-HSA-NEXT: v_accvgpr_write_b32 a2, v27 +; GCN-GFX908-HSA-NEXT: v_accvgpr_write_b32 a3, v28 +; GCN-GFX908-HSA-NEXT: s_waitcnt vmcnt(4) +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v28, 31, v12 +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v26, 31, v11 +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v40, 31, v10 +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v38, 31, v9 +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v37, v9 +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v39, v10 +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v25, v11 +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v27, v12 +; GCN-GFX908-HSA-NEXT: s_waitcnt vmcnt(3) +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v12, 31, v16 +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v10, 31, v15 +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v44, 31, v14 +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v42, 31, v13 +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v41, v13 +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v43, v14 +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v9, v15 +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v11, v16 +; GCN-GFX908-HSA-NEXT: s_waitcnt vmcnt(2) +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v16, 31, v20 +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v14, 31, v19 +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v48, 31, v18 +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v46, 31, v17 +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v45, v17 +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v47, v18 +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v13, v19 +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v15, v20 +; GCN-GFX908-HSA-NEXT: s_waitcnt vmcnt(1) +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v20, 31, v24 +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v18, 31, v23 +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v56, 31, v22 +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v54, 31, v21 +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v53, v21 +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v55, v22 +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v17, v23 +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v19, v24 +; GCN-GFX908-HSA-NEXT: global_load_dwordx4 v[21:24], v8, s[2:3] +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v32, 31, v7 +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v36, 31, v5 +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v34, 31, v4 +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v33, v4 +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v35, v5 +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v30, 31, v6 +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v29, v6 +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v31, v7 +; GCN-GFX908-HSA-NEXT: global_store_dwordx4 v8, v[33:36], s[0:1] offset:224 +; GCN-GFX908-HSA-NEXT: global_store_dwordx4 v8, v[29:32], s[0:1] offset:240 +; GCN-GFX908-HSA-NEXT: v_accvgpr_read_b32 v35, a3 +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v7, 31, v1 +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v5, 31, v0 +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v4, v0 +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v6, v1 +; GCN-GFX908-HSA-NEXT: v_accvgpr_read_b32 v34, a2 +; GCN-GFX908-HSA-NEXT: v_accvgpr_read_b32 v33, a1 +; GCN-GFX908-HSA-NEXT: v_accvgpr_read_b32 v32, a0 +; GCN-GFX908-HSA-NEXT: s_waitcnt vmcnt(3) +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v60, 31, v52 +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v58, 31, v51 +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v3, 31, v50 +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v1, 31, v49 +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v0, v49 +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v2, v50 +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v57, v51 +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v59, v52 +; GCN-GFX908-HSA-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1] offset:192 +; GCN-GFX908-HSA-NEXT: s_waitcnt vmcnt(3) +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v31, 31, v24 +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v29, 31, v23 +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v7, 31, v22 +; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v5, 31, v21 +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v4, v21 +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v6, v22 +; GCN-GFX908-HSA-NEXT: global_store_dwordx4 v8, v[32:35], s[0:1] offset:208 +; GCN-GFX908-HSA-NEXT: global_store_dwordx4 v8, v[37:40], s[0:1] offset:160 +; GCN-GFX908-HSA-NEXT: global_store_dwordx4 v8, v[25:28], s[0:1] offset:176 +; GCN-GFX908-HSA-NEXT: global_store_dwordx4 v8, v[41:44], s[0:1] offset:128 +; GCN-GFX908-HSA-NEXT: global_store_dwordx4 v8, v[9:12], s[0:1] offset:144 +; GCN-GFX908-HSA-NEXT: global_store_dwordx4 v8, v[45:48], s[0:1] offset:96 +; GCN-GFX908-HSA-NEXT: global_store_dwordx4 v8, v[13:16], s[0:1] offset:112 +; GCN-GFX908-HSA-NEXT: global_store_dwordx4 v8, v[53:56], s[0:1] offset:64 +; GCN-GFX908-HSA-NEXT: global_store_dwordx4 v8, v[17:20], s[0:1] offset:80 +; GCN-GFX908-HSA-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1] offset:32 +; GCN-GFX908-HSA-NEXT: global_store_dwordx4 v8, v[57:60], s[0:1] offset:48 +; GCN-GFX908-HSA-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1] +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v28, v23 +; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v30, v24 +; GCN-GFX908-HSA-NEXT: global_store_dwordx4 v8, v[28:31], s[0:1] offset:16 +; GCN-GFX908-HSA-NEXT: s_endpgm %ld = load <32 x i32>, ptr addrspace(1) %in %ext = sext <32 x i32> %ld to <32 x i64> store <32 x i64> %ext, ptr addrspace(1) %out ret void } -; FUNC-LABEL: {{^}}global_zextload_v32i32_to_v32i64: -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 - -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 - - -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-NOHSA-DAG: buffer_store_dwordx4 - -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-NOHSA-DAG: buffer_store_dwordx4 - -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-NOHSA-DAG: buffer_store_dwordx4 - -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-NOHSA-DAG: buffer_store_dwordx4 - - -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 - -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 - -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 - -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 define amdgpu_kernel void @global_zextload_v32i32_to_v32i64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-NOHSA-LABEL: global_zextload_v32i32_to_v32i64: +; SI-NOHSA: ; %bb.0: +; SI-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; SI-NOHSA-NEXT: s_mov_b32 s3, 0xf000 +; SI-NOHSA-NEXT: s_mov_b32 s2, -1 +; SI-NOHSA-NEXT: v_mov_b32_e32 v1, 0 +; SI-NOHSA-NEXT: s_mov_b32 s10, s2 +; SI-NOHSA-NEXT: s_mov_b32 s11, s3 +; SI-NOHSA-NEXT: v_mov_b32_e32 v3, v1 +; SI-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; SI-NOHSA-NEXT: s_mov_b32 s8, s6 +; SI-NOHSA-NEXT: s_mov_b32 s9, s7 +; SI-NOHSA-NEXT: s_mov_b32 s0, s4 +; SI-NOHSA-NEXT: s_mov_b32 s1, s5 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:112 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[8:11], off, s[8:11], 0 offset:96 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[12:15], off, s[8:11], 0 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[16:19], off, s[8:11], 0 offset:16 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[20:23], off, s[8:11], 0 offset:32 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[24:27], off, s[8:11], 0 offset:48 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(5) +; SI-NOHSA-NEXT: v_mov_b32_e32 v0, v4 +; SI-NOHSA-NEXT: v_mov_b32_e32 v2, v5 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[28:31], off, s[8:11], 0 offset:64 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[32:35], off, s[8:11], 0 offset:80 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:224 +; SI-NOHSA-NEXT: s_waitcnt expcnt(0) +; SI-NOHSA-NEXT: v_mov_b32_e32 v0, v6 +; SI-NOHSA-NEXT: v_mov_b32_e32 v2, v7 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:240 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(8) expcnt(0) +; SI-NOHSA-NEXT: v_mov_b32_e32 v0, v8 +; SI-NOHSA-NEXT: v_mov_b32_e32 v2, v9 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:192 +; SI-NOHSA-NEXT: s_waitcnt expcnt(0) +; SI-NOHSA-NEXT: v_mov_b32_e32 v0, v10 +; SI-NOHSA-NEXT: v_mov_b32_e32 v2, v11 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:208 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(4) expcnt(0) +; SI-NOHSA-NEXT: v_mov_b32_e32 v0, v32 +; SI-NOHSA-NEXT: v_mov_b32_e32 v2, v33 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:160 +; SI-NOHSA-NEXT: s_waitcnt expcnt(0) +; SI-NOHSA-NEXT: v_mov_b32_e32 v0, v34 +; SI-NOHSA-NEXT: v_mov_b32_e32 v2, v35 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:176 +; SI-NOHSA-NEXT: s_waitcnt expcnt(0) +; SI-NOHSA-NEXT: v_mov_b32_e32 v0, v28 +; SI-NOHSA-NEXT: v_mov_b32_e32 v2, v29 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:128 +; SI-NOHSA-NEXT: s_waitcnt expcnt(0) +; SI-NOHSA-NEXT: v_mov_b32_e32 v0, v30 +; SI-NOHSA-NEXT: v_mov_b32_e32 v2, v31 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:144 +; SI-NOHSA-NEXT: s_waitcnt expcnt(0) +; SI-NOHSA-NEXT: v_mov_b32_e32 v0, v24 +; SI-NOHSA-NEXT: v_mov_b32_e32 v2, v25 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:96 +; SI-NOHSA-NEXT: s_waitcnt expcnt(0) +; SI-NOHSA-NEXT: v_mov_b32_e32 v0, v26 +; SI-NOHSA-NEXT: v_mov_b32_e32 v2, v27 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:112 +; SI-NOHSA-NEXT: s_waitcnt expcnt(0) +; SI-NOHSA-NEXT: v_mov_b32_e32 v0, v20 +; SI-NOHSA-NEXT: v_mov_b32_e32 v2, v21 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:64 +; SI-NOHSA-NEXT: s_waitcnt expcnt(0) +; SI-NOHSA-NEXT: v_mov_b32_e32 v0, v22 +; SI-NOHSA-NEXT: v_mov_b32_e32 v2, v23 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:80 +; SI-NOHSA-NEXT: s_waitcnt expcnt(0) +; SI-NOHSA-NEXT: v_mov_b32_e32 v0, v16 +; SI-NOHSA-NEXT: v_mov_b32_e32 v2, v17 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32 +; SI-NOHSA-NEXT: s_waitcnt expcnt(0) +; SI-NOHSA-NEXT: v_mov_b32_e32 v0, v18 +; SI-NOHSA-NEXT: v_mov_b32_e32 v2, v19 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48 +; SI-NOHSA-NEXT: s_waitcnt expcnt(0) +; SI-NOHSA-NEXT: v_mov_b32_e32 v0, v12 +; SI-NOHSA-NEXT: v_mov_b32_e32 v2, v13 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 +; SI-NOHSA-NEXT: s_waitcnt expcnt(0) +; SI-NOHSA-NEXT: v_mov_b32_e32 v0, v14 +; SI-NOHSA-NEXT: v_mov_b32_e32 v2, v15 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16 +; SI-NOHSA-NEXT: s_endpgm +; +; GCNX3-HSA-LABEL: global_zextload_v32i32_to_v32i64: +; GCNX3-HSA: ; %bb.0: +; GCNX3-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCNX3-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 16 +; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0 +; GCNX3-HSA-NEXT: s_add_u32 s6, s2, 32 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2 +; GCNX3-HSA-NEXT: s_addc_u32 s7, s3, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3 +; GCNX3-HSA-NEXT: s_add_u32 s8, s2, 48 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[28:31], v[0:1] +; GCNX3-HSA-NEXT: s_addc_u32 s9, s3, 0 +; GCNX3-HSA-NEXT: s_add_u32 s10, s2, 64 +; GCNX3-HSA-NEXT: s_addc_u32 s11, s3, 0 +; GCNX3-HSA-NEXT: s_add_u32 s12, s2, 0x50 +; GCNX3-HSA-NEXT: s_addc_u32 s13, s3, 0 +; GCNX3-HSA-NEXT: s_add_u32 s14, s2, 0x60 +; GCNX3-HSA-NEXT: s_addc_u32 s15, s3, 0 +; GCNX3-HSA-NEXT: s_add_u32 s2, s2, 0x70 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s3, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[32:35], v[0:1] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s14 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s15 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[24:27], v[0:1] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s12 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s13 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[20:23], v[0:1] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s10 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s11 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[16:19], v[0:1] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s8 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s9 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[12:15], v[0:1] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s4 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s7 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s5 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s6 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5] +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[8:11], v[8:9] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, 0 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 16 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v3, v1 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(7) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, v28 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, v29 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v29, s1 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v28, s0 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[28:29], v[0:3] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v29, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v28, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0xe0 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, v30 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, v31 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v31, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v30, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0xf0 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[28:29], v[0:3] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v29, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v28, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0xc0 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(8) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, v32 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, v33 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[30:31], v[0:3] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v31, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v30, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0xd0 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v33, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v32, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0xa0 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, v34 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, v35 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v35, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v34, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0xb0 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[28:29], v[0:3] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v29, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v28, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0x80 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(9) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, v24 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, v25 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v25, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v24, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0x90 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[30:31], v[0:3] +; GCNX3-HSA-NEXT: s_nop 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, v26 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, v27 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v27, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v26, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0x60 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[32:33], v[0:3] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v31, s3 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(10) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, v20 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, v21 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[34:35], v[0:3] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v30, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, v22 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, v23 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0x70 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[28:29], v[0:3] +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(11) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, v16 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, v17 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[24:25], v[0:3] +; GCNX3-HSA-NEXT: s_nop 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, v18 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, v19 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[26:27], v[0:3] +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(12) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, v12 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, v13 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v13, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v12, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 64 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[30:31], v[0:3] +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, v14 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, v15 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[12:13], v[0:3] +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(12) +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, v8 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, v9 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0x50 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[8:9], v[0:3] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s2 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 32 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, v10 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, v11 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[8:9], v[0:3] +; GCNX3-HSA-NEXT: s_add_u32 s0, s0, 48 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, v4 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, v5 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s2 +; GCNX3-HSA-NEXT: s_addc_u32 s1, s1, 0 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s1 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, v6 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, v7 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s0 +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; GCNX3-HSA-NEXT: s_endpgm +; +; GCNX3-NOHSA-LABEL: global_zextload_v32i32_to_v32i64: +; GCNX3-NOHSA: ; %bb.0: +; GCNX3-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GCNX3-NOHSA-NEXT: s_mov_b32 s3, 0xf000 +; GCNX3-NOHSA-NEXT: s_mov_b32 s2, -1 +; GCNX3-NOHSA-NEXT: s_mov_b32 s10, s2 +; GCNX3-NOHSA-NEXT: s_mov_b32 s11, s3 +; GCNX3-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-NOHSA-NEXT: s_mov_b32 s8, s6 +; GCNX3-NOHSA-NEXT: s_mov_b32 s9, s7 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 offset:112 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:96 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[8:11], off, s[8:11], 0 offset:80 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[12:15], off, s[8:11], 0 offset:64 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[16:19], off, s[8:11], 0 offset:48 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[20:23], off, s[8:11], 0 offset:32 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[24:27], off, s[8:11], 0 offset:16 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[32:35], off, s[8:11], 0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v29, 0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v31, v29 +; GCNX3-NOHSA-NEXT: s_mov_b32 s0, s4 +; GCNX3-NOHSA-NEXT: s_mov_b32 s1, s5 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(7) +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v28, v0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v30, v1 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[28:31], off, s[0:3], 0 offset:224 +; GCNX3-NOHSA-NEXT: s_nop 0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v28, v2 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v30, v3 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[28:31], off, s[0:3], 0 offset:240 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(8) +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v28, v4 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v30, v5 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[28:31], off, s[0:3], 0 offset:192 +; GCNX3-NOHSA-NEXT: s_nop 0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v28, v6 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v30, v7 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[28:31], off, s[0:3], 0 offset:208 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(9) +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v28, v8 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v30, v9 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[28:31], off, s[0:3], 0 offset:160 +; GCNX3-NOHSA-NEXT: s_nop 0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v28, v10 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v30, v11 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[28:31], off, s[0:3], 0 offset:176 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(10) +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v28, v12 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v30, v13 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[28:31], off, s[0:3], 0 offset:128 +; GCNX3-NOHSA-NEXT: s_nop 0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v28, v14 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v30, v15 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[28:31], off, s[0:3], 0 offset:144 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(11) +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v28, v16 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v30, v17 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[28:31], off, s[0:3], 0 offset:96 +; GCNX3-NOHSA-NEXT: s_nop 0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v28, v18 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v30, v19 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[28:31], off, s[0:3], 0 offset:112 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(12) +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v28, v20 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v30, v21 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[28:31], off, s[0:3], 0 offset:64 +; GCNX3-NOHSA-NEXT: s_nop 0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v28, v22 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v30, v23 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[28:31], off, s[0:3], 0 offset:80 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(13) +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v28, v24 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v30, v25 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[28:31], off, s[0:3], 0 offset:32 +; GCNX3-NOHSA-NEXT: s_nop 0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v28, v26 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v30, v27 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[28:31], off, s[0:3], 0 offset:48 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(14) +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v28, v32 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v30, v33 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[28:31], off, s[0:3], 0 +; GCNX3-NOHSA-NEXT: s_nop 0 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v28, v34 +; GCNX3-NOHSA-NEXT: v_mov_b32_e32 v30, v35 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[28:31], off, s[0:3], 0 offset:16 +; GCNX3-NOHSA-NEXT: s_endpgm +; +; EG-LABEL: global_zextload_v32i32_to_v32i64: +; EG: ; %bb.0: +; EG-NEXT: ALU 0, @38, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 2 @22 +; EG-NEXT: ALU 10, @39, KC0[], KC1[] +; EG-NEXT: TEX 4 @28 +; EG-NEXT: ALU 100, @50, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T31.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T5.XYZW, T30.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T29.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T7.XYZW, T28.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T8.XYZW, T27.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T9.XYZW, T26.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T14.XYZW, T25.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T15.XYZW, T24.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T16.XYZW, T13.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T17.XYZW, T12.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T18.XYZW, T11.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T19.XYZW, T10.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T20.XYZW, T3.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T21.XYZW, T2.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T22.XYZW, T1.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T23.XYZW, T0.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: Fetch clause starting at 22: +; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 112, #1 +; EG-NEXT: VTX_READ_128 T2.XYZW, T0.X, 80, #1 +; EG-NEXT: VTX_READ_128 T3.XYZW, T0.X, 96, #1 +; EG-NEXT: Fetch clause starting at 28: +; EG-NEXT: VTX_READ_128 T10.XYZW, T0.X, 0, #1 +; EG-NEXT: VTX_READ_128 T11.XYZW, T0.X, 16, #1 +; EG-NEXT: VTX_READ_128 T12.XYZW, T0.X, 32, #1 +; EG-NEXT: VTX_READ_128 T13.XYZW, T0.X, 48, #1 +; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 64, #1 +; EG-NEXT: ALU clause starting at 38: +; EG-NEXT: MOV * T0.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 39: +; EG-NEXT: MOV T4.X, T1.X, +; EG-NEXT: MOV T4.Y, 0.0, +; EG-NEXT: MOV * T5.X, T1.Z, +; EG-NEXT: MOV * T5.Y, 0.0, +; EG-NEXT: MOV T6.X, T3.X, +; EG-NEXT: MOV T6.Y, 0.0, +; EG-NEXT: MOV * T7.X, T3.Z, +; EG-NEXT: MOV * T7.Y, 0.0, +; EG-NEXT: MOV T8.X, T2.X, +; EG-NEXT: MOV T8.Y, 0.0, +; EG-NEXT: MOV * T9.X, T2.Z, +; EG-NEXT: ALU clause starting at 50: +; EG-NEXT: MOV * T9.Y, 0.0, +; EG-NEXT: MOV T14.X, T0.X, +; EG-NEXT: MOV T14.Y, 0.0, +; EG-NEXT: MOV * T15.X, T0.Z, +; EG-NEXT: MOV * T15.Y, 0.0, +; EG-NEXT: MOV T16.X, T13.X, +; EG-NEXT: MOV T16.Y, 0.0, +; EG-NEXT: MOV * T17.X, T13.Z, +; EG-NEXT: MOV * T17.Y, 0.0, +; EG-NEXT: MOV T18.X, T12.X, +; EG-NEXT: MOV T18.Y, 0.0, +; EG-NEXT: MOV * T19.X, T12.Z, +; EG-NEXT: MOV * T19.Y, 0.0, +; EG-NEXT: MOV T20.X, T11.X, +; EG-NEXT: MOV T20.Y, 0.0, +; EG-NEXT: MOV * T21.X, T11.Z, +; EG-NEXT: MOV * T21.Y, 0.0, +; EG-NEXT: MOV T22.X, T10.X, +; EG-NEXT: MOV T22.Y, 0.0, +; EG-NEXT: MOV * T23.X, T10.Z, +; EG-NEXT: MOV T23.Y, 0.0, +; EG-NEXT: MOV T4.Z, T1.Y, +; EG-NEXT: MOV T4.W, 0.0, +; EG-NEXT: MOV * T5.Z, T1.W, +; EG-NEXT: MOV * T5.W, 0.0, +; EG-NEXT: MOV T6.Z, T3.Y, +; EG-NEXT: MOV T6.W, 0.0, +; EG-NEXT: MOV * T7.Z, T3.W, +; EG-NEXT: MOV * T7.W, 0.0, +; EG-NEXT: MOV T8.Z, T2.Y, +; EG-NEXT: MOV T8.W, 0.0, +; EG-NEXT: MOV * T9.Z, T2.W, +; EG-NEXT: MOV * T9.W, 0.0, +; EG-NEXT: MOV T14.Z, T0.Y, +; EG-NEXT: MOV T14.W, 0.0, +; EG-NEXT: MOV * T15.Z, T0.W, +; EG-NEXT: MOV * T15.W, 0.0, +; EG-NEXT: MOV T16.Z, T13.Y, +; EG-NEXT: MOV T16.W, 0.0, +; EG-NEXT: MOV * T17.Z, T13.W, +; EG-NEXT: MOV * T17.W, 0.0, +; EG-NEXT: MOV T18.Z, T12.Y, +; EG-NEXT: MOV T18.W, 0.0, +; EG-NEXT: MOV * T19.Z, T12.W, +; EG-NEXT: MOV * T19.W, 0.0, +; EG-NEXT: MOV T20.Z, T11.Y, +; EG-NEXT: MOV T20.W, 0.0, +; EG-NEXT: MOV * T21.Z, T11.W, +; EG-NEXT: MOV * T21.W, 0.0, +; EG-NEXT: MOV T22.Z, T10.Y, +; EG-NEXT: MOV T22.W, 0.0, +; EG-NEXT: MOV * T23.Z, T10.W, +; EG-NEXT: MOV T23.W, 0.0, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T0.X, PS, literal.x, +; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, +; EG-NEXT: 48(6.726233e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T2.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44) +; EG-NEXT: LSHR T3.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 80(1.121039e-43) +; EG-NEXT: LSHR T10.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 64(8.968310e-44) +; EG-NEXT: LSHR T11.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 112(1.569454e-43) +; EG-NEXT: LSHR T12.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 96(1.345247e-43) +; EG-NEXT: LSHR T13.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 144(2.017870e-43) +; EG-NEXT: LSHR T24.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 128(1.793662e-43) +; EG-NEXT: LSHR T25.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 176(2.466285e-43) +; EG-NEXT: LSHR T26.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 160(2.242078e-43) +; EG-NEXT: LSHR T27.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 208(2.914701e-43) +; EG-NEXT: LSHR T28.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 192(2.690493e-43) +; EG-NEXT: LSHR T29.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 240(3.363116e-43) +; EG-NEXT: LSHR T30.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 224(3.138909e-43) +; EG-NEXT: LSHR * T31.X, PV.W, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-HSA-LABEL: global_zextload_v32i32_to_v32i64: +; GCN-HSA: ; %bb.0: +; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCN-HSA-NEXT: v_mov_b32_e32 v1, 0 +; GCN-HSA-NEXT: v_mov_b32_e32 v3, v1 +; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCN-HSA-NEXT: global_load_dwordx4 v[4:7], v1, s[2:3] offset:112 +; GCN-HSA-NEXT: global_load_dwordx4 v[8:11], v1, s[2:3] offset:96 +; GCN-HSA-NEXT: global_load_dwordx4 v[12:15], v1, s[2:3] offset:80 +; GCN-HSA-NEXT: global_load_dwordx4 v[16:19], v1, s[2:3] offset:64 +; GCN-HSA-NEXT: global_load_dwordx4 v[20:23], v1, s[2:3] offset:48 +; GCN-HSA-NEXT: global_load_dwordx4 v[24:27], v1, s[2:3] offset:32 +; GCN-HSA-NEXT: global_load_dwordx4 v[28:31], v1, s[2:3] offset:16 +; GCN-HSA-NEXT: global_load_dwordx4 v[32:35], v1, s[2:3] +; GCN-HSA-NEXT: s_waitcnt vmcnt(7) +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v4 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v5 +; GCN-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] offset:224 +; GCN-HSA-NEXT: s_nop 0 +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v6 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v7 +; GCN-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] offset:240 +; GCN-HSA-NEXT: s_waitcnt vmcnt(8) +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v8 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v9 +; GCN-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] offset:192 +; GCN-HSA-NEXT: s_nop 0 +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v10 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v11 +; GCN-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] offset:208 +; GCN-HSA-NEXT: s_waitcnt vmcnt(9) +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v12 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v13 +; GCN-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] offset:160 +; GCN-HSA-NEXT: s_nop 0 +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v14 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v15 +; GCN-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] offset:176 +; GCN-HSA-NEXT: s_waitcnt vmcnt(10) +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v16 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v17 +; GCN-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] offset:128 +; GCN-HSA-NEXT: s_nop 0 +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v18 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v19 +; GCN-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] offset:144 +; GCN-HSA-NEXT: s_waitcnt vmcnt(11) +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v20 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v21 +; GCN-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] offset:96 +; GCN-HSA-NEXT: s_nop 0 +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v22 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v23 +; GCN-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] offset:112 +; GCN-HSA-NEXT: s_waitcnt vmcnt(12) +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v24 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v25 +; GCN-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] offset:64 +; GCN-HSA-NEXT: s_nop 0 +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v26 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v27 +; GCN-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] offset:80 +; GCN-HSA-NEXT: s_waitcnt vmcnt(13) +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v28 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v29 +; GCN-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] offset:32 +; GCN-HSA-NEXT: s_nop 0 +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v30 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v31 +; GCN-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] offset:48 +; GCN-HSA-NEXT: s_waitcnt vmcnt(14) +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v32 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v33 +; GCN-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] +; GCN-HSA-NEXT: s_nop 0 +; GCN-HSA-NEXT: v_mov_b32_e32 v0, v34 +; GCN-HSA-NEXT: v_mov_b32_e32 v2, v35 +; GCN-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] offset:16 +; GCN-HSA-NEXT: s_endpgm %ld = load <32 x i32>, ptr addrspace(1) %in %ext = zext <32 x i32> %ld to <32 x i64> store <32 x i64> %ext, ptr addrspace(1) %out ret void } -; FUNC-LABEL: {{^}}global_load_v32i32: -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 -; GCN-NOHSA: buffer_load_dwordx4 - -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 -; GCN-HSA: {{flat|global}}_load_dwordx4 - - -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-NOHSA-DAG: buffer_store_dwordx4 - -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-NOHSA-DAG: buffer_store_dwordx4 - -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-NOHSA-DAG: buffer_store_dwordx4 - -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-NOHSA-DAG: buffer_store_dwordx4 - -; GCN-NOT: accvgpr - -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 - -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 - -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 - -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 define amdgpu_kernel void @global_load_v32i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-NOHSA-LABEL: global_load_v32i32: +; SI-NOHSA: ; %bb.0: +; SI-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; SI-NOHSA-NEXT: s_mov_b32 s6, -1 +; SI-NOHSA-NEXT: s_mov_b32 s10, s6 +; SI-NOHSA-NEXT: s_mov_b32 s11, s7 +; SI-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; SI-NOHSA-NEXT: s_mov_b32 s4, s0 +; SI-NOHSA-NEXT: s_mov_b32 s5, s1 +; SI-NOHSA-NEXT: s_mov_b32 s8, s2 +; SI-NOHSA-NEXT: s_mov_b32 s9, s3 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[8:11], off, s[8:11], 0 offset:112 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[12:15], off, s[8:11], 0 offset:96 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[16:19], off, s[8:11], 0 offset:80 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[20:23], off, s[8:11], 0 offset:64 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[24:27], off, s[8:11], 0 offset:32 +; SI-NOHSA-NEXT: buffer_load_dwordx4 v[28:31], off, s[8:11], 0 offset:48 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(4) +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[12:15], off, s[4:7], 0 offset:96 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[8:11], off, s[4:7], 0 offset:112 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(4) +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[20:23], off, s[4:7], 0 offset:64 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[16:19], off, s[4:7], 0 offset:80 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(5) +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[24:27], off, s[4:7], 0 offset:32 +; SI-NOHSA-NEXT: s_waitcnt vmcnt(5) +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[28:31], off, s[4:7], 0 offset:48 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 +; SI-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16 +; SI-NOHSA-NEXT: s_endpgm +; +; GCNX3-HSA-LABEL: global_load_v32i32: +; GCNX3-HSA: ; %bb.0: +; GCNX3-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCNX3-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 16 +; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0 +; GCNX3-HSA-NEXT: s_add_u32 s6, s2, 48 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v29, s5 +; GCNX3-HSA-NEXT: s_addc_u32 s7, s3, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v28, s4 +; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 32 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s5 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s4 +; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 0x50 +; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v13, s5 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v12, s4 +; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 64 +; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v17, s5 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, s4 +; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 0x70 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s6 +; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s7 +; GCNX3-HSA-NEXT: s_add_u32 s2, s2, 0x60 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5] +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[8:11], v[8:9] +; GCNX3-HSA-NEXT: s_addc_u32 s3, s3, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v21, s5 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v25, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v20, s4 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v24, s2 +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[12:15], v[12:13] +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[16:19], v[16:17] +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[20:23], v[20:21] +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[24:27], v[24:25] +; GCNX3-HSA-NEXT: flat_load_dwordx4 v[28:31], v[28:29] +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0x60 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v33, s1 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v32, s0 +; GCNX3-HSA-NEXT: s_add_u32 s4, s0, 0x70 +; GCNX3-HSA-NEXT: s_addc_u32 s5, s1, 0 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(7) +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[32:33], v[0:3] +; GCNX3-HSA-NEXT: s_nop 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3 +; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 64 +; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0 +; GCNX3-HSA-NEXT: s_add_u32 s6, s0, 0x50 +; GCNX3-HSA-NEXT: s_addc_u32 s7, s1, 0 +; GCNX3-HSA-NEXT: s_add_u32 s8, s0, 32 +; GCNX3-HSA-NEXT: s_addc_u32 s9, s1, 0 +; GCNX3-HSA-NEXT: s_add_u32 s10, s0, 48 +; GCNX3-HSA-NEXT: s_addc_u32 s11, s1, 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, s10 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v3, s11 +; GCNX3-HSA-NEXT: s_add_u32 s0, s0, 16 +; GCNX3-HSA-NEXT: s_addc_u32 s1, s1, 0 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(7) +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[2:3], v[4:7] +; GCNX3-HSA-NEXT: s_nop 0 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v6, s8 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v7, s9 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(7) +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[6:7], v[8:11] +; GCNX3-HSA-NEXT: v_mov_b32_e32 v6, s6 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, s4 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s3 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v7, s7 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s1 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v3, s5 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s2 +; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s0 +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(7) +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[6:7], v[12:15] +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(7) +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[4:5], v[16:19] +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(7) +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[2:3], v[20:23] +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(7) +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[0:1], v[24:27] +; GCNX3-HSA-NEXT: s_waitcnt vmcnt(7) +; GCNX3-HSA-NEXT: flat_store_dwordx4 v[8:9], v[28:31] +; GCNX3-HSA-NEXT: s_endpgm +; +; GCNX3-NOHSA-LABEL: global_load_v32i32: +; GCNX3-NOHSA: ; %bb.0: +; GCNX3-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GCNX3-NOHSA-NEXT: s_mov_b32 s7, 0xf000 +; GCNX3-NOHSA-NEXT: s_mov_b32 s6, -1 +; GCNX3-NOHSA-NEXT: s_mov_b32 s10, s6 +; GCNX3-NOHSA-NEXT: s_mov_b32 s11, s7 +; GCNX3-NOHSA-NEXT: s_waitcnt lgkmcnt(0) +; GCNX3-NOHSA-NEXT: s_mov_b32 s8, s2 +; GCNX3-NOHSA-NEXT: s_mov_b32 s9, s3 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 offset:112 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:96 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[8:11], off, s[8:11], 0 offset:80 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[12:15], off, s[8:11], 0 offset:64 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[16:19], off, s[8:11], 0 offset:32 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[20:23], off, s[8:11], 0 offset:48 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[24:27], off, s[8:11], 0 +; GCNX3-NOHSA-NEXT: buffer_load_dwordx4 v[28:31], off, s[8:11], 0 offset:16 +; GCNX3-NOHSA-NEXT: s_mov_b32 s4, s0 +; GCNX3-NOHSA-NEXT: s_mov_b32 s5, s1 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(6) +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:96 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 offset:112 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(6) +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[12:15], off, s[4:7], 0 offset:64 +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[8:11], off, s[4:7], 0 offset:80 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(7) +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[16:19], off, s[4:7], 0 offset:32 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(7) +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[20:23], off, s[4:7], 0 offset:48 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(7) +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[24:27], off, s[4:7], 0 +; GCNX3-NOHSA-NEXT: s_waitcnt vmcnt(7) +; GCNX3-NOHSA-NEXT: buffer_store_dwordx4 v[28:31], off, s[4:7], 0 offset:16 +; GCNX3-NOHSA-NEXT: s_endpgm +; +; EG-LABEL: global_load_v32i32: +; EG: ; %bb.0: +; EG-NEXT: ALU 23, @28, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 7 @12 +; EG-NEXT: ALU 1, @52, KC0[], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T8.XYZW, T15.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T9.XYZW, T6.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T10.XYZW, T5.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T11.XYZW, T4.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T12.XYZW, T3.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T13.XYZW, T2.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T14.XYZW, T1.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T7.XYZW, T0.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: Fetch clause starting at 12: +; EG-NEXT: VTX_READ_128 T8.XYZW, T7.X, 96, #1 +; EG-NEXT: VTX_READ_128 T9.XYZW, T7.X, 112, #1 +; EG-NEXT: VTX_READ_128 T10.XYZW, T7.X, 64, #1 +; EG-NEXT: VTX_READ_128 T11.XYZW, T7.X, 80, #1 +; EG-NEXT: VTX_READ_128 T12.XYZW, T7.X, 32, #1 +; EG-NEXT: VTX_READ_128 T13.XYZW, T7.X, 48, #1 +; EG-NEXT: VTX_READ_128 T14.XYZW, T7.X, 0, #1 +; EG-NEXT: VTX_READ_128 T7.XYZW, T7.X, 16, #1 +; EG-NEXT: ALU clause starting at 28: +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T0.X, PV.W, literal.x, +; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, +; EG-NEXT: 48(6.726233e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T2.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44) +; EG-NEXT: LSHR T3.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 80(1.121039e-43) +; EG-NEXT: LSHR T4.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 64(8.968310e-44) +; EG-NEXT: LSHR T5.X, PV.W, literal.x, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; EG-NEXT: 2(2.802597e-45), 112(1.569454e-43) +; EG-NEXT: LSHR T6.X, PV.W, literal.x, +; EG-NEXT: MOV * T7.X, KC0[2].Z, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, +; EG-NEXT: 96(1.345247e-43), 0(0.000000e+00) +; EG-NEXT: ALU clause starting at 52: +; EG-NEXT: LSHR * T15.X, T0.W, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-HSA-LABEL: global_load_v32i32: +; GCN-HSA: ; %bb.0: +; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 +; GCN-HSA-NEXT: v_mov_b32_e32 v32, 0 +; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0) +; GCN-HSA-NEXT: global_load_dwordx4 v[0:3], v32, s[2:3] offset:96 +; GCN-HSA-NEXT: global_load_dwordx4 v[4:7], v32, s[2:3] offset:112 +; GCN-HSA-NEXT: global_load_dwordx4 v[8:11], v32, s[2:3] offset:64 +; GCN-HSA-NEXT: global_load_dwordx4 v[12:15], v32, s[2:3] offset:80 +; GCN-HSA-NEXT: global_load_dwordx4 v[16:19], v32, s[2:3] offset:32 +; GCN-HSA-NEXT: global_load_dwordx4 v[20:23], v32, s[2:3] offset:48 +; GCN-HSA-NEXT: global_load_dwordx4 v[24:27], v32, s[2:3] +; GCN-HSA-NEXT: global_load_dwordx4 v[28:31], v32, s[2:3] offset:16 +; GCN-HSA-NEXT: s_waitcnt vmcnt(7) +; GCN-HSA-NEXT: global_store_dwordx4 v32, v[0:3], s[0:1] offset:96 +; GCN-HSA-NEXT: s_waitcnt vmcnt(7) +; GCN-HSA-NEXT: global_store_dwordx4 v32, v[4:7], s[0:1] offset:112 +; GCN-HSA-NEXT: s_waitcnt vmcnt(7) +; GCN-HSA-NEXT: global_store_dwordx4 v32, v[8:11], s[0:1] offset:64 +; GCN-HSA-NEXT: s_waitcnt vmcnt(7) +; GCN-HSA-NEXT: global_store_dwordx4 v32, v[12:15], s[0:1] offset:80 +; GCN-HSA-NEXT: s_waitcnt vmcnt(7) +; GCN-HSA-NEXT: global_store_dwordx4 v32, v[16:19], s[0:1] offset:32 +; GCN-HSA-NEXT: s_waitcnt vmcnt(7) +; GCN-HSA-NEXT: global_store_dwordx4 v32, v[20:23], s[0:1] offset:48 +; GCN-HSA-NEXT: s_waitcnt vmcnt(7) +; GCN-HSA-NEXT: global_store_dwordx4 v32, v[24:27], s[0:1] +; GCN-HSA-NEXT: s_waitcnt vmcnt(7) +; GCN-HSA-NEXT: global_store_dwordx4 v32, v[28:31], s[0:1] offset:16 +; GCN-HSA-NEXT: s_endpgm %ld = load <32 x i32>, ptr addrspace(1) %in store <32 x i32> %ld, ptr addrspace(1) %out ret void -- GitLab From bb98227db19ae4d80af7a25a9423aae2aeaec61d Mon Sep 17 00:00:00 2001 From: Guillaume Chatelet Date: Fri, 1 Dec 2023 10:30:15 +0100 Subject: [PATCH 119/699] [libc][NFC] Remove named_pair (#73952) `named_pair` does not provide enough value to deserve its own header. --- libc/src/__support/CMakeLists.txt | 8 -------- libc/src/__support/math_extras.h | 11 ++++++++--- libc/src/__support/named_pair.h | 18 ------------------ libc/src/__support/number_pair.h | 6 ++++-- .../llvm-project-overlay/libc/BUILD.bazel | 7 ------- 5 files changed, 12 insertions(+), 38 deletions(-) delete mode 100644 libc/src/__support/named_pair.h diff --git a/libc/src/__support/CMakeLists.txt b/libc/src/__support/CMakeLists.txt index decd6ed2dbd2..ba80965b5aaa 100644 --- a/libc/src/__support/CMakeLists.txt +++ b/libc/src/__support/CMakeLists.txt @@ -10,12 +10,6 @@ add_header_library( libc.src.__support.CPP.new ) -add_header_library( - named_pair - HDRS - named_pair.h -) - add_header_library( common HDRS @@ -40,7 +34,6 @@ add_header_library( HDRS math_extras.h DEPENDS - .named_pair libc.src.__support.CPP.type_traits libc.src.__support.macros.attributes libc.src.__support.macros.config @@ -187,7 +180,6 @@ add_header_library( HDRS number_pair.h DEPENDS - .named_pair libc.src.__support.CPP.type_traits ) diff --git a/libc/src/__support/math_extras.h b/libc/src/__support/math_extras.h index cc22aa49d026..860cdda8586d 100644 --- a/libc/src/__support/math_extras.h +++ b/libc/src/__support/math_extras.h @@ -10,7 +10,6 @@ #ifndef LLVM_LIBC_SRC___SUPPORT_MATH_EXTRAS_H #define LLVM_LIBC_SRC___SUPPORT_MATH_EXTRAS_H -#include "named_pair.h" #include "src/__support/CPP/type_traits.h" #include "src/__support/macros/attributes.h" // LIBC_INLINE #include "src/__support/macros/config.h" // LIBC_HAS_BUILTIN @@ -18,7 +17,10 @@ namespace LIBC_NAMESPACE { // Add with carry -DEFINE_NAMED_PAIR_TEMPLATE(SumCarry, sum, carry); +template struct SumCarry { + T sum; + T carry; +}; // This version is always valid for constexpr. template @@ -91,7 +93,10 @@ add_with_carry(unsigned long long a, unsigned long long b, #endif // LIBC_HAS_BUILTIN(__builtin_addc) // Subtract with borrow -DEFINE_NAMED_PAIR_TEMPLATE(DiffBorrow, diff, borrow); +template struct DiffBorrow { + T diff; + T borrow; +}; // This version is always valid for constexpr. template diff --git a/libc/src/__support/named_pair.h b/libc/src/__support/named_pair.h deleted file mode 100644 index bd7dccf9810c..000000000000 --- a/libc/src/__support/named_pair.h +++ /dev/null @@ -1,18 +0,0 @@ -//===-- Utilities for pairs of numbers. -------------------------*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIBC_SRC___SUPPORT_NAMED_PAIR_H -#define LLVM_LIBC_SRC___SUPPORT_NAMED_PAIR_H - -#define DEFINE_NAMED_PAIR_TEMPLATE(Name, FirstField, SecondField) \ - template struct Name { \ - T1 FirstField; \ - T2 SecondField; \ - } - -#endif // LLVM_LIBC_SRC___SUPPORT_NAMED_PAIR_H diff --git a/libc/src/__support/number_pair.h b/libc/src/__support/number_pair.h index 5e553d817994..12e730836af2 100644 --- a/libc/src/__support/number_pair.h +++ b/libc/src/__support/number_pair.h @@ -10,13 +10,15 @@ #define LLVM_LIBC_SRC___SUPPORT_NUMBER_PAIR_H #include "CPP/type_traits.h" -#include "named_pair.h" #include namespace LIBC_NAMESPACE { -DEFINE_NAMED_PAIR_TEMPLATE(NumberPair, lo, hi); +template struct NumberPair { + T lo; + T hi; +}; template cpp::enable_if_t && cpp::is_unsigned_v, NumberPair> diff --git a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel index d53ca2021015..46d81987e7b3 100644 --- a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel @@ -432,7 +432,6 @@ libc_support_library( hdrs = ["src/__support/number_pair.h"], deps = [ ":__support_cpp_type_traits", - ":__support_named_pair", ], ) @@ -587,11 +586,6 @@ libc_support_library( ], ) -libc_support_library( - name = "__support_named_pair", - hdrs = ["src/__support/named_pair.h"], -) - libc_support_library( name = "__support_bit", hdrs = ["src/__support/bit.h"], @@ -608,7 +602,6 @@ libc_support_library( ":__support_cpp_type_traits", ":__support_macros_attributes", ":__support_macros_config", - ":__support_named_pair", ], ) -- GitLab From 5fe7ae848cc6cb2afc3aab332743ffa2bb635fc3 Mon Sep 17 00:00:00 2001 From: Matt Devereau Date: Mon, 20 Nov 2023 10:49:27 +0000 Subject: [PATCH 120/699] [AArch64][SME2] Add ldr_zt, str_zt builtins and intrinsics (#72849) Adds the builtins: void svldr_zt(uint64_t zt, const void *rn) void svstr_zt(uint64_t zt, void *rn) And the intrinsics: call void @llvm.aarch64.sme.ldr.zt(i32, ptr) tail call void @llvm.aarch64.sme.str.zt(i32, ptr) Patch by: Kerry McLaughlin kerry.mclaughlin@arm.com --- clang/include/clang/Basic/arm_sme.td | 8 ++++ .../acle_sme2_ldr_str_zt.c | 41 +++++++++++++++++++ .../aarch64-sme2-intrinsics/acle_sme2_imm.cpp | 7 +++- .../Target/AArch64/AArch64ISelDAGToDAG.cpp | 7 +++- .../Target/AArch64/AArch64ISelLowering.cpp | 18 ++++++++ llvm/lib/Target/AArch64/AArch64ISelLowering.h | 2 + .../Target/AArch64/AArch64RegisterInfo.cpp | 6 +++ .../lib/Target/AArch64/AArch64SMEInstrInfo.td | 4 +- llvm/lib/Target/AArch64/SMEInstrFormats.td | 23 ++++++++--- .../CodeGen/AArch64/sme2-intrinsics-zt0.ll | 27 ++++++++++++ 10 files changed, 134 insertions(+), 9 deletions(-) create mode 100644 clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ldr_str_zt.c create mode 100644 llvm/test/CodeGen/AArch64/sme2-intrinsics-zt0.ll diff --git a/clang/include/clang/Basic/arm_sme.td b/clang/include/clang/Basic/arm_sme.td index d55deeaa40bb..7aae3c832bb1 100644 --- a/clang/include/clang/Basic/arm_sme.td +++ b/clang/include/clang/Basic/arm_sme.td @@ -314,3 +314,11 @@ let TargetGuard = "sme2" in { def SVBMOPS : Inst<"svbmops_za32[_{d}]_m", "viPPdd", "iUi", MergeNone, "aarch64_sme_bmops_za32", [IsSharedZA, IsStreaming], [ImmCheck<0, ImmCheck0_3>]>; } + +// +// Spill and fill of ZT0 +// +let TargetGuard = "sme2" in { + def SVLDR_ZT : Inst<"svldr_zt", "viQ", "", MergeNone, "aarch64_sme_ldr_zt", [IsOverloadNone, IsStreamingCompatible, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>]>; + def SVSTR_ZT : Inst<"svstr_zt", "vi%", "", MergeNone, "aarch64_sme_str_zt", [IsOverloadNone, IsStreamingCompatible, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>]>; +} diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ldr_str_zt.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ldr_str_zt.c new file mode 100644 index 000000000000..126a4fc10458 --- /dev/null +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ldr_str_zt.c @@ -0,0 +1,41 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py + +// REQUIRES: aarch64-registered-target + +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s + +#include + +// LDR ZT0 + +// CHECK-LABEL: @test_svldr_zt( +// CHECK-NEXT: entry: +// CHECK-NEXT: tail call void @llvm.aarch64.sme.ldr.zt(i32 0, ptr [[BASE:%.*]]) +// CHECK-NEXT: ret void +// +// CPP-CHECK-LABEL: @_Z13test_svldr_ztPKv( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sme.ldr.zt(i32 0, ptr [[BASE:%.*]]) +// CPP-CHECK-NEXT: ret void +// +void test_svldr_zt(const void *base) __arm_streaming_compatible __arm_shared_za __arm_preserves_za { + svldr_zt(0, base); +} + +// STR ZT0 + +// CHECK-LABEL: @test_svstr_zt( +// CHECK-NEXT: entry: +// CHECK-NEXT: tail call void @llvm.aarch64.sme.str.zt(i32 0, ptr [[BASE:%.*]]) +// CHECK-NEXT: ret void +// +// CPP-CHECK-LABEL: @_Z13test_svstr_ztPv( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sme.str.zt(i32 0, ptr [[BASE:%.*]]) +// CPP-CHECK-NEXT: ret void +// +void test_svstr_zt(void *base) __arm_streaming_compatible __arm_shared_za __arm_preserves_za { + svstr_zt(0, base); +} diff --git a/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_imm.cpp b/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_imm.cpp index 4c35a238d9f9..70987ad395f7 100644 --- a/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_imm.cpp +++ b/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_imm.cpp @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple aarch64-none-linux-gnu \ -// RUN: -target-feature +sve2 -target-feature +sme2 -target-feature +sve -fsyntax-only -verify %s +// RUN: -target-feature +sve2 -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -fsyntax-only -verify %s // REQUIRES: aarch64-registered-target @@ -19,3 +19,8 @@ void test_outer_product(svbool_t pred, svint16_t s16, svuint16_t u16, svint32_t svbmops_za32_u32_m(4, pred, pred, u32, u32); // expected-error {{argument value 4 is outside the valid range [0, 3]}} svbmops_za32_s32_m(4, pred, pred, s32, s32); // expected-error {{argument value 4 is outside the valid range [0, 3]}} } + +void test_ldr_str_zt(const void *const_base, void *base) __arm_streaming_compatible __arm_shared_za __arm_preserves_za { + svldr_zt(1, const_base); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + svstr_zt(1, base); // expected-error {{argument value 1 is outside the valid range [0, 0]}} +} diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp index 136512db123b..2f49e9a6b37c 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -326,9 +326,14 @@ public: return false; } - template bool ImmToTile(SDValue N, SDValue &Imm) { + template + bool ImmToTile(SDValue N, SDValue &Imm) { if (auto *CI = dyn_cast(N)) { uint64_t C = CI->getZExtValue(); + + if (C > Max) + return false; + Imm = CurDAG->getRegister(BaseReg + C, MVT::Other); return true; } diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index cb093a161311..4379c3fde6f3 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -2753,6 +2753,20 @@ AArch64TargetLowering::EmitFill(MachineInstr &MI, MachineBasicBlock *BB) const { return BB; } +MachineBasicBlock *AArch64TargetLowering::EmitZTSpillFill(MachineInstr &MI, + MachineBasicBlock *BB, + bool IsSpill) const { + const TargetInstrInfo *TII = Subtarget->getInstrInfo(); + MachineInstrBuilder MIB; + unsigned Opc = IsSpill ? AArch64::STR_TX : AArch64::LDR_TX; + auto Rs = IsSpill ? RegState::Kill : RegState::Define; + MIB = BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(Opc)); + MIB.addReg(MI.getOperand(0).getReg(), Rs); + MIB.add(MI.getOperand(1)); // Base + MI.eraseFromParent(); // The pseudo is gone now. + return BB; +} + MachineBasicBlock * AArch64TargetLowering::EmitZAInstr(unsigned Opc, unsigned BaseReg, MachineInstr &MI, @@ -2869,6 +2883,10 @@ MachineBasicBlock *AArch64TargetLowering::EmitInstrWithCustomInserter( return EmitTileLoad(AArch64::LD1_MXIPXX_V_Q, AArch64::ZAQ0, MI, BB); case AArch64::LDR_ZA_PSEUDO: return EmitFill(MI, BB); + case AArch64::LDR_TX_PSEUDO: + return EmitZTSpillFill(MI, BB, /*IsSpill=*/false); + case AArch64::STR_TX_PSEUDO: + return EmitZTSpillFill(MI, BB, /*IsSpill=*/true); case AArch64::ZERO_M_PSEUDO: return EmitZero(MI, BB); } diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h index 25d7cb6d212d..009f8744b408 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h @@ -623,6 +623,8 @@ public: MachineBasicBlock *EmitZAInstr(unsigned Opc, unsigned BaseReg, MachineInstr &MI, MachineBasicBlock *BB, bool HasTile) const; + MachineBasicBlock *EmitZTSpillFill(MachineInstr &MI, MachineBasicBlock *BB, + bool IsSpill) const; MachineBasicBlock *EmitZero(MachineInstr &MI, MachineBasicBlock *BB) const; MachineBasicBlock * diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp index ed64a7b4984c..24ba9dd95004 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp @@ -440,6 +440,12 @@ AArch64RegisterInfo::getStrictlyReservedRegs(const MachineFunction &MF) const { Reserved.set(SubReg); } + if (MF.getSubtarget().hasSME2()) { + for (MCSubRegIterator SubReg(AArch64::ZT0, this, /*self=*/true); + SubReg.isValid(); ++SubReg) + Reserved.set(*SubReg); + } + markSuperRegs(Reserved, AArch64::FPCR); if (MF.getFunction().getCallingConv() == CallingConv::GRAAL) { diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td index bb9464a8d2e1..fcfa5f82a380 100644 --- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td @@ -541,8 +541,8 @@ defm UMOPS_MPPZZ_HtoS : sme2_int_mopx_tile<"umops", 0b101, int_aarch64_sme_umops def ZERO_T : sme2_zero_zt<"zero", 0b0001>; -def LDR_TX : sme2_spill_fill_vector<"ldr", 0b01111100>; -def STR_TX : sme2_spill_fill_vector<"str", 0b11111100>; +defm LDR_TX : sme2_spill_fill_vector<"ldr", 0b01111100, int_aarch64_sme_ldr_zt>; +defm STR_TX : sme2_spill_fill_vector<"str", 0b11111100, int_aarch64_sme_str_zt>; def MOVT_XTI : sme2_movt_zt_to_scalar<"movt", 0b0011111>; def MOVT_TIX : sme2_movt_scalar_to_zt<"movt", 0b0011111>; diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td index 6c9b1f11a4de..ef9c323e25bc 100644 --- a/llvm/lib/Target/AArch64/SMEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td @@ -10,11 +10,12 @@ // //===----------------------------------------------------------------------===// -def imm_to_tile8 : ComplexPattern", []>; -def imm_to_tile16 : ComplexPattern", []>; -def imm_to_tile32 : ComplexPattern", []>; -def imm_to_tile64 : ComplexPattern", []>; -def imm_to_tile128 : ComplexPattern", []>; +def imm_to_tile8 : ComplexPattern", []>; +def imm_to_tile16 : ComplexPattern", []>; +def imm_to_tile32 : ComplexPattern", []>; +def imm_to_tile64 : ComplexPattern", []>; +def imm_to_tile128 : ComplexPattern", []>; +def imm_to_zt : ComplexPattern", []>; def tileslice8 : ComplexPattern", []>; def tileslice16 : ComplexPattern", []>; @@ -3137,6 +3138,18 @@ class sme2_spill_fill_vector opc> let mayStore = opc{7}; } + +multiclass sme2_spill_fill_vector opc, SDPatternOperator op> { + def NAME : sme2_spill_fill_vector; + def NAME # _PSEUDO + : Pseudo<(outs), (ins ZTR:$ZTt, GPR64sp:$base), []>, Sched<[]> { + // Translated to actual instruction in AArch64ISelLowering.cpp + let usesCustomInserter = 1; + } + def : Pat<(op (imm_to_zt untyped:$tile), GPR64sp:$base), + (!cast(NAME # _PSEUDO) $tile, $base)>; +} + //===----------------------------------------------------------------------===/// // SME2 move to/from lookup table class sme2_movt_zt_to_scalar opc> diff --git a/llvm/test/CodeGen/AArch64/sme2-intrinsics-zt0.ll b/llvm/test/CodeGen/AArch64/sme2-intrinsics-zt0.ll new file mode 100644 index 000000000000..30205d86f2fb --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sme2-intrinsics-zt0.ll @@ -0,0 +1,27 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -verify-machineinstrs < %s | FileCheck %s + +; LDR + +define void @ldr_zt0(ptr %ptr) { +; CHECK-LABEL: ldr_zt0: +; CHECK: // %bb.0: +; CHECK-NEXT: ldr zt0, [x0] +; CHECK-NEXT: ret + call void @llvm.aarch64.sme.ldr.zt(i32 0, ptr %ptr) + ret void; +} + +; STR + +define void @str_zt0(ptr %ptr) { +; CHECK-LABEL: str_zt0: +; CHECK: // %bb.0: +; CHECK-NEXT: str zt0, [x0] +; CHECK-NEXT: ret + call void @llvm.aarch64.sme.str.zt(i32 0, ptr %ptr) + ret void; +} + +declare void @llvm.aarch64.sme.ldr.zt(i32, ptr) +declare void @llvm.aarch64.sme.str.zt(i32, ptr) -- GitLab From de55a2843fae6afd4b0589d81496096a4ff73cbd Mon Sep 17 00:00:00 2001 From: XinWang10 <108658776+XinWang10@users.noreply.github.com> Date: Fri, 1 Dec 2023 17:39:25 +0800 Subject: [PATCH 121/699] [X86][MC] Support Enc/Dec for EGPR for promoted BMI instructions (#73899) R16-R31 was added into GPRs in https://github.com/llvm/llvm-project/pull/70958, This patch supports the encoding/decoding for promoted BMI instructions in EVEX space. RFC: https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4 --- .../X86/MCTargetDesc/X86MCCodeEmitter.cpp | 6 +- llvm/lib/Target/X86/X86InstrArithmetic.td | 58 +++++-- llvm/lib/Target/X86/X86InstrMisc.td | 152 ++++++++++-------- llvm/lib/Target/X86/X86InstrShiftRotate.td | 59 ++++--- llvm/test/MC/Disassembler/X86/apx/andn.txt | 18 +++ llvm/test/MC/Disassembler/X86/apx/bextr.txt | 18 +++ llvm/test/MC/Disassembler/X86/apx/blsi.txt | 18 +++ llvm/test/MC/Disassembler/X86/apx/blsmsk.txt | 18 +++ llvm/test/MC/Disassembler/X86/apx/blsr.txt | 18 +++ llvm/test/MC/Disassembler/X86/apx/bzhi.txt | 18 +++ .../MC/Disassembler/X86/apx/evex-format.txt | 12 ++ llvm/test/MC/Disassembler/X86/apx/mulx.txt | 18 +++ llvm/test/MC/Disassembler/X86/apx/pdep.txt | 18 +++ llvm/test/MC/Disassembler/X86/apx/pext.txt | 18 +++ llvm/test/MC/Disassembler/X86/apx/rorx.txt | 18 +++ llvm/test/MC/Disassembler/X86/apx/sarx.txt | 18 +++ llvm/test/MC/Disassembler/X86/apx/shlx.txt | 18 +++ llvm/test/MC/Disassembler/X86/apx/shrx.txt | 18 +++ llvm/test/MC/X86/apx/andn-att.s | 20 +++ llvm/test/MC/X86/apx/andn-intel.s | 17 ++ llvm/test/MC/X86/apx/bextr-att.s | 20 +++ llvm/test/MC/X86/apx/bextr-intel.s | 17 ++ llvm/test/MC/X86/apx/blsi-att.s | 20 +++ llvm/test/MC/X86/apx/blsi-intel.s | 17 ++ llvm/test/MC/X86/apx/blsmsk-att.s | 20 +++ llvm/test/MC/X86/apx/blsmsk-intel.s | 17 ++ llvm/test/MC/X86/apx/blsr-att.s | 20 +++ llvm/test/MC/X86/apx/blsr-intel.s | 17 ++ llvm/test/MC/X86/apx/bzhi-att.s | 20 +++ llvm/test/MC/X86/apx/bzhi-intel.s | 17 ++ llvm/test/MC/X86/apx/evex-format-att.s | 12 ++ llvm/test/MC/X86/apx/evex-format-intel.s | 12 ++ llvm/test/MC/X86/apx/mulx-att.s | 20 +++ llvm/test/MC/X86/apx/mulx-intel.s | 17 ++ llvm/test/MC/X86/apx/pdep-att.s | 20 +++ llvm/test/MC/X86/apx/pdep-intel.s | 17 ++ llvm/test/MC/X86/apx/pext-att.s | 20 +++ llvm/test/MC/X86/apx/pext-intel.s | 17 ++ llvm/test/MC/X86/apx/rorx-att.s | 20 +++ llvm/test/MC/X86/apx/rorx-intel.s | 17 ++ llvm/test/MC/X86/apx/sarx-att.s | 20 +++ llvm/test/MC/X86/apx/sarx-intel.s | 17 ++ llvm/test/MC/X86/apx/shlx-att.s | 20 +++ llvm/test/MC/X86/apx/shlx-intel.s | 17 ++ llvm/test/MC/X86/apx/shrx-att.s | 20 +++ llvm/test/MC/X86/apx/shrx-intel.s | 17 ++ llvm/test/TableGen/x86-fold-tables.inc | 26 +++ 47 files changed, 942 insertions(+), 110 deletions(-) create mode 100644 llvm/test/MC/Disassembler/X86/apx/andn.txt create mode 100644 llvm/test/MC/Disassembler/X86/apx/bextr.txt create mode 100644 llvm/test/MC/Disassembler/X86/apx/blsi.txt create mode 100644 llvm/test/MC/Disassembler/X86/apx/blsmsk.txt create mode 100644 llvm/test/MC/Disassembler/X86/apx/blsr.txt create mode 100644 llvm/test/MC/Disassembler/X86/apx/bzhi.txt create mode 100644 llvm/test/MC/Disassembler/X86/apx/mulx.txt create mode 100644 llvm/test/MC/Disassembler/X86/apx/pdep.txt create mode 100644 llvm/test/MC/Disassembler/X86/apx/pext.txt create mode 100644 llvm/test/MC/Disassembler/X86/apx/rorx.txt create mode 100644 llvm/test/MC/Disassembler/X86/apx/sarx.txt create mode 100644 llvm/test/MC/Disassembler/X86/apx/shlx.txt create mode 100644 llvm/test/MC/Disassembler/X86/apx/shrx.txt create mode 100644 llvm/test/MC/X86/apx/andn-att.s create mode 100644 llvm/test/MC/X86/apx/andn-intel.s create mode 100644 llvm/test/MC/X86/apx/bextr-att.s create mode 100644 llvm/test/MC/X86/apx/bextr-intel.s create mode 100644 llvm/test/MC/X86/apx/blsi-att.s create mode 100644 llvm/test/MC/X86/apx/blsi-intel.s create mode 100644 llvm/test/MC/X86/apx/blsmsk-att.s create mode 100644 llvm/test/MC/X86/apx/blsmsk-intel.s create mode 100644 llvm/test/MC/X86/apx/blsr-att.s create mode 100644 llvm/test/MC/X86/apx/blsr-intel.s create mode 100644 llvm/test/MC/X86/apx/bzhi-att.s create mode 100644 llvm/test/MC/X86/apx/bzhi-intel.s create mode 100644 llvm/test/MC/X86/apx/mulx-att.s create mode 100644 llvm/test/MC/X86/apx/mulx-intel.s create mode 100644 llvm/test/MC/X86/apx/pdep-att.s create mode 100644 llvm/test/MC/X86/apx/pdep-intel.s create mode 100644 llvm/test/MC/X86/apx/pext-att.s create mode 100644 llvm/test/MC/X86/apx/pext-intel.s create mode 100644 llvm/test/MC/X86/apx/rorx-att.s create mode 100644 llvm/test/MC/X86/apx/rorx-intel.s create mode 100644 llvm/test/MC/X86/apx/sarx-att.s create mode 100644 llvm/test/MC/X86/apx/sarx-intel.s create mode 100644 llvm/test/MC/X86/apx/shlx-att.s create mode 100644 llvm/test/MC/X86/apx/shlx-intel.s create mode 100644 llvm/test/MC/X86/apx/shrx-att.s create mode 100644 llvm/test/MC/X86/apx/shrx-intel.s diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp index 1f130c22298e..b6ebbcf56aef 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp @@ -1115,10 +1115,10 @@ X86MCCodeEmitter::emitVEXOpcodePrefix(int MemOperand, const MCInst &MI, case X86II::MRMSrcMem4VOp3: { // Instruction format for 4VOp3: // src1(ModR/M), MemAddr, src3(VEX_4V) - Prefix.setR(MI, CurOp++); + Prefix.setRR2(MI, CurOp++); Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg); Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg); - Prefix.set4V(MI, CurOp + X86::AddrNumOperands); + Prefix.set4VV2(MI, CurOp + X86::AddrNumOperands); break; } case X86II::MRMSrcMemOp4: { @@ -1189,7 +1189,7 @@ X86MCCodeEmitter::emitVEXOpcodePrefix(int MemOperand, const MCInst &MI, // src1(ModR/M), src2(ModR/M), src3(VEX_4V) Prefix.setRR2(MI, CurOp++); Prefix.setBB2(MI, CurOp++); - Prefix.set4V(MI, CurOp++); + Prefix.set4VV2(MI, CurOp++); break; } case X86II::MRMSrcRegOp4: { diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td index 48188da291de..56cbc13eaaec 100644 --- a/llvm/lib/Target/X86/X86InstrArithmetic.td +++ b/llvm/lib/Target/X86/X86InstrArithmetic.td @@ -1289,21 +1289,34 @@ def : Pat<(X86testpat (loadi64 addr:$src1), i64relocImmSExt32_su:$src2), // multiclass bmi_andn { +let Predicates = [HasBMI, NoEGPR] in { def rr : I<0xF2, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), - !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), - [(set RC:$dst, EFLAGS, (X86and_flag (not RC:$src1), RC:$src2))]>, - Sched<[sched]>; + !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set RC:$dst, EFLAGS, (X86and_flag (not RC:$src1), RC:$src2))]>, + VEX_4V, Sched<[sched]>; def rm : I<0xF2, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), - !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), - [(set RC:$dst, EFLAGS, - (X86and_flag (not RC:$src1), (ld_frag addr:$src2)))]>, - Sched<[sched.Folded, sched.ReadAfterFold]>; + !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set RC:$dst, EFLAGS, + (X86and_flag (not RC:$src1), (ld_frag addr:$src2)))]>, + VEX_4V, Sched<[sched.Folded, sched.ReadAfterFold]>; +} +let Predicates = [HasBMI, HasEGPR, In64BitMode] in { + def rr_EVEX : I<0xF2, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), + !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set RC:$dst, EFLAGS, (X86and_flag (not RC:$src1), RC:$src2))]>, + EVEX_4V, Sched<[sched]>; + def rm_EVEX : I<0xF2, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), + !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set RC:$dst, EFLAGS, + (X86and_flag (not RC:$src1), (ld_frag addr:$src2)))]>, + EVEX_4V, Sched<[sched.Folded, sched.ReadAfterFold]>; +} } // Complexity is reduced to give and with immediate a chance to match first. -let Predicates = [HasBMI], Defs = [EFLAGS], AddedComplexity = -6 in { - defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32, WriteALU>, T8PS, VEX_4V; - defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64, WriteALU>, T8PS, VEX_4V, REX_W; +let Defs = [EFLAGS], AddedComplexity = -6 in { + defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32, WriteALU>, T8PS; + defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64, WriteALU>, T8PS, REX_W; } let Predicates = [HasBMI], AddedComplexity = -6 in { @@ -1323,6 +1336,7 @@ let Predicates = [HasBMI], AddedComplexity = -6 in { multiclass bmi_mulx { let hasSideEffects = 0 in { +let Predicates = [HasBMI2, NoEGPR] in { def rr : I<0xF6, MRMSrcReg, (outs RC:$dst1, RC:$dst2), (ins RC:$src), !strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"), []>, T8XD, VEX_4V, Sched<[WriteIMulH, sched]>; @@ -1346,15 +1360,27 @@ let hasSideEffects = 0 in { def Hrm : PseudoI<(outs RC:$dst), (ins x86memop:$src), []>, Sched<[sched.Folded]>; } +let Predicates = [HasBMI2, HasEGPR, In64BitMode] in + def rr#_EVEX : I<0xF6, MRMSrcReg, (outs RC:$dst1, RC:$dst2), (ins RC:$src), + !strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"), + []>, T8XD, EVEX_4V, Sched<[WriteIMulH, sched]>; +let Predicates = [HasBMI2, HasEGPR, In64BitMode], mayLoad = 1 in + def rm#_EVEX : I<0xF6, MRMSrcMem, (outs RC:$dst1, RC:$dst2), (ins x86memop:$src), + !strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"), + []>, T8XD, EVEX_4V, + Sched<[WriteIMulHLd, sched.Folded, + // Memory operand. + ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault, + // Implicit read of EDX/RDX + sched.ReadAfterFold]>; } - -let Predicates = [HasBMI2] in { - let Uses = [EDX] in - defm MULX32 : bmi_mulx<"mulx{l}", GR32, i32mem, WriteMULX32>; - let Uses = [RDX] in - defm MULX64 : bmi_mulx<"mulx{q}", GR64, i64mem, WriteMULX64>, REX_W; } +let Uses = [EDX] in + defm MULX32 : bmi_mulx<"mulx{l}", GR32, i32mem, WriteMULX32>; +let Uses = [RDX] in + defm MULX64 : bmi_mulx<"mulx{q}", GR64, i64mem, WriteMULX64>, REX_W; + //===----------------------------------------------------------------------===// // ADCX and ADOX Instructions // diff --git a/llvm/lib/Target/X86/X86InstrMisc.td b/llvm/lib/Target/X86/X86InstrMisc.td index 32aa82fc93ca..764d4bd6da2a 100644 --- a/llvm/lib/Target/X86/X86InstrMisc.td +++ b/llvm/lib/Target/X86/X86InstrMisc.td @@ -1214,19 +1214,19 @@ let Predicates = [HasBMI], Defs = [EFLAGS] in { multiclass bmi_bls { + X86FoldableSchedWrite sched, string Suffix = ""> { let hasSideEffects = 0 in { - def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src), - !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>, - T8PS, VEX_4V, Sched<[sched]>; + def rr#Suffix : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src), + !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>, + T8PS, VEX_4V, Sched<[sched]>; let mayLoad = 1 in - def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src), - !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>, - T8PS, VEX_4V, Sched<[sched.Folded]>; + def rm#Suffix : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src), + !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>, + T8PS, VEX_4V, Sched<[sched.Folded]>; } } -let Predicates = [HasBMI], Defs = [EFLAGS] in { +let Predicates = [HasBMI, NoEGPR], Defs = [EFLAGS] in { defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem, WriteBLS>; defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem, WriteBLS>, REX_W; defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem, WriteBLS>; @@ -1235,6 +1235,15 @@ let Predicates = [HasBMI], Defs = [EFLAGS] in { defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem, WriteBLS>, REX_W; } +let Predicates = [HasBMI, HasEGPR], Defs = [EFLAGS] in { + defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem, WriteBLS, "_EVEX">, EVEX; + defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem, WriteBLS, "_EVEX">, REX_W, EVEX; + defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem, WriteBLS, "_EVEX">, EVEX; + defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem, WriteBLS, "_EVEX">, REX_W, EVEX; + defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem, WriteBLS, "_EVEX">, EVEX; + defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem, WriteBLS, "_EVEX">, REX_W, EVEX; +} + //===----------------------------------------------------------------------===// // Pattern fragments to auto generate BMI instructions. //===----------------------------------------------------------------------===// @@ -1292,56 +1301,50 @@ let Predicates = [HasBMI] in { (BLSI64rr GR64:$src)>; } -multiclass bmi_bextr opc, string mnemonic, RegisterClass RC, - X86MemOperand x86memop, SDNode OpNode, - PatFrag ld_frag, X86FoldableSchedWrite Sched> { - def rr : I, - T8PS, VEX, Sched<[Sched]>; - def rm : I, T8PS, VEX, - Sched<[Sched.Folded, - // x86memop:$src1 - ReadDefault, ReadDefault, ReadDefault, ReadDefault, - ReadDefault, - // RC:$src2 - Sched.ReadAfterFold]>; +multiclass bmi4VOp3_base opc, string mnemonic, RegisterClass RC, + X86MemOperand x86memop, SDPatternOperator OpNode, + PatFrag ld_frag, X86FoldableSchedWrite Sched, + string Suffix = ""> { + def rr#Suffix : I, + T8PS, VEX, Sched<[Sched]>; +let mayLoad = 1 in + def rm#Suffix : I, T8PS, VEX, + Sched<[Sched.Folded, + // x86memop:$src1 + ReadDefault, ReadDefault, ReadDefault, ReadDefault, + ReadDefault, + // RC:$src2 + Sched.ReadAfterFold]>; } -let Predicates = [HasBMI], Defs = [EFLAGS] in { - defm BEXTR32 : bmi_bextr<0xF7, "bextr{l}", GR32, i32mem, - X86bextr, loadi32, WriteBEXTR>; - defm BEXTR64 : bmi_bextr<0xF7, "bextr{q}", GR64, i64mem, - X86bextr, loadi64, WriteBEXTR>, REX_W; -} - -multiclass bmi_bzhi opc, string mnemonic, RegisterClass RC, - X86MemOperand x86memop, SDNode Int, - PatFrag ld_frag, X86FoldableSchedWrite Sched> { - def rr : I, - T8PS, VEX, Sched<[Sched]>; - def rm : I, T8PS, VEX, - Sched<[Sched.Folded, - // x86memop:$src1 - ReadDefault, ReadDefault, ReadDefault, ReadDefault, - ReadDefault, - // RC:$src2 - Sched.ReadAfterFold]>; -} - -let Predicates = [HasBMI2], Defs = [EFLAGS] in { - defm BZHI32 : bmi_bzhi<0xF5, "bzhi{l}", GR32, i32mem, - X86bzhi, loadi32, WriteBZHI>; - defm BZHI64 : bmi_bzhi<0xF5, "bzhi{q}", GR64, i64mem, - X86bzhi, loadi64, WriteBZHI>, REX_W; +let Predicates = [HasBMI, NoEGPR], Defs = [EFLAGS] in { + defm BEXTR32 : bmi4VOp3_base<0xF7, "bextr{l}", GR32, i32mem, + X86bextr, loadi32, WriteBEXTR>; + defm BEXTR64 : bmi4VOp3_base<0xF7, "bextr{q}", GR64, i64mem, + X86bextr, loadi64, WriteBEXTR>, REX_W; +} +let Predicates = [HasBMI2, NoEGPR], Defs = [EFLAGS] in { + defm BZHI32 : bmi4VOp3_base<0xF5, "bzhi{l}", GR32, i32mem, + X86bzhi, loadi32, WriteBZHI>; + defm BZHI64 : bmi4VOp3_base<0xF5, "bzhi{q}", GR64, i64mem, + X86bzhi, loadi64, WriteBZHI>, REX_W; +} +let Predicates = [HasBMI, HasEGPR], Defs = [EFLAGS] in { + defm BEXTR32 : bmi4VOp3_base<0xF7, "bextr{l}", GR32, i32mem, + X86bextr, loadi32, WriteBEXTR, "_EVEX">, EVEX; + defm BEXTR64 : bmi4VOp3_base<0xF7, "bextr{q}", GR64, i64mem, + X86bextr, loadi64, WriteBEXTR, "_EVEX">, EVEX, REX_W; +} +let Predicates = [HasBMI2, HasEGPR], Defs = [EFLAGS] in { + defm BZHI32 : bmi4VOp3_base<0xF5, "bzhi{l}", GR32, i32mem, + X86bzhi, loadi32, WriteBZHI, "_EVEX">, EVEX; + defm BZHI64 : bmi4VOp3_base<0xF5, "bzhi{q}", GR64, i64mem, + X86bzhi, loadi64, WriteBZHI, "_EVEX">, EVEX, REX_W; } def CountTrailingOnes : SDNodeXForm { - def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), - !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), - [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>, - VEX_4V, Sched<[WriteALU]>; - def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), - !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), - [(set RC:$dst, (OpNode RC:$src1, (ld_frag addr:$src2)))]>, - VEX_4V, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>; -} - -let Predicates = [HasBMI2] in { + X86MemOperand x86memop, SDPatternOperator OpNode, + PatFrag ld_frag, string Suffix = ""> { + def rr#Suffix : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), + !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>, + VEX_4V, Sched<[WriteALU]>; + def rm#Suffix : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), + !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set RC:$dst, (OpNode RC:$src1, (ld_frag addr:$src2)))]>, + VEX_4V, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>; +} + +let Predicates = [HasBMI2, NoEGPR] in { defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem, X86pdep, loadi32>, T8XD; defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem, @@ -1406,6 +1409,17 @@ let Predicates = [HasBMI2] in { X86pext, loadi64>, T8XS, REX_W; } +let Predicates = [HasBMI2, HasEGPR] in { + defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem, + X86pdep, loadi32, "_EVEX">, T8XD, EVEX; + defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem, + X86pdep, loadi64, "_EVEX">, T8XD, REX_W, EVEX; + defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem, + X86pext, loadi32, "_EVEX">, T8XS, EVEX; + defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem, + X86pext, loadi64, "_EVEX">, T8XS, REX_W, EVEX; +} + //===----------------------------------------------------------------------===// // Lightweight Profiling Instructions diff --git a/llvm/lib/Target/X86/X86InstrShiftRotate.td b/llvm/lib/Target/X86/X86InstrShiftRotate.td index e416e4495e22..48bf23f8cbf7 100644 --- a/llvm/lib/Target/X86/X86InstrShiftRotate.td +++ b/llvm/lib/Target/X86/X86InstrShiftRotate.td @@ -824,38 +824,40 @@ def ROT64L2R_imm8 : SDNodeXForm { +multiclass bmi_rotate { let hasSideEffects = 0 in { - def ri : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, u8imm:$src2), - !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), - []>, TAXD, VEX, Sched<[WriteShift]>; + def ri#Suffix : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, u8imm:$src2), + !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, + TAXD, VEX, Sched<[WriteShift]>; let mayLoad = 1 in - def mi : Ii8<0xF0, MRMSrcMem, (outs RC:$dst), - (ins x86memop:$src1, u8imm:$src2), - !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), - []>, TAXD, VEX, Sched<[WriteShiftLd]>; + def mi#Suffix : Ii8<0xF0, MRMSrcMem, (outs RC:$dst), + (ins x86memop:$src1, u8imm:$src2), + !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, + TAXD, VEX, Sched<[WriteShiftLd]>; } } -multiclass bmi_shift { +multiclass bmi_shift { let hasSideEffects = 0 in { - def rr : I<0xF7, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2), - !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, - VEX, Sched<[WriteShift]>; + def rr#Suffix : I<0xF7, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2), + !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, + VEX, Sched<[WriteShift]>; let mayLoad = 1 in - def rm : I<0xF7, MRMSrcMem4VOp3, - (outs RC:$dst), (ins x86memop:$src1, RC:$src2), - !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, - VEX, Sched<[WriteShift.Folded, - // x86memop:$src1 - ReadDefault, ReadDefault, ReadDefault, ReadDefault, - ReadDefault, - // RC:$src2 - WriteShift.ReadAfterFold]>; + def rm#Suffix : I<0xF7, MRMSrcMem4VOp3, + (outs RC:$dst), (ins x86memop:$src1, RC:$src2), + !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, + VEX, Sched<[WriteShift.Folded, + // x86memop:$src1 + ReadDefault, ReadDefault, ReadDefault, ReadDefault, + ReadDefault, + // RC:$src2 + WriteShift.ReadAfterFold]>; } } -let Predicates = [HasBMI2] in { +let Predicates = [HasBMI2, NoEGPR] in { defm RORX32 : bmi_rotate<"rorx{l}", GR32, i32mem>; defm RORX64 : bmi_rotate<"rorx{q}", GR64, i64mem>, REX_W; defm SARX32 : bmi_shift<"sarx{l}", GR32, i32mem>, T8XS; @@ -864,7 +866,20 @@ let Predicates = [HasBMI2] in { defm SHRX64 : bmi_shift<"shrx{q}", GR64, i64mem>, T8XD, REX_W; defm SHLX32 : bmi_shift<"shlx{l}", GR32, i32mem>, T8PD; defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem>, T8PD, REX_W; +} +let Predicates = [HasBMI2, HasEGPR] in { + defm RORX32 : bmi_rotate<"rorx{l}", GR32, i32mem, "_EVEX">, EVEX; + defm RORX64 : bmi_rotate<"rorx{q}", GR64, i64mem, "_EVEX">, REX_W, EVEX; + defm SARX32 : bmi_shift<"sarx{l}", GR32, i32mem, "_EVEX">, T8XS, EVEX; + defm SARX64 : bmi_shift<"sarx{q}", GR64, i64mem, "_EVEX">, T8XS, REX_W, EVEX; + defm SHRX32 : bmi_shift<"shrx{l}", GR32, i32mem, "_EVEX">, T8XD, EVEX; + defm SHRX64 : bmi_shift<"shrx{q}", GR64, i64mem, "_EVEX">, T8XD, REX_W, EVEX; + defm SHLX32 : bmi_shift<"shlx{l}", GR32, i32mem, "_EVEX">, T8PD, EVEX; + defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem, "_EVEX">, T8PD, REX_W, EVEX; +} + +let Predicates = [HasBMI2] in { // Prefer RORX which is non-destructive and doesn't update EFLAGS. let AddedComplexity = 10 in { def : Pat<(rotr GR32:$src, (i8 imm:$shamt)), diff --git a/llvm/test/MC/Disassembler/X86/apx/andn.txt b/llvm/test/MC/Disassembler/X86/apx/andn.txt new file mode 100644 index 000000000000..8b943d2a0ac4 --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/andn.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: andnl %r18d, %r22d, %r26d +# INTEL: andn r26d, r22d, r18d +0x62,0x6a,0x4c,0x00,0xf2,0xd2 + +# ATT: andnq %r19, %r23, %r27 +# INTEL: andn r27, r23, r19 +0x62,0x6a,0xc4,0x00,0xf2,0xdb + +# ATT: andnl 291(%r28,%r29,4), %r18d, %r22d +# INTEL: andn r22d, r18d, dword ptr [r28 + 4*r29 + 291] +0x62,0x8a,0x68,0x00,0xf2,0xb4,0xac,0x23,0x01,0x00,0x00 + +# ATT: andnq 291(%r28,%r29,4), %r19, %r23 +# INTEL: andn r23, r19, qword ptr [r28 + 4*r29 + 291] +0x62,0x8a,0xe0,0x00,0xf2,0xbc,0xac,0x23,0x01,0x00,0x00 diff --git a/llvm/test/MC/Disassembler/X86/apx/bextr.txt b/llvm/test/MC/Disassembler/X86/apx/bextr.txt new file mode 100644 index 000000000000..abd92864b315 --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/bextr.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: bextrl %r18d, %r22d, %r26d +# INTEL: bextr r26d, r22d, r18d +0x62,0x6a,0x6c,0x00,0xf7,0xd6 + +# ATT: bextrl %r18d, 291(%r28,%r29,4), %r22d +# INTEL: bextr r22d, dword ptr [r28 + 4*r29 + 291], r18d +0x62,0x8a,0x68,0x00,0xf7,0xb4,0xac,0x23,0x01,0x00,0x00 + +# ATT: bextrq %r19, %r23, %r27 +# INTEL: bextr r27, r23, r19 +0x62,0x6a,0xe4,0x00,0xf7,0xdf + +# ATT: bextrq %r19, 291(%r28,%r29,4), %r23 +# INTEL: bextr r23, qword ptr [r28 + 4*r29 + 291], r19 +0x62,0x8a,0xe0,0x00,0xf7,0xbc,0xac,0x23,0x01,0x00,0x00 diff --git a/llvm/test/MC/Disassembler/X86/apx/blsi.txt b/llvm/test/MC/Disassembler/X86/apx/blsi.txt new file mode 100644 index 000000000000..254ec90caea5 --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/blsi.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: blsil %r18d, %r22d +# INTEL: blsi r22d, r18d +0x62,0xfa,0x4c,0x00,0xf3,0xda + +# ATT: blsiq %r19, %r23 +# INTEL: blsi r23, r19 +0x62,0xfa,0xc4,0x00,0xf3,0xdb + +# ATT: blsil 291(%r28,%r29,4), %r18d +# INTEL: blsi r18d, dword ptr [r28 + 4*r29 + 291] +0x62,0x9a,0x68,0x00,0xf3,0x9c,0xac,0x23,0x01,0x00,0x00 + +# ATT: blsiq 291(%r28,%r29,4), %r19 +# INTEL: blsi r19, qword ptr [r28 + 4*r29 + 291] +0x62,0x9a,0xe0,0x00,0xf3,0x9c,0xac,0x23,0x01,0x00,0x00 diff --git a/llvm/test/MC/Disassembler/X86/apx/blsmsk.txt b/llvm/test/MC/Disassembler/X86/apx/blsmsk.txt new file mode 100644 index 000000000000..5e47d3d3d625 --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/blsmsk.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: blsmskl %r18d, %r22d +# INTEL: blsmsk r22d, r18d +0x62,0xfa,0x4c,0x00,0xf3,0xd2 + +# ATT: blsmskq %r19, %r23 +# INTEL: blsmsk r23, r19 +0x62,0xfa,0xc4,0x00,0xf3,0xd3 + +# ATT: blsmskl 291(%r28,%r29,4), %r18d +# INTEL: blsmsk r18d, dword ptr [r28 + 4*r29 + 291] +0x62,0x9a,0x68,0x00,0xf3,0x94,0xac,0x23,0x01,0x00,0x00 + +# ATT: blsmskq 291(%r28,%r29,4), %r19 +# INTEL: blsmsk r19, qword ptr [r28 + 4*r29 + 291] +0x62,0x9a,0xe0,0x00,0xf3,0x94,0xac,0x23,0x01,0x00,0x00 diff --git a/llvm/test/MC/Disassembler/X86/apx/blsr.txt b/llvm/test/MC/Disassembler/X86/apx/blsr.txt new file mode 100644 index 000000000000..37df4306da26 --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/blsr.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: blsrl %r18d, %r22d +# INTEL: blsr r22d, r18d +0x62,0xfa,0x4c,0x00,0xf3,0xca + +# ATT: blsrq %r19, %r23 +# INTEL: blsr r23, r19 +0x62,0xfa,0xc4,0x00,0xf3,0xcb + +# ATT: blsrl 291(%r28,%r29,4), %r18d +# INTEL: blsr r18d, dword ptr [r28 + 4*r29 + 291] +0x62,0x9a,0x68,0x00,0xf3,0x8c,0xac,0x23,0x01,0x00,0x00 + +# ATT: blsrq 291(%r28,%r29,4), %r19 +# INTEL: blsr r19, qword ptr [r28 + 4*r29 + 291] +0x62,0x9a,0xe0,0x00,0xf3,0x8c,0xac,0x23,0x01,0x00,0x00 diff --git a/llvm/test/MC/Disassembler/X86/apx/bzhi.txt b/llvm/test/MC/Disassembler/X86/apx/bzhi.txt new file mode 100644 index 000000000000..44f496e3cc08 --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/bzhi.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: bzhil %r18d, %r22d, %r26d +# INTEL: bzhi r26d, r22d, r18d +0x62,0x6a,0x6c,0x00,0xf5,0xd6 + +# ATT: bzhil %r18d, 291(%r28,%r29,4), %r22d +# INTEL: bzhi r22d, dword ptr [r28 + 4*r29 + 291], r18d +0x62,0x8a,0x68,0x00,0xf5,0xb4,0xac,0x23,0x01,0x00,0x00 + +# ATT: bzhiq %r19, %r23, %r27 +# INTEL: bzhi r27, r23, r19 +0x62,0x6a,0xe4,0x00,0xf5,0xdf + +# ATT: bzhiq %r19, 291(%r28,%r29,4), %r23 +# INTEL: bzhi r23, qword ptr [r28 + 4*r29 + 291], r19 +0x62,0x8a,0xe0,0x00,0xf5,0xbc,0xac,0x23,0x01,0x00,0x00 diff --git a/llvm/test/MC/Disassembler/X86/apx/evex-format.txt b/llvm/test/MC/Disassembler/X86/apx/evex-format.txt index ee2c2c5bdf90..389b22cb4a22 100644 --- a/llvm/test/MC/Disassembler/X86/apx/evex-format.txt +++ b/llvm/test/MC/Disassembler/X86/apx/evex-format.txt @@ -62,8 +62,20 @@ # INTEL: vpslldq zmm0, zmmword ptr [r16 + r17], 0 0x62,0xf9,0x79,0x48,0x73,0x3c,0x08,0x00 +## MRMSrcMem4VOp3 + +# ATT: bzhiq %r19, 291(%r28,%r29,4), %r23 +# INTEL: bzhi r23, qword ptr [r28 + 4*r29 + 291], r19 +0x62,0x8a,0xe0,0x00,0xf5,0xbc,0xac,0x23,0x01,0x00,0x00 + ## MRMDestReg # ATT: vextractps $1, %xmm16, %r16d # INTEL: vextractps r16d, xmm16, 1 0x62,0xeb,0x7d,0x08,0x17,0xc0,0x01 + +## MRMSrcReg4VOp3 + +# ATT: bzhiq %r19, %r23, %r27 +# INTEL: bzhi r27, r23, r19 +0x62,0x6a,0xe4,0x00,0xf5,0xdf diff --git a/llvm/test/MC/Disassembler/X86/apx/mulx.txt b/llvm/test/MC/Disassembler/X86/apx/mulx.txt new file mode 100644 index 000000000000..5d9b53b99a71 --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/mulx.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: mulxl %r18d, %r22d, %r26d +# INTEL: mulx r26d, r22d, r18d +0x62,0x6a,0x4f,0x00,0xf6,0xd2 + +# ATT: mulxq %r19, %r23, %r27 +# INTEL: mulx r27, r23, r19 +0x62,0x6a,0xc7,0x00,0xf6,0xdb + +# ATT: mulxl 291(%r28,%r29,4), %r18d, %r22d +# INTEL: mulx r22d, r18d, dword ptr [r28 + 4*r29 + 291] +0x62,0x8a,0x6b,0x00,0xf6,0xb4,0xac,0x23,0x01,0x00,0x00 + +# ATT: mulxq 291(%r28,%r29,4), %r19, %r23 +# INTEL: mulx r23, r19, qword ptr [r28 + 4*r29 + 291] +0x62,0x8a,0xe3,0x00,0xf6,0xbc,0xac,0x23,0x01,0x00,0x00 diff --git a/llvm/test/MC/Disassembler/X86/apx/pdep.txt b/llvm/test/MC/Disassembler/X86/apx/pdep.txt new file mode 100644 index 000000000000..87268fe5e27d --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/pdep.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: pdepl %r18d, %r22d, %r26d +# INTEL: pdep r26d, r22d, r18d +0x62,0x6a,0x4f,0x00,0xf5,0xd2 + +# ATT: pdepq %r19, %r23, %r27 +# INTEL: pdep r27, r23, r19 +0x62,0x6a,0xc7,0x00,0xf5,0xdb + +# ATT: pdepl 291(%r28,%r29,4), %r18d, %r22d +# INTEL: pdep r22d, r18d, dword ptr [r28 + 4*r29 + 291] +0x62,0x8a,0x6b,0x00,0xf5,0xb4,0xac,0x23,0x01,0x00,0x00 + +# ATT: pdepq 291(%r28,%r29,4), %r19, %r23 +# INTEL: pdep r23, r19, qword ptr [r28 + 4*r29 + 291] +0x62,0x8a,0xe3,0x00,0xf5,0xbc,0xac,0x23,0x01,0x00,0x00 diff --git a/llvm/test/MC/Disassembler/X86/apx/pext.txt b/llvm/test/MC/Disassembler/X86/apx/pext.txt new file mode 100644 index 000000000000..6c5860aa8128 --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/pext.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: pextl %r18d, %r22d, %r26d +# INTEL: pext r26d, r22d, r18d +0x62,0x6a,0x4e,0x00,0xf5,0xd2 + +# ATT: pextq %r19, %r23, %r27 +# INTEL: pext r27, r23, r19 +0x62,0x6a,0xc6,0x00,0xf5,0xdb + +# ATT: pextl 291(%r28,%r29,4), %r18d, %r22d +# INTEL: pext r22d, r18d, dword ptr [r28 + 4*r29 + 291] +0x62,0x8a,0x6a,0x00,0xf5,0xb4,0xac,0x23,0x01,0x00,0x00 + +# ATT: pextq 291(%r28,%r29,4), %r19, %r23 +# INTEL: pext r23, r19, qword ptr [r28 + 4*r29 + 291] +0x62,0x8a,0xe2,0x00,0xf5,0xbc,0xac,0x23,0x01,0x00,0x00 diff --git a/llvm/test/MC/Disassembler/X86/apx/rorx.txt b/llvm/test/MC/Disassembler/X86/apx/rorx.txt new file mode 100644 index 000000000000..9860deaea86b --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/rorx.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: rorxl $123, %r18d, %r22d +# INTEL: rorx r22d, r18d, 123 +0x62,0xeb,0x7f,0x08,0xf0,0xf2,0x7b + +# ATT: rorxq $123, %r19, %r23 +# INTEL: rorx r23, r19, 123 +0x62,0xeb,0xff,0x08,0xf0,0xfb,0x7b + +# ATT: rorxl $123, 291(%r28,%r29,4), %r18d +# INTEL: rorx r18d, dword ptr [r28 + 4*r29 + 291], 123 +0x62,0x8b,0x7b,0x08,0xf0,0x94,0xac,0x23,0x01,0x00,0x00,0x7b + +# ATT: rorxq $123, 291(%r28,%r29,4), %r19 +# INTEL: rorx r19, qword ptr [r28 + 4*r29 + 291], 123 +0x62,0x8b,0xfb,0x08,0xf0,0x9c,0xac,0x23,0x01,0x00,0x00,0x7b diff --git a/llvm/test/MC/Disassembler/X86/apx/sarx.txt b/llvm/test/MC/Disassembler/X86/apx/sarx.txt new file mode 100644 index 000000000000..20018f4d4b12 --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/sarx.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: sarxl %r18d, %r22d, %r26d +# INTEL: sarx r26d, r22d, r18d +0x62,0x6a,0x6e,0x00,0xf7,0xd6 + +# ATT: sarxl %r18d, 291(%r28,%r29,4), %r22d +# INTEL: sarx r22d, dword ptr [r28 + 4*r29 + 291], r18d +0x62,0x8a,0x6a,0x00,0xf7,0xb4,0xac,0x23,0x01,0x00,0x00 + +# ATT: sarxq %r19, %r23, %r27 +# INTEL: sarx r27, r23, r19 +0x62,0x6a,0xe6,0x00,0xf7,0xdf + +# ATT: sarxq %r19, 291(%r28,%r29,4), %r23 +# INTEL: sarx r23, qword ptr [r28 + 4*r29 + 291], r19 +0x62,0x8a,0xe2,0x00,0xf7,0xbc,0xac,0x23,0x01,0x00,0x00 diff --git a/llvm/test/MC/Disassembler/X86/apx/shlx.txt b/llvm/test/MC/Disassembler/X86/apx/shlx.txt new file mode 100644 index 000000000000..f6d6250bd063 --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/shlx.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: shlxl %r18d, %r22d, %r26d +# INTEL: shlx r26d, r22d, r18d +0x62,0x6a,0x6d,0x00,0xf7,0xd6 + +# ATT: shlxl %r18d, 291(%r28,%r29,4), %r22d +# INTEL: shlx r22d, dword ptr [r28 + 4*r29 + 291], r18d +0x62,0x8a,0x69,0x00,0xf7,0xb4,0xac,0x23,0x01,0x00,0x00 + +# ATT: shlxq %r19, %r23, %r27 +# INTEL: shlx r27, r23, r19 +0x62,0x6a,0xe5,0x00,0xf7,0xdf + +# ATT: shlxq %r19, 291(%r28,%r29,4), %r23 +# INTEL: shlx r23, qword ptr [r28 + 4*r29 + 291], r19 +0x62,0x8a,0xe1,0x00,0xf7,0xbc,0xac,0x23,0x01,0x00,0x00 diff --git a/llvm/test/MC/Disassembler/X86/apx/shrx.txt b/llvm/test/MC/Disassembler/X86/apx/shrx.txt new file mode 100644 index 000000000000..09750e05c127 --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/shrx.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: shrxl %r18d, %r22d, %r26d +# INTEL: shrx r26d, r22d, r18d +0x62,0x6a,0x6f,0x00,0xf7,0xd6 + +# ATT: shrxl %r18d, 291(%r28,%r29,4), %r22d +# INTEL: shrx r22d, dword ptr [r28 + 4*r29 + 291], r18d +0x62,0x8a,0x6b,0x00,0xf7,0xb4,0xac,0x23,0x01,0x00,0x00 + +# ATT: shrxq %r19, %r23, %r27 +# INTEL: shrx r27, r23, r19 +0x62,0x6a,0xe7,0x00,0xf7,0xdf + +# ATT: shrxq %r19, 291(%r28,%r29,4), %r23 +# INTEL: shrx r23, qword ptr [r28 + 4*r29 + 291], r19 +0x62,0x8a,0xe3,0x00,0xf7,0xbc,0xac,0x23,0x01,0x00,0x00 diff --git a/llvm/test/MC/X86/apx/andn-att.s b/llvm/test/MC/X86/apx/andn-att.s new file mode 100644 index 000000000000..d68cee8bcf1f --- /dev/null +++ b/llvm/test/MC/X86/apx/andn-att.s @@ -0,0 +1,20 @@ +# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s +# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR + +# ERROR-COUNT-4: error: +# ERROR-NOT: error: +# CHECK: andnl %r18d, %r22d, %r26d +# CHECK: encoding: [0x62,0x6a,0x4c,0x00,0xf2,0xd2] + andnl %r18d, %r22d, %r26d + +# CHECK: andnq %r19, %r23, %r27 +# CHECK: encoding: [0x62,0x6a,0xc4,0x00,0xf2,0xdb] + andnq %r19, %r23, %r27 + +# CHECK: andnl 291(%r28,%r29,4), %r18d, %r22d +# CHECK: encoding: [0x62,0x8a,0x68,0x00,0xf2,0xb4,0xac,0x23,0x01,0x00,0x00] + andnl 291(%r28,%r29,4), %r18d, %r22d + +# CHECK: andnq 291(%r28,%r29,4), %r19, %r23 +# CHECK: encoding: [0x62,0x8a,0xe0,0x00,0xf2,0xbc,0xac,0x23,0x01,0x00,0x00] + andnq 291(%r28,%r29,4), %r19, %r23 diff --git a/llvm/test/MC/X86/apx/andn-intel.s b/llvm/test/MC/X86/apx/andn-intel.s new file mode 100644 index 000000000000..583e6e763b1e --- /dev/null +++ b/llvm/test/MC/X86/apx/andn-intel.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +# CHECK: andn r26d, r22d, r18d +# CHECK: encoding: [0x62,0x6a,0x4c,0x00,0xf2,0xd2] + andn r26d, r22d, r18d + +# CHECK: andn r27, r23, r19 +# CHECK: encoding: [0x62,0x6a,0xc4,0x00,0xf2,0xdb] + andn r27, r23, r19 + +# CHECK: andn r22d, r18d, dword ptr [r28 + 4*r29 + 291] +# CHECK: encoding: [0x62,0x8a,0x68,0x00,0xf2,0xb4,0xac,0x23,0x01,0x00,0x00] + andn r22d, r18d, dword ptr [r28 + 4*r29 + 291] + +# CHECK: andn r23, r19, qword ptr [r28 + 4*r29 + 291] +# CHECK: encoding: [0x62,0x8a,0xe0,0x00,0xf2,0xbc,0xac,0x23,0x01,0x00,0x00] + andn r23, r19, qword ptr [r28 + 4*r29 + 291] diff --git a/llvm/test/MC/X86/apx/bextr-att.s b/llvm/test/MC/X86/apx/bextr-att.s new file mode 100644 index 000000000000..6095ffa389a3 --- /dev/null +++ b/llvm/test/MC/X86/apx/bextr-att.s @@ -0,0 +1,20 @@ +# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s +# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR + +# ERROR-COUNT-4: error: +# ERROR-NOT: error: +# CHECK: bextrl %r18d, %r22d, %r26d +# CHECK: encoding: [0x62,0x6a,0x6c,0x00,0xf7,0xd6] + bextrl %r18d, %r22d, %r26d + +# CHECK: bextrl %r18d, 291(%r28,%r29,4), %r22d +# CHECK: encoding: [0x62,0x8a,0x68,0x00,0xf7,0xb4,0xac,0x23,0x01,0x00,0x00] + bextrl %r18d, 291(%r28,%r29,4), %r22d + +# CHECK: bextrq %r19, %r23, %r27 +# CHECK: encoding: [0x62,0x6a,0xe4,0x00,0xf7,0xdf] + bextrq %r19, %r23, %r27 + +# CHECK: bextrq %r19, 291(%r28,%r29,4), %r23 +# CHECK: encoding: [0x62,0x8a,0xe0,0x00,0xf7,0xbc,0xac,0x23,0x01,0x00,0x00] + bextrq %r19, 291(%r28,%r29,4), %r23 diff --git a/llvm/test/MC/X86/apx/bextr-intel.s b/llvm/test/MC/X86/apx/bextr-intel.s new file mode 100644 index 000000000000..af70c00c1d63 --- /dev/null +++ b/llvm/test/MC/X86/apx/bextr-intel.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +# CHECK: bextr r26d, r22d, r18d +# CHECK: encoding: [0x62,0x6a,0x6c,0x00,0xf7,0xd6] + bextr r26d, r22d, r18d + +# CHECK: bextr r22d, dword ptr [r28 + 4*r29 + 291], r18d +# CHECK: encoding: [0x62,0x8a,0x68,0x00,0xf7,0xb4,0xac,0x23,0x01,0x00,0x00] + bextr r22d, dword ptr [r28 + 4*r29 + 291], r18d + +# CHECK: bextr r27, r23, r19 +# CHECK: encoding: [0x62,0x6a,0xe4,0x00,0xf7,0xdf] + bextr r27, r23, r19 + +# CHECK: bextr r23, qword ptr [r28 + 4*r29 + 291], r19 +# CHECK: encoding: [0x62,0x8a,0xe0,0x00,0xf7,0xbc,0xac,0x23,0x01,0x00,0x00] + bextr r23, qword ptr [r28 + 4*r29 + 291], r19 diff --git a/llvm/test/MC/X86/apx/blsi-att.s b/llvm/test/MC/X86/apx/blsi-att.s new file mode 100644 index 000000000000..65b2fd2b4d09 --- /dev/null +++ b/llvm/test/MC/X86/apx/blsi-att.s @@ -0,0 +1,20 @@ +# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s +# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR + +# ERROR-COUNT-4: error: +# ERROR-NOT: error: +# CHECK: blsil %r18d, %r22d +# CHECK: encoding: [0x62,0xfa,0x4c,0x00,0xf3,0xda] + blsil %r18d, %r22d + +# CHECK: blsiq %r19, %r23 +# CHECK: encoding: [0x62,0xfa,0xc4,0x00,0xf3,0xdb] + blsiq %r19, %r23 + +# CHECK: blsil 291(%r28,%r29,4), %r18d +# CHECK: encoding: [0x62,0x9a,0x68,0x00,0xf3,0x9c,0xac,0x23,0x01,0x00,0x00] + blsil 291(%r28,%r29,4), %r18d + +# CHECK: blsiq 291(%r28,%r29,4), %r19 +# CHECK: encoding: [0x62,0x9a,0xe0,0x00,0xf3,0x9c,0xac,0x23,0x01,0x00,0x00] + blsiq 291(%r28,%r29,4), %r19 diff --git a/llvm/test/MC/X86/apx/blsi-intel.s b/llvm/test/MC/X86/apx/blsi-intel.s new file mode 100644 index 000000000000..edf5711cc74b --- /dev/null +++ b/llvm/test/MC/X86/apx/blsi-intel.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +# CHECK: blsi r22d, r18d +# CHECK: encoding: [0x62,0xfa,0x4c,0x00,0xf3,0xda] + blsi r22d, r18d + +# CHECK: blsi r23, r19 +# CHECK: encoding: [0x62,0xfa,0xc4,0x00,0xf3,0xdb] + blsi r23, r19 + +# CHECK: blsi r18d, dword ptr [r28 + 4*r29 + 291] +# CHECK: encoding: [0x62,0x9a,0x68,0x00,0xf3,0x9c,0xac,0x23,0x01,0x00,0x00] + blsi r18d, dword ptr [r28 + 4*r29 + 291] + +# CHECK: blsi r19, qword ptr [r28 + 4*r29 + 291] +# CHECK: encoding: [0x62,0x9a,0xe0,0x00,0xf3,0x9c,0xac,0x23,0x01,0x00,0x00] + blsi r19, qword ptr [r28 + 4*r29 + 291] diff --git a/llvm/test/MC/X86/apx/blsmsk-att.s b/llvm/test/MC/X86/apx/blsmsk-att.s new file mode 100644 index 000000000000..710fcabddcc3 --- /dev/null +++ b/llvm/test/MC/X86/apx/blsmsk-att.s @@ -0,0 +1,20 @@ +# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s +# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR + +# ERROR-COUNT-4: error: +# ERROR-NOT: error: +# CHECK: blsmskl %r18d, %r22d +# CHECK: encoding: [0x62,0xfa,0x4c,0x00,0xf3,0xd2] + blsmskl %r18d, %r22d + +# CHECK: blsmskq %r19, %r23 +# CHECK: encoding: [0x62,0xfa,0xc4,0x00,0xf3,0xd3] + blsmskq %r19, %r23 + +# CHECK: blsmskl 291(%r28,%r29,4), %r18d +# CHECK: encoding: [0x62,0x9a,0x68,0x00,0xf3,0x94,0xac,0x23,0x01,0x00,0x00] + blsmskl 291(%r28,%r29,4), %r18d + +# CHECK: blsmskq 291(%r28,%r29,4), %r19 +# CHECK: encoding: [0x62,0x9a,0xe0,0x00,0xf3,0x94,0xac,0x23,0x01,0x00,0x00] + blsmskq 291(%r28,%r29,4), %r19 diff --git a/llvm/test/MC/X86/apx/blsmsk-intel.s b/llvm/test/MC/X86/apx/blsmsk-intel.s new file mode 100644 index 000000000000..bb8197d3d410 --- /dev/null +++ b/llvm/test/MC/X86/apx/blsmsk-intel.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +# CHECK: blsmsk r22d, r18d +# CHECK: encoding: [0x62,0xfa,0x4c,0x00,0xf3,0xd2] + blsmsk r22d, r18d + +# CHECK: blsmsk r23, r19 +# CHECK: encoding: [0x62,0xfa,0xc4,0x00,0xf3,0xd3] + blsmsk r23, r19 + +# CHECK: blsmsk r18d, dword ptr [r28 + 4*r29 + 291] +# CHECK: encoding: [0x62,0x9a,0x68,0x00,0xf3,0x94,0xac,0x23,0x01,0x00,0x00] + blsmsk r18d, dword ptr [r28 + 4*r29 + 291] + +# CHECK: blsmsk r19, qword ptr [r28 + 4*r29 + 291] +# CHECK: encoding: [0x62,0x9a,0xe0,0x00,0xf3,0x94,0xac,0x23,0x01,0x00,0x00] + blsmsk r19, qword ptr [r28 + 4*r29 + 291] diff --git a/llvm/test/MC/X86/apx/blsr-att.s b/llvm/test/MC/X86/apx/blsr-att.s new file mode 100644 index 000000000000..c9ca56149cf1 --- /dev/null +++ b/llvm/test/MC/X86/apx/blsr-att.s @@ -0,0 +1,20 @@ +# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s +# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR + +# ERROR-COUNT-4: error: +# ERROR-NOT: error: +# CHECK: blsrl %r18d, %r22d +# CHECK: encoding: [0x62,0xfa,0x4c,0x00,0xf3,0xca] + blsrl %r18d, %r22d + +# CHECK: blsrq %r19, %r23 +# CHECK: encoding: [0x62,0xfa,0xc4,0x00,0xf3,0xcb] + blsrq %r19, %r23 + +# CHECK: blsrl 291(%r28,%r29,4), %r18d +# CHECK: encoding: [0x62,0x9a,0x68,0x00,0xf3,0x8c,0xac,0x23,0x01,0x00,0x00] + blsrl 291(%r28,%r29,4), %r18d + +# CHECK: blsrq 291(%r28,%r29,4), %r19 +# CHECK: encoding: [0x62,0x9a,0xe0,0x00,0xf3,0x8c,0xac,0x23,0x01,0x00,0x00] + blsrq 291(%r28,%r29,4), %r19 diff --git a/llvm/test/MC/X86/apx/blsr-intel.s b/llvm/test/MC/X86/apx/blsr-intel.s new file mode 100644 index 000000000000..acbfb8196461 --- /dev/null +++ b/llvm/test/MC/X86/apx/blsr-intel.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +# CHECK: blsr r22d, r18d +# CHECK: encoding: [0x62,0xfa,0x4c,0x00,0xf3,0xca] + blsr r22d, r18d + +# CHECK: blsr r23, r19 +# CHECK: encoding: [0x62,0xfa,0xc4,0x00,0xf3,0xcb] + blsr r23, r19 + +# CHECK: blsr r18d, dword ptr [r28 + 4*r29 + 291] +# CHECK: encoding: [0x62,0x9a,0x68,0x00,0xf3,0x8c,0xac,0x23,0x01,0x00,0x00] + blsr r18d, dword ptr [r28 + 4*r29 + 291] + +# CHECK: blsr r19, qword ptr [r28 + 4*r29 + 291] +# CHECK: encoding: [0x62,0x9a,0xe0,0x00,0xf3,0x8c,0xac,0x23,0x01,0x00,0x00] + blsr r19, qword ptr [r28 + 4*r29 + 291] diff --git a/llvm/test/MC/X86/apx/bzhi-att.s b/llvm/test/MC/X86/apx/bzhi-att.s new file mode 100644 index 000000000000..635cfa14e6b4 --- /dev/null +++ b/llvm/test/MC/X86/apx/bzhi-att.s @@ -0,0 +1,20 @@ +# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s +# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR + +# ERROR-COUNT-4: error: +# ERROR-NOT: error: +# CHECK: bzhil %r18d, %r22d, %r26d +# CHECK: encoding: [0x62,0x6a,0x6c,0x00,0xf5,0xd6] + bzhil %r18d, %r22d, %r26d + +# CHECK: bzhil %r18d, 291(%r28,%r29,4), %r22d +# CHECK: encoding: [0x62,0x8a,0x68,0x00,0xf5,0xb4,0xac,0x23,0x01,0x00,0x00] + bzhil %r18d, 291(%r28,%r29,4), %r22d + +# CHECK: bzhiq %r19, %r23, %r27 +# CHECK: encoding: [0x62,0x6a,0xe4,0x00,0xf5,0xdf] + bzhiq %r19, %r23, %r27 + +# CHECK: bzhiq %r19, 291(%r28,%r29,4), %r23 +# CHECK: encoding: [0x62,0x8a,0xe0,0x00,0xf5,0xbc,0xac,0x23,0x01,0x00,0x00] + bzhiq %r19, 291(%r28,%r29,4), %r23 diff --git a/llvm/test/MC/X86/apx/bzhi-intel.s b/llvm/test/MC/X86/apx/bzhi-intel.s new file mode 100644 index 000000000000..f7ab72dd717e --- /dev/null +++ b/llvm/test/MC/X86/apx/bzhi-intel.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +# CHECK: bzhi r26d, r22d, r18d +# CHECK: encoding: [0x62,0x6a,0x6c,0x00,0xf5,0xd6] + bzhi r26d, r22d, r18d + +# CHECK: bzhi r22d, dword ptr [r28 + 4*r29 + 291], r18d +# CHECK: encoding: [0x62,0x8a,0x68,0x00,0xf5,0xb4,0xac,0x23,0x01,0x00,0x00] + bzhi r22d, dword ptr [r28 + 4*r29 + 291], r18d + +# CHECK: bzhi r27, r23, r19 +# CHECK: encoding: [0x62,0x6a,0xe4,0x00,0xf5,0xdf] + bzhi r27, r23, r19 + +# CHECK: bzhi r23, qword ptr [r28 + 4*r29 + 291], r19 +# CHECK: encoding: [0x62,0x8a,0xe0,0x00,0xf5,0xbc,0xac,0x23,0x01,0x00,0x00] + bzhi r23, qword ptr [r28 + 4*r29 + 291], r19 diff --git a/llvm/test/MC/X86/apx/evex-format-att.s b/llvm/test/MC/X86/apx/evex-format-att.s index aedd09e7e698..0b2e860d6ba0 100644 --- a/llvm/test/MC/X86/apx/evex-format-att.s +++ b/llvm/test/MC/X86/apx/evex-format-att.s @@ -60,8 +60,20 @@ # CHECK: encoding: [0x62,0xf9,0x79,0x48,0x73,0x3c,0x08,0x00] vpslldq $0, (%r16,%r17), %zmm0 +## MRMSrcMem4VOp3 + +# CHECK: bzhiq %r19, 291(%r28,%r29,4), %r23 +# CHECK: encoding: [0x62,0x8a,0xe0,0x00,0xf5,0xbc,0xac,0x23,0x01,0x00,0x00] + bzhiq %r19, 291(%r28,%r29,4), %r23 + ## MRMDestReg # CHECK: vextractps $1, %xmm16, %r16d # CHECK: encoding: [0x62,0xeb,0x7d,0x08,0x17,0xc0,0x01] vextractps $1, %xmm16, %r16d + +## MRMSrcReg4VOp3 + +# CHECK: bzhiq %r19, %r23, %r27 +# CHECK: encoding: [0x62,0x6a,0xe4,0x00,0xf5,0xdf] + bzhiq %r19, %r23, %r27 diff --git a/llvm/test/MC/X86/apx/evex-format-intel.s b/llvm/test/MC/X86/apx/evex-format-intel.s index aa11a879f4b4..ececb7137b11 100644 --- a/llvm/test/MC/X86/apx/evex-format-intel.s +++ b/llvm/test/MC/X86/apx/evex-format-intel.s @@ -60,8 +60,20 @@ # CHECK: encoding: [0x62,0xf9,0x79,0x48,0x73,0x3c,0x08,0x00] vpslldq zmm0, zmmword ptr [r16 + r17], 0 +## MRMSrcMem4VOp3 + +# CHECK: bzhi r23, qword ptr [r28 + 4*r29 + 291], r19 +# CHECK: encoding: [0x62,0x8a,0xe0,0x00,0xf5,0xbc,0xac,0x23,0x01,0x00,0x00] + bzhi r23, qword ptr [r28 + 4*r29 + 291], r19 + ## MRMDestReg # CHECK: vextractps r16d, xmm16, 1 # CHECK: encoding: [0x62,0xeb,0x7d,0x08,0x17,0xc0,0x01] vextractps r16d, xmm16, 1 + +## MRMSrcReg4VOp3 + +# CHECK: bzhi r27, r23, r19 +# CHECK: encoding: [0x62,0x6a,0xe4,0x00,0xf5,0xdf] + bzhi r27, r23, r19 diff --git a/llvm/test/MC/X86/apx/mulx-att.s b/llvm/test/MC/X86/apx/mulx-att.s new file mode 100644 index 000000000000..976a79f469cd --- /dev/null +++ b/llvm/test/MC/X86/apx/mulx-att.s @@ -0,0 +1,20 @@ +# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s +# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR + +# ERROR-COUNT-4: error: +# ERROR-NOT: error: +# CHECK: mulxl %r18d, %r22d, %r26d +# CHECK: encoding: [0x62,0x6a,0x4f,0x00,0xf6,0xd2] + mulxl %r18d, %r22d, %r26d + +# CHECK: mulxq %r19, %r23, %r27 +# CHECK: encoding: [0x62,0x6a,0xc7,0x00,0xf6,0xdb] + mulxq %r19, %r23, %r27 + +# CHECK: mulxl 291(%r28,%r29,4), %r18d, %r22d +# CHECK: encoding: [0x62,0x8a,0x6b,0x00,0xf6,0xb4,0xac,0x23,0x01,0x00,0x00] + mulxl 291(%r28,%r29,4), %r18d, %r22d + +# CHECK: mulxq 291(%r28,%r29,4), %r19, %r23 +# CHECK: encoding: [0x62,0x8a,0xe3,0x00,0xf6,0xbc,0xac,0x23,0x01,0x00,0x00] + mulxq 291(%r28,%r29,4), %r19, %r23 diff --git a/llvm/test/MC/X86/apx/mulx-intel.s b/llvm/test/MC/X86/apx/mulx-intel.s new file mode 100644 index 000000000000..3db587502915 --- /dev/null +++ b/llvm/test/MC/X86/apx/mulx-intel.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +# CHECK: mulx r26d, r22d, r18d +# CHECK: encoding: [0x62,0x6a,0x4f,0x00,0xf6,0xd2] + mulx r26d, r22d, r18d + +# CHECK: mulx r27, r23, r19 +# CHECK: encoding: [0x62,0x6a,0xc7,0x00,0xf6,0xdb] + mulx r27, r23, r19 + +# CHECK: mulx r22d, r18d, dword ptr [r28 + 4*r29 + 291] +# CHECK: encoding: [0x62,0x8a,0x6b,0x00,0xf6,0xb4,0xac,0x23,0x01,0x00,0x00] + mulx r22d, r18d, dword ptr [r28 + 4*r29 + 291] + +# CHECK: mulx r23, r19, qword ptr [r28 + 4*r29 + 291] +# CHECK: encoding: [0x62,0x8a,0xe3,0x00,0xf6,0xbc,0xac,0x23,0x01,0x00,0x00] + mulx r23, r19, qword ptr [r28 + 4*r29 + 291] diff --git a/llvm/test/MC/X86/apx/pdep-att.s b/llvm/test/MC/X86/apx/pdep-att.s new file mode 100644 index 000000000000..c319b17e47f6 --- /dev/null +++ b/llvm/test/MC/X86/apx/pdep-att.s @@ -0,0 +1,20 @@ +# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s +# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR + +# ERROR-COUNT-4: error: +# ERROR-NOT: error: +# CHECK: pdepl %r18d, %r22d, %r26d +# CHECK: encoding: [0x62,0x6a,0x4f,0x00,0xf5,0xd2] + pdepl %r18d, %r22d, %r26d + +# CHECK: pdepq %r19, %r23, %r27 +# CHECK: encoding: [0x62,0x6a,0xc7,0x00,0xf5,0xdb] + pdepq %r19, %r23, %r27 + +# CHECK: pdepl 291(%r28,%r29,4), %r18d, %r22d +# CHECK: encoding: [0x62,0x8a,0x6b,0x00,0xf5,0xb4,0xac,0x23,0x01,0x00,0x00] + pdepl 291(%r28,%r29,4), %r18d, %r22d + +# CHECK: pdepq 291(%r28,%r29,4), %r19, %r23 +# CHECK: encoding: [0x62,0x8a,0xe3,0x00,0xf5,0xbc,0xac,0x23,0x01,0x00,0x00] + pdepq 291(%r28,%r29,4), %r19, %r23 diff --git a/llvm/test/MC/X86/apx/pdep-intel.s b/llvm/test/MC/X86/apx/pdep-intel.s new file mode 100644 index 000000000000..0f9e828c021c --- /dev/null +++ b/llvm/test/MC/X86/apx/pdep-intel.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +# CHECK: pdep r26d, r22d, r18d +# CHECK: encoding: [0x62,0x6a,0x4f,0x00,0xf5,0xd2] + pdep r26d, r22d, r18d + +# CHECK: pdep r27, r23, r19 +# CHECK: encoding: [0x62,0x6a,0xc7,0x00,0xf5,0xdb] + pdep r27, r23, r19 + +# CHECK: pdep r22d, r18d, dword ptr [r28 + 4*r29 + 291] +# CHECK: encoding: [0x62,0x8a,0x6b,0x00,0xf5,0xb4,0xac,0x23,0x01,0x00,0x00] + pdep r22d, r18d, dword ptr [r28 + 4*r29 + 291] + +# CHECK: pdep r23, r19, qword ptr [r28 + 4*r29 + 291] +# CHECK: encoding: [0x62,0x8a,0xe3,0x00,0xf5,0xbc,0xac,0x23,0x01,0x00,0x00] + pdep r23, r19, qword ptr [r28 + 4*r29 + 291] diff --git a/llvm/test/MC/X86/apx/pext-att.s b/llvm/test/MC/X86/apx/pext-att.s new file mode 100644 index 000000000000..c07fa1ac2082 --- /dev/null +++ b/llvm/test/MC/X86/apx/pext-att.s @@ -0,0 +1,20 @@ +# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s +# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR + +# ERROR-COUNT-4: error: +# ERROR-NOT: error: +# CHECK: pextl %r18d, %r22d, %r26d +# CHECK: encoding: [0x62,0x6a,0x4e,0x00,0xf5,0xd2] + pextl %r18d, %r22d, %r26d + +# CHECK: pextq %r19, %r23, %r27 +# CHECK: encoding: [0x62,0x6a,0xc6,0x00,0xf5,0xdb] + pextq %r19, %r23, %r27 + +# CHECK: pextl 291(%r28,%r29,4), %r18d, %r22d +# CHECK: encoding: [0x62,0x8a,0x6a,0x00,0xf5,0xb4,0xac,0x23,0x01,0x00,0x00] + pextl 291(%r28,%r29,4), %r18d, %r22d + +# CHECK: pextq 291(%r28,%r29,4), %r19, %r23 +# CHECK: encoding: [0x62,0x8a,0xe2,0x00,0xf5,0xbc,0xac,0x23,0x01,0x00,0x00] + pextq 291(%r28,%r29,4), %r19, %r23 diff --git a/llvm/test/MC/X86/apx/pext-intel.s b/llvm/test/MC/X86/apx/pext-intel.s new file mode 100644 index 000000000000..9a7e7d93094a --- /dev/null +++ b/llvm/test/MC/X86/apx/pext-intel.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +# CHECK: pext r26d, r22d, r18d +# CHECK: encoding: [0x62,0x6a,0x4e,0x00,0xf5,0xd2] + pext r26d, r22d, r18d + +# CHECK: pext r27, r23, r19 +# CHECK: encoding: [0x62,0x6a,0xc6,0x00,0xf5,0xdb] + pext r27, r23, r19 + +# CHECK: pext r22d, r18d, dword ptr [r28 + 4*r29 + 291] +# CHECK: encoding: [0x62,0x8a,0x6a,0x00,0xf5,0xb4,0xac,0x23,0x01,0x00,0x00] + pext r22d, r18d, dword ptr [r28 + 4*r29 + 291] + +# CHECK: pext r23, r19, qword ptr [r28 + 4*r29 + 291] +# CHECK: encoding: [0x62,0x8a,0xe2,0x00,0xf5,0xbc,0xac,0x23,0x01,0x00,0x00] + pext r23, r19, qword ptr [r28 + 4*r29 + 291] diff --git a/llvm/test/MC/X86/apx/rorx-att.s b/llvm/test/MC/X86/apx/rorx-att.s new file mode 100644 index 000000000000..fb613d95c7cb --- /dev/null +++ b/llvm/test/MC/X86/apx/rorx-att.s @@ -0,0 +1,20 @@ +# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s +# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR + +# ERROR-COUNT-4: error: +# ERROR-NOT: error: +# CHECK: rorxl $123, %r18d, %r22d +# CHECK: encoding: [0x62,0xeb,0x7f,0x08,0xf0,0xf2,0x7b] + rorxl $123, %r18d, %r22d + +# CHECK: rorxq $123, %r19, %r23 +# CHECK: encoding: [0x62,0xeb,0xff,0x08,0xf0,0xfb,0x7b] + rorxq $123, %r19, %r23 + +# CHECK: rorxl $123, 291(%r28,%r29,4), %r18d +# CHECK: encoding: [0x62,0x8b,0x7b,0x08,0xf0,0x94,0xac,0x23,0x01,0x00,0x00,0x7b] + rorxl $123, 291(%r28,%r29,4), %r18d + +# CHECK: rorxq $123, 291(%r28,%r29,4), %r19 +# CHECK: encoding: [0x62,0x8b,0xfb,0x08,0xf0,0x9c,0xac,0x23,0x01,0x00,0x00,0x7b] + rorxq $123, 291(%r28,%r29,4), %r19 diff --git a/llvm/test/MC/X86/apx/rorx-intel.s b/llvm/test/MC/X86/apx/rorx-intel.s new file mode 100644 index 000000000000..d3e63559cba5 --- /dev/null +++ b/llvm/test/MC/X86/apx/rorx-intel.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +# CHECK: rorx r22d, r18d, 123 +# CHECK: encoding: [0x62,0xeb,0x7f,0x08,0xf0,0xf2,0x7b] + rorx r22d, r18d, 123 + +# CHECK: rorx r23, r19, 123 +# CHECK: encoding: [0x62,0xeb,0xff,0x08,0xf0,0xfb,0x7b] + rorx r23, r19, 123 + +# CHECK: rorx r18d, dword ptr [r28 + 4*r29 + 291], 123 +# CHECK: encoding: [0x62,0x8b,0x7b,0x08,0xf0,0x94,0xac,0x23,0x01,0x00,0x00,0x7b] + rorx r18d, dword ptr [r28 + 4*r29 + 291], 123 + +# CHECK: rorx r19, qword ptr [r28 + 4*r29 + 291], 123 +# CHECK: encoding: [0x62,0x8b,0xfb,0x08,0xf0,0x9c,0xac,0x23,0x01,0x00,0x00,0x7b] + rorx r19, qword ptr [r28 + 4*r29 + 291], 123 diff --git a/llvm/test/MC/X86/apx/sarx-att.s b/llvm/test/MC/X86/apx/sarx-att.s new file mode 100644 index 000000000000..a174903d976c --- /dev/null +++ b/llvm/test/MC/X86/apx/sarx-att.s @@ -0,0 +1,20 @@ +# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s +# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR + +# ERROR-COUNT-4: error: +# ERROR-NOT: error: +# CHECK: sarxl %r18d, %r22d, %r26d +# CHECK: encoding: [0x62,0x6a,0x6e,0x00,0xf7,0xd6] + sarxl %r18d, %r22d, %r26d + +# CHECK: sarxl %r18d, 291(%r28,%r29,4), %r22d +# CHECK: encoding: [0x62,0x8a,0x6a,0x00,0xf7,0xb4,0xac,0x23,0x01,0x00,0x00] + sarxl %r18d, 291(%r28,%r29,4), %r22d + +# CHECK: sarxq %r19, %r23, %r27 +# CHECK: encoding: [0x62,0x6a,0xe6,0x00,0xf7,0xdf] + sarxq %r19, %r23, %r27 + +# CHECK: sarxq %r19, 291(%r28,%r29,4), %r23 +# CHECK: encoding: [0x62,0x8a,0xe2,0x00,0xf7,0xbc,0xac,0x23,0x01,0x00,0x00] + sarxq %r19, 291(%r28,%r29,4), %r23 diff --git a/llvm/test/MC/X86/apx/sarx-intel.s b/llvm/test/MC/X86/apx/sarx-intel.s new file mode 100644 index 000000000000..962b6ec313b9 --- /dev/null +++ b/llvm/test/MC/X86/apx/sarx-intel.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +# CHECK: sarx r26d, r22d, r18d +# CHECK: encoding: [0x62,0x6a,0x6e,0x00,0xf7,0xd6] + sarx r26d, r22d, r18d + +# CHECK: sarx r22d, dword ptr [r28 + 4*r29 + 291], r18d +# CHECK: encoding: [0x62,0x8a,0x6a,0x00,0xf7,0xb4,0xac,0x23,0x01,0x00,0x00] + sarx r22d, dword ptr [r28 + 4*r29 + 291], r18d + +# CHECK: sarx r27, r23, r19 +# CHECK: encoding: [0x62,0x6a,0xe6,0x00,0xf7,0xdf] + sarx r27, r23, r19 + +# CHECK: sarx r23, qword ptr [r28 + 4*r29 + 291], r19 +# CHECK: encoding: [0x62,0x8a,0xe2,0x00,0xf7,0xbc,0xac,0x23,0x01,0x00,0x00] + sarx r23, qword ptr [r28 + 4*r29 + 291], r19 diff --git a/llvm/test/MC/X86/apx/shlx-att.s b/llvm/test/MC/X86/apx/shlx-att.s new file mode 100644 index 000000000000..4e28119f0830 --- /dev/null +++ b/llvm/test/MC/X86/apx/shlx-att.s @@ -0,0 +1,20 @@ +# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s +# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR + +# ERROR-COUNT-4: error: +# ERROR-NOT: error: +# CHECK: shlxl %r18d, %r22d, %r26d +# CHECK: encoding: [0x62,0x6a,0x6d,0x00,0xf7,0xd6] + shlxl %r18d, %r22d, %r26d + +# CHECK: shlxl %r18d, 291(%r28,%r29,4), %r22d +# CHECK: encoding: [0x62,0x8a,0x69,0x00,0xf7,0xb4,0xac,0x23,0x01,0x00,0x00] + shlxl %r18d, 291(%r28,%r29,4), %r22d + +# CHECK: shlxq %r19, %r23, %r27 +# CHECK: encoding: [0x62,0x6a,0xe5,0x00,0xf7,0xdf] + shlxq %r19, %r23, %r27 + +# CHECK: shlxq %r19, 291(%r28,%r29,4), %r23 +# CHECK: encoding: [0x62,0x8a,0xe1,0x00,0xf7,0xbc,0xac,0x23,0x01,0x00,0x00] + shlxq %r19, 291(%r28,%r29,4), %r23 diff --git a/llvm/test/MC/X86/apx/shlx-intel.s b/llvm/test/MC/X86/apx/shlx-intel.s new file mode 100644 index 000000000000..9f16918a712d --- /dev/null +++ b/llvm/test/MC/X86/apx/shlx-intel.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +# CHECK: shlx r26d, r22d, r18d +# CHECK: encoding: [0x62,0x6a,0x6d,0x00,0xf7,0xd6] + shlx r26d, r22d, r18d + +# CHECK: shlx r22d, dword ptr [r28 + 4*r29 + 291], r18d +# CHECK: encoding: [0x62,0x8a,0x69,0x00,0xf7,0xb4,0xac,0x23,0x01,0x00,0x00] + shlx r22d, dword ptr [r28 + 4*r29 + 291], r18d + +# CHECK: shlx r27, r23, r19 +# CHECK: encoding: [0x62,0x6a,0xe5,0x00,0xf7,0xdf] + shlx r27, r23, r19 + +# CHECK: shlx r23, qword ptr [r28 + 4*r29 + 291], r19 +# CHECK: encoding: [0x62,0x8a,0xe1,0x00,0xf7,0xbc,0xac,0x23,0x01,0x00,0x00] + shlx r23, qword ptr [r28 + 4*r29 + 291], r19 diff --git a/llvm/test/MC/X86/apx/shrx-att.s b/llvm/test/MC/X86/apx/shrx-att.s new file mode 100644 index 000000000000..d9bb5f84af73 --- /dev/null +++ b/llvm/test/MC/X86/apx/shrx-att.s @@ -0,0 +1,20 @@ +# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s +# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR + +# ERROR-COUNT-4: error: +# ERROR-NOT: error: +# CHECK: shrxl %r18d, %r22d, %r26d +# CHECK: encoding: [0x62,0x6a,0x6f,0x00,0xf7,0xd6] + shrxl %r18d, %r22d, %r26d + +# CHECK: shrxl %r18d, 291(%r28,%r29,4), %r22d +# CHECK: encoding: [0x62,0x8a,0x6b,0x00,0xf7,0xb4,0xac,0x23,0x01,0x00,0x00] + shrxl %r18d, 291(%r28,%r29,4), %r22d + +# CHECK: shrxq %r19, %r23, %r27 +# CHECK: encoding: [0x62,0x6a,0xe7,0x00,0xf7,0xdf] + shrxq %r19, %r23, %r27 + +# CHECK: shrxq %r19, 291(%r28,%r29,4), %r23 +# CHECK: encoding: [0x62,0x8a,0xe3,0x00,0xf7,0xbc,0xac,0x23,0x01,0x00,0x00] + shrxq %r19, 291(%r28,%r29,4), %r23 diff --git a/llvm/test/MC/X86/apx/shrx-intel.s b/llvm/test/MC/X86/apx/shrx-intel.s new file mode 100644 index 000000000000..385c530a1108 --- /dev/null +++ b/llvm/test/MC/X86/apx/shrx-intel.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +# CHECK: shrx r26d, r22d, r18d +# CHECK: encoding: [0x62,0x6a,0x6f,0x00,0xf7,0xd6] + shrx r26d, r22d, r18d + +# CHECK: shrx r22d, dword ptr [r28 + 4*r29 + 291], r18d +# CHECK: encoding: [0x62,0x8a,0x6b,0x00,0xf7,0xb4,0xac,0x23,0x01,0x00,0x00] + shrx r22d, dword ptr [r28 + 4*r29 + 291], r18d + +# CHECK: shrx r27, r23, r19 +# CHECK: encoding: [0x62,0x6a,0xe7,0x00,0xf7,0xdf] + shrx r27, r23, r19 + +# CHECK: shrx r23, qword ptr [r28 + 4*r29 + 291], r19 +# CHECK: encoding: [0x62,0x8a,0xe3,0x00,0xf7,0xbc,0xac,0x23,0x01,0x00,0x00] + shrx r23, qword ptr [r28 + 4*r29 + 291], r19 diff --git a/llvm/test/TableGen/x86-fold-tables.inc b/llvm/test/TableGen/x86-fold-tables.inc index dcf650434c81..b2609f01e86a 100644 --- a/llvm/test/TableGen/x86-fold-tables.inc +++ b/llvm/test/TableGen/x86-fold-tables.inc @@ -411,7 +411,9 @@ static const X86FoldTableEntry Table1[] = { {X86::AESIMCrr, X86::AESIMCrm, TB_ALIGN_16}, {X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm, TB_ALIGN_16}, {X86::BEXTR32rr, X86::BEXTR32rm, 0}, + {X86::BEXTR32rr_EVEX, X86::BEXTR32rm_EVEX, 0}, {X86::BEXTR64rr, X86::BEXTR64rm, 0}, + {X86::BEXTR64rr_EVEX, X86::BEXTR64rm_EVEX, 0}, {X86::BEXTRI32ri, X86::BEXTRI32mi, 0}, {X86::BEXTRI64ri, X86::BEXTRI64mi, 0}, {X86::BLCFILL32rr, X86::BLCFILL32rm, 0}, @@ -427,13 +429,19 @@ static const X86FoldTableEntry Table1[] = { {X86::BLSFILL32rr, X86::BLSFILL32rm, 0}, {X86::BLSFILL64rr, X86::BLSFILL64rm, 0}, {X86::BLSI32rr, X86::BLSI32rm, 0}, + {X86::BLSI32rr_EVEX, X86::BLSI32rm_EVEX, 0}, {X86::BLSI64rr, X86::BLSI64rm, 0}, + {X86::BLSI64rr_EVEX, X86::BLSI64rm_EVEX, 0}, {X86::BLSIC32rr, X86::BLSIC32rm, 0}, {X86::BLSIC64rr, X86::BLSIC64rm, 0}, {X86::BLSMSK32rr, X86::BLSMSK32rm, 0}, + {X86::BLSMSK32rr_EVEX, X86::BLSMSK32rm_EVEX, 0}, {X86::BLSMSK64rr, X86::BLSMSK64rm, 0}, + {X86::BLSMSK64rr_EVEX, X86::BLSMSK64rm_EVEX, 0}, {X86::BLSR32rr, X86::BLSR32rm, 0}, + {X86::BLSR32rr_EVEX, X86::BLSR32rm_EVEX, 0}, {X86::BLSR64rr, X86::BLSR64rm, 0}, + {X86::BLSR64rr_EVEX, X86::BLSR64rm_EVEX, 0}, {X86::BSF16rr, X86::BSF16rm, 0}, {X86::BSF32rr, X86::BSF32rm, 0}, {X86::BSF64rr, X86::BSF64rm, 0}, @@ -441,7 +449,9 @@ static const X86FoldTableEntry Table1[] = { {X86::BSR32rr, X86::BSR32rm, 0}, {X86::BSR64rr, X86::BSR64rm, 0}, {X86::BZHI32rr, X86::BZHI32rm, 0}, + {X86::BZHI32rr_EVEX, X86::BZHI32rm_EVEX, 0}, {X86::BZHI64rr, X86::BZHI64rm, 0}, + {X86::BZHI64rr_EVEX, X86::BZHI64rm_EVEX, 0}, {X86::CMP16rr, X86::CMP16rm, 0}, {X86::CMP32rr, X86::CMP32rm, 0}, {X86::CMP64rr, X86::CMP64rm, 0}, @@ -582,7 +592,9 @@ static const X86FoldTableEntry Table1[] = { {X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16}, {X86::RCPSSr, X86::RCPSSm, 0}, {X86::RORX32ri, X86::RORX32mi, 0}, + {X86::RORX32ri_EVEX, X86::RORX32mi_EVEX, 0}, {X86::RORX64ri, X86::RORX64mi, 0}, + {X86::RORX64ri_EVEX, X86::RORX64mi_EVEX, 0}, {X86::ROUNDPDr, X86::ROUNDPDm, TB_ALIGN_16}, {X86::ROUNDPSr, X86::ROUNDPSm, TB_ALIGN_16}, {X86::ROUNDSDr, X86::ROUNDSDm, 0}, @@ -590,11 +602,17 @@ static const X86FoldTableEntry Table1[] = { {X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16}, {X86::RSQRTSSr, X86::RSQRTSSm, 0}, {X86::SARX32rr, X86::SARX32rm, 0}, + {X86::SARX32rr_EVEX, X86::SARX32rm_EVEX, 0}, {X86::SARX64rr, X86::SARX64rm, 0}, + {X86::SARX64rr_EVEX, X86::SARX64rm_EVEX, 0}, {X86::SHLX32rr, X86::SHLX32rm, 0}, + {X86::SHLX32rr_EVEX, X86::SHLX32rm_EVEX, 0}, {X86::SHLX64rr, X86::SHLX64rm, 0}, + {X86::SHLX64rr_EVEX, X86::SHLX64rm_EVEX, 0}, {X86::SHRX32rr, X86::SHRX32rm, 0}, + {X86::SHRX32rr_EVEX, X86::SHRX32rm_EVEX, 0}, {X86::SHRX64rr, X86::SHRX64rm, 0}, + {X86::SHRX64rr_EVEX, X86::SHRX64rm_EVEX, 0}, {X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16}, {X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16}, {X86::SQRTSDr, X86::SQRTSDm, 0}, @@ -1332,7 +1350,9 @@ static const X86FoldTableEntry Table2[] = { {X86::AND64rr, X86::AND64rm, 0}, {X86::AND8rr, X86::AND8rm, 0}, {X86::ANDN32rr, X86::ANDN32rm, 0}, + {X86::ANDN32rr_EVEX, X86::ANDN32rm_EVEX, 0}, {X86::ANDN64rr, X86::ANDN64rm, 0}, + {X86::ANDN64rr_EVEX, X86::ANDN64rm_EVEX, 0}, {X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16}, {X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16}, {X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16}, @@ -1479,7 +1499,9 @@ static const X86FoldTableEntry Table2[] = { {X86::MULSSrr, X86::MULSSrm, 0}, {X86::MULSSrr_Int, X86::MULSSrm_Int, TB_NO_REVERSE}, {X86::MULX32rr, X86::MULX32rm, 0}, + {X86::MULX32rr_EVEX, X86::MULX32rm_EVEX, 0}, {X86::MULX64rr, X86::MULX64rm, 0}, + {X86::MULX64rr_EVEX, X86::MULX64rm_EVEX, 0}, {X86::OR16rr, X86::OR16rm, 0}, {X86::OR32rr, X86::OR32rm, 0}, {X86::OR64rr, X86::OR64rm, 0}, @@ -1516,9 +1538,13 @@ static const X86FoldTableEntry Table2[] = { {X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16}, {X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16}, {X86::PDEP32rr, X86::PDEP32rm, 0}, + {X86::PDEP32rr_EVEX, X86::PDEP32rm_EVEX, 0}, {X86::PDEP64rr, X86::PDEP64rm, 0}, + {X86::PDEP64rr_EVEX, X86::PDEP64rm_EVEX, 0}, {X86::PEXT32rr, X86::PEXT32rm, 0}, + {X86::PEXT32rr_EVEX, X86::PEXT32rm_EVEX, 0}, {X86::PEXT64rr, X86::PEXT64rm, 0}, + {X86::PEXT64rr_EVEX, X86::PEXT64rm_EVEX, 0}, {X86::PFACCrr, X86::PFACCrm, 0}, {X86::PFADDrr, X86::PFADDrm, 0}, {X86::PFCMPEQrr, X86::PFCMPEQrm, 0}, -- GitLab From f42ce1621f5f4129fb37c4a1af958e1d47344107 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20Warzy=C5=84ski?= Date: Fri, 1 Dec 2023 10:08:00 +0000 Subject: [PATCH 122/699] [mlir][sve][nfc] Update a test to use transform-interpreter (#73771) This is a follow-up of #70040 in which the test updated here was missed. Includes a few additional NFC changes in preparation for extending this test. --- .../Dialect/Linalg/CPU/ArmSVE/matmul.mlir | 70 +++++++++++-------- 1 file changed, 42 insertions(+), 28 deletions(-) diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/matmul.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/matmul.mlir index 2024da2a585d..d771d32d548b 100644 --- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/matmul.mlir +++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/matmul.mlir @@ -1,8 +1,14 @@ -// RUN: mlir-opt %s -test-transform-dialect-interpreter -test-transform-dialect-erase-schedule \ -// RUN: -one-shot-bufferize -func-bufferize -cse -canonicalize -convert-vector-to-scf -arm-sve-legalize-vector-storage \ -// RUN: -convert-vector-to-llvm="enable-arm-sve" -test-lower-to-llvm | \ -// RUN: %mcr_aarch64_cmd -e=matmul_f32 -entry-point-result=void --march=aarch64 --mattr="+sve" -shared-libs=%mlir_runner_utils,%mlir_c_runner_utils | \ -// RUN: FileCheck %s +// DEFINE: %{compile} = mlir-opt %s \ +// DEFINE: -transform-interpreter -test-transform-dialect-erase-schedule \ +// DEFINE: -one-shot-bufferize -func-bufferize -cse -canonicalize -convert-vector-to-scf -arm-sve-legalize-vector-storage \ +// DEFINE: -convert-vector-to-llvm="enable-arm-sve" -test-lower-to-llvm -o %t +// DEFINE: %{entry_point} = matmul_f32 +// DEFINE: %{run} = %mcr_aarch64_cmd %t -e %{entry_point} -entry-point-result=void --march=aarch64 --mattr="+sve"\ +// DEFINE: -shared-libs=%mlir_runner_utils,%mlir_c_runner_utils + +// RUN: %{compile} + +// RUN: %{run} | FileCheck %s func.func @matmul_f32() { // Matrix dimensions @@ -40,29 +46,37 @@ func.func @matmul_f32() { return } -transform.sequence failures(propagate) { -^bb1(%module_op: !transform.any_op): - // Step 1: Tile - %matmul = transform.structured.match ops{["linalg.matmul"]} in %module_op : (!transform.any_op) -> !transform.any_op - %func_op = get_parent_op %matmul : (!transform.any_op) -> !transform.op<"func.func"> - %module_with_tiled_loops, %loops:3 = transform.structured.tile_using_for %matmul [2, [4], 1] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) - - // Step 2: Vectorize - %tiled_matmul = transform.structured.match ops{["linalg.matmul"]} in %module_with_tiled_loops : (!transform.any_op) -> !transform.any_op - transform.structured.vectorize %tiled_matmul vector_sizes [2, [4], 1] : !transform.any_op - - // Step 3: Lower vector.multi_reduction to vector.contract (+ some helpful patterns) - transform.apply_patterns to %func_op { - transform.apply_patterns.vector.reduction_to_contract - transform.apply_patterns.vector.transfer_permutation_patterns - transform.apply_patterns.vector.lower_masked_transfers - } : !transform.op<"func.func"> - - // Step 4: Lower vector.contract to vector.fma - transform.apply_patterns to %func_op { - transform.apply_patterns.vector.lower_contraction lowering_strategy = "outerproduct" - transform.apply_patterns.vector.lower_outerproduct - } : !transform.op<"func.func"> +module attributes {transform.with_named_sequence} { +transform.named_sequence @__transform_main(%module: !transform.any_op {transform.readonly}) { + %matmul = transform.structured.match ops{["linalg.matmul"]} in %module + : (!transform.any_op) -> !transform.any_op + + // Step 1: Tile + %module_with_tiled_loops, %loops:3 = transform.structured.tile_using_for %matmul [2, [4], 1] + : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) + + // Step 2: Vectorize + %tiled_matmul = transform.structured.match ops{["linalg.matmul"]} in %module_with_tiled_loops + : (!transform.any_op) -> !transform.any_op + transform.structured.vectorize %tiled_matmul vector_sizes [2, [4], 1] : !transform.any_op + + // Step 3: Lower vector.multi_reduction to vector.contract (+ some helpful patterns) + %func = transform.structured.match ops{["func.func"]} in %module + : (!transform.any_op) -> !transform.op<"func.func"> + transform.apply_patterns to %func { + transform.apply_patterns.vector.reduction_to_contract + transform.apply_patterns.vector.transfer_permutation_patterns + transform.apply_patterns.vector.lower_masked_transfers + } : !transform.op<"func.func"> + + // Step 4: Lower vector.contract to vector.fma + transform.apply_patterns to %func { + transform.apply_patterns.vector.lower_contraction lowering_strategy = "outerproduct" + transform.apply_patterns.vector.lower_outerproduct + } : !transform.op<"func.func"> + + transform.yield + } } func.func private @printMemrefF32(%ptr : tensor<*xf32>) -- GitLab From 1ee41b415398cde51c055a7b1a4d419350e7038f Mon Sep 17 00:00:00 2001 From: Nikolas Klauser Date: Fri, 1 Dec 2023 11:29:05 +0100 Subject: [PATCH 123/699] [libc++][NFC] Update the remaining old license headers --- libcxx/test/libcxx/numerics/bit.ops.pass.cpp | 8 ++++---- .../memory/ptr.align/assume_aligned.power2.verify.cpp | 7 +++---- .../sequences/forwardlist/forwardlist.spec/equal.pass.cpp | 7 +++---- .../forwardlist/forwardlist.spec/member_swap.pass.cpp | 7 +++---- .../forwardlist/forwardlist.spec/non_member_swap.pass.cpp | 7 +++---- .../forwardlist/forwardlist.spec/relational.pass.cpp | 7 +++---- .../forwardlist/forwardlist.spec/swap_noexcept.pass.cpp | 7 +++---- .../support.dynamic/destroying_delete_t.pass.cpp | 7 +++---- .../destroying_delete_t_declaration.pass.cpp | 7 +++---- .../language.support/support.dynamic/nothrow_t.pass.cpp | 7 +++---- .../language.support/support.dynamic/nothrow_t.verify.cpp | 7 +++---- .../test/std/numerics/bit/bit.pow.two/bit_ceil.pass.cpp | 8 ++++---- .../test/std/numerics/bit/bit.pow.two/bit_ceil.verify.cpp | 8 ++++---- .../test/std/numerics/bit/bit.pow.two/bit_floor.pass.cpp | 8 ++++---- .../test/std/numerics/bit/bit.pow.two/bit_width.pass.cpp | 8 ++++---- .../std/numerics/bit/bit.pow.two/has_single_bit.pass.cpp | 8 ++++---- .../std/numerics/bit/bitops.count/countl_one.pass.cpp | 8 ++++---- .../std/numerics/bit/bitops.count/countl_zero.pass.cpp | 8 ++++---- .../std/numerics/bit/bitops.count/countr_one.pass.cpp | 8 ++++---- .../std/numerics/bit/bitops.count/countr_zero.pass.cpp | 8 ++++---- .../test/std/numerics/bit/bitops.count/popcount.pass.cpp | 8 ++++---- libcxx/test/std/numerics/bit/bitops.rot/rotl.pass.cpp | 8 ++++---- libcxx/test/std/numerics/bit/bitops.rot/rotr.pass.cpp | 8 ++++---- .../std/thread/thread.mutex/thread.lock/types.verify.cpp | 7 +++---- .../func.wrap.func/func.wrap.func.con/deduct_F.pass.cpp | 7 +++---- .../func.wrap.func/func.wrap.func.con/deduct_F.verify.cpp | 7 +++---- .../func.wrap.func/func.wrap.func.con/deduct_ptr.pass.cpp | 7 +++---- .../util.smartptr.shared.spec/swap.pass.cpp | 7 +++---- .../util.smartptr.weak.spec/swap.pass.cpp | 7 +++---- .../meta.trans.other/common_reference.compile.pass.cpp | 7 +++---- 30 files changed, 103 insertions(+), 120 deletions(-) diff --git a/libcxx/test/libcxx/numerics/bit.ops.pass.cpp b/libcxx/test/libcxx/numerics/bit.ops.pass.cpp index 2a509db1d79a..d3ca8b2f8030 100644 --- a/libcxx/test/libcxx/numerics/bit.ops.pass.cpp +++ b/libcxx/test/libcxx/numerics/bit.ops.pass.cpp @@ -1,11 +1,11 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + // Test the __XXXX routines in the header. // These are not supposed to be exhaustive tests, just sanity checks. diff --git a/libcxx/test/libcxx/utilities/memory/ptr.align/assume_aligned.power2.verify.cpp b/libcxx/test/libcxx/utilities/memory/ptr.align/assume_aligned.power2.verify.cpp index 92c9e927a546..b206fe31ea19 100644 --- a/libcxx/test/libcxx/utilities/memory/ptr.align/assume_aligned.power2.verify.cpp +++ b/libcxx/test/libcxx/utilities/memory/ptr.align/assume_aligned.power2.verify.cpp @@ -1,9 +1,8 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/libcxx/test/std/containers/sequences/forwardlist/forwardlist.spec/equal.pass.cpp b/libcxx/test/std/containers/sequences/forwardlist/forwardlist.spec/equal.pass.cpp index a727487ed0d9..b21035f7dd74 100644 --- a/libcxx/test/std/containers/sequences/forwardlist/forwardlist.spec/equal.pass.cpp +++ b/libcxx/test/std/containers/sequences/forwardlist/forwardlist.spec/equal.pass.cpp @@ -1,9 +1,8 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/libcxx/test/std/containers/sequences/forwardlist/forwardlist.spec/member_swap.pass.cpp b/libcxx/test/std/containers/sequences/forwardlist/forwardlist.spec/member_swap.pass.cpp index 6b16d66fedb2..e7eea2e87bfe 100644 --- a/libcxx/test/std/containers/sequences/forwardlist/forwardlist.spec/member_swap.pass.cpp +++ b/libcxx/test/std/containers/sequences/forwardlist/forwardlist.spec/member_swap.pass.cpp @@ -1,9 +1,8 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/libcxx/test/std/containers/sequences/forwardlist/forwardlist.spec/non_member_swap.pass.cpp b/libcxx/test/std/containers/sequences/forwardlist/forwardlist.spec/non_member_swap.pass.cpp index e46a55cf81e4..54d26d0a6491 100644 --- a/libcxx/test/std/containers/sequences/forwardlist/forwardlist.spec/non_member_swap.pass.cpp +++ b/libcxx/test/std/containers/sequences/forwardlist/forwardlist.spec/non_member_swap.pass.cpp @@ -1,9 +1,8 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/libcxx/test/std/containers/sequences/forwardlist/forwardlist.spec/relational.pass.cpp b/libcxx/test/std/containers/sequences/forwardlist/forwardlist.spec/relational.pass.cpp index 29a180a96612..9ca19486a54b 100644 --- a/libcxx/test/std/containers/sequences/forwardlist/forwardlist.spec/relational.pass.cpp +++ b/libcxx/test/std/containers/sequences/forwardlist/forwardlist.spec/relational.pass.cpp @@ -1,9 +1,8 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/libcxx/test/std/containers/sequences/forwardlist/forwardlist.spec/swap_noexcept.pass.cpp b/libcxx/test/std/containers/sequences/forwardlist/forwardlist.spec/swap_noexcept.pass.cpp index b4568837a2e0..76f8b6213908 100644 --- a/libcxx/test/std/containers/sequences/forwardlist/forwardlist.spec/swap_noexcept.pass.cpp +++ b/libcxx/test/std/containers/sequences/forwardlist/forwardlist.spec/swap_noexcept.pass.cpp @@ -1,9 +1,8 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/libcxx/test/std/language.support/support.dynamic/destroying_delete_t.pass.cpp b/libcxx/test/std/language.support/support.dynamic/destroying_delete_t.pass.cpp index 7f52e2d8d508..95d2c41d7bfe 100644 --- a/libcxx/test/std/language.support/support.dynamic/destroying_delete_t.pass.cpp +++ b/libcxx/test/std/language.support/support.dynamic/destroying_delete_t.pass.cpp @@ -1,9 +1,8 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/libcxx/test/std/language.support/support.dynamic/destroying_delete_t_declaration.pass.cpp b/libcxx/test/std/language.support/support.dynamic/destroying_delete_t_declaration.pass.cpp index b98af1bfe1e4..1270853a1cca 100644 --- a/libcxx/test/std/language.support/support.dynamic/destroying_delete_t_declaration.pass.cpp +++ b/libcxx/test/std/language.support/support.dynamic/destroying_delete_t_declaration.pass.cpp @@ -1,9 +1,8 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/libcxx/test/std/language.support/support.dynamic/nothrow_t.pass.cpp b/libcxx/test/std/language.support/support.dynamic/nothrow_t.pass.cpp index 3a6231329f09..bfc41cb141aa 100644 --- a/libcxx/test/std/language.support/support.dynamic/nothrow_t.pass.cpp +++ b/libcxx/test/std/language.support/support.dynamic/nothrow_t.pass.cpp @@ -1,9 +1,8 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/libcxx/test/std/language.support/support.dynamic/nothrow_t.verify.cpp b/libcxx/test/std/language.support/support.dynamic/nothrow_t.verify.cpp index 50dd63a6350f..f2b345e80969 100644 --- a/libcxx/test/std/language.support/support.dynamic/nothrow_t.verify.cpp +++ b/libcxx/test/std/language.support/support.dynamic/nothrow_t.verify.cpp @@ -1,9 +1,8 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/libcxx/test/std/numerics/bit/bit.pow.two/bit_ceil.pass.cpp b/libcxx/test/std/numerics/bit/bit.pow.two/bit_ceil.pass.cpp index 4e794f129f36..5e37db95ab09 100644 --- a/libcxx/test/std/numerics/bit/bit.pow.two/bit_ceil.pass.cpp +++ b/libcxx/test/std/numerics/bit/bit.pow.two/bit_ceil.pass.cpp @@ -1,11 +1,11 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + // UNSUPPORTED: c++03, c++11, c++14, c++17 // template diff --git a/libcxx/test/std/numerics/bit/bit.pow.two/bit_ceil.verify.cpp b/libcxx/test/std/numerics/bit/bit.pow.two/bit_ceil.verify.cpp index 9424b0b24f8a..d37de690a48d 100644 --- a/libcxx/test/std/numerics/bit/bit.pow.two/bit_ceil.verify.cpp +++ b/libcxx/test/std/numerics/bit/bit.pow.two/bit_ceil.verify.cpp @@ -1,11 +1,11 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + // UNSUPPORTED: c++03, c++11, c++14, c++17 // template diff --git a/libcxx/test/std/numerics/bit/bit.pow.two/bit_floor.pass.cpp b/libcxx/test/std/numerics/bit/bit.pow.two/bit_floor.pass.cpp index 06ee38cf8261..38a46fcc1222 100644 --- a/libcxx/test/std/numerics/bit/bit.pow.two/bit_floor.pass.cpp +++ b/libcxx/test/std/numerics/bit/bit.pow.two/bit_floor.pass.cpp @@ -1,11 +1,11 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + // UNSUPPORTED: c++03, c++11, c++14, c++17 // template diff --git a/libcxx/test/std/numerics/bit/bit.pow.two/bit_width.pass.cpp b/libcxx/test/std/numerics/bit/bit.pow.two/bit_width.pass.cpp index cfb9a163b4fa..baf2032a4a1f 100644 --- a/libcxx/test/std/numerics/bit/bit.pow.two/bit_width.pass.cpp +++ b/libcxx/test/std/numerics/bit/bit.pow.two/bit_width.pass.cpp @@ -1,11 +1,11 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + // UNSUPPORTED: c++03, c++11, c++14, c++17 // template diff --git a/libcxx/test/std/numerics/bit/bit.pow.two/has_single_bit.pass.cpp b/libcxx/test/std/numerics/bit/bit.pow.two/has_single_bit.pass.cpp index 7b23627a3d02..81dca301e21f 100644 --- a/libcxx/test/std/numerics/bit/bit.pow.two/has_single_bit.pass.cpp +++ b/libcxx/test/std/numerics/bit/bit.pow.two/has_single_bit.pass.cpp @@ -1,11 +1,11 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + // UNSUPPORTED: c++03, c++11, c++14, c++17 // template diff --git a/libcxx/test/std/numerics/bit/bitops.count/countl_one.pass.cpp b/libcxx/test/std/numerics/bit/bitops.count/countl_one.pass.cpp index bbce57b9caea..92268cf563b4 100644 --- a/libcxx/test/std/numerics/bit/bitops.count/countl_one.pass.cpp +++ b/libcxx/test/std/numerics/bit/bitops.count/countl_one.pass.cpp @@ -1,11 +1,11 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + // UNSUPPORTED: c++03, c++11, c++14, c++17 // template diff --git a/libcxx/test/std/numerics/bit/bitops.count/countl_zero.pass.cpp b/libcxx/test/std/numerics/bit/bitops.count/countl_zero.pass.cpp index f103450eb834..9d5d361662e8 100644 --- a/libcxx/test/std/numerics/bit/bitops.count/countl_zero.pass.cpp +++ b/libcxx/test/std/numerics/bit/bitops.count/countl_zero.pass.cpp @@ -1,11 +1,11 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + // UNSUPPORTED: c++03, c++11, c++14, c++17 // template diff --git a/libcxx/test/std/numerics/bit/bitops.count/countr_one.pass.cpp b/libcxx/test/std/numerics/bit/bitops.count/countr_one.pass.cpp index 8e8ef1d535a5..63b60640ac04 100644 --- a/libcxx/test/std/numerics/bit/bitops.count/countr_one.pass.cpp +++ b/libcxx/test/std/numerics/bit/bitops.count/countr_one.pass.cpp @@ -1,11 +1,11 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + // UNSUPPORTED: c++03, c++11, c++14, c++17 // template diff --git a/libcxx/test/std/numerics/bit/bitops.count/countr_zero.pass.cpp b/libcxx/test/std/numerics/bit/bitops.count/countr_zero.pass.cpp index d0fdf921a09d..1df1d883a12e 100644 --- a/libcxx/test/std/numerics/bit/bitops.count/countr_zero.pass.cpp +++ b/libcxx/test/std/numerics/bit/bitops.count/countr_zero.pass.cpp @@ -1,11 +1,11 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + // UNSUPPORTED: c++03, c++11, c++14, c++17 // template diff --git a/libcxx/test/std/numerics/bit/bitops.count/popcount.pass.cpp b/libcxx/test/std/numerics/bit/bitops.count/popcount.pass.cpp index b8759c440432..588c5e0cf7af 100644 --- a/libcxx/test/std/numerics/bit/bitops.count/popcount.pass.cpp +++ b/libcxx/test/std/numerics/bit/bitops.count/popcount.pass.cpp @@ -1,11 +1,11 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + // UNSUPPORTED: c++03, c++11, c++14, c++17 // template diff --git a/libcxx/test/std/numerics/bit/bitops.rot/rotl.pass.cpp b/libcxx/test/std/numerics/bit/bitops.rot/rotl.pass.cpp index a1be03453abe..50e498b5761e 100644 --- a/libcxx/test/std/numerics/bit/bitops.rot/rotl.pass.cpp +++ b/libcxx/test/std/numerics/bit/bitops.rot/rotl.pass.cpp @@ -1,11 +1,11 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + // UNSUPPORTED: c++03, c++11, c++14, c++17 // template diff --git a/libcxx/test/std/numerics/bit/bitops.rot/rotr.pass.cpp b/libcxx/test/std/numerics/bit/bitops.rot/rotr.pass.cpp index 89fef32c36d4..00c9e617d2ed 100644 --- a/libcxx/test/std/numerics/bit/bitops.rot/rotr.pass.cpp +++ b/libcxx/test/std/numerics/bit/bitops.rot/rotr.pass.cpp @@ -1,11 +1,11 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + // UNSUPPORTED: c++03, c++11, c++14, c++17 // template diff --git a/libcxx/test/std/thread/thread.mutex/thread.lock/types.verify.cpp b/libcxx/test/std/thread/thread.mutex/thread.lock/types.verify.cpp index 623e5c3d22e7..1688470e1ac4 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.lock/types.verify.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.lock/types.verify.cpp @@ -1,9 +1,8 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/deduct_F.pass.cpp b/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/deduct_F.pass.cpp index 00d183168d4b..ef43ab9b64b5 100644 --- a/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/deduct_F.pass.cpp +++ b/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/deduct_F.pass.cpp @@ -1,9 +1,8 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/deduct_F.verify.cpp b/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/deduct_F.verify.cpp index 520e5f055a71..8a42d3be3571 100644 --- a/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/deduct_F.verify.cpp +++ b/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/deduct_F.verify.cpp @@ -1,9 +1,8 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/deduct_ptr.pass.cpp b/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/deduct_ptr.pass.cpp index cc61a75c84f9..ed4e0e96de3b 100644 --- a/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/deduct_ptr.pass.cpp +++ b/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/deduct_ptr.pass.cpp @@ -1,9 +1,8 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.spec/swap.pass.cpp b/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.spec/swap.pass.cpp index 47ae5dd8f729..94986eaa9e3f 100644 --- a/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.spec/swap.pass.cpp +++ b/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.spec/swap.pass.cpp @@ -1,9 +1,8 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.weak/util.smartptr.weak.spec/swap.pass.cpp b/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.weak/util.smartptr.weak.spec/swap.pass.cpp index 98429fd74063..d6fcd882cd66 100644 --- a/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.weak/util.smartptr.weak.spec/swap.pass.cpp +++ b/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.weak/util.smartptr.weak.spec/swap.pass.cpp @@ -1,9 +1,8 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/libcxx/test/std/utilities/meta/meta.trans/meta.trans.other/common_reference.compile.pass.cpp b/libcxx/test/std/utilities/meta/meta.trans/meta.trans.other/common_reference.compile.pass.cpp index 9332865eaa24..04a1451863c9 100644 --- a/libcxx/test/std/utilities/meta/meta.trans/meta.trans.other/common_reference.compile.pass.cpp +++ b/libcxx/test/std/utilities/meta/meta.trans/meta.trans.other/common_reference.compile.pass.cpp @@ -1,9 +1,8 @@ //===----------------------------------------------------------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// -- GitLab From f7d91faa790630eca506a29faa560d6783edcbc0 Mon Sep 17 00:00:00 2001 From: Benjamin Maxwell Date: Fri, 1 Dec 2023 10:39:01 +0000 Subject: [PATCH 124/699] [mlir][ArmSME] Add option to only enable streaming mode/ZA if required (#73931) This adds a `only-if-required-by-ops` flag to the `enable-arm-streaming` pass. This flag defaults to `false` (which preserves the original behaviour), however, if set to `true` the pass will only add the selected ZA/streaming mode to functions that contain ops that implement `ArmSMETileOpInterface`. This simplifies enabling these modes, as we can now first try lowering ops to ArmSME, then only if we succeed, add the relevant function attributes. --- .../mlir/Dialect/ArmSME/Transforms/Passes.h | 2 +- .../mlir/Dialect/ArmSME/Transforms/Passes.td | 6 ++++- .../ArmSME/Transforms/EnableArmStreaming.cpp | 25 ++++++++++++++++--- .../Dialect/ArmSME/enable-arm-streaming.mlir | 16 ++++++++++++ 4 files changed, 44 insertions(+), 5 deletions(-) diff --git a/mlir/include/mlir/Dialect/ArmSME/Transforms/Passes.h b/mlir/include/mlir/Dialect/ArmSME/Transforms/Passes.h index 11a7385fe311..21a97e9cbc79 100644 --- a/mlir/include/mlir/Dialect/ArmSME/Transforms/Passes.h +++ b/mlir/include/mlir/Dialect/ArmSME/Transforms/Passes.h @@ -27,7 +27,7 @@ namespace arm_sme { /// Pass to enable Armv9 Streaming SVE mode. std::unique_ptr createEnableArmStreamingPass( const ArmStreamingMode = ArmStreamingMode::Streaming, - const ArmZaMode = ArmZaMode::Disabled); + const ArmZaMode = ArmZaMode::Disabled, bool onlyIfRequiredByOps = false); /// Pass that allocates tile IDs to ArmSME operations. std::unique_ptr createTileAllocationPass(); diff --git a/mlir/include/mlir/Dialect/ArmSME/Transforms/Passes.td b/mlir/include/mlir/Dialect/ArmSME/Transforms/Passes.td index 3253b47e62ab..7b9c74e0b8f6 100644 --- a/mlir/include/mlir/Dialect/ArmSME/Transforms/Passes.td +++ b/mlir/include/mlir/Dialect/ArmSME/Transforms/Passes.td @@ -73,7 +73,11 @@ def EnableArmStreaming "new-za", "The function has ZA state. The ZA state is " "created on entry and destroyed on exit.") - )}]> + )}]>, + Option<"onlyIfRequiredByOps", "only-if-required-by-ops", "bool", + /*default=*/"false", + "Only apply the selected streaming/ZA modes if the function " + " contains ops that require them."> ]; let dependentDialects = ["func::FuncDialect"]; } diff --git a/mlir/lib/Dialect/ArmSME/Transforms/EnableArmStreaming.cpp b/mlir/lib/Dialect/ArmSME/Transforms/EnableArmStreaming.cpp index c3a1a1c9a3fb..79a6caffb6ee 100644 --- a/mlir/lib/Dialect/ArmSME/Transforms/EnableArmStreaming.cpp +++ b/mlir/lib/Dialect/ArmSME/Transforms/EnableArmStreaming.cpp @@ -33,6 +33,7 @@ // //===----------------------------------------------------------------------===// +#include "mlir/Dialect/ArmSME/IR/ArmSME.h" #include "mlir/Dialect/ArmSME/Transforms/Passes.h" #include "mlir/Dialect/ArmSME/Transforms/PassesEnums.cpp.inc" @@ -56,12 +57,28 @@ constexpr StringLiteral struct EnableArmStreamingPass : public arm_sme::impl::EnableArmStreamingBase { - EnableArmStreamingPass(ArmStreamingMode streamingMode, ArmZaMode zaMode) { + EnableArmStreamingPass(ArmStreamingMode streamingMode, ArmZaMode zaMode, + bool onlyIfRequiredByOps) { this->streamingMode = streamingMode; this->zaMode = zaMode; + this->onlyIfRequiredByOps = onlyIfRequiredByOps; } void runOnOperation() override { auto op = getOperation(); + + if (onlyIfRequiredByOps) { + bool foundTileOp = false; + op.walk([&](Operation *op) { + if (llvm::isa(op)) { + foundTileOp = true; + return WalkResult::interrupt(); + } + return WalkResult::advance(); + }); + if (!foundTileOp) + return; + } + if (op->getAttr(kEnableArmStreamingIgnoreAttr) || streamingMode == ArmStreamingMode::Disabled) return; @@ -81,6 +98,8 @@ struct EnableArmStreamingPass } // namespace std::unique_ptr mlir::arm_sme::createEnableArmStreamingPass( - const ArmStreamingMode streamingMode, const ArmZaMode zaMode) { - return std::make_unique(streamingMode, zaMode); + const ArmStreamingMode streamingMode, const ArmZaMode zaMode, + bool onlyIfRequiredByOps) { + return std::make_unique(streamingMode, zaMode, + onlyIfRequiredByOps); } diff --git a/mlir/test/Dialect/ArmSME/enable-arm-streaming.mlir b/mlir/test/Dialect/ArmSME/enable-arm-streaming.mlir index 70119b08c3e9..b1188acbc0b2 100644 --- a/mlir/test/Dialect/ArmSME/enable-arm-streaming.mlir +++ b/mlir/test/Dialect/ArmSME/enable-arm-streaming.mlir @@ -1,6 +1,7 @@ // RUN: mlir-opt %s -enable-arm-streaming -verify-diagnostics | FileCheck %s // RUN: mlir-opt %s -enable-arm-streaming=streaming-mode=streaming-locally -verify-diagnostics | FileCheck %s -check-prefix=CHECK-LOCALLY // RUN: mlir-opt %s -enable-arm-streaming=za-mode=new-za -verify-diagnostics | FileCheck %s -check-prefix=CHECK-ENABLE-ZA +// RUN: mlir-opt %s -enable-arm-streaming=only-if-required-by-ops -verify-diagnostics | FileCheck %s -check-prefix=IF-REQUIRED // CHECK-LABEL: @arm_streaming // CHECK-SAME: attributes {arm_streaming} @@ -17,3 +18,18 @@ func.func @arm_streaming() { return } // CHECK-ENABLE-ZA-LABEL: @not_arm_streaming // CHECK-ENABLE-ZA-SAME: attributes {enable_arm_streaming_ignore} func.func @not_arm_streaming() attributes {enable_arm_streaming_ignore} { return } + +// CHECK-LABEL: @requires_arm_streaming +// CHECK-SAME: attributes {arm_streaming} +// IF-REQUIRED: @requires_arm_streaming +// IF-REQUIRED-SAME: attributes {arm_streaming} +func.func @requires_arm_streaming() { + %tile = arm_sme.get_tile : vector<[4]x[4]xi32> + return +} + +// CHECK-LABEL: @does_not_require_arm_streaming +// CHECK-SAME: attributes {arm_streaming} +// IF-REQUIRED: @does_not_require_arm_streaming +// IF-REQUIRED-NOT: arm_streaming +func.func @does_not_require_arm_streaming() { return } -- GitLab From da1aff2b2a3192f5e32fa350de19aac0b89fed18 Mon Sep 17 00:00:00 2001 From: David Spickett Date: Fri, 1 Dec 2023 10:40:24 +0000 Subject: [PATCH 125/699] [llvm][PowerPC] Correct handling of spill slots for SPE when EXPENSIVE_CHECKS is enabled (#73940) This was modifying a container as it iterated it, which tripped a check in libstdc++'s debug checks. Instead, just assign to the item via the reference we already have. This fixes the following expensive checks failures on my machine: LLVM :: CodeGen/PowerPC/fp-strict.ll LLVM :: CodeGen/PowerPC/pr55463.ll LLVM :: CodeGen/PowerPC/register-pressure.ll LLVM :: CodeGen/PowerPC/spe.ll Which are some of the tests noted by #68594. --- llvm/lib/Target/PowerPC/PPCFrameLowering.cpp | 24 +++++++------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp index eb3bf3b2690b..245e78641ed6 100644 --- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp @@ -2334,24 +2334,16 @@ bool PPCFrameLowering::assignCalleeSavedSpillSlots( // In case of SPE we only have SuperRegs and CRs // in our CalleSaveInfo vector. - unsigned Idx = 0; for (auto &CalleeSaveReg : CSI) { - const MCPhysReg &Reg = CalleeSaveReg.getReg(); - const MCPhysReg &Lower = RegInfo->getSubReg(Reg, 1); - const MCPhysReg &Higher = RegInfo->getSubReg(Reg, 2); - - // Check only for SuperRegs. - if (Lower) { - if (MRI.isPhysRegModified(Higher)) { - Idx++; - continue; - } else { + MCPhysReg Reg = CalleeSaveReg.getReg(); + MCPhysReg Lower = RegInfo->getSubReg(Reg, 1); + MCPhysReg Higher = RegInfo->getSubReg(Reg, 2); + + if ( // Check only for SuperRegs. + Lower && // Replace Reg if only lower-32 bits modified - CSI.erase(CSI.begin() + Idx); - CSI.insert(CSI.begin() + Idx, CalleeSavedInfo(Lower)); - } - } - Idx++; + !MRI.isPhysRegModified(Higher)) + CalleeSaveReg = CalleeSavedInfo(Lower); } } -- GitLab From 289fe74ddbb4c8aa7128f60db6b20c119922b542 Mon Sep 17 00:00:00 2001 From: Vlad Serebrennikov Date: Fri, 1 Dec 2023 13:35:23 +0300 Subject: [PATCH 126/699] [clang][NFC] Fill in historical data on when C++ DRs 100-199 were fixed --- clang/test/CXX/drs/dr1xx.cpp | 20 ++++++++++---------- clang/www/cxx_dr_status.html | 20 ++++++++++---------- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/clang/test/CXX/drs/dr1xx.cpp b/clang/test/CXX/drs/dr1xx.cpp index 60e80a4c0e1c..50236eb7c949 100644 --- a/clang/test/CXX/drs/dr1xx.cpp +++ b/clang/test/CXX/drs/dr1xx.cpp @@ -72,7 +72,7 @@ namespace dr107 { // dr107: yes extern "C" S operator+(S, S) { return S(); } } -namespace dr108 { // dr108: yes +namespace dr108 { // dr108: 2.9 template struct A { struct B { typedef int X; }; B::X x; @@ -143,7 +143,7 @@ namespace dr114 { // dr114: yes } b; // expected-error {{abstract}} } -namespace dr115 { // dr115: yes +namespace dr115 { // dr115: 3.0 template int f(T); // expected-note +{{}} template int g(T); // expected-note +{{}} template int g(T, int); // expected-note +{{}} @@ -480,7 +480,7 @@ namespace dr140 { // dr140: yes void g(int n) { n = 2; } } -namespace dr141 { // dr141: yes +namespace dr141 { // dr141: 3.1 template void f(); template struct S { int n; }; // expected-note {{'::dr141::S::n' declared here}} struct A : S { @@ -518,7 +518,7 @@ namespace dr141 { // dr141: yes void i() { C().i(); } // ok!! } -namespace dr142 { // dr142: yes +namespace dr142 { // dr142: 2.8 class B { // expected-note +{{here}} public: int mi; // expected-note +{{here}} @@ -602,7 +602,7 @@ namespace dr148 { // dr148: yes // dr149: na -namespace dr151 { // dr151: yes +namespace dr151 { // dr151: 3.1 struct X {}; typedef int X::*p; #if __cplusplus < 201103L @@ -655,7 +655,7 @@ namespace dr159 { // dr159: 3.5 // dr160: na -namespace dr161 { // dr161: yes +namespace dr161 { // dr161: 3.1 class A { protected: struct B { int n; } b; // expected-note 2{{here}} @@ -724,7 +724,7 @@ namespace dr165 { // dr165: no void N::g() {} } -namespace dr166 { // dr166: yes +namespace dr166 { // dr166: 2.9 namespace A { class X; } template int f(T t) { return t.n; } @@ -827,7 +827,7 @@ namespace dr173 { // dr173: yes // dr174: sup 1012 -namespace dr175 { // dr175: yes +namespace dr175 { // dr175: 2.8 struct A {}; // expected-note {{here}} struct B : private A {}; // expected-note {{constrained by private inheritance}} struct C : B { @@ -836,7 +836,7 @@ namespace dr175 { // dr175: yes }; } -namespace dr176 { // dr176: yes +namespace dr176 { // dr176: 3.1 template class Y; template<> class Y { void f() { @@ -904,7 +904,7 @@ namespace dr179 { // dr179: yes int n = &f - &f; // expected-error {{arithmetic on pointers to the function type 'void ()'}} } -namespace dr180 { // dr180: yes +namespace dr180 { // dr180: 2.8 template struct X : T, T::some_base { X() : T::some_type_that_might_be_T(), T::some_base() {} friend class T::some_class; diff --git a/clang/www/cxx_dr_status.html b/clang/www/cxx_dr_status.html index 7cf657a47d64..141b2aa515ad 100755 --- a/clang/www/cxx_dr_status.html +++ b/clang/www/cxx_dr_status.html @@ -685,7 +685,7 @@ 108 TC1 Are classes nested in templates dependent? - Yes + Clang 2.9 109 @@ -727,7 +727,7 @@ 115 CD1 Address of template-id - Yes + Clang 3.0 116 @@ -883,13 +883,13 @@ 141 CD1 Non-member function templates in member access expressions - Yes + Clang 3.1 142 TC1 Injection-related errors in access example - Yes + Clang 2.8 143 @@ -943,7 +943,7 @@ 151 TC1 Terminology of zero-initialization - Yes + Clang 3.1 152 @@ -1003,7 +1003,7 @@ 161 TC1 Access to protected nested type - Yes + Clang 3.1 162 @@ -1033,7 +1033,7 @@ 166 TC1 Friend declarations of template-ids - Yes + Clang 2.9 167 @@ -1087,13 +1087,13 @@ 175 CD1 Class name injection and base name access - Yes + Clang 2.8 176 TC1 Name injection and templates - Yes + Clang 3.1 177 @@ -1117,7 +1117,7 @@ 180 CD1 typename and elaborated types - Yes + Clang 2.8 181 -- GitLab From 5a1020bb0083ebfcf5d8879ba99c21bf214fcb56 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Fri, 1 Dec 2023 11:40:52 +0100 Subject: [PATCH 127/699] [InstSimplify] Add test for disjoint or miscompile (NFC) The absorption case is already handled correctly, but the idempentence case is not. --- llvm/test/Transforms/InstCombine/select.ll | 43 ++++++++++++++++----- llvm/test/Transforms/InstSimplify/select.ll | 38 ++++++++++++++++++ 2 files changed, 72 insertions(+), 9 deletions(-) diff --git a/llvm/test/Transforms/InstCombine/select.ll b/llvm/test/Transforms/InstCombine/select.ll index b3764cfb97d4..f1ccd4747bd1 100644 --- a/llvm/test/Transforms/InstCombine/select.ll +++ b/llvm/test/Transforms/InstCombine/select.ll @@ -1919,9 +1919,9 @@ define i32 @select_dominating_cond_inverted_multiple_duplicating_preds(i1 %cond, ; CHECK-NEXT: br i1 [[COND:%.*]], label [[IF_FALSE:%.*]], label [[IF_TRUE:%.*]] ; CHECK: if.true: ; CHECK-NEXT: switch i32 [[COND2:%.*]], label [[SWITCH_CASE_1:%.*]] [ -; CHECK-NEXT: i32 1, label [[MERGE:%.*]] -; CHECK-NEXT: i32 2, label [[MERGE]] -; CHECK-NEXT: i32 3, label [[MERGE]] +; CHECK-NEXT: i32 1, label [[MERGE:%.*]] +; CHECK-NEXT: i32 2, label [[MERGE]] +; CHECK-NEXT: i32 3, label [[MERGE]] ; CHECK-NEXT: ] ; CHECK: switch.case.1: ; CHECK-NEXT: br label [[MERGE]] @@ -2172,13 +2172,13 @@ define i32 @test_invoke_neg(i32 %x, i32 %y) nounwind uwtable ssp personality ptr ; CHECK-LABEL: @test_invoke_neg( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[COND:%.*]] = invoke i1 @foo() -; CHECK-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] +; CHECK-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] ; CHECK: invoke.cont: ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND]], i32 [[X:%.*]], i32 [[Y:%.*]] ; CHECK-NEXT: ret i32 [[SEL]] ; CHECK: lpad: ; CHECK-NEXT: [[LP:%.*]] = landingpad { i1, i32 } -; CHECK-NEXT: filter [0 x i1] zeroinitializer +; CHECK-NEXT: filter [0 x i1] zeroinitializer ; CHECK-NEXT: unreachable ; entry: @@ -2205,14 +2205,14 @@ define i32 @test_invoke_2_neg(i1 %cond, i32 %x, i32 %y) nounwind uwtable ssp per ; CHECK-NEXT: br label [[MERGE:%.*]] ; CHECK: if.false: ; CHECK-NEXT: [[RESULT:%.*]] = invoke i32 @bar() -; CHECK-NEXT: to label [[MERGE]] unwind label [[LPAD:%.*]] +; CHECK-NEXT: to label [[MERGE]] unwind label [[LPAD:%.*]] ; CHECK: merge: ; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ 0, [[IF_TRUE]] ], [ [[RESULT]], [[IF_FALSE]] ] ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND]], i32 1, i32 [[PHI]] ; CHECK-NEXT: ret i32 [[SEL]] ; CHECK: lpad: ; CHECK-NEXT: [[LP:%.*]] = landingpad { i1, i32 } -; CHECK-NEXT: filter [0 x i1] zeroinitializer +; CHECK-NEXT: filter [0 x i1] zeroinitializer ; CHECK-NEXT: unreachable ; entry: @@ -2242,8 +2242,8 @@ define i32 @select_phi_same_condition_switch(i1 %cond, i32 %x, i32 %y) { ; CHECK-NEXT: br i1 [[COND:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]] ; CHECK: if.true: ; CHECK-NEXT: switch i32 [[X:%.*]], label [[EXIT:%.*]] [ -; CHECK-NEXT: i32 1, label [[MERGE:%.*]] -; CHECK-NEXT: i32 2, label [[MERGE]] +; CHECK-NEXT: i32 1, label [[MERGE:%.*]] +; CHECK-NEXT: i32 2, label [[MERGE]] ; CHECK-NEXT: ] ; CHECK: exit: ; CHECK-NEXT: ret i32 0 @@ -2903,6 +2903,31 @@ define ptr @select_replacement_gep_inbounds(ptr %base, i64 %offset) { ret ptr %sel } +define i8 @replace_false_op_eq_shl_or_disjoint(i8 %x) { +; CHECK-LABEL: @replace_false_op_eq_shl_or_disjoint( +; CHECK-NEXT: [[SHL:%.*]] = shl i8 [[X:%.*]], 3 +; CHECK-NEXT: [[OR:%.*]] = or i8 [[SHL]], [[X]] +; CHECK-NEXT: ret i8 [[OR]] +; + %eq0 = icmp eq i8 %x, -1 + %shl = shl i8 %x, 3 + %or = or disjoint i8 %x, %shl + %sel = select i1 %eq0, i8 -1, i8 %or + ret i8 %sel +} + +; FIXME: This is a miscompile. +define i8 @select_or_disjoint_eq(i8 %x, i8 %y) { +; CHECK-LABEL: @select_or_disjoint_eq( +; CHECK-NEXT: [[OR:%.*]] = or disjoint i8 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: ret i8 [[OR]] +; + %cmp = icmp eq i8 %x, %y + %or = or disjoint i8 %x, %y + %sel = select i1 %cmp, i8 %x, i8 %or + ret i8 %sel +} + define <2 x i1> @partial_true_undef_condval(<2 x i1> %x) { ; CHECK-LABEL: @partial_true_undef_condval( ; CHECK-NEXT: ret <2 x i1> diff --git a/llvm/test/Transforms/InstSimplify/select.ll b/llvm/test/Transforms/InstSimplify/select.ll index 16901b888933..473d8b8b0368 100644 --- a/llvm/test/Transforms/InstSimplify/select.ll +++ b/llvm/test/Transforms/InstSimplify/select.ll @@ -1429,6 +1429,21 @@ define i8 @replace_false_op_eq_shl_or(i8 %x) { ret i8 %sel } +define i8 @replace_false_op_eq_shl_or_disjoint(i8 %x) { +; CHECK-LABEL: @replace_false_op_eq_shl_or_disjoint( +; CHECK-NEXT: [[EQ0:%.*]] = icmp eq i8 [[X:%.*]], -1 +; CHECK-NEXT: [[SHL:%.*]] = shl i8 [[X]], 3 +; CHECK-NEXT: [[OR:%.*]] = or disjoint i8 [[X]], [[SHL]] +; CHECK-NEXT: [[SEL:%.*]] = select i1 [[EQ0]], i8 -1, i8 [[OR]] +; CHECK-NEXT: ret i8 [[SEL]] +; + %eq0 = icmp eq i8 %x, -1 + %shl = shl i8 %x, 3 + %or = or disjoint i8 %x, %shl + %sel = select i1 %eq0, i8 -1, i8 %or + ret i8 %sel +} + ; negative test - wrong cmp predicate define i8 @replace_false_op_sgt_neg_and(i8 %x) { @@ -1698,3 +1713,26 @@ define i8 @select_xor_cmp_unmatched_operands(i8 %0, i8 %1, i8 %c) { %5 = select i1 %3, i8 0, i8 %4 ret i8 %5 } + +define i8 @select_or_eq(i8 %x, i8 %y) { +; CHECK-LABEL: @select_or_eq( +; CHECK-NEXT: [[OR:%.*]] = or i8 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: ret i8 [[OR]] +; + %cmp = icmp eq i8 %x, %y + %or = or i8 %x, %y + %sel = select i1 %cmp, i8 %x, i8 %or + ret i8 %sel +} + +; FIXME: This is a miscompile. +define i8 @select_or_disjoint_eq(i8 %x, i8 %y) { +; CHECK-LABEL: @select_or_disjoint_eq( +; CHECK-NEXT: [[OR:%.*]] = or disjoint i8 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: ret i8 [[OR]] +; + %cmp = icmp eq i8 %x, %y + %or = or disjoint i8 %x, %y + %sel = select i1 %cmp, i8 %x, i8 %or + ret i8 %sel +} -- GitLab From cd31cf5989aaf6a187aaf3af4f94207c55a70d0f Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Fri, 1 Dec 2023 11:43:17 +0100 Subject: [PATCH 128/699] [InstSimplify] Fix or disjoint miscompile with op replacement Make sure %x does not get folded to "or disjoint %x, %x" without dropping the flag, as this would be a derefinement. --- llvm/lib/Analysis/InstructionSimplify.cpp | 11 ++++++++++- llvm/test/Transforms/InstCombine/select.ll | 3 +-- llvm/test/Transforms/InstSimplify/select.ll | 7 ++++--- 3 files changed, 15 insertions(+), 6 deletions(-) diff --git a/llvm/lib/Analysis/InstructionSimplify.cpp b/llvm/lib/Analysis/InstructionSimplify.cpp index 9f3b3f25ec3f..cef9f6ec179b 100644 --- a/llvm/lib/Analysis/InstructionSimplify.cpp +++ b/llvm/lib/Analysis/InstructionSimplify.cpp @@ -4331,8 +4331,17 @@ static Value *simplifyWithOpReplaced(Value *V, Value *Op, Value *RepOp, // x & x -> x, x | x -> x if ((Opcode == Instruction::And || Opcode == Instruction::Or) && - NewOps[0] == NewOps[1]) + NewOps[0] == NewOps[1]) { + // or disjoint x, x results in poison. + if (auto *PDI = dyn_cast(BO)) { + if (PDI->isDisjoint()) { + if (!DropFlags) + return nullptr; + DropFlags->push_back(BO); + } + } return NewOps[0]; + } // x - x -> 0, x ^ x -> 0. This is non-refining, because x is non-poison // by assumption and this case never wraps, so nowrap flags can be diff --git a/llvm/test/Transforms/InstCombine/select.ll b/llvm/test/Transforms/InstCombine/select.ll index f1ccd4747bd1..6f24758effac 100644 --- a/llvm/test/Transforms/InstCombine/select.ll +++ b/llvm/test/Transforms/InstCombine/select.ll @@ -2916,10 +2916,9 @@ define i8 @replace_false_op_eq_shl_or_disjoint(i8 %x) { ret i8 %sel } -; FIXME: This is a miscompile. define i8 @select_or_disjoint_eq(i8 %x, i8 %y) { ; CHECK-LABEL: @select_or_disjoint_eq( -; CHECK-NEXT: [[OR:%.*]] = or disjoint i8 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[OR:%.*]] = or i8 [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: ret i8 [[OR]] ; %cmp = icmp eq i8 %x, %y diff --git a/llvm/test/Transforms/InstSimplify/select.ll b/llvm/test/Transforms/InstSimplify/select.ll index 473d8b8b0368..b9c79f02245c 100644 --- a/llvm/test/Transforms/InstSimplify/select.ll +++ b/llvm/test/Transforms/InstSimplify/select.ll @@ -1725,11 +1725,12 @@ define i8 @select_or_eq(i8 %x, i8 %y) { ret i8 %sel } -; FIXME: This is a miscompile. define i8 @select_or_disjoint_eq(i8 %x, i8 %y) { ; CHECK-LABEL: @select_or_disjoint_eq( -; CHECK-NEXT: [[OR:%.*]] = or disjoint i8 [[X:%.*]], [[Y:%.*]] -; CHECK-NEXT: ret i8 [[OR]] +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[OR:%.*]] = or disjoint i8 [[X]], [[Y]] +; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i8 [[X]], i8 [[OR]] +; CHECK-NEXT: ret i8 [[SEL]] ; %cmp = icmp eq i8 %x, %y %or = or disjoint i8 %x, %y -- GitLab From 89b0044ca9a6fb233f8d6dd16db6bd4acc3d3f61 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Fri, 1 Dec 2023 12:14:57 +0100 Subject: [PATCH 129/699] [InstSimplify] Add test for implied cond with equal ops and constant (NFC) --- llvm/test/Transforms/InstSimplify/implies.ll | 26 ++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/llvm/test/Transforms/InstSimplify/implies.ll b/llvm/test/Transforms/InstSimplify/implies.ll index 41f199542847..75044f4d9a35 100644 --- a/llvm/test/Transforms/InstSimplify/implies.ll +++ b/llvm/test/Transforms/InstSimplify/implies.ll @@ -499,4 +499,30 @@ define i1 @lshr_value(i32 %length.i, i32 %i, i32 %v) { ret i1 %res } +define i1 @same_ops_with_constant(i8 %x) { +; CHECK-LABEL: @same_ops_with_constant( +; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i8 [[X:%.*]], 5 +; CHECK-NEXT: [[CMP2:%.*]] = icmp ugt i8 [[X]], 5 +; CHECK-NEXT: [[RES:%.*]] = icmp ule i1 [[CMP1]], [[CMP2]] +; CHECK-NEXT: ret i1 [[RES]] +; + %cmp1 = icmp sgt i8 %x, 5 + %cmp2 = icmp ugt i8 %x, 5 + %res = icmp ule i1 %cmp1, %cmp2 + ret i1 %res +} + +define i1 @same_ops_with_constant_wrong_sign(i8 %x) { +; CHECK-LABEL: @same_ops_with_constant_wrong_sign( +; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i8 [[X:%.*]], -5 +; CHECK-NEXT: [[CMP2:%.*]] = icmp ugt i8 [[X]], -5 +; CHECK-NEXT: [[RES:%.*]] = icmp ule i1 [[CMP1]], [[CMP2]] +; CHECK-NEXT: ret i1 [[RES]] +; + %cmp1 = icmp sgt i8 %x, -5 + %cmp2 = icmp ugt i8 %x, -5 + %res = icmp ule i1 %cmp1, %cmp2 + ret i1 %res +} + declare void @llvm.assume(i1) -- GitLab From 460faa0c87f0a9496cdaf6c856aff1886e29afe3 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Fri, 1 Dec 2023 12:15:58 +0100 Subject: [PATCH 130/699] [InstSimplify] Check common operand with constant earlier If both icmps have the same operands and the RHS is constant, we would currently go into the isImpliedCondMatchingOperands() code path, instead of the isImpliedCondCommonOperandWithConstants() path. Both are correct, but the latter can produce more accurate results if the implication is dependent on the sign. --- llvm/lib/Analysis/ValueTracking.cpp | 10 +++++----- llvm/test/Transforms/InstSimplify/implies.ll | 5 +---- 2 files changed, 6 insertions(+), 9 deletions(-) diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp index 9cfe7315a7a4..d8a72c9f7b98 100644 --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -8352,17 +8352,17 @@ static std::optional isImpliedCondICmps(const ICmpInst *LHS, CmpInst::Predicate LPred = LHSIsTrue ? LHS->getPredicate() : LHS->getInversePredicate(); - // Can we infer anything when the two compares have matching operands? - bool AreSwappedOps; - if (areMatchingOperands(L0, L1, R0, R1, AreSwappedOps)) - return isImpliedCondMatchingOperands(LPred, RPred, AreSwappedOps); - // Can we infer anything when the 0-operands match and the 1-operands are // constants (not necessarily matching)? const APInt *LC, *RC; if (L0 == R0 && match(L1, m_APInt(LC)) && match(R1, m_APInt(RC))) return isImpliedCondCommonOperandWithConstants(LPred, *LC, RPred, *RC); + // Can we infer anything when the two compares have matching operands? + bool AreSwappedOps; + if (areMatchingOperands(L0, L1, R0, R1, AreSwappedOps)) + return isImpliedCondMatchingOperands(LPred, RPred, AreSwappedOps); + // L0 = R0 = L1 + R1, L0 >=u L1 implies R0 >=u R1, L0 Date: Fri, 1 Dec 2023 11:29:19 +0000 Subject: [PATCH 131/699] TargetInstrInfo: make getOperandLatency return optional (NFC) (#73769) getOperandLatency has the following behavior: it returns -1 as a special value, negative numbers other than -1 on some target-specific overrides, or a valid non-negative latency. This behavior can be surprising, as some callers do arithmetic on these negative values. Change the interface of getOperandLatency to return a std::optional to prevent surprises in callers. While at it, change the interface of getInstrLatency to return unsigned instead of int. This change was inspired by a refactoring in TargetSchedModel::computeOperandLatency. --- llvm/include/llvm/CodeGen/TargetInstrInfo.h | 18 +-- llvm/include/llvm/MC/MCInstrItineraries.h | 40 +++--- .../SelectionDAG/ScheduleDAGSDNodes.cpp | 9 +- llvm/lib/CodeGen/TargetInstrInfo.cpp | 23 ++-- llvm/lib/CodeGen/TargetSchedule.cpp | 32 +++-- llvm/lib/MC/MCDisassembler/Disassembler.cpp | 11 +- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 117 +++++++++--------- llvm/lib/Target/ARM/ARMBaseInstrInfo.h | 76 ++++++------ llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 14 +-- llvm/lib/Target/Hexagon/HexagonInstrInfo.h | 9 +- llvm/lib/Target/Hexagon/HexagonSubtarget.cpp | 27 ++-- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 23 ++-- llvm/lib/Target/PowerPC/PPCInstrInfo.h | 16 +-- 13 files changed, 209 insertions(+), 206 deletions(-) diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h index 58355a32315b..282fecc3ea81 100644 --- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h +++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h @@ -1706,9 +1706,9 @@ public: return Opcode <= TargetOpcode::COPY; } - virtual int getOperandLatency(const InstrItineraryData *ItinData, - SDNode *DefNode, unsigned DefIdx, - SDNode *UseNode, unsigned UseIdx) const; + virtual std::optional + getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, + unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const; /// Compute and return the use operand latency of a given pair of def and use. /// In most cases, the static scheduling itinerary was enough to determine the @@ -1718,10 +1718,10 @@ public: /// This is a raw interface to the itinerary that may be directly overridden /// by a target. Use computeOperandLatency to get the best estimate of /// latency. - virtual int getOperandLatency(const InstrItineraryData *ItinData, - const MachineInstr &DefMI, unsigned DefIdx, - const MachineInstr &UseMI, - unsigned UseIdx) const; + virtual std::optional + getOperandLatency(const InstrItineraryData *ItinData, + const MachineInstr &DefMI, unsigned DefIdx, + const MachineInstr &UseMI, unsigned UseIdx) const; /// Compute the instruction latency of a given instruction. /// If the instruction has higher cost when predicated, it's returned via @@ -1732,8 +1732,8 @@ public: virtual unsigned getPredicationCost(const MachineInstr &MI) const; - virtual int getInstrLatency(const InstrItineraryData *ItinData, - SDNode *Node) const; + virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, + SDNode *Node) const; /// Return the default expected latency for a def based on its opcode. unsigned defaultDefLatency(const MCSchedModel &SchedModel, diff --git a/llvm/include/llvm/MC/MCInstrItineraries.h b/llvm/include/llvm/MC/MCInstrItineraries.h index 652922feddc3..b17c41ce3aa4 100644 --- a/llvm/include/llvm/MC/MCInstrItineraries.h +++ b/llvm/include/llvm/MC/MCInstrItineraries.h @@ -17,6 +17,7 @@ #include "llvm/MC/MCSchedule.h" #include +#include namespace llvm { @@ -162,18 +163,19 @@ public: return Latency; } - /// Return the cycle for the given class and operand. Return -1 if no - /// cycle is specified for the operand. - int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const { + /// Return the cycle for the given class and operand. Return std::nullopt if + /// the information is not available for the operand. + std::optional getOperandCycle(unsigned ItinClassIndx, + unsigned OperandIdx) const { if (isEmpty()) - return -1; + return std::nullopt; unsigned FirstIdx = Itineraries[ItinClassIndx].FirstOperandCycle; unsigned LastIdx = Itineraries[ItinClassIndx].LastOperandCycle; if ((FirstIdx + OperandIdx) >= LastIdx) - return -1; + return std::nullopt; - return (int)OperandCycles[FirstIdx + OperandIdx]; + return OperandCycles[FirstIdx + OperandIdx]; } /// Return true if there is a pipeline forwarding between instructions @@ -201,25 +203,27 @@ public: /// Compute and return the use operand latency of a given itinerary /// class and operand index if the value is produced by an instruction of the - /// specified itinerary class and def operand index. - int getOperandLatency(unsigned DefClass, unsigned DefIdx, - unsigned UseClass, unsigned UseIdx) const { + /// specified itinerary class and def operand index. Return std::nullopt if + /// the information is not available for the operand. + std::optional getOperandLatency(unsigned DefClass, unsigned DefIdx, + unsigned UseClass, + unsigned UseIdx) const { if (isEmpty()) - return -1; + return std::nullopt; - int DefCycle = getOperandCycle(DefClass, DefIdx); - if (DefCycle == -1) - return -1; + std::optional DefCycle = getOperandCycle(DefClass, DefIdx); + std::optional UseCycle = getOperandCycle(UseClass, UseIdx); + if (!DefCycle || !UseCycle) + return std::nullopt; - int UseCycle = getOperandCycle(UseClass, UseIdx); - if (UseCycle == -1) - return -1; + if (UseCycle > *DefCycle + 1) + return std::nullopt; - UseCycle = DefCycle - UseCycle + 1; + UseCycle = *DefCycle - *UseCycle + 1; if (UseCycle > 0 && hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx)) // FIXME: This assumes one cycle benefit for every pipeline forwarding. - --UseCycle; + UseCycle = *UseCycle - 1; return UseCycle; } diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp index 0579c1664d5c..4d6d350c46f5 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp @@ -659,7 +659,8 @@ void ScheduleDAGSDNodes::computeOperandLatency(SDNode *Def, SDNode *Use, if (Use->isMachineOpcode()) // Adjust the use operand index by num of defs. OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs(); - int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx); + std::optional Latency = + TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx); if (Latency > 1 && Use->getOpcode() == ISD::CopyToReg && !BB->succ_empty()) { unsigned Reg = cast(Use->getOperand(1))->getReg(); @@ -667,10 +668,10 @@ void ScheduleDAGSDNodes::computeOperandLatency(SDNode *Def, SDNode *Use, // This copy is a liveout value. It is likely coalesced, so reduce the // latency so not to penalize the def. // FIXME: need target specific adjustment here? - Latency = Latency - 1; + Latency = *Latency - 1; } - if (Latency >= 0) - dep.setLatency(Latency); + if (Latency) + dep.setLatency(*Latency); } void ScheduleDAGSDNodes::dumpNode(const SUnit &SU) const { diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp index ac056fea8c37..fbb7c81fa1f8 100644 --- a/llvm/lib/CodeGen/TargetInstrInfo.cpp +++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp @@ -1379,15 +1379,15 @@ bool TargetInstrInfo::getMemOperandWithOffset( // SelectionDAG latency interface. //===----------------------------------------------------------------------===// -int +std::optional TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const { if (!ItinData || ItinData->isEmpty()) - return -1; + return std::nullopt; if (!DefNode->isMachineOpcode()) - return -1; + return std::nullopt; unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass(); if (!UseNode->isMachineOpcode()) @@ -1396,8 +1396,8 @@ TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); } -int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, - SDNode *N) const { +unsigned TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, + SDNode *N) const { if (!ItinData || ItinData->isEmpty()) return 1; @@ -1461,8 +1461,9 @@ bool TargetInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel, return false; unsigned DefClass = DefMI.getDesc().getSchedClass(); - int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); - return (DefCycle != -1 && DefCycle <= 1); + std::optional DefCycle = + ItinData->getOperandCycle(DefClass, DefIdx); + return DefCycle <= 1; } bool TargetInstrInfo::isFunctionSafeToSplit(const MachineFunction &MF) const { @@ -1580,11 +1581,9 @@ unsigned TargetInstrInfo::getCallFrameSizeAt(MachineInstr &MI) const { /// Both DefMI and UseMI must be valid. By default, call directly to the /// itinerary. This may be overriden by the target. -int TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, - const MachineInstr &DefMI, - unsigned DefIdx, - const MachineInstr &UseMI, - unsigned UseIdx) const { +std::optional TargetInstrInfo::getOperandLatency( + const InstrItineraryData *ItinData, const MachineInstr &DefMI, + unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const { unsigned DefClass = DefMI.getDesc().getSchedClass(); unsigned UseClass = UseMI.getDesc().getSchedClass(); return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); diff --git a/llvm/lib/CodeGen/TargetSchedule.cpp b/llvm/lib/CodeGen/TargetSchedule.cpp index 3cedb38de2ad..a25d4ff78f4d 100644 --- a/llvm/lib/CodeGen/TargetSchedule.cpp +++ b/llvm/lib/CodeGen/TargetSchedule.cpp @@ -168,16 +168,20 @@ static unsigned findUseIdx(const MachineInstr *MI, unsigned UseOperIdx) { return UseIdx; } -// Top-level API for clients that know the operand indices. +// Top-level API for clients that know the operand indices. This doesn't need to +// return std::optional, as it always returns a valid latency. unsigned TargetSchedModel::computeOperandLatency( const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *UseMI, unsigned UseOperIdx) const { + const unsigned InstrLatency = computeInstrLatency(DefMI); + const unsigned DefaultDefLatency = TII->defaultDefLatency(SchedModel, *DefMI); + if (!hasInstrSchedModel() && !hasInstrItineraries()) - return TII->defaultDefLatency(SchedModel, *DefMI); + return InstrLatency; if (hasInstrItineraries()) { - int OperLatency = 0; + std::optional OperLatency; if (UseMI) { OperLatency = TII->getOperandLatency(&InstrItins, *DefMI, DefOperIdx, *UseMI, UseOperIdx); @@ -186,21 +190,13 @@ unsigned TargetSchedModel::computeOperandLatency( unsigned DefClass = DefMI->getDesc().getSchedClass(); OperLatency = InstrItins.getOperandCycle(DefClass, DefOperIdx); } - if (OperLatency >= 0) - return OperLatency; - - // No operand latency was found. - unsigned InstrLatency = TII->getInstrLatency(&InstrItins, *DefMI); - - // Expected latency is the max of the stage latency and itinerary props. - // Rather than directly querying InstrItins stage latency, we call a TII - // hook to allow subtargets to specialize latency. This hook is only - // applicable to the InstrItins model. InstrSchedModel should model all - // special cases without TII hooks. - InstrLatency = - std::max(InstrLatency, TII->defaultDefLatency(SchedModel, *DefMI)); - return InstrLatency; + + // Expected latency is the max of InstrLatency and DefaultDefLatency, if we + // didn't find an operand latency. + return OperLatency ? *OperLatency + : std::max(InstrLatency, DefaultDefLatency); } + // hasInstrSchedModel() const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); @@ -237,7 +233,7 @@ unsigned TargetSchedModel::computeOperandLatency( // FIXME: Automatically giving all implicit defs defaultDefLatency is // undesirable. We should only do it for defs that are known to the MC // desc like flags. Truly implicit defs should get 1 cycle latency. - return DefMI->isTransient() ? 0 : TII->defaultDefLatency(SchedModel, *DefMI); + return DefMI->isTransient() ? 0 : DefaultDefLatency; } unsigned diff --git a/llvm/lib/MC/MCDisassembler/Disassembler.cpp b/llvm/lib/MC/MCDisassembler/Disassembler.cpp index 067b951fbfcc..5e5a163c2902 100644 --- a/llvm/lib/MC/MCDisassembler/Disassembler.cpp +++ b/llvm/lib/MC/MCDisassembler/Disassembler.cpp @@ -180,12 +180,13 @@ static int getItineraryLatency(LLVMDisasmContext *DC, const MCInst &Inst) { const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode()); unsigned SCClass = Desc.getSchedClass(); - int Latency = 0; - for (unsigned OpIdx = 0, OpIdxEnd = Inst.getNumOperands(); OpIdx != OpIdxEnd; - ++OpIdx) - Latency = std::max(Latency, IID.getOperandCycle(SCClass, OpIdx)); + unsigned Latency = 0; - return Latency; + for (unsigned Idx = 0, IdxEnd = Inst.getNumOperands(); Idx != IdxEnd; ++Idx) + if (std::optional OperCycle = IID.getOperandCycle(SCClass, Idx)) + Latency = std::max(Latency, *OperCycle); + + return (int)Latency; } /// Gets latency information for \p Inst, based on \p DC information. diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index c09879fd9c2b..94f34b127696 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -3872,17 +3872,16 @@ unsigned ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, llvm_unreachable("Didn't find the number of microops"); } -int +std::optional ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, - const MCInstrDesc &DefMCID, - unsigned DefClass, + const MCInstrDesc &DefMCID, unsigned DefClass, unsigned DefIdx, unsigned DefAlign) const { int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; if (RegNo <= 0) // Def is the address writeback. return ItinData->getOperandCycle(DefClass, DefIdx); - int DefCycle; + unsigned DefCycle; if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) { // (regno / 2) + (regno % 2) + 1 DefCycle = RegNo / 2 + 1; @@ -3913,17 +3912,16 @@ ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, return DefCycle; } -int +std::optional ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, - const MCInstrDesc &DefMCID, - unsigned DefClass, + const MCInstrDesc &DefMCID, unsigned DefClass, unsigned DefIdx, unsigned DefAlign) const { int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; if (RegNo <= 0) // Def is the address writeback. return ItinData->getOperandCycle(DefClass, DefIdx); - int DefCycle; + unsigned DefCycle; if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) { // 4 registers would be issued: 1, 2, 1. // 5 registers would be issued: 1, 2, 2. @@ -3948,16 +3946,15 @@ ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, return DefCycle; } -int +std::optional ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData, - const MCInstrDesc &UseMCID, - unsigned UseClass, + const MCInstrDesc &UseMCID, unsigned UseClass, unsigned UseIdx, unsigned UseAlign) const { int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; if (RegNo <= 0) return ItinData->getOperandCycle(UseClass, UseIdx); - int UseCycle; + unsigned UseCycle; if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) { // (regno / 2) + (regno % 2) + 1 UseCycle = RegNo / 2 + 1; @@ -3988,16 +3985,15 @@ ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData, return UseCycle; } -int +std::optional ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData, - const MCInstrDesc &UseMCID, - unsigned UseClass, + const MCInstrDesc &UseMCID, unsigned UseClass, unsigned UseIdx, unsigned UseAlign) const { int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; if (RegNo <= 0) return ItinData->getOperandCycle(UseClass, UseIdx); - int UseCycle; + unsigned UseCycle; if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) { UseCycle = RegNo / 2; if (UseCycle < 2) @@ -4017,12 +4013,10 @@ ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData, return UseCycle; } -int -ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, - const MCInstrDesc &DefMCID, - unsigned DefIdx, unsigned DefAlign, - const MCInstrDesc &UseMCID, - unsigned UseIdx, unsigned UseAlign) const { +std::optional ARMBaseInstrInfo::getOperandLatency( + const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, + unsigned DefIdx, unsigned DefAlign, const MCInstrDesc &UseMCID, + unsigned UseIdx, unsigned UseAlign) const { unsigned DefClass = DefMCID.getSchedClass(); unsigned UseClass = UseMCID.getSchedClass(); @@ -4032,7 +4026,7 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, // This may be a def / use of a variable_ops instruction, the operand // latency might be determinable dynamically. Let the target try to // figure it out. - int DefCycle = -1; + std::optional DefCycle; bool LdmBypass = false; switch (DefMCID.getOpcode()) { default: @@ -4070,11 +4064,11 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, break; } - if (DefCycle == -1) + if (!DefCycle) // We can't seem to determine the result latency of the def, assume it's 2. DefCycle = 2; - int UseCycle = -1; + std::optional UseCycle; switch (UseMCID.getOpcode()) { default: UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); @@ -4108,21 +4102,24 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, break; } - if (UseCycle == -1) + if (!UseCycle) // Assume it's read in the first stage. UseCycle = 1; - UseCycle = DefCycle - UseCycle + 1; + if (UseCycle > *DefCycle + 1) + return std::nullopt; + + UseCycle = *DefCycle - *UseCycle + 1; if (UseCycle > 0) { if (LdmBypass) { // It's a variable_ops instruction so we can't use DefIdx here. Just use // first def operand. if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1, UseClass, UseIdx)) - --UseCycle; + UseCycle = *UseCycle - 1; } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx)) { - --UseCycle; + UseCycle = *UseCycle - 1; } } @@ -4362,14 +4359,12 @@ static int adjustDefLatency(const ARMSubtarget &Subtarget, return Adjust; } -int ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, - const MachineInstr &DefMI, - unsigned DefIdx, - const MachineInstr &UseMI, - unsigned UseIdx) const { +std::optional ARMBaseInstrInfo::getOperandLatency( + const InstrItineraryData *ItinData, const MachineInstr &DefMI, + unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const { // No operand latency. The caller may fall back to getInstrLatency. if (!ItinData || ItinData->isEmpty()) - return -1; + return std::nullopt; const MachineOperand &DefMO = DefMI.getOperand(DefIdx); Register Reg = DefMO.getReg(); @@ -4390,7 +4385,7 @@ int ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, ResolvedUseMI = getBundledUseMI(&getRegisterInfo(), UseMI, Reg, UseIdx, UseAdj); if (!ResolvedUseMI) - return -1; + return std::nullopt; } return getOperandLatencyImpl( @@ -4398,7 +4393,7 @@ int ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, Reg, *ResolvedUseMI, UseIdx, ResolvedUseMI->getDesc(), UseAdj); } -int ARMBaseInstrInfo::getOperandLatencyImpl( +std::optional ARMBaseInstrInfo::getOperandLatencyImpl( const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj, const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI, @@ -4430,7 +4425,7 @@ int ARMBaseInstrInfo::getOperandLatencyImpl( } if (DefMO.isImplicit() || UseMI.getOperand(UseIdx).isImplicit()) - return -1; + return std::nullopt; unsigned DefAlign = DefMI.hasOneMemOperand() ? (*DefMI.memoperands_begin())->getAlign().value() @@ -4440,25 +4435,25 @@ int ARMBaseInstrInfo::getOperandLatencyImpl( : 0; // Get the itinerary's latency if possible, and handle variable_ops. - int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, UseMCID, - UseIdx, UseAlign); + std::optional Latency = getOperandLatency( + ItinData, DefMCID, DefIdx, DefAlign, UseMCID, UseIdx, UseAlign); // Unable to find operand latency. The caller may resort to getInstrLatency. - if (Latency < 0) - return Latency; + if (!Latency) + return std::nullopt; // Adjust for IT block position. int Adj = DefAdj + UseAdj; // Adjust for dynamic def-side opcode variants not captured by the itinerary. Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign); - if (Adj >= 0 || (int)Latency > -Adj) { - return Latency + Adj; + if (Adj >= 0 || (int)*Latency > -Adj) { + return *Latency + Adj; } // Return the itinerary latency, which may be zero but not less than zero. return Latency; } -int +std::optional ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const { @@ -4474,10 +4469,11 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, return DefMCID.mayLoad() ? 3 : 1; if (!UseNode->isMachineOpcode()) { - int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx); + std::optional Latency = + ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx); int Adj = Subtarget.getPreISelOperandLatencyAdjustment(); int Threshold = 1 + Adj; - return Latency <= Threshold ? 1 : Latency - Adj; + return !Latency || Latency <= Threshold ? 1 : *Latency - Adj; } const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode()); @@ -4489,8 +4485,10 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, unsigned UseAlign = !UseMN->memoperands_empty() ? (*UseMN->memoperands_begin())->getAlign().value() : 0; - int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, - UseMCID, UseIdx, UseAlign); + std::optional Latency = getOperandLatency( + ItinData, DefMCID, DefIdx, DefAlign, UseMCID, UseIdx, UseAlign); + if (!Latency) + return std::nullopt; if (Latency > 1 && (Subtarget.isCortexA8() || Subtarget.isLikeA9() || @@ -4506,7 +4504,7 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); if (ShImm == 0 || (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) - --Latency; + Latency = *Latency - 1; break; } case ARM::t2LDRs: @@ -4517,7 +4515,7 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, unsigned ShAmt = cast(DefNode->getOperand(2))->getZExtValue(); if (ShAmt == 0 || ShAmt == 2) - --Latency; + Latency = *Latency - 1; break; } } @@ -4534,9 +4532,9 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, if (ShImm == 0 || ((ShImm == 1 || ShImm == 2 || ShImm == 3) && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) - Latency -= 2; + Latency = *Latency - 2; else if (ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr) - --Latency; + Latency = *Latency - 1; break; } case ARM::t2LDRs: @@ -4544,7 +4542,7 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, case ARM::t2LDRHs: case ARM::t2LDRSHs: // Thumb2 mode: lsl 0-3 only. - Latency -= 2; + Latency = *Latency - 2; break; } } @@ -4710,7 +4708,7 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, case ARM::VLD4LNq32Pseudo_UPD: // If the address is not 64-bit aligned, the latencies of these // instructions increases by one. - ++Latency; + Latency = *Latency + 1; break; } @@ -4787,8 +4785,8 @@ unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, return Latency; } -int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, - SDNode *Node) const { +unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, + SDNode *Node) const { if (!Node->isMachineOpcode()) return 1; @@ -4836,8 +4834,9 @@ bool ARMBaseInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel, unsigned DDomain = DefMI.getDesc().TSFlags & ARMII::DomainMask; if (DDomain == ARMII::DomainGeneral) { unsigned DefClass = DefMI.getDesc().getSchedClass(); - int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); - return (DefCycle != -1 && DefCycle <= 2); + std::optional DefCycle = + ItinData->getOperandCycle(DefClass, DefIdx); + return DefCycle <= 2; } return false; } diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h index 5efcc1a0d9fc..6aebf3b64e8d 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h @@ -316,13 +316,15 @@ public: unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const override; - int getOperandLatency(const InstrItineraryData *ItinData, - const MachineInstr &DefMI, unsigned DefIdx, - const MachineInstr &UseMI, - unsigned UseIdx) const override; - int getOperandLatency(const InstrItineraryData *ItinData, - SDNode *DefNode, unsigned DefIdx, - SDNode *UseNode, unsigned UseIdx) const override; + std::optional getOperandLatency(const InstrItineraryData *ItinData, + const MachineInstr &DefMI, + unsigned DefIdx, + const MachineInstr &UseMI, + unsigned UseIdx) const override; + std::optional getOperandLatency(const InstrItineraryData *ItinData, + SDNode *DefNode, unsigned DefIdx, + SDNode *UseNode, + unsigned UseIdx) const override; /// VFP/NEON execution domains. std::pair @@ -421,34 +423,34 @@ private: unsigned getInstBundleLength(const MachineInstr &MI) const; - int getVLDMDefCycle(const InstrItineraryData *ItinData, - const MCInstrDesc &DefMCID, - unsigned DefClass, - unsigned DefIdx, unsigned DefAlign) const; - int getLDMDefCycle(const InstrItineraryData *ItinData, - const MCInstrDesc &DefMCID, - unsigned DefClass, - unsigned DefIdx, unsigned DefAlign) const; - int getVSTMUseCycle(const InstrItineraryData *ItinData, - const MCInstrDesc &UseMCID, - unsigned UseClass, - unsigned UseIdx, unsigned UseAlign) const; - int getSTMUseCycle(const InstrItineraryData *ItinData, - const MCInstrDesc &UseMCID, - unsigned UseClass, - unsigned UseIdx, unsigned UseAlign) const; - int getOperandLatency(const InstrItineraryData *ItinData, - const MCInstrDesc &DefMCID, - unsigned DefIdx, unsigned DefAlign, - const MCInstrDesc &UseMCID, - unsigned UseIdx, unsigned UseAlign) const; - - int getOperandLatencyImpl(const InstrItineraryData *ItinData, - const MachineInstr &DefMI, unsigned DefIdx, - const MCInstrDesc &DefMCID, unsigned DefAdj, - const MachineOperand &DefMO, unsigned Reg, - const MachineInstr &UseMI, unsigned UseIdx, - const MCInstrDesc &UseMCID, unsigned UseAdj) const; + std::optional getVLDMDefCycle(const InstrItineraryData *ItinData, + const MCInstrDesc &DefMCID, + unsigned DefClass, unsigned DefIdx, + unsigned DefAlign) const; + std::optional getLDMDefCycle(const InstrItineraryData *ItinData, + const MCInstrDesc &DefMCID, + unsigned DefClass, unsigned DefIdx, + unsigned DefAlign) const; + std::optional getVSTMUseCycle(const InstrItineraryData *ItinData, + const MCInstrDesc &UseMCID, + unsigned UseClass, unsigned UseIdx, + unsigned UseAlign) const; + std::optional getSTMUseCycle(const InstrItineraryData *ItinData, + const MCInstrDesc &UseMCID, + unsigned UseClass, unsigned UseIdx, + unsigned UseAlign) const; + std::optional getOperandLatency(const InstrItineraryData *ItinData, + const MCInstrDesc &DefMCID, + unsigned DefIdx, unsigned DefAlign, + const MCInstrDesc &UseMCID, + unsigned UseIdx, + unsigned UseAlign) const; + + std::optional getOperandLatencyImpl( + const InstrItineraryData *ItinData, const MachineInstr &DefMI, + unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj, + const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI, + unsigned UseIdx, const MCInstrDesc &UseMCID, unsigned UseAdj) const; unsigned getPredicationCost(const MachineInstr &MI) const override; @@ -456,8 +458,8 @@ private: const MachineInstr &MI, unsigned *PredCost = nullptr) const override; - int getInstrLatency(const InstrItineraryData *ItinData, - SDNode *Node) const override; + unsigned getInstrLatency(const InstrItineraryData *ItinData, + SDNode *Node) const override; bool hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index 6f0210763bc5..1689b8f1e132 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -4295,11 +4295,9 @@ unsigned HexagonInstrInfo::getInstrTimingClassLatency( /// /// This is a raw interface to the itinerary that may be directly overriden by /// a target. Use computeOperandLatency to get the best estimate of latency. -int HexagonInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, - const MachineInstr &DefMI, - unsigned DefIdx, - const MachineInstr &UseMI, - unsigned UseIdx) const { +std::optional HexagonInstrInfo::getOperandLatency( + const InstrItineraryData *ItinData, const MachineInstr &DefMI, + unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const { const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); // Get DefIdx and UseIdx for super registers. @@ -4328,9 +4326,9 @@ int HexagonInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, } } - int Latency = TargetInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx, - UseMI, UseIdx); - if (!Latency) + std::optional Latency = TargetInstrInfo::getOperandLatency( + ItinData, DefMI, DefIdx, UseMI, UseIdx); + if (Latency == 0) // We should never have 0 cycle latency between two instructions unless // they can be packetized together. However, this decision can't be made // here. diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h index 0bc0877f6e70..645b57f4664d 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h @@ -309,10 +309,11 @@ public: /// /// This is a raw interface to the itinerary that may be directly overriden by /// a target. Use computeOperandLatency to get the best estimate of latency. - int getOperandLatency(const InstrItineraryData *ItinData, - const MachineInstr &DefMI, unsigned DefIdx, - const MachineInstr &UseMI, - unsigned UseIdx) const override; + std::optional getOperandLatency(const InstrItineraryData *ItinData, + const MachineInstr &DefMI, + unsigned DefIdx, + const MachineInstr &UseMI, + unsigned UseIdx) const override; /// Decompose the machine operand's target flags into two values - the direct /// target flag value and any of bit flags that are applied. diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp index 1c9c258df947..e1ad15bbc7c1 100644 --- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp +++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp @@ -467,7 +467,7 @@ void HexagonSubtarget::adjustSchedDependency(SUnit *Src, int SrcOpIdx, // default. if ((DstInst->isRegSequence() || DstInst->isCopy())) { Register DReg = DstInst->getOperand(0).getReg(); - int DLatency = -1; + std::optional DLatency; for (const auto &DDep : Dst->Succs) { MachineInstr *DDst = DDep.getSUnit()->getInstr(); int UseIdx = -1; @@ -482,21 +482,21 @@ void HexagonSubtarget::adjustSchedDependency(SUnit *Src, int SrcOpIdx, if (UseIdx == -1) continue; - int Latency = (InstrInfo.getOperandLatency(&InstrItins, *SrcInst, 0, - *DDst, UseIdx)); + std::optional Latency = + InstrInfo.getOperandLatency(&InstrItins, *SrcInst, 0, *DDst, UseIdx); + // Set DLatency for the first time. - DLatency = (DLatency == -1) ? Latency : DLatency; + if (!DLatency) + DLatency = Latency; // For multiple uses, if the Latency is different across uses, reset // DLatency. if (DLatency != Latency) { - DLatency = -1; + DLatency = std::nullopt; break; } } - - DLatency = std::max(DLatency, 0); - Dep.setLatency((unsigned)DLatency); + Dep.setLatency(DLatency ? *DLatency : 0); } // Try to schedule uses near definitions to generate .cur. @@ -581,15 +581,16 @@ void HexagonSubtarget::restoreLatency(SUnit *Src, SUnit *Dst) const { for (unsigned OpNum = 0; OpNum < DstI->getNumOperands(); OpNum++) { const MachineOperand &MO = DstI->getOperand(OpNum); if (MO.isReg() && MO.isUse() && MO.getReg() == DepR) { - int Latency = (InstrInfo.getOperandLatency(&InstrItins, *SrcI, - DefIdx, *DstI, OpNum)); + std::optional Latency = InstrInfo.getOperandLatency( + &InstrItins, *SrcI, DefIdx, *DstI, OpNum); // For some instructions (ex: COPY), we might end up with < 0 latency // as they don't have any Itinerary class associated with them. - Latency = std::max(Latency, 0); + if (!Latency) + Latency = 0; bool IsArtificial = I.isArtificial(); - Latency = updateLatency(*SrcI, *DstI, IsArtificial, Latency); - I.setLatency(Latency); + Latency = updateLatency(*SrcI, *DstI, IsArtificial, *Latency); + I.setLatency(*Latency); } } diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index 6784049348b1..49d003db8ffc 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -155,22 +155,21 @@ unsigned PPCInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, if (!MO.isReg() || !MO.isDef() || MO.isImplicit()) continue; - int Cycle = ItinData->getOperandCycle(DefClass, i); - if (Cycle < 0) + std::optional Cycle = ItinData->getOperandCycle(DefClass, i); + if (!Cycle) continue; - Latency = std::max(Latency, (unsigned) Cycle); + Latency = std::max(Latency, *Cycle); } return Latency; } -int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, - const MachineInstr &DefMI, unsigned DefIdx, - const MachineInstr &UseMI, - unsigned UseIdx) const { - int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx, - UseMI, UseIdx); +std::optional PPCInstrInfo::getOperandLatency( + const InstrItineraryData *ItinData, const MachineInstr &DefMI, + unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const { + std::optional Latency = PPCGenInstrInfo::getOperandLatency( + ItinData, DefMI, DefIdx, UseMI, UseIdx); if (!DefMI.getParent()) return Latency; @@ -190,7 +189,7 @@ int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, } if (UseMI.isBranch() && IsRegCR) { - if (Latency < 0) + if (!Latency) Latency = getInstrLatency(ItinData, DefMI); // On some cores, there is an additional delay between writing to a condition @@ -210,8 +209,8 @@ int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, case PPC::DIR_PWR7: case PPC::DIR_PWR8: // FIXME: Is this needed for POWER9? - Latency += 2; - break; + Latency = *Latency + 2; + break; } } diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h index 31e9859a4173..a8dc7d6d0e37 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h @@ -294,13 +294,15 @@ public: const MachineInstr &MI, unsigned *PredCost = nullptr) const override; - int getOperandLatency(const InstrItineraryData *ItinData, - const MachineInstr &DefMI, unsigned DefIdx, - const MachineInstr &UseMI, - unsigned UseIdx) const override; - int getOperandLatency(const InstrItineraryData *ItinData, - SDNode *DefNode, unsigned DefIdx, - SDNode *UseNode, unsigned UseIdx) const override { + std::optional getOperandLatency(const InstrItineraryData *ItinData, + const MachineInstr &DefMI, + unsigned DefIdx, + const MachineInstr &UseMI, + unsigned UseIdx) const override; + std::optional getOperandLatency(const InstrItineraryData *ItinData, + SDNode *DefNode, unsigned DefIdx, + SDNode *UseNode, + unsigned UseIdx) const override { return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, UseNode, UseIdx); } -- GitLab From 5a32014d82334c4c66c8cc7ae3ed2a489c07db07 Mon Sep 17 00:00:00 2001 From: "Oleksandr \"Alex\" Zinenko" Date: Fri, 1 Dec 2023 12:53:35 +0100 Subject: [PATCH 132/699] [mlir] update linalg transform ops docs --- .../Dialect/Linalg/TransformOps/LinalgTransformOps.td | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td b/mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td index fb660c646126..002926ff965f 100644 --- a/mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td +++ b/mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td @@ -1910,16 +1910,20 @@ def TileUsingForallOp : #### Example using `num_threads` ``` - %0 = pdl_match @match_matmul in %arg1 + %0 = transform.structured.match ops{["linalg.matmul"]} in %arg1 + : (!transform.any_op) -> !transform.any_op %3:2 = transform.structured.tile_using_forall %0 num_threads [10, 20] + : (!transform.any_op) -> (!transform.any_op, !transform.any_op) ``` #### Example using `tile_sizes` ``` - %0 = pdl_match @match_matmul in %arg1 - %sz = pdl_match @match_size_op in %arg1 + %0 = transform.structured.match ops{["linalg.matmul"]} in %arg1 + : (!transform.any_op) -> !transform.any_op + %sz = transform.structured.match ... %3:2 = transform.structured.tile_using_forall %0 tile_sizes [0, %sz, 20] + : (!transform.any_op, !transform.any_op) -> (!transform.any_op, !transform.any_op) ``` }]; -- GitLab From 69020827cf611170d0bc80879114a2427aa39960 Mon Sep 17 00:00:00 2001 From: Shivam Gupta Date: Fri, 1 Dec 2023 17:27:19 +0530 Subject: [PATCH 133/699] [NFC] Remove a space in CMake.rst The rendered document is not correctly indentated because of this space. --- llvm/docs/CMake.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/docs/CMake.rst b/llvm/docs/CMake.rst index 4b86eb9c01d2..7dd3fd26022e 100644 --- a/llvm/docs/CMake.rst +++ b/llvm/docs/CMake.rst @@ -389,7 +389,7 @@ enabled sub-projects. Nearly all of these variable names begin with will limit code coverage summaries to just the listed directories. If unset, coverage reports will include all sources identified by the tooling. - **LLVM_INDIVIDUAL_TEST_COVERAGE**: BOOL +**LLVM_INDIVIDUAL_TEST_COVERAGE**:BOOL Enable individual test case coverage. When set to ON, code coverage data for each test case will be generated and stored in a separate directory under the config.test_exec_root path. This feature allows code coverage analysis of each -- GitLab From 8727982bdfb84ce4adbd138c146a6b7ecaf98fdb Mon Sep 17 00:00:00 2001 From: Simon Tatham Date: Fri, 1 Dec 2023 12:00:18 +0000 Subject: [PATCH 134/699] [Driver] Add exclusive-group feature to multilib.yaml. (#69447) This allows a YAML-based multilib configuration to specify explicitly that a subset of its library directories are alternatives to each other, i.e. at most one of that subset should be selected. So if you have multiple sysroots each including a full set of headers and libraries, you can mark them as members of the same mutually exclusive group, and then you'll be sure that only one of them is selected, even if two or more are compatible with the compile options. This is particularly important in multilib setups including the libc++ headers, where selecting the include directories from two different sysroots can cause an actual build failure. This occurs when including , for example: libc++'s stdio.h is included first, and will try to use `#include_next` to fetch the underlying libc's version. But if there are two include directories from separate multilibs, then both of their C++ include directories will end up on the include path first, followed by both the C directories. So the `#include_next` from the first libc++ stdio.h will include the second libc++ stdio.h, which will do nothing because it has the same include guard macro, and the libc header won't ever be included at all. If more than one of the options in an exclusive group matches the given flags, the last one wins. The syntax for specifying this in multilib.yaml is to define a Groups section in which you specify your group names, and for each one, declare it to have Type: Exclusive. (This reserves space in the syntax for maybe adding other group types later, such as a group of mutually _dependent_ things that you must have all or none of.) Then each Variant record that's a member of a group has a Group: property giving that group's name. --- clang/include/clang/Driver/Multilib.h | 16 ++- clang/lib/Driver/Multilib.cpp | 108 ++++++++++++++++-- .../baremetal-multilib-exclusive-group.yaml | 79 +++++++++++++ .../baremetal-multilib-group-error.yaml | 27 +++++ 4 files changed, 218 insertions(+), 12 deletions(-) create mode 100644 clang/test/Driver/baremetal-multilib-exclusive-group.yaml create mode 100644 clang/test/Driver/baremetal-multilib-group-error.yaml diff --git a/clang/include/clang/Driver/Multilib.h b/clang/include/clang/Driver/Multilib.h index 1416559414f8..6a9533e6dd83 100644 --- a/clang/include/clang/Driver/Multilib.h +++ b/clang/include/clang/Driver/Multilib.h @@ -39,13 +39,22 @@ private: std::string IncludeSuffix; flags_list Flags; + // Optionally, a multilib can be assigned a string tag indicating that it's + // part of a group of mutually exclusive possibilities. If two or more + // multilibs have the same non-empty value of ExclusiveGroup, then only the + // last matching one of them will be selected. + // + // Setting this to the empty string is a special case, indicating that the + // directory is not mutually exclusive with anything else. + std::string ExclusiveGroup; + public: /// GCCSuffix, OSSuffix & IncludeSuffix will be appended directly to the /// sysroot string so they must either be empty or begin with a '/' character. /// This is enforced with an assert in the constructor. Multilib(StringRef GCCSuffix = {}, StringRef OSSuffix = {}, - StringRef IncludeSuffix = {}, - const flags_list &Flags = flags_list()); + StringRef IncludeSuffix = {}, const flags_list &Flags = flags_list(), + StringRef ExclusiveGroup = {}); /// Get the detected GCC installation path suffix for the multi-arch /// target variant. Always starts with a '/', unless empty @@ -63,6 +72,9 @@ public: /// All elements begin with either '-' or '!' const flags_list &flags() const { return Flags; } + /// Get the exclusive group label. + const std::string &exclusiveGroup() const { return ExclusiveGroup; } + LLVM_DUMP_METHOD void dump() const; /// print summary of the Multilib void print(raw_ostream &OS) const; diff --git a/clang/lib/Driver/Multilib.cpp b/clang/lib/Driver/Multilib.cpp index 48a494d9fa38..7681c1a3ce67 100644 --- a/clang/lib/Driver/Multilib.cpp +++ b/clang/lib/Driver/Multilib.cpp @@ -9,6 +9,7 @@ #include "clang/Driver/Multilib.h" #include "clang/Basic/LLVM.h" #include "clang/Basic/Version.h" +#include "llvm/ADT/DenseSet.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/StringRef.h" #include "llvm/Support/Compiler.h" @@ -29,9 +30,10 @@ using namespace driver; using namespace llvm::sys; Multilib::Multilib(StringRef GCCSuffix, StringRef OSSuffix, - StringRef IncludeSuffix, const flags_list &Flags) + StringRef IncludeSuffix, const flags_list &Flags, + StringRef ExclusiveGroup) : GCCSuffix(GCCSuffix), OSSuffix(OSSuffix), IncludeSuffix(IncludeSuffix), - Flags(Flags) { + Flags(Flags), ExclusiveGroup(ExclusiveGroup) { assert(GCCSuffix.empty() || (StringRef(GCCSuffix).front() == '/' && GCCSuffix.size() > 1)); assert(OSSuffix.empty() || @@ -96,13 +98,37 @@ bool MultilibSet::select(const Multilib::flags_list &Flags, llvm::SmallVector &Selected) const { llvm::StringSet<> FlagSet(expandFlags(Flags)); Selected.clear(); - llvm::copy_if(Multilibs, std::back_inserter(Selected), - [&FlagSet](const Multilib &M) { - for (const std::string &F : M.flags()) - if (!FlagSet.contains(F)) - return false; - return true; - }); + + // Decide which multilibs we're going to select at all. + llvm::DenseSet ExclusiveGroupsSelected; + for (const Multilib &M : llvm::reverse(Multilibs)) { + // If this multilib doesn't match all our flags, don't select it. + if (!llvm::all_of(M.flags(), [&FlagSet](const std::string &F) { + return FlagSet.contains(F); + })) + continue; + + const std::string &group = M.exclusiveGroup(); + if (!group.empty()) { + // If this multilib has the same ExclusiveGroup as one we've already + // selected, skip it. We're iterating in reverse order, so the group + // member we've selected already is preferred. + // + // Otherwise, add the group name to the set of groups we've already + // selected a member of. + auto [It, Inserted] = ExclusiveGroupsSelected.insert(group); + if (!Inserted) + continue; + } + + // Select this multilib. + Selected.push_back(M); + } + + // We iterated in reverse order, so now put Selected back the right way + // round. + std::reverse(Selected.begin(), Selected.end()); + return !Selected.empty(); } @@ -138,10 +164,39 @@ static const VersionTuple MultilibVersionCurrent(1, 0); struct MultilibSerialization { std::string Dir; std::vector Flags; + std::string Group; +}; + +enum class MultilibGroupType { + /* + * The only group type currently supported is 'Exclusive', which indicates a + * group of multilibs of which at most one may be selected. + */ + Exclusive, + + /* + * Future possibility: a second group type indicating a set of library + * directories that are mutually _dependent_ rather than mutually exclusive: + * if you include one you must include them all. + * + * It might also be useful to allow groups to be members of other groups, so + * that a mutually exclusive group could contain a mutually dependent set of + * library directories, or vice versa. + * + * These additional features would need changes in the implementation, but + * the YAML schema is set up so they can be added without requiring changes + * in existing users' multilib.yaml files. + */ +}; + +struct MultilibGroupSerialization { + std::string Name; + MultilibGroupType Type; }; struct MultilibSetSerialization { llvm::VersionTuple MultilibVersion; + std::vector Groups; std::vector Multilibs; std::vector FlagMatchers; }; @@ -152,6 +207,7 @@ template <> struct llvm::yaml::MappingTraits { static void mapping(llvm::yaml::IO &io, MultilibSerialization &V) { io.mapRequired("Dir", V.Dir); io.mapRequired("Flags", V.Flags); + io.mapOptional("Group", V.Group); } static std::string validate(IO &io, MultilibSerialization &V) { if (StringRef(V.Dir).starts_with("/")) @@ -160,6 +216,19 @@ template <> struct llvm::yaml::MappingTraits { } }; +template <> struct llvm::yaml::ScalarEnumerationTraits { + static void enumeration(IO &io, MultilibGroupType &Val) { + io.enumCase(Val, "Exclusive", MultilibGroupType::Exclusive); + } +}; + +template <> struct llvm::yaml::MappingTraits { + static void mapping(llvm::yaml::IO &io, MultilibGroupSerialization &V) { + io.mapRequired("Name", V.Name); + io.mapRequired("Type", V.Type); + } +}; + template <> struct llvm::yaml::MappingTraits { static void mapping(llvm::yaml::IO &io, MultilibSet::FlagMatcher &M) { io.mapRequired("Match", M.Match); @@ -180,6 +249,7 @@ template <> struct llvm::yaml::MappingTraits { static void mapping(llvm::yaml::IO &io, MultilibSetSerialization &M) { io.mapRequired("MultilibVersion", M.MultilibVersion); io.mapRequired("Variants", M.Multilibs); + io.mapOptional("Groups", M.Groups); io.mapOptional("Mappings", M.FlagMatchers); } static std::string validate(IO &io, MultilibSetSerialization &M) { @@ -191,11 +261,25 @@ template <> struct llvm::yaml::MappingTraits { if (M.MultilibVersion.getMinor() > MultilibVersionCurrent.getMinor()) return "multilib version " + M.MultilibVersion.getAsString() + " is unsupported"; + for (const MultilibSerialization &Lib : M.Multilibs) { + if (!Lib.Group.empty()) { + bool Found = false; + for (const MultilibGroupSerialization &Group : M.Groups) + if (Group.Name == Lib.Group) { + Found = true; + break; + } + if (!Found) + return "multilib \"" + Lib.Dir + + "\" specifies undefined group name \"" + Lib.Group + "\""; + } + } return std::string{}; } }; LLVM_YAML_IS_SEQUENCE_VECTOR(MultilibSerialization) +LLVM_YAML_IS_SEQUENCE_VECTOR(MultilibGroupSerialization) LLVM_YAML_IS_SEQUENCE_VECTOR(MultilibSet::FlagMatcher) llvm::ErrorOr @@ -214,7 +298,11 @@ MultilibSet::parseYaml(llvm::MemoryBufferRef Input, std::string Dir; if (M.Dir != ".") Dir = "/" + M.Dir; - Multilibs.emplace_back(Dir, Dir, Dir, M.Flags); + // We transfer M.Group straight into the ExclusiveGroup parameter for the + // Multilib constructor. If we later support more than one type of group, + // we'll have to look up the group name in MS.Groups, check its type, and + // decide what to do here. + Multilibs.emplace_back(Dir, Dir, Dir, M.Flags, M.Group); } return MultilibSet(std::move(Multilibs), std::move(MS.FlagMatchers)); diff --git a/clang/test/Driver/baremetal-multilib-exclusive-group.yaml b/clang/test/Driver/baremetal-multilib-exclusive-group.yaml new file mode 100644 index 000000000000..a98549efea4f --- /dev/null +++ b/clang/test/Driver/baremetal-multilib-exclusive-group.yaml @@ -0,0 +1,79 @@ +# UNSUPPORTED: system-windows + +# RUN: rm -rf %t + +# RUN: mkdir -p %t/baremetal_multilib/bin +# RUN: ln -s %clang %t/baremetal_multilib/bin/clang + +# RUN: mkdir -p %t/baremetal_multilib/lib/clang-runtimes +# RUN: ln -s %s %t/baremetal_multilib/lib/clang-runtimes/multilib.yaml + +# RUN: %t/baremetal_multilib/bin/clang -no-canonical-prefixes -x c++ %s -### -o %t.out --target=thumbv7em-none-unknown-eabi --sysroot= 2>%t.err + +# RUN: FileCheck -DSYSROOT=%t/baremetal_multilib %s < %t.err --check-prefix=POS +# RUN: FileCheck -DSYSROOT=%t/baremetal_multilib %s < %t.err --check-prefix=NEG + +# Expected results: +# +# Due to the Mappings section, all six of these library directories should +# match the command-line flag --target=thumbv7em-none-unknown-eabi. +# +# The two "non_exclusive" directories, which don't have an ExclusiveGroup at +# all, should both be selected. So should the two "own_group", each of which +# specifies a different value of ExclusiveGroup. But the three "exclusive", +# which have the _same_ ExclusiveGroup value, should not: the third one wins. +# So we expect five of these seven directories to show up in the clang-cc1 +# command line, but not testdir1_exclusive or testdir2_exclusive. + +# POS-DAG: "-internal-isystem" "[[SYSROOT]]/bin/../lib/clang-runtimes/testdir1_non_exclusive/include/c++/v1" +# POS-DAG: "-internal-isystem" "[[SYSROOT]]/bin/../lib/clang-runtimes/testdir2_non_exclusive/include/c++/v1" +# POS-DAG: "-internal-isystem" "[[SYSROOT]]/bin/../lib/clang-runtimes/testdir3_exclusive/include/c++/v1" +# POS-DAG: "-internal-isystem" "[[SYSROOT]]/bin/../lib/clang-runtimes/testdir1_own_group/include/c++/v1" +# POS-DAG: "-internal-isystem" "[[SYSROOT]]/bin/../lib/clang-runtimes/testdir2_own_group/include/c++/v1" + +# NEG-NOT: "-internal-isystem" "[[SYSROOT]]/bin/../lib/clang-runtimes/testdir1_exclusive/include/c++/v1" +# NEG-NOT: "-internal-isystem" "[[SYSROOT]]/bin/../lib/clang-runtimes/testdir2_exclusive/include/c++/v1" + +--- +MultilibVersion: 1.0 + +Groups: +- Name: actually_exclude_something + Type: Exclusive + +- Name: foo + Type: Exclusive + +- Name: bar + Type: Exclusive + +Variants: +- Dir: testdir1_non_exclusive + Flags: [--target=thumbv7m-none-unknown-eabi] + +- Dir: testdir2_non_exclusive + Flags: [--target=thumbv7em-none-unknown-eabi] + +- Dir: testdir1_exclusive + Flags: [--target=thumbv7m-none-unknown-eabi] + Group: actually_exclude_something + +- Dir: testdir2_exclusive + Flags: [--target=thumbv7em-none-unknown-eabi] + Group: actually_exclude_something + +- Dir: testdir3_exclusive + Flags: [--target=thumbv7em-none-unknown-eabi] + Group: actually_exclude_something + +- Dir: testdir1_own_group + Flags: [--target=thumbv7m-none-unknown-eabi] + Group: foo + +- Dir: testdir2_own_group + Flags: [--target=thumbv7em-none-unknown-eabi] + Group: bar + +Mappings: +- Match: --target=thumbv7em-none-unknown-eabi + Flags: [--target=thumbv7m-none-unknown-eabi] diff --git a/clang/test/Driver/baremetal-multilib-group-error.yaml b/clang/test/Driver/baremetal-multilib-group-error.yaml new file mode 100644 index 000000000000..1e8f83fa50d2 --- /dev/null +++ b/clang/test/Driver/baremetal-multilib-group-error.yaml @@ -0,0 +1,27 @@ +# UNSUPPORTED: system-windows + +# RUN: rm -rf %t + +# RUN: mkdir -p %t/baremetal_multilib/bin +# RUN: ln -s %clang %t/baremetal_multilib/bin/clang + +# RUN: mkdir -p %t/baremetal_multilib/lib/clang-runtimes +# RUN: ln -s %s %t/baremetal_multilib/lib/clang-runtimes/multilib.yaml + +# RUN: %t/baremetal_multilib/bin/clang -no-canonical-prefixes -x c++ %s -### -o %t.out --target=thumbv7em-none-unknown-eabi --sysroot= 2>%t.err +# RUN: FileCheck %s < %t.err + +--- +MultilibVersion: 1.0 + +Groups: +- Name: group1 + Type: Nonsense + +Variants: +- Dir: testdir1 + Flags: [--target=thumbv7m-none-unknown-eabi] + Group: nonexistent_group_name + +# CHECK: error: unknown enumerated scalar +# CHECK: error: multilib "testdir1" specifies undefined group name "nonexistent_group_name" -- GitLab From a2e8207178432f0af30e8c9e3b905a3fd770d500 Mon Sep 17 00:00:00 2001 From: Paul Walker Date: Thu, 30 Nov 2023 16:50:57 +0000 Subject: [PATCH 135/699] [NFC][LLVMContext] Clean up DenseMapInfo classes used for APInt & APFloat. DenseMapAPIntKeyInfo looks like a redundant definition because it mirrors the default used by DenseMap when not specified. Replacing DenseMapAPFloatKeyInfo with a specialisation of DenseMapInfo allows DenseMap to be more easily used when T is an aggregate type containing an APFloat. --- llvm/lib/IR/LLVMContextImpl.h | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/llvm/lib/IR/LLVMContextImpl.h b/llvm/lib/IR/LLVMContextImpl.h index b55107beba55..6a2029134498 100644 --- a/llvm/lib/IR/LLVMContextImpl.h +++ b/llvm/lib/IR/LLVMContextImpl.h @@ -73,9 +73,7 @@ class StringRef; class TypedPointerType; class ValueHandleBase; -using DenseMapAPIntKeyInfo = DenseMapInfo; - -struct DenseMapAPFloatKeyInfo { +template <> struct DenseMapInfo { static inline APFloat getEmptyKey() { return APFloat(APFloat::Bogus(), 1); } static inline APFloat getTombstoneKey() { return APFloat(APFloat::Bogus(), 2); @@ -1489,11 +1487,9 @@ public: DenseMap> IntZeroConstants; DenseMap> IntOneConstants; - DenseMap, DenseMapAPIntKeyInfo> - IntConstants; + DenseMap> IntConstants; - DenseMap, DenseMapAPFloatKeyInfo> - FPConstants; + DenseMap> FPConstants; FoldingSet AttrsSet; FoldingSet AttrsLists; -- GitLab From 85184b4aefbd01afd6e7be57bc6c1c404b3c13ce Mon Sep 17 00:00:00 2001 From: Dominik Adamski Date: Fri, 1 Dec 2023 13:33:11 +0100 Subject: [PATCH 136/699] [OpenMP] Fix libomptarget build issue (#74067) Libomptarget cannot be build because of the recent refactoring introduced in patch 148dec9fa43b : [OpenMP][NFC] Separate Envar (environment variable) handling (#73994) That patch moved handling of environment variables from libomptarget library. That's why we don't need usage of "llvm::omp::target" namespace if we handle environment variables. --- openmp/libomptarget/src/interface.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/openmp/libomptarget/src/interface.cpp b/openmp/libomptarget/src/interface.cpp index a2f713459e1d..ee1bd4932442 100644 --- a/openmp/libomptarget/src/interface.cpp +++ b/openmp/libomptarget/src/interface.cpp @@ -454,7 +454,6 @@ EXTERN void __tgt_target_nowait_query(void **AsyncHandle) { // for the device operations (work/spin wait on them) or block until they are // completed (use device side blocking mechanism). This allows the runtime to // adapt itself when there are a lot of long-running target regions in-flight. - using namespace llvm::omp::target; static thread_local utils::ExponentialBackoff QueryCounter( Int64Envar("OMPTARGET_QUERY_COUNT_MAX", 10), Int64Envar("OMPTARGET_QUERY_COUNT_THRESHOLD", 5), -- GitLab From 808b7d220309e279cf9c3d5762cb4c9120c0955f Mon Sep 17 00:00:00 2001 From: Guillaume Chatelet Date: Fri, 1 Dec 2023 13:55:31 +0100 Subject: [PATCH 137/699] [libc][NFC] rename LONG_DOUBLE_IS_DOUBLE into LIBC_LONG_DOUBLE_IS_FLOAT64 (#73948) --- libc/src/__support/FPUtil/generic/sqrt.h | 2 +- libc/src/__support/FPUtil/x86_64/sqrt.h | 2 +- libc/src/__support/float_to_string.h | 4 +- libc/src/__support/macros/properties/float.h | 8 ++-- libc/src/__support/str_to_float.h | 4 +- .../test/src/__support/FPUtil/fpbits_test.cpp | 2 +- libc/test/src/__support/str_to_float_test.cpp | 2 +- libc/test/src/stdio/sprintf_test.cpp | 44 +++++++++---------- libc/test/src/stdio/sscanf_test.cpp | 2 +- libc/test/src/stdlib/strtold_test.cpp | 4 +- 10 files changed, 36 insertions(+), 38 deletions(-) diff --git a/libc/src/__support/FPUtil/generic/sqrt.h b/libc/src/__support/FPUtil/generic/sqrt.h index 63e8329b0660..9c7e6a2f361c 100644 --- a/libc/src/__support/FPUtil/generic/sqrt.h +++ b/libc/src/__support/FPUtil/generic/sqrt.h @@ -43,7 +43,7 @@ LIBC_INLINE void normalize(int &exponent, mantissa <<= shift; } -#ifdef LONG_DOUBLE_IS_DOUBLE +#ifdef LIBC_LONG_DOUBLE_IS_FLOAT64 template <> LIBC_INLINE void normalize(int &exponent, uint64_t &mantissa) { normalize(exponent, mantissa); diff --git a/libc/src/__support/FPUtil/x86_64/sqrt.h b/libc/src/__support/FPUtil/x86_64/sqrt.h index 7edba5528d6a..cf3eb9b2f494 100644 --- a/libc/src/__support/FPUtil/x86_64/sqrt.h +++ b/libc/src/__support/FPUtil/x86_64/sqrt.h @@ -33,7 +33,7 @@ template <> LIBC_INLINE double sqrt(double x) { return result; } -#ifdef LONG_DOUBLE_IS_DOUBLE +#ifdef LIBC_LONG_DOUBLE_IS_FLOAT64 template <> LIBC_INLINE long double sqrt(long double x) { long double result; __asm__ __volatile__("sqrtsd %x1, %x0" : "=x"(result) : "x"(x)); diff --git a/libc/src/__support/float_to_string.h b/libc/src/__support/float_to_string.h index eb06cd9c08af..1bb4e5c5b924 100644 --- a/libc/src/__support/float_to_string.h +++ b/libc/src/__support/float_to_string.h @@ -602,7 +602,7 @@ public: } }; -#ifndef LONG_DOUBLE_IS_DOUBLE +#ifndef LIBC_LONG_DOUBLE_IS_FLOAT64 // --------------------------- LONG DOUBLE FUNCTIONS --------------------------- template <> @@ -754,7 +754,7 @@ FloatToString::get_negative_block(int block_index) { } } -#endif // LONG_DOUBLE_IS_DOUBLE +#endif // LIBC_LONG_DOUBLE_IS_FLOAT64 } // namespace LIBC_NAMESPACE diff --git a/libc/src/__support/macros/properties/float.h b/libc/src/__support/macros/properties/float.h index 4bafc3777a47..f1679fe51113 100644 --- a/libc/src/__support/macros/properties/float.h +++ b/libc/src/__support/macros/properties/float.h @@ -19,11 +19,9 @@ #include // LDBL_MANT_DIG // 'long double' properties. -#if (LDBL_MANT_DIG == DBL_MANT_DIG) -// TODO: Replace with LIBC_LONG_DOUBLE_IS_DOUBLE -#define LONG_DOUBLE_IS_DOUBLE -#endif -#if (LDBL_MANT_DIG == 64) +#if (LDBL_MANT_DIG == 53) +#define LIBC_LONG_DOUBLE_IS_FLOAT64 +#elif (LDBL_MANT_DIG == 64) // TODO: Replace with LIBC_LONG_DOUBLE_IS_X86_BIN80 #define SPECIAL_X86_LONG_DOUBLE #elif (LDBL_MANT_DIG == 113) diff --git a/libc/src/__support/str_to_float.h b/libc/src/__support/str_to_float.h index 81ab36dbf947..a92325730414 100644 --- a/libc/src/__support/str_to_float.h +++ b/libc/src/__support/str_to_float.h @@ -221,7 +221,7 @@ eisel_lemire(ExpandedFloat init_num, return output; } -#if !defined(LONG_DOUBLE_IS_DOUBLE) +#if !defined(LIBC_LONG_DOUBLE_IS_FLOAT64) template <> LIBC_INLINE cpp::optional> eisel_lemire(ExpandedFloat init_num, @@ -516,7 +516,7 @@ public: static constexpr double MAX_EXACT_INT = 9007199254740991.0; }; -#if defined(LONG_DOUBLE_IS_DOUBLE) +#if defined(LIBC_LONG_DOUBLE_IS_FLOAT64) template <> class ClingerConsts { public: static constexpr long double POWERS_OF_TEN_ARRAY[] = { diff --git a/libc/test/src/__support/FPUtil/fpbits_test.cpp b/libc/test/src/__support/FPUtil/fpbits_test.cpp index 027db8807ab2..52635cc2af09 100644 --- a/libc/test/src/__support/FPUtil/fpbits_test.cpp +++ b/libc/test/src/__support/FPUtil/fpbits_test.cpp @@ -213,7 +213,7 @@ TEST(LlvmLibcFPBitsTest, X86LongDoubleType) { } #else TEST(LlvmLibcFPBitsTest, LongDoubleType) { -#if defined(LONG_DOUBLE_IS_DOUBLE) +#if defined(LIBC_LONG_DOUBLE_IS_FLOAT64) return; // The tests for the "double" type cover for this case. #else using LongDoubleBits = FPBits; diff --git a/libc/test/src/__support/str_to_float_test.cpp b/libc/test/src/__support/str_to_float_test.cpp index ae729418ebe3..c2643d9a764e 100644 --- a/libc/test/src/__support/str_to_float_test.cpp +++ b/libc/test/src/__support/str_to_float_test.cpp @@ -279,7 +279,7 @@ TEST(LlvmLibcStrToFloatTest, SimpleDecimalConversionExtraTypes) { EXPECT_EQ(double_result.error, 0); } -#if defined(LONG_DOUBLE_IS_DOUBLE) +#if defined(LIBC_LONG_DOUBLE_IS_FLOAT64) TEST_F(LlvmLibcStrToFloatTest, EiselLemireFloat64AsLongDouble) { eisel_lemire_test(123, 0, 0x1EC00000000000, 1029); } diff --git a/libc/test/src/stdio/sprintf_test.cpp b/libc/test/src/stdio/sprintf_test.cpp index e41579a20656..e2265f5efbc4 100644 --- a/libc/test/src/stdio/sprintf_test.cpp +++ b/libc/test/src/stdio/sprintf_test.cpp @@ -644,7 +644,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatHexExpConv) { written = LIBC_NAMESPACE::sprintf(buff, "%La", 0.1L); #if defined(SPECIAL_X86_LONG_DOUBLE) ASSERT_STREQ_LEN(written, buff, "0xc.ccccccccccccccdp-7"); -#elif defined(LONG_DOUBLE_IS_DOUBLE) +#elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "0x1.999999999999ap-4"); #else // 128 bit long double ASSERT_STREQ_LEN(written, buff, "0x1.999999999999999999999999999ap-4"); @@ -653,7 +653,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatHexExpConv) { written = LIBC_NAMESPACE::sprintf(buff, "%La", 1.0e1000L); #if defined(SPECIAL_X86_LONG_DOUBLE) ASSERT_STREQ_LEN(written, buff, "0xf.38db1f9dd3dac05p+3318"); -#elif defined(LONG_DOUBLE_IS_DOUBLE) +#elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "inf"); #else // 128 bit long double ASSERT_STREQ_LEN(written, buff, "0x1.e71b63f3ba7b580af1a52d2a7379p+3321"); @@ -662,7 +662,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatHexExpConv) { written = LIBC_NAMESPACE::sprintf(buff, "%La", 1.0e-1000L); #if defined(SPECIAL_X86_LONG_DOUBLE) ASSERT_STREQ_LEN(written, buff, "0x8.68a9188a89e1467p-3325"); -#elif defined(LONG_DOUBLE_IS_DOUBLE) +#elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "0x0p+0"); #else // 128 bit long double ASSERT_STREQ_LEN(written, buff, "0x1.0d152311513c28ce202627c06ec2p-3322"); @@ -768,7 +768,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatHexExpConv) { written = LIBC_NAMESPACE::sprintf(buff, "%.1La", 0.1L); #if defined(SPECIAL_X86_LONG_DOUBLE) ASSERT_STREQ_LEN(written, buff, "0xc.dp-7"); -#elif defined(LONG_DOUBLE_IS_DOUBLE) +#elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "0x1.ap-4"); #else // 128 bit long double ASSERT_STREQ_LEN(written, buff, "0x1.ap-4"); @@ -777,7 +777,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatHexExpConv) { written = LIBC_NAMESPACE::sprintf(buff, "%.1La", 0xf.fffffffffffffffp16380L); #if defined(SPECIAL_X86_LONG_DOUBLE) ASSERT_STREQ_LEN(written, buff, "0x1.0p+16384"); -#elif defined(LONG_DOUBLE_IS_DOUBLE) +#elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "inf"); #else // 128 bit long double ASSERT_STREQ_LEN(written, buff, "0x2.0p+16383"); @@ -1024,14 +1024,14 @@ TEST_F(LlvmLibcSPrintfTest, FloatDecimalConv) { // Some float128 systems (specifically the ones used for aarch64 buildbots) // don't respect signs for long double NaNs. -#if defined(SPECIAL_X86_LONG_DOUBLE) || defined(LONG_DOUBLE_IS_DOUBLE) +#if defined(SPECIAL_X86_LONG_DOUBLE) || defined(LIBC_LONG_DOUBLE_IS_FLOAT64) written = LIBC_NAMESPACE::sprintf(buff, "%LF", -ld_nan); ASSERT_STREQ_LEN(written, buff, "-NAN"); #endif // Length Modifier Tests. - // TODO(michaelrj): Add tests for LONG_DOUBLE_IS_DOUBLE and 128 bit long + // TODO(michaelrj): Add tests for LIBC_LONG_DOUBLE_IS_FLOAT64 and 128 bit long // double systems. // TODO(michaelrj): Fix the tests to only depend on the digits the long double // is accurate for. @@ -1333,7 +1333,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatDecimalConv) { written = LIBC_NAMESPACE::sprintf(buff, "%La", 0.1L); #if defined(SPECIAL_X86_LONG_DOUBLE) ASSERT_STREQ_LEN(written, buff, "0xc.ccccccccccccccdp-7"); - #elif defined(LONG_DOUBLE_IS_DOUBLE) + #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "0x1.999999999999ap-4"); #else // 128 bit long double ASSERT_STREQ_LEN(written, buff, "0x1.999999999999999999999999999ap-4"); @@ -1342,7 +1342,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatDecimalConv) { written = LIBC_NAMESPACE::sprintf(buff, "%La", 1.0e1000L); #if defined(SPECIAL_X86_LONG_DOUBLE) ASSERT_STREQ_LEN(written, buff, "0xf.38db1f9dd3dac05p+3318"); - #elif defined(LONG_DOUBLE_IS_DOUBLE) + #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "inf"); #else // 128 bit long double ASSERT_STREQ_LEN(written, buff, "0x1.e71b63f3ba7b580af1a52d2a7379p+3321"); @@ -1351,7 +1351,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatDecimalConv) { written = LIBC_NAMESPACE::sprintf(buff, "%La", 1.0e-1000L); #if defined(SPECIAL_X86_LONG_DOUBLE) ASSERT_STREQ_LEN(written, buff, "0x8.68a9188a89e1467p-3325"); - #elif defined(LONG_DOUBLE_IS_DOUBLE) + #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "0x0p+0"); #else // 128 bit long double ASSERT_STREQ_LEN(written, buff, "0x1.0d152311513c28ce202627c06ec2p-3322"); @@ -1550,7 +1550,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatDecimalConv) { written = LIBC_NAMESPACE::sprintf(buff, "%.1La", 0.1L); #if defined(SPECIAL_X86_LONG_DOUBLE) ASSERT_STREQ_LEN(written, buff, "0xc.dp-7"); - #elif defined(LONG_DOUBLE_IS_DOUBLE) + #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "0x1.ap-4"); #else // 128 bit long double ASSERT_STREQ_LEN(written, buff, "0x1.ap-4"); @@ -1559,7 +1559,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatDecimalConv) { written = LIBC_NAMESPACE::sprintf(buff, "%.1La", 0xf.fffffffffffffffp16380L); #if defined(SPECIAL_X86_LONG_DOUBLE) ASSERT_STREQ_LEN(written, buff, "0x1.0p+16384"); - #elif defined(LONG_DOUBLE_IS_DOUBLE) + #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "inf"); #else // 128 bit long double ASSERT_STREQ_LEN(written, buff, "0x2.0p+16383"); @@ -1977,7 +1977,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatExponentConv) { written = LIBC_NAMESPACE::sprintf(buff, "%La", 0.1L); #if defined(SPECIAL_X86_LONG_DOUBLE) ASSERT_STREQ_LEN(written, buff, "0xc.ccccccccccccccdp-7"); - #elif defined(LONG_DOUBLE_IS_DOUBLE) + #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "0x1.999999999999ap-4"); #else // 128 bit long double ASSERT_STREQ_LEN(written, buff, "0x1.999999999999999999999999999ap-4"); @@ -1986,7 +1986,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatExponentConv) { written = LIBC_NAMESPACE::sprintf(buff, "%La", 1.0e1000L); #if defined(SPECIAL_X86_LONG_DOUBLE) ASSERT_STREQ_LEN(written, buff, "0xf.38db1f9dd3dac05p+3318"); - #elif defined(LONG_DOUBLE_IS_DOUBLE) + #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "inf"); #else // 128 bit long double ASSERT_STREQ_LEN(written, buff, "0x1.e71b63f3ba7b580af1a52d2a7379p+3321"); @@ -1995,7 +1995,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatExponentConv) { written = LIBC_NAMESPACE::sprintf(buff, "%La", 1.0e-1000L); #if defined(SPECIAL_X86_LONG_DOUBLE) ASSERT_STREQ_LEN(written, buff, "0x8.68a9188a89e1467p-3325"); - #elif defined(LONG_DOUBLE_IS_DOUBLE) + #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "0x0p+0"); #else // 128 bit long double ASSERT_STREQ_LEN(written, buff, "0x1.0d152311513c28ce202627c06ec2p-3322"); @@ -2173,7 +2173,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatExponentConv) { written = LIBC_NAMESPACE::sprintf(buff, "%.1La", 0.1L); #if defined(SPECIAL_X86_LONG_DOUBLE) ASSERT_STREQ_LEN(written, buff, "0xc.dp-7"); - #elif defined(LONG_DOUBLE_IS_DOUBLE) + #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "0x1.ap-4"); #else // 128 bit long double ASSERT_STREQ_LEN(written, buff, "0x1.ap-4"); @@ -2182,7 +2182,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatExponentConv) { written = LIBC_NAMESPACE::sprintf(buff, "%.1La", 0xf.fffffffffffffffp16380L); #if defined(SPECIAL_X86_LONG_DOUBLE) ASSERT_STREQ_LEN(written, buff, "0x1.0p+16384"); - #elif defined(LONG_DOUBLE_IS_DOUBLE) + #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "inf"); #else // 128 bit long double ASSERT_STREQ_LEN(written, buff, "0x2.0p+16383"); @@ -2616,7 +2616,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatAutoConv) { written = LIBC_NAMESPACE::sprintf(buff, "%La", 0.1L); #if defined(SPECIAL_X86_LONG_DOUBLE) ASSERT_STREQ_LEN(written, buff, "0xc.ccccccccccccccdp-7"); - #elif defined(LONG_DOUBLE_IS_DOUBLE) + #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "0x1.999999999999ap-4"); #else // 128 bit long double ASSERT_STREQ_LEN(written, buff, "0x1.999999999999999999999999999ap-4"); @@ -2625,7 +2625,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatAutoConv) { written = LIBC_NAMESPACE::sprintf(buff, "%La", 1.0e1000L); #if defined(SPECIAL_X86_LONG_DOUBLE) ASSERT_STREQ_LEN(written, buff, "0xf.38db1f9dd3dac05p+3318"); - #elif defined(LONG_DOUBLE_IS_DOUBLE) + #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "inf"); #else // 128 bit long double ASSERT_STREQ_LEN(written, buff, "0x1.e71b63f3ba7b580af1a52d2a7379p+3321"); @@ -2634,7 +2634,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatAutoConv) { written = LIBC_NAMESPACE::sprintf(buff, "%La", 1.0e-1000L); #if defined(SPECIAL_X86_LONG_DOUBLE) ASSERT_STREQ_LEN(written, buff, "0x8.68a9188a89e1467p-3325"); - #elif defined(LONG_DOUBLE_IS_DOUBLE) + #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "0x0p+0"); #else // 128 bit long double ASSERT_STREQ_LEN(written, buff, "0x1.0d152311513c28ce202627c06ec2p-3322"); @@ -2822,7 +2822,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatAutoConv) { written = LIBC_NAMESPACE::sprintf(buff, "%.1La", 0.1L); #if defined(SPECIAL_X86_LONG_DOUBLE) ASSERT_STREQ_LEN(written, buff, "0xc.dp-7"); - #elif defined(LONG_DOUBLE_IS_DOUBLE) + #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "0x1.ap-4"); #else // 128 bit long double ASSERT_STREQ_LEN(written, buff, "0x1.ap-4"); @@ -2831,7 +2831,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatAutoConv) { written = LIBC_NAMESPACE::sprintf(buff, "%.1La", 0xf.fffffffffffffffp16380L); #if defined(SPECIAL_X86_LONG_DOUBLE) ASSERT_STREQ_LEN(written, buff, "0x1.0p+16384"); - #elif defined(LONG_DOUBLE_IS_DOUBLE) + #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "inf"); #else // 128 bit long double ASSERT_STREQ_LEN(written, buff, "0x2.0p+16383"); diff --git a/libc/test/src/stdio/sscanf_test.cpp b/libc/test/src/stdio/sscanf_test.cpp index ec53c08bd9d4..db3c48cdbf7a 100644 --- a/libc/test/src/stdio/sscanf_test.cpp +++ b/libc/test/src/stdio/sscanf_test.cpp @@ -322,7 +322,7 @@ TEST(LlvmLibcSScanfTest, FloatConvLengthModifier) { EXPECT_EQ(ret_val, 1); // 1e600 may be larger than the maximum long double (if long double is double). // In that case both of these should be evaluated as inf. -#ifdef LONG_DOUBLE_IS_DOUBLE +#ifdef LIBC_LONG_DOUBLE_IS_FLOAT64 EXPECT_FP_EQ(ld_result, d_inf); #else EXPECT_FP_EQ(ld_result, 1.0e600L); diff --git a/libc/test/src/stdlib/strtold_test.cpp b/libc/test/src/stdlib/strtold_test.cpp index 680a93188c76..1ddf729689ff 100644 --- a/libc/test/src/stdlib/strtold_test.cpp +++ b/libc/test/src/stdlib/strtold_test.cpp @@ -16,7 +16,7 @@ #include #include -#if defined(LONG_DOUBLE_IS_DOUBLE) +#if defined(LIBC_LONG_DOUBLE_IS_FLOAT64) #define SELECT_CONST(val, _, __) val #elif defined(SPECIAL_X86_LONG_DOUBLE) #define SELECT_CONST(_, val, __) val @@ -26,7 +26,7 @@ class LlvmLibcStrToLDTest : public LIBC_NAMESPACE::testing::Test { public: -#if defined(LONG_DOUBLE_IS_DOUBLE) +#if defined(LIBC_LONG_DOUBLE_IS_FLOAT64) void run_test(const char *inputString, const ptrdiff_t expectedStrLen, const uint64_t expectedRawData, const int expectedErrno = 0) #else -- GitLab From f1d0276e4c42301155e900424ea734aca7ec97a8 Mon Sep 17 00:00:00 2001 From: Guillaume Chatelet Date: Fri, 1 Dec 2023 13:57:36 +0100 Subject: [PATCH 138/699] [libc][NFC] Rename LIBC_LONG_DOUBLE_IS_IEEE754_BIN128 to LIBC_LONG_DOUBLE_IS_FLOAT128 (#74052) To make it consistent with https://github.com/llvm/llvm-project/pull/73948 and https://github.com/llvm/llvm-project/pull/73950 --- libc/src/__support/macros/properties/float.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/libc/src/__support/macros/properties/float.h b/libc/src/__support/macros/properties/float.h index f1679fe51113..bd63f3346605 100644 --- a/libc/src/__support/macros/properties/float.h +++ b/libc/src/__support/macros/properties/float.h @@ -25,7 +25,7 @@ // TODO: Replace with LIBC_LONG_DOUBLE_IS_X86_BIN80 #define SPECIAL_X86_LONG_DOUBLE #elif (LDBL_MANT_DIG == 113) -#define LIBC_LONG_DOUBLE_IS_IEEE754_BIN128 +#define LIBC_LONG_DOUBLE_IS_FLOAT128 #endif // float16 support. @@ -69,13 +69,13 @@ using float16 = _Float16; using float128 = _Float128; #elif defined(LIBC_COMPILER_HAS_FLOAT128_EXTENSION) using float128 = __float128; -#elif defined(LIBC_LONG_DOUBLE_IS_IEEE754_BIN128) +#elif defined(LIBC_LONG_DOUBLE_IS_FLOAT128) using float128 = long double; #endif #if defined(LIBC_COMPILER_HAS_C23_FLOAT128) || \ defined(LIBC_COMPILER_HAS_FLOAT128_EXTENSION) || \ - defined(LIBC_LONG_DOUBLE_IS_IEEE754_BIN128) + defined(LIBC_LONG_DOUBLE_IS_FLOAT128) // TODO: Replace with LIBC_HAS_FLOAT128 #define LIBC_COMPILER_HAS_FLOAT128 #endif -- GitLab From 977af4252d1d60a1e9c546f0e4328b1a646ef635 Mon Sep 17 00:00:00 2001 From: Guillaume Chatelet Date: Fri, 1 Dec 2023 14:23:08 +0100 Subject: [PATCH 139/699] [libc][NFC] Rename SPECIAL_X86_LONG_DOUBLE in LIBC_LONG_DOUBLE_IS_X86_FLOAT80 (#73950) --- libc/src/__support/FPUtil/FPBits.h | 2 +- .../__support/FPUtil/ManipulationFunctions.h | 4 +- libc/src/__support/FPUtil/NormalFloat.h | 4 +- libc/src/__support/FPUtil/generic/sqrt.h | 6 +- .../FPUtil/generic/sqrt_80_bit_long_double.h | 4 +- libc/src/__support/macros/properties/float.h | 3 +- libc/src/__support/str_to_float.h | 4 +- libc/test/src/__support/str_to_float_test.cpp | 2 +- libc/test/src/stdio/sprintf_test.cpp | 57 ++++++++++--------- libc/test/src/stdlib/strtold_test.cpp | 2 +- 10 files changed, 44 insertions(+), 44 deletions(-) diff --git a/libc/src/__support/FPUtil/FPBits.h b/libc/src/__support/FPUtil/FPBits.h index 76a9fc6d772b..f5b73440de21 100644 --- a/libc/src/__support/FPUtil/FPBits.h +++ b/libc/src/__support/FPUtil/FPBits.h @@ -249,7 +249,7 @@ template struct FPBits { } // namespace fputil } // namespace LIBC_NAMESPACE -#ifdef SPECIAL_X86_LONG_DOUBLE +#ifdef LIBC_LONG_DOUBLE_IS_X86_FLOAT80 #include "x86_64/LongDoubleBits.h" #endif diff --git a/libc/src/__support/FPUtil/ManipulationFunctions.h b/libc/src/__support/FPUtil/ManipulationFunctions.h index 9286deee2d92..9d3fd075be47 100644 --- a/libc/src/__support/FPUtil/ManipulationFunctions.h +++ b/libc/src/__support/FPUtil/ManipulationFunctions.h @@ -186,8 +186,8 @@ LIBC_INLINE T nextafter(T from, U to) { } // namespace fputil } // namespace LIBC_NAMESPACE -#ifdef SPECIAL_X86_LONG_DOUBLE +#ifdef LIBC_LONG_DOUBLE_IS_X86_FLOAT80 #include "x86_64/NextAfterLongDouble.h" -#endif // SPECIAL_X86_LONG_DOUBLE +#endif // LIBC_LONG_DOUBLE_IS_X86_FLOAT80 #endif // LLVM_LIBC_SRC___SUPPORT_FPUTIL_MANIPULATIONFUNCTIONS_H diff --git a/libc/src/__support/FPUtil/NormalFloat.h b/libc/src/__support/FPUtil/NormalFloat.h index afbf97cc2b63..d59de14fb695 100644 --- a/libc/src/__support/FPUtil/NormalFloat.h +++ b/libc/src/__support/FPUtil/NormalFloat.h @@ -170,7 +170,7 @@ private: } }; -#ifdef SPECIAL_X86_LONG_DOUBLE +#ifdef LIBC_LONG_DOUBLE_IS_X86_FLOAT80 template <> LIBC_INLINE void NormalFloat::init_from_bits(FPBits bits) { @@ -259,7 +259,7 @@ template <> LIBC_INLINE NormalFloat::operator long double() const { result.set_implicit_bit(1); return static_cast(result); } -#endif // SPECIAL_X86_LONG_DOUBLE +#endif // LIBC_LONG_DOUBLE_IS_X86_FLOAT80 } // namespace fputil } // namespace LIBC_NAMESPACE diff --git a/libc/src/__support/FPUtil/generic/sqrt.h b/libc/src/__support/FPUtil/generic/sqrt.h index 9c7e6a2f361c..b93fa7a35f82 100644 --- a/libc/src/__support/FPUtil/generic/sqrt.h +++ b/libc/src/__support/FPUtil/generic/sqrt.h @@ -28,11 +28,11 @@ template struct SpecialLongDouble { static constexpr bool VALUE = false; }; -#if defined(SPECIAL_X86_LONG_DOUBLE) +#if defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) template <> struct SpecialLongDouble { static constexpr bool VALUE = true; }; -#endif // SPECIAL_X86_LONG_DOUBLE +#endif // LIBC_LONG_DOUBLE_IS_X86_FLOAT80 template LIBC_INLINE void normalize(int &exponent, @@ -48,7 +48,7 @@ template <> LIBC_INLINE void normalize(int &exponent, uint64_t &mantissa) { normalize(exponent, mantissa); } -#elif !defined(SPECIAL_X86_LONG_DOUBLE) +#elif !defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) template <> LIBC_INLINE void normalize(int &exponent, UInt128 &mantissa) { const uint64_t hi_bits = static_cast(mantissa >> 64); diff --git a/libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h b/libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h index 713c33890510..a3bf7e3cabad 100644 --- a/libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h +++ b/libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h @@ -34,7 +34,7 @@ LIBC_INLINE long double sqrt(long double x); // Correctly rounded SQRT for all rounding modes. // Shift-and-add algorithm. -#if defined(SPECIAL_X86_LONG_DOUBLE) +#if defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) LIBC_INLINE long double sqrt(long double x) { using UIntType = typename FPBits::UIntType; constexpr UIntType ONE = UIntType(1) @@ -135,7 +135,7 @@ LIBC_INLINE long double sqrt(long double x) { return out; } } -#endif // SPECIAL_X86_LONG_DOUBLE +#endif // LIBC_LONG_DOUBLE_IS_X86_FLOAT80 } // namespace x86 } // namespace fputil diff --git a/libc/src/__support/macros/properties/float.h b/libc/src/__support/macros/properties/float.h index bd63f3346605..bae51cbe8aee 100644 --- a/libc/src/__support/macros/properties/float.h +++ b/libc/src/__support/macros/properties/float.h @@ -22,8 +22,7 @@ #if (LDBL_MANT_DIG == 53) #define LIBC_LONG_DOUBLE_IS_FLOAT64 #elif (LDBL_MANT_DIG == 64) -// TODO: Replace with LIBC_LONG_DOUBLE_IS_X86_BIN80 -#define SPECIAL_X86_LONG_DOUBLE +#define LIBC_LONG_DOUBLE_IS_X86_FLOAT80 #elif (LDBL_MANT_DIG == 113) #define LIBC_LONG_DOUBLE_IS_FLOAT128 #endif diff --git a/libc/src/__support/str_to_float.h b/libc/src/__support/str_to_float.h index a92325730414..a872c25e2f09 100644 --- a/libc/src/__support/str_to_float.h +++ b/libc/src/__support/str_to_float.h @@ -89,7 +89,7 @@ template LIBC_INLINE void set_implicit_bit(fputil::FPBits &) { return; } -#if defined(SPECIAL_X86_LONG_DOUBLE) +#if defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) template <> LIBC_INLINE void set_implicit_bit(fputil::FPBits &result) { @@ -529,7 +529,7 @@ public: static constexpr long double MAX_EXACT_INT = ClingerConsts::MAX_EXACT_INT; }; -#elif defined(SPECIAL_X86_LONG_DOUBLE) +#elif defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) template <> class ClingerConsts { public: static constexpr long double POWERS_OF_TEN_ARRAY[] = { diff --git a/libc/test/src/__support/str_to_float_test.cpp b/libc/test/src/__support/str_to_float_test.cpp index c2643d9a764e..f9d12d95a50b 100644 --- a/libc/test/src/__support/str_to_float_test.cpp +++ b/libc/test/src/__support/str_to_float_test.cpp @@ -283,7 +283,7 @@ TEST(LlvmLibcStrToFloatTest, SimpleDecimalConversionExtraTypes) { TEST_F(LlvmLibcStrToFloatTest, EiselLemireFloat64AsLongDouble) { eisel_lemire_test(123, 0, 0x1EC00000000000, 1029); } -#elif defined(SPECIAL_X86_LONG_DOUBLE) +#elif defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) TEST_F(LlvmLibcStrToFloatTest, EiselLemireFloat80Simple) { eisel_lemire_test(123, 0, 0xf600000000000000, 16389); eisel_lemire_test(12345678901234568192u, 0, 0xab54a98ceb1f0c00, diff --git a/libc/test/src/stdio/sprintf_test.cpp b/libc/test/src/stdio/sprintf_test.cpp index e2265f5efbc4..344853beaf9f 100644 --- a/libc/test/src/stdio/sprintf_test.cpp +++ b/libc/test/src/stdio/sprintf_test.cpp @@ -642,7 +642,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatHexExpConv) { // Length Modifier Tests. written = LIBC_NAMESPACE::sprintf(buff, "%La", 0.1L); -#if defined(SPECIAL_X86_LONG_DOUBLE) +#if defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) ASSERT_STREQ_LEN(written, buff, "0xc.ccccccccccccccdp-7"); #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "0x1.999999999999ap-4"); @@ -651,7 +651,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatHexExpConv) { #endif written = LIBC_NAMESPACE::sprintf(buff, "%La", 1.0e1000L); -#if defined(SPECIAL_X86_LONG_DOUBLE) +#if defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) ASSERT_STREQ_LEN(written, buff, "0xf.38db1f9dd3dac05p+3318"); #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "inf"); @@ -660,7 +660,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatHexExpConv) { #endif written = LIBC_NAMESPACE::sprintf(buff, "%La", 1.0e-1000L); -#if defined(SPECIAL_X86_LONG_DOUBLE) +#if defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) ASSERT_STREQ_LEN(written, buff, "0x8.68a9188a89e1467p-3325"); #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "0x0p+0"); @@ -766,7 +766,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatHexExpConv) { ASSERT_STREQ_LEN(written, buff, "0x0p+0"); written = LIBC_NAMESPACE::sprintf(buff, "%.1La", 0.1L); -#if defined(SPECIAL_X86_LONG_DOUBLE) +#if defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) ASSERT_STREQ_LEN(written, buff, "0xc.dp-7"); #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "0x1.ap-4"); @@ -775,7 +775,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatHexExpConv) { #endif written = LIBC_NAMESPACE::sprintf(buff, "%.1La", 0xf.fffffffffffffffp16380L); -#if defined(SPECIAL_X86_LONG_DOUBLE) +#if defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) ASSERT_STREQ_LEN(written, buff, "0x1.0p+16384"); #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "inf"); @@ -1024,7 +1024,8 @@ TEST_F(LlvmLibcSPrintfTest, FloatDecimalConv) { // Some float128 systems (specifically the ones used for aarch64 buildbots) // don't respect signs for long double NaNs. -#if defined(SPECIAL_X86_LONG_DOUBLE) || defined(LIBC_LONG_DOUBLE_IS_FLOAT64) +#if defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) || \ + defined(LIBC_LONG_DOUBLE_IS_FLOAT64) written = LIBC_NAMESPACE::sprintf(buff, "%LF", -ld_nan); ASSERT_STREQ_LEN(written, buff, "-NAN"); #endif @@ -1042,7 +1043,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatDecimalConv) { written = LIBC_NAMESPACE::sprintf(buff, "%.Lf", -2.5L); ASSERT_STREQ_LEN(written, buff, "-2"); -#if defined(SPECIAL_X86_LONG_DOUBLE) +#if defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) written = LIBC_NAMESPACE::sprintf(buff, "%Lf", 1e100L); ASSERT_STREQ_LEN(written, buff, @@ -1327,11 +1328,11 @@ TEST_F(LlvmLibcSPrintfTest, FloatDecimalConv) { "570449525088342437216896462077260223998756027453411520977536701491759878" "422771447006016890777855573925295187921971811871399320142563330377888532" "179817332113"); -#endif // SPECIAL_X86_LONG_DOUBLE +#endif // LIBC_LONG_DOUBLE_IS_X86_FLOAT80 /* written = LIBC_NAMESPACE::sprintf(buff, "%La", 0.1L); - #if defined(SPECIAL_X86_LONG_DOUBLE) + #if defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) ASSERT_STREQ_LEN(written, buff, "0xc.ccccccccccccccdp-7"); #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "0x1.999999999999ap-4"); @@ -1340,7 +1341,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatDecimalConv) { #endif written = LIBC_NAMESPACE::sprintf(buff, "%La", 1.0e1000L); - #if defined(SPECIAL_X86_LONG_DOUBLE) + #if defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) ASSERT_STREQ_LEN(written, buff, "0xf.38db1f9dd3dac05p+3318"); #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "inf"); @@ -1349,7 +1350,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatDecimalConv) { #endif written = LIBC_NAMESPACE::sprintf(buff, "%La", 1.0e-1000L); - #if defined(SPECIAL_X86_LONG_DOUBLE) + #if defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) ASSERT_STREQ_LEN(written, buff, "0x8.68a9188a89e1467p-3325"); #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "0x0p+0"); @@ -1548,7 +1549,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatDecimalConv) { /* written = LIBC_NAMESPACE::sprintf(buff, "%.1La", 0.1L); - #if defined(SPECIAL_X86_LONG_DOUBLE) + #if defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) ASSERT_STREQ_LEN(written, buff, "0xc.dp-7"); #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "0x1.ap-4"); @@ -1557,7 +1558,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatDecimalConv) { #endif written = LIBC_NAMESPACE::sprintf(buff, "%.1La", - 0xf.fffffffffffffffp16380L); #if defined(SPECIAL_X86_LONG_DOUBLE) + 0xf.fffffffffffffffp16380L); #if defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) ASSERT_STREQ_LEN(written, buff, "0x1.0p+16384"); #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "inf"); @@ -1858,7 +1859,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatExponentConv) { // Length Modifier Tests. -#if defined(SPECIAL_X86_LONG_DOUBLE) +#if defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) written = LIBC_NAMESPACE::sprintf(buff, "%.9Le", 1000000000500000000.1L); ASSERT_STREQ_LEN(written, buff, "1.000000001e+18"); @@ -1975,7 +1976,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatExponentConv) { */ /* written = LIBC_NAMESPACE::sprintf(buff, "%La", 0.1L); - #if defined(SPECIAL_X86_LONG_DOUBLE) + #if defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) ASSERT_STREQ_LEN(written, buff, "0xc.ccccccccccccccdp-7"); #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "0x1.999999999999ap-4"); @@ -1984,7 +1985,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatExponentConv) { #endif written = LIBC_NAMESPACE::sprintf(buff, "%La", 1.0e1000L); - #if defined(SPECIAL_X86_LONG_DOUBLE) + #if defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) ASSERT_STREQ_LEN(written, buff, "0xf.38db1f9dd3dac05p+3318"); #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "inf"); @@ -1993,7 +1994,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatExponentConv) { #endif written = LIBC_NAMESPACE::sprintf(buff, "%La", 1.0e-1000L); - #if defined(SPECIAL_X86_LONG_DOUBLE) + #if defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) ASSERT_STREQ_LEN(written, buff, "0x8.68a9188a89e1467p-3325"); #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "0x0p+0"); @@ -2171,7 +2172,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatExponentConv) { /* written = LIBC_NAMESPACE::sprintf(buff, "%.1La", 0.1L); - #if defined(SPECIAL_X86_LONG_DOUBLE) + #if defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) ASSERT_STREQ_LEN(written, buff, "0xc.dp-7"); #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "0x1.ap-4"); @@ -2180,7 +2181,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatExponentConv) { #endif written = LIBC_NAMESPACE::sprintf(buff, "%.1La", - 0xf.fffffffffffffffp16380L); #if defined(SPECIAL_X86_LONG_DOUBLE) + 0xf.fffffffffffffffp16380L); #if defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) ASSERT_STREQ_LEN(written, buff, "0x1.0p+16384"); #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "inf"); @@ -2499,7 +2500,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatAutoConv) { // Length Modifier Tests. -#if defined(SPECIAL_X86_LONG_DOUBLE) +#if defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) written = LIBC_NAMESPACE::sprintf(buff, "%Lg", 0xf.fffffffffffffffp+16380L); ASSERT_STREQ_LEN(written, buff, "1.18973e+4932"); @@ -2507,7 +2508,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatAutoConv) { written = LIBC_NAMESPACE::sprintf(buff, "%Lg", 0xa.aaaaaaaaaaaaaabp-7L); ASSERT_STREQ_LEN(written, buff, "0.0833333"); -#endif // SPECIAL_X86_LONG_DOUBLE +#endif // LIBC_LONG_DOUBLE_IS_X86_FLOAT80 // TODO: Uncomment the below tests after long double support is added /* @@ -2614,7 +2615,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatAutoConv) { */ /* written = LIBC_NAMESPACE::sprintf(buff, "%La", 0.1L); - #if defined(SPECIAL_X86_LONG_DOUBLE) + #if defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) ASSERT_STREQ_LEN(written, buff, "0xc.ccccccccccccccdp-7"); #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "0x1.999999999999ap-4"); @@ -2623,7 +2624,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatAutoConv) { #endif written = LIBC_NAMESPACE::sprintf(buff, "%La", 1.0e1000L); - #if defined(SPECIAL_X86_LONG_DOUBLE) + #if defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) ASSERT_STREQ_LEN(written, buff, "0xf.38db1f9dd3dac05p+3318"); #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "inf"); @@ -2632,7 +2633,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatAutoConv) { #endif written = LIBC_NAMESPACE::sprintf(buff, "%La", 1.0e-1000L); - #if defined(SPECIAL_X86_LONG_DOUBLE) + #if defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) ASSERT_STREQ_LEN(written, buff, "0x8.68a9188a89e1467p-3325"); #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "0x0p+0"); @@ -2806,21 +2807,21 @@ TEST_F(LlvmLibcSPrintfTest, FloatAutoConv) { written = LIBC_NAMESPACE::sprintf(buff, "%.10g", 0x1.0p-1074); ASSERT_STREQ_LEN(written, buff, "4.940656458e-324"); -#if defined(SPECIAL_X86_LONG_DOUBLE) +#if defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) written = LIBC_NAMESPACE::sprintf(buff, "%.60Lg", 0xa.aaaaaaaaaaaaaabp-7L); ASSERT_STREQ_LEN( written, buff, "0.0833333333333333333355920878593448009041821933351457118988037"); -#endif // SPECIAL_X86_LONG_DOUBLE +#endif // LIBC_LONG_DOUBLE_IS_X86_FLOAT80 // Long double precision tests. // These are currently commented out because they require long double support // that isn't ready yet. /* written = LIBC_NAMESPACE::sprintf(buff, "%.1La", 0.1L); - #if defined(SPECIAL_X86_LONG_DOUBLE) + #if defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) ASSERT_STREQ_LEN(written, buff, "0xc.dp-7"); #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "0x1.ap-4"); @@ -2829,7 +2830,7 @@ TEST_F(LlvmLibcSPrintfTest, FloatAutoConv) { #endif written = LIBC_NAMESPACE::sprintf(buff, "%.1La", - 0xf.fffffffffffffffp16380L); #if defined(SPECIAL_X86_LONG_DOUBLE) + 0xf.fffffffffffffffp16380L); #if defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) ASSERT_STREQ_LEN(written, buff, "0x1.0p+16384"); #elif defined(LIBC_LONG_DOUBLE_IS_FLOAT64) ASSERT_STREQ_LEN(written, buff, "inf"); diff --git a/libc/test/src/stdlib/strtold_test.cpp b/libc/test/src/stdlib/strtold_test.cpp index 1ddf729689ff..37db385c959b 100644 --- a/libc/test/src/stdlib/strtold_test.cpp +++ b/libc/test/src/stdlib/strtold_test.cpp @@ -18,7 +18,7 @@ #if defined(LIBC_LONG_DOUBLE_IS_FLOAT64) #define SELECT_CONST(val, _, __) val -#elif defined(SPECIAL_X86_LONG_DOUBLE) +#elif defined(LIBC_LONG_DOUBLE_IS_X86_FLOAT80) #define SELECT_CONST(_, val, __) val #else #define SELECT_CONST(_, __, val) val -- GitLab From da86d4a8c956f0fcee21444eb6de9f05d39d6574 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Fri, 1 Dec 2023 14:25:16 +0100 Subject: [PATCH 140/699] [ValueTracking] Reduce duplication in haveNoCommonBitsSet() (NFC) Extract a function and call it with both operand orders, so that we don't have to explicitly commute every single pattern. --- llvm/lib/Analysis/ValueTracking.cpp | 50 ++++++++++++++--------------- 1 file changed, 24 insertions(+), 26 deletions(-) diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp index d8a72c9f7b98..8c29c242215d 100644 --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -186,47 +186,30 @@ KnownBits llvm::computeKnownBits(const Value *V, const APInt &DemandedElts, SimplifyQuery(DL, DT, AC, safeCxtI(V, CxtI), UseInstrInfo)); } -bool llvm::haveNoCommonBitsSet(const WithCache &LHSCache, - const WithCache &RHSCache, - const SimplifyQuery &SQ) { - const Value *LHS = LHSCache.getValue(); - const Value *RHS = RHSCache.getValue(); - - assert(LHS->getType() == RHS->getType() && - "LHS and RHS should have the same type"); - assert(LHS->getType()->isIntOrIntVectorTy() && - "LHS and RHS should be integers"); +static bool haveNoCommonBitsSetSpecialCases(const Value *LHS, + const Value *RHS) { // Look for an inverted mask: (X & ~M) op (Y & M). { Value *M; if (match(LHS, m_c_And(m_Not(m_Value(M)), m_Value())) && match(RHS, m_c_And(m_Specific(M), m_Value()))) return true; - if (match(RHS, m_c_And(m_Not(m_Value(M)), m_Value())) && - match(LHS, m_c_And(m_Specific(M), m_Value()))) - return true; } // X op (Y & ~X) - if (match(RHS, m_c_And(m_Not(m_Specific(LHS)), m_Value())) || - match(LHS, m_c_And(m_Not(m_Specific(RHS)), m_Value()))) + if (match(RHS, m_c_And(m_Not(m_Specific(LHS)), m_Value()))) return true; // X op ((X & Y) ^ Y) -- this is the canonical form of the previous pattern // for constant Y. Value *Y; - if (match(RHS, - m_c_Xor(m_c_And(m_Specific(LHS), m_Value(Y)), m_Deferred(Y))) || - match(LHS, m_c_Xor(m_c_And(m_Specific(RHS), m_Value(Y)), m_Deferred(Y)))) + if (match(RHS, m_c_Xor(m_c_And(m_Specific(LHS), m_Value(Y)), m_Deferred(Y)))) return true; // Peek through extends to find a 'not' of the other side: // (ext Y) op ext(~Y) - // (ext ~Y) op ext(Y) - if ((match(LHS, m_ZExtOrSExt(m_Value(Y))) && - match(RHS, m_ZExtOrSExt(m_Not(m_Specific(Y))))) || - (match(RHS, m_ZExtOrSExt(m_Value(Y))) && - match(LHS, m_ZExtOrSExt(m_Not(m_Specific(Y)))))) + if (match(LHS, m_ZExtOrSExt(m_Value(Y))) && + match(RHS, m_ZExtOrSExt(m_Not(m_Specific(Y))))) return true; // Look for: (A & B) op ~(A | B) @@ -235,11 +218,26 @@ bool llvm::haveNoCommonBitsSet(const WithCache &LHSCache, if (match(LHS, m_And(m_Value(A), m_Value(B))) && match(RHS, m_Not(m_c_Or(m_Specific(A), m_Specific(B))))) return true; - if (match(RHS, m_And(m_Value(A), m_Value(B))) && - match(LHS, m_Not(m_c_Or(m_Specific(A), m_Specific(B))))) - return true; } + return false; +} + +bool llvm::haveNoCommonBitsSet(const WithCache &LHSCache, + const WithCache &RHSCache, + const SimplifyQuery &SQ) { + const Value *LHS = LHSCache.getValue(); + const Value *RHS = RHSCache.getValue(); + + assert(LHS->getType() == RHS->getType() && + "LHS and RHS should have the same type"); + assert(LHS->getType()->isIntOrIntVectorTy() && + "LHS and RHS should be integers"); + + if (haveNoCommonBitsSetSpecialCases(LHS, RHS) || + haveNoCommonBitsSetSpecialCases(RHS, LHS)) + return true; + return KnownBits::haveNoCommonBitsSet(LHSCache.getKnownBits(SQ), RHSCache.getKnownBits(SQ)); } -- GitLab From 6e3b2cb46ef5b9d9d28ed337491ee7da7b296616 Mon Sep 17 00:00:00 2001 From: Eleanor Bonnici Date: Fri, 1 Dec 2023 13:54:04 +0000 Subject: [PATCH 141/699] [llvm][MC][ARM][Assembly] Emit relocations for ADRs and big-endian targets (#73834) Follow-up on https://github.com/llvm/llvm-project/pull/72873/ When ADR/LDR instructions reference a label in a different section, the offset is not known until link time, however, the assembler assumes it can resolve them in some cases. The previous patch addressed the issue for most LDR instructions, focusing on little-endian targets. This patch addresses the remaining work for ADRs and big-endian targets. --- .../Target/ARM/MCTargetDesc/ARMAsmBackend.cpp | 15 ++++++----- .../ARM/MCTargetDesc/ARMELFObjectWriter.cpp | 6 +++++ llvm/test/MC/ARM/pcrel-adr16-relocs.s | 26 +++++++++++++++++++ llvm/test/MC/ARM/pcrel-adr32-relocs.s | 24 +++++++++++++++++ llvm/test/MC/ARM/pcrel-arm-ldr-imm8-relocs.s | 6 +++++ llvm/test/MC/ARM/pcrel-global.s | 10 ++----- llvm/test/MC/ARM/pcrel-ldr-relocs.s | 8 ++++-- llvm/test/MC/ARM/pcrel-thumb-ldr2-relocs.s | 3 +++ llvm/test/MC/ARM/thumb1-relax-adr.s | 1 - 9 files changed, 82 insertions(+), 17 deletions(-) create mode 100644 llvm/test/MC/ARM/pcrel-adr16-relocs.s create mode 100644 llvm/test/MC/ARM/pcrel-adr32-relocs.s diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp index ca3b77e4a356..41b3c6005231 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp @@ -88,10 +88,12 @@ const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, {"fixup_arm_ldst_abs_12", 0, 32, 0}, {"fixup_thumb_adr_pcrel_10", 0, 8, - IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, - {"fixup_arm_adr_pcrel_12", 0, 32, IsPCRelConstant}, + MCFixupKindInfo::FKF_IsPCRel | + MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, + {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, {"fixup_t2_adr_pcrel_12", 0, 32, - IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, + MCFixupKindInfo::FKF_IsPCRel | + MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, {"fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, {"fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, @@ -133,10 +135,11 @@ const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { // ARMFixupKinds.h. // // Name Offset (bits) Size (bits) Flags - {"fixup_arm_ldst_pcrel_12", 0, 32, IsPCRelConstant}, + {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, {"fixup_t2_ldst_pcrel_12", 0, 32, - IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, - {"fixup_arm_pcrel_10_unscaled", 0, 32, IsPCRelConstant}, + MCFixupKindInfo::FKF_IsPCRel | + MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, + {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, {"fixup_arm_pcrel_10", 0, 32, IsPCRelConstant}, {"fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel | diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp index 985097fc3281..44695a86c4e3 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp @@ -164,6 +164,12 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target, return ELF::R_ARM_LDRS_PC_G0; case ARM::fixup_t2_ldst_pcrel_12: return ELF::R_ARM_THM_PC12; + case ARM::fixup_arm_adr_pcrel_12: + return ELF::R_ARM_ALU_PC_G0; + case ARM::fixup_thumb_adr_pcrel_10: + return ELF::R_ARM_THM_PC8; + case ARM::fixup_t2_adr_pcrel_12: + return ELF::R_ARM_THM_ALU_PREL_11_0; case ARM::fixup_bf_target: return ELF::R_ARM_THM_BF16; case ARM::fixup_bfc_target: diff --git a/llvm/test/MC/ARM/pcrel-adr16-relocs.s b/llvm/test/MC/ARM/pcrel-adr16-relocs.s new file mode 100644 index 000000000000..adef746c3607 --- /dev/null +++ b/llvm/test/MC/ARM/pcrel-adr16-relocs.s @@ -0,0 +1,26 @@ +@ RUN: llvm-mc -filetype=obj --triple=thumbv6m-none-eabi %s -o %t +@ RUN: llvm-readelf -r %t | FileCheck %s --check-prefix=RELOC +@ RUN: llvm-objdump -d --triple=thumbv6m-none-eabi %t | FileCheck %s --check-prefix=ADDEND + + .section .text._func1, "ax" + + .balign 4 + .global _func1 + .type _func1, %function +_func1: + adr r0, _func2 +@ RELOC: R_ARM_THM_PC8 + bx lr + +// Checking the encoding only, as the disassembly is not quite correct here. +//00000000 <_func1>: +// 0: a0ff adr r0, #1020 <_func1+0x103> + +// Thumb16 encoding supports only adding of the encoded immediate (not +// subtracting, see [Arm ARM]), therefore sign change is required if the pcrel +// offset is negative. This makes the calculation of the addend for +// R_ARM_THM_PC8 more complex, for details see [ELF for the Arm 32-bit +// architecture]. + +@ ADDEND: a0ff adr + diff --git a/llvm/test/MC/ARM/pcrel-adr32-relocs.s b/llvm/test/MC/ARM/pcrel-adr32-relocs.s new file mode 100644 index 000000000000..5fd30f24630f --- /dev/null +++ b/llvm/test/MC/ARM/pcrel-adr32-relocs.s @@ -0,0 +1,24 @@ +@ RUN: llvm-mc -filetype=obj -triple=armv7 %s -o %t +@ RUN: llvm-readelf -r %t | FileCheck %s --check-prefix=RELOC +@ RUN: llvm-objdump -d --triple=armv7 %t | FileCheck %s --check-prefix=ADDEND + +@ RUN: llvm-mc -filetype=obj --triple=armebv7-unknown-unknown %s -o %t +@ RUN: llvm-readelf -r %t | FileCheck %s --check-prefix=RELOC +@ RUN: llvm-objdump -d --triple=armebv7-unknown-unknown %t | FileCheck %s --check-prefix=ADDEND + + .section .text._func1, "ax" + + .balign 4 + .global _func1 + .type _func1, %function +_func1: + adr r0, _func2 +@ RELOC: R_ARM_ALU_PC_G0 + .thumb + adr r0, _func2 +@ RELOC: R_ARM_THM_ALU_PREL_11_0 + bx lr + +@ ADDEND: sub r0, pc, #8 +@ ADDEND-NEXT: adr.w r0, #-4 + diff --git a/llvm/test/MC/ARM/pcrel-arm-ldr-imm8-relocs.s b/llvm/test/MC/ARM/pcrel-arm-ldr-imm8-relocs.s index 40453d6ef341..f8b166d4c248 100644 --- a/llvm/test/MC/ARM/pcrel-arm-ldr-imm8-relocs.s +++ b/llvm/test/MC/ARM/pcrel-arm-ldr-imm8-relocs.s @@ -1,6 +1,9 @@ @ RUN: llvm-mc -filetype=obj -triple=armv7 %s -o %t @ RUN: llvm-readelf -r %t | FileCheck %s --check-prefix=ARM @ RUN: llvm-objdump -d --triple=armv7 %t | FileCheck %s --check-prefix=ARM_ADDEND +@ RUN: llvm-mc -filetype=obj --triple=armebv7-unknown-unknown %s -o %t +@ RUN: llvm-readelf -r %t | FileCheck %s --check-prefix=ARM +@ RUN: llvm-objdump -d --triple=armebv7-unknown-unknown %t | FileCheck %s --check-prefix=ARM_ADDEND @ ARM: R_ARM_LDRS_PC_G0 @ ARM: R_ARM_LDRS_PC_G0 @@ -8,6 +11,7 @@ @ ARM: R_ARM_LDRS_PC_G0 @ ARM: R_ARM_LDRS_PC_G0 @ ARM: R_ARM_LDRS_PC_G0 +@ ARM: R_ARM_LDRS_PC_G0 // The value format is decimal in these specific cases, but it's hex for other // ldr instructions. These checks are valid for both formats. @@ -18,6 +22,7 @@ @ ARM_ADDEND: r0, [pc, #-{{16|0x10}}] @ ARM_ADDEND: r0, [pc, #-{{16|0x10}}] @ ARM_ADDEND: r0, [pc] +@ ARM_ADDEND: r0, r1, [pc] .arm .section .text.bar, "ax" @@ -31,6 +36,7 @@ bar: ldrh r0, just_after-8 ldrsb r0, just_after-8 ldrsh r0, foo+8 + ldrd r0,r1, foo+8 bx lr .section .data.foo, "a", %progbits diff --git a/llvm/test/MC/ARM/pcrel-global.s b/llvm/test/MC/ARM/pcrel-global.s index 15d46cf2063e..1e9e6e989356 100644 --- a/llvm/test/MC/ARM/pcrel-global.s +++ b/llvm/test/MC/ARM/pcrel-global.s @@ -7,11 +7,9 @@ @ CHECK: There are no relocations in this file. @ DISASM-LABEL: : -@ DISASM-NEXT: adr.w r0, #-4 -@ DISASM-NEXT: adr.w r0, #-8 -@ DISASM-NEXT: ldr r0, [pc, #0x0] @ 0x14 +@ DISASM-NEXT: ldr r0, [pc, #0x0] @ 0x8 @ DISASM-NEXT: add r0, pc -@ DISASM-NEXT: .word 0xfffffff3 +@ DISASM-NEXT: .word 0xfffffffb @@ GNU assembler creates an R_ARM_REL32 referencing bar. @ DISASM-NOT: {{.}} @@ -20,16 +18,12 @@ .globl foo foo: vldr d0, foo @ arm_pcrel_10 -adr r2, foo @ arm_adr_pcrel_12 .thumb .thumb_func .type bar, %function .globl bar bar: -adr r0, bar @ thumb_adr_pcrel_10 -adr.w r0, bar @ t2_adr_pcrel_12 - ldr r0, .LCPI .LPC0_1: add r0, pc diff --git a/llvm/test/MC/ARM/pcrel-ldr-relocs.s b/llvm/test/MC/ARM/pcrel-ldr-relocs.s index 120d54ebafe0..e0f27f299499 100644 --- a/llvm/test/MC/ARM/pcrel-ldr-relocs.s +++ b/llvm/test/MC/ARM/pcrel-ldr-relocs.s @@ -4,12 +4,17 @@ @ RUN: llvm-mc -filetype=obj -triple=thumbv7 %s -o %t @ RUN: llvm-readelf -r %t | FileCheck %s --check-prefix=THUMB @ RUN: llvm-objdump -d --triple=thumbv7 %t | FileCheck %s --check-prefix=THUMB_ADDEND +@ RUN: llvm-mc -filetype=obj -triple=armebv7 %s -o %t +@ RUN: llvm-readelf -r %t | FileCheck %s --check-prefix=ARM +@ RUN: llvm-objdump -d --triple=armebv7 %t | FileCheck %s --check-prefix=ARM_ADDEND +@ RUN: llvm-mc -filetype=obj -triple=thumbebv7 %s -o %t +@ RUN: llvm-readelf -r %t | FileCheck %s --check-prefix=THUMB +@ RUN: llvm-objdump -d --triple=thumbebv7 %t | FileCheck %s --check-prefix=THUMB_ADDEND @ ARM: R_ARM_LDR_PC_G0 @ ARM: R_ARM_LDR_PC_G0 @ ARM: R_ARM_LDR_PC_G0 @ ARM: R_ARM_LDR_PC_G0 - @ ARM_ADDEND: r0, [pc, #-0x8] @ ARM_ADDEND: r0, [pc, #-0x8] @ ARM_ADDEND: r0, [pc, #-0x10] @@ -19,7 +24,6 @@ @ THUMB: R_ARM_THM_PC12 @ THUMB: R_ARM_THM_PC12 @ THUMB: R_ARM_THM_PC12 - @ THUMB_ADDEND: r0, [pc, #-0x4] @ THUMB_ADDEND: r0, [pc, #-0x4] @ THUMB_ADDEND: r0, [pc, #-0xc] diff --git a/llvm/test/MC/ARM/pcrel-thumb-ldr2-relocs.s b/llvm/test/MC/ARM/pcrel-thumb-ldr2-relocs.s index 17ca72bd3f00..3aa371fc7d70 100644 --- a/llvm/test/MC/ARM/pcrel-thumb-ldr2-relocs.s +++ b/llvm/test/MC/ARM/pcrel-thumb-ldr2-relocs.s @@ -1,6 +1,9 @@ @ RUN: llvm-mc -filetype=obj -triple=thumbv7 %s -o %t @ RUN: llvm-readelf -r %t | FileCheck %s --check-prefix=THUMB @ RUN: llvm-objdump -d --triple=thumbv7 %t | FileCheck %s --check-prefix=THUMB_ADDEND +@ RUN: llvm-mc -filetype=obj --triple=thumbebv7-unknown-unknown %s -o %t +@ RUN: llvm-readelf -r %t | FileCheck %s --check-prefix=THUMB +@ RUN: llvm-objdump -d --triple=thumbebv7-unknown-unknown %t | FileCheck %s --check-prefix=THUMB_ADDEND @ All the ldr variants produce a relocation @ THUMB: R_ARM_THM_PC12 diff --git a/llvm/test/MC/ARM/thumb1-relax-adr.s b/llvm/test/MC/ARM/thumb1-relax-adr.s index fc5c7c39df5a..97b566f4833e 100644 --- a/llvm/test/MC/ARM/thumb1-relax-adr.s +++ b/llvm/test/MC/ARM/thumb1-relax-adr.s @@ -1,6 +1,5 @@ @ RUN: not llvm-mc -triple thumbv6m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s @ RUN: not llvm-mc -triple thumbv7m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s -@ RUN: not llvm-mc -triple thumbv7m-none-eabi -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s .global func1 _func1: -- GitLab From 6ab7662f35bb5bc1d19a7e68ec0a710bbf71c2c4 Mon Sep 17 00:00:00 2001 From: Vlad Serebrennikov Date: Fri, 1 Dec 2023 17:56:27 +0400 Subject: [PATCH 142/699] [clang][NFC] Refactor expected directives in C++ DRs 100-199 (#74061) This patch continues the work started with ea5b1ef016d020c37f903d6c7d4f623be975dab8. See that commit and its corresponding PR for details. --- clang/test/CXX/drs/dr0xx.cpp | 56 ++- clang/test/CXX/drs/dr1xx.cpp | 681 ++++++++++++++++++++++------------- 2 files changed, 458 insertions(+), 279 deletions(-) diff --git a/clang/test/CXX/drs/dr0xx.cpp b/clang/test/CXX/drs/dr0xx.cpp index e79ce6daf265..768da0f8e6fa 100644 --- a/clang/test/CXX/drs/dr0xx.cpp +++ b/clang/test/CXX/drs/dr0xx.cpp @@ -89,12 +89,11 @@ namespace dr7 { // dr7: 3.4 class B : virtual private A {}; // #dr7-B class C : public B {} c; // #dr7-C // expected-error@#dr7-C {{inherited virtual base class 'A' has private destructor}} - // expected-note@#dr7-C {{in implicit default constructor for 'dr7::C' first required here}} - // expected-note@#dr7-B {{declared private here}} - + // expected-note@#dr7-C {{in implicit default constructor for 'dr7::C' first required here}} + // expected-note@#dr7-B {{declared private here}} // expected-error@#dr7-C {{inherited virtual base class 'A' has private destructor}} - // expected-note@#dr7-C {{in implicit destructor for 'dr7::C' first required here}} - // expected-note@#dr7-B {{declared private here}} + // expected-note@#dr7-C {{in implicit destructor for 'dr7::C' first required here}} + // expected-note@#dr7-B {{declared private here}} class VeryDerivedC : public B, virtual public A {} vdc; class X { ~X(); }; // #dr7-X @@ -237,11 +236,10 @@ namespace dr16 { // dr16: 2.8 // expected-note@#dr16-A-f-decl {{member is declared here}} A::f(); // #dr16-A-f-call // expected-error@#dr16-A-f-call {{'A' is a private member of 'dr16::A'}} - // expected-note@#dr16-B {{constrained by implicitly private inheritance here}} - // expected-note@#dr16-A {{member is declared here}} - + // expected-note@#dr16-B {{constrained by implicitly private inheritance here}} + // expected-note@#dr16-A {{member is declared here}} // expected-error@#dr16-A-f-call {{cannot cast 'dr16::C' to its private base class 'dr16::A'}} - // expected-note@#dr16-B {{implicitly declared private here}} + // expected-note@#dr16-B {{implicitly declared private here}} } }; } @@ -361,9 +359,9 @@ namespace dr26 { // dr26: yes // FIXME: In C++98, we diagnose this twice. B(const B &, B = B()); // cxx98-14-error@-1 {{recursive evaluation of default argument}} - // cxx98-14-note@-2 {{default argument used here}} + // cxx98-14-note@-2 {{default argument used here}} // cxx98-error@-3 {{recursive evaluation of default argument}} - // cxx98-note@-4 {{default argument used here}} + // cxx98-note@-4 {{default argument used here}} }; struct C { static C &f(); @@ -788,23 +786,20 @@ namespace dr49 { // dr49: 2.8 A<&k> a; A

b; // #dr49-b // cxx98-error@#dr49-b {{non-type template argument referring to object 'p' with internal linkage is a C++11 extension}} - // cxx98-note@#dr49-p {{non-type template argument refers to object here}} - + // cxx98-note@#dr49-p {{non-type template argument refers to object here}} // cxx98-14-error@#dr49-b {{non-type template argument for template parameter of pointer type 'int *' must have its address taken}} - // cxx98-14-note@#dr49-A {{template parameter is declared here}} + // cxx98-14-note@#dr49-A {{template parameter is declared here}} int *q = &k; // #dr49-q A c; // #dr49-c // cxx98-error@#dr49-c {{non-type template argument for template parameter of pointer type 'int *' must have its address taken}} - // cxx98-note@#dr49-A {{template parameter is declared here}} - + // cxx98-note@#dr49-A {{template parameter is declared here}} // cxx11-14-error@#dr49-c {{non-type template argument of type 'int *' is not a constant expression}} - // cxx11-14-note@#dr49-c {{read of non-constexpr variable 'q' is not allowed in a constant expression}} - // cxx11-14-note@#dr49-q {{declared here}} - // cxx11-14-note@#dr49-A {{template parameter is declared here}} - + // cxx11-14-note@#dr49-c {{read of non-constexpr variable 'q' is not allowed in a constant expression}} + // cxx11-14-note@#dr49-q {{declared here}} + // cxx11-14-note@#dr49-A {{template parameter is declared here}} // since-cxx17-error@#dr49-c {{non-type template argument is not a constant expression}} - // since-cxx17-note@#dr49-c {{read of non-constexpr variable 'q' is not allowed in a constant expression}} - // since-cxx17-note@#dr49-q {{declared here}} + // since-cxx17-note@#dr49-c {{read of non-constexpr variable 'q' is not allowed in a constant expression}} + // since-cxx17-note@#dr49-q {{declared here}} } namespace dr50 { // dr50: yes @@ -835,11 +830,10 @@ namespace dr52 { // dr52: 2.8 int k = b.A::n; // #dr52-k // FIXME: This first diagnostic is very strangely worded, and seems to be bogus. // expected-error@#dr52-k {{'A' is a private member of 'dr52::A'}} - // expected-note@#dr52-B {{constrained by private inheritance here}} - // expected-note@#dr52-A {{member is declared here}} - + // expected-note@#dr52-B {{constrained by private inheritance here}} + // expected-note@#dr52-A {{member is declared here}} // expected-error@#dr52-k {{cannot cast 'struct B' to its private base class 'dr52::A'}} - // expected-note@#dr52-B {{declared private here}} + // expected-note@#dr52-B {{declared private here}} } namespace dr53 { // dr53: yes @@ -1171,8 +1165,7 @@ namespace dr76 { // dr76: yes const volatile int n = 1; int arr[n]; // #dr76-vla // expected-error@#dr76-vla {{variable length arrays in C++ are a Clang extension}} - // expected-note@#dr76-vla {{read of volatile-qualified type 'const volatile int' is not allowed in a constant expression}} - + // expected-note@#dr76-vla {{read of volatile-qualified type 'const volatile int' is not allowed in a constant expression}} // expected-error@#dr76-vla {{variable length array declaration not allowed at file scope}} } @@ -1346,8 +1339,7 @@ namespace dr92 { // dr92: 4 c++17 // since-cxx17-note@-2 {{use 'noexcept(false)' instead}} void (*p)() throw(int) = &f; // #dr92-p // since-cxx17-error@#dr92-p {{ISO C++17 does not allow dynamic exception specifications}} - // since-cxx17-note@#dr92-p {{use 'noexcept(false)' instead}} - + // since-cxx17-note@#dr92-p {{use 'noexcept(false)' instead}} // cxx98-14-error@#dr92-p {{target exception specification is not superset of source}} // since-cxx17-warning@#dr92-p {{target exception specification is not superset of source}} void (*q)() throw(int); @@ -1363,11 +1355,11 @@ namespace dr92 { // dr92: 4 c++17 g(f); // cxx98-14-error@-1 {{target exception specification is not superset of source}} // since-cxx17-error@-2 {{no matching function for call to 'g'}} - // since-cxx17-note@#dr92-g {{candidate function not viable: no known conversion from 'void () throw(int, float)' to 'void (*)() throw()' for 1st argument}} + // since-cxx17-note@#dr92-g {{candidate function not viable: no known conversion from 'void () throw(int, float)' to 'void (*)() throw()' for 1st argument}} g(q); // cxx98-14-error@-1 {{target exception specification is not superset of source}} // since-cxx17-error@-2 {{no matching function for call to 'g'}} - // since-cxx17-note@#dr92-g {{candidate function not viable: no known conversion from 'void (*)() throw(int)' to 'void (*)() throw()' for 1st argument}} + // since-cxx17-note@#dr92-g {{candidate function not viable: no known conversion from 'void (*)() throw(int)' to 'void (*)() throw()' for 1st argument}} } // Prior to C++17, this is OK because the exception specification is not diff --git a/clang/test/CXX/drs/dr1xx.cpp b/clang/test/CXX/drs/dr1xx.cpp index 50236eb7c949..4465e7e0f1bf 100644 --- a/clang/test/CXX/drs/dr1xx.cpp +++ b/clang/test/CXX/drs/dr1xx.cpp @@ -1,30 +1,31 @@ -// RUN: %clang_cc1 -std=c++98 -triple x86_64-unknown-unknown %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -// RUN: %clang_cc1 -std=c++11 -triple x86_64-unknown-unknown %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -// RUN: %clang_cc1 -std=c++14 -triple x86_64-unknown-unknown %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -// RUN: %clang_cc1 -std=c++17 -triple x86_64-unknown-unknown %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-unknown %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -// RUN: %clang_cc1 -std=c++23 -triple x86_64-unknown-unknown %s -verify -fexceptions -fcxx-exceptions -pedantic-errors +// RUN: %clang_cc1 -std=c++98 -triple x86_64-unknown-unknown %s -verify=expected,cxx98,cxx98-11,cxx98-14,cxx98-17 -fexceptions -fcxx-exceptions -pedantic-errors +// RUN: %clang_cc1 -std=c++11 -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11,cxx98-11,cxx98-14,cxx98-17,cxx11-14 -fexceptions -fcxx-exceptions -pedantic-errors +// RUN: %clang_cc1 -std=c++14 -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11,cxx98-14,cxx98-17,cxx11-14 -fexceptions -fcxx-exceptions -pedantic-errors +// RUN: %clang_cc1 -std=c++17 -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11,since-cxx17,cxx98-17 -fexceptions -fcxx-exceptions -pedantic-errors +// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11,since-cxx17 -fexceptions -fcxx-exceptions -pedantic-errors +// RUN: %clang_cc1 -std=c++23 -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11,since-cxx17 -fexceptions -fcxx-exceptions -pedantic-errors namespace dr100 { // dr100: yes - template struct A {}; // expected-note 0-1{{declared here}} - template struct B {}; // expected-note 0-1{{declared here}} - template struct C {}; // expected-note 0-1{{declared here}} - template struct D {}; // expected-note 0-1{{declared here}} - A<&"foo"> a; // #100a - B<"bar"> b; // #100b - C<"baz"> c; // #100c - D<*"quux"> d; // #100d -#if __cplusplus < 201703L - // expected-error@#100a {{does not refer to any declaration}} - // expected-error@#100b {{does not refer to any declaration}} - // expected-error@#100c {{does not refer to any declaration}} - // expected-error@#100d {{does not refer to any declaration}} -#else - // expected-error@#100a {{pointer to string literal is not allowed in a template argument}} - // expected-error@#100b {{reference to string literal is not allowed in a template argument}} - // expected-error@#100c {{pointer to subobject of string literal is not allowed in a template argument}} - // expected-error@#100d {{reference to subobject of string literal is not allowed in a template argument}} -#endif + template struct A {}; // #dr100-A + template struct B {}; // #dr100-B + template struct C {}; // #dr100-C + template struct D {}; // #dr100-D + A<&"foo"> a; // #dr100-a + // cxx98-14-error@#dr100-a {{non-type template argument does not refer to any declaration}} + // cxx98-14-note@#dr100-A {{template parameter is declared here}} + // since-cxx17-error@#dr100-a {{pointer to string literal is not allowed in a template argument}} + B<"bar"> b; // #dr100-b + // cxx98-14-error@#dr100-b {{non-type template argument does not refer to any declaration}} + // cxx98-14-note@#dr100-B {{template parameter is declared here}} + // since-cxx17-error@#dr100-b {{reference to string literal is not allowed in a template argument}} + C<"baz"> c; // #dr100-c + // cxx98-14-error@#dr100-c {{non-type template argument does not refer to any declaration}} + // cxx98-14-note@#dr100-C {{template parameter is declared here}} + // since-cxx17-error@#dr100-c {{pointer to subobject of string literal is not allowed in a template argument}} + D<*"quux"> d; // #dr100-d + // cxx98-14-error@#dr100-d {{non-type template argument does not refer to any declaration}} + // cxx98-14-note@#dr100-D {{template parameter is declared here}} + // since-cxx17-error@#dr100-d {{reference to subobject of string literal is not allowed in a template argument}} } namespace dr101 { // dr101: 3.5 @@ -42,13 +43,16 @@ namespace dr101 { // dr101: 3.5 namespace dr102 { // dr102: yes namespace A { - template T f(T a, T b) { return a + b; } // expected-error {{neither visible in the template definition nor found by argument-dependent lookup}} + template T f(T a, T b) { return a + b; } + // expected-error@-1 {{call to function 'operator+' that is neither visible in the template definition nor found by argument-dependent lookup}} + // expected-note@#dr102-instantiation {{in instantiation of function template specialization 'dr102::A::f' requested here}} + // expected-note@#dr102-operator-plus {{'operator+' should be declared prior to the call site or in namespace 'dr102::B'}} } namespace B { struct S {}; } - B::S operator+(B::S, B::S); // expected-note {{should be declared prior to the call site or in namespace 'dr102::B'}} - template B::S A::f(B::S, B::S); // expected-note {{in instantiation of}} + B::S operator+(B::S, B::S); // #dr102-operator-plus + template B::S A::f(B::S, B::S); // #dr102-instantiation } // dr103: na @@ -58,13 +62,17 @@ namespace dr102 { // dr102: yes namespace dr106 { // dr106: sup 540 typedef int &r1; typedef r1 &r1; - typedef const r1 r1; // expected-warning {{has no effect}} - typedef const r1 &r1; // expected-warning {{has no effect}} + typedef const r1 r1; + // expected-warning@-1 {{'const' qualifier on reference type 'r1' (aka 'int &') has no effect}} + typedef const r1 &r1; + // expected-warning@-1 {{'const' qualifier on reference type 'r1' (aka 'int &') has no effect}} typedef const int &r2; typedef r2 &r2; - typedef const r2 r2; // expected-warning {{has no effect}} - typedef const r2 &r2; // expected-warning {{has no effect}} + typedef const r2 r2; + // expected-warning@-1 {{'const' qualifier on reference type 'r2' (aka 'const int &') has no effect}} + typedef const r2 &r2; + // expected-warning@-1 {{'const' qualifier on reference type 'r2' (aka 'const int &') has no effect}} } namespace dr107 { // dr107: yes @@ -76,10 +84,9 @@ namespace dr108 { // dr108: 2.9 template struct A { struct B { typedef int X; }; B::X x; -#if __cplusplus <= 201703L - // expected-error@-2 {{implicit 'typename' is a C++20 extension}} -#endif - struct C : B { X x; }; // expected-error {{unknown type name}} + // cxx98-17-error@-1 {{missing 'typename' prior to dependent type name B::X; implicit 'typename' is a C++20 extension}} + struct C : B { X x; }; + // expected-error@-1 {{unknown type name 'X'}} }; template<> struct A::B { int X; }; } @@ -87,46 +94,55 @@ namespace dr108 { // dr108: 2.9 namespace dr109 { // dr109: yes struct A { template void f(T); }; template struct B : T { - using T::template f; // expected-error {{'template' keyword not permitted here}} - using T::template f; // expected-error {{'template' keyword not permitted here}} expected-error {{using declaration cannot refer to a template specialization}} + using T::template f; + // expected-error@-1 {{'template' keyword not permitted here}} + using T::template f; + // expected-error@-1 {{'template' keyword not permitted here}} + // expected-error@-2 {{using declaration cannot refer to a template specialization}} // FIXME: We shouldn't suggest using the 'template' keyword in a location where it's not valid. - using T::f; // expected-error {{use 'template' keyword}} expected-error {{using declaration cannot refer to a template specialization}} - void g() { this->f(123); } // expected-error {{use 'template' keyword}} + using T::f; + // expected-error@-1 {{use 'template' keyword to treat 'f' as a dependent template name}} + // expected-error@-2 {{using declaration cannot refer to a template specialization}} + void g() { this->f(123); } + // expected-error@-1 {{use 'template' keyword to treat 'f' as a dependent template name}} }; } namespace dr111 { // dr111: dup 535 struct A { A(); A(volatile A&, int = 0); A(A&, const char * = "foo"); }; - struct B : A { B(); }; // expected-note +{{would lose const qualifier}} expected-note {{requires 0 arguments}} + struct B : A { B(); }; // #dr111-B const B b1; - B b2(b1); // expected-error {{no matching constructor}} + B b2(b1); + // expected-error@-1 {{no matching constructor for initialization of 'B'}} + // expected-note@#dr111-B {{candidate constructor (the implicit copy constructor) not viable: 1st argument ('const B') would lose const qualifier}} + // expected-note@#dr111-B {{candidate constructor not viable: requires 0 arguments, but 1 was provided}} } namespace dr112 { // dr112: yes struct T { int n; }; typedef T Arr[1]; - const T a1[1] = {}; + const T a1[1] = {}; // #dr112-a1 volatile T a2[1] = {}; - const Arr a3 = {}; + const Arr a3 = {}; // #dr112-a3 volatile Arr a4 = {}; template struct X {}; + // FIXME: Test this somehow in C++11 and on. X x1; + // cxx98-error@-1 {{non-type template argument referring to object 'a1' with internal linkage is a C++11 extension}} + // cxx98-note@#dr112-a1 {{non-type template argument refers to object here}} X x2; X x3; + // cxx98-error@-1 {{non-type template argument referring to object 'a3' with internal linkage is a C++11 extension}} + // cxx98-note@#dr112-a3 {{non-type template argument refers to object here}} X x4; -#if __cplusplus < 201103L - // expected-error@-5 {{internal linkage}} expected-note@-10 {{here}} - // expected-error@-4 {{internal linkage}} expected-note@-9 {{here}} -#else - // FIXME: Test this somehow. -#endif } namespace dr113 { // dr113: yes extern void (*p)(); void f() { - no_such_function(); // expected-error {{undeclared}} + no_such_function(); + // expected-error@-1 {{use of undeclared identifier 'no_such_function'}} p(); } void g(); @@ -135,31 +151,48 @@ namespace dr113 { // dr113: yes namespace dr114 { // dr114: yes struct A { - virtual void f(int) = 0; // expected-note {{unimplemented}} + virtual void f(int) = 0; // #dr114-A-f }; struct B : A { template void f(T); void g() { f(0); } - } b; // expected-error {{abstract}} + } b; + // expected-error@-1 {{variable type 'struct B' is an abstract class}} + // expected-note@#dr114-A-f {{unimplemented pure virtual method 'f' in 'B'}} } namespace dr115 { // dr115: 3.0 - template int f(T); // expected-note +{{}} - template int g(T); // expected-note +{{}} - template int g(T, int); // expected-note +{{}} + template int f(T); // #dr115-f + template int g(T); // #dr115-g + template int g(T, int); // #dr115-g-int - int k1 = f(&f); // expected-error {{no match}} + int k1 = f(&f); + // expected-error@-1 {{no matching function for call to 'f'}} + // expected-note@#dr115-f {{candidate template ignored: couldn't infer template argument 'T'}} int k2 = f(&f); - int k3 = f(&g); // expected-error {{no match}} + int k3 = f(&g); + // expected-error@-1 {{no matching function for call to 'f'}} + // expected-note@#dr115-f {{candidate template ignored: couldn't infer template argument 'T'}} void h() { - (void)&f; // expected-error {{address of overloaded function 'f' cannot be cast to type 'void'}} + (void)&f; + // expected-error@-1 {{address of overloaded function 'f' cannot be cast to type 'void'}} + // expected-note@#dr115-f {{candidate function template}} (void)&f; - (void)&g; // expected-error {{address of overloaded function 'g' cannot be cast to type 'void'}} - - &f; // expected-error {{reference to overloaded function could not be resolved}} - &f; // expected-warning {{unused}} - &g; // expected-error {{reference to overloaded function could not be resolved}} + (void)&g; + // expected-error@-1 {{address of overloaded function 'g' cannot be cast to type 'void'}} + // expected-note@#dr115-g-int {{candidate function template}} + // expected-note@#dr115-g {{candidate function template}} + + &f; + // expected-error@-1 {{reference to overloaded function could not be resolved; did you mean to call it?}} + // expected-note@#dr115-f {{possible target for call}} + &f; + // expected-warning@-1 {{expression result unused}} + &g; + // expected-error@-1 {{reference to overloaded function could not be resolved; did you mean to call it?}} + // expected-note@#dr115-g-int {{possible target for call}} + // expected-note@#dr115-g {{possible target for call}} } struct S { @@ -168,18 +201,25 @@ namespace dr115 { // dr115: 3.0 template static int g(T, int); } s; - int k4 = f(&s.f); // expected-error {{non-constant pointer to member}} + int k4 = f(&s.f); + // expected-error@-1 {{cannot create a non-constant pointer to member function}} int k5 = f(&s.f); - int k6 = f(&s.g); // expected-error {{non-constant pointer to member}} + int k6 = f(&s.g); + // expected-error@-1 {{cannot create a non-constant pointer to member function}} void i() { - (void)&s.f; // expected-error {{non-constant pointer to member}} + (void)&s.f; + // expected-error@-1 {{cannot create a non-constant pointer to member function}} (void)&s.f; - (void)&s.g; // expected-error {{non-constant pointer to member}} - - &s.f; // expected-error {{non-constant pointer to member}} - &s.f; // expected-warning {{unused}} - &s.g; // expected-error {{non-constant pointer to member}} + (void)&s.g; + // expected-error@-1 {{cannot create a non-constant pointer to member function}} + + &s.f; + // expected-error@-1 {{cannot create a non-constant pointer to member function}} + &s.f; + // expected-warning@-1 {{expression result unused}} + &s.g; + // expected-error@-1 {{cannot create a non-constant pointer to member function}} } struct T { @@ -188,40 +228,58 @@ namespace dr115 { // dr115: 3.0 template int g(T, int); } t; - int k7 = f(&s.f); // expected-error {{non-constant pointer to member}} + int k7 = f(&s.f); + // expected-error@-1 {{cannot create a non-constant pointer to member function}} int k8 = f(&s.f); - int k9 = f(&s.g); // expected-error {{non-constant pointer to member}} + int k9 = f(&s.g); + // expected-error@-1 {{cannot create a non-constant pointer to member function}} void j() { - (void)&s.f; // expected-error {{non-constant pointer to member}} + (void)&s.f; + // expected-error@-1 {{cannot create a non-constant pointer to member function}} (void)&s.f; - (void)&s.g; // expected-error {{non-constant pointer to member}} - - &s.f; // expected-error {{non-constant pointer to member}} - &s.f; // expected-warning {{unused}} - &s.g; // expected-error {{non-constant pointer to member}} + (void)&s.g; + // expected-error@-1 {{cannot create a non-constant pointer to member function}} + + &s.f; + // expected-error@-1 {{cannot create a non-constant pointer to member function}} + &s.f; + // expected-warning@-1 {{expression result unused}} + &s.g; + // expected-error@-1 {{cannot create a non-constant pointer to member function}} } #if __cplusplus >= 201103L // Special case kicks in only if a template argument list is specified. - template void with_default(); // expected-note +{{}} - int k10 = f(&with_default); // expected-error {{no matching function}} + template void with_default(); // #dr115-with-default + int k10 = f(&with_default); + // expected-error@-1 {{no matching function for call to 'f'}} + // expected-note@#dr115-f {{candidate template ignored: couldn't infer template argument 'T'}} int k11 = f(&with_default<>); void k() { - (void)&with_default; // expected-error {{overloaded function}} + (void)&with_default; + // expected-error@-1 {{address of overloaded function 'with_default' cannot be cast to type 'void'}} + // expected-note@#dr115-with-default {{candidate function template}} (void)&with_default<>; - &with_default; // expected-error {{overloaded function}} - &with_default<>; // expected-warning {{unused}} + &with_default; + // expected-error@-1 {{reference to overloaded function could not be resolved; did you mean to call it?}} + // expected-note@#dr115-with-default {{possible target for call}} + &with_default<>; + // expected-warning@-1 {{expression result unused}} } #endif } namespace dr116 { // dr116: yes template struct A {}; - template void f(A) {} // expected-note {{previous}} - template void f(A) {} // expected-error {{redefinition}} - template void f(A) {} // expected-note {{previous}} - template void f(A) {} // expected-error {{redefinition}} + template void f(A) {} // #dr116-f-N + template void f(A) {} + // expected-error@-1 {{redefinition of 'f'}} + // expected-note@#dr116-f-N {{previous definition is here}} + template void f(A) {} // #dr116-f-T + template void f(A) {} + // expected-error@-1 {{redefinition of 'f'}} + // expected-note@#dr116-f-T {{previous definition is here}} } // dr117: na @@ -235,7 +293,9 @@ namespace dr121 { // dr121: yes }; template struct Z { X::Y x; - T::Y y; // expected-error +{{}} + T::Y y; + // expected-error@-1 {{use 'template' keyword to treat 'Y' as a dependent template name}} + // cxx98-17-error@-2 {{missing 'typename' prior to dependent type name T::Y; implicit 'typename' is a C++20 extension}} }; Z z; } @@ -249,15 +309,19 @@ namespace dr122 { // dr122: yes // dr124: dup 201 // dr125: yes -struct dr125_A { struct dr125_B {}; }; // expected-note {{here}} +struct dr125_A { struct dr125_B {}; }; // #dr125_B dr125_A::dr125_B dr125_C(); namespace dr125_B { dr125_A dr125_C(); } namespace dr125 { struct X { friend dr125_A::dr125_B (::dr125_C)(); // ok friend dr125_A (::dr125_B::dr125_C)(); // ok - friend dr125_A::dr125_B::dr125_C(); // expected-error {{did you mean the constructor name 'dr125_B'?}} - // expected-error@-1 {{missing exception specification}} + friend dr125_A::dr125_B::dr125_C(); // #dr125_C + // expected-error@#dr125_C {{missing return type for function 'dr125_C'; did you mean the constructor name 'dr125_B'?}} + // cxx98-error@#dr125_C {{'dr125_B' is missing exception specification 'throw()'}} + // cxx98-note@#dr125_B {{previous declaration is here}} + // since-cxx11-error@#dr125_C {{'dr125_B' is missing exception specification 'noexcept'}} + // since-cxx11-note@#dr125_B {{previous declaration is here}} }; } @@ -275,7 +339,6 @@ namespace dr126 { // dr126: partial // So, when catching by non-const (or volatile) reference to pointer, we // should compare the exception type to the caught type and only accept an // exact match. -#if __cplusplus <= 201402L struct C {}; struct D : C {}; struct E : private C { friend class A; friend class B; }; @@ -283,53 +346,64 @@ namespace dr126 { // dr126: partial struct G : C {}; struct H : D, G {}; +#if __cplusplus <= 201402L struct A { virtual void cp() throw(C*); virtual void dp() throw(C*); - virtual void ep() throw(C*); // expected-note {{overridden}} - virtual void fp() throw(C*); // expected-note {{overridden}} + virtual void ep() throw(C*); // #dr126-ep + virtual void fp() throw(C*); // #dr126-fp virtual void gp() throw(C*); - virtual void hp() throw(C*); // expected-note {{overridden}} + virtual void hp() throw(C*); // #dr126-hp virtual void cr() throw(C&); virtual void dr() throw(C&); - virtual void er() throw(C&); // expected-note {{overridden}} - virtual void fr() throw(C&); // expected-note {{overridden}} + virtual void er() throw(C&); // #dr126-er + virtual void fr() throw(C&); // #dr126-fr virtual void gr() throw(C&); - virtual void hr() throw(C&); // expected-note {{overridden}} + virtual void hr() throw(C&); // #dr126-hr virtual void pv() throw(void*); -#if __cplusplus >= 201103L virtual void np() throw(C*); virtual void npm() throw(int C::*); - virtual void nr() throw(C*&); // expected-note {{overridden}} + virtual void nr() throw(C*&); // #dr126-nr virtual void ncr() throw(C*const&); -#endif virtual void ref1() throw(C *const&); virtual void ref2() throw(C *); virtual void v() throw(int); virtual void w() throw(const int); - virtual void x() throw(int*); // expected-note {{overridden}} + virtual void x() throw(int*); // #dr126-x virtual void y() throw(const int*); - virtual void z() throw(int); // expected-note {{overridden}} + virtual void z() throw(int); // #dr126-z }; struct B : A { virtual void cp() throw(C*); virtual void dp() throw(D*); - virtual void ep() throw(E*); // expected-error {{more lax}} - virtual void fp() throw(F*); // expected-error {{more lax}} + virtual void ep() throw(E*); + // cxx98-14-error@-1 {{exception specification of overriding function is more lax than base version}} + // cxx98-14-note@#dr126-ep {{overridden virtual function is here}} + virtual void fp() throw(F*); + // cxx98-14-error@-1 {{exception specification of overriding function is more lax than base version}} + // cxx98-14-note@#dr126-fp {{overridden virtual function is here}} virtual void gp() throw(G*); - virtual void hp() throw(H*); // expected-error {{more lax}} + virtual void hp() throw(H*); + // cxx98-14-error@-1 {{exception specification of overriding function is more lax than base version}} + // cxx98-14-note@#dr126-hp {{overridden virtual function is here}} virtual void cr() throw(C&); virtual void dr() throw(D&); - virtual void er() throw(E&); // expected-error {{more lax}} - virtual void fr() throw(F&); // expected-error {{more lax}} + virtual void er() throw(E&); + // cxx98-14-error@-1 {{exception specification of overriding function is more lax than base version}} + // cxx98-14-note@#dr126-er {{overridden virtual function is here}} + virtual void fr() throw(F&); + // cxx98-14-error@-1 {{exception specification of overriding function is more lax than base version}} + // cxx98-14-note@#dr126-fr {{overridden virtual function is here}} virtual void gr() throw(G&); - virtual void hr() throw(H&); // expected-error {{more lax}} + virtual void hr() throw(H&); + // cxx98-14-error@-1 {{exception specification of overriding function is more lax than base version}} + // cxx98-14-note@#dr126-hr {{overridden virtual function is here}} virtual void pv() throw(C*); @@ -337,22 +411,29 @@ namespace dr126 { // dr126: partial using nullptr_t = decltype(nullptr); virtual void np() throw(nullptr_t); virtual void npm() throw(nullptr_t&); - virtual void nr() throw(nullptr_t); // expected-error {{more lax}} + virtual void nr() throw(nullptr_t); + // cxx11-14-error@-1 {{exception specification of overriding function is more lax than base version}} + // cxx11-14-note@#dr126-nr {{overridden virtual function is here}} virtual void ncr() throw(nullptr_t); -#endif +#endif // __cplusplus >= 201103L virtual void ref1() throw(D *const &); virtual void ref2() throw(D *); virtual void v() throw(const int); virtual void w() throw(int); - virtual void x() throw(const int*); // expected-error {{more lax}} + virtual void x() throw(const int*); + // cxx98-14-error@-1 {{exception specification of overriding function is more lax than base version}} + // cxx98-14-note@#dr126-x {{overridden virtual function is here}} virtual void y() throw(int*); // ok - virtual void z() throw(long); // expected-error {{more lax}} + virtual void z() throw(long); + // cxx98-14-error@-1 {{exception specification of overriding function is more lax than base version}} + // cxx98-14-note@#dr126-z {{overridden virtual function is here}} }; -#else - void f() throw(int); // expected-error {{ISO C++17 does not allow}} expected-note {{use 'noexcept}} -#endif +#endif // __cplusplus <= 201402L + void f() throw(int); + // since-cxx17-error@-1 {{ISO C++17 does not allow dynamic exception specifications}} + // since-cxx17-note@-2 {{use 'noexcept(false)' instead}} } namespace dr127 { // dr127: yes @@ -360,11 +441,16 @@ namespace dr127 { // dr127: yes template struct A { A() { throw 0; } void *operator new(size_t, const char * = 0); - void operator delete(void *, const char *) { T::error; } // expected-error 2{{no members}} + void operator delete(void *, const char *) { T::error; } // #dr127-delete-const-char + // expected-error@#dr127-delete-const-char {{type 'void' cannot be used prior to '::' because it has no members}} + // expected-note@#dr127-p {{in instantiation of member function 'dr127::A::operator delete' requested here}} + + // expected-error@#dr127-delete-const-char {{type 'int' cannot be used prior to '::' because it has no members}} + // expected-note@#dr127-q {{in instantiation of member function 'dr127::A::operator delete' requested here}} void operator delete(void *) { T::error; } }; - A *p = new A; // expected-note {{instantiat}} - A *q = new ("") A; // expected-note {{instantiat}} + A *p = new A; // #dr127-p + A *q = new ("") A; // #dr127-q } namespace dr128 { // dr128: yes @@ -401,36 +487,50 @@ namespace dr135 { // dr135: yes } namespace dr136 { // dr136: 3.4 - void f(int, int, int = 0); // expected-note {{previous declaration is here}} - void g(int, int, int); // expected-note {{previous declaration is here}} + void f(int, int, int = 0); // #dr136-f + void g(int, int, int); // #dr136-g struct A { - friend void f(int, int = 0, int); // expected-error {{friend declaration specifying a default argument must be the only declaration}} - friend void g(int, int, int = 0); // expected-error {{friend declaration specifying a default argument must be the only declaration}} - friend void h(int, int, int = 0); // expected-error {{friend declaration specifying a default argument must be a definition}} - friend void i(int, int, int = 0) {} // expected-note {{previous declaration is here}} + friend void f(int, int = 0, int); + // expected-error@-1 {{friend declaration specifying a default argument must be the only declaration}} + // expected-note@#dr136-f {{previous declaration is here}} + friend void g(int, int, int = 0); + // expected-error@-1 {{friend declaration specifying a default argument must be the only declaration}} + // expected-note@#dr136-g {{previous declaration is here}} + friend void h(int, int, int = 0); + // expected-error@-1 {{friend declaration specifying a default argument must be a definition}} + friend void i(int, int, int = 0) {} // #dr136-A-i friend void j(int, int, int = 0) {} operator int(); }; - void i(int, int, int); // expected-error {{friend declaration specifying a default argument must be the only declaration}} + void i(int, int, int); + // expected-error@-1 {{friend declaration specifying a default argument must be the only declaration}} + // expected-note@#dr136-A-i {{previous declaration is here}} void q() { j(A(), A()); // ok, has default argument } - extern "C" void k(int, int, int, int); // expected-note 2{{previous declaration is here}} + extern "C" void k(int, int, int, int); // #dr136-k namespace NSA { struct A { - friend void dr136::k(int, int, int, int = 0); // expected-error {{friend declaration specifying a default argument must be the only declaration}} + friend void dr136::k(int, int, int, int = 0); + // expected-error@-1 {{friend declaration specifying a default argument must be the only declaration}} + // expected-note@#dr136-k {{previous declaration is here}} }; } namespace NSB { struct A { - friend void dr136::k(int, int, int = 0, int); // expected-error {{missing default argument on parameter}} expected-error {{must be the only declaration}} + friend void dr136::k(int, int, int = 0, int); // #dr136-friend-k + // expected-error@#dr136-friend-k {{friend declaration specifying a default argument must be the only declaration}} + // expected-note@#dr136-k {{previous declaration is here}} + // expected-error@#dr136-friend-k {{missing default argument on parameter}} }; } struct B { - void f(int); // expected-note {{previous declaration is here}} + void f(int); // #dr136-B-f }; struct C { - friend void B::f(int = 0); // expected-error {{friend declaration specifying a default argument must be the only declaration}} + friend void B::f(int = 0); + // expected-error@-1 {{friend declaration specifying a default argument must be the only declaration}} + // expected-note@#dr136-B-f {{previous declaration is here}} }; } @@ -440,13 +540,18 @@ namespace dr137 { // dr137: yes extern volatile void *vp; extern const volatile void *cvp; int *q = static_cast(p); - int *qc = static_cast(cp); // expected-error {{casts away qualifiers}} - int *qv = static_cast(vp); // expected-error {{casts away qualifiers}} - int *qcv = static_cast(cvp); // expected-error {{casts away qualifiers}} + int *qc = static_cast(cp); + // expected-error@-1 {{static_cast from 'const void *' to 'int *' casts away qualifiers}} + int *qv = static_cast(vp); + // expected-error@-1 {{static_cast from 'volatile void *' to 'int *' casts away qualifiers}} + int *qcv = static_cast(cvp); + // expected-error@-1 {{static_cast from 'const volatile void *' to 'int *' casts away qualifiers}} const int *cq = static_cast(p); const int *cqc = static_cast(cp); - const int *cqv = static_cast(vp); // expected-error {{casts away qualifiers}} - const int *cqcv = static_cast(cvp); // expected-error {{casts away qualifiers}} + const int *cqv = static_cast(vp); + // expected-error@-1 {{static_cast from 'volatile void *' to 'const int *' casts away qualifiers}} + const int *cqcv = static_cast(cvp); + // expected-error@-1 {{static_cast from 'const volatile void *' to 'const int *' casts away qualifiers}} const volatile int *cvq = static_cast(p); const volatile int *cvqc = static_cast(cp); const volatile int *cvqv = static_cast(vp); @@ -455,9 +560,11 @@ namespace dr137 { // dr137: yes namespace dr139 { // dr139: yes namespace example1 { - typedef int f; // expected-note {{previous}} + typedef int f; // #dr139-typedef-f struct A { - friend void f(A &); // expected-error {{different kind of symbol}} + friend void f(A &); + // expected-error@-1 {{redefinition of 'f' as different kind of symbol}} + // expected-note@#dr139-typedef-f {{previous definition is here}} }; } @@ -474,35 +581,41 @@ namespace dr139 { // dr139: yes } namespace dr140 { // dr140: yes - void f(int *const) {} // expected-note {{previous}} - void f(int[3]) {} // expected-error {{redefinition}} + void f(int *const) {} // #dr140-f-first + void f(int[3]) {} + // expected-error@-1 {{redefinition of 'f'}} + // expected-note@#dr140-f-first {{previous definition is here}} void g(const int); void g(int n) { n = 2; } } namespace dr141 { // dr141: 3.1 template void f(); - template struct S { int n; }; // expected-note {{'::dr141::S::n' declared here}} + template struct S { int n; }; // #dr141-S struct A : S { template void f(); - template struct S {}; + template struct S {}; // #dr141-A-S } a; struct B : S {} b; void g() { a.f(); - (void)a.S::n; // expected-error {{no member named 'n' in 'dr141::A::S'; did you mean '::dr141::S::n'?}} -#if __cplusplus < 201103L - // expected-error@-2 {{ambiguous}} - // expected-note@-11 {{lookup from the current scope}} - // expected-note@-9 {{lookup in the object type}} -#endif - b.f(); // expected-error {{no member}} expected-error +{{}} + (void)a.S::n; // #dr141-a + // cxx98-error@#dr141-a {{lookup of 'S' in member access expression is ambiguous; using member of 'struct A'}} + // cxx98-note@#dr141-A-S {{lookup in the object type 'struct A' refers here}} + // cxx98-note@#dr141-S {{lookup from the current scope refers here}} + // expected-error@#dr141-a {{no member named 'n' in 'dr141::A::S'; did you mean '::dr141::S::n'?}} + // expected-note@#dr141-S {{'::dr141::S::n' declared here}} + // FIXME: we issue a useful diagnostic first, then some bogus ones. + b.f(); + // expected-error@-1 {{no member named 'f' in 'dr141::B'}} + // expected-error@-2 +{{}} (void)b.S::n; } template struct C { T t; void g() { - t.f(); // expected-error {{use 'template'}} + t.f(); + // expected-error@-1 {{use 'template' keyword to treat 'f' as a dependent template name}} } void h() { (void)t.S::n; // ok @@ -519,28 +632,53 @@ namespace dr141 { // dr141: 3.1 } namespace dr142 { // dr142: 2.8 - class B { // expected-note +{{here}} + class B { // #dr142-B public: - int mi; // expected-note +{{here}} - static int si; // expected-note +{{here}} + int mi; // #dr142-B-mi + static int si; // #dr142-B-si }; - class D : private B { // expected-note +{{here}} + class D : private B { // #dr142-D }; class DD : public D { void f(); }; void DD::f() { - mi = 3; // expected-error {{private member}} - si = 3; // expected-error {{private member}} - B b_old; // expected-error {{private member}} + mi = 3; + // expected-error@-1 {{'mi' is a private member of 'dr142::B'}} + // expected-note@#dr142-D {{constrained by private inheritance here}} + // expected-note@#dr142-B-mi {{member is declared here}} + si = 3; + // expected-error@-1 {{'si' is a private member of 'dr142::B'}} + // expected-note@#dr142-D {{constrained by private inheritance here}} + // expected-note@#dr142-B-si {{member is declared here}} + B b_old; + // expected-error@-1 {{'B' is a private member of 'dr142::B'}} + // expected-note@#dr142-D {{constrained by private inheritance here}} + // expected-note@#dr142-B {{member is declared here}} dr142::B b; b.mi = 3; b.si = 3; - B::si = 3; // expected-error {{private member}} + B::si = 3; + // expected-error@-1 {{'B' is a private member of 'dr142::B'}} + // expected-note@#dr142-D {{constrained by private inheritance here}} + // expected-note@#dr142-B {{member is declared here}} dr142::B::si = 3; - B *bp1_old = this; // expected-error {{private member}} expected-error {{private base class}} - dr142::B *bp1 = this; // expected-error {{private base class}} - B *bp2_old = (B*)this; // expected-error 2{{private member}} + B *bp1_old = this; // #dr142-bp1_old + // expected-error@#dr142-bp1_old {{'B' is a private member of 'dr142::B'}} + // expected-note@#dr142-D {{constrained by private inheritance here}} + // expected-note@#dr142-B {{member is declared here}} + // expected-error@#dr142-bp1_old {{cannot cast 'dr142::DD' to its private base class 'B'}} + // expected-note@#dr142-D {{declared private here}} + dr142::B *bp1 = this; + // expected-error@-1 {{cannot cast 'dr142::DD' to its private base class 'dr142::B'}} + // expected-note@#dr142-D {{declared private here}} + B *bp2_old = (B*)this; // #dr142-bp2_old + // expected-error@#dr142-bp2_old {{'B' is a private member of 'dr142::B'}} + // expected-note@#dr142-D {{constrained by private inheritance here}} + // expected-note@#dr142-B {{member is declared here}} + // expected-error@#dr142-bp2_old {{'B' is a private member of 'dr142::B'}} + // expected-note@#dr142-D {{constrained by private inheritance here}} + // expected-note@#dr142-B {{member is declared here}} dr142::B *bp2 = (dr142::B*)this; bp2->mi = 3; } @@ -553,19 +691,19 @@ namespace dr143 { // dr143: yes struct X { friend void B::f(X); }; } void g(A::X x) { - f(x); // expected-error {{undeclared identifier 'f'}} + f(x); + // expected-error@-1 {{use of undeclared identifier 'f'}} } } namespace dr145 { // dr145: yes void f(bool b) { -#if __cplusplus <= 201402L - ++b; // expected-warning {{deprecated}} - b++; // expected-warning {{deprecated}} -#else - ++b; // expected-error {{increment}} - b++; // expected-error {{increment}} -#endif + ++b; + // cxx98-14-warning@-1 {{incrementing expression of type bool is deprecated and incompatible with C++17}} + // since-cxx17-error@-2 {{ISO C++17 does not allow incrementing expression of type bool}} + b++; + // cxx98-14-warning@-1 {{incrementing expression of type bool is deprecated and incompatible with C++17}} + // since-cxx17-error@-2 {{ISO C++17 does not allow incrementing expression of type bool}} } } @@ -576,13 +714,15 @@ namespace dr147 { // dr147: yes }; // Per core issue 1435, this is ill-formed because A::A does not // name the injected-class-name. (A::A does, though.) - template<> template<> A::A(int) {} // expected-error {{out-of-line constructor for 'A' cannot have template arguments}} + template<> template<> A::A(int) {} + // expected-error@-1 {{out-of-line constructor for 'A' cannot have template arguments}} template<> template<> A::A(float) {} } namespace example2 { struct A { A(); }; struct B : A { B(); }; - A::A a1; // expected-error {{is a constructor}} + A::A a1; + // expected-error@-1 {{qualified reference to 'A' is a constructor name rather than a type in this context}} B::A a2; } namespace example3 { @@ -590,7 +730,8 @@ namespace dr147 { // dr147: yes template A(T); static A a; }; - template<> A::A(A::a); // expected-error {{is a constructor}} + template<> A::A(A::a); + // expected-error@-1 {{qualified reference to 'A' is a constructor name rather than a template name in this context}} } } @@ -616,24 +757,28 @@ namespace dr151 { // dr151: 3.1 namespace dr152 { // dr152: yes struct A { - A(); // expected-note 0-2{{not viable}} - explicit A(const A&); // expected-note 1-2{{not a candidate}} + A(); // #dr152-A-ctor + explicit A(const A&); // #dr152-A-explicit-ctor }; A a1 = A(); -#if __cplusplus <= 201402L - // expected-error@-2 {{no matching constructor}} -#endif + // cxx98-14-error@-1 {{no matching constructor for initialization of 'A'}} + // cxx98-14-note@#dr152-A-explicit-ctor {{explicit constructor is not a candidate}} + // cxx98-14-note@#dr152-A-ctor {{candidate constructor not viable: requires 0 arguments, but 1 was provided}} A a2((A())); A &f(); - A a3 = f(); // expected-error {{no matching constructor}} + A a3 = f(); + // expected-error@-1 {{no matching constructor for initialization of 'A'}} + // expected-note@#dr152-A-explicit-ctor {{explicit constructor is not a candidate}} + // expected-note@#dr152-A-ctor {{candidate constructor not viable: requires 0 arguments, but 1 was provided}} A a4(f()); } // dr153: na namespace dr154 { // dr154: yes - union { int a; }; // expected-error {{must be declared 'static'}} + union { int a; }; + // expected-error@-1 {{nonymous unions at namespace or global scope must be declared 'static'}} namespace { union { int b; }; } @@ -641,7 +786,8 @@ namespace dr154 { // dr154: yes } namespace dr155 { // dr155: dup 632 - struct S { int n; } s = { { 1 } }; // expected-warning {{braces around scalar initializer}} + struct S { int n; } s = { { 1 } }; + // expected-warning@-1 {{braces around scalar initializer}} } // dr158 is in its own file. @@ -649,7 +795,8 @@ namespace dr155 { // dr155: dup 632 namespace dr159 { // dr159: 3.5 namespace X { void f(); } void f(); - void dr159::f() {} // expected-warning {{extra qualification}} + void dr159::f() {} + // expected-warning@-1 {{extra qualification on member 'f'}} void dr159::X::f() {} } @@ -658,9 +805,9 @@ namespace dr159 { // dr159: 3.5 namespace dr161 { // dr161: 3.1 class A { protected: - struct B { int n; } b; // expected-note 2{{here}} + struct B { int n; } b; // #dr161-B static B bs; - void f(); // expected-note {{here}} + void f(); // #dr161-f static void sf(); }; struct C : A {}; @@ -669,13 +816,19 @@ namespace dr161 { // dr161: 3.1 (void)b.n; B b1; C::B b2; // ok, accessible as a member of A - (void)&C::b; // expected-error {{protected}} + (void)&C::b; + // expected-error@-1 {{'b' is a protected member of 'dr161::A'}} + // expected-note@#dr161-B {{declared protected here}} (void)&C::bs; - (void)c.b; // expected-error {{protected}} + (void)c.b; + // expected-error@-1 {{'b' is a protected member of 'dr161::A'}} + // expected-note@#dr161-B {{declared protected here}} (void)c.bs; f(); sf(); - c.f(); // expected-error {{protected}} + c.f(); + // expected-error@-1 {{protected}} + // expected-note@#dr161-f {{declared protected here}} c.sf(); A::f(); D::f(); @@ -692,13 +845,17 @@ namespace dr162 { // dr162: no static int &f(int); void g() { - int &a = (&A::f)(0); // FIXME: expected-error {{could not be resolved}} - char &b = (&A::f)('0'); // expected-error {{could not be resolved}} + int &a = (&A::f)(0); + // FIXME: expected-error@-1 {{reference to overloaded function could not be resolved; did you mean to call it?}} + char &b = (&A::f)('0'); + // expected-error@-1 {{reference to overloaded function could not be resolved; did you mean to call it?}} } }; - int &c = (&A::f)(0); // FIXME: expected-error {{could not be resolved}} - char &d = (&A::f)('0'); // expected-error {{could not be resolved}} + int &c = (&A::f)(0); + // FIXME: expected-error@-1 {{reference to overloaded function could not be resolved; did you mean to call it?}} + char &d = (&A::f)('0'); + // expected-error@-1 {{reference to overloaded function could not be resolved; did you mean to call it?}} } // dr163: na @@ -729,7 +886,10 @@ namespace dr166 { // dr166: 2.9 template int f(T t) { return t.n; } int g(A::X); - template int h(T t) { return t.n; } // expected-error {{private}} + template int h(T t) { return t.n; } + // expected-error@-1 {{'n' is a private member of 'dr166::A::X'}} + // expected-note@#dr166-h-instantiation {{in instantiation of function template specialization 'dr166::h' requested here}} + // expected-note@#dr166-X-n {{implicitly declared private here}} int i(A::X); namespace A { @@ -738,7 +898,7 @@ namespace dr166 { // dr166: 2.9 friend int dr166::g(X); friend int h(X); friend int i(X); - int n; // expected-note 2{{here}} + int n; // #dr166-X-n }; int h(X x) { return x.n; } @@ -747,8 +907,10 @@ namespace dr166 { // dr166: 2.9 template int f(A::X); int g(A::X x) { return x.n; } - template int h(A::X); // expected-note {{instantiation}} - int i(A::X x) { return x.n; } // expected-error {{private}} + template int h(A::X); // #dr166-h-instantiation + int i(A::X x) { return x.n; } + // expected-error@-1 {{'n' is a private member of 'dr166::A::X'}} + // expected-note@#dr166-X-n {{implicitly declared private here}} } // dr167: sup 1012 @@ -768,23 +930,29 @@ namespace dr169 { // dr169: yes struct B { template struct C; template void f(); - template static int n; // expected-error 0-1{{extension}} + template static int n; + // cxx98-11-error@-1 {{variable templates are a C++14 extension}} }; struct D : A, B { using A::n; - using B::C; // expected-error {{using declaration cannot refer to a template specialization}} - using B::f; // expected-error {{using declaration cannot refer to a template specialization}} - using B::n; // expected-error {{using declaration cannot refer to a template specialization}} + using B::C; + // expected-error@-1 {{using declaration cannot refer to a template specialization}} + using B::f; + // expected-error@-1 {{using declaration cannot refer to a template specialization}} + using B::n; + // expected-error@-1 {{using declaration cannot refer to a template specialization}} }; } namespace { // dr171: yes int dr171a; } -int dr171b; // expected-note {{here}} +int dr171b; // #dr171b-int namespace dr171 { extern "C" void dr171a(); - extern "C" void dr171b(); // expected-error {{conflicts}} + extern "C" void dr171b(); + // expected-error@-1 {{declaration of 'dr171b' with C language linkage conflicts with declaration in global scope}} + // expected-note@#dr171b-int {{declared in global scope here}} } namespace dr172 { // dr172: yes @@ -810,12 +978,14 @@ namespace dr172 { // dr172: yes int check6a[sizeof(d) == sizeof(unsigned long) ? 1 : -1]; int check6b[-d > 0 ? 1 : -1]; - enum { e = (unsigned long long)-1 / 2 }; // expected-error 0-1{{extension}} - int check7a[sizeof(e) == sizeof(long) ? 1 : -1]; // expected-error 0-1{{extension}} + enum { e = (unsigned long long)-1 / 2 }; + // cxx98-error@-1 {{'long long' is a C++11 extension}} + int check7a[sizeof(e) == sizeof(long) ? 1 : -1]; int check7b[-e < 0 ? 1 : -1]; - enum { f = (unsigned long long)-1 / 2 + 1 }; // expected-error 0-1{{extension}} - int check8a[sizeof(f) == sizeof(unsigned long) ? 1 : -1]; // expected-error 0-1{{extension}} + enum { f = (unsigned long long)-1 / 2 + 1 }; + // cxx98-error@-1 {{'long long' is a C++11 extension}} + int check8a[sizeof(f) == sizeof(unsigned long) ? 1 : -1]; int check8b[-f > 0 ? 1 : -1]; } @@ -828,10 +998,13 @@ namespace dr173 { // dr173: yes // dr174: sup 1012 namespace dr175 { // dr175: 2.8 - struct A {}; // expected-note {{here}} - struct B : private A {}; // expected-note {{constrained by private inheritance}} + struct A {}; // #dr175-A + struct B : private A {}; // #dr175-B struct C : B { - A a; // expected-error {{private}} + A a; + // expected-error@-1 {{'A' is a private member of 'dr175::A'}} + // expected-note@#dr175-B {{constrained by private inheritance here}} + // expected-note@#dr175-A {{member is declared here}} dr175::A b; }; } @@ -840,12 +1013,14 @@ namespace dr176 { // dr176: 3.1 template class Y; template<> class Y { void f() { - typedef Y A; // expected-note {{here}} - typedef Y A; // expected-error {{different types ('Y' vs 'Y')}} + typedef Y A; // #dr176-A-first + typedef Y A; + // expected-error@-1 {{typedef redefinition with different types ('Y' vs 'Y')}} + // expected-note@#dr176-A-first {{previous definition is here}} } }; - template struct Base {}; // expected-note 2{{found}} + template struct Base {}; // #dr176-Base template struct Derived : public Base { void f() { typedef typename Derived::template Base A; @@ -855,35 +1030,44 @@ namespace dr176 { // dr176: 3.1 template struct Derived; template struct Derived2 : Base, Base { - typename Derived2::Base b; // expected-error {{found in multiple base classes}} + typename Derived2::Base b; + // expected-error@-1 {{member 'Base' found in multiple base classes of different types}} + // expected-note@#dr176-Base {{member type 'dr176::Base' found by ambiguous name lookup}} + // expected-note@#dr176-Base {{member type 'dr176::Base' found by ambiguous name lookup}} typename Derived2::Base d; }; - template class X { // expected-note {{here}} + template class X { // #dr176-X X *p1; X *p2; X *p3; - dr176::X *p4; // expected-error {{requires template arguments}} + dr176::X *p4; // #dr176-p4 + // cxx98-14-error@#dr176-p4 {{use of class template 'dr176::X' requires template arguments}} + // cxx98-14-note@#dr176-X {{template is declared here}} + // since-cxx17-error@#dr176-p4 {{use of class template 'X' requires template arguments; argument deduction not allowed in non-static class member}} + // since-cxx17-note@#dr176-X {{template is declared here}} }; } namespace dr177 { // dr177: yes struct B {}; struct A { - A(A &); // expected-note 0-1{{not viable: expects an lvalue}} - A(const B &); // expected-note 0-1{{not viable: no known conversion from 'A' to}} + A(A &); // #dr177-A-copy-ctor + A(const B &); // #dr177-A-ctor-from-B }; B b; A a = b; -#if __cplusplus <= 201402L - // expected-error@-2 {{no viable constructor copying variable}} -#endif + // cxx98-14-error@-1 {{no viable constructor copying variable of type 'A'}} + // cxx98-14-note@#dr177-A-copy-ctor {{candidate constructor not viable: expects an lvalue for 1st argument}} + // cxx98-14-note@#dr177-A-ctor-from-B {{candidate constructor not viable: no known conversion from 'A' to 'const B &' for 1st argument}} - struct C { C(C&); }; // expected-note {{not viable: expects an lvalue for 1st argument}} + struct C { C(C&); }; // #dr177-C-copy-ctor struct D : C {}; struct E { operator D(); }; E e; - C c = e; // expected-error {{no viable constructor copying variable of type 'D'}} + C c = e; + // expected-error@-1 {{no viable constructor copying variable of type 'D'}} + // expected-note@#dr177-C-copy-ctor {{candidate constructor not viable: expects an lvalue for 1st argument}} } namespace dr178 { // dr178: yes @@ -901,7 +1085,8 @@ namespace dr178 { // dr178: yes namespace dr179 { // dr179: yes void f(); - int n = &f - &f; // expected-error {{arithmetic on pointers to the function type 'void ()'}} + int n = &f - &f; + // expected-error@-1 {{arithmetic on pointers to the function type 'void ()'}} } namespace dr180 { // dr180: 2.8 @@ -916,8 +1101,10 @@ namespace dr180 { // dr180: 2.8 namespace dr181 { // dr181: yes namespace X { - template

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