From 6ce03ff3fef8fb6fa9afe8eb22c6d98bced26d48 Mon Sep 17 00:00:00 2001 From: Shubham Sandeep Rastogi Date: Mon, 5 Feb 2024 15:30:35 -0800 Subject: [PATCH 001/266] Revert "[IR] Use range-based for loops (NFC)" This reverts commit e8512786fedbfa6ddba70ceddc29d7122173ba5e. This revert is done because llvm::drop_begin over an empty ArrayRef doesn't return an empty range, and therefore can lead to an invalid address returned instead. See discussion in https://github.com/llvm/llvm-project/pull/80737 for more context. --- llvm/lib/IR/AsmWriter.cpp | 4 ++-- llvm/lib/IR/AutoUpgrade.cpp | 4 ++-- llvm/lib/IR/DebugInfo.cpp | 4 ++-- llvm/lib/IR/Function.cpp | 7 ++++--- llvm/lib/IR/ProfDataUtils.cpp | 4 ++-- llvm/lib/IR/Verifier.cpp | 7 ++++--- 6 files changed, 16 insertions(+), 14 deletions(-) diff --git a/llvm/lib/IR/AsmWriter.cpp b/llvm/lib/IR/AsmWriter.cpp index 35a98767a8be..7b56c471a745 100644 --- a/llvm/lib/IR/AsmWriter.cpp +++ b/llvm/lib/IR/AsmWriter.cpp @@ -1309,8 +1309,8 @@ void SlotTracker::CreateMetadataSlot(const MDNode *N) { ++mdnNext; // Recursively add any MDNodes referenced by operands. - for (const MDOperand &MDO : N->operands()) - if (const MDNode *Op = dyn_cast_or_null(MDO)) + for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) + if (const MDNode *Op = dyn_cast_or_null(N->getOperand(i))) CreateMetadataSlot(Op); } diff --git a/llvm/lib/IR/AutoUpgrade.cpp b/llvm/lib/IR/AutoUpgrade.cpp index 19d80eb9aec0..b90bbe71ac18 100644 --- a/llvm/lib/IR/AutoUpgrade.cpp +++ b/llvm/lib/IR/AutoUpgrade.cpp @@ -5209,8 +5209,8 @@ static Metadata *upgradeLoopArgument(Metadata *MD) { SmallVector Ops; Ops.reserve(T->getNumOperands()); Ops.push_back(upgradeLoopTag(T->getContext(), OldTag->getString())); - for (const MDOperand &MDO : llvm::drop_begin(T->operands())) - Ops.push_back(MDO); + for (unsigned I = 1, E = T->getNumOperands(); I != E; ++I) + Ops.push_back(T->getOperand(I)); return MDTuple::get(T->getContext(), Ops); } diff --git a/llvm/lib/IR/DebugInfo.cpp b/llvm/lib/IR/DebugInfo.cpp index 2cf88292b14e..d8c1b0d534f6 100644 --- a/llvm/lib/IR/DebugInfo.cpp +++ b/llvm/lib/IR/DebugInfo.cpp @@ -400,8 +400,8 @@ static MDNode *updateLoopMetadataDebugLocationsImpl( // Save space for the self-referential LoopID. SmallVector MDs = {nullptr}; - for (const MDOperand &MDO : llvm::drop_begin(OrigLoopID->operands())) { - Metadata *MD = MDO; + for (unsigned i = 1; i < OrigLoopID->getNumOperands(); ++i) { + Metadata *MD = OrigLoopID->getOperand(i); if (!MD) MDs.push_back(nullptr); else if (Metadata *NewMD = Updater(MD)) diff --git a/llvm/lib/IR/Function.cpp b/llvm/lib/IR/Function.cpp index d3e2ae0dede4..22e2455462bf 100644 --- a/llvm/lib/IR/Function.cpp +++ b/llvm/lib/IR/Function.cpp @@ -1976,9 +1976,10 @@ DenseSet Function::getImportGUIDs() const { if (MDNode *MD = getMetadata(LLVMContext::MD_prof)) if (MDString *MDS = dyn_cast(MD->getOperand(0))) if (MDS->getString().equals("function_entry_count")) - for (const MDOperand &MDO : llvm::drop_begin(MD->operands(), 2)) - R.insert( - mdconst::extract(MDO)->getValue().getZExtValue()); + for (unsigned i = 2; i < MD->getNumOperands(); i++) + R.insert(mdconst::extract(MD->getOperand(i)) + ->getValue() + .getZExtValue()); return R; } diff --git a/llvm/lib/IR/ProfDataUtils.cpp b/llvm/lib/IR/ProfDataUtils.cpp index dcb057c1b25f..b1a10d0ce5a5 100644 --- a/llvm/lib/IR/ProfDataUtils.cpp +++ b/llvm/lib/IR/ProfDataUtils.cpp @@ -162,8 +162,8 @@ bool extractProfTotalWeight(const MDNode *ProfileData, uint64_t &TotalVal) { return false; if (ProfDataName->getString().equals("branch_weights")) { - for (const MDOperand &MDO : llvm::drop_begin(ProfileData->operands())) { - auto *V = mdconst::dyn_extract(MDO); + for (unsigned Idx = 1; Idx < ProfileData->getNumOperands(); Idx++) { + auto *V = mdconst::dyn_extract(ProfileData->getOperand(Idx)); assert(V && "Malformed branch_weight in MD_prof node"); TotalVal += V->getValue().getZExtValue(); } diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp index 8d992c232ca7..b04d39c700a8 100644 --- a/llvm/lib/IR/Verifier.cpp +++ b/llvm/lib/IR/Verifier.cpp @@ -2913,8 +2913,8 @@ void Verifier::visitFunction(const Function &F) { VisitDebugLoc(I, I.getDebugLoc().getAsMDNode()); // The llvm.loop annotations also contain two DILocations. if (auto MD = I.getMetadata(LLVMContext::MD_loop)) - for (const MDOperand &MDO : llvm::drop_begin(MD->operands())) - VisitDebugLoc(I, dyn_cast_or_null(MDO)); + for (unsigned i = 1; i < MD->getNumOperands(); ++i) + VisitDebugLoc(I, dyn_cast_or_null(MD->getOperand(i))); if (BrokenDebugInfo) return; } @@ -4713,7 +4713,8 @@ void Verifier::visitProfMetadata(Instruction &I, MDNode *MD) { Check(MD->getNumOperands() == 1 + ExpectedNumOperands, "Wrong number of operands", MD); } - for (const MDOperand &MDO : llvm::drop_begin(MD->operands())) { + for (unsigned i = 1; i < MD->getNumOperands(); ++i) { + auto &MDO = MD->getOperand(i); Check(MDO, "second operand should not be null", MD); Check(mdconst::dyn_extract(MDO), "!prof brunch_weights operand is not a const int"); -- GitLab From e2cfdf7b6a09a2159a2ce3cf4fff022b6d98b928 Mon Sep 17 00:00:00 2001 From: Nikolas Klauser Date: Tue, 6 Feb 2024 00:51:32 +0100 Subject: [PATCH 002/266] [libc++] Fix vector (#80711) #80558 introduced code that assumed that the element type of `vector` is never const. This fixes it and adds a test. Eventually we should remove the `allocator` extension. --- .../__memory/uninitialized_algorithms.h | 2 +- .../sequences/vector/const_T.compile.pass.cpp | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+), 1 deletion(-) create mode 100644 libcxx/test/libcxx/containers/sequences/vector/const_T.compile.pass.cpp diff --git a/libcxx/include/__memory/uninitialized_algorithms.h b/libcxx/include/__memory/uninitialized_algorithms.h index 9733bb748f66..7e25a5c5fa19 100644 --- a/libcxx/include/__memory/uninitialized_algorithms.h +++ b/libcxx/include/__memory/uninitialized_algorithms.h @@ -643,7 +643,7 @@ __uninitialized_allocator_relocate(_Alloc& __alloc, _Tp* __first, _Tp* __last, _ __guard.__complete(); std::__allocator_destroy(__alloc, __first, __last); } else { - __builtin_memcpy(__result, __first, sizeof(_Tp) * (__last - __first)); + __builtin_memcpy(const_cast<__remove_const_t<_Tp>*>(__result), __first, sizeof(_Tp) * (__last - __first)); } } diff --git a/libcxx/test/libcxx/containers/sequences/vector/const_T.compile.pass.cpp b/libcxx/test/libcxx/containers/sequences/vector/const_T.compile.pass.cpp new file mode 100644 index 000000000000..62fff96ac5ab --- /dev/null +++ b/libcxx/test/libcxx/containers/sequences/vector/const_T.compile.pass.cpp @@ -0,0 +1,18 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Make sure that `vector` works + +#include + +void test() { + std::vector v; + v.emplace_back(1); + v.push_back(1); + v.resize(3); +} -- GitLab From dbed89814e5b9ba25a349a5b9acf4a7164e33834 Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Mon, 5 Feb 2024 17:58:19 -0600 Subject: [PATCH 003/266] [AMDGPU] Add missing `__builtin_amdgcn_wavefrontsize` builtin (#80741) Summary: The backend supports the wavefrontsize intrinsic, and suggests that it is tied to a corresponding clang builtin, but it is not actually present. This simply adds it in so it can be used from clang. This attribute likely isn't the best to rely on, but for the `libc` use-case we will need to detect a struct's differing size in a way that will depend on the wavefront size. --- clang/include/clang/Basic/BuiltinsAMDGPU.def | 1 + clang/test/CodeGenOpenCL/builtins-amdgcn.cl | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/clang/include/clang/Basic/BuiltinsAMDGPU.def b/clang/include/clang/Basic/BuiltinsAMDGPU.def index 5f8001e61a02..213311b96df7 100644 --- a/clang/include/clang/Basic/BuiltinsAMDGPU.def +++ b/clang/include/clang/Basic/BuiltinsAMDGPU.def @@ -69,6 +69,7 @@ BUILTIN(__builtin_amdgcn_s_dcache_inv, "v", "n") BUILTIN(__builtin_amdgcn_buffer_wbinvl1, "v", "n") BUILTIN(__builtin_amdgcn_fence, "vUicC*", "n") BUILTIN(__builtin_amdgcn_groupstaticsize, "Ui", "n") +BUILTIN(__builtin_amdgcn_wavefrontsize, "Ui", "nc") BUILTIN(__builtin_amdgcn_atomic_inc32, "UZiUZiD*UZiUicC*", "n") BUILTIN(__builtin_amdgcn_atomic_inc64, "UWiUWiD*UWiUicC*", "n") diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn.cl index 8d9e4e018b12..7d9010ee9067 100644 --- a/clang/test/CodeGenOpenCL/builtins-amdgcn.cl +++ b/clang/test/CodeGenOpenCL/builtins-amdgcn.cl @@ -832,6 +832,13 @@ void test_atomic_inc_dec(local uint *lptr, global uint *gptr, uint val) { res = __builtin_amdgcn_atomic_dec32((volatile global uint*)gptr, val, __ATOMIC_SEQ_CST, ""); } +// CHECK-LABEL test_wavefrontsize( +unsigned test_wavefrontsize() { + + // CHECK: call i32 @llvm.amdgcn.wavefrontsize() + return __builtin_amdgcn_wavefrontsize(); +} + // CHECK-DAG: [[$WI_RANGE]] = !{i32 0, i32 1024} // CHECK-DAG: [[$WS_RANGE]] = !{i16 1, i16 1025} // CHECK-DAG: attributes #[[$NOUNWIND_READONLY]] = { convergent mustprogress nocallback nofree nounwind willreturn memory(none) } -- GitLab From 5a9af39aab40bba52d4e46cabf4b1ab47f614fa2 Mon Sep 17 00:00:00 2001 From: Aart Bik <39774503+aartbik@users.noreply.github.com> Date: Mon, 5 Feb 2024 16:12:47 -0800 Subject: [PATCH 004/266] [mlir][sparse] made sparse vectorizer more robust on position of invariants (#80766) Because the sparse vectorizer relies on the code coming out of the sparsifier, the "patterns" are not always made very general. However, a recent change in the generated code revealed an obvious situation where the subscript analysis could be made a bit more robust. Fixes: https://github.com/llvm/llvm-project/issues/79897 --- .../Dialect/SparseTensor/Transforms/SparseVectorization.cpp | 6 ++++++ mlir/test/Dialect/SparseTensor/sparse_vector_mv.mlir | 3 +-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/mlir/lib/Dialect/SparseTensor/Transforms/SparseVectorization.cpp b/mlir/lib/Dialect/SparseTensor/Transforms/SparseVectorization.cpp index 3a487a3bd6a0..2b81d6cdc1ea 100644 --- a/mlir/lib/Dialect/SparseTensor/Transforms/SparseVectorization.cpp +++ b/mlir/lib/Dialect/SparseTensor/Transforms/SparseVectorization.cpp @@ -316,6 +316,12 @@ static bool vectorizeSubscripts(PatternRewriter &rewriter, scf::ForOp forOp, if (auto load = cast.getDefiningOp()) { Value inv = load.getOperand(0); Value idx = load.getOperand(1); + // Swap non-invariant. + if (!isInvariantValue(inv, block)) { + inv = idx; + idx = load.getOperand(0); + } + // Inspect. if (isInvariantValue(inv, block)) { if (auto arg = llvm::dyn_cast(idx)) { if (isInvariantArg(arg, block) || !innermost) diff --git a/mlir/test/Dialect/SparseTensor/sparse_vector_mv.mlir b/mlir/test/Dialect/SparseTensor/sparse_vector_mv.mlir index dfee2b1261b6..e25c3a02f912 100644 --- a/mlir/test/Dialect/SparseTensor/sparse_vector_mv.mlir +++ b/mlir/test/Dialect/SparseTensor/sparse_vector_mv.mlir @@ -1,4 +1,3 @@ -// FIXME: re-enable. // RUN: mlir-opt %s -sparsifier="vl=8" | FileCheck %s #Dense = #sparse_tensor.encoding<{ @@ -16,7 +15,7 @@ } // CHECK-LABEL: llvm.func @kernel_matvec -// C_HECK: llvm.intr.vector.reduce.fadd +// CHECK: llvm.intr.vector.reduce.fadd func.func @kernel_matvec(%arga: tensor, %argb: tensor, %argx: tensor) -> tensor { -- GitLab From 792d928e15aa30c8b686eff465598ceea0b03891 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Mon, 5 Feb 2024 16:44:11 -0800 Subject: [PATCH 005/266] [workflows] Fix lldb-tests and libclc-tests (#80751) This was broken by d25022bb689b9bf48a24c0ae6c29c1d3c2f32823, which caused the workflow to pass an empty string to ninja as the target. The 'all' target is probably not the right target for these tests, but this is what the behavior was before d25022bb689b9bf48a24c0ae6c29c1d3c2f32823. --- .github/workflows/libclc-tests.yml | 1 - .github/workflows/lldb-tests.yml | 1 - .github/workflows/llvm-project-tests.yml | 3 ++- 3 files changed, 2 insertions(+), 3 deletions(-) diff --git a/.github/workflows/libclc-tests.yml b/.github/workflows/libclc-tests.yml index 29d050db2f12..23192f776a98 100644 --- a/.github/workflows/libclc-tests.yml +++ b/.github/workflows/libclc-tests.yml @@ -36,5 +36,4 @@ jobs: name: Test libclc uses: ./.github/workflows/llvm-project-tests.yml with: - build_target: '' projects: clang;libclc diff --git a/.github/workflows/lldb-tests.yml b/.github/workflows/lldb-tests.yml index ef5d7c7d581b..6bb972195625 100644 --- a/.github/workflows/lldb-tests.yml +++ b/.github/workflows/lldb-tests.yml @@ -36,5 +36,4 @@ jobs: name: Build lldb uses: ./.github/workflows/llvm-project-tests.yml with: - build_target: '' projects: clang;lldb diff --git a/.github/workflows/llvm-project-tests.yml b/.github/workflows/llvm-project-tests.yml index 494263be7f0d..3bc7bd4957fa 100644 --- a/.github/workflows/llvm-project-tests.yml +++ b/.github/workflows/llvm-project-tests.yml @@ -22,8 +22,9 @@ on: workflow_call: inputs: build_target: - required: true + required: false type: string + default: "all" projects: required: true -- GitLab From eff77d8456a5ba9a05a0c3a29113643fbb180230 Mon Sep 17 00:00:00 2001 From: Florian Mayer Date: Mon, 5 Feb 2024 16:47:02 -0800 Subject: [PATCH 006/266] [scudo] [MTE] resize stack depot for allocation ring buffer (#74515) Co-authored-by: ChiaHungDuan --- compiler-rt/lib/scudo/standalone/combined.h | 121 ++++++++++++++---- .../standalone/fuzz/get_error_info_fuzzer.cpp | 14 +- compiler-rt/lib/scudo/standalone/platform.h | 10 -- .../lib/scudo/standalone/stack_depot.h | 96 +++++++++++--- .../scudo/standalone/tests/combined_test.cpp | 38 +++++- .../scudo/standalone/wrappers_c_bionic.cpp | 9 +- 6 files changed, 219 insertions(+), 69 deletions(-) diff --git a/compiler-rt/lib/scudo/standalone/combined.h b/compiler-rt/lib/scudo/standalone/combined.h index 62473d14d1f9..fa64d12d9e19 100644 --- a/compiler-rt/lib/scudo/standalone/combined.h +++ b/compiler-rt/lib/scudo/standalone/combined.h @@ -9,6 +9,7 @@ #ifndef SCUDO_COMBINED_H_ #define SCUDO_COMBINED_H_ +#include "atomic_helpers.h" #include "chunk.h" #include "common.h" #include "flags.h" @@ -282,7 +283,7 @@ public: return reinterpret_cast(addHeaderTag(reinterpret_cast(Ptr))); } - NOINLINE u32 collectStackTrace() { + NOINLINE u32 collectStackTrace(UNUSED StackDepot *Depot) { #ifdef HAVE_ANDROID_UNSAFE_FRAME_POINTER_CHASE // Discard collectStackTrace() frame and allocator function frame. constexpr uptr DiscardFrames = 2; @@ -290,7 +291,7 @@ public: uptr Size = android_unsafe_frame_pointer_chase(Stack, MaxTraceSize + DiscardFrames); Size = Min(Size, MaxTraceSize + DiscardFrames); - return Depot.insert(Stack + Min(DiscardFrames, Size), Stack + Size); + return Depot->insert(Stack + Min(DiscardFrames, Size), Stack + Size); #else return 0; #endif @@ -687,12 +688,12 @@ public: Quarantine.disable(); Primary.disable(); Secondary.disable(); - Depot.disable(); + Depot->disable(); } void enable() NO_THREAD_SAFETY_ANALYSIS { initThreadMaybe(); - Depot.enable(); + Depot->enable(); Secondary.enable(); Primary.enable(); Quarantine.enable(); @@ -915,8 +916,14 @@ public: Primary.Options.clear(OptionBit::AddLargeAllocationSlack); } - const char *getStackDepotAddress() const { - return reinterpret_cast(&Depot); + const char *getStackDepotAddress() { + initThreadMaybe(); + return reinterpret_cast(Depot); + } + + uptr getStackDepotSize() { + initThreadMaybe(); + return StackDepotSize; } const char *getRegionInfoArrayAddress() const { @@ -945,21 +952,35 @@ public: if (!Depot->find(Hash, &RingPos, &Size)) return; for (unsigned I = 0; I != Size && I != MaxTraceSize; ++I) - Trace[I] = static_cast((*Depot)[RingPos + I]); + Trace[I] = static_cast(Depot->at(RingPos + I)); } static void getErrorInfo(struct scudo_error_info *ErrorInfo, uintptr_t FaultAddr, const char *DepotPtr, - const char *RegionInfoPtr, const char *RingBufferPtr, - size_t RingBufferSize, const char *Memory, - const char *MemoryTags, uintptr_t MemoryAddr, - size_t MemorySize) { + size_t DepotSize, const char *RegionInfoPtr, + const char *RingBufferPtr, size_t RingBufferSize, + const char *Memory, const char *MemoryTags, + uintptr_t MemoryAddr, size_t MemorySize) { + // N.B. we need to support corrupted data in any of the buffers here. We get + // this information from an external process (the crashing process) that + // should not be able to crash the crash dumper (crash_dump on Android). + // See also the get_error_info_fuzzer. *ErrorInfo = {}; if (!allocatorSupportsMemoryTagging() || MemoryAddr + MemorySize < MemoryAddr) return; - auto *Depot = reinterpret_cast(DepotPtr); + const StackDepot *Depot = nullptr; + if (DepotPtr) { + // check for corrupted StackDepot. First we need to check whether we can + // read the metadata, then whether the metadata matches the size. + if (DepotSize < sizeof(*Depot)) + return; + Depot = reinterpret_cast(DepotPtr); + if (!Depot->isValid(DepotSize)) + return; + } + size_t NextErrorReport = 0; // Check for OOB in the current block and the two surrounding blocks. Beyond @@ -1025,7 +1046,9 @@ private: uptr GuardedAllocSlotSize = 0; #endif // GWP_ASAN_HOOKS - StackDepot Depot; + StackDepot *Depot = nullptr; + uptr StackDepotSize = 0; + MemMapT RawStackDepotMap; struct AllocationRingBuffer { struct Entry { @@ -1234,11 +1257,18 @@ private: storeEndMarker(RoundNewPtr, NewSize, BlockEnd); } - void storePrimaryAllocationStackMaybe(const Options &Options, void *Ptr) { + StackDepot *getDepotIfEnabled(const Options &Options) { if (!UNLIKELY(Options.get(OptionBit::TrackAllocationStacks))) + return nullptr; + return Depot; + } + + void storePrimaryAllocationStackMaybe(const Options &Options, void *Ptr) { + auto *Depot = getDepotIfEnabled(Options); + if (!Depot) return; auto *Ptr32 = reinterpret_cast(Ptr); - Ptr32[MemTagAllocationTraceIndex] = collectStackTrace(); + Ptr32[MemTagAllocationTraceIndex] = collectStackTrace(Depot); Ptr32[MemTagAllocationTidIndex] = getThreadID(); } @@ -1268,10 +1298,10 @@ private: void storeSecondaryAllocationStackMaybe(const Options &Options, void *Ptr, uptr Size) { - if (!UNLIKELY(Options.get(OptionBit::TrackAllocationStacks))) + auto *Depot = getDepotIfEnabled(Options); + if (!Depot) return; - - u32 Trace = collectStackTrace(); + u32 Trace = collectStackTrace(Depot); u32 Tid = getThreadID(); auto *Ptr32 = reinterpret_cast(Ptr); @@ -1283,14 +1313,14 @@ private: void storeDeallocationStackMaybe(const Options &Options, void *Ptr, u8 PrevTag, uptr Size) { - if (!UNLIKELY(Options.get(OptionBit::TrackAllocationStacks))) + auto *Depot = getDepotIfEnabled(Options); + if (!Depot) return; - auto *Ptr32 = reinterpret_cast(Ptr); u32 AllocationTrace = Ptr32[MemTagAllocationTraceIndex]; u32 AllocationTid = Ptr32[MemTagAllocationTidIndex]; - u32 DeallocationTrace = collectStackTrace(); + u32 DeallocationTrace = collectStackTrace(Depot); u32 DeallocationTid = getThreadID(); storeRingBufferEntry(addFixedTag(untagPointer(Ptr), PrevTag), @@ -1369,8 +1399,10 @@ private: UntaggedFaultAddr < ChunkAddr ? BUFFER_UNDERFLOW : BUFFER_OVERFLOW; R->allocation_address = ChunkAddr; R->allocation_size = Header.SizeOrUnusedBytes; - collectTraceMaybe(Depot, R->allocation_trace, - Data[MemTagAllocationTraceIndex]); + if (Depot) { + collectTraceMaybe(Depot, R->allocation_trace, + Data[MemTagAllocationTraceIndex]); + } R->allocation_tid = Data[MemTagAllocationTidIndex]; return NextErrorReport == NumErrorReports; }; @@ -1393,7 +1425,7 @@ private: auto *RingBuffer = reinterpret_cast(RingBufferPtr); size_t RingBufferElements = ringBufferElementsFromBytes(RingBufferSize); - if (!RingBuffer || RingBufferElements == 0) + if (!RingBuffer || RingBufferElements == 0 || !Depot) return; uptr Pos = atomic_load_relaxed(&RingBuffer->Pos); @@ -1483,6 +1515,43 @@ private: return; u32 AllocationRingBufferSize = static_cast(getFlags()->allocation_ring_buffer_size); + + // We store alloc and free stacks for each entry. + constexpr u32 kStacksPerRingBufferEntry = 2; + constexpr u32 kMaxU32Pow2 = ~(UINT32_MAX >> 1); + static_assert(isPowerOfTwo(kMaxU32Pow2)); + constexpr u32 kFramesPerStack = 8; + static_assert(isPowerOfTwo(kFramesPerStack)); + + // We need StackDepot to be aligned to 8-bytes so the ring we store after + // is correctly assigned. + static_assert(sizeof(Depot) % alignof(atomic_u64) == 0); + + // Make sure the maximum sized StackDepot fits withint a uintptr_t to + // simplify the overflow checking. + static_assert(sizeof(Depot) + UINT32_MAX * sizeof(atomic_u64) * UINT32_MAX * + sizeof(atomic_u32) < + UINTPTR_MAX); + + if (AllocationRingBufferSize > kMaxU32Pow2 / kStacksPerRingBufferEntry) + return; + u32 TabSize = static_cast(roundUpPowerOfTwo(kStacksPerRingBufferEntry * + AllocationRingBufferSize)); + if (TabSize > UINT32_MAX / kFramesPerStack) + return; + u32 RingSize = static_cast(TabSize * kFramesPerStack); + DCHECK(isPowerOfTwo(RingSize)); + + StackDepotSize = sizeof(Depot) + sizeof(atomic_u64) * RingSize + + sizeof(atomic_u32) * TabSize; + MemMapT DepotMap; + DepotMap.map( + /*Addr=*/0U, roundUp(StackDepotSize, getPageSizeCached()), + "scudo:stack_depot"); + Depot = reinterpret_cast(DepotMap.getBase()); + Depot->init(RingSize, TabSize); + RawStackDepotMap = DepotMap; + MemMapT MemMap; MemMap.map( /*Addr=*/0U, @@ -1505,6 +1574,10 @@ private: RawRingBufferMap.getCapacity()); } RawRingBuffer = nullptr; + if (Depot) { + RawStackDepotMap.unmap(RawStackDepotMap.getBase(), + RawStackDepotMap.getCapacity()); + } } static constexpr size_t ringBufferSizeInBytes(u32 RingBufferElements) { diff --git a/compiler-rt/lib/scudo/standalone/fuzz/get_error_info_fuzzer.cpp b/compiler-rt/lib/scudo/standalone/fuzz/get_error_info_fuzzer.cpp index 5b01ebe11c09..2cef1c44fadc 100644 --- a/compiler-rt/lib/scudo/standalone/fuzz/get_error_info_fuzzer.cpp +++ b/compiler-rt/lib/scudo/standalone/fuzz/get_error_info_fuzzer.cpp @@ -9,6 +9,7 @@ #define SCUDO_FUZZ #include "allocator_config.h" #include "combined.h" +#include "common.h" #include @@ -31,11 +32,6 @@ extern "C" int LLVMFuzzerTestOneInput(uint8_t *Data, size_t Size) { std::string StackDepotBytes = FDP.ConsumeRandomLengthString(FDP.remaining_bytes()); - std::vector StackDepot(sizeof(scudo::StackDepot), 0); - for (size_t i = 0; i < StackDepotBytes.length() && i < StackDepot.size(); - ++i) { - StackDepot[i] = StackDepotBytes[i]; - } std::string RegionInfoBytes = FDP.ConsumeRandomLengthString(FDP.remaining_bytes()); @@ -48,9 +44,9 @@ extern "C" int LLVMFuzzerTestOneInput(uint8_t *Data, size_t Size) { std::string RingBufferBytes = FDP.ConsumeRemainingBytesAsString(); scudo_error_info ErrorInfo; - AllocatorT::getErrorInfo(&ErrorInfo, FaultAddr, StackDepot.data(), - RegionInfo.data(), RingBufferBytes.data(), - RingBufferBytes.size(), Memory, MemoryTags, - MemoryAddr, MemorySize); + AllocatorT::getErrorInfo(&ErrorInfo, FaultAddr, StackDepotBytes.data(), + StackDepotBytes.size(), RegionInfo.data(), + RingBufferBytes.data(), RingBufferBytes.size(), + Memory, MemoryTags, MemoryAddr, MemorySize); return 0; } diff --git a/compiler-rt/lib/scudo/standalone/platform.h b/compiler-rt/lib/scudo/standalone/platform.h index b71a86be7669..5af1275e32d2 100644 --- a/compiler-rt/lib/scudo/standalone/platform.h +++ b/compiler-rt/lib/scudo/standalone/platform.h @@ -63,16 +63,6 @@ #define SCUDO_CAN_USE_MTE (SCUDO_LINUX || SCUDO_TRUSTY) #endif -// Use smaller table sizes for fuzzing in order to reduce input size. -// Trusty just has less available memory. -#ifndef SCUDO_SMALL_STACK_DEPOT -#if defined(SCUDO_FUZZ) || SCUDO_TRUSTY -#define SCUDO_SMALL_STACK_DEPOT 1 -#else -#define SCUDO_SMALL_STACK_DEPOT 0 -#endif -#endif - #ifndef SCUDO_ENABLE_HOOKS #define SCUDO_ENABLE_HOOKS 0 #endif diff --git a/compiler-rt/lib/scudo/standalone/stack_depot.h b/compiler-rt/lib/scudo/standalone/stack_depot.h index e887d1b43a7c..8fe67ec0d54c 100644 --- a/compiler-rt/lib/scudo/standalone/stack_depot.h +++ b/compiler-rt/lib/scudo/standalone/stack_depot.h @@ -10,6 +10,7 @@ #define SCUDO_STACK_DEPOT_H_ #include "atomic_helpers.h" +#include "common.h" #include "mutex.h" namespace scudo { @@ -38,7 +39,7 @@ public: } }; -class StackDepot { +class alignas(16) StackDepot { HybridMutex RingEndMu; u32 RingEnd = 0; @@ -62,28 +63,81 @@ class StackDepot { // This is achieved by re-checking the hash of the stack trace before // returning the trace. -#if SCUDO_SMALL_STACK_DEPOT - static const uptr TabBits = 4; -#else - static const uptr TabBits = 16; -#endif - static const uptr TabSize = 1 << TabBits; - static const uptr TabMask = TabSize - 1; - atomic_u32 Tab[TabSize] = {}; - -#if SCUDO_SMALL_STACK_DEPOT - static const uptr RingBits = 4; -#else - static const uptr RingBits = 19; -#endif - static const uptr RingSize = 1 << RingBits; - static const uptr RingMask = RingSize - 1; - atomic_u64 Ring[RingSize] = {}; + uptr RingSize = 0; + uptr RingMask = 0; + uptr TabMask = 0; + // This is immediately followed by RingSize atomic_u64 and + // (TabMask + 1) atomic_u32. + + atomic_u64 *getRing() { + return reinterpret_cast(reinterpret_cast(this) + + sizeof(StackDepot)); + } + + atomic_u32 *getTab() { + return reinterpret_cast(reinterpret_cast(this) + + sizeof(StackDepot) + + sizeof(atomic_u64) * RingSize); + } + + const atomic_u64 *getRing() const { + return reinterpret_cast( + reinterpret_cast(this) + sizeof(StackDepot)); + } + + const atomic_u32 *getTab() const { + return reinterpret_cast( + reinterpret_cast(this) + sizeof(StackDepot) + + sizeof(atomic_u64) * RingSize); + } public: + void init(uptr RingSz, uptr TabSz) { + DCHECK(isPowerOfTwo(RingSz)); + DCHECK(isPowerOfTwo(TabSz)); + RingSize = RingSz; + RingMask = RingSz - 1; + TabMask = TabSz - 1; + } + + // Ensure that RingSize, RingMask and TabMask are set up in a way that + // all accesses are within range of BufSize. + bool isValid(uptr BufSize) const { + if (RingSize > UINTPTR_MAX / sizeof(atomic_u64)) + return false; + if (RingSize == 0 || !isPowerOfTwo(RingSize)) + return false; + uptr RingBytes = sizeof(atomic_u64) * RingSize; + if (RingMask + 1 != RingSize) + return false; + + if (TabMask == 0) + return false; + if ((TabMask - 1) > UINTPTR_MAX / sizeof(atomic_u32)) + return false; + uptr TabSize = TabMask + 1; + if (!isPowerOfTwo(TabSize)) + return false; + uptr TabBytes = sizeof(atomic_u32) * TabSize; + + // Subtract and detect underflow. + if (BufSize < sizeof(StackDepot)) + return false; + BufSize -= sizeof(StackDepot); + if (BufSize < TabBytes) + return false; + BufSize -= TabBytes; + if (BufSize < RingBytes) + return false; + return BufSize == RingBytes; + } + // Insert hash of the stack trace [Begin, End) into the stack depot, and // return the hash. u32 insert(uptr *Begin, uptr *End) { + auto *Tab = getTab(); + auto *Ring = getRing(); + MurMur2HashBuilder B; for (uptr *I = Begin; I != End; ++I) B.add(u32(*I) >> 2); @@ -112,6 +166,9 @@ public: // accessed via operator[] passing indexes between *RingPosPtr and // *RingPosPtr + *SizePtr. bool find(u32 Hash, uptr *RingPosPtr, uptr *SizePtr) const { + auto *Tab = getTab(); + auto *Ring = getRing(); + u32 Pos = Hash & TabMask; u32 RingPos = atomic_load_relaxed(&Tab[Pos]); if (RingPos >= RingSize) @@ -133,7 +190,8 @@ public: return B.get() == Hash; } - u64 operator[](uptr RingPos) const { + u64 at(uptr RingPos) const { + auto *Ring = getRing(); return atomic_load_relaxed(&Ring[RingPos & RingMask]); } diff --git a/compiler-rt/lib/scudo/standalone/tests/combined_test.cpp b/compiler-rt/lib/scudo/standalone/tests/combined_test.cpp index 13f5ac132837..3785e2261d84 100644 --- a/compiler-rt/lib/scudo/standalone/tests/combined_test.cpp +++ b/compiler-rt/lib/scudo/standalone/tests/combined_test.cpp @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// #include "memtag.h" +#include "stack_depot.h" #include "tests/scudo_unit_test.h" #include "allocator_config.h" @@ -870,8 +871,8 @@ SCUDO_TYPED_TEST(ScudoCombinedTest, ReallocateInPlaceStress) { SCUDO_TYPED_TEST(ScudoCombinedTest, RingBufferSize) { auto *Allocator = this->Allocator.get(); auto Size = Allocator->getRingBufferSize(); - if (Size > 0) - EXPECT_EQ(Allocator->getRingBufferAddress()[Size - 1], '\0'); + ASSERT_GT(Size, 0); + EXPECT_EQ(Allocator->getRingBufferAddress()[Size - 1], '\0'); } SCUDO_TYPED_TEST(ScudoCombinedTest, RingBufferAddress) { @@ -881,6 +882,39 @@ SCUDO_TYPED_TEST(ScudoCombinedTest, RingBufferAddress) { EXPECT_EQ(Addr, Allocator->getRingBufferAddress()); } +SCUDO_TYPED_TEST(ScudoCombinedTest, StackDepotSize) { + auto *Allocator = this->Allocator.get(); + auto Size = Allocator->getStackDepotSize(); + ASSERT_GT(Size, 0); + EXPECT_EQ(Allocator->getStackDepotAddress()[Size - 1], '\0'); +} + +SCUDO_TYPED_TEST(ScudoCombinedTest, StackDepotAddress) { + auto *Allocator = this->Allocator.get(); + auto *Addr = Allocator->getStackDepotAddress(); + EXPECT_NE(Addr, nullptr); + EXPECT_EQ(Addr, Allocator->getStackDepotAddress()); +} + +SCUDO_TYPED_TEST(ScudoCombinedTest, StackDepot) { + alignas(scudo::StackDepot) char Buf[sizeof(scudo::StackDepot) + + 1024 * sizeof(scudo::atomic_u64) + + 1024 * sizeof(scudo::atomic_u32)] = {}; + auto *Depot = reinterpret_cast(Buf); + Depot->init(1024, 1024); + ASSERT_TRUE(Depot->isValid(sizeof(Buf))); + ASSERT_FALSE(Depot->isValid(sizeof(Buf) - 1)); + scudo::uptr Stack[] = {1, 2, 3}; + scudo::u32 Elem = Depot->insert(&Stack[0], &Stack[3]); + scudo::uptr RingPosPtr = 0; + scudo::uptr SizePtr = 0; + ASSERT_TRUE(Depot->find(Elem, &RingPosPtr, &SizePtr)); + ASSERT_EQ(SizePtr, 3); + EXPECT_EQ(Depot->at(RingPosPtr), 1); + EXPECT_EQ(Depot->at(RingPosPtr + 1), 2); + EXPECT_EQ(Depot->at(RingPosPtr + 2), 3); +} + #if SCUDO_CAN_USE_PRIMARY64 #if SCUDO_TRUSTY diff --git a/compiler-rt/lib/scudo/standalone/wrappers_c_bionic.cpp b/compiler-rt/lib/scudo/standalone/wrappers_c_bionic.cpp index 21694c3f17fe..e9d8c1e8d3db 100644 --- a/compiler-rt/lib/scudo/standalone/wrappers_c_bionic.cpp +++ b/compiler-rt/lib/scudo/standalone/wrappers_c_bionic.cpp @@ -43,10 +43,9 @@ INTERFACE void __scudo_get_error_info( const char *stack_depot, size_t stack_depot_size, const char *region_info, const char *ring_buffer, size_t ring_buffer_size, const char *memory, const char *memory_tags, uintptr_t memory_addr, size_t memory_size) { - (void)(stack_depot_size); - Allocator.getErrorInfo(error_info, fault_addr, stack_depot, region_info, - ring_buffer, ring_buffer_size, memory, memory_tags, - memory_addr, memory_size); + Allocator.getErrorInfo(error_info, fault_addr, stack_depot, stack_depot_size, + region_info, ring_buffer, ring_buffer_size, memory, + memory_tags, memory_addr, memory_size); } INTERFACE const char *__scudo_get_stack_depot_addr() { @@ -54,7 +53,7 @@ INTERFACE const char *__scudo_get_stack_depot_addr() { } INTERFACE size_t __scudo_get_stack_depot_size() { - return sizeof(scudo::StackDepot); + return Allocator.getStackDepotSize(); } INTERFACE const char *__scudo_get_region_info_addr() { -- GitLab From c175157dc158d1e4ebdf60c6af75a5106c474780 Mon Sep 17 00:00:00 2001 From: Aart Bik <39774503+aartbik@users.noreply.github.com> Date: Mon, 5 Feb 2024 16:48:14 -0800 Subject: [PATCH 007/266] [mlir][sparse] fix windows build issue with hex literals (#80770) Fixes: https://github.com/llvm/llvm-project/issues/73828 --- .../mlir/Dialect/SparseTensor/IR/Enums.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/mlir/include/mlir/Dialect/SparseTensor/IR/Enums.h b/mlir/include/mlir/Dialect/SparseTensor/IR/Enums.h index 1f662e204230..86c52bfc651e 100644 --- a/mlir/include/mlir/Dialect/SparseTensor/IR/Enums.h +++ b/mlir/include/mlir/Dialect/SparseTensor/IR/Enums.h @@ -530,27 +530,27 @@ static_assert((isUniqueLT(LevelType::Dense) && /// constexpr uint64_t encodeDim(uint64_t i, uint64_t cf, uint64_t cm) { if (cf != 0) { - assert(cf <= 0xfffff && cm == 0 && i <= 0xfffff); - return (0x01ULL << 60) | (cf << 20) | i; + assert(cf <= 0xfffffu && cm == 0 && i <= 0xfffffu); + return (static_cast(0x01u) << 60) | (cf << 20) | i; } if (cm != 0) { - assert(cm <= 0xfffff && i <= 0xfffff); - return (0x02ULL << 60) | (cm << 20) | i; + assert(cm <= 0xfffffu && i <= 0xfffffu); + return (static_cast(0x02u) << 60) | (cm << 20) | i; } assert(i <= 0x0fffffffffffffffu); return i; } constexpr uint64_t encodeLvl(uint64_t i, uint64_t c, uint64_t ii) { if (c != 0) { - assert(c <= 0xfffff && ii <= 0xfffff && i <= 0xfffff); - return (0x03ULL << 60) | (c << 20) | (ii << 40) | i; + assert(c <= 0xfffffu && ii <= 0xfffffu && i <= 0xfffffu); + return (static_cast(0x03u) << 60) | (c << 20) | (ii << 40) | i; } assert(i <= 0x0fffffffffffffffu); return i; } -constexpr bool isEncodedFloor(uint64_t v) { return (v >> 60) == 0x01; } -constexpr bool isEncodedMod(uint64_t v) { return (v >> 60) == 0x02; } -constexpr bool isEncodedMul(uint64_t v) { return (v >> 60) == 0x03; } +constexpr bool isEncodedFloor(uint64_t v) { return (v >> 60) == 0x01u; } +constexpr bool isEncodedMod(uint64_t v) { return (v >> 60) == 0x02u; } +constexpr bool isEncodedMul(uint64_t v) { return (v >> 60) == 0x03u; } constexpr uint64_t decodeIndex(uint64_t v) { return v & 0xfffffu; } constexpr uint64_t decodeConst(uint64_t v) { return (v >> 20) & 0xfffffu; } constexpr uint64_t decodeMulc(uint64_t v) { return (v >> 20) & 0xfffffu; } -- GitLab From c3291253c3b5d1794492ccebe39b7c2c5f74c378 Mon Sep 17 00:00:00 2001 From: Florian Mayer Date: Mon, 5 Feb 2024 16:56:39 -0800 Subject: [PATCH 008/266] Revert "[scudo] [MTE] resize stack depot for allocation ring buffer" (#80777) Reverts llvm/llvm-project#74515 Broke build: https://lab.llvm.org/buildbot/#/builders/75/builds/42512 --- compiler-rt/lib/scudo/standalone/combined.h | 121 ++++-------------- .../standalone/fuzz/get_error_info_fuzzer.cpp | 14 +- compiler-rt/lib/scudo/standalone/platform.h | 10 ++ .../lib/scudo/standalone/stack_depot.h | 96 +++----------- .../scudo/standalone/tests/combined_test.cpp | 38 +----- .../scudo/standalone/wrappers_c_bionic.cpp | 9 +- 6 files changed, 69 insertions(+), 219 deletions(-) diff --git a/compiler-rt/lib/scudo/standalone/combined.h b/compiler-rt/lib/scudo/standalone/combined.h index fa64d12d9e19..62473d14d1f9 100644 --- a/compiler-rt/lib/scudo/standalone/combined.h +++ b/compiler-rt/lib/scudo/standalone/combined.h @@ -9,7 +9,6 @@ #ifndef SCUDO_COMBINED_H_ #define SCUDO_COMBINED_H_ -#include "atomic_helpers.h" #include "chunk.h" #include "common.h" #include "flags.h" @@ -283,7 +282,7 @@ public: return reinterpret_cast(addHeaderTag(reinterpret_cast(Ptr))); } - NOINLINE u32 collectStackTrace(UNUSED StackDepot *Depot) { + NOINLINE u32 collectStackTrace() { #ifdef HAVE_ANDROID_UNSAFE_FRAME_POINTER_CHASE // Discard collectStackTrace() frame and allocator function frame. constexpr uptr DiscardFrames = 2; @@ -291,7 +290,7 @@ public: uptr Size = android_unsafe_frame_pointer_chase(Stack, MaxTraceSize + DiscardFrames); Size = Min(Size, MaxTraceSize + DiscardFrames); - return Depot->insert(Stack + Min(DiscardFrames, Size), Stack + Size); + return Depot.insert(Stack + Min(DiscardFrames, Size), Stack + Size); #else return 0; #endif @@ -688,12 +687,12 @@ public: Quarantine.disable(); Primary.disable(); Secondary.disable(); - Depot->disable(); + Depot.disable(); } void enable() NO_THREAD_SAFETY_ANALYSIS { initThreadMaybe(); - Depot->enable(); + Depot.enable(); Secondary.enable(); Primary.enable(); Quarantine.enable(); @@ -916,14 +915,8 @@ public: Primary.Options.clear(OptionBit::AddLargeAllocationSlack); } - const char *getStackDepotAddress() { - initThreadMaybe(); - return reinterpret_cast(Depot); - } - - uptr getStackDepotSize() { - initThreadMaybe(); - return StackDepotSize; + const char *getStackDepotAddress() const { + return reinterpret_cast(&Depot); } const char *getRegionInfoArrayAddress() const { @@ -952,35 +945,21 @@ public: if (!Depot->find(Hash, &RingPos, &Size)) return; for (unsigned I = 0; I != Size && I != MaxTraceSize; ++I) - Trace[I] = static_cast(Depot->at(RingPos + I)); + Trace[I] = static_cast((*Depot)[RingPos + I]); } static void getErrorInfo(struct scudo_error_info *ErrorInfo, uintptr_t FaultAddr, const char *DepotPtr, - size_t DepotSize, const char *RegionInfoPtr, - const char *RingBufferPtr, size_t RingBufferSize, - const char *Memory, const char *MemoryTags, - uintptr_t MemoryAddr, size_t MemorySize) { - // N.B. we need to support corrupted data in any of the buffers here. We get - // this information from an external process (the crashing process) that - // should not be able to crash the crash dumper (crash_dump on Android). - // See also the get_error_info_fuzzer. + const char *RegionInfoPtr, const char *RingBufferPtr, + size_t RingBufferSize, const char *Memory, + const char *MemoryTags, uintptr_t MemoryAddr, + size_t MemorySize) { *ErrorInfo = {}; if (!allocatorSupportsMemoryTagging() || MemoryAddr + MemorySize < MemoryAddr) return; - const StackDepot *Depot = nullptr; - if (DepotPtr) { - // check for corrupted StackDepot. First we need to check whether we can - // read the metadata, then whether the metadata matches the size. - if (DepotSize < sizeof(*Depot)) - return; - Depot = reinterpret_cast(DepotPtr); - if (!Depot->isValid(DepotSize)) - return; - } - + auto *Depot = reinterpret_cast(DepotPtr); size_t NextErrorReport = 0; // Check for OOB in the current block and the two surrounding blocks. Beyond @@ -1046,9 +1025,7 @@ private: uptr GuardedAllocSlotSize = 0; #endif // GWP_ASAN_HOOKS - StackDepot *Depot = nullptr; - uptr StackDepotSize = 0; - MemMapT RawStackDepotMap; + StackDepot Depot; struct AllocationRingBuffer { struct Entry { @@ -1257,18 +1234,11 @@ private: storeEndMarker(RoundNewPtr, NewSize, BlockEnd); } - StackDepot *getDepotIfEnabled(const Options &Options) { - if (!UNLIKELY(Options.get(OptionBit::TrackAllocationStacks))) - return nullptr; - return Depot; - } - void storePrimaryAllocationStackMaybe(const Options &Options, void *Ptr) { - auto *Depot = getDepotIfEnabled(Options); - if (!Depot) + if (!UNLIKELY(Options.get(OptionBit::TrackAllocationStacks))) return; auto *Ptr32 = reinterpret_cast(Ptr); - Ptr32[MemTagAllocationTraceIndex] = collectStackTrace(Depot); + Ptr32[MemTagAllocationTraceIndex] = collectStackTrace(); Ptr32[MemTagAllocationTidIndex] = getThreadID(); } @@ -1298,10 +1268,10 @@ private: void storeSecondaryAllocationStackMaybe(const Options &Options, void *Ptr, uptr Size) { - auto *Depot = getDepotIfEnabled(Options); - if (!Depot) + if (!UNLIKELY(Options.get(OptionBit::TrackAllocationStacks))) return; - u32 Trace = collectStackTrace(Depot); + + u32 Trace = collectStackTrace(); u32 Tid = getThreadID(); auto *Ptr32 = reinterpret_cast(Ptr); @@ -1313,14 +1283,14 @@ private: void storeDeallocationStackMaybe(const Options &Options, void *Ptr, u8 PrevTag, uptr Size) { - auto *Depot = getDepotIfEnabled(Options); - if (!Depot) + if (!UNLIKELY(Options.get(OptionBit::TrackAllocationStacks))) return; + auto *Ptr32 = reinterpret_cast(Ptr); u32 AllocationTrace = Ptr32[MemTagAllocationTraceIndex]; u32 AllocationTid = Ptr32[MemTagAllocationTidIndex]; - u32 DeallocationTrace = collectStackTrace(Depot); + u32 DeallocationTrace = collectStackTrace(); u32 DeallocationTid = getThreadID(); storeRingBufferEntry(addFixedTag(untagPointer(Ptr), PrevTag), @@ -1399,10 +1369,8 @@ private: UntaggedFaultAddr < ChunkAddr ? BUFFER_UNDERFLOW : BUFFER_OVERFLOW; R->allocation_address = ChunkAddr; R->allocation_size = Header.SizeOrUnusedBytes; - if (Depot) { - collectTraceMaybe(Depot, R->allocation_trace, - Data[MemTagAllocationTraceIndex]); - } + collectTraceMaybe(Depot, R->allocation_trace, + Data[MemTagAllocationTraceIndex]); R->allocation_tid = Data[MemTagAllocationTidIndex]; return NextErrorReport == NumErrorReports; }; @@ -1425,7 +1393,7 @@ private: auto *RingBuffer = reinterpret_cast(RingBufferPtr); size_t RingBufferElements = ringBufferElementsFromBytes(RingBufferSize); - if (!RingBuffer || RingBufferElements == 0 || !Depot) + if (!RingBuffer || RingBufferElements == 0) return; uptr Pos = atomic_load_relaxed(&RingBuffer->Pos); @@ -1515,43 +1483,6 @@ private: return; u32 AllocationRingBufferSize = static_cast(getFlags()->allocation_ring_buffer_size); - - // We store alloc and free stacks for each entry. - constexpr u32 kStacksPerRingBufferEntry = 2; - constexpr u32 kMaxU32Pow2 = ~(UINT32_MAX >> 1); - static_assert(isPowerOfTwo(kMaxU32Pow2)); - constexpr u32 kFramesPerStack = 8; - static_assert(isPowerOfTwo(kFramesPerStack)); - - // We need StackDepot to be aligned to 8-bytes so the ring we store after - // is correctly assigned. - static_assert(sizeof(Depot) % alignof(atomic_u64) == 0); - - // Make sure the maximum sized StackDepot fits withint a uintptr_t to - // simplify the overflow checking. - static_assert(sizeof(Depot) + UINT32_MAX * sizeof(atomic_u64) * UINT32_MAX * - sizeof(atomic_u32) < - UINTPTR_MAX); - - if (AllocationRingBufferSize > kMaxU32Pow2 / kStacksPerRingBufferEntry) - return; - u32 TabSize = static_cast(roundUpPowerOfTwo(kStacksPerRingBufferEntry * - AllocationRingBufferSize)); - if (TabSize > UINT32_MAX / kFramesPerStack) - return; - u32 RingSize = static_cast(TabSize * kFramesPerStack); - DCHECK(isPowerOfTwo(RingSize)); - - StackDepotSize = sizeof(Depot) + sizeof(atomic_u64) * RingSize + - sizeof(atomic_u32) * TabSize; - MemMapT DepotMap; - DepotMap.map( - /*Addr=*/0U, roundUp(StackDepotSize, getPageSizeCached()), - "scudo:stack_depot"); - Depot = reinterpret_cast(DepotMap.getBase()); - Depot->init(RingSize, TabSize); - RawStackDepotMap = DepotMap; - MemMapT MemMap; MemMap.map( /*Addr=*/0U, @@ -1574,10 +1505,6 @@ private: RawRingBufferMap.getCapacity()); } RawRingBuffer = nullptr; - if (Depot) { - RawStackDepotMap.unmap(RawStackDepotMap.getBase(), - RawStackDepotMap.getCapacity()); - } } static constexpr size_t ringBufferSizeInBytes(u32 RingBufferElements) { diff --git a/compiler-rt/lib/scudo/standalone/fuzz/get_error_info_fuzzer.cpp b/compiler-rt/lib/scudo/standalone/fuzz/get_error_info_fuzzer.cpp index 2cef1c44fadc..5b01ebe11c09 100644 --- a/compiler-rt/lib/scudo/standalone/fuzz/get_error_info_fuzzer.cpp +++ b/compiler-rt/lib/scudo/standalone/fuzz/get_error_info_fuzzer.cpp @@ -9,7 +9,6 @@ #define SCUDO_FUZZ #include "allocator_config.h" #include "combined.h" -#include "common.h" #include @@ -32,6 +31,11 @@ extern "C" int LLVMFuzzerTestOneInput(uint8_t *Data, size_t Size) { std::string StackDepotBytes = FDP.ConsumeRandomLengthString(FDP.remaining_bytes()); + std::vector StackDepot(sizeof(scudo::StackDepot), 0); + for (size_t i = 0; i < StackDepotBytes.length() && i < StackDepot.size(); + ++i) { + StackDepot[i] = StackDepotBytes[i]; + } std::string RegionInfoBytes = FDP.ConsumeRandomLengthString(FDP.remaining_bytes()); @@ -44,9 +48,9 @@ extern "C" int LLVMFuzzerTestOneInput(uint8_t *Data, size_t Size) { std::string RingBufferBytes = FDP.ConsumeRemainingBytesAsString(); scudo_error_info ErrorInfo; - AllocatorT::getErrorInfo(&ErrorInfo, FaultAddr, StackDepotBytes.data(), - StackDepotBytes.size(), RegionInfo.data(), - RingBufferBytes.data(), RingBufferBytes.size(), - Memory, MemoryTags, MemoryAddr, MemorySize); + AllocatorT::getErrorInfo(&ErrorInfo, FaultAddr, StackDepot.data(), + RegionInfo.data(), RingBufferBytes.data(), + RingBufferBytes.size(), Memory, MemoryTags, + MemoryAddr, MemorySize); return 0; } diff --git a/compiler-rt/lib/scudo/standalone/platform.h b/compiler-rt/lib/scudo/standalone/platform.h index 5af1275e32d2..b71a86be7669 100644 --- a/compiler-rt/lib/scudo/standalone/platform.h +++ b/compiler-rt/lib/scudo/standalone/platform.h @@ -63,6 +63,16 @@ #define SCUDO_CAN_USE_MTE (SCUDO_LINUX || SCUDO_TRUSTY) #endif +// Use smaller table sizes for fuzzing in order to reduce input size. +// Trusty just has less available memory. +#ifndef SCUDO_SMALL_STACK_DEPOT +#if defined(SCUDO_FUZZ) || SCUDO_TRUSTY +#define SCUDO_SMALL_STACK_DEPOT 1 +#else +#define SCUDO_SMALL_STACK_DEPOT 0 +#endif +#endif + #ifndef SCUDO_ENABLE_HOOKS #define SCUDO_ENABLE_HOOKS 0 #endif diff --git a/compiler-rt/lib/scudo/standalone/stack_depot.h b/compiler-rt/lib/scudo/standalone/stack_depot.h index 8fe67ec0d54c..e887d1b43a7c 100644 --- a/compiler-rt/lib/scudo/standalone/stack_depot.h +++ b/compiler-rt/lib/scudo/standalone/stack_depot.h @@ -10,7 +10,6 @@ #define SCUDO_STACK_DEPOT_H_ #include "atomic_helpers.h" -#include "common.h" #include "mutex.h" namespace scudo { @@ -39,7 +38,7 @@ public: } }; -class alignas(16) StackDepot { +class StackDepot { HybridMutex RingEndMu; u32 RingEnd = 0; @@ -63,81 +62,28 @@ class alignas(16) StackDepot { // This is achieved by re-checking the hash of the stack trace before // returning the trace. - uptr RingSize = 0; - uptr RingMask = 0; - uptr TabMask = 0; - // This is immediately followed by RingSize atomic_u64 and - // (TabMask + 1) atomic_u32. - - atomic_u64 *getRing() { - return reinterpret_cast(reinterpret_cast(this) + - sizeof(StackDepot)); - } - - atomic_u32 *getTab() { - return reinterpret_cast(reinterpret_cast(this) + - sizeof(StackDepot) + - sizeof(atomic_u64) * RingSize); - } - - const atomic_u64 *getRing() const { - return reinterpret_cast( - reinterpret_cast(this) + sizeof(StackDepot)); - } - - const atomic_u32 *getTab() const { - return reinterpret_cast( - reinterpret_cast(this) + sizeof(StackDepot) + - sizeof(atomic_u64) * RingSize); - } +#if SCUDO_SMALL_STACK_DEPOT + static const uptr TabBits = 4; +#else + static const uptr TabBits = 16; +#endif + static const uptr TabSize = 1 << TabBits; + static const uptr TabMask = TabSize - 1; + atomic_u32 Tab[TabSize] = {}; + +#if SCUDO_SMALL_STACK_DEPOT + static const uptr RingBits = 4; +#else + static const uptr RingBits = 19; +#endif + static const uptr RingSize = 1 << RingBits; + static const uptr RingMask = RingSize - 1; + atomic_u64 Ring[RingSize] = {}; public: - void init(uptr RingSz, uptr TabSz) { - DCHECK(isPowerOfTwo(RingSz)); - DCHECK(isPowerOfTwo(TabSz)); - RingSize = RingSz; - RingMask = RingSz - 1; - TabMask = TabSz - 1; - } - - // Ensure that RingSize, RingMask and TabMask are set up in a way that - // all accesses are within range of BufSize. - bool isValid(uptr BufSize) const { - if (RingSize > UINTPTR_MAX / sizeof(atomic_u64)) - return false; - if (RingSize == 0 || !isPowerOfTwo(RingSize)) - return false; - uptr RingBytes = sizeof(atomic_u64) * RingSize; - if (RingMask + 1 != RingSize) - return false; - - if (TabMask == 0) - return false; - if ((TabMask - 1) > UINTPTR_MAX / sizeof(atomic_u32)) - return false; - uptr TabSize = TabMask + 1; - if (!isPowerOfTwo(TabSize)) - return false; - uptr TabBytes = sizeof(atomic_u32) * TabSize; - - // Subtract and detect underflow. - if (BufSize < sizeof(StackDepot)) - return false; - BufSize -= sizeof(StackDepot); - if (BufSize < TabBytes) - return false; - BufSize -= TabBytes; - if (BufSize < RingBytes) - return false; - return BufSize == RingBytes; - } - // Insert hash of the stack trace [Begin, End) into the stack depot, and // return the hash. u32 insert(uptr *Begin, uptr *End) { - auto *Tab = getTab(); - auto *Ring = getRing(); - MurMur2HashBuilder B; for (uptr *I = Begin; I != End; ++I) B.add(u32(*I) >> 2); @@ -166,9 +112,6 @@ public: // accessed via operator[] passing indexes between *RingPosPtr and // *RingPosPtr + *SizePtr. bool find(u32 Hash, uptr *RingPosPtr, uptr *SizePtr) const { - auto *Tab = getTab(); - auto *Ring = getRing(); - u32 Pos = Hash & TabMask; u32 RingPos = atomic_load_relaxed(&Tab[Pos]); if (RingPos >= RingSize) @@ -190,8 +133,7 @@ public: return B.get() == Hash; } - u64 at(uptr RingPos) const { - auto *Ring = getRing(); + u64 operator[](uptr RingPos) const { return atomic_load_relaxed(&Ring[RingPos & RingMask]); } diff --git a/compiler-rt/lib/scudo/standalone/tests/combined_test.cpp b/compiler-rt/lib/scudo/standalone/tests/combined_test.cpp index 3785e2261d84..13f5ac132837 100644 --- a/compiler-rt/lib/scudo/standalone/tests/combined_test.cpp +++ b/compiler-rt/lib/scudo/standalone/tests/combined_test.cpp @@ -7,7 +7,6 @@ //===----------------------------------------------------------------------===// #include "memtag.h" -#include "stack_depot.h" #include "tests/scudo_unit_test.h" #include "allocator_config.h" @@ -871,8 +870,8 @@ SCUDO_TYPED_TEST(ScudoCombinedTest, ReallocateInPlaceStress) { SCUDO_TYPED_TEST(ScudoCombinedTest, RingBufferSize) { auto *Allocator = this->Allocator.get(); auto Size = Allocator->getRingBufferSize(); - ASSERT_GT(Size, 0); - EXPECT_EQ(Allocator->getRingBufferAddress()[Size - 1], '\0'); + if (Size > 0) + EXPECT_EQ(Allocator->getRingBufferAddress()[Size - 1], '\0'); } SCUDO_TYPED_TEST(ScudoCombinedTest, RingBufferAddress) { @@ -882,39 +881,6 @@ SCUDO_TYPED_TEST(ScudoCombinedTest, RingBufferAddress) { EXPECT_EQ(Addr, Allocator->getRingBufferAddress()); } -SCUDO_TYPED_TEST(ScudoCombinedTest, StackDepotSize) { - auto *Allocator = this->Allocator.get(); - auto Size = Allocator->getStackDepotSize(); - ASSERT_GT(Size, 0); - EXPECT_EQ(Allocator->getStackDepotAddress()[Size - 1], '\0'); -} - -SCUDO_TYPED_TEST(ScudoCombinedTest, StackDepotAddress) { - auto *Allocator = this->Allocator.get(); - auto *Addr = Allocator->getStackDepotAddress(); - EXPECT_NE(Addr, nullptr); - EXPECT_EQ(Addr, Allocator->getStackDepotAddress()); -} - -SCUDO_TYPED_TEST(ScudoCombinedTest, StackDepot) { - alignas(scudo::StackDepot) char Buf[sizeof(scudo::StackDepot) + - 1024 * sizeof(scudo::atomic_u64) + - 1024 * sizeof(scudo::atomic_u32)] = {}; - auto *Depot = reinterpret_cast(Buf); - Depot->init(1024, 1024); - ASSERT_TRUE(Depot->isValid(sizeof(Buf))); - ASSERT_FALSE(Depot->isValid(sizeof(Buf) - 1)); - scudo::uptr Stack[] = {1, 2, 3}; - scudo::u32 Elem = Depot->insert(&Stack[0], &Stack[3]); - scudo::uptr RingPosPtr = 0; - scudo::uptr SizePtr = 0; - ASSERT_TRUE(Depot->find(Elem, &RingPosPtr, &SizePtr)); - ASSERT_EQ(SizePtr, 3); - EXPECT_EQ(Depot->at(RingPosPtr), 1); - EXPECT_EQ(Depot->at(RingPosPtr + 1), 2); - EXPECT_EQ(Depot->at(RingPosPtr + 2), 3); -} - #if SCUDO_CAN_USE_PRIMARY64 #if SCUDO_TRUSTY diff --git a/compiler-rt/lib/scudo/standalone/wrappers_c_bionic.cpp b/compiler-rt/lib/scudo/standalone/wrappers_c_bionic.cpp index e9d8c1e8d3db..21694c3f17fe 100644 --- a/compiler-rt/lib/scudo/standalone/wrappers_c_bionic.cpp +++ b/compiler-rt/lib/scudo/standalone/wrappers_c_bionic.cpp @@ -43,9 +43,10 @@ INTERFACE void __scudo_get_error_info( const char *stack_depot, size_t stack_depot_size, const char *region_info, const char *ring_buffer, size_t ring_buffer_size, const char *memory, const char *memory_tags, uintptr_t memory_addr, size_t memory_size) { - Allocator.getErrorInfo(error_info, fault_addr, stack_depot, stack_depot_size, - region_info, ring_buffer, ring_buffer_size, memory, - memory_tags, memory_addr, memory_size); + (void)(stack_depot_size); + Allocator.getErrorInfo(error_info, fault_addr, stack_depot, region_info, + ring_buffer, ring_buffer_size, memory, memory_tags, + memory_addr, memory_size); } INTERFACE const char *__scudo_get_stack_depot_addr() { @@ -53,7 +54,7 @@ INTERFACE const char *__scudo_get_stack_depot_addr() { } INTERFACE size_t __scudo_get_stack_depot_size() { - return Allocator.getStackDepotSize(); + return sizeof(scudo::StackDepot); } INTERFACE const char *__scudo_get_region_info_addr() { -- GitLab From 99ddd77ed9e12f55f8d4b66eec02154a0b3a6bf0 Mon Sep 17 00:00:00 2001 From: modiking Date: Mon, 5 Feb 2024 17:01:00 -0800 Subject: [PATCH 009/266] [LoopUnroll] Introduce PragmaUnrollFullMaxIterations as a hard cap on how many iterations we try to unroll (#78648) Fixes [PR77842](https://github.com/llvm/llvm-project/issues/77842) where UBSAN causes pragma full unroll to try and unroll INT_MAX times. This sets a cap to make sure we don't attempt this and crash the compiler. Testing: ninja check-all with new test --------- Co-authored-by: Nikita Popov --- llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp | 17 +++++- llvm/test/Transforms/LoopUnroll/pr77842.ll | 54 +++++++++++++++++++ 2 files changed, 69 insertions(+), 2 deletions(-) create mode 100644 llvm/test/Transforms/LoopUnroll/pr77842.ll diff --git a/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp b/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp index 7cfeb019af97..7dfe4aca6fe4 100644 --- a/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp +++ b/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp @@ -173,6 +173,10 @@ static cl::opt cl::desc("Default threshold (max size of unrolled " "loop), used in all but O3 optimizations")); +static cl::opt PragmaUnrollFullMaxIterations( + "pragma-unroll-full-max-iterations", cl::init(1'000'000), cl::Hidden, + cl::desc("Maximum allowed iterations to unroll under pragma unroll full.")); + /// A magic value for use with the Threshold parameter to indicate /// that the loop unroll should be performed regardless of how much /// code expansion would result. @@ -776,8 +780,17 @@ shouldPragmaUnroll(Loop *L, const PragmaInfo &PInfo, return PInfo.PragmaCount; } - if (PInfo.PragmaFullUnroll && TripCount != 0) + if (PInfo.PragmaFullUnroll && TripCount != 0) { + // Certain cases with UBSAN can cause trip count to be calculated as + // INT_MAX, Block full unrolling at a reasonable limit so that the compiler + // doesn't hang trying to unroll the loop. See PR77842 + if (TripCount > PragmaUnrollFullMaxIterations) { + LLVM_DEBUG(dbgs() << "Won't unroll; trip count is too large\n"); + return std::nullopt; + } + return TripCount; + } if (PInfo.PragmaEnableUnroll && !TripCount && MaxTripCount && MaxTripCount <= UP.MaxUpperBound) @@ -1282,7 +1295,7 @@ tryToUnrollLoop(Loop *L, DominatorTree &DT, LoopInfo *LI, ScalarEvolution &SE, } // Do not attempt partial/runtime unrolling in FullLoopUnrolling - if (OnlyFullUnroll && !(UP.Count >= MaxTripCount)) { + if (OnlyFullUnroll && (UP.Count < TripCount || UP.Count < MaxTripCount)) { LLVM_DEBUG( dbgs() << "Not attempting partial/runtime unroll in FullLoopUnroll.\n"); return LoopUnrollResult::Unmodified; diff --git a/llvm/test/Transforms/LoopUnroll/pr77842.ll b/llvm/test/Transforms/LoopUnroll/pr77842.ll new file mode 100644 index 000000000000..4c1de8f8fa49 --- /dev/null +++ b/llvm/test/Transforms/LoopUnroll/pr77842.ll @@ -0,0 +1,54 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -passes=loop-unroll-full -S %s | FileCheck %s + +; Validate that loop unroll full doesn't try to fully unroll values whose trip counts are too large. + +define void @foo(i64 %end) { +; CHECK-LABEL: define void @foo( +; CHECK-SAME: i64 [[END:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[LOOPHEADER:%.*]] +; CHECK: loopheader: +; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEW:%.*]], [[BACKEDGE:%.*]] ] +; CHECK-NEXT: [[EXIT:%.*]] = icmp eq i64 [[IV]], [[END]] +; CHECK-NEXT: br i1 [[EXIT]], label [[FOR_COND_CLEANUP_LOOPEXIT:%.*]], label [[CONT23:%.*]] +; CHECK: for.cond.cleanup.loopexit: +; CHECK-NEXT: ret void +; CHECK: cont23: +; CHECK-NEXT: [[EXITCOND241:%.*]] = icmp eq i64 [[IV]], 2147483647 +; CHECK-NEXT: br i1 [[EXITCOND241]], label [[HANDLER_ADD_OVERFLOW:%.*]], label [[BACKEDGE]] +; CHECK: handler.add_overflow: +; CHECK-NEXT: unreachable +; CHECK: backedge: +; CHECK-NEXT: [[IV_NEW]] = add i64 [[IV]], 1 +; CHECK-NEXT: br label [[LOOPHEADER]], !llvm.loop [[LOOP0:![0-9]+]] +; +entry: + br label %loopheader + +loopheader: + %iv = phi i64 [ 0, %entry ], [ %iv_new, %backedge ] + %exit = icmp eq i64 %iv, %end + br i1 %exit, label %for.cond.cleanup.loopexit, label %cont23 + +for.cond.cleanup.loopexit: + ret void + +cont23: + %exitcond241 = icmp eq i64 %iv, 2147483647 + br i1 %exitcond241, label %handler.add_overflow, label %backedge + +handler.add_overflow: + unreachable + +backedge: ; preds = %cont23 + %iv_new = add i64 %iv, 1 + br label %loopheader, !llvm.loop !0 +} + +!0 = distinct !{!0, !1} +!1 = !{!"llvm.loop.unroll.full"} +;. +; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]]} +; CHECK: [[META1]] = !{!"llvm.loop.unroll.full"} +;. -- GitLab From a71147dd28c6676fc46e4ec0a5d6e0b0823cced5 Mon Sep 17 00:00:00 2001 From: Congcong Cai Date: Tue, 6 Feb 2024 09:07:58 +0800 Subject: [PATCH 010/266] [WebAssembly] improve getRegForPromotedValue to avoid meanless value copy (#80469) When promoted value, it is meaningless to copy value from reg to another reg with the same type. This PR add additional check for this cases to reduce the code size. Fixes: #80053. --- .../WebAssembly/WebAssemblyFastISel.cpp | 4 ++ .../CodeGen/WebAssembly/suboptimal-compare.ll | 43 +++++++++++++++++++ 2 files changed, 47 insertions(+) create mode 100644 llvm/test/CodeGen/WebAssembly/suboptimal-compare.ll diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp index 7f0140a5e8c6..1c62290704fe 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp @@ -559,6 +559,8 @@ unsigned WebAssemblyFastISel::getRegForUnsignedValue(const Value *V) { Register VReg = getRegForValue(V); if (VReg == 0) return 0; + if (From == To) + return VReg; return zeroExtend(VReg, V, From, To); } @@ -568,6 +570,8 @@ unsigned WebAssemblyFastISel::getRegForSignedValue(const Value *V) { Register VReg = getRegForValue(V); if (VReg == 0) return 0; + if (From == To) + return VReg; return signExtend(VReg, V, From, To); } diff --git a/llvm/test/CodeGen/WebAssembly/suboptimal-compare.ll b/llvm/test/CodeGen/WebAssembly/suboptimal-compare.ll new file mode 100644 index 000000000000..fadeb397a884 --- /dev/null +++ b/llvm/test/CodeGen/WebAssembly/suboptimal-compare.ll @@ -0,0 +1,43 @@ +; RUN: llc < %s -fast-isel -O0 | FileCheck %s + +target triple = "wasm32-unknown-unknown" + +; CHECK-LABEL: gh_80053: # @gh_80053 +; CHECK-NEXT: .functype gh_80053 (i32) -> (i32) +; CHECK-NEXT: .local i32, i32, i32, i32, i32, i32 +; CHECK: i32.const 0 +; CHECK-NEXT: local.set 1 +; CHECK-NEXT: local.get 0 +; CHECK-NEXT: local.get 1 +; CHECK-NEXT: i32.eq +; CHECK-NEXT: local.set 2 +; CHECK-NEXT: i32.const 1 +; CHECK-NEXT: local.set 3 +; CHECK-NEXT: local.get 2 +; CHECK-NEXT: local.get 3 +; CHECK-NEXT: i32.and +; CHECK-NEXT: local.set 4 +; CHECK-NEXT: block +; CHECK-NEXT: local.get 4 +; CHECK-NEXT: i32.eqz +; CHECK-NEXT: br_if 0 # 0: down to label0 +; CHECK: i32.const 0 +; CHECK-NEXT: local.set 5 +; CHECK-NEXT: local.get 5 +; CHECK-NEXT: return +; CHECK-NEXT: .LBB0_2: # %BB03 +; CHECK-NEXT: end_block # label0: +; CHECK-NEXT: i32.const 1 +; CHECK-NEXT: local.set 6 +; CHECK-NEXT: local.get 6 +; CHECK-NEXT: return +; CHECK-NEXT: end_function +define i1 @gh_80053(ptr) { +BB01: + %eq = icmp eq ptr %0, null + br i1 %eq, label %BB02, label %BB03 +BB02: + ret i1 0 +BB03: + ret i1 1 +} -- GitLab From 06a728f3feab876f9195738b5774e82dadc0f3a7 Mon Sep 17 00:00:00 2001 From: Jinyang He Date: Tue, 6 Feb 2024 09:09:13 +0800 Subject: [PATCH 011/266] [lld][ELF] Support relax R_LARCH_ALIGN (#78692) Refer to commit 6611d58f5bbc ("Relax R_RISCV_ALIGN"), we can relax R_LARCH_ALIGN by same way. Reuse `SymbolAnchor`, `RISCVRelaxAux` and `initSymbolAnchors` to simplify codes. As `riscvFinalizeRelax` is an arch-specific function, put it override on `TargetInfo::finalizeRelax`, so that LoongArch can override it, too. The flow of relax R_LARCH_ALIGN is almost consistent with RISCV. The difference is that LoongArch only has 4-bytes NOP and all executable insn is 4-bytes aligned. So LoongArch not need rewrite NOP sequence. Alignment maxBytesEmit parameter is supported in psABI v2.30. --- lld/ELF/Arch/LoongArch.cpp | 156 ++++++++++++++++++++- lld/ELF/Arch/RISCV.cpp | 29 +--- lld/ELF/InputSection.cpp | 7 +- lld/ELF/InputSection.h | 24 +++- lld/ELF/Target.h | 3 + lld/ELF/Writer.cpp | 4 +- lld/test/ELF/loongarch-relax-align.s | 126 +++++++++++++++++ lld/test/ELF/loongarch-relax-emit-relocs.s | 49 +++++++ 8 files changed, 363 insertions(+), 35 deletions(-) create mode 100644 lld/test/ELF/loongarch-relax-align.s create mode 100644 lld/test/ELF/loongarch-relax-emit-relocs.s diff --git a/lld/ELF/Arch/LoongArch.cpp b/lld/ELF/Arch/LoongArch.cpp index ab2ec5b447d0..05fd38fb753f 100644 --- a/lld/ELF/Arch/LoongArch.cpp +++ b/lld/ELF/Arch/LoongArch.cpp @@ -36,6 +36,8 @@ public: bool usesOnlyLowPageBits(RelType type) const override; void relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const override; + bool relaxOnce(int pass) const override; + void finalizeRelax(int passes) const override; }; } // end anonymous namespace @@ -465,8 +467,9 @@ RelExpr LoongArch::getRelExpr(const RelType type, const Symbol &s, case R_LARCH_TLS_GD_HI20: return R_TLSGD_GOT; case R_LARCH_RELAX: - // LoongArch linker relaxation is not implemented yet. - return R_NONE; + return config->relax ? R_RELAX_HINT : R_NONE; + case R_LARCH_ALIGN: + return R_RELAX_HINT; // Other known relocs that are explicitly unimplemented: // @@ -659,6 +662,155 @@ void LoongArch::relocate(uint8_t *loc, const Relocation &rel, } } +static bool relax(InputSection &sec) { + const uint64_t secAddr = sec.getVA(); + const MutableArrayRef relocs = sec.relocs(); + auto &aux = *sec.relaxAux; + bool changed = false; + ArrayRef sa = ArrayRef(aux.anchors); + uint64_t delta = 0; + + std::fill_n(aux.relocTypes.get(), relocs.size(), R_LARCH_NONE); + aux.writes.clear(); + for (auto [i, r] : llvm::enumerate(relocs)) { + const uint64_t loc = secAddr + r.offset - delta; + uint32_t &cur = aux.relocDeltas[i], remove = 0; + switch (r.type) { + case R_LARCH_ALIGN: { + const uint64_t addend = + r.sym->isUndefined() ? Log2_64(r.addend) + 1 : r.addend; + const uint64_t allBytes = (1 << (addend & 0xff)) - 4; + const uint64_t align = 1 << (addend & 0xff); + const uint64_t maxBytes = addend >> 8; + const uint64_t off = loc & (align - 1); + const uint64_t curBytes = off == 0 ? 0 : align - off; + // All bytes beyond the alignment boundary should be removed. + // If emit bytes more than max bytes to emit, remove all. + if (maxBytes != 0 && curBytes > maxBytes) + remove = allBytes; + else + remove = allBytes - curBytes; + // If we can't satisfy this alignment, we've found a bad input. + if (LLVM_UNLIKELY(static_cast(remove) < 0)) { + errorOrWarn(getErrorLocation((const uint8_t *)loc) + + "insufficient padding bytes for " + lld::toString(r.type) + + ": " + Twine(allBytes) + " bytes available for " + + "requested alignment of " + Twine(align) + " bytes"); + remove = 0; + } + break; + } + } + + // For all anchors whose offsets are <= r.offset, they are preceded by + // the previous relocation whose `relocDeltas` value equals `delta`. + // Decrease their st_value and update their st_size. + for (; sa.size() && sa[0].offset <= r.offset; sa = sa.slice(1)) { + if (sa[0].end) + sa[0].d->size = sa[0].offset - delta - sa[0].d->value; + else + sa[0].d->value = sa[0].offset - delta; + } + delta += remove; + if (delta != cur) { + cur = delta; + changed = true; + } + } + + for (const SymbolAnchor &a : sa) { + if (a.end) + a.d->size = a.offset - delta - a.d->value; + else + a.d->value = a.offset - delta; + } + // Inform assignAddresses that the size has changed. + if (!isUInt<32>(delta)) + fatal("section size decrease is too large: " + Twine(delta)); + sec.bytesDropped = delta; + return changed; +} + +// When relaxing just R_LARCH_ALIGN, relocDeltas is usually changed only once in +// the absence of a linker script. For call and load/store R_LARCH_RELAX, code +// shrinkage may reduce displacement and make more relocations eligible for +// relaxation. Code shrinkage may increase displacement to a call/load/store +// target at a higher fixed address, invalidating an earlier relaxation. Any +// change in section sizes can have cascading effect and require another +// relaxation pass. +bool LoongArch::relaxOnce(int pass) const { + if (config->relocatable) + return false; + + if (pass == 0) + initSymbolAnchors(); + + SmallVector storage; + bool changed = false; + for (OutputSection *osec : outputSections) { + if (!(osec->flags & SHF_EXECINSTR)) + continue; + for (InputSection *sec : getInputSections(*osec, storage)) + changed |= relax(*sec); + } + return changed; +} + +void LoongArch::finalizeRelax(int passes) const { + log("relaxation passes: " + Twine(passes)); + SmallVector storage; + for (OutputSection *osec : outputSections) { + if (!(osec->flags & SHF_EXECINSTR)) + continue; + for (InputSection *sec : getInputSections(*osec, storage)) { + RelaxAux &aux = *sec->relaxAux; + if (!aux.relocDeltas) + continue; + + MutableArrayRef rels = sec->relocs(); + ArrayRef old = sec->content(); + size_t newSize = old.size() - aux.relocDeltas[rels.size() - 1]; + uint8_t *p = context().bAlloc.Allocate(newSize); + uint64_t offset = 0; + int64_t delta = 0; + sec->content_ = p; + sec->size = newSize; + sec->bytesDropped = 0; + + // Update section content: remove NOPs for R_LARCH_ALIGN and rewrite + // instructions for relaxed relocations. + for (size_t i = 0, e = rels.size(); i != e; ++i) { + uint32_t remove = aux.relocDeltas[i] - delta; + delta = aux.relocDeltas[i]; + if (remove == 0 && aux.relocTypes[i] == R_LARCH_NONE) + continue; + + // Copy from last location to the current relocated location. + const Relocation &r = rels[i]; + uint64_t size = r.offset - offset; + memcpy(p, old.data() + offset, size); + p += size; + offset = r.offset + remove; + } + memcpy(p, old.data() + offset, old.size() - offset); + + // Subtract the previous relocDeltas value from the relocation offset. + // For a pair of R_LARCH_XXX/R_LARCH_RELAX with the same offset, decrease + // their r_offset by the same delta. + delta = 0; + for (size_t i = 0, e = rels.size(); i != e;) { + uint64_t cur = rels[i].offset; + do { + rels[i].offset -= delta; + if (aux.relocTypes[i] != R_LARCH_NONE) + rels[i].type = aux.relocTypes[i]; + } while (++i != e && rels[i].offset == cur); + delta = aux.relocDeltas[i - 1]; + } + } + } +} + TargetInfo *elf::getLoongArchTargetInfo() { static LoongArch target; return ⌖ diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp index 8ce92b4badfb..5fcab4d39d43 100644 --- a/lld/ELF/Arch/RISCV.cpp +++ b/lld/ELF/Arch/RISCV.cpp @@ -45,6 +45,7 @@ public: uint64_t val) const override; void relocateAlloc(InputSectionBase &sec, uint8_t *buf) const override; bool relaxOnce(int pass) const override; + void finalizeRelax(int passes) const override; }; } // end anonymous namespace @@ -104,26 +105,6 @@ static uint32_t setLO12_S(uint32_t insn, uint32_t imm) { (extractBits(imm, 4, 0) << 7); } -namespace { -struct SymbolAnchor { - uint64_t offset; - Defined *d; - bool end; // true for the anchor of st_value+st_size -}; -} // namespace - -struct elf::RISCVRelaxAux { - // This records symbol start and end offsets which will be adjusted according - // to the nearest relocDeltas element. - SmallVector anchors; - // For relocations[i], the actual offset is - // r_offset - (i ? relocDeltas[i-1] : 0). - std::unique_ptr relocDeltas; - // For relocations[i], the actual type is relocTypes[i]. - std::unique_ptr relocTypes; - SmallVector writes; -}; - RISCV::RISCV() { copyRel = R_RISCV_COPY; pltRel = R_RISCV_JUMP_SLOT; @@ -695,13 +676,13 @@ void RISCV::relocateAlloc(InputSectionBase &sec, uint8_t *buf) const { } } -static void initSymbolAnchors() { +void elf::initSymbolAnchors() { SmallVector storage; for (OutputSection *osec : outputSections) { if (!(osec->flags & SHF_EXECINSTR)) continue; for (InputSection *sec : getInputSections(*osec, storage)) { - sec->relaxAux = make(); + sec->relaxAux = make(); if (sec->relocs().size()) { sec->relaxAux->relocDeltas = std::make_unique(sec->relocs().size()); @@ -948,7 +929,7 @@ bool RISCV::relaxOnce(int pass) const { return changed; } -void elf::riscvFinalizeRelax(int passes) { +void RISCV::finalizeRelax(int passes) const { llvm::TimeTraceScope timeScope("Finalize RISC-V relaxation"); log("relaxation passes: " + Twine(passes)); SmallVector storage; @@ -956,7 +937,7 @@ void elf::riscvFinalizeRelax(int passes) { if (!(osec->flags & SHF_EXECINSTR)) continue; for (InputSection *sec : getInputSections(*osec, storage)) { - RISCVRelaxAux &aux = *sec->relaxAux; + RelaxAux &aux = *sec->relaxAux; if (!aux.relocDeltas) continue; diff --git a/lld/ELF/InputSection.cpp b/lld/ELF/InputSection.cpp index 0e0b9783bd88..3d726b4c4b77 100644 --- a/lld/ELF/InputSection.cpp +++ b/lld/ELF/InputSection.cpp @@ -354,9 +354,10 @@ InputSectionBase *InputSection::getRelocatedSection() const { template void InputSection::copyRelocations(uint8_t *buf) { - if (config->relax && !config->relocatable && config->emachine == EM_RISCV) { - // On RISC-V, relaxation might change relocations: copy from internal ones - // that are updated by relaxation. + if (config->relax && !config->relocatable && + (config->emachine == EM_RISCV || config->emachine == EM_LOONGARCH)) { + // On LoongArch and RISC-V, relaxation might change relocations: copy + // from internal ones that are updated by relaxation. InputSectionBase *sec = getRelocatedSection(); copyRelocations(buf, llvm::make_range(sec->relocations.begin(), sec->relocations.end())); diff --git a/lld/ELF/InputSection.h b/lld/ELF/InputSection.h index bb9dff38ae02..b8af962877b4 100644 --- a/lld/ELF/InputSection.h +++ b/lld/ELF/InputSection.h @@ -102,7 +102,23 @@ protected: link(link), info(info) {} }; -struct RISCVRelaxAux; +struct SymbolAnchor { + uint64_t offset; + Defined *d; + bool end; // true for the anchor of st_value+st_size +}; + +struct RelaxAux { + // This records symbol start and end offsets which will be adjusted according + // to the nearest relocDeltas element. + SmallVector anchors; + // For relocations[i], the actual offset is + // r_offset - (i ? relocDeltas[i-1] : 0). + std::unique_ptr relocDeltas; + // For relocations[i], the actual type is relocTypes[i]. + std::unique_ptr relocTypes; + SmallVector writes; +}; // This corresponds to a section of an input file. class InputSectionBase : public SectionBase { @@ -227,9 +243,9 @@ public: // basic blocks. JumpInstrMod *jumpInstrMod = nullptr; - // Auxiliary information for RISC-V linker relaxation. RISC-V does not use - // jumpInstrMod. - RISCVRelaxAux *relaxAux; + // Auxiliary information for RISC-V and LoongArch linker relaxation. + // They do not use jumpInstrMod. + RelaxAux *relaxAux; // The compressed content size when `compressed` is true. size_t compressedSize; diff --git a/lld/ELF/Target.h b/lld/ELF/Target.h index ab6b6b9c013b..ed00e81c0e6c 100644 --- a/lld/ELF/Target.h +++ b/lld/ELF/Target.h @@ -95,6 +95,8 @@ public: // Do a linker relaxation pass and return true if we changed something. virtual bool relaxOnce(int pass) const { return false; } + // Do finalize relaxation after collecting relaxation infos. + virtual void finalizeRelax(int passes) const {} virtual void applyJumpInstrMod(uint8_t *loc, JumpModType type, JumpModType val) const {} @@ -236,6 +238,7 @@ void addArmSyntheticSectionMappingSymbol(Defined *); void sortArmMappingSymbols(); void convertArmInstructionstoBE8(InputSection *sec, uint8_t *buf); void createTaggedSymbols(const SmallVector &files); +void initSymbolAnchors(); LLVM_LIBRARY_VISIBILITY extern const TargetInfo *target; TargetInfo *getTarget(); diff --git a/lld/ELF/Writer.cpp b/lld/ELF/Writer.cpp index 501c10f35849..6df43a34be01 100644 --- a/lld/ELF/Writer.cpp +++ b/lld/ELF/Writer.cpp @@ -1752,8 +1752,8 @@ template void Writer::finalizeAddressDependentContent() { } } } - if (!config->relocatable && config->emachine == EM_RISCV) - riscvFinalizeRelax(pass); + if (!config->relocatable) + target->finalizeRelax(pass); if (config->relocatable) for (OutputSection *sec : outputSections) diff --git a/lld/test/ELF/loongarch-relax-align.s b/lld/test/ELF/loongarch-relax-align.s new file mode 100644 index 000000000000..ab61e15d5cac --- /dev/null +++ b/lld/test/ELF/loongarch-relax-align.s @@ -0,0 +1,126 @@ +# REQUIRES: loongarch + +# RUN: llvm-mc --filetype=obj --triple=loongarch32 --mattr=+relax %s -o %t.32.o +# RUN: llvm-mc --filetype=obj --triple=loongarch64 --mattr=+relax %s -o %t.64.o +# RUN: ld.lld --section-start=.text=0x10000 --section-start=.text2=0x20000 -e 0 %t.32.o -o %t.32 +# RUN: ld.lld --section-start=.text=0x10000 --section-start=.text2=0x20000 -e 0 %t.64.o -o %t.64 +# RUN: ld.lld --section-start=.text=0x10000 --section-start=.text2=0x20000 -e 0 %t.32.o --no-relax -o %t.32n +# RUN: ld.lld --section-start=.text=0x10000 --section-start=.text2=0x20000 -e 0 %t.64.o --no-relax -o %t.64n +# RUN: llvm-objdump -td --no-show-raw-insn %t.32 | FileCheck %s +# RUN: llvm-objdump -td --no-show-raw-insn %t.64 | FileCheck %s +# RUN: llvm-objdump -td --no-show-raw-insn %t.32n | FileCheck %s +# RUN: llvm-objdump -td --no-show-raw-insn %t.64n | FileCheck %s + +## Test the R_LARCH_ALIGN without symbol index. +# RUN: llvm-mc --filetype=obj --triple=loongarch64 --mattr=+relax %s -o %t.o64.o --defsym=old=1 +# RUN: ld.lld --section-start=.text=0x10000 --section-start=.text2=0x20000 -e 0 %t.o64.o -o %t.o64 +# RUN: ld.lld --section-start=.text=0x10000 --section-start=.text2=0x20000 -e 0 %t.o64.o --no-relax -o %t.o64n +# RUN: llvm-objdump -td --no-show-raw-insn %t.o64 | FileCheck %s +# RUN: llvm-objdump -td --no-show-raw-insn %t.o64n | FileCheck %s + +## -r keeps section contents unchanged. +# RUN: ld.lld -r %t.64.o -o %t.64.r +# RUN: llvm-objdump -dr --no-show-raw-insn %t.64.r | FileCheck %s --check-prefix=CHECKR + +# CHECK-DAG: {{0*}}10000 l .text {{0*}}44 .Ltext_start +# CHECK-DAG: {{0*}}10038 l .text {{0*}}0c .L1 +# CHECK-DAG: {{0*}}10040 l .text {{0*}}04 .L2 +# CHECK-DAG: {{0*}}20000 l .text2 {{0*}}14 .Ltext2_start + +# CHECK: <.Ltext_start>: +# CHECK-NEXT: break 1 +# CHECK-NEXT: break 2 +# CHECK-NEXT: nop +# CHECK-NEXT: nop +# CHECK-NEXT: break 3 +# CHECK-NEXT: break 4 +# CHECK-NEXT: nop +# CHECK-NEXT: nop +# CHECK-NEXT: pcalau12i $a0, 0 +# CHECK-NEXT: addi.{{[dw]}} $a0, $a0, 0 +# CHECK-NEXT: pcalau12i $a0, 0 +# CHECK-NEXT: addi.{{[dw]}} $a0, $a0, 56 +# CHECK-NEXT: pcalau12i $a0, 0 +# CHECK-NEXT: addi.{{[dw]}} $a0, $a0, 64 +# CHECK-EMPTY: +# CHECK-NEXT: <.L1>: +# CHECK-NEXT: nop +# CHECK-NEXT: nop +# CHECK-EMPTY: +# CHECK-NEXT: <.L2>: +# CHECK-NEXT: break 5 + +# CHECK: <.Ltext2_start>: +# CHECK-NEXT: pcalau12i $a0, 0 +# CHECK-NEXT: addi.{{[dw]}} $a0, $a0, 0 +# CHECK-NEXT: nop +# CHECK-NEXT: nop +# CHECK-NEXT: break 6 + +# CHECKR: <.Ltext2_start>: +# CHECKR-NEXT: pcalau12i $a0, 0 +# CHECKR-NEXT: {{0*}}00: R_LARCH_PCALA_HI20 .Ltext2_start +# CHECKR-NEXT: {{0*}}00: R_LARCH_RELAX *ABS* +# CHECKR-NEXT: addi.d $a0, $a0, 0 +# CHECKR-NEXT: {{0*}}04: R_LARCH_PCALA_LO12 .Ltext2_start +# CHECKR-NEXT: {{0*}}04: R_LARCH_RELAX *ABS* +# CHECKR-NEXT: nop +# CHECKR-NEXT: {{0*}}08: R_LARCH_ALIGN .Lalign_symbol+0x4 +# CHECKR-NEXT: nop +# CHECKR-NEXT: nop +# CHECKR-NEXT: break 6 + +.macro .fake_p2align_4 max=0 + .ifdef old + .if \max==0 + .reloc ., R_LARCH_ALIGN, 0xc + nop; nop; nop + .endif + .else + .reloc ., R_LARCH_ALIGN, .Lalign_symbol + 0x4 + (\max << 8) + nop; nop; nop + .endif +.endm + + .text +.Lalign_symbol: +.Ltext_start: + break 1 + break 2 +## +0x8: Emit 2 nops, delete 1 nop. + .fake_p2align_4 + + break 3 +## +0x14: Emit 3 nops > 8 bytes, not emit. + .fake_p2align_4 8 + + break 4 + .fake_p2align_4 8 +## +0x18: Emit 2 nops <= 8 bytes. + +## Compensate +.ifdef old + nop; nop +.endif + +## +0x20: Test symbol value and symbol size can be handled. + la.pcrel $a0, .Ltext_start + la.pcrel $a0, .L1 + la.pcrel $a0, .L2 + +## +0x38: Emit 2 nops, delete 1 nop. +.L1: + .fake_p2align_4 +.L2: + break 5 + .size .L1, . - .L1 + .size .L2, . - .L2 + .size .Ltext_start, . - .Ltext_start + +## Test another text section. + .section .text2,"ax",@progbits +.Ltext2_start: + la.pcrel $a0, .Ltext2_start + .fake_p2align_4 + break 6 + .size .Ltext2_start, . - .Ltext2_start diff --git a/lld/test/ELF/loongarch-relax-emit-relocs.s b/lld/test/ELF/loongarch-relax-emit-relocs.s new file mode 100644 index 000000000000..581fce8c95ca --- /dev/null +++ b/lld/test/ELF/loongarch-relax-emit-relocs.s @@ -0,0 +1,49 @@ +# REQUIRES: loongarch +## Test that we can handle --emit-relocs while relaxing. + +# RUN: llvm-mc --filetype=obj --triple=loongarch32 --mattr=+relax %s -o %t.32.o +# RUN: llvm-mc --filetype=obj --triple=loongarch64 --mattr=+relax %s -o %t.64.o +# RUN: ld.lld -Ttext=0x10000 --emit-relocs %t.32.o -o %t.32 +# RUN: ld.lld -Ttext=0x10000 --emit-relocs %t.64.o -o %t.64 +# RUN: llvm-objdump -dr %t.32 | FileCheck %s +# RUN: llvm-objdump -dr %t.64 | FileCheck %s + +## -r should keep original relocations. +# RUN: ld.lld -r %t.64.o -o %t.64.r +# RUN: llvm-objdump -dr %t.64.r | FileCheck %s --check-prefix=CHECKR + +## --no-relax should keep original relocations. +## TODO Due to R_LARCH_RELAX is not relaxed, it plays same as --relax now. +# RUN: ld.lld -Ttext=0x10000 --emit-relocs --no-relax %t.64.o -o %t.64.norelax +# RUN: llvm-objdump -dr %t.64.norelax | FileCheck %s + +# CHECK: 00010000 <_start>: +# CHECK-NEXT: pcalau12i $a0, 0 +# CHECK-NEXT: R_LARCH_PCALA_HI20 _start +# CHECK-NEXT: R_LARCH_RELAX *ABS* +# CHECK-NEXT: addi.{{[dw]}} $a0, $a0, 0 +# CHECK-NEXT: R_LARCH_PCALA_LO12 _start +# CHECK-NEXT: R_LARCH_RELAX *ABS* +# CHECK-NEXT: nop +# CHECK-NEXT: R_LARCH_ALIGN .Lla-relax-align0+0x4 +# CHECK-NEXT: nop +# CHECK-NEXT: ret + +# CHECKR: <_start>: +# CHECKR-NEXT: pcalau12i $a0, 0 +# CHECKR-NEXT: R_LARCH_PCALA_HI20 _start +# CHECKR-NEXT: R_LARCH_RELAX *ABS* +# CHECKR-NEXT: addi.d $a0, $a0, 0 +# CHECKR-NEXT: R_LARCH_PCALA_LO12 _start +# CHECKR-NEXT: R_LARCH_RELAX *ABS* +# CHECKR-NEXT: nop +# CHECKR-NEXT: R_LARCH_ALIGN .Lla-relax-align0+0x4 +# CHECKR-NEXT: nop +# CHECKR-NEXT: nop +# CHECKR-NEXT: ret + +.global _start +_start: + la.pcrel $a0, _start + .p2align 4 + ret -- GitLab From abe102b87204a8b5bb637b675ed58ee6695016af Mon Sep 17 00:00:00 2001 From: Enna1 Date: Tue, 6 Feb 2024 09:18:06 +0800 Subject: [PATCH 012/266] [Sanitizer][NFC] Replaces a few `InternalScopedString::AppendF` with `InternalScopedString::Append` (#80574) --- compiler-rt/lib/asan/asan_descriptions.cpp | 6 ++--- compiler-rt/lib/hwasan/hwasan_report.cpp | 22 +++++++++---------- .../lib/memprof/memprof_descriptions.cpp | 2 +- .../sanitizer_stacktrace_libcdep.cpp | 8 +++---- .../sanitizer_stacktrace_printer.cpp | 10 ++++----- 5 files changed, 24 insertions(+), 24 deletions(-) diff --git a/compiler-rt/lib/asan/asan_descriptions.cpp b/compiler-rt/lib/asan/asan_descriptions.cpp index ef6f3e0a096f..05a277cfa0a8 100644 --- a/compiler-rt/lib/asan/asan_descriptions.cpp +++ b/compiler-rt/lib/asan/asan_descriptions.cpp @@ -245,11 +245,11 @@ static void PrintAccessAndVarIntersection(const StackVarDescr &var, uptr addr, InternalScopedString str; str.AppendF(" [%zd, %zd)", var.beg, var_end); // Render variable name. - str.AppendF(" '"); + str.Append(" '"); for (uptr i = 0; i < var.name_len; ++i) { str.AppendF("%c", var.name_pos[i]); } - str.AppendF("'"); + str.Append("'"); if (var.line > 0) { str.AppendF(" (line %zd)", var.line); } @@ -260,7 +260,7 @@ static void PrintAccessAndVarIntersection(const StackVarDescr &var, uptr addr, str.AppendF("%s <== Memory access at offset %zd %s this variable%s\n", d.Location(), addr, pos_descr, d.Default()); } else { - str.AppendF("\n"); + str.Append("\n"); } Printf("%s", str.data()); } diff --git a/compiler-rt/lib/hwasan/hwasan_report.cpp b/compiler-rt/lib/hwasan/hwasan_report.cpp index 12a4fa47f215..c3d260d1a61f 100644 --- a/compiler-rt/lib/hwasan/hwasan_report.cpp +++ b/compiler-rt/lib/hwasan/hwasan_report.cpp @@ -388,7 +388,7 @@ static void PrintTagInfoAroundAddr(uptr addr, uptr num_rows, print_tag(s, row + i); s.Append(row + i == addr ? "]" : " "); } - s.AppendF("\n"); + s.Append("\n"); } } @@ -418,10 +418,10 @@ static void PrintTagsAroundAddr(uptr addr, GetTag get_tag, tag_t short_tag = get_short_tag(tag_addr); s.AppendF("%02x", short_tag); } else { - s.AppendF(".."); + s.Append(".."); } }); - s.AppendF( + s.Append( "See " "https://clang.llvm.org/docs/" "HardwareAssistedAddressSanitizerDesign.html#short-granules for a " @@ -947,16 +947,16 @@ TailOverwrittenReport::~TailOverwrittenReport() { InternalScopedString s; u8 *tail = tail_copy; - s.AppendF("Tail contains: "); - for (uptr i = 0; i < kShadowAlignment - tail_size; i++) s.AppendF(".. "); + s.Append("Tail contains: "); + for (uptr i = 0; i < kShadowAlignment - tail_size; i++) s.Append(".. "); for (uptr i = 0; i < tail_size; i++) s.AppendF("%02x ", tail[i]); - s.AppendF("\n"); - s.AppendF("Expected: "); - for (uptr i = 0; i < kShadowAlignment - tail_size; i++) s.AppendF(".. "); + s.Append("\n"); + s.Append("Expected: "); + for (uptr i = 0; i < kShadowAlignment - tail_size; i++) s.Append(".. "); for (uptr i = 0; i < tail_size; i++) s.AppendF("%02x ", actual_expected[i]); - s.AppendF("\n"); - s.AppendF(" "); - for (uptr i = 0; i < kShadowAlignment - tail_size; i++) s.AppendF(" "); + s.Append("\n"); + s.Append(" "); + for (uptr i = 0; i < kShadowAlignment - tail_size; i++) s.Append(" "); for (uptr i = 0; i < tail_size; i++) s.AppendF("%s ", actual_expected[i] != tail[i] ? "^^" : " "); diff --git a/compiler-rt/lib/memprof/memprof_descriptions.cpp b/compiler-rt/lib/memprof/memprof_descriptions.cpp index 48b74b6bc87f..4fbe2943e653 100644 --- a/compiler-rt/lib/memprof/memprof_descriptions.cpp +++ b/compiler-rt/lib/memprof/memprof_descriptions.cpp @@ -51,7 +51,7 @@ void DescribeThread(MemprofThreadContext *context) { InternalScopedString str; str.AppendF("Thread %s", MemprofThreadIdAndName(context).c_str()); if (context->parent_tid == kInvalidTid) { - str.AppendF(" created by unknown thread\n"); + str.Append(" created by unknown thread\n"); Printf("%s", str.data()); return; } diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace_libcdep.cpp b/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace_libcdep.cpp index 561eae9ab780..1a0e00d5d5af 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace_libcdep.cpp +++ b/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace_libcdep.cpp @@ -63,7 +63,7 @@ class StackTraceTextPrinter { if (dedup_frames_-- > 0) { if (dedup_token_->length()) - dedup_token_->AppendF("--"); + dedup_token_->Append("--"); if (stack->info.function) dedup_token_->Append(stack->info.function); } @@ -99,7 +99,7 @@ void StackTrace::PrintTo(InternalScopedString *output) const { output, &dedup_token); if (trace == nullptr || size == 0) { - output->AppendF(" \n\n"); + output->Append(" \n\n"); return; } @@ -111,7 +111,7 @@ void StackTrace::PrintTo(InternalScopedString *output) const { } // Always add a trailing empty line after stack trace. - output->AppendF("\n"); + output->Append("\n"); // Append deduplication token, if non-empty. if (dedup_token.length()) @@ -198,7 +198,7 @@ void __sanitizer_symbolize_pc(uptr pc, const char *fmt, char *out_buf, StackTraceTextPrinter printer(fmt, '\0', &output, nullptr); if (!printer.ProcessAddressFrames(pc)) { output.clear(); - output.AppendF(""); + output.Append(""); } CopyStringToBuffer(output, out_buf, out_buf_size); } diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace_printer.cpp b/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace_printer.cpp index 748d832ccc21..b23796fccf6e 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace_printer.cpp +++ b/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace_printer.cpp @@ -152,12 +152,12 @@ static void MaybeBuildIdToBuffer(const AddressInfo &info, bool PrefixSpace, InternalScopedString *buffer) { if (info.uuid_size) { if (PrefixSpace) - buffer->AppendF(" "); - buffer->AppendF("(BuildId: "); + buffer->Append(" "); + buffer->Append("(BuildId: "); for (uptr i = 0; i < info.uuid_size; ++i) { buffer->AppendF("%02x", info.uuid[i]); } - buffer->AppendF(")"); + buffer->Append(")"); } } @@ -249,7 +249,7 @@ void FormattedStackTracePrinter::RenderFrame(InternalScopedString *buffer, MaybeBuildIdToBuffer(*info, /*PrefixSpace=*/true, buffer); #endif } else { - buffer->AppendF("()"); + buffer->Append("()"); } break; case 'M': @@ -339,7 +339,7 @@ void StackTracePrinter::RenderSourceLocation(InternalScopedString *buffer, buffer->AppendF("%s(%d", StripPathPrefix(file, strip_path_prefix), line); if (column > 0) buffer->AppendF(",%d", column); - buffer->AppendF(")"); + buffer->Append(")"); return; } -- GitLab From c1c5b854adc9414ee3d8c55ddd07bdb4cc5b7171 Mon Sep 17 00:00:00 2001 From: Nilanjana Basu Date: Mon, 5 Feb 2024 17:23:58 -0800 Subject: [PATCH 013/266] [LV] Remove loop trip count threshold for deciding whether to interleave a loop (#67725) A set of microbenchmarks (https://github.com/llvm/llvm-test-suite/pull/26) showed that loop interleaving can be beneficial for loops with low trip count as well. Loop interleaving count computation is updated accordingly in prior patches while this patch removes the loop trip count threshold for interleaving. --- .../Transforms/Vectorize/LoopVectorize.cpp | 13 - .../LoopDistribute/basic-with-memchecks.ll | 2 + .../AArch64/deterministic-type-shrinkage.ll | 46 +- .../interleave_count_for_estimated_tc.ll | 5 +- .../AArch64/interleave_count_for_known_tc.ll | 5 +- .../AArch64/sve-inductions-unusual-types.ll | 85 +- .../LoopVectorize/SystemZ/zero_unroll.ll | 2 +- .../X86/imprecise-through-phis.ll | 96 +- .../LoopVectorize/X86/interleave_short_tc.ll | 9 +- .../X86/limit-vf-by-tripcount.ll | 67 +- .../LoopVectorize/X86/load-deref-pred.ll | 724 +++++-- .../LoopVectorize/X86/metadata-enable.ll | 1710 +++++++++-------- .../LoopVectorize/X86/strided_load_cost.ll | 202 +- .../LoopVectorize/X86/unroll-small-loops.ll | 49 +- .../X86/vect.omp.force.small-tc.ll | 59 +- .../X86/vectorization-remarks-loopid-dbg.ll | 2 +- .../X86/vectorization-remarks.ll | 2 +- .../PhaseOrdering/AArch64/quant_4x4.ll | 406 ++-- .../PhaseOrdering/X86/excessive-unrolling.ll | 178 +- 19 files changed, 2164 insertions(+), 1498 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp index 55466720aa11..1a7b301c35f2 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -267,11 +267,6 @@ static cl::opt EnableMaskedInterleavedMemAccesses( "enable-masked-interleaved-mem-accesses", cl::init(false), cl::Hidden, cl::desc("Enable vectorization on masked interleaved memory accesses in a loop")); -static cl::opt TinyTripCountInterleaveThreshold( - "tiny-trip-count-interleave-threshold", cl::init(128), cl::Hidden, - cl::desc("We don't interleave loops with a estimated constant trip count " - "below this number")); - static cl::opt ForceTargetNumScalarRegs( "force-target-num-scalar-regs", cl::init(0), cl::Hidden, cl::desc("A flag that overrides the target's number of scalar registers.")); @@ -5348,14 +5343,6 @@ LoopVectorizationCostModel::selectInterleaveCount(ElementCount VF, auto BestKnownTC = getSmallBestKnownTC(*PSE.getSE(), TheLoop); const bool HasReductions = !Legal->getReductionVars().empty(); - // Do not interleave loops with a relatively small known or estimated trip - // count. But we will interleave when InterleaveSmallLoopScalarReduction is - // enabled, and the code has scalar reductions(HasReductions && VF = 1), - // because with the above conditions interleaving can expose ILP and break - // cross iteration dependences for reductions. - if (BestKnownTC && (*BestKnownTC < TinyTripCountInterleaveThreshold) && - !(InterleaveSmallLoopScalarReduction && HasReductions && VF.isScalar())) - return 1; // If we did not calculate the cost for VF (because the user selected the VF) // then we calculate the cost of VF here. diff --git a/llvm/test/Transforms/LoopDistribute/basic-with-memchecks.ll b/llvm/test/Transforms/LoopDistribute/basic-with-memchecks.ll index d1cff14c3f4b..27ca1a7541db 100644 --- a/llvm/test/Transforms/LoopDistribute/basic-with-memchecks.ll +++ b/llvm/test/Transforms/LoopDistribute/basic-with-memchecks.ll @@ -79,6 +79,8 @@ entry: ; VECTORIZE: mul <4 x i32> +; VECTORIZE: mul <4 x i32> +; VECTORIZE-NOT: mul <4 x i32> for.body: ; preds = %for.body, %entry %ind = phi i64 [ 0, %entry ], [ %add, %for.body ] diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/deterministic-type-shrinkage.ll b/llvm/test/Transforms/LoopVectorize/AArch64/deterministic-type-shrinkage.ll index 03f055413583..9a7b9f570cf7 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/deterministic-type-shrinkage.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/deterministic-type-shrinkage.ll @@ -326,34 +326,40 @@ define void @trunc_invariant_sdiv_result(i32 %a, i32 %b, ptr noalias %src, ptr % ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[INDEX]] +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[TMP3]], i64 16 ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i8>, ptr [[TMP3]], align 1 -; CHECK-NEXT: [[TMP4:%.*]] = zext <16 x i8> [[WIDE_LOAD]] to <16 x i16> -; CHECK-NEXT: [[TMP5:%.*]] = mul <16 x i16> [[TMP2]], [[TMP4]] -; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i16, ptr [[DST]], i64 [[INDEX]] -; CHECK-NEXT: store <16 x i16> [[TMP5]], ptr [[TMP6]], align 2 -; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 -; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], 96 -; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]] +; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <16 x i8>, ptr [[TMP4]], align 1 +; CHECK-NEXT: [[TMP5:%.*]] = zext <16 x i8> [[WIDE_LOAD]] to <16 x i16> +; CHECK-NEXT: [[TMP6:%.*]] = zext <16 x i8> [[WIDE_LOAD1]] to <16 x i16> +; CHECK-NEXT: [[TMP7:%.*]] = mul <16 x i16> [[TMP2]], [[TMP5]] +; CHECK-NEXT: [[TMP8:%.*]] = mul <16 x i16> [[TMP2]], [[TMP6]] +; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i16, ptr [[DST]], i64 [[INDEX]] +; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i8, ptr [[TMP9]], i64 32 +; CHECK-NEXT: store <16 x i16> [[TMP7]], ptr [[TMP9]], align 2 +; CHECK-NEXT: store <16 x i16> [[TMP8]], ptr [[TMP10]], align 2 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 32 +; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], 96 +; CHECK-NEXT: br i1 [[TMP11]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]] ; CHECK: middle.block: ; CHECK-NEXT: br i1 false, label [[EXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]] ; CHECK: vec.epilog.iter.check: ; CHECK-NEXT: br i1 false, label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]] ; CHECK: vec.epilog.ph: -; CHECK-NEXT: [[TMP8:%.*]] = trunc i32 [[INVAR_DIV]] to i16 -; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i16> poison, i16 [[TMP8]], i64 0 -; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <4 x i16> [[TMP9]], <4 x i16> poison, <4 x i32> zeroinitializer +; CHECK-NEXT: [[TMP12:%.*]] = trunc i32 [[INVAR_DIV]] to i16 +; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i16> poison, i16 [[TMP12]], i64 0 +; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x i16> [[TMP13]], <4 x i16> poison, <4 x i32> zeroinitializer ; CHECK-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]] ; CHECK: vec.epilog.vector.body: -; CHECK-NEXT: [[INDEX3:%.*]] = phi i64 [ 96, [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT5:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ] -; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[INDEX3]] -; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i8>, ptr [[TMP11]], align 1 -; CHECK-NEXT: [[TMP12:%.*]] = zext <4 x i8> [[WIDE_LOAD4]] to <4 x i16> -; CHECK-NEXT: [[TMP13:%.*]] = mul <4 x i16> [[TMP10]], [[TMP12]] -; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i16, ptr [[DST]], i64 [[INDEX3]] -; CHECK-NEXT: store <4 x i16> [[TMP13]], ptr [[TMP14]], align 2 -; CHECK-NEXT: [[INDEX_NEXT5]] = add nuw i64 [[INDEX3]], 4 -; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i64 [[INDEX_NEXT5]], 100 -; CHECK-NEXT: br i1 [[TMP15]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]] +; CHECK-NEXT: [[INDEX4:%.*]] = phi i64 [ 96, [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT6:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ] +; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[INDEX4]] +; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i8>, ptr [[TMP15]], align 1 +; CHECK-NEXT: [[TMP16:%.*]] = zext <4 x i8> [[WIDE_LOAD5]] to <4 x i16> +; CHECK-NEXT: [[TMP17:%.*]] = mul <4 x i16> [[TMP14]], [[TMP16]] +; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i16, ptr [[DST]], i64 [[INDEX4]] +; CHECK-NEXT: store <4 x i16> [[TMP17]], ptr [[TMP18]], align 2 +; CHECK-NEXT: [[INDEX_NEXT6]] = add nuw i64 [[INDEX4]], 4 +; CHECK-NEXT: [[TMP19:%.*]] = icmp eq i64 [[INDEX_NEXT6]], 100 +; CHECK-NEXT: br i1 [[TMP19]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]] ; CHECK: vec.epilog.middle.block: ; CHECK-NEXT: br i1 true, label [[EXIT]], label [[VEC_EPILOG_SCALAR_PH]] ; CHECK: vec.epilog.scalar.ph: diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/interleave_count_for_estimated_tc.ll b/llvm/test/Transforms/LoopVectorize/AArch64/interleave_count_for_estimated_tc.ll index 691c0fc8facc..95cbf121377f 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/interleave_count_for_estimated_tc.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/interleave_count_for_estimated_tc.ll @@ -1,6 +1,5 @@ -; RUN: opt < %s -tiny-trip-count-interleave-threshold=16 -force-target-max-vector-interleave=8 -p loop-vectorize -S -pass-remarks=loop-vectorize -disable-output 2>&1 | FileCheck %s -; RUN: opt < %s -tiny-trip-count-interleave-threshold=16 -force-target-max-vector-interleave=8 -p loop-vectorize -S 2>&1 | FileCheck %s -check-prefix=CHECK-IR -; TODO: remove -tiny-trip-count-interleave-threshold once the interleave threshold is removed +; RUN: opt < %s -force-target-max-vector-interleave=8 -p loop-vectorize -S -pass-remarks=loop-vectorize -disable-output 2>&1 | FileCheck %s +; RUN: opt < %s -force-target-max-vector-interleave=8 -p loop-vectorize -S 2>&1 | FileCheck %s -check-prefix=CHECK-IR target triple = "aarch64-linux-gnu" diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/interleave_count_for_known_tc.ll b/llvm/test/Transforms/LoopVectorize/AArch64/interleave_count_for_known_tc.ll index 6ea0229ab8ea..a3b45f7b5ca5 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/interleave_count_for_known_tc.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/interleave_count_for_known_tc.ll @@ -1,6 +1,5 @@ -; RUN: opt < %s -tiny-trip-count-interleave-threshold=16 -force-target-max-vector-interleave=8 -p loop-vectorize -S -pass-remarks=loop-vectorize -disable-output 2>&1 | FileCheck %s -; RUN: opt < %s -tiny-trip-count-interleave-threshold=16 -force-target-max-vector-interleave=8 -p loop-vectorize -S 2>&1 | FileCheck %s -check-prefix=CHECK-IR -; TODO: remove -tiny-trip-count-interleave-threshold once the interleave threshold is removed +; RUN: opt < %s -force-target-max-vector-interleave=8 -p loop-vectorize -S -pass-remarks=loop-vectorize -disable-output 2>&1 | FileCheck %s +; RUN: opt < %s -force-target-max-vector-interleave=8 -p loop-vectorize -S 2>&1 | FileCheck %s -check-prefix=CHECK-IR target triple = "aarch64-linux-gnu" diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions-unusual-types.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions-unusual-types.ll index 0fe8fa3f4154..3217f508f0ad 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions-unusual-types.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions-unusual-types.ll @@ -12,25 +12,38 @@ define void @induction_i7(ptr %dst) #0 { ; CHECK-LABEL: @induction_i7( ; CHECK: vector.ph: ; CHECK: %ind.end = trunc i64 %n.vec to i7 -; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64() -; CHECK-NEXT: [[TMP16:%.*]] = mul i64 [[TMP15]], 2 -; CHECK-NEXT: [[TMP4:%.*]] = call @llvm.experimental.stepvector.nxv2i8() -; CHECK: [[TMP5:%.*]] = trunc [[TMP4]] to -; CHECK-NEXT: [[TMP6:%.*]] = add [[TMP5]], zeroinitializer -; CHECK-NEXT: [[TMP7:%.*]] = mul [[TMP6]], shufflevector ( insertelement ( poison, i7 1, i64 0), poison, zeroinitializer) -; CHECK-NEXT: [[INDUCTION:%.*]] = add zeroinitializer, [[TMP7]] +; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64() +; CHECK-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 4 +; CHECK-NEXT: [[TMP6:%.*]] = call @llvm.experimental.stepvector.nxv2i8() +; CHECK-NEXT: [[TMP7:%.*]] = trunc [[TMP6]] to +; CHECK-NEXT: [[TMP8:%.*]] = add [[TMP7]], zeroinitializer +; CHECK-NEXT: [[TMP9:%.*]] = mul [[TMP8]], shufflevector ( insertelement ( poison, i7 1, i64 0), poison, zeroinitializer) +; CHECK-NEXT: [[INDUCTION:%.*]] = add zeroinitializer, [[TMP9]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %vector.ph ], [ [[INDEX_NEXT:%.*]], %vector.body ] ; CHECK-NEXT: [[VEC_IND:%.*]] = phi [ [[INDUCTION]], %vector.ph ], [ [[VEC_IND_NEXT:%.*]], %vector.body ] -; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[INDEX]], 0 -; CHECK-NEXT: [[TMP11:%.*]] = add [[VEC_IND]], zeroinitializer -; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i64, ptr [[DST:%.*]], i64 [[TMP10]] -; CHECK-NEXT: [[EXT:%.+]] = zext [[TMP11]] to -; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i64, ptr [[TMP12]], i32 0 -; CHECK-NEXT: store [[EXT]], ptr [[TMP13]], align 8 -; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP16]] -; CHECK-NEXT: [[VEC_IND_NEXT]] = add [[VEC_IND]], -; +; CHECK-NEXT: [[STEP_ADD:%.*]] = add [[VEC_IND]], [[DOTSPLAT:%.*]] +; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[INDEX]], 0 +; CHECK-NEXT: [[TMP14:%.*]] = call i64 @llvm.vscale.i64() +; CHECK-NEXT: [[TMP15:%.*]] = mul i64 [[TMP14]], 2 +; CHECK-NEXT: [[TMP16:%.*]] = add i64 [[TMP15]], 0 +; CHECK-NEXT: [[TMP17:%.*]] = mul i64 [[TMP16]], 1 +; CHECK-NEXT: [[TMP18:%.*]] = add i64 [[INDEX]], [[TMP17]] +; CHECK-NEXT: [[TMP19:%.*]] = add [[VEC_IND]], zeroinitializer +; CHECK-NEXT: [[TMP20:%.*]] = add [[STEP_ADD]], zeroinitializer +; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i64, ptr [[DST:%.*]], i64 [[TMP13]] +; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i64, ptr [[DST:%.*]], i64 [[TMP18]] +; CHECK-NEXT: [[TMP23:%.*]] = zext [[TMP19]] to +; CHECK-NEXT: [[TMP24:%.*]] = zext [[TMP20]] to +; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i64, ptr [[TMP21]], i32 0 +; CHECK-NEXT: [[TMP26:%.*]] = call i64 @llvm.vscale.i64() +; CHECK-NEXT: [[TMP27:%.*]] = mul i64 [[TMP26]], 2 +; CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds i64, ptr [[TMP21]], i64 [[TMP27]] +; CHECK-NEXT: store [[TMP23]], ptr [[TMP25]], align 8 +; CHECK-NEXT: store [[TMP24]], ptr [[TMP28]], align 8 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP5]] +; CHECK-NEXT: [[VEC_IND_NEXT]] = add [[STEP_ADD]], [[DOTSPLAT]] + entry: br label %for.body @@ -59,24 +72,34 @@ define void @induction_i3_zext(ptr %dst) #0 { ; CHECK-LABEL: @induction_i3_zext( ; CHECK: vector.ph: ; CHECK: %ind.end = trunc i64 %n.vec to i3 -; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64() -; CHECK-NEXT: [[TMP16:%.*]] = mul i64 [[TMP15]], 2 -; CHECK: [[TMP4:%.*]] = call @llvm.experimental.stepvector.nxv2i8() -; CHECK: [[TMP5:%.*]] = trunc [[TMP4]] to -; CHECK-NEXT: [[TMP6:%.*]] = add [[TMP5]], zeroinitializer -; CHECK-NEXT: [[TMP7:%.*]] = mul [[TMP6]], shufflevector ( insertelement ( poison, i3 1, i64 0), poison, zeroinitializer) -; CHECK-NEXT: [[INDUCTION:%.*]] = add zeroinitializer, [[TMP7]] +; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64() +; CHECK-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 4 +; CHECK-NEXT: [[TMP6:%.*]] = call @llvm.experimental.stepvector.nxv2i8() +; CHECK-NEXT: [[TMP7:%.*]] = trunc [[TMP6]] to +; CHECK-NEXT: [[TMP8:%.*]] = add [[TMP7]], zeroinitializer +; CHECK-NEXT: [[TMP9:%.*]] = mul [[TMP8]], shufflevector ( insertelement ( poison, i3 1, i64 0), poison, zeroinitializer) ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %vector.ph ], [ [[INDEX_NEXT:%.*]], %vector.body ] ; CHECK-NEXT: [[VEC_IND:%.*]] = phi [ [[INDUCTION]], %vector.ph ], [ [[VEC_IND_NEXT:%.*]], %vector.body ] -; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[INDEX]], 0 -; CHECK-NEXT: [[TMP10:%.*]] = zext [[VEC_IND]] to -; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i64, ptr [[DST:%.*]], i64 [[TMP9]] -; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i64, ptr [[TMP12]], i32 0 -; CHECK-NEXT: store [[TMP10]], ptr [[TMP13]], align 8 -; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP16]] -; CHECK-NEXT: [[VEC_IND_NEXT]] = add [[VEC_IND]], -; +; CHECK-NEXT: [[STEP_ADD:%.*]] = add [[VEC_IND]], [[DOTSPLAT]] +; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[INDEX]], 0 +; CHECK-NEXT: [[TMP14:%.*]] = call i64 @llvm.vscale.i64() +; CHECK-NEXT: [[TMP15:%.*]] = mul i64 [[TMP14]], 2 +; CHECK-NEXT: [[TMP16:%.*]] = add i64 [[TMP15]], 0 +; CHECK-NEXT: [[TMP17:%.*]] = mul i64 [[TMP16]], 1 +; CHECK-NEXT: [[TMP18:%.*]] = add i64 [[INDEX]], [[TMP17]] +; CHECK-NEXT: [[TMP19:%.*]] = zext [[VEC_IND]] to +; CHECK-NEXT: [[TMP20:%.*]] = zext [[STEP_ADD]] to +; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[TMP13]] +; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[TMP18]] +; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds i64, ptr [[TMP21]], i32 0 +; CHECK-NEXT: [[TMP24:%.*]] = call i64 @llvm.vscale.i64() +; CHECK-NEXT: [[TMP25:%.*]] = mul i64 [[TMP24]], 2 +; CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds i64, ptr [[TMP21]], i64 [[TMP25]] +; CHECK-NEXT: store [[TMP19]], ptr [[TMP23]], align 8 +; CHECK-NEXT: store [[TMP20]], ptr [[TMP26]], align 8 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP5]] +; CHECK-NEXT: [[VEC_IND_NEXT]] = add [[STEP_ADD]], [[DOTSPLAT]] entry: br label %for.body diff --git a/llvm/test/Transforms/LoopVectorize/SystemZ/zero_unroll.ll b/llvm/test/Transforms/LoopVectorize/SystemZ/zero_unroll.ll index d469178fec0e..d8535d510ca0 100644 --- a/llvm/test/Transforms/LoopVectorize/SystemZ/zero_unroll.ll +++ b/llvm/test/Transforms/LoopVectorize/SystemZ/zero_unroll.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -passes=loop-vectorize -mtriple=s390x-linux-gnu -tiny-trip-count-interleave-threshold=4 -vectorizer-min-trip-count=8 < %s | FileCheck %s +; RUN: opt -S -passes=loop-vectorize -mtriple=s390x-linux-gnu -vectorizer-min-trip-count=8 < %s | FileCheck %s define i32 @main(i32 %arg, ptr nocapture readnone %arg1) #0 { ;CHECK: vector.body: diff --git a/llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll b/llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll index fd826ce454ed..87f525fbce17 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll @@ -73,23 +73,33 @@ define double @sumIfVector(ptr nocapture readonly %arr) { ; SSE: vector.body: ; SSE-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; SSE-NEXT: [[VEC_PHI:%.*]] = phi <2 x double> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PREDPHI:%.*]], [[VECTOR_BODY]] ] +; SSE-NEXT: [[VEC_PHI1:%.*]] = phi <2 x double> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PREDPHI3:%.*]], [[VECTOR_BODY]] ] ; SSE-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 0 -; SSE-NEXT: [[TMP1:%.*]] = getelementptr double, ptr [[ARR:%.*]], i32 [[TMP0]] -; SSE-NEXT: [[TMP2:%.*]] = getelementptr double, ptr [[TMP1]], i32 0 -; SSE-NEXT: [[WIDE_LOAD:%.*]] = load <2 x double>, ptr [[TMP2]], align 8 -; SSE-NEXT: [[TMP3:%.*]] = fcmp fast une <2 x double> [[WIDE_LOAD]], -; SSE-NEXT: [[TMP5:%.*]] = xor <2 x i1> [[TMP3]], -; SSE-NEXT: [[TMP4:%.*]] = fadd fast <2 x double> [[VEC_PHI]], [[WIDE_LOAD]] -; SSE-NEXT: [[PREDPHI]] = select <2 x i1> [[TMP3]], <2 x double> [[TMP4]], <2 x double> [[VEC_PHI]] -; SSE-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2 -; SSE-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], 32 -; SSE-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; SSE-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 2 +; SSE-NEXT: [[TMP2:%.*]] = getelementptr double, ptr [[ARR:%.*]], i32 [[TMP0]] +; SSE-NEXT: [[TMP3:%.*]] = getelementptr double, ptr [[ARR]], i32 [[TMP1]] +; SSE-NEXT: [[TMP4:%.*]] = getelementptr double, ptr [[TMP2]], i32 0 +; SSE-NEXT: [[TMP5:%.*]] = getelementptr double, ptr [[TMP2]], i32 2 +; SSE-NEXT: [[WIDE_LOAD:%.*]] = load <2 x double>, ptr [[TMP4]], align 8 +; SSE-NEXT: [[WIDE_LOAD2:%.*]] = load <2 x double>, ptr [[TMP5]], align 8 +; SSE-NEXT: [[TMP6:%.*]] = fcmp fast une <2 x double> [[WIDE_LOAD]], +; SSE-NEXT: [[TMP7:%.*]] = fcmp fast une <2 x double> [[WIDE_LOAD2]], +; SSE-NEXT: [[TMP8:%.*]] = xor <2 x i1> [[TMP6]], +; SSE-NEXT: [[TMP9:%.*]] = xor <2 x i1> [[TMP7]], +; SSE-NEXT: [[TMP10:%.*]] = fadd fast <2 x double> [[VEC_PHI]], [[WIDE_LOAD]] +; SSE-NEXT: [[TMP11:%.*]] = fadd fast <2 x double> [[VEC_PHI1]], [[WIDE_LOAD2]] +; SSE-NEXT: [[PREDPHI]] = select <2 x i1> [[TMP6]], <2 x double> [[TMP10]], <2 x double> [[VEC_PHI]] +; SSE-NEXT: [[PREDPHI3]] = select <2 x i1> [[TMP7]], <2 x double> [[TMP11]], <2 x double> [[VEC_PHI1]] +; SSE-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 +; SSE-NEXT: [[TMP12:%.*]] = icmp eq i32 [[INDEX_NEXT]], 32 +; SSE-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] ; SSE: middle.block: -; SSE-NEXT: [[TMP7:%.*]] = call fast double @llvm.vector.reduce.fadd.v2f64(double -0.000000e+00, <2 x double> [[PREDPHI]]) +; SSE-NEXT: [[BIN_RDX:%.*]] = fadd fast <2 x double> [[PREDPHI3]], [[PREDPHI]] +; SSE-NEXT: [[TMP13:%.*]] = call fast double @llvm.vector.reduce.fadd.v2f64(double -0.000000e+00, <2 x double> [[BIN_RDX]]) ; SSE-NEXT: br i1 true, label [[DONE:%.*]], label [[SCALAR_PH]] ; SSE: scalar.ph: ; SSE-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ 32, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] -; SSE-NEXT: [[BC_MERGE_RDX:%.*]] = phi double [ 0.000000e+00, [[ENTRY]] ], [ [[TMP7]], [[MIDDLE_BLOCK]] ] +; SSE-NEXT: [[BC_MERGE_RDX:%.*]] = phi double [ 0.000000e+00, [[ENTRY]] ], [ [[TMP13]], [[MIDDLE_BLOCK]] ] ; SSE-NEXT: br label [[LOOP:%.*]] ; SSE: loop: ; SSE-NEXT: [[I:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[I_NEXT:%.*]], [[NEXT_ITER:%.*]] ] @@ -107,9 +117,9 @@ define double @sumIfVector(ptr nocapture readonly %arr) { ; SSE-NEXT: [[TOT_NEXT]] = phi double [ [[TOT]], [[NO_ADD]] ], [ [[TOT_NEW]], [[DO_ADD]] ] ; SSE-NEXT: [[I_NEXT]] = add i32 [[I]], 1 ; SSE-NEXT: [[AGAIN:%.*]] = icmp ult i32 [[I_NEXT]], 32 -; SSE-NEXT: br i1 [[AGAIN]], label [[LOOP]], label [[DONE]], !llvm.loop [[LOOP2:![0-9]+]] +; SSE-NEXT: br i1 [[AGAIN]], label [[LOOP]], label [[DONE]], !llvm.loop [[LOOP3:![0-9]+]] ; SSE: done: -; SSE-NEXT: [[TOT_NEXT_LCSSA:%.*]] = phi double [ [[TOT_NEXT]], [[NEXT_ITER]] ], [ [[TMP7]], [[MIDDLE_BLOCK]] ] +; SSE-NEXT: [[TOT_NEXT_LCSSA:%.*]] = phi double [ [[TOT_NEXT]], [[NEXT_ITER]] ], [ [[TMP13]], [[MIDDLE_BLOCK]] ] ; SSE-NEXT: ret double [[TOT_NEXT_LCSSA]] ; ; AVX-LABEL: @sumIfVector( @@ -120,23 +130,53 @@ define double @sumIfVector(ptr nocapture readonly %arr) { ; AVX: vector.body: ; AVX-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; AVX-NEXT: [[VEC_PHI:%.*]] = phi <4 x double> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PREDPHI:%.*]], [[VECTOR_BODY]] ] +; AVX-NEXT: [[VEC_PHI1:%.*]] = phi <4 x double> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PREDPHI7:%.*]], [[VECTOR_BODY]] ] +; AVX-NEXT: [[VEC_PHI2:%.*]] = phi <4 x double> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PREDPHI8:%.*]], [[VECTOR_BODY]] ] +; AVX-NEXT: [[VEC_PHI3:%.*]] = phi <4 x double> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PREDPHI9:%.*]], [[VECTOR_BODY]] ] ; AVX-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 0 -; AVX-NEXT: [[TMP1:%.*]] = getelementptr double, ptr [[ARR:%.*]], i32 [[TMP0]] -; AVX-NEXT: [[TMP2:%.*]] = getelementptr double, ptr [[TMP1]], i32 0 -; AVX-NEXT: [[WIDE_LOAD:%.*]] = load <4 x double>, ptr [[TMP2]], align 8 -; AVX-NEXT: [[TMP3:%.*]] = fcmp fast une <4 x double> [[WIDE_LOAD]], -; AVX-NEXT: [[TMP5:%.*]] = xor <4 x i1> [[TMP3]], -; AVX-NEXT: [[TMP4:%.*]] = fadd fast <4 x double> [[VEC_PHI]], [[WIDE_LOAD]] -; AVX-NEXT: [[PREDPHI]] = select <4 x i1> [[TMP3]], <4 x double> [[TMP4]], <4 x double> [[VEC_PHI]] -; AVX-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 -; AVX-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], 32 -; AVX-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; AVX-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 4 +; AVX-NEXT: [[TMP2:%.*]] = add i32 [[INDEX]], 8 +; AVX-NEXT: [[TMP3:%.*]] = add i32 [[INDEX]], 12 +; AVX-NEXT: [[TMP4:%.*]] = getelementptr double, ptr [[ARR:%.*]], i32 [[TMP0]] +; AVX-NEXT: [[TMP5:%.*]] = getelementptr double, ptr [[ARR]], i32 [[TMP1]] +; AVX-NEXT: [[TMP6:%.*]] = getelementptr double, ptr [[ARR]], i32 [[TMP2]] +; AVX-NEXT: [[TMP7:%.*]] = getelementptr double, ptr [[ARR]], i32 [[TMP3]] +; AVX-NEXT: [[TMP8:%.*]] = getelementptr double, ptr [[TMP4]], i32 0 +; AVX-NEXT: [[TMP9:%.*]] = getelementptr double, ptr [[TMP4]], i32 4 +; AVX-NEXT: [[TMP10:%.*]] = getelementptr double, ptr [[TMP4]], i32 8 +; AVX-NEXT: [[TMP11:%.*]] = getelementptr double, ptr [[TMP4]], i32 12 +; AVX-NEXT: [[WIDE_LOAD:%.*]] = load <4 x double>, ptr [[TMP8]], align 8 +; AVX-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x double>, ptr [[TMP9]], align 8 +; AVX-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x double>, ptr [[TMP10]], align 8 +; AVX-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x double>, ptr [[TMP11]], align 8 +; AVX-NEXT: [[TMP12:%.*]] = fcmp fast une <4 x double> [[WIDE_LOAD]], +; AVX-NEXT: [[TMP13:%.*]] = fcmp fast une <4 x double> [[WIDE_LOAD4]], +; AVX-NEXT: [[TMP14:%.*]] = fcmp fast une <4 x double> [[WIDE_LOAD5]], +; AVX-NEXT: [[TMP15:%.*]] = fcmp fast une <4 x double> [[WIDE_LOAD6]], +; AVX-NEXT: [[TMP16:%.*]] = xor <4 x i1> [[TMP12]], +; AVX-NEXT: [[TMP17:%.*]] = xor <4 x i1> [[TMP13]], +; AVX-NEXT: [[TMP18:%.*]] = xor <4 x i1> [[TMP14]], +; AVX-NEXT: [[TMP19:%.*]] = xor <4 x i1> [[TMP15]], +; AVX-NEXT: [[TMP20:%.*]] = fadd fast <4 x double> [[VEC_PHI]], [[WIDE_LOAD]] +; AVX-NEXT: [[TMP21:%.*]] = fadd fast <4 x double> [[VEC_PHI1]], [[WIDE_LOAD4]] +; AVX-NEXT: [[TMP22:%.*]] = fadd fast <4 x double> [[VEC_PHI2]], [[WIDE_LOAD5]] +; AVX-NEXT: [[TMP23:%.*]] = fadd fast <4 x double> [[VEC_PHI3]], [[WIDE_LOAD6]] +; AVX-NEXT: [[PREDPHI]] = select <4 x i1> [[TMP12]], <4 x double> [[TMP20]], <4 x double> [[VEC_PHI]] +; AVX-NEXT: [[PREDPHI7]] = select <4 x i1> [[TMP13]], <4 x double> [[TMP21]], <4 x double> [[VEC_PHI1]] +; AVX-NEXT: [[PREDPHI8]] = select <4 x i1> [[TMP14]], <4 x double> [[TMP22]], <4 x double> [[VEC_PHI2]] +; AVX-NEXT: [[PREDPHI9]] = select <4 x i1> [[TMP15]], <4 x double> [[TMP23]], <4 x double> [[VEC_PHI3]] +; AVX-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 16 +; AVX-NEXT: [[TMP24:%.*]] = icmp eq i32 [[INDEX_NEXT]], 32 +; AVX-NEXT: br i1 [[TMP24]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] ; AVX: middle.block: -; AVX-NEXT: [[TMP7:%.*]] = call fast double @llvm.vector.reduce.fadd.v4f64(double -0.000000e+00, <4 x double> [[PREDPHI]]) +; AVX-NEXT: [[BIN_RDX:%.*]] = fadd fast <4 x double> [[PREDPHI7]], [[PREDPHI]] +; AVX-NEXT: [[BIN_RDX10:%.*]] = fadd fast <4 x double> [[PREDPHI8]], [[BIN_RDX]] +; AVX-NEXT: [[BIN_RDX11:%.*]] = fadd fast <4 x double> [[PREDPHI9]], [[BIN_RDX10]] +; AVX-NEXT: [[TMP25:%.*]] = call fast double @llvm.vector.reduce.fadd.v4f64(double -0.000000e+00, <4 x double> [[BIN_RDX11]]) ; AVX-NEXT: br i1 true, label [[DONE:%.*]], label [[SCALAR_PH]] ; AVX: scalar.ph: ; AVX-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ 32, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] -; AVX-NEXT: [[BC_MERGE_RDX:%.*]] = phi double [ 0.000000e+00, [[ENTRY]] ], [ [[TMP7]], [[MIDDLE_BLOCK]] ] +; AVX-NEXT: [[BC_MERGE_RDX:%.*]] = phi double [ 0.000000e+00, [[ENTRY]] ], [ [[TMP25]], [[MIDDLE_BLOCK]] ] ; AVX-NEXT: br label [[LOOP:%.*]] ; AVX: loop: ; AVX-NEXT: [[I:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[I_NEXT:%.*]], [[NEXT_ITER:%.*]] ] @@ -154,9 +194,9 @@ define double @sumIfVector(ptr nocapture readonly %arr) { ; AVX-NEXT: [[TOT_NEXT]] = phi double [ [[TOT]], [[NO_ADD]] ], [ [[TOT_NEW]], [[DO_ADD]] ] ; AVX-NEXT: [[I_NEXT]] = add i32 [[I]], 1 ; AVX-NEXT: [[AGAIN:%.*]] = icmp ult i32 [[I_NEXT]], 32 -; AVX-NEXT: br i1 [[AGAIN]], label [[LOOP]], label [[DONE]], !llvm.loop [[LOOP2:![0-9]+]] +; AVX-NEXT: br i1 [[AGAIN]], label [[LOOP]], label [[DONE]], !llvm.loop [[LOOP3:![0-9]+]] ; AVX: done: -; AVX-NEXT: [[TOT_NEXT_LCSSA:%.*]] = phi double [ [[TOT_NEXT]], [[NEXT_ITER]] ], [ [[TMP7]], [[MIDDLE_BLOCK]] ] +; AVX-NEXT: [[TOT_NEXT_LCSSA:%.*]] = phi double [ [[TOT_NEXT]], [[NEXT_ITER]] ], [ [[TMP25]], [[MIDDLE_BLOCK]] ] ; AVX-NEXT: ret double [[TOT_NEXT_LCSSA]] ; entry: diff --git a/llvm/test/Transforms/LoopVectorize/X86/interleave_short_tc.ll b/llvm/test/Transforms/LoopVectorize/X86/interleave_short_tc.ll index 4857d27df633..93d4e4c6d167 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/interleave_short_tc.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/interleave_short_tc.ll @@ -1,18 +1,15 @@ ; Check that we won't interleave by more than half the "best known" estimated trip count. -; The loop is expected to be vectorized by 4 and interleaving suppresed due to -; short trip count which is controled by "tiny-trip-count-interleave-threshold". -; RUN: opt -passes=loop-vectorize -force-vector-width=4 -vectorizer-min-trip-count=4 -S < %s | FileCheck %s ; ; The loop is expected to be vectorized by 4 and computed interleaving factor is 1. ; Thus the resulting step is 4. -; RUN: opt -passes=loop-vectorize -force-vector-width=4 -vectorizer-min-trip-count=4 -tiny-trip-count-interleave-threshold=4 -S < %s | FileCheck %s +; RUN: opt -passes=loop-vectorize -force-vector-width=4 -vectorizer-min-trip-count=4 -S < %s | FileCheck %s ; The loop is expected to be vectorized by 2 and computed interleaving factor is 2. ; Thus the resulting step is 4. -; RUN: opt -passes=loop-vectorize -force-vector-width=2 -vectorizer-min-trip-count=4 -tiny-trip-count-interleave-threshold=4 -S < %s | FileCheck %s +; RUN: opt -passes=loop-vectorize -force-vector-width=2 -vectorizer-min-trip-count=4 -S < %s | FileCheck %s -; Check that we won't interleave by more than half the "best known" estimated trip count. +; Check that we won't interleave by more than "best known" estimated trip count. target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/LoopVectorize/X86/limit-vf-by-tripcount.ll b/llvm/test/Transforms/LoopVectorize/X86/limit-vf-by-tripcount.ll index e30230120c44..7159a54234b4 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/limit-vf-by-tripcount.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/limit-vf-by-tripcount.ll @@ -85,16 +85,16 @@ define void @test_tc_18(ptr noalias %src, ptr noalias %dst) { ; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ 16, [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ] ; CHECK-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]] ; CHECK: vec.epilog.vector.body: -; CHECK-NEXT: [[INDEX2:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT4:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ] -; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[INDEX2]], 0 +; CHECK-NEXT: [[INDEX1:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT3:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ] +; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[INDEX1]], 0 ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[TMP6]] ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[TMP7]], i32 0 -; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <2 x i8>, ptr [[TMP8]], align 64 +; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <2 x i8>, ptr [[TMP8]], align 64 ; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[TMP6]] ; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i8, ptr [[TMP9]], i32 0 -; CHECK-NEXT: store <2 x i8> [[WIDE_LOAD3]], ptr [[TMP10]], align 64 -; CHECK-NEXT: [[INDEX_NEXT4]] = add nuw i64 [[INDEX2]], 2 -; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT4]], 18 +; CHECK-NEXT: store <2 x i8> [[WIDE_LOAD2]], ptr [[TMP10]], align 64 +; CHECK-NEXT: [[INDEX_NEXT3]] = add nuw i64 [[INDEX1]], 2 +; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT3]], 18 ; CHECK-NEXT: br i1 [[TMP11]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]] ; CHECK: vec.epilog.middle.block: ; CHECK-NEXT: br i1 true, label [[EXIT]], label [[VEC_EPILOG_SCALAR_PH]] @@ -158,16 +158,16 @@ define void @test_tc_19(ptr noalias %src, ptr noalias %dst) { ; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ 16, [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ] ; CHECK-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]] ; CHECK: vec.epilog.vector.body: -; CHECK-NEXT: [[INDEX2:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT4:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ] -; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[INDEX2]], 0 +; CHECK-NEXT: [[INDEX1:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT3:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ] +; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[INDEX1]], 0 ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[TMP6]] ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[TMP7]], i32 0 -; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <2 x i8>, ptr [[TMP8]], align 64 +; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <2 x i8>, ptr [[TMP8]], align 64 ; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[TMP6]] ; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i8, ptr [[TMP9]], i32 0 -; CHECK-NEXT: store <2 x i8> [[WIDE_LOAD3]], ptr [[TMP10]], align 64 -; CHECK-NEXT: [[INDEX_NEXT4]] = add nuw i64 [[INDEX2]], 2 -; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT4]], 18 +; CHECK-NEXT: store <2 x i8> [[WIDE_LOAD2]], ptr [[TMP10]], align 64 +; CHECK-NEXT: [[INDEX_NEXT3]] = add nuw i64 [[INDEX1]], 2 +; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT3]], 18 ; CHECK-NEXT: br i1 [[TMP11]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] ; CHECK: vec.epilog.middle.block: ; CHECK-NEXT: br i1 false, label [[EXIT]], label [[VEC_EPILOG_SCALAR_PH]] @@ -212,19 +212,40 @@ define void @test_tc_20(ptr noalias %src, ptr noalias %dst) { ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 -; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[SRC:%.*]], i64 [[TMP0]] -; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i32 0 -; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i8>, ptr [[TMP2]], align 64 -; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[DST:%.*]], i64 [[TMP0]] -; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[TMP3]], i32 0 -; CHECK-NEXT: store <4 x i8> [[WIDE_LOAD]], ptr [[TMP4]], align 64 -; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 -; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 20 -; CHECK-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]] +; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 4 +; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 8 +; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 12 +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[SRC:%.*]], i64 [[TMP0]] +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[TMP2]] +; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[TMP3]] +; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[TMP4]], i32 0 +; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr [[TMP4]], i32 4 +; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i8, ptr [[TMP4]], i32 8 +; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i8, ptr [[TMP4]], i32 12 +; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i8>, ptr [[TMP8]], align 64 +; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i8>, ptr [[TMP9]], align 64 +; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <4 x i8>, ptr [[TMP10]], align 64 +; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x i8>, ptr [[TMP11]], align 64 +; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i8, ptr [[DST:%.*]], i64 [[TMP0]] +; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[TMP2]] +; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[TMP3]] +; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i8, ptr [[TMP12]], i32 0 +; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i8, ptr [[TMP12]], i32 4 +; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i8, ptr [[TMP12]], i32 8 +; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i8, ptr [[TMP12]], i32 12 +; CHECK-NEXT: store <4 x i8> [[WIDE_LOAD]], ptr [[TMP16]], align 64 +; CHECK-NEXT: store <4 x i8> [[WIDE_LOAD1]], ptr [[TMP17]], align 64 +; CHECK-NEXT: store <4 x i8> [[WIDE_LOAD2]], ptr [[TMP18]], align 64 +; CHECK-NEXT: store <4 x i8> [[WIDE_LOAD3]], ptr [[TMP19]], align 64 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 +; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], 16 +; CHECK-NEXT: br i1 [[TMP20]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]] ; CHECK: middle.block: -; CHECK-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] +; CHECK-NEXT: br i1 false, label [[EXIT:%.*]], label [[SCALAR_PH]] ; CHECK: scalar.ph: -; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 20, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 16, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: ; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[I_NEXT:%.*]], [[LOOP]] ] diff --git a/llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll b/llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll index 19ac52cf0d0b..91b8e149487a 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll @@ -2507,48 +2507,147 @@ define i32 @test_stride_three(i64 %len, ptr %test_base) { ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP29:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP116:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP117:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP118:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP119:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 3 ; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0 ; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX]], 6 ; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], 9 -; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE:%.*]], i64 [[TMP0]] -; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP1]] -; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP2]] -; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP3]] -; CHECK-NEXT: [[TMP8:%.*]] = load i1, ptr [[TMP4]], align 1 -; CHECK-NEXT: [[TMP9:%.*]] = load i1, ptr [[TMP5]], align 1 -; CHECK-NEXT: [[TMP10:%.*]] = load i1, ptr [[TMP6]], align 1 -; CHECK-NEXT: [[TMP11:%.*]] = load i1, ptr [[TMP7]], align 1 -; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i1> poison, i1 [[TMP8]], i32 0 -; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i1> [[TMP12]], i1 [[TMP9]], i32 1 -; CHECK-NEXT: [[TMP14:%.*]] = insertelement <4 x i1> [[TMP13]], i1 [[TMP10]], i32 2 -; CHECK-NEXT: [[TMP15:%.*]] = insertelement <4 x i1> [[TMP14]], i1 [[TMP11]], i32 3 -; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP0]] -; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP1]] -; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP2]] -; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP3]] -; CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP16]], align 4 -; CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP17]], align 4 -; CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP18]], align 4 -; CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP19]], align 4 -; CHECK-NEXT: [[TMP24:%.*]] = insertelement <4 x i32> poison, i32 [[TMP20]], i32 0 -; CHECK-NEXT: [[TMP25:%.*]] = insertelement <4 x i32> [[TMP24]], i32 [[TMP21]], i32 1 -; CHECK-NEXT: [[TMP26:%.*]] = insertelement <4 x i32> [[TMP25]], i32 [[TMP22]], i32 2 -; CHECK-NEXT: [[TMP27:%.*]] = insertelement <4 x i32> [[TMP26]], i32 [[TMP23]], i32 3 -; CHECK-NEXT: [[TMP28:%.*]] = xor <4 x i1> [[TMP15]], -; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP15]], <4 x i32> [[TMP27]], <4 x i32> zeroinitializer -; CHECK-NEXT: [[TMP29]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]] -; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 -; CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[INDEX_NEXT]], 32 -; CHECK-NEXT: br i1 [[TMP30]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP30:![0-9]+]] +; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 12 +; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 15 +; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 18 +; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 21 +; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[OFFSET_IDX]], 24 +; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[OFFSET_IDX]], 27 +; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[OFFSET_IDX]], 30 +; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[OFFSET_IDX]], 33 +; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[OFFSET_IDX]], 36 +; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[OFFSET_IDX]], 39 +; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[OFFSET_IDX]], 42 +; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[OFFSET_IDX]], 45 +; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE:%.*]], i64 [[TMP0]] +; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP2]] +; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP3]] +; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP4]] +; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP5]] +; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP6]] +; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP7]] +; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP8]] +; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP9]] +; CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP10]] +; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP11]] +; CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP12]] +; CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP13]] +; CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP14]] +; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP15]] +; CHECK-NEXT: [[TMP32:%.*]] = load i1, ptr [[TMP16]], align 1 +; CHECK-NEXT: [[TMP33:%.*]] = load i1, ptr [[TMP17]], align 1 +; CHECK-NEXT: [[TMP34:%.*]] = load i1, ptr [[TMP18]], align 1 +; CHECK-NEXT: [[TMP35:%.*]] = load i1, ptr [[TMP19]], align 1 +; CHECK-NEXT: [[TMP36:%.*]] = insertelement <4 x i1> poison, i1 [[TMP32]], i32 0 +; CHECK-NEXT: [[TMP37:%.*]] = insertelement <4 x i1> [[TMP36]], i1 [[TMP33]], i32 1 +; CHECK-NEXT: [[TMP38:%.*]] = insertelement <4 x i1> [[TMP37]], i1 [[TMP34]], i32 2 +; CHECK-NEXT: [[TMP39:%.*]] = insertelement <4 x i1> [[TMP38]], i1 [[TMP35]], i32 3 +; CHECK-NEXT: [[TMP40:%.*]] = load i1, ptr [[TMP20]], align 1 +; CHECK-NEXT: [[TMP41:%.*]] = load i1, ptr [[TMP21]], align 1 +; CHECK-NEXT: [[TMP42:%.*]] = load i1, ptr [[TMP22]], align 1 +; CHECK-NEXT: [[TMP43:%.*]] = load i1, ptr [[TMP23]], align 1 +; CHECK-NEXT: [[TMP44:%.*]] = insertelement <4 x i1> poison, i1 [[TMP40]], i32 0 +; CHECK-NEXT: [[TMP45:%.*]] = insertelement <4 x i1> [[TMP44]], i1 [[TMP41]], i32 1 +; CHECK-NEXT: [[TMP46:%.*]] = insertelement <4 x i1> [[TMP45]], i1 [[TMP42]], i32 2 +; CHECK-NEXT: [[TMP47:%.*]] = insertelement <4 x i1> [[TMP46]], i1 [[TMP43]], i32 3 +; CHECK-NEXT: [[TMP48:%.*]] = load i1, ptr [[TMP24]], align 1 +; CHECK-NEXT: [[TMP49:%.*]] = load i1, ptr [[TMP25]], align 1 +; CHECK-NEXT: [[TMP50:%.*]] = load i1, ptr [[TMP26]], align 1 +; CHECK-NEXT: [[TMP51:%.*]] = load i1, ptr [[TMP27]], align 1 +; CHECK-NEXT: [[TMP52:%.*]] = insertelement <4 x i1> poison, i1 [[TMP48]], i32 0 +; CHECK-NEXT: [[TMP53:%.*]] = insertelement <4 x i1> [[TMP52]], i1 [[TMP49]], i32 1 +; CHECK-NEXT: [[TMP54:%.*]] = insertelement <4 x i1> [[TMP53]], i1 [[TMP50]], i32 2 +; CHECK-NEXT: [[TMP55:%.*]] = insertelement <4 x i1> [[TMP54]], i1 [[TMP51]], i32 3 +; CHECK-NEXT: [[TMP56:%.*]] = load i1, ptr [[TMP28]], align 1 +; CHECK-NEXT: [[TMP57:%.*]] = load i1, ptr [[TMP29]], align 1 +; CHECK-NEXT: [[TMP58:%.*]] = load i1, ptr [[TMP30]], align 1 +; CHECK-NEXT: [[TMP59:%.*]] = load i1, ptr [[TMP31]], align 1 +; CHECK-NEXT: [[TMP60:%.*]] = insertelement <4 x i1> poison, i1 [[TMP56]], i32 0 +; CHECK-NEXT: [[TMP61:%.*]] = insertelement <4 x i1> [[TMP60]], i1 [[TMP57]], i32 1 +; CHECK-NEXT: [[TMP62:%.*]] = insertelement <4 x i1> [[TMP61]], i1 [[TMP58]], i32 2 +; CHECK-NEXT: [[TMP63:%.*]] = insertelement <4 x i1> [[TMP62]], i1 [[TMP59]], i32 3 +; CHECK-NEXT: [[TMP64:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP0]] +; CHECK-NEXT: [[TMP65:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP66:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP2]] +; CHECK-NEXT: [[TMP67:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP3]] +; CHECK-NEXT: [[TMP68:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP4]] +; CHECK-NEXT: [[TMP69:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP5]] +; CHECK-NEXT: [[TMP70:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP6]] +; CHECK-NEXT: [[TMP71:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP7]] +; CHECK-NEXT: [[TMP72:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP8]] +; CHECK-NEXT: [[TMP73:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP9]] +; CHECK-NEXT: [[TMP74:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP10]] +; CHECK-NEXT: [[TMP75:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP11]] +; CHECK-NEXT: [[TMP76:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP12]] +; CHECK-NEXT: [[TMP77:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP13]] +; CHECK-NEXT: [[TMP78:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP14]] +; CHECK-NEXT: [[TMP79:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP15]] +; CHECK-NEXT: [[TMP80:%.*]] = load i32, ptr [[TMP64]], align 4 +; CHECK-NEXT: [[TMP81:%.*]] = load i32, ptr [[TMP65]], align 4 +; CHECK-NEXT: [[TMP82:%.*]] = load i32, ptr [[TMP66]], align 4 +; CHECK-NEXT: [[TMP83:%.*]] = load i32, ptr [[TMP67]], align 4 +; CHECK-NEXT: [[TMP84:%.*]] = insertelement <4 x i32> poison, i32 [[TMP80]], i32 0 +; CHECK-NEXT: [[TMP85:%.*]] = insertelement <4 x i32> [[TMP84]], i32 [[TMP81]], i32 1 +; CHECK-NEXT: [[TMP86:%.*]] = insertelement <4 x i32> [[TMP85]], i32 [[TMP82]], i32 2 +; CHECK-NEXT: [[TMP87:%.*]] = insertelement <4 x i32> [[TMP86]], i32 [[TMP83]], i32 3 +; CHECK-NEXT: [[TMP88:%.*]] = load i32, ptr [[TMP68]], align 4 +; CHECK-NEXT: [[TMP89:%.*]] = load i32, ptr [[TMP69]], align 4 +; CHECK-NEXT: [[TMP90:%.*]] = load i32, ptr [[TMP70]], align 4 +; CHECK-NEXT: [[TMP91:%.*]] = load i32, ptr [[TMP71]], align 4 +; CHECK-NEXT: [[TMP92:%.*]] = insertelement <4 x i32> poison, i32 [[TMP88]], i32 0 +; CHECK-NEXT: [[TMP93:%.*]] = insertelement <4 x i32> [[TMP92]], i32 [[TMP89]], i32 1 +; CHECK-NEXT: [[TMP94:%.*]] = insertelement <4 x i32> [[TMP93]], i32 [[TMP90]], i32 2 +; CHECK-NEXT: [[TMP95:%.*]] = insertelement <4 x i32> [[TMP94]], i32 [[TMP91]], i32 3 +; CHECK-NEXT: [[TMP96:%.*]] = load i32, ptr [[TMP72]], align 4 +; CHECK-NEXT: [[TMP97:%.*]] = load i32, ptr [[TMP73]], align 4 +; CHECK-NEXT: [[TMP98:%.*]] = load i32, ptr [[TMP74]], align 4 +; CHECK-NEXT: [[TMP99:%.*]] = load i32, ptr [[TMP75]], align 4 +; CHECK-NEXT: [[TMP100:%.*]] = insertelement <4 x i32> poison, i32 [[TMP96]], i32 0 +; CHECK-NEXT: [[TMP101:%.*]] = insertelement <4 x i32> [[TMP100]], i32 [[TMP97]], i32 1 +; CHECK-NEXT: [[TMP102:%.*]] = insertelement <4 x i32> [[TMP101]], i32 [[TMP98]], i32 2 +; CHECK-NEXT: [[TMP103:%.*]] = insertelement <4 x i32> [[TMP102]], i32 [[TMP99]], i32 3 +; CHECK-NEXT: [[TMP104:%.*]] = load i32, ptr [[TMP76]], align 4 +; CHECK-NEXT: [[TMP105:%.*]] = load i32, ptr [[TMP77]], align 4 +; CHECK-NEXT: [[TMP106:%.*]] = load i32, ptr [[TMP78]], align 4 +; CHECK-NEXT: [[TMP107:%.*]] = load i32, ptr [[TMP79]], align 4 +; CHECK-NEXT: [[TMP108:%.*]] = insertelement <4 x i32> poison, i32 [[TMP104]], i32 0 +; CHECK-NEXT: [[TMP109:%.*]] = insertelement <4 x i32> [[TMP108]], i32 [[TMP105]], i32 1 +; CHECK-NEXT: [[TMP110:%.*]] = insertelement <4 x i32> [[TMP109]], i32 [[TMP106]], i32 2 +; CHECK-NEXT: [[TMP111:%.*]] = insertelement <4 x i32> [[TMP110]], i32 [[TMP107]], i32 3 +; CHECK-NEXT: [[TMP112:%.*]] = xor <4 x i1> [[TMP39]], +; CHECK-NEXT: [[TMP113:%.*]] = xor <4 x i1> [[TMP47]], +; CHECK-NEXT: [[TMP114:%.*]] = xor <4 x i1> [[TMP55]], +; CHECK-NEXT: [[TMP115:%.*]] = xor <4 x i1> [[TMP63]], +; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[TMP87]], <4 x i32> zeroinitializer +; CHECK-NEXT: [[PREDPHI4:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[TMP95]], <4 x i32> zeroinitializer +; CHECK-NEXT: [[PREDPHI5:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[TMP103]], <4 x i32> zeroinitializer +; CHECK-NEXT: [[PREDPHI6:%.*]] = select <4 x i1> [[TMP63]], <4 x i32> [[TMP111]], <4 x i32> zeroinitializer +; CHECK-NEXT: [[TMP116]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]] +; CHECK-NEXT: [[TMP117]] = add <4 x i32> [[VEC_PHI1]], [[PREDPHI4]] +; CHECK-NEXT: [[TMP118]] = add <4 x i32> [[VEC_PHI2]], [[PREDPHI5]] +; CHECK-NEXT: [[TMP119]] = add <4 x i32> [[VEC_PHI3]], [[PREDPHI6]] +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 +; CHECK-NEXT: [[TMP120:%.*]] = icmp eq i64 [[INDEX_NEXT]], 32 +; CHECK-NEXT: br i1 [[TMP120]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP30:![0-9]+]] ; CHECK: middle.block: -; CHECK-NEXT: [[TMP31:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP29]]) +; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP117]], [[TMP116]] +; CHECK-NEXT: [[BIN_RDX7:%.*]] = add <4 x i32> [[TMP118]], [[BIN_RDX]] +; CHECK-NEXT: [[BIN_RDX8:%.*]] = add <4 x i32> [[TMP119]], [[BIN_RDX7]] +; CHECK-NEXT: [[TMP121:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX8]]) ; CHECK-NEXT: br i1 false, label [[LOOP_EXIT:%.*]], label [[SCALAR_PH]] ; CHECK: scalar.ph: ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 96, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] -; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[TMP31]], [[MIDDLE_BLOCK]] ] +; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[TMP121]], [[MIDDLE_BLOCK]] ] ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ] @@ -2567,7 +2666,7 @@ define i32 @test_stride_three(i64 %len, ptr %test_base) { ; CHECK-NEXT: [[EXIT:%.*]] = icmp ugt i64 [[IV]], 100 ; CHECK-NEXT: br i1 [[EXIT]], label [[LOOP_EXIT]], label [[LOOP]], !llvm.loop [[LOOP31:![0-9]+]] ; CHECK: loop_exit: -; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[LATCH]] ], [ [[TMP31]], [[MIDDLE_BLOCK]] ] +; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[LATCH]] ], [ [[TMP121]], [[MIDDLE_BLOCK]] ] ; CHECK-NEXT: ret i32 [[ACCUM_NEXT_LCSSA]] ; entry: @@ -2605,48 +2704,81 @@ define i32 @test_non_unit_stride_four(i64 %len, ptr %test_base) { ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP29:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP58:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP59:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 4 ; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0 ; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 4 ; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX]], 8 ; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], 12 -; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE:%.*]], i64 [[TMP0]] -; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP1]] -; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP2]] -; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP3]] -; CHECK-NEXT: [[TMP8:%.*]] = load i1, ptr [[TMP4]], align 1 -; CHECK-NEXT: [[TMP9:%.*]] = load i1, ptr [[TMP5]], align 1 -; CHECK-NEXT: [[TMP10:%.*]] = load i1, ptr [[TMP6]], align 1 -; CHECK-NEXT: [[TMP11:%.*]] = load i1, ptr [[TMP7]], align 1 -; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i1> poison, i1 [[TMP8]], i32 0 -; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i1> [[TMP12]], i1 [[TMP9]], i32 1 -; CHECK-NEXT: [[TMP14:%.*]] = insertelement <4 x i1> [[TMP13]], i1 [[TMP10]], i32 2 -; CHECK-NEXT: [[TMP15:%.*]] = insertelement <4 x i1> [[TMP14]], i1 [[TMP11]], i32 3 -; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP0]] -; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP1]] -; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP2]] -; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP3]] -; CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP16]], align 4 -; CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP17]], align 4 -; CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP18]], align 4 -; CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP19]], align 4 -; CHECK-NEXT: [[TMP24:%.*]] = insertelement <4 x i32> poison, i32 [[TMP20]], i32 0 -; CHECK-NEXT: [[TMP25:%.*]] = insertelement <4 x i32> [[TMP24]], i32 [[TMP21]], i32 1 -; CHECK-NEXT: [[TMP26:%.*]] = insertelement <4 x i32> [[TMP25]], i32 [[TMP22]], i32 2 -; CHECK-NEXT: [[TMP27:%.*]] = insertelement <4 x i32> [[TMP26]], i32 [[TMP23]], i32 3 -; CHECK-NEXT: [[TMP28:%.*]] = xor <4 x i1> [[TMP15]], -; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP15]], <4 x i32> [[TMP27]], <4 x i32> zeroinitializer -; CHECK-NEXT: [[TMP29]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]] -; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 -; CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[INDEX_NEXT]], 24 -; CHECK-NEXT: br i1 [[TMP30]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP32:![0-9]+]] +; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 16 +; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 20 +; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 24 +; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 28 +; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE:%.*]], i64 [[TMP0]] +; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP2]] +; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP3]] +; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP4]] +; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP5]] +; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP6]] +; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP7]] +; CHECK-NEXT: [[TMP16:%.*]] = load i1, ptr [[TMP8]], align 1 +; CHECK-NEXT: [[TMP17:%.*]] = load i1, ptr [[TMP9]], align 1 +; CHECK-NEXT: [[TMP18:%.*]] = load i1, ptr [[TMP10]], align 1 +; CHECK-NEXT: [[TMP19:%.*]] = load i1, ptr [[TMP11]], align 1 +; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x i1> poison, i1 [[TMP16]], i32 0 +; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x i1> [[TMP20]], i1 [[TMP17]], i32 1 +; CHECK-NEXT: [[TMP22:%.*]] = insertelement <4 x i1> [[TMP21]], i1 [[TMP18]], i32 2 +; CHECK-NEXT: [[TMP23:%.*]] = insertelement <4 x i1> [[TMP22]], i1 [[TMP19]], i32 3 +; CHECK-NEXT: [[TMP24:%.*]] = load i1, ptr [[TMP12]], align 1 +; CHECK-NEXT: [[TMP25:%.*]] = load i1, ptr [[TMP13]], align 1 +; CHECK-NEXT: [[TMP26:%.*]] = load i1, ptr [[TMP14]], align 1 +; CHECK-NEXT: [[TMP27:%.*]] = load i1, ptr [[TMP15]], align 1 +; CHECK-NEXT: [[TMP28:%.*]] = insertelement <4 x i1> poison, i1 [[TMP24]], i32 0 +; CHECK-NEXT: [[TMP29:%.*]] = insertelement <4 x i1> [[TMP28]], i1 [[TMP25]], i32 1 +; CHECK-NEXT: [[TMP30:%.*]] = insertelement <4 x i1> [[TMP29]], i1 [[TMP26]], i32 2 +; CHECK-NEXT: [[TMP31:%.*]] = insertelement <4 x i1> [[TMP30]], i1 [[TMP27]], i32 3 +; CHECK-NEXT: [[TMP32:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP0]] +; CHECK-NEXT: [[TMP33:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP34:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP2]] +; CHECK-NEXT: [[TMP35:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP3]] +; CHECK-NEXT: [[TMP36:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP4]] +; CHECK-NEXT: [[TMP37:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP5]] +; CHECK-NEXT: [[TMP38:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP6]] +; CHECK-NEXT: [[TMP39:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP7]] +; CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr [[TMP32]], align 4 +; CHECK-NEXT: [[TMP41:%.*]] = load i32, ptr [[TMP33]], align 4 +; CHECK-NEXT: [[TMP42:%.*]] = load i32, ptr [[TMP34]], align 4 +; CHECK-NEXT: [[TMP43:%.*]] = load i32, ptr [[TMP35]], align 4 +; CHECK-NEXT: [[TMP44:%.*]] = insertelement <4 x i32> poison, i32 [[TMP40]], i32 0 +; CHECK-NEXT: [[TMP45:%.*]] = insertelement <4 x i32> [[TMP44]], i32 [[TMP41]], i32 1 +; CHECK-NEXT: [[TMP46:%.*]] = insertelement <4 x i32> [[TMP45]], i32 [[TMP42]], i32 2 +; CHECK-NEXT: [[TMP47:%.*]] = insertelement <4 x i32> [[TMP46]], i32 [[TMP43]], i32 3 +; CHECK-NEXT: [[TMP48:%.*]] = load i32, ptr [[TMP36]], align 4 +; CHECK-NEXT: [[TMP49:%.*]] = load i32, ptr [[TMP37]], align 4 +; CHECK-NEXT: [[TMP50:%.*]] = load i32, ptr [[TMP38]], align 4 +; CHECK-NEXT: [[TMP51:%.*]] = load i32, ptr [[TMP39]], align 4 +; CHECK-NEXT: [[TMP52:%.*]] = insertelement <4 x i32> poison, i32 [[TMP48]], i32 0 +; CHECK-NEXT: [[TMP53:%.*]] = insertelement <4 x i32> [[TMP52]], i32 [[TMP49]], i32 1 +; CHECK-NEXT: [[TMP54:%.*]] = insertelement <4 x i32> [[TMP53]], i32 [[TMP50]], i32 2 +; CHECK-NEXT: [[TMP55:%.*]] = insertelement <4 x i32> [[TMP54]], i32 [[TMP51]], i32 3 +; CHECK-NEXT: [[TMP56:%.*]] = xor <4 x i1> [[TMP23]], +; CHECK-NEXT: [[TMP57:%.*]] = xor <4 x i1> [[TMP31]], +; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP23]], <4 x i32> [[TMP47]], <4 x i32> zeroinitializer +; CHECK-NEXT: [[PREDPHI2:%.*]] = select <4 x i1> [[TMP31]], <4 x i32> [[TMP55]], <4 x i32> zeroinitializer +; CHECK-NEXT: [[TMP58]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]] +; CHECK-NEXT: [[TMP59]] = add <4 x i32> [[VEC_PHI1]], [[PREDPHI2]] +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 +; CHECK-NEXT: [[TMP60:%.*]] = icmp eq i64 [[INDEX_NEXT]], 24 +; CHECK-NEXT: br i1 [[TMP60]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP32:![0-9]+]] ; CHECK: middle.block: -; CHECK-NEXT: [[TMP31:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP29]]) +; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP59]], [[TMP58]] +; CHECK-NEXT: [[TMP61:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX]]) ; CHECK-NEXT: br i1 false, label [[LOOP_EXIT:%.*]], label [[SCALAR_PH]] ; CHECK: scalar.ph: ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 96, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] -; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[TMP31]], [[MIDDLE_BLOCK]] ] +; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[TMP61]], [[MIDDLE_BLOCK]] ] ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ] @@ -2665,7 +2797,7 @@ define i32 @test_non_unit_stride_four(i64 %len, ptr %test_base) { ; CHECK-NEXT: [[EXIT:%.*]] = icmp ugt i64 [[IV]], 100 ; CHECK-NEXT: br i1 [[EXIT]], label [[LOOP_EXIT]], label [[LOOP]], !llvm.loop [[LOOP33:![0-9]+]] ; CHECK: loop_exit: -; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[LATCH]] ], [ [[TMP31]], [[MIDDLE_BLOCK]] ] +; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[LATCH]] ], [ [[TMP61]], [[MIDDLE_BLOCK]] ] ; CHECK-NEXT: ret i32 [[ACCUM_NEXT_LCSSA]] ; entry: @@ -2703,48 +2835,147 @@ define i32 @test_non_unit_stride_five(i64 %len, ptr %test_base) { ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP29:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP116:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP117:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP118:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP119:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 5 ; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0 ; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 5 ; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX]], 10 ; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], 15 -; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE:%.*]], i64 [[TMP0]] -; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP1]] -; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP2]] -; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP3]] -; CHECK-NEXT: [[TMP8:%.*]] = load i1, ptr [[TMP4]], align 1 -; CHECK-NEXT: [[TMP9:%.*]] = load i1, ptr [[TMP5]], align 1 -; CHECK-NEXT: [[TMP10:%.*]] = load i1, ptr [[TMP6]], align 1 -; CHECK-NEXT: [[TMP11:%.*]] = load i1, ptr [[TMP7]], align 1 -; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i1> poison, i1 [[TMP8]], i32 0 -; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i1> [[TMP12]], i1 [[TMP9]], i32 1 -; CHECK-NEXT: [[TMP14:%.*]] = insertelement <4 x i1> [[TMP13]], i1 [[TMP10]], i32 2 -; CHECK-NEXT: [[TMP15:%.*]] = insertelement <4 x i1> [[TMP14]], i1 [[TMP11]], i32 3 -; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP0]] -; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP1]] -; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP2]] -; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP3]] -; CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP16]], align 4 -; CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP17]], align 4 -; CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP18]], align 4 -; CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP19]], align 4 -; CHECK-NEXT: [[TMP24:%.*]] = insertelement <4 x i32> poison, i32 [[TMP20]], i32 0 -; CHECK-NEXT: [[TMP25:%.*]] = insertelement <4 x i32> [[TMP24]], i32 [[TMP21]], i32 1 -; CHECK-NEXT: [[TMP26:%.*]] = insertelement <4 x i32> [[TMP25]], i32 [[TMP22]], i32 2 -; CHECK-NEXT: [[TMP27:%.*]] = insertelement <4 x i32> [[TMP26]], i32 [[TMP23]], i32 3 -; CHECK-NEXT: [[TMP28:%.*]] = xor <4 x i1> [[TMP15]], -; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP15]], <4 x i32> [[TMP27]], <4 x i32> zeroinitializer -; CHECK-NEXT: [[TMP29]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]] -; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 -; CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[INDEX_NEXT]], 20 -; CHECK-NEXT: br i1 [[TMP30]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP34:![0-9]+]] +; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 20 +; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 25 +; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 30 +; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 35 +; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[OFFSET_IDX]], 40 +; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[OFFSET_IDX]], 45 +; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[OFFSET_IDX]], 50 +; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[OFFSET_IDX]], 55 +; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[OFFSET_IDX]], 60 +; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[OFFSET_IDX]], 65 +; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[OFFSET_IDX]], 70 +; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[OFFSET_IDX]], 75 +; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE:%.*]], i64 [[TMP0]] +; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP2]] +; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP3]] +; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP4]] +; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP5]] +; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP6]] +; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP7]] +; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP8]] +; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP9]] +; CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP10]] +; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP11]] +; CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP12]] +; CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP13]] +; CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP14]] +; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP15]] +; CHECK-NEXT: [[TMP32:%.*]] = load i1, ptr [[TMP16]], align 1 +; CHECK-NEXT: [[TMP33:%.*]] = load i1, ptr [[TMP17]], align 1 +; CHECK-NEXT: [[TMP34:%.*]] = load i1, ptr [[TMP18]], align 1 +; CHECK-NEXT: [[TMP35:%.*]] = load i1, ptr [[TMP19]], align 1 +; CHECK-NEXT: [[TMP36:%.*]] = insertelement <4 x i1> poison, i1 [[TMP32]], i32 0 +; CHECK-NEXT: [[TMP37:%.*]] = insertelement <4 x i1> [[TMP36]], i1 [[TMP33]], i32 1 +; CHECK-NEXT: [[TMP38:%.*]] = insertelement <4 x i1> [[TMP37]], i1 [[TMP34]], i32 2 +; CHECK-NEXT: [[TMP39:%.*]] = insertelement <4 x i1> [[TMP38]], i1 [[TMP35]], i32 3 +; CHECK-NEXT: [[TMP40:%.*]] = load i1, ptr [[TMP20]], align 1 +; CHECK-NEXT: [[TMP41:%.*]] = load i1, ptr [[TMP21]], align 1 +; CHECK-NEXT: [[TMP42:%.*]] = load i1, ptr [[TMP22]], align 1 +; CHECK-NEXT: [[TMP43:%.*]] = load i1, ptr [[TMP23]], align 1 +; CHECK-NEXT: [[TMP44:%.*]] = insertelement <4 x i1> poison, i1 [[TMP40]], i32 0 +; CHECK-NEXT: [[TMP45:%.*]] = insertelement <4 x i1> [[TMP44]], i1 [[TMP41]], i32 1 +; CHECK-NEXT: [[TMP46:%.*]] = insertelement <4 x i1> [[TMP45]], i1 [[TMP42]], i32 2 +; CHECK-NEXT: [[TMP47:%.*]] = insertelement <4 x i1> [[TMP46]], i1 [[TMP43]], i32 3 +; CHECK-NEXT: [[TMP48:%.*]] = load i1, ptr [[TMP24]], align 1 +; CHECK-NEXT: [[TMP49:%.*]] = load i1, ptr [[TMP25]], align 1 +; CHECK-NEXT: [[TMP50:%.*]] = load i1, ptr [[TMP26]], align 1 +; CHECK-NEXT: [[TMP51:%.*]] = load i1, ptr [[TMP27]], align 1 +; CHECK-NEXT: [[TMP52:%.*]] = insertelement <4 x i1> poison, i1 [[TMP48]], i32 0 +; CHECK-NEXT: [[TMP53:%.*]] = insertelement <4 x i1> [[TMP52]], i1 [[TMP49]], i32 1 +; CHECK-NEXT: [[TMP54:%.*]] = insertelement <4 x i1> [[TMP53]], i1 [[TMP50]], i32 2 +; CHECK-NEXT: [[TMP55:%.*]] = insertelement <4 x i1> [[TMP54]], i1 [[TMP51]], i32 3 +; CHECK-NEXT: [[TMP56:%.*]] = load i1, ptr [[TMP28]], align 1 +; CHECK-NEXT: [[TMP57:%.*]] = load i1, ptr [[TMP29]], align 1 +; CHECK-NEXT: [[TMP58:%.*]] = load i1, ptr [[TMP30]], align 1 +; CHECK-NEXT: [[TMP59:%.*]] = load i1, ptr [[TMP31]], align 1 +; CHECK-NEXT: [[TMP60:%.*]] = insertelement <4 x i1> poison, i1 [[TMP56]], i32 0 +; CHECK-NEXT: [[TMP61:%.*]] = insertelement <4 x i1> [[TMP60]], i1 [[TMP57]], i32 1 +; CHECK-NEXT: [[TMP62:%.*]] = insertelement <4 x i1> [[TMP61]], i1 [[TMP58]], i32 2 +; CHECK-NEXT: [[TMP63:%.*]] = insertelement <4 x i1> [[TMP62]], i1 [[TMP59]], i32 3 +; CHECK-NEXT: [[TMP64:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP0]] +; CHECK-NEXT: [[TMP65:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP66:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP2]] +; CHECK-NEXT: [[TMP67:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP3]] +; CHECK-NEXT: [[TMP68:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP4]] +; CHECK-NEXT: [[TMP69:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP5]] +; CHECK-NEXT: [[TMP70:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP6]] +; CHECK-NEXT: [[TMP71:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP7]] +; CHECK-NEXT: [[TMP72:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP8]] +; CHECK-NEXT: [[TMP73:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP9]] +; CHECK-NEXT: [[TMP74:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP10]] +; CHECK-NEXT: [[TMP75:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP11]] +; CHECK-NEXT: [[TMP76:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP12]] +; CHECK-NEXT: [[TMP77:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP13]] +; CHECK-NEXT: [[TMP78:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP14]] +; CHECK-NEXT: [[TMP79:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP15]] +; CHECK-NEXT: [[TMP80:%.*]] = load i32, ptr [[TMP64]], align 4 +; CHECK-NEXT: [[TMP81:%.*]] = load i32, ptr [[TMP65]], align 4 +; CHECK-NEXT: [[TMP82:%.*]] = load i32, ptr [[TMP66]], align 4 +; CHECK-NEXT: [[TMP83:%.*]] = load i32, ptr [[TMP67]], align 4 +; CHECK-NEXT: [[TMP84:%.*]] = insertelement <4 x i32> poison, i32 [[TMP80]], i32 0 +; CHECK-NEXT: [[TMP85:%.*]] = insertelement <4 x i32> [[TMP84]], i32 [[TMP81]], i32 1 +; CHECK-NEXT: [[TMP86:%.*]] = insertelement <4 x i32> [[TMP85]], i32 [[TMP82]], i32 2 +; CHECK-NEXT: [[TMP87:%.*]] = insertelement <4 x i32> [[TMP86]], i32 [[TMP83]], i32 3 +; CHECK-NEXT: [[TMP88:%.*]] = load i32, ptr [[TMP68]], align 4 +; CHECK-NEXT: [[TMP89:%.*]] = load i32, ptr [[TMP69]], align 4 +; CHECK-NEXT: [[TMP90:%.*]] = load i32, ptr [[TMP70]], align 4 +; CHECK-NEXT: [[TMP91:%.*]] = load i32, ptr [[TMP71]], align 4 +; CHECK-NEXT: [[TMP92:%.*]] = insertelement <4 x i32> poison, i32 [[TMP88]], i32 0 +; CHECK-NEXT: [[TMP93:%.*]] = insertelement <4 x i32> [[TMP92]], i32 [[TMP89]], i32 1 +; CHECK-NEXT: [[TMP94:%.*]] = insertelement <4 x i32> [[TMP93]], i32 [[TMP90]], i32 2 +; CHECK-NEXT: [[TMP95:%.*]] = insertelement <4 x i32> [[TMP94]], i32 [[TMP91]], i32 3 +; CHECK-NEXT: [[TMP96:%.*]] = load i32, ptr [[TMP72]], align 4 +; CHECK-NEXT: [[TMP97:%.*]] = load i32, ptr [[TMP73]], align 4 +; CHECK-NEXT: [[TMP98:%.*]] = load i32, ptr [[TMP74]], align 4 +; CHECK-NEXT: [[TMP99:%.*]] = load i32, ptr [[TMP75]], align 4 +; CHECK-NEXT: [[TMP100:%.*]] = insertelement <4 x i32> poison, i32 [[TMP96]], i32 0 +; CHECK-NEXT: [[TMP101:%.*]] = insertelement <4 x i32> [[TMP100]], i32 [[TMP97]], i32 1 +; CHECK-NEXT: [[TMP102:%.*]] = insertelement <4 x i32> [[TMP101]], i32 [[TMP98]], i32 2 +; CHECK-NEXT: [[TMP103:%.*]] = insertelement <4 x i32> [[TMP102]], i32 [[TMP99]], i32 3 +; CHECK-NEXT: [[TMP104:%.*]] = load i32, ptr [[TMP76]], align 4 +; CHECK-NEXT: [[TMP105:%.*]] = load i32, ptr [[TMP77]], align 4 +; CHECK-NEXT: [[TMP106:%.*]] = load i32, ptr [[TMP78]], align 4 +; CHECK-NEXT: [[TMP107:%.*]] = load i32, ptr [[TMP79]], align 4 +; CHECK-NEXT: [[TMP108:%.*]] = insertelement <4 x i32> poison, i32 [[TMP104]], i32 0 +; CHECK-NEXT: [[TMP109:%.*]] = insertelement <4 x i32> [[TMP108]], i32 [[TMP105]], i32 1 +; CHECK-NEXT: [[TMP110:%.*]] = insertelement <4 x i32> [[TMP109]], i32 [[TMP106]], i32 2 +; CHECK-NEXT: [[TMP111:%.*]] = insertelement <4 x i32> [[TMP110]], i32 [[TMP107]], i32 3 +; CHECK-NEXT: [[TMP112:%.*]] = xor <4 x i1> [[TMP39]], +; CHECK-NEXT: [[TMP113:%.*]] = xor <4 x i1> [[TMP47]], +; CHECK-NEXT: [[TMP114:%.*]] = xor <4 x i1> [[TMP55]], +; CHECK-NEXT: [[TMP115:%.*]] = xor <4 x i1> [[TMP63]], +; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[TMP87]], <4 x i32> zeroinitializer +; CHECK-NEXT: [[PREDPHI4:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[TMP95]], <4 x i32> zeroinitializer +; CHECK-NEXT: [[PREDPHI5:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[TMP103]], <4 x i32> zeroinitializer +; CHECK-NEXT: [[PREDPHI6:%.*]] = select <4 x i1> [[TMP63]], <4 x i32> [[TMP111]], <4 x i32> zeroinitializer +; CHECK-NEXT: [[TMP116]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]] +; CHECK-NEXT: [[TMP117]] = add <4 x i32> [[VEC_PHI1]], [[PREDPHI4]] +; CHECK-NEXT: [[TMP118]] = add <4 x i32> [[VEC_PHI2]], [[PREDPHI5]] +; CHECK-NEXT: [[TMP119]] = add <4 x i32> [[VEC_PHI3]], [[PREDPHI6]] +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 +; CHECK-NEXT: [[TMP120:%.*]] = icmp eq i64 [[INDEX_NEXT]], 16 +; CHECK-NEXT: br i1 [[TMP120]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP34:![0-9]+]] ; CHECK: middle.block: -; CHECK-NEXT: [[TMP31:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP29]]) +; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP117]], [[TMP116]] +; CHECK-NEXT: [[BIN_RDX7:%.*]] = add <4 x i32> [[TMP118]], [[BIN_RDX]] +; CHECK-NEXT: [[BIN_RDX8:%.*]] = add <4 x i32> [[TMP119]], [[BIN_RDX7]] +; CHECK-NEXT: [[TMP121:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX8]]) ; CHECK-NEXT: br i1 false, label [[LOOP_EXIT:%.*]], label [[SCALAR_PH]] ; CHECK: scalar.ph: -; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 100, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] -; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[TMP31]], [[MIDDLE_BLOCK]] ] +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 80, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] +; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[TMP121]], [[MIDDLE_BLOCK]] ] ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ] @@ -2763,7 +2994,7 @@ define i32 @test_non_unit_stride_five(i64 %len, ptr %test_base) { ; CHECK-NEXT: [[EXIT:%.*]] = icmp ugt i64 [[IV]], 100 ; CHECK-NEXT: br i1 [[EXIT]], label [[LOOP_EXIT]], label [[LOOP]], !llvm.loop [[LOOP35:![0-9]+]] ; CHECK: loop_exit: -; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[LATCH]] ], [ [[TMP31]], [[MIDDLE_BLOCK]] ] +; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[LATCH]] ], [ [[TMP121]], [[MIDDLE_BLOCK]] ] ; CHECK-NEXT: ret i32 [[ACCUM_NEXT_LCSSA]] ; entry: @@ -2800,73 +3031,244 @@ define i32 @neg_test_non_unit_stride_off_by_four_bytes(i64 %len, ptr %test_base) ; CHECK: vector.ph: ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: -; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_LOAD_CONTINUE6:%.*]] ] -; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP37:%.*]], [[PRED_LOAD_CONTINUE6]] ] +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_LOAD_CONTINUE33:%.*]] ] +; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP148:%.*]], [[PRED_LOAD_CONTINUE33]] ] +; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP149:%.*]], [[PRED_LOAD_CONTINUE33]] ] +; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP150:%.*]], [[PRED_LOAD_CONTINUE33]] ] +; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP151:%.*]], [[PRED_LOAD_CONTINUE33]] ] ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 2 ; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0 ; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 2 ; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX]], 4 ; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], 6 -; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE:%.*]], i64 [[TMP0]] -; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP1]] -; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP2]] -; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP3]] -; CHECK-NEXT: [[TMP8:%.*]] = load i1, ptr [[TMP4]], align 1 -; CHECK-NEXT: [[TMP9:%.*]] = load i1, ptr [[TMP5]], align 1 -; CHECK-NEXT: [[TMP10:%.*]] = load i1, ptr [[TMP6]], align 1 -; CHECK-NEXT: [[TMP11:%.*]] = load i1, ptr [[TMP7]], align 1 -; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i1> poison, i1 [[TMP8]], i32 0 -; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i1> [[TMP12]], i1 [[TMP9]], i32 1 -; CHECK-NEXT: [[TMP14:%.*]] = insertelement <4 x i1> [[TMP13]], i1 [[TMP10]], i32 2 -; CHECK-NEXT: [[TMP15:%.*]] = insertelement <4 x i1> [[TMP14]], i1 [[TMP11]], i32 3 -; CHECK-NEXT: [[TMP16:%.*]] = extractelement <4 x i1> [[TMP15]], i32 0 -; CHECK-NEXT: br i1 [[TMP16]], label [[PRED_LOAD_IF:%.*]], label [[PRED_LOAD_CONTINUE:%.*]] +; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 8 +; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 10 +; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 12 +; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 14 +; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[OFFSET_IDX]], 16 +; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[OFFSET_IDX]], 18 +; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[OFFSET_IDX]], 20 +; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[OFFSET_IDX]], 22 +; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[OFFSET_IDX]], 24 +; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[OFFSET_IDX]], 26 +; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[OFFSET_IDX]], 28 +; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[OFFSET_IDX]], 30 +; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE:%.*]], i64 [[TMP0]] +; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP2]] +; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP3]] +; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP4]] +; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP5]] +; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP6]] +; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP7]] +; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP8]] +; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP9]] +; CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP10]] +; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP11]] +; CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP12]] +; CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP13]] +; CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP14]] +; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP15]] +; CHECK-NEXT: [[TMP32:%.*]] = load i1, ptr [[TMP16]], align 1 +; CHECK-NEXT: [[TMP33:%.*]] = load i1, ptr [[TMP17]], align 1 +; CHECK-NEXT: [[TMP34:%.*]] = load i1, ptr [[TMP18]], align 1 +; CHECK-NEXT: [[TMP35:%.*]] = load i1, ptr [[TMP19]], align 1 +; CHECK-NEXT: [[TMP36:%.*]] = insertelement <4 x i1> poison, i1 [[TMP32]], i32 0 +; CHECK-NEXT: [[TMP37:%.*]] = insertelement <4 x i1> [[TMP36]], i1 [[TMP33]], i32 1 +; CHECK-NEXT: [[TMP38:%.*]] = insertelement <4 x i1> [[TMP37]], i1 [[TMP34]], i32 2 +; CHECK-NEXT: [[TMP39:%.*]] = insertelement <4 x i1> [[TMP38]], i1 [[TMP35]], i32 3 +; CHECK-NEXT: [[TMP40:%.*]] = load i1, ptr [[TMP20]], align 1 +; CHECK-NEXT: [[TMP41:%.*]] = load i1, ptr [[TMP21]], align 1 +; CHECK-NEXT: [[TMP42:%.*]] = load i1, ptr [[TMP22]], align 1 +; CHECK-NEXT: [[TMP43:%.*]] = load i1, ptr [[TMP23]], align 1 +; CHECK-NEXT: [[TMP44:%.*]] = insertelement <4 x i1> poison, i1 [[TMP40]], i32 0 +; CHECK-NEXT: [[TMP45:%.*]] = insertelement <4 x i1> [[TMP44]], i1 [[TMP41]], i32 1 +; CHECK-NEXT: [[TMP46:%.*]] = insertelement <4 x i1> [[TMP45]], i1 [[TMP42]], i32 2 +; CHECK-NEXT: [[TMP47:%.*]] = insertelement <4 x i1> [[TMP46]], i1 [[TMP43]], i32 3 +; CHECK-NEXT: [[TMP48:%.*]] = load i1, ptr [[TMP24]], align 1 +; CHECK-NEXT: [[TMP49:%.*]] = load i1, ptr [[TMP25]], align 1 +; CHECK-NEXT: [[TMP50:%.*]] = load i1, ptr [[TMP26]], align 1 +; CHECK-NEXT: [[TMP51:%.*]] = load i1, ptr [[TMP27]], align 1 +; CHECK-NEXT: [[TMP52:%.*]] = insertelement <4 x i1> poison, i1 [[TMP48]], i32 0 +; CHECK-NEXT: [[TMP53:%.*]] = insertelement <4 x i1> [[TMP52]], i1 [[TMP49]], i32 1 +; CHECK-NEXT: [[TMP54:%.*]] = insertelement <4 x i1> [[TMP53]], i1 [[TMP50]], i32 2 +; CHECK-NEXT: [[TMP55:%.*]] = insertelement <4 x i1> [[TMP54]], i1 [[TMP51]], i32 3 +; CHECK-NEXT: [[TMP56:%.*]] = load i1, ptr [[TMP28]], align 1 +; CHECK-NEXT: [[TMP57:%.*]] = load i1, ptr [[TMP29]], align 1 +; CHECK-NEXT: [[TMP58:%.*]] = load i1, ptr [[TMP30]], align 1 +; CHECK-NEXT: [[TMP59:%.*]] = load i1, ptr [[TMP31]], align 1 +; CHECK-NEXT: [[TMP60:%.*]] = insertelement <4 x i1> poison, i1 [[TMP56]], i32 0 +; CHECK-NEXT: [[TMP61:%.*]] = insertelement <4 x i1> [[TMP60]], i1 [[TMP57]], i32 1 +; CHECK-NEXT: [[TMP62:%.*]] = insertelement <4 x i1> [[TMP61]], i1 [[TMP58]], i32 2 +; CHECK-NEXT: [[TMP63:%.*]] = insertelement <4 x i1> [[TMP62]], i1 [[TMP59]], i32 3 +; CHECK-NEXT: [[TMP64:%.*]] = extractelement <4 x i1> [[TMP39]], i32 0 +; CHECK-NEXT: br i1 [[TMP64]], label [[PRED_LOAD_IF:%.*]], label [[PRED_LOAD_CONTINUE:%.*]] ; CHECK: pred.load.if: -; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP0]] -; CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4 -; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x i32> poison, i32 [[TMP18]], i32 0 +; CHECK-NEXT: [[TMP65:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP0]] +; CHECK-NEXT: [[TMP66:%.*]] = load i32, ptr [[TMP65]], align 4 +; CHECK-NEXT: [[TMP67:%.*]] = insertelement <4 x i32> poison, i32 [[TMP66]], i32 0 ; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE]] ; CHECK: pred.load.continue: -; CHECK-NEXT: [[TMP20:%.*]] = phi <4 x i32> [ poison, [[VECTOR_BODY]] ], [ [[TMP19]], [[PRED_LOAD_IF]] ] -; CHECK-NEXT: [[TMP21:%.*]] = extractelement <4 x i1> [[TMP15]], i32 1 -; CHECK-NEXT: br i1 [[TMP21]], label [[PRED_LOAD_IF1:%.*]], label [[PRED_LOAD_CONTINUE2:%.*]] -; CHECK: pred.load.if1: -; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP1]] -; CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4 -; CHECK-NEXT: [[TMP24:%.*]] = insertelement <4 x i32> [[TMP20]], i32 [[TMP23]], i32 1 -; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE2]] -; CHECK: pred.load.continue2: -; CHECK-NEXT: [[TMP25:%.*]] = phi <4 x i32> [ [[TMP20]], [[PRED_LOAD_CONTINUE]] ], [ [[TMP24]], [[PRED_LOAD_IF1]] ] -; CHECK-NEXT: [[TMP26:%.*]] = extractelement <4 x i1> [[TMP15]], i32 2 -; CHECK-NEXT: br i1 [[TMP26]], label [[PRED_LOAD_IF3:%.*]], label [[PRED_LOAD_CONTINUE4:%.*]] -; CHECK: pred.load.if3: -; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP2]] -; CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4 -; CHECK-NEXT: [[TMP29:%.*]] = insertelement <4 x i32> [[TMP25]], i32 [[TMP28]], i32 2 -; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE4]] -; CHECK: pred.load.continue4: -; CHECK-NEXT: [[TMP30:%.*]] = phi <4 x i32> [ [[TMP25]], [[PRED_LOAD_CONTINUE2]] ], [ [[TMP29]], [[PRED_LOAD_IF3]] ] -; CHECK-NEXT: [[TMP31:%.*]] = extractelement <4 x i1> [[TMP15]], i32 3 -; CHECK-NEXT: br i1 [[TMP31]], label [[PRED_LOAD_IF5:%.*]], label [[PRED_LOAD_CONTINUE6]] -; CHECK: pred.load.if5: -; CHECK-NEXT: [[TMP32:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP3]] -; CHECK-NEXT: [[TMP33:%.*]] = load i32, ptr [[TMP32]], align 4 -; CHECK-NEXT: [[TMP34:%.*]] = insertelement <4 x i32> [[TMP30]], i32 [[TMP33]], i32 3 -; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE6]] -; CHECK: pred.load.continue6: -; CHECK-NEXT: [[TMP35:%.*]] = phi <4 x i32> [ [[TMP30]], [[PRED_LOAD_CONTINUE4]] ], [ [[TMP34]], [[PRED_LOAD_IF5]] ] -; CHECK-NEXT: [[TMP36:%.*]] = xor <4 x i1> [[TMP15]], -; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP15]], <4 x i32> [[TMP35]], <4 x i32> zeroinitializer -; CHECK-NEXT: [[TMP37]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]] -; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 -; CHECK-NEXT: [[TMP38:%.*]] = icmp eq i64 [[INDEX_NEXT]], 52 -; CHECK-NEXT: br i1 [[TMP38]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP36:![0-9]+]] +; CHECK-NEXT: [[TMP68:%.*]] = phi <4 x i32> [ poison, [[VECTOR_BODY]] ], [ [[TMP67]], [[PRED_LOAD_IF]] ] +; CHECK-NEXT: [[TMP69:%.*]] = extractelement <4 x i1> [[TMP39]], i32 1 +; CHECK-NEXT: br i1 [[TMP69]], label [[PRED_LOAD_IF4:%.*]], label [[PRED_LOAD_CONTINUE5:%.*]] +; CHECK: pred.load.if4: +; CHECK-NEXT: [[TMP70:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP71:%.*]] = load i32, ptr [[TMP70]], align 4 +; CHECK-NEXT: [[TMP72:%.*]] = insertelement <4 x i32> [[TMP68]], i32 [[TMP71]], i32 1 +; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE5]] +; CHECK: pred.load.continue5: +; CHECK-NEXT: [[TMP73:%.*]] = phi <4 x i32> [ [[TMP68]], [[PRED_LOAD_CONTINUE]] ], [ [[TMP72]], [[PRED_LOAD_IF4]] ] +; CHECK-NEXT: [[TMP74:%.*]] = extractelement <4 x i1> [[TMP39]], i32 2 +; CHECK-NEXT: br i1 [[TMP74]], label [[PRED_LOAD_IF6:%.*]], label [[PRED_LOAD_CONTINUE7:%.*]] +; CHECK: pred.load.if6: +; CHECK-NEXT: [[TMP75:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP2]] +; CHECK-NEXT: [[TMP76:%.*]] = load i32, ptr [[TMP75]], align 4 +; CHECK-NEXT: [[TMP77:%.*]] = insertelement <4 x i32> [[TMP73]], i32 [[TMP76]], i32 2 +; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE7]] +; CHECK: pred.load.continue7: +; CHECK-NEXT: [[TMP78:%.*]] = phi <4 x i32> [ [[TMP73]], [[PRED_LOAD_CONTINUE5]] ], [ [[TMP77]], [[PRED_LOAD_IF6]] ] +; CHECK-NEXT: [[TMP79:%.*]] = extractelement <4 x i1> [[TMP39]], i32 3 +; CHECK-NEXT: br i1 [[TMP79]], label [[PRED_LOAD_IF8:%.*]], label [[PRED_LOAD_CONTINUE9:%.*]] +; CHECK: pred.load.if8: +; CHECK-NEXT: [[TMP80:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP3]] +; CHECK-NEXT: [[TMP81:%.*]] = load i32, ptr [[TMP80]], align 4 +; CHECK-NEXT: [[TMP82:%.*]] = insertelement <4 x i32> [[TMP78]], i32 [[TMP81]], i32 3 +; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE9]] +; CHECK: pred.load.continue9: +; CHECK-NEXT: [[TMP83:%.*]] = phi <4 x i32> [ [[TMP78]], [[PRED_LOAD_CONTINUE7]] ], [ [[TMP82]], [[PRED_LOAD_IF8]] ] +; CHECK-NEXT: [[TMP84:%.*]] = extractelement <4 x i1> [[TMP47]], i32 0 +; CHECK-NEXT: br i1 [[TMP84]], label [[PRED_LOAD_IF10:%.*]], label [[PRED_LOAD_CONTINUE11:%.*]] +; CHECK: pred.load.if10: +; CHECK-NEXT: [[TMP85:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP4]] +; CHECK-NEXT: [[TMP86:%.*]] = load i32, ptr [[TMP85]], align 4 +; CHECK-NEXT: [[TMP87:%.*]] = insertelement <4 x i32> poison, i32 [[TMP86]], i32 0 +; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE11]] +; CHECK: pred.load.continue11: +; CHECK-NEXT: [[TMP88:%.*]] = phi <4 x i32> [ poison, [[PRED_LOAD_CONTINUE9]] ], [ [[TMP87]], [[PRED_LOAD_IF10]] ] +; CHECK-NEXT: [[TMP89:%.*]] = extractelement <4 x i1> [[TMP47]], i32 1 +; CHECK-NEXT: br i1 [[TMP89]], label [[PRED_LOAD_IF12:%.*]], label [[PRED_LOAD_CONTINUE13:%.*]] +; CHECK: pred.load.if12: +; CHECK-NEXT: [[TMP90:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP5]] +; CHECK-NEXT: [[TMP91:%.*]] = load i32, ptr [[TMP90]], align 4 +; CHECK-NEXT: [[TMP92:%.*]] = insertelement <4 x i32> [[TMP88]], i32 [[TMP91]], i32 1 +; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE13]] +; CHECK: pred.load.continue13: +; CHECK-NEXT: [[TMP93:%.*]] = phi <4 x i32> [ [[TMP88]], [[PRED_LOAD_CONTINUE11]] ], [ [[TMP92]], [[PRED_LOAD_IF12]] ] +; CHECK-NEXT: [[TMP94:%.*]] = extractelement <4 x i1> [[TMP47]], i32 2 +; CHECK-NEXT: br i1 [[TMP94]], label [[PRED_LOAD_IF14:%.*]], label [[PRED_LOAD_CONTINUE15:%.*]] +; CHECK: pred.load.if14: +; CHECK-NEXT: [[TMP95:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP6]] +; CHECK-NEXT: [[TMP96:%.*]] = load i32, ptr [[TMP95]], align 4 +; CHECK-NEXT: [[TMP97:%.*]] = insertelement <4 x i32> [[TMP93]], i32 [[TMP96]], i32 2 +; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE15]] +; CHECK: pred.load.continue15: +; CHECK-NEXT: [[TMP98:%.*]] = phi <4 x i32> [ [[TMP93]], [[PRED_LOAD_CONTINUE13]] ], [ [[TMP97]], [[PRED_LOAD_IF14]] ] +; CHECK-NEXT: [[TMP99:%.*]] = extractelement <4 x i1> [[TMP47]], i32 3 +; CHECK-NEXT: br i1 [[TMP99]], label [[PRED_LOAD_IF16:%.*]], label [[PRED_LOAD_CONTINUE17:%.*]] +; CHECK: pred.load.if16: +; CHECK-NEXT: [[TMP100:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP7]] +; CHECK-NEXT: [[TMP101:%.*]] = load i32, ptr [[TMP100]], align 4 +; CHECK-NEXT: [[TMP102:%.*]] = insertelement <4 x i32> [[TMP98]], i32 [[TMP101]], i32 3 +; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE17]] +; CHECK: pred.load.continue17: +; CHECK-NEXT: [[TMP103:%.*]] = phi <4 x i32> [ [[TMP98]], [[PRED_LOAD_CONTINUE15]] ], [ [[TMP102]], [[PRED_LOAD_IF16]] ] +; CHECK-NEXT: [[TMP104:%.*]] = extractelement <4 x i1> [[TMP55]], i32 0 +; CHECK-NEXT: br i1 [[TMP104]], label [[PRED_LOAD_IF18:%.*]], label [[PRED_LOAD_CONTINUE19:%.*]] +; CHECK: pred.load.if18: +; CHECK-NEXT: [[TMP105:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP8]] +; CHECK-NEXT: [[TMP106:%.*]] = load i32, ptr [[TMP105]], align 4 +; CHECK-NEXT: [[TMP107:%.*]] = insertelement <4 x i32> poison, i32 [[TMP106]], i32 0 +; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE19]] +; CHECK: pred.load.continue19: +; CHECK-NEXT: [[TMP108:%.*]] = phi <4 x i32> [ poison, [[PRED_LOAD_CONTINUE17]] ], [ [[TMP107]], [[PRED_LOAD_IF18]] ] +; CHECK-NEXT: [[TMP109:%.*]] = extractelement <4 x i1> [[TMP55]], i32 1 +; CHECK-NEXT: br i1 [[TMP109]], label [[PRED_LOAD_IF20:%.*]], label [[PRED_LOAD_CONTINUE21:%.*]] +; CHECK: pred.load.if20: +; CHECK-NEXT: [[TMP110:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP9]] +; CHECK-NEXT: [[TMP111:%.*]] = load i32, ptr [[TMP110]], align 4 +; CHECK-NEXT: [[TMP112:%.*]] = insertelement <4 x i32> [[TMP108]], i32 [[TMP111]], i32 1 +; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE21]] +; CHECK: pred.load.continue21: +; CHECK-NEXT: [[TMP113:%.*]] = phi <4 x i32> [ [[TMP108]], [[PRED_LOAD_CONTINUE19]] ], [ [[TMP112]], [[PRED_LOAD_IF20]] ] +; CHECK-NEXT: [[TMP114:%.*]] = extractelement <4 x i1> [[TMP55]], i32 2 +; CHECK-NEXT: br i1 [[TMP114]], label [[PRED_LOAD_IF22:%.*]], label [[PRED_LOAD_CONTINUE23:%.*]] +; CHECK: pred.load.if22: +; CHECK-NEXT: [[TMP115:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP10]] +; CHECK-NEXT: [[TMP116:%.*]] = load i32, ptr [[TMP115]], align 4 +; CHECK-NEXT: [[TMP117:%.*]] = insertelement <4 x i32> [[TMP113]], i32 [[TMP116]], i32 2 +; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE23]] +; CHECK: pred.load.continue23: +; CHECK-NEXT: [[TMP118:%.*]] = phi <4 x i32> [ [[TMP113]], [[PRED_LOAD_CONTINUE21]] ], [ [[TMP117]], [[PRED_LOAD_IF22]] ] +; CHECK-NEXT: [[TMP119:%.*]] = extractelement <4 x i1> [[TMP55]], i32 3 +; CHECK-NEXT: br i1 [[TMP119]], label [[PRED_LOAD_IF24:%.*]], label [[PRED_LOAD_CONTINUE25:%.*]] +; CHECK: pred.load.if24: +; CHECK-NEXT: [[TMP120:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP11]] +; CHECK-NEXT: [[TMP121:%.*]] = load i32, ptr [[TMP120]], align 4 +; CHECK-NEXT: [[TMP122:%.*]] = insertelement <4 x i32> [[TMP118]], i32 [[TMP121]], i32 3 +; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE25]] +; CHECK: pred.load.continue25: +; CHECK-NEXT: [[TMP123:%.*]] = phi <4 x i32> [ [[TMP118]], [[PRED_LOAD_CONTINUE23]] ], [ [[TMP122]], [[PRED_LOAD_IF24]] ] +; CHECK-NEXT: [[TMP124:%.*]] = extractelement <4 x i1> [[TMP63]], i32 0 +; CHECK-NEXT: br i1 [[TMP124]], label [[PRED_LOAD_IF26:%.*]], label [[PRED_LOAD_CONTINUE27:%.*]] +; CHECK: pred.load.if26: +; CHECK-NEXT: [[TMP125:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP12]] +; CHECK-NEXT: [[TMP126:%.*]] = load i32, ptr [[TMP125]], align 4 +; CHECK-NEXT: [[TMP127:%.*]] = insertelement <4 x i32> poison, i32 [[TMP126]], i32 0 +; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE27]] +; CHECK: pred.load.continue27: +; CHECK-NEXT: [[TMP128:%.*]] = phi <4 x i32> [ poison, [[PRED_LOAD_CONTINUE25]] ], [ [[TMP127]], [[PRED_LOAD_IF26]] ] +; CHECK-NEXT: [[TMP129:%.*]] = extractelement <4 x i1> [[TMP63]], i32 1 +; CHECK-NEXT: br i1 [[TMP129]], label [[PRED_LOAD_IF28:%.*]], label [[PRED_LOAD_CONTINUE29:%.*]] +; CHECK: pred.load.if28: +; CHECK-NEXT: [[TMP130:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP13]] +; CHECK-NEXT: [[TMP131:%.*]] = load i32, ptr [[TMP130]], align 4 +; CHECK-NEXT: [[TMP132:%.*]] = insertelement <4 x i32> [[TMP128]], i32 [[TMP131]], i32 1 +; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE29]] +; CHECK: pred.load.continue29: +; CHECK-NEXT: [[TMP133:%.*]] = phi <4 x i32> [ [[TMP128]], [[PRED_LOAD_CONTINUE27]] ], [ [[TMP132]], [[PRED_LOAD_IF28]] ] +; CHECK-NEXT: [[TMP134:%.*]] = extractelement <4 x i1> [[TMP63]], i32 2 +; CHECK-NEXT: br i1 [[TMP134]], label [[PRED_LOAD_IF30:%.*]], label [[PRED_LOAD_CONTINUE31:%.*]] +; CHECK: pred.load.if30: +; CHECK-NEXT: [[TMP135:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP14]] +; CHECK-NEXT: [[TMP136:%.*]] = load i32, ptr [[TMP135]], align 4 +; CHECK-NEXT: [[TMP137:%.*]] = insertelement <4 x i32> [[TMP133]], i32 [[TMP136]], i32 2 +; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE31]] +; CHECK: pred.load.continue31: +; CHECK-NEXT: [[TMP138:%.*]] = phi <4 x i32> [ [[TMP133]], [[PRED_LOAD_CONTINUE29]] ], [ [[TMP137]], [[PRED_LOAD_IF30]] ] +; CHECK-NEXT: [[TMP139:%.*]] = extractelement <4 x i1> [[TMP63]], i32 3 +; CHECK-NEXT: br i1 [[TMP139]], label [[PRED_LOAD_IF32:%.*]], label [[PRED_LOAD_CONTINUE33]] +; CHECK: pred.load.if32: +; CHECK-NEXT: [[TMP140:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP15]] +; CHECK-NEXT: [[TMP141:%.*]] = load i32, ptr [[TMP140]], align 4 +; CHECK-NEXT: [[TMP142:%.*]] = insertelement <4 x i32> [[TMP138]], i32 [[TMP141]], i32 3 +; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE33]] +; CHECK: pred.load.continue33: +; CHECK-NEXT: [[TMP143:%.*]] = phi <4 x i32> [ [[TMP138]], [[PRED_LOAD_CONTINUE31]] ], [ [[TMP142]], [[PRED_LOAD_IF32]] ] +; CHECK-NEXT: [[TMP144:%.*]] = xor <4 x i1> [[TMP39]], +; CHECK-NEXT: [[TMP145:%.*]] = xor <4 x i1> [[TMP47]], +; CHECK-NEXT: [[TMP146:%.*]] = xor <4 x i1> [[TMP55]], +; CHECK-NEXT: [[TMP147:%.*]] = xor <4 x i1> [[TMP63]], +; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[TMP83]], <4 x i32> zeroinitializer +; CHECK-NEXT: [[PREDPHI34:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[TMP103]], <4 x i32> zeroinitializer +; CHECK-NEXT: [[PREDPHI35:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[TMP123]], <4 x i32> zeroinitializer +; CHECK-NEXT: [[PREDPHI36:%.*]] = select <4 x i1> [[TMP63]], <4 x i32> [[TMP143]], <4 x i32> zeroinitializer +; CHECK-NEXT: [[TMP148]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]] +; CHECK-NEXT: [[TMP149]] = add <4 x i32> [[VEC_PHI1]], [[PREDPHI34]] +; CHECK-NEXT: [[TMP150]] = add <4 x i32> [[VEC_PHI2]], [[PREDPHI35]] +; CHECK-NEXT: [[TMP151]] = add <4 x i32> [[VEC_PHI3]], [[PREDPHI36]] +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 +; CHECK-NEXT: [[TMP152:%.*]] = icmp eq i64 [[INDEX_NEXT]], 48 +; CHECK-NEXT: br i1 [[TMP152]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP36:![0-9]+]] ; CHECK: middle.block: -; CHECK-NEXT: [[TMP39:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP37]]) -; CHECK-NEXT: br i1 true, label [[LOOP_EXIT:%.*]], label [[SCALAR_PH]] +; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP149]], [[TMP148]] +; CHECK-NEXT: [[BIN_RDX37:%.*]] = add <4 x i32> [[TMP150]], [[BIN_RDX]] +; CHECK-NEXT: [[BIN_RDX38:%.*]] = add <4 x i32> [[TMP151]], [[BIN_RDX37]] +; CHECK-NEXT: [[TMP153:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX38]]) +; CHECK-NEXT: br i1 false, label [[LOOP_EXIT:%.*]], label [[SCALAR_PH]] ; CHECK: scalar.ph: -; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 104, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] -; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[TMP39]], [[MIDDLE_BLOCK]] ] +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 96, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] +; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[TMP153]], [[MIDDLE_BLOCK]] ] ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ] @@ -2885,7 +3287,7 @@ define i32 @neg_test_non_unit_stride_off_by_four_bytes(i64 %len, ptr %test_base) ; CHECK-NEXT: [[EXIT:%.*]] = icmp ugt i64 [[IV]], 100 ; CHECK-NEXT: br i1 [[EXIT]], label [[LOOP_EXIT]], label [[LOOP]], !llvm.loop [[LOOP37:![0-9]+]] ; CHECK: loop_exit: -; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[LATCH]] ], [ [[TMP39]], [[MIDDLE_BLOCK]] ] +; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[LATCH]] ], [ [[TMP153]], [[MIDDLE_BLOCK]] ] ; CHECK-NEXT: ret i32 [[ACCUM_NEXT_LCSSA]] ; entry: diff --git a/llvm/test/Transforms/LoopVectorize/X86/metadata-enable.ll b/llvm/test/Transforms/LoopVectorize/X86/metadata-enable.ll index cc36c2ba6f75..e76b8261515e 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/metadata-enable.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/metadata-enable.ll @@ -21,84 +21,84 @@ define i32 @enabled(ptr noalias nocapture %a, ptr noalias nocapture readonly %b, ; O1-NEXT: entry: ; O1-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[N:%.*]], i64 0 ; O1-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer -; O1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[B:%.*]], align 4 -; O1-NEXT: [[TMP0:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], [[BROADCAST_SPLAT]] -; O1-NEXT: store <4 x i32> [[TMP0]], ptr [[A:%.*]], align 4 -; O1-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 16 -; O1-NEXT: [[WIDE_LOAD_1:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4 -; O1-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_1]], [[BROADCAST_SPLAT]] -; O1-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 16 +; O1-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[B:%.*]], i64 16 +; O1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[B]], align 4 +; O1-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4 +; O1-NEXT: [[TMP1:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], [[BROADCAST_SPLAT]] +; O1-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1]], [[BROADCAST_SPLAT]] +; O1-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[A:%.*]], i64 16 +; O1-NEXT: store <4 x i32> [[TMP1]], ptr [[A]], align 4 ; O1-NEXT: store <4 x i32> [[TMP2]], ptr [[TMP3]], align 4 ; O1-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 32 -; O1-NEXT: [[WIDE_LOAD_2:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 -; O1-NEXT: [[TMP5:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_2]], [[BROADCAST_SPLAT]] -; O1-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 32 -; O1-NEXT: store <4 x i32> [[TMP5]], ptr [[TMP6]], align 4 -; O1-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 48 -; O1-NEXT: [[WIDE_LOAD_3:%.*]] = load <4 x i32>, ptr [[TMP7]], align 4 -; O1-NEXT: [[TMP8:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_3]], [[BROADCAST_SPLAT]] +; O1-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 48 +; O1-NEXT: [[WIDE_LOAD_1:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 +; O1-NEXT: [[WIDE_LOAD1_1:%.*]] = load <4 x i32>, ptr [[TMP5]], align 4 +; O1-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_1]], [[BROADCAST_SPLAT]] +; O1-NEXT: [[TMP7:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_1]], [[BROADCAST_SPLAT]] +; O1-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 32 ; O1-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 48 -; O1-NEXT: store <4 x i32> [[TMP8]], ptr [[TMP9]], align 4 +; O1-NEXT: store <4 x i32> [[TMP6]], ptr [[TMP8]], align 4 +; O1-NEXT: store <4 x i32> [[TMP7]], ptr [[TMP9]], align 4 ; O1-NEXT: [[TMP10:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 64 -; O1-NEXT: [[WIDE_LOAD_4:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4 -; O1-NEXT: [[TMP11:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_4]], [[BROADCAST_SPLAT]] -; O1-NEXT: [[TMP12:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 64 -; O1-NEXT: store <4 x i32> [[TMP11]], ptr [[TMP12]], align 4 -; O1-NEXT: [[TMP13:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 80 -; O1-NEXT: [[WIDE_LOAD_5:%.*]] = load <4 x i32>, ptr [[TMP13]], align 4 -; O1-NEXT: [[TMP14:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_5]], [[BROADCAST_SPLAT]] +; O1-NEXT: [[TMP11:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 80 +; O1-NEXT: [[WIDE_LOAD_2:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4 +; O1-NEXT: [[WIDE_LOAD1_2:%.*]] = load <4 x i32>, ptr [[TMP11]], align 4 +; O1-NEXT: [[TMP12:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_2]], [[BROADCAST_SPLAT]] +; O1-NEXT: [[TMP13:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_2]], [[BROADCAST_SPLAT]] +; O1-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 64 ; O1-NEXT: [[TMP15:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 80 -; O1-NEXT: store <4 x i32> [[TMP14]], ptr [[TMP15]], align 4 +; O1-NEXT: store <4 x i32> [[TMP12]], ptr [[TMP14]], align 4 +; O1-NEXT: store <4 x i32> [[TMP13]], ptr [[TMP15]], align 4 ; O1-NEXT: [[TMP16:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 96 -; O1-NEXT: [[WIDE_LOAD_6:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4 -; O1-NEXT: [[TMP17:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_6]], [[BROADCAST_SPLAT]] -; O1-NEXT: [[TMP18:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 96 -; O1-NEXT: store <4 x i32> [[TMP17]], ptr [[TMP18]], align 4 -; O1-NEXT: [[TMP19:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 112 -; O1-NEXT: [[WIDE_LOAD_7:%.*]] = load <4 x i32>, ptr [[TMP19]], align 4 -; O1-NEXT: [[TMP20:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_7]], [[BROADCAST_SPLAT]] +; O1-NEXT: [[TMP17:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 112 +; O1-NEXT: [[WIDE_LOAD_3:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4 +; O1-NEXT: [[WIDE_LOAD1_3:%.*]] = load <4 x i32>, ptr [[TMP17]], align 4 +; O1-NEXT: [[TMP18:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_3]], [[BROADCAST_SPLAT]] +; O1-NEXT: [[TMP19:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_3]], [[BROADCAST_SPLAT]] +; O1-NEXT: [[TMP20:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 96 ; O1-NEXT: [[TMP21:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 112 -; O1-NEXT: store <4 x i32> [[TMP20]], ptr [[TMP21]], align 4 +; O1-NEXT: store <4 x i32> [[TMP18]], ptr [[TMP20]], align 4 +; O1-NEXT: store <4 x i32> [[TMP19]], ptr [[TMP21]], align 4 ; O1-NEXT: [[TMP22:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 128 -; O1-NEXT: [[WIDE_LOAD_8:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4 -; O1-NEXT: [[TMP23:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_8]], [[BROADCAST_SPLAT]] -; O1-NEXT: [[TMP24:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 128 -; O1-NEXT: store <4 x i32> [[TMP23]], ptr [[TMP24]], align 4 -; O1-NEXT: [[TMP25:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 144 -; O1-NEXT: [[WIDE_LOAD_9:%.*]] = load <4 x i32>, ptr [[TMP25]], align 4 -; O1-NEXT: [[TMP26:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_9]], [[BROADCAST_SPLAT]] +; O1-NEXT: [[TMP23:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 144 +; O1-NEXT: [[WIDE_LOAD_4:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4 +; O1-NEXT: [[WIDE_LOAD1_4:%.*]] = load <4 x i32>, ptr [[TMP23]], align 4 +; O1-NEXT: [[TMP24:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_4]], [[BROADCAST_SPLAT]] +; O1-NEXT: [[TMP25:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_4]], [[BROADCAST_SPLAT]] +; O1-NEXT: [[TMP26:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 128 ; O1-NEXT: [[TMP27:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 144 -; O1-NEXT: store <4 x i32> [[TMP26]], ptr [[TMP27]], align 4 +; O1-NEXT: store <4 x i32> [[TMP24]], ptr [[TMP26]], align 4 +; O1-NEXT: store <4 x i32> [[TMP25]], ptr [[TMP27]], align 4 ; O1-NEXT: [[TMP28:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 160 -; O1-NEXT: [[WIDE_LOAD_10:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4 -; O1-NEXT: [[TMP29:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_10]], [[BROADCAST_SPLAT]] -; O1-NEXT: [[TMP30:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 160 -; O1-NEXT: store <4 x i32> [[TMP29]], ptr [[TMP30]], align 4 -; O1-NEXT: [[TMP31:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 176 -; O1-NEXT: [[WIDE_LOAD_11:%.*]] = load <4 x i32>, ptr [[TMP31]], align 4 -; O1-NEXT: [[TMP32:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_11]], [[BROADCAST_SPLAT]] +; O1-NEXT: [[TMP29:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 176 +; O1-NEXT: [[WIDE_LOAD_5:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4 +; O1-NEXT: [[WIDE_LOAD1_5:%.*]] = load <4 x i32>, ptr [[TMP29]], align 4 +; O1-NEXT: [[TMP30:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_5]], [[BROADCAST_SPLAT]] +; O1-NEXT: [[TMP31:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_5]], [[BROADCAST_SPLAT]] +; O1-NEXT: [[TMP32:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 160 ; O1-NEXT: [[TMP33:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 176 -; O1-NEXT: store <4 x i32> [[TMP32]], ptr [[TMP33]], align 4 +; O1-NEXT: store <4 x i32> [[TMP30]], ptr [[TMP32]], align 4 +; O1-NEXT: store <4 x i32> [[TMP31]], ptr [[TMP33]], align 4 ; O1-NEXT: [[TMP34:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 192 -; O1-NEXT: [[WIDE_LOAD_12:%.*]] = load <4 x i32>, ptr [[TMP34]], align 4 -; O1-NEXT: [[TMP35:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_12]], [[BROADCAST_SPLAT]] -; O1-NEXT: [[TMP36:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 192 -; O1-NEXT: store <4 x i32> [[TMP35]], ptr [[TMP36]], align 4 -; O1-NEXT: [[TMP37:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 208 -; O1-NEXT: [[WIDE_LOAD_13:%.*]] = load <4 x i32>, ptr [[TMP37]], align 4 -; O1-NEXT: [[TMP38:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_13]], [[BROADCAST_SPLAT]] +; O1-NEXT: [[TMP35:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 208 +; O1-NEXT: [[WIDE_LOAD_6:%.*]] = load <4 x i32>, ptr [[TMP34]], align 4 +; O1-NEXT: [[WIDE_LOAD1_6:%.*]] = load <4 x i32>, ptr [[TMP35]], align 4 +; O1-NEXT: [[TMP36:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_6]], [[BROADCAST_SPLAT]] +; O1-NEXT: [[TMP37:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_6]], [[BROADCAST_SPLAT]] +; O1-NEXT: [[TMP38:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 192 ; O1-NEXT: [[TMP39:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 208 -; O1-NEXT: store <4 x i32> [[TMP38]], ptr [[TMP39]], align 4 +; O1-NEXT: store <4 x i32> [[TMP36]], ptr [[TMP38]], align 4 +; O1-NEXT: store <4 x i32> [[TMP37]], ptr [[TMP39]], align 4 ; O1-NEXT: [[TMP40:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 224 -; O1-NEXT: [[WIDE_LOAD_14:%.*]] = load <4 x i32>, ptr [[TMP40]], align 4 -; O1-NEXT: [[TMP41:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_14]], [[BROADCAST_SPLAT]] -; O1-NEXT: [[TMP42:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 224 -; O1-NEXT: store <4 x i32> [[TMP41]], ptr [[TMP42]], align 4 -; O1-NEXT: [[TMP43:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 240 -; O1-NEXT: [[WIDE_LOAD_15:%.*]] = load <4 x i32>, ptr [[TMP43]], align 4 -; O1-NEXT: [[TMP44:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_15]], [[BROADCAST_SPLAT]] +; O1-NEXT: [[TMP41:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 240 +; O1-NEXT: [[WIDE_LOAD_7:%.*]] = load <4 x i32>, ptr [[TMP40]], align 4 +; O1-NEXT: [[WIDE_LOAD1_7:%.*]] = load <4 x i32>, ptr [[TMP41]], align 4 +; O1-NEXT: [[TMP42:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_7]], [[BROADCAST_SPLAT]] +; O1-NEXT: [[TMP43:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_7]], [[BROADCAST_SPLAT]] +; O1-NEXT: [[TMP44:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 224 ; O1-NEXT: [[TMP45:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 240 -; O1-NEXT: store <4 x i32> [[TMP44]], ptr [[TMP45]], align 4 +; O1-NEXT: store <4 x i32> [[TMP42]], ptr [[TMP44]], align 4 +; O1-NEXT: store <4 x i32> [[TMP43]], ptr [[TMP45]], align 4 ; O1-NEXT: [[TMP46:%.*]] = load i32, ptr [[A]], align 4 ; O1-NEXT: ret i32 [[TMP46]] ; @@ -106,84 +106,84 @@ define i32 @enabled(ptr noalias nocapture %a, ptr noalias nocapture readonly %b, ; O2-NEXT: entry: ; O2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[N:%.*]], i64 0 ; O2-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer -; O2-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[B:%.*]], align 4 -; O2-NEXT: [[TMP0:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], [[BROADCAST_SPLAT]] -; O2-NEXT: store <4 x i32> [[TMP0]], ptr [[A:%.*]], align 4 -; O2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 16 -; O2-NEXT: [[WIDE_LOAD_1:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4 -; O2-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_1]], [[BROADCAST_SPLAT]] -; O2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 16 +; O2-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[B:%.*]], i64 16 +; O2-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[B]], align 4 +; O2-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4 +; O2-NEXT: [[TMP1:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[A:%.*]], i64 16 +; O2-NEXT: store <4 x i32> [[TMP1]], ptr [[A]], align 4 ; O2-NEXT: store <4 x i32> [[TMP2]], ptr [[TMP3]], align 4 ; O2-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 32 -; O2-NEXT: [[WIDE_LOAD_2:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 -; O2-NEXT: [[TMP5:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_2]], [[BROADCAST_SPLAT]] -; O2-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 32 -; O2-NEXT: store <4 x i32> [[TMP5]], ptr [[TMP6]], align 4 -; O2-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 48 -; O2-NEXT: [[WIDE_LOAD_3:%.*]] = load <4 x i32>, ptr [[TMP7]], align 4 -; O2-NEXT: [[TMP8:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_3]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 48 +; O2-NEXT: [[WIDE_LOAD_1:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 +; O2-NEXT: [[WIDE_LOAD1_1:%.*]] = load <4 x i32>, ptr [[TMP5]], align 4 +; O2-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_1]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP7:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_1]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 32 ; O2-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 48 -; O2-NEXT: store <4 x i32> [[TMP8]], ptr [[TMP9]], align 4 +; O2-NEXT: store <4 x i32> [[TMP6]], ptr [[TMP8]], align 4 +; O2-NEXT: store <4 x i32> [[TMP7]], ptr [[TMP9]], align 4 ; O2-NEXT: [[TMP10:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 64 -; O2-NEXT: [[WIDE_LOAD_4:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4 -; O2-NEXT: [[TMP11:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_4]], [[BROADCAST_SPLAT]] -; O2-NEXT: [[TMP12:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 64 -; O2-NEXT: store <4 x i32> [[TMP11]], ptr [[TMP12]], align 4 -; O2-NEXT: [[TMP13:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 80 -; O2-NEXT: [[WIDE_LOAD_5:%.*]] = load <4 x i32>, ptr [[TMP13]], align 4 -; O2-NEXT: [[TMP14:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_5]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP11:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 80 +; O2-NEXT: [[WIDE_LOAD_2:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4 +; O2-NEXT: [[WIDE_LOAD1_2:%.*]] = load <4 x i32>, ptr [[TMP11]], align 4 +; O2-NEXT: [[TMP12:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_2]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP13:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_2]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 64 ; O2-NEXT: [[TMP15:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 80 -; O2-NEXT: store <4 x i32> [[TMP14]], ptr [[TMP15]], align 4 +; O2-NEXT: store <4 x i32> [[TMP12]], ptr [[TMP14]], align 4 +; O2-NEXT: store <4 x i32> [[TMP13]], ptr [[TMP15]], align 4 ; O2-NEXT: [[TMP16:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 96 -; O2-NEXT: [[WIDE_LOAD_6:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4 -; O2-NEXT: [[TMP17:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_6]], [[BROADCAST_SPLAT]] -; O2-NEXT: [[TMP18:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 96 -; O2-NEXT: store <4 x i32> [[TMP17]], ptr [[TMP18]], align 4 -; O2-NEXT: [[TMP19:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 112 -; O2-NEXT: [[WIDE_LOAD_7:%.*]] = load <4 x i32>, ptr [[TMP19]], align 4 -; O2-NEXT: [[TMP20:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_7]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP17:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 112 +; O2-NEXT: [[WIDE_LOAD_3:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4 +; O2-NEXT: [[WIDE_LOAD1_3:%.*]] = load <4 x i32>, ptr [[TMP17]], align 4 +; O2-NEXT: [[TMP18:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_3]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP19:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_3]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP20:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 96 ; O2-NEXT: [[TMP21:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 112 -; O2-NEXT: store <4 x i32> [[TMP20]], ptr [[TMP21]], align 4 +; O2-NEXT: store <4 x i32> [[TMP18]], ptr [[TMP20]], align 4 +; O2-NEXT: store <4 x i32> [[TMP19]], ptr [[TMP21]], align 4 ; O2-NEXT: [[TMP22:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 128 -; O2-NEXT: [[WIDE_LOAD_8:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4 -; O2-NEXT: [[TMP23:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_8]], [[BROADCAST_SPLAT]] -; O2-NEXT: [[TMP24:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 128 -; O2-NEXT: store <4 x i32> [[TMP23]], ptr [[TMP24]], align 4 -; O2-NEXT: [[TMP25:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 144 -; O2-NEXT: [[WIDE_LOAD_9:%.*]] = load <4 x i32>, ptr [[TMP25]], align 4 -; O2-NEXT: [[TMP26:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_9]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP23:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 144 +; O2-NEXT: [[WIDE_LOAD_4:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4 +; O2-NEXT: [[WIDE_LOAD1_4:%.*]] = load <4 x i32>, ptr [[TMP23]], align 4 +; O2-NEXT: [[TMP24:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_4]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP25:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_4]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP26:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 128 ; O2-NEXT: [[TMP27:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 144 -; O2-NEXT: store <4 x i32> [[TMP26]], ptr [[TMP27]], align 4 +; O2-NEXT: store <4 x i32> [[TMP24]], ptr [[TMP26]], align 4 +; O2-NEXT: store <4 x i32> [[TMP25]], ptr [[TMP27]], align 4 ; O2-NEXT: [[TMP28:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 160 -; O2-NEXT: [[WIDE_LOAD_10:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4 -; O2-NEXT: [[TMP29:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_10]], [[BROADCAST_SPLAT]] -; O2-NEXT: [[TMP30:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 160 -; O2-NEXT: store <4 x i32> [[TMP29]], ptr [[TMP30]], align 4 -; O2-NEXT: [[TMP31:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 176 -; O2-NEXT: [[WIDE_LOAD_11:%.*]] = load <4 x i32>, ptr [[TMP31]], align 4 -; O2-NEXT: [[TMP32:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_11]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP29:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 176 +; O2-NEXT: [[WIDE_LOAD_5:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4 +; O2-NEXT: [[WIDE_LOAD1_5:%.*]] = load <4 x i32>, ptr [[TMP29]], align 4 +; O2-NEXT: [[TMP30:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_5]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP31:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_5]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP32:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 160 ; O2-NEXT: [[TMP33:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 176 -; O2-NEXT: store <4 x i32> [[TMP32]], ptr [[TMP33]], align 4 +; O2-NEXT: store <4 x i32> [[TMP30]], ptr [[TMP32]], align 4 +; O2-NEXT: store <4 x i32> [[TMP31]], ptr [[TMP33]], align 4 ; O2-NEXT: [[TMP34:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 192 -; O2-NEXT: [[WIDE_LOAD_12:%.*]] = load <4 x i32>, ptr [[TMP34]], align 4 -; O2-NEXT: [[TMP35:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_12]], [[BROADCAST_SPLAT]] -; O2-NEXT: [[TMP36:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 192 -; O2-NEXT: store <4 x i32> [[TMP35]], ptr [[TMP36]], align 4 -; O2-NEXT: [[TMP37:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 208 -; O2-NEXT: [[WIDE_LOAD_13:%.*]] = load <4 x i32>, ptr [[TMP37]], align 4 -; O2-NEXT: [[TMP38:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_13]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP35:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 208 +; O2-NEXT: [[WIDE_LOAD_6:%.*]] = load <4 x i32>, ptr [[TMP34]], align 4 +; O2-NEXT: [[WIDE_LOAD1_6:%.*]] = load <4 x i32>, ptr [[TMP35]], align 4 +; O2-NEXT: [[TMP36:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_6]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP37:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_6]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP38:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 192 ; O2-NEXT: [[TMP39:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 208 -; O2-NEXT: store <4 x i32> [[TMP38]], ptr [[TMP39]], align 4 +; O2-NEXT: store <4 x i32> [[TMP36]], ptr [[TMP38]], align 4 +; O2-NEXT: store <4 x i32> [[TMP37]], ptr [[TMP39]], align 4 ; O2-NEXT: [[TMP40:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 224 -; O2-NEXT: [[WIDE_LOAD_14:%.*]] = load <4 x i32>, ptr [[TMP40]], align 4 -; O2-NEXT: [[TMP41:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_14]], [[BROADCAST_SPLAT]] -; O2-NEXT: [[TMP42:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 224 -; O2-NEXT: store <4 x i32> [[TMP41]], ptr [[TMP42]], align 4 -; O2-NEXT: [[TMP43:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 240 -; O2-NEXT: [[WIDE_LOAD_15:%.*]] = load <4 x i32>, ptr [[TMP43]], align 4 -; O2-NEXT: [[TMP44:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_15]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP41:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 240 +; O2-NEXT: [[WIDE_LOAD_7:%.*]] = load <4 x i32>, ptr [[TMP40]], align 4 +; O2-NEXT: [[WIDE_LOAD1_7:%.*]] = load <4 x i32>, ptr [[TMP41]], align 4 +; O2-NEXT: [[TMP42:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_7]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP43:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_7]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP44:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 224 ; O2-NEXT: [[TMP45:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 240 -; O2-NEXT: store <4 x i32> [[TMP44]], ptr [[TMP45]], align 4 +; O2-NEXT: store <4 x i32> [[TMP42]], ptr [[TMP44]], align 4 +; O2-NEXT: store <4 x i32> [[TMP43]], ptr [[TMP45]], align 4 ; O2-NEXT: [[TMP46:%.*]] = load i32, ptr [[A]], align 4 ; O2-NEXT: ret i32 [[TMP46]] ; @@ -191,84 +191,84 @@ define i32 @enabled(ptr noalias nocapture %a, ptr noalias nocapture readonly %b, ; O3-NEXT: entry: ; O3-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[N:%.*]], i64 0 ; O3-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer -; O3-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[B:%.*]], align 4 -; O3-NEXT: [[TMP0:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], [[BROADCAST_SPLAT]] -; O3-NEXT: store <4 x i32> [[TMP0]], ptr [[A:%.*]], align 4 -; O3-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 16 -; O3-NEXT: [[WIDE_LOAD_1:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4 -; O3-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_1]], [[BROADCAST_SPLAT]] -; O3-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 16 +; O3-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[B:%.*]], i64 16 +; O3-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[B]], align 4 +; O3-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4 +; O3-NEXT: [[TMP1:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[A:%.*]], i64 16 +; O3-NEXT: store <4 x i32> [[TMP1]], ptr [[A]], align 4 ; O3-NEXT: store <4 x i32> [[TMP2]], ptr [[TMP3]], align 4 ; O3-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 32 -; O3-NEXT: [[WIDE_LOAD_2:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 -; O3-NEXT: [[TMP5:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_2]], [[BROADCAST_SPLAT]] -; O3-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 32 -; O3-NEXT: store <4 x i32> [[TMP5]], ptr [[TMP6]], align 4 -; O3-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 48 -; O3-NEXT: [[WIDE_LOAD_3:%.*]] = load <4 x i32>, ptr [[TMP7]], align 4 -; O3-NEXT: [[TMP8:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_3]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 48 +; O3-NEXT: [[WIDE_LOAD_1:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 +; O3-NEXT: [[WIDE_LOAD1_1:%.*]] = load <4 x i32>, ptr [[TMP5]], align 4 +; O3-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_1]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP7:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_1]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 32 ; O3-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 48 -; O3-NEXT: store <4 x i32> [[TMP8]], ptr [[TMP9]], align 4 +; O3-NEXT: store <4 x i32> [[TMP6]], ptr [[TMP8]], align 4 +; O3-NEXT: store <4 x i32> [[TMP7]], ptr [[TMP9]], align 4 ; O3-NEXT: [[TMP10:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 64 -; O3-NEXT: [[WIDE_LOAD_4:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4 -; O3-NEXT: [[TMP11:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_4]], [[BROADCAST_SPLAT]] -; O3-NEXT: [[TMP12:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 64 -; O3-NEXT: store <4 x i32> [[TMP11]], ptr [[TMP12]], align 4 -; O3-NEXT: [[TMP13:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 80 -; O3-NEXT: [[WIDE_LOAD_5:%.*]] = load <4 x i32>, ptr [[TMP13]], align 4 -; O3-NEXT: [[TMP14:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_5]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP11:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 80 +; O3-NEXT: [[WIDE_LOAD_2:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4 +; O3-NEXT: [[WIDE_LOAD1_2:%.*]] = load <4 x i32>, ptr [[TMP11]], align 4 +; O3-NEXT: [[TMP12:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_2]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP13:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_2]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 64 ; O3-NEXT: [[TMP15:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 80 -; O3-NEXT: store <4 x i32> [[TMP14]], ptr [[TMP15]], align 4 +; O3-NEXT: store <4 x i32> [[TMP12]], ptr [[TMP14]], align 4 +; O3-NEXT: store <4 x i32> [[TMP13]], ptr [[TMP15]], align 4 ; O3-NEXT: [[TMP16:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 96 -; O3-NEXT: [[WIDE_LOAD_6:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4 -; O3-NEXT: [[TMP17:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_6]], [[BROADCAST_SPLAT]] -; O3-NEXT: [[TMP18:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 96 -; O3-NEXT: store <4 x i32> [[TMP17]], ptr [[TMP18]], align 4 -; O3-NEXT: [[TMP19:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 112 -; O3-NEXT: [[WIDE_LOAD_7:%.*]] = load <4 x i32>, ptr [[TMP19]], align 4 -; O3-NEXT: [[TMP20:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_7]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP17:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 112 +; O3-NEXT: [[WIDE_LOAD_3:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4 +; O3-NEXT: [[WIDE_LOAD1_3:%.*]] = load <4 x i32>, ptr [[TMP17]], align 4 +; O3-NEXT: [[TMP18:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_3]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP19:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_3]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP20:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 96 ; O3-NEXT: [[TMP21:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 112 -; O3-NEXT: store <4 x i32> [[TMP20]], ptr [[TMP21]], align 4 +; O3-NEXT: store <4 x i32> [[TMP18]], ptr [[TMP20]], align 4 +; O3-NEXT: store <4 x i32> [[TMP19]], ptr [[TMP21]], align 4 ; O3-NEXT: [[TMP22:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 128 -; O3-NEXT: [[WIDE_LOAD_8:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4 -; O3-NEXT: [[TMP23:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_8]], [[BROADCAST_SPLAT]] -; O3-NEXT: [[TMP24:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 128 -; O3-NEXT: store <4 x i32> [[TMP23]], ptr [[TMP24]], align 4 -; O3-NEXT: [[TMP25:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 144 -; O3-NEXT: [[WIDE_LOAD_9:%.*]] = load <4 x i32>, ptr [[TMP25]], align 4 -; O3-NEXT: [[TMP26:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_9]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP23:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 144 +; O3-NEXT: [[WIDE_LOAD_4:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4 +; O3-NEXT: [[WIDE_LOAD1_4:%.*]] = load <4 x i32>, ptr [[TMP23]], align 4 +; O3-NEXT: [[TMP24:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_4]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP25:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_4]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP26:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 128 ; O3-NEXT: [[TMP27:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 144 -; O3-NEXT: store <4 x i32> [[TMP26]], ptr [[TMP27]], align 4 +; O3-NEXT: store <4 x i32> [[TMP24]], ptr [[TMP26]], align 4 +; O3-NEXT: store <4 x i32> [[TMP25]], ptr [[TMP27]], align 4 ; O3-NEXT: [[TMP28:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 160 -; O3-NEXT: [[WIDE_LOAD_10:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4 -; O3-NEXT: [[TMP29:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_10]], [[BROADCAST_SPLAT]] -; O3-NEXT: [[TMP30:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 160 -; O3-NEXT: store <4 x i32> [[TMP29]], ptr [[TMP30]], align 4 -; O3-NEXT: [[TMP31:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 176 -; O3-NEXT: [[WIDE_LOAD_11:%.*]] = load <4 x i32>, ptr [[TMP31]], align 4 -; O3-NEXT: [[TMP32:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_11]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP29:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 176 +; O3-NEXT: [[WIDE_LOAD_5:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4 +; O3-NEXT: [[WIDE_LOAD1_5:%.*]] = load <4 x i32>, ptr [[TMP29]], align 4 +; O3-NEXT: [[TMP30:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_5]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP31:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_5]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP32:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 160 ; O3-NEXT: [[TMP33:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 176 -; O3-NEXT: store <4 x i32> [[TMP32]], ptr [[TMP33]], align 4 +; O3-NEXT: store <4 x i32> [[TMP30]], ptr [[TMP32]], align 4 +; O3-NEXT: store <4 x i32> [[TMP31]], ptr [[TMP33]], align 4 ; O3-NEXT: [[TMP34:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 192 -; O3-NEXT: [[WIDE_LOAD_12:%.*]] = load <4 x i32>, ptr [[TMP34]], align 4 -; O3-NEXT: [[TMP35:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_12]], [[BROADCAST_SPLAT]] -; O3-NEXT: [[TMP36:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 192 -; O3-NEXT: store <4 x i32> [[TMP35]], ptr [[TMP36]], align 4 -; O3-NEXT: [[TMP37:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 208 -; O3-NEXT: [[WIDE_LOAD_13:%.*]] = load <4 x i32>, ptr [[TMP37]], align 4 -; O3-NEXT: [[TMP38:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_13]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP35:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 208 +; O3-NEXT: [[WIDE_LOAD_6:%.*]] = load <4 x i32>, ptr [[TMP34]], align 4 +; O3-NEXT: [[WIDE_LOAD1_6:%.*]] = load <4 x i32>, ptr [[TMP35]], align 4 +; O3-NEXT: [[TMP36:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_6]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP37:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_6]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP38:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 192 ; O3-NEXT: [[TMP39:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 208 -; O3-NEXT: store <4 x i32> [[TMP38]], ptr [[TMP39]], align 4 +; O3-NEXT: store <4 x i32> [[TMP36]], ptr [[TMP38]], align 4 +; O3-NEXT: store <4 x i32> [[TMP37]], ptr [[TMP39]], align 4 ; O3-NEXT: [[TMP40:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 224 -; O3-NEXT: [[WIDE_LOAD_14:%.*]] = load <4 x i32>, ptr [[TMP40]], align 4 -; O3-NEXT: [[TMP41:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_14]], [[BROADCAST_SPLAT]] -; O3-NEXT: [[TMP42:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 224 -; O3-NEXT: store <4 x i32> [[TMP41]], ptr [[TMP42]], align 4 -; O3-NEXT: [[TMP43:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 240 -; O3-NEXT: [[WIDE_LOAD_15:%.*]] = load <4 x i32>, ptr [[TMP43]], align 4 -; O3-NEXT: [[TMP44:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_15]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP41:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 240 +; O3-NEXT: [[WIDE_LOAD_7:%.*]] = load <4 x i32>, ptr [[TMP40]], align 4 +; O3-NEXT: [[WIDE_LOAD1_7:%.*]] = load <4 x i32>, ptr [[TMP41]], align 4 +; O3-NEXT: [[TMP42:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_7]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP43:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_7]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP44:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 224 ; O3-NEXT: [[TMP45:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 240 -; O3-NEXT: store <4 x i32> [[TMP44]], ptr [[TMP45]], align 4 +; O3-NEXT: store <4 x i32> [[TMP42]], ptr [[TMP44]], align 4 +; O3-NEXT: store <4 x i32> [[TMP43]], ptr [[TMP45]], align 4 ; O3-NEXT: [[TMP46:%.*]] = load i32, ptr [[A]], align 4 ; O3-NEXT: ret i32 [[TMP46]] ; @@ -276,84 +276,84 @@ define i32 @enabled(ptr noalias nocapture %a, ptr noalias nocapture readonly %b, ; O3DEFAULT-NEXT: entry: ; O3DEFAULT-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[N:%.*]], i64 0 ; O3DEFAULT-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer -; O3DEFAULT-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[B:%.*]], align 4 -; O3DEFAULT-NEXT: [[TMP0:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], [[BROADCAST_SPLAT]] -; O3DEFAULT-NEXT: store <4 x i32> [[TMP0]], ptr [[A:%.*]], align 4 -; O3DEFAULT-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 16 -; O3DEFAULT-NEXT: [[WIDE_LOAD_1:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4 -; O3DEFAULT-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_1]], [[BROADCAST_SPLAT]] -; O3DEFAULT-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 16 +; O3DEFAULT-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[B:%.*]], i64 16 +; O3DEFAULT-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[B]], align 4 +; O3DEFAULT-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4 +; O3DEFAULT-NEXT: [[TMP1:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[A:%.*]], i64 16 +; O3DEFAULT-NEXT: store <4 x i32> [[TMP1]], ptr [[A]], align 4 ; O3DEFAULT-NEXT: store <4 x i32> [[TMP2]], ptr [[TMP3]], align 4 ; O3DEFAULT-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 32 -; O3DEFAULT-NEXT: [[WIDE_LOAD_2:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 -; O3DEFAULT-NEXT: [[TMP5:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_2]], [[BROADCAST_SPLAT]] -; O3DEFAULT-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 32 -; O3DEFAULT-NEXT: store <4 x i32> [[TMP5]], ptr [[TMP6]], align 4 -; O3DEFAULT-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 48 -; O3DEFAULT-NEXT: [[WIDE_LOAD_3:%.*]] = load <4 x i32>, ptr [[TMP7]], align 4 -; O3DEFAULT-NEXT: [[TMP8:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_3]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 48 +; O3DEFAULT-NEXT: [[WIDE_LOAD_1:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 +; O3DEFAULT-NEXT: [[WIDE_LOAD1_1:%.*]] = load <4 x i32>, ptr [[TMP5]], align 4 +; O3DEFAULT-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_1]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP7:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_1]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 32 ; O3DEFAULT-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 48 -; O3DEFAULT-NEXT: store <4 x i32> [[TMP8]], ptr [[TMP9]], align 4 +; O3DEFAULT-NEXT: store <4 x i32> [[TMP6]], ptr [[TMP8]], align 4 +; O3DEFAULT-NEXT: store <4 x i32> [[TMP7]], ptr [[TMP9]], align 4 ; O3DEFAULT-NEXT: [[TMP10:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 64 -; O3DEFAULT-NEXT: [[WIDE_LOAD_4:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4 -; O3DEFAULT-NEXT: [[TMP11:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_4]], [[BROADCAST_SPLAT]] -; O3DEFAULT-NEXT: [[TMP12:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 64 -; O3DEFAULT-NEXT: store <4 x i32> [[TMP11]], ptr [[TMP12]], align 4 -; O3DEFAULT-NEXT: [[TMP13:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 80 -; O3DEFAULT-NEXT: [[WIDE_LOAD_5:%.*]] = load <4 x i32>, ptr [[TMP13]], align 4 -; O3DEFAULT-NEXT: [[TMP14:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_5]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP11:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 80 +; O3DEFAULT-NEXT: [[WIDE_LOAD_2:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4 +; O3DEFAULT-NEXT: [[WIDE_LOAD1_2:%.*]] = load <4 x i32>, ptr [[TMP11]], align 4 +; O3DEFAULT-NEXT: [[TMP12:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_2]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP13:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_2]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 64 ; O3DEFAULT-NEXT: [[TMP15:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 80 -; O3DEFAULT-NEXT: store <4 x i32> [[TMP14]], ptr [[TMP15]], align 4 +; O3DEFAULT-NEXT: store <4 x i32> [[TMP12]], ptr [[TMP14]], align 4 +; O3DEFAULT-NEXT: store <4 x i32> [[TMP13]], ptr [[TMP15]], align 4 ; O3DEFAULT-NEXT: [[TMP16:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 96 -; O3DEFAULT-NEXT: [[WIDE_LOAD_6:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4 -; O3DEFAULT-NEXT: [[TMP17:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_6]], [[BROADCAST_SPLAT]] -; O3DEFAULT-NEXT: [[TMP18:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 96 -; O3DEFAULT-NEXT: store <4 x i32> [[TMP17]], ptr [[TMP18]], align 4 -; O3DEFAULT-NEXT: [[TMP19:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 112 -; O3DEFAULT-NEXT: [[WIDE_LOAD_7:%.*]] = load <4 x i32>, ptr [[TMP19]], align 4 -; O3DEFAULT-NEXT: [[TMP20:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_7]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP17:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 112 +; O3DEFAULT-NEXT: [[WIDE_LOAD_3:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4 +; O3DEFAULT-NEXT: [[WIDE_LOAD1_3:%.*]] = load <4 x i32>, ptr [[TMP17]], align 4 +; O3DEFAULT-NEXT: [[TMP18:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_3]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP19:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_3]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP20:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 96 ; O3DEFAULT-NEXT: [[TMP21:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 112 -; O3DEFAULT-NEXT: store <4 x i32> [[TMP20]], ptr [[TMP21]], align 4 +; O3DEFAULT-NEXT: store <4 x i32> [[TMP18]], ptr [[TMP20]], align 4 +; O3DEFAULT-NEXT: store <4 x i32> [[TMP19]], ptr [[TMP21]], align 4 ; O3DEFAULT-NEXT: [[TMP22:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 128 -; O3DEFAULT-NEXT: [[WIDE_LOAD_8:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4 -; O3DEFAULT-NEXT: [[TMP23:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_8]], [[BROADCAST_SPLAT]] -; O3DEFAULT-NEXT: [[TMP24:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 128 -; O3DEFAULT-NEXT: store <4 x i32> [[TMP23]], ptr [[TMP24]], align 4 -; O3DEFAULT-NEXT: [[TMP25:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 144 -; O3DEFAULT-NEXT: [[WIDE_LOAD_9:%.*]] = load <4 x i32>, ptr [[TMP25]], align 4 -; O3DEFAULT-NEXT: [[TMP26:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_9]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP23:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 144 +; O3DEFAULT-NEXT: [[WIDE_LOAD_4:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4 +; O3DEFAULT-NEXT: [[WIDE_LOAD1_4:%.*]] = load <4 x i32>, ptr [[TMP23]], align 4 +; O3DEFAULT-NEXT: [[TMP24:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_4]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP25:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_4]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP26:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 128 ; O3DEFAULT-NEXT: [[TMP27:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 144 -; O3DEFAULT-NEXT: store <4 x i32> [[TMP26]], ptr [[TMP27]], align 4 +; O3DEFAULT-NEXT: store <4 x i32> [[TMP24]], ptr [[TMP26]], align 4 +; O3DEFAULT-NEXT: store <4 x i32> [[TMP25]], ptr [[TMP27]], align 4 ; O3DEFAULT-NEXT: [[TMP28:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 160 -; O3DEFAULT-NEXT: [[WIDE_LOAD_10:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4 -; O3DEFAULT-NEXT: [[TMP29:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_10]], [[BROADCAST_SPLAT]] -; O3DEFAULT-NEXT: [[TMP30:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 160 -; O3DEFAULT-NEXT: store <4 x i32> [[TMP29]], ptr [[TMP30]], align 4 -; O3DEFAULT-NEXT: [[TMP31:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 176 -; O3DEFAULT-NEXT: [[WIDE_LOAD_11:%.*]] = load <4 x i32>, ptr [[TMP31]], align 4 -; O3DEFAULT-NEXT: [[TMP32:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_11]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP29:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 176 +; O3DEFAULT-NEXT: [[WIDE_LOAD_5:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4 +; O3DEFAULT-NEXT: [[WIDE_LOAD1_5:%.*]] = load <4 x i32>, ptr [[TMP29]], align 4 +; O3DEFAULT-NEXT: [[TMP30:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_5]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP31:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_5]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP32:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 160 ; O3DEFAULT-NEXT: [[TMP33:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 176 -; O3DEFAULT-NEXT: store <4 x i32> [[TMP32]], ptr [[TMP33]], align 4 +; O3DEFAULT-NEXT: store <4 x i32> [[TMP30]], ptr [[TMP32]], align 4 +; O3DEFAULT-NEXT: store <4 x i32> [[TMP31]], ptr [[TMP33]], align 4 ; O3DEFAULT-NEXT: [[TMP34:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 192 -; O3DEFAULT-NEXT: [[WIDE_LOAD_12:%.*]] = load <4 x i32>, ptr [[TMP34]], align 4 -; O3DEFAULT-NEXT: [[TMP35:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_12]], [[BROADCAST_SPLAT]] -; O3DEFAULT-NEXT: [[TMP36:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 192 -; O3DEFAULT-NEXT: store <4 x i32> [[TMP35]], ptr [[TMP36]], align 4 -; O3DEFAULT-NEXT: [[TMP37:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 208 -; O3DEFAULT-NEXT: [[WIDE_LOAD_13:%.*]] = load <4 x i32>, ptr [[TMP37]], align 4 -; O3DEFAULT-NEXT: [[TMP38:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_13]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP35:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 208 +; O3DEFAULT-NEXT: [[WIDE_LOAD_6:%.*]] = load <4 x i32>, ptr [[TMP34]], align 4 +; O3DEFAULT-NEXT: [[WIDE_LOAD1_6:%.*]] = load <4 x i32>, ptr [[TMP35]], align 4 +; O3DEFAULT-NEXT: [[TMP36:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_6]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP37:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_6]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP38:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 192 ; O3DEFAULT-NEXT: [[TMP39:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 208 -; O3DEFAULT-NEXT: store <4 x i32> [[TMP38]], ptr [[TMP39]], align 4 +; O3DEFAULT-NEXT: store <4 x i32> [[TMP36]], ptr [[TMP38]], align 4 +; O3DEFAULT-NEXT: store <4 x i32> [[TMP37]], ptr [[TMP39]], align 4 ; O3DEFAULT-NEXT: [[TMP40:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 224 -; O3DEFAULT-NEXT: [[WIDE_LOAD_14:%.*]] = load <4 x i32>, ptr [[TMP40]], align 4 -; O3DEFAULT-NEXT: [[TMP41:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_14]], [[BROADCAST_SPLAT]] -; O3DEFAULT-NEXT: [[TMP42:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 224 -; O3DEFAULT-NEXT: store <4 x i32> [[TMP41]], ptr [[TMP42]], align 4 -; O3DEFAULT-NEXT: [[TMP43:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 240 -; O3DEFAULT-NEXT: [[WIDE_LOAD_15:%.*]] = load <4 x i32>, ptr [[TMP43]], align 4 -; O3DEFAULT-NEXT: [[TMP44:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_15]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP41:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 240 +; O3DEFAULT-NEXT: [[WIDE_LOAD_7:%.*]] = load <4 x i32>, ptr [[TMP40]], align 4 +; O3DEFAULT-NEXT: [[WIDE_LOAD1_7:%.*]] = load <4 x i32>, ptr [[TMP41]], align 4 +; O3DEFAULT-NEXT: [[TMP42:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_7]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP43:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_7]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP44:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 224 ; O3DEFAULT-NEXT: [[TMP45:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 240 -; O3DEFAULT-NEXT: store <4 x i32> [[TMP44]], ptr [[TMP45]], align 4 +; O3DEFAULT-NEXT: store <4 x i32> [[TMP42]], ptr [[TMP44]], align 4 +; O3DEFAULT-NEXT: store <4 x i32> [[TMP43]], ptr [[TMP45]], align 4 ; O3DEFAULT-NEXT: [[TMP46:%.*]] = load i32, ptr [[A]], align 4 ; O3DEFAULT-NEXT: ret i32 [[TMP46]] ; @@ -361,84 +361,84 @@ define i32 @enabled(ptr noalias nocapture %a, ptr noalias nocapture readonly %b, ; Os-NEXT: entry: ; Os-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[N:%.*]], i64 0 ; Os-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer -; Os-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[B:%.*]], align 4 -; Os-NEXT: [[TMP0:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], [[BROADCAST_SPLAT]] -; Os-NEXT: store <4 x i32> [[TMP0]], ptr [[A:%.*]], align 4 -; Os-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 16 -; Os-NEXT: [[WIDE_LOAD_1:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4 -; Os-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_1]], [[BROADCAST_SPLAT]] -; Os-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 16 +; Os-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[B:%.*]], i64 16 +; Os-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[B]], align 4 +; Os-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4 +; Os-NEXT: [[TMP1:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[A:%.*]], i64 16 +; Os-NEXT: store <4 x i32> [[TMP1]], ptr [[A]], align 4 ; Os-NEXT: store <4 x i32> [[TMP2]], ptr [[TMP3]], align 4 ; Os-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 32 -; Os-NEXT: [[WIDE_LOAD_2:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 -; Os-NEXT: [[TMP5:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_2]], [[BROADCAST_SPLAT]] -; Os-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 32 -; Os-NEXT: store <4 x i32> [[TMP5]], ptr [[TMP6]], align 4 -; Os-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 48 -; Os-NEXT: [[WIDE_LOAD_3:%.*]] = load <4 x i32>, ptr [[TMP7]], align 4 -; Os-NEXT: [[TMP8:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_3]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 48 +; Os-NEXT: [[WIDE_LOAD_1:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 +; Os-NEXT: [[WIDE_LOAD1_1:%.*]] = load <4 x i32>, ptr [[TMP5]], align 4 +; Os-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_1]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP7:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_1]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 32 ; Os-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 48 -; Os-NEXT: store <4 x i32> [[TMP8]], ptr [[TMP9]], align 4 +; Os-NEXT: store <4 x i32> [[TMP6]], ptr [[TMP8]], align 4 +; Os-NEXT: store <4 x i32> [[TMP7]], ptr [[TMP9]], align 4 ; Os-NEXT: [[TMP10:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 64 -; Os-NEXT: [[WIDE_LOAD_4:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4 -; Os-NEXT: [[TMP11:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_4]], [[BROADCAST_SPLAT]] -; Os-NEXT: [[TMP12:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 64 -; Os-NEXT: store <4 x i32> [[TMP11]], ptr [[TMP12]], align 4 -; Os-NEXT: [[TMP13:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 80 -; Os-NEXT: [[WIDE_LOAD_5:%.*]] = load <4 x i32>, ptr [[TMP13]], align 4 -; Os-NEXT: [[TMP14:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_5]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP11:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 80 +; Os-NEXT: [[WIDE_LOAD_2:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4 +; Os-NEXT: [[WIDE_LOAD1_2:%.*]] = load <4 x i32>, ptr [[TMP11]], align 4 +; Os-NEXT: [[TMP12:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_2]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP13:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_2]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 64 ; Os-NEXT: [[TMP15:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 80 -; Os-NEXT: store <4 x i32> [[TMP14]], ptr [[TMP15]], align 4 +; Os-NEXT: store <4 x i32> [[TMP12]], ptr [[TMP14]], align 4 +; Os-NEXT: store <4 x i32> [[TMP13]], ptr [[TMP15]], align 4 ; Os-NEXT: [[TMP16:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 96 -; Os-NEXT: [[WIDE_LOAD_6:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4 -; Os-NEXT: [[TMP17:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_6]], [[BROADCAST_SPLAT]] -; Os-NEXT: [[TMP18:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 96 -; Os-NEXT: store <4 x i32> [[TMP17]], ptr [[TMP18]], align 4 -; Os-NEXT: [[TMP19:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 112 -; Os-NEXT: [[WIDE_LOAD_7:%.*]] = load <4 x i32>, ptr [[TMP19]], align 4 -; Os-NEXT: [[TMP20:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_7]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP17:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 112 +; Os-NEXT: [[WIDE_LOAD_3:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4 +; Os-NEXT: [[WIDE_LOAD1_3:%.*]] = load <4 x i32>, ptr [[TMP17]], align 4 +; Os-NEXT: [[TMP18:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_3]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP19:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_3]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP20:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 96 ; Os-NEXT: [[TMP21:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 112 -; Os-NEXT: store <4 x i32> [[TMP20]], ptr [[TMP21]], align 4 +; Os-NEXT: store <4 x i32> [[TMP18]], ptr [[TMP20]], align 4 +; Os-NEXT: store <4 x i32> [[TMP19]], ptr [[TMP21]], align 4 ; Os-NEXT: [[TMP22:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 128 -; Os-NEXT: [[WIDE_LOAD_8:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4 -; Os-NEXT: [[TMP23:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_8]], [[BROADCAST_SPLAT]] -; Os-NEXT: [[TMP24:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 128 -; Os-NEXT: store <4 x i32> [[TMP23]], ptr [[TMP24]], align 4 -; Os-NEXT: [[TMP25:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 144 -; Os-NEXT: [[WIDE_LOAD_9:%.*]] = load <4 x i32>, ptr [[TMP25]], align 4 -; Os-NEXT: [[TMP26:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_9]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP23:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 144 +; Os-NEXT: [[WIDE_LOAD_4:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4 +; Os-NEXT: [[WIDE_LOAD1_4:%.*]] = load <4 x i32>, ptr [[TMP23]], align 4 +; Os-NEXT: [[TMP24:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_4]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP25:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_4]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP26:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 128 ; Os-NEXT: [[TMP27:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 144 -; Os-NEXT: store <4 x i32> [[TMP26]], ptr [[TMP27]], align 4 +; Os-NEXT: store <4 x i32> [[TMP24]], ptr [[TMP26]], align 4 +; Os-NEXT: store <4 x i32> [[TMP25]], ptr [[TMP27]], align 4 ; Os-NEXT: [[TMP28:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 160 -; Os-NEXT: [[WIDE_LOAD_10:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4 -; Os-NEXT: [[TMP29:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_10]], [[BROADCAST_SPLAT]] -; Os-NEXT: [[TMP30:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 160 -; Os-NEXT: store <4 x i32> [[TMP29]], ptr [[TMP30]], align 4 -; Os-NEXT: [[TMP31:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 176 -; Os-NEXT: [[WIDE_LOAD_11:%.*]] = load <4 x i32>, ptr [[TMP31]], align 4 -; Os-NEXT: [[TMP32:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_11]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP29:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 176 +; Os-NEXT: [[WIDE_LOAD_5:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4 +; Os-NEXT: [[WIDE_LOAD1_5:%.*]] = load <4 x i32>, ptr [[TMP29]], align 4 +; Os-NEXT: [[TMP30:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_5]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP31:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_5]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP32:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 160 ; Os-NEXT: [[TMP33:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 176 -; Os-NEXT: store <4 x i32> [[TMP32]], ptr [[TMP33]], align 4 +; Os-NEXT: store <4 x i32> [[TMP30]], ptr [[TMP32]], align 4 +; Os-NEXT: store <4 x i32> [[TMP31]], ptr [[TMP33]], align 4 ; Os-NEXT: [[TMP34:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 192 -; Os-NEXT: [[WIDE_LOAD_12:%.*]] = load <4 x i32>, ptr [[TMP34]], align 4 -; Os-NEXT: [[TMP35:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_12]], [[BROADCAST_SPLAT]] -; Os-NEXT: [[TMP36:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 192 -; Os-NEXT: store <4 x i32> [[TMP35]], ptr [[TMP36]], align 4 -; Os-NEXT: [[TMP37:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 208 -; Os-NEXT: [[WIDE_LOAD_13:%.*]] = load <4 x i32>, ptr [[TMP37]], align 4 -; Os-NEXT: [[TMP38:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_13]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP35:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 208 +; Os-NEXT: [[WIDE_LOAD_6:%.*]] = load <4 x i32>, ptr [[TMP34]], align 4 +; Os-NEXT: [[WIDE_LOAD1_6:%.*]] = load <4 x i32>, ptr [[TMP35]], align 4 +; Os-NEXT: [[TMP36:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_6]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP37:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_6]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP38:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 192 ; Os-NEXT: [[TMP39:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 208 -; Os-NEXT: store <4 x i32> [[TMP38]], ptr [[TMP39]], align 4 +; Os-NEXT: store <4 x i32> [[TMP36]], ptr [[TMP38]], align 4 +; Os-NEXT: store <4 x i32> [[TMP37]], ptr [[TMP39]], align 4 ; Os-NEXT: [[TMP40:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 224 -; Os-NEXT: [[WIDE_LOAD_14:%.*]] = load <4 x i32>, ptr [[TMP40]], align 4 -; Os-NEXT: [[TMP41:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_14]], [[BROADCAST_SPLAT]] -; Os-NEXT: [[TMP42:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 224 -; Os-NEXT: store <4 x i32> [[TMP41]], ptr [[TMP42]], align 4 -; Os-NEXT: [[TMP43:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 240 -; Os-NEXT: [[WIDE_LOAD_15:%.*]] = load <4 x i32>, ptr [[TMP43]], align 4 -; Os-NEXT: [[TMP44:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_15]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP41:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 240 +; Os-NEXT: [[WIDE_LOAD_7:%.*]] = load <4 x i32>, ptr [[TMP40]], align 4 +; Os-NEXT: [[WIDE_LOAD1_7:%.*]] = load <4 x i32>, ptr [[TMP41]], align 4 +; Os-NEXT: [[TMP42:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_7]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP43:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_7]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP44:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 224 ; Os-NEXT: [[TMP45:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 240 -; Os-NEXT: store <4 x i32> [[TMP44]], ptr [[TMP45]], align 4 +; Os-NEXT: store <4 x i32> [[TMP42]], ptr [[TMP44]], align 4 +; Os-NEXT: store <4 x i32> [[TMP43]], ptr [[TMP45]], align 4 ; Os-NEXT: [[TMP46:%.*]] = load i32, ptr [[A]], align 4 ; Os-NEXT: ret i32 [[TMP46]] ; @@ -446,84 +446,84 @@ define i32 @enabled(ptr noalias nocapture %a, ptr noalias nocapture readonly %b, ; Oz-NEXT: entry: ; Oz-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[N:%.*]], i64 0 ; Oz-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer -; Oz-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[B:%.*]], align 4 -; Oz-NEXT: [[TMP0:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], [[BROADCAST_SPLAT]] -; Oz-NEXT: store <4 x i32> [[TMP0]], ptr [[A:%.*]], align 4 -; Oz-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 16 -; Oz-NEXT: [[WIDE_LOAD_1:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4 -; Oz-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_1]], [[BROADCAST_SPLAT]] -; Oz-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 16 +; Oz-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[B:%.*]], i64 16 +; Oz-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[B]], align 4 +; Oz-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4 +; Oz-NEXT: [[TMP1:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], [[BROADCAST_SPLAT]] +; Oz-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1]], [[BROADCAST_SPLAT]] +; Oz-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[A:%.*]], i64 16 +; Oz-NEXT: store <4 x i32> [[TMP1]], ptr [[A]], align 4 ; Oz-NEXT: store <4 x i32> [[TMP2]], ptr [[TMP3]], align 4 ; Oz-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 32 -; Oz-NEXT: [[WIDE_LOAD_2:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 -; Oz-NEXT: [[TMP5:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_2]], [[BROADCAST_SPLAT]] -; Oz-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 32 -; Oz-NEXT: store <4 x i32> [[TMP5]], ptr [[TMP6]], align 4 -; Oz-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 48 -; Oz-NEXT: [[WIDE_LOAD_3:%.*]] = load <4 x i32>, ptr [[TMP7]], align 4 -; Oz-NEXT: [[TMP8:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_3]], [[BROADCAST_SPLAT]] +; Oz-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 48 +; Oz-NEXT: [[WIDE_LOAD_1:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 +; Oz-NEXT: [[WIDE_LOAD1_1:%.*]] = load <4 x i32>, ptr [[TMP5]], align 4 +; Oz-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_1]], [[BROADCAST_SPLAT]] +; Oz-NEXT: [[TMP7:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_1]], [[BROADCAST_SPLAT]] +; Oz-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 32 ; Oz-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 48 -; Oz-NEXT: store <4 x i32> [[TMP8]], ptr [[TMP9]], align 4 +; Oz-NEXT: store <4 x i32> [[TMP6]], ptr [[TMP8]], align 4 +; Oz-NEXT: store <4 x i32> [[TMP7]], ptr [[TMP9]], align 4 ; Oz-NEXT: [[TMP10:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 64 -; Oz-NEXT: [[WIDE_LOAD_4:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4 -; Oz-NEXT: [[TMP11:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_4]], [[BROADCAST_SPLAT]] -; Oz-NEXT: [[TMP12:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 64 -; Oz-NEXT: store <4 x i32> [[TMP11]], ptr [[TMP12]], align 4 -; Oz-NEXT: [[TMP13:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 80 -; Oz-NEXT: [[WIDE_LOAD_5:%.*]] = load <4 x i32>, ptr [[TMP13]], align 4 -; Oz-NEXT: [[TMP14:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_5]], [[BROADCAST_SPLAT]] +; Oz-NEXT: [[TMP11:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 80 +; Oz-NEXT: [[WIDE_LOAD_2:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4 +; Oz-NEXT: [[WIDE_LOAD1_2:%.*]] = load <4 x i32>, ptr [[TMP11]], align 4 +; Oz-NEXT: [[TMP12:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_2]], [[BROADCAST_SPLAT]] +; Oz-NEXT: [[TMP13:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_2]], [[BROADCAST_SPLAT]] +; Oz-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 64 ; Oz-NEXT: [[TMP15:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 80 -; Oz-NEXT: store <4 x i32> [[TMP14]], ptr [[TMP15]], align 4 +; Oz-NEXT: store <4 x i32> [[TMP12]], ptr [[TMP14]], align 4 +; Oz-NEXT: store <4 x i32> [[TMP13]], ptr [[TMP15]], align 4 ; Oz-NEXT: [[TMP16:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 96 -; Oz-NEXT: [[WIDE_LOAD_6:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4 -; Oz-NEXT: [[TMP17:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_6]], [[BROADCAST_SPLAT]] -; Oz-NEXT: [[TMP18:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 96 -; Oz-NEXT: store <4 x i32> [[TMP17]], ptr [[TMP18]], align 4 -; Oz-NEXT: [[TMP19:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 112 -; Oz-NEXT: [[WIDE_LOAD_7:%.*]] = load <4 x i32>, ptr [[TMP19]], align 4 -; Oz-NEXT: [[TMP20:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_7]], [[BROADCAST_SPLAT]] +; Oz-NEXT: [[TMP17:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 112 +; Oz-NEXT: [[WIDE_LOAD_3:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4 +; Oz-NEXT: [[WIDE_LOAD1_3:%.*]] = load <4 x i32>, ptr [[TMP17]], align 4 +; Oz-NEXT: [[TMP18:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_3]], [[BROADCAST_SPLAT]] +; Oz-NEXT: [[TMP19:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_3]], [[BROADCAST_SPLAT]] +; Oz-NEXT: [[TMP20:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 96 ; Oz-NEXT: [[TMP21:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 112 -; Oz-NEXT: store <4 x i32> [[TMP20]], ptr [[TMP21]], align 4 +; Oz-NEXT: store <4 x i32> [[TMP18]], ptr [[TMP20]], align 4 +; Oz-NEXT: store <4 x i32> [[TMP19]], ptr [[TMP21]], align 4 ; Oz-NEXT: [[TMP22:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 128 -; Oz-NEXT: [[WIDE_LOAD_8:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4 -; Oz-NEXT: [[TMP23:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_8]], [[BROADCAST_SPLAT]] -; Oz-NEXT: [[TMP24:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 128 -; Oz-NEXT: store <4 x i32> [[TMP23]], ptr [[TMP24]], align 4 -; Oz-NEXT: [[TMP25:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 144 -; Oz-NEXT: [[WIDE_LOAD_9:%.*]] = load <4 x i32>, ptr [[TMP25]], align 4 -; Oz-NEXT: [[TMP26:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_9]], [[BROADCAST_SPLAT]] +; Oz-NEXT: [[TMP23:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 144 +; Oz-NEXT: [[WIDE_LOAD_4:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4 +; Oz-NEXT: [[WIDE_LOAD1_4:%.*]] = load <4 x i32>, ptr [[TMP23]], align 4 +; Oz-NEXT: [[TMP24:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_4]], [[BROADCAST_SPLAT]] +; Oz-NEXT: [[TMP25:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_4]], [[BROADCAST_SPLAT]] +; Oz-NEXT: [[TMP26:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 128 ; Oz-NEXT: [[TMP27:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 144 -; Oz-NEXT: store <4 x i32> [[TMP26]], ptr [[TMP27]], align 4 +; Oz-NEXT: store <4 x i32> [[TMP24]], ptr [[TMP26]], align 4 +; Oz-NEXT: store <4 x i32> [[TMP25]], ptr [[TMP27]], align 4 ; Oz-NEXT: [[TMP28:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 160 -; Oz-NEXT: [[WIDE_LOAD_10:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4 -; Oz-NEXT: [[TMP29:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_10]], [[BROADCAST_SPLAT]] -; Oz-NEXT: [[TMP30:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 160 -; Oz-NEXT: store <4 x i32> [[TMP29]], ptr [[TMP30]], align 4 -; Oz-NEXT: [[TMP31:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 176 -; Oz-NEXT: [[WIDE_LOAD_11:%.*]] = load <4 x i32>, ptr [[TMP31]], align 4 -; Oz-NEXT: [[TMP32:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_11]], [[BROADCAST_SPLAT]] +; Oz-NEXT: [[TMP29:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 176 +; Oz-NEXT: [[WIDE_LOAD_5:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4 +; Oz-NEXT: [[WIDE_LOAD1_5:%.*]] = load <4 x i32>, ptr [[TMP29]], align 4 +; Oz-NEXT: [[TMP30:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_5]], [[BROADCAST_SPLAT]] +; Oz-NEXT: [[TMP31:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_5]], [[BROADCAST_SPLAT]] +; Oz-NEXT: [[TMP32:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 160 ; Oz-NEXT: [[TMP33:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 176 -; Oz-NEXT: store <4 x i32> [[TMP32]], ptr [[TMP33]], align 4 +; Oz-NEXT: store <4 x i32> [[TMP30]], ptr [[TMP32]], align 4 +; Oz-NEXT: store <4 x i32> [[TMP31]], ptr [[TMP33]], align 4 ; Oz-NEXT: [[TMP34:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 192 -; Oz-NEXT: [[WIDE_LOAD_12:%.*]] = load <4 x i32>, ptr [[TMP34]], align 4 -; Oz-NEXT: [[TMP35:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_12]], [[BROADCAST_SPLAT]] -; Oz-NEXT: [[TMP36:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 192 -; Oz-NEXT: store <4 x i32> [[TMP35]], ptr [[TMP36]], align 4 -; Oz-NEXT: [[TMP37:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 208 -; Oz-NEXT: [[WIDE_LOAD_13:%.*]] = load <4 x i32>, ptr [[TMP37]], align 4 -; Oz-NEXT: [[TMP38:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_13]], [[BROADCAST_SPLAT]] +; Oz-NEXT: [[TMP35:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 208 +; Oz-NEXT: [[WIDE_LOAD_6:%.*]] = load <4 x i32>, ptr [[TMP34]], align 4 +; Oz-NEXT: [[WIDE_LOAD1_6:%.*]] = load <4 x i32>, ptr [[TMP35]], align 4 +; Oz-NEXT: [[TMP36:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_6]], [[BROADCAST_SPLAT]] +; Oz-NEXT: [[TMP37:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_6]], [[BROADCAST_SPLAT]] +; Oz-NEXT: [[TMP38:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 192 ; Oz-NEXT: [[TMP39:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 208 -; Oz-NEXT: store <4 x i32> [[TMP38]], ptr [[TMP39]], align 4 +; Oz-NEXT: store <4 x i32> [[TMP36]], ptr [[TMP38]], align 4 +; Oz-NEXT: store <4 x i32> [[TMP37]], ptr [[TMP39]], align 4 ; Oz-NEXT: [[TMP40:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 224 -; Oz-NEXT: [[WIDE_LOAD_14:%.*]] = load <4 x i32>, ptr [[TMP40]], align 4 -; Oz-NEXT: [[TMP41:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_14]], [[BROADCAST_SPLAT]] -; Oz-NEXT: [[TMP42:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 224 -; Oz-NEXT: store <4 x i32> [[TMP41]], ptr [[TMP42]], align 4 -; Oz-NEXT: [[TMP43:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 240 -; Oz-NEXT: [[WIDE_LOAD_15:%.*]] = load <4 x i32>, ptr [[TMP43]], align 4 -; Oz-NEXT: [[TMP44:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_15]], [[BROADCAST_SPLAT]] +; Oz-NEXT: [[TMP41:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 240 +; Oz-NEXT: [[WIDE_LOAD_7:%.*]] = load <4 x i32>, ptr [[TMP40]], align 4 +; Oz-NEXT: [[WIDE_LOAD1_7:%.*]] = load <4 x i32>, ptr [[TMP41]], align 4 +; Oz-NEXT: [[TMP42:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_7]], [[BROADCAST_SPLAT]] +; Oz-NEXT: [[TMP43:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_7]], [[BROADCAST_SPLAT]] +; Oz-NEXT: [[TMP44:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 224 ; Oz-NEXT: [[TMP45:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 240 -; Oz-NEXT: store <4 x i32> [[TMP44]], ptr [[TMP45]], align 4 +; Oz-NEXT: store <4 x i32> [[TMP42]], ptr [[TMP44]], align 4 +; Oz-NEXT: store <4 x i32> [[TMP43]], ptr [[TMP45]], align 4 ; Oz-NEXT: [[TMP46:%.*]] = load i32, ptr [[A]], align 4 ; Oz-NEXT: ret i32 [[TMP46]] ; @@ -531,84 +531,84 @@ define i32 @enabled(ptr noalias nocapture %a, ptr noalias nocapture readonly %b, ; O1VEC2-NEXT: entry: ; O1VEC2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[N:%.*]], i64 0 ; O1VEC2-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer -; O1VEC2-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[B:%.*]], align 4 -; O1VEC2-NEXT: [[TMP0:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], [[BROADCAST_SPLAT]] -; O1VEC2-NEXT: store <4 x i32> [[TMP0]], ptr [[A:%.*]], align 4 -; O1VEC2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 16 -; O1VEC2-NEXT: [[WIDE_LOAD_1:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4 -; O1VEC2-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_1]], [[BROADCAST_SPLAT]] -; O1VEC2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 16 +; O1VEC2-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[B:%.*]], i64 16 +; O1VEC2-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[B]], align 4 +; O1VEC2-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4 +; O1VEC2-NEXT: [[TMP1:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], [[BROADCAST_SPLAT]] +; O1VEC2-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1]], [[BROADCAST_SPLAT]] +; O1VEC2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[A:%.*]], i64 16 +; O1VEC2-NEXT: store <4 x i32> [[TMP1]], ptr [[A]], align 4 ; O1VEC2-NEXT: store <4 x i32> [[TMP2]], ptr [[TMP3]], align 4 ; O1VEC2-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 32 -; O1VEC2-NEXT: [[WIDE_LOAD_2:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 -; O1VEC2-NEXT: [[TMP5:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_2]], [[BROADCAST_SPLAT]] -; O1VEC2-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 32 -; O1VEC2-NEXT: store <4 x i32> [[TMP5]], ptr [[TMP6]], align 4 -; O1VEC2-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 48 -; O1VEC2-NEXT: [[WIDE_LOAD_3:%.*]] = load <4 x i32>, ptr [[TMP7]], align 4 -; O1VEC2-NEXT: [[TMP8:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_3]], [[BROADCAST_SPLAT]] +; O1VEC2-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 48 +; O1VEC2-NEXT: [[WIDE_LOAD_1:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 +; O1VEC2-NEXT: [[WIDE_LOAD1_1:%.*]] = load <4 x i32>, ptr [[TMP5]], align 4 +; O1VEC2-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_1]], [[BROADCAST_SPLAT]] +; O1VEC2-NEXT: [[TMP7:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_1]], [[BROADCAST_SPLAT]] +; O1VEC2-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 32 ; O1VEC2-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 48 -; O1VEC2-NEXT: store <4 x i32> [[TMP8]], ptr [[TMP9]], align 4 +; O1VEC2-NEXT: store <4 x i32> [[TMP6]], ptr [[TMP8]], align 4 +; O1VEC2-NEXT: store <4 x i32> [[TMP7]], ptr [[TMP9]], align 4 ; O1VEC2-NEXT: [[TMP10:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 64 -; O1VEC2-NEXT: [[WIDE_LOAD_4:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4 -; O1VEC2-NEXT: [[TMP11:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_4]], [[BROADCAST_SPLAT]] -; O1VEC2-NEXT: [[TMP12:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 64 -; O1VEC2-NEXT: store <4 x i32> [[TMP11]], ptr [[TMP12]], align 4 -; O1VEC2-NEXT: [[TMP13:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 80 -; O1VEC2-NEXT: [[WIDE_LOAD_5:%.*]] = load <4 x i32>, ptr [[TMP13]], align 4 -; O1VEC2-NEXT: [[TMP14:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_5]], [[BROADCAST_SPLAT]] +; O1VEC2-NEXT: [[TMP11:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 80 +; O1VEC2-NEXT: [[WIDE_LOAD_2:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4 +; O1VEC2-NEXT: [[WIDE_LOAD1_2:%.*]] = load <4 x i32>, ptr [[TMP11]], align 4 +; O1VEC2-NEXT: [[TMP12:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_2]], [[BROADCAST_SPLAT]] +; O1VEC2-NEXT: [[TMP13:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_2]], [[BROADCAST_SPLAT]] +; O1VEC2-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 64 ; O1VEC2-NEXT: [[TMP15:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 80 -; O1VEC2-NEXT: store <4 x i32> [[TMP14]], ptr [[TMP15]], align 4 +; O1VEC2-NEXT: store <4 x i32> [[TMP12]], ptr [[TMP14]], align 4 +; O1VEC2-NEXT: store <4 x i32> [[TMP13]], ptr [[TMP15]], align 4 ; O1VEC2-NEXT: [[TMP16:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 96 -; O1VEC2-NEXT: [[WIDE_LOAD_6:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4 -; O1VEC2-NEXT: [[TMP17:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_6]], [[BROADCAST_SPLAT]] -; O1VEC2-NEXT: [[TMP18:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 96 -; O1VEC2-NEXT: store <4 x i32> [[TMP17]], ptr [[TMP18]], align 4 -; O1VEC2-NEXT: [[TMP19:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 112 -; O1VEC2-NEXT: [[WIDE_LOAD_7:%.*]] = load <4 x i32>, ptr [[TMP19]], align 4 -; O1VEC2-NEXT: [[TMP20:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_7]], [[BROADCAST_SPLAT]] +; O1VEC2-NEXT: [[TMP17:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 112 +; O1VEC2-NEXT: [[WIDE_LOAD_3:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4 +; O1VEC2-NEXT: [[WIDE_LOAD1_3:%.*]] = load <4 x i32>, ptr [[TMP17]], align 4 +; O1VEC2-NEXT: [[TMP18:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_3]], [[BROADCAST_SPLAT]] +; O1VEC2-NEXT: [[TMP19:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_3]], [[BROADCAST_SPLAT]] +; O1VEC2-NEXT: [[TMP20:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 96 ; O1VEC2-NEXT: [[TMP21:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 112 -; O1VEC2-NEXT: store <4 x i32> [[TMP20]], ptr [[TMP21]], align 4 +; O1VEC2-NEXT: store <4 x i32> [[TMP18]], ptr [[TMP20]], align 4 +; O1VEC2-NEXT: store <4 x i32> [[TMP19]], ptr [[TMP21]], align 4 ; O1VEC2-NEXT: [[TMP22:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 128 -; O1VEC2-NEXT: [[WIDE_LOAD_8:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4 -; O1VEC2-NEXT: [[TMP23:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_8]], [[BROADCAST_SPLAT]] -; O1VEC2-NEXT: [[TMP24:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 128 -; O1VEC2-NEXT: store <4 x i32> [[TMP23]], ptr [[TMP24]], align 4 -; O1VEC2-NEXT: [[TMP25:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 144 -; O1VEC2-NEXT: [[WIDE_LOAD_9:%.*]] = load <4 x i32>, ptr [[TMP25]], align 4 -; O1VEC2-NEXT: [[TMP26:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_9]], [[BROADCAST_SPLAT]] +; O1VEC2-NEXT: [[TMP23:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 144 +; O1VEC2-NEXT: [[WIDE_LOAD_4:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4 +; O1VEC2-NEXT: [[WIDE_LOAD1_4:%.*]] = load <4 x i32>, ptr [[TMP23]], align 4 +; O1VEC2-NEXT: [[TMP24:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_4]], [[BROADCAST_SPLAT]] +; O1VEC2-NEXT: [[TMP25:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_4]], [[BROADCAST_SPLAT]] +; O1VEC2-NEXT: [[TMP26:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 128 ; O1VEC2-NEXT: [[TMP27:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 144 -; O1VEC2-NEXT: store <4 x i32> [[TMP26]], ptr [[TMP27]], align 4 +; O1VEC2-NEXT: store <4 x i32> [[TMP24]], ptr [[TMP26]], align 4 +; O1VEC2-NEXT: store <4 x i32> [[TMP25]], ptr [[TMP27]], align 4 ; O1VEC2-NEXT: [[TMP28:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 160 -; O1VEC2-NEXT: [[WIDE_LOAD_10:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4 -; O1VEC2-NEXT: [[TMP29:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_10]], [[BROADCAST_SPLAT]] -; O1VEC2-NEXT: [[TMP30:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 160 -; O1VEC2-NEXT: store <4 x i32> [[TMP29]], ptr [[TMP30]], align 4 -; O1VEC2-NEXT: [[TMP31:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 176 -; O1VEC2-NEXT: [[WIDE_LOAD_11:%.*]] = load <4 x i32>, ptr [[TMP31]], align 4 -; O1VEC2-NEXT: [[TMP32:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_11]], [[BROADCAST_SPLAT]] +; O1VEC2-NEXT: [[TMP29:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 176 +; O1VEC2-NEXT: [[WIDE_LOAD_5:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4 +; O1VEC2-NEXT: [[WIDE_LOAD1_5:%.*]] = load <4 x i32>, ptr [[TMP29]], align 4 +; O1VEC2-NEXT: [[TMP30:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_5]], [[BROADCAST_SPLAT]] +; O1VEC2-NEXT: [[TMP31:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_5]], [[BROADCAST_SPLAT]] +; O1VEC2-NEXT: [[TMP32:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 160 ; O1VEC2-NEXT: [[TMP33:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 176 -; O1VEC2-NEXT: store <4 x i32> [[TMP32]], ptr [[TMP33]], align 4 +; O1VEC2-NEXT: store <4 x i32> [[TMP30]], ptr [[TMP32]], align 4 +; O1VEC2-NEXT: store <4 x i32> [[TMP31]], ptr [[TMP33]], align 4 ; O1VEC2-NEXT: [[TMP34:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 192 -; O1VEC2-NEXT: [[WIDE_LOAD_12:%.*]] = load <4 x i32>, ptr [[TMP34]], align 4 -; O1VEC2-NEXT: [[TMP35:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_12]], [[BROADCAST_SPLAT]] -; O1VEC2-NEXT: [[TMP36:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 192 -; O1VEC2-NEXT: store <4 x i32> [[TMP35]], ptr [[TMP36]], align 4 -; O1VEC2-NEXT: [[TMP37:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 208 -; O1VEC2-NEXT: [[WIDE_LOAD_13:%.*]] = load <4 x i32>, ptr [[TMP37]], align 4 -; O1VEC2-NEXT: [[TMP38:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_13]], [[BROADCAST_SPLAT]] +; O1VEC2-NEXT: [[TMP35:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 208 +; O1VEC2-NEXT: [[WIDE_LOAD_6:%.*]] = load <4 x i32>, ptr [[TMP34]], align 4 +; O1VEC2-NEXT: [[WIDE_LOAD1_6:%.*]] = load <4 x i32>, ptr [[TMP35]], align 4 +; O1VEC2-NEXT: [[TMP36:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_6]], [[BROADCAST_SPLAT]] +; O1VEC2-NEXT: [[TMP37:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_6]], [[BROADCAST_SPLAT]] +; O1VEC2-NEXT: [[TMP38:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 192 ; O1VEC2-NEXT: [[TMP39:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 208 -; O1VEC2-NEXT: store <4 x i32> [[TMP38]], ptr [[TMP39]], align 4 +; O1VEC2-NEXT: store <4 x i32> [[TMP36]], ptr [[TMP38]], align 4 +; O1VEC2-NEXT: store <4 x i32> [[TMP37]], ptr [[TMP39]], align 4 ; O1VEC2-NEXT: [[TMP40:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 224 -; O1VEC2-NEXT: [[WIDE_LOAD_14:%.*]] = load <4 x i32>, ptr [[TMP40]], align 4 -; O1VEC2-NEXT: [[TMP41:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_14]], [[BROADCAST_SPLAT]] -; O1VEC2-NEXT: [[TMP42:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 224 -; O1VEC2-NEXT: store <4 x i32> [[TMP41]], ptr [[TMP42]], align 4 -; O1VEC2-NEXT: [[TMP43:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 240 -; O1VEC2-NEXT: [[WIDE_LOAD_15:%.*]] = load <4 x i32>, ptr [[TMP43]], align 4 -; O1VEC2-NEXT: [[TMP44:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_15]], [[BROADCAST_SPLAT]] +; O1VEC2-NEXT: [[TMP41:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 240 +; O1VEC2-NEXT: [[WIDE_LOAD_7:%.*]] = load <4 x i32>, ptr [[TMP40]], align 4 +; O1VEC2-NEXT: [[WIDE_LOAD1_7:%.*]] = load <4 x i32>, ptr [[TMP41]], align 4 +; O1VEC2-NEXT: [[TMP42:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_7]], [[BROADCAST_SPLAT]] +; O1VEC2-NEXT: [[TMP43:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_7]], [[BROADCAST_SPLAT]] +; O1VEC2-NEXT: [[TMP44:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 224 ; O1VEC2-NEXT: [[TMP45:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 240 -; O1VEC2-NEXT: store <4 x i32> [[TMP44]], ptr [[TMP45]], align 4 +; O1VEC2-NEXT: store <4 x i32> [[TMP42]], ptr [[TMP44]], align 4 +; O1VEC2-NEXT: store <4 x i32> [[TMP43]], ptr [[TMP45]], align 4 ; O1VEC2-NEXT: [[TMP46:%.*]] = load i32, ptr [[A]], align 4 ; O1VEC2-NEXT: ret i32 [[TMP46]] ; @@ -616,84 +616,84 @@ define i32 @enabled(ptr noalias nocapture %a, ptr noalias nocapture readonly %b, ; OzVEC2-NEXT: entry: ; OzVEC2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[N:%.*]], i64 0 ; OzVEC2-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer -; OzVEC2-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[B:%.*]], align 4 -; OzVEC2-NEXT: [[TMP0:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], [[BROADCAST_SPLAT]] -; OzVEC2-NEXT: store <4 x i32> [[TMP0]], ptr [[A:%.*]], align 4 -; OzVEC2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 16 -; OzVEC2-NEXT: [[WIDE_LOAD_1:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4 -; OzVEC2-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_1]], [[BROADCAST_SPLAT]] -; OzVEC2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 16 +; OzVEC2-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[B:%.*]], i64 16 +; OzVEC2-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[B]], align 4 +; OzVEC2-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4 +; OzVEC2-NEXT: [[TMP1:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], [[BROADCAST_SPLAT]] +; OzVEC2-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1]], [[BROADCAST_SPLAT]] +; OzVEC2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[A:%.*]], i64 16 +; OzVEC2-NEXT: store <4 x i32> [[TMP1]], ptr [[A]], align 4 ; OzVEC2-NEXT: store <4 x i32> [[TMP2]], ptr [[TMP3]], align 4 ; OzVEC2-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 32 -; OzVEC2-NEXT: [[WIDE_LOAD_2:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 -; OzVEC2-NEXT: [[TMP5:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_2]], [[BROADCAST_SPLAT]] -; OzVEC2-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 32 -; OzVEC2-NEXT: store <4 x i32> [[TMP5]], ptr [[TMP6]], align 4 -; OzVEC2-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 48 -; OzVEC2-NEXT: [[WIDE_LOAD_3:%.*]] = load <4 x i32>, ptr [[TMP7]], align 4 -; OzVEC2-NEXT: [[TMP8:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_3]], [[BROADCAST_SPLAT]] +; OzVEC2-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 48 +; OzVEC2-NEXT: [[WIDE_LOAD_1:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 +; OzVEC2-NEXT: [[WIDE_LOAD1_1:%.*]] = load <4 x i32>, ptr [[TMP5]], align 4 +; OzVEC2-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_1]], [[BROADCAST_SPLAT]] +; OzVEC2-NEXT: [[TMP7:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_1]], [[BROADCAST_SPLAT]] +; OzVEC2-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 32 ; OzVEC2-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 48 -; OzVEC2-NEXT: store <4 x i32> [[TMP8]], ptr [[TMP9]], align 4 +; OzVEC2-NEXT: store <4 x i32> [[TMP6]], ptr [[TMP8]], align 4 +; OzVEC2-NEXT: store <4 x i32> [[TMP7]], ptr [[TMP9]], align 4 ; OzVEC2-NEXT: [[TMP10:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 64 -; OzVEC2-NEXT: [[WIDE_LOAD_4:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4 -; OzVEC2-NEXT: [[TMP11:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_4]], [[BROADCAST_SPLAT]] -; OzVEC2-NEXT: [[TMP12:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 64 -; OzVEC2-NEXT: store <4 x i32> [[TMP11]], ptr [[TMP12]], align 4 -; OzVEC2-NEXT: [[TMP13:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 80 -; OzVEC2-NEXT: [[WIDE_LOAD_5:%.*]] = load <4 x i32>, ptr [[TMP13]], align 4 -; OzVEC2-NEXT: [[TMP14:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_5]], [[BROADCAST_SPLAT]] +; OzVEC2-NEXT: [[TMP11:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 80 +; OzVEC2-NEXT: [[WIDE_LOAD_2:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4 +; OzVEC2-NEXT: [[WIDE_LOAD1_2:%.*]] = load <4 x i32>, ptr [[TMP11]], align 4 +; OzVEC2-NEXT: [[TMP12:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_2]], [[BROADCAST_SPLAT]] +; OzVEC2-NEXT: [[TMP13:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_2]], [[BROADCAST_SPLAT]] +; OzVEC2-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 64 ; OzVEC2-NEXT: [[TMP15:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 80 -; OzVEC2-NEXT: store <4 x i32> [[TMP14]], ptr [[TMP15]], align 4 +; OzVEC2-NEXT: store <4 x i32> [[TMP12]], ptr [[TMP14]], align 4 +; OzVEC2-NEXT: store <4 x i32> [[TMP13]], ptr [[TMP15]], align 4 ; OzVEC2-NEXT: [[TMP16:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 96 -; OzVEC2-NEXT: [[WIDE_LOAD_6:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4 -; OzVEC2-NEXT: [[TMP17:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_6]], [[BROADCAST_SPLAT]] -; OzVEC2-NEXT: [[TMP18:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 96 -; OzVEC2-NEXT: store <4 x i32> [[TMP17]], ptr [[TMP18]], align 4 -; OzVEC2-NEXT: [[TMP19:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 112 -; OzVEC2-NEXT: [[WIDE_LOAD_7:%.*]] = load <4 x i32>, ptr [[TMP19]], align 4 -; OzVEC2-NEXT: [[TMP20:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_7]], [[BROADCAST_SPLAT]] +; OzVEC2-NEXT: [[TMP17:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 112 +; OzVEC2-NEXT: [[WIDE_LOAD_3:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4 +; OzVEC2-NEXT: [[WIDE_LOAD1_3:%.*]] = load <4 x i32>, ptr [[TMP17]], align 4 +; OzVEC2-NEXT: [[TMP18:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_3]], [[BROADCAST_SPLAT]] +; OzVEC2-NEXT: [[TMP19:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_3]], [[BROADCAST_SPLAT]] +; OzVEC2-NEXT: [[TMP20:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 96 ; OzVEC2-NEXT: [[TMP21:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 112 -; OzVEC2-NEXT: store <4 x i32> [[TMP20]], ptr [[TMP21]], align 4 +; OzVEC2-NEXT: store <4 x i32> [[TMP18]], ptr [[TMP20]], align 4 +; OzVEC2-NEXT: store <4 x i32> [[TMP19]], ptr [[TMP21]], align 4 ; OzVEC2-NEXT: [[TMP22:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 128 -; OzVEC2-NEXT: [[WIDE_LOAD_8:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4 -; OzVEC2-NEXT: [[TMP23:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_8]], [[BROADCAST_SPLAT]] -; OzVEC2-NEXT: [[TMP24:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 128 -; OzVEC2-NEXT: store <4 x i32> [[TMP23]], ptr [[TMP24]], align 4 -; OzVEC2-NEXT: [[TMP25:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 144 -; OzVEC2-NEXT: [[WIDE_LOAD_9:%.*]] = load <4 x i32>, ptr [[TMP25]], align 4 -; OzVEC2-NEXT: [[TMP26:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_9]], [[BROADCAST_SPLAT]] +; OzVEC2-NEXT: [[TMP23:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 144 +; OzVEC2-NEXT: [[WIDE_LOAD_4:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4 +; OzVEC2-NEXT: [[WIDE_LOAD1_4:%.*]] = load <4 x i32>, ptr [[TMP23]], align 4 +; OzVEC2-NEXT: [[TMP24:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_4]], [[BROADCAST_SPLAT]] +; OzVEC2-NEXT: [[TMP25:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_4]], [[BROADCAST_SPLAT]] +; OzVEC2-NEXT: [[TMP26:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 128 ; OzVEC2-NEXT: [[TMP27:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 144 -; OzVEC2-NEXT: store <4 x i32> [[TMP26]], ptr [[TMP27]], align 4 +; OzVEC2-NEXT: store <4 x i32> [[TMP24]], ptr [[TMP26]], align 4 +; OzVEC2-NEXT: store <4 x i32> [[TMP25]], ptr [[TMP27]], align 4 ; OzVEC2-NEXT: [[TMP28:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 160 -; OzVEC2-NEXT: [[WIDE_LOAD_10:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4 -; OzVEC2-NEXT: [[TMP29:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_10]], [[BROADCAST_SPLAT]] -; OzVEC2-NEXT: [[TMP30:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 160 -; OzVEC2-NEXT: store <4 x i32> [[TMP29]], ptr [[TMP30]], align 4 -; OzVEC2-NEXT: [[TMP31:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 176 -; OzVEC2-NEXT: [[WIDE_LOAD_11:%.*]] = load <4 x i32>, ptr [[TMP31]], align 4 -; OzVEC2-NEXT: [[TMP32:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_11]], [[BROADCAST_SPLAT]] +; OzVEC2-NEXT: [[TMP29:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 176 +; OzVEC2-NEXT: [[WIDE_LOAD_5:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4 +; OzVEC2-NEXT: [[WIDE_LOAD1_5:%.*]] = load <4 x i32>, ptr [[TMP29]], align 4 +; OzVEC2-NEXT: [[TMP30:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_5]], [[BROADCAST_SPLAT]] +; OzVEC2-NEXT: [[TMP31:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_5]], [[BROADCAST_SPLAT]] +; OzVEC2-NEXT: [[TMP32:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 160 ; OzVEC2-NEXT: [[TMP33:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 176 -; OzVEC2-NEXT: store <4 x i32> [[TMP32]], ptr [[TMP33]], align 4 +; OzVEC2-NEXT: store <4 x i32> [[TMP30]], ptr [[TMP32]], align 4 +; OzVEC2-NEXT: store <4 x i32> [[TMP31]], ptr [[TMP33]], align 4 ; OzVEC2-NEXT: [[TMP34:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 192 -; OzVEC2-NEXT: [[WIDE_LOAD_12:%.*]] = load <4 x i32>, ptr [[TMP34]], align 4 -; OzVEC2-NEXT: [[TMP35:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_12]], [[BROADCAST_SPLAT]] -; OzVEC2-NEXT: [[TMP36:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 192 -; OzVEC2-NEXT: store <4 x i32> [[TMP35]], ptr [[TMP36]], align 4 -; OzVEC2-NEXT: [[TMP37:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 208 -; OzVEC2-NEXT: [[WIDE_LOAD_13:%.*]] = load <4 x i32>, ptr [[TMP37]], align 4 -; OzVEC2-NEXT: [[TMP38:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_13]], [[BROADCAST_SPLAT]] +; OzVEC2-NEXT: [[TMP35:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 208 +; OzVEC2-NEXT: [[WIDE_LOAD_6:%.*]] = load <4 x i32>, ptr [[TMP34]], align 4 +; OzVEC2-NEXT: [[WIDE_LOAD1_6:%.*]] = load <4 x i32>, ptr [[TMP35]], align 4 +; OzVEC2-NEXT: [[TMP36:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_6]], [[BROADCAST_SPLAT]] +; OzVEC2-NEXT: [[TMP37:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_6]], [[BROADCAST_SPLAT]] +; OzVEC2-NEXT: [[TMP38:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 192 ; OzVEC2-NEXT: [[TMP39:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 208 -; OzVEC2-NEXT: store <4 x i32> [[TMP38]], ptr [[TMP39]], align 4 +; OzVEC2-NEXT: store <4 x i32> [[TMP36]], ptr [[TMP38]], align 4 +; OzVEC2-NEXT: store <4 x i32> [[TMP37]], ptr [[TMP39]], align 4 ; OzVEC2-NEXT: [[TMP40:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 224 -; OzVEC2-NEXT: [[WIDE_LOAD_14:%.*]] = load <4 x i32>, ptr [[TMP40]], align 4 -; OzVEC2-NEXT: [[TMP41:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_14]], [[BROADCAST_SPLAT]] -; OzVEC2-NEXT: [[TMP42:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 224 -; OzVEC2-NEXT: store <4 x i32> [[TMP41]], ptr [[TMP42]], align 4 -; OzVEC2-NEXT: [[TMP43:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 240 -; OzVEC2-NEXT: [[WIDE_LOAD_15:%.*]] = load <4 x i32>, ptr [[TMP43]], align 4 -; OzVEC2-NEXT: [[TMP44:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_15]], [[BROADCAST_SPLAT]] +; OzVEC2-NEXT: [[TMP41:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 240 +; OzVEC2-NEXT: [[WIDE_LOAD_7:%.*]] = load <4 x i32>, ptr [[TMP40]], align 4 +; OzVEC2-NEXT: [[WIDE_LOAD1_7:%.*]] = load <4 x i32>, ptr [[TMP41]], align 4 +; OzVEC2-NEXT: [[TMP42:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_7]], [[BROADCAST_SPLAT]] +; OzVEC2-NEXT: [[TMP43:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_7]], [[BROADCAST_SPLAT]] +; OzVEC2-NEXT: [[TMP44:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 224 ; OzVEC2-NEXT: [[TMP45:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 240 -; OzVEC2-NEXT: store <4 x i32> [[TMP44]], ptr [[TMP45]], align 4 +; OzVEC2-NEXT: store <4 x i32> [[TMP42]], ptr [[TMP44]], align 4 +; OzVEC2-NEXT: store <4 x i32> [[TMP43]], ptr [[TMP45]], align 4 ; OzVEC2-NEXT: [[TMP46:%.*]] = load i32, ptr [[A]], align 4 ; OzVEC2-NEXT: ret i32 [[TMP46]] ; @@ -701,84 +701,84 @@ define i32 @enabled(ptr noalias nocapture %a, ptr noalias nocapture readonly %b, ; O3DIS-NEXT: entry: ; O3DIS-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[N:%.*]], i64 0 ; O3DIS-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer -; O3DIS-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[B:%.*]], align 4 -; O3DIS-NEXT: [[TMP0:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], [[BROADCAST_SPLAT]] -; O3DIS-NEXT: store <4 x i32> [[TMP0]], ptr [[A:%.*]], align 4 -; O3DIS-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 16 -; O3DIS-NEXT: [[WIDE_LOAD_1:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4 -; O3DIS-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_1]], [[BROADCAST_SPLAT]] -; O3DIS-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 16 +; O3DIS-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[B:%.*]], i64 16 +; O3DIS-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[B]], align 4 +; O3DIS-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4 +; O3DIS-NEXT: [[TMP1:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], [[BROADCAST_SPLAT]] +; O3DIS-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1]], [[BROADCAST_SPLAT]] +; O3DIS-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[A:%.*]], i64 16 +; O3DIS-NEXT: store <4 x i32> [[TMP1]], ptr [[A]], align 4 ; O3DIS-NEXT: store <4 x i32> [[TMP2]], ptr [[TMP3]], align 4 ; O3DIS-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 32 -; O3DIS-NEXT: [[WIDE_LOAD_2:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 -; O3DIS-NEXT: [[TMP5:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_2]], [[BROADCAST_SPLAT]] -; O3DIS-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 32 -; O3DIS-NEXT: store <4 x i32> [[TMP5]], ptr [[TMP6]], align 4 -; O3DIS-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 48 -; O3DIS-NEXT: [[WIDE_LOAD_3:%.*]] = load <4 x i32>, ptr [[TMP7]], align 4 -; O3DIS-NEXT: [[TMP8:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_3]], [[BROADCAST_SPLAT]] +; O3DIS-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 48 +; O3DIS-NEXT: [[WIDE_LOAD_1:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 +; O3DIS-NEXT: [[WIDE_LOAD1_1:%.*]] = load <4 x i32>, ptr [[TMP5]], align 4 +; O3DIS-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_1]], [[BROADCAST_SPLAT]] +; O3DIS-NEXT: [[TMP7:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_1]], [[BROADCAST_SPLAT]] +; O3DIS-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 32 ; O3DIS-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 48 -; O3DIS-NEXT: store <4 x i32> [[TMP8]], ptr [[TMP9]], align 4 +; O3DIS-NEXT: store <4 x i32> [[TMP6]], ptr [[TMP8]], align 4 +; O3DIS-NEXT: store <4 x i32> [[TMP7]], ptr [[TMP9]], align 4 ; O3DIS-NEXT: [[TMP10:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 64 -; O3DIS-NEXT: [[WIDE_LOAD_4:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4 -; O3DIS-NEXT: [[TMP11:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_4]], [[BROADCAST_SPLAT]] -; O3DIS-NEXT: [[TMP12:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 64 -; O3DIS-NEXT: store <4 x i32> [[TMP11]], ptr [[TMP12]], align 4 -; O3DIS-NEXT: [[TMP13:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 80 -; O3DIS-NEXT: [[WIDE_LOAD_5:%.*]] = load <4 x i32>, ptr [[TMP13]], align 4 -; O3DIS-NEXT: [[TMP14:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_5]], [[BROADCAST_SPLAT]] +; O3DIS-NEXT: [[TMP11:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 80 +; O3DIS-NEXT: [[WIDE_LOAD_2:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4 +; O3DIS-NEXT: [[WIDE_LOAD1_2:%.*]] = load <4 x i32>, ptr [[TMP11]], align 4 +; O3DIS-NEXT: [[TMP12:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_2]], [[BROADCAST_SPLAT]] +; O3DIS-NEXT: [[TMP13:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_2]], [[BROADCAST_SPLAT]] +; O3DIS-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 64 ; O3DIS-NEXT: [[TMP15:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 80 -; O3DIS-NEXT: store <4 x i32> [[TMP14]], ptr [[TMP15]], align 4 +; O3DIS-NEXT: store <4 x i32> [[TMP12]], ptr [[TMP14]], align 4 +; O3DIS-NEXT: store <4 x i32> [[TMP13]], ptr [[TMP15]], align 4 ; O3DIS-NEXT: [[TMP16:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 96 -; O3DIS-NEXT: [[WIDE_LOAD_6:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4 -; O3DIS-NEXT: [[TMP17:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_6]], [[BROADCAST_SPLAT]] -; O3DIS-NEXT: [[TMP18:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 96 -; O3DIS-NEXT: store <4 x i32> [[TMP17]], ptr [[TMP18]], align 4 -; O3DIS-NEXT: [[TMP19:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 112 -; O3DIS-NEXT: [[WIDE_LOAD_7:%.*]] = load <4 x i32>, ptr [[TMP19]], align 4 -; O3DIS-NEXT: [[TMP20:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_7]], [[BROADCAST_SPLAT]] +; O3DIS-NEXT: [[TMP17:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 112 +; O3DIS-NEXT: [[WIDE_LOAD_3:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4 +; O3DIS-NEXT: [[WIDE_LOAD1_3:%.*]] = load <4 x i32>, ptr [[TMP17]], align 4 +; O3DIS-NEXT: [[TMP18:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_3]], [[BROADCAST_SPLAT]] +; O3DIS-NEXT: [[TMP19:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_3]], [[BROADCAST_SPLAT]] +; O3DIS-NEXT: [[TMP20:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 96 ; O3DIS-NEXT: [[TMP21:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 112 -; O3DIS-NEXT: store <4 x i32> [[TMP20]], ptr [[TMP21]], align 4 +; O3DIS-NEXT: store <4 x i32> [[TMP18]], ptr [[TMP20]], align 4 +; O3DIS-NEXT: store <4 x i32> [[TMP19]], ptr [[TMP21]], align 4 ; O3DIS-NEXT: [[TMP22:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 128 -; O3DIS-NEXT: [[WIDE_LOAD_8:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4 -; O3DIS-NEXT: [[TMP23:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_8]], [[BROADCAST_SPLAT]] -; O3DIS-NEXT: [[TMP24:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 128 -; O3DIS-NEXT: store <4 x i32> [[TMP23]], ptr [[TMP24]], align 4 -; O3DIS-NEXT: [[TMP25:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 144 -; O3DIS-NEXT: [[WIDE_LOAD_9:%.*]] = load <4 x i32>, ptr [[TMP25]], align 4 -; O3DIS-NEXT: [[TMP26:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_9]], [[BROADCAST_SPLAT]] +; O3DIS-NEXT: [[TMP23:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 144 +; O3DIS-NEXT: [[WIDE_LOAD_4:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4 +; O3DIS-NEXT: [[WIDE_LOAD1_4:%.*]] = load <4 x i32>, ptr [[TMP23]], align 4 +; O3DIS-NEXT: [[TMP24:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_4]], [[BROADCAST_SPLAT]] +; O3DIS-NEXT: [[TMP25:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_4]], [[BROADCAST_SPLAT]] +; O3DIS-NEXT: [[TMP26:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 128 ; O3DIS-NEXT: [[TMP27:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 144 -; O3DIS-NEXT: store <4 x i32> [[TMP26]], ptr [[TMP27]], align 4 +; O3DIS-NEXT: store <4 x i32> [[TMP24]], ptr [[TMP26]], align 4 +; O3DIS-NEXT: store <4 x i32> [[TMP25]], ptr [[TMP27]], align 4 ; O3DIS-NEXT: [[TMP28:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 160 -; O3DIS-NEXT: [[WIDE_LOAD_10:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4 -; O3DIS-NEXT: [[TMP29:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_10]], [[BROADCAST_SPLAT]] -; O3DIS-NEXT: [[TMP30:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 160 -; O3DIS-NEXT: store <4 x i32> [[TMP29]], ptr [[TMP30]], align 4 -; O3DIS-NEXT: [[TMP31:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 176 -; O3DIS-NEXT: [[WIDE_LOAD_11:%.*]] = load <4 x i32>, ptr [[TMP31]], align 4 -; O3DIS-NEXT: [[TMP32:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_11]], [[BROADCAST_SPLAT]] +; O3DIS-NEXT: [[TMP29:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 176 +; O3DIS-NEXT: [[WIDE_LOAD_5:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4 +; O3DIS-NEXT: [[WIDE_LOAD1_5:%.*]] = load <4 x i32>, ptr [[TMP29]], align 4 +; O3DIS-NEXT: [[TMP30:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_5]], [[BROADCAST_SPLAT]] +; O3DIS-NEXT: [[TMP31:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_5]], [[BROADCAST_SPLAT]] +; O3DIS-NEXT: [[TMP32:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 160 ; O3DIS-NEXT: [[TMP33:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 176 -; O3DIS-NEXT: store <4 x i32> [[TMP32]], ptr [[TMP33]], align 4 +; O3DIS-NEXT: store <4 x i32> [[TMP30]], ptr [[TMP32]], align 4 +; O3DIS-NEXT: store <4 x i32> [[TMP31]], ptr [[TMP33]], align 4 ; O3DIS-NEXT: [[TMP34:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 192 -; O3DIS-NEXT: [[WIDE_LOAD_12:%.*]] = load <4 x i32>, ptr [[TMP34]], align 4 -; O3DIS-NEXT: [[TMP35:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_12]], [[BROADCAST_SPLAT]] -; O3DIS-NEXT: [[TMP36:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 192 -; O3DIS-NEXT: store <4 x i32> [[TMP35]], ptr [[TMP36]], align 4 -; O3DIS-NEXT: [[TMP37:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 208 -; O3DIS-NEXT: [[WIDE_LOAD_13:%.*]] = load <4 x i32>, ptr [[TMP37]], align 4 -; O3DIS-NEXT: [[TMP38:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_13]], [[BROADCAST_SPLAT]] +; O3DIS-NEXT: [[TMP35:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 208 +; O3DIS-NEXT: [[WIDE_LOAD_6:%.*]] = load <4 x i32>, ptr [[TMP34]], align 4 +; O3DIS-NEXT: [[WIDE_LOAD1_6:%.*]] = load <4 x i32>, ptr [[TMP35]], align 4 +; O3DIS-NEXT: [[TMP36:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_6]], [[BROADCAST_SPLAT]] +; O3DIS-NEXT: [[TMP37:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_6]], [[BROADCAST_SPLAT]] +; O3DIS-NEXT: [[TMP38:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 192 ; O3DIS-NEXT: [[TMP39:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 208 -; O3DIS-NEXT: store <4 x i32> [[TMP38]], ptr [[TMP39]], align 4 +; O3DIS-NEXT: store <4 x i32> [[TMP36]], ptr [[TMP38]], align 4 +; O3DIS-NEXT: store <4 x i32> [[TMP37]], ptr [[TMP39]], align 4 ; O3DIS-NEXT: [[TMP40:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 224 -; O3DIS-NEXT: [[WIDE_LOAD_14:%.*]] = load <4 x i32>, ptr [[TMP40]], align 4 -; O3DIS-NEXT: [[TMP41:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_14]], [[BROADCAST_SPLAT]] -; O3DIS-NEXT: [[TMP42:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 224 -; O3DIS-NEXT: store <4 x i32> [[TMP41]], ptr [[TMP42]], align 4 -; O3DIS-NEXT: [[TMP43:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 240 -; O3DIS-NEXT: [[WIDE_LOAD_15:%.*]] = load <4 x i32>, ptr [[TMP43]], align 4 -; O3DIS-NEXT: [[TMP44:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_15]], [[BROADCAST_SPLAT]] +; O3DIS-NEXT: [[TMP41:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 240 +; O3DIS-NEXT: [[WIDE_LOAD_7:%.*]] = load <4 x i32>, ptr [[TMP40]], align 4 +; O3DIS-NEXT: [[WIDE_LOAD1_7:%.*]] = load <4 x i32>, ptr [[TMP41]], align 4 +; O3DIS-NEXT: [[TMP42:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_7]], [[BROADCAST_SPLAT]] +; O3DIS-NEXT: [[TMP43:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_7]], [[BROADCAST_SPLAT]] +; O3DIS-NEXT: [[TMP44:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 224 ; O3DIS-NEXT: [[TMP45:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 240 -; O3DIS-NEXT: store <4 x i32> [[TMP44]], ptr [[TMP45]], align 4 +; O3DIS-NEXT: store <4 x i32> [[TMP42]], ptr [[TMP44]], align 4 +; O3DIS-NEXT: store <4 x i32> [[TMP43]], ptr [[TMP45]], align 4 ; O3DIS-NEXT: [[TMP46:%.*]] = load i32, ptr [[A]], align 4 ; O3DIS-NEXT: ret i32 [[TMP46]] ; @@ -823,84 +823,84 @@ define i32 @nopragma(ptr noalias nocapture %a, ptr noalias nocapture readonly %b ; O2-NEXT: entry: ; O2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[N:%.*]], i64 0 ; O2-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer -; O2-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[B:%.*]], align 4 -; O2-NEXT: [[TMP0:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], [[BROADCAST_SPLAT]] -; O2-NEXT: store <4 x i32> [[TMP0]], ptr [[A:%.*]], align 4 -; O2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 16 -; O2-NEXT: [[WIDE_LOAD_1:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4 -; O2-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_1]], [[BROADCAST_SPLAT]] -; O2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 16 +; O2-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[B:%.*]], i64 16 +; O2-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[B]], align 4 +; O2-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4 +; O2-NEXT: [[TMP1:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[A:%.*]], i64 16 +; O2-NEXT: store <4 x i32> [[TMP1]], ptr [[A]], align 4 ; O2-NEXT: store <4 x i32> [[TMP2]], ptr [[TMP3]], align 4 ; O2-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 32 -; O2-NEXT: [[WIDE_LOAD_2:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 -; O2-NEXT: [[TMP5:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_2]], [[BROADCAST_SPLAT]] -; O2-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 32 -; O2-NEXT: store <4 x i32> [[TMP5]], ptr [[TMP6]], align 4 -; O2-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 48 -; O2-NEXT: [[WIDE_LOAD_3:%.*]] = load <4 x i32>, ptr [[TMP7]], align 4 -; O2-NEXT: [[TMP8:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_3]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 48 +; O2-NEXT: [[WIDE_LOAD_1:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 +; O2-NEXT: [[WIDE_LOAD1_1:%.*]] = load <4 x i32>, ptr [[TMP5]], align 4 +; O2-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_1]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP7:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_1]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 32 ; O2-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 48 -; O2-NEXT: store <4 x i32> [[TMP8]], ptr [[TMP9]], align 4 +; O2-NEXT: store <4 x i32> [[TMP6]], ptr [[TMP8]], align 4 +; O2-NEXT: store <4 x i32> [[TMP7]], ptr [[TMP9]], align 4 ; O2-NEXT: [[TMP10:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 64 -; O2-NEXT: [[WIDE_LOAD_4:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4 -; O2-NEXT: [[TMP11:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_4]], [[BROADCAST_SPLAT]] -; O2-NEXT: [[TMP12:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 64 -; O2-NEXT: store <4 x i32> [[TMP11]], ptr [[TMP12]], align 4 -; O2-NEXT: [[TMP13:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 80 -; O2-NEXT: [[WIDE_LOAD_5:%.*]] = load <4 x i32>, ptr [[TMP13]], align 4 -; O2-NEXT: [[TMP14:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_5]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP11:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 80 +; O2-NEXT: [[WIDE_LOAD_2:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4 +; O2-NEXT: [[WIDE_LOAD1_2:%.*]] = load <4 x i32>, ptr [[TMP11]], align 4 +; O2-NEXT: [[TMP12:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_2]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP13:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_2]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 64 ; O2-NEXT: [[TMP15:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 80 -; O2-NEXT: store <4 x i32> [[TMP14]], ptr [[TMP15]], align 4 +; O2-NEXT: store <4 x i32> [[TMP12]], ptr [[TMP14]], align 4 +; O2-NEXT: store <4 x i32> [[TMP13]], ptr [[TMP15]], align 4 ; O2-NEXT: [[TMP16:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 96 -; O2-NEXT: [[WIDE_LOAD_6:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4 -; O2-NEXT: [[TMP17:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_6]], [[BROADCAST_SPLAT]] -; O2-NEXT: [[TMP18:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 96 -; O2-NEXT: store <4 x i32> [[TMP17]], ptr [[TMP18]], align 4 -; O2-NEXT: [[TMP19:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 112 -; O2-NEXT: [[WIDE_LOAD_7:%.*]] = load <4 x i32>, ptr [[TMP19]], align 4 -; O2-NEXT: [[TMP20:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_7]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP17:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 112 +; O2-NEXT: [[WIDE_LOAD_3:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4 +; O2-NEXT: [[WIDE_LOAD1_3:%.*]] = load <4 x i32>, ptr [[TMP17]], align 4 +; O2-NEXT: [[TMP18:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_3]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP19:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_3]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP20:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 96 ; O2-NEXT: [[TMP21:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 112 -; O2-NEXT: store <4 x i32> [[TMP20]], ptr [[TMP21]], align 4 +; O2-NEXT: store <4 x i32> [[TMP18]], ptr [[TMP20]], align 4 +; O2-NEXT: store <4 x i32> [[TMP19]], ptr [[TMP21]], align 4 ; O2-NEXT: [[TMP22:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 128 -; O2-NEXT: [[WIDE_LOAD_8:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4 -; O2-NEXT: [[TMP23:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_8]], [[BROADCAST_SPLAT]] -; O2-NEXT: [[TMP24:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 128 -; O2-NEXT: store <4 x i32> [[TMP23]], ptr [[TMP24]], align 4 -; O2-NEXT: [[TMP25:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 144 -; O2-NEXT: [[WIDE_LOAD_9:%.*]] = load <4 x i32>, ptr [[TMP25]], align 4 -; O2-NEXT: [[TMP26:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_9]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP23:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 144 +; O2-NEXT: [[WIDE_LOAD_4:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4 +; O2-NEXT: [[WIDE_LOAD1_4:%.*]] = load <4 x i32>, ptr [[TMP23]], align 4 +; O2-NEXT: [[TMP24:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_4]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP25:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_4]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP26:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 128 ; O2-NEXT: [[TMP27:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 144 -; O2-NEXT: store <4 x i32> [[TMP26]], ptr [[TMP27]], align 4 +; O2-NEXT: store <4 x i32> [[TMP24]], ptr [[TMP26]], align 4 +; O2-NEXT: store <4 x i32> [[TMP25]], ptr [[TMP27]], align 4 ; O2-NEXT: [[TMP28:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 160 -; O2-NEXT: [[WIDE_LOAD_10:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4 -; O2-NEXT: [[TMP29:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_10]], [[BROADCAST_SPLAT]] -; O2-NEXT: [[TMP30:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 160 -; O2-NEXT: store <4 x i32> [[TMP29]], ptr [[TMP30]], align 4 -; O2-NEXT: [[TMP31:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 176 -; O2-NEXT: [[WIDE_LOAD_11:%.*]] = load <4 x i32>, ptr [[TMP31]], align 4 -; O2-NEXT: [[TMP32:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_11]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP29:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 176 +; O2-NEXT: [[WIDE_LOAD_5:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4 +; O2-NEXT: [[WIDE_LOAD1_5:%.*]] = load <4 x i32>, ptr [[TMP29]], align 4 +; O2-NEXT: [[TMP30:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_5]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP31:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_5]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP32:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 160 ; O2-NEXT: [[TMP33:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 176 -; O2-NEXT: store <4 x i32> [[TMP32]], ptr [[TMP33]], align 4 +; O2-NEXT: store <4 x i32> [[TMP30]], ptr [[TMP32]], align 4 +; O2-NEXT: store <4 x i32> [[TMP31]], ptr [[TMP33]], align 4 ; O2-NEXT: [[TMP34:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 192 -; O2-NEXT: [[WIDE_LOAD_12:%.*]] = load <4 x i32>, ptr [[TMP34]], align 4 -; O2-NEXT: [[TMP35:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_12]], [[BROADCAST_SPLAT]] -; O2-NEXT: [[TMP36:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 192 -; O2-NEXT: store <4 x i32> [[TMP35]], ptr [[TMP36]], align 4 -; O2-NEXT: [[TMP37:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 208 -; O2-NEXT: [[WIDE_LOAD_13:%.*]] = load <4 x i32>, ptr [[TMP37]], align 4 -; O2-NEXT: [[TMP38:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_13]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP35:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 208 +; O2-NEXT: [[WIDE_LOAD_6:%.*]] = load <4 x i32>, ptr [[TMP34]], align 4 +; O2-NEXT: [[WIDE_LOAD1_6:%.*]] = load <4 x i32>, ptr [[TMP35]], align 4 +; O2-NEXT: [[TMP36:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_6]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP37:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_6]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP38:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 192 ; O2-NEXT: [[TMP39:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 208 -; O2-NEXT: store <4 x i32> [[TMP38]], ptr [[TMP39]], align 4 +; O2-NEXT: store <4 x i32> [[TMP36]], ptr [[TMP38]], align 4 +; O2-NEXT: store <4 x i32> [[TMP37]], ptr [[TMP39]], align 4 ; O2-NEXT: [[TMP40:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 224 -; O2-NEXT: [[WIDE_LOAD_14:%.*]] = load <4 x i32>, ptr [[TMP40]], align 4 -; O2-NEXT: [[TMP41:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_14]], [[BROADCAST_SPLAT]] -; O2-NEXT: [[TMP42:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 224 -; O2-NEXT: store <4 x i32> [[TMP41]], ptr [[TMP42]], align 4 -; O2-NEXT: [[TMP43:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 240 -; O2-NEXT: [[WIDE_LOAD_15:%.*]] = load <4 x i32>, ptr [[TMP43]], align 4 -; O2-NEXT: [[TMP44:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_15]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP41:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 240 +; O2-NEXT: [[WIDE_LOAD_7:%.*]] = load <4 x i32>, ptr [[TMP40]], align 4 +; O2-NEXT: [[WIDE_LOAD1_7:%.*]] = load <4 x i32>, ptr [[TMP41]], align 4 +; O2-NEXT: [[TMP42:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_7]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP43:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_7]], [[BROADCAST_SPLAT]] +; O2-NEXT: [[TMP44:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 224 ; O2-NEXT: [[TMP45:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 240 -; O2-NEXT: store <4 x i32> [[TMP44]], ptr [[TMP45]], align 4 +; O2-NEXT: store <4 x i32> [[TMP42]], ptr [[TMP44]], align 4 +; O2-NEXT: store <4 x i32> [[TMP43]], ptr [[TMP45]], align 4 ; O2-NEXT: [[TMP46:%.*]] = load i32, ptr [[A]], align 4 ; O2-NEXT: ret i32 [[TMP46]] ; @@ -908,84 +908,84 @@ define i32 @nopragma(ptr noalias nocapture %a, ptr noalias nocapture readonly %b ; O3-NEXT: entry: ; O3-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[N:%.*]], i64 0 ; O3-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer -; O3-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[B:%.*]], align 4 -; O3-NEXT: [[TMP0:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], [[BROADCAST_SPLAT]] -; O3-NEXT: store <4 x i32> [[TMP0]], ptr [[A:%.*]], align 4 -; O3-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 16 -; O3-NEXT: [[WIDE_LOAD_1:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4 -; O3-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_1]], [[BROADCAST_SPLAT]] -; O3-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 16 +; O3-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[B:%.*]], i64 16 +; O3-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[B]], align 4 +; O3-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4 +; O3-NEXT: [[TMP1:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[A:%.*]], i64 16 +; O3-NEXT: store <4 x i32> [[TMP1]], ptr [[A]], align 4 ; O3-NEXT: store <4 x i32> [[TMP2]], ptr [[TMP3]], align 4 ; O3-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 32 -; O3-NEXT: [[WIDE_LOAD_2:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 -; O3-NEXT: [[TMP5:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_2]], [[BROADCAST_SPLAT]] -; O3-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 32 -; O3-NEXT: store <4 x i32> [[TMP5]], ptr [[TMP6]], align 4 -; O3-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 48 -; O3-NEXT: [[WIDE_LOAD_3:%.*]] = load <4 x i32>, ptr [[TMP7]], align 4 -; O3-NEXT: [[TMP8:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_3]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 48 +; O3-NEXT: [[WIDE_LOAD_1:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 +; O3-NEXT: [[WIDE_LOAD1_1:%.*]] = load <4 x i32>, ptr [[TMP5]], align 4 +; O3-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_1]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP7:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_1]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 32 ; O3-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 48 -; O3-NEXT: store <4 x i32> [[TMP8]], ptr [[TMP9]], align 4 +; O3-NEXT: store <4 x i32> [[TMP6]], ptr [[TMP8]], align 4 +; O3-NEXT: store <4 x i32> [[TMP7]], ptr [[TMP9]], align 4 ; O3-NEXT: [[TMP10:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 64 -; O3-NEXT: [[WIDE_LOAD_4:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4 -; O3-NEXT: [[TMP11:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_4]], [[BROADCAST_SPLAT]] -; O3-NEXT: [[TMP12:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 64 -; O3-NEXT: store <4 x i32> [[TMP11]], ptr [[TMP12]], align 4 -; O3-NEXT: [[TMP13:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 80 -; O3-NEXT: [[WIDE_LOAD_5:%.*]] = load <4 x i32>, ptr [[TMP13]], align 4 -; O3-NEXT: [[TMP14:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_5]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP11:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 80 +; O3-NEXT: [[WIDE_LOAD_2:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4 +; O3-NEXT: [[WIDE_LOAD1_2:%.*]] = load <4 x i32>, ptr [[TMP11]], align 4 +; O3-NEXT: [[TMP12:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_2]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP13:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_2]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 64 ; O3-NEXT: [[TMP15:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 80 -; O3-NEXT: store <4 x i32> [[TMP14]], ptr [[TMP15]], align 4 +; O3-NEXT: store <4 x i32> [[TMP12]], ptr [[TMP14]], align 4 +; O3-NEXT: store <4 x i32> [[TMP13]], ptr [[TMP15]], align 4 ; O3-NEXT: [[TMP16:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 96 -; O3-NEXT: [[WIDE_LOAD_6:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4 -; O3-NEXT: [[TMP17:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_6]], [[BROADCAST_SPLAT]] -; O3-NEXT: [[TMP18:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 96 -; O3-NEXT: store <4 x i32> [[TMP17]], ptr [[TMP18]], align 4 -; O3-NEXT: [[TMP19:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 112 -; O3-NEXT: [[WIDE_LOAD_7:%.*]] = load <4 x i32>, ptr [[TMP19]], align 4 -; O3-NEXT: [[TMP20:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_7]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP17:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 112 +; O3-NEXT: [[WIDE_LOAD_3:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4 +; O3-NEXT: [[WIDE_LOAD1_3:%.*]] = load <4 x i32>, ptr [[TMP17]], align 4 +; O3-NEXT: [[TMP18:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_3]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP19:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_3]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP20:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 96 ; O3-NEXT: [[TMP21:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 112 -; O3-NEXT: store <4 x i32> [[TMP20]], ptr [[TMP21]], align 4 +; O3-NEXT: store <4 x i32> [[TMP18]], ptr [[TMP20]], align 4 +; O3-NEXT: store <4 x i32> [[TMP19]], ptr [[TMP21]], align 4 ; O3-NEXT: [[TMP22:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 128 -; O3-NEXT: [[WIDE_LOAD_8:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4 -; O3-NEXT: [[TMP23:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_8]], [[BROADCAST_SPLAT]] -; O3-NEXT: [[TMP24:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 128 -; O3-NEXT: store <4 x i32> [[TMP23]], ptr [[TMP24]], align 4 -; O3-NEXT: [[TMP25:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 144 -; O3-NEXT: [[WIDE_LOAD_9:%.*]] = load <4 x i32>, ptr [[TMP25]], align 4 -; O3-NEXT: [[TMP26:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_9]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP23:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 144 +; O3-NEXT: [[WIDE_LOAD_4:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4 +; O3-NEXT: [[WIDE_LOAD1_4:%.*]] = load <4 x i32>, ptr [[TMP23]], align 4 +; O3-NEXT: [[TMP24:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_4]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP25:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_4]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP26:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 128 ; O3-NEXT: [[TMP27:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 144 -; O3-NEXT: store <4 x i32> [[TMP26]], ptr [[TMP27]], align 4 +; O3-NEXT: store <4 x i32> [[TMP24]], ptr [[TMP26]], align 4 +; O3-NEXT: store <4 x i32> [[TMP25]], ptr [[TMP27]], align 4 ; O3-NEXT: [[TMP28:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 160 -; O3-NEXT: [[WIDE_LOAD_10:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4 -; O3-NEXT: [[TMP29:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_10]], [[BROADCAST_SPLAT]] -; O3-NEXT: [[TMP30:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 160 -; O3-NEXT: store <4 x i32> [[TMP29]], ptr [[TMP30]], align 4 -; O3-NEXT: [[TMP31:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 176 -; O3-NEXT: [[WIDE_LOAD_11:%.*]] = load <4 x i32>, ptr [[TMP31]], align 4 -; O3-NEXT: [[TMP32:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_11]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP29:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 176 +; O3-NEXT: [[WIDE_LOAD_5:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4 +; O3-NEXT: [[WIDE_LOAD1_5:%.*]] = load <4 x i32>, ptr [[TMP29]], align 4 +; O3-NEXT: [[TMP30:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_5]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP31:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_5]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP32:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 160 ; O3-NEXT: [[TMP33:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 176 -; O3-NEXT: store <4 x i32> [[TMP32]], ptr [[TMP33]], align 4 +; O3-NEXT: store <4 x i32> [[TMP30]], ptr [[TMP32]], align 4 +; O3-NEXT: store <4 x i32> [[TMP31]], ptr [[TMP33]], align 4 ; O3-NEXT: [[TMP34:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 192 -; O3-NEXT: [[WIDE_LOAD_12:%.*]] = load <4 x i32>, ptr [[TMP34]], align 4 -; O3-NEXT: [[TMP35:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_12]], [[BROADCAST_SPLAT]] -; O3-NEXT: [[TMP36:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 192 -; O3-NEXT: store <4 x i32> [[TMP35]], ptr [[TMP36]], align 4 -; O3-NEXT: [[TMP37:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 208 -; O3-NEXT: [[WIDE_LOAD_13:%.*]] = load <4 x i32>, ptr [[TMP37]], align 4 -; O3-NEXT: [[TMP38:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_13]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP35:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 208 +; O3-NEXT: [[WIDE_LOAD_6:%.*]] = load <4 x i32>, ptr [[TMP34]], align 4 +; O3-NEXT: [[WIDE_LOAD1_6:%.*]] = load <4 x i32>, ptr [[TMP35]], align 4 +; O3-NEXT: [[TMP36:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_6]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP37:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_6]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP38:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 192 ; O3-NEXT: [[TMP39:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 208 -; O3-NEXT: store <4 x i32> [[TMP38]], ptr [[TMP39]], align 4 +; O3-NEXT: store <4 x i32> [[TMP36]], ptr [[TMP38]], align 4 +; O3-NEXT: store <4 x i32> [[TMP37]], ptr [[TMP39]], align 4 ; O3-NEXT: [[TMP40:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 224 -; O3-NEXT: [[WIDE_LOAD_14:%.*]] = load <4 x i32>, ptr [[TMP40]], align 4 -; O3-NEXT: [[TMP41:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_14]], [[BROADCAST_SPLAT]] -; O3-NEXT: [[TMP42:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 224 -; O3-NEXT: store <4 x i32> [[TMP41]], ptr [[TMP42]], align 4 -; O3-NEXT: [[TMP43:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 240 -; O3-NEXT: [[WIDE_LOAD_15:%.*]] = load <4 x i32>, ptr [[TMP43]], align 4 -; O3-NEXT: [[TMP44:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_15]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP41:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 240 +; O3-NEXT: [[WIDE_LOAD_7:%.*]] = load <4 x i32>, ptr [[TMP40]], align 4 +; O3-NEXT: [[WIDE_LOAD1_7:%.*]] = load <4 x i32>, ptr [[TMP41]], align 4 +; O3-NEXT: [[TMP42:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_7]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP43:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_7]], [[BROADCAST_SPLAT]] +; O3-NEXT: [[TMP44:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 224 ; O3-NEXT: [[TMP45:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 240 -; O3-NEXT: store <4 x i32> [[TMP44]], ptr [[TMP45]], align 4 +; O3-NEXT: store <4 x i32> [[TMP42]], ptr [[TMP44]], align 4 +; O3-NEXT: store <4 x i32> [[TMP43]], ptr [[TMP45]], align 4 ; O3-NEXT: [[TMP46:%.*]] = load i32, ptr [[A]], align 4 ; O3-NEXT: ret i32 [[TMP46]] ; @@ -993,84 +993,84 @@ define i32 @nopragma(ptr noalias nocapture %a, ptr noalias nocapture readonly %b ; O3DEFAULT-NEXT: entry: ; O3DEFAULT-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[N:%.*]], i64 0 ; O3DEFAULT-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer -; O3DEFAULT-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[B:%.*]], align 4 -; O3DEFAULT-NEXT: [[TMP0:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], [[BROADCAST_SPLAT]] -; O3DEFAULT-NEXT: store <4 x i32> [[TMP0]], ptr [[A:%.*]], align 4 -; O3DEFAULT-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 16 -; O3DEFAULT-NEXT: [[WIDE_LOAD_1:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4 -; O3DEFAULT-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_1]], [[BROADCAST_SPLAT]] -; O3DEFAULT-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 16 +; O3DEFAULT-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[B:%.*]], i64 16 +; O3DEFAULT-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[B]], align 4 +; O3DEFAULT-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4 +; O3DEFAULT-NEXT: [[TMP1:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[A:%.*]], i64 16 +; O3DEFAULT-NEXT: store <4 x i32> [[TMP1]], ptr [[A]], align 4 ; O3DEFAULT-NEXT: store <4 x i32> [[TMP2]], ptr [[TMP3]], align 4 ; O3DEFAULT-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 32 -; O3DEFAULT-NEXT: [[WIDE_LOAD_2:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 -; O3DEFAULT-NEXT: [[TMP5:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_2]], [[BROADCAST_SPLAT]] -; O3DEFAULT-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 32 -; O3DEFAULT-NEXT: store <4 x i32> [[TMP5]], ptr [[TMP6]], align 4 -; O3DEFAULT-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 48 -; O3DEFAULT-NEXT: [[WIDE_LOAD_3:%.*]] = load <4 x i32>, ptr [[TMP7]], align 4 -; O3DEFAULT-NEXT: [[TMP8:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_3]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 48 +; O3DEFAULT-NEXT: [[WIDE_LOAD_1:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 +; O3DEFAULT-NEXT: [[WIDE_LOAD1_1:%.*]] = load <4 x i32>, ptr [[TMP5]], align 4 +; O3DEFAULT-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_1]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP7:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_1]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 32 ; O3DEFAULT-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 48 -; O3DEFAULT-NEXT: store <4 x i32> [[TMP8]], ptr [[TMP9]], align 4 +; O3DEFAULT-NEXT: store <4 x i32> [[TMP6]], ptr [[TMP8]], align 4 +; O3DEFAULT-NEXT: store <4 x i32> [[TMP7]], ptr [[TMP9]], align 4 ; O3DEFAULT-NEXT: [[TMP10:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 64 -; O3DEFAULT-NEXT: [[WIDE_LOAD_4:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4 -; O3DEFAULT-NEXT: [[TMP11:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_4]], [[BROADCAST_SPLAT]] -; O3DEFAULT-NEXT: [[TMP12:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 64 -; O3DEFAULT-NEXT: store <4 x i32> [[TMP11]], ptr [[TMP12]], align 4 -; O3DEFAULT-NEXT: [[TMP13:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 80 -; O3DEFAULT-NEXT: [[WIDE_LOAD_5:%.*]] = load <4 x i32>, ptr [[TMP13]], align 4 -; O3DEFAULT-NEXT: [[TMP14:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_5]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP11:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 80 +; O3DEFAULT-NEXT: [[WIDE_LOAD_2:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4 +; O3DEFAULT-NEXT: [[WIDE_LOAD1_2:%.*]] = load <4 x i32>, ptr [[TMP11]], align 4 +; O3DEFAULT-NEXT: [[TMP12:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_2]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP13:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_2]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 64 ; O3DEFAULT-NEXT: [[TMP15:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 80 -; O3DEFAULT-NEXT: store <4 x i32> [[TMP14]], ptr [[TMP15]], align 4 +; O3DEFAULT-NEXT: store <4 x i32> [[TMP12]], ptr [[TMP14]], align 4 +; O3DEFAULT-NEXT: store <4 x i32> [[TMP13]], ptr [[TMP15]], align 4 ; O3DEFAULT-NEXT: [[TMP16:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 96 -; O3DEFAULT-NEXT: [[WIDE_LOAD_6:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4 -; O3DEFAULT-NEXT: [[TMP17:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_6]], [[BROADCAST_SPLAT]] -; O3DEFAULT-NEXT: [[TMP18:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 96 -; O3DEFAULT-NEXT: store <4 x i32> [[TMP17]], ptr [[TMP18]], align 4 -; O3DEFAULT-NEXT: [[TMP19:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 112 -; O3DEFAULT-NEXT: [[WIDE_LOAD_7:%.*]] = load <4 x i32>, ptr [[TMP19]], align 4 -; O3DEFAULT-NEXT: [[TMP20:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_7]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP17:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 112 +; O3DEFAULT-NEXT: [[WIDE_LOAD_3:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4 +; O3DEFAULT-NEXT: [[WIDE_LOAD1_3:%.*]] = load <4 x i32>, ptr [[TMP17]], align 4 +; O3DEFAULT-NEXT: [[TMP18:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_3]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP19:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_3]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP20:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 96 ; O3DEFAULT-NEXT: [[TMP21:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 112 -; O3DEFAULT-NEXT: store <4 x i32> [[TMP20]], ptr [[TMP21]], align 4 +; O3DEFAULT-NEXT: store <4 x i32> [[TMP18]], ptr [[TMP20]], align 4 +; O3DEFAULT-NEXT: store <4 x i32> [[TMP19]], ptr [[TMP21]], align 4 ; O3DEFAULT-NEXT: [[TMP22:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 128 -; O3DEFAULT-NEXT: [[WIDE_LOAD_8:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4 -; O3DEFAULT-NEXT: [[TMP23:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_8]], [[BROADCAST_SPLAT]] -; O3DEFAULT-NEXT: [[TMP24:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 128 -; O3DEFAULT-NEXT: store <4 x i32> [[TMP23]], ptr [[TMP24]], align 4 -; O3DEFAULT-NEXT: [[TMP25:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 144 -; O3DEFAULT-NEXT: [[WIDE_LOAD_9:%.*]] = load <4 x i32>, ptr [[TMP25]], align 4 -; O3DEFAULT-NEXT: [[TMP26:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_9]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP23:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 144 +; O3DEFAULT-NEXT: [[WIDE_LOAD_4:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4 +; O3DEFAULT-NEXT: [[WIDE_LOAD1_4:%.*]] = load <4 x i32>, ptr [[TMP23]], align 4 +; O3DEFAULT-NEXT: [[TMP24:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_4]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP25:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_4]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP26:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 128 ; O3DEFAULT-NEXT: [[TMP27:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 144 -; O3DEFAULT-NEXT: store <4 x i32> [[TMP26]], ptr [[TMP27]], align 4 +; O3DEFAULT-NEXT: store <4 x i32> [[TMP24]], ptr [[TMP26]], align 4 +; O3DEFAULT-NEXT: store <4 x i32> [[TMP25]], ptr [[TMP27]], align 4 ; O3DEFAULT-NEXT: [[TMP28:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 160 -; O3DEFAULT-NEXT: [[WIDE_LOAD_10:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4 -; O3DEFAULT-NEXT: [[TMP29:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_10]], [[BROADCAST_SPLAT]] -; O3DEFAULT-NEXT: [[TMP30:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 160 -; O3DEFAULT-NEXT: store <4 x i32> [[TMP29]], ptr [[TMP30]], align 4 -; O3DEFAULT-NEXT: [[TMP31:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 176 -; O3DEFAULT-NEXT: [[WIDE_LOAD_11:%.*]] = load <4 x i32>, ptr [[TMP31]], align 4 -; O3DEFAULT-NEXT: [[TMP32:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_11]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP29:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 176 +; O3DEFAULT-NEXT: [[WIDE_LOAD_5:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4 +; O3DEFAULT-NEXT: [[WIDE_LOAD1_5:%.*]] = load <4 x i32>, ptr [[TMP29]], align 4 +; O3DEFAULT-NEXT: [[TMP30:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_5]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP31:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_5]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP32:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 160 ; O3DEFAULT-NEXT: [[TMP33:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 176 -; O3DEFAULT-NEXT: store <4 x i32> [[TMP32]], ptr [[TMP33]], align 4 +; O3DEFAULT-NEXT: store <4 x i32> [[TMP30]], ptr [[TMP32]], align 4 +; O3DEFAULT-NEXT: store <4 x i32> [[TMP31]], ptr [[TMP33]], align 4 ; O3DEFAULT-NEXT: [[TMP34:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 192 -; O3DEFAULT-NEXT: [[WIDE_LOAD_12:%.*]] = load <4 x i32>, ptr [[TMP34]], align 4 -; O3DEFAULT-NEXT: [[TMP35:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_12]], [[BROADCAST_SPLAT]] -; O3DEFAULT-NEXT: [[TMP36:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 192 -; O3DEFAULT-NEXT: store <4 x i32> [[TMP35]], ptr [[TMP36]], align 4 -; O3DEFAULT-NEXT: [[TMP37:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 208 -; O3DEFAULT-NEXT: [[WIDE_LOAD_13:%.*]] = load <4 x i32>, ptr [[TMP37]], align 4 -; O3DEFAULT-NEXT: [[TMP38:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_13]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP35:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 208 +; O3DEFAULT-NEXT: [[WIDE_LOAD_6:%.*]] = load <4 x i32>, ptr [[TMP34]], align 4 +; O3DEFAULT-NEXT: [[WIDE_LOAD1_6:%.*]] = load <4 x i32>, ptr [[TMP35]], align 4 +; O3DEFAULT-NEXT: [[TMP36:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_6]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP37:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_6]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP38:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 192 ; O3DEFAULT-NEXT: [[TMP39:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 208 -; O3DEFAULT-NEXT: store <4 x i32> [[TMP38]], ptr [[TMP39]], align 4 +; O3DEFAULT-NEXT: store <4 x i32> [[TMP36]], ptr [[TMP38]], align 4 +; O3DEFAULT-NEXT: store <4 x i32> [[TMP37]], ptr [[TMP39]], align 4 ; O3DEFAULT-NEXT: [[TMP40:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 224 -; O3DEFAULT-NEXT: [[WIDE_LOAD_14:%.*]] = load <4 x i32>, ptr [[TMP40]], align 4 -; O3DEFAULT-NEXT: [[TMP41:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_14]], [[BROADCAST_SPLAT]] -; O3DEFAULT-NEXT: [[TMP42:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 224 -; O3DEFAULT-NEXT: store <4 x i32> [[TMP41]], ptr [[TMP42]], align 4 -; O3DEFAULT-NEXT: [[TMP43:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 240 -; O3DEFAULT-NEXT: [[WIDE_LOAD_15:%.*]] = load <4 x i32>, ptr [[TMP43]], align 4 -; O3DEFAULT-NEXT: [[TMP44:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_15]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP41:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 240 +; O3DEFAULT-NEXT: [[WIDE_LOAD_7:%.*]] = load <4 x i32>, ptr [[TMP40]], align 4 +; O3DEFAULT-NEXT: [[WIDE_LOAD1_7:%.*]] = load <4 x i32>, ptr [[TMP41]], align 4 +; O3DEFAULT-NEXT: [[TMP42:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_7]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP43:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_7]], [[BROADCAST_SPLAT]] +; O3DEFAULT-NEXT: [[TMP44:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 224 ; O3DEFAULT-NEXT: [[TMP45:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 240 -; O3DEFAULT-NEXT: store <4 x i32> [[TMP44]], ptr [[TMP45]], align 4 +; O3DEFAULT-NEXT: store <4 x i32> [[TMP42]], ptr [[TMP44]], align 4 +; O3DEFAULT-NEXT: store <4 x i32> [[TMP43]], ptr [[TMP45]], align 4 ; O3DEFAULT-NEXT: [[TMP46:%.*]] = load i32, ptr [[A]], align 4 ; O3DEFAULT-NEXT: ret i32 [[TMP46]] ; @@ -1078,84 +1078,84 @@ define i32 @nopragma(ptr noalias nocapture %a, ptr noalias nocapture readonly %b ; Os-NEXT: entry: ; Os-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[N:%.*]], i64 0 ; Os-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer -; Os-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[B:%.*]], align 4 -; Os-NEXT: [[TMP0:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], [[BROADCAST_SPLAT]] -; Os-NEXT: store <4 x i32> [[TMP0]], ptr [[A:%.*]], align 4 -; Os-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 16 -; Os-NEXT: [[WIDE_LOAD_1:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4 -; Os-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_1]], [[BROADCAST_SPLAT]] -; Os-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 16 +; Os-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[B:%.*]], i64 16 +; Os-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[B]], align 4 +; Os-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4 +; Os-NEXT: [[TMP1:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[A:%.*]], i64 16 +; Os-NEXT: store <4 x i32> [[TMP1]], ptr [[A]], align 4 ; Os-NEXT: store <4 x i32> [[TMP2]], ptr [[TMP3]], align 4 ; Os-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 32 -; Os-NEXT: [[WIDE_LOAD_2:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 -; Os-NEXT: [[TMP5:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_2]], [[BROADCAST_SPLAT]] -; Os-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 32 -; Os-NEXT: store <4 x i32> [[TMP5]], ptr [[TMP6]], align 4 -; Os-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 48 -; Os-NEXT: [[WIDE_LOAD_3:%.*]] = load <4 x i32>, ptr [[TMP7]], align 4 -; Os-NEXT: [[TMP8:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_3]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 48 +; Os-NEXT: [[WIDE_LOAD_1:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 +; Os-NEXT: [[WIDE_LOAD1_1:%.*]] = load <4 x i32>, ptr [[TMP5]], align 4 +; Os-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_1]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP7:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_1]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 32 ; Os-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 48 -; Os-NEXT: store <4 x i32> [[TMP8]], ptr [[TMP9]], align 4 +; Os-NEXT: store <4 x i32> [[TMP6]], ptr [[TMP8]], align 4 +; Os-NEXT: store <4 x i32> [[TMP7]], ptr [[TMP9]], align 4 ; Os-NEXT: [[TMP10:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 64 -; Os-NEXT: [[WIDE_LOAD_4:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4 -; Os-NEXT: [[TMP11:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_4]], [[BROADCAST_SPLAT]] -; Os-NEXT: [[TMP12:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 64 -; Os-NEXT: store <4 x i32> [[TMP11]], ptr [[TMP12]], align 4 -; Os-NEXT: [[TMP13:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 80 -; Os-NEXT: [[WIDE_LOAD_5:%.*]] = load <4 x i32>, ptr [[TMP13]], align 4 -; Os-NEXT: [[TMP14:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_5]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP11:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 80 +; Os-NEXT: [[WIDE_LOAD_2:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4 +; Os-NEXT: [[WIDE_LOAD1_2:%.*]] = load <4 x i32>, ptr [[TMP11]], align 4 +; Os-NEXT: [[TMP12:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_2]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP13:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_2]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 64 ; Os-NEXT: [[TMP15:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 80 -; Os-NEXT: store <4 x i32> [[TMP14]], ptr [[TMP15]], align 4 +; Os-NEXT: store <4 x i32> [[TMP12]], ptr [[TMP14]], align 4 +; Os-NEXT: store <4 x i32> [[TMP13]], ptr [[TMP15]], align 4 ; Os-NEXT: [[TMP16:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 96 -; Os-NEXT: [[WIDE_LOAD_6:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4 -; Os-NEXT: [[TMP17:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_6]], [[BROADCAST_SPLAT]] -; Os-NEXT: [[TMP18:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 96 -; Os-NEXT: store <4 x i32> [[TMP17]], ptr [[TMP18]], align 4 -; Os-NEXT: [[TMP19:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 112 -; Os-NEXT: [[WIDE_LOAD_7:%.*]] = load <4 x i32>, ptr [[TMP19]], align 4 -; Os-NEXT: [[TMP20:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_7]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP17:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 112 +; Os-NEXT: [[WIDE_LOAD_3:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4 +; Os-NEXT: [[WIDE_LOAD1_3:%.*]] = load <4 x i32>, ptr [[TMP17]], align 4 +; Os-NEXT: [[TMP18:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_3]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP19:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_3]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP20:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 96 ; Os-NEXT: [[TMP21:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 112 -; Os-NEXT: store <4 x i32> [[TMP20]], ptr [[TMP21]], align 4 +; Os-NEXT: store <4 x i32> [[TMP18]], ptr [[TMP20]], align 4 +; Os-NEXT: store <4 x i32> [[TMP19]], ptr [[TMP21]], align 4 ; Os-NEXT: [[TMP22:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 128 -; Os-NEXT: [[WIDE_LOAD_8:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4 -; Os-NEXT: [[TMP23:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_8]], [[BROADCAST_SPLAT]] -; Os-NEXT: [[TMP24:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 128 -; Os-NEXT: store <4 x i32> [[TMP23]], ptr [[TMP24]], align 4 -; Os-NEXT: [[TMP25:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 144 -; Os-NEXT: [[WIDE_LOAD_9:%.*]] = load <4 x i32>, ptr [[TMP25]], align 4 -; Os-NEXT: [[TMP26:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_9]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP23:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 144 +; Os-NEXT: [[WIDE_LOAD_4:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4 +; Os-NEXT: [[WIDE_LOAD1_4:%.*]] = load <4 x i32>, ptr [[TMP23]], align 4 +; Os-NEXT: [[TMP24:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_4]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP25:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_4]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP26:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 128 ; Os-NEXT: [[TMP27:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 144 -; Os-NEXT: store <4 x i32> [[TMP26]], ptr [[TMP27]], align 4 +; Os-NEXT: store <4 x i32> [[TMP24]], ptr [[TMP26]], align 4 +; Os-NEXT: store <4 x i32> [[TMP25]], ptr [[TMP27]], align 4 ; Os-NEXT: [[TMP28:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 160 -; Os-NEXT: [[WIDE_LOAD_10:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4 -; Os-NEXT: [[TMP29:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_10]], [[BROADCAST_SPLAT]] -; Os-NEXT: [[TMP30:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 160 -; Os-NEXT: store <4 x i32> [[TMP29]], ptr [[TMP30]], align 4 -; Os-NEXT: [[TMP31:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 176 -; Os-NEXT: [[WIDE_LOAD_11:%.*]] = load <4 x i32>, ptr [[TMP31]], align 4 -; Os-NEXT: [[TMP32:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_11]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP29:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 176 +; Os-NEXT: [[WIDE_LOAD_5:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4 +; Os-NEXT: [[WIDE_LOAD1_5:%.*]] = load <4 x i32>, ptr [[TMP29]], align 4 +; Os-NEXT: [[TMP30:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_5]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP31:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_5]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP32:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 160 ; Os-NEXT: [[TMP33:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 176 -; Os-NEXT: store <4 x i32> [[TMP32]], ptr [[TMP33]], align 4 +; Os-NEXT: store <4 x i32> [[TMP30]], ptr [[TMP32]], align 4 +; Os-NEXT: store <4 x i32> [[TMP31]], ptr [[TMP33]], align 4 ; Os-NEXT: [[TMP34:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 192 -; Os-NEXT: [[WIDE_LOAD_12:%.*]] = load <4 x i32>, ptr [[TMP34]], align 4 -; Os-NEXT: [[TMP35:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_12]], [[BROADCAST_SPLAT]] -; Os-NEXT: [[TMP36:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 192 -; Os-NEXT: store <4 x i32> [[TMP35]], ptr [[TMP36]], align 4 -; Os-NEXT: [[TMP37:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 208 -; Os-NEXT: [[WIDE_LOAD_13:%.*]] = load <4 x i32>, ptr [[TMP37]], align 4 -; Os-NEXT: [[TMP38:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_13]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP35:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 208 +; Os-NEXT: [[WIDE_LOAD_6:%.*]] = load <4 x i32>, ptr [[TMP34]], align 4 +; Os-NEXT: [[WIDE_LOAD1_6:%.*]] = load <4 x i32>, ptr [[TMP35]], align 4 +; Os-NEXT: [[TMP36:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_6]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP37:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_6]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP38:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 192 ; Os-NEXT: [[TMP39:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 208 -; Os-NEXT: store <4 x i32> [[TMP38]], ptr [[TMP39]], align 4 +; Os-NEXT: store <4 x i32> [[TMP36]], ptr [[TMP38]], align 4 +; Os-NEXT: store <4 x i32> [[TMP37]], ptr [[TMP39]], align 4 ; Os-NEXT: [[TMP40:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 224 -; Os-NEXT: [[WIDE_LOAD_14:%.*]] = load <4 x i32>, ptr [[TMP40]], align 4 -; Os-NEXT: [[TMP41:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_14]], [[BROADCAST_SPLAT]] -; Os-NEXT: [[TMP42:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 224 -; Os-NEXT: store <4 x i32> [[TMP41]], ptr [[TMP42]], align 4 -; Os-NEXT: [[TMP43:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 240 -; Os-NEXT: [[WIDE_LOAD_15:%.*]] = load <4 x i32>, ptr [[TMP43]], align 4 -; Os-NEXT: [[TMP44:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_15]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP41:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 240 +; Os-NEXT: [[WIDE_LOAD_7:%.*]] = load <4 x i32>, ptr [[TMP40]], align 4 +; Os-NEXT: [[WIDE_LOAD1_7:%.*]] = load <4 x i32>, ptr [[TMP41]], align 4 +; Os-NEXT: [[TMP42:%.*]] = add nsw <4 x i32> [[WIDE_LOAD_7]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP43:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1_7]], [[BROADCAST_SPLAT]] +; Os-NEXT: [[TMP44:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 224 ; Os-NEXT: [[TMP45:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 240 -; Os-NEXT: store <4 x i32> [[TMP44]], ptr [[TMP45]], align 4 +; Os-NEXT: store <4 x i32> [[TMP42]], ptr [[TMP44]], align 4 +; Os-NEXT: store <4 x i32> [[TMP43]], ptr [[TMP45]], align 4 ; Os-NEXT: [[TMP46:%.*]] = load i32, ptr [[A]], align 4 ; Os-NEXT: ret i32 [[TMP46]] ; @@ -1186,16 +1186,24 @@ define i32 @nopragma(ptr noalias nocapture %a, ptr noalias nocapture readonly %b ; O1VEC2: vector.body: ; O1VEC2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; O1VEC2-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 -; O1VEC2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[B:%.*]], i64 [[TMP0]] -; O1VEC2-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0 -; O1VEC2-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4 -; O1VEC2-NEXT: [[TMP3:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], [[BROADCAST_SPLAT]] -; O1VEC2-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[TMP0]] -; O1VEC2-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i32 0 -; O1VEC2-NEXT: store <4 x i32> [[TMP3]], ptr [[TMP5]], align 4 -; O1VEC2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 -; O1VEC2-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 64 -; O1VEC2-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; O1VEC2-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 4 +; O1VEC2-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[B:%.*]], i64 [[TMP0]] +; O1VEC2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[TMP1]] +; O1VEC2-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i32 0 +; O1VEC2-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i32 4 +; O1VEC2-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 +; O1VEC2-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP5]], align 4 +; O1VEC2-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], [[BROADCAST_SPLAT]] +; O1VEC2-NEXT: [[TMP7:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1]], [[BROADCAST_SPLAT]] +; O1VEC2-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[TMP0]] +; O1VEC2-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP1]] +; O1VEC2-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[TMP8]], i32 0 +; O1VEC2-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[TMP8]], i32 4 +; O1VEC2-NEXT: store <4 x i32> [[TMP6]], ptr [[TMP10]], align 4 +; O1VEC2-NEXT: store <4 x i32> [[TMP7]], ptr [[TMP11]], align 4 +; O1VEC2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 +; O1VEC2-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 64 +; O1VEC2-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] ; O1VEC2: middle.block: ; O1VEC2-NEXT: br i1 true, label [[FOR_END:%.*]], label [[SCALAR_PH]] ; O1VEC2: scalar.ph: @@ -1204,16 +1212,16 @@ define i32 @nopragma(ptr noalias nocapture %a, ptr noalias nocapture readonly %b ; O1VEC2: for.body: ; O1VEC2-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ] ; O1VEC2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDVARS_IV]] -; O1VEC2-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 -; O1VEC2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[N]] +; O1VEC2-NEXT: [[TMP13:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +; O1VEC2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[N]] ; O1VEC2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV]] ; O1VEC2-NEXT: store i32 [[ADD]], ptr [[ARRAYIDX2]], align 4 ; O1VEC2-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; O1VEC2-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 64 ; O1VEC2-NEXT: br i1 [[EXITCOND]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]] ; O1VEC2: for.end: -; O1VEC2-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 -; O1VEC2-NEXT: ret i32 [[TMP8]] +; O1VEC2-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4 +; O1VEC2-NEXT: ret i32 [[TMP14]] ; ; OzVEC2-LABEL: @nopragma( ; OzVEC2-NEXT: entry: @@ -1225,16 +1233,24 @@ define i32 @nopragma(ptr noalias nocapture %a, ptr noalias nocapture readonly %b ; OzVEC2: vector.body: ; OzVEC2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; OzVEC2-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 -; OzVEC2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[B:%.*]], i64 [[TMP0]] -; OzVEC2-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0 -; OzVEC2-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4 -; OzVEC2-NEXT: [[TMP3:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], [[BROADCAST_SPLAT]] -; OzVEC2-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[TMP0]] -; OzVEC2-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i32 0 -; OzVEC2-NEXT: store <4 x i32> [[TMP3]], ptr [[TMP5]], align 4 -; OzVEC2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 -; OzVEC2-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 64 -; OzVEC2-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; OzVEC2-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 4 +; OzVEC2-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[B:%.*]], i64 [[TMP0]] +; OzVEC2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[TMP1]] +; OzVEC2-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i32 0 +; OzVEC2-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i32 4 +; OzVEC2-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 +; OzVEC2-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP5]], align 4 +; OzVEC2-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], [[BROADCAST_SPLAT]] +; OzVEC2-NEXT: [[TMP7:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1]], [[BROADCAST_SPLAT]] +; OzVEC2-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[TMP0]] +; OzVEC2-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP1]] +; OzVEC2-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[TMP8]], i32 0 +; OzVEC2-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[TMP8]], i32 4 +; OzVEC2-NEXT: store <4 x i32> [[TMP6]], ptr [[TMP10]], align 4 +; OzVEC2-NEXT: store <4 x i32> [[TMP7]], ptr [[TMP11]], align 4 +; OzVEC2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 +; OzVEC2-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 64 +; OzVEC2-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] ; OzVEC2: middle.block: ; OzVEC2-NEXT: br i1 true, label [[FOR_END:%.*]], label [[SCALAR_PH]] ; OzVEC2: scalar.ph: @@ -1243,16 +1259,16 @@ define i32 @nopragma(ptr noalias nocapture %a, ptr noalias nocapture readonly %b ; OzVEC2: for.body: ; OzVEC2-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ] ; OzVEC2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDVARS_IV]] -; OzVEC2-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 -; OzVEC2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[N]] +; OzVEC2-NEXT: [[TMP13:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +; OzVEC2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[N]] ; OzVEC2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV]] ; OzVEC2-NEXT: store i32 [[ADD]], ptr [[ARRAYIDX2]], align 4 ; OzVEC2-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; OzVEC2-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 64 ; OzVEC2-NEXT: br i1 [[EXITCOND]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]] ; OzVEC2: for.end: -; OzVEC2-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 -; OzVEC2-NEXT: ret i32 [[TMP8]] +; OzVEC2-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4 +; OzVEC2-NEXT: ret i32 [[TMP14]] ; ; O3DIS-LABEL: @nopragma( ; O3DIS-NEXT: entry: diff --git a/llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll b/llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll index 1917023394f0..a72e15870726 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll @@ -18,7 +18,10 @@ define i32 @matrix_row_col(ptr nocapture readonly %data, i32 %i, i32 %j) local_u ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <8 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP36:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <8 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP144:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <8 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP145:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <8 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP146:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <8 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP147:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 ; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2 @@ -27,62 +30,179 @@ define i32 @matrix_row_col(ptr nocapture readonly %data, i32 %i, i32 %j) local_u ; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 5 ; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[INDEX]], 6 ; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], 7 -; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA:%.*]], i64 [[IDXPROM]], i64 [[TMP0]] -; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[TMP8]], i32 0 -; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i32>, ptr [[TMP9]], align 4, !tbaa [[TBAA1:![0-9]+]] -; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP0]], i64 [[IDXPROM5]] -; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP1]], i64 [[IDXPROM5]] -; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP2]], i64 [[IDXPROM5]] -; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP3]], i64 [[IDXPROM5]] -; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP4]], i64 [[IDXPROM5]] -; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP5]], i64 [[IDXPROM5]] -; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP6]], i64 [[IDXPROM5]] -; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP7]], i64 [[IDXPROM5]] -; CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP10]], align 4, !tbaa [[TBAA1]] -; CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP11]], align 4, !tbaa [[TBAA1]] -; CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP12]], align 4, !tbaa [[TBAA1]] -; CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP13]], align 4, !tbaa [[TBAA1]] -; CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP14]], align 4, !tbaa [[TBAA1]] -; CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP15]], align 4, !tbaa [[TBAA1]] -; CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP16]], align 4, !tbaa [[TBAA1]] -; CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP17]], align 4, !tbaa [[TBAA1]] -; CHECK-NEXT: [[TMP26:%.*]] = insertelement <8 x i32> poison, i32 [[TMP18]], i32 0 -; CHECK-NEXT: [[TMP27:%.*]] = insertelement <8 x i32> [[TMP26]], i32 [[TMP19]], i32 1 -; CHECK-NEXT: [[TMP28:%.*]] = insertelement <8 x i32> [[TMP27]], i32 [[TMP20]], i32 2 -; CHECK-NEXT: [[TMP29:%.*]] = insertelement <8 x i32> [[TMP28]], i32 [[TMP21]], i32 3 -; CHECK-NEXT: [[TMP30:%.*]] = insertelement <8 x i32> [[TMP29]], i32 [[TMP22]], i32 4 -; CHECK-NEXT: [[TMP31:%.*]] = insertelement <8 x i32> [[TMP30]], i32 [[TMP23]], i32 5 -; CHECK-NEXT: [[TMP32:%.*]] = insertelement <8 x i32> [[TMP31]], i32 [[TMP24]], i32 6 -; CHECK-NEXT: [[TMP33:%.*]] = insertelement <8 x i32> [[TMP32]], i32 [[TMP25]], i32 7 -; CHECK-NEXT: [[TMP34:%.*]] = mul nsw <8 x i32> [[TMP33]], [[WIDE_LOAD]] -; CHECK-NEXT: [[TMP35:%.*]] = add <8 x i32> [[VEC_PHI]], -; CHECK-NEXT: [[TMP36]] = add <8 x i32> [[TMP35]], [[TMP34]] -; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 -; CHECK-NEXT: [[TMP37:%.*]] = icmp eq i64 [[INDEX_NEXT]], 96 -; CHECK-NEXT: br i1 [[TMP37]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]] +; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 8 +; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[INDEX]], 9 +; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[INDEX]], 10 +; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[INDEX]], 11 +; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[INDEX]], 12 +; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[INDEX]], 13 +; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[INDEX]], 14 +; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[INDEX]], 15 +; CHECK-NEXT: [[TMP16:%.*]] = add i64 [[INDEX]], 16 +; CHECK-NEXT: [[TMP17:%.*]] = add i64 [[INDEX]], 17 +; CHECK-NEXT: [[TMP18:%.*]] = add i64 [[INDEX]], 18 +; CHECK-NEXT: [[TMP19:%.*]] = add i64 [[INDEX]], 19 +; CHECK-NEXT: [[TMP20:%.*]] = add i64 [[INDEX]], 20 +; CHECK-NEXT: [[TMP21:%.*]] = add i64 [[INDEX]], 21 +; CHECK-NEXT: [[TMP22:%.*]] = add i64 [[INDEX]], 22 +; CHECK-NEXT: [[TMP23:%.*]] = add i64 [[INDEX]], 23 +; CHECK-NEXT: [[TMP24:%.*]] = add i64 [[INDEX]], 24 +; CHECK-NEXT: [[TMP25:%.*]] = add i64 [[INDEX]], 25 +; CHECK-NEXT: [[TMP26:%.*]] = add i64 [[INDEX]], 26 +; CHECK-NEXT: [[TMP27:%.*]] = add i64 [[INDEX]], 27 +; CHECK-NEXT: [[TMP28:%.*]] = add i64 [[INDEX]], 28 +; CHECK-NEXT: [[TMP29:%.*]] = add i64 [[INDEX]], 29 +; CHECK-NEXT: [[TMP30:%.*]] = add i64 [[INDEX]], 30 +; CHECK-NEXT: [[TMP31:%.*]] = add i64 [[INDEX]], 31 +; CHECK-NEXT: [[TMP32:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA:%.*]], i64 [[IDXPROM]], i64 [[TMP0]] +; CHECK-NEXT: [[TMP33:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[IDXPROM]], i64 [[TMP8]] +; CHECK-NEXT: [[TMP34:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[IDXPROM]], i64 [[TMP16]] +; CHECK-NEXT: [[TMP35:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[IDXPROM]], i64 [[TMP24]] +; CHECK-NEXT: [[TMP36:%.*]] = getelementptr inbounds i32, ptr [[TMP32]], i32 0 +; CHECK-NEXT: [[TMP37:%.*]] = getelementptr inbounds i32, ptr [[TMP32]], i32 8 +; CHECK-NEXT: [[TMP38:%.*]] = getelementptr inbounds i32, ptr [[TMP32]], i32 16 +; CHECK-NEXT: [[TMP39:%.*]] = getelementptr inbounds i32, ptr [[TMP32]], i32 24 +; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i32>, ptr [[TMP36]], align 4, !tbaa [[TBAA1:![0-9]+]] +; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <8 x i32>, ptr [[TMP37]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <8 x i32>, ptr [[TMP38]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <8 x i32>, ptr [[TMP39]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP40:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP0]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP41:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP1]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP42:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP2]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP43:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP3]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP44:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP4]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP45:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP5]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP46:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP6]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP47:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP7]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP48:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP8]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP49:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP9]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP50:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP10]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP51:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP11]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP52:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP12]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP53:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP13]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP54:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP14]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP55:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP15]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP56:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP16]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP57:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP17]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP58:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP18]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP59:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP19]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP60:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP20]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP61:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP21]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP62:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP22]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP63:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP23]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP64:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP24]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP65:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP25]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP66:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP26]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP67:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP27]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP68:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP28]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP69:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP29]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP70:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP30]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP71:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[TMP31]], i64 [[IDXPROM5]] +; CHECK-NEXT: [[TMP72:%.*]] = load i32, ptr [[TMP40]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP73:%.*]] = load i32, ptr [[TMP41]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP74:%.*]] = load i32, ptr [[TMP42]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP75:%.*]] = load i32, ptr [[TMP43]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP76:%.*]] = load i32, ptr [[TMP44]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP77:%.*]] = load i32, ptr [[TMP45]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP78:%.*]] = load i32, ptr [[TMP46]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP79:%.*]] = load i32, ptr [[TMP47]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP80:%.*]] = insertelement <8 x i32> poison, i32 [[TMP72]], i32 0 +; CHECK-NEXT: [[TMP81:%.*]] = insertelement <8 x i32> [[TMP80]], i32 [[TMP73]], i32 1 +; CHECK-NEXT: [[TMP82:%.*]] = insertelement <8 x i32> [[TMP81]], i32 [[TMP74]], i32 2 +; CHECK-NEXT: [[TMP83:%.*]] = insertelement <8 x i32> [[TMP82]], i32 [[TMP75]], i32 3 +; CHECK-NEXT: [[TMP84:%.*]] = insertelement <8 x i32> [[TMP83]], i32 [[TMP76]], i32 4 +; CHECK-NEXT: [[TMP85:%.*]] = insertelement <8 x i32> [[TMP84]], i32 [[TMP77]], i32 5 +; CHECK-NEXT: [[TMP86:%.*]] = insertelement <8 x i32> [[TMP85]], i32 [[TMP78]], i32 6 +; CHECK-NEXT: [[TMP87:%.*]] = insertelement <8 x i32> [[TMP86]], i32 [[TMP79]], i32 7 +; CHECK-NEXT: [[TMP88:%.*]] = load i32, ptr [[TMP48]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP89:%.*]] = load i32, ptr [[TMP49]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP90:%.*]] = load i32, ptr [[TMP50]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP91:%.*]] = load i32, ptr [[TMP51]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP92:%.*]] = load i32, ptr [[TMP52]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP93:%.*]] = load i32, ptr [[TMP53]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP94:%.*]] = load i32, ptr [[TMP54]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP95:%.*]] = load i32, ptr [[TMP55]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP96:%.*]] = insertelement <8 x i32> poison, i32 [[TMP88]], i32 0 +; CHECK-NEXT: [[TMP97:%.*]] = insertelement <8 x i32> [[TMP96]], i32 [[TMP89]], i32 1 +; CHECK-NEXT: [[TMP98:%.*]] = insertelement <8 x i32> [[TMP97]], i32 [[TMP90]], i32 2 +; CHECK-NEXT: [[TMP99:%.*]] = insertelement <8 x i32> [[TMP98]], i32 [[TMP91]], i32 3 +; CHECK-NEXT: [[TMP100:%.*]] = insertelement <8 x i32> [[TMP99]], i32 [[TMP92]], i32 4 +; CHECK-NEXT: [[TMP101:%.*]] = insertelement <8 x i32> [[TMP100]], i32 [[TMP93]], i32 5 +; CHECK-NEXT: [[TMP102:%.*]] = insertelement <8 x i32> [[TMP101]], i32 [[TMP94]], i32 6 +; CHECK-NEXT: [[TMP103:%.*]] = insertelement <8 x i32> [[TMP102]], i32 [[TMP95]], i32 7 +; CHECK-NEXT: [[TMP104:%.*]] = load i32, ptr [[TMP56]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP105:%.*]] = load i32, ptr [[TMP57]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP106:%.*]] = load i32, ptr [[TMP58]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP107:%.*]] = load i32, ptr [[TMP59]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP108:%.*]] = load i32, ptr [[TMP60]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP109:%.*]] = load i32, ptr [[TMP61]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP110:%.*]] = load i32, ptr [[TMP62]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP111:%.*]] = load i32, ptr [[TMP63]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP112:%.*]] = insertelement <8 x i32> poison, i32 [[TMP104]], i32 0 +; CHECK-NEXT: [[TMP113:%.*]] = insertelement <8 x i32> [[TMP112]], i32 [[TMP105]], i32 1 +; CHECK-NEXT: [[TMP114:%.*]] = insertelement <8 x i32> [[TMP113]], i32 [[TMP106]], i32 2 +; CHECK-NEXT: [[TMP115:%.*]] = insertelement <8 x i32> [[TMP114]], i32 [[TMP107]], i32 3 +; CHECK-NEXT: [[TMP116:%.*]] = insertelement <8 x i32> [[TMP115]], i32 [[TMP108]], i32 4 +; CHECK-NEXT: [[TMP117:%.*]] = insertelement <8 x i32> [[TMP116]], i32 [[TMP109]], i32 5 +; CHECK-NEXT: [[TMP118:%.*]] = insertelement <8 x i32> [[TMP117]], i32 [[TMP110]], i32 6 +; CHECK-NEXT: [[TMP119:%.*]] = insertelement <8 x i32> [[TMP118]], i32 [[TMP111]], i32 7 +; CHECK-NEXT: [[TMP120:%.*]] = load i32, ptr [[TMP64]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP121:%.*]] = load i32, ptr [[TMP65]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP122:%.*]] = load i32, ptr [[TMP66]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP123:%.*]] = load i32, ptr [[TMP67]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP124:%.*]] = load i32, ptr [[TMP68]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP125:%.*]] = load i32, ptr [[TMP69]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP126:%.*]] = load i32, ptr [[TMP70]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP127:%.*]] = load i32, ptr [[TMP71]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP128:%.*]] = insertelement <8 x i32> poison, i32 [[TMP120]], i32 0 +; CHECK-NEXT: [[TMP129:%.*]] = insertelement <8 x i32> [[TMP128]], i32 [[TMP121]], i32 1 +; CHECK-NEXT: [[TMP130:%.*]] = insertelement <8 x i32> [[TMP129]], i32 [[TMP122]], i32 2 +; CHECK-NEXT: [[TMP131:%.*]] = insertelement <8 x i32> [[TMP130]], i32 [[TMP123]], i32 3 +; CHECK-NEXT: [[TMP132:%.*]] = insertelement <8 x i32> [[TMP131]], i32 [[TMP124]], i32 4 +; CHECK-NEXT: [[TMP133:%.*]] = insertelement <8 x i32> [[TMP132]], i32 [[TMP125]], i32 5 +; CHECK-NEXT: [[TMP134:%.*]] = insertelement <8 x i32> [[TMP133]], i32 [[TMP126]], i32 6 +; CHECK-NEXT: [[TMP135:%.*]] = insertelement <8 x i32> [[TMP134]], i32 [[TMP127]], i32 7 +; CHECK-NEXT: [[TMP136:%.*]] = mul nsw <8 x i32> [[TMP87]], [[WIDE_LOAD]] +; CHECK-NEXT: [[TMP137:%.*]] = mul nsw <8 x i32> [[TMP103]], [[WIDE_LOAD4]] +; CHECK-NEXT: [[TMP138:%.*]] = mul nsw <8 x i32> [[TMP119]], [[WIDE_LOAD5]] +; CHECK-NEXT: [[TMP139:%.*]] = mul nsw <8 x i32> [[TMP135]], [[WIDE_LOAD6]] +; CHECK-NEXT: [[TMP140:%.*]] = add <8 x i32> [[VEC_PHI]], +; CHECK-NEXT: [[TMP141:%.*]] = add <8 x i32> [[VEC_PHI1]], +; CHECK-NEXT: [[TMP142:%.*]] = add <8 x i32> [[VEC_PHI2]], +; CHECK-NEXT: [[TMP143:%.*]] = add <8 x i32> [[VEC_PHI3]], +; CHECK-NEXT: [[TMP144]] = add <8 x i32> [[TMP140]], [[TMP136]] +; CHECK-NEXT: [[TMP145]] = add <8 x i32> [[TMP141]], [[TMP137]] +; CHECK-NEXT: [[TMP146]] = add <8 x i32> [[TMP142]], [[TMP138]] +; CHECK-NEXT: [[TMP147]] = add <8 x i32> [[TMP143]], [[TMP139]] +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 32 +; CHECK-NEXT: [[TMP148:%.*]] = icmp eq i64 [[INDEX_NEXT]], 96 +; CHECK-NEXT: br i1 [[TMP148]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]] ; CHECK: middle.block: -; CHECK-NEXT: [[TMP38:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[TMP36]]) +; CHECK-NEXT: [[BIN_RDX:%.*]] = add <8 x i32> [[TMP145]], [[TMP144]] +; CHECK-NEXT: [[BIN_RDX7:%.*]] = add <8 x i32> [[TMP146]], [[BIN_RDX]] +; CHECK-NEXT: [[BIN_RDX8:%.*]] = add <8 x i32> [[TMP147]], [[BIN_RDX7]] +; CHECK-NEXT: [[TMP149:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[BIN_RDX8]]) ; CHECK-NEXT: br i1 false, label [[FOR_COND_CLEANUP:%.*]], label [[SCALAR_PH]] ; CHECK: scalar.ph: ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 96, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] -; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[TMP38]], [[MIDDLE_BLOCK]] ] +; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[TMP149]], [[MIDDLE_BLOCK]] ] ; CHECK-NEXT: br label [[FOR_BODY:%.*]] ; CHECK: for.cond.cleanup: -; CHECK-NEXT: [[ADD7_LCSSA:%.*]] = phi i32 [ [[ADD7:%.*]], [[FOR_BODY]] ], [ [[TMP38]], [[MIDDLE_BLOCK]] ] +; CHECK-NEXT: [[ADD7_LCSSA:%.*]] = phi i32 [ [[ADD7:%.*]], [[FOR_BODY]] ], [ [[TMP149]], [[MIDDLE_BLOCK]] ] ; CHECK-NEXT: ret i32 [[ADD7_LCSSA]] ; CHECK: for.body: ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ] ; CHECK-NEXT: [[SUM_015:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[ADD7]], [[FOR_BODY]] ] ; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[IDXPROM]], i64 [[INDVARS_IV]] -; CHECK-NEXT: [[TMP39:%.*]] = load i32, ptr [[ARRAYIDX2]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[TMP150:%.*]] = load i32, ptr [[ARRAYIDX2]], align 4, !tbaa [[TBAA1]] ; CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [100 x i32], ptr [[DATA]], i64 [[INDVARS_IV]], i64 [[IDXPROM5]] -; CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr [[ARRAYIDX6]], align 4, !tbaa [[TBAA1]] -; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP40]], [[TMP39]] +; CHECK-NEXT: [[TMP151:%.*]] = load i32, ptr [[ARRAYIDX6]], align 4, !tbaa [[TBAA1]] +; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP151]], [[TMP150]] ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SUM_015]], 4 ; CHECK-NEXT: [[ADD7]] = add i32 [[ADD]], [[MUL]] ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 100 -; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] +; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] ; entry: %idxprom = sext i32 %i to i64 diff --git a/llvm/test/Transforms/LoopVectorize/X86/unroll-small-loops.ll b/llvm/test/Transforms/LoopVectorize/X86/unroll-small-loops.ll index 5b79d6af9ed9..76230994ed87 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/unroll-small-loops.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/unroll-small-loops.ll @@ -41,14 +41,20 @@ for.end: ; preds = %for.body ret void } -; TODO: We should unroll this loop 4 times since TC being a multiple of VF means +; We should unroll this loop 4 times since TC being a multiple of VF means ; that the epilogue loop may not need to run, making it profitable for ; the vector loop to run even once ; ; CHECK-VECTOR-LABEL: @foo_trip_count_16( ; CHECK-VECTOR: load <4 x i32> +; CHECK-VECTOR: load <4 x i32> +; CHECK-VECTOR: load <4 x i32> +; CHECK-VECTOR: load <4 x i32> ; CHECK-VECTOR-NOT: load <4 x i32> ; CHECK-VECTOR: store <4 x i32> +; CHECK-VECTOR: store <4 x i32> +; CHECK-VECTOR: store <4 x i32> +; CHECK-VECTOR: store <4 x i32> ; CHECK-VECTOR-NOT: store <4 x i32> ; CHECK-VECTOR: ret ; @@ -77,14 +83,20 @@ for.end: ; preds = %for.body ret void } -; TODO: We should unroll this loop twice since TC not being a multiple of VF may require -; the epilogue loop to run, making it profitable when the vector loop runs -; at least twice. +; We should unroll this loop four times since unrolling it twice +; will produce the same epilogue TC of 1, making larger unroll count +; more profitable ; ; CHECK-VECTOR-LABEL: @foo_trip_count_17( ; CHECK-VECTOR: load <4 x i32> +; CHECK-VECTOR: load <4 x i32> +; CHECK-VECTOR: load <4 x i32> +; CHECK-VECTOR: load <4 x i32> ; CHECK-VECTOR-NOT: load <4 x i32> ; CHECK-VECTOR: store <4 x i32> +; CHECK-VECTOR: store <4 x i32> +; CHECK-VECTOR: store <4 x i32> +; CHECK-VECTOR: store <4 x i32> ; CHECK-VECTOR-NOT: store <4 x i32> ; CHECK-VECTOR: ret ; @@ -113,15 +125,16 @@ for.end: ; preds = %for.body ret void } -; TODO: We should unroll this loop 4 times since TC being a multiple of VF means -; that the epilogue loop may not need to run, making it profitable for -; the vector loop to run even once. The IC is restricted to 4 since -; that is the maximum supported for the target. +; We should unroll this loop twice since unrolling four times will +; create an epilogue loop of TC 8, while unrolling it twice will +; eliminate the epologue loop altogether ; ; CHECK-VECTOR-LABEL: @foo_trip_count_24( ; CHECK-VECTOR: load <4 x i32> +; CHECK-VECTOR: load <4 x i32> ; CHECK-VECTOR-NOT: load <4 x i32> ; CHECK-VECTOR: store <4 x i32> +; CHECK-VECTOR: store <4 x i32> ; CHECK-VECTOR-NOT: store <4 x i32> ; CHECK-VECTOR: ret ; @@ -150,14 +163,16 @@ for.end: ; preds = %for.body ret void } -; TODO: We should unroll this loop twice since TC not being a multiple of VF may require +; We should unroll this loop twice since TC not being a multiple of VF may require ; the epilogue loop to run, making it profitable when the vector loop runs ; at least twice. ; ; CHECK-VECTOR-LABEL: @foo_trip_count_25( ; CHECK-VECTOR: load <4 x i32> +; CHECK-VECTOR: load <4 x i32> ; CHECK-VECTOR-NOT: load <4 x i32> ; CHECK-VECTOR: store <4 x i32> +; CHECK-VECTOR: store <4 x i32> ; CHECK-VECTOR-NOT: store <4 x i32> ; CHECK-VECTOR: ret ; @@ -186,14 +201,20 @@ for.end: ; preds = %for.body ret void } -; TODO: We should unroll this loop 4 times since TC not being a multiple of VF may require +; We should unroll this loop 4 times since TC not being a multiple of VF may require ; the epilogue loop to run, making it profitable when the vector loop runs ; at least twice. ; ; CHECK-VECTOR-LABEL: @foo_trip_count_33( ; CHECK-VECTOR: load <4 x i32> +; CHECK-VECTOR: load <4 x i32> +; CHECK-VECTOR: load <4 x i32> +; CHECK-VECTOR: load <4 x i32> ; CHECK-VECTOR-NOT: load <4 x i32> ; CHECK-VECTOR: store <4 x i32> +; CHECK-VECTOR: store <4 x i32> +; CHECK-VECTOR: store <4 x i32> +; CHECK-VECTOR: store <4 x i32> ; CHECK-VECTOR-NOT: store <4 x i32> ; CHECK-VECTOR: ret ; @@ -222,15 +243,21 @@ for.end: ; preds = %for.body ret void } -; TODO: We should unroll this loop 4 times since TC not being a multiple of VF may require +; We should unroll this loop 4 times since TC not being a multiple of VF may require ; the epilogue loop to run, making it profitable when the vector loop runs ; at least twice. The IC is restricted to 4 since that is the maximum supported ; for the target. ; ; CHECK-VECTOR-LABEL: @foo_trip_count_101( ; CHECK-VECTOR: load <4 x i32> +; CHECK-VECTOR: load <4 x i32> +; CHECK-VECTOR: load <4 x i32> +; CHECK-VECTOR: load <4 x i32> ; CHECK-VECTOR-NOT: load <4 x i32> ; CHECK-VECTOR: store <4 x i32> +; CHECK-VECTOR: store <4 x i32> +; CHECK-VECTOR: store <4 x i32> +; CHECK-VECTOR: store <4 x i32> ; CHECK-VECTOR-NOT: store <4 x i32> ; CHECK-VECTOR: ret ; diff --git a/llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll b/llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll index 3c2ea22e799d..daa35d31f2e0 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll @@ -27,29 +27,56 @@ define void @vectorized(ptr noalias nocapture %A, ptr noalias nocapture readonly ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 -; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds float, ptr [[B:%.*]], i64 [[TMP0]] -; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i32 0 -; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP0:![0-9]+]] -; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds float, ptr [[A:%.*]], i64 [[TMP0]] -; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds float, ptr [[TMP3]], i32 0 -; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x float>, ptr [[TMP4]], align 4, !llvm.access.group [[ACC_GRP0]] -; CHECK-NEXT: [[TMP5:%.*]] = fadd fast <4 x float> [[WIDE_LOAD]], [[WIDE_LOAD1]] -; CHECK-NEXT: store <4 x float> [[TMP5]], ptr [[TMP4]], align 4, !llvm.access.group [[ACC_GRP0]] -; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 -; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 20 -; CHECK-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP1:![0-9]+]] +; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 4 +; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 8 +; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 12 +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds float, ptr [[B:%.*]], i64 [[TMP0]] +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP2]] +; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP3]] +; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i32 0 +; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i32 4 +; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i32 8 +; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i32 12 +; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP0:![0-9]+]] +; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x float>, ptr [[TMP9]], align 4, !llvm.access.group [[ACC_GRP0]] +; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <4 x float>, ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP0]] +; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x float>, ptr [[TMP11]], align 4, !llvm.access.group [[ACC_GRP0]] +; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds float, ptr [[A:%.*]], i64 [[TMP0]] +; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP2]] +; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP3]] +; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i32 0 +; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i32 4 +; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i32 8 +; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i32 12 +; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x float>, ptr [[TMP16]], align 4, !llvm.access.group [[ACC_GRP0]] +; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x float>, ptr [[TMP17]], align 4, !llvm.access.group [[ACC_GRP0]] +; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x float>, ptr [[TMP18]], align 4, !llvm.access.group [[ACC_GRP0]] +; CHECK-NEXT: [[WIDE_LOAD7:%.*]] = load <4 x float>, ptr [[TMP19]], align 4, !llvm.access.group [[ACC_GRP0]] +; CHECK-NEXT: [[TMP20:%.*]] = fadd fast <4 x float> [[WIDE_LOAD]], [[WIDE_LOAD4]] +; CHECK-NEXT: [[TMP21:%.*]] = fadd fast <4 x float> [[WIDE_LOAD1]], [[WIDE_LOAD5]] +; CHECK-NEXT: [[TMP22:%.*]] = fadd fast <4 x float> [[WIDE_LOAD2]], [[WIDE_LOAD6]] +; CHECK-NEXT: [[TMP23:%.*]] = fadd fast <4 x float> [[WIDE_LOAD3]], [[WIDE_LOAD7]] +; CHECK-NEXT: store <4 x float> [[TMP20]], ptr [[TMP16]], align 4, !llvm.access.group [[ACC_GRP0]] +; CHECK-NEXT: store <4 x float> [[TMP21]], ptr [[TMP17]], align 4, !llvm.access.group [[ACC_GRP0]] +; CHECK-NEXT: store <4 x float> [[TMP22]], ptr [[TMP18]], align 4, !llvm.access.group [[ACC_GRP0]] +; CHECK-NEXT: store <4 x float> [[TMP23]], ptr [[TMP19]], align 4, !llvm.access.group [[ACC_GRP0]] +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 +; CHECK-NEXT: [[TMP24:%.*]] = icmp eq i64 [[INDEX_NEXT]], 16 +; CHECK-NEXT: br i1 [[TMP24]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP1:![0-9]+]] ; CHECK: middle.block: -; CHECK-NEXT: br i1 true, label [[FOR_END:%.*]], label [[SCALAR_PH]] +; CHECK-NEXT: br i1 false, label [[FOR_END:%.*]], label [[SCALAR_PH]] ; CHECK: scalar.ph: -; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 20, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 16, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] ; CHECK-NEXT: br label [[FOR_BODY:%.*]] ; CHECK: for.body: ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ] ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[INDVARS_IV]] -; CHECK-NEXT: [[TMP7:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP0]] +; CHECK-NEXT: [[TMP25:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP0]] ; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[INDVARS_IV]] -; CHECK-NEXT: [[TMP8:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP0]] -; CHECK-NEXT: [[ADD:%.*]] = fadd fast float [[TMP7]], [[TMP8]] +; CHECK-NEXT: [[TMP26:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP0]] +; CHECK-NEXT: [[ADD:%.*]] = fadd fast float [[TMP25]], [[TMP26]] ; CHECK-NEXT: store float [[ADD]], ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP0]] ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 20 diff --git a/llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks-loopid-dbg.ll b/llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks-loopid-dbg.ll index 4dfbdf1adee2..d774f778b7fd 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks-loopid-dbg.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks-loopid-dbg.ll @@ -6,7 +6,7 @@ ; DEBUG-OUTPUT-NOT: .loc ; DEBUG-OUTPUT-NOT: {{.*}}.debug_info -; VECTORIZED: remark: vectorization-remarks.c:17:8: vectorized loop (vectorization width: 4, interleaved count: 1) +; VECTORIZED: remark: vectorization-remarks.c:17:8: vectorized loop (vectorization width: 4, interleaved count: 2) ; UNROLLED: remark: vectorization-remarks.c:17:8: interleaved loop (interleaved count: 4) ; NONE: remark: vectorization-remarks.c:17:8: loop not vectorized: vectorization and interleaving are explicitly disabled, or the loop has already been vectorized diff --git a/llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks.ll b/llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks.ll index 63ed666eb624..f0b960c64056 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks.ll @@ -6,7 +6,7 @@ ; DEBUG-OUTPUT-NOT: .loc ; DEBUG-OUTPUT-NOT: {{.*}}.debug_info -; VECTORIZED: remark: vectorization-remarks.c:17:8: vectorized loop (vectorization width: 4, interleaved count: 1) +; VECTORIZED: remark: vectorization-remarks.c:17:8: vectorized loop (vectorization width: 4, interleaved count: 2) ; UNROLLED: remark: vectorization-remarks.c:17:8: interleaved loop (interleaved count: 4) ; NONE: remark: vectorization-remarks.c:17:8: loop not vectorized: vectorization and interleaving are explicitly disabled, or the loop has already been vectorized diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/quant_4x4.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/quant_4x4.ll index 7b9f3a2e13a6..d18b207e8707 100644 --- a/llvm/test/Transforms/PhaseOrdering/AArch64/quant_4x4.ll +++ b/llvm/test/Transforms/PhaseOrdering/AArch64/quant_4x4.ll @@ -22,62 +22,62 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT27]] ; CHECK-NEXT: br i1 [[CONFLICT_RDX]], label [[FOR_BODY:%.*]], label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: -; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i16>, ptr [[DCT]], align 2, !alias.scope !0, !noalias !3 -; CHECK-NEXT: [[TMP0:%.*]] = sext <8 x i16> [[WIDE_LOAD]] to <8 x i32> -; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <8 x i16> [[WIDE_LOAD]], zeroinitializer -; CHECK-NEXT: [[WIDE_LOAD28:%.*]] = load <8 x i16>, ptr [[BIAS]], align 2, !alias.scope !6 -; CHECK-NEXT: [[TMP2:%.*]] = zext <8 x i16> [[WIDE_LOAD28]] to <8 x i32> -; CHECK-NEXT: [[WIDE_LOAD29:%.*]] = load <8 x i16>, ptr [[MF]], align 2, !alias.scope !7 -; CHECK-NEXT: [[TMP3:%.*]] = zext <8 x i16> [[WIDE_LOAD29]] to <8 x i32> -; CHECK-NEXT: [[TMP4:%.*]] = sub nsw <8 x i32> [[TMP2]], [[TMP0]] -; CHECK-NEXT: [[TMP5:%.*]] = mul <8 x i32> [[TMP4]], [[TMP3]] -; CHECK-NEXT: [[TMP6:%.*]] = lshr <8 x i32> [[TMP5]], -; CHECK-NEXT: [[TMP7:%.*]] = trunc <8 x i32> [[TMP6]] to <8 x i16> -; CHECK-NEXT: [[TMP8:%.*]] = sub <8 x i16> zeroinitializer, [[TMP7]] -; CHECK-NEXT: [[TMP9:%.*]] = add nuw nsw <8 x i32> [[TMP2]], [[TMP0]] -; CHECK-NEXT: [[TMP10:%.*]] = mul <8 x i32> [[TMP9]], [[TMP3]] -; CHECK-NEXT: [[TMP11:%.*]] = lshr <8 x i32> [[TMP10]], -; CHECK-NEXT: [[TMP12:%.*]] = trunc <8 x i32> [[TMP11]] to <8 x i16> -; CHECK-NEXT: [[PREDPHI:%.*]] = select <8 x i1> [[TMP1]], <8 x i16> [[TMP12]], <8 x i16> [[TMP8]] -; CHECK-NEXT: store <8 x i16> [[PREDPHI]], ptr [[DCT]], align 2, !alias.scope !0, !noalias !3 -; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i8, ptr [[DCT]], i64 16 -; CHECK-NEXT: [[WIDE_LOAD_1:%.*]] = load <8 x i16>, ptr [[TMP13]], align 2, !alias.scope !0, !noalias !3 -; CHECK-NEXT: [[TMP14:%.*]] = sext <8 x i16> [[WIDE_LOAD_1]] to <8 x i32> -; CHECK-NEXT: [[TMP15:%.*]] = icmp sgt <8 x i16> [[WIDE_LOAD_1]], zeroinitializer -; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i8, ptr [[BIAS]], i64 16 -; CHECK-NEXT: [[WIDE_LOAD28_1:%.*]] = load <8 x i16>, ptr [[TMP16]], align 2, !alias.scope !6 -; CHECK-NEXT: [[TMP17:%.*]] = zext <8 x i16> [[WIDE_LOAD28_1]] to <8 x i32> -; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i8, ptr [[MF]], i64 16 -; CHECK-NEXT: [[WIDE_LOAD29_1:%.*]] = load <8 x i16>, ptr [[TMP18]], align 2, !alias.scope !7 -; CHECK-NEXT: [[TMP19:%.*]] = zext <8 x i16> [[WIDE_LOAD29_1]] to <8 x i32> -; CHECK-NEXT: [[TMP20:%.*]] = sub nsw <8 x i32> [[TMP17]], [[TMP14]] -; CHECK-NEXT: [[TMP21:%.*]] = mul <8 x i32> [[TMP20]], [[TMP19]] -; CHECK-NEXT: [[TMP22:%.*]] = lshr <8 x i32> [[TMP21]], -; CHECK-NEXT: [[TMP23:%.*]] = trunc <8 x i32> [[TMP22]] to <8 x i16> -; CHECK-NEXT: [[TMP24:%.*]] = sub <8 x i16> zeroinitializer, [[TMP23]] -; CHECK-NEXT: [[TMP25:%.*]] = add nuw nsw <8 x i32> [[TMP17]], [[TMP14]] -; CHECK-NEXT: [[TMP26:%.*]] = mul <8 x i32> [[TMP25]], [[TMP19]] -; CHECK-NEXT: [[TMP27:%.*]] = lshr <8 x i32> [[TMP26]], -; CHECK-NEXT: [[TMP28:%.*]] = trunc <8 x i32> [[TMP27]] to <8 x i16> -; CHECK-NEXT: [[PREDPHI_1:%.*]] = select <8 x i1> [[TMP15]], <8 x i16> [[TMP28]], <8 x i16> [[TMP24]] -; CHECK-NEXT: store <8 x i16> [[PREDPHI_1]], ptr [[TMP13]], align 2, !alias.scope !0, !noalias !3 -; CHECK-NEXT: [[TMP29:%.*]] = or <8 x i16> [[PREDPHI]], [[PREDPHI_1]] -; CHECK-NEXT: [[TMP30:%.*]] = sext <8 x i16> [[TMP29]] to <8 x i32> -; CHECK-NEXT: [[TMP31:%.*]] = tail call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> [[TMP30]]) +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[DCT]], i64 16 +; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i16>, ptr [[DCT]], align 2, !alias.scope [[META0:![0-9]+]], !noalias [[META3:![0-9]+]] +; CHECK-NEXT: [[WIDE_LOAD29:%.*]] = load <8 x i16>, ptr [[TMP0]], align 2, !alias.scope [[META0]], !noalias [[META3]] +; CHECK-NEXT: [[TMP1:%.*]] = sext <8 x i16> [[WIDE_LOAD]] to <8 x i32> +; CHECK-NEXT: [[TMP2:%.*]] = sext <8 x i16> [[WIDE_LOAD29]] to <8 x i32> +; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt <8 x i16> [[WIDE_LOAD]], zeroinitializer +; CHECK-NEXT: [[TMP4:%.*]] = icmp sgt <8 x i16> [[WIDE_LOAD29]], zeroinitializer +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[BIAS]], i64 16 +; CHECK-NEXT: [[WIDE_LOAD30:%.*]] = load <8 x i16>, ptr [[BIAS]], align 2, !alias.scope [[META6:![0-9]+]] +; CHECK-NEXT: [[WIDE_LOAD31:%.*]] = load <8 x i16>, ptr [[TMP5]], align 2, !alias.scope [[META6]] +; CHECK-NEXT: [[TMP6:%.*]] = zext <8 x i16> [[WIDE_LOAD30]] to <8 x i32> +; CHECK-NEXT: [[TMP7:%.*]] = zext <8 x i16> [[WIDE_LOAD31]] to <8 x i32> +; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[MF]], i64 16 +; CHECK-NEXT: [[WIDE_LOAD32:%.*]] = load <8 x i16>, ptr [[MF]], align 2, !alias.scope [[META7:![0-9]+]] +; CHECK-NEXT: [[WIDE_LOAD33:%.*]] = load <8 x i16>, ptr [[TMP8]], align 2, !alias.scope [[META7]] +; CHECK-NEXT: [[TMP9:%.*]] = zext <8 x i16> [[WIDE_LOAD32]] to <8 x i32> +; CHECK-NEXT: [[TMP10:%.*]] = zext <8 x i16> [[WIDE_LOAD33]] to <8 x i32> +; CHECK-NEXT: [[TMP11:%.*]] = sub nsw <8 x i32> [[TMP6]], [[TMP1]] +; CHECK-NEXT: [[TMP12:%.*]] = sub nsw <8 x i32> [[TMP7]], [[TMP2]] +; CHECK-NEXT: [[TMP13:%.*]] = mul <8 x i32> [[TMP11]], [[TMP9]] +; CHECK-NEXT: [[TMP14:%.*]] = mul <8 x i32> [[TMP12]], [[TMP10]] +; CHECK-NEXT: [[TMP15:%.*]] = lshr <8 x i32> [[TMP13]], +; CHECK-NEXT: [[TMP16:%.*]] = lshr <8 x i32> [[TMP14]], +; CHECK-NEXT: [[TMP17:%.*]] = trunc <8 x i32> [[TMP15]] to <8 x i16> +; CHECK-NEXT: [[TMP18:%.*]] = trunc <8 x i32> [[TMP16]] to <8 x i16> +; CHECK-NEXT: [[TMP19:%.*]] = sub <8 x i16> zeroinitializer, [[TMP17]] +; CHECK-NEXT: [[TMP20:%.*]] = sub <8 x i16> zeroinitializer, [[TMP18]] +; CHECK-NEXT: [[TMP21:%.*]] = add nuw nsw <8 x i32> [[TMP6]], [[TMP1]] +; CHECK-NEXT: [[TMP22:%.*]] = add nuw nsw <8 x i32> [[TMP7]], [[TMP2]] +; CHECK-NEXT: [[TMP23:%.*]] = mul <8 x i32> [[TMP21]], [[TMP9]] +; CHECK-NEXT: [[TMP24:%.*]] = mul <8 x i32> [[TMP22]], [[TMP10]] +; CHECK-NEXT: [[TMP25:%.*]] = lshr <8 x i32> [[TMP23]], +; CHECK-NEXT: [[TMP26:%.*]] = lshr <8 x i32> [[TMP24]], +; CHECK-NEXT: [[TMP27:%.*]] = trunc <8 x i32> [[TMP25]] to <8 x i16> +; CHECK-NEXT: [[TMP28:%.*]] = trunc <8 x i32> [[TMP26]] to <8 x i16> +; CHECK-NEXT: [[PREDPHI:%.*]] = select <8 x i1> [[TMP3]], <8 x i16> [[TMP27]], <8 x i16> [[TMP19]] +; CHECK-NEXT: [[PREDPHI34:%.*]] = select <8 x i1> [[TMP4]], <8 x i16> [[TMP28]], <8 x i16> [[TMP20]] +; CHECK-NEXT: store <8 x i16> [[PREDPHI]], ptr [[DCT]], align 2, !alias.scope [[META0]], !noalias [[META3]] +; CHECK-NEXT: store <8 x i16> [[PREDPHI34]], ptr [[TMP0]], align 2, !alias.scope [[META0]], !noalias [[META3]] +; CHECK-NEXT: [[BIN_RDX35:%.*]] = or <8 x i16> [[PREDPHI34]], [[PREDPHI]] +; CHECK-NEXT: [[BIN_RDX:%.*]] = sext <8 x i16> [[BIN_RDX35]] to <8 x i32> +; CHECK-NEXT: [[TMP29:%.*]] = tail call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> [[BIN_RDX]]) ; CHECK-NEXT: br label [[FOR_COND_CLEANUP:%.*]] ; CHECK: for.cond.cleanup: -; CHECK-NEXT: [[OR_LCSSA:%.*]] = phi i32 [ [[TMP31]], [[VECTOR_BODY]] ], [ [[OR_15:%.*]], [[IF_END_15:%.*]] ] +; CHECK-NEXT: [[OR_LCSSA:%.*]] = phi i32 [ [[TMP29]], [[VECTOR_BODY]] ], [ [[OR_15:%.*]], [[IF_END_15:%.*]] ] ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[OR_LCSSA]], 0 ; CHECK-NEXT: [[LNOT_EXT:%.*]] = zext i1 [[TOBOOL]] to i32 ; CHECK-NEXT: ret i32 [[LNOT_EXT]] ; CHECK: for.body: -; CHECK-NEXT: [[TMP32:%.*]] = load i16, ptr [[DCT]], align 2 -; CHECK-NEXT: [[CONV:%.*]] = sext i16 [[TMP32]] to i32 -; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i16 [[TMP32]], 0 -; CHECK-NEXT: [[TMP33:%.*]] = load i16, ptr [[BIAS]], align 2 -; CHECK-NEXT: [[CONV5:%.*]] = zext i16 [[TMP33]] to i32 -; CHECK-NEXT: [[TMP34:%.*]] = load i16, ptr [[MF]], align 2 -; CHECK-NEXT: [[CONV11:%.*]] = zext i16 [[TMP34]] to i32 +; CHECK-NEXT: [[TMP30:%.*]] = load i16, ptr [[DCT]], align 2 +; CHECK-NEXT: [[CONV:%.*]] = sext i16 [[TMP30]] to i32 +; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i16 [[TMP30]], 0 +; CHECK-NEXT: [[TMP31:%.*]] = load i16, ptr [[BIAS]], align 2 +; CHECK-NEXT: [[CONV5:%.*]] = zext i16 [[TMP31]] to i32 +; CHECK-NEXT: [[TMP32:%.*]] = load i16, ptr [[MF]], align 2 +; CHECK-NEXT: [[CONV11:%.*]] = zext i16 [[TMP32]] to i32 ; CHECK-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] ; CHECK: if.then: ; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[CONV5]], [[CONV]] @@ -89,29 +89,29 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK-NEXT: [[ADD21:%.*]] = sub nsw i32 [[CONV5]], [[CONV]] ; CHECK-NEXT: [[MUL25:%.*]] = mul i32 [[ADD21]], [[CONV11]] ; CHECK-NEXT: [[SHR26:%.*]] = lshr i32 [[MUL25]], 16 -; CHECK-NEXT: [[TMP35:%.*]] = trunc i32 [[SHR26]] to i16 -; CHECK-NEXT: [[CONV28:%.*]] = sub i16 0, [[TMP35]] +; CHECK-NEXT: [[TMP33:%.*]] = trunc i32 [[SHR26]] to i16 +; CHECK-NEXT: [[CONV28:%.*]] = sub i16 0, [[TMP33]] ; CHECK-NEXT: br label [[IF_END]] ; CHECK: if.end: ; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i16 [ [[CONV28]], [[IF_ELSE]] ], [ [[CONV12]], [[IF_THEN]] ] ; CHECK-NEXT: store i16 [[STOREMERGE]], ptr [[DCT]], align 2 ; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i8, ptr [[DCT]], i64 2 -; CHECK-NEXT: [[TMP36:%.*]] = load i16, ptr [[ARRAYIDX_1]], align 2 -; CHECK-NEXT: [[CONV_1:%.*]] = sext i16 [[TMP36]] to i32 -; CHECK-NEXT: [[CMP1_1:%.*]] = icmp sgt i16 [[TMP36]], 0 +; CHECK-NEXT: [[TMP34:%.*]] = load i16, ptr [[ARRAYIDX_1]], align 2 +; CHECK-NEXT: [[CONV_1:%.*]] = sext i16 [[TMP34]] to i32 +; CHECK-NEXT: [[CMP1_1:%.*]] = icmp sgt i16 [[TMP34]], 0 ; CHECK-NEXT: [[ARRAYIDX4_1:%.*]] = getelementptr inbounds i8, ptr [[BIAS]], i64 2 -; CHECK-NEXT: [[TMP37:%.*]] = load i16, ptr [[ARRAYIDX4_1]], align 2 -; CHECK-NEXT: [[CONV5_1:%.*]] = zext i16 [[TMP37]] to i32 +; CHECK-NEXT: [[TMP35:%.*]] = load i16, ptr [[ARRAYIDX4_1]], align 2 +; CHECK-NEXT: [[CONV5_1:%.*]] = zext i16 [[TMP35]] to i32 ; CHECK-NEXT: [[ARRAYIDX10_1:%.*]] = getelementptr inbounds i8, ptr [[MF]], i64 2 -; CHECK-NEXT: [[TMP38:%.*]] = load i16, ptr [[ARRAYIDX10_1]], align 2 -; CHECK-NEXT: [[CONV11_1:%.*]] = zext i16 [[TMP38]] to i32 +; CHECK-NEXT: [[TMP36:%.*]] = load i16, ptr [[ARRAYIDX10_1]], align 2 +; CHECK-NEXT: [[CONV11_1:%.*]] = zext i16 [[TMP36]] to i32 ; CHECK-NEXT: br i1 [[CMP1_1]], label [[IF_THEN_1:%.*]], label [[IF_ELSE_1:%.*]] ; CHECK: if.else.1: ; CHECK-NEXT: [[ADD21_1:%.*]] = sub nsw i32 [[CONV5_1]], [[CONV_1]] ; CHECK-NEXT: [[MUL25_1:%.*]] = mul i32 [[ADD21_1]], [[CONV11_1]] ; CHECK-NEXT: [[SHR26_1:%.*]] = lshr i32 [[MUL25_1]], 16 -; CHECK-NEXT: [[TMP39:%.*]] = trunc i32 [[SHR26_1]] to i16 -; CHECK-NEXT: [[CONV28_1:%.*]] = sub i16 0, [[TMP39]] +; CHECK-NEXT: [[TMP37:%.*]] = trunc i32 [[SHR26_1]] to i16 +; CHECK-NEXT: [[CONV28_1:%.*]] = sub i16 0, [[TMP37]] ; CHECK-NEXT: br label [[IF_END_1:%.*]] ; CHECK: if.then.1: ; CHECK-NEXT: [[ADD_1:%.*]] = add nuw nsw i32 [[CONV5_1]], [[CONV_1]] @@ -122,24 +122,24 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK: if.end.1: ; CHECK-NEXT: [[STOREMERGE_1:%.*]] = phi i16 [ [[CONV28_1]], [[IF_ELSE_1]] ], [ [[CONV12_1]], [[IF_THEN_1]] ] ; CHECK-NEXT: store i16 [[STOREMERGE_1]], ptr [[ARRAYIDX_1]], align 2 -; CHECK-NEXT: [[OR_131:%.*]] = or i16 [[STOREMERGE]], [[STOREMERGE_1]] +; CHECK-NEXT: [[OR_137:%.*]] = or i16 [[STOREMERGE]], [[STOREMERGE_1]] ; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i8, ptr [[DCT]], i64 4 -; CHECK-NEXT: [[TMP40:%.*]] = load i16, ptr [[ARRAYIDX_2]], align 2 -; CHECK-NEXT: [[CONV_2:%.*]] = sext i16 [[TMP40]] to i32 -; CHECK-NEXT: [[CMP1_2:%.*]] = icmp sgt i16 [[TMP40]], 0 +; CHECK-NEXT: [[TMP38:%.*]] = load i16, ptr [[ARRAYIDX_2]], align 2 +; CHECK-NEXT: [[CONV_2:%.*]] = sext i16 [[TMP38]] to i32 +; CHECK-NEXT: [[CMP1_2:%.*]] = icmp sgt i16 [[TMP38]], 0 ; CHECK-NEXT: [[ARRAYIDX4_2:%.*]] = getelementptr inbounds i8, ptr [[BIAS]], i64 4 -; CHECK-NEXT: [[TMP41:%.*]] = load i16, ptr [[ARRAYIDX4_2]], align 2 -; CHECK-NEXT: [[CONV5_2:%.*]] = zext i16 [[TMP41]] to i32 +; CHECK-NEXT: [[TMP39:%.*]] = load i16, ptr [[ARRAYIDX4_2]], align 2 +; CHECK-NEXT: [[CONV5_2:%.*]] = zext i16 [[TMP39]] to i32 ; CHECK-NEXT: [[ARRAYIDX10_2:%.*]] = getelementptr inbounds i8, ptr [[MF]], i64 4 -; CHECK-NEXT: [[TMP42:%.*]] = load i16, ptr [[ARRAYIDX10_2]], align 2 -; CHECK-NEXT: [[CONV11_2:%.*]] = zext i16 [[TMP42]] to i32 +; CHECK-NEXT: [[TMP40:%.*]] = load i16, ptr [[ARRAYIDX10_2]], align 2 +; CHECK-NEXT: [[CONV11_2:%.*]] = zext i16 [[TMP40]] to i32 ; CHECK-NEXT: br i1 [[CMP1_2]], label [[IF_THEN_2:%.*]], label [[IF_ELSE_2:%.*]] ; CHECK: if.else.2: ; CHECK-NEXT: [[ADD21_2:%.*]] = sub nsw i32 [[CONV5_2]], [[CONV_2]] ; CHECK-NEXT: [[MUL25_2:%.*]] = mul i32 [[ADD21_2]], [[CONV11_2]] ; CHECK-NEXT: [[SHR26_2:%.*]] = lshr i32 [[MUL25_2]], 16 -; CHECK-NEXT: [[TMP43:%.*]] = trunc i32 [[SHR26_2]] to i16 -; CHECK-NEXT: [[CONV28_2:%.*]] = sub i16 0, [[TMP43]] +; CHECK-NEXT: [[TMP41:%.*]] = trunc i32 [[SHR26_2]] to i16 +; CHECK-NEXT: [[CONV28_2:%.*]] = sub i16 0, [[TMP41]] ; CHECK-NEXT: br label [[IF_END_2:%.*]] ; CHECK: if.then.2: ; CHECK-NEXT: [[ADD_2:%.*]] = add nuw nsw i32 [[CONV5_2]], [[CONV_2]] @@ -150,24 +150,24 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK: if.end.2: ; CHECK-NEXT: [[STOREMERGE_2:%.*]] = phi i16 [ [[CONV28_2]], [[IF_ELSE_2]] ], [ [[CONV12_2]], [[IF_THEN_2]] ] ; CHECK-NEXT: store i16 [[STOREMERGE_2]], ptr [[ARRAYIDX_2]], align 2 -; CHECK-NEXT: [[OR_232:%.*]] = or i16 [[OR_131]], [[STOREMERGE_2]] +; CHECK-NEXT: [[OR_238:%.*]] = or i16 [[OR_137]], [[STOREMERGE_2]] ; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i8, ptr [[DCT]], i64 6 -; CHECK-NEXT: [[TMP44:%.*]] = load i16, ptr [[ARRAYIDX_3]], align 2 -; CHECK-NEXT: [[CONV_3:%.*]] = sext i16 [[TMP44]] to i32 -; CHECK-NEXT: [[CMP1_3:%.*]] = icmp sgt i16 [[TMP44]], 0 +; CHECK-NEXT: [[TMP42:%.*]] = load i16, ptr [[ARRAYIDX_3]], align 2 +; CHECK-NEXT: [[CONV_3:%.*]] = sext i16 [[TMP42]] to i32 +; CHECK-NEXT: [[CMP1_3:%.*]] = icmp sgt i16 [[TMP42]], 0 ; CHECK-NEXT: [[ARRAYIDX4_3:%.*]] = getelementptr inbounds i8, ptr [[BIAS]], i64 6 -; CHECK-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX4_3]], align 2 -; CHECK-NEXT: [[CONV5_3:%.*]] = zext i16 [[TMP45]] to i32 +; CHECK-NEXT: [[TMP43:%.*]] = load i16, ptr [[ARRAYIDX4_3]], align 2 +; CHECK-NEXT: [[CONV5_3:%.*]] = zext i16 [[TMP43]] to i32 ; CHECK-NEXT: [[ARRAYIDX10_3:%.*]] = getelementptr inbounds i8, ptr [[MF]], i64 6 -; CHECK-NEXT: [[TMP46:%.*]] = load i16, ptr [[ARRAYIDX10_3]], align 2 -; CHECK-NEXT: [[CONV11_3:%.*]] = zext i16 [[TMP46]] to i32 +; CHECK-NEXT: [[TMP44:%.*]] = load i16, ptr [[ARRAYIDX10_3]], align 2 +; CHECK-NEXT: [[CONV11_3:%.*]] = zext i16 [[TMP44]] to i32 ; CHECK-NEXT: br i1 [[CMP1_3]], label [[IF_THEN_3:%.*]], label [[IF_ELSE_3:%.*]] ; CHECK: if.else.3: ; CHECK-NEXT: [[ADD21_3:%.*]] = sub nsw i32 [[CONV5_3]], [[CONV_3]] ; CHECK-NEXT: [[MUL25_3:%.*]] = mul i32 [[ADD21_3]], [[CONV11_3]] ; CHECK-NEXT: [[SHR26_3:%.*]] = lshr i32 [[MUL25_3]], 16 -; CHECK-NEXT: [[TMP47:%.*]] = trunc i32 [[SHR26_3]] to i16 -; CHECK-NEXT: [[CONV28_3:%.*]] = sub i16 0, [[TMP47]] +; CHECK-NEXT: [[TMP45:%.*]] = trunc i32 [[SHR26_3]] to i16 +; CHECK-NEXT: [[CONV28_3:%.*]] = sub i16 0, [[TMP45]] ; CHECK-NEXT: br label [[IF_END_3:%.*]] ; CHECK: if.then.3: ; CHECK-NEXT: [[ADD_3:%.*]] = add nuw nsw i32 [[CONV5_3]], [[CONV_3]] @@ -178,24 +178,24 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK: if.end.3: ; CHECK-NEXT: [[STOREMERGE_3:%.*]] = phi i16 [ [[CONV28_3]], [[IF_ELSE_3]] ], [ [[CONV12_3]], [[IF_THEN_3]] ] ; CHECK-NEXT: store i16 [[STOREMERGE_3]], ptr [[ARRAYIDX_3]], align 2 -; CHECK-NEXT: [[OR_333:%.*]] = or i16 [[OR_232]], [[STOREMERGE_3]] +; CHECK-NEXT: [[OR_339:%.*]] = or i16 [[OR_238]], [[STOREMERGE_3]] ; CHECK-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i8, ptr [[DCT]], i64 8 -; CHECK-NEXT: [[TMP48:%.*]] = load i16, ptr [[ARRAYIDX_4]], align 2 -; CHECK-NEXT: [[CONV_4:%.*]] = sext i16 [[TMP48]] to i32 -; CHECK-NEXT: [[CMP1_4:%.*]] = icmp sgt i16 [[TMP48]], 0 +; CHECK-NEXT: [[TMP46:%.*]] = load i16, ptr [[ARRAYIDX_4]], align 2 +; CHECK-NEXT: [[CONV_4:%.*]] = sext i16 [[TMP46]] to i32 +; CHECK-NEXT: [[CMP1_4:%.*]] = icmp sgt i16 [[TMP46]], 0 ; CHECK-NEXT: [[ARRAYIDX4_4:%.*]] = getelementptr inbounds i8, ptr [[BIAS]], i64 8 -; CHECK-NEXT: [[TMP49:%.*]] = load i16, ptr [[ARRAYIDX4_4]], align 2 -; CHECK-NEXT: [[CONV5_4:%.*]] = zext i16 [[TMP49]] to i32 +; CHECK-NEXT: [[TMP47:%.*]] = load i16, ptr [[ARRAYIDX4_4]], align 2 +; CHECK-NEXT: [[CONV5_4:%.*]] = zext i16 [[TMP47]] to i32 ; CHECK-NEXT: [[ARRAYIDX10_4:%.*]] = getelementptr inbounds i8, ptr [[MF]], i64 8 -; CHECK-NEXT: [[TMP50:%.*]] = load i16, ptr [[ARRAYIDX10_4]], align 2 -; CHECK-NEXT: [[CONV11_4:%.*]] = zext i16 [[TMP50]] to i32 +; CHECK-NEXT: [[TMP48:%.*]] = load i16, ptr [[ARRAYIDX10_4]], align 2 +; CHECK-NEXT: [[CONV11_4:%.*]] = zext i16 [[TMP48]] to i32 ; CHECK-NEXT: br i1 [[CMP1_4]], label [[IF_THEN_4:%.*]], label [[IF_ELSE_4:%.*]] ; CHECK: if.else.4: ; CHECK-NEXT: [[ADD21_4:%.*]] = sub nsw i32 [[CONV5_4]], [[CONV_4]] ; CHECK-NEXT: [[MUL25_4:%.*]] = mul i32 [[ADD21_4]], [[CONV11_4]] ; CHECK-NEXT: [[SHR26_4:%.*]] = lshr i32 [[MUL25_4]], 16 -; CHECK-NEXT: [[TMP51:%.*]] = trunc i32 [[SHR26_4]] to i16 -; CHECK-NEXT: [[CONV28_4:%.*]] = sub i16 0, [[TMP51]] +; CHECK-NEXT: [[TMP49:%.*]] = trunc i32 [[SHR26_4]] to i16 +; CHECK-NEXT: [[CONV28_4:%.*]] = sub i16 0, [[TMP49]] ; CHECK-NEXT: br label [[IF_END_4:%.*]] ; CHECK: if.then.4: ; CHECK-NEXT: [[ADD_4:%.*]] = add nuw nsw i32 [[CONV5_4]], [[CONV_4]] @@ -206,24 +206,24 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK: if.end.4: ; CHECK-NEXT: [[STOREMERGE_4:%.*]] = phi i16 [ [[CONV28_4]], [[IF_ELSE_4]] ], [ [[CONV12_4]], [[IF_THEN_4]] ] ; CHECK-NEXT: store i16 [[STOREMERGE_4]], ptr [[ARRAYIDX_4]], align 2 -; CHECK-NEXT: [[OR_434:%.*]] = or i16 [[OR_333]], [[STOREMERGE_4]] +; CHECK-NEXT: [[OR_440:%.*]] = or i16 [[OR_339]], [[STOREMERGE_4]] ; CHECK-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i8, ptr [[DCT]], i64 10 -; CHECK-NEXT: [[TMP52:%.*]] = load i16, ptr [[ARRAYIDX_5]], align 2 -; CHECK-NEXT: [[CONV_5:%.*]] = sext i16 [[TMP52]] to i32 -; CHECK-NEXT: [[CMP1_5:%.*]] = icmp sgt i16 [[TMP52]], 0 +; CHECK-NEXT: [[TMP50:%.*]] = load i16, ptr [[ARRAYIDX_5]], align 2 +; CHECK-NEXT: [[CONV_5:%.*]] = sext i16 [[TMP50]] to i32 +; CHECK-NEXT: [[CMP1_5:%.*]] = icmp sgt i16 [[TMP50]], 0 ; CHECK-NEXT: [[ARRAYIDX4_5:%.*]] = getelementptr inbounds i8, ptr [[BIAS]], i64 10 -; CHECK-NEXT: [[TMP53:%.*]] = load i16, ptr [[ARRAYIDX4_5]], align 2 -; CHECK-NEXT: [[CONV5_5:%.*]] = zext i16 [[TMP53]] to i32 +; CHECK-NEXT: [[TMP51:%.*]] = load i16, ptr [[ARRAYIDX4_5]], align 2 +; CHECK-NEXT: [[CONV5_5:%.*]] = zext i16 [[TMP51]] to i32 ; CHECK-NEXT: [[ARRAYIDX10_5:%.*]] = getelementptr inbounds i8, ptr [[MF]], i64 10 -; CHECK-NEXT: [[TMP54:%.*]] = load i16, ptr [[ARRAYIDX10_5]], align 2 -; CHECK-NEXT: [[CONV11_5:%.*]] = zext i16 [[TMP54]] to i32 +; CHECK-NEXT: [[TMP52:%.*]] = load i16, ptr [[ARRAYIDX10_5]], align 2 +; CHECK-NEXT: [[CONV11_5:%.*]] = zext i16 [[TMP52]] to i32 ; CHECK-NEXT: br i1 [[CMP1_5]], label [[IF_THEN_5:%.*]], label [[IF_ELSE_5:%.*]] ; CHECK: if.else.5: ; CHECK-NEXT: [[ADD21_5:%.*]] = sub nsw i32 [[CONV5_5]], [[CONV_5]] ; CHECK-NEXT: [[MUL25_5:%.*]] = mul i32 [[ADD21_5]], [[CONV11_5]] ; CHECK-NEXT: [[SHR26_5:%.*]] = lshr i32 [[MUL25_5]], 16 -; CHECK-NEXT: [[TMP55:%.*]] = trunc i32 [[SHR26_5]] to i16 -; CHECK-NEXT: [[CONV28_5:%.*]] = sub i16 0, [[TMP55]] +; CHECK-NEXT: [[TMP53:%.*]] = trunc i32 [[SHR26_5]] to i16 +; CHECK-NEXT: [[CONV28_5:%.*]] = sub i16 0, [[TMP53]] ; CHECK-NEXT: br label [[IF_END_5:%.*]] ; CHECK: if.then.5: ; CHECK-NEXT: [[ADD_5:%.*]] = add nuw nsw i32 [[CONV5_5]], [[CONV_5]] @@ -234,24 +234,24 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK: if.end.5: ; CHECK-NEXT: [[STOREMERGE_5:%.*]] = phi i16 [ [[CONV28_5]], [[IF_ELSE_5]] ], [ [[CONV12_5]], [[IF_THEN_5]] ] ; CHECK-NEXT: store i16 [[STOREMERGE_5]], ptr [[ARRAYIDX_5]], align 2 -; CHECK-NEXT: [[OR_535:%.*]] = or i16 [[OR_434]], [[STOREMERGE_5]] +; CHECK-NEXT: [[OR_541:%.*]] = or i16 [[OR_440]], [[STOREMERGE_5]] ; CHECK-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i8, ptr [[DCT]], i64 12 -; CHECK-NEXT: [[TMP56:%.*]] = load i16, ptr [[ARRAYIDX_6]], align 2 -; CHECK-NEXT: [[CONV_6:%.*]] = sext i16 [[TMP56]] to i32 -; CHECK-NEXT: [[CMP1_6:%.*]] = icmp sgt i16 [[TMP56]], 0 +; CHECK-NEXT: [[TMP54:%.*]] = load i16, ptr [[ARRAYIDX_6]], align 2 +; CHECK-NEXT: [[CONV_6:%.*]] = sext i16 [[TMP54]] to i32 +; CHECK-NEXT: [[CMP1_6:%.*]] = icmp sgt i16 [[TMP54]], 0 ; CHECK-NEXT: [[ARRAYIDX4_6:%.*]] = getelementptr inbounds i8, ptr [[BIAS]], i64 12 -; CHECK-NEXT: [[TMP57:%.*]] = load i16, ptr [[ARRAYIDX4_6]], align 2 -; CHECK-NEXT: [[CONV5_6:%.*]] = zext i16 [[TMP57]] to i32 +; CHECK-NEXT: [[TMP55:%.*]] = load i16, ptr [[ARRAYIDX4_6]], align 2 +; CHECK-NEXT: [[CONV5_6:%.*]] = zext i16 [[TMP55]] to i32 ; CHECK-NEXT: [[ARRAYIDX10_6:%.*]] = getelementptr inbounds i8, ptr [[MF]], i64 12 -; CHECK-NEXT: [[TMP58:%.*]] = load i16, ptr [[ARRAYIDX10_6]], align 2 -; CHECK-NEXT: [[CONV11_6:%.*]] = zext i16 [[TMP58]] to i32 +; CHECK-NEXT: [[TMP56:%.*]] = load i16, ptr [[ARRAYIDX10_6]], align 2 +; CHECK-NEXT: [[CONV11_6:%.*]] = zext i16 [[TMP56]] to i32 ; CHECK-NEXT: br i1 [[CMP1_6]], label [[IF_THEN_6:%.*]], label [[IF_ELSE_6:%.*]] ; CHECK: if.else.6: ; CHECK-NEXT: [[ADD21_6:%.*]] = sub nsw i32 [[CONV5_6]], [[CONV_6]] ; CHECK-NEXT: [[MUL25_6:%.*]] = mul i32 [[ADD21_6]], [[CONV11_6]] ; CHECK-NEXT: [[SHR26_6:%.*]] = lshr i32 [[MUL25_6]], 16 -; CHECK-NEXT: [[TMP59:%.*]] = trunc i32 [[SHR26_6]] to i16 -; CHECK-NEXT: [[CONV28_6:%.*]] = sub i16 0, [[TMP59]] +; CHECK-NEXT: [[TMP57:%.*]] = trunc i32 [[SHR26_6]] to i16 +; CHECK-NEXT: [[CONV28_6:%.*]] = sub i16 0, [[TMP57]] ; CHECK-NEXT: br label [[IF_END_6:%.*]] ; CHECK: if.then.6: ; CHECK-NEXT: [[ADD_6:%.*]] = add nuw nsw i32 [[CONV5_6]], [[CONV_6]] @@ -262,24 +262,24 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK: if.end.6: ; CHECK-NEXT: [[STOREMERGE_6:%.*]] = phi i16 [ [[CONV28_6]], [[IF_ELSE_6]] ], [ [[CONV12_6]], [[IF_THEN_6]] ] ; CHECK-NEXT: store i16 [[STOREMERGE_6]], ptr [[ARRAYIDX_6]], align 2 -; CHECK-NEXT: [[OR_636:%.*]] = or i16 [[OR_535]], [[STOREMERGE_6]] +; CHECK-NEXT: [[OR_642:%.*]] = or i16 [[OR_541]], [[STOREMERGE_6]] ; CHECK-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i8, ptr [[DCT]], i64 14 -; CHECK-NEXT: [[TMP60:%.*]] = load i16, ptr [[ARRAYIDX_7]], align 2 -; CHECK-NEXT: [[CONV_7:%.*]] = sext i16 [[TMP60]] to i32 -; CHECK-NEXT: [[CMP1_7:%.*]] = icmp sgt i16 [[TMP60]], 0 +; CHECK-NEXT: [[TMP58:%.*]] = load i16, ptr [[ARRAYIDX_7]], align 2 +; CHECK-NEXT: [[CONV_7:%.*]] = sext i16 [[TMP58]] to i32 +; CHECK-NEXT: [[CMP1_7:%.*]] = icmp sgt i16 [[TMP58]], 0 ; CHECK-NEXT: [[ARRAYIDX4_7:%.*]] = getelementptr inbounds i8, ptr [[BIAS]], i64 14 -; CHECK-NEXT: [[TMP61:%.*]] = load i16, ptr [[ARRAYIDX4_7]], align 2 -; CHECK-NEXT: [[CONV5_7:%.*]] = zext i16 [[TMP61]] to i32 +; CHECK-NEXT: [[TMP59:%.*]] = load i16, ptr [[ARRAYIDX4_7]], align 2 +; CHECK-NEXT: [[CONV5_7:%.*]] = zext i16 [[TMP59]] to i32 ; CHECK-NEXT: [[ARRAYIDX10_7:%.*]] = getelementptr inbounds i8, ptr [[MF]], i64 14 -; CHECK-NEXT: [[TMP62:%.*]] = load i16, ptr [[ARRAYIDX10_7]], align 2 -; CHECK-NEXT: [[CONV11_7:%.*]] = zext i16 [[TMP62]] to i32 +; CHECK-NEXT: [[TMP60:%.*]] = load i16, ptr [[ARRAYIDX10_7]], align 2 +; CHECK-NEXT: [[CONV11_7:%.*]] = zext i16 [[TMP60]] to i32 ; CHECK-NEXT: br i1 [[CMP1_7]], label [[IF_THEN_7:%.*]], label [[IF_ELSE_7:%.*]] ; CHECK: if.else.7: ; CHECK-NEXT: [[ADD21_7:%.*]] = sub nsw i32 [[CONV5_7]], [[CONV_7]] ; CHECK-NEXT: [[MUL25_7:%.*]] = mul i32 [[ADD21_7]], [[CONV11_7]] ; CHECK-NEXT: [[SHR26_7:%.*]] = lshr i32 [[MUL25_7]], 16 -; CHECK-NEXT: [[TMP63:%.*]] = trunc i32 [[SHR26_7]] to i16 -; CHECK-NEXT: [[CONV28_7:%.*]] = sub i16 0, [[TMP63]] +; CHECK-NEXT: [[TMP61:%.*]] = trunc i32 [[SHR26_7]] to i16 +; CHECK-NEXT: [[CONV28_7:%.*]] = sub i16 0, [[TMP61]] ; CHECK-NEXT: br label [[IF_END_7:%.*]] ; CHECK: if.then.7: ; CHECK-NEXT: [[ADD_7:%.*]] = add nuw nsw i32 [[CONV5_7]], [[CONV_7]] @@ -290,24 +290,24 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK: if.end.7: ; CHECK-NEXT: [[STOREMERGE_7:%.*]] = phi i16 [ [[CONV28_7]], [[IF_ELSE_7]] ], [ [[CONV12_7]], [[IF_THEN_7]] ] ; CHECK-NEXT: store i16 [[STOREMERGE_7]], ptr [[ARRAYIDX_7]], align 2 -; CHECK-NEXT: [[OR_737:%.*]] = or i16 [[OR_636]], [[STOREMERGE_7]] +; CHECK-NEXT: [[OR_743:%.*]] = or i16 [[OR_642]], [[STOREMERGE_7]] ; CHECK-NEXT: [[ARRAYIDX_8:%.*]] = getelementptr inbounds i8, ptr [[DCT]], i64 16 -; CHECK-NEXT: [[TMP64:%.*]] = load i16, ptr [[ARRAYIDX_8]], align 2 -; CHECK-NEXT: [[CONV_8:%.*]] = sext i16 [[TMP64]] to i32 -; CHECK-NEXT: [[CMP1_8:%.*]] = icmp sgt i16 [[TMP64]], 0 +; CHECK-NEXT: [[TMP62:%.*]] = load i16, ptr [[ARRAYIDX_8]], align 2 +; CHECK-NEXT: [[CONV_8:%.*]] = sext i16 [[TMP62]] to i32 +; CHECK-NEXT: [[CMP1_8:%.*]] = icmp sgt i16 [[TMP62]], 0 ; CHECK-NEXT: [[ARRAYIDX4_8:%.*]] = getelementptr inbounds i8, ptr [[BIAS]], i64 16 -; CHECK-NEXT: [[TMP65:%.*]] = load i16, ptr [[ARRAYIDX4_8]], align 2 -; CHECK-NEXT: [[CONV5_8:%.*]] = zext i16 [[TMP65]] to i32 +; CHECK-NEXT: [[TMP63:%.*]] = load i16, ptr [[ARRAYIDX4_8]], align 2 +; CHECK-NEXT: [[CONV5_8:%.*]] = zext i16 [[TMP63]] to i32 ; CHECK-NEXT: [[ARRAYIDX10_8:%.*]] = getelementptr inbounds i8, ptr [[MF]], i64 16 -; CHECK-NEXT: [[TMP66:%.*]] = load i16, ptr [[ARRAYIDX10_8]], align 2 -; CHECK-NEXT: [[CONV11_8:%.*]] = zext i16 [[TMP66]] to i32 +; CHECK-NEXT: [[TMP64:%.*]] = load i16, ptr [[ARRAYIDX10_8]], align 2 +; CHECK-NEXT: [[CONV11_8:%.*]] = zext i16 [[TMP64]] to i32 ; CHECK-NEXT: br i1 [[CMP1_8]], label [[IF_THEN_8:%.*]], label [[IF_ELSE_8:%.*]] ; CHECK: if.else.8: ; CHECK-NEXT: [[ADD21_8:%.*]] = sub nsw i32 [[CONV5_8]], [[CONV_8]] ; CHECK-NEXT: [[MUL25_8:%.*]] = mul i32 [[ADD21_8]], [[CONV11_8]] ; CHECK-NEXT: [[SHR26_8:%.*]] = lshr i32 [[MUL25_8]], 16 -; CHECK-NEXT: [[TMP67:%.*]] = trunc i32 [[SHR26_8]] to i16 -; CHECK-NEXT: [[CONV28_8:%.*]] = sub i16 0, [[TMP67]] +; CHECK-NEXT: [[TMP65:%.*]] = trunc i32 [[SHR26_8]] to i16 +; CHECK-NEXT: [[CONV28_8:%.*]] = sub i16 0, [[TMP65]] ; CHECK-NEXT: br label [[IF_END_8:%.*]] ; CHECK: if.then.8: ; CHECK-NEXT: [[ADD_8:%.*]] = add nuw nsw i32 [[CONV5_8]], [[CONV_8]] @@ -318,24 +318,24 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK: if.end.8: ; CHECK-NEXT: [[STOREMERGE_8:%.*]] = phi i16 [ [[CONV28_8]], [[IF_ELSE_8]] ], [ [[CONV12_8]], [[IF_THEN_8]] ] ; CHECK-NEXT: store i16 [[STOREMERGE_8]], ptr [[ARRAYIDX_8]], align 2 -; CHECK-NEXT: [[OR_838:%.*]] = or i16 [[OR_737]], [[STOREMERGE_8]] +; CHECK-NEXT: [[OR_844:%.*]] = or i16 [[OR_743]], [[STOREMERGE_8]] ; CHECK-NEXT: [[ARRAYIDX_9:%.*]] = getelementptr inbounds i8, ptr [[DCT]], i64 18 -; CHECK-NEXT: [[TMP68:%.*]] = load i16, ptr [[ARRAYIDX_9]], align 2 -; CHECK-NEXT: [[CONV_9:%.*]] = sext i16 [[TMP68]] to i32 -; CHECK-NEXT: [[CMP1_9:%.*]] = icmp sgt i16 [[TMP68]], 0 +; CHECK-NEXT: [[TMP66:%.*]] = load i16, ptr [[ARRAYIDX_9]], align 2 +; CHECK-NEXT: [[CONV_9:%.*]] = sext i16 [[TMP66]] to i32 +; CHECK-NEXT: [[CMP1_9:%.*]] = icmp sgt i16 [[TMP66]], 0 ; CHECK-NEXT: [[ARRAYIDX4_9:%.*]] = getelementptr inbounds i8, ptr [[BIAS]], i64 18 -; CHECK-NEXT: [[TMP69:%.*]] = load i16, ptr [[ARRAYIDX4_9]], align 2 -; CHECK-NEXT: [[CONV5_9:%.*]] = zext i16 [[TMP69]] to i32 +; CHECK-NEXT: [[TMP67:%.*]] = load i16, ptr [[ARRAYIDX4_9]], align 2 +; CHECK-NEXT: [[CONV5_9:%.*]] = zext i16 [[TMP67]] to i32 ; CHECK-NEXT: [[ARRAYIDX10_9:%.*]] = getelementptr inbounds i8, ptr [[MF]], i64 18 -; CHECK-NEXT: [[TMP70:%.*]] = load i16, ptr [[ARRAYIDX10_9]], align 2 -; CHECK-NEXT: [[CONV11_9:%.*]] = zext i16 [[TMP70]] to i32 +; CHECK-NEXT: [[TMP68:%.*]] = load i16, ptr [[ARRAYIDX10_9]], align 2 +; CHECK-NEXT: [[CONV11_9:%.*]] = zext i16 [[TMP68]] to i32 ; CHECK-NEXT: br i1 [[CMP1_9]], label [[IF_THEN_9:%.*]], label [[IF_ELSE_9:%.*]] ; CHECK: if.else.9: ; CHECK-NEXT: [[ADD21_9:%.*]] = sub nsw i32 [[CONV5_9]], [[CONV_9]] ; CHECK-NEXT: [[MUL25_9:%.*]] = mul i32 [[ADD21_9]], [[CONV11_9]] ; CHECK-NEXT: [[SHR26_9:%.*]] = lshr i32 [[MUL25_9]], 16 -; CHECK-NEXT: [[TMP71:%.*]] = trunc i32 [[SHR26_9]] to i16 -; CHECK-NEXT: [[CONV28_9:%.*]] = sub i16 0, [[TMP71]] +; CHECK-NEXT: [[TMP69:%.*]] = trunc i32 [[SHR26_9]] to i16 +; CHECK-NEXT: [[CONV28_9:%.*]] = sub i16 0, [[TMP69]] ; CHECK-NEXT: br label [[IF_END_9:%.*]] ; CHECK: if.then.9: ; CHECK-NEXT: [[ADD_9:%.*]] = add nuw nsw i32 [[CONV5_9]], [[CONV_9]] @@ -346,24 +346,24 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK: if.end.9: ; CHECK-NEXT: [[STOREMERGE_9:%.*]] = phi i16 [ [[CONV28_9]], [[IF_ELSE_9]] ], [ [[CONV12_9]], [[IF_THEN_9]] ] ; CHECK-NEXT: store i16 [[STOREMERGE_9]], ptr [[ARRAYIDX_9]], align 2 -; CHECK-NEXT: [[OR_939:%.*]] = or i16 [[OR_838]], [[STOREMERGE_9]] +; CHECK-NEXT: [[OR_945:%.*]] = or i16 [[OR_844]], [[STOREMERGE_9]] ; CHECK-NEXT: [[ARRAYIDX_10:%.*]] = getelementptr inbounds i8, ptr [[DCT]], i64 20 -; CHECK-NEXT: [[TMP72:%.*]] = load i16, ptr [[ARRAYIDX_10]], align 2 -; CHECK-NEXT: [[CONV_10:%.*]] = sext i16 [[TMP72]] to i32 -; CHECK-NEXT: [[CMP1_10:%.*]] = icmp sgt i16 [[TMP72]], 0 +; CHECK-NEXT: [[TMP70:%.*]] = load i16, ptr [[ARRAYIDX_10]], align 2 +; CHECK-NEXT: [[CONV_10:%.*]] = sext i16 [[TMP70]] to i32 +; CHECK-NEXT: [[CMP1_10:%.*]] = icmp sgt i16 [[TMP70]], 0 ; CHECK-NEXT: [[ARRAYIDX4_10:%.*]] = getelementptr inbounds i8, ptr [[BIAS]], i64 20 -; CHECK-NEXT: [[TMP73:%.*]] = load i16, ptr [[ARRAYIDX4_10]], align 2 -; CHECK-NEXT: [[CONV5_10:%.*]] = zext i16 [[TMP73]] to i32 +; CHECK-NEXT: [[TMP71:%.*]] = load i16, ptr [[ARRAYIDX4_10]], align 2 +; CHECK-NEXT: [[CONV5_10:%.*]] = zext i16 [[TMP71]] to i32 ; CHECK-NEXT: [[ARRAYIDX10_10:%.*]] = getelementptr inbounds i8, ptr [[MF]], i64 20 -; CHECK-NEXT: [[TMP74:%.*]] = load i16, ptr [[ARRAYIDX10_10]], align 2 -; CHECK-NEXT: [[CONV11_10:%.*]] = zext i16 [[TMP74]] to i32 +; CHECK-NEXT: [[TMP72:%.*]] = load i16, ptr [[ARRAYIDX10_10]], align 2 +; CHECK-NEXT: [[CONV11_10:%.*]] = zext i16 [[TMP72]] to i32 ; CHECK-NEXT: br i1 [[CMP1_10]], label [[IF_THEN_10:%.*]], label [[IF_ELSE_10:%.*]] ; CHECK: if.else.10: ; CHECK-NEXT: [[ADD21_10:%.*]] = sub nsw i32 [[CONV5_10]], [[CONV_10]] ; CHECK-NEXT: [[MUL25_10:%.*]] = mul i32 [[ADD21_10]], [[CONV11_10]] ; CHECK-NEXT: [[SHR26_10:%.*]] = lshr i32 [[MUL25_10]], 16 -; CHECK-NEXT: [[TMP75:%.*]] = trunc i32 [[SHR26_10]] to i16 -; CHECK-NEXT: [[CONV28_10:%.*]] = sub i16 0, [[TMP75]] +; CHECK-NEXT: [[TMP73:%.*]] = trunc i32 [[SHR26_10]] to i16 +; CHECK-NEXT: [[CONV28_10:%.*]] = sub i16 0, [[TMP73]] ; CHECK-NEXT: br label [[IF_END_10:%.*]] ; CHECK: if.then.10: ; CHECK-NEXT: [[ADD_10:%.*]] = add nuw nsw i32 [[CONV5_10]], [[CONV_10]] @@ -374,24 +374,24 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK: if.end.10: ; CHECK-NEXT: [[STOREMERGE_10:%.*]] = phi i16 [ [[CONV28_10]], [[IF_ELSE_10]] ], [ [[CONV12_10]], [[IF_THEN_10]] ] ; CHECK-NEXT: store i16 [[STOREMERGE_10]], ptr [[ARRAYIDX_10]], align 2 -; CHECK-NEXT: [[OR_1040:%.*]] = or i16 [[OR_939]], [[STOREMERGE_10]] +; CHECK-NEXT: [[OR_1046:%.*]] = or i16 [[OR_945]], [[STOREMERGE_10]] ; CHECK-NEXT: [[ARRAYIDX_11:%.*]] = getelementptr inbounds i8, ptr [[DCT]], i64 22 -; CHECK-NEXT: [[TMP76:%.*]] = load i16, ptr [[ARRAYIDX_11]], align 2 -; CHECK-NEXT: [[CONV_11:%.*]] = sext i16 [[TMP76]] to i32 -; CHECK-NEXT: [[CMP1_11:%.*]] = icmp sgt i16 [[TMP76]], 0 +; CHECK-NEXT: [[TMP74:%.*]] = load i16, ptr [[ARRAYIDX_11]], align 2 +; CHECK-NEXT: [[CONV_11:%.*]] = sext i16 [[TMP74]] to i32 +; CHECK-NEXT: [[CMP1_11:%.*]] = icmp sgt i16 [[TMP74]], 0 ; CHECK-NEXT: [[ARRAYIDX4_11:%.*]] = getelementptr inbounds i8, ptr [[BIAS]], i64 22 -; CHECK-NEXT: [[TMP77:%.*]] = load i16, ptr [[ARRAYIDX4_11]], align 2 -; CHECK-NEXT: [[CONV5_11:%.*]] = zext i16 [[TMP77]] to i32 +; CHECK-NEXT: [[TMP75:%.*]] = load i16, ptr [[ARRAYIDX4_11]], align 2 +; CHECK-NEXT: [[CONV5_11:%.*]] = zext i16 [[TMP75]] to i32 ; CHECK-NEXT: [[ARRAYIDX10_11:%.*]] = getelementptr inbounds i8, ptr [[MF]], i64 22 -; CHECK-NEXT: [[TMP78:%.*]] = load i16, ptr [[ARRAYIDX10_11]], align 2 -; CHECK-NEXT: [[CONV11_11:%.*]] = zext i16 [[TMP78]] to i32 +; CHECK-NEXT: [[TMP76:%.*]] = load i16, ptr [[ARRAYIDX10_11]], align 2 +; CHECK-NEXT: [[CONV11_11:%.*]] = zext i16 [[TMP76]] to i32 ; CHECK-NEXT: br i1 [[CMP1_11]], label [[IF_THEN_11:%.*]], label [[IF_ELSE_11:%.*]] ; CHECK: if.else.11: ; CHECK-NEXT: [[ADD21_11:%.*]] = sub nsw i32 [[CONV5_11]], [[CONV_11]] ; CHECK-NEXT: [[MUL25_11:%.*]] = mul i32 [[ADD21_11]], [[CONV11_11]] ; CHECK-NEXT: [[SHR26_11:%.*]] = lshr i32 [[MUL25_11]], 16 -; CHECK-NEXT: [[TMP79:%.*]] = trunc i32 [[SHR26_11]] to i16 -; CHECK-NEXT: [[CONV28_11:%.*]] = sub i16 0, [[TMP79]] +; CHECK-NEXT: [[TMP77:%.*]] = trunc i32 [[SHR26_11]] to i16 +; CHECK-NEXT: [[CONV28_11:%.*]] = sub i16 0, [[TMP77]] ; CHECK-NEXT: br label [[IF_END_11:%.*]] ; CHECK: if.then.11: ; CHECK-NEXT: [[ADD_11:%.*]] = add nuw nsw i32 [[CONV5_11]], [[CONV_11]] @@ -402,24 +402,24 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK: if.end.11: ; CHECK-NEXT: [[STOREMERGE_11:%.*]] = phi i16 [ [[CONV28_11]], [[IF_ELSE_11]] ], [ [[CONV12_11]], [[IF_THEN_11]] ] ; CHECK-NEXT: store i16 [[STOREMERGE_11]], ptr [[ARRAYIDX_11]], align 2 -; CHECK-NEXT: [[OR_1141:%.*]] = or i16 [[OR_1040]], [[STOREMERGE_11]] +; CHECK-NEXT: [[OR_1147:%.*]] = or i16 [[OR_1046]], [[STOREMERGE_11]] ; CHECK-NEXT: [[ARRAYIDX_12:%.*]] = getelementptr inbounds i8, ptr [[DCT]], i64 24 -; CHECK-NEXT: [[TMP80:%.*]] = load i16, ptr [[ARRAYIDX_12]], align 2 -; CHECK-NEXT: [[CONV_12:%.*]] = sext i16 [[TMP80]] to i32 -; CHECK-NEXT: [[CMP1_12:%.*]] = icmp sgt i16 [[TMP80]], 0 +; CHECK-NEXT: [[TMP78:%.*]] = load i16, ptr [[ARRAYIDX_12]], align 2 +; CHECK-NEXT: [[CONV_12:%.*]] = sext i16 [[TMP78]] to i32 +; CHECK-NEXT: [[CMP1_12:%.*]] = icmp sgt i16 [[TMP78]], 0 ; CHECK-NEXT: [[ARRAYIDX4_12:%.*]] = getelementptr inbounds i8, ptr [[BIAS]], i64 24 -; CHECK-NEXT: [[TMP81:%.*]] = load i16, ptr [[ARRAYIDX4_12]], align 2 -; CHECK-NEXT: [[CONV5_12:%.*]] = zext i16 [[TMP81]] to i32 +; CHECK-NEXT: [[TMP79:%.*]] = load i16, ptr [[ARRAYIDX4_12]], align 2 +; CHECK-NEXT: [[CONV5_12:%.*]] = zext i16 [[TMP79]] to i32 ; CHECK-NEXT: [[ARRAYIDX10_12:%.*]] = getelementptr inbounds i8, ptr [[MF]], i64 24 -; CHECK-NEXT: [[TMP82:%.*]] = load i16, ptr [[ARRAYIDX10_12]], align 2 -; CHECK-NEXT: [[CONV11_12:%.*]] = zext i16 [[TMP82]] to i32 +; CHECK-NEXT: [[TMP80:%.*]] = load i16, ptr [[ARRAYIDX10_12]], align 2 +; CHECK-NEXT: [[CONV11_12:%.*]] = zext i16 [[TMP80]] to i32 ; CHECK-NEXT: br i1 [[CMP1_12]], label [[IF_THEN_12:%.*]], label [[IF_ELSE_12:%.*]] ; CHECK: if.else.12: ; CHECK-NEXT: [[ADD21_12:%.*]] = sub nsw i32 [[CONV5_12]], [[CONV_12]] ; CHECK-NEXT: [[MUL25_12:%.*]] = mul i32 [[ADD21_12]], [[CONV11_12]] ; CHECK-NEXT: [[SHR26_12:%.*]] = lshr i32 [[MUL25_12]], 16 -; CHECK-NEXT: [[TMP83:%.*]] = trunc i32 [[SHR26_12]] to i16 -; CHECK-NEXT: [[CONV28_12:%.*]] = sub i16 0, [[TMP83]] +; CHECK-NEXT: [[TMP81:%.*]] = trunc i32 [[SHR26_12]] to i16 +; CHECK-NEXT: [[CONV28_12:%.*]] = sub i16 0, [[TMP81]] ; CHECK-NEXT: br label [[IF_END_12:%.*]] ; CHECK: if.then.12: ; CHECK-NEXT: [[ADD_12:%.*]] = add nuw nsw i32 [[CONV5_12]], [[CONV_12]] @@ -430,24 +430,24 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK: if.end.12: ; CHECK-NEXT: [[STOREMERGE_12:%.*]] = phi i16 [ [[CONV28_12]], [[IF_ELSE_12]] ], [ [[CONV12_12]], [[IF_THEN_12]] ] ; CHECK-NEXT: store i16 [[STOREMERGE_12]], ptr [[ARRAYIDX_12]], align 2 -; CHECK-NEXT: [[OR_1242:%.*]] = or i16 [[OR_1141]], [[STOREMERGE_12]] +; CHECK-NEXT: [[OR_1248:%.*]] = or i16 [[OR_1147]], [[STOREMERGE_12]] ; CHECK-NEXT: [[ARRAYIDX_13:%.*]] = getelementptr inbounds i8, ptr [[DCT]], i64 26 -; CHECK-NEXT: [[TMP84:%.*]] = load i16, ptr [[ARRAYIDX_13]], align 2 -; CHECK-NEXT: [[CONV_13:%.*]] = sext i16 [[TMP84]] to i32 -; CHECK-NEXT: [[CMP1_13:%.*]] = icmp sgt i16 [[TMP84]], 0 +; CHECK-NEXT: [[TMP82:%.*]] = load i16, ptr [[ARRAYIDX_13]], align 2 +; CHECK-NEXT: [[CONV_13:%.*]] = sext i16 [[TMP82]] to i32 +; CHECK-NEXT: [[CMP1_13:%.*]] = icmp sgt i16 [[TMP82]], 0 ; CHECK-NEXT: [[ARRAYIDX4_13:%.*]] = getelementptr inbounds i8, ptr [[BIAS]], i64 26 -; CHECK-NEXT: [[TMP85:%.*]] = load i16, ptr [[ARRAYIDX4_13]], align 2 -; CHECK-NEXT: [[CONV5_13:%.*]] = zext i16 [[TMP85]] to i32 +; CHECK-NEXT: [[TMP83:%.*]] = load i16, ptr [[ARRAYIDX4_13]], align 2 +; CHECK-NEXT: [[CONV5_13:%.*]] = zext i16 [[TMP83]] to i32 ; CHECK-NEXT: [[ARRAYIDX10_13:%.*]] = getelementptr inbounds i8, ptr [[MF]], i64 26 -; CHECK-NEXT: [[TMP86:%.*]] = load i16, ptr [[ARRAYIDX10_13]], align 2 -; CHECK-NEXT: [[CONV11_13:%.*]] = zext i16 [[TMP86]] to i32 +; CHECK-NEXT: [[TMP84:%.*]] = load i16, ptr [[ARRAYIDX10_13]], align 2 +; CHECK-NEXT: [[CONV11_13:%.*]] = zext i16 [[TMP84]] to i32 ; CHECK-NEXT: br i1 [[CMP1_13]], label [[IF_THEN_13:%.*]], label [[IF_ELSE_13:%.*]] ; CHECK: if.else.13: ; CHECK-NEXT: [[ADD21_13:%.*]] = sub nsw i32 [[CONV5_13]], [[CONV_13]] ; CHECK-NEXT: [[MUL25_13:%.*]] = mul i32 [[ADD21_13]], [[CONV11_13]] ; CHECK-NEXT: [[SHR26_13:%.*]] = lshr i32 [[MUL25_13]], 16 -; CHECK-NEXT: [[TMP87:%.*]] = trunc i32 [[SHR26_13]] to i16 -; CHECK-NEXT: [[CONV28_13:%.*]] = sub i16 0, [[TMP87]] +; CHECK-NEXT: [[TMP85:%.*]] = trunc i32 [[SHR26_13]] to i16 +; CHECK-NEXT: [[CONV28_13:%.*]] = sub i16 0, [[TMP85]] ; CHECK-NEXT: br label [[IF_END_13:%.*]] ; CHECK: if.then.13: ; CHECK-NEXT: [[ADD_13:%.*]] = add nuw nsw i32 [[CONV5_13]], [[CONV_13]] @@ -458,24 +458,24 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK: if.end.13: ; CHECK-NEXT: [[STOREMERGE_13:%.*]] = phi i16 [ [[CONV28_13]], [[IF_ELSE_13]] ], [ [[CONV12_13]], [[IF_THEN_13]] ] ; CHECK-NEXT: store i16 [[STOREMERGE_13]], ptr [[ARRAYIDX_13]], align 2 -; CHECK-NEXT: [[OR_1343:%.*]] = or i16 [[OR_1242]], [[STOREMERGE_13]] +; CHECK-NEXT: [[OR_1349:%.*]] = or i16 [[OR_1248]], [[STOREMERGE_13]] ; CHECK-NEXT: [[ARRAYIDX_14:%.*]] = getelementptr inbounds i8, ptr [[DCT]], i64 28 -; CHECK-NEXT: [[TMP88:%.*]] = load i16, ptr [[ARRAYIDX_14]], align 2 -; CHECK-NEXT: [[CONV_14:%.*]] = sext i16 [[TMP88]] to i32 -; CHECK-NEXT: [[CMP1_14:%.*]] = icmp sgt i16 [[TMP88]], 0 +; CHECK-NEXT: [[TMP86:%.*]] = load i16, ptr [[ARRAYIDX_14]], align 2 +; CHECK-NEXT: [[CONV_14:%.*]] = sext i16 [[TMP86]] to i32 +; CHECK-NEXT: [[CMP1_14:%.*]] = icmp sgt i16 [[TMP86]], 0 ; CHECK-NEXT: [[ARRAYIDX4_14:%.*]] = getelementptr inbounds i8, ptr [[BIAS]], i64 28 -; CHECK-NEXT: [[TMP89:%.*]] = load i16, ptr [[ARRAYIDX4_14]], align 2 -; CHECK-NEXT: [[CONV5_14:%.*]] = zext i16 [[TMP89]] to i32 +; CHECK-NEXT: [[TMP87:%.*]] = load i16, ptr [[ARRAYIDX4_14]], align 2 +; CHECK-NEXT: [[CONV5_14:%.*]] = zext i16 [[TMP87]] to i32 ; CHECK-NEXT: [[ARRAYIDX10_14:%.*]] = getelementptr inbounds i8, ptr [[MF]], i64 28 -; CHECK-NEXT: [[TMP90:%.*]] = load i16, ptr [[ARRAYIDX10_14]], align 2 -; CHECK-NEXT: [[CONV11_14:%.*]] = zext i16 [[TMP90]] to i32 +; CHECK-NEXT: [[TMP88:%.*]] = load i16, ptr [[ARRAYIDX10_14]], align 2 +; CHECK-NEXT: [[CONV11_14:%.*]] = zext i16 [[TMP88]] to i32 ; CHECK-NEXT: br i1 [[CMP1_14]], label [[IF_THEN_14:%.*]], label [[IF_ELSE_14:%.*]] ; CHECK: if.else.14: ; CHECK-NEXT: [[ADD21_14:%.*]] = sub nsw i32 [[CONV5_14]], [[CONV_14]] ; CHECK-NEXT: [[MUL25_14:%.*]] = mul i32 [[ADD21_14]], [[CONV11_14]] ; CHECK-NEXT: [[SHR26_14:%.*]] = lshr i32 [[MUL25_14]], 16 -; CHECK-NEXT: [[TMP91:%.*]] = trunc i32 [[SHR26_14]] to i16 -; CHECK-NEXT: [[CONV28_14:%.*]] = sub i16 0, [[TMP91]] +; CHECK-NEXT: [[TMP89:%.*]] = trunc i32 [[SHR26_14]] to i16 +; CHECK-NEXT: [[CONV28_14:%.*]] = sub i16 0, [[TMP89]] ; CHECK-NEXT: br label [[IF_END_14:%.*]] ; CHECK: if.then.14: ; CHECK-NEXT: [[ADD_14:%.*]] = add nuw nsw i32 [[CONV5_14]], [[CONV_14]] @@ -486,24 +486,24 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK: if.end.14: ; CHECK-NEXT: [[STOREMERGE_14:%.*]] = phi i16 [ [[CONV28_14]], [[IF_ELSE_14]] ], [ [[CONV12_14]], [[IF_THEN_14]] ] ; CHECK-NEXT: store i16 [[STOREMERGE_14]], ptr [[ARRAYIDX_14]], align 2 -; CHECK-NEXT: [[OR_1444:%.*]] = or i16 [[OR_1343]], [[STOREMERGE_14]] +; CHECK-NEXT: [[OR_1450:%.*]] = or i16 [[OR_1349]], [[STOREMERGE_14]] ; CHECK-NEXT: [[ARRAYIDX_15:%.*]] = getelementptr inbounds i8, ptr [[DCT]], i64 30 -; CHECK-NEXT: [[TMP92:%.*]] = load i16, ptr [[ARRAYIDX_15]], align 2 -; CHECK-NEXT: [[CONV_15:%.*]] = sext i16 [[TMP92]] to i32 -; CHECK-NEXT: [[CMP1_15:%.*]] = icmp sgt i16 [[TMP92]], 0 +; CHECK-NEXT: [[TMP90:%.*]] = load i16, ptr [[ARRAYIDX_15]], align 2 +; CHECK-NEXT: [[CONV_15:%.*]] = sext i16 [[TMP90]] to i32 +; CHECK-NEXT: [[CMP1_15:%.*]] = icmp sgt i16 [[TMP90]], 0 ; CHECK-NEXT: [[ARRAYIDX4_15:%.*]] = getelementptr inbounds i8, ptr [[BIAS]], i64 30 -; CHECK-NEXT: [[TMP93:%.*]] = load i16, ptr [[ARRAYIDX4_15]], align 2 -; CHECK-NEXT: [[CONV5_15:%.*]] = zext i16 [[TMP93]] to i32 +; CHECK-NEXT: [[TMP91:%.*]] = load i16, ptr [[ARRAYIDX4_15]], align 2 +; CHECK-NEXT: [[CONV5_15:%.*]] = zext i16 [[TMP91]] to i32 ; CHECK-NEXT: [[ARRAYIDX10_15:%.*]] = getelementptr inbounds i8, ptr [[MF]], i64 30 -; CHECK-NEXT: [[TMP94:%.*]] = load i16, ptr [[ARRAYIDX10_15]], align 2 -; CHECK-NEXT: [[CONV11_15:%.*]] = zext i16 [[TMP94]] to i32 +; CHECK-NEXT: [[TMP92:%.*]] = load i16, ptr [[ARRAYIDX10_15]], align 2 +; CHECK-NEXT: [[CONV11_15:%.*]] = zext i16 [[TMP92]] to i32 ; CHECK-NEXT: br i1 [[CMP1_15]], label [[IF_THEN_15:%.*]], label [[IF_ELSE_15:%.*]] ; CHECK: if.else.15: ; CHECK-NEXT: [[ADD21_15:%.*]] = sub nsw i32 [[CONV5_15]], [[CONV_15]] ; CHECK-NEXT: [[MUL25_15:%.*]] = mul i32 [[ADD21_15]], [[CONV11_15]] ; CHECK-NEXT: [[SHR26_15:%.*]] = lshr i32 [[MUL25_15]], 16 -; CHECK-NEXT: [[TMP95:%.*]] = trunc i32 [[SHR26_15]] to i16 -; CHECK-NEXT: [[CONV28_15:%.*]] = sub i16 0, [[TMP95]] +; CHECK-NEXT: [[TMP93:%.*]] = trunc i32 [[SHR26_15]] to i16 +; CHECK-NEXT: [[CONV28_15:%.*]] = sub i16 0, [[TMP93]] ; CHECK-NEXT: br label [[IF_END_15]] ; CHECK: if.then.15: ; CHECK-NEXT: [[ADD_15:%.*]] = add nuw nsw i32 [[CONV5_15]], [[CONV_15]] @@ -514,8 +514,8 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK: if.end.15: ; CHECK-NEXT: [[STOREMERGE_15:%.*]] = phi i16 [ [[CONV28_15]], [[IF_ELSE_15]] ], [ [[CONV12_15]], [[IF_THEN_15]] ] ; CHECK-NEXT: store i16 [[STOREMERGE_15]], ptr [[ARRAYIDX_15]], align 2 -; CHECK-NEXT: [[OR_1545:%.*]] = or i16 [[OR_1444]], [[STOREMERGE_15]] -; CHECK-NEXT: [[OR_15]] = sext i16 [[OR_1545]] to i32 +; CHECK-NEXT: [[OR_1551:%.*]] = or i16 [[OR_1450]], [[STOREMERGE_15]] +; CHECK-NEXT: [[OR_15]] = sext i16 [[OR_1551]] to i32 ; CHECK-NEXT: br label [[FOR_COND_CLEANUP]] ; entry: diff --git a/llvm/test/Transforms/PhaseOrdering/X86/excessive-unrolling.ll b/llvm/test/Transforms/PhaseOrdering/X86/excessive-unrolling.ll index fd6bb61d0369..741e3ad4f7b9 100644 --- a/llvm/test/Transforms/PhaseOrdering/X86/excessive-unrolling.ll +++ b/llvm/test/Transforms/PhaseOrdering/X86/excessive-unrolling.ll @@ -13,124 +13,124 @@ define void @test_known_trip_count() { ; CHECK-LABEL: @test_known_trip_count( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x double>, ptr @b, align 16 -; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <2 x double>, ptr @c, align 16 -; CHECK-NEXT: [[TMP0:%.*]] = fadd <2 x double> [[WIDE_LOAD]], [[WIDE_LOAD3]] +; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 2), align 16 +; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <2 x double>, ptr @c, align 16 +; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 2), align 16 +; CHECK-NEXT: [[TMP0:%.*]] = fadd <2 x double> [[WIDE_LOAD]], [[WIDE_LOAD4]] +; CHECK-NEXT: [[TMP1:%.*]] = fadd <2 x double> [[WIDE_LOAD3]], [[WIDE_LOAD5]] ; CHECK-NEXT: store <2 x double> [[TMP0]], ptr @a, align 16 -; CHECK-NEXT: [[WIDE_LOAD_1:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 2), align 16 -; CHECK-NEXT: [[WIDE_LOAD3_1:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 2), align 16 -; CHECK-NEXT: [[TMP1:%.*]] = fadd <2 x double> [[WIDE_LOAD_1]], [[WIDE_LOAD3_1]] ; CHECK-NEXT: store <2 x double> [[TMP1]], ptr getelementptr inbounds ([58 x double], ptr @a, i64 0, i64 2), align 16 -; CHECK-NEXT: [[WIDE_LOAD_2:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 4), align 16 -; CHECK-NEXT: [[WIDE_LOAD3_2:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 4), align 16 -; CHECK-NEXT: [[TMP2:%.*]] = fadd <2 x double> [[WIDE_LOAD_2]], [[WIDE_LOAD3_2]] +; CHECK-NEXT: [[WIDE_LOAD_1:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 4), align 16 +; CHECK-NEXT: [[WIDE_LOAD3_1:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 6), align 16 +; CHECK-NEXT: [[WIDE_LOAD4_1:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 4), align 16 +; CHECK-NEXT: [[WIDE_LOAD5_1:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 6), align 16 +; CHECK-NEXT: [[TMP2:%.*]] = fadd <2 x double> [[WIDE_LOAD_1]], [[WIDE_LOAD4_1]] +; CHECK-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[WIDE_LOAD3_1]], [[WIDE_LOAD5_1]] ; CHECK-NEXT: store <2 x double> [[TMP2]], ptr getelementptr inbounds ([58 x double], ptr @a, i64 0, i64 4), align 16 -; CHECK-NEXT: [[WIDE_LOAD_3:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 6), align 16 -; CHECK-NEXT: [[WIDE_LOAD3_3:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 6), align 16 -; CHECK-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[WIDE_LOAD_3]], [[WIDE_LOAD3_3]] ; CHECK-NEXT: store <2 x double> [[TMP3]], ptr getelementptr inbounds ([58 x double], ptr @a, i64 0, i64 6), align 16 -; CHECK-NEXT: [[WIDE_LOAD_4:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 8), align 16 -; CHECK-NEXT: [[WIDE_LOAD3_4:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 8), align 16 -; CHECK-NEXT: [[TMP4:%.*]] = fadd <2 x double> [[WIDE_LOAD_4]], [[WIDE_LOAD3_4]] +; CHECK-NEXT: [[WIDE_LOAD_2:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 8), align 16 +; CHECK-NEXT: [[WIDE_LOAD3_2:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 10), align 16 +; CHECK-NEXT: [[WIDE_LOAD4_2:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 8), align 16 +; CHECK-NEXT: [[WIDE_LOAD5_2:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 10), align 16 +; CHECK-NEXT: [[TMP4:%.*]] = fadd <2 x double> [[WIDE_LOAD_2]], [[WIDE_LOAD4_2]] +; CHECK-NEXT: [[TMP5:%.*]] = fadd <2 x double> [[WIDE_LOAD3_2]], [[WIDE_LOAD5_2]] ; CHECK-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([58 x double], ptr @a, i64 0, i64 8), align 16 -; CHECK-NEXT: [[WIDE_LOAD_5:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 10), align 16 -; CHECK-NEXT: [[WIDE_LOAD3_5:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 10), align 16 -; CHECK-NEXT: [[TMP5:%.*]] = fadd <2 x double> [[WIDE_LOAD_5]], [[WIDE_LOAD3_5]] ; CHECK-NEXT: store <2 x double> [[TMP5]], ptr getelementptr inbounds ([58 x double], ptr @a, i64 0, i64 10), align 16 -; CHECK-NEXT: [[WIDE_LOAD_6:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 12), align 16 -; CHECK-NEXT: [[WIDE_LOAD3_6:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 12), align 16 -; CHECK-NEXT: [[TMP6:%.*]] = fadd <2 x double> [[WIDE_LOAD_6]], [[WIDE_LOAD3_6]] +; CHECK-NEXT: [[WIDE_LOAD_3:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 12), align 16 +; CHECK-NEXT: [[WIDE_LOAD3_3:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 14), align 16 +; CHECK-NEXT: [[WIDE_LOAD4_3:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 12), align 16 +; CHECK-NEXT: [[WIDE_LOAD5_3:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 14), align 16 +; CHECK-NEXT: [[TMP6:%.*]] = fadd <2 x double> [[WIDE_LOAD_3]], [[WIDE_LOAD4_3]] +; CHECK-NEXT: [[TMP7:%.*]] = fadd <2 x double> [[WIDE_LOAD3_3]], [[WIDE_LOAD5_3]] ; CHECK-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([58 x double], ptr @a, i64 0, i64 12), align 16 -; CHECK-NEXT: [[WIDE_LOAD_7:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 14), align 16 -; CHECK-NEXT: [[WIDE_LOAD3_7:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 14), align 16 -; CHECK-NEXT: [[TMP7:%.*]] = fadd <2 x double> [[WIDE_LOAD_7]], [[WIDE_LOAD3_7]] ; CHECK-NEXT: store <2 x double> [[TMP7]], ptr getelementptr inbounds ([58 x double], ptr @a, i64 0, i64 14), align 16 -; CHECK-NEXT: [[WIDE_LOAD_8:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 16), align 16 -; CHECK-NEXT: [[WIDE_LOAD3_8:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 16), align 16 -; CHECK-NEXT: [[TMP8:%.*]] = fadd <2 x double> [[WIDE_LOAD_8]], [[WIDE_LOAD3_8]] +; CHECK-NEXT: [[WIDE_LOAD_4:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 16), align 16 +; CHECK-NEXT: [[WIDE_LOAD3_4:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 18), align 16 +; CHECK-NEXT: [[WIDE_LOAD4_4:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 16), align 16 +; CHECK-NEXT: [[WIDE_LOAD5_4:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 18), align 16 +; CHECK-NEXT: [[TMP8:%.*]] = fadd <2 x double> [[WIDE_LOAD_4]], [[WIDE_LOAD4_4]] +; CHECK-NEXT: [[TMP9:%.*]] = fadd <2 x double> [[WIDE_LOAD3_4]], [[WIDE_LOAD5_4]] ; CHECK-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([58 x double], ptr @a, i64 0, i64 16), align 16 -; CHECK-NEXT: [[WIDE_LOAD_9:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 18), align 16 -; CHECK-NEXT: [[WIDE_LOAD3_9:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 18), align 16 -; CHECK-NEXT: [[TMP9:%.*]] = fadd <2 x double> [[WIDE_LOAD_9]], [[WIDE_LOAD3_9]] ; CHECK-NEXT: store <2 x double> [[TMP9]], ptr getelementptr inbounds ([58 x double], ptr @a, i64 0, i64 18), align 16 -; CHECK-NEXT: [[WIDE_LOAD_10:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 20), align 16 -; CHECK-NEXT: [[WIDE_LOAD3_10:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 20), align 16 -; CHECK-NEXT: [[TMP10:%.*]] = fadd <2 x double> [[WIDE_LOAD_10]], [[WIDE_LOAD3_10]] +; CHECK-NEXT: [[WIDE_LOAD_5:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 20), align 16 +; CHECK-NEXT: [[WIDE_LOAD3_5:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 22), align 16 +; CHECK-NEXT: [[WIDE_LOAD4_5:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 20), align 16 +; CHECK-NEXT: [[WIDE_LOAD5_5:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 22), align 16 +; CHECK-NEXT: [[TMP10:%.*]] = fadd <2 x double> [[WIDE_LOAD_5]], [[WIDE_LOAD4_5]] +; CHECK-NEXT: [[TMP11:%.*]] = fadd <2 x double> [[WIDE_LOAD3_5]], [[WIDE_LOAD5_5]] ; CHECK-NEXT: store <2 x double> [[TMP10]], ptr getelementptr inbounds ([58 x double], ptr @a, i64 0, i64 20), align 16 -; CHECK-NEXT: [[WIDE_LOAD_11:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 22), align 16 -; CHECK-NEXT: [[WIDE_LOAD3_11:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 22), align 16 -; CHECK-NEXT: [[TMP11:%.*]] = fadd <2 x double> [[WIDE_LOAD_11]], [[WIDE_LOAD3_11]] ; CHECK-NEXT: store <2 x double> [[TMP11]], ptr getelementptr inbounds ([58 x double], ptr @a, i64 0, i64 22), align 16 -; CHECK-NEXT: [[WIDE_LOAD_12:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 24), align 16 -; CHECK-NEXT: [[WIDE_LOAD3_12:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 24), align 16 -; CHECK-NEXT: [[TMP12:%.*]] = fadd <2 x double> [[WIDE_LOAD_12]], [[WIDE_LOAD3_12]] +; CHECK-NEXT: [[WIDE_LOAD_6:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 24), align 16 +; CHECK-NEXT: [[WIDE_LOAD3_6:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 26), align 16 +; CHECK-NEXT: [[WIDE_LOAD4_6:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 24), align 16 +; CHECK-NEXT: [[WIDE_LOAD5_6:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 26), align 16 +; CHECK-NEXT: [[TMP12:%.*]] = fadd <2 x double> [[WIDE_LOAD_6]], [[WIDE_LOAD4_6]] +; CHECK-NEXT: [[TMP13:%.*]] = fadd <2 x double> [[WIDE_LOAD3_6]], [[WIDE_LOAD5_6]] ; CHECK-NEXT: store <2 x double> [[TMP12]], ptr getelementptr inbounds ([58 x double], ptr @a, i64 0, i64 24), align 16 -; CHECK-NEXT: [[WIDE_LOAD_13:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 26), align 16 -; CHECK-NEXT: [[WIDE_LOAD3_13:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 26), align 16 -; CHECK-NEXT: [[TMP13:%.*]] = fadd <2 x double> [[WIDE_LOAD_13]], [[WIDE_LOAD3_13]] ; CHECK-NEXT: store <2 x double> [[TMP13]], ptr getelementptr inbounds ([58 x double], ptr @a, i64 0, i64 26), align 16 -; CHECK-NEXT: [[WIDE_LOAD_14:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 28), align 16 -; CHECK-NEXT: [[WIDE_LOAD3_14:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 28), align 16 -; CHECK-NEXT: [[TMP14:%.*]] = fadd <2 x double> [[WIDE_LOAD_14]], [[WIDE_LOAD3_14]] +; CHECK-NEXT: [[WIDE_LOAD_7:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 28), align 16 +; CHECK-NEXT: [[WIDE_LOAD3_7:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 30), align 16 +; CHECK-NEXT: [[WIDE_LOAD4_7:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 28), align 16 +; CHECK-NEXT: [[WIDE_LOAD5_7:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 30), align 16 +; CHECK-NEXT: [[TMP14:%.*]] = fadd <2 x double> [[WIDE_LOAD_7]], [[WIDE_LOAD4_7]] +; CHECK-NEXT: [[TMP15:%.*]] = fadd <2 x double> [[WIDE_LOAD3_7]], [[WIDE_LOAD5_7]] ; CHECK-NEXT: store <2 x double> [[TMP14]], ptr getelementptr inbounds ([58 x double], ptr @a, i64 0, i64 28), align 16 -; CHECK-NEXT: [[WIDE_LOAD_15:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 30), align 16 -; CHECK-NEXT: [[WIDE_LOAD3_15:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 30), align 16 -; CHECK-NEXT: [[TMP15:%.*]] = fadd <2 x double> [[WIDE_LOAD_15]], [[WIDE_LOAD3_15]] ; CHECK-NEXT: store <2 x double> [[TMP15]], ptr getelementptr inbounds ([58 x double], ptr @a, i64 0, i64 30), align 16 -; CHECK-NEXT: [[WIDE_LOAD_16:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 32), align 16 -; CHECK-NEXT: [[WIDE_LOAD3_16:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 32), align 16 -; CHECK-NEXT: [[TMP16:%.*]] = fadd <2 x double> [[WIDE_LOAD_16]], [[WIDE_LOAD3_16]] +; CHECK-NEXT: [[WIDE_LOAD_8:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 32), align 16 +; CHECK-NEXT: [[WIDE_LOAD3_8:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 34), align 16 +; CHECK-NEXT: [[WIDE_LOAD4_8:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 32), align 16 +; CHECK-NEXT: [[WIDE_LOAD5_8:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 34), align 16 +; CHECK-NEXT: [[TMP16:%.*]] = fadd <2 x double> [[WIDE_LOAD_8]], [[WIDE_LOAD4_8]] +; CHECK-NEXT: [[TMP17:%.*]] = fadd <2 x double> [[WIDE_LOAD3_8]], [[WIDE_LOAD5_8]] ; CHECK-NEXT: store <2 x double> [[TMP16]], ptr getelementptr inbounds ([58 x double], ptr @a, i64 0, i64 32), align 16 -; CHECK-NEXT: [[WIDE_LOAD_17:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 34), align 16 -; CHECK-NEXT: [[WIDE_LOAD3_17:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 34), align 16 -; CHECK-NEXT: [[TMP17:%.*]] = fadd <2 x double> [[WIDE_LOAD_17]], [[WIDE_LOAD3_17]] ; CHECK-NEXT: store <2 x double> [[TMP17]], ptr getelementptr inbounds ([58 x double], ptr @a, i64 0, i64 34), align 16 -; CHECK-NEXT: [[WIDE_LOAD_18:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 36), align 16 -; CHECK-NEXT: [[WIDE_LOAD3_18:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 36), align 16 -; CHECK-NEXT: [[TMP18:%.*]] = fadd <2 x double> [[WIDE_LOAD_18]], [[WIDE_LOAD3_18]] +; CHECK-NEXT: [[WIDE_LOAD_9:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 36), align 16 +; CHECK-NEXT: [[WIDE_LOAD3_9:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 38), align 16 +; CHECK-NEXT: [[WIDE_LOAD4_9:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 36), align 16 +; CHECK-NEXT: [[WIDE_LOAD5_9:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 38), align 16 +; CHECK-NEXT: [[TMP18:%.*]] = fadd <2 x double> [[WIDE_LOAD_9]], [[WIDE_LOAD4_9]] +; CHECK-NEXT: [[TMP19:%.*]] = fadd <2 x double> [[WIDE_LOAD3_9]], [[WIDE_LOAD5_9]] ; CHECK-NEXT: store <2 x double> [[TMP18]], ptr getelementptr inbounds ([58 x double], ptr @a, i64 0, i64 36), align 16 -; CHECK-NEXT: [[WIDE_LOAD_19:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 38), align 16 -; CHECK-NEXT: [[WIDE_LOAD3_19:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 38), align 16 -; CHECK-NEXT: [[TMP19:%.*]] = fadd <2 x double> [[WIDE_LOAD_19]], [[WIDE_LOAD3_19]] ; CHECK-NEXT: store <2 x double> [[TMP19]], ptr getelementptr inbounds ([58 x double], ptr @a, i64 0, i64 38), align 16 -; CHECK-NEXT: [[WIDE_LOAD_20:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 40), align 16 -; CHECK-NEXT: [[WIDE_LOAD3_20:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 40), align 16 -; CHECK-NEXT: [[TMP20:%.*]] = fadd <2 x double> [[WIDE_LOAD_20]], [[WIDE_LOAD3_20]] +; CHECK-NEXT: [[WIDE_LOAD_10:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 40), align 16 +; CHECK-NEXT: [[WIDE_LOAD3_10:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 42), align 16 +; CHECK-NEXT: [[WIDE_LOAD4_10:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 40), align 16 +; CHECK-NEXT: [[WIDE_LOAD5_10:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 42), align 16 +; CHECK-NEXT: [[TMP20:%.*]] = fadd <2 x double> [[WIDE_LOAD_10]], [[WIDE_LOAD4_10]] +; CHECK-NEXT: [[TMP21:%.*]] = fadd <2 x double> [[WIDE_LOAD3_10]], [[WIDE_LOAD5_10]] ; CHECK-NEXT: store <2 x double> [[TMP20]], ptr getelementptr inbounds ([58 x double], ptr @a, i64 0, i64 40), align 16 -; CHECK-NEXT: [[WIDE_LOAD_21:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 42), align 16 -; CHECK-NEXT: [[WIDE_LOAD3_21:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 42), align 16 -; CHECK-NEXT: [[TMP21:%.*]] = fadd <2 x double> [[WIDE_LOAD_21]], [[WIDE_LOAD3_21]] ; CHECK-NEXT: store <2 x double> [[TMP21]], ptr getelementptr inbounds ([58 x double], ptr @a, i64 0, i64 42), align 16 -; CHECK-NEXT: [[WIDE_LOAD_22:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 44), align 16 -; CHECK-NEXT: [[WIDE_LOAD3_22:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 44), align 16 -; CHECK-NEXT: [[TMP22:%.*]] = fadd <2 x double> [[WIDE_LOAD_22]], [[WIDE_LOAD3_22]] +; CHECK-NEXT: [[WIDE_LOAD_11:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 44), align 16 +; CHECK-NEXT: [[WIDE_LOAD3_11:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 46), align 16 +; CHECK-NEXT: [[WIDE_LOAD4_11:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 44), align 16 +; CHECK-NEXT: [[WIDE_LOAD5_11:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 46), align 16 +; CHECK-NEXT: [[TMP22:%.*]] = fadd <2 x double> [[WIDE_LOAD_11]], [[WIDE_LOAD4_11]] +; CHECK-NEXT: [[TMP23:%.*]] = fadd <2 x double> [[WIDE_LOAD3_11]], [[WIDE_LOAD5_11]] ; CHECK-NEXT: store <2 x double> [[TMP22]], ptr getelementptr inbounds ([58 x double], ptr @a, i64 0, i64 44), align 16 -; CHECK-NEXT: [[WIDE_LOAD_23:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 46), align 16 -; CHECK-NEXT: [[WIDE_LOAD3_23:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 46), align 16 -; CHECK-NEXT: [[TMP23:%.*]] = fadd <2 x double> [[WIDE_LOAD_23]], [[WIDE_LOAD3_23]] ; CHECK-NEXT: store <2 x double> [[TMP23]], ptr getelementptr inbounds ([58 x double], ptr @a, i64 0, i64 46), align 16 -; CHECK-NEXT: [[WIDE_LOAD_24:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 48), align 16 -; CHECK-NEXT: [[WIDE_LOAD3_24:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 48), align 16 -; CHECK-NEXT: [[TMP24:%.*]] = fadd <2 x double> [[WIDE_LOAD_24]], [[WIDE_LOAD3_24]] +; CHECK-NEXT: [[WIDE_LOAD_12:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 48), align 16 +; CHECK-NEXT: [[WIDE_LOAD3_12:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 50), align 16 +; CHECK-NEXT: [[WIDE_LOAD4_12:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 48), align 16 +; CHECK-NEXT: [[WIDE_LOAD5_12:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 50), align 16 +; CHECK-NEXT: [[TMP24:%.*]] = fadd <2 x double> [[WIDE_LOAD_12]], [[WIDE_LOAD4_12]] +; CHECK-NEXT: [[TMP25:%.*]] = fadd <2 x double> [[WIDE_LOAD3_12]], [[WIDE_LOAD5_12]] ; CHECK-NEXT: store <2 x double> [[TMP24]], ptr getelementptr inbounds ([58 x double], ptr @a, i64 0, i64 48), align 16 -; CHECK-NEXT: [[WIDE_LOAD_25:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 50), align 16 -; CHECK-NEXT: [[WIDE_LOAD3_25:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 50), align 16 -; CHECK-NEXT: [[TMP25:%.*]] = fadd <2 x double> [[WIDE_LOAD_25]], [[WIDE_LOAD3_25]] ; CHECK-NEXT: store <2 x double> [[TMP25]], ptr getelementptr inbounds ([58 x double], ptr @a, i64 0, i64 50), align 16 -; CHECK-NEXT: [[WIDE_LOAD_26:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 52), align 16 -; CHECK-NEXT: [[WIDE_LOAD3_26:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 52), align 16 -; CHECK-NEXT: [[TMP26:%.*]] = fadd <2 x double> [[WIDE_LOAD_26]], [[WIDE_LOAD3_26]] +; CHECK-NEXT: [[WIDE_LOAD_13:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 52), align 16 +; CHECK-NEXT: [[WIDE_LOAD3_13:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 54), align 16 +; CHECK-NEXT: [[WIDE_LOAD4_13:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 52), align 16 +; CHECK-NEXT: [[WIDE_LOAD5_13:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 54), align 16 +; CHECK-NEXT: [[TMP26:%.*]] = fadd <2 x double> [[WIDE_LOAD_13]], [[WIDE_LOAD4_13]] +; CHECK-NEXT: [[TMP27:%.*]] = fadd <2 x double> [[WIDE_LOAD3_13]], [[WIDE_LOAD5_13]] ; CHECK-NEXT: store <2 x double> [[TMP26]], ptr getelementptr inbounds ([58 x double], ptr @a, i64 0, i64 52), align 16 -; CHECK-NEXT: [[WIDE_LOAD_27:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 54), align 16 -; CHECK-NEXT: [[WIDE_LOAD3_27:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 54), align 16 -; CHECK-NEXT: [[TMP27:%.*]] = fadd <2 x double> [[WIDE_LOAD_27]], [[WIDE_LOAD3_27]] ; CHECK-NEXT: store <2 x double> [[TMP27]], ptr getelementptr inbounds ([58 x double], ptr @a, i64 0, i64 54), align 16 -; CHECK-NEXT: [[WIDE_LOAD_28:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 56), align 16 -; CHECK-NEXT: [[WIDE_LOAD3_28:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 56), align 16 -; CHECK-NEXT: [[TMP28:%.*]] = fadd <2 x double> [[WIDE_LOAD_28]], [[WIDE_LOAD3_28]] +; CHECK-NEXT: [[WIDE_LOAD_14:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 0, i64 56), align 16 +; CHECK-NEXT: [[WIDE_LOAD3_14:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 1, i64 0), align 16 +; CHECK-NEXT: [[WIDE_LOAD4_14:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 0, i64 56), align 16 +; CHECK-NEXT: [[WIDE_LOAD5_14:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 1, i64 0), align 16 +; CHECK-NEXT: [[TMP28:%.*]] = fadd <2 x double> [[WIDE_LOAD_14]], [[WIDE_LOAD4_14]] +; CHECK-NEXT: [[TMP29:%.*]] = fadd <2 x double> [[WIDE_LOAD3_14]], [[WIDE_LOAD5_14]] ; CHECK-NEXT: store <2 x double> [[TMP28]], ptr getelementptr inbounds ([58 x double], ptr @a, i64 0, i64 56), align 16 -; CHECK-NEXT: [[WIDE_LOAD_29:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @b, i64 1, i64 0), align 16 -; CHECK-NEXT: [[WIDE_LOAD3_29:%.*]] = load <2 x double>, ptr getelementptr inbounds ([58 x double], ptr @c, i64 1, i64 0), align 16 -; CHECK-NEXT: [[TMP29:%.*]] = fadd <2 x double> [[WIDE_LOAD_29]], [[WIDE_LOAD3_29]] ; CHECK-NEXT: store <2 x double> [[TMP29]], ptr getelementptr inbounds ([58 x double], ptr @a, i64 1, i64 0), align 16 ; CHECK-NEXT: [[TMP30:%.*]] = load double, ptr getelementptr inbounds ([58 x double], ptr @b, i64 1, i64 2), align 16 ; CHECK-NEXT: [[TMP31:%.*]] = load double, ptr getelementptr inbounds ([58 x double], ptr @c, i64 1, i64 2), align 16 -- GitLab From c0cb0be85ca7aa3f9c14f2c8272f581a20474619 Mon Sep 17 00:00:00 2001 From: Derek Schuff Date: Mon, 5 Feb 2024 17:38:54 -0800 Subject: [PATCH 014/266] Mark llvm/test/CodeGen/WebAssembly/immediates.ll as passing on MIPS (#80771) Fixes #80533 --- llvm/test/CodeGen/WebAssembly/immediates.ll | 6 ------ 1 file changed, 6 deletions(-) diff --git a/llvm/test/CodeGen/WebAssembly/immediates.ll b/llvm/test/CodeGen/WebAssembly/immediates.ll index e2342f391b13..9de5aa740249 100644 --- a/llvm/test/CodeGen/WebAssembly/immediates.ll +++ b/llvm/test/CodeGen/WebAssembly/immediates.ll @@ -1,11 +1,5 @@ ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s -; Usually MIPS hosts uses a legacy (non IEEE 754-2008) encoding for NaNs. -; Tests like `nan_f32` failed in attempt to compare hard-coded IEEE 754-2008 -; NaN value and a legacy NaN value provided by a system. -; FIXME: This should be based on host not target, but there's no "system-mips" feature. -; XFAIL: target={{(mips|mipsel|mips64|mips64el)-.*}} - ; Test that basic immediates assemble as expected. target triple = "wasm32-unknown-unknown" -- GitLab From 0123cefc00177e4fc7daa0dadf98ca8336760785 Mon Sep 17 00:00:00 2001 From: jeffreytan81 Date: Mon, 5 Feb 2024 17:40:28 -0800 Subject: [PATCH 015/266] Add a new SBProcess:: GetCoreFile() API (#80767) We have a Python script that needs to locate coredump path during debugging so that we can retrieve certain metadata files associated with it. Currently, there is no API for this. This patch adds a new `SBProcess::GetCoreFile()` to retrieve target dump file spec used for dump debugging. Note: this is different from the main executable module spec. To achieve this, the patch hoists m_core_file into PostMortemProcess for sharing. --------- Co-authored-by: jeffreytan81 --- lldb/include/lldb/API/SBProcess.h | 9 ++++++++ lldb/include/lldb/Target/PostMortemProcess.h | 9 ++++++++ lldb/include/lldb/Target/Process.h | 7 +++++++ lldb/include/lldb/Target/ProcessTrace.h | 3 ++- lldb/source/API/SBProcess.cpp | 11 ++++++++++ .../FreeBSDKernel/ProcessFreeBSDKernel.cpp | 21 +++++++++++-------- .../FreeBSDKernel/ProcessFreeBSDKernel.h | 3 ++- .../Process/elf-core/ProcessElfCore.cpp | 6 +++--- .../Plugins/Process/elf-core/ProcessElfCore.h | 1 - .../Process/mach-core/ProcessMachCore.cpp | 4 ++-- .../Process/mach-core/ProcessMachCore.h | 1 - .../Process/minidump/ProcessMinidump.cpp | 2 +- .../Process/minidump/ProcessMinidump.h | 1 - lldb/source/Target/ProcessTrace.cpp | 7 ++++--- .../postmortem/elf-core/TestLinuxCore.py | 11 ++++++++++ 15 files changed, 73 insertions(+), 23 deletions(-) diff --git a/lldb/include/lldb/API/SBProcess.h b/lldb/include/lldb/API/SBProcess.h index 8c1c81418f83..4f92a41f3028 100644 --- a/lldb/include/lldb/API/SBProcess.h +++ b/lldb/include/lldb/API/SBProcess.h @@ -398,6 +398,15 @@ public: /// valid. lldb::SBProcessInfo GetProcessInfo(); + /// Get the file specification for the core file that is currently being used + /// for the process. If the process is not loaded from a core file, then an + /// invalid file specification will be returned. + /// + /// \return + /// The path to the core file for this target or an invalid file spec if + /// the process isn't loaded from a core file. + lldb::SBFileSpec GetCoreFile(); + /// Allocate memory within the process. /// /// This function will allocate memory in the process's address space. diff --git a/lldb/include/lldb/Target/PostMortemProcess.h b/lldb/include/lldb/Target/PostMortemProcess.h index 7207fc99ef29..9c9cd7fa599b 100644 --- a/lldb/include/lldb/Target/PostMortemProcess.h +++ b/lldb/include/lldb/Target/PostMortemProcess.h @@ -24,7 +24,16 @@ class PostMortemProcess : public Process { using Process::Process; public: + PostMortemProcess(lldb::TargetSP target_sp, lldb::ListenerSP listener_sp, + const FileSpec &core_file) + : Process(target_sp, listener_sp), m_core_file(core_file) {} + bool IsLiveDebugSession() const override { return false; } + + FileSpec GetCoreFile() const override { return m_core_file; } + +protected: + FileSpec m_core_file; }; } // namespace lldb_private diff --git a/lldb/include/lldb/Target/Process.h b/lldb/include/lldb/Target/Process.h index 7048921d6034..0ad626ffd361 100644 --- a/lldb/include/lldb/Target/Process.h +++ b/lldb/include/lldb/Target/Process.h @@ -1503,6 +1503,13 @@ public: virtual bool IsLiveDebugSession() const { return true; }; + /// Provide a way to retrieve the core dump file that is loaded for debugging. + /// Only available if IsLiveDebugSession() returns true. + /// + /// \return + /// File path to the core file. + virtual FileSpec GetCoreFile() const { return {}; } + /// Before lldb detaches from a process, it warns the user that they are /// about to lose their debug session. In some cases, this warning doesn't /// need to be emitted -- for instance, with core file debugging where the diff --git a/lldb/include/lldb/Target/ProcessTrace.h b/lldb/include/lldb/Target/ProcessTrace.h index 037dea232cc0..7a025100f680 100644 --- a/lldb/include/lldb/Target/ProcessTrace.h +++ b/lldb/include/lldb/Target/ProcessTrace.h @@ -27,7 +27,8 @@ public: static llvm::StringRef GetPluginDescriptionStatic(); - ProcessTrace(lldb::TargetSP target_sp, lldb::ListenerSP listener_sp); + ProcessTrace(lldb::TargetSP target_sp, lldb::ListenerSP listener_sp, + const FileSpec &core_file); ~ProcessTrace() override; diff --git a/lldb/source/API/SBProcess.cpp b/lldb/source/API/SBProcess.cpp index 4864ea0e7d02..a9fe91532468 100644 --- a/lldb/source/API/SBProcess.cpp +++ b/lldb/source/API/SBProcess.cpp @@ -1244,6 +1244,17 @@ lldb::SBProcessInfo SBProcess::GetProcessInfo() { return sb_proc_info; } +lldb::SBFileSpec SBProcess::GetCoreFile() { + LLDB_INSTRUMENT_VA(this); + + ProcessSP process_sp(GetSP()); + FileSpec core_file; + if (process_sp) { + core_file = process_sp->GetCoreFile(); + } + return SBFileSpec(core_file); +} + lldb::addr_t SBProcess::AllocateMemory(size_t size, uint32_t permissions, lldb::SBError &sb_error) { LLDB_INSTRUMENT_VA(this, size, permissions, sb_error); diff --git a/lldb/source/Plugins/Process/FreeBSDKernel/ProcessFreeBSDKernel.cpp b/lldb/source/Plugins/Process/FreeBSDKernel/ProcessFreeBSDKernel.cpp index 601f5df43dbb..997b59085110 100644 --- a/lldb/source/Plugins/Process/FreeBSDKernel/ProcessFreeBSDKernel.cpp +++ b/lldb/source/Plugins/Process/FreeBSDKernel/ProcessFreeBSDKernel.cpp @@ -32,7 +32,7 @@ namespace { class ProcessFreeBSDKernelFVC : public ProcessFreeBSDKernel { public: ProcessFreeBSDKernelFVC(lldb::TargetSP target_sp, lldb::ListenerSP listener, - fvc_t *fvc); + fvc_t *fvc, const FileSpec &core_file); ~ProcessFreeBSDKernelFVC(); @@ -67,8 +67,9 @@ private: } // namespace ProcessFreeBSDKernel::ProcessFreeBSDKernel(lldb::TargetSP target_sp, - ListenerSP listener_sp) - : PostMortemProcess(target_sp, listener_sp) {} + ListenerSP listener_sp, + const FileSpec &core_file) + : PostMortemProcess(target_sp, listener_sp, core_file) {} lldb::ProcessSP ProcessFreeBSDKernel::CreateInstance(lldb::TargetSP target_sp, ListenerSP listener_sp, @@ -82,7 +83,7 @@ lldb::ProcessSP ProcessFreeBSDKernel::CreateInstance(lldb::TargetSP target_sp, crash_file->GetPath().c_str(), nullptr, nullptr, nullptr); if (fvc) return std::make_shared(target_sp, listener_sp, - fvc); + fvc, *crash_file); #endif #if defined(__FreeBSD__) @@ -91,7 +92,7 @@ lldb::ProcessSP ProcessFreeBSDKernel::CreateInstance(lldb::TargetSP target_sp, crash_file->GetPath().c_str(), O_RDONLY, nullptr, nullptr); if (kvm) return std::make_shared(target_sp, listener_sp, - kvm); + kvm, *crash_file); #endif } return nullptr; @@ -276,8 +277,9 @@ lldb::addr_t ProcessFreeBSDKernel::FindSymbol(const char *name) { ProcessFreeBSDKernelFVC::ProcessFreeBSDKernelFVC(lldb::TargetSP target_sp, ListenerSP listener_sp, - fvc_t *fvc) - : ProcessFreeBSDKernel(target_sp, listener_sp), m_fvc(fvc) {} + fvc_t *fvc, + const FileSpec &core_file) + : ProcessFreeBSDKernel(target_sp, listener_sp, crash_file), m_fvc(fvc) {} ProcessFreeBSDKernelFVC::~ProcessFreeBSDKernelFVC() { if (m_fvc) @@ -303,8 +305,9 @@ const char *ProcessFreeBSDKernelFVC::GetError() { return fvc_geterr(m_fvc); } ProcessFreeBSDKernelKVM::ProcessFreeBSDKernelKVM(lldb::TargetSP target_sp, ListenerSP listener_sp, - kvm_t *fvc) - : ProcessFreeBSDKernel(target_sp, listener_sp), m_kvm(fvc) {} + kvm_t *fvc, + const FileSpec &core_file) + : ProcessFreeBSDKernel(target_sp, listener_sp, core_file), m_kvm(fvc) {} ProcessFreeBSDKernelKVM::~ProcessFreeBSDKernelKVM() { if (m_kvm) diff --git a/lldb/source/Plugins/Process/FreeBSDKernel/ProcessFreeBSDKernel.h b/lldb/source/Plugins/Process/FreeBSDKernel/ProcessFreeBSDKernel.h index 5bd463126307..06c9d062441e 100644 --- a/lldb/source/Plugins/Process/FreeBSDKernel/ProcessFreeBSDKernel.h +++ b/lldb/source/Plugins/Process/FreeBSDKernel/ProcessFreeBSDKernel.h @@ -13,7 +13,8 @@ class ProcessFreeBSDKernel : public lldb_private::PostMortemProcess { public: - ProcessFreeBSDKernel(lldb::TargetSP target_sp, lldb::ListenerSP listener); + ProcessFreeBSDKernel(lldb::TargetSP target_sp, lldb::ListenerSP listener, + const lldb_private::FileSpec &core_file); static lldb::ProcessSP CreateInstance(lldb::TargetSP target_sp, lldb::ListenerSP listener, diff --git a/lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp b/lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp index 7723009787f7..36812c27a5b6 100644 --- a/lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp +++ b/lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp @@ -99,7 +99,7 @@ bool ProcessElfCore::CanDebug(lldb::TargetSP target_sp, ProcessElfCore::ProcessElfCore(lldb::TargetSP target_sp, lldb::ListenerSP listener_sp, const FileSpec &core_file) - : PostMortemProcess(target_sp, listener_sp), m_core_file(core_file) {} + : PostMortemProcess(target_sp, listener_sp, core_file) {} // Destructor ProcessElfCore::~ProcessElfCore() { @@ -261,8 +261,8 @@ Status ProcessElfCore::DoLoadCore() { exe_module_spec.GetFileSpec().SetFile(m_nt_file_entries[0].path, FileSpec::Style::native); if (exe_module_spec.GetFileSpec()) { - exe_module_sp = GetTarget().GetOrCreateModule(exe_module_spec, - true /* notify */); + exe_module_sp = + GetTarget().GetOrCreateModule(exe_module_spec, true /* notify */); if (exe_module_sp) GetTarget().SetExecutableModule(exe_module_sp, eLoadDependentsNo); } diff --git a/lldb/source/Plugins/Process/elf-core/ProcessElfCore.h b/lldb/source/Plugins/Process/elf-core/ProcessElfCore.h index 1454e8735a67..2cec635bbacf 100644 --- a/lldb/source/Plugins/Process/elf-core/ProcessElfCore.h +++ b/lldb/source/Plugins/Process/elf-core/ProcessElfCore.h @@ -127,7 +127,6 @@ private: VMRangeToPermissions; lldb::ModuleSP m_core_module_sp; - lldb_private::FileSpec m_core_file; std::string m_dyld_plugin_name; // True if m_thread_contexts contains valid entries diff --git a/lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp b/lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp index a2ea19388b75..3961dcf0fbcc 100644 --- a/lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp +++ b/lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp @@ -111,8 +111,8 @@ bool ProcessMachCore::CanDebug(lldb::TargetSP target_sp, ProcessMachCore::ProcessMachCore(lldb::TargetSP target_sp, ListenerSP listener_sp, const FileSpec &core_file) - : PostMortemProcess(target_sp, listener_sp), m_core_aranges(), - m_core_range_infos(), m_core_module_sp(), m_core_file(core_file), + : PostMortemProcess(target_sp, listener_sp, core_file), m_core_aranges(), + m_core_range_infos(), m_core_module_sp(), m_dyld_addr(LLDB_INVALID_ADDRESS), m_mach_kernel_addr(LLDB_INVALID_ADDRESS) {} diff --git a/lldb/source/Plugins/Process/mach-core/ProcessMachCore.h b/lldb/source/Plugins/Process/mach-core/ProcessMachCore.h index c8820209e3f3..8996ae116614 100644 --- a/lldb/source/Plugins/Process/mach-core/ProcessMachCore.h +++ b/lldb/source/Plugins/Process/mach-core/ProcessMachCore.h @@ -130,7 +130,6 @@ private: VMRangeToFileOffset m_core_aranges; VMRangeToPermissions m_core_range_infos; lldb::ModuleSP m_core_module_sp; - lldb_private::FileSpec m_core_file; lldb::addr_t m_dyld_addr; lldb::addr_t m_mach_kernel_addr; llvm::StringRef m_dyld_plugin_name; diff --git a/lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp b/lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp index b72307c7e4b9..13599f4a1553 100644 --- a/lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp +++ b/lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp @@ -156,7 +156,7 @@ ProcessMinidump::ProcessMinidump(lldb::TargetSP target_sp, lldb::ListenerSP listener_sp, const FileSpec &core_file, DataBufferSP core_data) - : PostMortemProcess(target_sp, listener_sp), m_core_file(core_file), + : PostMortemProcess(target_sp, listener_sp, core_file), m_core_data(std::move(core_data)), m_active_exception(nullptr), m_is_wow64(false) {} diff --git a/lldb/source/Plugins/Process/minidump/ProcessMinidump.h b/lldb/source/Plugins/Process/minidump/ProcessMinidump.h index 0e4e52c0113f..3f3123a0a8b5 100644 --- a/lldb/source/Plugins/Process/minidump/ProcessMinidump.h +++ b/lldb/source/Plugins/Process/minidump/ProcessMinidump.h @@ -107,7 +107,6 @@ protected: JITLoaderList &GetJITLoaders() override; private: - FileSpec m_core_file; lldb::DataBufferSP m_core_data; llvm::ArrayRef m_thread_list; const minidump::ExceptionStream *m_active_exception; diff --git a/lldb/source/Target/ProcessTrace.cpp b/lldb/source/Target/ProcessTrace.cpp index 3a41f257627c..4718a7ca50a7 100644 --- a/lldb/source/Target/ProcessTrace.cpp +++ b/lldb/source/Target/ProcessTrace.cpp @@ -36,15 +36,16 @@ ProcessSP ProcessTrace::CreateInstance(TargetSP target_sp, bool can_connect) { if (can_connect) return nullptr; - return std::make_shared(target_sp, listener_sp); + return std::make_shared(target_sp, listener_sp, *crash_file); } bool ProcessTrace::CanDebug(TargetSP target_sp, bool plugin_specified_by_name) { return plugin_specified_by_name; } -ProcessTrace::ProcessTrace(TargetSP target_sp, ListenerSP listener_sp) - : PostMortemProcess(target_sp, listener_sp) {} +ProcessTrace::ProcessTrace(TargetSP target_sp, ListenerSP listener_sp, + const FileSpec &core_file) + : PostMortemProcess(target_sp, listener_sp, core_file) {} ProcessTrace::~ProcessTrace() { Clear(); diff --git a/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py b/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py index d6907075820e..7ec5e0d7c830 100644 --- a/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py +++ b/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py @@ -633,6 +633,17 @@ class LinuxCoreTestCase(TestBase): self.expect("register read --all") + def test_get_core_file_api(self): + """ + Test SBProcess::GetCoreFile() API can successfully get the core file. + """ + core_file_name = "linux-x86_64.core" + target = self.dbg.CreateTarget("linux-x86_64.out") + process = target.LoadCore(core_file_name) + self.assertTrue(process, PROCESS_IS_VALID) + self.assertEqual(process.GetCoreFile().GetFilename(), core_file_name) + self.dbg.DeleteTarget(target) + def check_memory_regions(self, process, region_count): region_list = process.GetMemoryRegions() self.assertEqual(region_list.GetSize(), region_count) -- GitLab From 2c2d291b4568381999442e47fc77f949f19be0bc Mon Sep 17 00:00:00 2001 From: Younan Zhang Date: Tue, 6 Feb 2024 09:59:16 +0800 Subject: [PATCH 016/266] [concepts] Extract function template pack arguments from the current instantiation if possible (#80594) Before the constraint substitution, we employ `getTemplateInstantiationArgs`, which in turn attempts to inspect `TemplateArgument`s from the function template. For parameter packs from their parent contexts, we used to extract the arguments from the specialization type, in which could result in non-canonical argument types e.g. `PackExpansionType`. This may break the contract that, during a tree transformation, in `TreeTransform::TryExpandParameterPacks`, the corresponding `TemplateArgument`s for an `UnexpandedParameterPack` are expected to be of `Pack` kinds if we're expanding template parameters. Fixes https://github.com/llvm/llvm-project/issues/72557. --- clang/docs/ReleaseNotes.rst | 3 ++ clang/lib/Sema/SemaTemplateInstantiate.cpp | 32 +++++++++++++++++-- .../SemaTemplate/concepts-out-of-line-def.cpp | 18 +++++++++++ 3 files changed, 51 insertions(+), 2 deletions(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 3596109bf044..4d57ea4fd55b 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -197,6 +197,9 @@ Bug Fixes to C++ Support Fixes (`#67976 `_) - Fix crash and diagnostic with const qualified member operator new. Fixes (`#79748 `_) +- Fixed a crash where substituting into a requires-expression that involves parameter packs + during the equivalence determination of two constraint expressions. + (`#72557 `_) - Fix a crash when specializing an out-of-line member function with a default parameter where we did an incorrect specialization of the initialization of the default parameter. diff --git a/clang/lib/Sema/SemaTemplateInstantiate.cpp b/clang/lib/Sema/SemaTemplateInstantiate.cpp index e5999fa50117..6d59180bc446 100644 --- a/clang/lib/Sema/SemaTemplateInstantiate.cpp +++ b/clang/lib/Sema/SemaTemplateInstantiate.cpp @@ -241,10 +241,38 @@ Response HandleFunctionTemplateDecl(const FunctionTemplateDecl *FTD, while (const Type *Ty = NNS ? NNS->getAsType() : nullptr) { if (NNS->isInstantiationDependent()) { - if (const auto *TSTy = Ty->getAs()) + if (const auto *TSTy = Ty->getAs()) { + ArrayRef Arguments = TSTy->template_arguments(); + // Prefer template arguments from the injected-class-type if possible. + // For example, + // ```cpp + // template struct S { + // template void foo(); + // }; + // template template + // ^^^^^^^^^^^^^ InjectedTemplateArgs + // They're of kind TemplateArgument::Pack, not of + // TemplateArgument::Type. + // void S::foo() {} + // ^^^^^^^ + // TSTy->template_arguments() (which are of PackExpansionType) + // ``` + // This meets the contract in + // TreeTransform::TryExpandParameterPacks that the template arguments + // for unexpanded parameters should be of a Pack kind. + if (TSTy->isCurrentInstantiation()) { + auto *RD = TSTy->getCanonicalTypeInternal()->getAsCXXRecordDecl(); + if (ClassTemplateDecl *CTD = RD->getDescribedClassTemplate()) + Arguments = CTD->getInjectedTemplateArgs(); + else if (auto *Specialization = + dyn_cast(RD)) + Arguments = + Specialization->getTemplateInstantiationArgs().asArray(); + } Result.addOuterTemplateArguments( - const_cast(FTD), TSTy->template_arguments(), + const_cast(FTD), Arguments, /*Final=*/false); + } } NNS = NNS->getPrefix(); diff --git a/clang/test/SemaTemplate/concepts-out-of-line-def.cpp b/clang/test/SemaTemplate/concepts-out-of-line-def.cpp index b6fea2e0b4b3..0142efcdc3ee 100644 --- a/clang/test/SemaTemplate/concepts-out-of-line-def.cpp +++ b/clang/test/SemaTemplate/concepts-out-of-line-def.cpp @@ -581,3 +581,21 @@ void S::test(T target, U... value) } {} } // namespace GH74447 + +namespace GH72557 { + +template +concept IsAnyOf = true; + +template struct DerivedCollection { + template + requires IsAnyOf + unsigned long index(); +}; + +template +template + requires IsAnyOf +unsigned long DerivedCollection::index() {} + +} // namespace GH72557 -- GitLab From 62838b872f1d8c6ffd88c355ece9324258169bdd Mon Sep 17 00:00:00 2001 From: Jie Fu Date: Tue, 6 Feb 2024 10:11:10 +0800 Subject: [PATCH 017/266] [mlir][test] Fix -Wformat in sparse_tensor.c (NFC) llvm-project/mlir/test/CAPI/sparse_tensor.c:50:42: error: format specifies type 'unsigned long' but the argument has type 'MlirSparseTensorLevelType' (aka 'unsigned long long') [-Werror,-Wformat] 50 | fprintf(stderr, "level_type: %lu\n", lvlTypes[l]); | ~~~ ^~~~~~~~~~~ | %llu 1 error generated. --- mlir/test/CAPI/sparse_tensor.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mlir/test/CAPI/sparse_tensor.c b/mlir/test/CAPI/sparse_tensor.c index 4f1d39751754..f5d43a2eccdc 100644 --- a/mlir/test/CAPI/sparse_tensor.c +++ b/mlir/test/CAPI/sparse_tensor.c @@ -47,7 +47,7 @@ static int testRoundtripEncoding(MlirContext ctx) { malloc(sizeof(MlirSparseTensorLevelType) * lvlRank); for (int l = 0; l < lvlRank; ++l) { lvlTypes[l] = mlirSparseTensorEncodingAttrGetLvlType(originalAttr, l); - fprintf(stderr, "level_type: %lu\n", lvlTypes[l]); + fprintf(stderr, "level_type: %llu\n", lvlTypes[l]); } // CHECK: posWidth: 32 int posWidth = mlirSparseTensorEncodingAttrGetPosWidth(originalAttr); -- GitLab From 8f80df0f52c4294d23d0510b01be6d6491714058 Mon Sep 17 00:00:00 2001 From: Aiden Grossman Date: Mon, 5 Feb 2024 18:16:19 -0800 Subject: [PATCH 018/266] [Github] Use building LLVM as perf-training for CI container (#80713) This patch adjusts the build process for building the toolchain for the CI container to perform more rigorous perf-training for PGO, particularly building the entirety of LLVM as that is what showed the best results while benchmarking. This patch also splits the job into two stages to avoid timeouts due to the large increase in buildtime. There are a couple other hacks added in here to make things work that we can do away with eventually once we're able to run jobs like this on more powerful self-hosted runners. --- .github/workflows/build-ci-container.yml | 54 +++++++++++++++++- .../containers/github-action-ci/Dockerfile | 55 ------------------- .../github-action-ci/bootstrap.patch | 13 +++++ .../github-action-ci/stage1.Dockerfile | 44 +++++++++++++++ .../github-action-ci/stage2.Dockerfile | 27 +++++++++ .../containers/github-action-ci/storage.conf | 4 ++ 6 files changed, 139 insertions(+), 58 deletions(-) delete mode 100644 .github/workflows/containers/github-action-ci/Dockerfile create mode 100644 .github/workflows/containers/github-action-ci/bootstrap.patch create mode 100644 .github/workflows/containers/github-action-ci/stage1.Dockerfile create mode 100644 .github/workflows/containers/github-action-ci/stage2.Dockerfile create mode 100644 .github/workflows/containers/github-action-ci/storage.conf diff --git a/.github/workflows/build-ci-container.yml b/.github/workflows/build-ci-container.yml index ad3d50d4d578..3f2bf57eb850 100644 --- a/.github/workflows/build-ci-container.yml +++ b/.github/workflows/build-ci-container.yml @@ -1,4 +1,3 @@ - name: Build CI Container permissions: @@ -19,9 +18,41 @@ on: - '.github/workflows/containers/github-action-ci/**' jobs: - build-ci-container: + # TODO(boomanaiden154): Switch this back to a single stage build when we can + # run this on the self-hosted runners and don't have to do it this way to + # avoid timeouts. + build-ci-container-stage1: if: github.repository_owner == 'llvm' runs-on: ubuntu-latest + steps: + - name: Checkout LLVM + uses: actions/checkout@v4 + with: + sparse-checkout: .github/workflows/containers/github-action-ci/ + - name: Change podman Root Direcotry + run: | + mkdir -p ~/.config/containers + sudo mkdir -p /mnt/podman + sudo chown `whoami`:`whoami` /mnt/podman + cp ./.github/workflows/containers/github-action-ci/storage.conf ~/.config/containers/storage.conf + podman info + - name: Build container stage1 + working-directory: ./.github/workflows/containers/github-action-ci/ + run: | + podman build -t stage1-toolchain --target stage1-toolchain -f stage1.Dockerfile . + - name: Save container image + run: | + podman save stage1-toolchain > stage1-toolchain.tar + - name: Upload container image + uses: actions/upload-artifact@v4 + with: + name: stage1-toolchain + path: stage1-toolchain.tar + retention-days: 1 + build-ci-container-stage2: + if: github.repository_owner == 'llvm' + runs-on: ubuntu-latest + needs: build-ci-container-stage1 permissions: packages: write steps: @@ -38,10 +69,27 @@ jobs: with: sparse-checkout: .github/workflows/containers/github-action-ci/ + - name: Change podman Root Direcotry + run: | + mkdir -p ~/.config/containers + sudo mkdir -p /mnt/podman + sudo chown `whoami`:`whoami` /mnt/podman + cp ./.github/workflows/containers/github-action-ci/storage.conf ~/.config/containers/storage.conf + podman info + + - name: Download stage1-toolchain + uses: actions/download-artifact@v4 + with: + name: stage1-toolchain + + - name: Load stage1-toolchain + run: | + podman load -i stage1-toolchain.tar + - name: Build Container working-directory: ./.github/workflows/containers/github-action-ci/ run: | - podman build -t ${{ steps.vars.outputs.container-name-tag }} . + podman build -t ${{ steps.vars.outputs.container-name-tag }} -f stage2.Dockerfile . podman tag ${{ steps.vars.outputs.container-name-tag }} ${{ steps.vars.outputs.container-name }}:latest - name: Test Container diff --git a/.github/workflows/containers/github-action-ci/Dockerfile b/.github/workflows/containers/github-action-ci/Dockerfile deleted file mode 100644 index 66fa81d5a10a..000000000000 --- a/.github/workflows/containers/github-action-ci/Dockerfile +++ /dev/null @@ -1,55 +0,0 @@ -FROM docker.io/library/ubuntu:22.04 as base -ENV LLVM_SYSROOT=/opt/llvm - -FROM base as toolchain -ENV LLVM_VERSION=17.0.6 - -RUN apt-get update && \ - apt-get install -y \ - wget \ - gcc \ - g++ \ - cmake \ - ninja-build \ - python3 \ - git - -RUN wget https://github.com/llvm/llvm-project/archive/refs/tags/llvmorg-$LLVM_VERSION.tar.gz && tar -xf llvmorg-$LLVM_VERSION.tar.gz - -WORKDIR /llvm-project-llvmorg-$LLVM_VERSION - -RUN mkdir build - -RUN cmake -B ./build -G Ninja ./llvm \ - -C ./clang/cmake/caches/BOLT-PGO.cmake \ - -DBOOTSTRAP_LLVM_ENABLE_LLD=ON \ - -DBOOTSTRAP_BOOTSTRAP_LLVM_ENABLE_LLD=ON \ - -DPGO_INSTRUMENT_LTO=Thin \ - -DLLVM_ENABLE_RUNTIMES="compiler-rt" \ - -DCMAKE_INSTALL_PREFIX="$LLVM_SYSROOT" \ - -DLLVM_ENABLE_PROJECTS="bolt;clang;lld;clang-tools-extra" \ - -DLLVM_DISTRIBUTION_COMPONENTS="lld;compiler-rt;clang-format" \ - -DCLANG_DEFAULT_LINKER="lld" - -RUN ninja -C ./build stage2-clang-bolt stage2-install-distribution && ninja -C ./build install-distribution && rm -rf ./build - -FROM base - -COPY --from=toolchain $LLVM_SYSROOT $LLVM_SYSROOT - -# Need to install curl for hendrikmuhs/ccache-action -# Need nodejs for some of the GitHub actions. -# Need perl-modules for clang analyzer tests. -RUN apt-get update && \ - apt-get install -y \ - binutils \ - cmake \ - curl \ - libstdc++-11-dev \ - ninja-build \ - nodejs \ - perl-modules \ - python3-psutil - -ENV LLVM_SYSROOT=$LLVM_SYSROOT -ENV PATH=${LLVM_SYSROOT}/bin:${PATH} diff --git a/.github/workflows/containers/github-action-ci/bootstrap.patch b/.github/workflows/containers/github-action-ci/bootstrap.patch new file mode 100644 index 000000000000..55631c54a396 --- /dev/null +++ b/.github/workflows/containers/github-action-ci/bootstrap.patch @@ -0,0 +1,13 @@ +diff --git a/clang/cmake/caches/BOLT-PGO.cmake b/clang/cmake/caches/BOLT-PGO.cmake +index 1a04ca9a74e5..d092820e4115 100644 +--- a/clang/cmake/caches/BOLT-PGO.cmake ++++ b/clang/cmake/caches/BOLT-PGO.cmake +@@ -4,6 +4,8 @@ set(CLANG_BOOTSTRAP_TARGETS + stage2-clang-bolt + stage2-distribution + stage2-install-distribution ++ clang ++ lld + CACHE STRING "") + set(BOOTSTRAP_CLANG_BOOTSTRAP_TARGETS + clang-bolt diff --git a/.github/workflows/containers/github-action-ci/stage1.Dockerfile b/.github/workflows/containers/github-action-ci/stage1.Dockerfile new file mode 100644 index 000000000000..fbc4548e6636 --- /dev/null +++ b/.github/workflows/containers/github-action-ci/stage1.Dockerfile @@ -0,0 +1,44 @@ +FROM docker.io/library/ubuntu:22.04 as base +ENV LLVM_SYSROOT=/opt/llvm + +FROM base as stage1-toolchain +ENV LLVM_VERSION=17.0.6 + +RUN apt-get update && \ + apt-get install -y \ + wget \ + gcc \ + g++ \ + cmake \ + ninja-build \ + python3 \ + git \ + curl + +RUN curl -O -L https://github.com/llvm/llvm-project/archive/refs/tags/llvmorg-$LLVM_VERSION.tar.gz && tar -xf llvmorg-$LLVM_VERSION.tar.gz + +WORKDIR /llvm-project-llvmorg-$LLVM_VERSION + +COPY bootstrap.patch / + +# TODO(boomanaiden154): Remove the patch pulled from a LLVM PR once we bump +# the toolchain to version 18 and the patch is in-tree. +# TODO(boomanaiden154): Remove the bootstrap patch once we unsplit the build +# and no longer need to explicitly build the stage2 dependencies. +RUN curl https://github.com/llvm/llvm-project/commit/dd0356d741aefa25ece973d6cc4b55dcb73b84b4.patch | patch -p1 && cat /bootstrap.patch | patch -p1 + +RUN mkdir build + +RUN cmake -B ./build -G Ninja ./llvm \ + -C ./clang/cmake/caches/BOLT-PGO.cmake \ + -DBOOTSTRAP_LLVM_ENABLE_LLD=ON \ + -DBOOTSTRAP_BOOTSTRAP_LLVM_ENABLE_LLD=ON \ + -DPGO_INSTRUMENT_LTO=Thin \ + -DLLVM_ENABLE_RUNTIMES="compiler-rt" \ + -DCMAKE_INSTALL_PREFIX="$LLVM_SYSROOT" \ + -DLLVM_ENABLE_PROJECTS="bolt;clang;lld;clang-tools-extra" \ + -DLLVM_DISTRIBUTION_COMPONENTS="lld;compiler-rt;clang-format" \ + -DCLANG_DEFAULT_LINKER="lld" \ + -DBOOTSTRAP_CLANG_PGO_TRAINING_DATA_SOURCE_DIR=/llvm-project-llvmorg-$LLVM_VERSION/llvm + +RUN ninja -C ./build stage2-instrumented-clang stage2-instrumented-lld diff --git a/.github/workflows/containers/github-action-ci/stage2.Dockerfile b/.github/workflows/containers/github-action-ci/stage2.Dockerfile new file mode 100644 index 000000000000..e1a06cb68a58 --- /dev/null +++ b/.github/workflows/containers/github-action-ci/stage2.Dockerfile @@ -0,0 +1,27 @@ +FROM docker.io/library/ubuntu:22.04 as base +ENV LLVM_SYSROOT=/opt/llvm + +FROM stage1-toolchain AS stage2-toolchain + +RUN ninja -C ./build stage2-clang-bolt stage2-install-distribution && ninja -C ./build install-distribution && rm -rf ./build + +FROM base + +COPY --from=stage2-toolchain $LLVM_SYSROOT $LLVM_SYSROOT + +# Need to install curl for hendrikmuhs/ccache-action +# Need nodejs for some of the GitHub actions. +# Need perl-modules for clang analyzer tests. +RUN apt-get update && \ + apt-get install -y \ + binutils \ + cmake \ + curl \ + libstdc++-11-dev \ + ninja-build \ + nodejs \ + perl-modules \ + python3-psutil + +ENV LLVM_SYSROOT=$LLVM_SYSROOT +ENV PATH=${LLVM_SYSROOT}/bin:${PATH} diff --git a/.github/workflows/containers/github-action-ci/storage.conf b/.github/workflows/containers/github-action-ci/storage.conf new file mode 100644 index 000000000000..60f295ff1e96 --- /dev/null +++ b/.github/workflows/containers/github-action-ci/storage.conf @@ -0,0 +1,4 @@ +[storage] + driver = "overlay" + runroot = "/mnt/podman/container" + graphroot = "/mnt/podman/image" -- GitLab From 5953532615595918d006ace2ad83fe33d1cd3915 Mon Sep 17 00:00:00 2001 From: Jason Molenda Date: Mon, 5 Feb 2024 18:45:01 -0800 Subject: [PATCH 019/266] [lldb] Add QSupported key to report watchpoint types supported (#80376) debugserver on arm64 devices can manage both Byte Address Select watchpoints (1-8 bytes) and MASK watchpoints (8 bytes-2 gigabytes). This adds a SupportedWatchpointTypes key to the QSupported response from debugserver with a list of these, so lldb can take full advantage of them when creating larger regions with a single hardware watchpoint. Also add documentation for this, and two other lldb extensions, to the lldb-gdb-remote.txt documentation. Re-enable TestLargeWatchpoint.py on Darwin systems when testing with the in-tree built debugserver. I can remove the "in-tree built debugserver" in the future when this new key is handled by an Xcode debugserver. --- lldb/docs/lldb-gdb-remote.txt | 56 ++++++++++++++++--- .../lldb/Breakpoint/WatchpointAlgorithms.h | 4 +- lldb/include/lldb/lldb-enumerations.h | 26 --------- lldb/include/lldb/lldb-private-enumerations.h | 27 +++++++++ .../tools/lldb-server/gdbremote_testcase.py | 2 + .../Breakpoint/WatchpointAlgorithms.cpp | 3 +- .../GDBRemoteCommunicationClient.cpp | 17 ++++++ .../gdb-remote/GDBRemoteCommunicationClient.h | 4 ++ .../Process/gdb-remote/ProcessGDBRemote.cpp | 11 +--- .../large-watchpoint/TestLargeWatchpoint.py | 5 -- lldb/tools/debugserver/source/RNBRemote.cpp | 30 +++++----- 11 files changed, 118 insertions(+), 67 deletions(-) diff --git a/lldb/docs/lldb-gdb-remote.txt b/lldb/docs/lldb-gdb-remote.txt index 58269e4c2b68..76ac3f28d73b 100644 --- a/lldb/docs/lldb-gdb-remote.txt +++ b/lldb/docs/lldb-gdb-remote.txt @@ -38,7 +38,45 @@ read packet: + read packet: $OK#9a send packet: + +//---------------------------------------------------------------------- +// "QSupported" +// +// BRIEF +// Query the GDB remote server for features it supports +// +// PRIORITY TO IMPLEMENT +// Optional. +//---------------------------------------------------------------------- + +QSupported is a standard GDB Remote Serial Protocol packet, but +there are several additions to the response that lldb can parse. +They are not all listed here. + +An example exchange: + +send packet: qSupported:xmlRegisters=i386,arm,mips,arc;multiprocess+;fork-events+;vfork-events+ + +read packet: qXfer:features:read+;PacketSize=20000;qEcho+;native-signals+;SupportedCompressions=lzfse,zlib-deflate,lz4,lzma;SupportedWatchpointTypes=aarch64-mask,aarch64-bas; + +In the example above, three lldb extensions are shown: + PacketSize=20000 + The base 16 maximum packet size that the stub can handle. + SupportedCompressions= + A list of compression types that the stub can use to compress packets + when the QEnableCompression packet is used to request one of them. + SupportedWatchpointTypes= + A list of watchpoint types that this stub can manage. + Currently defined names are: + x86_64 64-bit x86-64 watchpoints + (1, 2, 4, 8 byte watchpoints aligned to those amounts) + aarch64-bas AArch64 Byte Address Select watchpoints + (any number of contiguous bytes within a doubleword) + aarch64-mask AArch64 MASK watchpoints + (any power-of-2 region of memory from 8 to 2GB, aligned) + If nothing is specified, lldb will default to sending power-of-2 + watchpoints, up to a pointer size, `sizeof(void*)`, a reasonable + baseline assumption. //---------------------------------------------------------------------- // "A" - launch args packet @@ -594,7 +632,7 @@ read packet: /E;AAAAAAAAA With LLDB, for register information, remote GDB servers can add support for the "qRegisterInfoN" packet where "N" is a zero based -base16 register number that must start at zero and increase by one +base 16 register number that must start at zero and increase by one for each register that is supported. The response is done in typical GDB remote fashion where a series of "KEY:VALUE;" pairs are returned. An example for the x86_64 registers is included below: @@ -1053,7 +1091,7 @@ Suggested key names: // 64-bit slices so it may be impossible to know until you're attached to a real // process to know what you're working with. // -// All numeric fields return base-16 numbers without any "0x" prefix. +// All numeric fields return base 16 numbers without any "0x" prefix. //---------------------------------------------------------------------- An i386 process: @@ -1085,7 +1123,7 @@ main-binary-uuid: is the UUID of a firmware type binary that the gdb stub knows main-binary-address: is the load address of the firmware type binary main-binary-slide: is the slide of the firmware type binary, if address isn't known -binary-addresses: A comma-separated list of binary load addresses base16. +binary-addresses: A comma-separated list of binary load addresses base 16. lldb will parse the binaries in memory to get UUIDs, then try to find the binaries & debug info by UUID. Intended for use with a small number of firmware type binaries where the @@ -1302,7 +1340,7 @@ tuples to return are: dirty-pages:[][,#00 // -// $C:#00 +// $C:#00 // // Where "#00" is the actual checksum value if noack mode is not enabled. The checksum // value is for the "N" or -// "C:" bytes in the packet. +// "C:" bytes in the packet. // -// The size of the uncompressed payload in base10 is provided because it will simplify +// The size of the uncompressed payload in base 10 is provided because it will simplify // decompression if the final buffer size needed is known ahead of time. // // Compression on low-latency connections is unlikely to be an improvement. Particularly diff --git a/lldb/include/lldb/Breakpoint/WatchpointAlgorithms.h b/lldb/include/lldb/Breakpoint/WatchpointAlgorithms.h index a9ec070bbcfe..7d6d9f442b38 100644 --- a/lldb/include/lldb/Breakpoint/WatchpointAlgorithms.h +++ b/lldb/include/lldb/Breakpoint/WatchpointAlgorithms.h @@ -11,7 +11,7 @@ #include "lldb/Breakpoint/WatchpointResource.h" #include "lldb/Utility/ArchSpec.h" -#include "lldb/lldb-public.h" +#include "lldb/lldb-private.h" #include @@ -58,7 +58,7 @@ public: /// watchpoint cannot be set. static std::vector AtomizeWatchpointRequest( lldb::addr_t addr, size_t size, bool read, bool write, - lldb::WatchpointHardwareFeature supported_features, ArchSpec &arch); + WatchpointHardwareFeature supported_features, ArchSpec &arch); protected: struct Region { diff --git a/lldb/include/lldb/lldb-enumerations.h b/lldb/include/lldb/lldb-enumerations.h index 50cbccba4d7c..392d333c23a4 100644 --- a/lldb/include/lldb/lldb-enumerations.h +++ b/lldb/include/lldb/lldb-enumerations.h @@ -448,32 +448,6 @@ enum WatchpointWriteType { eWatchpointWriteTypeOnModify }; -/// The hardware and native stub capabilities for a given target, -/// for translating a user's watchpoint request into hardware -/// capable watchpoint resources. -FLAGS_ENUM(WatchpointHardwareFeature){ - /// lldb will fall back to a default that assumes the target - /// can watch up to pointer-size power-of-2 regions, aligned to - /// power-of-2. - eWatchpointHardwareFeatureUnknown = (1u << 0), - - /// Intel systems can watch 1, 2, 4, or 8 bytes (in 64-bit targets), - /// aligned naturally. - eWatchpointHardwareX86 = (1u << 1), - - /// ARM systems with Byte Address Select watchpoints - /// can watch any consecutive series of bytes up to the - /// size of a pointer (4 or 8 bytes), at a pointer-size - /// alignment. - eWatchpointHardwareArmBAS = (1u << 2), - - /// ARM systems with MASK watchpoints can watch any power-of-2 - /// sized region from 8 bytes to 2 gigabytes, aligned to that - /// same power-of-2 alignment. - eWatchpointHardwareArmMASK = (1u << 3), -}; -LLDB_MARK_AS_BITMASK_ENUM(WatchpointHardwareFeature) - /// Programming language type. /// /// These enumerations use the same language enumerations as the DWARF diff --git a/lldb/include/lldb/lldb-private-enumerations.h b/lldb/include/lldb/lldb-private-enumerations.h index 5f1597200a83..9e8ab56305be 100644 --- a/lldb/include/lldb/lldb-private-enumerations.h +++ b/lldb/include/lldb/lldb-private-enumerations.h @@ -9,6 +9,7 @@ #ifndef LLDB_LLDB_PRIVATE_ENUMERATIONS_H #define LLDB_LLDB_PRIVATE_ENUMERATIONS_H +#include "lldb/lldb-enumerations.h" #include "llvm/ADT/StringRef.h" #include "llvm/Support/FormatProviders.h" #include "llvm/Support/raw_ostream.h" @@ -282,4 +283,30 @@ enum InterruptionControl : bool { DoNotAllowInterruption = false, }; +/// The hardware and native stub capabilities for a given target, +/// for translating a user's watchpoint request into hardware +/// capable watchpoint resources. +FLAGS_ENUM(WatchpointHardwareFeature){ + /// lldb will fall back to a default that assumes the target + /// can watch up to pointer-size power-of-2 regions, aligned to + /// power-of-2. + eWatchpointHardwareFeatureUnknown = (1u << 0), + + /// Intel systems can watch 1, 2, 4, or 8 bytes (in 64-bit targets), + /// aligned naturally. + eWatchpointHardwareX86 = (1u << 1), + + /// ARM systems with Byte Address Select watchpoints + /// can watch any consecutive series of bytes up to the + /// size of a pointer (4 or 8 bytes), at a pointer-size + /// alignment. + eWatchpointHardwareArmBAS = (1u << 2), + + /// ARM systems with MASK watchpoints can watch any power-of-2 + /// sized region from 8 bytes to 2 gigabytes, aligned to that + /// same power-of-2 alignment. + eWatchpointHardwareArmMASK = (1u << 3), +}; +LLDB_MARK_AS_BITMASK_ENUM(WatchpointHardwareFeature) + #endif // LLDB_LLDB_PRIVATE_ENUMERATIONS_H diff --git a/lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py b/lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py index 3341b6e54a3b..75522158b322 100644 --- a/lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py +++ b/lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py @@ -921,6 +921,8 @@ class GdbRemoteTestCaseBase(Base, metaclass=GdbRemoteTestCaseFactory): "qSaveCore", "native-signals", "QNonStop", + "SupportedWatchpointTypes", + "SupportedCompressions", ] def parse_qSupported_response(self, context): diff --git a/lldb/source/Breakpoint/WatchpointAlgorithms.cpp b/lldb/source/Breakpoint/WatchpointAlgorithms.cpp index 94f1dfffbf29..3caf29b04317 100644 --- a/lldb/source/Breakpoint/WatchpointAlgorithms.cpp +++ b/lldb/source/Breakpoint/WatchpointAlgorithms.cpp @@ -27,8 +27,7 @@ WatchpointAlgorithms::AtomizeWatchpointRequest( std::vector entries; - if (supported_features & - WatchpointHardwareFeature::eWatchpointHardwareArmMASK) { + if (supported_features & eWatchpointHardwareArmMASK) { entries = PowerOf2Watchpoints(addr, size, /*min_byte_size*/ 1, diff --git a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp index 7bb449841851..6f8aa2622899 100644 --- a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp +++ b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp @@ -403,6 +403,18 @@ void GDBRemoteCommunicationClient::GetRemoteQSupported() { x.split(compressions, ','); if (!compressions.empty()) MaybeEnableCompression(compressions); + } else if (x.consume_front("SupportedWatchpointTypes=")) { + llvm::SmallVector watchpoint_types; + x.split(watchpoint_types, ','); + m_watchpoint_types = eWatchpointHardwareFeatureUnknown; + for (auto wp_type : watchpoint_types) { + if (wp_type == "x86_64") + m_watchpoint_types |= eWatchpointHardwareX86; + if (wp_type == "aarch64-mask") + m_watchpoint_types |= eWatchpointHardwareArmMASK; + if (wp_type == "aarch64-bas") + m_watchpoint_types |= eWatchpointHardwareArmBAS; + } } else if (x.consume_front("PacketSize=")) { StringExtractorGDBRemote packet_response(x); m_max_packet_size = @@ -1828,6 +1840,11 @@ std::optional GDBRemoteCommunicationClient::GetWatchpointSlotCount() { return num; } +WatchpointHardwareFeature +GDBRemoteCommunicationClient::GetSupportedWatchpointTypes() { + return m_watchpoint_types; +} + std::optional GDBRemoteCommunicationClient::GetWatchpointReportedAfter() { if (m_qHostInfo_is_valid == eLazyBoolCalculate) GetHostInfo(); diff --git a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h index 866b0773d86d..bd2d3e232b46 100644 --- a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h +++ b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h @@ -199,6 +199,8 @@ public: std::optional GetWatchpointReportedAfter(); + WatchpointHardwareFeature GetSupportedWatchpointTypes(); + const ArchSpec &GetHostArchitecture(); std::chrono::seconds GetHostDefaultPacketTimeout(); @@ -581,6 +583,8 @@ protected: lldb::tid_t m_curr_tid_run = LLDB_INVALID_THREAD_ID; uint32_t m_num_supported_hardware_watchpoints = 0; + WatchpointHardwareFeature m_watchpoint_types = + eWatchpointHardwareFeatureUnknown; uint32_t m_low_mem_addressing_bits = 0; uint32_t m_high_mem_addressing_bits = 0; diff --git a/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp b/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp index 4e3447e767c3..629b191f3117 100644 --- a/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp +++ b/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp @@ -3156,16 +3156,7 @@ Status ProcessGDBRemote::EnableWatchpoint(WatchpointSP wp_sp, bool notify) { ArchSpec target_arch = GetTarget().GetArchitecture(); WatchpointHardwareFeature supported_features = - eWatchpointHardwareFeatureUnknown; - - // LWP_TODO: enable MASK watchpoint for arm64 debugserver - // when it reports that it supports them. - if (target_arch.GetTriple().getOS() == llvm::Triple::MacOSX && - target_arch.GetTriple().getArch() == llvm::Triple::aarch64) { -#if 0 - supported_features |= eWatchpointHardwareArmMASK; -#endif - } + m_gdb_comm.GetSupportedWatchpointTypes(); std::vector resources = WatchpointAlgorithms::AtomizeWatchpointRequest( diff --git a/lldb/test/API/functionalities/watchpoint/large-watchpoint/TestLargeWatchpoint.py b/lldb/test/API/functionalities/watchpoint/large-watchpoint/TestLargeWatchpoint.py index f7ceb47c0b61..c5e161497e62 100644 --- a/lldb/test/API/functionalities/watchpoint/large-watchpoint/TestLargeWatchpoint.py +++ b/lldb/test/API/functionalities/watchpoint/large-watchpoint/TestLargeWatchpoint.py @@ -25,11 +25,6 @@ class UnalignedWatchpointTestCase(TestBase): @skipIf(archs=no_match(["arm64", "arm64e", "aarch64"])) @skipUnlessDarwin - # LWP_TODO: until debugserver advertises that it supports - # MASK watchpoints, this test can't be enabled, lldb won't - # try to send watchpoints larger than 8 bytes. - @skipIfDarwin - # debugserver only gained the ability to watch larger regions # with this patch. @skipIfOutOfTreeDebugserver diff --git a/lldb/tools/debugserver/source/RNBRemote.cpp b/lldb/tools/debugserver/source/RNBRemote.cpp index 224ed033fc42..20384920823d 100644 --- a/lldb/tools/debugserver/source/RNBRemote.cpp +++ b/lldb/tools/debugserver/source/RNBRemote.cpp @@ -3557,10 +3557,10 @@ static bool GetProcessNameFrom_vAttach(const char *&p, rnb_err_t RNBRemote::HandlePacket_qSupported(const char *p) { uint32_t max_packet_size = 128 * 1024; // 128KBytes is a reasonable max packet // size--debugger can always use less - char buf[256]; - snprintf(buf, sizeof(buf), - "qXfer:features:read+;PacketSize=%x;qEcho+;native-signals+", - max_packet_size); + std::stringstream reply; + reply << "qXfer:features:read+;PacketSize=" << std::hex << max_packet_size + << ";"; + reply << "qEcho+;native-signals+;"; bool enable_compression = false; (void)enable_compression; @@ -3574,15 +3574,19 @@ rnb_err_t RNBRemote::HandlePacket_qSupported(const char *p) { #endif if (enable_compression) { - strcat(buf, ";SupportedCompressions=lzfse,zlib-deflate,lz4,lzma;" - "DefaultCompressionMinSize="); - char numbuf[16]; - snprintf(numbuf, sizeof(numbuf), "%zu", m_compression_minsize); - numbuf[sizeof(numbuf) - 1] = '\0'; - strcat(buf, numbuf); - } - - return SendPacket(buf); + reply << "SupportedCompressions=lzfse,zlib-deflate,lz4,lzma;"; + reply << "DefaultCompressionMinSize=" << std::dec << m_compression_minsize + << ";"; + } + +#if (defined(__arm64__) || defined(__aarch64__)) + reply << "SupportedWatchpointTypes=aarch64-mask,aarch64-bas;"; +#endif +#if defined(__x86_64__) + reply << "SupportedWatchpointTypes=x86_64;"; +#endif + + return SendPacket(reply.str().c_str()); } static bool process_does_not_exist (nub_process_t pid) { -- GitLab From 87ff65b07c82337d99b0dc0ca562e394ecedc11b Mon Sep 17 00:00:00 2001 From: Jie Fu Date: Tue, 6 Feb 2024 10:44:52 +0800 Subject: [PATCH 020/266] [mlir][test] Fix -Wformat in sparse_tensor.c (NFC) llvm-project/mlir/test/CAPI/sparse_tensor.c:50:43: error: format specifies type 'unsigned long long' but the argument has type 'MlirSparseTensorLevelType' (aka 'unsigned long') [-Werror,-Wformat] fprintf(stderr, "level_type: %llu\n", lvlTypes[l]); ~~~~ ^~~~~~~~~~~ %lu 1 error generated. --- mlir/test/CAPI/sparse_tensor.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/mlir/test/CAPI/sparse_tensor.c b/mlir/test/CAPI/sparse_tensor.c index f5d43a2eccdc..2c6ad559f19d 100644 --- a/mlir/test/CAPI/sparse_tensor.c +++ b/mlir/test/CAPI/sparse_tensor.c @@ -14,6 +14,7 @@ #include "mlir-c/RegisterEverything.h" #include +#include #include #include #include @@ -47,7 +48,7 @@ static int testRoundtripEncoding(MlirContext ctx) { malloc(sizeof(MlirSparseTensorLevelType) * lvlRank); for (int l = 0; l < lvlRank; ++l) { lvlTypes[l] = mlirSparseTensorEncodingAttrGetLvlType(originalAttr, l); - fprintf(stderr, "level_type: %llu\n", lvlTypes[l]); + fprintf(stderr, "level_type: %" PRIu64 "\n", lvlTypes[l]); } // CHECK: posWidth: 32 int posWidth = mlirSparseTensorEncodingAttrGetPosWidth(originalAttr); -- GitLab From c1ac2cfac7f160107041758f458aaf1087f5cac2 Mon Sep 17 00:00:00 2001 From: "Oleksandr \"Alex\" Zinenko" Date: Tue, 6 Feb 2024 03:59:41 +0100 Subject: [PATCH 021/266] Use a markdown list in Affine dialect docs --- mlir/docs/Dialects/Affine.md | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/mlir/docs/Dialects/Affine.md b/mlir/docs/Dialects/Affine.md index 8bc4dcfdc7eb..f34a9b1c1a86 100644 --- a/mlir/docs/Dialects/Affine.md +++ b/mlir/docs/Dialects/Affine.md @@ -61,17 +61,22 @@ Example: The affine dialect imposes certain restrictions on dimension and symbolic identifiers to enable powerful analysis and transformation. An SSA value's use -can be bound to a symbolic identifier if that SSA value is either 1. a region -argument for an op with trait `AffineScope` (eg. `FuncOp`), 2. a value defined -at the top level of an `AffineScope` op (i.e., immediately enclosed by the -latter), 3. a value that dominates the `AffineScope` op enclosing the value's -use, 4. the result of a -constant operation, 5. the result of an +can be bound to a symbolic identifier if that SSA value is either: + +1. a region argument for an op with trait `AffineScope` (eg. `FuncOp`), +2. a value defined at the top level of an `AffineScope` op (i.e., +immediately enclosed by the latter), +3. a value that dominates the `AffineScope` op enclosing the value's +use, +4. the result of a constant operation, +5. the result of an [`affine.apply` operation](#affineapply-mliraffineapplyop) that recursively takes as -arguments any valid symbolic identifiers, or 6. the result of a +arguments any valid symbolic identifiers, or +6. the result of a [`dim` operation](MemRef.md/#memrefdim-mlirmemrefdimop) on either a memref that is an argument to a `AffineScope` op or a memref where the corresponding dimension is either static or a dynamic one in turn bound to a valid symbol. + *Note:* if the use of an SSA value is not contained in any op with the `AffineScope` trait, only the rules 4-6 can be applied. -- GitLab From 9a5fb74fd162da70609fe5f81864d01cdc776df1 Mon Sep 17 00:00:00 2001 From: Artem Tyurin Date: Tue, 6 Feb 2024 04:10:39 +0100 Subject: [PATCH 022/266] [mlir][spirv] Handle a missing case when inlining spirv.ReturnValue (#80733) Fixes https://github.com/llvm/llvm-project/issues/73285. --- mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp | 4 +++- .../Dialect/SPIRV/Transforms/inlining.mlir | 22 +++++++++++++++++++ 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp b/mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp index db26fa81790d..e914f46bdef6 100644 --- a/mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp +++ b/mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp @@ -95,7 +95,9 @@ struct SPIRVInlinerInterface : public DialectInlinerInterface { OpBuilder(op).create(op->getLoc(), newDest); op->erase(); } else if (auto retValOp = dyn_cast(op)) { - llvm_unreachable("unimplemented spirv.ReturnValue in inliner"); + OpBuilder(op).create(retValOp->getLoc(), newDest, + retValOp->getOperands()); + op->erase(); } } diff --git a/mlir/test/Dialect/SPIRV/Transforms/inlining.mlir b/mlir/test/Dialect/SPIRV/Transforms/inlining.mlir index 8d663b4edc45..3aadb19ec158 100644 --- a/mlir/test/Dialect/SPIRV/Transforms/inlining.mlir +++ b/mlir/test/Dialect/SPIRV/Transforms/inlining.mlir @@ -224,5 +224,27 @@ spirv.module Logical GLSL450 { spirv.ExecutionMode @inline_into_selection_region "LocalSize", 32, 1, 1 } +// ----- + +spirv.module Logical GLSL450 { + // CHECK-LABEL: @foo + spirv.func @foo(%arg0: i32) -> i32 "None" { + // CHECK-NOT: spirv.FunctionCall + // CHECK-NEXT: spirv.Constant 1 + %res = spirv.FunctionCall @bar(%arg0) : (i32) -> i32 + spirv.ReturnValue %res : i32 + } + + spirv.func @bar(%arg1: i32) -> i32 "None" attributes {sym_visibility = "private"} { + %cst1_i32 = spirv.Constant 1 : i32 + %0 = spirv.IEqual %arg1, %cst1_i32 : i32 + spirv.BranchConditional %0, ^bb1(%cst1_i32 : i32), ^bb2 + ^bb1(%1: i32): + spirv.ReturnValue %1 : i32 + ^bb2: + spirv.ReturnValue %cst1_i32 : i32 + } +} + // TODO: Add tests for inlining structured control flow into // structured control flow. -- GitLab From d193ac4f7180d8242c25d941cf3ff8a150538af6 Mon Sep 17 00:00:00 2001 From: Han-Chung Wang Date: Mon, 5 Feb 2024 20:03:24 -0800 Subject: [PATCH 023/266] [mlir][vector] Drop inner unit dims for xWrite on dynamic shapes. (#80725) This is part of https://github.com/llvm/llvm-project/commit/66347e516e22f9159b86024071fb92f364ac4418 The regression in downstream projects is about transfer_read patterns, which needs more investigation. Add the support for transfer_write for now. --- .../Vector/Transforms/VectorTransforms.cpp | 15 +++++++------ ...tor-transfer-collapse-inner-most-dims.mlir | 21 +++++++++++++++++++ 2 files changed, 30 insertions(+), 6 deletions(-) diff --git a/mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp b/mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp index 12aa11e9e33f..4034dc40685a 100644 --- a/mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp +++ b/mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp @@ -1318,7 +1318,7 @@ class DropInnerMostUnitDimsTransferWrite return failure(); auto srcType = dyn_cast(writeOp.getSource().getType()); - if (!srcType || !srcType.hasStaticShape()) + if (!srcType) return failure(); if (!writeOp.getPermutationMap().isMinorIdentity()) @@ -1341,20 +1341,23 @@ class DropInnerMostUnitDimsTransferWrite VectorType::get(targetType.getShape().drop_back(dimsToDrop), targetType.getElementType()); + Location loc = writeOp.getLoc(); + SmallVector sizes = + memref::getMixedSizes(rewriter, loc, writeOp.getSource()); + SmallVector offsets(srcType.getRank(), + rewriter.getIndexAttr(0)); + SmallVector strides(srcType.getRank(), + rewriter.getIndexAttr(1)); MemRefType resultMemrefType = getMemRefTypeWithDroppingInnerDims(rewriter, srcType, dimsToDrop); - SmallVector offsets(srcType.getRank(), 0); - SmallVector strides(srcType.getRank(), 1); ArrayAttr inBoundsAttr = writeOp.getInBounds() ? rewriter.getArrayAttr( writeOp.getInBoundsAttr().getValue().drop_back(dimsToDrop)) : ArrayAttr(); - Location loc = writeOp.getLoc(); Value rankedReducedView = rewriter.create( - loc, resultMemrefType, writeOp.getSource(), offsets, srcType.getShape(), - strides); + loc, resultMemrefType, writeOp.getSource(), offsets, sizes, strides); auto permMap = getTransferMinorIdentityMap( cast(rankedReducedView.getType()), resultTargetVecType); diff --git a/mlir/test/Dialect/Vector/vector-transfer-collapse-inner-most-dims.mlir b/mlir/test/Dialect/Vector/vector-transfer-collapse-inner-most-dims.mlir index d6d69c8af885..750879df129b 100644 --- a/mlir/test/Dialect/Vector/vector-transfer-collapse-inner-most-dims.mlir +++ b/mlir/test/Dialect/Vector/vector-transfer-collapse-inner-most-dims.mlir @@ -119,6 +119,27 @@ func.func @drop_inner_most_dim_for_transfer_write(%arg0: memref<1x512x16x1xf32, // ----- +func.func @outer_dyn_drop_inner_most_dim_for_transfer_write(%arg0: memref>, %arg1: vector<1x16x16x1xf32>, %arg2: index) { + %c0 = arith.constant 0 : index + vector.transfer_write %arg1, %arg0[%arg2, %c0, %c0, %c0] + {in_bounds = [true, true, true, true]} + : vector<1x16x16x1xf32>, memref> + return +} +// CHECK: func.func @outer_dyn_drop_inner_most_dim_for_transfer_write +// CHECK-SAME: %[[DEST:[a-zA-Z0-9]+]] +// CHECK-SAME: %[[VEC:[a-zA-Z0-9]+]] +// CHECK-SAME: %[[IDX:[a-zA-Z0-9]+]] +// CHECK-DAG: %[[C0:.+]] = arith.constant 0 : index +// CHECK-DAG: %[[D0:.+]] = memref.dim %[[SRC]], %[[C0]] +// CHECK: %[[SUBVIEW:.+]] = memref.subview %[[DEST]][0, 0, 0, 0] [%[[D0]], 512, 16, 1] +// CHECK-SAME: memref> to memref> +// CHECK: %[[CAST:.+]] = vector.shape_cast %[[VEC]] : vector<1x16x16x1xf32> to vector<1x16x16xf32> +// CHECK: vector.transfer_write %[[CAST]], %[[SUBVIEW]] +// CHECK-SAME: [%[[IDX]], %[[C0]], %[[C0]]] + +// ----- + func.func @non_unit_strides(%arg0: memref<512x16x1xf32, strided<[8192, 16, 4], offset: ?>>, %arg1: vector<16x16x1xf32>, %arg2: index) { %c0 = arith.constant 0 : index vector.transfer_write %arg1, %arg0[%arg2, %c0, %c0] -- GitLab From 942cb2427a0e19f63b2f5b7da3d3fa6a594df3fe Mon Sep 17 00:00:00 2001 From: Arthur Eubanks Date: Mon, 5 Feb 2024 21:17:09 -0700 Subject: [PATCH 024/266] [CodeGen][NewPM] Consolidate PASS_NAME and CONSTRUCTOR in MachinePassRegistry.def (#80779) This matches the optimization pipeline's PassRegistry.def. I ran into a bug where CONSTRUCTOR wasn't always being used (in PassBuilder::registerMachineFunctionAnalyses()). Make DUMMY_* just accept a pass name, there's no point in having proper constructors if the generated dummy class has a templated constructor accepting arbitrary arguments. Remove unused getPassNameFromLegacyName() as it was using this but for no purpose. Remove DUMMY_MACHINE_FUNCTION_ANALYSIS, we can just add those as we port them. This for some reason exposed missing mock calls in existing unittests. --- llvm/include/llvm/Passes/CodeGenPassBuilder.h | 77 +---- .../llvm/Passes/MachinePassRegistry.def | 317 ++++++++---------- llvm/include/llvm/Target/TargetMachine.h | 5 - llvm/lib/Passes/CodeGenPassBuilder.cpp | 2 +- llvm/lib/Passes/PassBuilder.cpp | 29 +- .../MIR/PassBuilderCallbacksTest.cpp | 6 + 6 files changed, 172 insertions(+), 264 deletions(-) diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index 2c8073ad551b..40cc0c046531 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -78,14 +78,14 @@ namespace llvm { // FIXME: Dummy target independent passes definitions that have not yet been // ported to new pass manager. Once they do, remove these. -#define DUMMY_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ +#define DUMMY_FUNCTION_PASS(NAME, PASS_NAME) \ struct PASS_NAME : public PassInfoMixin { \ template PASS_NAME(Ts &&...) {} \ PreservedAnalyses run(Function &, FunctionAnalysisManager &) { \ return PreservedAnalyses::all(); \ } \ }; -#define DUMMY_MACHINE_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ +#define DUMMY_MACHINE_MODULE_PASS(NAME, PASS_NAME) \ struct PASS_NAME : public MachinePassInfoMixin { \ template PASS_NAME(Ts &&...) {} \ Error run(Module &, MachineFunctionAnalysisManager &) { \ @@ -96,7 +96,7 @@ namespace llvm { llvm_unreachable("this api is to make new PM api happy"); \ } \ }; -#define DUMMY_MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ +#define DUMMY_MACHINE_FUNCTION_PASS(NAME, PASS_NAME) \ struct PASS_NAME : public MachinePassInfoMixin { \ template PASS_NAME(Ts &&...) {} \ PreservedAnalyses run(MachineFunction &, \ @@ -104,17 +104,6 @@ namespace llvm { return PreservedAnalyses::all(); \ } \ }; -#define DUMMY_MACHINE_FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \ - struct PASS_NAME : public AnalysisInfoMixin { \ - template PASS_NAME(Ts &&...) {} \ - using Result = struct {}; \ - template \ - Result run(IRUnitT &, AnalysisManagerT &, ExtraArgTs &&...) { \ - return {}; \ - } \ - static AnalysisKey Key; \ - }; #include "llvm/Passes/MachinePassRegistry.def" /// This class provides access to building LLVM's passes. @@ -150,7 +139,6 @@ public: void registerModuleAnalyses(ModuleAnalysisManager &) const; void registerFunctionAnalyses(FunctionAnalysisManager &) const; void registerMachineFunctionAnalyses(MachineFunctionAnalysisManager &) const; - std::pair getPassNameFromLegacyName(StringRef) const; void registerAnalyses(MachineFunctionAnalysisManager &MFAM) const { registerModuleAnalyses(*MFAM.MAM); @@ -608,8 +596,8 @@ static inline AAManager registerAAAnalyses() { template void CodeGenPassBuilder::registerModuleAnalyses( ModuleAnalysisManager &MAM) const { -#define MODULE_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \ - MAM.registerPass([&] { return PASS_NAME CONSTRUCTOR; }); +#define MODULE_ANALYSIS(NAME, CREATE_PASS) \ + MAM.registerPass([&] { return CREATE_PASS; }); #include "MachinePassRegistry.def" derived().registerTargetAnalysis(MAM); } @@ -619,8 +607,8 @@ void CodeGenPassBuilder::registerFunctionAnalyses( FunctionAnalysisManager &FAM) const { FAM.registerPass([this] { return registerAAAnalyses(); }); -#define FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \ - FAM.registerPass([&] { return PASS_NAME CONSTRUCTOR; }); +#define FUNCTION_ANALYSIS(NAME, CREATE_PASS) \ + FAM.registerPass([&] { return CREATE_PASS; }); #include "MachinePassRegistry.def" derived().registerTargetAnalysis(FAM); } @@ -628,59 +616,12 @@ void CodeGenPassBuilder::registerFunctionAnalyses( template void CodeGenPassBuilder::registerMachineFunctionAnalyses( MachineFunctionAnalysisManager &MFAM) const { -#define MACHINE_FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \ - MFAM.registerPass([&] { return PASS_NAME CONSTRUCTOR; }); +#define MACHINE_FUNCTION_ANALYSIS(NAME, CREATE_PASS) \ + MFAM.registerPass([&] { return CREATE_PASS; }); #include "MachinePassRegistry.def" derived().registerTargetAnalysis(MFAM); } -// FIXME: For new PM, use pass name directly in commandline seems good. -// Translate stringfied pass name to its old commandline name. Returns the -// matching legacy name and a boolean value indicating if the pass is a machine -// pass. -template -std::pair -CodeGenPassBuilder::getPassNameFromLegacyName(StringRef Name) const { - std::pair Ret; - if (Name.empty()) - return Ret; - -#define FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ - if (Name == NAME) \ - Ret = {#PASS_NAME, false}; -#define DUMMY_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ - if (Name == NAME) \ - Ret = {#PASS_NAME, false}; -#define MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ - if (Name == NAME) \ - Ret = {#PASS_NAME, false}; -#define DUMMY_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ - if (Name == NAME) \ - Ret = {#PASS_NAME, false}; -#define MACHINE_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ - if (Name == NAME) \ - Ret = {#PASS_NAME, true}; -#define DUMMY_MACHINE_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ - if (Name == NAME) \ - Ret = {#PASS_NAME, true}; -#define MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ - if (Name == NAME) \ - Ret = {#PASS_NAME, true}; -#define DUMMY_MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ - if (Name == NAME) \ - Ret = {#PASS_NAME, true}; -#include "llvm/Passes/MachinePassRegistry.def" - - if (Ret.first.empty()) - Ret = derived().getTargetPassNameFromLegacyName(Name); - - if (Ret.first.empty()) - report_fatal_error(Twine('\"') + Twine(Name) + - Twine("\" pass could not be found.")); - - return Ret; -} - template void CodeGenPassBuilder::addISelPasses(AddIRPass &addPass) const { derived().addGlobalMergePass(addPass); diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def index e311682a5619..5c3d2659fdfb 100644 --- a/llvm/include/llvm/Passes/MachinePassRegistry.def +++ b/llvm/include/llvm/Passes/MachinePassRegistry.def @@ -14,84 +14,82 @@ // NOTE: NO INCLUDE GUARD DESIRED! #ifndef MODULE_ANALYSIS -#define MODULE_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) +#define MODULE_ANALYSIS(NAME, CREATE_PASS) #endif -MODULE_ANALYSIS("collector-metadata", CollectorMetadataAnalysis, ()) -MODULE_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis, (PIC)) +MODULE_ANALYSIS("collector-metadata", CollectorMetadataAnalysis()) +MODULE_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis(PIC)) #undef MODULE_ANALYSIS #ifndef MODULE_PASS -#define MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) +#define MODULE_PASS(NAME, CREATE_PASS) #endif -MODULE_PASS("global-merge", GlobalMergePass, (TM, GlobalMergeOptions())) -MODULE_PASS("jmc-instrumenter", JMCInstrumenterPass, ()) -MODULE_PASS("lower-emutls", LowerEmuTLSPass, ()) -MODULE_PASS("pre-isel-intrinsic-lowering", PreISelIntrinsicLoweringPass, ()) -MODULE_PASS("shadow-stack-gc-lowering", ShadowStackGCLoweringPass, ()) +MODULE_PASS("global-merge", GlobalMergePass(TM, GlobalMergeOptions())) +MODULE_PASS("jmc-instrumenter", JMCInstrumenterPass()) +MODULE_PASS("lower-emutls", LowerEmuTLSPass()) +MODULE_PASS("pre-isel-intrinsic-lowering", PreISelIntrinsicLoweringPass()) +MODULE_PASS("shadow-stack-gc-lowering", ShadowStackGCLoweringPass()) #undef MODULE_PASS #ifndef FUNCTION_ANALYSIS -#define FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) +#define FUNCTION_ANALYSIS(NAME, CREATE_PASS) #endif -FUNCTION_ANALYSIS("gc-function", GCFunctionAnalysis, ()) -FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis, (PIC)) -FUNCTION_ANALYSIS("ssp-layout", SSPLayoutAnalysis, ()) -FUNCTION_ANALYSIS("target-ir", TargetIRAnalysis, - (std::move(TM.getTargetIRAnalysis()))) +FUNCTION_ANALYSIS("gc-function", GCFunctionAnalysis()) +FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis(PIC)) +FUNCTION_ANALYSIS("ssp-layout", SSPLayoutAnalysis()) +FUNCTION_ANALYSIS("target-ir", TargetIRAnalysis(std::move(TM.getTargetIRAnalysis()))) #undef FUNCTION_ANALYSIS #ifndef FUNCTION_PASS -#define FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) +#define FUNCTION_PASS(NAME, CREATE_PASS) #endif -FUNCTION_PASS("callbr-prepare", CallBrPreparePass, ()) -FUNCTION_PASS("cfguard", CFGuardPass, ()) -FUNCTION_PASS("codegenprepare", CodeGenPreparePass, (TM)) -FUNCTION_PASS("consthoist", ConstantHoistingPass, ()) -FUNCTION_PASS("dwarf-eh-prepare", DwarfEHPreparePass, (TM)) -FUNCTION_PASS("ee-instrument", EntryExitInstrumenterPass, (false)) -FUNCTION_PASS("expand-large-div-rem", ExpandLargeDivRemPass, (TM)) -FUNCTION_PASS("expand-large-fp-convert", ExpandLargeFpConvertPass, (TM)) -FUNCTION_PASS("expand-memcmp", ExpandMemCmpPass, (TM)) -FUNCTION_PASS("expand-reductions", ExpandReductionsPass, ()) -FUNCTION_PASS("expandvp", ExpandVectorPredicationPass, ()) -FUNCTION_PASS("gc-lowering", GCLoweringPass, ()) -FUNCTION_PASS("indirectbr-expand", IndirectBrExpandPass, (TM)) -FUNCTION_PASS("interleaved-access", InterleavedAccessPass, (TM)) -FUNCTION_PASS("interleaved-load-combine", InterleavedLoadCombinePass, (TM)) -FUNCTION_PASS("lower-constant-intrinsics", LowerConstantIntrinsicsPass, ()) -FUNCTION_PASS("lower-invoke", LowerInvokePass, ()) -FUNCTION_PASS("mergeicmps", MergeICmpsPass, ()) -FUNCTION_PASS("partially-inline-libcalls", PartiallyInlineLibCallsPass, ()) -FUNCTION_PASS("post-inline-ee-instrument", EntryExitInstrumenterPass, (true)) -FUNCTION_PASS("replace-with-veclib", ReplaceWithVeclib, ()) -FUNCTION_PASS("safe-stack", SafeStackPass, (TM)) -FUNCTION_PASS("scalarize-masked-mem-intrin", ScalarizeMaskedMemIntrinPass, ()) -FUNCTION_PASS("select-optimize", SelectOptimizePass, (TM)) -FUNCTION_PASS("sjlj-eh-prepare", SjLjEHPreparePass, (TM)) -FUNCTION_PASS("stack-protector", StackProtectorPass, (TM)) -FUNCTION_PASS("tlshoist", TLSVariableHoistPass, ()) -FUNCTION_PASS("unreachableblockelim", UnreachableBlockElimPass, ()) -FUNCTION_PASS("verify", VerifierPass, ()) -FUNCTION_PASS("wasm-eh-prepare", WasmEHPreparePass, ()) -FUNCTION_PASS("win-eh-prepare", WinEHPreparePass, ()) +FUNCTION_PASS("callbr-prepare", CallBrPreparePass()) +FUNCTION_PASS("cfguard", CFGuardPass()) +FUNCTION_PASS("codegenprepare", CodeGenPreparePass(TM)) +FUNCTION_PASS("consthoist", ConstantHoistingPass()) +FUNCTION_PASS("dwarf-eh-prepare", DwarfEHPreparePass(TM)) +FUNCTION_PASS("ee-instrument", EntryExitInstrumenterPass(false)) +FUNCTION_PASS("expand-large-div-rem", ExpandLargeDivRemPass(TM)) +FUNCTION_PASS("expand-large-fp-convert", ExpandLargeFpConvertPass(TM)) +FUNCTION_PASS("expand-memcmp", ExpandMemCmpPass(TM)) +FUNCTION_PASS("expand-reductions", ExpandReductionsPass()) +FUNCTION_PASS("expandvp", ExpandVectorPredicationPass()) +FUNCTION_PASS("gc-lowering", GCLoweringPass()) +FUNCTION_PASS("indirectbr-expand", IndirectBrExpandPass(TM)) +FUNCTION_PASS("interleaved-access", InterleavedAccessPass(TM)) +FUNCTION_PASS("interleaved-load-combine", InterleavedLoadCombinePass(TM)) +FUNCTION_PASS("lower-constant-intrinsics", LowerConstantIntrinsicsPass()) +FUNCTION_PASS("lower-invoke", LowerInvokePass()) +FUNCTION_PASS("mergeicmps", MergeICmpsPass()) +FUNCTION_PASS("partially-inline-libcalls", PartiallyInlineLibCallsPass()) +FUNCTION_PASS("post-inline-ee-instrument", EntryExitInstrumenterPass(true)) +FUNCTION_PASS("replace-with-veclib", ReplaceWithVeclib()) +FUNCTION_PASS("safe-stack", SafeStackPass(TM)) +FUNCTION_PASS("scalarize-masked-mem-intrin", ScalarizeMaskedMemIntrinPass()) +FUNCTION_PASS("select-optimize", SelectOptimizePass(TM)) +FUNCTION_PASS("sjlj-eh-prepare", SjLjEHPreparePass(TM)) +FUNCTION_PASS("stack-protector", StackProtectorPass(TM)) +FUNCTION_PASS("tlshoist", TLSVariableHoistPass()) +FUNCTION_PASS("unreachableblockelim", UnreachableBlockElimPass()) +FUNCTION_PASS("verify", VerifierPass()) +FUNCTION_PASS("wasm-eh-prepare", WasmEHPreparePass()) +FUNCTION_PASS("win-eh-prepare", WinEHPreparePass()) #undef FUNCTION_PASS #ifndef LOOP_PASS -#define LOOP_PASS(NAME, PASS_NAME, CONSTRUCTOR) +#define LOOP_PASS(NAME, CREATE_PASS) #endif -LOOP_PASS("loop-reduce", LoopStrengthReducePass, ()) +LOOP_PASS("loop-reduce", LoopStrengthReducePass()) #undef LOOP_PASS #ifndef MACHINE_MODULE_PASS -#define MACHINE_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) +#define MACHINE_MODULE_PASS(NAME, CREATE_PASS) #endif #undef MACHINE_MODULE_PASS #ifndef MACHINE_FUNCTION_ANALYSIS -#define MACHINE_FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) +#define MACHINE_FUNCTION_ANALYSIS(NAME, CREATE_PASS) #endif -MACHINE_FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis, - (PIC)) +MACHINE_FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis(PIC)) // LiveVariables currently requires pure SSA form. // FIXME: Once TwoAddressInstruction pass no longer uses kill flags, // LiveVariables can be removed completely, and LiveIntervals can be directly @@ -123,11 +121,11 @@ MACHINE_FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis, #undef MACHINE_FUNCTION_ANALYSIS #ifndef MACHINE_FUNCTION_PASS -#define MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) +#define MACHINE_FUNCTION_PASS(NAME, CREATE_PASS) #endif -// MACHINE_FUNCTION_PASS("free-machine-function", FreeMachineFunctionPass, ()) -MACHINE_FUNCTION_PASS("no-op-machine-function", NoOpMachineFunctionPass, ()) -MACHINE_FUNCTION_PASS("print", PrintMIRPass, ()) +// MACHINE_FUNCTION_PASS("free-machine-function", FreeMachineFunctionPass()) +MACHINE_FUNCTION_PASS("no-op-machine-function", NoOpMachineFunctionPass()) +MACHINE_FUNCTION_PASS("print", PrintMIRPass()) #undef MACHINE_FUNCTION_PASS // After a pass is converted to new pass manager, its entry should be moved from @@ -135,130 +133,101 @@ MACHINE_FUNCTION_PASS("print", PrintMIRPass, ()) // DUMMY_MACHINE_FUNCTION_PASS to MACHINE_FUNCTION_PASS. #ifndef DUMMY_FUNCTION_PASS -#define DUMMY_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) +#define DUMMY_FUNCTION_PASS(NAME, PASS_NAME) #endif -DUMMY_FUNCTION_PASS("atomic-expand", AtomicExpandPass, ()) +DUMMY_FUNCTION_PASS("atomic-expand", AtomicExpandPass) #undef DUMMY_FUNCTION_PASS #ifndef DUMMY_MACHINE_MODULE_PASS -#define DUMMY_MACHINE_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) +#define DUMMY_MACHINE_MODULE_PASS(NAME, PASS_NAME) #endif -DUMMY_MACHINE_MODULE_PASS("machine-outliner", MachineOutlinerPass, ()) -DUMMY_MACHINE_MODULE_PASS("pseudo-probe-inserter", PseudoProbeInserterPass, ()) -DUMMY_MACHINE_MODULE_PASS("mir-debugify", DebugifyMachineModule, ()) -DUMMY_MACHINE_MODULE_PASS("mir-check-debugify", CheckDebugMachineModulePass, ()) -DUMMY_MACHINE_MODULE_PASS("mir-strip-debug", StripDebugMachineModulePass, - (OnlyDebugified)) +DUMMY_MACHINE_MODULE_PASS("machine-outliner", MachineOutlinerPass) +DUMMY_MACHINE_MODULE_PASS("pseudo-probe-inserter", PseudoProbeInserterPass) +DUMMY_MACHINE_MODULE_PASS("mir-debugify", DebugifyMachineModule) +DUMMY_MACHINE_MODULE_PASS("mir-check-debugify", CheckDebugMachineModulePass) +DUMMY_MACHINE_MODULE_PASS("mir-strip-debug", StripDebugMachineModulePass) #undef DUMMY_MACHINE_MODULE_PASS #ifndef DUMMY_MACHINE_FUNCTION_PASS -#define DUMMY_MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) +#define DUMMY_MACHINE_FUNCTION_PASS(NAME, PASS_NAME) #endif -DUMMY_MACHINE_FUNCTION_PASS("bbsections-prepare", BasicBlockSectionsPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("bbsections-profile-reader", - BasicBlockSectionsProfileReaderPass, (Buf)) -DUMMY_MACHINE_FUNCTION_PASS("block-placement", MachineBlockPlacementPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("block-placement-stats", - MachineBlockPlacementStatsPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("branch-folder", BranchFolderPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("break-false-deps", BreakFalseDepsPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("cfguard-longjmp", CFGuardLongjmpPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("cfi-fixup", CFIFixupPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("cfi-instr-inserter", CFIInstrInserterPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("dead-mi-elimination", - DeadMachineInstructionElimPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("detect-dead-lanes", DetectDeadLanesPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("dot-machine-cfg", MachineCFGPrinter, ()) -DUMMY_MACHINE_FUNCTION_PASS("early-ifcvt", EarlyIfConverterPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("early-machinelicm", EarlyMachineLICMPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("early-tailduplication", EarlyTailDuplicatePass, ()) -DUMMY_MACHINE_FUNCTION_PASS("fentry-insert", FEntryInserterPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("finalize-isel", FinalizeISelPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("fixup-statepoint-caller-saved", - FixupStatepointCallerSavedPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("fs-profile-loader", MIRProfileLoaderNewPass, - (File, ProfileFile, P, FS)) -DUMMY_MACHINE_FUNCTION_PASS("funclet-layout", FuncletLayoutPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("gc-empty-basic-blocks", GCEmptyBasicBlocksPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("implicit-null-checks", ImplicitNullChecksPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("instruction-select", InstructionSelectPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("irtranslator", IRTranslatorPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("kcfi", MachineKCFIPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("legalizer", LegalizerPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("livedebugvalues", LiveDebugValuesPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("liveintervals", LiveIntervalsPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("localstackalloc", LocalStackSlotPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("lrshrink", LiveRangeShrinkPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("machine-combiner", MachineCombinerPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("machine-cp", MachineCopyPropagationPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("machine-cse", MachineCSEPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("machine-function-splitter", - MachineFunctionSplitterPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("machine-latecleanup", MachineLateInstrsCleanupPass, - ()) -DUMMY_MACHINE_FUNCTION_PASS("machine-sanmd", MachineSanitizerBinaryMetadata, ()) -DUMMY_MACHINE_FUNCTION_PASS("machine-scheduler", MachineSchedulerPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("machine-sink", MachineSinkingPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("machine-uniformity", - MachineUniformityInfoWrapperPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("machineinstr-printer", MachineFunctionPrinterPass, - (OS, Banner)) -DUMMY_MACHINE_FUNCTION_PASS("machinelicm", MachineLICMPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("machineverifier", MachineVerifierPass, (Banner)) -DUMMY_MACHINE_FUNCTION_PASS("mirfs-discriminators", MIRAddFSDiscriminatorsPass, - (P)) -DUMMY_MACHINE_FUNCTION_PASS("opt-phis", OptimizePHIsPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("patchable-function", PatchableFunctionPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("peephole-opt", PeepholeOptimizerPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("phi-node-elimination", PHIEliminationPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("post-RA-sched", PostRASchedulerPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("postmisched", PostMachineSchedulerPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("postra-machine-sink", PostRAMachineSinkingPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("postrapseudos", ExpandPostRAPseudosPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("print-machine-cycles", MachineCycleInfoPrinterPass, - ()) -DUMMY_MACHINE_FUNCTION_PASS("print-machine-uniformity", - MachineUniformityInfoPrinterPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("processimpdefs", ProcessImplicitDefsPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("prologepilog", PrologEpilogInserterPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("prologepilog-code", PrologEpilogCodeInserterPass, - ()) -DUMMY_MACHINE_FUNCTION_PASS("ra-basic", RABasicPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("ra-fast", RAFastPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("ra-greedy", RAGreedyPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("ra-pbqp", RAPBQPPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("reg-usage-collector", RegUsageInfoCollectorPass, - ()) -DUMMY_MACHINE_FUNCTION_PASS("reg-usage-propagation", - RegUsageInfoPropagationPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("regalloc", RegAllocPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("regallocscoringpass", RegAllocScoringPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("regbankselect", RegBankSelectPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("removeredundantdebugvalues", - RemoveRedundantDebugValuesPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("rename-independent-subregs", - RenameIndependentSubregsPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("reset-machine-function", ResetMachineFunctionPass, - ()) -DUMMY_MACHINE_FUNCTION_PASS("shrink-wrap", ShrinkWrapPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("simple-register-coalescing", RegisterCoalescerPass, - ()) -DUMMY_MACHINE_FUNCTION_PASS("stack-coloring", StackColoringPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("stack-frame-layout", StackFrameLayoutAnalysisPass, - ()) -DUMMY_MACHINE_FUNCTION_PASS("stack-slot-coloring", StackSlotColoringPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("stackmap-liveness", StackMapLivenessPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("tailduplication", TailDuplicatePass, ()) -DUMMY_MACHINE_FUNCTION_PASS("twoaddressinstruction", TwoAddressInstructionPass, - ()) -DUMMY_MACHINE_FUNCTION_PASS("unpack-mi-bundles", UnpackMachineBundlesPass, - (Ftor)) -DUMMY_MACHINE_FUNCTION_PASS("virtregrewriter", VirtRegRewriterPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("xray-instrumentation", XRayInstrumentationPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("bbsections-prepare", BasicBlockSectionsPass) +DUMMY_MACHINE_FUNCTION_PASS("bbsections-profile-reader", BasicBlockSectionsProfileReaderPass) +DUMMY_MACHINE_FUNCTION_PASS("block-placement", MachineBlockPlacementPass) +DUMMY_MACHINE_FUNCTION_PASS("block-placement-stats", MachineBlockPlacementStatsPass) +DUMMY_MACHINE_FUNCTION_PASS("branch-folder", BranchFolderPass) +DUMMY_MACHINE_FUNCTION_PASS("break-false-deps", BreakFalseDepsPass) +DUMMY_MACHINE_FUNCTION_PASS("cfguard-longjmp", CFGuardLongjmpPass) +DUMMY_MACHINE_FUNCTION_PASS("cfi-fixup", CFIFixupPass) +DUMMY_MACHINE_FUNCTION_PASS("cfi-instr-inserter", CFIInstrInserterPass) +DUMMY_MACHINE_FUNCTION_PASS("dead-mi-elimination", DeadMachineInstructionElimPass) +DUMMY_MACHINE_FUNCTION_PASS("detect-dead-lanes", DetectDeadLanesPass) +DUMMY_MACHINE_FUNCTION_PASS("dot-machine-cfg", MachineCFGPrinter) +DUMMY_MACHINE_FUNCTION_PASS("early-ifcvt", EarlyIfConverterPass) +DUMMY_MACHINE_FUNCTION_PASS("early-machinelicm", EarlyMachineLICMPass) +DUMMY_MACHINE_FUNCTION_PASS("early-tailduplication", EarlyTailDuplicatePass) +DUMMY_MACHINE_FUNCTION_PASS("fentry-insert", FEntryInserterPass) +DUMMY_MACHINE_FUNCTION_PASS("finalize-isel", FinalizeISelPass) +DUMMY_MACHINE_FUNCTION_PASS("fixup-statepoint-caller-saved", FixupStatepointCallerSavedPass) +DUMMY_MACHINE_FUNCTION_PASS("fs-profile-loader", MIRProfileLoaderNewPass) +DUMMY_MACHINE_FUNCTION_PASS("funclet-layout", FuncletLayoutPass) +DUMMY_MACHINE_FUNCTION_PASS("gc-empty-basic-blocks", GCEmptyBasicBlocksPass) +DUMMY_MACHINE_FUNCTION_PASS("implicit-null-checks", ImplicitNullChecksPass) +DUMMY_MACHINE_FUNCTION_PASS("instruction-select", InstructionSelectPass) +DUMMY_MACHINE_FUNCTION_PASS("irtranslator", IRTranslatorPass) +DUMMY_MACHINE_FUNCTION_PASS("kcfi", MachineKCFIPass) +DUMMY_MACHINE_FUNCTION_PASS("legalizer", LegalizerPass) +DUMMY_MACHINE_FUNCTION_PASS("livedebugvalues", LiveDebugValuesPass) +DUMMY_MACHINE_FUNCTION_PASS("liveintervals", LiveIntervalsPass) +DUMMY_MACHINE_FUNCTION_PASS("localstackalloc", LocalStackSlotPass) +DUMMY_MACHINE_FUNCTION_PASS("lrshrink", LiveRangeShrinkPass) +DUMMY_MACHINE_FUNCTION_PASS("machine-combiner", MachineCombinerPass) +DUMMY_MACHINE_FUNCTION_PASS("machine-cp", MachineCopyPropagationPass) +DUMMY_MACHINE_FUNCTION_PASS("machine-cse", MachineCSEPass) +DUMMY_MACHINE_FUNCTION_PASS("machine-function-splitter", MachineFunctionSplitterPass) +DUMMY_MACHINE_FUNCTION_PASS("machine-latecleanup", MachineLateInstrsCleanupPass) +DUMMY_MACHINE_FUNCTION_PASS("machine-sanmd", MachineSanitizerBinaryMetadata) +DUMMY_MACHINE_FUNCTION_PASS("machine-scheduler", MachineSchedulerPass) +DUMMY_MACHINE_FUNCTION_PASS("machine-sink", MachineSinkingPass) +DUMMY_MACHINE_FUNCTION_PASS("machine-uniformity", MachineUniformityInfoWrapperPass) +DUMMY_MACHINE_FUNCTION_PASS("machineinstr-printer", MachineFunctionPrinterPass) +DUMMY_MACHINE_FUNCTION_PASS("machinelicm", MachineLICMPass) +DUMMY_MACHINE_FUNCTION_PASS("machineverifier", MachineVerifierPass) +DUMMY_MACHINE_FUNCTION_PASS("mirfs-discriminators", MIRAddFSDiscriminatorsPass) +DUMMY_MACHINE_FUNCTION_PASS("opt-phis", OptimizePHIsPass) +DUMMY_MACHINE_FUNCTION_PASS("patchable-function", PatchableFunctionPass) +DUMMY_MACHINE_FUNCTION_PASS("peephole-opt", PeepholeOptimizerPass) +DUMMY_MACHINE_FUNCTION_PASS("phi-node-elimination", PHIEliminationPass) +DUMMY_MACHINE_FUNCTION_PASS("post-RA-sched", PostRASchedulerPass) +DUMMY_MACHINE_FUNCTION_PASS("postmisched", PostMachineSchedulerPass) +DUMMY_MACHINE_FUNCTION_PASS("postra-machine-sink", PostRAMachineSinkingPass) +DUMMY_MACHINE_FUNCTION_PASS("postrapseudos", ExpandPostRAPseudosPass) +DUMMY_MACHINE_FUNCTION_PASS("print-machine-cycles", MachineCycleInfoPrinterPass) +DUMMY_MACHINE_FUNCTION_PASS("print-machine-uniformity", MachineUniformityInfoPrinterPass) +DUMMY_MACHINE_FUNCTION_PASS("processimpdefs", ProcessImplicitDefsPass) +DUMMY_MACHINE_FUNCTION_PASS("prologepilog", PrologEpilogInserterPass) +DUMMY_MACHINE_FUNCTION_PASS("prologepilog-code", PrologEpilogCodeInserterPass) +DUMMY_MACHINE_FUNCTION_PASS("ra-basic", RABasicPass) +DUMMY_MACHINE_FUNCTION_PASS("ra-fast", RAFastPass) +DUMMY_MACHINE_FUNCTION_PASS("ra-greedy", RAGreedyPass) +DUMMY_MACHINE_FUNCTION_PASS("ra-pbqp", RAPBQPPass) +DUMMY_MACHINE_FUNCTION_PASS("reg-usage-collector", RegUsageInfoCollectorPass) +DUMMY_MACHINE_FUNCTION_PASS("reg-usage-propagation", RegUsageInfoPropagationPass) +DUMMY_MACHINE_FUNCTION_PASS("regalloc", RegAllocPass) +DUMMY_MACHINE_FUNCTION_PASS("regallocscoringpass", RegAllocScoringPass) +DUMMY_MACHINE_FUNCTION_PASS("regbankselect", RegBankSelectPass) +DUMMY_MACHINE_FUNCTION_PASS("removeredundantdebugvalues", RemoveRedundantDebugValuesPass) +DUMMY_MACHINE_FUNCTION_PASS("rename-independent-subregs", RenameIndependentSubregsPass) +DUMMY_MACHINE_FUNCTION_PASS("reset-machine-function", ResetMachineFunctionPass) +DUMMY_MACHINE_FUNCTION_PASS("shrink-wrap", ShrinkWrapPass) +DUMMY_MACHINE_FUNCTION_PASS("simple-register-coalescing", RegisterCoalescerPass) +DUMMY_MACHINE_FUNCTION_PASS("stack-coloring", StackColoringPass) +DUMMY_MACHINE_FUNCTION_PASS("stack-frame-layout", StackFrameLayoutAnalysisPass) +DUMMY_MACHINE_FUNCTION_PASS("stack-slot-coloring", StackSlotColoringPass) +DUMMY_MACHINE_FUNCTION_PASS("stackmap-liveness", StackMapLivenessPass) +DUMMY_MACHINE_FUNCTION_PASS("tailduplication", TailDuplicatePass) +DUMMY_MACHINE_FUNCTION_PASS("twoaddressinstruction", TwoAddressInstructionPass) +DUMMY_MACHINE_FUNCTION_PASS("unpack-mi-bundles", UnpackMachineBundlesPass) +DUMMY_MACHINE_FUNCTION_PASS("virtregrewriter", VirtRegRewriterPass) +DUMMY_MACHINE_FUNCTION_PASS("xray-instrumentation", XRayInstrumentationPass) #undef DUMMY_MACHINE_FUNCTION_PASS - -#ifndef DUMMY_MACHINE_FUNCTION_ANALYSIS -#define DUMMY_MACHINE_FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) -#endif -DUMMY_MACHINE_FUNCTION_ANALYSIS("gc-analysis", GCMachineCodeAnalysisPass, ()) -#undef DUMMY_MACHINE_FUNCTION_ANALYSIS diff --git a/llvm/include/llvm/Target/TargetMachine.h b/llvm/include/llvm/Target/TargetMachine.h index a522a12299bb..7462f61d32b5 100644 --- a/llvm/include/llvm/Target/TargetMachine.h +++ b/llvm/include/llvm/Target/TargetMachine.h @@ -465,11 +465,6 @@ public: inconvertibleErrorCode()); } - virtual std::pair getPassNameFromLegacyName(StringRef) { - llvm_unreachable( - "getPassNameFromLegacyName parseMIRPipeline is not overridden"); - } - /// Add passes to the specified pass manager to get machine code emitted with /// the MCJIT. This method returns true if machine code is not supported. It /// fills the MCContext Ctx pointer which can be used to build custom diff --git a/llvm/lib/Passes/CodeGenPassBuilder.cpp b/llvm/lib/Passes/CodeGenPassBuilder.cpp index 927727cba6fc..16332200f9b4 100644 --- a/llvm/lib/Passes/CodeGenPassBuilder.cpp +++ b/llvm/lib/Passes/CodeGenPassBuilder.cpp @@ -16,7 +16,7 @@ using namespace llvm; namespace llvm { -#define DUMMY_MACHINE_FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \ +#define DUMMY_MACHINE_FUNCTION_ANALYSIS(NAME, CREATE_PASS) \ AnalysisKey PASS_NAME::Key; #include "llvm/Passes/MachinePassRegistry.def" } // namespace llvm diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp index 0f33af22dbd9..89947711d4bf 100644 --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -398,10 +398,10 @@ PassBuilder::PassBuilder(TargetMachine *TM, PipelineTuningOptions PTO, PIC->addClassToPassName(decltype(CREATE_PASS)::name(), NAME); #include "PassRegistry.def" -#define MACHINE_FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \ - PIC->addClassToPassName(PASS_NAME::name(), NAME); -#define MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ - PIC->addClassToPassName(PASS_NAME::name(), NAME); +#define MACHINE_FUNCTION_ANALYSIS(NAME, CREATE_PASS) \ + PIC->addClassToPassName(decltype(CREATE_PASS)::name(), NAME); +#define MACHINE_FUNCTION_PASS(NAME, CREATE_PASS) \ + PIC->addClassToPassName(decltype(CREATE_PASS)::name(), NAME); #include "llvm/Passes/MachinePassRegistry.def" } } @@ -441,8 +441,8 @@ void PassBuilder::registerFunctionAnalyses(FunctionAnalysisManager &FAM) { void PassBuilder::registerMachineFunctionAnalyses( MachineFunctionAnalysisManager &MFAM) { -#define MACHINE_FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \ - MFAM.registerPass([&] { return PASS_NAME(); }); +#define MACHINE_FUNCTION_ANALYSIS(NAME, CREATE_PASS) \ + MFAM.registerPass([&] { return CREATE_PASS; }); #include "llvm/Passes/MachinePassRegistry.def" for (auto &C : MachineFunctionAnalysisRegistrationCallbacks) @@ -1860,14 +1860,14 @@ Error PassBuilder::parseMachinePass(MachineFunctionPassManager &MFPM, return make_error("invalid pipeline", inconvertibleErrorCode()); -#define MACHINE_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ +#define MACHINE_MODULE_PASS(NAME, CREATE_PASS) \ if (Name == NAME) { \ - MFPM.addPass(PASS_NAME()); \ + MFPM.addPass(CREATE_PASS); \ return Error::success(); \ } -#define MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ +#define MACHINE_FUNCTION_PASS(NAME, CREATE_PASS) \ if (Name == NAME) { \ - MFPM.addPass(PASS_NAME()); \ + MFPM.addPass(CREATE_PASS); \ return Error::success(); \ } #include "llvm/Passes/MachinePassRegistry.def" @@ -2179,18 +2179,15 @@ void PassBuilder::printPassNames(raw_ostream &OS) { #include "PassRegistry.def" OS << "Machine module passes (WIP):\n"; -#define MACHINE_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ - printPassName(NAME, OS); +#define MACHINE_MODULE_PASS(NAME, CREATE_PASS) printPassName(NAME, OS); #include "llvm/Passes/MachinePassRegistry.def" OS << "Machine function passes (WIP):\n"; -#define MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ - printPassName(NAME, OS); +#define MACHINE_FUNCTION_PASS(NAME, CREATE_PASS) printPassName(NAME, OS); #include "llvm/Passes/MachinePassRegistry.def" OS << "Machine function analyses (WIP):\n"; -#define MACHINE_FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \ - printPassName(NAME, OS); +#define MACHINE_FUNCTION_ANALYSIS(NAME, CREATE_PASS) printPassName(NAME, OS); #include "llvm/Passes/MachinePassRegistry.def" } diff --git a/llvm/unittests/MIR/PassBuilderCallbacksTest.cpp b/llvm/unittests/MIR/PassBuilderCallbacksTest.cpp index 88522d45bc6b..0527d720f85f 100644 --- a/llvm/unittests/MIR/PassBuilderCallbacksTest.cpp +++ b/llvm/unittests/MIR/PassBuilderCallbacksTest.cpp @@ -433,6 +433,12 @@ TEST_F(MachineFunctionCallbacksTest, InstrumentedPasses) { CallbacksHandle, runBeforeNonSkippedPass(HasNameRegex("MockPassHandle"), HasName("test"))) .InSequence(PISequence); + EXPECT_CALL(CallbacksHandle, + runBeforeAnalysis(HasNameRegex("MockAnalysisHandle"), _)) + .InSequence(PISequence); + EXPECT_CALL(CallbacksHandle, + runAfterAnalysis(HasNameRegex("MockAnalysisHandle"), _)) + .InSequence(PISequence); EXPECT_CALL(CallbacksHandle, runAfterPass(HasNameRegex("MockPassHandle"), HasName("test"), _)) .InSequence(PISequence); -- GitLab From 617602d4f23e89e56afd0f550bcf72deb83ed0cb Mon Sep 17 00:00:00 2001 From: sstwcw Date: Mon, 29 Jan 2024 05:24:51 +0000 Subject: [PATCH 025/266] [clang-format] Handle generic selections inside parentheses (#79785) new ```C while (_Generic(x, // long: x)(x) > x) { } while (_Generic(x, // long: x)(x)) { } ``` old ```C while (_Generic(x, // long: x)(x) > x) { } while (_Generic(x, // long: x)(x)) { } ``` In the first case above, the second line previously aligned to the open parenthesis. The 4 spaces did not get added by the fallback line near the end of getNewLineColumn because there was already some indentaton. Now the spaces get added explicitly. In the second case above, without the fake parentheses, the second line did not respect the outer parentheses, because the LastSpace field did not get set without the fake parentheses. Now the indentation of the outer level is used instead. --- clang/lib/Format/ContinuationIndenter.cpp | 7 +++++-- clang/unittests/Format/FormatTest.cpp | 9 +++++++++ 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/clang/lib/Format/ContinuationIndenter.cpp b/clang/lib/Format/ContinuationIndenter.cpp index a3aca4a72531..671ae540c75b 100644 --- a/clang/lib/Format/ContinuationIndenter.cpp +++ b/clang/lib/Format/ContinuationIndenter.cpp @@ -1702,8 +1702,11 @@ void ContinuationIndenter::moveStatePastFakeLParens(LineState &State, // Special case for generic selection expressions, its comma-separated // expressions are not aligned to the opening paren like regular calls, but // rather continuation-indented relative to the _Generic keyword. - if (Previous && Previous->endsSequence(tok::l_paren, tok::kw__Generic)) - NewParenState.Indent = CurrentState.LastSpace; + if (Previous && Previous->endsSequence(tok::l_paren, tok::kw__Generic) && + State.Stack.size() > 1) { + NewParenState.Indent = State.Stack[State.Stack.size() - 2].Indent + + Style.ContinuationIndentWidth; + } if ((shouldUnindentNextOperator(Current) || (Previous && diff --git a/clang/unittests/Format/FormatTest.cpp b/clang/unittests/Format/FormatTest.cpp index 2f7febd49de4..87a02a4dfbf2 100644 --- a/clang/unittests/Format/FormatTest.cpp +++ b/clang/unittests/Format/FormatTest.cpp @@ -24147,6 +24147,15 @@ TEST_F(FormatTest, C11Generic) { " double _Complex: dc,\n" " long double _Complex: ldc)"); + verifyFormat("while (_Generic(x, //\n" + " long: x)(x) > x) {\n" + "}"); + verifyFormat("while (_Generic(x, //\n" + " long: x)(x)) {\n" + "}"); + verifyFormat("x(_Generic(x, //\n" + " long: x)(x));"); + FormatStyle Style = getLLVMStyle(); Style.ColumnLimit = 40; verifyFormat("#define LIMIT_MAX(T) \\\n" -- GitLab From 1442b0e65370b603dcd4c7cfc300f19937c3bc79 Mon Sep 17 00:00:00 2001 From: Jason Eckhardt Date: Mon, 5 Feb 2024 23:23:13 -0600 Subject: [PATCH 026/266] [TableGen] Remove redundant buffer copies for ULEB128 decode calls. (#80199) This patch removes a couple of redundant buffer copies in emitTable for setting up calls to decodeULEB128. Instead, provide the Table.data buffer directly to the calls-- where decodeULEB128 does its own buffer overflow checking. Factor out 7 explicit loops to emit ULEB128 bytes into emitULEB128. Also factor out 4 copies of 24-bit numtoskip emission into emitNumToSkip. The functionality is already covered by existing unit tests and by virtue of most of the in-tree back-ends exercising the decoder emitter. --- llvm/utils/TableGen/DecoderEmitter.cpp | 120 +++++++++++-------------- 1 file changed, 52 insertions(+), 68 deletions(-) diff --git a/llvm/utils/TableGen/DecoderEmitter.cpp b/llvm/utils/TableGen/DecoderEmitter.cpp index 525aae02ded9..591ee5c72887 100644 --- a/llvm/utils/TableGen/DecoderEmitter.cpp +++ b/llvm/utils/TableGen/DecoderEmitter.cpp @@ -775,6 +775,33 @@ void DecoderEmitter::emitTable(formatted_raw_ostream &OS, DecoderTable &Table, Indentation += 2; + // Emit ULEB128 encoded value to OS, returning the number of bytes emitted. + auto emitULEB128 = [](DecoderTable::const_iterator I, + formatted_raw_ostream &OS) { + unsigned Len = 0; + while (*I >= 128) { + OS << (unsigned)*I++ << ", "; + Len++; + } + OS << (unsigned)*I++ << ", "; + return Len + 1; + }; + + // Emit 24-bit numtoskip value to OS, returning the NumToSkip value. + auto emitNumToSkip = [](DecoderTable::const_iterator I, + formatted_raw_ostream &OS) { + uint8_t Byte = *I++; + uint32_t NumToSkip = Byte; + OS << (unsigned)Byte << ", "; + Byte = *I++; + OS << (unsigned)Byte << ", "; + NumToSkip |= Byte << 8; + Byte = *I++; + OS << utostr(Byte) << ", "; + NumToSkip |= Byte << 16; + return NumToSkip; + }; + // FIXME: We may be able to use the NumToSkip values to recover // appropriate indentation levels. DecoderTable::const_iterator I = Table.begin(); @@ -794,14 +821,11 @@ void DecoderEmitter::emitTable(formatted_raw_ostream &OS, DecoderTable &Table, OS.indent(Indentation) << "MCD::OPC_ExtractField, "; // ULEB128 encoded start value. - uint8_t Buffer[16], *P = Buffer; - while ((*P++ = *I++) >= 128) - assert((P - Buffer) <= (ptrdiff_t)sizeof(Buffer) && - "ULEB128 value too large!"); - unsigned Start = decodeULEB128(Buffer); - for (P = Buffer; *P >= 128; ++P) - OS << (unsigned)*P << ", "; - OS << (unsigned)*P << ", "; + const char *ErrMsg = nullptr; + unsigned Start = decodeULEB128(Table.data() + Pos + 1, nullptr, + Table.data() + Table.size(), &ErrMsg); + assert(ErrMsg == nullptr && "ULEB128 value too large!"); + I += emitULEB128(I, OS); unsigned Len = *I++; OS << Len << ", // Inst{"; @@ -814,20 +838,11 @@ void DecoderEmitter::emitTable(formatted_raw_ostream &OS, DecoderTable &Table, ++I; OS.indent(Indentation) << "MCD::OPC_FilterValue, "; // The filter value is ULEB128 encoded. - while (*I >= 128) - OS << (unsigned)*I++ << ", "; - OS << (unsigned)*I++ << ", "; + I += emitULEB128(I, OS); // 24-bit numtoskip value. - uint8_t Byte = *I++; - uint32_t NumToSkip = Byte; - OS << (unsigned)Byte << ", "; - Byte = *I++; - OS << (unsigned)Byte << ", "; - NumToSkip |= Byte << 8; - Byte = *I++; - OS << utostr(Byte) << ", "; - NumToSkip |= Byte << 16; + uint32_t NumToSkip = emitNumToSkip(I, OS); + I += 3; OS << "// Skip to: " << ((I - Table.begin()) + NumToSkip) << "\n"; break; } @@ -835,46 +850,27 @@ void DecoderEmitter::emitTable(formatted_raw_ostream &OS, DecoderTable &Table, ++I; OS.indent(Indentation) << "MCD::OPC_CheckField, "; // ULEB128 encoded start value. - for (; *I >= 128; ++I) - OS << (unsigned)*I << ", "; - OS << (unsigned)*I++ << ", "; + I += emitULEB128(I, OS); // 8-bit length. unsigned Len = *I++; OS << Len << ", "; // ULEB128 encoded field value. - for (; *I >= 128; ++I) - OS << (unsigned)*I << ", "; - OS << (unsigned)*I++ << ", "; + I += emitULEB128(I, OS); + // 24-bit numtoskip value. - uint8_t Byte = *I++; - uint32_t NumToSkip = Byte; - OS << (unsigned)Byte << ", "; - Byte = *I++; - OS << (unsigned)Byte << ", "; - NumToSkip |= Byte << 8; - Byte = *I++; - OS << utostr(Byte) << ", "; - NumToSkip |= Byte << 16; + uint32_t NumToSkip = emitNumToSkip(I, OS); + I += 3; OS << "// Skip to: " << ((I - Table.begin()) + NumToSkip) << "\n"; break; } case MCD::OPC_CheckPredicate: { ++I; OS.indent(Indentation) << "MCD::OPC_CheckPredicate, "; - for (; *I >= 128; ++I) - OS << (unsigned)*I << ", "; - OS << (unsigned)*I++ << ", "; + I += emitULEB128(I, OS); // 24-bit numtoskip value. - uint8_t Byte = *I++; - uint32_t NumToSkip = Byte; - OS << (unsigned)Byte << ", "; - Byte = *I++; - OS << (unsigned)Byte << ", "; - NumToSkip |= Byte << 8; - Byte = *I++; - OS << utostr(Byte) << ", "; - NumToSkip |= Byte << 16; + uint32_t NumToSkip = emitNumToSkip(I, OS); + I += 3; OS << "// Skip to: " << ((I - Table.begin()) + NumToSkip) << "\n"; break; } @@ -882,23 +878,18 @@ void DecoderEmitter::emitTable(formatted_raw_ostream &OS, DecoderTable &Table, case MCD::OPC_TryDecode: { bool IsTry = *I == MCD::OPC_TryDecode; ++I; - // Extract the ULEB128 encoded Opcode to a buffer. - uint8_t Buffer[16], *p = Buffer; - while ((*p++ = *I++) >= 128) - assert((p - Buffer) <= (ptrdiff_t)sizeof(Buffer) - && "ULEB128 value too large!"); // Decode the Opcode value. - unsigned Opc = decodeULEB128(Buffer); + const char *ErrMsg = nullptr; + unsigned Opc = decodeULEB128(Table.data() + Pos + 1, nullptr, + Table.data() + Table.size(), &ErrMsg); + assert(ErrMsg == nullptr && "ULEB128 value too large!"); + OS.indent(Indentation) << "MCD::OPC_" << (IsTry ? "Try" : "") << "Decode, "; - for (p = Buffer; *p >= 128; ++p) - OS << (unsigned)*p << ", "; - OS << (unsigned)*p << ", "; + I += emitULEB128(I, OS); // Decoder index. - for (; *I >= 128; ++I) - OS << (unsigned)*I << ", "; - OS << (unsigned)*I++ << ", "; + I += emitULEB128(I, OS); if (!IsTry) { OS << "// Opcode: " << NumberedEncodings[Opc] << "\n"; @@ -908,15 +899,8 @@ void DecoderEmitter::emitTable(formatted_raw_ostream &OS, DecoderTable &Table, // Fallthrough for OPC_TryDecode. // 24-bit numtoskip value. - uint8_t Byte = *I++; - uint32_t NumToSkip = Byte; - OS << (unsigned)Byte << ", "; - Byte = *I++; - OS << (unsigned)Byte << ", "; - NumToSkip |= Byte << 8; - Byte = *I++; - OS << utostr(Byte) << ", "; - NumToSkip |= Byte << 16; + uint32_t NumToSkip = emitNumToSkip(I, OS); + I += 3; OS << "// Opcode: " << NumberedEncodings[Opc] << ", skip to: " << ((I - Table.begin()) + NumToSkip) << "\n"; -- GitLab From fa70b5d1309f15244cb5528d545d42865cbf8e18 Mon Sep 17 00:00:00 2001 From: Yuxuan Chen Date: Mon, 5 Feb 2024 21:43:49 -0800 Subject: [PATCH 027/266] [Coroutines][NFC] Refactor CoroSplit for Switch Resume ABI (#80758) --- llvm/lib/Transforms/Coroutines/CoroSplit.cpp | 471 ++++++++++--------- 1 file changed, 237 insertions(+), 234 deletions(-) diff --git a/llvm/lib/Transforms/Coroutines/CoroSplit.cpp b/llvm/lib/Transforms/Coroutines/CoroSplit.cpp index 7758b52abc20..a552b3ac2008 100644 --- a/llvm/lib/Transforms/Coroutines/CoroSplit.cpp +++ b/llvm/lib/Transforms/Coroutines/CoroSplit.cpp @@ -407,104 +407,6 @@ static void replaceCoroEnd(AnyCoroEndInst *End, const coro::Shape &Shape, End->eraseFromParent(); } -// Create an entry block for a resume function with a switch that will jump to -// suspend points. -static void createResumeEntryBlock(Function &F, coro::Shape &Shape) { - assert(Shape.ABI == coro::ABI::Switch); - LLVMContext &C = F.getContext(); - - // resume.entry: - // %index.addr = getelementptr inbounds %f.Frame, %f.Frame* %FramePtr, i32 0, - // i32 2 - // % index = load i32, i32* %index.addr - // switch i32 %index, label %unreachable [ - // i32 0, label %resume.0 - // i32 1, label %resume.1 - // ... - // ] - - auto *NewEntry = BasicBlock::Create(C, "resume.entry", &F); - auto *UnreachBB = BasicBlock::Create(C, "unreachable", &F); - - IRBuilder<> Builder(NewEntry); - auto *FramePtr = Shape.FramePtr; - auto *FrameTy = Shape.FrameTy; - auto *GepIndex = Builder.CreateStructGEP( - FrameTy, FramePtr, Shape.getSwitchIndexField(), "index.addr"); - auto *Index = Builder.CreateLoad(Shape.getIndexType(), GepIndex, "index"); - auto *Switch = - Builder.CreateSwitch(Index, UnreachBB, Shape.CoroSuspends.size()); - Shape.SwitchLowering.ResumeSwitch = Switch; - - size_t SuspendIndex = 0; - for (auto *AnyS : Shape.CoroSuspends) { - auto *S = cast(AnyS); - ConstantInt *IndexVal = Shape.getIndex(SuspendIndex); - - // Replace CoroSave with a store to Index: - // %index.addr = getelementptr %f.frame... (index field number) - // store i32 %IndexVal, i32* %index.addr1 - auto *Save = S->getCoroSave(); - Builder.SetInsertPoint(Save); - if (S->isFinal()) { - // The coroutine should be marked done if it reaches the final suspend - // point. - markCoroutineAsDone(Builder, Shape, FramePtr); - } else { - auto *GepIndex = Builder.CreateStructGEP( - FrameTy, FramePtr, Shape.getSwitchIndexField(), "index.addr"); - Builder.CreateStore(IndexVal, GepIndex); - } - - Save->replaceAllUsesWith(ConstantTokenNone::get(C)); - Save->eraseFromParent(); - - // Split block before and after coro.suspend and add a jump from an entry - // switch: - // - // whateverBB: - // whatever - // %0 = call i8 @llvm.coro.suspend(token none, i1 false) - // switch i8 %0, label %suspend[i8 0, label %resume - // i8 1, label %cleanup] - // becomes: - // - // whateverBB: - // whatever - // br label %resume.0.landing - // - // resume.0: ; <--- jump from the switch in the resume.entry - // %0 = tail call i8 @llvm.coro.suspend(token none, i1 false) - // br label %resume.0.landing - // - // resume.0.landing: - // %1 = phi i8[-1, %whateverBB], [%0, %resume.0] - // switch i8 % 1, label %suspend [i8 0, label %resume - // i8 1, label %cleanup] - - auto *SuspendBB = S->getParent(); - auto *ResumeBB = - SuspendBB->splitBasicBlock(S, "resume." + Twine(SuspendIndex)); - auto *LandingBB = ResumeBB->splitBasicBlock( - S->getNextNode(), ResumeBB->getName() + Twine(".landing")); - Switch->addCase(IndexVal, ResumeBB); - - cast(SuspendBB->getTerminator())->setSuccessor(0, LandingBB); - auto *PN = PHINode::Create(Builder.getInt8Ty(), 2, ""); - PN->insertBefore(LandingBB->begin()); - S->replaceAllUsesWith(PN); - PN->addIncoming(Builder.getInt8(-1), SuspendBB); - PN->addIncoming(S, ResumeBB); - - ++SuspendIndex; - } - - Builder.SetInsertPoint(UnreachBB); - Builder.CreateUnreachable(); - - Shape.SwitchLowering.ResumeEntryBlock = NewEntry; -} - // In the resume function, we remove the last case (when coro::Shape is built, // the final suspend point (if present) is always the last element of // CoroSuspends array) since it is an undefined behavior to resume a coroutine @@ -1161,16 +1063,6 @@ void CoroCloner::create() { /*Elide=*/ FKind == CoroCloner::Kind::SwitchCleanup); } -// Create a resume clone by cloning the body of the original function, setting -// new entry block and replacing coro.suspend an appropriate value to force -// resume or cleanup pass for every suspend point. -static Function *createClone(Function &F, const Twine &Suffix, - coro::Shape &Shape, CoroCloner::Kind FKind) { - CoroCloner Cloner(F, Suffix, Shape, FKind); - Cloner.create(); - return Cloner.getFunction(); -} - static void updateAsyncFuncPointerContextSize(coro::Shape &Shape) { assert(Shape.ABI == coro::ABI::Async); @@ -1212,67 +1104,6 @@ static void replaceFrameSizeAndAlignment(coro::Shape &Shape) { } } -// Create a global constant array containing pointers to functions provided and -// set Info parameter of CoroBegin to point at this constant. Example: -// -// @f.resumers = internal constant [2 x void(%f.frame*)*] -// [void(%f.frame*)* @f.resume, void(%f.frame*)* @f.destroy] -// define void @f() { -// ... -// call i8* @llvm.coro.begin(i8* null, i32 0, i8* null, -// i8* bitcast([2 x void(%f.frame*)*] * @f.resumers to i8*)) -// -// Assumes that all the functions have the same signature. -static void setCoroInfo(Function &F, coro::Shape &Shape, - ArrayRef Fns) { - // This only works under the switch-lowering ABI because coro elision - // only works on the switch-lowering ABI. - assert(Shape.ABI == coro::ABI::Switch); - - SmallVector Args(Fns.begin(), Fns.end()); - assert(!Args.empty()); - Function *Part = *Fns.begin(); - Module *M = Part->getParent(); - auto *ArrTy = ArrayType::get(Part->getType(), Args.size()); - - auto *ConstVal = ConstantArray::get(ArrTy, Args); - auto *GV = new GlobalVariable(*M, ConstVal->getType(), /*isConstant=*/true, - GlobalVariable::PrivateLinkage, ConstVal, - F.getName() + Twine(".resumers")); - - // Update coro.begin instruction to refer to this constant. - LLVMContext &C = F.getContext(); - auto *BC = ConstantExpr::getPointerCast(GV, PointerType::getUnqual(C)); - Shape.getSwitchCoroId()->setInfo(BC); -} - -// Store addresses of Resume/Destroy/Cleanup functions in the coroutine frame. -static void updateCoroFrame(coro::Shape &Shape, Function *ResumeFn, - Function *DestroyFn, Function *CleanupFn) { - assert(Shape.ABI == coro::ABI::Switch); - - IRBuilder<> Builder(&*Shape.getInsertPtAfterFramePtr()); - - auto *ResumeAddr = Builder.CreateStructGEP( - Shape.FrameTy, Shape.FramePtr, coro::Shape::SwitchFieldIndex::Resume, - "resume.addr"); - Builder.CreateStore(ResumeFn, ResumeAddr); - - Value *DestroyOrCleanupFn = DestroyFn; - - CoroIdInst *CoroId = Shape.getSwitchCoroId(); - if (CoroAllocInst *CA = CoroId->getCoroAlloc()) { - // If there is a CoroAlloc and it returns false (meaning we elide the - // allocation, use CleanupFn instead of DestroyFn). - DestroyOrCleanupFn = Builder.CreateSelect(CA, DestroyFn, CleanupFn); - } - - auto *DestroyAddr = Builder.CreateStructGEP( - Shape.FrameTy, Shape.FramePtr, coro::Shape::SwitchFieldIndex::Destroy, - "destroy.addr"); - Builder.CreateStore(DestroyOrCleanupFn, DestroyAddr); -} - static void postSplitCleanup(Function &F) { removeUnreachableBlocks(F); @@ -1447,34 +1278,6 @@ static bool shouldBeMustTail(const CallInst &CI, const Function &F) { return true; } -// Add musttail to any resume instructions that is immediately followed by a -// suspend (i.e. ret). We do this even in -O0 to support guaranteed tail call -// for symmetrical coroutine control transfer (C++ Coroutines TS extension). -// This transformation is done only in the resume part of the coroutine that has -// identical signature and calling convention as the coro.resume call. -static void addMustTailToCoroResumes(Function &F, TargetTransformInfo &TTI) { - bool changed = false; - - // Collect potential resume instructions. - SmallVector Resumes; - for (auto &I : instructions(F)) - if (auto *Call = dyn_cast(&I)) - if (shouldBeMustTail(*Call, F)) - Resumes.push_back(Call); - - // Set musttail on those that are followed by a ret instruction. - for (CallInst *Call : Resumes) - // Skip targets which don't support tail call on the specific case. - if (TTI.supportsTailCallFor(Call) && - simplifyTerminatorLeadingToRet(Call->getNextNode())) { - Call->setTailCallKind(CallInst::TCK_MustTail); - changed = true; - } - - if (changed) - removeUnreachableBlocks(F); -} - // Coroutine has no suspend points. Remove heap allocation for the coroutine // frame if possible. static void handleNoSuspendCoroutine(coro::Shape &Shape) { @@ -1678,44 +1481,244 @@ static void simplifySuspendPoints(coro::Shape &Shape) { } } -static void splitSwitchCoroutine(Function &F, coro::Shape &Shape, - SmallVectorImpl &Clones, - TargetTransformInfo &TTI) { - assert(Shape.ABI == coro::ABI::Switch); - - createResumeEntryBlock(F, Shape); - auto ResumeClone = createClone(F, ".resume", Shape, - CoroCloner::Kind::SwitchResume); - auto DestroyClone = createClone(F, ".destroy", Shape, - CoroCloner::Kind::SwitchUnwind); - auto CleanupClone = createClone(F, ".cleanup", Shape, - CoroCloner::Kind::SwitchCleanup); - - postSplitCleanup(*ResumeClone); - postSplitCleanup(*DestroyClone); - postSplitCleanup(*CleanupClone); - - // Adding musttail call to support symmetric transfer. - // Skip targets which don't support tail call. - // - // FIXME: Could we support symmetric transfer effectively without musttail - // call? - if (TTI.supportsTailCalls()) - addMustTailToCoroResumes(*ResumeClone, TTI); +namespace { - // Store addresses resume/destroy/cleanup functions in the coroutine frame. - updateCoroFrame(Shape, ResumeClone, DestroyClone, CleanupClone); +struct SwitchCoroutineSplitter { + static void split(Function &F, coro::Shape &Shape, + SmallVectorImpl &Clones, + TargetTransformInfo &TTI) { + assert(Shape.ABI == coro::ABI::Switch); - assert(Clones.empty()); - Clones.push_back(ResumeClone); - Clones.push_back(DestroyClone); - Clones.push_back(CleanupClone); - - // Create a constant array referring to resume/destroy/clone functions pointed - // by the last argument of @llvm.coro.info, so that CoroElide pass can - // determined correct function to call. - setCoroInfo(F, Shape, Clones); -} + createResumeEntryBlock(F, Shape); + auto *ResumeClone = + createClone(F, ".resume", Shape, CoroCloner::Kind::SwitchResume); + auto *DestroyClone = + createClone(F, ".destroy", Shape, CoroCloner::Kind::SwitchUnwind); + auto *CleanupClone = + createClone(F, ".cleanup", Shape, CoroCloner::Kind::SwitchCleanup); + + postSplitCleanup(*ResumeClone); + postSplitCleanup(*DestroyClone); + postSplitCleanup(*CleanupClone); + + // Adding musttail call to support symmetric transfer. + // Skip targets which don't support tail call. + // + // FIXME: Could we support symmetric transfer effectively without musttail + // call? + if (TTI.supportsTailCalls()) + addMustTailToCoroResumes(*ResumeClone, TTI); + + // Store addresses resume/destroy/cleanup functions in the coroutine frame. + updateCoroFrame(Shape, ResumeClone, DestroyClone, CleanupClone); + + assert(Clones.empty()); + Clones.push_back(ResumeClone); + Clones.push_back(DestroyClone); + Clones.push_back(CleanupClone); + + // Create a constant array referring to resume/destroy/clone functions + // pointed by the last argument of @llvm.coro.info, so that CoroElide pass + // can determined correct function to call. + setCoroInfo(F, Shape, Clones); + } + +private: + // Create a resume clone by cloning the body of the original function, setting + // new entry block and replacing coro.suspend an appropriate value to force + // resume or cleanup pass for every suspend point. + static Function *createClone(Function &F, const Twine &Suffix, + coro::Shape &Shape, CoroCloner::Kind FKind) { + CoroCloner Cloner(F, Suffix, Shape, FKind); + Cloner.create(); + return Cloner.getFunction(); + } + + // Create an entry block for a resume function with a switch that will jump to + // suspend points. + static void createResumeEntryBlock(Function &F, coro::Shape &Shape) { + LLVMContext &C = F.getContext(); + + // resume.entry: + // %index.addr = getelementptr inbounds %f.Frame, %f.Frame* %FramePtr, i32 + // 0, i32 2 % index = load i32, i32* %index.addr switch i32 %index, label + // %unreachable [ + // i32 0, label %resume.0 + // i32 1, label %resume.1 + // ... + // ] + + auto *NewEntry = BasicBlock::Create(C, "resume.entry", &F); + auto *UnreachBB = BasicBlock::Create(C, "unreachable", &F); + + IRBuilder<> Builder(NewEntry); + auto *FramePtr = Shape.FramePtr; + auto *FrameTy = Shape.FrameTy; + auto *GepIndex = Builder.CreateStructGEP( + FrameTy, FramePtr, Shape.getSwitchIndexField(), "index.addr"); + auto *Index = Builder.CreateLoad(Shape.getIndexType(), GepIndex, "index"); + auto *Switch = + Builder.CreateSwitch(Index, UnreachBB, Shape.CoroSuspends.size()); + Shape.SwitchLowering.ResumeSwitch = Switch; + + size_t SuspendIndex = 0; + for (auto *AnyS : Shape.CoroSuspends) { + auto *S = cast(AnyS); + ConstantInt *IndexVal = Shape.getIndex(SuspendIndex); + + // Replace CoroSave with a store to Index: + // %index.addr = getelementptr %f.frame... (index field number) + // store i32 %IndexVal, i32* %index.addr1 + auto *Save = S->getCoroSave(); + Builder.SetInsertPoint(Save); + if (S->isFinal()) { + // The coroutine should be marked done if it reaches the final suspend + // point. + markCoroutineAsDone(Builder, Shape, FramePtr); + } else { + auto *GepIndex = Builder.CreateStructGEP( + FrameTy, FramePtr, Shape.getSwitchIndexField(), "index.addr"); + Builder.CreateStore(IndexVal, GepIndex); + } + + Save->replaceAllUsesWith(ConstantTokenNone::get(C)); + Save->eraseFromParent(); + + // Split block before and after coro.suspend and add a jump from an entry + // switch: + // + // whateverBB: + // whatever + // %0 = call i8 @llvm.coro.suspend(token none, i1 false) + // switch i8 %0, label %suspend[i8 0, label %resume + // i8 1, label %cleanup] + // becomes: + // + // whateverBB: + // whatever + // br label %resume.0.landing + // + // resume.0: ; <--- jump from the switch in the resume.entry + // %0 = tail call i8 @llvm.coro.suspend(token none, i1 false) + // br label %resume.0.landing + // + // resume.0.landing: + // %1 = phi i8[-1, %whateverBB], [%0, %resume.0] + // switch i8 % 1, label %suspend [i8 0, label %resume + // i8 1, label %cleanup] + + auto *SuspendBB = S->getParent(); + auto *ResumeBB = + SuspendBB->splitBasicBlock(S, "resume." + Twine(SuspendIndex)); + auto *LandingBB = ResumeBB->splitBasicBlock( + S->getNextNode(), ResumeBB->getName() + Twine(".landing")); + Switch->addCase(IndexVal, ResumeBB); + + cast(SuspendBB->getTerminator())->setSuccessor(0, LandingBB); + auto *PN = PHINode::Create(Builder.getInt8Ty(), 2, ""); + PN->insertBefore(LandingBB->begin()); + S->replaceAllUsesWith(PN); + PN->addIncoming(Builder.getInt8(-1), SuspendBB); + PN->addIncoming(S, ResumeBB); + + ++SuspendIndex; + } + + Builder.SetInsertPoint(UnreachBB); + Builder.CreateUnreachable(); + + Shape.SwitchLowering.ResumeEntryBlock = NewEntry; + } + + // Add musttail to any resume instructions that is immediately followed by a + // suspend (i.e. ret). We do this even in -O0 to support guaranteed tail call + // for symmetrical coroutine control transfer (C++ Coroutines TS extension). + // This transformation is done only in the resume part of the coroutine that + // has identical signature and calling convention as the coro.resume call. + static void addMustTailToCoroResumes(Function &F, TargetTransformInfo &TTI) { + bool Changed = false; + + // Collect potential resume instructions. + SmallVector Resumes; + for (auto &I : instructions(F)) + if (auto *Call = dyn_cast(&I)) + if (shouldBeMustTail(*Call, F)) + Resumes.push_back(Call); + + // Set musttail on those that are followed by a ret instruction. + for (CallInst *Call : Resumes) + // Skip targets which don't support tail call on the specific case. + if (TTI.supportsTailCallFor(Call) && + simplifyTerminatorLeadingToRet(Call->getNextNode())) { + Call->setTailCallKind(CallInst::TCK_MustTail); + Changed = true; + } + + if (Changed) + removeUnreachableBlocks(F); + } + + // Store addresses of Resume/Destroy/Cleanup functions in the coroutine frame. + static void updateCoroFrame(coro::Shape &Shape, Function *ResumeFn, + Function *DestroyFn, Function *CleanupFn) { + IRBuilder<> Builder(&*Shape.getInsertPtAfterFramePtr()); + + auto *ResumeAddr = Builder.CreateStructGEP( + Shape.FrameTy, Shape.FramePtr, coro::Shape::SwitchFieldIndex::Resume, + "resume.addr"); + Builder.CreateStore(ResumeFn, ResumeAddr); + + Value *DestroyOrCleanupFn = DestroyFn; + + CoroIdInst *CoroId = Shape.getSwitchCoroId(); + if (CoroAllocInst *CA = CoroId->getCoroAlloc()) { + // If there is a CoroAlloc and it returns false (meaning we elide the + // allocation, use CleanupFn instead of DestroyFn). + DestroyOrCleanupFn = Builder.CreateSelect(CA, DestroyFn, CleanupFn); + } + + auto *DestroyAddr = Builder.CreateStructGEP( + Shape.FrameTy, Shape.FramePtr, coro::Shape::SwitchFieldIndex::Destroy, + "destroy.addr"); + Builder.CreateStore(DestroyOrCleanupFn, DestroyAddr); + } + + // Create a global constant array containing pointers to functions provided + // and set Info parameter of CoroBegin to point at this constant. Example: + // + // @f.resumers = internal constant [2 x void(%f.frame*)*] + // [void(%f.frame*)* @f.resume, void(%f.frame*)* + // @f.destroy] + // define void @f() { + // ... + // call i8* @llvm.coro.begin(i8* null, i32 0, i8* null, + // i8* bitcast([2 x void(%f.frame*)*] * @f.resumers to + // i8*)) + // + // Assumes that all the functions have the same signature. + static void setCoroInfo(Function &F, coro::Shape &Shape, + ArrayRef Fns) { + // This only works under the switch-lowering ABI because coro elision + // only works on the switch-lowering ABI. + SmallVector Args(Fns.begin(), Fns.end()); + assert(!Args.empty()); + Function *Part = *Fns.begin(); + Module *M = Part->getParent(); + auto *ArrTy = ArrayType::get(Part->getType(), Args.size()); + + auto *ConstVal = ConstantArray::get(ArrTy, Args); + auto *GV = new GlobalVariable(*M, ConstVal->getType(), /*isConstant=*/true, + GlobalVariable::PrivateLinkage, ConstVal, + F.getName() + Twine(".resumers")); + + // Update coro.begin instruction to refer to this constant. + LLVMContext &C = F.getContext(); + auto *BC = ConstantExpr::getPointerCast(GV, PointerType::getUnqual(C)); + Shape.getSwitchCoroId()->setInfo(BC); + } +}; + +} // namespace static void replaceAsyncResumeFunction(CoroSuspendAsyncInst *Suspend, Value *Continuation) { @@ -2027,7 +2030,7 @@ splitCoroutine(Function &F, SmallVectorImpl &Clones, } else { switch (Shape.ABI) { case coro::ABI::Switch: - splitSwitchCoroutine(F, Shape, Clones, TTI); + SwitchCoroutineSplitter::split(F, Shape, Clones, TTI); break; case coro::ABI::Async: splitAsyncCoroutine(F, Shape, Clones); -- GitLab From 397e91f0f387bf2db0cc320a9078a60d2334545e Mon Sep 17 00:00:00 2001 From: Enna1 Date: Tue, 6 Feb 2024 14:25:55 +0800 Subject: [PATCH 028/266] =?UTF-8?q?[MemProf][NFC]=20Compute=20SHADOW=5FENT?= =?UTF-8?q?RY=5FSIZE=20from=20MEM=5FGRANULARITY=20and=20SHA=E2=80=A6=20(#8?= =?UTF-8?q?0589)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit …DOW_SCALE As MEM_GRANULARITY represents the size of memory block mapped to a single shadow entry, and SHADOW_SCALE represents the scale of shadow mapping, so the single shadow entry size can be computed as (MEM_GRANULARITY >> SHADOW_SCALE). This patch replaces the hardcoded SHADOW_ENTRY_SIZE with (MEM_GRANULARITY >> SHADOW_SCALE). --- compiler-rt/lib/memprof/memprof_mapping.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler-rt/lib/memprof/memprof_mapping.h b/compiler-rt/lib/memprof/memprof_mapping.h index ba05b88db307..1cc0836834cd 100644 --- a/compiler-rt/lib/memprof/memprof_mapping.h +++ b/compiler-rt/lib/memprof/memprof_mapping.h @@ -29,8 +29,6 @@ extern uptr kHighMemEnd; // Initialized in __memprof_init. } // namespace __memprof -#define SHADOW_ENTRY_SIZE 8 - // Size of memory block mapped to a single shadow location #define MEM_GRANULARITY 64ULL @@ -39,6 +37,8 @@ extern uptr kHighMemEnd; // Initialized in __memprof_init. #define MEM_TO_SHADOW(mem) \ ((((mem) & SHADOW_MASK) >> SHADOW_SCALE) + (SHADOW_OFFSET)) +#define SHADOW_ENTRY_SIZE (MEM_GRANULARITY >> SHADOW_SCALE) + #define kLowMemBeg 0 #define kLowMemEnd (SHADOW_OFFSET ? SHADOW_OFFSET - 1 : 0) -- GitLab From 0716d31649c44dd622cca6632b0c46a8dcafaa2d Mon Sep 17 00:00:00 2001 From: Yeting Kuo <46629943+yetingk@users.noreply.github.com> Date: Tue, 6 Feb 2024 14:41:47 +0800 Subject: [PATCH 029/266] [RISCV][NFC] Use maybe_unused instead of casting to void to fix unused variable warning. (#80651) --- .../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 4 ++-- .../RISCV/Disassembler/RISCVDisassembler.cpp | 20 +++++++++---------- .../RISCV/MCTargetDesc/RISCVAsmBackend.cpp | 11 +++++----- llvm/lib/Target/RISCV/RISCVFoldMasks.cpp | 3 ++- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 11 +++++----- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 12 +++++------ llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 1 - 7 files changed, 29 insertions(+), 33 deletions(-) diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index f6e8386aff45..4063719582bb 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -1222,8 +1222,8 @@ public: int64_t Imm = 0; if (Kind == KindTy::Immediate) { RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; - bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); - (void)IsConstantImm; + [[maybe_unused]] bool IsConstantImm = + evaluateConstantImm(getImm(), Imm, VK); assert(IsConstantImm && "Invalid VTypeI Operand!"); } else { Imm = getVType(); diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 4dd039159e29..f1ca1212ec37 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -380,8 +380,8 @@ static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder) { uint32_t Rd = fieldFromInstruction(Insn, 7, 5); - DecodeStatus Result = DecodeGPRNoX0RegisterClass(Inst, Rd, Address, Decoder); - (void)Result; + [[maybe_unused]] DecodeStatus Result = + DecodeGPRNoX0RegisterClass(Inst, Rd, Address, Decoder); assert(Result == MCDisassembler::Success && "Invalid register"); Inst.addOperand(Inst.getOperand(0)); Inst.addOperand(MCOperand::createImm(0)); @@ -392,8 +392,8 @@ static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder) { uint32_t Rs1 = fieldFromInstruction(Insn, 7, 5); - DecodeStatus Result = DecodeGPRX1X5RegisterClass(Inst, Rs1, Address, Decoder); - (void)Result; + [[maybe_unused]] DecodeStatus Result = + DecodeGPRX1X5RegisterClass(Inst, Rs1, Address, Decoder); assert(Result == MCDisassembler::Success && "Invalid register"); return MCDisassembler::Success; } @@ -404,8 +404,8 @@ static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, uint32_t Insn, Inst.addOperand(MCOperand::createReg(RISCV::X0)); uint32_t SImm6 = fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); - DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder); - (void)Result; + [[maybe_unused]] DecodeStatus Result = + decodeSImmOperand<6>(Inst, SImm6, Address, Decoder); assert(Result == MCDisassembler::Success && "Invalid immediate"); return MCDisassembler::Success; } @@ -417,8 +417,8 @@ static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, uint32_t Insn, Inst.addOperand(Inst.getOperand(0)); uint32_t UImm6 = fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); - DecodeStatus Result = decodeUImmOperand<6>(Inst, UImm6, Address, Decoder); - (void)Result; + [[maybe_unused]] DecodeStatus Result = + decodeUImmOperand<6>(Inst, UImm6, Address, Decoder); assert(Result == MCDisassembler::Success && "Invalid immediate"); return MCDisassembler::Success; } @@ -454,8 +454,8 @@ static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn, DecodeGPRRegisterClass(Inst, Rd1, Address, Decoder); DecodeGPRRegisterClass(Inst, Rd2, Address, Decoder); DecodeGPRRegisterClass(Inst, Rs1, Address, Decoder); - DecodeStatus Result = decodeUImmOperand<2>(Inst, UImm2, Address, Decoder); - (void)Result; + [[maybe_unused]] DecodeStatus Result = + decodeUImmOperand<2>(Inst, UImm2, Address, Decoder); assert(Result == MCDisassembler::Success && "Invalid immediate"); // Disassemble the final operand which is implicit. diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp index bd49875c9591..182a9c1544fd 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp @@ -186,9 +186,8 @@ void RISCVAsmBackend::relaxInstruction(MCInst &Inst, case RISCV::C_BNEZ: case RISCV::C_J: case RISCV::C_JAL: { - bool Success = RISCVRVC::uncompress(Res, Inst, STI); + [[maybe_unused]] bool Success = RISCVRVC::uncompress(Res, Inst, STI); assert(Success && "Can't uncompress instruction"); - (void)Success; break; } case RISCV::BEQ: @@ -218,9 +217,9 @@ bool RISCVAsmBackend::relaxDwarfLineAddr(MCDwarfLineAddrFragment &DF, size_t OldSize = Data.size(); int64_t Value; - bool IsAbsolute = AddrDelta.evaluateKnownAbsolute(Value, Layout); + [[maybe_unused]] bool IsAbsolute = + AddrDelta.evaluateKnownAbsolute(Value, Layout); assert(IsAbsolute && "CFA with invalid expression"); - (void)IsAbsolute; Data.clear(); Fixups.clear(); @@ -283,9 +282,9 @@ bool RISCVAsmBackend::relaxDwarfCFA(MCDwarfCallFrameFragment &DF, int64_t Value; if (AddrDelta.evaluateAsAbsolute(Value, Layout.getAssembler())) return false; - bool IsAbsolute = AddrDelta.evaluateKnownAbsolute(Value, Layout); + [[maybe_unused]] bool IsAbsolute = + AddrDelta.evaluateKnownAbsolute(Value, Layout); assert(IsAbsolute && "CFA with invalid expression"); - (void)IsAbsolute; Data.clear(); Fixups.clear(); diff --git a/llvm/lib/Target/RISCV/RISCVFoldMasks.cpp b/llvm/lib/Target/RISCV/RISCVFoldMasks.cpp index 6ee006525df5..271d28f86a67 100644 --- a/llvm/lib/Target/RISCV/RISCVFoldMasks.cpp +++ b/llvm/lib/Target/RISCV/RISCVFoldMasks.cpp @@ -146,7 +146,8 @@ bool RISCVFoldMasks::convertToUnmasked(MachineInstr &MI, // everything else. See the comment on RISCVMaskedPseudo for details. const unsigned Opc = I->UnmaskedPseudo; const MCInstrDesc &MCID = TII->get(Opc); - const bool HasPolicyOp = RISCVII::hasVecPolicyOp(MCID.TSFlags); + [[maybe_unused]] const bool HasPolicyOp = + RISCVII::hasVecPolicyOp(MCID.TSFlags); const bool HasPassthru = RISCVII::isFirstDefTiedToFirstUse(MCID); #ifndef NDEBUG const MCInstrDesc &MaskedMCID = TII->get(MI.getOpcode()); diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp index 48ca7b74384c..80797e36ad40 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -2081,10 +2081,10 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) { break; RISCVII::VLMUL SubVecLMUL = RISCVTargetLowering::getLMUL(SubVecContainerVT); - bool IsSubVecPartReg = SubVecLMUL == RISCVII::VLMUL::LMUL_F2 || - SubVecLMUL == RISCVII::VLMUL::LMUL_F4 || - SubVecLMUL == RISCVII::VLMUL::LMUL_F8; - (void)IsSubVecPartReg; // Silence unused variable warning without asserts. + [[maybe_unused]] bool IsSubVecPartReg = + SubVecLMUL == RISCVII::VLMUL::LMUL_F2 || + SubVecLMUL == RISCVII::VLMUL::LMUL_F4 || + SubVecLMUL == RISCVII::VLMUL::LMUL_F8; assert((!IsSubVecPartReg || V.isUndef()) && "Expecting lowering to have created legal INSERT_SUBVECTORs when " "the subvector is smaller than a full-sized register"); @@ -2263,9 +2263,8 @@ bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand( case InlineAsm::ConstraintCode::o: case InlineAsm::ConstraintCode::m: { SDValue Op0, Op1; - bool Found = SelectAddrRegImm(Op, Op0, Op1); + [[maybe_unused]] bool Found = SelectAddrRegImm(Op, Op0, Op1); assert(Found && "SelectAddrRegImm should always succeed"); - (void)Found; OutOps.push_back(Op0); OutOps.push_back(Op1); return false; diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 9f501ea7425d..27037f4d5c5c 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -8512,12 +8512,12 @@ static SDValue lowerGetVectorLength(SDNode *N, SelectionDAG &DAG, // Determine the VF that corresponds to LMUL 1 for ElementWidth. unsigned LMul1VF = RISCV::RVVBitsPerBlock / ElementWidth; // We don't support VF==1 with ELEN==32. - unsigned MinVF = RISCV::RVVBitsPerBlock / Subtarget.getELen(); + [[maybe_unused]] unsigned MinVF = + RISCV::RVVBitsPerBlock / Subtarget.getELen(); - unsigned VF = N->getConstantOperandVal(2); + [[maybe_unused]] unsigned VF = N->getConstantOperandVal(2); assert(VF >= MinVF && VF <= (LMul1VF * 8) && isPowerOf2_32(VF) && "Unexpected VF"); - (void)MinVF; bool Fractional = VF < LMul1VF; unsigned LMulVal = Fractional ? LMul1VF / VF : VF / LMul1VF; @@ -11227,7 +11227,7 @@ SDValue RISCVTargetLowering::lowerMaskedGather(SDValue Op, SDValue Chain = MemSD->getChain(); SDValue BasePtr = MemSD->getBasePtr(); - ISD::LoadExtType LoadExtType; + [[maybe_unused]] ISD::LoadExtType LoadExtType; SDValue Index, Mask, PassThru, VL; if (auto *VPGN = dyn_cast(Op.getNode())) { @@ -11255,7 +11255,6 @@ SDValue RISCVTargetLowering::lowerMaskedGather(SDValue Op, // Targets have to explicitly opt-in for extending vector loads. assert(LoadExtType == ISD::NON_EXTLOAD && "Unexpected extending MGATHER/VP_GATHER"); - (void)LoadExtType; // If the mask is known to be all ones, optimize to an unmasked intrinsic; // the selection of the masked intrinsics doesn't do this for us. @@ -11325,7 +11324,7 @@ SDValue RISCVTargetLowering::lowerMaskedScatter(SDValue Op, SDValue Chain = MemSD->getChain(); SDValue BasePtr = MemSD->getBasePtr(); - bool IsTruncatingStore = false; + [[maybe_unused]] bool IsTruncatingStore = false; SDValue Index, Mask, Val, VL; if (auto *VPSN = dyn_cast(Op.getNode())) { @@ -11354,7 +11353,6 @@ SDValue RISCVTargetLowering::lowerMaskedScatter(SDValue Op, // Targets have to explicitly opt-in for extending vector loads and // truncating vector stores. assert(!IsTruncatingStore && "Unexpected truncating MSCATTER/VP_SCATTER"); - (void)IsTruncatingStore; // If the mask is known to be all ones, optimize to an unmasked intrinsic; // the selection of the masked intrinsics doesn't do this for us. diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index df516d7cd5c0..89eb71d91742 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -1172,7 +1172,6 @@ bool RISCVInstrInfo::optimizeCondBranch(MachineInstr &MI) const { SmallVector Cond; if (analyzeBranch(*MBB, TBB, FBB, Cond, /*AllowModify=*/false)) return false; - (void)FBB; RISCVCC::CondCode CC = static_cast(Cond[0].getImm()); assert(CC != RISCVCC::COND_INVALID); -- GitLab From d53043fa8b2223a1c985e4c74794aa248b4c9e6b Mon Sep 17 00:00:00 2001 From: Adrian Kuegel Date: Tue, 6 Feb 2024 06:45:00 +0000 Subject: [PATCH 030/266] [mlir][Bazel] Adjust BUILD.bazel according to 0d091206dd656c2a9d31d6088a4aa6f9c2cc7156 --- .../llvm-project-overlay/mlir/BUILD.bazel | 51 ++++++++++++++++--- 1 file changed, 44 insertions(+), 7 deletions(-) diff --git a/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel b/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel index 2b547fbfcdec..b136cd3d4bc9 100644 --- a/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel @@ -902,8 +902,8 @@ cc_library( textual_hdrs = glob(MLIR_BINDINGS_PYTHON_HEADERS), deps = [ ":CAPIIRHeaders", - "@pybind11", "@local_config_python//:python_headers", + "@pybind11", ], ) @@ -920,8 +920,8 @@ cc_library( textual_hdrs = glob(MLIR_BINDINGS_PYTHON_HEADERS), deps = [ ":CAPIIR", - "@pybind11", "@local_config_python//:python_headers", + "@pybind11", ], ) @@ -963,8 +963,8 @@ cc_library( ":MLIRBindingsPythonHeadersAndDeps", ":Support", "//llvm:Support", - "@pybind11", "@local_config_python//:python_headers", + "@pybind11", ], ) @@ -983,8 +983,8 @@ cc_library( ":CAPIIRHeaders", ":MLIRBindingsPythonHeaders", "//llvm:Support", - "@pybind11", "@local_config_python//:python_headers", + "@pybind11", ], ) @@ -1094,8 +1094,8 @@ cc_binary( deps = [ ":CAPIExecutionEngine", ":MLIRBindingsPythonHeadersAndDeps", - "@pybind11", "@local_config_python//:python_headers", + "@pybind11", ], ) @@ -1114,8 +1114,8 @@ cc_binary( deps = [ ":CAPILinalg", ":MLIRBindingsPythonHeadersAndDeps", - "@pybind11", "@local_config_python//:python_headers", + "@pybind11", ], ) @@ -6886,8 +6886,8 @@ cc_library( ], deps = [ ":ConversionPassIncGen", - ":FuncDialect", ":EmitCDialect", + ":FuncDialect", ":IR", ":Pass", ":Support", @@ -9039,6 +9039,7 @@ cc_library( ":NVVMDialect", ":NVVMTarget", ":OpenACCDialect", + ":OpenACCTransforms", ":OpenMPDialect", ":OpenMPToLLVM", ":PDLDialect", @@ -9812,6 +9813,42 @@ cc_library( ], ) +gentbl_cc_library( + name = "OpenACCPassIncGen", + tbl_outs = [ + ( + [ + "-gen-pass-decls", + "-name=OpenACC", + ], + "include/mlir/Dialect/OpenACC/Transforms/Passes.h.inc", + ), + ], + tblgen = ":mlir-tblgen", + td_file = "include/mlir/Dialect/OpenACC/Transforms/Passes.td", + deps = [":PassBaseTdFiles"], +) + +cc_library( + name = "OpenACCTransforms", + srcs = glob( + [ + "lib/Dialect/OpenACC/Transforms/*.cpp", + "lib/Dialect/OpenACC/Transforms/*.h", + ], + ), + hdrs = glob(["include/mlir/Dialect/OpenACC/Transforms/*.h"]), + includes = ["include"], + deps = [ + ":FuncDialect", + ":LLVMIRTransforms", + ":OpenACCDialect", + ":OpenACCPassIncGen", + ":Pass", + ":TransformUtils", + ], +) + ## OpenMP dialect # TODO(gcmn): This is sticking td files in a cc_library -- GitLab From 7d055af14b7dd7e782b87fb883205eda65e8bd44 Mon Sep 17 00:00:00 2001 From: Joshua Cao Date: Mon, 5 Feb 2024 22:59:03 -0800 Subject: [PATCH 031/266] [mlir][Symbol] Add verification that symbol's parent is a SymbolTable (#80590) Following the discussion in https://discourse.llvm.org/t/symboltable-and-symbol-parent-child-relationship/75446, we should enforce that a symbol's immediate parent is a symbol table. I changed some tests to pass the verification. In most cases, we can wrap the func with a module, change the func to another op with regions i.e. scf.if, or change the expected error message. --------- Co-authored-by: Mehdi Amini --- mlir/include/mlir/IR/SymbolInterfaces.td | 5 +++ mlir/test/Dialect/LLVMIR/global.mlir | 2 +- .../Dialect/Linalg/transform-op-replace.mlir | 6 ++-- mlir/test/Dialect/Transform/ops-invalid.mlir | 3 +- mlir/test/IR/invalid-func-op.mlir | 4 +-- mlir/test/IR/region.mlir | 7 ++-- mlir/test/IR/traits.mlir | 33 +++++++++-------- mlir/test/Transforms/canonicalize-dce.mlir | 14 ++++---- mlir/test/Transforms/canonicalize.mlir | 13 ++++--- mlir/test/Transforms/constant-fold.mlir | 11 +++--- mlir/test/Transforms/cse.mlir | 11 +++--- mlir/test/Transforms/test-legalizer-full.mlir | 8 +++-- mlir/test/python/ir/value.py | 36 +++---------------- 13 files changed, 68 insertions(+), 85 deletions(-) diff --git a/mlir/include/mlir/IR/SymbolInterfaces.td b/mlir/include/mlir/IR/SymbolInterfaces.td index 844601f8f683..60b38185fa8c 100644 --- a/mlir/include/mlir/IR/SymbolInterfaces.td +++ b/mlir/include/mlir/IR/SymbolInterfaces.td @@ -171,6 +171,11 @@ def Symbol : OpInterface<"SymbolOpInterface"> { if (concreteOp.isDeclaration() && concreteOp.isPublic()) return concreteOp.emitOpError("symbol declaration cannot have public " "visibility"); + auto parent = $_op->getParentOp(); + if (parent && !parent->hasTrait() && parent->isRegistered()) { + return concreteOp.emitOpError("symbol's parent must have the SymbolTable " + "trait"); + } return success(); }]; diff --git a/mlir/test/Dialect/LLVMIR/global.mlir b/mlir/test/Dialect/LLVMIR/global.mlir index 0649e814bfdf..3fa7636d4dd6 100644 --- a/mlir/test/Dialect/LLVMIR/global.mlir +++ b/mlir/test/Dialect/LLVMIR/global.mlir @@ -132,7 +132,7 @@ llvm.mlir.global internal constant @constant(37.0) : !llvm.label // ----- func.func @foo() { - // expected-error @+1 {{must appear at the module level}} + // expected-error @+1 {{op symbol's parent must have the SymbolTable trait}} llvm.mlir.global internal @bar(42) : i32 return diff --git a/mlir/test/Dialect/Linalg/transform-op-replace.mlir b/mlir/test/Dialect/Linalg/transform-op-replace.mlir index 2801522e81ac..1a40912977de 100644 --- a/mlir/test/Dialect/Linalg/transform-op-replace.mlir +++ b/mlir/test/Dialect/Linalg/transform-op-replace.mlir @@ -12,8 +12,10 @@ module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["func.func"]} in %arg1 : (!transform.any_op) -> !transform.any_op transform.structured.replace %0 { - func.func @foo() { - "dummy_op"() : () -> () + builtin.module { + func.func @foo() { + "dummy_op"() : () -> () + } } } : (!transform.any_op) -> !transform.any_op transform.yield diff --git a/mlir/test/Dialect/Transform/ops-invalid.mlir b/mlir/test/Dialect/Transform/ops-invalid.mlir index e3f5bcf403f2..73a5f36af929 100644 --- a/mlir/test/Dialect/Transform/ops-invalid.mlir +++ b/mlir/test/Dialect/Transform/ops-invalid.mlir @@ -433,10 +433,9 @@ module { // ----- module attributes { transform.with_named_sequence} { - // expected-note @below {{ancestor transform op}} transform.sequence failures(suppress) { ^bb0(%arg0: !transform.any_op): - // expected-error @below {{cannot be defined inside another transform op}} + // expected-error @below {{op symbol's parent must have the SymbolTable trai}} transform.named_sequence @nested() { transform.yield } diff --git a/mlir/test/IR/invalid-func-op.mlir b/mlir/test/IR/invalid-func-op.mlir index d995689ebb8d..8fd7af22e959 100644 --- a/mlir/test/IR/invalid-func-op.mlir +++ b/mlir/test/IR/invalid-func-op.mlir @@ -31,7 +31,7 @@ func.func @func_op() { // ----- func.func @func_op() { - // expected-error@+1 {{entry block must have 1 arguments to match function signature}} + // expected-error@+1 {{op symbol's parent must have the SymbolTable trait}} func.func @mixed_named_arguments(f32) { ^entry: return @@ -42,7 +42,7 @@ func.func @func_op() { // ----- func.func @func_op() { - // expected-error@+1 {{type of entry block argument #0('i32') must match the type of the corresponding argument in function signature('f32')}} + // expected-error@+1 {{op symbol's parent must have the SymbolTable trait}} func.func @mixed_named_arguments(f32) { ^entry(%arg : i32): return diff --git a/mlir/test/IR/region.mlir b/mlir/test/IR/region.mlir index bf4b1bb4e5ab..0b959915d6bb 100644 --- a/mlir/test/IR/region.mlir +++ b/mlir/test/IR/region.mlir @@ -87,18 +87,17 @@ func.func @named_region_has_wrong_number_of_blocks() { // CHECK: test.single_no_terminator_op "test.single_no_terminator_op"() ( { - func.func @foo1() { return } - func.func @foo2() { return } + %foo = arith.constant 1 : i32 } ) : () -> () // CHECK: test.variadic_no_terminator_op "test.variadic_no_terminator_op"() ( { - func.func @foo1() { return } + %foo = arith.constant 1 : i32 }, { - func.func @foo2() { return } + %bar = arith.constant 1 : i32 } ) : () -> () diff --git a/mlir/test/IR/traits.mlir b/mlir/test/IR/traits.mlir index 0402ebe75875..1e046706379c 100644 --- a/mlir/test/IR/traits.mlir +++ b/mlir/test/IR/traits.mlir @@ -572,15 +572,13 @@ func.func @failedHasDominanceScopeOutsideDominanceFreeScope() -> () { // Ensure that SSACFG regions of operations in GRAPH regions are // checked for dominance -func.func @illegalInsideDominanceFreeScope() -> () { +func.func @illegalInsideDominanceFreeScope(%cond: i1) -> () { test.graph_region { - func.func @test() -> i1 { - ^bb1: + scf.if %cond { // expected-error @+1 {{operand #0 does not dominate this use}} %2:3 = "bar"(%1) : (i64) -> (i1,i1,i1) // expected-note @+1 {{operand defined here}} - %1 = "baz"(%2#0) : (i1) -> (i64) - return %2#1 : i1 + %1 = "baz"(%2#0) : (i1) -> (i64) } "terminator"() : () -> () } @@ -591,20 +589,21 @@ func.func @illegalInsideDominanceFreeScope() -> () { // Ensure that SSACFG regions of operations in GRAPH regions are // checked for dominance -func.func @illegalCDFGInsideDominanceFreeScope() -> () { +func.func @illegalCFGInsideDominanceFreeScope(%cond: i1) -> () { test.graph_region { - func.func @test() -> i1 { - ^bb1: - // expected-error @+1 {{operand #0 does not dominate this use}} - %2:3 = "bar"(%1) : (i64) -> (i1,i1,i1) - cf.br ^bb4 - ^bb2: - cf.br ^bb2 - ^bb4: - %1 = "foo"() : ()->i64 // expected-note {{operand defined here}} - return %2#1 : i1 + scf.if %cond { + "test.ssacfg_region"() ({ + ^bb1: + // expected-error @+1 {{operand #0 does not dominate this use}} + %2:3 = "bar"(%1) : (i64) -> (i1,i1,i1) + cf.br ^bb4 + ^bb2: + cf.br ^bb2 + ^bb4: + %1 = "foo"() : ()->i64 // expected-note {{operand defined here}} + }) : () -> () } - "terminator"() : () -> () + "terminator"() : () -> () } return } diff --git a/mlir/test/Transforms/canonicalize-dce.mlir b/mlir/test/Transforms/canonicalize-dce.mlir index 46545d2e9fd5..3048a7fed636 100644 --- a/mlir/test/Transforms/canonicalize-dce.mlir +++ b/mlir/test/Transforms/canonicalize-dce.mlir @@ -77,15 +77,15 @@ func.func @f(%arg0: f32, %pred: i1) { // Test case: Recursively DCE into enclosed regions. -// CHECK: func @f(%arg0: f32) -// CHECK-NEXT: func @g(%arg1: f32) -// CHECK-NEXT: return +// CHECK: func.func @f(%arg0: f32) +// CHECK-NOT: arith.addf func.func @f(%arg0: f32) { - func.func @g(%arg1: f32) { - %0 = "arith.addf"(%arg1, %arg1) : (f32, f32) -> f32 - return - } + "test.region"() ( + { + %0 = "arith.addf"(%arg0, %arg0) : (f32, f32) -> f32 + } + ) : () -> () return } diff --git a/mlir/test/Transforms/canonicalize.mlir b/mlir/test/Transforms/canonicalize.mlir index 9b578e6c2631..2cf86b50d432 100644 --- a/mlir/test/Transforms/canonicalize.mlir +++ b/mlir/test/Transforms/canonicalize.mlir @@ -424,16 +424,15 @@ func.func @write_only_alloca_fold(%v: f32) { // CHECK-LABEL: func @dead_block_elim func.func @dead_block_elim() { // CHECK-NOT: ^bb - func.func @nested() { - return + builtin.module { + func.func @nested() { + return - ^bb1: - return + ^bb1: + return + } } return - -^bb1: - return } // CHECK-LABEL: func @dyn_shape_fold(%arg0: index, %arg1: index) diff --git a/mlir/test/Transforms/constant-fold.mlir b/mlir/test/Transforms/constant-fold.mlir index 45ee03fa31d2..253163f2af91 100644 --- a/mlir/test/Transforms/constant-fold.mlir +++ b/mlir/test/Transforms/constant-fold.mlir @@ -756,12 +756,15 @@ func.func @cmpf_inf() -> (i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1 // CHECK-LABEL: func @nested_isolated_region func.func @nested_isolated_region() { + // CHECK-NEXT: builtin.module { // CHECK-NEXT: func @isolated_op // CHECK-NEXT: arith.constant 2 - func.func @isolated_op() { - %0 = arith.constant 1 : i32 - %2 = arith.addi %0, %0 : i32 - "foo.yield"(%2) : (i32) -> () + builtin.module { + func.func @isolated_op() { + %0 = arith.constant 1 : i32 + %2 = arith.addi %0, %0 : i32 + "foo.yield"(%2) : (i32) -> () + } } // CHECK: "foo.unknown_region" diff --git a/mlir/test/Transforms/cse.mlir b/mlir/test/Transforms/cse.mlir index c764d2b9bd57..11a331026847 100644 --- a/mlir/test/Transforms/cse.mlir +++ b/mlir/test/Transforms/cse.mlir @@ -228,11 +228,14 @@ func.func @nested_isolated() -> i32 { // CHECK-NEXT: arith.constant 1 %0 = arith.constant 1 : i32 + // CHECK-NEXT: builtin.module // CHECK-NEXT: @nested_func - func.func @nested_func() { - // CHECK-NEXT: arith.constant 1 - %foo = arith.constant 1 : i32 - "foo.yield"(%foo) : (i32) -> () + builtin.module { + func.func @nested_func() { + // CHECK-NEXT: arith.constant 1 + %foo = arith.constant 1 : i32 + "foo.yield"(%foo) : (i32) -> () + } } // CHECK: "foo.region" diff --git a/mlir/test/Transforms/test-legalizer-full.mlir b/mlir/test/Transforms/test-legalizer-full.mlir index 74f312e8144a..5f1148cac650 100644 --- a/mlir/test/Transforms/test-legalizer-full.mlir +++ b/mlir/test/Transforms/test-legalizer-full.mlir @@ -37,9 +37,11 @@ func.func @recursively_legal_invalid_op() { } /// Operation that is dynamically legal, i.e. the function has a pattern /// applied to legalize the argument type before it becomes recursively legal. - func.func @dynamic_func(%arg: i64) attributes {test.recursively_legal} { - %ignored = "test.illegal_op_f"() : () -> (i32) - "test.return"() : () -> () + builtin.module { + func.func @dynamic_func(%arg: i64) attributes {test.recursively_legal} { + %ignored = "test.illegal_op_f"() : () -> (i32) + "test.return"() : () -> () + } } "test.return"() : () -> () diff --git a/mlir/test/python/ir/value.py b/mlir/test/python/ir/value.py index acbf463113a6..28ef0f2ef3e2 100644 --- a/mlir/test/python/ir/value.py +++ b/mlir/test/python/ir/value.py @@ -167,28 +167,15 @@ def testValuePrintAsOperand(): print(value2) topFn = func.FuncOp("test", ([i32, i32], [])) - entry_block1 = Block.create_at_start(topFn.operation.regions[0], [i32, i32]) + entry_block = Block.create_at_start(topFn.operation.regions[0], [i32, i32]) - with InsertionPoint(entry_block1): + with InsertionPoint(entry_block): value3 = Operation.create("custom.op3", results=[i32]).results[0] # CHECK: Value(%[[VAL3:.*]] = "custom.op3"() : () -> i32) print(value3) value4 = Operation.create("custom.op4", results=[i32]).results[0] # CHECK: Value(%[[VAL4:.*]] = "custom.op4"() : () -> i32) print(value4) - - f = func.FuncOp("test", ([i32, i32], [])) - entry_block2 = Block.create_at_start(f.operation.regions[0], [i32, i32]) - with InsertionPoint(entry_block2): - value5 = Operation.create("custom.op5", results=[i32]).results[0] - # CHECK: Value(%[[VAL5:.*]] = "custom.op5"() : () -> i32) - print(value5) - value6 = Operation.create("custom.op6", results=[i32]).results[0] - # CHECK: Value(%[[VAL6:.*]] = "custom.op6"() : () -> i32) - print(value6) - - func.ReturnOp([]) - func.ReturnOp([]) # CHECK: %[[VAL1]] @@ -215,20 +202,10 @@ def testValuePrintAsOperand(): # CHECK: %1 print(value4.get_name(use_local_scope=True)) - # CHECK: %[[VAL5]] - print(value5.get_name()) - # CHECK: %[[VAL6]] - print(value6.get_name()) - # CHECK: %[[ARG0:.*]] - print(entry_block1.arguments[0].get_name()) + print(entry_block.arguments[0].get_name()) # CHECK: %[[ARG1:.*]] - print(entry_block1.arguments[1].get_name()) - - # CHECK: %[[ARG2:.*]] - print(entry_block2.arguments[0].get_name()) - # CHECK: %[[ARG3:.*]] - print(entry_block2.arguments[1].get_name()) + print(entry_block.arguments[1].get_name()) # CHECK: module { # CHECK: %[[VAL1]] = "custom.op1"() : () -> i32 @@ -236,11 +213,6 @@ def testValuePrintAsOperand(): # CHECK: func.func @test(%[[ARG0]]: i32, %[[ARG1]]: i32) { # CHECK: %[[VAL3]] = "custom.op3"() : () -> i32 # CHECK: %[[VAL4]] = "custom.op4"() : () -> i32 - # CHECK: func @test(%[[ARG2]]: i32, %[[ARG3]]: i32) { - # CHECK: %[[VAL5]] = "custom.op5"() : () -> i32 - # CHECK: %[[VAL6]] = "custom.op6"() : () -> i32 - # CHECK: return - # CHECK: } # CHECK: return # CHECK: } # CHECK: } -- GitLab From 47a12cca442cb52c33fc592183998f3b7bdd5094 Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Tue, 6 Feb 2024 16:12:07 +0900 Subject: [PATCH 032/266] CoverageMapping.cpp: s/MaxBitmapID/MaxBitmapIdx/ in getMaxBitmapSize() --- llvm/lib/ProfileData/Coverage/CoverageMapping.cpp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp b/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp index 39e43f86eab5..f2b4b5ce0b23 100644 --- a/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp +++ b/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp @@ -491,20 +491,20 @@ static unsigned getMaxCounterID(const CounterMappingContext &Ctx, /// Returns the bit count static unsigned getMaxBitmapSize(const CounterMappingContext &Ctx, const CoverageMappingRecord &Record) { - unsigned MaxBitmapID = 0; + unsigned MaxBitmapIdx = 0; unsigned NumConditions = 0; // Scan max(BitmapIdx). // Note that `<=` is used insted of `<`, because `BitmapIdx == 0` is valid - // and `MaxBitmapID is `unsigned`. `BitmapIdx` is unique in the record. + // and `MaxBitmapIdx is `unsigned`. `BitmapIdx` is unique in the record. for (const auto &Region : reverse(Record.MappingRegions)) { if (Region.Kind == CounterMappingRegion::MCDCDecisionRegion && - MaxBitmapID <= Region.MCDCParams.BitmapIdx) { - MaxBitmapID = Region.MCDCParams.BitmapIdx; + MaxBitmapIdx <= Region.MCDCParams.BitmapIdx) { + MaxBitmapIdx = Region.MCDCParams.BitmapIdx; NumConditions = Region.MCDCParams.NumConditions; } } unsigned SizeInBits = llvm::alignTo(uint64_t(1) << NumConditions, CHAR_BIT); - return MaxBitmapID * CHAR_BIT + SizeInBits; + return MaxBitmapIdx * CHAR_BIT + SizeInBits; } namespace { -- GitLab From 03881dc0a7695f4c499cc07042b8c59ad7b7335a Mon Sep 17 00:00:00 2001 From: Marius Brehler Date: Tue, 6 Feb 2024 08:49:10 +0100 Subject: [PATCH 033/266] [mlir][emitc] Add a `declare_func` operation (#80297) This adds the `emitc.declare_func` operation that allows to emit the declaration of an `emitc.func` at a specific location. --- mlir/include/mlir/Dialect/EmitC/IR/EmitC.td | 42 +++++++++++++++++++ mlir/lib/Dialect/EmitC/IR/EmitC.cpp | 18 +++++++++ mlir/lib/Target/Cpp/TranslateToCpp.cpp | 45 ++++++++++++++++++--- mlir/test/Dialect/EmitC/invalid_ops.mlir | 10 +++++ mlir/test/Dialect/EmitC/ops.mlir | 2 + mlir/test/Target/Cpp/declare_func.mlir | 16 ++++++++ 6 files changed, 127 insertions(+), 6 deletions(-) create mode 100644 mlir/test/Target/Cpp/declare_func.mlir diff --git a/mlir/include/mlir/Dialect/EmitC/IR/EmitC.td b/mlir/include/mlir/Dialect/EmitC/IR/EmitC.td index 6871948d14cf..39cc360cef41 100644 --- a/mlir/include/mlir/Dialect/EmitC/IR/EmitC.td +++ b/mlir/include/mlir/Dialect/EmitC/IR/EmitC.td @@ -460,6 +460,48 @@ def EmitC_CallOp : EmitC_Op<"call", }]; } +def EmitC_DeclareFuncOp : EmitC_Op<"declare_func", [ + DeclareOpInterfaceMethods +]> { + let summary = "An operation to declare a function"; + let description = [{ + The `declare_func` operation allows to insert a function declaration for an + `emitc.func` at a specific position. The operation only requires the `callee` + of the `emitc.func` to be specified as an attribute. + + Example: + + ```mlir + emitc.declare_func @bar + emitc.func @foo(%arg0: i32) -> i32 { + %0 = emitc.call @bar(%arg0) : (i32) -> (i32) + emitc.return %0 : i32 + } + + emitc.func @bar(%arg0: i32) -> i32 { + emitc.return %arg0 : i32 + } + ``` + + ```c++ + // Code emitted for the operations above. + int32_t bar(int32_t v1); + int32_t foo(int32_t v1) { + int32_t v2 = bar(v1); + return v2; + } + + int32_t bar(int32_t v1) { + return v1; + } + ``` + }]; + let arguments = (ins FlatSymbolRefAttr:$sym_name); + let assemblyFormat = [{ + $sym_name attr-dict + }]; +} + def EmitC_FuncOp : EmitC_Op<"func", [ AutomaticAllocationScope, FunctionOpInterface, IsolatedFromAbove diff --git a/mlir/lib/Dialect/EmitC/IR/EmitC.cpp b/mlir/lib/Dialect/EmitC/IR/EmitC.cpp index f384fcbefcfd..0fe2c0dcfc7c 100644 --- a/mlir/lib/Dialect/EmitC/IR/EmitC.cpp +++ b/mlir/lib/Dialect/EmitC/IR/EmitC.cpp @@ -393,6 +393,24 @@ FunctionType CallOp::getCalleeType() { return FunctionType::get(getContext(), getOperandTypes(), getResultTypes()); } +//===----------------------------------------------------------------------===// +// DeclareFuncOp +//===----------------------------------------------------------------------===// + +LogicalResult +DeclareFuncOp::verifySymbolUses(SymbolTableCollection &symbolTable) { + // Check that the sym_name attribute was specified. + auto fnAttr = getSymNameAttr(); + if (!fnAttr) + return emitOpError("requires a 'sym_name' symbol reference attribute"); + FuncOp fn = symbolTable.lookupNearestSymbolFrom(*this, fnAttr); + if (!fn) + return emitOpError() << "'" << fnAttr.getValue() + << "' does not reference a valid function"; + + return success(); +} + //===----------------------------------------------------------------------===// // FuncOp //===----------------------------------------------------------------------===// diff --git a/mlir/lib/Target/Cpp/TranslateToCpp.cpp b/mlir/lib/Target/Cpp/TranslateToCpp.cpp index 0e73122dcc0b..a53d7d1701a9 100644 --- a/mlir/lib/Target/Cpp/TranslateToCpp.cpp +++ b/mlir/lib/Target/Cpp/TranslateToCpp.cpp @@ -14,6 +14,7 @@ #include "mlir/IR/BuiltinTypes.h" #include "mlir/IR/Dialect.h" #include "mlir/IR/Operation.h" +#include "mlir/IR/SymbolTable.h" #include "mlir/Support/IndentedOstream.h" #include "mlir/Support/LLVM.h" #include "mlir/Target/Cpp/CppEmitter.h" @@ -855,8 +856,9 @@ static LogicalResult printFunctionBody(CppEmitter &emitter, // needs to be printed after the closing brace. // When generating code for an emitc.for and emitc.verbatim op, printing a // trailing semicolon is handled within the printOperation function. - bool trailingSemicolon = !isa(op); + bool trailingSemicolon = + !isa(op); if (failed(emitter.emitOperation( op, /*trailingSemicolon=*/trailingSemicolon))) @@ -938,6 +940,37 @@ static LogicalResult printOperation(CppEmitter &emitter, return success(); } +static LogicalResult printOperation(CppEmitter &emitter, + DeclareFuncOp declareFuncOp) { + CppEmitter::Scope scope(emitter); + raw_indented_ostream &os = emitter.ostream(); + + auto functionOp = SymbolTable::lookupNearestSymbolFrom( + declareFuncOp, declareFuncOp.getSymNameAttr()); + + if (!functionOp) + return failure(); + + if (functionOp.getSpecifiers()) { + for (Attribute specifier : functionOp.getSpecifiersAttr()) { + os << cast(specifier).str() << " "; + } + } + + if (failed(emitter.emitTypes(functionOp.getLoc(), + functionOp.getFunctionType().getResults()))) + return failure(); + os << " " << functionOp.getName(); + + os << "("; + Operation *operation = functionOp.getOperation(); + if (failed(printFunctionArgs(emitter, operation, functionOp.getArguments()))) + return failure(); + os << ");"; + + return success(); +} + CppEmitter::CppEmitter(raw_ostream &os, bool declareVariablesAtTop) : os(os), declareVariablesAtTop(declareVariablesAtTop) { valueInScopeCount.push(0); @@ -1251,10 +1284,10 @@ LogicalResult CppEmitter::emitOperation(Operation &op, bool trailingSemicolon) { // EmitC ops. .Case( + emitc::ConstantOp, emitc::DeclareFuncOp, emitc::DivOp, + emitc::ExpressionOp, emitc::ForOp, emitc::FuncOp, emitc::IfOp, + emitc::IncludeOp, emitc::MulOp, emitc::RemOp, emitc::ReturnOp, + emitc::SubOp, emitc::VariableOp, emitc::VerbatimOp>( [&](auto op) { return printOperation(*this, op); }) // Func ops. .Case( diff --git a/mlir/test/Dialect/EmitC/invalid_ops.mlir b/mlir/test/Dialect/EmitC/invalid_ops.mlir index 6d2471b4d2b4..121a2163d383 100644 --- a/mlir/test/Dialect/EmitC/invalid_ops.mlir +++ b/mlir/test/Dialect/EmitC/invalid_ops.mlir @@ -321,3 +321,13 @@ func.func @return_inside_func.func(%0: i32) -> (i32) { // expected-error@+1 {{expected non-function type}} emitc.func @func_variadic(...) + +// ----- + +// expected-error@+1 {{'emitc.declare_func' op 'bar' does not reference a valid function}} +emitc.declare_func @bar + +// ----- + +// expected-error@+1 {{'emitc.declare_func' op requires attribute 'sym_name'}} +"emitc.declare_func"() : () -> () diff --git a/mlir/test/Dialect/EmitC/ops.mlir b/mlir/test/Dialect/EmitC/ops.mlir index e03c3d58c3e8..93119be14c90 100644 --- a/mlir/test/Dialect/EmitC/ops.mlir +++ b/mlir/test/Dialect/EmitC/ops.mlir @@ -15,6 +15,8 @@ func.func @f(%arg0: i32, %f: !emitc.opaque<"int32_t">) { return } +emitc.declare_func @func + emitc.func @func(%arg0 : i32) { emitc.call_opaque "foo"(%arg0) : (i32) -> () emitc.return diff --git a/mlir/test/Target/Cpp/declare_func.mlir b/mlir/test/Target/Cpp/declare_func.mlir new file mode 100644 index 000000000000..72c087a3388e --- /dev/null +++ b/mlir/test/Target/Cpp/declare_func.mlir @@ -0,0 +1,16 @@ +// RUN: mlir-translate -mlir-to-cpp %s | FileCheck %s + +// CHECK: int32_t bar(int32_t [[V1:[^ ]*]]); +emitc.declare_func @bar +// CHECK: int32_t bar(int32_t [[V1:[^ ]*]]) { +emitc.func @bar(%arg0: i32) -> i32 { + emitc.return %arg0 : i32 +} + + +// CHECK: static inline int32_t foo(int32_t [[V1:[^ ]*]]); +emitc.declare_func @foo +// CHECK: static inline int32_t foo(int32_t [[V1:[^ ]*]]) { +emitc.func @foo(%arg0: i32) -> i32 attributes {specifiers = ["static","inline"]} { + emitc.return %arg0 : i32 +} -- GitLab From 38476b063f164995b85e47472e3c2e0a9c5f9075 Mon Sep 17 00:00:00 2001 From: Aiden Grossman Date: Mon, 5 Feb 2024 23:49:34 -0800 Subject: [PATCH 034/266] [Github] Add script to count running jobs (#80250) This patch adds a script to automatically query the number of running jobs and print them to the terminal as this functionality isn't available through the Github UI (unless you are a Github administrator). --- llvm/utils/count_running_jobs.py | 49 ++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 llvm/utils/count_running_jobs.py diff --git a/llvm/utils/count_running_jobs.py b/llvm/utils/count_running_jobs.py new file mode 100644 index 000000000000..a53bc02f7b0a --- /dev/null +++ b/llvm/utils/count_running_jobs.py @@ -0,0 +1,49 @@ +# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +# See https://llvm.org/LICENSE.txt for license information. +# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +"""Tool for counting the number of currently running Github actions jobs. + +This tool counts and enumerates the currently active jobs in Github actions +for the monorepo. + +python3 ./count_running_jobs.py --token= + +Note that the token argument is optional. If it is not specified, the queries +will be performed unauthenticated. +""" + +import argparse +import github + + +def main(token): + workflows = ( + github.Github(args.token) + .get_repo("llvm/llvm-project") + .get_workflow_runs(status="in_progress") + ) + + in_progress_jobs = 0 + + for workflow in workflows: + for job in workflow.jobs(): + if job.status == "in_progress": + print(f"{workflow.name}/{job.name}") + in_progress_jobs += 1 + + print(f"\nFound {in_progress_jobs} running jobs.") + + +if __name__ == "__main__": + parser = argparse.ArgumentParser( + description="A tool for listing and counting Github actions jobs" + ) + parser.add_argument( + "--token", + type=str, + help="The Github token to use to authorize with the API", + default=None, + nargs="?", + ) + args = parser.parse_args() + main(args.token) -- GitLab From 0b62218110f0945c6957e549f9fc1a2f2f87a604 Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Tue, 6 Feb 2024 17:15:38 +0900 Subject: [PATCH 035/266] Anonymize `MCDCRecordProcessor` --- llvm/lib/ProfileData/Coverage/CoverageMapping.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp b/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp index f2b4b5ce0b23..6b189c314632 100644 --- a/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp +++ b/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp @@ -223,6 +223,8 @@ Expected CounterMappingContext::evaluate(const Counter &C) const { return LastPoppedValue; } +namespace { + class MCDCRecordProcessor { /// A bitmap representing the executed test vectors for a boolean expression. /// Each index of the bitmap corresponds to a possible test vector. An index @@ -398,6 +400,8 @@ public: } }; +} // namespace + Expected CounterMappingContext::evaluateMCDCRegion( const CounterMappingRegion &Region, ArrayRef Branches) { -- GitLab From 933247d9d6a2aee66de49e84077ce116630e76cd Mon Sep 17 00:00:00 2001 From: Anton Sidorenko Date: Tue, 6 Feb 2024 12:02:06 +0300 Subject: [PATCH 036/266] [SimplifyLibCalls] Merge sqrt into the power of exp (#79146) Under fast-math flags it's possible to convert `sqrt(exp(X)) `into `exp(X * 0.5)`. I suppose that this transformation is always profitable. This is similar to the optimization existing in GCC. --- .../llvm/Transforms/Utils/SimplifyLibCalls.h | 1 + .../lib/Transforms/Utils/SimplifyLibCalls.cpp | 67 ++++++++++ llvm/test/Transforms/InstCombine/sqrt.ll | 120 ++++++++++++++++++ 3 files changed, 188 insertions(+) diff --git a/llvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h b/llvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h index eb10545ee149..1aad0b298845 100644 --- a/llvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h +++ b/llvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h @@ -201,6 +201,7 @@ private: Value *optimizeFMinFMax(CallInst *CI, IRBuilderBase &B); Value *optimizeLog(CallInst *CI, IRBuilderBase &B); Value *optimizeSqrt(CallInst *CI, IRBuilderBase &B); + Value *mergeSqrtToExp(CallInst *CI, IRBuilderBase &B); Value *optimizeSinCosPi(CallInst *CI, bool IsSin, IRBuilderBase &B); Value *optimizeTan(CallInst *CI, IRBuilderBase &B); // Wrapper for all floating point library call optimizations diff --git a/llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp b/llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp index 9e9d09757e18..f79549f79389 100644 --- a/llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp +++ b/llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp @@ -2545,6 +2545,70 @@ Value *LibCallSimplifier::optimizeLog(CallInst *Log, IRBuilderBase &B) { return Ret; } +// sqrt(exp(X)) -> exp(X * 0.5) +Value *LibCallSimplifier::mergeSqrtToExp(CallInst *CI, IRBuilderBase &B) { + if (!CI->hasAllowReassoc()) + return nullptr; + + Function *SqrtFn = CI->getCalledFunction(); + CallInst *Arg = dyn_cast(CI->getArgOperand(0)); + if (!Arg || !Arg->hasAllowReassoc() || !Arg->hasOneUse()) + return nullptr; + Intrinsic::ID ArgID = Arg->getIntrinsicID(); + LibFunc ArgLb = NotLibFunc; + TLI->getLibFunc(*Arg, ArgLb); + + LibFunc SqrtLb, ExpLb, Exp2Lb, Exp10Lb; + + if (TLI->getLibFunc(SqrtFn->getName(), SqrtLb)) + switch (SqrtLb) { + case LibFunc_sqrtf: + ExpLb = LibFunc_expf; + Exp2Lb = LibFunc_exp2f; + Exp10Lb = LibFunc_exp10f; + break; + case LibFunc_sqrt: + ExpLb = LibFunc_exp; + Exp2Lb = LibFunc_exp2; + Exp10Lb = LibFunc_exp10; + break; + case LibFunc_sqrtl: + ExpLb = LibFunc_expl; + Exp2Lb = LibFunc_exp2l; + Exp10Lb = LibFunc_exp10l; + break; + default: + return nullptr; + } + else if (SqrtFn->getIntrinsicID() == Intrinsic::sqrt) { + if (CI->getType()->getScalarType()->isFloatTy()) { + ExpLb = LibFunc_expf; + Exp2Lb = LibFunc_exp2f; + Exp10Lb = LibFunc_exp10f; + } else if (CI->getType()->getScalarType()->isDoubleTy()) { + ExpLb = LibFunc_exp; + Exp2Lb = LibFunc_exp2; + Exp10Lb = LibFunc_exp10; + } else + return nullptr; + } else + return nullptr; + + if (ArgLb != ExpLb && ArgLb != Exp2Lb && ArgLb != Exp10Lb && + ArgID != Intrinsic::exp && ArgID != Intrinsic::exp2) + return nullptr; + + IRBuilderBase::InsertPointGuard Guard(B); + B.SetInsertPoint(Arg); + auto *ExpOperand = Arg->getOperand(0); + auto *FMul = + B.CreateFMulFMF(ExpOperand, ConstantFP::get(ExpOperand->getType(), 0.5), + CI, "merged.sqrt"); + + Arg->setOperand(0, FMul); + return Arg; +} + Value *LibCallSimplifier::optimizeSqrt(CallInst *CI, IRBuilderBase &B) { Module *M = CI->getModule(); Function *Callee = CI->getCalledFunction(); @@ -2557,6 +2621,9 @@ Value *LibCallSimplifier::optimizeSqrt(CallInst *CI, IRBuilderBase &B) { Callee->getIntrinsicID() == Intrinsic::sqrt)) Ret = optimizeUnaryDoubleFP(CI, B, TLI, true); + if (Value *Opt = mergeSqrtToExp(CI, B)) + return Opt; + if (!CI->isFast()) return Ret; diff --git a/llvm/test/Transforms/InstCombine/sqrt.ll b/llvm/test/Transforms/InstCombine/sqrt.ll index 004df3e30c72..f72fe5a6a581 100644 --- a/llvm/test/Transforms/InstCombine/sqrt.ll +++ b/llvm/test/Transforms/InstCombine/sqrt.ll @@ -88,7 +88,127 @@ define float @sqrt_call_fabs_f32(float %x) { ret float %sqrt } +define double @sqrt_exp(double %x) { +; CHECK-LABEL: @sqrt_exp( +; CHECK-NEXT: [[MERGED_SQRT:%.*]] = fmul reassoc double [[X:%.*]], 5.000000e-01 +; CHECK-NEXT: [[E:%.*]] = call reassoc double @llvm.exp.f64(double [[MERGED_SQRT]]) +; CHECK-NEXT: ret double [[E]] +; + %e = call reassoc double @llvm.exp.f64(double %x) + %res = call reassoc double @llvm.sqrt.f64(double %e) + ret double %res +} + +define double @sqrt_exp_2(double %x) { +; CHECK-LABEL: @sqrt_exp_2( +; CHECK-NEXT: [[MERGED_SQRT:%.*]] = fmul reassoc double [[X:%.*]], 5.000000e-01 +; CHECK-NEXT: [[E:%.*]] = call reassoc double @exp(double [[MERGED_SQRT]]) +; CHECK-NEXT: ret double [[E]] +; + %e = call reassoc double @exp(double %x) + %res = call reassoc double @sqrt(double %e) + ret double %res +} + +define double @sqrt_exp2(double %x) { +; CHECK-LABEL: @sqrt_exp2( +; CHECK-NEXT: [[MERGED_SQRT:%.*]] = fmul reassoc double [[X:%.*]], 5.000000e-01 +; CHECK-NEXT: [[E:%.*]] = call reassoc double @exp2(double [[MERGED_SQRT]]) +; CHECK-NEXT: ret double [[E]] +; + %e = call reassoc double @exp2(double %x) + %res = call reassoc double @sqrt(double %e) + ret double %res +} + +define double @sqrt_exp10(double %x) { +; CHECK-LABEL: @sqrt_exp10( +; CHECK-NEXT: [[MERGED_SQRT:%.*]] = fmul reassoc double [[X:%.*]], 5.000000e-01 +; CHECK-NEXT: [[E:%.*]] = call reassoc double @exp10(double [[MERGED_SQRT]]) +; CHECK-NEXT: ret double [[E]] +; + %e = call reassoc double @exp10(double %x) + %res = call reassoc double @sqrt(double %e) + ret double %res +} + +; Negative test +define double @sqrt_exp_nofast_1(double %x) { +; CHECK-LABEL: @sqrt_exp_nofast_1( +; CHECK-NEXT: [[E:%.*]] = call double @llvm.exp.f64(double [[X:%.*]]) +; CHECK-NEXT: [[RES:%.*]] = call reassoc double @llvm.sqrt.f64(double [[E]]) +; CHECK-NEXT: ret double [[RES]] +; + %e = call double @llvm.exp.f64(double %x) + %res = call reassoc double @llvm.sqrt.f64(double %e) + ret double %res +} + +; Negative test +define double @sqrt_exp_nofast_2(double %x) { +; CHECK-LABEL: @sqrt_exp_nofast_2( +; CHECK-NEXT: [[E:%.*]] = call reassoc double @llvm.exp.f64(double [[X:%.*]]) +; CHECK-NEXT: [[RES:%.*]] = call double @llvm.sqrt.f64(double [[E]]) +; CHECK-NEXT: ret double [[RES]] +; + %e = call reassoc double @llvm.exp.f64(double %x) + %res = call double @llvm.sqrt.f64(double %e) + ret double %res +} + +define double @sqrt_exp_merge_constant(double %x, double %y) { +; CHECK-LABEL: @sqrt_exp_merge_constant( +; CHECK-NEXT: [[MERGED_SQRT:%.*]] = fmul reassoc nsz double [[X:%.*]], 5.000000e+00 +; CHECK-NEXT: [[E:%.*]] = call reassoc double @llvm.exp.f64(double [[MERGED_SQRT]]) +; CHECK-NEXT: ret double [[E]] +; + %mul = fmul reassoc nsz double %x, 10.0 + %e = call reassoc double @llvm.exp.f64(double %mul) + %res = call reassoc nsz double @llvm.sqrt.f64(double %e) + ret double %res +} + +define double @sqrt_exp_intr_and_libcall(double %x) { +; CHECK-LABEL: @sqrt_exp_intr_and_libcall( +; CHECK-NEXT: [[MERGED_SQRT:%.*]] = fmul reassoc double [[X:%.*]], 5.000000e-01 +; CHECK-NEXT: [[E:%.*]] = call reassoc double @exp(double [[MERGED_SQRT]]) +; CHECK-NEXT: ret double [[E]] +; + %e = call reassoc double @exp(double %x) + %res = call reassoc double @llvm.sqrt.f64(double %e) + ret double %res +} + +define double @sqrt_exp_intr_and_libcall_2(double %x) { +; CHECK-LABEL: @sqrt_exp_intr_and_libcall_2( +; CHECK-NEXT: [[MERGED_SQRT:%.*]] = fmul reassoc double [[X:%.*]], 5.000000e-01 +; CHECK-NEXT: [[E:%.*]] = call reassoc double @llvm.exp.f64(double [[MERGED_SQRT]]) +; CHECK-NEXT: ret double [[E]] +; + %e = call reassoc double @llvm.exp.f64(double %x) + %res = call reassoc double @sqrt(double %e) + ret double %res +} + +define <2 x float> @sqrt_exp_vec(<2 x float> %x) { +; CHECK-LABEL: @sqrt_exp_vec( +; CHECK-NEXT: [[MERGED_SQRT:%.*]] = fmul reassoc <2 x float> [[X:%.*]], +; CHECK-NEXT: [[E:%.*]] = call reassoc <2 x float> @llvm.exp.v2f32(<2 x float> [[MERGED_SQRT]]) +; CHECK-NEXT: ret <2 x float> [[E]] +; + %e = call reassoc <2 x float> @llvm.exp.v2f32(<2 x float> %x) + %res = call reassoc <2 x float> @llvm.sqrt.v2f32(<2 x float> %e) + ret <2 x float> %res +} + declare i32 @foo(double) declare double @sqrt(double) readnone declare float @sqrtf(float) declare float @llvm.fabs.f32(float) +declare double @llvm.exp.f64(double) +declare double @llvm.sqrt.f64(double) +declare double @exp(double) +declare double @exp2(double) +declare double @exp10(double) +declare <2 x float> @llvm.exp.v2f32(<2 x float>) +declare <2 x float> @llvm.sqrt.v2f32(<2 x float>) -- GitLab From 984dd15d4da33337b2800d4776aa8ecc168b145e Mon Sep 17 00:00:00 2001 From: j-jorge Date: Tue, 6 Feb 2024 10:06:33 +0100 Subject: [PATCH 037/266] [clang-format] Add MainIncludeChar option. (#78752) Resolves #27008, #39735, #53013, #63619. Hello, this PR adds the MainIncludeChar option to clang-format, allowing to select which include syntax must be considered when searching for the main header: quotes (`#include "foo.hpp"`, the default), brackets (`#include `), or both. The lack of support for brackets has been reported many times, see the linked issues, so I am pretty sure there is a need for it :) A short note about why I did not implement a regex approach as discussed in #53013: while a regex would have allowed many extra ways to describe the main header, the bug descriptions listed above suggest a very simple need: support brackets for the main header. This PR answers this needs in a quite simple way, with a very simple style option. IMHO the feature space covered by the regex (again, for which there is no demand :)) can be implemented latter, in addition to the proposed option. The PR also includes tests for the option with and without grouped includes. --- clang/docs/ClangFormatStyleOptions.rst | 19 ++++ clang/include/clang/Format/Format.h | 1 + .../clang/Tooling/Inclusions/IncludeStyle.h | 23 ++++ clang/lib/Format/Format.cpp | 2 + .../lib/Tooling/Inclusions/HeaderIncludes.cpp | 14 ++- clang/lib/Tooling/Inclusions/IncludeStyle.cpp | 7 ++ clang/unittests/Format/SortIncludesTest.cpp | 106 ++++++++++++++++++ 7 files changed, 170 insertions(+), 2 deletions(-) diff --git a/clang/docs/ClangFormatStyleOptions.rst b/clang/docs/ClangFormatStyleOptions.rst index 976d9e2716ef..f86be2c1246f 100644 --- a/clang/docs/ClangFormatStyleOptions.rst +++ b/clang/docs/ClangFormatStyleOptions.rst @@ -4142,6 +4142,25 @@ the configuration (without a prefix: ``Auto``). A(z); -> z; A(a, b); // will not be expanded. +.. _MainIncludeChar: + +**MainIncludeChar** (``MainIncludeCharDiscriminator``) :versionbadge:`clang-format 18` :ref:`¶ ` + When guessing whether a #include is the "main" include, only the include + directives that use the specified character are considered. + + Possible values: + + * ``MICD_Quote`` (in configuration: ``Quote``) + Main include uses quotes: ``#include "foo.hpp"`` (the default). + + * ``MICD_AngleBracket`` (in configuration: ``AngleBracket``) + Main include uses angle brackets: ``#include ``. + + * ``MICD_Any`` (in configuration: ``Any``) + Main include uses either quotes or angle brackets. + + + .. _MaxEmptyLinesToKeep: **MaxEmptyLinesToKeep** (``Unsigned``) :versionbadge:`clang-format 3.7` :ref:`¶ ` diff --git a/clang/include/clang/Format/Format.h b/clang/include/clang/Format/Format.h index 2ca80a7889f8..415321310c24 100644 --- a/clang/include/clang/Format/Format.h +++ b/clang/include/clang/Format/Format.h @@ -4846,6 +4846,7 @@ struct FormatStyle { R.IncludeStyle.IncludeIsMainRegex && IncludeStyle.IncludeIsMainSourceRegex == R.IncludeStyle.IncludeIsMainSourceRegex && + IncludeStyle.MainIncludeChar == R.IncludeStyle.MainIncludeChar && IndentAccessModifiers == R.IndentAccessModifiers && IndentCaseBlocks == R.IndentCaseBlocks && IndentCaseLabels == R.IndentCaseLabels && diff --git a/clang/include/clang/Tooling/Inclusions/IncludeStyle.h b/clang/include/clang/Tooling/Inclusions/IncludeStyle.h index d6b2b0192477..c91e4a6b0ac5 100644 --- a/clang/include/clang/Tooling/Inclusions/IncludeStyle.h +++ b/clang/include/clang/Tooling/Inclusions/IncludeStyle.h @@ -151,6 +151,21 @@ struct IncludeStyle { /// before any other include. /// \version 10 std::string IncludeIsMainSourceRegex; + + /// Character to consider in the include directives for the main header. + enum MainIncludeCharDiscriminator : int8_t { + /// Main include uses quotes: ``#include "foo.hpp"`` (the default). + MICD_Quote, + /// Main include uses angle brackets: ``#include ``. + MICD_AngleBracket, + /// Main include uses either quotes or angle brackets. + MICD_Any + }; + + /// When guessing whether a #include is the "main" include, only the include + /// directives that use the specified character are considered. + /// \version 18 + MainIncludeCharDiscriminator MainIncludeChar; }; } // namespace tooling @@ -174,6 +189,14 @@ struct ScalarEnumerationTraits< enumeration(IO &IO, clang::tooling::IncludeStyle::IncludeBlocksStyle &Value); }; +template <> +struct ScalarEnumerationTraits< + clang::tooling::IncludeStyle::MainIncludeCharDiscriminator> { + static void enumeration( + IO &IO, + clang::tooling::IncludeStyle::MainIncludeCharDiscriminator &Value); +}; + } // namespace yaml } // namespace llvm diff --git a/clang/lib/Format/Format.cpp b/clang/lib/Format/Format.cpp index 01d6e9aca0d2..9c780cd7a5f4 100644 --- a/clang/lib/Format/Format.cpp +++ b/clang/lib/Format/Format.cpp @@ -1018,6 +1018,7 @@ template <> struct MappingTraits { IO.mapOptional("MacroBlockBegin", Style.MacroBlockBegin); IO.mapOptional("MacroBlockEnd", Style.MacroBlockEnd); IO.mapOptional("Macros", Style.Macros); + IO.mapOptional("MainIncludeChar", Style.IncludeStyle.MainIncludeChar); IO.mapOptional("MaxEmptyLinesToKeep", Style.MaxEmptyLinesToKeep); IO.mapOptional("NamespaceIndentation", Style.NamespaceIndentation); IO.mapOptional("NamespaceMacros", Style.NamespaceMacros); @@ -1496,6 +1497,7 @@ FormatStyle getLLVMStyle(FormatStyle::LanguageKind Language) { {".*", 1, 0, false}}; LLVMStyle.IncludeStyle.IncludeIsMainRegex = "(Test)?$"; LLVMStyle.IncludeStyle.IncludeBlocks = tooling::IncludeStyle::IBS_Preserve; + LLVMStyle.IncludeStyle.MainIncludeChar = tooling::IncludeStyle::MICD_Quote; LLVMStyle.IndentAccessModifiers = false; LLVMStyle.IndentCaseLabels = false; LLVMStyle.IndentCaseBlocks = false; diff --git a/clang/lib/Tooling/Inclusions/HeaderIncludes.cpp b/clang/lib/Tooling/Inclusions/HeaderIncludes.cpp index d275222ac6b5..4313da66efc0 100644 --- a/clang/lib/Tooling/Inclusions/HeaderIncludes.cpp +++ b/clang/lib/Tooling/Inclusions/HeaderIncludes.cpp @@ -234,8 +234,18 @@ int IncludeCategoryManager::getSortIncludePriority(StringRef IncludeName, return Ret; } bool IncludeCategoryManager::isMainHeader(StringRef IncludeName) const { - if (!IncludeName.starts_with("\"")) - return false; + switch (Style.MainIncludeChar) { + case IncludeStyle::MICD_Quote: + if (!IncludeName.starts_with("\"")) + return false; + break; + case IncludeStyle::MICD_AngleBracket: + if (!IncludeName.starts_with("<")) + return false; + break; + case IncludeStyle::MICD_Any: + break; + } IncludeName = IncludeName.drop_front(1).drop_back(1); // remove the surrounding "" or <> diff --git a/clang/lib/Tooling/Inclusions/IncludeStyle.cpp b/clang/lib/Tooling/Inclusions/IncludeStyle.cpp index da5bb00d1013..05dfb50589de 100644 --- a/clang/lib/Tooling/Inclusions/IncludeStyle.cpp +++ b/clang/lib/Tooling/Inclusions/IncludeStyle.cpp @@ -28,5 +28,12 @@ void ScalarEnumerationTraits::enumeration( IO.enumCase(Value, "Regroup", IncludeStyle::IBS_Regroup); } +void ScalarEnumerationTraits:: + enumeration(IO &IO, IncludeStyle::MainIncludeCharDiscriminator &Value) { + IO.enumCase(Value, "Quote", IncludeStyle::MICD_Quote); + IO.enumCase(Value, "AngleBracket", IncludeStyle::MICD_AngleBracket); + IO.enumCase(Value, "Any", IncludeStyle::MICD_Any); +} + } // namespace yaml } // namespace llvm diff --git a/clang/unittests/Format/SortIncludesTest.cpp b/clang/unittests/Format/SortIncludesTest.cpp index ec142e03b128..772eb53806b4 100644 --- a/clang/unittests/Format/SortIncludesTest.cpp +++ b/clang/unittests/Format/SortIncludesTest.cpp @@ -976,6 +976,112 @@ TEST_F(SortIncludesTest, EXPECT_EQ(Code, sort(Code, "input.h", 0)); } +TEST_F(SortIncludesTest, MainIncludeChar) { + std::string Code = "#include \n" + "#include \"quote/input.h\"\n" + "#include \n"; + + // Default behavior + EXPECT_EQ("#include \"quote/input.h\"\n" + "#include \n" + "#include \n", + sort(Code, "input.cc", 1)); + + Style.MainIncludeChar = tooling::IncludeStyle::MICD_Quote; + EXPECT_EQ("#include \"quote/input.h\"\n" + "#include \n" + "#include \n", + sort(Code, "input.cc", 1)); + + Style.MainIncludeChar = tooling::IncludeStyle::MICD_AngleBracket; + EXPECT_EQ("#include \n" + "#include \"quote/input.h\"\n" + "#include \n", + sort(Code, "input.cc", 1)); +} + +TEST_F(SortIncludesTest, MainIncludeCharAnyPickQuote) { + Style.MainIncludeChar = tooling::IncludeStyle::MICD_Any; + EXPECT_EQ("#include \"input.h\"\n" + "#include \n" + "#include \n", + sort("#include \n" + "#include \"input.h\"\n" + "#include \n", + "input.cc", 1)); +} + +TEST_F(SortIncludesTest, MainIncludeCharAnyPickAngleBracket) { + Style.MainIncludeChar = tooling::IncludeStyle::MICD_Any; + EXPECT_EQ("#include \n" + "#include \n" + "#include \n", + sort("#include \n" + "#include \n" + "#include \n", + "input.cc", 1)); +} + +TEST_F(SortIncludesTest, MainIncludeCharQuoteAndRegroup) { + Style.IncludeCategories = { + {"lib-a", 1, 0, false}, {"lib-b", 2, 0, false}, {"lib-c", 3, 0, false}}; + Style.IncludeBlocks = tooling::IncludeStyle::IBS_Regroup; + Style.MainIncludeChar = tooling::IncludeStyle::MICD_Quote; + + EXPECT_EQ("#include \"lib-b/input.h\"\n" + "\n" + "#include \n" + "#include \n" + "#include \n" + "\n" + "#include \n" + "#include \n" + "\n" + "#include \n" + "#include \n" + "#include \n", + sort("#include \n" + "#include \n" + "#include \n" + "#include \n" + "#include \"lib-b/input.h\"\n" + "#include \n" + "#include \n" + "#include \n" + "#include \n", + "input.cc")); +} + +TEST_F(SortIncludesTest, MainIncludeCharAngleBracketAndRegroup) { + Style.IncludeCategories = { + {"lib-a", 1, 0, false}, {"lib-b", 2, 0, false}, {"lib-c", 3, 0, false}}; + Style.IncludeBlocks = tooling::IncludeStyle::IBS_Regroup; + Style.MainIncludeChar = tooling::IncludeStyle::MICD_AngleBracket; + + EXPECT_EQ("#include \n" + "\n" + "#include \n" + "#include \n" + "\n" + "#include \"lib-b/input.h\"\n" + "#include \n" + "#include \n" + "\n" + "#include \n" + "#include \n" + "#include \n", + sort("#include \n" + "#include \n" + "#include \n" + "#include \n" + "#include \"lib-b/input.h\"\n" + "#include \n" + "#include \n" + "#include \n" + "#include \n", + "input.cc")); +} + TEST_F(SortIncludesTest, DoNotRegroupGroupsInGoogleObjCStyle) { FmtStyle = getGoogleStyle(FormatStyle::LK_ObjC); -- GitLab From edfc21a5759e9f5f5025885da9b0b879204aff22 Mon Sep 17 00:00:00 2001 From: vigbalu <70995650+vigbalu@users.noreply.github.com> Date: Tue, 6 Feb 2024 14:42:47 +0530 Subject: [PATCH 038/266] [OMPD] Runtime Entry Point functions for OMPD in libomp.so need C linkage as per standard. (#79246) Adding extern "C" to all the entry point functions to make sure that these functions are not mangled. --- openmp/runtime/src/include/omp-tools.h.var | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/openmp/runtime/src/include/omp-tools.h.var b/openmp/runtime/src/include/omp-tools.h.var index a3ec0309db18..1d1a0f7771e9 100644 --- a/openmp/runtime/src/include/omp-tools.h.var +++ b/openmp/runtime/src/include/omp-tools.h.var @@ -211,6 +211,10 @@ typedef enum kmp_mutex_impl_t { * definitions generated from spec *****************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + typedef enum ompt_callbacks_t { ompt_callback_thread_begin = 1, ompt_callback_thread_end = 2, @@ -1414,4 +1418,8 @@ typedef ompt_record_ompt_t *(*ompt_get_record_ompt_t) ( #define ompd_segment_none 0 +#if defined(__cplusplus) +} // extern "C" +#endif + #endif /* __OMPT__ */ -- GitLab From 42b5b720caf62e0710b9c1e32e894d8606106a19 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 6 Feb 2024 14:54:47 +0530 Subject: [PATCH 039/266] AMDGPU/GlobalISel: Fix not running -global-isel in global isel test --- .../GlobalISel/llvm.amdgcn.trig.preop.ll | 72 +++++++++++++++---- 1 file changed, 57 insertions(+), 15 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll index 51e1fee0db24..1d5cc1e1ec04 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii < %s | FileCheck -check-prefixes=GCN,CI %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,VI %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s +; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii < %s | FileCheck -check-prefixes=GCN,CI %s +; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,VI %s +; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s +; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s +; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s define double @v_trig_preop_f64(double %a, i32 %b) { ; GCN-LABEL: v_trig_preop_f64: @@ -45,7 +45,13 @@ define amdgpu_kernel void @s_trig_preop_f64(double %a, i32 %b) { ; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: v_mov_b32_e32 v0, s2 ; CI-NEXT: v_trig_preop_f64 v[0:1], s[0:1], v0 -; CI-NEXT: flat_store_dwordx2 v[0:1], v[0:1] +; CI-NEXT: s_add_u32 s0, s0, 4 +; CI-NEXT: s_addc_u32 s1, s1, 0 +; CI-NEXT: v_mov_b32_e32 v3, s1 +; CI-NEXT: v_mov_b32_e32 v2, s0 +; CI-NEXT: flat_store_dword v[0:1], v0 +; CI-NEXT: s_waitcnt vmcnt(0) +; CI-NEXT: flat_store_dword v[2:3], v1 ; CI-NEXT: s_waitcnt vmcnt(0) ; CI-NEXT: s_endpgm ; @@ -56,7 +62,13 @@ define amdgpu_kernel void @s_trig_preop_f64(double %a, i32 %b) { ; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: v_mov_b32_e32 v0, s2 ; VI-NEXT: v_trig_preop_f64 v[0:1], s[0:1], v0 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[0:1] +; VI-NEXT: s_add_u32 s0, s0, 4 +; VI-NEXT: s_addc_u32 s1, s1, 0 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: flat_store_dword v[0:1], v0 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: flat_store_dword v[2:3], v1 ; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_endpgm ; @@ -98,14 +110,44 @@ define amdgpu_kernel void @s_trig_preop_f64(double %a, i32 %b) { } define amdgpu_kernel void @s_trig_preop_f64_imm(double %a, i32 %b) { -; GCN-LABEL: s_trig_preop_f64_imm: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: v_trig_preop_f64 v[0:1], s[0:1], 7 -; GCN-NEXT: flat_store_dwordx2 v[0:1], v[0:1] -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: s_endpgm +; CI-LABEL: s_trig_preop_f64_imm: +; CI: ; %bb.0: +; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 +; CI-NEXT: s_waitcnt lgkmcnt(0) +; CI-NEXT: v_trig_preop_f64 v[0:1], s[0:1], 7 +; CI-NEXT: s_add_u32 s0, s0, 4 +; CI-NEXT: s_addc_u32 s1, s1, 0 +; CI-NEXT: v_mov_b32_e32 v3, s1 +; CI-NEXT: v_mov_b32_e32 v2, s0 +; CI-NEXT: flat_store_dword v[0:1], v0 +; CI-NEXT: s_waitcnt vmcnt(0) +; CI-NEXT: flat_store_dword v[2:3], v1 +; CI-NEXT: s_waitcnt vmcnt(0) +; CI-NEXT: s_endpgm +; +; VI-LABEL: s_trig_preop_f64_imm: +; VI: ; %bb.0: +; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: v_trig_preop_f64 v[0:1], s[0:1], 7 +; VI-NEXT: s_add_u32 s0, s0, 4 +; VI-NEXT: s_addc_u32 s1, s1, 0 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: flat_store_dword v[0:1], v0 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: flat_store_dword v[2:3], v1 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: s_trig_preop_f64_imm: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_trig_preop_f64 v[0:1], s[0:1], 7 +; GFX9-NEXT: flat_store_dwordx2 v[0:1], v[0:1] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_endpgm ; ; GFX10-LABEL: s_trig_preop_f64_imm: ; GFX10: ; %bb.0: -- GitLab From 0473e322f67228a9c2dbf462357e5b4a2b3799be Mon Sep 17 00:00:00 2001 From: Benjamin Maxwell Date: Tue, 6 Feb 2024 09:30:55 +0000 Subject: [PATCH 040/266] [mlir][ArmSME] Add rewrite to lift illegal vector.transposes to memory (#80170) When unrolling the reduction dimension of something like a matmul for SME, you can end up with transposed reads of illegal types, like so: ```mlir %illegalRead = vector.transfer_read %memref[%a, %b] : memref, vector<[8]x4xf32> %legalType = vector.transpose %illegalRead, [1, 0] : vector<[8]x4xf32> to vector<4x[8]xf32> ``` Here the `vector<[8]x4xf32>` is an illegal type, there's no way to lower a scalable vector of fixed vectors. However, as the final type `vector<4x[8]xf32>` is legal, we can instead lift the transpose to memory (producing a strided memref), and eliminate all the illegal types. This is shown below. ```mlir %readSubview = memref.subview %memref[%a, %b] [%c8_vscale, %c4] [%c1, %c1] : memref to memref %transpose = memref.transpose %readSubview (d0, d1) -> (d1, d0) : memref to memref %legalType = vector.transfer_read %transpose[%c0, %c0] : memref, vector<4x[8]xf32> ``` --- .../ArmSME/Transforms/VectorLegalization.cpp | 144 +++++++++++++++++- .../Dialect/ArmSME/vector-legalization.mlir | 75 +++++++++ 2 files changed, 218 insertions(+), 1 deletion(-) diff --git a/mlir/lib/Dialect/ArmSME/Transforms/VectorLegalization.cpp b/mlir/lib/Dialect/ArmSME/Transforms/VectorLegalization.cpp index 14b9d8e34da6..e88f82c92eba 100644 --- a/mlir/lib/Dialect/ArmSME/Transforms/VectorLegalization.cpp +++ b/mlir/lib/Dialect/ArmSME/Transforms/VectorLegalization.cpp @@ -18,6 +18,7 @@ #include "mlir/Dialect/ArmSME/Utils/Utils.h" #include "mlir/Dialect/Func/IR/FuncOps.h" #include "mlir/Dialect/Func/Transforms/OneToNFuncConversions.h" +#include "mlir/Dialect/MemRef/IR/MemRef.h" #include "mlir/Dialect/SCF/Transforms/Patterns.h" #include "mlir/Dialect/Utils/IndexingUtils.h" #include "mlir/Transforms/OneToNTypeConversion.h" @@ -415,6 +416,146 @@ struct FoldExtractFromVectorOfSMELikeCreateMasks } }; +/// Lifts an illegal vector.transpose and vector.transfer_read to a +/// memref.subview + memref.transpose, followed by a legal read. +/// +/// 'Illegal' here means a leading scalable dimension and a fixed trailing +/// dimension, which has no valid lowering. +/// +/// The memref.transpose is metadata-only transpose that produces a strided +/// memref, which eventually becomes a loop reading individual elements. +/// +/// Example: +/// +/// BEFORE: +/// ```mlir +/// %illegalRead = vector.transfer_read %memref[%a, %b] +/// : memref, vector<[8]x4xf32> +/// %legalType = vector.transpose %illegalRead, [1, 0] +/// : vector<[8]x4xf32> to vector<4x[8]xf32> +/// ``` +/// +/// AFTER: +/// ```mlir +/// %readSubview = memref.subview %memref[%a, %b] [%c8_vscale, %c4] [%c1, %c1] +/// : memref to memref +/// %transpose = memref.transpose %readSubview (d0, d1) -> (d1, d0) +/// : memref to memref +/// %legalType = vector.transfer_read %transpose[%c0, %c0] +/// : memref, vector<4x[8]xf32> +/// ``` +struct LiftIllegalVectorTransposeToMemory + : public OpRewritePattern { + using OpRewritePattern::OpRewritePattern; + + static bool isIllegalVectorType(VectorType vType) { + bool seenFixedDim = false; + for (bool scalableFlag : llvm::reverse(vType.getScalableDims())) { + seenFixedDim |= !scalableFlag; + if (seenFixedDim && scalableFlag) + return true; + } + return false; + } + + static Value getExtensionSource(Operation *op) { + if (isa(op)) + return op->getOperand(0); + return {}; + } + + LogicalResult matchAndRewrite(vector::TransposeOp transposeOp, + PatternRewriter &rewriter) const override { + auto sourceType = transposeOp.getSourceVectorType(); + auto resultType = transposeOp.getResultVectorType(); + if (!isIllegalVectorType(sourceType) || isIllegalVectorType(resultType)) + return rewriter.notifyMatchFailure( + transposeOp, "expected transpose from illegal type to legal type"); + + // Look through extend for transfer_read. + Value maybeRead = transposeOp.getVector(); + auto *transposeSourceOp = maybeRead.getDefiningOp(); + Operation *extendOp = nullptr; + if (Value extendSource = getExtensionSource(transposeSourceOp)) { + maybeRead = extendSource; + extendOp = transposeSourceOp; + } + + auto illegalRead = maybeRead.getDefiningOp(); + if (!illegalRead) + return rewriter.notifyMatchFailure( + transposeOp, + "expected source to be (possibly extended) transfer_read"); + + if (!illegalRead.getPermutationMap().isIdentity()) + return rewriter.notifyMatchFailure( + illegalRead, "expected read to have identity permutation map"); + + auto loc = transposeOp.getLoc(); + auto zero = rewriter.create(loc, 0); + auto one = rewriter.create(loc, 1); + + // Create a subview that matches the size of the illegal read vector type. + auto readType = illegalRead.getVectorType(); + auto readSizes = llvm::map_to_vector( + llvm::zip_equal(readType.getShape(), readType.getScalableDims()), + [&](auto dim) -> Value { + auto [size, isScalable] = dim; + auto dimSize = rewriter.create(loc, size); + if (!isScalable) + return dimSize; + auto vscale = rewriter.create(loc); + return rewriter.create(loc, vscale, dimSize); + }); + SmallVector strides(readType.getRank(), Value(one)); + auto readSubview = rewriter.create( + loc, illegalRead.getSource(), illegalRead.getIndices(), readSizes, + strides); + + // Apply the transpose to all values/attributes of the transfer_read: + // - The mask + Value mask = illegalRead.getMask(); + if (mask) { + // Note: The transpose for the mask should fold into the + // vector.create_mask/constant_mask op, which will then become legal. + mask = rewriter.create(loc, mask, + transposeOp.getPermutation()); + } + // - The source memref + mlir::AffineMap transposeMap = AffineMap::getPermutationMap( + transposeOp.getPermutation(), getContext()); + auto transposedSubview = rewriter.create( + loc, readSubview, AffineMapAttr::get(transposeMap)); + ArrayAttr inBoundsAttr = illegalRead.getInBoundsAttr(); + // - The `in_bounds` attribute + if (inBoundsAttr) { + SmallVector inBoundsValues(inBoundsAttr.begin(), + inBoundsAttr.end()); + applyPermutationToVector(inBoundsValues, transposeOp.getPermutation()); + inBoundsAttr = rewriter.getArrayAttr(inBoundsValues); + } + + VectorType legalReadType = resultType.clone(readType.getElementType()); + // Note: The indices are all zero as the subview is already offset. + SmallVector readIndices(illegalRead.getIndices().size(), zero); + auto legalRead = rewriter.create( + loc, legalReadType, transposedSubview, readIndices, + illegalRead.getPermutationMapAttr(), illegalRead.getPadding(), mask, + inBoundsAttr); + + // Replace the transpose with the new read, extending the result if + // necessary. + rewriter.replaceOp(transposeOp, [&]() -> Operation * { + if (extendOp) + return rewriter.create(loc, extendOp->getName().getIdentifier(), + Value(legalRead), resultType); + return legalRead; + }()); + + return success(); + } +}; + struct VectorLegalizationPass : public arm_sme::impl::VectorLegalizationBase { void runOnOperation() override { @@ -434,7 +575,8 @@ struct VectorLegalizationPass return success(); }); - patterns.add(context); + patterns.add(context); // Note: High benefit to ensure masked outer products are lowered first. patterns.add( converter, context, 1024); diff --git a/mlir/test/Dialect/ArmSME/vector-legalization.mlir b/mlir/test/Dialect/ArmSME/vector-legalization.mlir index a2526db9b483..11888c675f0b 100644 --- a/mlir/test/Dialect/ArmSME/vector-legalization.mlir +++ b/mlir/test/Dialect/ArmSME/vector-legalization.mlir @@ -302,3 +302,78 @@ func.func @non_constant_extract_from_vector_create_mask_non_constant(%index: ind %extract = vector.extract %mask[%index] : vector<[4]x[4]xi1> from vector<4x[4]x[4]xi1> return %extract : vector<[4]x[4]xi1> } + +// ----- + +// CHECK-LABEL: @lift_illegal_transpose_to_memory( +// CHECK-SAME: %[[INDEXA:[a-z0-9]+]]: index, +// CHECK-SAME: %[[INDEXB:[a-z0-9]+]]: index, +// CHECK-SAME: %[[MEMREF:[a-z0-9]+]]: memref) +func.func @lift_illegal_transpose_to_memory(%a: index, %b: index, %memref: memref) -> vector<4x[8]xf32> { + // CHECK-DAG: %[[C0:.*]] = arith.constant 0 : index + // CHECK-DAG: %[[C8:.*]] = arith.constant 8 : index + // CHECK-DAG: %[[C0_F32:.*]] = arith.constant 0.000000e+00 : f32 + // CHECK-DAG: %[[VSCALE:.*]] = vector.vscale + // CHECK-DAG: %[[C8_VSCALE:.*]] = arith.muli %[[VSCALE]], %[[C8]] : index + // CHECK-NEXT: %[[READ_SUBVIEW:.*]] = memref.subview %[[MEMREF]][%[[INDEXA]], %[[INDEXB]]] [%[[C8_VSCALE]], 4] [1, 1] : memref to memref> + // CHECK-NEXT: %[[CAST:.*]] = memref.cast %[[READ_SUBVIEW]] : memref> to memref> + // CHECK-NEXT: %[[TRANSPOSE:.*]] = memref.transpose %[[CAST]] (d0, d1) -> (d1, d0) : memref> to memref> + // CHECK-NEXT: %[[LEGAL_READ:.*]] = vector.transfer_read %[[TRANSPOSE]][%c0, %c0], %[[C0_F32]] : memref>, vector<4x[8]xf32> + // CHECK-NEXT: return %[[LEGAL_READ]] + %pad = arith.constant 0.0 : f32 + %illegalRead = vector.transfer_read %memref[%a, %b], %pad : memref, vector<[8]x4xf32> + %legalType = vector.transpose %illegalRead, [1, 0] : vector<[8]x4xf32> to vector<4x[8]xf32> + return %legalType : vector<4x[8]xf32> +} + +// ----- + +// CHECK-LABEL: @lift_illegal_transpose_to_memory_with_mask( +// CHECK-SAME: %[[DIM0:[a-z0-9]+]]: index, +// CHECK-SAME: %[[DIM1:[a-z0-9]+]]: index, +// CHECK-SAME: %[[MEMREF:[a-z0-9]+]]: memref +func.func @lift_illegal_transpose_to_memory_with_mask(%dim0: index, %dim1: index, %memref: memref, %a: index, %b: index) -> vector<4x[8]xf32> { + // CHECK-DAG: %[[READ_SUBVIEW:.*]] = memref.subview %[[MEMREF]] + // CHECK-DAG: %[[CAST:.*]] = memref.cast %[[READ_SUBVIEW]] + // CHECK-DAG: %[[TRANSPOSE:.*]] = memref.transpose %[[CAST]] + // CHECK-DAG: %[[MASK:.*]] = vector.create_mask %[[DIM1]], %[[DIM0]] : vector<4x[8]xi1> + // CHECK: %[[LEGAL_READ:.*]] = vector.transfer_read %[[TRANSPOSE]] + // CHECK-SAME: %[[MASK]] : memref>, vector<4x[8]xf32> + // CHECK-NEXT: return %[[LEGAL_READ]] + %pad = arith.constant 0.0 : f32 + %mask = vector.create_mask %dim0, %dim1 : vector<[8]x4xi1> + %illegalRead = vector.transfer_read %memref[%a, %b], %pad, %mask : memref, vector<[8]x4xf32> + %legalType = vector.transpose %illegalRead, [1, 0] : vector<[8]x4xf32> to vector<4x[8]xf32> + return %legalType : vector<4x[8]xf32> +} + +// ----- + +// CHECK-LABEL: @lift_illegal_transpose_to_memory_with_arith_extop( +// CHECK-SAME: %[[MEMREF:[a-z0-9]+]]: memref +func.func @lift_illegal_transpose_to_memory_with_arith_extop(%a: index, %b: index, %memref: memref) -> vector<4x[8]xi32> { + // CHECK-DAG: %[[READ_SUBVIEW:.*]] = memref.subview %[[MEMREF]] + // CHECK-DAG: %[[CAST:.*]] = memref.cast %[[READ_SUBVIEW]] + // CHECK-DAG: %[[TRANSPOSE:.*]] = memref.transpose %[[CAST]] + // CHECK: %[[LEGAL_READ:.*]] = vector.transfer_read %[[TRANSPOSE]] + // CHECK-NEXT: %[[EXT_TYPE:.*]] = arith.extsi %[[LEGAL_READ]] : vector<4x[8]xi8> to vector<4x[8]xi32> + // CHECK-NEXT: return %[[EXT_TYPE]] + %pad = arith.constant 0 : i8 + %illegalRead = vector.transfer_read %memref[%a, %b], %pad : memref, vector<[8]x4xi8> + %extRead = arith.extsi %illegalRead : vector<[8]x4xi8> to vector<[8]x4xi32> + %legalType = vector.transpose %extRead, [1, 0] : vector<[8]x4xi32> to vector<4x[8]xi32> + return %legalType : vector<4x[8]xi32> +} + +// ----- + +// CHECK-LABEL: @lift_illegal_transpose_to_memory_with_in_bounds_attr +func.func @lift_illegal_transpose_to_memory_with_in_bounds_attr(%a: index, %b: index, %memref: memref) -> vector<4x[8]xf32> { + // CHECK: vector.transfer_read + // CHECK-SAME: in_bounds = [true, false] + // CHECK-NOT: in_bounds = [false, true] + %pad = arith.constant 0.0 : f32 + %illegalRead = vector.transfer_read %memref[%a, %b], %pad {in_bounds = [false, true]}: memref, vector<[8]x4xf32> + %legalType = vector.transpose %illegalRead, [1, 0] : vector<[8]x4xf32> to vector<4x[8]xf32> + return %legalType : vector<4x[8]xf32> +} -- GitLab From 3eb1e6d8e930f5aff17b8d6bcc160f5bbf8cabc7 Mon Sep 17 00:00:00 2001 From: michaelrj-google <71531609+michaelrj-google@users.noreply.github.com> Date: Tue, 6 Feb 2024 01:36:05 -0800 Subject: [PATCH 041/266] [libc] Move libc_errno inside of LIBC_NAMESPACE (#80774) Having libc_errno outside of the namespace causes versioning issues when trying to link the tests against LLVM-libc. Most of this patch is just moving libc_errno inside the namespace in tests. This isn't necessary in the function implementations since those are already inside the namespace. --- libc/src/errno/libc_errno.cpp | 2 + libc/src/errno/libc_errno.h | 3 +- libc/test/IntegrationTest/test.h | 9 +- libc/test/UnitTest/ErrnoSetterMatcher.h | 4 +- libc/test/UnitTest/FPMatcher.h | 8 +- libc/test/UnitTest/FuchsiaTest.h | 9 +- libc/test/UnitTest/LibcTest.h | 9 +- .../src/pthread/pthread_create_test.cpp | 2 +- .../src/pthread/pthread_join_test.cpp | 2 +- .../integration/src/unistd/getcwd_test.cpp | 4 +- .../test/src/__support/str_to_double_test.cpp | 2 +- libc/test/src/__support/str_to_float_test.cpp | 2 +- libc/test/src/__support/str_to_fp_test.h | 2 +- libc/test/src/dirent/dirent_test.cpp | 8 +- libc/test/src/errno/errno_test.cpp | 2 +- libc/test/src/math/RoundToIntegerTest.h | 2 +- libc/test/src/math/acosf_test.cpp | 2 +- libc/test/src/math/acoshf_test.cpp | 2 +- libc/test/src/math/asinf_test.cpp | 2 +- libc/test/src/math/asinhf_test.cpp | 2 +- libc/test/src/math/atanf_test.cpp | 2 +- libc/test/src/math/atanhf_test.cpp | 2 +- libc/test/src/math/cosf_test.cpp | 2 +- libc/test/src/math/coshf_test.cpp | 4 +- libc/test/src/math/exp10_test.cpp | 2 +- libc/test/src/math/exp10f_test.cpp | 12 +- libc/test/src/math/exp2_test.cpp | 2 +- libc/test/src/math/exp2f_test.cpp | 12 +- libc/test/src/math/exp_test.cpp | 2 +- libc/test/src/math/expf_test.cpp | 12 +- libc/test/src/math/expm1_test.cpp | 2 +- libc/test/src/math/expm1f_test.cpp | 12 +- libc/test/src/math/log10_test.cpp | 2 +- libc/test/src/math/log1p_test.cpp | 2 +- libc/test/src/math/log1pf_test.cpp | 2 +- libc/test/src/math/log2_test.cpp | 2 +- libc/test/src/math/log2f_test.cpp | 4 +- libc/test/src/math/log_test.cpp | 2 +- libc/test/src/math/powf_test.cpp | 2 +- libc/test/src/math/sincosf_test.cpp | 2 +- libc/test/src/math/sinf_test.cpp | 2 +- libc/test/src/math/sinhf_test.cpp | 4 +- libc/test/src/math/smoke/RoundToIntegerTest.h | 2 +- libc/test/src/math/smoke/acosf_test.cpp | 2 +- libc/test/src/math/smoke/acoshf_test.cpp | 2 +- libc/test/src/math/smoke/asinf_test.cpp | 2 +- libc/test/src/math/smoke/asinhf_test.cpp | 2 +- libc/test/src/math/smoke/atanf_test.cpp | 2 +- libc/test/src/math/smoke/atanhf_test.cpp | 2 +- libc/test/src/math/smoke/cosf_test.cpp | 2 +- libc/test/src/math/smoke/coshf_test.cpp | 4 +- libc/test/src/math/smoke/exp10f_test.cpp | 4 +- libc/test/src/math/smoke/exp2f_test.cpp | 4 +- libc/test/src/math/smoke/expf_test.cpp | 4 +- libc/test/src/math/smoke/expm1f_test.cpp | 4 +- libc/test/src/math/smoke/sincosf_test.cpp | 2 +- libc/test/src/math/smoke/sinf_test.cpp | 2 +- libc/test/src/math/smoke/sinhf_test.cpp | 4 +- libc/test/src/math/smoke/tanf_test.cpp | 2 +- libc/test/src/math/smoke/tanhf_test.cpp | 2 +- libc/test/src/math/tanf_test.cpp | 2 +- libc/test/src/math/tanhf_test.cpp | 2 +- libc/test/src/sched/affinity_test.cpp | 8 +- libc/test/src/sched/cpu_count_test.cpp | 2 +- libc/test/src/sched/get_priority_test.cpp | 2 +- .../src/sched/param_and_scheduler_test.cpp | 45 +++---- .../src/sched/sched_rr_get_interval_test.cpp | 8 +- libc/test/src/sched/yield_test.cpp | 2 +- libc/test/src/signal/sigaltstack_test.cpp | 2 +- libc/test/src/signal/signal_test.cpp | 2 +- libc/test/src/signal/sigprocmask_test.cpp | 2 +- libc/test/src/stdio/fgetc_test.cpp | 2 +- libc/test/src/stdio/fgetc_unlocked_test.cpp | 2 +- libc/test/src/stdio/fgets_test.cpp | 2 +- libc/test/src/stdio/fileop_test.cpp | 22 ++-- libc/test/src/stdio/fopencookie_test.cpp | 8 +- libc/test/src/stdio/remove_test.cpp | 4 +- libc/test/src/stdio/setvbuf_test.cpp | 2 +- libc/test/src/stdio/unlocked_fileop_test.cpp | 4 +- libc/test/src/stdlib/StrtolTest.h | 112 +++++++++--------- libc/test/src/stdlib/atof_test.cpp | 4 +- libc/test/src/stdlib/strtod_test.cpp | 2 +- libc/test/src/stdlib/strtof_test.cpp | 2 +- libc/test/src/stdlib/strtoint32_test.cpp | 4 +- libc/test/src/stdlib/strtoint64_test.cpp | 4 +- libc/test/src/stdlib/strtold_test.cpp | 2 +- libc/test/src/string/strdup_test.cpp | 6 +- libc/test/src/sys/mman/linux/madvise_test.cpp | 4 +- libc/test/src/sys/mman/linux/mincore_test.cpp | 14 +-- libc/test/src/sys/mman/linux/mlock_test.cpp | 17 +-- libc/test/src/sys/mman/linux/mmap_test.cpp | 4 +- .../test/src/sys/mman/linux/mprotect_test.cpp | 2 +- .../src/sys/mman/linux/posix_madvise_test.cpp | 4 +- libc/test/src/sys/prctl/linux/prctl_test.cpp | 2 +- .../src/sys/random/linux/getrandom_test.cpp | 4 +- .../sys/resource/getrlimit_setrlimit_test.cpp | 6 +- libc/test/src/sys/select/select_ui_test.cpp | 2 +- libc/test/src/sys/sendfile/sendfile_test.cpp | 2 +- libc/test/src/sys/stat/chmod_test.cpp | 8 +- libc/test/src/sys/stat/fchmod_test.cpp | 8 +- libc/test/src/sys/stat/fchmodat_test.cpp | 8 +- libc/test/src/sys/stat/fstat_test.cpp | 6 +- libc/test/src/sys/stat/lstat_test.cpp | 6 +- libc/test/src/sys/stat/stat_test.cpp | 6 +- libc/test/src/termios/termios_test.cpp | 10 +- libc/test/src/time/gmtime_test.cpp | 2 +- libc/test/src/time/nanosleep_test.cpp | 2 +- libc/test/src/unistd/access_test.cpp | 6 +- libc/test/src/unistd/chdir_test.cpp | 6 +- libc/test/src/unistd/dup2_test.cpp | 2 +- libc/test/src/unistd/dup3_test.cpp | 2 +- libc/test/src/unistd/dup_test.cpp | 2 +- libc/test/src/unistd/fchdir_test.cpp | 6 +- libc/test/src/unistd/ftruncate_test.cpp | 2 +- libc/test/src/unistd/isatty_test.cpp | 8 +- libc/test/src/unistd/link_test.cpp | 2 +- libc/test/src/unistd/linkat_test.cpp | 2 +- libc/test/src/unistd/readlink_test.cpp | 2 +- libc/test/src/unistd/readlinkat_test.cpp | 2 +- libc/test/src/unistd/symlink_test.cpp | 2 +- libc/test/src/unistd/symlinkat_test.cpp | 2 +- libc/test/src/unistd/syscall_test.cpp | 2 +- libc/test/src/unistd/truncate_test.cpp | 2 +- 123 files changed, 330 insertions(+), 312 deletions(-) diff --git a/libc/src/errno/libc_errno.cpp b/libc/src/errno/libc_errno.cpp index e54bdd156d6b..4af21dccc156 100644 --- a/libc/src/errno/libc_errno.cpp +++ b/libc/src/errno/libc_errno.cpp @@ -44,5 +44,7 @@ LIBC_NAMESPACE::Errno::operator int() { return errno; } #endif // LIBC_FULL_BUILD +namespace LIBC_NAMESPACE { // Define the global `libc_errno` instance. LIBC_NAMESPACE::Errno libc_errno; +} // namespace LIBC_NAMESPACE diff --git a/libc/src/errno/libc_errno.h b/libc/src/errno/libc_errno.h index 632faeaaeff6..6a6ddbc3a9c0 100644 --- a/libc/src/errno/libc_errno.h +++ b/libc/src/errno/libc_errno.h @@ -39,8 +39,9 @@ struct Errno { void operator=(int); operator int(); }; -} // namespace LIBC_NAMESPACE extern LIBC_NAMESPACE::Errno libc_errno; +} // namespace LIBC_NAMESPACE + #endif // LLVM_LIBC_SRC_ERRNO_LIBC_ERRNO_H diff --git a/libc/test/IntegrationTest/test.h b/libc/test/IntegrationTest/test.h index c015bb44586f..64906ef17939 100644 --- a/libc/test/IntegrationTest/test.h +++ b/libc/test/IntegrationTest/test.h @@ -68,9 +68,12 @@ //////////////////////////////////////////////////////////////////////////////// // Errno checks. -#define ASSERT_ERRNO_EQ(VAL) ASSERT_EQ(VAL, static_cast(libc_errno)) -#define ASSERT_ERRNO_SUCCESS() ASSERT_EQ(0, static_cast(libc_errno)) -#define ASSERT_ERRNO_FAILURE() ASSERT_NE(0, static_cast(libc_errno)) +#define ASSERT_ERRNO_EQ(VAL) \ + ASSERT_EQ(VAL, static_cast(LIBC_NAMESPACE::libc_errno)) +#define ASSERT_ERRNO_SUCCESS() \ + ASSERT_EQ(0, static_cast(LIBC_NAMESPACE::libc_errno)) +#define ASSERT_ERRNO_FAILURE() \ + ASSERT_NE(0, static_cast(LIBC_NAMESPACE::libc_errno)) // Integration tests are compiled with -ffreestanding which stops treating // the main function as a non-overloadable special function. Hence, we use a diff --git a/libc/test/UnitTest/ErrnoSetterMatcher.h b/libc/test/UnitTest/ErrnoSetterMatcher.h index 6b15bd4e9b79..745ba4182023 100644 --- a/libc/test/UnitTest/ErrnoSetterMatcher.h +++ b/libc/test/UnitTest/ErrnoSetterMatcher.h @@ -109,8 +109,8 @@ public: bool match(T got) { actual_return = got; - actual_errno = libc_errno; - libc_errno = 0; + actual_errno = LIBC_NAMESPACE::libc_errno; + LIBC_NAMESPACE::libc_errno = 0; if constexpr (ignore_errno()) return return_cmp.compare(actual_return); else diff --git a/libc/test/UnitTest/FPMatcher.h b/libc/test/UnitTest/FPMatcher.h index 210690a9c6ec..c4a1cfa1bc1d 100644 --- a/libc/test/UnitTest/FPMatcher.h +++ b/libc/test/UnitTest/FPMatcher.h @@ -132,8 +132,8 @@ template struct FPTest : public Test { #define EXPECT_MATH_ERRNO(expected) \ do { \ if (math_errhandling & MATH_ERRNO) { \ - int actual = libc_errno; \ - libc_errno = 0; \ + int actual = LIBC_NAMESPACE::libc_errno; \ + LIBC_NAMESPACE::libc_errno = 0; \ EXPECT_EQ(actual, expected); \ } \ } while (0) @@ -141,8 +141,8 @@ template struct FPTest : public Test { #define ASSERT_MATH_ERRNO(expected) \ do { \ if (math_errhandling & MATH_ERRNO) { \ - int actual = libc_errno; \ - libc_errno = 0; \ + int actual = LIBC_NAMESPACE::libc_errno; \ + LIBC_NAMESPACE::libc_errno = 0; \ ASSERT_EQ(actual, expected); \ } \ } while (0) diff --git a/libc/test/UnitTest/FuchsiaTest.h b/libc/test/UnitTest/FuchsiaTest.h index 1b7537965813..e9e8348ee5dd 100644 --- a/libc/test/UnitTest/FuchsiaTest.h +++ b/libc/test/UnitTest/FuchsiaTest.h @@ -14,9 +14,12 @@ #define WITH_SIGNAL(X) #X // These macros are used in string unittests. -#define ASSERT_ERRNO_EQ(VAL) ASSERT_EQ(VAL, static_cast(libc_errno)) -#define ASSERT_ERRNO_SUCCESS() ASSERT_EQ(0, static_cast(libc_errno)) -#define ASSERT_ERRNO_FAILURE() ASSERT_NE(0, static_cast(libc_errno)) +#define ASSERT_ERRNO_EQ(VAL) \ + ASSERT_EQ(VAL, static_cast(LIBC_NAMESPACE::libc_errno)) +#define ASSERT_ERRNO_SUCCESS() \ + ASSERT_EQ(0, static_cast(LIBC_NAMESPACE::libc_errno)) +#define ASSERT_ERRNO_FAILURE() \ + ASSERT_NE(0, static_cast(LIBC_NAMESPACE::libc_errno)) #ifndef EXPECT_DEATH // Since zxtest has ASSERT_DEATH but not EXPECT_DEATH, wrap calling it diff --git a/libc/test/UnitTest/LibcTest.h b/libc/test/UnitTest/LibcTest.h index 1a90d10d7ec0..047f18036b0a 100644 --- a/libc/test/UnitTest/LibcTest.h +++ b/libc/test/UnitTest/LibcTest.h @@ -446,9 +446,12 @@ CString libc_make_test_file_path_func(const char *file_name); //////////////////////////////////////////////////////////////////////////////// // Errno checks. -#define ASSERT_ERRNO_EQ(VAL) ASSERT_EQ(VAL, static_cast(libc_errno)) -#define ASSERT_ERRNO_SUCCESS() ASSERT_EQ(0, static_cast(libc_errno)) -#define ASSERT_ERRNO_FAILURE() ASSERT_NE(0, static_cast(libc_errno)) +#define ASSERT_ERRNO_EQ(VAL) \ + ASSERT_EQ(VAL, static_cast(LIBC_NAMESPACE::libc_errno)) +#define ASSERT_ERRNO_SUCCESS() \ + ASSERT_EQ(0, static_cast(LIBC_NAMESPACE::libc_errno)) +#define ASSERT_ERRNO_FAILURE() \ + ASSERT_NE(0, static_cast(LIBC_NAMESPACE::libc_errno)) //////////////////////////////////////////////////////////////////////////////// // Subprocess checks. diff --git a/libc/test/integration/src/pthread/pthread_create_test.cpp b/libc/test/integration/src/pthread/pthread_create_test.cpp index 5da91c6ec9a7..29da4d5c3c8d 100644 --- a/libc/test/integration/src/pthread/pthread_create_test.cpp +++ b/libc/test/integration/src/pthread/pthread_create_test.cpp @@ -332,7 +332,7 @@ static void run_failure_tests() { } TEST_MAIN() { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; run_success_tests(); run_failure_tests(); return 0; diff --git a/libc/test/integration/src/pthread/pthread_join_test.cpp b/libc/test/integration/src/pthread/pthread_join_test.cpp index da1a968aa47d..994fa57a6b33 100644 --- a/libc/test/integration/src/pthread/pthread_join_test.cpp +++ b/libc/test/integration/src/pthread/pthread_join_test.cpp @@ -25,7 +25,7 @@ static void nullJoinTest() { } TEST_MAIN() { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; nullJoinTest(); return 0; } diff --git a/libc/test/integration/src/unistd/getcwd_test.cpp b/libc/test/integration/src/unistd/getcwd_test.cpp index 87687d09b9e7..551768187bf0 100644 --- a/libc/test/integration/src/unistd/getcwd_test.cpp +++ b/libc/test/integration/src/unistd/getcwd_test.cpp @@ -31,12 +31,12 @@ TEST_MAIN(int argc, char **argv, char **envp) { cwd = LIBC_NAMESPACE::getcwd(buffer, 0); ASSERT_TRUE(cwd == nullptr); ASSERT_ERRNO_EQ(EINVAL); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // Insufficient size cwd = LIBC_NAMESPACE::getcwd(buffer, 2); ASSERT_TRUE(cwd == nullptr); - int err = libc_errno; + int err = LIBC_NAMESPACE::libc_errno; ASSERT_EQ(err, ERANGE); return 0; diff --git a/libc/test/src/__support/str_to_double_test.cpp b/libc/test/src/__support/str_to_double_test.cpp index b66935f0988e..3c6d03978803 100644 --- a/libc/test/src/__support/str_to_double_test.cpp +++ b/libc/test/src/__support/str_to_double_test.cpp @@ -90,7 +90,7 @@ TEST(LlvmLibcStrToDblTest, SimpleDecimalConversionExtraTypes) { uint64_t double_output_mantissa = 0; uint32_t output_exp2 = 0; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; auto double_result = internal::simple_decimal_conversion("123456789012345678900"); diff --git a/libc/test/src/__support/str_to_float_test.cpp b/libc/test/src/__support/str_to_float_test.cpp index 3102fa7aa91e..f23d8706d77d 100644 --- a/libc/test/src/__support/str_to_float_test.cpp +++ b/libc/test/src/__support/str_to_float_test.cpp @@ -46,7 +46,7 @@ TEST(LlvmLibcStrToFltTest, SimpleDecimalConversionExtraTypes) { uint32_t float_output_mantissa = 0; uint32_t output_exp2 = 0; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; auto float_result = internal::simple_decimal_conversion("123456789012345678900"); float_output_mantissa = float_result.num.mantissa; diff --git a/libc/test/src/__support/str_to_fp_test.h b/libc/test/src/__support/str_to_fp_test.h index 32a313309392..bddff035fdd1 100644 --- a/libc/test/src/__support/str_to_fp_test.h +++ b/libc/test/src/__support/str_to_fp_test.h @@ -66,7 +66,7 @@ template struct LlvmLibcStrToFloatTest : public testing::Test { const int expectedErrno = 0) { StorageType actual_output_mantissa = 0; uint32_t actual_output_exp2 = 0; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; auto result = internal::simple_decimal_conversion(numStart); diff --git a/libc/test/src/dirent/dirent_test.cpp b/libc/test/src/dirent/dirent_test.cpp index e2e0399673be..41f522a6a75f 100644 --- a/libc/test/src/dirent/dirent_test.cpp +++ b/libc/test/src/dirent/dirent_test.cpp @@ -55,17 +55,17 @@ TEST(LlvmLibcDirentTest, SimpleOpenAndRead) { } TEST(LlvmLibcDirentTest, OpenNonExistentDir) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ::DIR *dir = LIBC_NAMESPACE::opendir("___xyz123__.non_existent__"); ASSERT_TRUE(dir == nullptr); ASSERT_ERRNO_EQ(ENOENT); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; } TEST(LlvmLibcDirentTest, OpenFile) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ::DIR *dir = LIBC_NAMESPACE::opendir("testdata/file1.txt"); ASSERT_TRUE(dir == nullptr); ASSERT_ERRNO_EQ(ENOTDIR); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; } diff --git a/libc/test/src/errno/errno_test.cpp b/libc/test/src/errno/errno_test.cpp index 876ebfc0ac26..b0db22a85f3b 100644 --- a/libc/test/src/errno/errno_test.cpp +++ b/libc/test/src/errno/errno_test.cpp @@ -11,6 +11,6 @@ TEST(LlvmLibcErrnoTest, Basic) { int test_val = 123; - libc_errno = test_val; + LIBC_NAMESPACE::libc_errno = test_val; ASSERT_ERRNO_EQ(test_val); } diff --git a/libc/test/src/math/RoundToIntegerTest.h b/libc/test/src/math/RoundToIntegerTest.h index 5239528c9246..9bd4ba52f61b 100644 --- a/libc/test/src/math/RoundToIntegerTest.h +++ b/libc/test/src/math/RoundToIntegerTest.h @@ -51,7 +51,7 @@ private: void test_one_input(RoundToIntegerFunc func, F input, I expected, bool expectError) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; LIBC_NAMESPACE::fputil::clear_except(FE_ALL_EXCEPT); ASSERT_EQ(func(input), expected); diff --git a/libc/test/src/math/acosf_test.cpp b/libc/test/src/math/acosf_test.cpp index 81f697c315a2..c273184d58f3 100644 --- a/libc/test/src/math/acosf_test.cpp +++ b/libc/test/src/math/acosf_test.cpp @@ -22,7 +22,7 @@ namespace mpfr = LIBC_NAMESPACE::testing::mpfr; using LlvmLibcAcosfTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcAcosfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::acosf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/math/acoshf_test.cpp b/libc/test/src/math/acoshf_test.cpp index 6d43105c83c2..a0e845b2b247 100644 --- a/libc/test/src/math/acoshf_test.cpp +++ b/libc/test/src/math/acoshf_test.cpp @@ -22,7 +22,7 @@ using LlvmLibcAcoshfTest = LIBC_NAMESPACE::testing::FPTest; namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcAcoshfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::acoshf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/math/asinf_test.cpp b/libc/test/src/math/asinf_test.cpp index 77ac2bc216f7..a24fdcc36e14 100644 --- a/libc/test/src/math/asinf_test.cpp +++ b/libc/test/src/math/asinf_test.cpp @@ -23,7 +23,7 @@ using LlvmLibcAsinfTest = LIBC_NAMESPACE::testing::FPTest; namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcAsinfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::asinf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/math/asinhf_test.cpp b/libc/test/src/math/asinhf_test.cpp index 9b925bf254a9..3127861c9a1b 100644 --- a/libc/test/src/math/asinhf_test.cpp +++ b/libc/test/src/math/asinhf_test.cpp @@ -22,7 +22,7 @@ using LlvmLibcAsinhfTest = LIBC_NAMESPACE::testing::FPTest; namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcAsinhfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::asinhf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/math/atanf_test.cpp b/libc/test/src/math/atanf_test.cpp index b5d30fbd5679..1fa7165805c7 100644 --- a/libc/test/src/math/atanf_test.cpp +++ b/libc/test/src/math/atanf_test.cpp @@ -22,7 +22,7 @@ using LlvmLibcAtanfTest = LIBC_NAMESPACE::testing::FPTest; namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcAtanfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; LIBC_NAMESPACE::fputil::clear_except(FE_ALL_EXCEPT); EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::atanf(aNaN)); EXPECT_FP_EXCEPTION(0); diff --git a/libc/test/src/math/atanhf_test.cpp b/libc/test/src/math/atanhf_test.cpp index 9dea65dccd8f..1b45436094da 100644 --- a/libc/test/src/math/atanhf_test.cpp +++ b/libc/test/src/math/atanhf_test.cpp @@ -23,7 +23,7 @@ namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcAtanhfTest, SpecialNumbers) { using Sign = LIBC_NAMESPACE::fputil::Sign; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; LIBC_NAMESPACE::fputil::clear_except(FE_ALL_EXCEPT); EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::atanhf(aNaN)); EXPECT_FP_EXCEPTION(0); diff --git a/libc/test/src/math/cosf_test.cpp b/libc/test/src/math/cosf_test.cpp index 9a988d76c598..93ab06dc80b2 100644 --- a/libc/test/src/math/cosf_test.cpp +++ b/libc/test/src/math/cosf_test.cpp @@ -24,7 +24,7 @@ using LlvmLibcCosfTest = LIBC_NAMESPACE::testing::FPTest; namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcCosfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ(aNaN, LIBC_NAMESPACE::cosf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/math/coshf_test.cpp b/libc/test/src/math/coshf_test.cpp index 843ecb8925ad..3b8e14fb5f03 100644 --- a/libc/test/src/math/coshf_test.cpp +++ b/libc/test/src/math/coshf_test.cpp @@ -23,7 +23,7 @@ using LlvmLibcCoshfTest = LIBC_NAMESPACE::testing::FPTest; namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcCoshfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ(aNaN, LIBC_NAMESPACE::coshf(aNaN)); EXPECT_MATH_ERRNO(0); @@ -42,7 +42,7 @@ TEST_F(LlvmLibcCoshfTest, SpecialNumbers) { } TEST_F(LlvmLibcCoshfTest, Overflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_WITH_EXCEPTION( inf, LIBC_NAMESPACE::coshf(FPBits(0x7f7fffffU).get_val()), FE_OVERFLOW); EXPECT_MATH_ERRNO(ERANGE); diff --git a/libc/test/src/math/exp10_test.cpp b/libc/test/src/math/exp10_test.cpp index e9990b3ed8e6..d71b5a223037 100644 --- a/libc/test/src/math/exp10_test.cpp +++ b/libc/test/src/math/exp10_test.cpp @@ -106,7 +106,7 @@ TEST_F(LlvmLibcExp10Test, InDoubleRange) { double x = FPBits(v).get_val(); if (isnan(x) || isinf(x) || x < 0.0) continue; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; double result = LIBC_NAMESPACE::exp10(x); ++cc; if (isnan(result) || isinf(result)) diff --git a/libc/test/src/math/exp10f_test.cpp b/libc/test/src/math/exp10f_test.cpp index 0866488935c2..4e2d065f1292 100644 --- a/libc/test/src/math/exp10f_test.cpp +++ b/libc/test/src/math/exp10f_test.cpp @@ -21,7 +21,7 @@ using LlvmLibcExp10fTest = LIBC_NAMESPACE::testing::FPTest; namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcExp10fTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ(aNaN, LIBC_NAMESPACE::exp10f(aNaN)); EXPECT_MATH_ERRNO(0); @@ -40,7 +40,7 @@ TEST_F(LlvmLibcExp10fTest, SpecialNumbers) { } TEST_F(LlvmLibcExp10fTest, Overflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_WITH_EXCEPTION( inf, LIBC_NAMESPACE::exp10f(FPBits(0x7f7fffffU).get_val()), FE_OVERFLOW); EXPECT_MATH_ERRNO(ERANGE); @@ -55,7 +55,7 @@ TEST_F(LlvmLibcExp10fTest, Overflow) { } TEST_F(LlvmLibcExp10fTest, Underflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_WITH_EXCEPTION( 0.0f, LIBC_NAMESPACE::exp10f(FPBits(0xff7fffffU).get_val()), FE_UNDERFLOW); @@ -97,7 +97,7 @@ TEST_F(LlvmLibcExp10fTest, TrickyInputs) { 0x41200000, // x = 10.0f }; for (int i = 0; i < N; ++i) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; float x = FPBits(INPUTS[i]).get_val(); EXPECT_MPFR_MATCH_ALL_ROUNDING(mpfr::Operation::Exp10, x, LIBC_NAMESPACE::exp10f(x), 0.5); @@ -113,14 +113,14 @@ TEST_F(LlvmLibcExp10fTest, InFloatRange) { float x = FPBits(v).get_val(); if (isnan(x) || isinf(x)) continue; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; float result = LIBC_NAMESPACE::exp10f(x); // If the computation resulted in an error or did not produce valid result // in the single-precision floating point range, then ignore comparing with // MPFR result as MPFR can still produce valid results because of its // wider precision. - if (isnan(result) || isinf(result) || libc_errno != 0) + if (isnan(result) || isinf(result) || LIBC_NAMESPACE::libc_errno != 0) continue; ASSERT_MPFR_MATCH_ALL_ROUNDING(mpfr::Operation::Exp10, x, LIBC_NAMESPACE::exp10f(x), 0.5); diff --git a/libc/test/src/math/exp2_test.cpp b/libc/test/src/math/exp2_test.cpp index d66c9b757625..2f9d7b3a2a6c 100644 --- a/libc/test/src/math/exp2_test.cpp +++ b/libc/test/src/math/exp2_test.cpp @@ -81,7 +81,7 @@ TEST_F(LlvmLibcExp2Test, InDoubleRange) { double x = FPBits(v).get_val(); if (isnan(x) || isinf(x) || x < 0.0) continue; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; double result = LIBC_NAMESPACE::exp2(x); ++cc; if (isnan(result) || isinf(result)) diff --git a/libc/test/src/math/exp2f_test.cpp b/libc/test/src/math/exp2f_test.cpp index 18607b1d0491..f5ea8554be5c 100644 --- a/libc/test/src/math/exp2f_test.cpp +++ b/libc/test/src/math/exp2f_test.cpp @@ -22,7 +22,7 @@ using LlvmLibcExp2fTest = LIBC_NAMESPACE::testing::FPTest; namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcExp2fTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ(aNaN, LIBC_NAMESPACE::exp2f(aNaN)); EXPECT_MATH_ERRNO(0); @@ -41,7 +41,7 @@ TEST_F(LlvmLibcExp2fTest, SpecialNumbers) { } TEST_F(LlvmLibcExp2fTest, Overflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_WITH_EXCEPTION( inf, LIBC_NAMESPACE::exp2f(FPBits(0x7f7fffffU).get_val()), FE_OVERFLOW); EXPECT_MATH_ERRNO(ERANGE); @@ -72,7 +72,7 @@ TEST_F(LlvmLibcExp2fTest, TrickyInputs) { 0xc3150000U, /*-0x1.2ap+7f*/ }; for (int i = 0; i < N; ++i) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; float x = FPBits(INPUTS[i]).get_val(); EXPECT_MPFR_MATCH_ALL_ROUNDING(mpfr::Operation::Exp2, x, LIBC_NAMESPACE::exp2f(x), 0.5); @@ -81,7 +81,7 @@ TEST_F(LlvmLibcExp2fTest, TrickyInputs) { } TEST_F(LlvmLibcExp2fTest, Underflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_WITH_EXCEPTION( 0.0f, LIBC_NAMESPACE::exp2f(FPBits(0xff7fffffU).get_val()), FE_UNDERFLOW); EXPECT_MATH_ERRNO(ERANGE); @@ -109,14 +109,14 @@ TEST_F(LlvmLibcExp2fTest, InFloatRange) { float x = FPBits(v).get_val(); if (isnan(x) || isinf(x)) continue; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; float result = LIBC_NAMESPACE::exp2f(x); // If the computation resulted in an error or did not produce valid result // in the single-precision floating point range, then ignore comparing with // MPFR result as MPFR can still produce valid results because of its // wider precision. - if (isnan(result) || isinf(result) || libc_errno != 0) + if (isnan(result) || isinf(result) || LIBC_NAMESPACE::libc_errno != 0) continue; ASSERT_MPFR_MATCH_ALL_ROUNDING(mpfr::Operation::Exp2, x, LIBC_NAMESPACE::exp2f(x), 0.5); diff --git a/libc/test/src/math/exp_test.cpp b/libc/test/src/math/exp_test.cpp index 454107f307d8..006db00b9194 100644 --- a/libc/test/src/math/exp_test.cpp +++ b/libc/test/src/math/exp_test.cpp @@ -79,7 +79,7 @@ TEST_F(LlvmLibcExpTest, InDoubleRange) { double x = FPBits(v).get_val(); if (isnan(x) || isinf(x) || x < 0.0) continue; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; double result = LIBC_NAMESPACE::exp(x); ++cc; if (isnan(result) || isinf(result)) diff --git a/libc/test/src/math/expf_test.cpp b/libc/test/src/math/expf_test.cpp index 0ac64ceec1c7..ffd9da500488 100644 --- a/libc/test/src/math/expf_test.cpp +++ b/libc/test/src/math/expf_test.cpp @@ -21,7 +21,7 @@ using LlvmLibcExpfTest = LIBC_NAMESPACE::testing::FPTest; namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcExpfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ(aNaN, LIBC_NAMESPACE::expf(aNaN)); EXPECT_MATH_ERRNO(0); @@ -40,7 +40,7 @@ TEST_F(LlvmLibcExpfTest, SpecialNumbers) { } TEST_F(LlvmLibcExpfTest, Overflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_WITH_EXCEPTION( inf, LIBC_NAMESPACE::expf(FPBits(0x7f7fffffU).get_val()), FE_OVERFLOW); EXPECT_MATH_ERRNO(ERANGE); @@ -55,7 +55,7 @@ TEST_F(LlvmLibcExpfTest, Overflow) { } TEST_F(LlvmLibcExpfTest, Underflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_WITH_EXCEPTION( 0.0f, LIBC_NAMESPACE::expf(FPBits(0xff7fffffU).get_val()), FE_UNDERFLOW); EXPECT_MATH_ERRNO(ERANGE); @@ -76,7 +76,7 @@ TEST_F(LlvmLibcExpfTest, Underflow) { TEST_F(LlvmLibcExpfTest, Borderline) { float x; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; x = FPBits(0x42affff8U).get_val(); ASSERT_MPFR_MATCH_ALL_ROUNDING(mpfr::Operation::Exp, x, LIBC_NAMESPACE::expf(x), 0.5); @@ -110,14 +110,14 @@ TEST_F(LlvmLibcExpfTest, InFloatRange) { float x = FPBits(v).get_val(); if (isnan(x) || isinf(x)) continue; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; float result = LIBC_NAMESPACE::expf(x); // If the computation resulted in an error or did not produce valid result // in the single-precision floating point range, then ignore comparing with // MPFR result as MPFR can still produce valid results because of its // wider precision. - if (isnan(result) || isinf(result) || libc_errno != 0) + if (isnan(result) || isinf(result) || LIBC_NAMESPACE::libc_errno != 0) continue; EXPECT_MPFR_MATCH_ALL_ROUNDING(mpfr::Operation::Exp, x, LIBC_NAMESPACE::expf(x), 0.5); diff --git a/libc/test/src/math/expm1_test.cpp b/libc/test/src/math/expm1_test.cpp index 99ef8275eab7..ccc6e3609548 100644 --- a/libc/test/src/math/expm1_test.cpp +++ b/libc/test/src/math/expm1_test.cpp @@ -75,7 +75,7 @@ TEST_F(LlvmLibcExpm1Test, InDoubleRange) { double x = FPBits(v).get_val(); if (isnan(x) || isinf(x) || x < 0.0) continue; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; double result = LIBC_NAMESPACE::expm1(x); ++cc; if (isnan(result) || isinf(result)) diff --git a/libc/test/src/math/expm1f_test.cpp b/libc/test/src/math/expm1f_test.cpp index cc820803cc30..94a9301f8eb2 100644 --- a/libc/test/src/math/expm1f_test.cpp +++ b/libc/test/src/math/expm1f_test.cpp @@ -21,7 +21,7 @@ using LlvmLibcExpm1fTest = LIBC_NAMESPACE::testing::FPTest; namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcExpm1fTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ(aNaN, LIBC_NAMESPACE::expm1f(aNaN)); EXPECT_MATH_ERRNO(0); @@ -40,7 +40,7 @@ TEST_F(LlvmLibcExpm1fTest, SpecialNumbers) { } TEST_F(LlvmLibcExpm1fTest, Overflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_WITH_EXCEPTION( inf, LIBC_NAMESPACE::expm1f(FPBits(0x7f7fffffU).get_val()), FE_OVERFLOW); EXPECT_MATH_ERRNO(ERANGE); @@ -55,7 +55,7 @@ TEST_F(LlvmLibcExpm1fTest, Overflow) { } TEST_F(LlvmLibcExpm1fTest, Underflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ(-1.0f, LIBC_NAMESPACE::expm1f(FPBits(0xff7fffffU).get_val())); float x = FPBits(0xc2cffff8U).get_val(); @@ -70,7 +70,7 @@ TEST_F(LlvmLibcExpm1fTest, Underflow) { TEST_F(LlvmLibcExpm1fTest, Borderline) { float x; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; x = FPBits(0x42affff8U).get_val(); ASSERT_MPFR_MATCH_ALL_ROUNDING(mpfr::Operation::Expm1, x, LIBC_NAMESPACE::expm1f(x), 0.5); @@ -119,14 +119,14 @@ TEST_F(LlvmLibcExpm1fTest, InFloatRange) { float x = FPBits(v).get_val(); if (isnan(x) || isinf(x)) continue; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; float result = LIBC_NAMESPACE::expm1f(x); // If the computation resulted in an error or did not produce valid result // in the single-precision floating point range, then ignore comparing with // MPFR result as MPFR can still produce valid results because of its // wider precision. - if (isnan(result) || isinf(result) || libc_errno != 0) + if (isnan(result) || isinf(result) || LIBC_NAMESPACE::libc_errno != 0) continue; ASSERT_MPFR_MATCH_ALL_ROUNDING(mpfr::Operation::Expm1, x, LIBC_NAMESPACE::expm1f(x), 0.5); diff --git a/libc/test/src/math/log10_test.cpp b/libc/test/src/math/log10_test.cpp index de9206f2daec..ed4a24b95159 100644 --- a/libc/test/src/math/log10_test.cpp +++ b/libc/test/src/math/log10_test.cpp @@ -102,7 +102,7 @@ TEST_F(LlvmLibcLog10Test, InDoubleRange) { double x = FPBits(v).get_val(); if (isnan(x) || isinf(x) || x < 0.0) continue; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; double result = LIBC_NAMESPACE::log10(x); ++cc; if (isnan(result) || isinf(result)) diff --git a/libc/test/src/math/log1p_test.cpp b/libc/test/src/math/log1p_test.cpp index f70c0f87560c..d769659356c9 100644 --- a/libc/test/src/math/log1p_test.cpp +++ b/libc/test/src/math/log1p_test.cpp @@ -102,7 +102,7 @@ TEST_F(LlvmLibcLog1pTest, InDoubleRange) { double x = FPBits(v).get_val(); if (isnan(x) || isinf(x) || x < 0.0) continue; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; double result = LIBC_NAMESPACE::log1p(x); ++cc; if (isnan(result) || isinf(result)) diff --git a/libc/test/src/math/log1pf_test.cpp b/libc/test/src/math/log1pf_test.cpp index 37144838552c..2f6330ee6ce6 100644 --- a/libc/test/src/math/log1pf_test.cpp +++ b/libc/test/src/math/log1pf_test.cpp @@ -76,7 +76,7 @@ TEST_F(LlvmLibcLog1pfTest, InFloatRange) { float x = FPBits(v).get_val(); if (isnan(x) || isinf(x)) continue; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_MPFR_MATCH_ALL_ROUNDING(mpfr::Operation::Log1p, x, LIBC_NAMESPACE::log1pf(x), 0.5); } diff --git a/libc/test/src/math/log2_test.cpp b/libc/test/src/math/log2_test.cpp index 65eae58b3508..f4ee0ff5185b 100644 --- a/libc/test/src/math/log2_test.cpp +++ b/libc/test/src/math/log2_test.cpp @@ -101,7 +101,7 @@ TEST_F(LlvmLibcLog2Test, InDoubleRange) { double x = FPBits(v).get_val(); if (isnan(x) || isinf(x) || x < 0.0) continue; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; double result = LIBC_NAMESPACE::log2(x); ++cc; if (isnan(result) || isinf(result)) diff --git a/libc/test/src/math/log2f_test.cpp b/libc/test/src/math/log2f_test.cpp index 0793bf8a0409..d8b4808f5cda 100644 --- a/libc/test/src/math/log2f_test.cpp +++ b/libc/test/src/math/log2f_test.cpp @@ -52,13 +52,13 @@ TEST_F(LlvmLibcLog2fTest, InFloatRange) { float x = FPBits(v).get_val(); if (isnan(x) || isinf(x)) continue; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; float result = LIBC_NAMESPACE::log2f(x); // If the computation resulted in an error or did not produce valid result // in the single-precision floating point range, then ignore comparing with // MPFR result as MPFR can still produce valid results because of its // wider precision. - if (isnan(result) || isinf(result) || libc_errno != 0) + if (isnan(result) || isinf(result) || LIBC_NAMESPACE::libc_errno != 0) continue; ASSERT_MPFR_MATCH_ALL_ROUNDING(mpfr::Operation::Log2, x, LIBC_NAMESPACE::log2f(x), 0.5); diff --git a/libc/test/src/math/log_test.cpp b/libc/test/src/math/log_test.cpp index 457117c1757a..b1f1ab775462 100644 --- a/libc/test/src/math/log_test.cpp +++ b/libc/test/src/math/log_test.cpp @@ -100,7 +100,7 @@ TEST_F(LlvmLibcLogTest, InDoubleRange) { double x = FPBits(v).get_val(); if (isnan(x) || isinf(x) || x < 0.0) continue; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; double result = LIBC_NAMESPACE::log(x); ++cc; if (isnan(result) || isinf(result)) diff --git a/libc/test/src/math/powf_test.cpp b/libc/test/src/math/powf_test.cpp index 608bd85bbf0c..3dffeb603499 100644 --- a/libc/test/src/math/powf_test.cpp +++ b/libc/test/src/math/powf_test.cpp @@ -72,7 +72,7 @@ TEST_F(LlvmLibcPowfTest, InFloatRange) { if (isnan(y) || isinf(y)) continue; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; float result = LIBC_NAMESPACE::powf(x, y); ++cc; if (isnan(result) || isinf(result)) diff --git a/libc/test/src/math/sincosf_test.cpp b/libc/test/src/math/sincosf_test.cpp index 76fda6354f63..2c0c7eaaa25f 100644 --- a/libc/test/src/math/sincosf_test.cpp +++ b/libc/test/src/math/sincosf_test.cpp @@ -25,7 +25,7 @@ using LIBC_NAMESPACE::testing::SDCOMP26094_VALUES; namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcSinCosfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; float sin, cos; LIBC_NAMESPACE::sincosf(aNaN, &sin, &cos); diff --git a/libc/test/src/math/sinf_test.cpp b/libc/test/src/math/sinf_test.cpp index 32afc4f1c60d..94c1114e6889 100644 --- a/libc/test/src/math/sinf_test.cpp +++ b/libc/test/src/math/sinf_test.cpp @@ -25,7 +25,7 @@ using LIBC_NAMESPACE::testing::SDCOMP26094_VALUES; namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcSinfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ(aNaN, LIBC_NAMESPACE::sinf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/math/sinhf_test.cpp b/libc/test/src/math/sinhf_test.cpp index 765fdc6c2bcc..f14150bb0442 100644 --- a/libc/test/src/math/sinhf_test.cpp +++ b/libc/test/src/math/sinhf_test.cpp @@ -23,7 +23,7 @@ using LlvmLibcSinhfTest = LIBC_NAMESPACE::testing::FPTest; namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcSinhfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ(aNaN, LIBC_NAMESPACE::sinhf(aNaN)); EXPECT_MATH_ERRNO(0); @@ -66,7 +66,7 @@ TEST_F(LlvmLibcSinhfTest, SmallValues) { } TEST_F(LlvmLibcSinhfTest, Overflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_WITH_EXCEPTION( inf, LIBC_NAMESPACE::sinhf(FPBits(0x7f7fffffU).get_val()), FE_OVERFLOW); EXPECT_MATH_ERRNO(ERANGE); diff --git a/libc/test/src/math/smoke/RoundToIntegerTest.h b/libc/test/src/math/smoke/RoundToIntegerTest.h index 1fdff23e9159..59694131f7f5 100644 --- a/libc/test/src/math/smoke/RoundToIntegerTest.h +++ b/libc/test/src/math/smoke/RoundToIntegerTest.h @@ -46,7 +46,7 @@ private: void test_one_input(RoundToIntegerFunc func, F input, I expected, bool expectError) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; LIBC_NAMESPACE::fputil::clear_except(FE_ALL_EXCEPT); ASSERT_EQ(func(input), expected); diff --git a/libc/test/src/math/smoke/acosf_test.cpp b/libc/test/src/math/smoke/acosf_test.cpp index 2d8fba96718c..864c9ea4d317 100644 --- a/libc/test/src/math/smoke/acosf_test.cpp +++ b/libc/test/src/math/smoke/acosf_test.cpp @@ -19,7 +19,7 @@ using LlvmLibcAcosfTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcAcosfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::acosf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/math/smoke/acoshf_test.cpp b/libc/test/src/math/smoke/acoshf_test.cpp index 85c24e08ab79..b3ba740c2024 100644 --- a/libc/test/src/math/smoke/acoshf_test.cpp +++ b/libc/test/src/math/smoke/acoshf_test.cpp @@ -19,7 +19,7 @@ using LlvmLibcAcoshfTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcAcoshfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::acoshf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/math/smoke/asinf_test.cpp b/libc/test/src/math/smoke/asinf_test.cpp index 57bb7dcf6e84..e6afb23a397f 100644 --- a/libc/test/src/math/smoke/asinf_test.cpp +++ b/libc/test/src/math/smoke/asinf_test.cpp @@ -19,7 +19,7 @@ using LlvmLibcAsinfTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcAsinfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::asinf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/math/smoke/asinhf_test.cpp b/libc/test/src/math/smoke/asinhf_test.cpp index 0c6ac537ef1c..7a520cdc050a 100644 --- a/libc/test/src/math/smoke/asinhf_test.cpp +++ b/libc/test/src/math/smoke/asinhf_test.cpp @@ -19,7 +19,7 @@ using LlvmLibcAsinhfTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcAsinhfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::asinhf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/math/smoke/atanf_test.cpp b/libc/test/src/math/smoke/atanf_test.cpp index 156ce0744b0e..8cc1b418f869 100644 --- a/libc/test/src/math/smoke/atanf_test.cpp +++ b/libc/test/src/math/smoke/atanf_test.cpp @@ -19,7 +19,7 @@ using LlvmLibcAtanfTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcAtanfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; LIBC_NAMESPACE::fputil::clear_except(FE_ALL_EXCEPT); EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::atanf(aNaN)); diff --git a/libc/test/src/math/smoke/atanhf_test.cpp b/libc/test/src/math/smoke/atanhf_test.cpp index c613f9bdf35f..e1d6d2532d39 100644 --- a/libc/test/src/math/smoke/atanhf_test.cpp +++ b/libc/test/src/math/smoke/atanhf_test.cpp @@ -20,7 +20,7 @@ using LlvmLibcAtanhfTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcAtanhfTest, SpecialNumbers) { using Sign = LIBC_NAMESPACE::fputil::Sign; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; LIBC_NAMESPACE::fputil::clear_except(FE_ALL_EXCEPT); EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::atanhf(aNaN)); diff --git a/libc/test/src/math/smoke/cosf_test.cpp b/libc/test/src/math/smoke/cosf_test.cpp index c9efc791885f..539c428eadf1 100644 --- a/libc/test/src/math/smoke/cosf_test.cpp +++ b/libc/test/src/math/smoke/cosf_test.cpp @@ -19,7 +19,7 @@ using LlvmLibcCosfTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcCosfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::cosf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/math/smoke/coshf_test.cpp b/libc/test/src/math/smoke/coshf_test.cpp index aa224dcc156f..e38802f93647 100644 --- a/libc/test/src/math/smoke/coshf_test.cpp +++ b/libc/test/src/math/smoke/coshf_test.cpp @@ -20,7 +20,7 @@ using LlvmLibcCoshfTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcCoshfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::coshf(aNaN)); EXPECT_MATH_ERRNO(0); @@ -39,7 +39,7 @@ TEST_F(LlvmLibcCoshfTest, SpecialNumbers) { } TEST_F(LlvmLibcCoshfTest, Overflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_WITH_EXCEPTION( inf, LIBC_NAMESPACE::coshf(FPBits(0x7f7fffffU).get_val()), FE_OVERFLOW); EXPECT_MATH_ERRNO(ERANGE); diff --git a/libc/test/src/math/smoke/exp10f_test.cpp b/libc/test/src/math/smoke/exp10f_test.cpp index d242edf04fb3..f6533e983dac 100644 --- a/libc/test/src/math/smoke/exp10f_test.cpp +++ b/libc/test/src/math/smoke/exp10f_test.cpp @@ -18,7 +18,7 @@ using LlvmLibcExp10fTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcExp10fTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::exp10f(aNaN)); EXPECT_MATH_ERRNO(0); @@ -41,7 +41,7 @@ TEST_F(LlvmLibcExp10fTest, SpecialNumbers) { } TEST_F(LlvmLibcExp10fTest, Overflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_WITH_EXCEPTION( inf, LIBC_NAMESPACE::exp10f(FPBits(0x7f7fffffU).get_val()), FE_OVERFLOW); EXPECT_MATH_ERRNO(ERANGE); diff --git a/libc/test/src/math/smoke/exp2f_test.cpp b/libc/test/src/math/smoke/exp2f_test.cpp index e4e56ed23bcf..7baab630a4cb 100644 --- a/libc/test/src/math/smoke/exp2f_test.cpp +++ b/libc/test/src/math/smoke/exp2f_test.cpp @@ -19,7 +19,7 @@ using LlvmLibcExp2fTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcExp2fTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::exp2f(aNaN)); EXPECT_MATH_ERRNO(0); @@ -43,7 +43,7 @@ TEST_F(LlvmLibcExp2fTest, SpecialNumbers) { } TEST_F(LlvmLibcExp2fTest, Overflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_WITH_EXCEPTION( inf, LIBC_NAMESPACE::exp2f(FPBits(0x7f7fffffU).get_val()), FE_OVERFLOW); EXPECT_MATH_ERRNO(ERANGE); diff --git a/libc/test/src/math/smoke/expf_test.cpp b/libc/test/src/math/smoke/expf_test.cpp index 24fc35b552ca..2968704f83e3 100644 --- a/libc/test/src/math/smoke/expf_test.cpp +++ b/libc/test/src/math/smoke/expf_test.cpp @@ -18,7 +18,7 @@ using LlvmLibcExpfTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcExpfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::expf(aNaN)); EXPECT_MATH_ERRNO(0); @@ -37,7 +37,7 @@ TEST_F(LlvmLibcExpfTest, SpecialNumbers) { } TEST_F(LlvmLibcExpfTest, Overflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_WITH_EXCEPTION( inf, LIBC_NAMESPACE::expf(FPBits(0x7f7fffffU).get_val()), FE_OVERFLOW); EXPECT_MATH_ERRNO(ERANGE); diff --git a/libc/test/src/math/smoke/expm1f_test.cpp b/libc/test/src/math/smoke/expm1f_test.cpp index 3d6dae77ec00..4ef8d50ba551 100644 --- a/libc/test/src/math/smoke/expm1f_test.cpp +++ b/libc/test/src/math/smoke/expm1f_test.cpp @@ -18,7 +18,7 @@ using LlvmLibcExpm1fTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcExpm1fTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::expm1f(aNaN)); EXPECT_MATH_ERRNO(0); @@ -37,7 +37,7 @@ TEST_F(LlvmLibcExpm1fTest, SpecialNumbers) { } TEST_F(LlvmLibcExpm1fTest, Overflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_WITH_EXCEPTION( inf, LIBC_NAMESPACE::expm1f(FPBits(0x7f7fffffU).get_val()), FE_OVERFLOW); EXPECT_MATH_ERRNO(ERANGE); diff --git a/libc/test/src/math/smoke/sincosf_test.cpp b/libc/test/src/math/smoke/sincosf_test.cpp index 0de47f3307fe..a1447ad57e11 100644 --- a/libc/test/src/math/smoke/sincosf_test.cpp +++ b/libc/test/src/math/smoke/sincosf_test.cpp @@ -19,7 +19,7 @@ using LlvmLibcSinCosfTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcSinCosfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; float sin, cos; LIBC_NAMESPACE::sincosf(aNaN, &sin, &cos); diff --git a/libc/test/src/math/smoke/sinf_test.cpp b/libc/test/src/math/smoke/sinf_test.cpp index bbd7634e0028..e51726646bc6 100644 --- a/libc/test/src/math/smoke/sinf_test.cpp +++ b/libc/test/src/math/smoke/sinf_test.cpp @@ -19,7 +19,7 @@ using LlvmLibcSinfTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcSinfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ(aNaN, LIBC_NAMESPACE::sinf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/math/smoke/sinhf_test.cpp b/libc/test/src/math/smoke/sinhf_test.cpp index 0563ccbf77aa..23334293b73f 100644 --- a/libc/test/src/math/smoke/sinhf_test.cpp +++ b/libc/test/src/math/smoke/sinhf_test.cpp @@ -20,7 +20,7 @@ using LlvmLibcSinhfTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcSinhfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ(aNaN, LIBC_NAMESPACE::sinhf(aNaN)); EXPECT_MATH_ERRNO(0); @@ -50,7 +50,7 @@ TEST_F(LlvmLibcSinhfTest, SmallValues) { } TEST_F(LlvmLibcSinhfTest, Overflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_WITH_EXCEPTION( inf, LIBC_NAMESPACE::sinhf(FPBits(0x7f7fffffU).get_val()), FE_OVERFLOW); EXPECT_MATH_ERRNO(ERANGE); diff --git a/libc/test/src/math/smoke/tanf_test.cpp b/libc/test/src/math/smoke/tanf_test.cpp index fa93da29829a..53a153254b31 100644 --- a/libc/test/src/math/smoke/tanf_test.cpp +++ b/libc/test/src/math/smoke/tanf_test.cpp @@ -19,7 +19,7 @@ using LlvmLibcTanfTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcTanfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ(aNaN, LIBC_NAMESPACE::tanf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/math/smoke/tanhf_test.cpp b/libc/test/src/math/smoke/tanhf_test.cpp index f32e8cc9591f..7cb80dca7919 100644 --- a/libc/test/src/math/smoke/tanhf_test.cpp +++ b/libc/test/src/math/smoke/tanhf_test.cpp @@ -19,7 +19,7 @@ using LlvmLibcTanhfTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcTanhfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ(aNaN, LIBC_NAMESPACE::tanhf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/math/tanf_test.cpp b/libc/test/src/math/tanf_test.cpp index 5621e819522f..c8d9d52e3f69 100644 --- a/libc/test/src/math/tanf_test.cpp +++ b/libc/test/src/math/tanf_test.cpp @@ -25,7 +25,7 @@ using LIBC_NAMESPACE::testing::SDCOMP26094_VALUES; namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcTanfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ(aNaN, LIBC_NAMESPACE::tanf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/math/tanhf_test.cpp b/libc/test/src/math/tanhf_test.cpp index 862ba6cc7eeb..28da7ffbeddd 100644 --- a/libc/test/src/math/tanhf_test.cpp +++ b/libc/test/src/math/tanhf_test.cpp @@ -22,7 +22,7 @@ using LlvmLibcTanhfTest = LIBC_NAMESPACE::testing::FPTest; namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcTanhfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ(aNaN, LIBC_NAMESPACE::tanhf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/sched/affinity_test.cpp b/libc/test/src/sched/affinity_test.cpp index 38433edecbd0..b5085203e5ce 100644 --- a/libc/test/src/sched/affinity_test.cpp +++ b/libc/test/src/sched/affinity_test.cpp @@ -17,7 +17,7 @@ TEST(LlvmLibcSchedAffinityTest, SmokeTest) { cpu_set_t mask; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; pid_t tid = LIBC_NAMESPACE::syscall_impl(SYS_gettid); ASSERT_GT(tid, pid_t(0)); @@ -32,15 +32,15 @@ TEST(LlvmLibcSchedAffinityTest, BadMask) { using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; pid_t tid = LIBC_NAMESPACE::syscall_impl(SYS_gettid); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_THAT( LIBC_NAMESPACE::sched_getaffinity(tid, sizeof(cpu_set_t), nullptr), Fails(EFAULT)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_THAT( LIBC_NAMESPACE::sched_setaffinity(tid, sizeof(cpu_set_t), nullptr), Fails(EFAULT)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; } diff --git a/libc/test/src/sched/cpu_count_test.cpp b/libc/test/src/sched/cpu_count_test.cpp index ca3e80818a5c..5250368a2616 100644 --- a/libc/test/src/sched/cpu_count_test.cpp +++ b/libc/test/src/sched/cpu_count_test.cpp @@ -17,7 +17,7 @@ TEST(LlvmLibcSchedCpuCountTest, SmokeTest) { cpu_set_t mask; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; pid_t tid = LIBC_NAMESPACE::syscall_impl(SYS_gettid); ASSERT_GT(tid, pid_t(0)); diff --git a/libc/test/src/sched/get_priority_test.cpp b/libc/test/src/sched/get_priority_test.cpp index 4ff7890c4f40..59205c51e4a1 100644 --- a/libc/test/src/sched/get_priority_test.cpp +++ b/libc/test/src/sched/get_priority_test.cpp @@ -58,7 +58,7 @@ TEST(LlvmLibcSchedGetPriorityTest, HandleBadPolicyTest) { } TEST(LlvmLibcSchedGetPriorityTest, SmokeTest) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // We Test: // SCHED_OTHER, SCHED_FIFO, SCHED_RR diff --git a/libc/test/src/sched/param_and_scheduler_test.cpp b/libc/test/src/sched/param_and_scheduler_test.cpp index 7fcb667a31a9..8e81f2ed1517 100644 --- a/libc/test/src/sched/param_and_scheduler_test.cpp +++ b/libc/test/src/sched/param_and_scheduler_test.cpp @@ -37,7 +37,7 @@ class SchedTest : public LIBC_NAMESPACE::testing::Test { public: void testSched(int policy, bool can_set) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int init_policy = LIBC_NAMESPACE::sched_getscheduler(0); ASSERT_GE(init_policy, 0); @@ -55,38 +55,40 @@ public: // Negative pid ASSERT_EQ(LIBC_NAMESPACE::sched_setscheduler(-1, policy, ¶m), -1); ASSERT_ERRNO_EQ(EINVAL); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(LIBC_NAMESPACE::sched_getscheduler(-1), -1); ASSERT_ERRNO_EQ(EINVAL); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // Invalid Policy ASSERT_EQ(LIBC_NAMESPACE::sched_setscheduler(0, policy | 128, ¶m), -1); ASSERT_ERRNO_EQ(EINVAL); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // Out of bounds priority param.sched_priority = min_priority - 1; ASSERT_EQ(LIBC_NAMESPACE::sched_setscheduler(0, policy, ¶m), -1); ASSERT_ERRNO_EQ(EINVAL); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; param.sched_priority = max_priority + 1; ASSERT_EQ(LIBC_NAMESPACE::sched_setscheduler(0, policy, ¶m), -1); // A bit hard to test as depending if we are root or not we can run into // different issues. - ASSERT_TRUE(libc_errno == EINVAL || libc_errno == EPERM); - libc_errno = 0; + ASSERT_TRUE(LIBC_NAMESPACE::libc_errno == EINVAL || + LIBC_NAMESPACE::libc_errno == EPERM); + LIBC_NAMESPACE::libc_errno = 0; // Some sched policies require permissions, so skip param.sched_priority = min_priority; // Success / missing permissions. ASSERT_EQ(LIBC_NAMESPACE::sched_setscheduler(0, policy, ¶m), can_set ? 0 : -1); - ASSERT_TRUE(can_set ? (libc_errno == 0) - : (libc_errno == EINVAL || libc_errno == EPERM)); - libc_errno = 0; + ASSERT_TRUE(can_set ? (LIBC_NAMESPACE::libc_errno == 0) + : (LIBC_NAMESPACE::libc_errno == EINVAL || + LIBC_NAMESPACE::libc_errno == EPERM)); + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(LIBC_NAMESPACE::sched_getscheduler(0), can_set ? policy : init_policy); @@ -96,12 +98,12 @@ public: param.sched_priority = -1; ASSERT_EQ(LIBC_NAMESPACE::sched_setparam(0, ¶m), -1); ASSERT_ERRNO_EQ(EINVAL); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; param.sched_priority = max_priority + 1; ASSERT_EQ(LIBC_NAMESPACE::sched_setparam(0, ¶m), -1); ASSERT_ERRNO_EQ(EINVAL); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; for (int priority = min_priority; priority <= max_priority; ++priority) { ASSERT_EQ(LIBC_NAMESPACE::sched_getparam(0, ¶m), 0); @@ -113,17 +115,18 @@ public: // Negative pid ASSERT_EQ(LIBC_NAMESPACE::sched_setparam(-1, ¶m), -1); ASSERT_ERRNO_EQ(EINVAL); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(LIBC_NAMESPACE::sched_getparam(-1, ¶m), -1); ASSERT_ERRNO_EQ(EINVAL); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // Success / missing permissions ASSERT_EQ(LIBC_NAMESPACE::sched_setparam(0, ¶m), can_set ? 0 : -1); - ASSERT_TRUE(can_set ? (libc_errno == 0) - : (libc_errno == EINVAL || libc_errno == EPERM)); - libc_errno = 0; + ASSERT_TRUE(can_set ? (LIBC_NAMESPACE::libc_errno == 0) + : (LIBC_NAMESPACE::libc_errno == EINVAL || + LIBC_NAMESPACE::libc_errno == EPERM)); + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(LIBC_NAMESPACE::sched_getparam(0, ¶m), 0); ASSERT_ERRNO_SUCCESS(); @@ -134,7 +137,7 @@ public: // Null test ASSERT_EQ(LIBC_NAMESPACE::sched_setscheduler(0, policy, nullptr), -1); ASSERT_ERRNO_EQ(EINVAL); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; } }; @@ -152,13 +155,13 @@ LIST_SCHED_TESTS(SCHED_BATCH, true) LIST_SCHED_TESTS(SCHED_IDLE, true) TEST(LlvmLibcSchedParamAndSchedulerTest, NullParamTest) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(LIBC_NAMESPACE::sched_setparam(0, nullptr), -1); ASSERT_ERRNO_EQ(EINVAL); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(LIBC_NAMESPACE::sched_getparam(0, nullptr), -1); ASSERT_ERRNO_EQ(EINVAL); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; } diff --git a/libc/test/src/sched/sched_rr_get_interval_test.cpp b/libc/test/src/sched/sched_rr_get_interval_test.cpp index 5e024f07ced1..c22a2c76d743 100644 --- a/libc/test/src/sched/sched_rr_get_interval_test.cpp +++ b/libc/test/src/sched/sched_rr_get_interval_test.cpp @@ -17,7 +17,7 @@ #include TEST(LlvmLibcSchedRRGetIntervalTest, SmokeTest) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; auto SetSched = [&](int policy) { int min_priority = LIBC_NAMESPACE::sched_get_priority_min(policy); ASSERT_GE(min_priority, 0); @@ -58,19 +58,19 @@ TEST(LlvmLibcSchedRRGetIntervalTest, SmokeTest) { // Null timespec ASSERT_EQ(LIBC_NAMESPACE::sched_rr_get_interval(0, nullptr), -1); ASSERT_ERRNO_EQ(EFAULT); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // Negative pid ASSERT_EQ(LIBC_NAMESPACE::sched_rr_get_interval(-1, &ts), -1); ASSERT_ERRNO_EQ(EINVAL); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; } // Negative tests don't have SCHED_RR set SetSched(SCHED_OTHER); ASSERT_EQ(LIBC_NAMESPACE::sched_rr_get_interval(0, &ts), 0); ASSERT_ERRNO_SUCCESS(); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // TODO: Missing unkown pid -> ESRCH. This is read only so safe to try a few // unlikely values. diff --git a/libc/test/src/sched/yield_test.cpp b/libc/test/src/sched/yield_test.cpp index 5e4e07bc199b..f1627a71fa9a 100644 --- a/libc/test/src/sched/yield_test.cpp +++ b/libc/test/src/sched/yield_test.cpp @@ -11,7 +11,7 @@ #include "test/UnitTest/Test.h" TEST(LlvmLibcSchedYieldTest, SmokeTest) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // sched_yield() always succeeds, just do a basic test that errno/ret are // properly 0. ASSERT_EQ(LIBC_NAMESPACE::sched_yield(), 0); diff --git a/libc/test/src/signal/sigaltstack_test.cpp b/libc/test/src/signal/sigaltstack_test.cpp index 5e1a3a4e2062..12bf2bf5e372 100644 --- a/libc/test/src/signal/sigaltstack_test.cpp +++ b/libc/test/src/signal/sigaltstack_test.cpp @@ -47,7 +47,7 @@ static void handler(int) { TEST(LlvmLibcSignalTest, SigaltstackRunOnAltStack) { struct sigaction action; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_THAT(LIBC_NAMESPACE::sigaction(SIGUSR1, nullptr, &action), Succeeds(0)); action.sa_handler = handler; diff --git a/libc/test/src/signal/signal_test.cpp b/libc/test/src/signal/signal_test.cpp index 78f8bfbd719b..70e95a8c159a 100644 --- a/libc/test/src/signal/signal_test.cpp +++ b/libc/test/src/signal/signal_test.cpp @@ -19,7 +19,7 @@ using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; TEST(LlvmLibcSignal, Invalid) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; LIBC_NAMESPACE::sighandler_t valid = +[](int) {}; EXPECT_THAT((void *)LIBC_NAMESPACE::signal(0, valid), Fails(EINVAL, (void *)SIG_ERR)); diff --git a/libc/test/src/signal/sigprocmask_test.cpp b/libc/test/src/signal/sigprocmask_test.cpp index 3e7e3a5c62db..12403f68b593 100644 --- a/libc/test/src/signal/sigprocmask_test.cpp +++ b/libc/test/src/signal/sigprocmask_test.cpp @@ -33,7 +33,7 @@ using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; // This tests for invalid input. TEST_F(LlvmLibcSignalTest, SigprocmaskInvalid) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; sigset_t valid; // 17 and -4 are out of the range for sigprocmask's how paramater. diff --git a/libc/test/src/stdio/fgetc_test.cpp b/libc/test/src/stdio/fgetc_test.cpp index 6e6c0ed9b26b..989bb312afad 100644 --- a/libc/test/src/stdio/fgetc_test.cpp +++ b/libc/test/src/stdio/fgetc_test.cpp @@ -33,7 +33,7 @@ public: // This is an error and not a real EOF. ASSERT_EQ(LIBC_NAMESPACE::feof(file), 0); ASSERT_NE(LIBC_NAMESPACE::ferror(file), 0); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(0, LIBC_NAMESPACE::fclose(file)); diff --git a/libc/test/src/stdio/fgetc_unlocked_test.cpp b/libc/test/src/stdio/fgetc_unlocked_test.cpp index 0d704ecee750..48d7a043cad7 100644 --- a/libc/test/src/stdio/fgetc_unlocked_test.cpp +++ b/libc/test/src/stdio/fgetc_unlocked_test.cpp @@ -36,7 +36,7 @@ public: // This is an error and not a real EOF. ASSERT_EQ(LIBC_NAMESPACE::feof(file), 0); ASSERT_NE(LIBC_NAMESPACE::ferror(file), 0); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(0, LIBC_NAMESPACE::fclose(file)); diff --git a/libc/test/src/stdio/fgets_test.cpp b/libc/test/src/stdio/fgets_test.cpp index aab8bae3d97e..d005a71710d2 100644 --- a/libc/test/src/stdio/fgets_test.cpp +++ b/libc/test/src/stdio/fgets_test.cpp @@ -36,7 +36,7 @@ TEST(LlvmLibcFgetsTest, WriteAndReadCharacters) { // This is an error and not a real EOF. ASSERT_EQ(LIBC_NAMESPACE::feof(file), 0); ASSERT_NE(LIBC_NAMESPACE::ferror(file), 0); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(0, LIBC_NAMESPACE::fclose(file)); diff --git a/libc/test/src/stdio/fileop_test.cpp b/libc/test/src/stdio/fileop_test.cpp index d620aa076ef0..f5dbc4981839 100644 --- a/libc/test/src/stdio/fileop_test.cpp +++ b/libc/test/src/stdio/fileop_test.cpp @@ -39,7 +39,7 @@ TEST(LlvmLibcFILETest, SimpleFileOperations) { ASSERT_THAT(LIBC_NAMESPACE::fread(read_data, 1, sizeof(CONTENT), file), returns(EQ(size_t(0))).with_errno(NE(0))); ASSERT_NE(LIBC_NAMESPACE::ferror(file), 0); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; LIBC_NAMESPACE::clearerr(file); ASSERT_EQ(LIBC_NAMESPACE::ferror(file), 0); @@ -70,7 +70,7 @@ TEST(LlvmLibcFILETest, SimpleFileOperations) { ASSERT_THAT(LIBC_NAMESPACE::fwrite(CONTENT, 1, sizeof(CONTENT), file), returns(EQ(size_t(0))).with_errno(NE(0))); ASSERT_NE(LIBC_NAMESPACE::ferror(file), 0); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; LIBC_NAMESPACE::clearerr(file); @@ -78,15 +78,15 @@ TEST(LlvmLibcFILETest, SimpleFileOperations) { ASSERT_THAT(LIBC_NAMESPACE::fputs(CONTENT, file), returns(EQ(EOF)).with_errno(NE(0))); ASSERT_NE(LIBC_NAMESPACE::ferror(file), 0); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; LIBC_NAMESPACE::clearerr(file); ASSERT_EQ(LIBC_NAMESPACE::ferror(file), 0); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_THAT(LIBC_NAMESPACE::fwrite("nothing", 1, 1, file), returns(EQ(0)).with_errno(NE(0))); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(LIBC_NAMESPACE::fclose(file), 0); @@ -101,10 +101,10 @@ TEST(LlvmLibcFILETest, SimpleFileOperations) { ASSERT_EQ(LIBC_NAMESPACE::ferror(file), 0); // This is not a readable file. - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_THAT(LIBC_NAMESPACE::fread(data, 1, 1, file), returns(EQ(0)).with_errno(NE(0))); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(0, LIBC_NAMESPACE::fclose(file)); @@ -119,15 +119,15 @@ TEST(LlvmLibcFILETest, SimpleFileOperations) { // Check that the other functions correctly set libc_errno. - // libc_errno = 0; + // LIBC_NAMESPACE::libc_errno = 0; // ASSERT_NE(LIBC_NAMESPACE::fseek(file, 0, SEEK_SET), 0); // ASSERT_ERRNO_FAILURE(); - // libc_errno = 0; + // LIBC_NAMESPACE::libc_errno = 0; // ASSERT_NE(LIBC_NAMESPACE::fclose(file), 0); // ASSERT_ERRNO_FAILURE(); - // libc_errno = 0; + // LIBC_NAMESPACE::libc_errno = 0; // ASSERT_EQ(LIBC_NAMESPACE::fopen("INVALID FILE NAME", "r"), // static_cast(nullptr)); // ASSERT_ERRNO_FAILURE(); @@ -163,7 +163,7 @@ TEST(LlvmLibcFILETest, FOpenFWriteSizeGreaterThanOne) { constexpr size_t WRITE_NMEMB = sizeof(WRITE_DATA) / sizeof(MyStruct); constexpr char FILENAME[] = "testdata/fread_fwrite.test"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; FILE *file = LIBC_NAMESPACE::fopen(FILENAME, "w"); ASSERT_FALSE(file == nullptr); ASSERT_EQ(size_t(0), LIBC_NAMESPACE::fwrite(WRITE_DATA, 0, 1, file)); diff --git a/libc/test/src/stdio/fopencookie_test.cpp b/libc/test/src/stdio/fopencookie_test.cpp index 2edfc7e210d7..6c86b8759801 100644 --- a/libc/test/src/stdio/fopencookie_test.cpp +++ b/libc/test/src/stdio/fopencookie_test.cpp @@ -67,7 +67,7 @@ int seek_ss(void *cookie, off64_t *offset, int whence) { } else if (whence == SEEK_END) { new_offset = *offset + ss->endpos; } else { - libc_errno = EINVAL; + LIBC_NAMESPACE::libc_errno = EINVAL; return -1; } if (new_offset < 0 || size_t(new_offset) > ss->bufsize) @@ -115,7 +115,7 @@ TEST(LlvmLibcFOpenCookie, ReadOnlyCookieTest) { ASSERT_EQ(size_t(0), LIBC_NAMESPACE::fwrite(CONTENT, 1, sizeof(CONTENT), f)); ASSERT_NE(LIBC_NAMESPACE::ferror(f), 0); ASSERT_ERRNO_FAILURE(); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; LIBC_NAMESPACE::clearerr(f); ASSERT_EQ(LIBC_NAMESPACE::ferror(f), 0); @@ -149,7 +149,7 @@ TEST(LlvmLibcFOpenCookie, WriteOnlyCookieTest) { LIBC_NAMESPACE::fread(read_data, 1, sizeof(WRITE_DATA), f)); ASSERT_NE(LIBC_NAMESPACE::ferror(f), 0); ASSERT_ERRNO_EQ(EBADF); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; LIBC_NAMESPACE::clearerr(f); ASSERT_EQ(LIBC_NAMESPACE::ferror(f), 0); @@ -178,7 +178,7 @@ TEST(LlvmLibcFOpenCookie, AppendOnlyCookieTest) { ASSERT_EQ(LIBC_NAMESPACE::fread(read_data, 1, READ_SIZE, f), size_t(0)); ASSERT_NE(LIBC_NAMESPACE::ferror(f), 0); ASSERT_ERRNO_FAILURE(); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; LIBC_NAMESPACE::clearerr(f); ASSERT_EQ(LIBC_NAMESPACE::ferror(f), 0); diff --git a/libc/test/src/stdio/remove_test.cpp b/libc/test/src/stdio/remove_test.cpp index 539c23d0fb90..72875600903a 100644 --- a/libc/test/src/stdio/remove_test.cpp +++ b/libc/test/src/stdio/remove_test.cpp @@ -20,7 +20,7 @@ TEST(LlvmLibcRemoveTest, CreateAndRemoveFile) { // The test strategy is to create a file and remove it, and also verify that // it was removed. - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; @@ -39,7 +39,7 @@ TEST(LlvmLibcRemoveTest, CreateAndRemoveFile) { TEST(LlvmLibcRemoveTest, CreateAndRemoveDir) { // The test strategy is to create a dir and remove it, and also verify that // it was removed. - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; constexpr const char *FILENAME = "remove.test.dir"; diff --git a/libc/test/src/stdio/setvbuf_test.cpp b/libc/test/src/stdio/setvbuf_test.cpp index 725694bb8ae1..d42ebac12ead 100644 --- a/libc/test/src/stdio/setvbuf_test.cpp +++ b/libc/test/src/stdio/setvbuf_test.cpp @@ -102,6 +102,6 @@ TEST(LlvmLibcSetbufTest, InvalidBufferMode) { 0); ASSERT_ERRNO_EQ(EINVAL); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(0, LIBC_NAMESPACE::fclose(f)); } diff --git a/libc/test/src/stdio/unlocked_fileop_test.cpp b/libc/test/src/stdio/unlocked_fileop_test.cpp index cf20701ca0e3..09697a6452f4 100644 --- a/libc/test/src/stdio/unlocked_fileop_test.cpp +++ b/libc/test/src/stdio/unlocked_fileop_test.cpp @@ -37,7 +37,7 @@ TEST(LlvmLibcFILETest, UnlockedReadAndWrite) { LIBC_NAMESPACE::fread_unlocked(data, 1, sizeof(READ_SIZE), f)); ASSERT_NE(LIBC_NAMESPACE::ferror_unlocked(f), 0); ASSERT_ERRNO_FAILURE(); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; LIBC_NAMESPACE::clearerr_unlocked(f); ASSERT_EQ(LIBC_NAMESPACE::ferror_unlocked(f), 0); @@ -58,7 +58,7 @@ TEST(LlvmLibcFILETest, UnlockedReadAndWrite) { LIBC_NAMESPACE::fwrite_unlocked(CONTENT, 1, sizeof(CONTENT), f)); ASSERT_NE(LIBC_NAMESPACE::ferror_unlocked(f), 0); ASSERT_ERRNO_FAILURE(); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; LIBC_NAMESPACE::clearerr_unlocked(f); ASSERT_EQ(LIBC_NAMESPACE::ferror_unlocked(f), 0); diff --git a/libc/test/src/stdlib/StrtolTest.h b/libc/test/src/stdlib/StrtolTest.h index 50ed4cca3950..8a67848e4c33 100644 --- a/libc/test/src/stdlib/StrtolTest.h +++ b/libc/test/src/stdlib/StrtolTest.h @@ -35,7 +35,7 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { void InvalidBase(FunctionT func) { const char *ten = "10"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(ten, nullptr, -1), ReturnT(0)); ASSERT_ERRNO_EQ(EINVAL); } @@ -45,23 +45,23 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { // TODO: Look into collapsing these repeated segments. const char *ten = "10"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(ten, &str_end, 10), ReturnT(10)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - ten, ptrdiff_t(2)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(ten, nullptr, 10), ReturnT(10)); ASSERT_ERRNO_SUCCESS(); const char *hundred = "100"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(hundred, &str_end, 10), ReturnT(100)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - hundred, ptrdiff_t(3)); const char *big_number = "1234567890"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(big_number, &str_end, 10), ReturnT(1234567890)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - big_number, ptrdiff_t(10)); @@ -69,7 +69,7 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { // This number is larger than 2^32, meaning that if long is only 32 bits // wide, strtol will return LONG_MAX. const char *bigger_number = "12345678900"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; if constexpr (sizeof(ReturnT) < 8) { ASSERT_EQ(func(bigger_number, &str_end, 10), T_MAX); ASSERT_ERRNO_EQ(ERANGE); @@ -80,14 +80,14 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { EXPECT_EQ(str_end - bigger_number, ptrdiff_t(11)); const char *too_big_number = "123456789012345678901"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(too_big_number, &str_end, 10), T_MAX); ASSERT_ERRNO_EQ(ERANGE); EXPECT_EQ(str_end - too_big_number, ptrdiff_t(21)); const char *long_number_range_test = "10000000000000000000000000000000000000000000000000"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(long_number_range_test, &str_end, 10), T_MAX); ASSERT_ERRNO_EQ(ERANGE); EXPECT_EQ(str_end - long_number_range_test, ptrdiff_t(50)); @@ -95,19 +95,19 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { // For most negative numbers, the unsigned functions treat it the same as // casting a negative variable to an unsigned type. const char *negative = "-100"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(negative, &str_end, 10), ReturnT(-100)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - negative, ptrdiff_t(4)); const char *big_negative_number = "-1234567890"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(big_negative_number, &str_end, 10), ReturnT(-1234567890)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - big_negative_number, ptrdiff_t(11)); const char *too_big_negative_number = "-123456789012345678901"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // If the number is signed, it should return the smallest negative number // for the current type, but if it's unsigned it should max out and return // the largest positive number for the current type. From the standard: @@ -125,73 +125,73 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { char *str_end = nullptr; const char *spaces_before = " 10"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(spaces_before, &str_end, 10), ReturnT(10)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - spaces_before, ptrdiff_t(7)); const char *spaces_after = "10 "; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(spaces_after, &str_end, 10), ReturnT(10)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - spaces_after, ptrdiff_t(2)); const char *word_before = "word10"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(word_before, &str_end, 10), ReturnT(0)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - word_before, ptrdiff_t(0)); const char *word_after = "10word"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(word_after, &str_end, 10), ReturnT(10)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - word_after, ptrdiff_t(2)); const char *two_numbers = "10 999"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(two_numbers, &str_end, 10), ReturnT(10)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - two_numbers, ptrdiff_t(2)); const char *two_signs = "--10 999"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(two_signs, &str_end, 10), ReturnT(0)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - two_signs, ptrdiff_t(0)); const char *sign_before = "+2=4"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(sign_before, &str_end, 10), ReturnT(2)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - sign_before, ptrdiff_t(2)); const char *sign_after = "2+2=4"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(sign_after, &str_end, 10), ReturnT(2)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - sign_after, ptrdiff_t(1)); const char *tab_before = "\t10"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(tab_before, &str_end, 10), ReturnT(10)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - tab_before, ptrdiff_t(3)); const char *all_together = "\t -12345and+67890"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(all_together, &str_end, 10), ReturnT(-12345)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - all_together, ptrdiff_t(9)); const char *just_spaces = " "; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(just_spaces, &str_end, 10), ReturnT(0)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - just_spaces, ptrdiff_t(0)); const char *just_space_and_sign = " +"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(just_space_and_sign, &str_end, 10), ReturnT(0)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - just_space_and_sign, ptrdiff_t(0)); @@ -209,12 +209,12 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { for (int first_digit = 0; first_digit <= 36; ++first_digit) { small_string[0] = int_to_b36_char(first_digit); if (first_digit < base) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(small_string, nullptr, base), static_cast(first_digit)); ASSERT_ERRNO_SUCCESS(); } else { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(small_string, nullptr, base), ReturnT(0)); ASSERT_ERRNO_SUCCESS(); } @@ -227,18 +227,18 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { for (int second_digit = 0; second_digit <= 36; ++second_digit) { small_string[1] = int_to_b36_char(second_digit); if (first_digit < base && second_digit < base) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ( func(small_string, nullptr, base), static_cast(second_digit + (first_digit * base))); ASSERT_ERRNO_SUCCESS(); } else if (first_digit < base) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(small_string, nullptr, base), static_cast(first_digit)); ASSERT_ERRNO_SUCCESS(); } else { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(small_string, nullptr, base), ReturnT(0)); ASSERT_ERRNO_SUCCESS(); } @@ -256,14 +256,14 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { if (first_digit < base && second_digit < base && third_digit < base) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(small_string, nullptr, base), static_cast(third_digit + (second_digit * base) + (first_digit * base * base))); ASSERT_ERRNO_SUCCESS(); } else if (first_digit < base && second_digit < base) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ( func(small_string, nullptr, base), static_cast(second_digit + (first_digit * base))); @@ -273,23 +273,23 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { // The number is treated as a one digit hexadecimal. if (base == 16 && first_digit == 0 && second_digit == 33) { if (third_digit < base) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(small_string, nullptr, base), static_cast(third_digit)); ASSERT_ERRNO_SUCCESS(); } else { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(small_string, nullptr, base), ReturnT(0)); ASSERT_ERRNO_SUCCESS(); } } else { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(small_string, nullptr, base), static_cast(first_digit)); ASSERT_ERRNO_SUCCESS(); } } else { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(small_string, nullptr, base), ReturnT(0)); ASSERT_ERRNO_SUCCESS(); } @@ -303,19 +303,19 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { char *str_end = nullptr; const char *no_prefix = "123abc"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(no_prefix, &str_end, 16), ReturnT(0x123abc)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - no_prefix, ptrdiff_t(6)); const char *yes_prefix = "0x456def"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(yes_prefix, &str_end, 16), ReturnT(0x456def)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - yes_prefix, ptrdiff_t(8)); const char *letter_after_prefix = "0xabc123"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(letter_after_prefix, &str_end, 16), ReturnT(0xabc123)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - letter_after_prefix, ptrdiff_t(8)); @@ -326,7 +326,7 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { // Max size for unsigned 32 bit numbers const char *max_32_bit_value = "0xFFFFFFFF"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(max_32_bit_value, &str_end, 0), ((is_signed_v && sizeof(ReturnT) == 4) ? T_MAX @@ -335,7 +335,7 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { EXPECT_EQ(str_end - max_32_bit_value, ptrdiff_t(10)); const char *negative_max_32_bit_value = "-0xFFFFFFFF"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(negative_max_32_bit_value, &str_end, 0), ((is_signed_v && sizeof(ReturnT) == 4) ? T_MIN @@ -346,13 +346,13 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { // Max size for signed 32 bit numbers const char *max_31_bit_value = "0x7FFFFFFF"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(max_31_bit_value, &str_end, 0), ReturnT(0x7FFFFFFF)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - max_31_bit_value, ptrdiff_t(10)); const char *negative_max_31_bit_value = "-0x7FFFFFFF"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(negative_max_31_bit_value, &str_end, 0), -ReturnT(0x7FFFFFFF)); ASSERT_ERRNO_SUCCESS(); @@ -361,7 +361,7 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { // Max size for unsigned 64 bit numbers const char *max_64_bit_value = "0xFFFFFFFFFFFFFFFF"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(max_64_bit_value, &str_end, 0), (is_signed_v || sizeof(ReturnT) < 8 ? T_MAX @@ -372,7 +372,7 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { // See the end of CleanBase10Decode for an explanation of how this large // negative number can end up as T_MAX. const char *negative_max_64_bit_value = "-0xFFFFFFFFFFFFFFFF"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ( func(negative_max_64_bit_value, &str_end, 0), (is_signed_v @@ -384,14 +384,14 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { // Max size for signed 64 bit numbers const char *max_63_bit_value = "0x7FFFFFFFFFFFFFFF"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(max_63_bit_value, &str_end, 0), (sizeof(ReturnT) < 8 ? T_MAX : ReturnT(0x7FFFFFFFFFFFFFFF))); ASSERT_ERRNO_EQ(sizeof(ReturnT) < 8 ? ERANGE : 0); EXPECT_EQ(str_end - max_63_bit_value, ptrdiff_t(18)); const char *negative_max_63_bit_value = "-0x7FFFFFFFFFFFFFFF"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(negative_max_63_bit_value, &str_end, 0), (sizeof(ReturnT) >= 8 ? -ReturnT(0x7FFFFFFFFFFFFFFF) : (is_signed_v ? T_MIN : T_MAX))); @@ -403,23 +403,23 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { char *str_end = nullptr; const char *just_prefix = "0x"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(just_prefix, &str_end, 16), ReturnT(0)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - just_prefix, ptrdiff_t(1)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(just_prefix, &str_end, 0), ReturnT(0)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - just_prefix, ptrdiff_t(1)); const char *prefix_with_x_after = "0xx"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(prefix_with_x_after, &str_end, 16), ReturnT(0)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - prefix_with_x_after, ptrdiff_t(1)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(prefix_with_x_after, &str_end, 0), ReturnT(0)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - prefix_with_x_after, ptrdiff_t(1)); @@ -429,43 +429,43 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { char *str_end = nullptr; const char *base_ten = "12345"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(base_ten, &str_end, 0), ReturnT(12345)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - base_ten, ptrdiff_t(5)); const char *base_sixteen_no_prefix = "123abc"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(base_sixteen_no_prefix, &str_end, 0), ReturnT(123)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - base_sixteen_no_prefix, ptrdiff_t(3)); const char *base_sixteen_with_prefix = "0x456def"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(base_sixteen_with_prefix, &str_end, 0), ReturnT(0x456def)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - base_sixteen_with_prefix, ptrdiff_t(8)); const char *base_eight_with_prefix = "012345"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(base_eight_with_prefix, &str_end, 0), ReturnT(012345)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - base_eight_with_prefix, ptrdiff_t(6)); const char *just_zero = "0"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(just_zero, &str_end, 0), ReturnT(0)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - just_zero, ptrdiff_t(1)); const char *just_zero_x = "0x"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(just_zero_x, &str_end, 0), ReturnT(0)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - just_zero_x, ptrdiff_t(1)); const char *just_zero_eight = "08"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(just_zero_eight, &str_end, 0), ReturnT(0)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - just_zero_eight, ptrdiff_t(1)); diff --git a/libc/test/src/stdlib/atof_test.cpp b/libc/test/src/stdlib/atof_test.cpp index 858ab326e38d..1e4259b792d7 100644 --- a/libc/test/src/stdlib/atof_test.cpp +++ b/libc/test/src/stdlib/atof_test.cpp @@ -23,13 +23,13 @@ TEST(LlvmLibcAToFTest, SimpleTest) { LIBC_NAMESPACE::fputil::FPBits expected_fp = LIBC_NAMESPACE::fputil::FPBits(uint64_t(0x405ec00000000000)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_THAT(LIBC_NAMESPACE::atof("123"), Succeeds(expected_fp.get_val())); } TEST(LlvmLibcAToFTest, FailedParsingTest) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // atof does not flag errors. EXPECT_THAT(LIBC_NAMESPACE::atof("???"), Succeeds(0.0)); } diff --git a/libc/test/src/stdlib/strtod_test.cpp b/libc/test/src/stdlib/strtod_test.cpp index e68c8610b407..92d14640e653 100644 --- a/libc/test/src/stdlib/strtod_test.cpp +++ b/libc/test/src/stdlib/strtod_test.cpp @@ -46,7 +46,7 @@ public: LIBC_NAMESPACE::fputil::FPBits expected_fp = LIBC_NAMESPACE::fputil::FPBits(expectedRawData); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; double result = LIBC_NAMESPACE::strtod(inputString, &str_end); if (expectedErrno == 0) EXPECT_THAT(result, Succeeds(expected_fp.get_val())); diff --git a/libc/test/src/stdlib/strtof_test.cpp b/libc/test/src/stdlib/strtof_test.cpp index b43c32f90261..d7991745b69e 100644 --- a/libc/test/src/stdlib/strtof_test.cpp +++ b/libc/test/src/stdlib/strtof_test.cpp @@ -43,7 +43,7 @@ public: LIBC_NAMESPACE::fputil::FPBits expected_fp = LIBC_NAMESPACE::fputil::FPBits(expectedRawData); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; float result = LIBC_NAMESPACE::strtof(inputString, &str_end); EXPECT_EQ(str_end - inputString, expectedStrLen); diff --git a/libc/test/src/stdlib/strtoint32_test.cpp b/libc/test/src/stdlib/strtoint32_test.cpp index 4ca20f3333f5..a7c9141d9f79 100644 --- a/libc/test/src/stdlib/strtoint32_test.cpp +++ b/libc/test/src/stdlib/strtoint32_test.cpp @@ -20,7 +20,7 @@ int32_t strtoint32(const char *__restrict str, char **__restrict str_end, int base) { auto result = internal::strtointeger(str, base); if (result.has_error()) - libc_errno = result.error; + LIBC_NAMESPACE::libc_errno = result.error; if (str_end != nullptr) *str_end = const_cast(str + result.parsed_len); @@ -32,7 +32,7 @@ uint32_t strtouint32(const char *__restrict str, char **__restrict str_end, int base) { auto result = internal::strtointeger(str, base); if (result.has_error()) - libc_errno = result.error; + LIBC_NAMESPACE::libc_errno = result.error; if (str_end != nullptr) *str_end = const_cast(str + result.parsed_len); diff --git a/libc/test/src/stdlib/strtoint64_test.cpp b/libc/test/src/stdlib/strtoint64_test.cpp index f8d807b146f2..350b5aca4c85 100644 --- a/libc/test/src/stdlib/strtoint64_test.cpp +++ b/libc/test/src/stdlib/strtoint64_test.cpp @@ -20,7 +20,7 @@ int64_t strtoint64(const char *__restrict str, char **__restrict str_end, int base) { auto result = internal::strtointeger(str, base); if (result.has_error()) - libc_errno = result.error; + LIBC_NAMESPACE::libc_errno = result.error; if (str_end != nullptr) *str_end = const_cast(str + result.parsed_len); @@ -32,7 +32,7 @@ uint64_t strtouint64(const char *__restrict str, char **__restrict str_end, int base) { auto result = internal::strtointeger(str, base); if (result.has_error()) - libc_errno = result.error; + LIBC_NAMESPACE::libc_errno = result.error; if (str_end != nullptr) *str_end = const_cast(str + result.parsed_len); diff --git a/libc/test/src/stdlib/strtold_test.cpp b/libc/test/src/stdlib/strtold_test.cpp index cbe0a47b9b71..052558979556 100644 --- a/libc/test/src/stdlib/strtold_test.cpp +++ b/libc/test/src/stdlib/strtold_test.cpp @@ -77,7 +77,7 @@ public: LIBC_NAMESPACE::fputil::FPBits(expectedRawData); const int expected_errno = expectedErrno; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; long double result = LIBC_NAMESPACE::strtold(inputString, &str_end); LIBC_NAMESPACE::fputil::FPBits actual_fp = diff --git a/libc/test/src/string/strdup_test.cpp b/libc/test/src/string/strdup_test.cpp index caf8c2e61c0e..fd3cceaaa17c 100644 --- a/libc/test/src/string/strdup_test.cpp +++ b/libc/test/src/string/strdup_test.cpp @@ -15,7 +15,7 @@ TEST(LlvmLibcStrDupTest, EmptyString) { const char *empty = ""; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; char *result = LIBC_NAMESPACE::strdup(empty); ASSERT_ERRNO_SUCCESS(); @@ -28,7 +28,7 @@ TEST(LlvmLibcStrDupTest, EmptyString) { TEST(LlvmLibcStrDupTest, AnyString) { const char *abc = "abc"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; char *result = LIBC_NAMESPACE::strdup(abc); ASSERT_ERRNO_SUCCESS(); @@ -39,7 +39,7 @@ TEST(LlvmLibcStrDupTest, AnyString) { } TEST(LlvmLibcStrDupTest, NullPtr) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; char *result = LIBC_NAMESPACE::strdup(nullptr); ASSERT_ERRNO_SUCCESS(); diff --git a/libc/test/src/sys/mman/linux/madvise_test.cpp b/libc/test/src/sys/mman/linux/madvise_test.cpp index e45cf19f8913..6768d111c0d9 100644 --- a/libc/test/src/sys/mman/linux/madvise_test.cpp +++ b/libc/test/src/sys/mman/linux/madvise_test.cpp @@ -20,7 +20,7 @@ using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; TEST(LlvmLibcMadviseTest, NoError) { size_t alloc_size = 128; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; void *addr = LIBC_NAMESPACE::mmap(nullptr, alloc_size, PROT_READ, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); ASSERT_ERRNO_SUCCESS(); @@ -38,7 +38,7 @@ TEST(LlvmLibcMadviseTest, NoError) { } TEST(LlvmLibcMadviseTest, Error_BadPtr) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_THAT(LIBC_NAMESPACE::madvise(nullptr, 8, MADV_SEQUENTIAL), Fails(ENOMEM)); } diff --git a/libc/test/src/sys/mman/linux/mincore_test.cpp b/libc/test/src/sys/mman/linux/mincore_test.cpp index 2814694849fc..8e0c29c2ac17 100644 --- a/libc/test/src/sys/mman/linux/mincore_test.cpp +++ b/libc/test/src/sys/mman/linux/mincore_test.cpp @@ -27,7 +27,7 @@ using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; TEST(LlvmLibcMincoreTest, UnMappedMemory) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; unsigned char vec; int res = LIBC_NAMESPACE::mincore(nullptr, 1, &vec); EXPECT_THAT(res, Fails(ENOMEM, -1)); @@ -39,7 +39,7 @@ TEST(LlvmLibcMincoreTest, UnalignedAddr) { MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); EXPECT_NE(addr, MAP_FAILED); EXPECT_EQ(reinterpret_cast(addr) % page_size, 0ul); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int res = LIBC_NAMESPACE::mincore(static_cast(addr) + 1, 1, nullptr); EXPECT_THAT(res, Fails(EINVAL, -1)); EXPECT_THAT(LIBC_NAMESPACE::munmap(addr, page_size), Succeeds()); @@ -51,7 +51,7 @@ TEST(LlvmLibcMincoreTest, InvalidVec) { MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); EXPECT_NE(addr, MAP_FAILED); EXPECT_EQ(reinterpret_cast(addr) % page_size, 0ul); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int res = LIBC_NAMESPACE::mincore(addr, 1, nullptr); EXPECT_THAT(res, Fails(EFAULT, -1)); } @@ -63,7 +63,7 @@ TEST(LlvmLibcMincoreTest, NoError) { EXPECT_NE(addr, MAP_FAILED); EXPECT_EQ(reinterpret_cast(addr) % page_size, 0ul); unsigned char vec; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int res = LIBC_NAMESPACE::mincore(addr, 1, &vec); EXPECT_THAT(res, Succeeds()); EXPECT_THAT(LIBC_NAMESPACE::munmap(addr, page_size), Succeeds()); @@ -76,7 +76,7 @@ TEST(LlvmLibcMincoreTest, NegativeLength) { EXPECT_NE(addr, MAP_FAILED); EXPECT_EQ(reinterpret_cast(addr) % page_size, 0ul); unsigned char vec; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int res = LIBC_NAMESPACE::mincore(addr, -1, &vec); EXPECT_THAT(res, Fails(ENOMEM, -1)); EXPECT_THAT(LIBC_NAMESPACE::munmap(addr, page_size), Succeeds()); @@ -102,11 +102,11 @@ TEST(LlvmLibcMincoreTest, PageOut) { // page out the memory { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_THAT(LIBC_NAMESPACE::madvise(addr, page_size, MADV_DONTNEED), Succeeds()); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int res = LIBC_NAMESPACE::mincore(addr, page_size, &vec); EXPECT_EQ(vec & 1u, 0u); EXPECT_THAT(res, Succeeds()); diff --git a/libc/test/src/sys/mman/linux/mlock_test.cpp b/libc/test/src/sys/mman/linux/mlock_test.cpp index f1d1af1e7692..804038a68a7e 100644 --- a/libc/test/src/sys/mman/linux/mlock_test.cpp +++ b/libc/test/src/sys/mman/linux/mlock_test.cpp @@ -120,7 +120,7 @@ TEST(LlvmLibcMlockTest, MLock2) { TEST(LlvmLibcMlockTest, InvalidFlag) { size_t alloc_size = 128; // page size - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; void *addr = LIBC_NAMESPACE::mmap(nullptr, alloc_size, PROT_READ, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); ASSERT_ERRNO_SUCCESS(); @@ -151,8 +151,9 @@ TEST(LlvmLibcMlockTest, MLockAll) { Succeeds()); auto retval = LIBC_NAMESPACE::mlockall(MCL_CURRENT); if (retval == -1) { - EXPECT_TRUE(libc_errno == ENOMEM || libc_errno == EPERM); - libc_errno = 0; + EXPECT_TRUE(LIBC_NAMESPACE::libc_errno == ENOMEM || + LIBC_NAMESPACE::libc_errno == EPERM); + LIBC_NAMESPACE::libc_errno = 0; return; } unsigned char vec; @@ -164,8 +165,9 @@ TEST(LlvmLibcMlockTest, MLockAll) { { auto retval = LIBC_NAMESPACE::mlockall(MCL_FUTURE); if (retval == -1) { - EXPECT_TRUE(libc_errno == ENOMEM || libc_errno == EPERM); - libc_errno = 0; + EXPECT_TRUE(LIBC_NAMESPACE::libc_errno == ENOMEM || + LIBC_NAMESPACE::libc_errno == EPERM); + LIBC_NAMESPACE::libc_errno = 0; return; } PageHolder holder; @@ -180,8 +182,9 @@ TEST(LlvmLibcMlockTest, MLockAll) { { auto retval = LIBC_NAMESPACE::mlockall(MCL_FUTURE | MCL_ONFAULT); if (retval == -1) { - EXPECT_TRUE(libc_errno == ENOMEM || libc_errno == EPERM); - libc_errno = 0; + EXPECT_TRUE(LIBC_NAMESPACE::libc_errno == ENOMEM || + LIBC_NAMESPACE::libc_errno == EPERM); + LIBC_NAMESPACE::libc_errno = 0; return; } PageHolder holder; diff --git a/libc/test/src/sys/mman/linux/mmap_test.cpp b/libc/test/src/sys/mman/linux/mmap_test.cpp index b996f26db860..dcbc75808f13 100644 --- a/libc/test/src/sys/mman/linux/mmap_test.cpp +++ b/libc/test/src/sys/mman/linux/mmap_test.cpp @@ -19,7 +19,7 @@ using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; TEST(LlvmLibcMMapTest, NoError) { size_t alloc_size = 128; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; void *addr = LIBC_NAMESPACE::mmap(nullptr, alloc_size, PROT_READ, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); ASSERT_ERRNO_SUCCESS(); @@ -34,7 +34,7 @@ TEST(LlvmLibcMMapTest, NoError) { } TEST(LlvmLibcMMapTest, Error_InvalidSize) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; void *addr = LIBC_NAMESPACE::mmap(nullptr, 0, PROT_READ, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); EXPECT_THAT(addr, Fails(EINVAL, MAP_FAILED)); diff --git a/libc/test/src/sys/mman/linux/mprotect_test.cpp b/libc/test/src/sys/mman/linux/mprotect_test.cpp index 96f625984101..46e449e54779 100644 --- a/libc/test/src/sys/mman/linux/mprotect_test.cpp +++ b/libc/test/src/sys/mman/linux/mprotect_test.cpp @@ -21,7 +21,7 @@ using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; TEST(LlvmLibcMProtectTest, NoError) { size_t alloc_size = 128; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; void *addr = LIBC_NAMESPACE::mmap(nullptr, alloc_size, PROT_READ, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); ASSERT_ERRNO_SUCCESS(); diff --git a/libc/test/src/sys/mman/linux/posix_madvise_test.cpp b/libc/test/src/sys/mman/linux/posix_madvise_test.cpp index d20db69042b7..ee6489c5ed2f 100644 --- a/libc/test/src/sys/mman/linux/posix_madvise_test.cpp +++ b/libc/test/src/sys/mman/linux/posix_madvise_test.cpp @@ -20,7 +20,7 @@ using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; TEST(LlvmLibcPosixMadviseTest, NoError) { size_t alloc_size = 128; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; void *addr = LIBC_NAMESPACE::mmap(nullptr, alloc_size, PROT_READ, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); ASSERT_ERRNO_SUCCESS(); @@ -38,7 +38,7 @@ TEST(LlvmLibcPosixMadviseTest, NoError) { } TEST(LlvmLibcPosixMadviseTest, Error_BadPtr) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // posix_madvise is a no-op on DONTNEED, so it shouldn't fail even with the // nullptr. EXPECT_EQ(LIBC_NAMESPACE::posix_madvise(nullptr, 8, POSIX_MADV_DONTNEED), 0); diff --git a/libc/test/src/sys/prctl/linux/prctl_test.cpp b/libc/test/src/sys/prctl/linux/prctl_test.cpp index 6278dcec588a..b528edc65595 100644 --- a/libc/test/src/sys/prctl/linux/prctl_test.cpp +++ b/libc/test/src/sys/prctl/linux/prctl_test.cpp @@ -34,7 +34,7 @@ TEST(LlvmLibcSysPrctlTest, GetSetName) { TEST(LlvmLibcSysPrctlTest, GetTHPDisable) { // Manually check errno since the return value logic here is not // covered in ErrnoSetterMatcher. - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int ret = LIBC_NAMESPACE::prctl(PR_GET_THP_DISABLE, 0, 0, 0, 0); ASSERT_ERRNO_SUCCESS(); // PR_GET_THP_DISABLE return (as the function result) the current diff --git a/libc/test/src/sys/random/linux/getrandom_test.cpp b/libc/test/src/sys/random/linux/getrandom_test.cpp index 5a595afb0cda..e3481b73ca00 100644 --- a/libc/test/src/sys/random/linux/getrandom_test.cpp +++ b/libc/test/src/sys/random/linux/getrandom_test.cpp @@ -15,13 +15,13 @@ TEST(LlvmLibcGetRandomTest, InvalidFlag) { LIBC_NAMESPACE::cpp::array buffer; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_THAT(LIBC_NAMESPACE::getrandom(buffer.data(), buffer.size(), -1), LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails(EINVAL)); } TEST(LlvmLibcGetRandomTest, InvalidBuffer) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_THAT(LIBC_NAMESPACE::getrandom(nullptr, 65536, 0), LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails(EFAULT)); } diff --git a/libc/test/src/sys/resource/getrlimit_setrlimit_test.cpp b/libc/test/src/sys/resource/getrlimit_setrlimit_test.cpp index 1a0d79f4e752..62d21c33e998 100644 --- a/libc/test/src/sys/resource/getrlimit_setrlimit_test.cpp +++ b/libc/test/src/sys/resource/getrlimit_setrlimit_test.cpp @@ -29,7 +29,7 @@ TEST(LlvmLibcResourceLimitsTest, SetNoFileLimit) { constexpr const char *TEST_FILE1 = "testdata/resource_limits1.test"; constexpr const char *TEST_FILE2 = "testdata/resource_limits2.test"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int fd1 = LIBC_NAMESPACE::open(TEST_FILE1, O_CREAT | O_WRONLY, S_IRWXU); ASSERT_GT(fd1, 0); @@ -54,7 +54,7 @@ TEST(LlvmLibcResourceLimitsTest, SetNoFileLimit) { ASSERT_LT(fd2, 0); ASSERT_ERRNO_FAILURE(); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_THAT(LIBC_NAMESPACE::close(fd1), Succeeds(0)); fd2 = LIBC_NAMESPACE::open(TEST_FILE2, O_RDONLY); @@ -64,7 +64,7 @@ TEST(LlvmLibcResourceLimitsTest, SetNoFileLimit) { ASSERT_LT(fd1, 0); ASSERT_ERRNO_FAILURE(); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_THAT(LIBC_NAMESPACE::close(fd2), Succeeds(0)); ASSERT_THAT(LIBC_NAMESPACE::unlink(TEST_FILE1), Succeeds(0)); diff --git a/libc/test/src/sys/select/select_ui_test.cpp b/libc/test/src/sys/select/select_ui_test.cpp index 2e6baced801b..a158cab8ff05 100644 --- a/libc/test/src/sys/select/select_ui_test.cpp +++ b/libc/test/src/sys/select/select_ui_test.cpp @@ -18,7 +18,7 @@ // Instead, one has to run it manually and press a key on the keyboard // to make the test succeed. TEST(LlvmLibcSelectTest, ReadStdinAfterSelect) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; constexpr int STDIN_FD = 0; fd_set set; FD_ZERO(&set); diff --git a/libc/test/src/sys/sendfile/sendfile_test.cpp b/libc/test/src/sys/sendfile/sendfile_test.cpp index 5ea9ca8d05c5..59025438a246 100644 --- a/libc/test/src/sys/sendfile/sendfile_test.cpp +++ b/libc/test/src/sys/sendfile/sendfile_test.cpp @@ -35,7 +35,7 @@ TEST(LlvmLibcSendfileTest, CreateAndTransfer) { constexpr const char *OUT_FILE = "testdata/sendfile_out.test"; const char IN_DATA[] = "sendfile test"; constexpr ssize_t IN_SIZE = ssize_t(sizeof(IN_DATA)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int in_fd = LIBC_NAMESPACE::open(IN_FILE, O_CREAT | O_WRONLY, S_IRWXU); ASSERT_GT(in_fd, 0); diff --git a/libc/test/src/sys/stat/chmod_test.cpp b/libc/test/src/sys/stat/chmod_test.cpp index 6fd056b2bd6c..c688996615ce 100644 --- a/libc/test/src/sys/stat/chmod_test.cpp +++ b/libc/test/src/sys/stat/chmod_test.cpp @@ -28,7 +28,7 @@ TEST(LlvmLibcChmodTest, ChangeAndOpen) { constexpr const char *TEST_FILE = "testdata/chmod.test"; const char WRITE_DATA[] = "test data"; constexpr ssize_t WRITE_SIZE = ssize_t(sizeof(WRITE_DATA)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int fd = LIBC_NAMESPACE::open(TEST_FILE, O_APPEND | O_WRONLY); ASSERT_GT(fd, 0); @@ -46,7 +46,7 @@ TEST(LlvmLibcChmodTest, ChangeAndOpen) { // Opening for writing should fail. EXPECT_EQ(LIBC_NAMESPACE::open(TEST_FILE, O_APPEND | O_WRONLY), -1); ASSERT_ERRNO_FAILURE(); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // But opening for reading should succeed. fd = LIBC_NAMESPACE::open(TEST_FILE, O_APPEND | O_RDONLY); EXPECT_GT(fd, 0); @@ -57,9 +57,9 @@ TEST(LlvmLibcChmodTest, ChangeAndOpen) { } TEST(LlvmLibcChmodTest, NonExistentFile) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; ASSERT_THAT(LIBC_NAMESPACE::chmod("non-existent-file", S_IRUSR), Fails(ENOENT)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; } diff --git a/libc/test/src/sys/stat/fchmod_test.cpp b/libc/test/src/sys/stat/fchmod_test.cpp index a0a93b03d22e..91c0f68b8708 100644 --- a/libc/test/src/sys/stat/fchmod_test.cpp +++ b/libc/test/src/sys/stat/fchmod_test.cpp @@ -28,7 +28,7 @@ TEST(LlvmLibcChmodTest, ChangeAndOpen) { constexpr const char *TEST_FILE = "testdata/fchmod.test"; const char WRITE_DATA[] = "test data"; constexpr ssize_t WRITE_SIZE = ssize_t(sizeof(WRITE_DATA)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int fd = LIBC_NAMESPACE::open(TEST_FILE, O_APPEND | O_WRONLY); ASSERT_GT(fd, 0); @@ -46,7 +46,7 @@ TEST(LlvmLibcChmodTest, ChangeAndOpen) { // Opening for writing should fail. EXPECT_EQ(LIBC_NAMESPACE::open(TEST_FILE, O_APPEND | O_WRONLY), -1); ASSERT_ERRNO_FAILURE(); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // But opening for reading should succeed. fd = LIBC_NAMESPACE::open(TEST_FILE, O_APPEND | O_RDONLY); EXPECT_GT(fd, 0); @@ -57,8 +57,8 @@ TEST(LlvmLibcChmodTest, ChangeAndOpen) { } TEST(LlvmLibcChmodTest, NonExistentFile) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(LIBC_NAMESPACE::fchmod(-1, S_IRUSR), -1); ASSERT_ERRNO_FAILURE(); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; } diff --git a/libc/test/src/sys/stat/fchmodat_test.cpp b/libc/test/src/sys/stat/fchmodat_test.cpp index e2cf170728ec..c43ef8ae1331 100644 --- a/libc/test/src/sys/stat/fchmodat_test.cpp +++ b/libc/test/src/sys/stat/fchmodat_test.cpp @@ -30,7 +30,7 @@ TEST(LlvmLibcFchmodatTest, ChangeAndOpen) { constexpr const char *TEST_FILE_BASENAME = "fchmodat.test"; const char WRITE_DATA[] = "fchmodat test"; constexpr ssize_t WRITE_SIZE = ssize_t(sizeof(WRITE_DATA)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int fd = LIBC_NAMESPACE::open(TEST_FILE, O_CREAT | O_WRONLY, S_IRWXU); ASSERT_GT(fd, 0); @@ -49,7 +49,7 @@ TEST(LlvmLibcFchmodatTest, ChangeAndOpen) { // Opening for writing should fail. EXPECT_EQ(LIBC_NAMESPACE::open(TEST_FILE, O_APPEND | O_WRONLY), -1); ASSERT_ERRNO_FAILURE(); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // But opening for reading should succeed. fd = LIBC_NAMESPACE::open(TEST_FILE, O_APPEND | O_RDONLY); EXPECT_GT(fd, 0); @@ -63,10 +63,10 @@ TEST(LlvmLibcFchmodatTest, ChangeAndOpen) { } TEST(LlvmLibcFchmodatTest, NonExistentFile) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; ASSERT_THAT( LIBC_NAMESPACE::fchmodat(AT_FDCWD, "non-existent-file", S_IRUSR, 0), Fails(ENOENT)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; } diff --git a/libc/test/src/sys/stat/fstat_test.cpp b/libc/test/src/sys/stat/fstat_test.cpp index 33769ea1f05a..1379eae26a47 100644 --- a/libc/test/src/sys/stat/fstat_test.cpp +++ b/libc/test/src/sys/stat/fstat_test.cpp @@ -26,7 +26,7 @@ TEST(LlvmLibcFStatTest, CreatAndReadMode) { // make it readonly using chmod. We test that chmod actually succeeded by // trying to open the file for writing and failing. constexpr const char *TEST_FILE = "testdata/fstat.test"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int fd = LIBC_NAMESPACE::open(TEST_FILE, O_CREAT | O_WRONLY, S_IRWXU); ASSERT_GT(fd, 0); @@ -42,9 +42,9 @@ TEST(LlvmLibcFStatTest, CreatAndReadMode) { } TEST(LlvmLibcFStatTest, NonExistentFile) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; struct stat statbuf; ASSERT_THAT(LIBC_NAMESPACE::fstat(-1, &statbuf), Fails(EBADF)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; } diff --git a/libc/test/src/sys/stat/lstat_test.cpp b/libc/test/src/sys/stat/lstat_test.cpp index a3b3c2cb0c1d..b44b3d1a59ce 100644 --- a/libc/test/src/sys/stat/lstat_test.cpp +++ b/libc/test/src/sys/stat/lstat_test.cpp @@ -26,7 +26,7 @@ TEST(LlvmLibcLStatTest, CreatAndReadMode) { // make it readonly using chmod. We test that chmod actually succeeded by // trying to open the file for writing and failing. constexpr const char *TEST_FILE = "testdata/lstat.test"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int fd = LIBC_NAMESPACE::open(TEST_FILE, O_CREAT | O_WRONLY, S_IRWXU); ASSERT_GT(fd, 0); @@ -42,10 +42,10 @@ TEST(LlvmLibcLStatTest, CreatAndReadMode) { } TEST(LlvmLibcLStatTest, NonExistentFile) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; struct stat statbuf; ASSERT_THAT(LIBC_NAMESPACE::lstat("non-existent-file", &statbuf), Fails(ENOENT)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; } diff --git a/libc/test/src/sys/stat/stat_test.cpp b/libc/test/src/sys/stat/stat_test.cpp index 1286e12fd611..baf363382022 100644 --- a/libc/test/src/sys/stat/stat_test.cpp +++ b/libc/test/src/sys/stat/stat_test.cpp @@ -26,7 +26,7 @@ TEST(LlvmLibcStatTest, CreatAndReadMode) { // make it readonly using chmod. We test that chmod actually succeeded by // trying to open the file for writing and failing. constexpr const char *TEST_FILE = "testdata/stat.test"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int fd = LIBC_NAMESPACE::open(TEST_FILE, O_CREAT | O_WRONLY, S_IRWXU); ASSERT_GT(fd, 0); @@ -42,10 +42,10 @@ TEST(LlvmLibcStatTest, CreatAndReadMode) { } TEST(LlvmLibcStatTest, NonExistentFile) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; struct stat statbuf; ASSERT_THAT(LIBC_NAMESPACE::stat("non-existent-file", &statbuf), Fails(ENOENT)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; } diff --git a/libc/test/src/termios/termios_test.cpp b/libc/test/src/termios/termios_test.cpp index 790c010c5b7e..f8fc09a8bbf0 100644 --- a/libc/test/src/termios/termios_test.cpp +++ b/libc/test/src/termios/termios_test.cpp @@ -30,21 +30,21 @@ using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; TEST(LlvmLibcTermiosTest, SpeedSmokeTest) { struct termios t; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_THAT(LIBC_NAMESPACE::cfsetispeed(&t, B50), Succeeds(0)); ASSERT_EQ(LIBC_NAMESPACE::cfgetispeed(&t), speed_t(B50)); ASSERT_THAT(LIBC_NAMESPACE::cfsetospeed(&t, B75), Succeeds(0)); ASSERT_EQ(LIBC_NAMESPACE::cfgetospeed(&t), speed_t(B75)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_THAT(LIBC_NAMESPACE::cfsetispeed(&t, ~CBAUD), Fails(EINVAL)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_THAT(LIBC_NAMESPACE::cfsetospeed(&t, ~CBAUD), Fails(EINVAL)); } TEST(LlvmLibcTermiosTest, GetAttrSmokeTest) { struct termios t; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int fd = LIBC_NAMESPACE::open("/dev/tty", O_RDONLY); if (fd < 0) return; // When /dev/tty is not available, no point continuing. @@ -54,7 +54,7 @@ TEST(LlvmLibcTermiosTest, GetAttrSmokeTest) { } TEST(LlvmLibcTermiosTest, TcGetSidSmokeTest) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int fd = LIBC_NAMESPACE::open("/dev/tty", O_RDONLY); if (fd < 0) return; // When /dev/tty is not available, no point continuing. diff --git a/libc/test/src/time/gmtime_test.cpp b/libc/test/src/time/gmtime_test.cpp index d4bcc7d5831e..433fbf666705 100644 --- a/libc/test/src/time/gmtime_test.cpp +++ b/libc/test/src/time/gmtime_test.cpp @@ -28,7 +28,7 @@ TEST(LlvmLibcGmTime, OutOfRange) { EXPECT_TRUE(tm_data == nullptr); ASSERT_ERRNO_EQ(EOVERFLOW); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; seconds = INT_MIN * static_cast( TimeConstants::NUMBER_OF_SECONDS_IN_LEAP_YEAR) - 1; diff --git a/libc/test/src/time/nanosleep_test.cpp b/libc/test/src/time/nanosleep_test.cpp index 8baaa29df478..2a6eea4d5e16 100644 --- a/libc/test/src/time/nanosleep_test.cpp +++ b/libc/test/src/time/nanosleep_test.cpp @@ -18,7 +18,7 @@ namespace cpp = LIBC_NAMESPACE::cpp; TEST(LlvmLibcNanosleep, SmokeTest) { // TODO: When we have the code to read clocks, test that time has passed. using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; struct timespec tim = {1, 500}; struct timespec tim2 = {0, 0}; diff --git a/libc/test/src/unistd/access_test.cpp b/libc/test/src/unistd/access_test.cpp index 1371afa1a00f..808cd5f3c8d8 100644 --- a/libc/test/src/unistd/access_test.cpp +++ b/libc/test/src/unistd/access_test.cpp @@ -21,7 +21,7 @@ TEST(LlvmLibcAccessTest, CreateAndTest) { // The test strategy is to repeatedly create a file in different modes and // test that it is accessable in those modes but not in others. - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; constexpr const char *FILENAME = "access.test"; auto TEST_FILE = libc_make_test_file_path(FILENAME); @@ -46,10 +46,10 @@ TEST(LlvmLibcAccessTest, CreateAndTest) { ASSERT_ERRNO_SUCCESS(); ASSERT_EQ(LIBC_NAMESPACE::access(TEST_FILE, R_OK), -1); ASSERT_ERRNO_EQ(EACCES); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(LIBC_NAMESPACE::access(TEST_FILE, W_OK), -1); ASSERT_ERRNO_EQ(EACCES); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_THAT(LIBC_NAMESPACE::unlink(TEST_FILE), Succeeds(0)); } diff --git a/libc/test/src/unistd/chdir_test.cpp b/libc/test/src/unistd/chdir_test.cpp index f187a771a122..51dc7bb15d3e 100644 --- a/libc/test/src/unistd/chdir_test.cpp +++ b/libc/test/src/unistd/chdir_test.cpp @@ -27,7 +27,7 @@ TEST(LlvmLibcChdirTest, ChangeAndOpen) { auto TEST_FILE = libc_make_test_file_path(FILENAME2); constexpr const char *FILENAME3 = "chdir.test"; auto TEST_FILE_BASE = libc_make_test_file_path(FILENAME3); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int fd = LIBC_NAMESPACE::open(TEST_FILE, O_PATH); ASSERT_GT(fd, 0); @@ -42,8 +42,8 @@ TEST(LlvmLibcChdirTest, ChangeAndOpen) { } TEST(LlvmLibcChdirTest, ChangeToNonExistentDir) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; ASSERT_THAT(LIBC_NAMESPACE::chdir("non-existent-dir"), Fails(ENOENT)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; } diff --git a/libc/test/src/unistd/dup2_test.cpp b/libc/test/src/unistd/dup2_test.cpp index 6fa09670e90a..2b2b3f3eef9a 100644 --- a/libc/test/src/unistd/dup2_test.cpp +++ b/libc/test/src/unistd/dup2_test.cpp @@ -20,7 +20,7 @@ TEST(LlvmLibcdupTest, ReadAndWriteViaDup) { constexpr int DUPFD = 0xD0; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; constexpr const char *FILENAME = "dup2.test"; auto TEST_FILE = libc_make_test_file_path(FILENAME); diff --git a/libc/test/src/unistd/dup3_test.cpp b/libc/test/src/unistd/dup3_test.cpp index cb0761ad0d87..7b1c8e0e2519 100644 --- a/libc/test/src/unistd/dup3_test.cpp +++ b/libc/test/src/unistd/dup3_test.cpp @@ -25,7 +25,7 @@ TEST(LlvmLibcdupTest, ReadAndWriteViaDup) { constexpr int DUPFD = 0xD0; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; constexpr const char *FILENAME = "dup3.test"; diff --git a/libc/test/src/unistd/dup_test.cpp b/libc/test/src/unistd/dup_test.cpp index f303cda5caac..c7bf87714210 100644 --- a/libc/test/src/unistd/dup_test.cpp +++ b/libc/test/src/unistd/dup_test.cpp @@ -19,7 +19,7 @@ #include TEST(LlvmLibcdupTest, ReadAndWriteViaDup) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; constexpr const char *FILENAME = "dup.test"; auto TEST_FILE = libc_make_test_file_path(FILENAME); diff --git a/libc/test/src/unistd/fchdir_test.cpp b/libc/test/src/unistd/fchdir_test.cpp index 0d1fc810a9e3..ae88e1f22ed6 100644 --- a/libc/test/src/unistd/fchdir_test.cpp +++ b/libc/test/src/unistd/fchdir_test.cpp @@ -27,7 +27,7 @@ TEST(LlvmLibcChdirTest, ChangeAndOpen) { auto TEST_FILE = libc_make_test_file_path(FILENAME2); constexpr const char *FILENAME3 = "fchdir.test"; auto TEST_FILE_BASE = libc_make_test_file_path(FILENAME3); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int dir_fd = LIBC_NAMESPACE::open(TEST_DIR, O_DIRECTORY); ASSERT_GT(dir_fd, 0); @@ -47,8 +47,8 @@ TEST(LlvmLibcChdirTest, ChangeAndOpen) { TEST(LlvmLibcChdirTest, ChangeToNonExistentDir) { using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(LIBC_NAMESPACE::fchdir(0), -1); ASSERT_ERRNO_FAILURE(); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; } diff --git a/libc/test/src/unistd/ftruncate_test.cpp b/libc/test/src/unistd/ftruncate_test.cpp index d338ceb9ec42..2fe4002692a8 100644 --- a/libc/test/src/unistd/ftruncate_test.cpp +++ b/libc/test/src/unistd/ftruncate_test.cpp @@ -34,7 +34,7 @@ TEST(LlvmLibcFtruncateTest, CreateAndTruncate) { // 2. Read it to make sure what was written is actually in the file. // 3. Truncate to 1 byte. // 4. Try to read more than 1 byte and fail. - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int fd = LIBC_NAMESPACE::open(TEST_FILE, O_WRONLY | O_CREAT, S_IRWXU); ASSERT_ERRNO_SUCCESS(); ASSERT_GT(fd, 0); diff --git a/libc/test/src/unistd/isatty_test.cpp b/libc/test/src/unistd/isatty_test.cpp index 8f9c58f56b07..c20eead46c06 100644 --- a/libc/test/src/unistd/isatty_test.cpp +++ b/libc/test/src/unistd/isatty_test.cpp @@ -21,7 +21,7 @@ using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; TEST(LlvmLibcIsATTYTest, StdInOutTests) { // If stdin is connected to a terminal, assume that all of the standard i/o // fds are. - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; if (LIBC_NAMESPACE::isatty(0)) { EXPECT_THAT(LIBC_NAMESPACE::isatty(0), Succeeds(1)); // stdin EXPECT_THAT(LIBC_NAMESPACE::isatty(1), Succeeds(1)); // stdout @@ -34,14 +34,14 @@ TEST(LlvmLibcIsATTYTest, StdInOutTests) { } TEST(LlvmLibcIsATTYTest, BadFdTest) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_THAT(LIBC_NAMESPACE::isatty(-1), Fails(EBADF, 0)); // invalid fd } TEST(LlvmLibcIsATTYTest, DevTTYTest) { constexpr const char *FILENAME = "/dev/tty"; auto TTY_FILE = libc_make_test_file_path(FILENAME); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int fd = LIBC_NAMESPACE::open(TTY_FILE, O_RDONLY); if (fd > 0) { ASSERT_ERRNO_SUCCESS(); @@ -53,7 +53,7 @@ TEST(LlvmLibcIsATTYTest, DevTTYTest) { TEST(LlvmLibcIsATTYTest, FileTest) { constexpr const char *FILENAME = "isatty.test"; auto TEST_FILE = libc_make_test_file_path(FILENAME); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int fd = LIBC_NAMESPACE::open(TEST_FILE, O_WRONLY | O_CREAT, S_IRWXU); ASSERT_ERRNO_SUCCESS(); ASSERT_GT(fd, 0); diff --git a/libc/test/src/unistd/link_test.cpp b/libc/test/src/unistd/link_test.cpp index fd377dd02114..3f1af2ec63f5 100644 --- a/libc/test/src/unistd/link_test.cpp +++ b/libc/test/src/unistd/link_test.cpp @@ -28,7 +28,7 @@ TEST(LlvmLibcLinkTest, CreateAndUnlink) { // 2. Create a link to that file. // 3. Open the link to check that the link was created. // 4. Cleanup the file and its link. - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int write_fd = LIBC_NAMESPACE::open(TEST_FILE, O_WRONLY | O_CREAT, S_IRWXU); ASSERT_ERRNO_SUCCESS(); ASSERT_GT(write_fd, 0); diff --git a/libc/test/src/unistd/linkat_test.cpp b/libc/test/src/unistd/linkat_test.cpp index 50384b1ecafb..c6e457560428 100644 --- a/libc/test/src/unistd/linkat_test.cpp +++ b/libc/test/src/unistd/linkat_test.cpp @@ -34,7 +34,7 @@ TEST(LlvmLibcLinkatTest, CreateAndUnlink) { // 2. Create a link to that file. // 3. Open the link to check that the link was created. // 4. Cleanup the file and its link. - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int write_fd = LIBC_NAMESPACE::open(TEST_FILE_PATH, O_WRONLY | O_CREAT, S_IRWXU); ASSERT_ERRNO_SUCCESS(); diff --git a/libc/test/src/unistd/readlink_test.cpp b/libc/test/src/unistd/readlink_test.cpp index 191993808221..20f395134911 100644 --- a/libc/test/src/unistd/readlink_test.cpp +++ b/libc/test/src/unistd/readlink_test.cpp @@ -22,7 +22,7 @@ TEST(LlvmLibcReadlinkTest, CreateAndUnlink) { auto LINK_VAL = libc_make_test_file_path(FILENAME); constexpr const char *FILENAME2 = "readlink.test.link"; auto LINK = libc_make_test_file_path(FILENAME2); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // The test strategy is as follows: // 1. Create a symlink with value LINK_VAL. diff --git a/libc/test/src/unistd/readlinkat_test.cpp b/libc/test/src/unistd/readlinkat_test.cpp index 03b35c5718ab..39d81d9ba544 100644 --- a/libc/test/src/unistd/readlinkat_test.cpp +++ b/libc/test/src/unistd/readlinkat_test.cpp @@ -24,7 +24,7 @@ TEST(LlvmLibcReadlinkatTest, CreateAndUnlink) { auto LINK_VAL = libc_make_test_file_path(FILENAME); constexpr const char *FILENAME2 = "readlinkat.test.link"; auto LINK = libc_make_test_file_path(FILENAME2); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // The test strategy is as follows: // 1. Create a symlink with value LINK_VAL. diff --git a/libc/test/src/unistd/symlink_test.cpp b/libc/test/src/unistd/symlink_test.cpp index 2be0431e473e..9e8b81c38269 100644 --- a/libc/test/src/unistd/symlink_test.cpp +++ b/libc/test/src/unistd/symlink_test.cpp @@ -30,7 +30,7 @@ TEST(LlvmLibcSymlinkTest, CreateAndUnlink) { // 2. Create a symlink to that file. // 3. Open the symlink to check that the symlink was created. // 4. Cleanup the file and its symlink. - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int write_fd = LIBC_NAMESPACE::open(TEST_FILE, O_WRONLY | O_CREAT, S_IRWXU); ASSERT_ERRNO_SUCCESS(); ASSERT_GT(write_fd, 0); diff --git a/libc/test/src/unistd/symlinkat_test.cpp b/libc/test/src/unistd/symlinkat_test.cpp index 4888574b6cd4..b6588a988b79 100644 --- a/libc/test/src/unistd/symlinkat_test.cpp +++ b/libc/test/src/unistd/symlinkat_test.cpp @@ -34,7 +34,7 @@ TEST(LlvmLibcSymlinkatTest, CreateAndUnlink) { // 2. Create a link to that file. // 3. Open the link to check that the link was created. // 4. Cleanup the file and its link. - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int write_fd = LIBC_NAMESPACE::open(TEST_FILE_PATH, O_WRONLY | O_CREAT, S_IRWXU); ASSERT_ERRNO_SUCCESS(); diff --git a/libc/test/src/unistd/syscall_test.cpp b/libc/test/src/unistd/syscall_test.cpp index aabbffc20d1b..cee29bd9afa3 100644 --- a/libc/test/src/unistd/syscall_test.cpp +++ b/libc/test/src/unistd/syscall_test.cpp @@ -27,7 +27,7 @@ using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; // because the macro generates a call to the actual internal function // (__llvm_libc_syscall) which is inside the namespace. TEST(LlvmLibcSyscallTest, TrivialCall) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_GE(LIBC_NAMESPACE::syscall(SYS_gettid), 0l); ASSERT_ERRNO_SUCCESS(); diff --git a/libc/test/src/unistd/truncate_test.cpp b/libc/test/src/unistd/truncate_test.cpp index a4cb9323bb86..261dd63d2afc 100644 --- a/libc/test/src/unistd/truncate_test.cpp +++ b/libc/test/src/unistd/truncate_test.cpp @@ -34,7 +34,7 @@ TEST(LlvmLibcTruncateTest, CreateAndTruncate) { // 2. Read it to make sure what was written is actually in the file. // 3. Truncate to 1 byte. // 4. Try to read more than 1 byte and fail. - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int fd = LIBC_NAMESPACE::open(TEST_FILE, O_WRONLY | O_CREAT, S_IRWXU); ASSERT_ERRNO_SUCCESS(); ASSERT_GT(fd, 0); -- GitLab From 6ec926df739b0f0ac0d970b0181d62ad6e564784 Mon Sep 17 00:00:00 2001 From: wangpc Date: Tue, 6 Feb 2024 17:35:46 +0800 Subject: [PATCH 042/266] [llvm-mca] Fix doc error --- llvm/docs/CommandGuide/llvm-mca.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/docs/CommandGuide/llvm-mca.rst b/llvm/docs/CommandGuide/llvm-mca.rst index 324e1e6e7bd1..86e3c91706da 100644 --- a/llvm/docs/CommandGuide/llvm-mca.rst +++ b/llvm/docs/CommandGuide/llvm-mca.rst @@ -350,7 +350,7 @@ an InstrumentRegion does not need a comment to end the region. Comments that are prefixed with `LLVM-MCA-` but do not correspond to a valid `INSTRUMENT_TYPE` for the target cause an error, except for `BEGIN` and `END`, since those correspond to AnalysisRegions. Comments -that do not start with `LLVM-MCA-` are ignored by :program `llvm-mca`. +that do not start with `LLVM-MCA-` are ignored by :program:`llvm-mca`. An instruction (a MCInst) is added to an InstrumentRegion R only if its location is in range [R.RangeStart, R.RangeEnd]. -- GitLab From 168002ece26269a4a6fcfce96ac8e66f6414c9e7 Mon Sep 17 00:00:00 2001 From: Nilanjana Basu Date: Tue, 6 Feb 2024 01:38:26 -0800 Subject: [PATCH 043/266] [Tests][LoopDistribute] Fixes failing unit test (#80809) Removed target-triple in target-independent test case to fix failing test caused by https://github.com/llvm/llvm-project/pull/67725. --- llvm/test/Transforms/LoopDistribute/basic-with-memchecks.ll | 2 -- 1 file changed, 2 deletions(-) diff --git a/llvm/test/Transforms/LoopDistribute/basic-with-memchecks.ll b/llvm/test/Transforms/LoopDistribute/basic-with-memchecks.ll index 27ca1a7541db..2b9f777e9f3b 100644 --- a/llvm/test/Transforms/LoopDistribute/basic-with-memchecks.ll +++ b/llvm/test/Transforms/LoopDistribute/basic-with-memchecks.ll @@ -18,7 +18,6 @@ ; } target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" -target triple = "x86_64-apple-macosx10.10.0" @B = common global ptr null, align 8 @A = common global ptr null, align 8 @@ -78,7 +77,6 @@ entry: ; CHECK: for.end: -; VECTORIZE: mul <4 x i32> ; VECTORIZE: mul <4 x i32> ; VECTORIZE-NOT: mul <4 x i32> -- GitLab From c9fd738388810aeaac99454989a150eb29f08521 Mon Sep 17 00:00:00 2001 From: paperchalice Date: Tue, 6 Feb 2024 17:56:56 +0800 Subject: [PATCH 044/266] [CodeGen] Port DeadMachineInstructionElim to new pass manager (#80582) A simple enough op pass so we can test standard instrumentations in future. --- .../llvm/CodeGen/DeadMachineInstructionElim.h | 25 +++++++ llvm/include/llvm/Passes/CodeGenPassBuilder.h | 1 + .../llvm/Passes/MachinePassRegistry.def | 2 +- .../CodeGen/DeadMachineInstructionElim.cpp | 66 ++++++++++++------- llvm/lib/Passes/PassBuilder.cpp | 1 + llvm/test/CodeGen/AArch64/elim-dead-mi.mir | 1 + 6 files changed, 71 insertions(+), 25 deletions(-) create mode 100644 llvm/include/llvm/CodeGen/DeadMachineInstructionElim.h diff --git a/llvm/include/llvm/CodeGen/DeadMachineInstructionElim.h b/llvm/include/llvm/CodeGen/DeadMachineInstructionElim.h new file mode 100644 index 000000000000..b9fe7cfccf9a --- /dev/null +++ b/llvm/include/llvm/CodeGen/DeadMachineInstructionElim.h @@ -0,0 +1,25 @@ +//===- llvm/CodeGen/DeadMachineInstructionElim.h ----------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_DEADMACHINEINSTRUCTIONELIM_H +#define LLVM_CODEGEN_DEADMACHINEINSTRUCTIONELIM_H + +#include "llvm/CodeGen/MachinePassManager.h" + +namespace llvm { + +class DeadMachineInstructionElimPass + : public MachinePassInfoMixin { +public: + PreservedAnalyses run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM); +}; + +} // namespace llvm + +#endif // LLVM_CODEGEN_DEADMACHINEINSTRUCTIONELIM_H diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index 40cc0c046531..fa6dbd4a4973 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -26,6 +26,7 @@ #include "llvm/CodeGen/AssignmentTrackingAnalysis.h" #include "llvm/CodeGen/CallBrPrepare.h" #include "llvm/CodeGen/CodeGenPrepare.h" +#include "llvm/CodeGen/DeadMachineInstructionElim.h" #include "llvm/CodeGen/DwarfEHPrepare.h" #include "llvm/CodeGen/ExpandMemCmp.h" #include "llvm/CodeGen/ExpandReductions.h" diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def index 5c3d2659fdfb..d8972080beeb 100644 --- a/llvm/include/llvm/Passes/MachinePassRegistry.def +++ b/llvm/include/llvm/Passes/MachinePassRegistry.def @@ -123,6 +123,7 @@ MACHINE_FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis(PI #ifndef MACHINE_FUNCTION_PASS #define MACHINE_FUNCTION_PASS(NAME, CREATE_PASS) #endif +MACHINE_FUNCTION_PASS("dead-mi-elimination", DeadMachineInstructionElimPass()) // MACHINE_FUNCTION_PASS("free-machine-function", FreeMachineFunctionPass()) MACHINE_FUNCTION_PASS("no-op-machine-function", NoOpMachineFunctionPass()) MACHINE_FUNCTION_PASS("print", PrintMIRPass()) @@ -160,7 +161,6 @@ DUMMY_MACHINE_FUNCTION_PASS("break-false-deps", BreakFalseDepsPass) DUMMY_MACHINE_FUNCTION_PASS("cfguard-longjmp", CFGuardLongjmpPass) DUMMY_MACHINE_FUNCTION_PASS("cfi-fixup", CFIFixupPass) DUMMY_MACHINE_FUNCTION_PASS("cfi-instr-inserter", CFIInstrInserterPass) -DUMMY_MACHINE_FUNCTION_PASS("dead-mi-elimination", DeadMachineInstructionElimPass) DUMMY_MACHINE_FUNCTION_PASS("detect-dead-lanes", DetectDeadLanesPass) DUMMY_MACHINE_FUNCTION_PASS("dot-machine-cfg", MachineCFGPrinter) DUMMY_MACHINE_FUNCTION_PASS("early-ifcvt", EarlyIfConverterPass) diff --git a/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp b/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp index 6a7de3b241fe..facc01452d2f 100644 --- a/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp +++ b/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp @@ -10,6 +10,7 @@ // //===----------------------------------------------------------------------===// +#include "llvm/CodeGen/DeadMachineInstructionElim.h" #include "llvm/ADT/PostOrderIterator.h" #include "llvm/ADT/Statistic.h" #include "llvm/CodeGen/LiveRegUnits.h" @@ -28,37 +29,57 @@ using namespace llvm; STATISTIC(NumDeletes, "Number of dead instructions deleted"); namespace { - class DeadMachineInstructionElim : public MachineFunctionPass { - bool runOnMachineFunction(MachineFunction &MF) override; +class DeadMachineInstructionElimImpl { + const MachineRegisterInfo *MRI = nullptr; + const TargetInstrInfo *TII = nullptr; + LiveRegUnits LivePhysRegs; - const MachineRegisterInfo *MRI = nullptr; - const TargetInstrInfo *TII = nullptr; - LiveRegUnits LivePhysRegs; +public: + bool runImpl(MachineFunction &MF); - public: - static char ID; // Pass identification, replacement for typeid - DeadMachineInstructionElim() : MachineFunctionPass(ID) { - initializeDeadMachineInstructionElimPass(*PassRegistry::getPassRegistry()); - } +private: + bool isDead(const MachineInstr *MI) const; + bool eliminateDeadMI(MachineFunction &MF); +}; - void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.setPreservesCFG(); - MachineFunctionPass::getAnalysisUsage(AU); - } +class DeadMachineInstructionElim : public MachineFunctionPass { +public: + static char ID; // Pass identification, replacement for typeid - private: - bool isDead(const MachineInstr *MI) const; + DeadMachineInstructionElim() : MachineFunctionPass(ID) { + initializeDeadMachineInstructionElimPass(*PassRegistry::getPassRegistry()); + } + + bool runOnMachineFunction(MachineFunction &MF) override { + if (skipFunction(MF.getFunction())) + return false; + return DeadMachineInstructionElimImpl().runImpl(MF); + } - bool eliminateDeadMI(MachineFunction &MF); - }; + void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.setPreservesCFG(); + MachineFunctionPass::getAnalysisUsage(AU); + } +}; +} // namespace + +PreservedAnalyses +DeadMachineInstructionElimPass::run(MachineFunction &MF, + MachineFunctionAnalysisManager &) { + if (!DeadMachineInstructionElimImpl().runImpl(MF)) + return PreservedAnalyses::all(); + PreservedAnalyses PA; + PA.preserveSet(); + return PA; } + char DeadMachineInstructionElim::ID = 0; char &llvm::DeadMachineInstructionElimID = DeadMachineInstructionElim::ID; INITIALIZE_PASS(DeadMachineInstructionElim, DEBUG_TYPE, "Remove dead machine instructions", false, false) -bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const { +bool DeadMachineInstructionElimImpl::isDead(const MachineInstr *MI) const { // Technically speaking inline asm without side effects and no defs can still // be deleted. But there is so much bad inline asm code out there, we should // let them be. @@ -102,10 +123,7 @@ bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const { return true; } -bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) { - if (skipFunction(MF.getFunction())) - return false; - +bool DeadMachineInstructionElimImpl::runImpl(MachineFunction &MF) { MRI = &MF.getRegInfo(); const TargetSubtargetInfo &ST = MF.getSubtarget(); @@ -118,7 +136,7 @@ bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) { return AnyChanges; } -bool DeadMachineInstructionElim::eliminateDeadMI(MachineFunction &MF) { +bool DeadMachineInstructionElimImpl::eliminateDeadMI(MachineFunction &MF) { bool AnyChanges = false; // Loop over all instructions in all blocks, from bottom to top, so that it's diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp index 89947711d4bf..7c306c4a21da 100644 --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -76,6 +76,7 @@ #include "llvm/CodeGen/BasicBlockSectionsProfileReader.h" #include "llvm/CodeGen/CallBrPrepare.h" #include "llvm/CodeGen/CodeGenPrepare.h" +#include "llvm/CodeGen/DeadMachineInstructionElim.h" #include "llvm/CodeGen/DwarfEHPrepare.h" #include "llvm/CodeGen/ExpandLargeDivRem.h" #include "llvm/CodeGen/ExpandLargeFpConvert.h" diff --git a/llvm/test/CodeGen/AArch64/elim-dead-mi.mir b/llvm/test/CodeGen/AArch64/elim-dead-mi.mir index 0542b46f2e39..9612f3269f16 100644 --- a/llvm/test/CodeGen/AArch64/elim-dead-mi.mir +++ b/llvm/test/CodeGen/AArch64/elim-dead-mi.mir @@ -1,5 +1,6 @@ # RUN: llc -mtriple=aarch64 -o - %s \ # RUN: -run-pass dead-mi-elimination | FileCheck %s +# RUN: llc -mtriple=aarch64 -o - %s -p dead-mi-elimination | FileCheck %s --- | @c = internal unnamed_addr global [3 x i8] zeroinitializer, align 4 @d = common dso_local local_unnamed_addr global i32 0, align 4 -- GitLab From c6b5ea339d9f257b64f4ca468e447f0e29a909a4 Mon Sep 17 00:00:00 2001 From: AtariDreams <83477269+AtariDreams@users.noreply.github.com> Date: Tue, 6 Feb 2024 05:00:35 -0500 Subject: [PATCH 045/266] [Transforms] Expand optimizeTan to fold more inverse trig pairs (#77799) optimizeTan has been renamed to optimizeTrigInversionPairs as a result. Sadly, this is not mathematically true that all inverse pairs fold to x. For example, asin(sin(x)) does not fold to x if x is over 2pi. --- .../llvm/Transforms/Utils/SimplifyLibCalls.h | 2 +- .../lib/Transforms/Utils/SimplifyLibCalls.cpp | 59 ++++++-- .../Transforms/InstCombine/tan-nofastmath.ll | 17 --- llvm/test/Transforms/InstCombine/tan.ll | 23 --- llvm/test/Transforms/InstCombine/trig.ll | 140 ++++++++++++++++++ 5 files changed, 185 insertions(+), 56 deletions(-) delete mode 100644 llvm/test/Transforms/InstCombine/tan-nofastmath.ll delete mode 100644 llvm/test/Transforms/InstCombine/tan.ll create mode 100644 llvm/test/Transforms/InstCombine/trig.ll diff --git a/llvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h b/llvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h index 1aad0b298845..1b6b525b19ca 100644 --- a/llvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h +++ b/llvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h @@ -203,7 +203,7 @@ private: Value *optimizeSqrt(CallInst *CI, IRBuilderBase &B); Value *mergeSqrtToExp(CallInst *CI, IRBuilderBase &B); Value *optimizeSinCosPi(CallInst *CI, bool IsSin, IRBuilderBase &B); - Value *optimizeTan(CallInst *CI, IRBuilderBase &B); + Value *optimizeTrigInversionPairs(CallInst *CI, IRBuilderBase &B); // Wrapper for all floating point library call optimizations Value *optimizeFloatingPointLibCall(CallInst *CI, LibFunc Func, IRBuilderBase &B); diff --git a/llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp b/llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp index f79549f79389..26a34aa99e1b 100644 --- a/llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp +++ b/llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp @@ -2681,13 +2681,16 @@ Value *LibCallSimplifier::optimizeSqrt(CallInst *CI, IRBuilderBase &B) { return copyFlags(*CI, FabsCall); } -// TODO: Generalize to handle any trig function and its inverse. -Value *LibCallSimplifier::optimizeTan(CallInst *CI, IRBuilderBase &B) { +Value *LibCallSimplifier::optimizeTrigInversionPairs(CallInst *CI, + IRBuilderBase &B) { Module *M = CI->getModule(); Function *Callee = CI->getCalledFunction(); Value *Ret = nullptr; StringRef Name = Callee->getName(); - if (UnsafeFPShrink && Name == "tan" && hasFloatVersion(M, Name)) + if (UnsafeFPShrink && + (Name == "tan" || Name == "atanh" || Name == "sinh" || Name == "cosh" || + Name == "asinh") && + hasFloatVersion(M, Name)) Ret = optimizeUnaryDoubleFP(CI, B, TLI, true); Value *Op1 = CI->getArgOperand(0); @@ -2700,16 +2703,34 @@ Value *LibCallSimplifier::optimizeTan(CallInst *CI, IRBuilderBase &B) { return Ret; // tan(atan(x)) -> x - // tanf(atanf(x)) -> x - // tanl(atanl(x)) -> x + // atanh(tanh(x)) -> x + // sinh(asinh(x)) -> x + // asinh(sinh(x)) -> x + // cosh(acosh(x)) -> x LibFunc Func; Function *F = OpC->getCalledFunction(); if (F && TLI->getLibFunc(F->getName(), Func) && - isLibFuncEmittable(M, TLI, Func) && - ((Func == LibFunc_atan && Callee->getName() == "tan") || - (Func == LibFunc_atanf && Callee->getName() == "tanf") || - (Func == LibFunc_atanl && Callee->getName() == "tanl"))) - Ret = OpC->getArgOperand(0); + isLibFuncEmittable(M, TLI, Func)) { + LibFunc inverseFunc = llvm::StringSwitch(Callee->getName()) + .Case("tan", LibFunc_atan) + .Case("atanh", LibFunc_tanh) + .Case("sinh", LibFunc_asinh) + .Case("cosh", LibFunc_acosh) + .Case("tanf", LibFunc_atanf) + .Case("atanhf", LibFunc_tanhf) + .Case("sinhf", LibFunc_asinhf) + .Case("coshf", LibFunc_acoshf) + .Case("tanl", LibFunc_atanl) + .Case("atanhl", LibFunc_tanhl) + .Case("sinhl", LibFunc_asinhl) + .Case("coshl", LibFunc_acoshl) + .Case("asinh", LibFunc_sinh) + .Case("asinhf", LibFunc_sinhf) + .Case("asinhl", LibFunc_sinhl) + .Default(NumLibFuncs); // Used as error value + if (Func == inverseFunc) + Ret = OpC->getArgOperand(0); + } return Ret; } @@ -3702,7 +3723,19 @@ Value *LibCallSimplifier::optimizeFloatingPointLibCall(CallInst *CI, case LibFunc_tan: case LibFunc_tanf: case LibFunc_tanl: - return optimizeTan(CI, Builder); + case LibFunc_sinh: + case LibFunc_sinhf: + case LibFunc_sinhl: + case LibFunc_asinh: + case LibFunc_asinhf: + case LibFunc_asinhl: + case LibFunc_cosh: + case LibFunc_coshf: + case LibFunc_coshl: + case LibFunc_atanh: + case LibFunc_atanhf: + case LibFunc_atanhl: + return optimizeTrigInversionPairs(CI, Builder); case LibFunc_ceil: return replaceUnaryCall(CI, Builder, Intrinsic::ceil); case LibFunc_floor: @@ -3720,17 +3753,13 @@ Value *LibCallSimplifier::optimizeFloatingPointLibCall(CallInst *CI, case LibFunc_acos: case LibFunc_acosh: case LibFunc_asin: - case LibFunc_asinh: case LibFunc_atan: - case LibFunc_atanh: case LibFunc_cbrt: - case LibFunc_cosh: case LibFunc_exp: case LibFunc_exp10: case LibFunc_expm1: case LibFunc_cos: case LibFunc_sin: - case LibFunc_sinh: case LibFunc_tanh: if (UnsafeFPShrink && hasFloatVersion(M, CI->getCalledFunction()->getName())) return optimizeUnaryDoubleFP(CI, Builder, TLI, true); diff --git a/llvm/test/Transforms/InstCombine/tan-nofastmath.ll b/llvm/test/Transforms/InstCombine/tan-nofastmath.ll deleted file mode 100644 index 514ff4e40d61..000000000000 --- a/llvm/test/Transforms/InstCombine/tan-nofastmath.ll +++ /dev/null @@ -1,17 +0,0 @@ -; RUN: opt < %s -passes=instcombine -S | FileCheck %s - -define float @mytan(float %x) { -entry: - %call = call float @atanf(float %x) - %call1 = call float @tanf(float %call) - ret float %call1 -} - -; CHECK-LABEL: define float @mytan( -; CHECK: %call = call float @atanf(float %x) -; CHECK-NEXT: %call1 = call float @tanf(float %call) -; CHECK-NEXT: ret float %call1 -; CHECK-NEXT: } - -declare float @tanf(float) -declare float @atanf(float) diff --git a/llvm/test/Transforms/InstCombine/tan.ll b/llvm/test/Transforms/InstCombine/tan.ll deleted file mode 100644 index 49f6e00e6d9b..000000000000 --- a/llvm/test/Transforms/InstCombine/tan.ll +++ /dev/null @@ -1,23 +0,0 @@ -; RUN: opt < %s -passes=instcombine -S | FileCheck %s - -define float @mytan(float %x) { - %call = call fast float @atanf(float %x) - %call1 = call fast float @tanf(float %call) - ret float %call1 -} - -; CHECK-LABEL: define float @mytan( -; CHECK: ret float %x - -define float @test2(ptr %fptr) { - %call1 = call fast float %fptr() - %tan = call fast float @tanf(float %call1) - ret float %tan -} - -; CHECK-LABEL: @test2 -; CHECK: tanf - -declare float @tanf(float) -declare float @atanf(float) - diff --git a/llvm/test/Transforms/InstCombine/trig.ll b/llvm/test/Transforms/InstCombine/trig.ll new file mode 100644 index 000000000000..5dda1524396d --- /dev/null +++ b/llvm/test/Transforms/InstCombine/trig.ll @@ -0,0 +1,140 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt < %s -passes=instcombine -S | FileCheck %s + +define float @tanAtanInverseFast(float %x) { +; CHECK-LABEL: define float @tanAtanInverseFast( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[CALL:%.*]] = call fast float @atanf(float [[X]]) +; CHECK-NEXT: ret float [[X]] +; + %call = call fast float @atanf(float %x) + %call1 = call fast float @tanf(float %call) + ret float %call1 +} + +define float @atanhTanhInverseFast(float %x) { +; CHECK-LABEL: define float @atanhTanhInverseFast( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[CALL:%.*]] = call fast float @tanhf(float [[X]]) +; CHECK-NEXT: ret float [[X]] +; + %call = call fast float @tanhf(float %x) + %call1 = call fast float @atanhf(float %call) + ret float %call1 +} + +define float @sinhAsinhInverseFast(float %x) { +; CHECK-LABEL: define float @sinhAsinhInverseFast( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[CALL:%.*]] = call fast float @asinhf(float [[X]]) +; CHECK-NEXT: ret float [[X]] +; + %call = call fast float @asinhf(float %x) + %call1 = call fast float @sinhf(float %call) + ret float %call1 +} + +define float @asinhSinhInverseFast(float %x) { +; CHECK-LABEL: define float @asinhSinhInverseFast( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[CALL:%.*]] = call fast float @sinhf(float [[X]]) +; CHECK-NEXT: ret float [[X]] +; + %call = call fast float @sinhf(float %x) + %call1 = call fast float @asinhf(float %call) + ret float %call1 +} + +define float @coshAcoshInverseFast(float %x) { +; CHECK-LABEL: define float @coshAcoshInverseFast( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[CALL:%.*]] = call fast float @acoshf(float [[X]]) +; CHECK-NEXT: ret float [[X]] +; + %call = call fast float @acoshf(float %x) + %call1 = call fast float @coshf(float %call) + ret float %call1 +} + +define float @indirectTanCall(ptr %fptr) { +; CHECK-LABEL: define float @indirectTanCall( +; CHECK-SAME: ptr [[FPTR:%.*]]) { +; CHECK-NEXT: [[CALL1:%.*]] = call fast float [[FPTR]]() +; CHECK-NEXT: [[TAN:%.*]] = call fast float @tanf(float [[CALL1]]) +; CHECK-NEXT: ret float [[TAN]] +; + %call1 = call fast float %fptr() + %tan = call fast float @tanf(float %call1) + ret float %tan +} + +; No fast-math. + +define float @tanAtanInverse(float %x) { +; CHECK-LABEL: define float @tanAtanInverse( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[CALL:%.*]] = call float @atanf(float [[X]]) +; CHECK-NEXT: [[CALL1:%.*]] = call float @tanf(float [[CALL]]) +; CHECK-NEXT: ret float [[CALL1]] +; + %call = call float @atanf(float %x) + %call1 = call float @tanf(float %call) + ret float %call1 +} + +define float @atanhTanhInverse(float %x) { +; CHECK-LABEL: define float @atanhTanhInverse( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[CALL:%.*]] = call float @tanhf(float [[X]]) +; CHECK-NEXT: [[CALL1:%.*]] = call float @atanhf(float [[CALL]]) +; CHECK-NEXT: ret float [[CALL1]] +; + %call = call float @tanhf(float %x) + %call1 = call float @atanhf(float %call) + ret float %call1 +} + +define float @sinhAsinhInverse(float %x) { +; CHECK-LABEL: define float @sinhAsinhInverse( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[CALL:%.*]] = call float @asinhf(float [[X]]) +; CHECK-NEXT: [[CALL1:%.*]] = call float @sinhf(float [[CALL]]) +; CHECK-NEXT: ret float [[CALL1]] +; + %call = call float @asinhf(float %x) + %call1 = call float @sinhf(float %call) + ret float %call1 +} + +define float @asinhSinhInverse(float %x) { +; CHECK-LABEL: define float @asinhSinhInverse( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[CALL:%.*]] = call float @sinhf(float [[X]]) +; CHECK-NEXT: [[CALL1:%.*]] = call float @asinhf(float [[CALL]]) +; CHECK-NEXT: ret float [[CALL1]] +; + %call = call float @sinhf(float %x) + %call1 = call float @asinhf(float %call) + ret float %call1 +} + +define float @coshAcoshInverse(float %x) { +; CHECK-LABEL: define float @coshAcoshInverse( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[CALL:%.*]] = call float @acoshf(float [[X]]) +; CHECK-NEXT: [[CALL1:%.*]] = call float @coshf(float [[CALL]]) +; CHECK-NEXT: ret float [[CALL1]] +; + %call = call float @acoshf(float %x) + %call1 = call float @coshf(float %call) + ret float %call1 +} + +declare float @asinhf(float) +declare float @sinhf(float) +declare float @acoshf(float) +declare float @coshf(float) +declare float @tanhf(float) +declare float @atanhf(float) +declare float @tanf(float) +declare float @atanf(float) -- GitLab From 35904ec4e1fca8d26c37a7f6aafd6c32f0ef9b09 Mon Sep 17 00:00:00 2001 From: Sjoerd Meijer Date: Tue, 6 Feb 2024 10:29:42 +0000 Subject: [PATCH 046/266] [AArch64] MI Scheduler STP combine (#80188) Add opcodes for different store instructions to the target hook that can enable more STP pairs. This is split off from the patch that does the same for some load instructions (#79003). Patch co-authored by Cameron McInally. --- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 15 ++++ .../test/CodeGen/AArch64/arm64-ldp-cluster.ll | 72 ++++++++++++++++++- 2 files changed, 86 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index f5c5ff6d98aa..9add7d87017a 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -4206,6 +4206,21 @@ static bool canPairLdStOpc(unsigned FirstOpc, unsigned SecondOpc) { switch (FirstOpc) { default: return false; + case AArch64::STRSui: + case AArch64::STURSi: + return SecondOpc == AArch64::STRSui || SecondOpc == AArch64::STURSi; + case AArch64::STRDui: + case AArch64::STURDi: + return SecondOpc == AArch64::STRDui || SecondOpc == AArch64::STURDi; + case AArch64::STRQui: + case AArch64::STURQi: + return SecondOpc == AArch64::STRQui || SecondOpc == AArch64::STURQi; + case AArch64::STRWui: + case AArch64::STURWi: + return SecondOpc == AArch64::STRWui || SecondOpc == AArch64::STURWi; + case AArch64::STRXui: + case AArch64::STURXi: + return SecondOpc == AArch64::STRXui || SecondOpc == AArch64::STURXi; case AArch64::LDRSui: case AArch64::LDURSi: return SecondOpc == AArch64::LDRSui || SecondOpc == AArch64::LDURSi; diff --git a/llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll b/llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll index d1bce2fbfa9f..8c7b31fd34c4 100644 --- a/llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll +++ b/llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll @@ -1,5 +1,5 @@ ; REQUIRES: asserts -; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s +; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefixes=CHECK,CHECK-A57 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=exynos-m3 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s ; Test ldr clustering. @@ -227,3 +227,73 @@ entry: store i64 %r53, ptr %wb ret void } + +; CHECK: ********** MI Scheduling ********** +; CHECK: STURWi_STRWui:%bb.0 entry +; CHECK: Cluster ld/st SU(3) - SU(4) +; CHECK: SU(3): STURWi %{{[0-9]+}}:gpr32 +; CHECK: SU(4): STRWui %{{[0-9]+}}:gpr32 +; +define void @STURWi_STRWui(ptr nocapture readonly %arg, i32 %b, i32 %c) { +entry: + %r51 = getelementptr i8, ptr %arg, i64 -4 + store i32 %b, ptr %r51 + store i32 %c, ptr %arg + ret void +} + +; CHECK: ********** MI Scheduling ********** +; CHECK: STURXi_STRXui:%bb.0 entry +; CHECK: Cluster ld/st SU(3) - SU(4) +; CHECK: SU(3): STURXi %{{[0-9]+}}:gpr64 +; CHECK: SU(4): STRXui %{{[0-9]+}}:gpr64 +; +define void @STURXi_STRXui(ptr nocapture readonly %arg, i64 %b, i64 %c) { +entry: + %r51 = getelementptr i8, ptr %arg, i64 -8 + store i64 %b, ptr %r51 + store i64 %c, ptr %arg + ret void +} + +; CHECK-A57: ********** MI Scheduling ********** +; CHECK-A57: STURSi_STRSui:%bb.0 entry +; CHECK-A57: Cluster ld/st SU(3) - SU(4) +; CHECK-A57: SU(3): STURSi %{{[0-9]+}}:fpr32 +; CHECK-A57: SU(4): STRSui %{{[0-9]+}}:fpr32 +; +define void @STURSi_STRSui(ptr nocapture readonly %arg, float %b, float %c) { +entry: + %r51 = getelementptr i8, ptr %arg, i64 -4 + store float %b, ptr %r51 + store float %c, ptr %arg + ret void +} + +; CHECK-A57: ********** MI Scheduling ********** +; CHECK-A57: STURDi_STRDui:%bb.0 entry +; CHECK-A57: Cluster ld/st SU(3) - SU(4) +; CHECK-A57: SU(3): STURDi %{{[0-9]+}}:fpr64 +; CHECK-A57: SU(4): STRDui %{{[0-9]+}}:fpr64 +; +define void @STURDi_STRDui(ptr nocapture readonly %arg, <2 x float> %b, <2 x float> %c) { +entry: + %r51 = getelementptr i8, ptr %arg, i64 -8 + store <2 x float> %b, ptr %r51 + store <2 x float> %c, ptr %arg + ret void +} + +; CHECK-A57: ********** MI Scheduling ********** +; CHECK-A57: STURQi_STRQui:%bb.0 entry +; CHECK-A57: Cluster ld/st SU(3) - SU(4) +; CHECK-A57: SU(3): STURQi %{{[0-9]+}}:fpr128 +; CHECK-A57: SU(4): STRQui %{{[0-9]+}}:fpr128 +; +define void @STURQi_STRQui(ptr nocapture readonly %arg, <2 x double> %b, <2 x double> %c) { +entry: + %r51 = getelementptr i8, ptr %arg, i64 -16 + store <2 x double> %b, ptr %r51 + store <2 x double> %c, ptr %arg + ret void +} -- GitLab From 2f7d9abf7c2ba1e697d46ffca0bf2f5a2bf8ba0c Mon Sep 17 00:00:00 2001 From: Cullen Rhodes Date: Tue, 6 Feb 2024 10:25:02 +0000 Subject: [PATCH 047/266] [mlir][ArmSME][nfc] Fix broken doc links to fmopa_2way op --- mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEOps.td | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEOps.td b/mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEOps.td index 2aaf1d878725..51fd4b7ca21b 100644 --- a/mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEOps.td +++ b/mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEOps.td @@ -1009,7 +1009,7 @@ def FMops2WayOp ``` Refer to - [fmopa_2way](#arm_smefmopa_2way-arm_smefmopa_2wayop) for a detailed + [fmopa_2way](#arm_smefmopa_2way-arm_smefmopa2wayop) for a detailed description of 2-way outer products. | Spec | Features | @@ -1031,7 +1031,7 @@ def SMopa2WayOp ``` Refer to - [fmopa_2way](#arm_smefmopa_2way-arm_smefmopa_2wayop) for a detailed + [fmopa_2way](#arm_smefmopa_2way-arm_smefmopa2wayop) for a detailed description of 2-way outer products. | Spec | Features | @@ -1052,7 +1052,7 @@ def SMops2WayOp ``` Refer to - [fmopa_2way](#arm_smefmopa_2way-arm_smefmopa_2wayop) for a detailed + [fmopa_2way](#arm_smefmopa_2way-arm_smefmopa2wayop) for a detailed description of 2-way outer products. | Spec | Features | @@ -1073,7 +1073,7 @@ def UMopa2WayOp ``` Refer to - [fmopa_2way](#arm_smefmopa_2way-arm_smefmopa_2wayop) for a detailed + [fmopa_2way](#arm_smefmopa_2way-arm_smefmopa2wayop) for a detailed description of 2-way outer products. | Spec | Features | @@ -1094,7 +1094,7 @@ def UMops2WayOp ``` Refer to - [fmopa_2way](#arm_smefmopa_2way-arm_smefmopa_2wayop) for a detailed + [fmopa_2way](#arm_smefmopa_2way-arm_smefmopa2wayop) for a detailed description of 2-way outer products. | Spec | Features | -- GitLab From bc569f6eb3848361ae637de0a873e1c442958a71 Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Tue, 6 Feb 2024 18:31:07 +0800 Subject: [PATCH 048/266] [RISCV] Add test case for shufflevector that gets scalarized. NFC This shufflevector gets scalarized into a build_vector of extract_vector_elts because the output type doesn't match the input vector type. Normally this is combined back into a vector_shuffle in DAGCombine, but this one fails because we don't consider a extract_subvector to be cheap, specifically because it's at an index > 31. This should be canonicalized back into a vector_shuffle at some point so we can lower it as a vrgather.vv. --- .../RISCV/rvv/fixed-vectors-int-shuffles.ll | 97 +++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll index 23629ace4cf4..acad71bb5959 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll @@ -719,3 +719,100 @@ define <8 x i32> @shuffle_v8i32_2(<8 x i32> %x, <8 x i32> %y) { %s = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> ret <8 x i32> %s } + +; FIXME: This could be expressed as a vrgather.vv +define <8 x i8> @shuffle_v64i8_v8i8(<64 x i8> %wide.vec) { +; RV32-LABEL: shuffle_v64i8_v8i8: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -128 +; RV32-NEXT: .cfi_def_cfa_offset 128 +; RV32-NEXT: sw ra, 124(sp) # 4-byte Folded Spill +; RV32-NEXT: sw s0, 120(sp) # 4-byte Folded Spill +; RV32-NEXT: .cfi_offset ra, -4 +; RV32-NEXT: .cfi_offset s0, -8 +; RV32-NEXT: addi s0, sp, 128 +; RV32-NEXT: .cfi_def_cfa s0, 0 +; RV32-NEXT: andi sp, sp, -64 +; RV32-NEXT: li a0, 64 +; RV32-NEXT: mv a1, sp +; RV32-NEXT: vsetvli zero, a0, e8, m4, ta, ma +; RV32-NEXT: vse8.v v8, (a1) +; RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma +; RV32-NEXT: vslidedown.vi v10, v8, 8 +; RV32-NEXT: vmv.x.s a0, v10 +; RV32-NEXT: vmv.x.s a1, v8 +; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; RV32-NEXT: vmv.v.x v10, a1 +; RV32-NEXT: vslide1down.vx v10, v10, a0 +; RV32-NEXT: vsetivli zero, 1, e8, m2, ta, ma +; RV32-NEXT: vslidedown.vi v12, v8, 16 +; RV32-NEXT: vmv.x.s a0, v12 +; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; RV32-NEXT: vslide1down.vx v10, v10, a0 +; RV32-NEXT: vsetivli zero, 1, e8, m2, ta, ma +; RV32-NEXT: vslidedown.vi v8, v8, 24 +; RV32-NEXT: vmv.x.s a0, v8 +; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; RV32-NEXT: vslide1down.vx v8, v10, a0 +; RV32-NEXT: lbu a0, 32(sp) +; RV32-NEXT: lbu a1, 40(sp) +; RV32-NEXT: lbu a2, 48(sp) +; RV32-NEXT: lbu a3, 56(sp) +; RV32-NEXT: vslide1down.vx v8, v8, a0 +; RV32-NEXT: vslide1down.vx v8, v8, a1 +; RV32-NEXT: vslide1down.vx v8, v8, a2 +; RV32-NEXT: vslide1down.vx v8, v8, a3 +; RV32-NEXT: addi sp, s0, -128 +; RV32-NEXT: lw ra, 124(sp) # 4-byte Folded Reload +; RV32-NEXT: lw s0, 120(sp) # 4-byte Folded Reload +; RV32-NEXT: addi sp, sp, 128 +; RV32-NEXT: ret +; +; RV64-LABEL: shuffle_v64i8_v8i8: +; RV64: # %bb.0: +; RV64-NEXT: addi sp, sp, -128 +; RV64-NEXT: .cfi_def_cfa_offset 128 +; RV64-NEXT: sd ra, 120(sp) # 8-byte Folded Spill +; RV64-NEXT: sd s0, 112(sp) # 8-byte Folded Spill +; RV64-NEXT: .cfi_offset ra, -8 +; RV64-NEXT: .cfi_offset s0, -16 +; RV64-NEXT: addi s0, sp, 128 +; RV64-NEXT: .cfi_def_cfa s0, 0 +; RV64-NEXT: andi sp, sp, -64 +; RV64-NEXT: li a0, 64 +; RV64-NEXT: mv a1, sp +; RV64-NEXT: vsetvli zero, a0, e8, m4, ta, ma +; RV64-NEXT: vse8.v v8, (a1) +; RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma +; RV64-NEXT: vslidedown.vi v10, v8, 8 +; RV64-NEXT: vmv.x.s a0, v10 +; RV64-NEXT: vmv.x.s a1, v8 +; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; RV64-NEXT: vmv.v.x v10, a1 +; RV64-NEXT: vslide1down.vx v10, v10, a0 +; RV64-NEXT: vsetivli zero, 1, e8, m2, ta, ma +; RV64-NEXT: vslidedown.vi v12, v8, 16 +; RV64-NEXT: vmv.x.s a0, v12 +; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; RV64-NEXT: vslide1down.vx v10, v10, a0 +; RV64-NEXT: vsetivli zero, 1, e8, m2, ta, ma +; RV64-NEXT: vslidedown.vi v8, v8, 24 +; RV64-NEXT: vmv.x.s a0, v8 +; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; RV64-NEXT: vslide1down.vx v8, v10, a0 +; RV64-NEXT: lbu a0, 32(sp) +; RV64-NEXT: lbu a1, 40(sp) +; RV64-NEXT: lbu a2, 48(sp) +; RV64-NEXT: lbu a3, 56(sp) +; RV64-NEXT: vslide1down.vx v8, v8, a0 +; RV64-NEXT: vslide1down.vx v8, v8, a1 +; RV64-NEXT: vslide1down.vx v8, v8, a2 +; RV64-NEXT: vslide1down.vx v8, v8, a3 +; RV64-NEXT: addi sp, s0, -128 +; RV64-NEXT: ld ra, 120(sp) # 8-byte Folded Reload +; RV64-NEXT: ld s0, 112(sp) # 8-byte Folded Reload +; RV64-NEXT: addi sp, sp, 128 +; RV64-NEXT: ret + %s = shufflevector <64 x i8> %wide.vec, <64 x i8> poison, <8 x i32> + ret <8 x i8> %s +} -- GitLab From 726cf604569d893d3bcb2c50d7905a95db92ddfd Mon Sep 17 00:00:00 2001 From: wangpc Date: Tue, 6 Feb 2024 18:35:33 +0800 Subject: [PATCH 049/266] [llvm-mca] Add an empty line to fix doc error --- llvm/docs/CommandGuide/llvm-mca.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/docs/CommandGuide/llvm-mca.rst b/llvm/docs/CommandGuide/llvm-mca.rst index 86e3c91706da..eae5e1406b89 100644 --- a/llvm/docs/CommandGuide/llvm-mca.rst +++ b/llvm/docs/CommandGuide/llvm-mca.rst @@ -908,6 +908,7 @@ process instructions. * Retire (Instruction is retired; writes are architecturally committed). The in-order pipeline implements the following sequence of stages: + * InOrderIssue (Instruction is issued to the processor pipelines). * Retire (Instruction is retired; writes are architecturally committed). -- GitLab From 292d9e869fcfc2ece694848db4022b0b939847e3 Mon Sep 17 00:00:00 2001 From: Qiu Chaofan Date: Tue, 6 Feb 2024 18:37:31 +0800 Subject: [PATCH 050/266] [PowerPC] Mask constant operands in ValueBit tracking (#67653) In IR or C code, shift amount larger than value size is undefined behavior. But in practice, backend lowering for shift_parts produces add/sub of shift amounts, thus constant shift amounts might be negative or larger than value size, which depends on ISA definition. PowerPC ISA says, the lowest 7 bits (6 bits for 32-bit instruction) will be taken, and if the highest among them is 1, result will be zero, otherwise the low 6 bits (or 5 on 32-bit) are used as shift amount. This commit emulates the behavior and avoids array overflow in bit permutation's value bits calculator. --- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 37 ++++-- llvm/test/CodeGen/PowerPC/pr59074.ll | 132 ++++++++++++++++++++ 2 files changed, 156 insertions(+), 13 deletions(-) create mode 100644 llvm/test/CodeGen/PowerPC/pr59074.ll diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 6a3710407bc4..9e5f0b36616d 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -1632,7 +1632,8 @@ class BitPermutationSelector { default: break; case ISD::ROTL: if (isa(V.getOperand(1))) { - unsigned RotAmt = V.getConstantOperandVal(1); + assert(isPowerOf2_32(NumBits) && "rotl bits should be power of 2!"); + unsigned RotAmt = V.getConstantOperandVal(1) & (NumBits - 1); const auto &LHSBits = *getValueBits(V.getOperand(0), NumBits).second; @@ -1645,15 +1646,20 @@ class BitPermutationSelector { case ISD::SHL: case PPCISD::SHL: if (isa(V.getOperand(1))) { - unsigned ShiftAmt = V.getConstantOperandVal(1); + // sld takes 7 bits, slw takes 6. + unsigned ShiftAmt = V.getConstantOperandVal(1) & ((NumBits << 1) - 1); const auto &LHSBits = *getValueBits(V.getOperand(0), NumBits).second; - for (unsigned i = ShiftAmt; i < NumBits; ++i) - Bits[i] = LHSBits[i - ShiftAmt]; - - for (unsigned i = 0; i < ShiftAmt; ++i) - Bits[i] = ValueBit(ValueBit::ConstZero); + if (ShiftAmt >= NumBits) { + for (unsigned i = 0; i < NumBits; ++i) + Bits[i] = ValueBit(ValueBit::ConstZero); + } else { + for (unsigned i = ShiftAmt; i < NumBits; ++i) + Bits[i] = LHSBits[i - ShiftAmt]; + for (unsigned i = 0; i < ShiftAmt; ++i) + Bits[i] = ValueBit(ValueBit::ConstZero); + } return std::make_pair(Interesting = true, &Bits); } @@ -1661,15 +1667,20 @@ class BitPermutationSelector { case ISD::SRL: case PPCISD::SRL: if (isa(V.getOperand(1))) { - unsigned ShiftAmt = V.getConstantOperandVal(1); + // srd takes lowest 7 bits, srw takes 6. + unsigned ShiftAmt = V.getConstantOperandVal(1) & ((NumBits << 1) - 1); const auto &LHSBits = *getValueBits(V.getOperand(0), NumBits).second; - for (unsigned i = 0; i < NumBits - ShiftAmt; ++i) - Bits[i] = LHSBits[i + ShiftAmt]; - - for (unsigned i = NumBits - ShiftAmt; i < NumBits; ++i) - Bits[i] = ValueBit(ValueBit::ConstZero); + if (ShiftAmt >= NumBits) { + for (unsigned i = 0; i < NumBits; ++i) + Bits[i] = ValueBit(ValueBit::ConstZero); + } else { + for (unsigned i = 0; i < NumBits - ShiftAmt; ++i) + Bits[i] = LHSBits[i + ShiftAmt]; + for (unsigned i = NumBits - ShiftAmt; i < NumBits; ++i) + Bits[i] = ValueBit(ValueBit::ConstZero); + } return std::make_pair(Interesting = true, &Bits); } diff --git a/llvm/test/CodeGen/PowerPC/pr59074.ll b/llvm/test/CodeGen/PowerPC/pr59074.ll new file mode 100644 index 000000000000..3e328c6ad9f0 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/pr59074.ll @@ -0,0 +1,132 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s --check-prefix=LE64 +; RUN: llc -mtriple=powerpcle-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s --check-prefix=LE32 +; RUN: llc -mtriple=powerpc64-ibm-aix -mcpu=pwr7 < %s | FileCheck %s --check-prefix=BE64 +; RUN: llc -mtriple=powerpc-ibm-aix -mcpu=pwr7 < %s | FileCheck %s --check-prefix=BE32 + +; To verify this doesn't crash due to array out of bound. +define void @pr59074(ptr %0) { +; LE64-LABEL: pr59074: +; LE64: # %bb.0: # %entry +; LE64-NEXT: lwz 6, 0(3) +; LE64-NEXT: li 7, 12 +; LE64-NEXT: ld 4, 16(3) +; LE64-NEXT: ld 5, 24(3) +; LE64-NEXT: addi 6, 6, -12 +; LE64-NEXT: std 4, 16(3) +; LE64-NEXT: std 5, 24(3) +; LE64-NEXT: srd 6, 7, 6 +; LE64-NEXT: li 7, 0 +; LE64-NEXT: std 7, 8(3) +; LE64-NEXT: std 6, 0(3) +; LE64-NEXT: blr +; +; LE32-LABEL: pr59074: +; LE32: # %bb.0: # %entry +; LE32-NEXT: stwu 1, -80(1) +; LE32-NEXT: .cfi_def_cfa_offset 80 +; LE32-NEXT: lwz 4, 0(3) +; LE32-NEXT: xxlxor 0, 0, 0 +; LE32-NEXT: li 5, 4 +; LE32-NEXT: addi 6, 1, 16 +; LE32-NEXT: li 7, 0 +; LE32-NEXT: li 8, 12 +; LE32-NEXT: xxswapd 0, 0 +; LE32-NEXT: addi 4, 4, -12 +; LE32-NEXT: rlwinm 9, 4, 29, 28, 31 +; LE32-NEXT: stxvd2x 0, 6, 5 +; LE32-NEXT: stw 7, 44(1) +; LE32-NEXT: stw 7, 40(1) +; LE32-NEXT: stw 7, 36(1) +; LE32-NEXT: stw 8, 16(1) +; LE32-NEXT: lwzux 5, 9, 6 +; LE32-NEXT: li 6, 7 +; LE32-NEXT: lwz 7, 8(9) +; LE32-NEXT: nand 6, 4, 6 +; LE32-NEXT: lwz 8, 4(9) +; LE32-NEXT: clrlwi 4, 4, 29 +; LE32-NEXT: lwz 9, 12(9) +; LE32-NEXT: clrlwi 6, 6, 27 +; LE32-NEXT: subfic 11, 4, 32 +; LE32-NEXT: srw 5, 5, 4 +; LE32-NEXT: slwi 10, 7, 1 +; LE32-NEXT: srw 7, 7, 4 +; LE32-NEXT: slw 6, 10, 6 +; LE32-NEXT: srw 10, 8, 4 +; LE32-NEXT: slw 8, 8, 11 +; LE32-NEXT: slw 11, 9, 11 +; LE32-NEXT: srw 4, 9, 4 +; LE32-NEXT: or 5, 8, 5 +; LE32-NEXT: or 7, 11, 7 +; LE32-NEXT: or 6, 10, 6 +; LE32-NEXT: stw 4, 12(3) +; LE32-NEXT: stw 7, 8(3) +; LE32-NEXT: stw 5, 0(3) +; LE32-NEXT: stw 6, 4(3) +; LE32-NEXT: addi 1, 1, 80 +; LE32-NEXT: blr +; +; BE64-LABEL: pr59074: +; BE64: # %bb.0: # %entry +; BE64-NEXT: lwz 6, 12(3) +; BE64-NEXT: li 7, 12 +; BE64-NEXT: ld 4, 24(3) +; BE64-NEXT: ld 5, 16(3) +; BE64-NEXT: addi 6, 6, -12 +; BE64-NEXT: std 4, 24(3) +; BE64-NEXT: std 5, 16(3) +; BE64-NEXT: srd 6, 7, 6 +; BE64-NEXT: li 7, 0 +; BE64-NEXT: std 7, 0(3) +; BE64-NEXT: std 6, 8(3) +; BE64-NEXT: blr +; +; BE32-LABEL: pr59074: +; BE32: # %bb.0: # %entry +; BE32-NEXT: lwz 4, 12(3) +; BE32-NEXT: xxlxor 0, 0, 0 +; BE32-NEXT: addi 5, 1, -64 +; BE32-NEXT: li 6, 12 +; BE32-NEXT: li 7, 0 +; BE32-NEXT: addi 8, 1, -48 +; BE32-NEXT: li 10, 7 +; BE32-NEXT: stxvw4x 0, 0, 5 +; BE32-NEXT: addi 4, 4, -12 +; BE32-NEXT: stw 6, -36(1) +; BE32-NEXT: stw 7, -40(1) +; BE32-NEXT: stw 7, -44(1) +; BE32-NEXT: rlwinm 9, 4, 29, 28, 31 +; BE32-NEXT: stw 7, -48(1) +; BE32-NEXT: sub 5, 8, 9 +; BE32-NEXT: nand 6, 4, 10 +; BE32-NEXT: clrlwi 4, 4, 29 +; BE32-NEXT: clrlwi 6, 6, 27 +; BE32-NEXT: lwz 7, 4(5) +; BE32-NEXT: lwz 8, 8(5) +; BE32-NEXT: lwz 9, 0(5) +; BE32-NEXT: lwz 5, 12(5) +; BE32-NEXT: slwi 10, 7, 1 +; BE32-NEXT: srw 11, 8, 4 +; BE32-NEXT: srw 7, 7, 4 +; BE32-NEXT: srw 5, 5, 4 +; BE32-NEXT: slw 6, 10, 6 +; BE32-NEXT: subfic 10, 4, 32 +; BE32-NEXT: srw 4, 9, 4 +; BE32-NEXT: slw 8, 8, 10 +; BE32-NEXT: slw 10, 9, 10 +; BE32-NEXT: or 6, 11, 6 +; BE32-NEXT: or 7, 10, 7 +; BE32-NEXT: or 5, 8, 5 +; BE32-NEXT: stw 4, 0(3) +; BE32-NEXT: stw 6, 8(3) +; BE32-NEXT: stw 5, 12(3) +; BE32-NEXT: stw 7, 4(3) +; BE32-NEXT: blr +entry: + %v1 = load <2 x i128>, <2 x i128>* %0 + %v2 = insertelement <2 x i128> %v1, i128 12, i32 0 + %v3 = sub <2 x i128> %v1, %v2 + %v4 = lshr <2 x i128> %v2, %v3 + store <2 x i128> %v4, <2 x i128>* %0 + ret void +} -- GitLab From 6dfb31adf6ca17d05c3832f1e43252a4c0c9f2af Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Tue, 6 Feb 2024 10:03:15 +0100 Subject: [PATCH 051/266] [clang][Interp][NFC] Simplify test case By checking using verify={ref,expected},both. --- clang/test/AST/Interp/literals.cpp | 382 ++++++++++------------------- 1 file changed, 129 insertions(+), 253 deletions(-) diff --git a/clang/test/AST/Interp/literals.cpp b/clang/test/AST/Interp/literals.cpp index 0031e577580a..c2bc5338ea92 100644 --- a/clang/test/AST/Interp/literals.cpp +++ b/clang/test/AST/Interp/literals.cpp @@ -1,7 +1,7 @@ -// RUN: %clang_cc1 -fexperimental-new-constant-interpreter -Wno-vla -fms-extensions -std=c++11 -verify %s -// RUN: %clang_cc1 -fexperimental-new-constant-interpreter -Wno-vla -fms-extensions -std=c++20 -verify %s -// RUN: %clang_cc1 -std=c++11 -fms-extensions -Wno-vla -verify=ref %s -// RUN: %clang_cc1 -std=c++20 -fms-extensions -Wno-vla -verify=ref %s +// RUN: %clang_cc1 -fexperimental-new-constant-interpreter -Wno-vla -fms-extensions -std=c++11 -verify=expected,both %s +// RUN: %clang_cc1 -fexperimental-new-constant-interpreter -Wno-vla -fms-extensions -std=c++20 -verify=expected,both %s +// RUN: %clang_cc1 -std=c++11 -fms-extensions -Wno-vla -verify=ref,both %s +// RUN: %clang_cc1 -std=c++20 -fms-extensions -Wno-vla -verify=ref,both %s #define INT_MIN (~__INT_MAX__) #define INT_MAX __INT_MAX__ @@ -11,21 +11,19 @@ typedef __PTRDIFF_TYPE__ ptrdiff_t; static_assert(true, ""); -static_assert(false, ""); // expected-error{{failed}} ref-error{{failed}} +static_assert(false, ""); // both-error{{failed}} static_assert(nullptr == nullptr, ""); static_assert(__null == __null, ""); static_assert(1 == 1, ""); -static_assert(1 == 3, ""); // expected-error{{failed}} ref-error{{failed}} +static_assert(1 == 3, ""); // both-error{{failed}} constexpr void* v = nullptr; static_assert(__null == v, ""); constexpr int number = 10; static_assert(number == 10, ""); -static_assert(number != 10, ""); // expected-error{{failed}} \ - // ref-error{{failed}} \ - // expected-note{{evaluates to}} \ - // ref-note{{evaluates to}} +static_assert(number != 10, ""); // both-error{{failed}} \ + // both-note{{evaluates to}} static_assert(__objc_yes, ""); static_assert(!__objc_no, ""); @@ -38,22 +36,14 @@ static_assert(one == 1, ""); constexpr bool b2 = bool(); static_assert(!b2, ""); -constexpr int Failed1 = 1 / 0; // expected-error {{must be initialized by a constant expression}} \ - // expected-note {{division by zero}} \ - // expected-note {{declared here}} \ - // ref-error {{must be initialized by a constant expression}} \ - // ref-note {{division by zero}} \ - // ref-note {{declared here}} -constexpr int Failed2 = Failed1 + 1; // expected-error {{must be initialized by a constant expression}} \ - // expected-note {{declared here}} \ - // expected-note {{initializer of 'Failed1' is not a constant expression}} \ - // ref-error {{must be initialized by a constant expression}} \ - // ref-note {{declared here}} \ - // ref-note {{initializer of 'Failed1' is not a constant expression}} -static_assert(Failed2 == 0, ""); // expected-error {{not an integral constant expression}} \ - // expected-note {{initializer of 'Failed2' is not a constant expression}} \ - // ref-error {{not an integral constant expression}} \ - // ref-note {{initializer of 'Failed2' is not a constant expression}} +constexpr int Failed1 = 1 / 0; // both-error {{must be initialized by a constant expression}} \ + // both-note {{division by zero}} \ + // both-note {{declared here}} +constexpr int Failed2 = Failed1 + 1; // both-error {{must be initialized by a constant expression}} \ + // both-note {{declared here}} \ + // both-note {{initializer of 'Failed1' is not a constant expression}} +static_assert(Failed2 == 0, ""); // both-error {{not an integral constant expression}} \ + // both-note {{initializer of 'Failed2' is not a constant expression}} namespace ScalarTypes { constexpr int ScalarInitInt = int(); @@ -112,10 +102,8 @@ namespace IntegralCasts { static_assert(!nu, ""); }; -constexpr int UninitI; // expected-error {{must be initialized by a constant expression}} \ - // ref-error {{must be initialized by a constant expression}} -constexpr int *UninitPtr; // expected-error {{must be initialized by a constant expression}} \ - // ref-error {{must be initialized by a constant expression}} +constexpr int UninitI; // both-error {{must be initialized by a constant expression}} +constexpr int *UninitPtr; // both-error {{must be initialized by a constant expression}} constexpr bool getTrue() { return true; } constexpr bool getFalse() { return false; } @@ -134,7 +122,7 @@ static_assert(false == 0, ""); static_assert(!5 == false, ""); static_assert(!0, ""); static_assert(-true, ""); -static_assert(-false, ""); //expected-error{{failed}} ref-error{{failed}} +static_assert(-false, ""); //both-error{{failed}} static_assert(~0 == -1, ""); static_assert(~1 == -2, ""); @@ -143,10 +131,8 @@ static_assert(~255 == -256, ""); static_assert(~INT_MIN == INT_MAX, ""); static_assert(~INT_MAX == INT_MIN, ""); -static_assert(-(1 << 31), ""); // expected-error {{not an integral constant expression}} \ - // expected-note {{outside the range of representable values}} \ - // ref-error {{not an integral constant expression}} \ - // ref-note {{outside the range of representable values}} \ +static_assert(-(1 << 31), ""); // both-error {{not an integral constant expression}} \ + // both-note {{outside the range of representable values}} namespace PrimitiveEmptyInitList { constexpr int a = {}; @@ -199,10 +185,8 @@ namespace PointerComparison { constexpr void *pv = (void*)&s.a; constexpr void *qv = (void*)&s.b; constexpr bool v1 = null < (int*)0; - constexpr bool v2 = null < pv; // expected-error {{must be initialized by a constant expression}} \ - // expected-note {{comparison between 'nullptr' and '&s.a' has unspecified value}} \ - // ref-error {{must be initialized by a constant expression}} \ - // ref-note {{comparison between 'nullptr' and '&s.a' has unspecified value}} \ + constexpr bool v2 = null < pv; // both-error {{must be initialized by a constant expression}} \ + // both-note {{comparison between 'nullptr' and '&s.a' has unspecified value}} constexpr bool v3 = null == pv; // ok constexpr bool v4 = qv == pv; // ok @@ -213,10 +197,8 @@ namespace PointerComparison { // ref-note {{unequal pointers to void}} constexpr bool v8 = qv > (void*)&s.a; // ref-error {{constant expression}} \ // ref-note {{unequal pointers to void}} - constexpr bool v6 = qv > null; // expected-error {{must be initialized by a constant expression}} \ - // expected-note {{comparison between '&s.b' and 'nullptr' has unspecified value}} \ - // ref-error {{must be initialized by a constant expression}} \ - // ref-note {{comparison between '&s.b' and 'nullptr' has unspecified value}} + constexpr bool v6 = qv > null; // both-error {{must be initialized by a constant expression}} \ + // both-note {{comparison between '&s.b' and 'nullptr' has unspecified value}} constexpr bool v7 = qv <= (void*)&s.b; // ok @@ -229,10 +211,8 @@ namespace PointerComparison { constexpr long m3 = (&m3 + 1) - (&m3); static_assert(m3 == 1, ""); - constexpr long m4 = &m4 + 2 - &m4; // ref-error {{must be initialized by a constant expression}} \ - // ref-note {{cannot refer to element 2 of non-array object}} \ - // expected-error {{must be initialized by a constant expression}} \ - // expected-note {{cannot refer to element 2 of non-array object}} + constexpr long m4 = &m4 + 2 - &m4; // both-error {{must be initialized by a constant expression}} \ + // both-note {{cannot refer to element 2 of non-array object}} } namespace SizeOf { @@ -257,11 +237,9 @@ namespace SizeOf { static_assert(sizeof(bool) == 1, ""); static_assert(sizeof(char) == 1, ""); - constexpr int F = sizeof(void); // expected-error{{incomplete type 'void'}} \ - // ref-error{{incomplete type 'void'}} + constexpr int F = sizeof(void); // both-error{{incomplete type 'void'}} - constexpr int F2 = sizeof(gimme); // expected-error{{to a function type}} \ - // ref-error{{to a function type}} + constexpr int F2 = sizeof(gimme); // both-error{{to a function type}} struct S { @@ -273,22 +251,19 @@ namespace SizeOf { void func() { int n = 12; - constexpr int oofda = sizeof(int[n++]); // expected-error {{must be initialized by a constant expression}} \ - // ref-error {{must be initialized by a constant expression}} + constexpr int oofda = sizeof(int[n++]); // both-error {{must be initialized by a constant expression}} } #if __cplusplus >= 201402L constexpr int IgnoredRejected() { // ref-error {{never produces a constant expression}} int n = 0; - sizeof(int[n++]); // expected-warning {{expression result unused}} \ - // ref-warning {{expression result unused}} \ + sizeof(int[n++]); // both-warning {{expression result unused}} \ // ref-note 2{{subexpression not valid in a constant expression}} return n; } /// FIXME: This is rejected because the parameter so sizeof() is not constant. /// produce a proper diagnostic. - static_assert(IgnoredRejected() == 0, ""); // expected-error {{not an integral constant expression}} \ - // ref-error {{not an integral constant expression}} \ + static_assert(IgnoredRejected() == 0, ""); // both-error {{not an integral constant expression}} \ // ref-note {{in call to 'IgnoredRejected()'}} #endif @@ -317,32 +292,22 @@ namespace rem { static_assert(-3 % -4 == -3, ""); constexpr int zero() { return 0; } - static_assert(10 % zero() == 20, ""); // ref-error {{not an integral constant expression}} \ - // ref-note {{division by zero}} \ - // expected-error {{not an integral constant expression}} \ - // expected-note {{division by zero}} - + static_assert(10 % zero() == 20, ""); // both-error {{not an integral constant expression}} \ + // both-note {{division by zero}} static_assert(true % true == 0, ""); static_assert(false % true == 0, ""); - static_assert(true % false == 10, ""); // ref-error {{not an integral constant expression}} \ - // ref-note {{division by zero}} \ - // expected-error {{not an integral constant expression}} \ - // expected-note {{division by zero}} - constexpr int x = INT_MIN % - 1; // ref-error {{must be initialized by a constant expression}} \ - // ref-note {{value 2147483648 is outside the range}} \ - // expected-error {{must be initialized by a constant expression}} \ - // expected-note {{value 2147483648 is outside the range}} \ - + static_assert(true % false == 10, ""); // both-error {{not an integral constant expression}} \ + // both-note {{division by zero}} + constexpr int x = INT_MIN % - 1; // both-error {{must be initialized by a constant expression}} \ + // both-note {{value 2147483648 is outside the range}} }; namespace div { constexpr int zero() { return 0; } static_assert(12 / 3 == 4, ""); - static_assert(12 / zero() == 12, ""); // ref-error {{not an integral constant expression}} \ - // ref-note {{division by zero}} \ - // expected-error {{not an integral constant expression}} \ - // expected-note {{division by zero}} + static_assert(12 / zero() == 12, ""); // both-error {{not an integral constant expression}} \ + // both-note {{division by zero}} static_assert(12 / -3 == -4, ""); static_assert(-12 / 3 == -4, ""); @@ -351,11 +316,8 @@ namespace div { constexpr long unsigned RHS = 3; static_assert(LHS / RHS == 4, ""); - constexpr int x = INT_MIN / - 1; // ref-error {{must be initialized by a constant expression}} \ - // ref-note {{value 2147483648 is outside the range}} \ - // expected-error {{must be initialized by a constant expression}} \ - // expected-note {{value 2147483648 is outside the range}} \ - + constexpr int x = INT_MIN / - 1; // both-error {{must be initialized by a constant expression}} \ + // both-note {{value 2147483648 is outside the range}} }; namespace cond { @@ -446,8 +408,7 @@ namespace bitXor { #if __cplusplus >= 201402L constexpr bool IgnoredUnary() { bool bo = true; - !bo; // expected-warning {{expression result unused}} \ - // ref-warning {{expression result unused}} + !bo; // both-warning {{expression result unused}} return bo; } static_assert(IgnoredUnary(), ""); @@ -482,15 +443,11 @@ namespace strings { #pragma clang diagnostic ignored "-Wmultichar" constexpr int mc = 'abc'; static_assert(mc == 'abc', ""); - __WCHAR_TYPE__ wm = L'abc'; // ref-error{{wide character literals may not contain multiple characters}} \ - // expected-error{{wide character literals may not contain multiple characters}} - __WCHAR_TYPE__ wu = u'abc'; // ref-error{{Unicode character literals may not contain multiple characters}} \ - // expected-error{{Unicode character literals may not contain multiple characters}} - __WCHAR_TYPE__ wU = U'abc'; // ref-error{{Unicode character literals may not contain multiple characters}} \ - // expected-error{{Unicode character literals may not contain multiple characters}} + __WCHAR_TYPE__ wm = L'abc'; // both-error{{wide character literals may not contain multiple characters}} + __WCHAR_TYPE__ wu = u'abc'; // both-error{{Unicode character literals may not contain multiple characters}} + __WCHAR_TYPE__ wU = U'abc'; // both-error{{Unicode character literals may not contain multiple characters}} #if __cplusplus > 201103L - __WCHAR_TYPE__ wu8 = u8'abc'; // ref-error{{Unicode character literals may not contain multiple characters}} \ - // expected-error{{Unicode character literals may not contain multiple characters}} + __WCHAR_TYPE__ wu8 = u8'abc'; // both-error{{Unicode character literals may not contain multiple characters}} #endif #pragma clang diagnostic pop @@ -507,26 +464,19 @@ namespace strings { static_assert(foo2[3] == '\0', ""); static_assert(foo2[6] == 'f', ""); static_assert(foo2[7] == '\0', ""); - static_assert(foo2[8] == '\0', ""); // expected-error {{not an integral constant expression}} \ - // expected-note {{read of dereferenced one-past-the-end pointer}} \ - // ref-error {{not an integral constant expression}} \ - // ref-note {{read of dereferenced one-past-the-end pointer}} + static_assert(foo2[8] == '\0', ""); // both-error {{not an integral constant expression}} \ + // both-note {{read of dereferenced one-past-the-end pointer}} constexpr char foo3[4] = "abc"; static_assert(foo3[3] == '\0', ""); - static_assert(foo3[4] == '\0', ""); // expected-error {{not an integral constant expression}} \ - // expected-note {{read of dereferenced one-past-the-end pointer}} \ - // ref-error {{not an integral constant expression}} \ - // ref-note {{read of dereferenced one-past-the-end pointer}} + static_assert(foo3[4] == '\0', ""); // both-error {{not an integral constant expression}} \ + // both-note {{read of dereferenced one-past-the-end pointer}} - constexpr char foo4[2] = "abcd"; // expected-error {{initializer-string for char array is too long}} \ - // ref-error {{initializer-string for char array is too long}} + constexpr char foo4[2] = "abcd"; // both-error {{initializer-string for char array is too long}} static_assert(foo4[0] == 'a', ""); static_assert(foo4[1] == 'b', ""); - static_assert(foo4[2] == '\0', ""); // expected-error {{not an integral constant expression}} \ - // expected-note {{read of dereferenced one-past-the-end pointer}} \ - // ref-error {{not an integral constant expression}} \ - // ref-note {{read of dereferenced one-past-the-end pointer}} + static_assert(foo4[2] == '\0', ""); // both-error {{not an integral constant expression}} \ + // both-note {{read of dereferenced one-past-the-end pointer}} constexpr char foo5[12] = "abc\xff"; #if defined(__CHAR_UNSIGNED__) || __CHAR_BIT__ > 8 @@ -574,16 +524,13 @@ namespace IncDec { constexpr int three() { int a = 0; - return ++a + ++a; // expected-warning {{multiple unsequenced modifications to 'a'}} \ - // ref-warning {{multiple unsequenced modifications to 'a'}} \ - + return ++a + ++a; // both-warning {{multiple unsequenced modifications to 'a'}} } static_assert(three() == 3, ""); constexpr bool incBool() { bool b = false; - return ++b; // expected-error {{ISO C++17 does not allow incrementing expression of type bool}} \ - // ref-error {{ISO C++17 does not allow incrementing expression of type bool}} + return ++b; // both-error {{ISO C++17 does not allow incrementing expression of type bool}} } static_assert(incBool(), ""); @@ -611,73 +558,54 @@ namespace IncDec { } return 1; } - static_assert(uninit(), ""); // ref-error {{not an integral constant expression}} \ + static_assert(uninit(), ""); // both-error {{not an integral constant expression}} \ // ref-note {{in call to 'uninit()'}} \ - // expected-error {{not an integral constant expression}} \ // expected-note {{in call to 'uninit()'}} - static_assert(uninit(), ""); // ref-error {{not an integral constant expression}} \ + static_assert(uninit(), ""); // both-error {{not an integral constant expression}} \ // ref-note {{in call to 'uninit()'}} \ - // expected-error {{not an integral constant expression}} \ // expected-note {{in call to 'uninit()'}} - static_assert(uninit(), ""); // ref-error {{not an integral constant expression}} \ + static_assert(uninit(), ""); // both-error {{not an integral constant expression}} \ // ref-note {{in call to 'uninit()'}} \ - // expected-error {{not an integral constant expression}} \ // expected-note {{in call to 'uninit()'}} - static_assert(uninit(), ""); // ref-error {{not an integral constant expression}} \ + static_assert(uninit(), ""); // both-error {{not an integral constant expression}} \ // ref-note {{in call to 'uninit()'}} \ - // expected-error {{not an integral constant expression}} \ // expected-note {{in call to 'uninit()'}} - static_assert(uninit(), ""); // ref-error {{not an integral constant expression}} \ + static_assert(uninit(), ""); // both-error {{not an integral constant expression}} \ // ref-note {{in call to 'uninit()'}} \ - // expected-error {{not an integral constant expression}} \ // expected-note {{in call to 'uninit()'}} - static_assert(uninit(), ""); // ref-error {{not an integral constant expression}} \ + static_assert(uninit(), ""); // both-error {{not an integral constant expression}} \ // ref-note {{in call to 'uninit()'}} \ - // expected-error {{not an integral constant expression}} \ // expected-note {{in call to 'uninit()'}} - static_assert(uninit(), ""); // ref-error {{not an integral constant expression}} \ + static_assert(uninit(), ""); // both-error {{not an integral constant expression}} \ // ref-note {{in call to 'uninit()'}} \ - // expected-error {{not an integral constant expression}} \ // expected-note {{in call to 'uninit()'}} - static_assert(uninit(), ""); // ref-error {{not an integral constant expression}} \ + static_assert(uninit(), ""); // both-error {{not an integral constant expression}} \ // ref-note {{in call to 'uninit()'}} \ - // expected-error {{not an integral constant expression}} \ // expected-note {{in call to 'uninit()'}} - static_assert(uninit(), ""); // ref-error {{not an integral constant expression}} \ + static_assert(uninit(), ""); // both-error {{not an integral constant expression}} \ // ref-note {{in call to 'uninit()'}} \ - // expected-error {{not an integral constant expression}} \ // expected-note {{in call to 'uninit()'}} - static_assert(uninit(), ""); // ref-error {{not an integral constant expression}} \ + static_assert(uninit(), ""); // both-error {{not an integral constant expression}} \ // ref-note {{in call to 'uninit()'}} \ - // expected-error {{not an integral constant expression}} \ // expected-note {{in call to 'uninit()'}} - constexpr int OverFlow() { // ref-error {{never produces a constant expression}} \ - // expected-error {{never produces a constant expression}} + constexpr int OverFlow() { // both-error {{never produces a constant expression}} int a = INT_MAX; - ++a; // ref-note 2{{is outside the range}} \ - // expected-note 2{{is outside the range}} + ++a; // both-note 2{{is outside the range}} return -1; } - static_assert(OverFlow() == -1, ""); // expected-error {{not an integral constant expression}} \ - // expected-note {{in call to 'OverFlow()'}} \ - // ref-error {{not an integral constant expression}} \ - // ref-note {{in call to 'OverFlow()'}} - + static_assert(OverFlow() == -1, ""); // both-error {{not an integral constant expression}} \ + // both-note {{in call to 'OverFlow()'}} - constexpr int UnderFlow() { // ref-error {{never produces a constant expression}} \ - // expected-error {{never produces a constant expression}} + constexpr int UnderFlow() { // both-error {{never produces a constant expression}} int a = INT_MIN; - --a; // ref-note 2{{is outside the range}} \ - // expected-note 2{{is outside the range}} + --a; // both-note 2{{is outside the range}} return -1; } - static_assert(UnderFlow() == -1, ""); // expected-error {{not an integral constant expression}} \ - // expected-note {{in call to 'UnderFlow()'}} \ - // ref-error {{not an integral constant expression}} \ - // ref-note {{in call to 'UnderFlow()'}} + static_assert(UnderFlow() == -1, ""); // both-error {{not an integral constant expression}} \ + // both-note {{in call to 'UnderFlow()'}} constexpr int getTwo() { int i = 1; @@ -691,26 +619,20 @@ namespace IncDec { static_assert(sub(7) == 5, ""); constexpr int add(int a, int b) { - a += b; // expected-note {{is outside the range of representable values}} \ - // ref-note {{is outside the range of representable values}} + a += b; // both-note {{is outside the range of representable values}} return a; } static_assert(add(1, 2) == 3, ""); - static_assert(add(INT_MAX, 1) == 0, ""); // expected-error {{not an integral constant expression}} \ - // expected-note {{in call to 'add}} \ - // ref-error {{not an integral constant expression}} \ - // ref-note {{in call to 'add}} + static_assert(add(INT_MAX, 1) == 0, ""); // both-error {{not an integral constant expression}} \ + // both-note {{in call to 'add}} constexpr int sub(int a, int b) { - a -= b; // expected-note {{is outside the range of representable values}} \ - // ref-note {{is outside the range of representable values}} + a -= b; // both-note {{is outside the range of representable values}} return a; } static_assert(sub(10, 20) == -10, ""); - static_assert(sub(INT_MIN, 1) == 0, ""); // expected-error {{not an integral constant expression}} \ - // expected-note {{in call to 'sub}} \ - // ref-error {{not an integral constant expression}} \ - // ref-note {{in call to 'sub}} + static_assert(sub(INT_MIN, 1) == 0, ""); // both-error {{not an integral constant expression}} \ + // both-note {{in call to 'sub}} constexpr int subAll(int a) { return (a -= a); @@ -792,26 +714,18 @@ namespace IncDec { constexpr int IntRem(int a, int b) { int r; r = a; - r %= b; // expected-note {{division by zero}} \ - // ref-note {{division by zero}} \ - // expected-note {{outside the range of representable values}} \ - // ref-note {{outside the range of representable values}} + r %= b; // both-note {{division by zero}} \ + // both-note {{outside the range of representable values}} return r; } static_assert(IntRem(2, 2) == 0, ""); static_assert(IntRem(2, 1) == 0, ""); static_assert(IntRem(9, 7) == 2, ""); - static_assert(IntRem(5, 0) == 0, ""); // expected-error {{not an integral constant expression}} \ - // expected-note {{in call to 'IntRem(5, 0)'}} \ - // ref-error {{not an integral constant expression}} \ - // ref-note {{in call to 'IntRem(5, 0)'}} - - static_assert(IntRem(INT_MIN, -1) == 0, ""); // expected-error {{not an integral constant expression}} \ - // expected-note {{in call to 'IntRem}} \ - // ref-error {{not an integral constant expression}} \ - // ref-note {{in call to 'IntRem}} - + static_assert(IntRem(5, 0) == 0, ""); // both-error {{not an integral constant expression}} \ + // both-note {{in call to 'IntRem(5, 0)'}} + static_assert(IntRem(INT_MIN, -1) == 0, ""); // both-error {{not an integral constant expression}} \ + // both-note {{in call to 'IntRem}} constexpr bool BoolDiv(bool b1, bool b2) { bool a; @@ -825,25 +739,19 @@ namespace IncDec { constexpr int IntDiv(int a, int b) { int r; r = a; - r /= b; // expected-note {{division by zero}} \ - // ref-note {{division by zero}} \ - // expected-note {{outside the range of representable values}} \ - // ref-note {{outside the range of representable values}} + r /= b; // both-note {{division by zero}} \ + // both-note {{outside the range of representable values}} return r; } static_assert(IntDiv(2, 2) == 1, ""); static_assert(IntDiv(12, 20) == 0, ""); static_assert(IntDiv(2, 1) == 2, ""); static_assert(IntDiv(9, 7) == 1, ""); - static_assert(IntDiv(5, 0) == 0, ""); // expected-error {{not an integral constant expression}} \ - // expected-note {{in call to 'IntDiv(5, 0)'}} \ - // ref-error {{not an integral constant expression}} \ - // ref-note {{in call to 'IntDiv(5, 0)'}} + static_assert(IntDiv(5, 0) == 0, ""); // both-error {{not an integral constant expression}} \ + // both-note {{in call to 'IntDiv(5, 0)'}} - static_assert(IntDiv(INT_MIN, -1) == 0, ""); // expected-error {{not an integral constant expression}} \ - // expected-note {{in call to 'IntDiv}} \ - // ref-error {{not an integral constant expression}} \ - // ref-note {{in call to 'IntDiv}} + static_assert(IntDiv(INT_MIN, -1) == 0, ""); // both-error {{not an integral constant expression}} \ + // both-note {{in call to 'IntDiv}} constexpr bool BoolMul(bool b1, bool b2) { bool a; @@ -859,18 +767,15 @@ namespace IncDec { constexpr int IntMul(int a, int b) { int r; r = a; - r *= b; // expected-note {{is outside the range of representable values of type 'int'}} \ - // ref-note {{is outside the range of representable values of type 'int'}} + r *= b; // both-note {{is outside the range of representable values of type 'int'}} return r; } static_assert(IntMul(2, 2) == 4, ""); static_assert(IntMul(12, 20) == 240, ""); static_assert(IntMul(2, 1) == 2, ""); static_assert(IntMul(9, 7) == 63, ""); - static_assert(IntMul(INT_MAX, 2) == 0, ""); // expected-error {{not an integral constant expression}} \ - // expected-note {{in call to 'IntMul}} \ - // ref-error {{not an integral constant expression}} \ - // ref-note {{in call to 'IntMul}} + static_assert(IntMul(INT_MAX, 2) == 0, ""); // both-error {{not an integral constant expression}} \ + // both-note {{in call to 'IntMul}} constexpr int arr[] = {1,2,3}; constexpr int ptrInc1() { const int *p = arr; @@ -885,11 +790,9 @@ namespace IncDec { } static_assert(ptrInc2() == 2, ""); - constexpr int ptrInc3() { // expected-error {{never produces a constant expression}} \ - // ref-error {{never produces a constant expression}} + constexpr int ptrInc3() { // both-error {{never produces a constant expression}} const int *p = arr; - p += 12; // expected-note {{cannot refer to element 12 of array of 3 elements}} \ - // ref-note {{cannot refer to element 12 of array of 3 elements}} + p += 12; // both-note {{cannot refer to element 12 of array of 3 elements}} return *p; } @@ -901,11 +804,9 @@ namespace IncDec { } static_assert(ptrIncDec1() == 2, ""); - constexpr int ptrDec1() { // expected-error {{never produces a constant expression}} \ - // ref-error {{never produces a constant expression}} + constexpr int ptrDec1() { // both-error {{never produces a constant expression}} const int *p = arr; - p -= 1; // expected-note {{cannot refer to element -1 of array of 3 elements}} \ - // ref-note {{cannot refer to element -1 of array of 3 elements}} + p -= 1; // both-note {{cannot refer to element -1 of array of 3 elements}} return *p; } @@ -1133,10 +1034,8 @@ namespace PredefinedExprs { } constexpr char heh(unsigned index) { - __FUNCTION__; // ref-warning {{result unused}} \ - // expected-warning {{result unused}} - __extension__ __FUNCTION__; // ref-warning {{result unused}} \ - // expected-warning {{result unused}} + __FUNCTION__; // both-warning {{result unused}} + __extension__ __FUNCTION__; // both-warning {{result unused}} return __FUNCTION__[index]; } static_assert(heh(0) == 'h', ""); @@ -1158,8 +1057,7 @@ namespace NE { #if __cplusplus > 201402L constexpr int a() { int b = 0; - (void)noexcept(++b); // expected-warning {{expression with side effects has no effect in an unevaluated context}} \ - // ref-warning {{expression with side effects has no effect in an unevaluated context}} + (void)noexcept(++b); // both-warning {{expression with side effects has no effect in an unevaluated context}} return b; } @@ -1170,60 +1068,38 @@ namespace NE { namespace PointerCasts { constexpr int M = 10; constexpr const int *P = &M; - constexpr intptr_t A = (intptr_t)P; // ref-error {{must be initialized by a constant expression}} \ - // ref-note {{cast that performs the conversions of a reinterpret_cast}} \ - // expected-error {{must be initialized by a constant expression}} \ - // expected-note {{cast that performs the conversions of a reinterpret_cast}} + constexpr intptr_t A = (intptr_t)P; // both-error {{must be initialized by a constant expression}} \ + // both-note {{cast that performs the conversions of a reinterpret_cast}} - int array[(intptr_t)(char*)0]; // ref-warning {{variable length array folded to constant array}} \ - // expected-warning {{variable length array folded to constant array}} + int array[(intptr_t)(char*)0]; // both-warning {{variable length array folded to constant array}} } namespace InvalidDeclRefs { - bool b00; // ref-note {{declared here}} \ - // expected-note {{declared here}} - static_assert(b00, ""); // ref-error {{not an integral constant expression}} \ - // ref-note {{read of non-const variable}} \ - // expected-error {{not an integral constant expression}} \ - // expected-note {{read of non-const variable}} - - float b01; // ref-note {{declared here}} \ - // expected-note {{declared here}} - static_assert(b01, ""); // ref-error {{not an integral constant expression}} \ - // ref-note {{read of non-constexpr variable}} \ - // expected-error {{not an integral constant expression}} \ - // expected-note {{read of non-constexpr variable}} - - extern const int b02; // ref-note {{declared here}} \ - // expected-note {{declared here}} - static_assert(b02, ""); // ref-error {{not an integral constant expression}} \ - // ref-note {{initializer of 'b02' is unknown}} \ - // expected-error {{not an integral constant expression}} \ - // expected-note {{initializer of 'b02' is unknown}} - - int b03 = 3; // ref-note {{declared here}} \ - // expected-note {{declared here}} - static_assert(b03, ""); // ref-error {{not an integral constant expression}} \ - // ref-note {{read of non-const variable}} \ - // expected-error {{not an integral constant expression}} \ - // expected-note {{read of non-const variable}} + bool b00; // both-note {{declared here}} + static_assert(b00, ""); // both-error {{not an integral constant expression}} \ + // both-note {{read of non-const variable}} + + float b01; // both-note {{declared here}} + static_assert(b01, ""); // both-error {{not an integral constant expression}} \ + // both-note {{read of non-constexpr variable}} + + extern const int b02; // both-note {{declared here}} + static_assert(b02, ""); // both-error {{not an integral constant expression}} \ + // both-note {{initializer of 'b02' is unknown}} + + int b03 = 3; // both-note {{declared here}} + static_assert(b03, ""); // both-error {{not an integral constant expression}} \ + // both-note {{read of non-const variable}} } namespace NonConstReads { - void *p = nullptr; // ref-note {{declared here}} \ - // expected-note {{declared here}} - static_assert(!p, ""); // ref-error {{not an integral constant expression}} \ - // ref-note {{read of non-constexpr variable 'p'}} \ - // expected-error {{not an integral constant expression}} \ - // expected-note {{read of non-constexpr variable 'p'}} - - int arr[!p]; // ref-error {{variable length array}} \ - // expected-error {{variable length array}} - - int z; // ref-note {{declared here}} \ - // expected-note {{declared here}} - static_assert(z == 0, ""); // ref-error {{not an integral constant expression}} \ - // ref-note {{read of non-const variable 'z'}} \ - // expected-error {{not an integral constant expression}} \ - // expected-note {{read of non-const variable 'z'}} + void *p = nullptr; // both-note {{declared here}} + static_assert(!p, ""); // both-error {{not an integral constant expression}} \ + // both-note {{read of non-constexpr variable 'p'}} + + int arr[!p]; // both-error {{variable length array}} + + int z; // both-note {{declared here}} + static_assert(z == 0, ""); // both-error {{not an integral constant expression}} \ + // both-note {{read of non-const variable 'z'}} } -- GitLab From 3d186a77cf1aa979014a6443cb423a633c167d9f Mon Sep 17 00:00:00 2001 From: Sander de Smalen Date: Tue, 6 Feb 2024 10:42:44 +0000 Subject: [PATCH 052/266] [Clang][AArch64] Fix some target guards and remove +sve from tests. (#80681) The TargetGuard fields for 'svldr[_vnum]_za' and 'svstr[_vnum]_za' were incorrectly set to `+sve` instead of `+sme`. This means that compiling code that uses these intrinsics requires compiling for both `+sve` as well as `+sme`. This PR also fixes the target guards for the `svadd` and `svsub` builtins that are enabled under `+sme2,+sme-i16i64` and `+sme2,+sme-f64f64`, as it initially did the following: ``` let TargetGuard = "+sme2" in { let TargetGuard = "+sme-i16i64" in { // Builtins defined here will be predicated only by // '+sme-i16i64', and not '+sme2,+sme-i16i64'. } } ``` This PR also removes `-target-feature +sve` from all the SME tests, to ensure that the SME features are sufficient to build the tests. --- clang/include/clang/Basic/arm_sme.td | 28 +++++++++++-------- .../aarch64-sme-intrinsics/acle_sme_add-i32.c | 10 +++---- .../aarch64-sme-intrinsics/acle_sme_add-i64.c | 10 +++---- .../aarch64-sme-intrinsics/acle_sme_cnt.c | 6 ++-- .../aarch64-sme-intrinsics/acle_sme_ld1.c | 6 ++-- .../acle_sme_ld1_vnum.c | 6 ++-- .../aarch64-sme-intrinsics/acle_sme_ldr.c | 6 ++-- .../acle_sme_mopa-za32.c | 10 +++---- .../acle_sme_mopa-za64.c | 10 +++---- .../acle_sme_mops-za32.c | 10 +++---- .../acle_sme_mops-za64.c | 10 +++---- .../aarch64-sme-intrinsics/acle_sme_read.c | 10 +++---- .../aarch64-sme-intrinsics/acle_sme_st1.c | 6 ++-- .../acle_sme_st1_vnum.c | 6 ++-- .../aarch64-sme-intrinsics/acle_sme_str.c | 6 ++-- .../aarch64-sme-intrinsics/acle_sme_write.c | 10 +++---- .../aarch64-sme-intrinsics/acle_sme_zero.c | 6 ++-- .../aarch64-sme2-intrinsics/acle_sme2_add.c | 10 +++---- .../aarch64-sme2-intrinsics/acle_sme2_bmop.c | 10 +++---- .../aarch64-sme2-intrinsics/acle_sme2_clamp.c | 20 ++++++------- .../aarch64-sme2-intrinsics/acle_sme2_cvt.c | 10 +++---- .../aarch64-sme2-intrinsics/acle_sme2_cvtn.c | 10 +++---- .../aarch64-sme2-intrinsics/acle_sme2_frint.c | 10 +++---- .../acle_sme2_luti2_lane_zt.c | 6 ++-- .../acle_sme2_luti2_lane_zt_x2.c | 6 ++-- .../acle_sme2_luti2_lane_zt_x4.c | 6 ++-- .../acle_sme2_luti4_lane_zt.c | 6 ++-- .../acle_sme2_luti4_lane_zt_x2.c | 6 ++-- .../acle_sme2_luti4_lane_zt_x4.c | 6 ++-- .../aarch64-sme2-intrinsics/acle_sme2_max.c | 10 +++---- .../aarch64-sme2-intrinsics/acle_sme2_maxnm.c | 10 +++---- .../aarch64-sme2-intrinsics/acle_sme2_min.c | 10 +++---- .../aarch64-sme2-intrinsics/acle_sme2_minnm.c | 10 +++---- .../aarch64-sme2-intrinsics/acle_sme2_mop.c | 10 +++---- .../aarch64-sme2-intrinsics/acle_sme2_read.c | 6 ++-- .../acle_sme2_reinterpret_svcount_svbool.c | 8 +++--- .../aarch64-sme2-intrinsics/acle_sme2_sub.c | 10 +++---- .../acle_sme2_unpkx2.c | 12 ++++---- .../acle_sme2_unpkx4.c | 12 ++++---- .../acle_sme2_vector_add.c | 10 +++---- .../acle_sme2_vector_qrshr.c | 10 +++---- .../acle_sme2_vector_rshl.c | 10 +++---- .../acle_sme2_vector_selx2.c | 10 +++---- .../acle_sme2_vector_selx4.c | 10 +++---- .../acle_sme2_vector_uzpx2.c | 10 +++---- .../acle_sme2_vector_uzpx4.c | 10 +++---- .../acle_sme2_vector_zipx2.c | 10 +++---- .../acle_sme2_vector_zipx4.c | 10 +++---- .../aarch64-sme2-intrinsics/acle_sme2_write.c | 10 +++---- 49 files changed, 232 insertions(+), 228 deletions(-) diff --git a/clang/include/clang/Basic/arm_sme.td b/clang/include/clang/Basic/arm_sme.td index 695e1bddf9ff..2da0e8d2aba9 100644 --- a/clang/include/clang/Basic/arm_sme.td +++ b/clang/include/clang/Basic/arm_sme.td @@ -44,6 +44,7 @@ defm SVLD1_ZA32 : ZALoad<"za32", "i", "aarch64_sme_ld1w", [ImmCheck<0, ImmCheck0 defm SVLD1_ZA64 : ZALoad<"za64", "l", "aarch64_sme_ld1d", [ImmCheck<0, ImmCheck0_7>]>; defm SVLD1_ZA128 : ZALoad<"za128", "q", "aarch64_sme_ld1q", [ImmCheck<0, ImmCheck0_15>]>; +let TargetGuard = "sme" in { def SVLDR_VNUM_ZA : MInst<"svldr_vnum_za", "vmQl", "", [IsOverloadNone, IsStreamingCompatible, IsInOutZA], MemEltTyDefault, "aarch64_sme_ldr">; @@ -51,6 +52,7 @@ def SVLDR_VNUM_ZA : MInst<"svldr_vnum_za", "vmQl", "", def SVLDR_ZA : MInst<"svldr_za", "vmQ", "", [IsOverloadNone, IsStreamingCompatible, IsInOutZA], MemEltTyDefault, "aarch64_sme_ldr", []>; +} //////////////////////////////////////////////////////////////////////////////// // Stores @@ -81,6 +83,7 @@ defm SVST1_ZA32 : ZAStore<"za32", "i", "aarch64_sme_st1w", [ImmCheck<0, ImmCheck defm SVST1_ZA64 : ZAStore<"za64", "l", "aarch64_sme_st1d", [ImmCheck<0, ImmCheck0_7>]>; defm SVST1_ZA128 : ZAStore<"za128", "q", "aarch64_sme_st1q", [ImmCheck<0, ImmCheck0_15>]>; +let TargetGuard = "sme" in { def SVSTR_VNUM_ZA : MInst<"svstr_vnum_za", "vm%l", "", [IsOverloadNone, IsStreamingCompatible, IsInZA], MemEltTyDefault, "aarch64_sme_str">; @@ -88,6 +91,7 @@ def SVSTR_VNUM_ZA : MInst<"svstr_vnum_za", "vm%l", "", def SVSTR_ZA : MInst<"svstr_za", "vm%", "", [IsOverloadNone, IsStreamingCompatible, IsInZA], MemEltTyDefault, "aarch64_sme_str", []>; +} //////////////////////////////////////////////////////////////////////////////// // Read horizontal/vertical ZA slices @@ -277,22 +281,22 @@ multiclass ZAAddSub { def NAME # _ZA32_VG1x2_I32 : Inst<"sv" # n_suffix # "_za32[_{d}]_vg1x2", "vm2", "iUif", MergeNone, "aarch64_sme_" # n_suffix # "_za32_vg1x2", [IsStreaming, IsInOutZA], []>; def NAME # _ZA32_VG1X4_I32 : Inst<"sv" # n_suffix # "_za32[_{d}]_vg1x4", "vm4", "iUif", MergeNone, "aarch64_sme_" # n_suffix # "_za32_vg1x4", [IsStreaming, IsInOutZA], []>; + } - let TargetGuard = "sme-i16i64" in { - def NAME # _WRITE_SINGLE_ZA64_VG1X2_I64 : Inst<"sv" # n_suffix # "_write[_single]_za64[_{d}]_vg1x2", "vm2d", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_write_single_za_vg1x2", [IsStreaming, IsInOutZA], []>; - def NAME # _WRITE_SINGLE_ZA64_VG1X4_I64 : Inst<"sv" # n_suffix # "_write[_single]_za64[_{d}]_vg1x4", "vm4d", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_write_single_za_vg1x4", [IsStreaming, IsInOutZA], []>; + let TargetGuard = "sme2,sme-i16i64" in { + def NAME # _WRITE_SINGLE_ZA64_VG1X2_I64 : Inst<"sv" # n_suffix # "_write[_single]_za64[_{d}]_vg1x2", "vm2d", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_write_single_za_vg1x2", [IsStreaming, IsInOutZA], []>; + def NAME # _WRITE_SINGLE_ZA64_VG1X4_I64 : Inst<"sv" # n_suffix # "_write[_single]_za64[_{d}]_vg1x4", "vm4d", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_write_single_za_vg1x4", [IsStreaming, IsInOutZA], []>; - def NAME # _WRITE_ZA64_VG1x2_I64 : Inst<"sv" # n_suffix # "_write_za64[_{d}]_vg1x2", "vm22", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_write_za_vg1x2", [IsStreaming, IsInOutZA], []>; - def NAME # _WRITE_ZA64_VG1x4_I64 : Inst<"sv" # n_suffix # "_write_za64[_{d}]_vg1x4", "vm44", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_write_za_vg1x4", [IsStreaming, IsInOutZA], []>; + def NAME # _WRITE_ZA64_VG1x2_I64 : Inst<"sv" # n_suffix # "_write_za64[_{d}]_vg1x2", "vm22", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_write_za_vg1x2", [IsStreaming, IsInOutZA], []>; + def NAME # _WRITE_ZA64_VG1x4_I64 : Inst<"sv" # n_suffix # "_write_za64[_{d}]_vg1x4", "vm44", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_write_za_vg1x4", [IsStreaming, IsInOutZA], []>; - def NAME # _ZA64_VG1X2_I64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x2", "vm2", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x2", [IsStreaming, IsInOutZA], []>; - def NAME # _ZA64_VG1X4_I64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x4", "vm4", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x4", [IsStreaming, IsInOutZA], []>; - } + def NAME # _ZA64_VG1X2_I64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x2", "vm2", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x2", [IsStreaming, IsInOutZA], []>; + def NAME # _ZA64_VG1X4_I64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x4", "vm4", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x4", [IsStreaming, IsInOutZA], []>; + } - let TargetGuard = "sme-f64f64" in { - def NAME # _ZA64_VG1X2_F64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x2", "vm2", "d", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x2", [IsStreaming, IsInOutZA], []>; - def NAME # _ZA64_VG1X4_F64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x4", "vm4", "d", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x4", [IsStreaming, IsInOutZA], []>; - } + let TargetGuard = "sme2,sme-f64f64" in { + def NAME # _ZA64_VG1X2_F64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x2", "vm2", "d", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x2", [IsStreaming, IsInOutZA], []>; + def NAME # _ZA64_VG1X4_F64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x4", "vm4", "d", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x4", [IsStreaming, IsInOutZA], []>; } } diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i32.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i32.c index 695e0afa3d0d..a333d85818d2 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i32.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i32.c @@ -1,10 +1,10 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c index a3c3d8bf13db..7617dcef7ea9 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c @@ -1,10 +1,10 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c index 2c2f100ac7f8..5fa4c35ed770 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c index 0502073097d5..b26e32e5ff83 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c index 60feebced32d..02d4d034befb 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c index b0c1dd904284..c2c89aee03b5 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za32.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za32.c index 3dcc2c70d3cf..e036cb45feff 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za32.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za32.c @@ -1,10 +1,10 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -target-feature +bf16 -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +bf16 -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za64.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za64.c index 06a6a19ca3f7..84338597cdb3 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za64.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za64.c @@ -1,10 +1,10 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +bf16 -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za32.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za32.c index 69641df8a80f..7b1a8b0a0201 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za32.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za32.c @@ -1,10 +1,10 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -target-feature +bf16 -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +bf16 -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za64.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za64.c index d726855c9743..3d2a4e4d2b38 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za64.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za64.c @@ -1,10 +1,10 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +bf16 -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_read.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_read.c index ed1e70a3a469..9e44d1c92534 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_read.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_read.c @@ -1,10 +1,10 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c index f93f3e5138b2..d8e4b853308d 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c index b4bc041a21d5..467cf9fd092a 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c index 2ad7e3642572..e58021bf8bf4 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_write.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_write.c index a00a48ceafcc..483e81327502 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_write.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_write.c @@ -1,10 +1,10 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c index 9963c0e48b8e..1baa43b7187b 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_add.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_add.c index cfc2ee0f77be..2cc99d4fb88d 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_add.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_add.c @@ -2,11 +2,11 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_bmop.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_bmop.c index 720254c84212..1ff7a7fedf1b 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_bmop.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_bmop.c @@ -2,11 +2,11 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_clamp.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_clamp.c index a5dec263bff2..257cb5952501 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_clamp.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_clamp.c @@ -1,15 +1,15 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve \ -// RUN: -S -Werror -emit-llvm -disable-O0-optnone -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve \ -// RUN: -S -Werror -emit-llvm -disable-O0-optnone -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve \ -// RUN: -S -Werror -emit-llvm -disable-O0-optnone -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve \ -// RUN: -S -Werror -emit-llvm -disable-O0-optnone -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve \ -// RUN: -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 \ +// RUN: -S -Werror -emit-llvm -disable-O0-optnone -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 \ +// RUN: -S -Werror -emit-llvm -disable-O0-optnone -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 \ +// RUN: -S -Werror -emit-llvm -disable-O0-optnone -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 \ +// RUN: -S -Werror -emit-llvm -disable-O0-optnone -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 \ +// RUN: -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvt.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvt.c index a8d881b1e2ed..79a11c2ec153 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvt.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvt.c @@ -2,11 +2,11 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -D__SVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -D__SVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -D__SVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -D__SVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvtn.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvtn.c index f03e998131df..2b2b2e5c0f41 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvtn.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvtn.c @@ -2,11 +2,11 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -D__SVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -D__SVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -D__SVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -D__SVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_frint.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_frint.c index b90358112e47..8d1e358176c3 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_frint.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_frint.c @@ -2,11 +2,11 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt.c index 7c210fbe6923..70c31a4a87e7 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt.c @@ -2,9 +2,9 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c index d7ef75ce01dd..5bc9c9088517 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c @@ -2,9 +2,9 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c index f65c0ef61f81..82c004e3105a 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c @@ -2,9 +2,9 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt.c index cbab1cc8e81b..e8706f957691 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt.c @@ -2,9 +2,9 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c index f7f16281ff40..99feafbd682a 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c @@ -2,9 +2,9 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c index 3fedfdc33089..0f0c33e48bd9 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c @@ -2,9 +2,9 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_max.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_max.c index 4b9b4363ec62..a4e2616784ef 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_max.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_max.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s // REQUIRES: aarch64-registered-target #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_maxnm.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_maxnm.c index 5e499573304c..3e554212cb70 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_maxnm.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_maxnm.c @@ -1,11 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include #ifdef SVE_OVERLOADED_FORMS diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_min.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_min.c index 26c175c76532..a438fd395219 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_min.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_min.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s // REQUIRES: aarch64-registered-target #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_minnm.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_minnm.c index 8c5e7eb40199..b0cbdc748dc8 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_minnm.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_minnm.c @@ -1,11 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include #ifdef SVE_OVERLOADED_FORMS diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_mop.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_mop.c index b552bbb66a25..5cc0e0e1d36e 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_mop.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_mop.c @@ -2,11 +2,11 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_read.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_read.c index cd87ee009995..5fd4b0405652 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_read.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_read.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c index 6847eb99af2d..b86cb19c01e3 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c @@ -2,10 +2,10 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_sub.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_sub.c index c7da703ddb27..7af8c589994f 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_sub.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_sub.c @@ -2,11 +2,11 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_unpkx2.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_unpkx2.c index 6f20b37f8789..5937a288dd84 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_unpkx2.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_unpkx2.c @@ -2,12 +2,12 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature -S -disable-O0-optnone -Werror -Wall -o /dev/null %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include #ifdef SVE_OVERLOADED_FORMS diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_unpkx4.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_unpkx4.c index 781b699c882b..f54c09d5ef2c 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_unpkx4.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_unpkx4.c @@ -2,12 +2,12 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature -S -disable-O0-optnone -Werror -Wall -o /dev/null %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include #ifdef SVE_OVERLOADED_FORMS diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_add.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_add.c index 2b24f65efc26..2fb5d3bea27c 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_add.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_add.c @@ -2,11 +2,11 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_qrshr.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_qrshr.c index 32f9bc3ab880..eee927acc22e 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_qrshr.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_qrshr.c @@ -1,11 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_rshl.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_rshl.c index 8735016ae728..6308d6c596f1 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_rshl.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_rshl.c @@ -1,11 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include #ifdef SVE_OVERLOADED_FORMS diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_selx2.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_selx2.c index 32eb9a4b40c4..c2ecbf93bfaa 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_selx2.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_selx2.c @@ -1,11 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include #ifdef SVE_OVERLOADED_FORMS diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_selx4.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_selx4.c index 6e9d5cf4492f..784c24c8e7cb 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_selx4.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_selx4.c @@ -1,11 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include #ifdef SVE_OVERLOADED_FORMS diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_uzpx2.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_uzpx2.c index f4dadef8fa57..6349cec77119 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_uzpx2.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_uzpx2.c @@ -1,11 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_uzpx4.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_uzpx4.c index ff7f0c501f55..3d56948e25f7 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_uzpx4.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_uzpx4.c @@ -1,11 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_zipx2.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_zipx2.c index 3f13b3a0db73..4cc1f3af32ec 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_zipx2.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_zipx2.c @@ -1,10 +1,10 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_zipx4.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_zipx4.c index b8408ea31ed0..cc356600ab53 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_zipx4.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_zipx4.c @@ -1,10 +1,10 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_write.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_write.c index 33733356f307..069bf13ff8d2 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_write.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_write.c @@ -1,11 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -target-feature +sve -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include -- GitLab From c302909760d67a6d149fece3b79c90e47a25ba4d Mon Sep 17 00:00:00 2001 From: Orlando Cazalet-Hyams Date: Tue, 6 Feb 2024 10:45:31 +0000 Subject: [PATCH 053/266] [RemoveDIs] Fix DPValue hoisting in hoistSuccIdenticalTerminatorToSwitchOrIf (#80822) Follow up to #79476 - that patch added a call to hoistLockstepIdenticalDPValues which hoists identical DPValues in lockstep, matching dbg intrinsic hoisting behaviour. The code deleted in this patch, which unconditionally hoists DPValues, should have been deleted in that patch. Update test with --try-experimental-debuginfo-iterators to check the behaviour. Follow up to #79476 - that change introduces a call to hoistLockstepIdenticalDPValues. --- llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 5 ----- llvm/test/Transforms/SimplifyCFG/X86/sink-common-code.ll | 2 ++ 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp index f5b398cae04e..7424fe31945d 100644 --- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp +++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp @@ -1842,11 +1842,6 @@ bool SimplifyCFGOpt::hoistSuccIdenticalTerminatorToSwitchOrIf( Locs.push_back(I1->getDebugLoc()); for (auto *OtherSuccTI : OtherSuccTIs) Locs.push_back(OtherSuccTI->getDebugLoc()); - // Also clone DPValues from the existing terminator, and all others (to - // duplicate existing hoisting behaviour). - NT->cloneDebugInfoFrom(I1); - for (Instruction *OtherSuccTI : OtherSuccTIs) - NT->cloneDebugInfoFrom(OtherSuccTI); NT->setDebugLoc(DILocation::getMergedLocations(Locs)); // PHIs created below will adopt NT's merged DebugLoc. diff --git a/llvm/test/Transforms/SimplifyCFG/X86/sink-common-code.ll b/llvm/test/Transforms/SimplifyCFG/X86/sink-common-code.ll index 26107965a1a8..630c71df0536 100644 --- a/llvm/test/Transforms/SimplifyCFG/X86/sink-common-code.ll +++ b/llvm/test/Transforms/SimplifyCFG/X86/sink-common-code.ll @@ -1,6 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -passes=simplifycfg -simplifycfg-require-and-preserve-domtree=1 -sink-common-insts -S | FileCheck %s +; RUN: opt --try-experimental-debuginfo-iterators < %s -passes=simplifycfg -simplifycfg-require-and-preserve-domtree=1 -sink-common-insts -S | FileCheck %s ; RUN: opt < %s -passes='simplifycfg' -S | FileCheck %s +; RUN: opt --try-experimental-debuginfo-iterators < %s -passes='simplifycfg' -S | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-pc-linux-gnu" -- GitLab From 7f292b8fb12aed094b8422aad9fcb7b2907c54c9 Mon Sep 17 00:00:00 2001 From: Rin Dobrescu Date: Tue, 6 Feb 2024 11:02:06 +0000 Subject: [PATCH 054/266] [AArch64] Convert concat(uhadd(a,b), uhadd(c,d)) to uhadd(concat(a,c), concat(b,d)) (#80674) We can convert concat(v4i16 uhadd(a,b), v4i16 uhadd(c,d)) to v8i16 uhadd(concat(a,c), concat(b,d)), which can lead to further simplifications. --- .../Target/AArch64/AArch64ISelLowering.cpp | 49 ++---- llvm/test/CodeGen/AArch64/avoid-pre-trunc.ll | 93 ++++------- .../AArch64/concat-vector-add-combine.ll | 152 ++++++++++++++++++ 3 files changed, 190 insertions(+), 104 deletions(-) create mode 100644 llvm/test/CodeGen/AArch64/concat-vector-add-combine.ll diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index b59f8d730604..8573939b0438 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -18299,50 +18299,23 @@ static SDValue performConcatVectorsCombine(SDNode *N, if (DCI.isBeforeLegalizeOps()) return SDValue(); - // Optimise concat_vectors of two [us]avgceils or [us]avgfloors that use - // extracted subvectors from the same original vectors. Combine these into a - // single avg that operates on the two original vectors. - // avgceil is the target independant name for rhadd, avgfloor is a hadd. - // Example: - // (concat_vectors (v8i8 (avgceils (extract_subvector (v16i8 OpA, <0>), - // extract_subvector (v16i8 OpB, <0>))), - // (v8i8 (avgceils (extract_subvector (v16i8 OpA, <8>), - // extract_subvector (v16i8 OpB, <8>))))) - // -> - // (v16i8(avgceils(v16i8 OpA, v16i8 OpB))) - if (N->getNumOperands() == 2 && N0Opc == N1Opc && + // Optimise concat_vectors of two [us]avgceils or [us]avgfloors with a 128-bit + // destination size, combine into an avg of two contacts of the source + // vectors. eg: concat(uhadd(a,b), uhadd(c, d)) -> uhadd(concat(a, c), + // concat(b, d)) + if (N->getNumOperands() == 2 && N0Opc == N1Opc && VT.is128BitVector() && (N0Opc == ISD::AVGCEILU || N0Opc == ISD::AVGCEILS || - N0Opc == ISD::AVGFLOORU || N0Opc == ISD::AVGFLOORS)) { + N0Opc == ISD::AVGFLOORU || N0Opc == ISD::AVGFLOORS) && + N0->hasOneUse() && N1->hasOneUse()) { SDValue N00 = N0->getOperand(0); SDValue N01 = N0->getOperand(1); SDValue N10 = N1->getOperand(0); SDValue N11 = N1->getOperand(1); - EVT N00VT = N00.getValueType(); - EVT N10VT = N10.getValueType(); - - if (N00->getOpcode() == ISD::EXTRACT_SUBVECTOR && - N01->getOpcode() == ISD::EXTRACT_SUBVECTOR && - N10->getOpcode() == ISD::EXTRACT_SUBVECTOR && - N11->getOpcode() == ISD::EXTRACT_SUBVECTOR && N00VT == N10VT) { - SDValue N00Source = N00->getOperand(0); - SDValue N01Source = N01->getOperand(0); - SDValue N10Source = N10->getOperand(0); - SDValue N11Source = N11->getOperand(0); - - if (N00Source == N10Source && N01Source == N11Source && - N00Source.getValueType() == VT && N01Source.getValueType() == VT) { - assert(N0.getValueType() == N1.getValueType()); - - uint64_t N00Index = N00.getConstantOperandVal(1); - uint64_t N01Index = N01.getConstantOperandVal(1); - uint64_t N10Index = N10.getConstantOperandVal(1); - uint64_t N11Index = N11.getConstantOperandVal(1); - - if (N00Index == N01Index && N10Index == N11Index && N00Index == 0 && - N10Index == N00VT.getVectorNumElements()) - return DAG.getNode(N0Opc, dl, VT, N00Source, N01Source); - } + if (!N00.isUndef() && !N01.isUndef() && !N10.isUndef() && !N11.isUndef()) { + SDValue Concat0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, N00, N10); + SDValue Concat1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, N01, N11); + return DAG.getNode(N0Opc, dl, VT, Concat0, Concat1); } } diff --git a/llvm/test/CodeGen/AArch64/avoid-pre-trunc.ll b/llvm/test/CodeGen/AArch64/avoid-pre-trunc.ll index 24cce9a2b26b..c4de177176e3 100644 --- a/llvm/test/CodeGen/AArch64/avoid-pre-trunc.ll +++ b/llvm/test/CodeGen/AArch64/avoid-pre-trunc.ll @@ -1,75 +1,36 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 ; RUN: llc -mtriple=aarch64 < %s | FileCheck %s -define i32 @lower_lshr(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d, <4 x i32> %e, <4 x i32> %f, <4 x i32> %g, <4 x i32> %h) { -; CHECK-LABEL: lower_lshr: -; CHECK: // %bb.0: -; CHECK-NEXT: addv s0, v0.4s -; CHECK-NEXT: addv s1, v1.4s -; CHECK-NEXT: addv s4, v4.4s -; CHECK-NEXT: addv s5, v5.4s -; CHECK-NEXT: addv s2, v2.4s -; CHECK-NEXT: addv s6, v6.4s -; CHECK-NEXT: mov v0.s[1], v1.s[0] -; CHECK-NEXT: addv s1, v3.4s -; CHECK-NEXT: addv s3, v7.4s -; CHECK-NEXT: mov v4.s[1], v5.s[0] -; CHECK-NEXT: mov v0.s[2], v2.s[0] -; CHECK-NEXT: mov v4.s[2], v6.s[0] -; CHECK-NEXT: mov v0.s[3], v1.s[0] -; CHECK-NEXT: mov v4.s[3], v3.s[0] -; CHECK-NEXT: xtn v1.4h, v0.4s -; CHECK-NEXT: shrn v0.4h, v0.4s, #16 -; CHECK-NEXT: xtn v2.4h, v4.4s -; CHECK-NEXT: shrn v3.4h, v4.4s, #16 -; CHECK-NEXT: uhadd v0.4h, v1.4h, v0.4h -; CHECK-NEXT: uhadd v1.4h, v2.4h, v3.4h -; CHECK-NEXT: mov v0.d[1], v1.d[0] -; CHECK-NEXT: uaddlv s0, v0.8h -; CHECK-NEXT: fmov w0, s0 -; CHECK-NEXT: ret - %l87 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %a) - %l174 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %b) - %l257 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %c) - %l340 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %d) - %l427 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %e) - %l514 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %f) - %l597 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %g) - %l680 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %h) - %l681 = insertelement <8 x i32> poison, i32 %l87, i32 0 - %l682 = insertelement <8 x i32> %l681, i32 %l174, i32 1 - %l683 = insertelement <8 x i32> %l682, i32 %l257, i32 2 - %l684 = insertelement <8 x i32> %l683, i32 %l340, i32 3 - %l685 = insertelement <8 x i32> %l684, i32 %l427, i32 4 - %l686 = insertelement <8 x i32> %l685, i32 %l514, i32 5 - %l687 = insertelement <8 x i32> %l686, i32 %l597, i32 6 - %l688 = insertelement <8 x i32> %l687, i32 %l680, i32 7 - %l689 = and <8 x i32> %l688, - %l690 = lshr <8 x i32> %l688, - %l691 = add nuw nsw <8 x i32> %l689, %l690 - %l692 = lshr <8 x i32> %l691, - %l693 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %l692) - ret i32 %l693 -} -declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) -declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>) - define <16 x i8> @lower_trunc_16xi8(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f, i16 %g, i16 %h, i16 %i, i16 %j, i16 %k, i16 %l, i16 %m, i16 %n, i16 %o, i16 %p) { ; CHECK-LABEL: lower_trunc_16xi8: ; CHECK: // %bb.0: ; CHECK-NEXT: fmov s0, w0 -; CHECK-NEXT: add x8, sp, #56 -; CHECK-NEXT: ld1r { v1.8h }, [x8] +; CHECK-NEXT: ldr h1, [sp] +; CHECK-NEXT: add x8, sp, #8 +; CHECK-NEXT: ld1 { v1.h }[1], [x8] +; CHECK-NEXT: add x8, sp, #16 ; CHECK-NEXT: mov v0.h[1], w1 -; CHECK-NEXT: add v3.8h, v1.8h, v1.8h +; CHECK-NEXT: ld1 { v1.h }[2], [x8] +; CHECK-NEXT: add x8, sp, #24 ; CHECK-NEXT: mov v0.h[2], w2 +; CHECK-NEXT: ld1 { v1.h }[3], [x8] +; CHECK-NEXT: add x8, sp, #32 ; CHECK-NEXT: mov v0.h[3], w3 +; CHECK-NEXT: ld1 { v1.h }[4], [x8] +; CHECK-NEXT: add x8, sp, #40 +; CHECK-NEXT: ld1 { v1.h }[5], [x8] +; CHECK-NEXT: add x8, sp, #48 ; CHECK-NEXT: mov v0.h[4], w4 +; CHECK-NEXT: ld1 { v1.h }[6], [x8] +; CHECK-NEXT: add x8, sp, #56 ; CHECK-NEXT: mov v0.h[5], w5 +; CHECK-NEXT: ld1 { v1.h }[7], [x8] ; CHECK-NEXT: mov v0.h[6], w6 -; CHECK-NEXT: add v2.8h, v0.8h, v0.8h +; CHECK-NEXT: add v2.8h, v1.8h, v1.8h +; CHECK-NEXT: mov v0.h[7], w7 +; CHECK-NEXT: add v3.8h, v0.8h, v0.8h ; CHECK-NEXT: uzp1 v0.16b, v0.16b, v1.16b -; CHECK-NEXT: uzp1 v1.16b, v2.16b, v3.16b +; CHECK-NEXT: uzp1 v1.16b, v3.16b, v2.16b ; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b ; CHECK-NEXT: ret %a1 = insertelement <16 x i16> poison, i16 %a, i16 0 @@ -80,14 +41,14 @@ define <16 x i8> @lower_trunc_16xi8(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f1 = insertelement <16 x i16> %e1, i16 %f, i16 5 %g1 = insertelement <16 x i16> %f1, i16 %g, i16 6 %h1 = insertelement <16 x i16> %g1, i16 %h, i16 7 - %i1 = insertelement <16 x i16> %f1, i16 %i, i16 8 - %j1 = insertelement <16 x i16> %g1, i16 %j, i16 9 - %k1 = insertelement <16 x i16> %f1, i16 %k, i16 10 - %l1 = insertelement <16 x i16> %g1, i16 %l, i16 11 - %m1 = insertelement <16 x i16> %f1, i16 %m, i16 12 - %n1 = insertelement <16 x i16> %g1, i16 %n, i16 13 - %o1 = insertelement <16 x i16> %f1, i16 %o, i16 14 - %p1 = insertelement <16 x i16> %g1, i16 %p, i16 15 + %i1 = insertelement <16 x i16> %h1, i16 %i, i16 8 + %j1 = insertelement <16 x i16> %i1, i16 %j, i16 9 + %k1 = insertelement <16 x i16> %j1, i16 %k, i16 10 + %l1 = insertelement <16 x i16> %k1, i16 %l, i16 11 + %m1 = insertelement <16 x i16> %l1, i16 %m, i16 12 + %n1 = insertelement <16 x i16> %m1, i16 %n, i16 13 + %o1 = insertelement <16 x i16> %n1, i16 %o, i16 14 + %p1 = insertelement <16 x i16> %o1, i16 %p, i16 15 %t = trunc <16 x i16> %p1 to <16 x i8> %s = add <16 x i16> %p1, %p1 %t2 = trunc <16 x i16> %s to <16 x i8> diff --git a/llvm/test/CodeGen/AArch64/concat-vector-add-combine.ll b/llvm/test/CodeGen/AArch64/concat-vector-add-combine.ll new file mode 100644 index 000000000000..34899cb47dba --- /dev/null +++ b/llvm/test/CodeGen/AArch64/concat-vector-add-combine.ll @@ -0,0 +1,152 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -mtriple=aarch64 < %s | FileCheck %s + +define i16 @combine_add_16xi16(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f, i16 %g, i16 %h, i16 %i, i16 %j, i16 %k, i16 %l, i16 %m, i16 %n, i16 %o, i16 %p) { +; CHECK-LABEL: combine_add_16xi16: +; CHECK: // %bb.0: +; CHECK-NEXT: fmov s0, w0 +; CHECK-NEXT: ldr h1, [sp] +; CHECK-NEXT: add x8, sp, #8 +; CHECK-NEXT: ld1 { v1.h }[1], [x8] +; CHECK-NEXT: add x8, sp, #16 +; CHECK-NEXT: mov v0.h[1], w1 +; CHECK-NEXT: ld1 { v1.h }[2], [x8] +; CHECK-NEXT: add x8, sp, #24 +; CHECK-NEXT: mov v0.h[2], w2 +; CHECK-NEXT: ld1 { v1.h }[3], [x8] +; CHECK-NEXT: add x8, sp, #32 +; CHECK-NEXT: mov v0.h[3], w3 +; CHECK-NEXT: ld1 { v1.h }[4], [x8] +; CHECK-NEXT: add x8, sp, #40 +; CHECK-NEXT: ld1 { v1.h }[5], [x8] +; CHECK-NEXT: add x8, sp, #48 +; CHECK-NEXT: mov v0.h[4], w4 +; CHECK-NEXT: ld1 { v1.h }[6], [x8] +; CHECK-NEXT: add x8, sp, #56 +; CHECK-NEXT: mov v0.h[5], w5 +; CHECK-NEXT: ld1 { v1.h }[7], [x8] +; CHECK-NEXT: mov v0.h[6], w6 +; CHECK-NEXT: mov v0.h[7], w7 +; CHECK-NEXT: uzp2 v2.16b, v0.16b, v1.16b +; CHECK-NEXT: uzp1 v0.16b, v0.16b, v1.16b +; CHECK-NEXT: uhadd v0.16b, v0.16b, v2.16b +; CHECK-NEXT: uaddlv h0, v0.16b +; CHECK-NEXT: umov w0, v0.h[0] +; CHECK-NEXT: ret + %a1 = insertelement <16 x i16> poison, i16 %a, i16 0 + %b1 = insertelement <16 x i16> %a1, i16 %b, i16 1 + %c1 = insertelement <16 x i16> %b1, i16 %c, i16 2 + %d1 = insertelement <16 x i16> %c1, i16 %d, i16 3 + %e1 = insertelement <16 x i16> %d1, i16 %e, i16 4 + %f1 = insertelement <16 x i16> %e1, i16 %f, i16 5 + %g1 = insertelement <16 x i16> %f1, i16 %g, i16 6 + %h1 = insertelement <16 x i16> %g1, i16 %h, i16 7 + %i1 = insertelement <16 x i16> %h1, i16 %i, i16 8 + %j1 = insertelement <16 x i16> %i1, i16 %j, i16 9 + %k1 = insertelement <16 x i16> %j1, i16 %k, i16 10 + %l1 = insertelement <16 x i16> %k1, i16 %l, i16 11 + %m1 = insertelement <16 x i16> %l1, i16 %m, i16 12 + %n1 = insertelement <16 x i16> %m1, i16 %n, i16 13 + %o1 = insertelement <16 x i16> %n1, i16 %o, i16 14 + %p1 = insertelement <16 x i16> %o1, i16 %p, i16 15 + %x = and <16 x i16> %p1, + %sh1 = lshr <16 x i16> %p1, + %s = add nuw nsw <16 x i16> %x, %sh1 + %sh2 = lshr <16 x i16> %s, + %res = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %sh2) + ret i16 %res +} + +define i32 @combine_add_8xi32(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h) local_unnamed_addr #0 { +; CHECK-LABEL: combine_add_8xi32: +; CHECK: // %bb.0: +; CHECK-NEXT: fmov s0, w4 +; CHECK-NEXT: fmov s1, w0 +; CHECK-NEXT: mov v0.s[1], w5 +; CHECK-NEXT: mov v1.s[1], w1 +; CHECK-NEXT: mov v0.s[2], w6 +; CHECK-NEXT: mov v1.s[2], w2 +; CHECK-NEXT: mov v0.s[3], w7 +; CHECK-NEXT: mov v1.s[3], w3 +; CHECK-NEXT: uzp2 v2.8h, v1.8h, v0.8h +; CHECK-NEXT: uzp1 v0.8h, v1.8h, v0.8h +; CHECK-NEXT: uhadd v0.8h, v0.8h, v2.8h +; CHECK-NEXT: uaddlv s0, v0.8h +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %a1 = insertelement <8 x i32> poison, i32 %a, i32 0 + %b1 = insertelement <8 x i32> %a1, i32 %b, i32 1 + %c1 = insertelement <8 x i32> %b1, i32 %c, i32 2 + %d1 = insertelement <8 x i32> %c1, i32 %d, i32 3 + %e1 = insertelement <8 x i32> %d1, i32 %e, i32 4 + %f1 = insertelement <8 x i32> %e1, i32 %f, i32 5 + %g1 = insertelement <8 x i32> %f1, i32 %g, i32 6 + %h1 = insertelement <8 x i32> %g1, i32 %h, i32 7 + %x = and <8 x i32> %h1, + %sh1 = lshr <8 x i32> %h1, + %s = add nuw nsw <8 x i32> %x, %sh1 + %sh2 = lshr <8 x i32> %s, + %res = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %sh2) + ret i32 %res +} + +define i32 @combine_undef_add_8xi32(i32 %a, i32 %b, i32 %c, i32 %d) local_unnamed_addr #0 { +; CHECK-LABEL: combine_undef_add_8xi32: +; CHECK: // %bb.0: +; CHECK-NEXT: fmov s1, w0 +; CHECK-NEXT: movi v0.2d, #0000000000000000 +; CHECK-NEXT: mov v1.s[1], w1 +; CHECK-NEXT: uhadd v0.4h, v0.4h, v0.4h +; CHECK-NEXT: mov v1.s[2], w2 +; CHECK-NEXT: mov v1.s[3], w3 +; CHECK-NEXT: xtn v2.4h, v1.4s +; CHECK-NEXT: shrn v1.4h, v1.4s, #16 +; CHECK-NEXT: uhadd v1.4h, v2.4h, v1.4h +; CHECK-NEXT: mov v1.d[1], v0.d[0] +; CHECK-NEXT: uaddlv s0, v1.8h +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %a1 = insertelement <8 x i32> poison, i32 %a, i32 0 + %b1 = insertelement <8 x i32> %a1, i32 %b, i32 1 + %c1 = insertelement <8 x i32> %b1, i32 %c, i32 2 + %d1 = insertelement <8 x i32> %c1, i32 %d, i32 3 + %e1 = insertelement <8 x i32> %d1, i32 undef, i32 4 + %f1 = insertelement <8 x i32> %e1, i32 undef, i32 5 + %g1 = insertelement <8 x i32> %f1, i32 undef, i32 6 + %h1 = insertelement <8 x i32> %g1, i32 undef, i32 7 + %x = and <8 x i32> %h1, + %sh1 = lshr <8 x i32> %h1, + %s = add nuw nsw <8 x i32> %x, %sh1 + %sh2 = lshr <8 x i32> %s, + %res = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %sh2) + ret i32 %res +} + +define i64 @combine_add_4xi64(i64 %a, i64 %b, i64 %c, i64 %d) local_unnamed_addr #0 { +; CHECK-LABEL: combine_add_4xi64: +; CHECK: // %bb.0: +; CHECK-NEXT: fmov d0, x2 +; CHECK-NEXT: fmov d1, x0 +; CHECK-NEXT: mov v0.d[1], x3 +; CHECK-NEXT: mov v1.d[1], x1 +; CHECK-NEXT: uzp2 v2.4s, v1.4s, v0.4s +; CHECK-NEXT: uzp1 v0.4s, v1.4s, v0.4s +; CHECK-NEXT: uhadd v0.4s, v0.4s, v2.4s +; CHECK-NEXT: uaddlv d0, v0.4s +; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: ret + %a1 = insertelement <4 x i64> poison, i64 %a, i64 0 + %b1 = insertelement <4 x i64> %a1, i64 %b, i64 1 + %c1 = insertelement <4 x i64> %b1, i64 %c, i64 2 + %d1 = insertelement <4 x i64> %c1, i64 %d, i64 3 + %x = and <4 x i64> %d1, + %sh1 = lshr <4 x i64> %d1, + %s = add nuw nsw <4 x i64> %x, %sh1 + %sh2 = lshr <4 x i64> %s, + %res = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %sh2) + ret i64 %res +} + +declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16>) +declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>) +declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64>) -- GitLab From 8924a9ffcb3696288cca3334cd60a099d3fcda79 Mon Sep 17 00:00:00 2001 From: Simon Camphausen Date: Tue, 6 Feb 2024 12:04:13 +0100 Subject: [PATCH 055/266] [mlir][EmitC] Remove unreachable code and fix Windows build warning (#80677) --- mlir/lib/Target/Cpp/TranslateToCpp.cpp | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/mlir/lib/Target/Cpp/TranslateToCpp.cpp b/mlir/lib/Target/Cpp/TranslateToCpp.cpp index a53d7d1701a9..e27fddc2c610 100644 --- a/mlir/lib/Target/Cpp/TranslateToCpp.cpp +++ b/mlir/lib/Target/Cpp/TranslateToCpp.cpp @@ -69,12 +69,12 @@ inline LogicalResult interleaveCommaWithError(const Container &c, /// Return the precedence of a operator as an integer, higher values /// imply higher precedence. -static int getOperatorPrecedence(Operation *operation) { - return llvm::TypeSwitch(operation) +static FailureOr getOperatorPrecedence(Operation *operation) { + return llvm::TypeSwitch>(operation) .Case([&](auto op) { return 11; }) .Case([&](auto op) { return 13; }) .Case([&](auto op) { return 13; }) - .Case([&](auto op) { + .Case([&](auto op) -> FailureOr { switch (op.getPredicate()) { case emitc::CmpPredicate::eq: case emitc::CmpPredicate::ne: @@ -87,13 +87,14 @@ static int getOperatorPrecedence(Operation *operation) { case emitc::CmpPredicate::three_way: return 10; } + return op->emitError("unsupported cmp predicate"); }) .Case([&](auto op) { return 12; }) .Case([&](auto op) { return 12; }) .Case([&](auto op) { return 12; }) .Case([&](auto op) { return 11; }) - .Case([&](auto op) { return 14; }); - llvm_unreachable("Unsupported operator"); + .Case([&](auto op) { return 14; }) + .Default([](auto op) { return op->emitError("unsupported operation"); }); } namespace { @@ -1120,7 +1121,10 @@ LogicalResult CppEmitter::emitExpression(ExpressionOp expressionOp) { Operation *rootOp = expressionOp.getRootOp(); emittedExpression = expressionOp; - pushExpressionPrecedence(getOperatorPrecedence(rootOp)); + FailureOr precedence = getOperatorPrecedence(rootOp); + if (failed(precedence)) + return failure(); + pushExpressionPrecedence(precedence.value()); if (failed(emitOperation(*rootOp, /*trailingSemicolon=*/false))) return failure(); @@ -1137,13 +1141,15 @@ LogicalResult CppEmitter::emitOperand(Value value) { if (isPartOfCurrentExpression(value)) { Operation *def = value.getDefiningOp(); assert(def && "Expected operand to be defined by an operation"); - int precedence = getOperatorPrecedence(def); - bool encloseInParenthesis = precedence < getExpressionPrecedence(); + FailureOr precedence = getOperatorPrecedence(def); + if (failed(precedence)) + return failure(); + bool encloseInParenthesis = precedence.value() < getExpressionPrecedence(); if (encloseInParenthesis) { os << "("; pushExpressionPrecedence(lowestPrecedence()); } else - pushExpressionPrecedence(precedence); + pushExpressionPrecedence(precedence.value()); if (failed(emitOperation(*def, /*trailingSemicolon=*/false))) return failure(); -- GitLab From de8ba2f60334dc44f6906a0722435db41564b421 Mon Sep 17 00:00:00 2001 From: Francesco Petrogalli Date: Tue, 6 Feb 2024 12:11:10 +0100 Subject: [PATCH 056/266] [CodeGen] Update comments for ValueType.td. [NFC] (#80670) The enums needed by the file MachineValueType.h are auto-generated since commit ddaf085e7bcb903d5ae1cafc4667b8c3d302897e --- llvm/include/llvm/CodeGen/ValueTypes.td | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/llvm/include/llvm/CodeGen/ValueTypes.td b/llvm/include/llvm/CodeGen/ValueTypes.td index 25f0d385259d..55baaf867e73 100644 --- a/llvm/include/llvm/CodeGen/ValueTypes.td +++ b/llvm/include/llvm/CodeGen/ValueTypes.td @@ -6,9 +6,8 @@ // //===----------------------------------------------------------------------===// // -// Value types - These values correspond to the register types defined in the -// MachineValueTypes.h file. If you update anything here, you must update it -// there as well! +// ValueTypes.td - list of ValueType instances supported by the the +// CodeGen infrastructure. // //===----------------------------------------------------------------------===// -- GitLab From 82950a695ddbd92beb07bf58b48067a1f67d57e3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Tue, 6 Feb 2024 12:02:08 +0100 Subject: [PATCH 057/266] [clang][Interp] Protect ArrayElemPtr ops from dummy pointers Change the semantics of Pointer::isDummy() to check for a null Pointee and returnd false in that case. Then call CheckDummy() in ArrayElemPtr{,Pop} to protect those ops from operating on dummy pointers and enable a few tests in test/Sema/ that now work with the new constant interpreter. --- clang/lib/AST/Interp/Interp.cpp | 2 +- clang/lib/AST/Interp/Interp.h | 28 +++++++++++-------- clang/lib/AST/Interp/Pointer.h | 6 +++- .../fp-eval-pragma-with-float-double_t-1.c | 25 ++++++++++++++--- .../fp-eval-pragma-with-float-double_t-2.c | 20 +++++++++++++ .../fp-eval-pragma-with-float-double_t-3.c | 20 ++++++++++++- 6 files changed, 83 insertions(+), 18 deletions(-) diff --git a/clang/lib/AST/Interp/Interp.cpp b/clang/lib/AST/Interp/Interp.cpp index 0766ad88e922..683151f7caf5 100644 --- a/clang/lib/AST/Interp/Interp.cpp +++ b/clang/lib/AST/Interp/Interp.cpp @@ -272,7 +272,7 @@ static bool CheckConstant(InterpState &S, CodePtr OpPC, const Pointer &Ptr) { } bool CheckDummy(InterpState &S, CodePtr OpPC, const Pointer &Ptr) { - return !Ptr.isZero() && !Ptr.isDummy(); + return !Ptr.isDummy(); } bool CheckNull(InterpState &S, CodePtr OpPC, const Pointer &Ptr, diff --git a/clang/lib/AST/Interp/Interp.h b/clang/lib/AST/Interp/Interp.h index e41604e125eb..6c99fa2f9d14 100644 --- a/clang/lib/AST/Interp/Interp.h +++ b/clang/lib/AST/Interp/Interp.h @@ -1855,6 +1855,23 @@ inline bool ArrayElemPtr(InterpState &S, CodePtr OpPC) { const T &Offset = S.Stk.pop(); const Pointer &Ptr = S.Stk.peek(); + if (!CheckDummy(S, OpPC, Ptr)) + return false; + + if (!OffsetHelper(S, OpPC, Offset, Ptr)) + return false; + + return NarrowPtr(S, OpPC); +} + +template ::T> +inline bool ArrayElemPtrPop(InterpState &S, CodePtr OpPC) { + const T &Offset = S.Stk.pop(); + const Pointer &Ptr = S.Stk.pop(); + + if (!CheckDummy(S, OpPC, Ptr)) + return false; + if (!OffsetHelper(S, OpPC, Offset, Ptr)) return false; @@ -1877,17 +1894,6 @@ inline bool ArrayDecay(InterpState &S, CodePtr OpPC) { return false; } -template ::T> -inline bool ArrayElemPtrPop(InterpState &S, CodePtr OpPC) { - const T &Offset = S.Stk.pop(); - const Pointer &Ptr = S.Stk.pop(); - - if (!OffsetHelper(S, OpPC, Offset, Ptr)) - return false; - - return NarrowPtr(S, OpPC); -} - inline bool Call(InterpState &S, CodePtr OpPC, const Function *Func) { if (Func->hasThisPointer()) { size_t ThisOffset = diff --git a/clang/lib/AST/Interp/Pointer.h b/clang/lib/AST/Interp/Pointer.h index 53b89c51b5a8..b3a3a98a043c 100644 --- a/clang/lib/AST/Interp/Pointer.h +++ b/clang/lib/AST/Interp/Pointer.h @@ -340,7 +340,11 @@ public: /// Checks if a structure is a base class. bool isBaseClass() const { return isField() && getInlineDesc()->IsBase; } /// Checks if the pointer pointers to a dummy value. - bool isDummy() const { return getDeclDesc()->isDummy(); } + bool isDummy() const { + if (!Pointee) + return false; + return getDeclDesc()->isDummy(); + } /// Checks if an object or a subfield is mutable. bool isConst() const { diff --git a/clang/test/Sema/fp-eval-pragma-with-float-double_t-1.c b/clang/test/Sema/fp-eval-pragma-with-float-double_t-1.c index ed47101d6443..c72510beddb1 100644 --- a/clang/test/Sema/fp-eval-pragma-with-float-double_t-1.c +++ b/clang/test/Sema/fp-eval-pragma-with-float-double_t-1.c @@ -1,23 +1,40 @@ // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -DNOERROR %s -// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ -// RUN: -x c++ -DCPP -DNOERROR %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -DNOERROR %s -fexperimental-new-constant-interpreter + +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP -DNOERROR %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP -DNOERROR %s -fexperimental-new-constant-interpreter // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ // RUN: -ffp-eval-method=source -DNOERROR %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ +// RUN: -ffp-eval-method=source -DNOERROR %s -fexperimental-new-constant-interpreter + // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ // RUN: -ffp-eval-method=source \ // RUN: -DNOERROR %s - +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ +// RUN: -ffp-eval-method=source \ +// RUN: -DNOERROR %s -fexperimental-new-constant-interpreter + // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ // RUN: -ffp-eval-method=double %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ +// RUN: -ffp-eval-method=double %s -fexperimental-new-constant-interpreter + // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ // RUN: -ffp-eval-method=double %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ +// RUN: -ffp-eval-method=double %s -fexperimental-new-constant-interpreter // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ // RUN: -ffp-eval-method=extended %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ +// RUN: -ffp-eval-method=extended %s -fexperimental-new-constant-interpreter + // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ // RUN: -ffp-eval-method=extended %s - +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ +// RUN: -ffp-eval-method=extended %s -fexperimental-new-constant-interpreter #ifdef NOERROR // expected-no-diagnostics diff --git a/clang/test/Sema/fp-eval-pragma-with-float-double_t-2.c b/clang/test/Sema/fp-eval-pragma-with-float-double_t-2.c index 61bf7c970807..f26b43f7cd37 100644 --- a/clang/test/Sema/fp-eval-pragma-with-float-double_t-2.c +++ b/clang/test/Sema/fp-eval-pragma-with-float-double_t-2.c @@ -1,21 +1,41 @@ // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -DNOERROR %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -DNOERROR %s -fexperimental-new-constant-interpreter + // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ // RUN: -x c++ -DCPP -DNOERROR %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ +// RUN: -x c++ -DCPP -DNOERROR %s -fexperimental-new-constant-interpreter // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ // RUN: -ffp-eval-method=double -DNOERROR %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ +// RUN: -ffp-eval-method=double -DNOERROR %s -fexperimental-new-constant-interpreter + // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ // RUN: -ffp-eval-method=double -DNOERROR %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ +// RUN: -ffp-eval-method=double -DNOERROR %s -fexperimental-new-constant-interpreter + // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ // RUN: -ffp-eval-method=source %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ +// RUN: -ffp-eval-method=source %s -fexperimental-new-constant-interpreter + // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ // RUN: -ffp-eval-method=source %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ +// RUN: -ffp-eval-method=source %s -fexperimental-new-constant-interpreter // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ // RUN: -ffp-eval-method=extended %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ +// RUN: -ffp-eval-method=extended %s -fexperimental-new-constant-interpreter + // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ // RUN: -ffp-eval-method=extended %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ +// RUN: -ffp-eval-method=extended %s -fexperimental-new-constant-interpreter #ifdef NOERROR // expected-no-diagnostics diff --git a/clang/test/Sema/fp-eval-pragma-with-float-double_t-3.c b/clang/test/Sema/fp-eval-pragma-with-float-double_t-3.c index 8be5c5535af3..d58a36dc108a 100644 --- a/clang/test/Sema/fp-eval-pragma-with-float-double_t-3.c +++ b/clang/test/Sema/fp-eval-pragma-with-float-double_t-3.c @@ -1,22 +1,40 @@ // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -DNOERROR %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -DNOERROR %s -fexperimental-new-constant-interpreter + // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ // RUN: -x c++ -DCPP -DNOERROR %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ +// RUN: -x c++ -DCPP -DNOERROR %s -fexperimental-new-constant-interpreter // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ // RUN: -ffp-eval-method=extended -DNOERROR %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ +// RUN: -ffp-eval-method=extended -DNOERROR %s -fexperimental-new-constant-interpreter + // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ // RUN: -ffp-eval-method=extended -DNOERROR %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ +// RUN: -ffp-eval-method=extended -DNOERROR %s -fexperimental-new-constant-interpreter // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ // RUN: -ffp-eval-method=source %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ +// RUN: -ffp-eval-method=source %s -fexperimental-new-constant-interpreter + // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ // RUN: -ffp-eval-method=source %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ +// RUN: -ffp-eval-method=source %s -fexperimental-new-constant-interpreter // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ // RUN: -ffp-eval-method=double %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ +// RUN: -ffp-eval-method=double %s -fexperimental-new-constant-interpreter + // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ // RUN: -ffp-eval-method=double %s - +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ +// RUN: -ffp-eval-method=double %s -fexperimental-new-constant-interpreter #ifdef NOERROR // expected-no-diagnostics -- GitLab From ccc77f1194f894db8ec93131124a7a2848e3e079 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Tue, 6 Feb 2024 12:37:27 +0100 Subject: [PATCH 058/266] [clang][Interp][NFC] Fix comment typos --- clang/lib/AST/Interp/Interp.h | 2 +- clang/lib/AST/Interp/Pointer.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/clang/lib/AST/Interp/Interp.h b/clang/lib/AST/Interp/Interp.h index 6c99fa2f9d14..b33cf55c61f0 100644 --- a/clang/lib/AST/Interp/Interp.h +++ b/clang/lib/AST/Interp/Interp.h @@ -1878,7 +1878,7 @@ inline bool ArrayElemPtrPop(InterpState &S, CodePtr OpPC) { return NarrowPtr(S, OpPC); } -/// Just takes a pointer and checks if its' an incomplete +/// Just takes a pointer and checks if it's an incomplete /// array type. inline bool ArrayDecay(InterpState &S, CodePtr OpPC) { const Pointer &Ptr = S.Stk.pop(); diff --git a/clang/lib/AST/Interp/Pointer.h b/clang/lib/AST/Interp/Pointer.h index b3a3a98a043c..fa2e03d71190 100644 --- a/clang/lib/AST/Interp/Pointer.h +++ b/clang/lib/AST/Interp/Pointer.h @@ -339,7 +339,7 @@ public: } /// Checks if a structure is a base class. bool isBaseClass() const { return isField() && getInlineDesc()->IsBase; } - /// Checks if the pointer pointers to a dummy value. + /// Checks if the pointer points to a dummy value. bool isDummy() const { if (!Pointee) return false; -- GitLab From cf94e0082e5e0a9be43a69d9fae588bc2aafab91 Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Tue, 6 Feb 2024 12:38:58 +0100 Subject: [PATCH 059/266] [bazel] Add missing dependency for 0473e322f67228a9c2dbf462357e5b4a2b3799be --- utils/bazel/llvm-project-overlay/mlir/BUILD.bazel | 1 + 1 file changed, 1 insertion(+) diff --git a/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel b/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel index b136cd3d4bc9..1d7958751253 100644 --- a/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel @@ -2104,6 +2104,7 @@ cc_library( ":IR", ":LLVMCommonConversion", ":LLVMDialect", + ":MemRefDialect", ":Pass", ":SCFDialect", ":SCFTransforms", -- GitLab From b8cdc2638e4c067fd633b345aba75fee81c4054f Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 6 Feb 2024 12:19:31 +0000 Subject: [PATCH 060/266] [DAG] visitCTPOP - if only the upper half of the ctpop operand is zero then see if its profitable to only count the lower half. (#80473) --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 18 ++++++++++++++++++ llvm/test/CodeGen/AMDGPU/ctpop64.ll | 18 ++++++++---------- llvm/test/CodeGen/X86/ctpop-mask.ll | 10 +++++----- 3 files changed, 31 insertions(+), 15 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 7f91de12e10d..291a085b485f 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -11142,11 +11142,29 @@ SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) { SDValue DAGCombiner::visitCTPOP(SDNode *N) { SDValue N0 = N->getOperand(0); EVT VT = N->getValueType(0); + unsigned NumBits = VT.getScalarSizeInBits(); SDLoc DL(N); // fold (ctpop c1) -> c2 if (SDValue C = DAG.FoldConstantArithmetic(ISD::CTPOP, DL, VT, {N0})) return C; + + // If the upper bits are known to be zero, then see if its profitable to + // only count the lower bits. + if (VT.isScalarInteger() && NumBits > 8 && (NumBits & 1) == 0) { + EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), NumBits / 2); + if (hasOperation(ISD::CTPOP, HalfVT) && + TLI.isTypeDesirableForOp(ISD::CTPOP, HalfVT) && + TLI.isTruncateFree(N0, HalfVT) && TLI.isZExtFree(HalfVT, VT)) { + APInt UpperBits = APInt::getHighBitsSet(NumBits, NumBits / 2); + if (DAG.MaskedValueIsZero(N0, UpperBits)) { + SDValue PopCnt = DAG.getNode(ISD::CTPOP, DL, HalfVT, + DAG.getZExtOrTrunc(N0, DL, HalfVT)); + return DAG.getZExtOrTrunc(PopCnt, DL, VT); + } + } + } + return SDValue(); } diff --git a/llvm/test/CodeGen/AMDGPU/ctpop64.ll b/llvm/test/CodeGen/AMDGPU/ctpop64.ll index 1346678e51e3..3b9c3e3ba175 100644 --- a/llvm/test/CodeGen/AMDGPU/ctpop64.ll +++ b/llvm/test/CodeGen/AMDGPU/ctpop64.ll @@ -452,12 +452,11 @@ define amdgpu_kernel void @s_ctpop_i65(ptr addrspace(1) noalias %out, i65 %val) ; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_mov_b32 s0, s4 +; SI-NEXT: s_and_b32 s4, s8, 0xff ; SI-NEXT: s_mov_b32 s1, s5 -; SI-NEXT: s_and_b32 s4, s8, 1 -; SI-NEXT: s_mov_b32 s5, 0 -; SI-NEXT: s_bcnt1_i32_b64 s6, s[6:7] -; SI-NEXT: s_bcnt1_i32_b64 s4, s[4:5] -; SI-NEXT: s_add_i32 s4, s6, s4 +; SI-NEXT: s_bcnt1_i32_b32 s4, s4 +; SI-NEXT: s_bcnt1_i32_b64 s5, s[6:7] +; SI-NEXT: s_add_i32 s4, s5, s4 ; SI-NEXT: v_mov_b32_e32 v0, s4 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: s_endpgm @@ -470,12 +469,11 @@ define amdgpu_kernel void @s_ctpop_i65(ptr addrspace(1) noalias %out, i65 %val) ; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_mov_b32 s0, s4 +; VI-NEXT: s_and_b32 s4, s8, 0xff ; VI-NEXT: s_mov_b32 s1, s5 -; VI-NEXT: s_and_b32 s4, s8, 1 -; VI-NEXT: s_mov_b32 s5, 0 -; VI-NEXT: s_bcnt1_i32_b64 s6, s[6:7] -; VI-NEXT: s_bcnt1_i32_b64 s4, s[4:5] -; VI-NEXT: s_add_i32 s4, s6, s4 +; VI-NEXT: s_bcnt1_i32_b32 s4, s4 +; VI-NEXT: s_bcnt1_i32_b64 s5, s[6:7] +; VI-NEXT: s_add_i32 s4, s5, s4 ; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: s_endpgm diff --git a/llvm/test/CodeGen/X86/ctpop-mask.ll b/llvm/test/CodeGen/X86/ctpop-mask.ll index abbcf22f77e4..e0a96a9f9887 100644 --- a/llvm/test/CodeGen/X86/ctpop-mask.ll +++ b/llvm/test/CodeGen/X86/ctpop-mask.ll @@ -25,7 +25,7 @@ define i64 @ctpop_mask2(i64 %x) nounwind readnone { ; X64-POPCOUNT-LABEL: ctpop_mask2: ; X64-POPCOUNT: # %bb.0: ; X64-POPCOUNT-NEXT: andl $3, %edi -; X64-POPCOUNT-NEXT: popcntq %rdi, %rax +; X64-POPCOUNT-NEXT: popcntl %edi, %eax ; X64-POPCOUNT-NEXT: retq ; ; X86-NO-POPCOUNT-LABEL: ctpop_mask2: @@ -189,7 +189,7 @@ define i64 @ctpop_mask4(i64 %x) nounwind readnone { ; X64-POPCOUNT-LABEL: ctpop_mask4: ; X64-POPCOUNT: # %bb.0: ; X64-POPCOUNT-NEXT: andl $15, %edi -; X64-POPCOUNT-NEXT: popcntq %rdi, %rax +; X64-POPCOUNT-NEXT: popcntl %edi, %eax ; X64-POPCOUNT-NEXT: retq ; ; X86-NO-POPCOUNT-LABEL: ctpop_mask4: @@ -271,7 +271,7 @@ define i64 @ctpop_mask5(i64 %x) nounwind readnone { ; X64-POPCOUNT-LABEL: ctpop_mask5: ; X64-POPCOUNT: # %bb.0: ; X64-POPCOUNT-NEXT: andl $31, %edi -; X64-POPCOUNT-NEXT: popcntq %rdi, %rax +; X64-POPCOUNT-NEXT: popcntl %edi, %eax ; X64-POPCOUNT-NEXT: retq ; ; X86-NO-POPCOUNT-LABEL: ctpop_mask5: @@ -392,7 +392,7 @@ define i64 @ctpop_shifted_mask6(i64 %x) nounwind readnone { ; X64-POPCOUNT-LABEL: ctpop_shifted_mask6: ; X64-POPCOUNT: # %bb.0: ; X64-POPCOUNT-NEXT: andl $26112, %edi # imm = 0x6600 -; X64-POPCOUNT-NEXT: popcntq %rdi, %rax +; X64-POPCOUNT-NEXT: popcntl %edi, %eax ; X64-POPCOUNT-NEXT: retq ; ; X86-NO-POPCOUNT-LABEL: ctpop_shifted_mask6: @@ -556,7 +556,7 @@ define i64 @ctpop_shifted_mask8(i64 %x) nounwind readnone { ; X64-POPCOUNT-LABEL: ctpop_shifted_mask8: ; X64-POPCOUNT: # %bb.0: ; X64-POPCOUNT-NEXT: andl $65280, %edi # imm = 0xFF00 -; X64-POPCOUNT-NEXT: popcntq %rdi, %rax +; X64-POPCOUNT-NEXT: popcntl %edi, %eax ; X64-POPCOUNT-NEXT: retq ; ; X86-NO-POPCOUNT-LABEL: ctpop_shifted_mask8: -- GitLab From 29fa64f845df6b1ba3f562564ab97a07aa7077ee Mon Sep 17 00:00:00 2001 From: Kareem Ergawy Date: Tue, 6 Feb 2024 13:36:13 +0100 Subject: [PATCH 061/266] [flang][OpenMP][NFC] Outline `genOpWithBody` & `createBodyOfOp` args (#80817) This PR outlines the arguments of the open CodeGen functions into 2 separate structs. This was, in part, motivated by the delayed privatization WIP #79862 where we had to extend the signatures of both functions containing quite a bit of default values (`nullptr`, `false`). This PR does not add any new arguments yet though, just outlines the existing ones. --- flang/lib/Lower/OpenMP.cpp | 162 ++++++++++++++++++++----------------- 1 file changed, 86 insertions(+), 76 deletions(-) diff --git a/flang/lib/Lower/OpenMP.cpp b/flang/lib/Lower/OpenMP.cpp index 0a68aba16261..dad88fc1d764 100644 --- a/flang/lib/Lower/OpenMP.cpp +++ b/flang/lib/Lower/OpenMP.cpp @@ -2250,6 +2250,17 @@ createAndSetPrivatizedLoopVar(Fortran::lower::AbstractConverter &converter, return storeOp; } +struct CreateBodyOfOpInfo { + Fortran::lower::AbstractConverter &converter; + mlir::Location &loc; + Fortran::lower::pft::Evaluation &eval; + bool genNested = true; + const Fortran::parser::OmpClauseList *clauses = nullptr; + const llvm::SmallVector &args = {}; + bool outerCombined = false; + DataSharingProcessor *dsp = nullptr; +}; + /// Create the body (block) for an OpenMP Operation. /// /// \param [in] op - the operation the body belongs to. @@ -2263,13 +2274,8 @@ createAndSetPrivatizedLoopVar(Fortran::lower::AbstractConverter &converter, /// \param [in] outerCombined - is this an outer operation - prevents /// privatization. template -static void createBodyOfOp( - Op &op, Fortran::lower::AbstractConverter &converter, mlir::Location &loc, - Fortran::lower::pft::Evaluation &eval, bool genNested, - const Fortran::parser::OmpClauseList *clauses = nullptr, - const llvm::SmallVector &args = {}, - bool outerCombined = false, DataSharingProcessor *dsp = nullptr) { - fir::FirOpBuilder &firOpBuilder = converter.getFirOpBuilder(); +static void createBodyOfOp(Op &op, CreateBodyOfOpInfo info) { + fir::FirOpBuilder &firOpBuilder = info.converter.getFirOpBuilder(); auto insertMarker = [](fir::FirOpBuilder &builder) { mlir::Value undef = builder.create(builder.getUnknownLoc(), @@ -2281,22 +2287,22 @@ static void createBodyOfOp( // argument. Also update the symbol's address with the mlir argument value. // e.g. For loops the argument is the induction variable. And all further // uses of the induction variable should use this mlir value. - if (args.size()) { + if (info.args.size()) { std::size_t loopVarTypeSize = 0; - for (const Fortran::semantics::Symbol *arg : args) + for (const Fortran::semantics::Symbol *arg : info.args) loopVarTypeSize = std::max(loopVarTypeSize, arg->GetUltimate().size()); - mlir::Type loopVarType = getLoopVarType(converter, loopVarTypeSize); - llvm::SmallVector tiv(args.size(), loopVarType); - llvm::SmallVector locs(args.size(), loc); + mlir::Type loopVarType = getLoopVarType(info.converter, loopVarTypeSize); + llvm::SmallVector tiv(info.args.size(), loopVarType); + llvm::SmallVector locs(info.args.size(), info.loc); firOpBuilder.createBlock(&op.getRegion(), {}, tiv, locs); // The argument is not currently in memory, so make a temporary for the // argument, and store it there, then bind that location to the argument. mlir::Operation *storeOp = nullptr; - for (auto [argIndex, argSymbol] : llvm::enumerate(args)) { + for (auto [argIndex, argSymbol] : llvm::enumerate(info.args)) { mlir::Value indexVal = fir::getBase(op.getRegion().front().getArgument(argIndex)); - storeOp = - createAndSetPrivatizedLoopVar(converter, loc, indexVal, argSymbol); + storeOp = createAndSetPrivatizedLoopVar(info.converter, info.loc, + indexVal, argSymbol); } firOpBuilder.setInsertionPointAfter(storeOp); } else { @@ -2308,44 +2314,44 @@ static void createBodyOfOp( // If it is an unstructured region and is not the outer region of a combined // construct, create empty blocks for all evaluations. - if (eval.lowerAsUnstructured() && !outerCombined) + if (info.eval.lowerAsUnstructured() && !info.outerCombined) Fortran::lower::createEmptyRegionBlocks( - firOpBuilder, eval.getNestedEvaluations()); + firOpBuilder, info.eval.getNestedEvaluations()); // Start with privatization, so that the lowering of the nested // code will use the right symbols. constexpr bool isLoop = std::is_same_v || std::is_same_v; - bool privatize = clauses && !outerCombined; + bool privatize = info.clauses && !info.outerCombined; firOpBuilder.setInsertionPoint(marker); std::optional tempDsp; if (privatize) { - if (!dsp) { - tempDsp.emplace(converter, *clauses, eval); + if (!info.dsp) { + tempDsp.emplace(info.converter, *info.clauses, info.eval); tempDsp->processStep1(); } } if constexpr (std::is_same_v) { - threadPrivatizeVars(converter, eval); - if (clauses) { + threadPrivatizeVars(info.converter, info.eval); + if (info.clauses) { firOpBuilder.setInsertionPoint(marker); - ClauseProcessor(converter, *clauses).processCopyin(); + ClauseProcessor(info.converter, *info.clauses).processCopyin(); } } - if (genNested) { + if (info.genNested) { // genFIR(Evaluation&) tries to patch up unterminated blocks, causing // a lot of complications for our approach if the terminator generation // is delayed past this point. Insert a temporary terminator here, then // delete it. firOpBuilder.setInsertionPointToEnd(&op.getRegion().back()); - auto *temp = Fortran::lower::genOpenMPTerminator(firOpBuilder, - op.getOperation(), loc); + auto *temp = Fortran::lower::genOpenMPTerminator( + firOpBuilder, op.getOperation(), info.loc); firOpBuilder.setInsertionPointAfter(marker); - genNestedEvaluations(converter, eval); + genNestedEvaluations(info.converter, info.eval); temp->erase(); } @@ -2380,28 +2386,28 @@ static void createBodyOfOp( mlir::Block *exit = firOpBuilder.createBlock(®ion); for (mlir::Block *b : exits) { firOpBuilder.setInsertionPointToEnd(b); - firOpBuilder.create(loc, exit); + firOpBuilder.create(info.loc, exit); } return exit; }; if (auto *exitBlock = getUniqueExit(op.getRegion())) { firOpBuilder.setInsertionPointToEnd(exitBlock); - auto *term = Fortran::lower::genOpenMPTerminator(firOpBuilder, - op.getOperation(), loc); + auto *term = Fortran::lower::genOpenMPTerminator( + firOpBuilder, op.getOperation(), info.loc); // Only insert lastprivate code when there actually is an exit block. // Such a block may not exist if the nested code produced an infinite // loop (this may not make sense in production code, but a user could // write that and we should handle it). firOpBuilder.setInsertionPoint(term); if (privatize) { - if (!dsp) { + if (!info.dsp) { assert(tempDsp.has_value()); tempDsp->processStep2(op, isLoop); } else { - if (isLoop && args.size() > 0) - dsp->setLoopIV(converter.getSymbolAddress(*args[0])); - dsp->processStep2(op, isLoop); + if (isLoop && info.args.size() > 0) + info.dsp->setLoopIV(info.converter.getSymbolAddress(*info.args[0])); + info.dsp->processStep2(op, isLoop); } } } @@ -2475,17 +2481,24 @@ static void genBodyOfTargetDataOp( genNestedEvaluations(converter, eval); } +struct GenOpWithBodyInfo { + Fortran::lower::AbstractConverter &converter; + Fortran::lower::pft::Evaluation &eval; + bool genNested = false; + mlir::Location currentLocation; + bool outerCombined = false; + const Fortran::parser::OmpClauseList *clauseList = nullptr; +}; + template -static OpTy genOpWithBody(Fortran::lower::AbstractConverter &converter, - Fortran::lower::pft::Evaluation &eval, bool genNested, - mlir::Location currentLocation, bool outerCombined, - const Fortran::parser::OmpClauseList *clauseList, - Args &&...args) { - auto op = converter.getFirOpBuilder().create( - currentLocation, std::forward(args)...); - createBodyOfOp(op, converter, currentLocation, eval, genNested, - clauseList, - /*args=*/{}, outerCombined); +static OpTy genOpWithBody(GenOpWithBodyInfo info, Args &&...args) { + auto op = info.converter.getFirOpBuilder().create( + info.currentLocation, std::forward(args)...); + createBodyOfOp( + op, {info.converter, info.currentLocation, info.eval, info.genNested, + info.clauseList, + /*args*/ llvm::SmallVector{}, + info.outerCombined}); return op; } @@ -2493,11 +2506,9 @@ static mlir::omp::MasterOp genMasterOp(Fortran::lower::AbstractConverter &converter, Fortran::lower::pft::Evaluation &eval, bool genNested, mlir::Location currentLocation) { - return genOpWithBody(converter, eval, genNested, - currentLocation, - /*outerCombined=*/false, - /*clauseList=*/nullptr, - /*resultTypes=*/mlir::TypeRange()); + return genOpWithBody( + {converter, eval, genNested, currentLocation}, + /*resultTypes=*/mlir::TypeRange()); } static mlir::omp::OrderedRegionOp @@ -2505,9 +2516,8 @@ genOrderedRegionOp(Fortran::lower::AbstractConverter &converter, Fortran::lower::pft::Evaluation &eval, bool genNested, mlir::Location currentLocation) { return genOpWithBody( - converter, eval, genNested, currentLocation, - /*outerCombined=*/false, - /*clauseList=*/nullptr, /*simd=*/false); + {converter, eval, genNested, currentLocation}, + /*simd=*/false); } static mlir::omp::ParallelOp @@ -2534,7 +2544,7 @@ genParallelOp(Fortran::lower::AbstractConverter &converter, cp.processReduction(currentLocation, reductionVars, reductionDeclSymbols); return genOpWithBody( - converter, eval, genNested, currentLocation, outerCombined, &clauseList, + {converter, eval, genNested, currentLocation, outerCombined, &clauseList}, /*resultTypes=*/mlir::TypeRange(), ifClauseOperand, numThreadsClauseOperand, allocateOperands, allocatorOperands, reductionVars, @@ -2553,8 +2563,8 @@ genSectionOp(Fortran::lower::AbstractConverter &converter, // Currently only private/firstprivate clause is handled, and // all privatization is done within `omp.section` operations. return genOpWithBody( - converter, eval, genNested, currentLocation, - /*outerCombined=*/false, §ionsClauseList); + {converter, eval, genNested, currentLocation, + /*outerCombined=*/false, §ionsClauseList}); } static mlir::omp::SingleOp @@ -2574,9 +2584,9 @@ genSingleOp(Fortran::lower::AbstractConverter &converter, ClauseProcessor(converter, endClauseList).processNowait(nowaitAttr); return genOpWithBody( - converter, eval, genNested, currentLocation, - /*outerCombined=*/false, &beginClauseList, allocateOperands, - allocatorOperands, nowaitAttr); + {converter, eval, genNested, currentLocation, + /*outerCombined=*/false, &beginClauseList}, + allocateOperands, allocatorOperands, nowaitAttr); } static mlir::omp::TaskOp @@ -2607,9 +2617,9 @@ genTaskOp(Fortran::lower::AbstractConverter &converter, currentLocation, llvm::omp::Directive::OMPD_task); return genOpWithBody( - converter, eval, genNested, currentLocation, - /*outerCombined=*/false, &clauseList, ifClauseOperand, finalClauseOperand, - untiedAttr, mergeableAttr, + {converter, eval, genNested, currentLocation, + /*outerCombined=*/false, &clauseList}, + ifClauseOperand, finalClauseOperand, untiedAttr, mergeableAttr, /*in_reduction_vars=*/mlir::ValueRange(), /*in_reductions=*/nullptr, priorityClauseOperand, dependTypeOperands.empty() @@ -2630,8 +2640,8 @@ genTaskGroupOp(Fortran::lower::AbstractConverter &converter, cp.processTODO( currentLocation, llvm::omp::Directive::OMPD_taskgroup); return genOpWithBody( - converter, eval, genNested, currentLocation, - /*outerCombined=*/false, &clauseList, + {converter, eval, genNested, currentLocation, + /*outerCombined=*/false, &clauseList}, /*task_reduction_vars=*/mlir::ValueRange(), /*task_reductions=*/nullptr, allocateOperands, allocatorOperands); } @@ -3014,7 +3024,7 @@ genTeamsOp(Fortran::lower::AbstractConverter &converter, currentLocation, llvm::omp::Directive::OMPD_teams); return genOpWithBody( - converter, eval, genNested, currentLocation, outerCombined, &clauseList, + {converter, eval, genNested, currentLocation, outerCombined, &clauseList}, /*num_teams_lower=*/nullptr, numTeamsClauseOperand, ifClauseOperand, threadLimitClauseOperand, allocateOperands, allocatorOperands, reductionVars, @@ -3258,9 +3268,10 @@ createSimdLoop(Fortran::lower::AbstractConverter &converter, auto *nestedEval = getCollapsedLoopEval( eval, Fortran::lower::getCollapseValue(loopOpClauseList)); - createBodyOfOp(simdLoopOp, converter, loc, *nestedEval, - /*genNested=*/true, &loopOpClauseList, - iv, /*outer=*/false, &dsp); + createBodyOfOp( + simdLoopOp, {converter, loc, *nestedEval, + /*genNested=*/true, &loopOpClauseList, iv, + /*outerCombined=*/false, &dsp}); } static void createWsLoop(Fortran::lower::AbstractConverter &converter, @@ -3333,9 +3344,10 @@ static void createWsLoop(Fortran::lower::AbstractConverter &converter, auto *nestedEval = getCollapsedLoopEval( eval, Fortran::lower::getCollapseValue(beginClauseList)); - createBodyOfOp(wsLoopOp, converter, loc, *nestedEval, - /*genNested=*/true, &beginClauseList, iv, - /*outer=*/false, &dsp); + createBodyOfOp(wsLoopOp, + {converter, loc, *nestedEval, + /*genNested=*/true, &beginClauseList, iv, + /*outerCombined=*/false, &dsp}); } static void createSimdWsLoop( @@ -3616,8 +3628,8 @@ genOMP(Fortran::lower::AbstractConverter &converter, currentLocation, mlir::FlatSymbolRefAttr::get(firOpBuilder.getContext(), global.getSymName())); }(); - createBodyOfOp(criticalOp, converter, currentLocation, - eval, /*genNested=*/true); + createBodyOfOp(criticalOp, + {converter, currentLocation, eval}); } static void @@ -3659,10 +3671,8 @@ genOMP(Fortran::lower::AbstractConverter &converter, } // SECTIONS construct - genOpWithBody(converter, eval, - /*genNested=*/false, currentLocation, - /*outerCombined=*/false, - /*clauseList=*/nullptr, + genOpWithBody({converter, eval, + /*genNested=*/false, currentLocation}, /*reduction_vars=*/mlir::ValueRange(), /*reductions=*/nullptr, allocateOperands, allocatorOperands, nowaitClauseOperand); -- GitLab From 2e3de997ab7cd8728c484bc39e24fecbb97dfae8 Mon Sep 17 00:00:00 2001 From: David Green Date: Tue, 6 Feb 2024 12:39:48 +0000 Subject: [PATCH 062/266] [DAG] Generalize setcc(setcc) fold to use known bits. If we have a `SETCC (SETCC), 0, NE` and ZeroOrOneBooleanContent, we can remove the outer setcc as it will produce the same value as the inner. This can be generalized to anything where the top bits are known to be 0, as the value will remain as 1 or 0. --- .../CodeGen/SelectionDAG/TargetLowering.cpp | 22 +++++---- llvm/test/CodeGen/AArch64/setcc_knownbits.ll | 5 +- .../CodeGen/WebAssembly/xor_reassociate.ll | 2 +- llvm/test/CodeGen/X86/lzcnt-cmp.ll | 46 +++++++++---------- llvm/test/CodeGen/X86/umul_fix_sat.ll | 14 +++--- llvm/test/CodeGen/X86/xor.ll | 11 +++-- 6 files changed, 52 insertions(+), 48 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index b15f62bc3aae..a4987de43779 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -4718,21 +4718,25 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, DAG.getConstant(C1 & Imm, dl, ExtDstTy), Cond); } else if ((N1C->isZero() || N1C->isOne()) && (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { - // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC - if (N0.getOpcode() == ISD::SETCC && + // SETCC (X), [0|1], [EQ|NE] -> X if X is known 0/1. i1 types are + // excluded as they are handled below whilst checking for foldBooleans. + if ((N0.getOpcode() == ISD::SETCC || VT.getScalarType() != MVT::i1) && isTypeLegal(VT) && VT.bitsLE(N0.getValueType()) && (N0.getValueType() == MVT::i1 || - getBooleanContents(N0.getOperand(0).getValueType()) == - ZeroOrOneBooleanContent)) { + getBooleanContents(N0.getValueType()) == ZeroOrOneBooleanContent) && + DAG.MaskedValueIsZero( + N0, APInt::getBitsSetFrom(N0.getValueSizeInBits(), 1))) { bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (!N1C->isOne()); if (TrueWhenTrue) return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); // Invert the condition. - ISD::CondCode CC = cast(N0.getOperand(2))->get(); - CC = ISD::getSetCCInverse(CC, N0.getOperand(0).getValueType()); - if (DCI.isBeforeLegalizeOps() || - isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType())) - return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); + if (N0.getOpcode() == ISD::SETCC) { + ISD::CondCode CC = cast(N0.getOperand(2))->get(); + CC = ISD::getSetCCInverse(CC, N0.getOperand(0).getValueType()); + if (DCI.isBeforeLegalizeOps() || + isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType())) + return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); + } } if ((N0.getOpcode() == ISD::XOR || diff --git a/llvm/test/CodeGen/AArch64/setcc_knownbits.ll b/llvm/test/CodeGen/AArch64/setcc_knownbits.ll index af5c1586a4c6..9e9c814be026 100644 --- a/llvm/test/CodeGen/AArch64/setcc_knownbits.ll +++ b/llvm/test/CodeGen/AArch64/setcc_knownbits.ll @@ -49,9 +49,8 @@ define i1 @lshr_ctlz_undef_cmpeq_one_i64(i64 %in) { ; CHECK-LABEL: lshr_ctlz_undef_cmpeq_one_i64: ; CHECK: // %bb.0: ; CHECK-NEXT: clz x8, x0 -; CHECK-NEXT: lsr x8, x8, #6 -; CHECK-NEXT: cmp x8, #1 -; CHECK-NEXT: cset w0, eq +; CHECK-NEXT: lsr x0, x8, #6 +; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 ; CHECK-NEXT: ret %ctlz = call i64 @llvm.ctlz.i64(i64 %in, i1 -1) %lshr = lshr i64 %ctlz, 6 diff --git a/llvm/test/CodeGen/WebAssembly/xor_reassociate.ll b/llvm/test/CodeGen/WebAssembly/xor_reassociate.ll index 9ef9c14084a7..3dd8463d9dd1 100644 --- a/llvm/test/CodeGen/WebAssembly/xor_reassociate.ll +++ b/llvm/test/CodeGen/WebAssembly/xor_reassociate.ll @@ -17,7 +17,7 @@ define i32 @reassociate_xor(float %x, float %y) { ; CHECK-NEXT: local.get 0 ; CHECK-NEXT: f32.const 0x1p-23 ; CHECK-NEXT: f32.gt -; CHECK-NEXT: i32.ne +; CHECK-NEXT: i32.xor ; CHECK-NEXT: br_if 0 # 0: down to label0 ; CHECK-NEXT: # %bb.1: # %if.then.i ; CHECK-NEXT: i32.const 0 diff --git a/llvm/test/CodeGen/X86/lzcnt-cmp.ll b/llvm/test/CodeGen/X86/lzcnt-cmp.ll index c1cce6f5d8ca..6c8d5c9d55a6 100644 --- a/llvm/test/CodeGen/X86/lzcnt-cmp.ll +++ b/llvm/test/CodeGen/X86/lzcnt-cmp.ll @@ -50,35 +50,33 @@ define i1 @lshr_ctlz_undef_cmpeq_one_i64(i64 %in) nounwind { ; X86-BSR-NEXT: xorl $31, %eax ; X86-BSR-NEXT: addl $32, %eax ; X86-BSR-NEXT: .LBB1_2: -; X86-BSR-NEXT: testl $-64, %eax -; X86-BSR-NEXT: setne %al +; X86-BSR-NEXT: shrl $6, %eax +; X86-BSR-NEXT: # kill: def $al killed $al killed $eax ; X86-BSR-NEXT: retl ; ; X86-LZCNT-LABEL: lshr_ctlz_undef_cmpeq_one_i64: ; X86-LZCNT: # %bb.0: -; X86-LZCNT-NEXT: lzcntl {{[0-9]+}}(%esp), %eax -; X86-LZCNT-NEXT: addl $32, %eax -; X86-LZCNT-NEXT: xorl %ecx, %ecx +; X86-LZCNT-NEXT: lzcntl {{[0-9]+}}(%esp), %ecx +; X86-LZCNT-NEXT: addl $32, %ecx +; X86-LZCNT-NEXT: xorl %eax, %eax ; X86-LZCNT-NEXT: cmpl $0, {{[0-9]+}}(%esp) -; X86-LZCNT-NEXT: cmovel %eax, %ecx -; X86-LZCNT-NEXT: testb $64, %cl -; X86-LZCNT-NEXT: setne %al +; X86-LZCNT-NEXT: cmovel %ecx, %eax +; X86-LZCNT-NEXT: shrl $6, %eax +; X86-LZCNT-NEXT: # kill: def $al killed $al killed $eax ; X86-LZCNT-NEXT: retl ; ; X64-BSR-LABEL: lshr_ctlz_undef_cmpeq_one_i64: ; X64-BSR: # %bb.0: ; X64-BSR-NEXT: bsrq %rdi, %rax ; X64-BSR-NEXT: shrl $6, %eax -; X64-BSR-NEXT: cmpl $1, %eax -; X64-BSR-NEXT: sete %al +; X64-BSR-NEXT: # kill: def $al killed $al killed $rax ; X64-BSR-NEXT: retq ; ; X64-LZCNT-LABEL: lshr_ctlz_undef_cmpeq_one_i64: ; X64-LZCNT: # %bb.0: ; X64-LZCNT-NEXT: lzcntq %rdi, %rax ; X64-LZCNT-NEXT: shrl $6, %eax -; X64-LZCNT-NEXT: cmpl $1, %eax -; X64-LZCNT-NEXT: sete %al +; X64-LZCNT-NEXT: # kill: def $al killed $al killed $rax ; X64-LZCNT-NEXT: retq %ctlz = call i64 @llvm.ctlz.i64(i64 %in, i1 -1) %lshr = lshr i64 %ctlz, 6 @@ -131,33 +129,33 @@ define i1 @lshr_ctlz_undef_cmpne_zero_i64(i64 %in) nounwind { ; X86-BSR-NEXT: xorl $31, %eax ; X86-BSR-NEXT: addl $32, %eax ; X86-BSR-NEXT: .LBB3_2: -; X86-BSR-NEXT: testl $-64, %eax -; X86-BSR-NEXT: setne %al +; X86-BSR-NEXT: shrl $6, %eax +; X86-BSR-NEXT: # kill: def $al killed $al killed $eax ; X86-BSR-NEXT: retl ; ; X86-LZCNT-LABEL: lshr_ctlz_undef_cmpne_zero_i64: ; X86-LZCNT: # %bb.0: -; X86-LZCNT-NEXT: lzcntl {{[0-9]+}}(%esp), %eax -; X86-LZCNT-NEXT: addl $32, %eax -; X86-LZCNT-NEXT: xorl %ecx, %ecx +; X86-LZCNT-NEXT: lzcntl {{[0-9]+}}(%esp), %ecx +; X86-LZCNT-NEXT: addl $32, %ecx +; X86-LZCNT-NEXT: xorl %eax, %eax ; X86-LZCNT-NEXT: cmpl $0, {{[0-9]+}}(%esp) -; X86-LZCNT-NEXT: cmovel %eax, %ecx -; X86-LZCNT-NEXT: testb $64, %cl -; X86-LZCNT-NEXT: setne %al +; X86-LZCNT-NEXT: cmovel %ecx, %eax +; X86-LZCNT-NEXT: shrl $6, %eax +; X86-LZCNT-NEXT: # kill: def $al killed $al killed $eax ; X86-LZCNT-NEXT: retl ; ; X64-BSR-LABEL: lshr_ctlz_undef_cmpne_zero_i64: ; X64-BSR: # %bb.0: ; X64-BSR-NEXT: bsrq %rdi, %rax -; X64-BSR-NEXT: testl $-64, %eax -; X64-BSR-NEXT: setne %al +; X64-BSR-NEXT: shrl $6, %eax +; X64-BSR-NEXT: # kill: def $al killed $al killed $rax ; X64-BSR-NEXT: retq ; ; X64-LZCNT-LABEL: lshr_ctlz_undef_cmpne_zero_i64: ; X64-LZCNT: # %bb.0: ; X64-LZCNT-NEXT: lzcntq %rdi, %rax -; X64-LZCNT-NEXT: testb $64, %al -; X64-LZCNT-NEXT: setne %al +; X64-LZCNT-NEXT: shrl $6, %eax +; X64-LZCNT-NEXT: # kill: def $al killed $al killed $rax ; X64-LZCNT-NEXT: retq %ctlz = call i64 @llvm.ctlz.i64(i64 %in, i1 -1) %lshr = lshr i64 %ctlz, 6 diff --git a/llvm/test/CodeGen/X86/umul_fix_sat.ll b/llvm/test/CodeGen/X86/umul_fix_sat.ll index 6b6845147e04..8c7078c72632 100644 --- a/llvm/test/CodeGen/X86/umul_fix_sat.ll +++ b/llvm/test/CodeGen/X86/umul_fix_sat.ll @@ -517,15 +517,13 @@ define i64 @func8(i64 %x, i64 %y) nounwind { ; X86-NEXT: adcl $0, %ecx ; X86-NEXT: addl %ebp, %edx ; X86-NEXT: adcl $0, %ecx +; X86-NEXT: shldl $1, %edx, %ecx ; X86-NEXT: shrdl $31, %edx, %eax -; X86-NEXT: movl %edx, %esi -; X86-NEXT: shrl $31, %esi -; X86-NEXT: xorl %edi, %edi -; X86-NEXT: negl %esi -; X86-NEXT: sbbl %edi, %edi -; X86-NEXT: orl %edi, %eax -; X86-NEXT: shrdl $31, %ecx, %edx -; X86-NEXT: orl %edi, %edx +; X86-NEXT: testl $-2147483648, %edx # imm = 0x80000000 +; X86-NEXT: movl $-1, %edx +; X86-NEXT: cmovnel %edx, %eax +; X86-NEXT: cmovnel %edx, %ecx +; X86-NEXT: movl %ecx, %edx ; X86-NEXT: popl %esi ; X86-NEXT: popl %edi ; X86-NEXT: popl %ebx diff --git a/llvm/test/CodeGen/X86/xor.ll b/llvm/test/CodeGen/X86/xor.ll index 2072568b7ba7..8c8b7cc51610 100644 --- a/llvm/test/CodeGen/X86/xor.ll +++ b/llvm/test/CodeGen/X86/xor.ll @@ -403,14 +403,19 @@ define i32 @PR17487(i1 %tobool) { ; ; X64-LIN-LABEL: PR17487: ; X64-LIN: # %bb.0: -; X64-LIN-NEXT: movl %edi, %eax -; X64-LIN-NEXT: andl $1, %eax +; X64-LIN-NEXT: movd %edi, %xmm0 +; X64-LIN-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1] +; X64-LIN-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; X64-LIN-NEXT: pextrw $4, %xmm0, %eax ; X64-LIN-NEXT: retq ; ; X64-WIN-LABEL: PR17487: ; X64-WIN: # %bb.0: -; X64-WIN-NEXT: andb $1, %cl ; X64-WIN-NEXT: movzbl %cl, %eax +; X64-WIN-NEXT: movd %eax, %xmm0 +; X64-WIN-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1] +; X64-WIN-NEXT: pand __xmm@00000000000000010000000000000001(%rip), %xmm0 +; X64-WIN-NEXT: pextrw $4, %xmm0, %eax ; X64-WIN-NEXT: retq %tmp = insertelement <2 x i1> undef, i1 %tobool, i32 1 %tmp1 = zext <2 x i1> %tmp to <2 x i64> -- GitLab From a2e5287d5a499521aaf093f812cbedcbbc2a4bc8 Mon Sep 17 00:00:00 2001 From: Jacek Caban Date: Tue, 6 Feb 2024 13:47:58 +0100 Subject: [PATCH 063/266] [llvm-readobj][Object][COFF] Print COFF import library symbol export name. (#78769) getExportName implementation is based on lld-link. In its current form, it's mostly about convenience, but it will be more useful for EXPORTAS support, for which export name is not possible to deduce from other printed properties. --- lld/test/COFF/def-export-cpp.s | 1 + lld/test/COFF/def-export-stdcall.s | 13 ++++++++++ lld/test/COFF/dllexport.s | 4 +++ llvm/include/llvm/Object/COFFImportFile.h | 1 + llvm/lib/Object/COFFImportFile.cpp | 26 +++++++++++++++++++ .../tools/llvm-dlltool/coff-decorated.def | 7 +++++ llvm/test/tools/llvm-dlltool/coff-exports.def | 3 +++ llvm/test/tools/llvm-dlltool/coff-noname.def | 1 + .../llvm-dlltool/no-leading-underscore.def | 2 ++ llvm/test/tools/llvm-lib/arm64ec-implib.test | 2 ++ .../tools/llvm-readobj/COFF/file-headers.test | 1 + llvm/tools/llvm-readobj/COFFImportDumper.cpp | 3 +++ 12 files changed, 64 insertions(+) diff --git a/lld/test/COFF/def-export-cpp.s b/lld/test/COFF/def-export-cpp.s index e00b35b1c5b3..370b8ddba410 100644 --- a/lld/test/COFF/def-export-cpp.s +++ b/lld/test/COFF/def-export-cpp.s @@ -10,6 +10,7 @@ # IMPLIB: File: foo.dll # IMPLIB: Name type: undecorate +# IMPLIB-NEXT: Export name: GetPathOnDisk # IMPLIB-NEXT: Symbol: __imp_?GetPathOnDisk@@YA_NPEA_W@Z # IMPLIB-NEXT: Symbol: ?GetPathOnDisk@@YA_NPEA_W@Z diff --git a/lld/test/COFF/def-export-stdcall.s b/lld/test/COFF/def-export-stdcall.s index f015e205c74a..7e4e04c77cbe 100644 --- a/lld/test/COFF/def-export-stdcall.s +++ b/lld/test/COFF/def-export-stdcall.s @@ -6,15 +6,19 @@ # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix UNDECORATED-EXPORTS %s # UNDECORATED-IMPLIB: Name type: noprefix +# UNDECORATED-IMPLIB-NEXT: Export name: _underscored # UNDECORATED-IMPLIB-NEXT: __imp___underscored # UNDECORATED-IMPLIB-NEXT: __underscored # UNDECORATED-IMPLIB: Name type: undecorate +# UNDECORATED-IMPLIB-NEXT: Export name: fastcall # UNDECORATED-IMPLIB-NEXT: __imp_@fastcall@8 # UNDECORATED-IMPLIB-NEXT: fastcall@8 # UNDECORATED-IMPLIB: Name type: undecorate +# UNDECORATED-IMPLIB-NEXT: Export name: stdcall # UNDECORATED-IMPLIB-NEXT: __imp__stdcall@8 # UNDECORATED-IMPLIB-NEXT: _stdcall@8 # UNDECORATED-IMPLIB: Name type: undecorate +# UNDECORATED-IMPLIB-NEXT: Export name: vectorcall # UNDECORATED-IMPLIB-NEXT: __imp_vectorcall@@8 # UNDECORATED-IMPLIB-NEXT: vectorcall@@8 @@ -30,12 +34,15 @@ # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix DECORATED-EXPORTS %s # DECORATED-IMPLIB: Name type: name +# DECORATED-IMPLIB-NEXT: Export name: @fastcall@8 # DECORATED-IMPLIB-NEXT: __imp_@fastcall@8 # DECORATED-IMPLIB-NEXT: @fastcall@8 # DECORATED-IMPLIB: Name type: name +# DECORATED-IMPLIB-NEXT: Export name: _stdcall@8 # DECORATED-IMPLIB-NEXT: __imp__stdcall@8 # DECORATED-IMPLIB-NEXT: _stdcall@8 # DECORATED-IMPLIB: Name type: name +# DECORATED-IMPLIB-NEXT: Export name: vectorcall@@8 # DECORATED-IMPLIB-NEXT: __imp_vectorcall@@8 # DECORATED-IMPLIB-NEXT: vectorcall@@8 @@ -51,14 +58,17 @@ # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix DECORATED-MINGW-EXPORTS %s # DECORATED-MINGW-IMPLIB: Name type: name +# DECORATED-MINGW-IMPLIB-NEXT: Export name: @fastcall@8 # DECORATED-MINGW-IMPLIB-NEXT: __imp_@fastcall@8 # DECORATED-MINGW-IMPLIB-NEXT: fastcall@8 # DECORATED-MINGW-IMPLIB: Name type: noprefix +# DECORATED-MINGW-IMPLIB-NEXT: Export name: stdcall@8 # DECORATED-MINGW-IMPLIB-NEXT: __imp__stdcall@8 # DECORATED-MINGW-IMPLIB-NEXT: _stdcall@8 # GNU tools don't support vectorcall, but this test is just to track that # lld's behaviour remains consistent over time. # DECORATED-MINGW-IMPLIB: Name type: name +# DECORATED-MINGW-IMPLIB-NEXT: Export name: vectorcall@@8 # DECORATED-MINGW-IMPLIB-NEXT: __imp_vectorcall@@8 # DECORATED-MINGW-IMPLIB-NEXT: vectorcall@@8 @@ -75,14 +85,17 @@ # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix MINGW-KILL-AT-EXPORTS %s # MINGW-KILL-AT-IMPLIB: Name type: noprefix +# MINGW-KILL-AT-IMPLIB: Export name: fastcall # MINGW-KILL-AT-IMPLIB: __imp__fastcall # MINGW-KILL-AT-IMPLIB-NEXT: _fastcall # MINGW-KILL-AT-IMPLIB: Name type: noprefix +# MINGW-KILL-AT-IMPLIB-NEXT: Export name: stdcall # MINGW-KILL-AT-IMPLIB-NEXT: __imp__stdcall # MINGW-KILL-AT-IMPLIB-NEXT: _stdcall # GNU tools don't support vectorcall, but this test is just to track that # lld's behaviour remains consistent over time. # MINGW-KILL-AT-IMPLIB: Name type: noprefix +# MINGW-KILL-AT-IMPLIB-NEXT: Export name: vectorcall # MINGW-KILL-AT-IMPLIB-NEXT: __imp__vectorcall # MINGW-KILL-AT-IMPLIB-NEXT: _vectorcall diff --git a/lld/test/COFF/dllexport.s b/lld/test/COFF/dllexport.s index a238b70ce1b4..b04ebc3a33c3 100644 --- a/lld/test/COFF/dllexport.s +++ b/lld/test/COFF/dllexport.s @@ -6,15 +6,19 @@ # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix DECORATED-EXPORTS %s # DECORATED-IMPLIB: Name type: name +# DECORATED-IMPLIB-NEXT: Export name: @fastcall@8 # DECORATED-IMPLIB-NEXT: __imp_@fastcall@8 # DECORATED-IMPLIB-NEXT: @fastcall@8 # DECORATED-IMPLIB: Name type: name +# DECORATED-IMPLIB-NEXT: Export name: _stdcall@8 # DECORATED-IMPLIB-NEXT: __imp__stdcall@8 # DECORATED-IMPLIB-NEXT: _stdcall@8 # DECORATED-IMPLIB: Name type: noprefix +# DECORATED-IMPLIB-NEXT: Export name: _underscored # DECORATED-IMPLIB-NEXT: __imp___underscored # DECORATED-IMPLIB-NEXT: __underscored # DECORATED-IMPLIB: Name type: name +# DECORATED-IMPLIB-NEXT: Export name: vectorcall@@8 # DECORATED-IMPLIB-NEXT: __imp_vectorcall@@8 # DECORATED-IMPLIB-NEXT: vectorcall@@8 diff --git a/llvm/include/llvm/Object/COFFImportFile.h b/llvm/include/llvm/Object/COFFImportFile.h index edc836ff0348..45a4a795fd19 100644 --- a/llvm/include/llvm/Object/COFFImportFile.h +++ b/llvm/include/llvm/Object/COFFImportFile.h @@ -66,6 +66,7 @@ public: uint16_t getMachine() const { return getCOFFImportHeader()->Machine; } StringRef getFileFormatName() const; + StringRef getExportName() const; private: bool isData() const { diff --git a/llvm/lib/Object/COFFImportFile.cpp b/llvm/lib/Object/COFFImportFile.cpp index 60556c149bf7..d7d26f4f4180 100644 --- a/llvm/lib/Object/COFFImportFile.cpp +++ b/llvm/lib/Object/COFFImportFile.cpp @@ -52,6 +52,32 @@ StringRef COFFImportFile::getFileFormatName() const { } } +StringRef COFFImportFile::getExportName() const { + const coff_import_header *hdr = getCOFFImportHeader(); + StringRef name = Data.getBuffer().substr(sizeof(*hdr)).split('\0').first; + + auto ltrim1 = [](StringRef s, StringRef chars) { + return !s.empty() && chars.contains(s[0]) ? s.substr(1) : s; + }; + + switch (hdr->getNameType()) { + case IMPORT_ORDINAL: + name = ""; + break; + case IMPORT_NAME_NOPREFIX: + name = ltrim1(name, "?@_"); + break; + case IMPORT_NAME_UNDECORATE: + name = ltrim1(name, "?@_"); + name = name.substr(0, name.find('@')); + break; + default: + break; + } + + return name; +} + static uint16_t getImgRelRelocation(MachineTypes Machine) { switch (Machine) { default: diff --git a/llvm/test/tools/llvm-dlltool/coff-decorated.def b/llvm/test/tools/llvm-dlltool/coff-decorated.def index 856804686168..fc81f23d09d6 100644 --- a/llvm/test/tools/llvm-dlltool/coff-decorated.def +++ b/llvm/test/tools/llvm-dlltool/coff-decorated.def @@ -14,25 +14,32 @@ OtherStdcallExportName@4=CdeclInternalFunction CdeclExportName=StdcallInternalFunction@4 ; CHECK: Name type: noprefix +; CHECK-NEXT: Export name: CdeclFunction ; CHECK-NEXT: Symbol: __imp__CdeclFunction ; CHECK-NEXT: Symbol: _CdeclFunction ; CHECK: Name type: undecorate +; CHECK-NEXT: Export name: StdcallFunction ; CHECK-NEXT: Symbol: __imp__StdcallFunction@4 ; CHECK-NEXT: Symbol: _StdcallFunction@4 ; CHECK: Name type: undecorate +; CHECK-NEXT: Export name: FastcallFunction ; CHECK-NEXT: Symbol: __imp_@FastcallFunction@4 ; CHECK-NEXT: Symbol: @FastcallFunction@4 ; CHECK: Name type: name +; CHECK-NEXT: Export name: ??_7exception@@6B@ ; CHECK-NEXT: Symbol: __imp_??_7exception@@6B@ ; CHECK-NEXT: Symbol: ??_7exception@@6B@ ; CHECK-NM: W _StdcallAlias@4 ; CHECK-NM: U _StdcallFunction@4 ; CHECK: Name type: undecorate +; CHECK-NEXT: Export name: StdcallExportName ; CHECK-NEXT: Symbol: __imp__StdcallExportName@4{{$}} ; CHECK-NEXT: Symbol: _StdcallExportName@4{{$}} ; CHECK: Name type: undecorate +; CHECK-NEXT: Export name: OtherStdcallExportName ; CHECK-NEXT: Symbol: __imp__OtherStdcallExportName@4{{$}} ; CHECK-NEXT: Symbol: _OtherStdcallExportName@4{{$}} ; CHECK: Name type: noprefix +; CHECK-NEXT: Export name: CdeclExportName ; CHECK-NEXT: Symbol: __imp__CdeclExportName ; CHECK-NEXT: Symbol: _CdeclExportName diff --git a/llvm/test/tools/llvm-dlltool/coff-exports.def b/llvm/test/tools/llvm-dlltool/coff-exports.def index 57c557446021..267424db1b8c 100644 --- a/llvm/test/tools/llvm-dlltool/coff-exports.def +++ b/llvm/test/tools/llvm-dlltool/coff-exports.def @@ -17,12 +17,15 @@ AnotherFunction ; CHECK-ARM64: Format: COFF-import-file-ARM64 ; CHECK: Type: code ; CHECK: Name type: name +; CHECK-NEXT: Export name: TestFunction1 ; CHECK-NEXT: Symbol: __imp_TestFunction1 ; CHECK-NEXT: Symbol: TestFunction1 ; CHECK: Name type: name +; CHECK-NEXT: Export name: TestFunction2 ; CHECK-NEXT: Symbol: __imp_TestFunction2{{$}} ; CHECK-NEXT: Symbol: TestFunction2{{$}} ; CHECK: Name type: name +; CHECK-NEXT: Export name: TestFunction3 ; CHECK-NEXT: Symbol: __imp_TestFunction3{{$}} ; CHECK-NEXT: Symbol: TestFunction3{{$}} diff --git a/llvm/test/tools/llvm-dlltool/coff-noname.def b/llvm/test/tools/llvm-dlltool/coff-noname.def index 27e60efbd2d8..7cb05846ce28 100644 --- a/llvm/test/tools/llvm-dlltool/coff-noname.def +++ b/llvm/test/tools/llvm-dlltool/coff-noname.def @@ -12,5 +12,6 @@ ByNameFunction ; CHECK-NEXT: Symbol: __imp__ByOrdinalFunction ; CHECK-NEXT: Symbol: _ByOrdinalFunction ; CHECK: Name type: noprefix +; CHECK-NEXT: Export name: ByNameFunction ; CHECK-NEXT: Symbol: __imp__ByNameFunction ; CHECK-NEXT: Symbol: _ByNameFunction diff --git a/llvm/test/tools/llvm-dlltool/no-leading-underscore.def b/llvm/test/tools/llvm-dlltool/no-leading-underscore.def index 6b78e15d2b5f..9c5e77ca29a8 100644 --- a/llvm/test/tools/llvm-dlltool/no-leading-underscore.def +++ b/llvm/test/tools/llvm-dlltool/no-leading-underscore.def @@ -9,9 +9,11 @@ alias == func DecoratedFunction@4 ; CHECK: Name type: name +; CHECK-NEXT: Export name: func ; CHECK-NEXT: Symbol: __imp_func ; CHECK-NEXT: Symbol: func ; CHECK: Name type: undecorate +; CHECK-NEXT: Export name: DecoratedFunction ; CHECK-NEXT: Symbol: __imp_DecoratedFunction@4 ; CHECK-NEXT: Symbol: DecoratedFunction@4 diff --git a/llvm/test/tools/llvm-lib/arm64ec-implib.test b/llvm/test/tools/llvm-lib/arm64ec-implib.test index 2672f8d38b7f..4250c775daa6 100644 --- a/llvm/test/tools/llvm-lib/arm64ec-implib.test +++ b/llvm/test/tools/llvm-lib/arm64ec-implib.test @@ -36,6 +36,7 @@ READOBJ-NEXT: File: test.dll READOBJ-NEXT: Format: COFF-import-file-ARM64EC READOBJ-NEXT: Type: code READOBJ-NEXT: Name type: name +READOBJ-NEXT: Export name: funcexp READOBJ-NEXT: Symbol: __imp_funcexp READOBJ-NEXT: Symbol: funcexp READOBJ-EMPTY: @@ -43,6 +44,7 @@ READOBJ-NEXT: File: test.dll READOBJ-NEXT: Format: COFF-import-file-ARM64EC READOBJ-NEXT: Type: data READOBJ-NEXT: Name type: name +READOBJ-NEXT: Export name: dataexp READOBJ-NEXT: Symbol: __imp_dataexp Creating a new lib containing the existing lib: diff --git a/llvm/test/tools/llvm-readobj/COFF/file-headers.test b/llvm/test/tools/llvm-readobj/COFF/file-headers.test index b83a6cf5b972..32f39e196b00 100644 --- a/llvm/test/tools/llvm-readobj/COFF/file-headers.test +++ b/llvm/test/tools/llvm-readobj/COFF/file-headers.test @@ -323,6 +323,7 @@ symbols: # IMPORTLIB:Format: COFF-import-file-i386 # IMPORTLIB-NEXT:Type: code # IMPORTLIB-NEXT:Name type: noprefix +# IMPORTLIB-NEXT:Export name: func # IMPORTLIB-NEXT:Symbol: __imp__func # IMPORTLIB-NEXT:Symbol: _func # IMPORTLIB-NOT:{{.}} diff --git a/llvm/tools/llvm-readobj/COFFImportDumper.cpp b/llvm/tools/llvm-readobj/COFFImportDumper.cpp index 8aedc310ae3a..656ca32f03a7 100644 --- a/llvm/tools/llvm-readobj/COFFImportDumper.cpp +++ b/llvm/tools/llvm-readobj/COFFImportDumper.cpp @@ -47,6 +47,9 @@ void dumpCOFFImportFile(const COFFImportFile *File, ScopedPrinter &Writer) { break; } + if (H->getNameType() != COFF::IMPORT_ORDINAL) + Writer.printString("Export name", File->getExportName()); + for (const object::BasicSymbolRef &Sym : File->symbols()) { raw_ostream &OS = Writer.startLine(); OS << "Symbol: "; -- GitLab From a18e92d020b895b712175a3b13a3d021608115a7 Mon Sep 17 00:00:00 2001 From: Mariya Podchishchaeva Date: Tue, 6 Feb 2024 15:57:35 +0300 Subject: [PATCH 064/266] [clang] Fix unexpected `-Wconstant-logical-operand` in C23 (#80724) C23 has `bool`, but logical operators still return int. Check that we're not in C to avoid false-positive -Wconstant-logical-operand. Fixes https://github.com/llvm/llvm-project/issues/64356 --- clang/docs/ReleaseNotes.rst | 4 ++++ clang/lib/Sema/SemaExpr.cpp | 2 +- clang/test/Sema/warn-int-in-bool-context.c | 11 +++++++++++ 3 files changed, 16 insertions(+), 1 deletion(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 4d57ea4fd55b..802c44b6c860 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -164,6 +164,10 @@ Bug Fixes in This Version - Clang now accepts qualified partial/explicit specializations of variable templates that are not nominable in the lookup context of the specialization. +- Clang now doesn't produce false-positive warning `-Wconstant-logical-operand` + for logical operators in C23. + Fixes (`#64356 `_). + Bug Fixes to Compiler Builtins ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp index d15278bce5a6..4049ab3bf6ca 100644 --- a/clang/lib/Sema/SemaExpr.cpp +++ b/clang/lib/Sema/SemaExpr.cpp @@ -14073,7 +14073,7 @@ inline QualType Sema::CheckLogicalOperands(ExprResult &LHS, ExprResult &RHS, Expr::EvalResult EVResult; if (RHS.get()->EvaluateAsInt(EVResult, Context)) { llvm::APSInt Result = EVResult.Val.getInt(); - if ((getLangOpts().Bool && !RHS.get()->getType()->isBooleanType() && + if ((getLangOpts().CPlusPlus && !RHS.get()->getType()->isBooleanType() && !RHS.get()->getExprLoc().isMacroID()) || (Result != 0 && Result != 1)) { Diag(Loc, diag::warn_logical_instead_of_bitwise) diff --git a/clang/test/Sema/warn-int-in-bool-context.c b/clang/test/Sema/warn-int-in-bool-context.c index a6890161b5af..c111a5af23f5 100644 --- a/clang/test/Sema/warn-int-in-bool-context.c +++ b/clang/test/Sema/warn-int-in-bool-context.c @@ -79,3 +79,14 @@ int test(int a, unsigned b, enum num n) { // Don't warn in macros. return SHIFT(1, a); } + +int GH64356(int arg) { + if ((arg == 1) && (1 == 1)) return 1; + return 0; + + if ((64 > 32) && (32 < 64)) + return 2; + + if ((1 == 1) && (arg == 1)) return 1; + return 0; +} -- GitLab From e6866955f637634f439f7004a38be32b1c5185e2 Mon Sep 17 00:00:00 2001 From: Leandro Lupori Date: Tue, 6 Feb 2024 10:02:42 -0300 Subject: [PATCH 065/266] [flang][OpenMP] Accept firstprivate vars in copyprivate (#80467) This is patch 1 of 4, to add support for COPYPRIVATE. Original PR: https://github.com/llvm/llvm-project/pull/73128 --- flang/lib/Semantics/resolve-directives.cpp | 3 ++- flang/test/Semantics/OpenMP/copyprivate03.f90 | 7 +++++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/flang/lib/Semantics/resolve-directives.cpp b/flang/lib/Semantics/resolve-directives.cpp index 8d38790d2006..4b6d083671bc 100644 --- a/flang/lib/Semantics/resolve-directives.cpp +++ b/flang/lib/Semantics/resolve-directives.cpp @@ -2467,7 +2467,8 @@ void OmpAttributeVisitor::CheckDataCopyingClause( // either 'private' or 'threadprivate' in enclosing context. if (!checkSymbol->test(Symbol::Flag::OmpThreadprivate) && !(HasSymbolInEnclosingScope(symbol, currScope()) && - symbol.test(Symbol::Flag::OmpPrivate))) { + (symbol.test(Symbol::Flag::OmpPrivate) || + symbol.test(Symbol::Flag::OmpFirstPrivate)))) { context_.Say(name.source, "COPYPRIVATE variable '%s' is not PRIVATE or THREADPRIVATE in " "outer context"_err_en_US, diff --git a/flang/test/Semantics/OpenMP/copyprivate03.f90 b/flang/test/Semantics/OpenMP/copyprivate03.f90 index eccc308b1d5a..9d39fdb6b13c 100644 --- a/flang/test/Semantics/OpenMP/copyprivate03.f90 +++ b/flang/test/Semantics/OpenMP/copyprivate03.f90 @@ -34,6 +34,13 @@ program omp_copyprivate !$omp end parallel !$omp end parallel sections + !The use of FIRSTPRIVATE with COPYPRIVATE is allowed + !$omp parallel firstprivate(a) + !$omp single + a = a + k + !$omp end single copyprivate(a) + !$omp end parallel + print *, a, b end program omp_copyprivate -- GitLab From 48927e9592e8bb70f85ff6431c7bf514fe5d1c07 Mon Sep 17 00:00:00 2001 From: Leandro Lupori Date: Tue, 6 Feb 2024 10:04:20 -0300 Subject: [PATCH 066/266] [flang][OpenMP] Fix privatization of threadprivate common block (#77821) In some cases, when privatizing a threadprivate common block, the original symbol will correspond to the common block, instead of its threadprivate version. This can happen, for instance, with a common block, declared in a separate module, used by a parent procedure and privatized in its child procedure. In this case, symbol lookup won't find a symbol in the parent procedure, but only in the module where the common block was defined. Fixes https://github.com/llvm/llvm-project/issues/65028 --- flang/lib/Lower/OpenMP.cpp | 34 ++++++++++++++----- .../OpenMP/threadprivate-commonblock-use.f90 | 29 ++++++++++++++++ 2 files changed, 54 insertions(+), 9 deletions(-) create mode 100644 flang/test/Lower/OpenMP/threadprivate-commonblock-use.f90 diff --git a/flang/lib/Lower/OpenMP.cpp b/flang/lib/Lower/OpenMP.cpp index dad88fc1d764..9a02d3b3909e 100644 --- a/flang/lib/Lower/OpenMP.cpp +++ b/flang/lib/Lower/OpenMP.cpp @@ -2143,6 +2143,19 @@ static fir::ExtendedValue getExtendedValue(fir::ExtendedValue base, }); } +#ifndef NDEBUG +static bool isThreadPrivate(Fortran::lower::SymbolRef sym) { + if (const auto *details = + sym->detailsIf()) { + for (const auto &obj : details->objects()) + if (!obj->test(Fortran::semantics::Symbol::Flag::OmpThreadprivate)) + return false; + return true; + } + return sym->test(Fortran::semantics::Symbol::Flag::OmpThreadprivate); +} +#endif + static void threadPrivatizeVars(Fortran::lower::AbstractConverter &converter, Fortran::lower::pft::Evaluation &eval) { fir::FirOpBuilder &firOpBuilder = converter.getFirOpBuilder(); @@ -2150,18 +2163,21 @@ static void threadPrivatizeVars(Fortran::lower::AbstractConverter &converter, mlir::OpBuilder::InsertPoint insPt = firOpBuilder.saveInsertionPoint(); firOpBuilder.setInsertionPointToStart(firOpBuilder.getAllocaBlock()); - // Get the original ThreadprivateOp corresponding to the symbol and use the - // symbol value from that operation to create one ThreadprivateOp copy - // operation inside the parallel region. + // If the symbol corresponds to the original ThreadprivateOp, use the symbol + // value from that operation to create one ThreadprivateOp copy operation + // inside the parallel region. + // In some cases, however, the symbol will correspond to the original, + // non-threadprivate variable. This can happen, for instance, with a common + // block, declared in a separate module, used by a parent procedure and + // privatized in its child procedure. auto genThreadprivateOp = [&](Fortran::lower::SymbolRef sym) -> mlir::Value { - mlir::Value symOriThreadprivateValue = converter.getSymbolAddress(sym); - mlir::Operation *op = symOriThreadprivateValue.getDefiningOp(); + assert(isThreadPrivate(sym)); + mlir::Value symValue = converter.getSymbolAddress(sym); + mlir::Operation *op = symValue.getDefiningOp(); if (auto declOp = mlir::dyn_cast(op)) op = declOp.getMemref().getDefiningOp(); - assert(mlir::isa(op) && - "Threadprivate operation not created"); - mlir::Value symValue = - mlir::dyn_cast(op).getSymAddr(); + if (mlir::isa(op)) + symValue = mlir::dyn_cast(op).getSymAddr(); return firOpBuilder.create( currentLocation, symValue.getType(), symValue); }; diff --git a/flang/test/Lower/OpenMP/threadprivate-commonblock-use.f90 b/flang/test/Lower/OpenMP/threadprivate-commonblock-use.f90 new file mode 100644 index 000000000000..28616f7595a0 --- /dev/null +++ b/flang/test/Lower/OpenMP/threadprivate-commonblock-use.f90 @@ -0,0 +1,29 @@ +! This test checks lowering of OpenMP Threadprivate Directive. +! Test for common block, defined in one module, used in a subroutine of +! another module and privatized in a nested subroutine. + +!RUN: %flang_fc1 -emit-hlfir -fopenmp %s -o - | FileCheck %s + +!CHECK: fir.global common @cmn_(dense<0> : vector<4xi8>) : !fir.array<4xi8> +module m0 + common /cmn/ k1 + !$omp threadprivate(/cmn/) +end + +module m1 +contains + subroutine ss1 + use m0 + contains +!CHECK-LABEL: func @_QMm1Fss1Pss2 +!CHECK: %[[CMN:.*]] = fir.address_of(@cmn_) : !fir.ref> +!CHECK: omp.parallel +!CHECK: %{{.*}} = omp.threadprivate %[[CMN]] : !fir.ref> -> !fir.ref> + subroutine ss2 + !$omp parallel copyin (k1) + !$omp end parallel + end subroutine ss2 + end subroutine ss1 +end + +end -- GitLab From b06568fa623c746d40638137504d52e19911bf32 Mon Sep 17 00:00:00 2001 From: "Kevin P. Neal" Date: Fri, 11 Aug 2023 10:57:41 -0400 Subject: [PATCH 067/266] [FPEnv][llvm-reduce] Correct strictfp test. Correct llvm-reduce strictfp test to follow the rules documented in the LangRef: https://llvm.org/docs/LangRef.html#constrained-floating-point-intrinsics This test needed the strictfp attribute added to a function call. Note that attributes of intrinsics cannot be changed in declarations, but attributes can be changed in call sites. Thus the changes to the declarations. And the constrained intrinsics have strictfp attributes by default. Test changes verified with D146845. --- .../test/tools/llvm-reduce/remove-attributes-strictfp.ll | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/llvm/test/tools/llvm-reduce/remove-attributes-strictfp.ll b/llvm/test/tools/llvm-reduce/remove-attributes-strictfp.ll index 8607aae9dda2..cdb17d2d5321 100644 --- a/llvm/test/tools/llvm-reduce/remove-attributes-strictfp.ll +++ b/llvm/test/tools/llvm-reduce/remove-attributes-strictfp.ll @@ -28,7 +28,7 @@ define float @strictfp_declaration(float %x, float %y) #0 { ; CHECK-LABEL: define float @strictfp_no_constrained_ops(float %x, float %y) ; RESULT-SAME: [[STRICTFP_ONLY]] { define float @strictfp_no_constrained_ops(float %x, float %y) #0 { - %val = call float @llvm.copysign.f32(float %x, float %y) + %val = call float @llvm.copysign.f32(float %x, float %y) #1 ret float %val } @@ -38,11 +38,10 @@ declare float @strict.extern.func(float, float) #0 declare float @extern.func(float, float) -declare float @llvm.copysign.f32(float, float) #1 -declare float @llvm.experimental.constrained.fadd.f32(float, float, metadata, metadata) #2 +declare float @llvm.copysign.f32(float, float) +declare float @llvm.experimental.constrained.fadd.f32(float, float, metadata, metadata) ; RESULT: attributes [[STRICTFP_ONLY]] = { strictfp } attributes #0 = { nounwind strictfp } -attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: readwrite) } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) strictfp } -- GitLab From 026f3c1bbc1fbd9d7c25fc3a97b1c29d7ae7e2b5 Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Tue, 6 Feb 2024 07:22:13 -0600 Subject: [PATCH 068/266] [libc] Remove CPU dependent AMDGPU instructions (#80707) Summary: Some recent changes allowed us to remove target level divergence one these instructions. This patch removes the wavefront dependent divergence for the ballot and thread ID functions, as well as the clock. The changes to the "Vendor" library simply disables target specific optimizations in the implementation. This should be removed in its entirety when the LLVM `libm` is sufficiently implemented. The remaining areas of divergence is only the RPC packet size and the fixed frequency counter. --- libc/src/__support/GPU/amdgpu/utils.h | 22 +----- libc/src/math/gpu/vendor/amdgpu/platform.h | 85 +--------------------- 2 files changed, 8 insertions(+), 99 deletions(-) diff --git a/libc/src/__support/GPU/amdgpu/utils.h b/libc/src/__support/GPU/amdgpu/utils.h index 96e3efccb3b5..58bbe29cb3a7 100644 --- a/libc/src/__support/GPU/amdgpu/utils.h +++ b/libc/src/__support/GPU/amdgpu/utils.h @@ -113,10 +113,7 @@ LIBC_INLINE uint32_t get_lane_size() { return LANE_SIZE; } /// Returns the id of the thread inside of an AMD wavefront executing together. [[clang::convergent]] LIBC_INLINE uint32_t get_lane_id() { - if constexpr (LANE_SIZE == 64) - return __builtin_amdgcn_mbcnt_hi(~0u, __builtin_amdgcn_mbcnt_lo(~0u, 0u)); - else - return __builtin_amdgcn_mbcnt_lo(~0u, 0u); + return __builtin_amdgcn_mbcnt_hi(~0u, __builtin_amdgcn_mbcnt_lo(~0u, 0u)); } /// Returns the bit-mask of active threads in the current wavefront. @@ -134,11 +131,7 @@ LIBC_INLINE uint32_t get_lane_size() { return LANE_SIZE; } [[clang::convergent]] LIBC_INLINE uint64_t ballot(uint64_t lane_mask, bool x) { // the lane_mask & gives the nvptx semantics when lane_mask is a subset of // the active threads - if constexpr (LANE_SIZE == 64) { - return lane_mask & __builtin_amdgcn_ballot_w64(x); - } else { - return lane_mask & __builtin_amdgcn_ballot_w32(x); - } + return lane_mask & __builtin_amdgcn_ballot_w64(x); } /// Waits for all the threads in the block to converge and issues a fence. @@ -153,15 +146,8 @@ LIBC_INLINE uint32_t get_lane_size() { return LANE_SIZE; } } /// Returns the current value of the GPU's processor clock. -/// NOTE: The RDNA3 and RDNA2 architectures use a 20-bit cycle cycle counter. -LIBC_INLINE uint64_t processor_clock() { - if constexpr (LIBC_HAS_BUILTIN(__builtin_amdgcn_s_memtime)) - return __builtin_amdgcn_s_memtime(); - else if constexpr (LIBC_HAS_BUILTIN(__builtin_readcyclecounter)) - return __builtin_readcyclecounter(); - else - return 0; -} +/// NOTE: The RDNA3 and RDNA2 architectures use a 20-bit cycle counter. +LIBC_INLINE uint64_t processor_clock() { return __builtin_readcyclecounter(); } /// Returns a fixed-frequency timestamp. The actual frequency is dependent on /// the card and can only be queried via the driver. diff --git a/libc/src/math/gpu/vendor/amdgpu/platform.h b/libc/src/math/gpu/vendor/amdgpu/platform.h index 160a8508cd8b..cee01e938e30 100644 --- a/libc/src/math/gpu/vendor/amdgpu/platform.h +++ b/libc/src/math/gpu/vendor/amdgpu/platform.h @@ -32,88 +32,11 @@ extern const LIBC_INLINE_VAR uint8_t __oclc_correctly_rounded_sqrt32 = 1; // Disable finite math optimizations. extern const LIBC_INLINE_VAR uint8_t __oclc_finite_only_opt = 0; -#if defined(__gfx700__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 7000; -#elif defined(__gfx701__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 7001; -#elif defined(__gfx702__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 7002; -#elif defined(__gfx703__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 7003; -#elif defined(__gfx704__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 7004; -#elif defined(__gfx705__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 7005; -#elif defined(__gfx801__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 8001; -#elif defined(__gfx802__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 8002; -#elif defined(__gfx803__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 8003; -#elif defined(__gfx805__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 8005; -#elif defined(__gfx810__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 8100; -#elif defined(__gfx900__) +// Set the ISA value to a high enough value that the ROCm device library math +// functions will assume we have fast FMA operations among other features. This +// is determined to be safe on all targets by looking at the source code. +// https://github.com/ROCm/ROCm-Device-Libs/blob/amd-stg-open/ocml/src/opts.h extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 9000; -#elif defined(__gfx902__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 9002; -#elif defined(__gfx904__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 9004; -#elif defined(__gfx906__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 9006; -#elif defined(__gfx908__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 9008; -#elif defined(__gfx909__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 9009; -#elif defined(__gfx90a__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 9010; -#elif defined(__gfx90c__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 9012; -#elif defined(__gfx940__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 9400; -#elif defined(__gfx941__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 9401; -#elif defined(__gfx942__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 9402; -#elif defined(__gfx1010__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 10100; -#elif defined(__gfx1011__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 10101; -#elif defined(__gfx1012__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 10102; -#elif defined(__gfx1013__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 10103; -#elif defined(__gfx1030__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 10300; -#elif defined(__gfx1031__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 10301; -#elif defined(__gfx1032__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 10302; -#elif defined(__gfx1033__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 10303; -#elif defined(__gfx1034__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 10304; -#elif defined(__gfx1035__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 10305; -#elif defined(__gfx1036__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 10306; -#elif defined(__gfx1100__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 11000; -#elif defined(__gfx1101__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 11001; -#elif defined(__gfx1102__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 11002; -#elif defined(__gfx1103__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 11003; -#elif defined(__gfx1150__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 11500; -#elif defined(__gfx1151__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 11501; -#else -#error "Unknown AMDGPU architecture" -#endif -} // These aliases cause clang to emit the control constants with ODR linkage. // This allows us to link against the symbols without preventing them from being -- GitLab From ddc493579fa1b7eed058c7ed8a5a6b5755a31953 Mon Sep 17 00:00:00 2001 From: Jeremy Morse Date: Tue, 6 Feb 2024 13:08:44 +0000 Subject: [PATCH 069/266] [DebugInfo][RemoveDIs] Don't allocate one DPMarker per instruction (#79345) This is an optimisation patch that shouldn't have any functional effect. There's no need for all instructions to have a DPMarker attached to them, because not all instructions have adjacent DPValues (aka dbg.values). This patch inserts the appropriate conditionals into functions like BasicBlock::spliceDebugInfo to ensure we don't step on a null pointer when there isn't a DPMarker allocated. Mostly, this is a case of calling createMarker occasionally, which will create a marker on an instruction if there isn't one there already. Also folded into this is the use of adoptDbgValues, which is a natural extension: if we have a sequence of instructions and debug records: %foo = add i32 %0,... # dbg_value { %foo, ... # dbg_value { %bar, ... %baz = add i32 %... %qux = add i32 %... and delete, for example, the %baz instruction, then the dbg_value records would naturally be transferred onto the %qux instruction (they "fall down" onto it). There's no point in creating and splicing DPMarkers in the case shown when %qux doesn't have a DPMarker already, we can instead just change the owner of %baz's DPMarker from %baz to %qux. This also avoids calling setParent on every DPValue. Update LoopRotationUtils: it was relying on each instruction having it's own distinct end(), so that we could express ranges and lack-of-ranges. That's no longer true though: so switch to storing the range of DPValues on the next instruction when we want to consider it's range next time around the loop (see the nearby comment). --- llvm/include/llvm/IR/Instruction.h | 6 ++ llvm/lib/IR/BasicBlock.cpp | 58 +++++++++-------- llvm/lib/IR/DebugProgramInstruction.cpp | 22 +++++-- llvm/lib/IR/Instruction.cpp | 62 ++++++++++++++----- llvm/lib/Transforms/Utils/Local.cpp | 2 +- .../Transforms/Utils/LoopRotationUtils.cpp | 20 +++--- llvm/unittests/IR/BasicBlockDbgInfoTest.cpp | 11 ++-- 7 files changed, 121 insertions(+), 60 deletions(-) diff --git a/llvm/include/llvm/IR/Instruction.h b/llvm/include/llvm/IR/Instruction.h index a785a43a0f11..cd814e21be1a 100644 --- a/llvm/include/llvm/IR/Instruction.h +++ b/llvm/include/llvm/IR/Instruction.h @@ -90,6 +90,12 @@ public: /// Returns true if any DPValues are attached to this instruction. bool hasDbgValues() const; + /// Transfer any DPValues on the position \p It onto this instruction, + /// by simply adopting the sequence of DPValues (which is efficient) if + /// possible, by merging two sequences otherwise. + void adoptDbgValues(BasicBlock *BB, InstListType::iterator It, + bool InsertAtHead); + /// Erase any DPValues attached to this instruction. void dropDbgValues(); diff --git a/llvm/lib/IR/BasicBlock.cpp b/llvm/lib/IR/BasicBlock.cpp index dca528328384..bb55f48df4b3 100644 --- a/llvm/lib/IR/BasicBlock.cpp +++ b/llvm/lib/IR/BasicBlock.cpp @@ -81,8 +81,10 @@ void BasicBlock::convertToNewDbgValues() { continue; } - // Create a marker to store DPValues in. Technically we don't need to store - // one marker per instruction, but that's a future optimisation. + if (DPVals.empty()) + continue; + + // Create a marker to store DPValues in. createMarker(&I); DPMarker *Marker = I.DbgMarker; @@ -769,6 +771,7 @@ void BasicBlock::flushTerminatorDbgValues() { return; // Transfer DPValues from the trailing position onto the terminator. + createMarker(Term); Term->DbgMarker->absorbDebugValues(*TrailingDPValues, false); TrailingDPValues->eraseFromParent(); deleteTrailingDPValues(); @@ -812,10 +815,9 @@ void BasicBlock::spliceDebugInfoEmptyBlock(BasicBlock::iterator Dest, if (!SrcTrailingDPValues) return; - DPMarker *M = Dest->DbgMarker; - M->absorbDebugValues(*SrcTrailingDPValues, InsertAtHead); - SrcTrailingDPValues->eraseFromParent(); - Src->deleteTrailingDPValues(); + Dest->adoptDbgValues(Src, Src->end(), InsertAtHead); + // adoptDbgValues should have released the trailing DPValues. + assert(!Src->getTrailingDPValues()); return; } @@ -882,7 +884,6 @@ void BasicBlock::spliceDebugInfo(BasicBlock::iterator Dest, BasicBlock *Src, } if (First->hasDbgValues()) { - DPMarker *CurMarker = Src->getMarker(First); // Place them at the front, it would look like this: // Dest // | @@ -890,8 +891,7 @@ void BasicBlock::spliceDebugInfo(BasicBlock::iterator Dest, BasicBlock *Src, // Src-block: ~~~~~~~~++++B---B---B---B:::C // | | // First Last - CurMarker->absorbDebugValues(*OurTrailingDPValues, true); - OurTrailingDPValues->eraseFromParent(); + First->adoptDbgValues(this, end(), true); } else { // No current marker, create one and absorb in. (FIXME: we can avoid an // allocation in the future). @@ -911,7 +911,8 @@ void BasicBlock::spliceDebugInfo(BasicBlock::iterator Dest, BasicBlock *Src, if (!MoreDanglingDPValues) return; - // FIXME: we could avoid an allocation here sometimes. + // FIXME: we could avoid an allocation here sometimes. (adoptDbgValues + // requires an iterator). DPMarker *LastMarker = Src->createMarker(Last); LastMarker->absorbDebugValues(*MoreDanglingDPValues, true); MoreDanglingDPValues->eraseFromParent(); @@ -993,20 +994,22 @@ void BasicBlock::spliceDebugInfoImpl(BasicBlock::iterator Dest, BasicBlock *Src, // Detach the marker at Dest -- this lets us move the "====" DPValues around. DPMarker *DestMarker = nullptr; if (Dest != end()) { - DestMarker = getMarker(Dest); - DestMarker->removeFromParent(); - createMarker(&*Dest); + if ((DestMarker = getMarker(Dest))) + DestMarker->removeFromParent(); } // If we're moving the tail range of DPValues (":::"), absorb them into the // front of the DPValues at Dest. if (ReadFromTail && Src->getMarker(Last)) { - DPMarker *OntoDest = getMarker(Dest); DPMarker *FromLast = Src->getMarker(Last); - OntoDest->absorbDebugValues(*FromLast, true); if (LastIsEnd) { - FromLast->eraseFromParent(); - Src->deleteTrailingDPValues(); + Dest->adoptDbgValues(Src, Last, true); + // adoptDbgValues will release any trailers. + assert(!Src->getTrailingDPValues()); + } else { + // FIXME: can we use adoptDbgValues here to reduce allocations? + DPMarker *OntoDest = createMarker(Dest); + OntoDest->absorbDebugValues(*FromLast, true); } } @@ -1014,10 +1017,14 @@ void BasicBlock::spliceDebugInfoImpl(BasicBlock::iterator Dest, BasicBlock *Src, // move their markers onto Last. They remain in the Src block. No action // needed. if (!ReadFromHead && First->hasDbgValues()) { - DPMarker *OntoLast = Src->createMarker(Last); - DPMarker *FromFirst = Src->createMarker(First); - OntoLast->absorbDebugValues(*FromFirst, - true); // Always insert at head of it. + if (Last != Src->end()) { + Last->adoptDbgValues(Src, First, true); + } else { + DPMarker *OntoLast = Src->createMarker(Last); + DPMarker *FromFirst = Src->createMarker(First); + // Always insert at front of Last. + OntoLast->absorbDebugValues(*FromFirst, true); + } } // Finally, do something with the "====" DPValues we detached. @@ -1025,12 +1032,12 @@ void BasicBlock::spliceDebugInfoImpl(BasicBlock::iterator Dest, BasicBlock *Src, if (InsertAtHead) { // Insert them at the end of the DPValues at Dest. The "::::" DPValues // might be in front of them. - DPMarker *NewDestMarker = getMarker(Dest); + DPMarker *NewDestMarker = createMarker(Dest); NewDestMarker->absorbDebugValues(*DestMarker, false); } else { // Insert them right at the start of the range we moved, ahead of First // and the "++++" DPValues. - DPMarker *FirstMarker = getMarker(First); + DPMarker *FirstMarker = createMarker(First); FirstMarker->absorbDebugValues(*DestMarker, true); } DestMarker->eraseFromParent(); @@ -1082,9 +1089,7 @@ void BasicBlock::insertDPValueAfter(DPValue *DPV, Instruction *I) { assert(I->getParent() == this); iterator NextIt = std::next(I->getIterator()); - DPMarker *NextMarker = getMarker(NextIt); - if (!NextMarker) - NextMarker = createMarker(NextIt); + DPMarker *NextMarker = createMarker(NextIt); NextMarker->insertDPValue(DPV, true); } @@ -1097,6 +1102,7 @@ void BasicBlock::insertDPValueBefore(DPValue *DPV, if (!Where->DbgMarker) createMarker(Where); bool InsertAtHead = Where.getHeadBit(); + createMarker(&*Where); Where->DbgMarker->insertDPValue(DPV, InsertAtHead); } diff --git a/llvm/lib/IR/DebugProgramInstruction.cpp b/llvm/lib/IR/DebugProgramInstruction.cpp index 03085b3bfd12..1a62902115be 100644 --- a/llvm/lib/IR/DebugProgramInstruction.cpp +++ b/llvm/lib/IR/DebugProgramInstruction.cpp @@ -434,13 +434,23 @@ void DPMarker::removeMarker() { // instruction. If there isn't a next instruction, put them on the // "trailing" list. DPMarker *NextMarker = Owner->getParent()->getNextMarker(Owner); - if (NextMarker == nullptr) { - NextMarker = new DPMarker(); - Owner->getParent()->setTrailingDPValues(NextMarker); + if (NextMarker) { + NextMarker->absorbDebugValues(*this, true); + eraseFromParent(); + } else { + // We can avoid a deallocation -- just store this marker onto the next + // instruction. Unless we're at the end of the block, in which case this + // marker becomes the trailing marker of a degenerate block. + BasicBlock::iterator NextIt = std::next(Owner->getIterator()); + if (NextIt == getParent()->end()) { + getParent()->setTrailingDPValues(this); + MarkedInstr = nullptr; + } else { + NextIt->DbgMarker = this; + MarkedInstr = &*NextIt; + } } - NextMarker->absorbDebugValues(*this, true); - - eraseFromParent(); + Owner->DbgMarker = nullptr; } void DPMarker::removeFromParent() { diff --git a/llvm/lib/IR/Instruction.cpp b/llvm/lib/IR/Instruction.cpp index 904ce17fb0e7..23a3e72da51d 100644 --- a/llvm/lib/IR/Instruction.cpp +++ b/llvm/lib/IR/Instruction.cpp @@ -111,11 +111,6 @@ void Instruction::insertAfter(Instruction *InsertPos) { BasicBlock *DestParent = InsertPos->getParent(); DestParent->getInstList().insertAfter(InsertPos->getIterator(), this); - - // No need to manually update DPValues: if we insert after an instruction - // position, then we can never have any DPValues on "this". - if (DestParent->IsNewDbgInfoFormat) - DestParent->createMarker(this); } BasicBlock::iterator Instruction::insertInto(BasicBlock *ParentBB, @@ -138,17 +133,15 @@ void Instruction::insertBefore(BasicBlock &BB, if (!BB.IsNewDbgInfoFormat) return; - BB.createMarker(this); - // We've inserted "this": if InsertAtHead is set then it comes before any // DPValues attached to InsertPos. But if it's not set, then any DPValues // should now come before "this". bool InsertAtHead = InsertPos.getHeadBit(); if (!InsertAtHead) { DPMarker *SrcMarker = BB.getMarker(InsertPos); - // If there's no source marker, InsertPos is very likely end(). - if (SrcMarker) - DbgMarker->absorbDebugValues(*SrcMarker, false); + if (SrcMarker && !SrcMarker->empty()) { + adoptDbgValues(&BB, InsertPos, false); + } } // If we're inserting a terminator, check if we need to flush out @@ -212,14 +205,13 @@ void Instruction::moveBeforeImpl(BasicBlock &BB, InstListType::iterator I, BB.getInstList().splice(I, getParent()->getInstList(), getIterator()); if (BB.IsNewDbgInfoFormat && !Preserve) { - if (!DbgMarker) - BB.createMarker(this); DPMarker *NextMarker = getParent()->getNextMarker(this); // If we're inserting at point I, and not in front of the DPValues attached // there, then we should absorb the DPValues attached to I. - if (NextMarker && !InsertAtHead) - DbgMarker->absorbDebugValues(*NextMarker, false); + if (!InsertAtHead && NextMarker && !NextMarker->empty()) { + adoptDbgValues(&BB, I, false); + } } if (isTerminator()) @@ -258,6 +250,48 @@ std::optional Instruction::getDbgReinsertionPosition() { bool Instruction::hasDbgValues() const { return !getDbgValueRange().empty(); } +void Instruction::adoptDbgValues(BasicBlock *BB, BasicBlock::iterator It, + bool InsertAtHead) { + DPMarker *SrcMarker = BB->getMarker(It); + auto ReleaseTrailingDPValues = [BB, It, SrcMarker]() { + if (BB->end() == It) { + SrcMarker->eraseFromParent(); + BB->deleteTrailingDPValues(); + } + }; + + if (!SrcMarker || SrcMarker->StoredDPValues.empty()) { + ReleaseTrailingDPValues(); + return; + } + + // If we have DPMarkers attached to this instruction, we have to honour the + // ordering of DPValues between this and the other marker. Fall back to just + // absorbing from the source. + if (DbgMarker || It == BB->end()) { + // Ensure we _do_ have a marker. + getParent()->createMarker(this); + DbgMarker->absorbDebugValues(*SrcMarker, InsertAtHead); + + // Having transferred everything out of SrcMarker, we _could_ clean it up + // and free the marker now. However, that's a lot of heap-accounting for a + // small amount of memory with a good chance of re-use. Leave it for the + // moment. It will be released when the Instruction is freed in the worst + // case. + // However: if we transferred from a trailing marker off the end of the + // block, it's important to not leave the empty marker trailing. It will + // give a misleading impression that some debug records have been left + // trailing. + ReleaseTrailingDPValues(); + } else { + // Optimisation: we're transferring all the DPValues from the source marker + // onto this empty location: just adopt the other instructions marker. + DbgMarker = SrcMarker; + DbgMarker->MarkedInstr = this; + It->DbgMarker = nullptr; + } +} + void Instruction::dropDbgValues() { if (DbgMarker) DbgMarker->dropDPValues(); diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp index 459e3d980592..e4aa25f7ac6a 100644 --- a/llvm/lib/Transforms/Utils/Local.cpp +++ b/llvm/lib/Transforms/Utils/Local.cpp @@ -2044,7 +2044,7 @@ static void insertDPValuesForPHIs(BasicBlock *BB, auto InsertionPt = Parent->getFirstInsertionPt(); assert(InsertionPt != Parent->end() && "Ill-formed basic block"); - InsertionPt->DbgMarker->insertDPValue(NewDbgII, true); + Parent->insertDPValueBefore(NewDbgII, InsertionPt); } } diff --git a/llvm/lib/Transforms/Utils/LoopRotationUtils.cpp b/llvm/lib/Transforms/Utils/LoopRotationUtils.cpp index 504f4430dc2c..ec59a0773020 100644 --- a/llvm/lib/Transforms/Utils/LoopRotationUtils.cpp +++ b/llvm/lib/Transforms/Utils/LoopRotationUtils.cpp @@ -596,7 +596,10 @@ bool LoopRotate::rotateLoop(Loop *L, bool SimplifiedLatch) { // on the next instruction, here labelled xyzzy, before we hoist %foo. // Later, we only only clone DPValues from that position (xyzzy) onwards, // which avoids cloning DPValue "blah" multiple times. - std::optional NextDbgInst = std::nullopt; + // (Stored as a range because it gives us a natural way of testing whether + // there were DPValues on the next instruction before we hoisted things). + iterator_range NextDbgInsts = + (I != E) ? I->getDbgValueRange() : DPMarker::getEmptyDPValueRange(); while (I != E) { Instruction *Inst = &*I++; @@ -611,9 +614,10 @@ bool LoopRotate::rotateLoop(Loop *L, bool SimplifiedLatch) { !Inst->mayWriteToMemory() && !Inst->isTerminator() && !isa(Inst) && !isa(Inst)) { - if (LoopEntryBranch->getParent()->IsNewDbgInfoFormat) { + if (LoopEntryBranch->getParent()->IsNewDbgInfoFormat && + !NextDbgInsts.empty()) { auto DbgValueRange = - LoopEntryBranch->cloneDebugInfoFrom(Inst, NextDbgInst); + LoopEntryBranch->cloneDebugInfoFrom(Inst, NextDbgInsts.begin()); RemapDPValueRange(M, DbgValueRange, ValueMap, RF_NoModuleLevelChanges | RF_IgnoreMissingLocals); // Erase anything we've seen before. @@ -622,7 +626,8 @@ bool LoopRotate::rotateLoop(Loop *L, bool SimplifiedLatch) { DPV.eraseFromParent(); } - NextDbgInst = I->getDbgValueRange().begin(); + NextDbgInsts = I->getDbgValueRange(); + Inst->moveBefore(LoopEntryBranch); ++NumInstrsHoisted; @@ -635,11 +640,12 @@ bool LoopRotate::rotateLoop(Loop *L, bool SimplifiedLatch) { ++NumInstrsDuplicated; - if (LoopEntryBranch->getParent()->IsNewDbgInfoFormat) { - auto Range = C->cloneDebugInfoFrom(Inst, NextDbgInst); + if (LoopEntryBranch->getParent()->IsNewDbgInfoFormat && + !NextDbgInsts.empty()) { + auto Range = C->cloneDebugInfoFrom(Inst, NextDbgInsts.begin()); RemapDPValueRange(M, Range, ValueMap, RF_NoModuleLevelChanges | RF_IgnoreMissingLocals); - NextDbgInst = std::nullopt; + NextDbgInsts = DPMarker::getEmptyDPValueRange(); // Erase anything we've seen before. for (DPValue &DPV : make_early_inc_range(Range)) if (DbgIntrinsics.count(makeHash(&DPV))) diff --git a/llvm/unittests/IR/BasicBlockDbgInfoTest.cpp b/llvm/unittests/IR/BasicBlockDbgInfoTest.cpp index fb4847fc0a82..827b4a9c0cc3 100644 --- a/llvm/unittests/IR/BasicBlockDbgInfoTest.cpp +++ b/llvm/unittests/IR/BasicBlockDbgInfoTest.cpp @@ -225,10 +225,9 @@ TEST(BasicBlockDbgInfoTest, MarkerOperations) { // then they would sit "above" the new instruction. Instr1->insertBefore(BB, BB.end()); EXPECT_EQ(Instr1->DbgMarker->StoredDPValues.size(), 2u); - // However we won't de-allocate the trailing marker until a terminator is - // inserted. - EXPECT_EQ(EndMarker->StoredDPValues.size(), 0u); - EXPECT_EQ(BB.getTrailingDPValues(), EndMarker); + // We should de-allocate the trailing marker when something is inserted + // at end(). + EXPECT_EQ(BB.getTrailingDPValues(), nullptr); // Remove Instr1: now the DPValues will fall down again, Instr1->removeFromParent(); @@ -394,12 +393,12 @@ TEST(BasicBlockDbgInfoTest, InstrDbgAccess) { Instruction *CInst = BInst->getNextNode(); Instruction *DInst = CInst->getNextNode(); - ASSERT_TRUE(BInst->DbgMarker); + ASSERT_FALSE(BInst->DbgMarker); ASSERT_TRUE(CInst->DbgMarker); ASSERT_EQ(CInst->DbgMarker->StoredDPValues.size(), 1u); DPValue *DPV1 = &*CInst->DbgMarker->StoredDPValues.begin(); ASSERT_TRUE(DPV1); - EXPECT_EQ(BInst->DbgMarker->StoredDPValues.size(), 0u); + EXPECT_FALSE(BInst->hasDbgValues()); // Clone DPValues from one inst to another. Other arguments to clone are // tested in DPMarker test. -- GitLab From 54c29e01c2bf6980bf999496e221f214e521d3ff Mon Sep 17 00:00:00 2001 From: ostannard Date: Tue, 6 Feb 2024 13:32:00 +0000 Subject: [PATCH 070/266] [AArch64] Set predicates for FP/SIMD InstAliases (#79033) These are aliases for instructions which are are only available when the fp-armv8 or neon features are enabled, so their predicates should be set appropriately. --- llvm/lib/Target/AArch64/AArch64InstrInfo.td | 24 ++- llvm/test/MC/AArch64/no-fp-errors.s | 170 ++++++++++++++++++++ 2 files changed, 193 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index c476617e679f..77fdb688d042 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -3532,6 +3532,7 @@ def : InstAlias<"ldr $Rt, [$Rn, $offset]", (LDURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>; def : InstAlias<"ldr $Rt, [$Rn, $offset]", (LDURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>; +let Predicates = [HasFPARMv8] in { def : InstAlias<"ldr $Rt, [$Rn, $offset]", (LDURBi FPR8Op:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; def : InstAlias<"ldr $Rt, [$Rn, $offset]", @@ -3542,6 +3543,7 @@ def : InstAlias<"ldr $Rt, [$Rn, $offset]", (LDURDi FPR64Op:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>; def : InstAlias<"ldr $Rt, [$Rn, $offset]", (LDURQi FPR128Op:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>; +} // zextload -> i64 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), @@ -4175,6 +4177,7 @@ def : InstAlias<"str $Rt, [$Rn, $offset]", (STURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>; def : InstAlias<"str $Rt, [$Rn, $offset]", (STURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>; +let Predicates = [HasFPARMv8] in { def : InstAlias<"str $Rt, [$Rn, $offset]", (STURBi FPR8Op:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; def : InstAlias<"str $Rt, [$Rn, $offset]", @@ -4185,6 +4188,7 @@ def : InstAlias<"str $Rt, [$Rn, $offset]", (STURDi FPR64Op:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>; def : InstAlias<"str $Rt, [$Rn, $offset]", (STURQi FPR128Op:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>; +} def : InstAlias<"strb $Rt, [$Rn, $offset]", (STURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; @@ -4595,8 +4599,10 @@ def FMOVD0 : Pseudo<(outs FPR64:$Rd), (ins), [(set f64:$Rd, (fpimm0))]>, // Similarly add aliases def : InstAlias<"fmov $Rd, #0.0", (FMOVWHr FPR16:$Rd, WZR), 0>, Requires<[HasFullFP16]>; +let Predicates = [HasFPARMv8] in { def : InstAlias<"fmov $Rd, #0.0", (FMOVWSr FPR32:$Rd, WZR), 0>; def : InstAlias<"fmov $Rd, #0.0", (FMOVXDr FPR64:$Rd, XZR), 0>; +} def : Pat<(bf16 fpimm0), (FMOVH0)>; @@ -5040,10 +5046,12 @@ defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg", UnOpFrag<(sub immAllZerosV, node:$LHS)> >; defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>; // Aliases for MVN -> NOT. +let Predicates = [HasNEON] in { def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}", (NOTv8i8 V64:$Vd, V64:$Vn)>; def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}", (NOTv16i8 V128:$Vd, V128:$Vn)>; +} def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>; def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>; @@ -5318,6 +5326,7 @@ def : Pat<(AArch64bsp (v4i32 V128:$Rd), V128:$Rn, V128:$Rm), def : Pat<(AArch64bsp (v2i64 V128:$Rd), V128:$Rn, V128:$Rm), (BSPv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>; +let Predicates = [HasNEON] in { def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}", (ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>; def : InstAlias<"mov{\t$dst.8h, $src.8h|.8h\t$dst, $src}", @@ -5495,6 +5504,7 @@ def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" # def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" # "|faclt.2d\t$dst, $src1, $src2}", (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>; +} //===----------------------------------------------------------------------===// // Advanced SIMD three scalar instructions. @@ -5557,6 +5567,7 @@ defm : FMULScalarFromIndexedLane0Patterns<"FMULX", "16", "32", "64", int_aarch64_neon_fmulx, [HasNEONorSME]>; +let Predicates = [HasNEON] in { def : InstAlias<"cmls $dst, $src1, $src2", (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; def : InstAlias<"cmle $dst, $src1, $src2", @@ -5565,6 +5576,8 @@ def : InstAlias<"cmlo $dst, $src1, $src2", (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; def : InstAlias<"cmlt $dst, $src1, $src2", (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; +} +let Predicates = [HasFPARMv8] in { def : InstAlias<"fcmle $dst, $src1, $src2", (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>; def : InstAlias<"fcmle $dst, $src1, $src2", @@ -5581,6 +5594,7 @@ def : InstAlias<"faclt $dst, $src1, $src2", (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>; def : InstAlias<"faclt $dst, $src1, $src2", (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; +} //===----------------------------------------------------------------------===// // Advanced SIMD three scalar instructions (mixed operands). @@ -7027,6 +7041,7 @@ defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>; // AdvSIMD ORR defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", AArch64orri>; +let Predicates = [HasNEON] in { def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>; def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>; def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>; @@ -7046,6 +7061,7 @@ def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>; def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>; def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>; def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>; +} // AdvSIMD FMOV def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0, 0b1111, V128, fpimm8, @@ -7129,6 +7145,7 @@ let Predicates = [HasNEON] in { ssub)>; } +let Predicates = [HasNEON] in { def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>; @@ -7138,6 +7155,7 @@ def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"movi.2s $Vd, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"movi.4s $Vd, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>; +} def : Pat<(v2i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))), (MOVIv2i32 imm0_255:$imm8, imm:$shift)>; @@ -7173,6 +7191,7 @@ def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0, 0b1110, V128, imm0_255, let isReMaterializable = 1, isAsCheapAsAMove = 1 in defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">; +let Predicates = [HasNEON] in { def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>; @@ -7182,6 +7201,7 @@ def : InstAlias<"mvni.4h $Vd, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"mvni.8h $Vd, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"mvni.2s $Vd, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"mvni.4s $Vd, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>; +} def : Pat<(v2i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))), (MVNIv2i32 imm0_255:$imm8, imm:$shift)>; @@ -7669,6 +7689,7 @@ def : Pat<(v2i64 (zext (v2i32 (extract_high_v4i32 (v4i32 V128:$Rn)) ))), def : Pat<(v2i64 (sext (v2i32 (extract_high_v4i32 (v4i32 V128:$Rn)) ))), (SSHLLv4i32_shift V128:$Rn, (i32 0))>; +let Predicates = [HasNEON] in { // Vector shift sxtl aliases def : InstAlias<"sxtl.8h $dst, $src1", (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>; @@ -7724,6 +7745,7 @@ def : InstAlias<"uxtl2.2d $dst, $src1", (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>; def : InstAlias<"uxtl2 $dst.2d, $src1.4s", (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>; +} // If an integer is about to be converted to a floating point value, // just load it on the floating point unit. @@ -8172,7 +8194,7 @@ def AESIMCrr : AESInst< 0b0111, "aesimc", int_aarch64_crypto_aesimc>; // Pseudo instructions for AESMCrr/AESIMCrr with a register constraint required // for AES fusion on some CPUs. -let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in { +let hasSideEffects = 0, mayStore = 0, mayLoad = 0, Predicates = [HasAES] in { def AESMCrrTied: Pseudo<(outs V128:$Rd), (ins V128:$Rn), [], "$Rn = $Rd">, Sched<[WriteVq]>; def AESIMCrrTied: Pseudo<(outs V128:$Rd), (ins V128:$Rn), [], "$Rn = $Rd">, diff --git a/llvm/test/MC/AArch64/no-fp-errors.s b/llvm/test/MC/AArch64/no-fp-errors.s index 1595ba4798b0..9fe3cba83e25 100644 --- a/llvm/test/MC/AArch64/no-fp-errors.s +++ b/llvm/test/MC/AArch64/no-fp-errors.s @@ -191,3 +191,173 @@ label: // CHECK: [[@LINE-1]]:7: error: expected writable system register or pstate msr FPSR, x0 // CHECK: [[@LINE-1]]:7: error: expected writable system register or pstate + + ldr s0, [x0, #1] +// CHECK: [[@LINE-1]]:3: error: instruction requires: fp-armv8 + str q0, [x0, #1] +// CHECK: [[@LINE-1]]:3: error: instruction requires: fp-armv8 + + fmov s0, #0.0 +// CHECK: [[@LINE-1]]:3: error: instruction requires: fp-armv8 + fmov d0, #0.0 +// CHECK: [[@LINE-1]]:3: error: instruction requires: fp-armv8 + + mvn v0.8b, v1.8b +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + mvn v0.16b, v1.16b +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + + mov v0.16b, v1.16b +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + mov v0.8h, v1.8h +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + mov v0.4s, v1.4s +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + mov v0.2d, v1.2d +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + + mov v0.8b, v1.8b +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + mov v0.4h, v1.4h +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + mov v0.2s, v1.2s +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + mov v0.1d, v1.1d +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + + faclt v0.4h, v1.4h, v2.4h +// CHECK: [[@LINE-1]]:3: error: instruction requires: fullfp16 neon + faclt v0.8h, v1.8h, v2.8h +// CHECK: [[@LINE-1]]:3: error: instruction requires: fullfp16 neon + faclt v0.2s, v1.2s, v2.2s +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + faclt v0.4s, v1.4s, v2.4s +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + faclt v0.2d, v1.2d, v2.2d +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + + cmls d0, d1, d2 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + cmle d0, d1, d2 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + cmlo d0, d1, d2 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + cmlt d0, d1, d2 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + + fcmle s0, s1, s2 +// CHECK: [[@LINE-1]]:3: error: instruction requires: fp-armv8 + fcmle d0, d1, d2 +// CHECK: [[@LINE-1]]:3: error: instruction requires: fp-armv8 + fcmlt s0, s1, s2 +// CHECK: [[@LINE-1]]:3: error: instruction requires: fp-armv8 + fcmlt d0, d1, d2 +// CHECK: [[@LINE-1]]:3: error: instruction requires: fp-armv8 + facle s0, s1, s2 +// CHECK: [[@LINE-1]]:3: error: instruction requires: fp-armv8 + facle d0, d1, d2 +// CHECK: [[@LINE-1]]:3: error: instruction requires: fp-armv8 + faclt s0, s1, s2 +// CHECK: [[@LINE-1]]:3: error: instruction requires: fp-armv8 + faclt d0, d1, d2 +// CHECK: [[@LINE-1]]:3: error: instruction requires: fp-armv8 + + bic v0.4h, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + bic v0.8h, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + bic v0.2s, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + bic v0.4s, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + + bic.4h v0, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + bic.8h v0, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + bic.2s v0, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + bic.4s v0, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + + orr v0.4h, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + orr v0.8h, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + orr v0.2s, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + orr v0.4s, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + + orr.4h v0, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + orr.8h v0, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + orr.2s v0, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + orr.4s v0, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + + movi v0.4h, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + movi v0.8h, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + movi v0.2s, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + movi v0.4s, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + + movi.4h v0, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + movi.8h v0, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + movi.2s v0, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + movi.4s v0, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + + mvni v0.4h, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + mvni v0.8h, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + mvni v0.2s, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + mvni v0.4s, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + + mvni.4h v0, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + mvni.8h v0, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + mvni.2s v0, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + mvni.4s v0, #42 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + + sxtl.8h v0, v1 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + sxtl.4s v0, v1 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + sxtl.2d v0, v1 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + + sxtl2.8h v0, v1 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + sxtl2.4s v0, v1 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + sxtl2.2d v0, v1 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + + uxtl.8h v0, v1 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + uxtl.4s v0, v1 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + uxtl.2d v0, v1 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + + uxtl2.8h v0, v1 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + uxtl2.4s v0, v1 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon + uxtl2.2d v0, v1 +// CHECK: [[@LINE-1]]:3: error: instruction requires: neon -- GitLab From 26db3c3b72d3c915ad296a5a5313210bde8ce3e1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Tue, 6 Feb 2024 14:14:42 +0100 Subject: [PATCH 071/266] [clang][Interp] Handle discarding ConstantExprs Assume no side-effects in the presence of a cashed result in the form of an APValue. This is also what the current interpreter does. --- clang/lib/AST/Interp/ByteCodeExprGen.cpp | 15 +++++++++------ clang/test/AST/Interp/cxx20.cpp | 13 +++++++++++++ .../SemaCXX/cxx11-default-member-initializers.cpp | 2 ++ 3 files changed, 24 insertions(+), 6 deletions(-) diff --git a/clang/lib/AST/Interp/ByteCodeExprGen.cpp b/clang/lib/AST/Interp/ByteCodeExprGen.cpp index 10e32d9b7bcf..f31755e72e8d 100644 --- a/clang/lib/AST/Interp/ByteCodeExprGen.cpp +++ b/clang/lib/AST/Interp/ByteCodeExprGen.cpp @@ -1030,14 +1030,17 @@ bool ByteCodeExprGen::VisitSubstNonTypeTemplateParmExpr( template bool ByteCodeExprGen::VisitConstantExpr(const ConstantExpr *E) { - // Try to emit the APValue directly, without visiting the subexpr. - // This will only fail if we can't emit the APValue, so won't emit any - // diagnostics or any double values. std::optional T = classify(E->getType()); - if (T && E->hasAPValueResult() && - this->visitAPValue(E->getAPValueResult(), *T, E)) - return true; + if (T && E->hasAPValueResult()) { + // Try to emit the APValue directly, without visiting the subexpr. + // This will only fail if we can't emit the APValue, so won't emit any + // diagnostics or any double values. + if (DiscardResult) + return true; + if (this->visitAPValue(E->getAPValueResult(), *T, E)) + return true; + } return this->delegate(E->getSubExpr()); } diff --git a/clang/test/AST/Interp/cxx20.cpp b/clang/test/AST/Interp/cxx20.cpp index 50a7c0292587..0af553a77892 100644 --- a/clang/test/AST/Interp/cxx20.cpp +++ b/clang/test/AST/Interp/cxx20.cpp @@ -752,3 +752,16 @@ namespace TryCatch { } static_assert(foo() == 11); } + +namespace IgnoredConstantExpr { + consteval int immediate() { return 0;} + struct ReferenceToNestedMembers { + int m; + int a = ((void)immediate(), m); + int b = ((void)immediate(), this->m); + }; + struct ReferenceToNestedMembersTest { + void* m = nullptr; + ReferenceToNestedMembers j{0}; + } test_reference_to_nested_members; +} diff --git a/clang/test/SemaCXX/cxx11-default-member-initializers.cpp b/clang/test/SemaCXX/cxx11-default-member-initializers.cpp index 9c18c73be8f6..dd8e9c6b7fc1 100644 --- a/clang/test/SemaCXX/cxx11-default-member-initializers.cpp +++ b/clang/test/SemaCXX/cxx11-default-member-initializers.cpp @@ -1,5 +1,7 @@ // RUN: %clang_cc1 -std=c++11 -verify %s -pedantic +// RUN: %clang_cc1 -std=c++11 -verify %s -pedantic -fexperimental-new-constant-interpreter // RUN: %clang_cc1 -std=c++20 -verify %s -pedantic +// RUN: %clang_cc1 -std=c++20 -verify %s -pedantic -fexperimental-new-constant-interpreter namespace PR31692 { -- GitLab From 83eb8126dd0c7457d43f5e6bce8911a528f93af9 Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Tue, 6 Feb 2024 07:37:41 -0600 Subject: [PATCH 072/266] [libc] Fix accidentally deleted braces after change Summary: Oops. --- libc/src/math/gpu/vendor/amdgpu/platform.h | 1 + 1 file changed, 1 insertion(+) diff --git a/libc/src/math/gpu/vendor/amdgpu/platform.h b/libc/src/math/gpu/vendor/amdgpu/platform.h index cee01e938e30..e5a9f810cd10 100644 --- a/libc/src/math/gpu/vendor/amdgpu/platform.h +++ b/libc/src/math/gpu/vendor/amdgpu/platform.h @@ -37,6 +37,7 @@ extern const LIBC_INLINE_VAR uint8_t __oclc_finite_only_opt = 0; // is determined to be safe on all targets by looking at the source code. // https://github.com/ROCm/ROCm-Device-Libs/blob/amd-stg-open/ocml/src/opts.h extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 9000; +} // These aliases cause clang to emit the control constants with ODR linkage. // This allows us to link against the symbols without preventing them from being -- GitLab From f89fe08d770d912bc1e7b9b52c1859a44abea69a Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Tue, 6 Feb 2024 13:47:31 +0000 Subject: [PATCH 073/266] [Matrix] Convert column-vector ops feeding dot product to row-vectors. (#72647) Generalize the logic used to convert column-vector ops to row-vectors to support converting chains of operations. A potential next step is to further generalize this to convert column-vector ops to row-vector ops in general, not just for operands of dot products. Dot-product handling would then be driven by the general conversion, rather than the other way around. PR: https://github.com/llvm/llvm-project/pull/72647 --- .../Scalar/LowerMatrixIntrinsics.cpp | 54 ++++++++++++++----- .../LowerMatrixIntrinsics/dot-product-int.ll | 47 ++++------------ 2 files changed, 50 insertions(+), 51 deletions(-) diff --git a/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp b/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp index 72b9db1e73d7..b528762b5456 100644 --- a/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp +++ b/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp @@ -1332,8 +1332,8 @@ public: if (!IsIntVec && !FMF.allowReassoc()) return; - auto CanBeFlattened = [this](Value *Op) { - if (match(Op, m_BinOp()) && ShapeMap.find(Op) != ShapeMap.end()) + auto CanBeFlattened = [](Value *Op) { + if (match(Op, m_BinOp())) return true; return match( Op, m_OneUse(m_CombineOr( @@ -1346,6 +1346,9 @@ public: // the returned cost is < 0, the argument is cheaper to use in the // dot-product lowering. auto GetCostForArg = [this, &CanBeFlattened](Value *Op, unsigned N) { + if (ShapeMap.find(Op) == ShapeMap.end()) + return InstructionCost::getInvalid(); + if (!isa(Op)) return InstructionCost(0); @@ -1356,7 +1359,7 @@ public: InstructionCost EmbedCost(0); // Roughly estimate the cost for embedding the columns into a vector. for (unsigned I = 1; I < N; ++I) - EmbedCost -= + EmbedCost += TTI.getShuffleCost(TTI::SK_Splice, FixedVectorType::get(EltTy, 1), std::nullopt, TTI::TCK_RecipThroughput); return EmbedCost; @@ -1378,7 +1381,7 @@ public: // vector. InstructionCost EmbedCost(0); for (unsigned I = 1; I < N; ++I) - EmbedCost += + EmbedCost -= TTI.getShuffleCost(TTI::SK_Splice, FixedVectorType::get(EltTy, 1), std::nullopt, TTI::TCK_RecipThroughput); return EmbedCost; @@ -1391,7 +1394,29 @@ public: return TTI.getMemoryOpCost(Instruction::Load, VecTy, Align(1), 0) - N * TTI.getMemoryOpCost(Instruction::Load, EltTy, Align(1), 0); }; - auto LHSCost = GetCostForArg(LHS, LShape.NumColumns); + + // Iterate over LHS and operations feeding LHS and check if it is profitable + // to flatten the visited ops. For each op, we compute the difference + // between the flattened and matrix versions. + SmallPtrSet Seen; + SmallVector WorkList; + SmallVector ToFlatten; + WorkList.push_back(LHS); + InstructionCost LHSCost(0); + while (!WorkList.empty()) { + Value *Op = WorkList.pop_back_val(); + if (!Seen.insert(Op).second) + continue; + + InstructionCost OpCost = GetCostForArg(Op, LShape.NumColumns); + if (OpCost + LHSCost >= LHSCost) + continue; + + LHSCost += OpCost; + ToFlatten.push_back(Op); + if (auto *I = dyn_cast(Op)) + WorkList.append(I->op_begin(), I->op_end()); + } // We compare the costs of a vector.reduce.add to sequential add. int AddOpCode = IsIntVec ? Instruction::Add : Instruction::FAdd; @@ -1412,16 +1437,16 @@ public: FusedInsts.insert(MatMul); IRBuilder<> Builder(MatMul); auto FlattenArg = [&Builder, &FusedInsts, &CanBeFlattened, - this](Value *Op) -> Value * { + this](Value *Op) { // Matmul must be the only user of loads because we don't use LowerLoad // for row vectors (LowerLoad results in scalar loads and shufflevectors // instead of single vector load). if (!CanBeFlattened(Op)) - return Op; + return; if (match(Op, m_BinOp()) && ShapeMap.find(Op) != ShapeMap.end()) { ShapeMap[Op] = ShapeMap[Op].t(); - return Op; + return; } FusedInsts.insert(cast(Op)); @@ -1432,16 +1457,19 @@ public: auto *NewLoad = Builder.CreateLoad(Op->getType(), Arg); Op->replaceAllUsesWith(NewLoad); cast(Op)->eraseFromParent(); - return NewLoad; + return; } else if (match(Op, m_Intrinsic( m_Value(Arg)))) { ToRemove.push_back(cast(Op)); - return Arg; + Op->replaceAllUsesWith(Arg); + return; } - - return Op; }; - LHS = FlattenArg(LHS); + + for (auto *V : ToFlatten) + FlattenArg(V); + + LHS = MatMul->getArgOperand(0); // Insert mul/fmul and llvm.vector.reduce.fadd Value *Mul = diff --git a/llvm/test/Transforms/LowerMatrixIntrinsics/dot-product-int.ll b/llvm/test/Transforms/LowerMatrixIntrinsics/dot-product-int.ll index 7bbd0c500485..f15dbed1f1f5 100644 --- a/llvm/test/Transforms/LowerMatrixIntrinsics/dot-product-int.ll +++ b/llvm/test/Transforms/LowerMatrixIntrinsics/dot-product-int.ll @@ -119,44 +119,15 @@ entry: define <1 x i32> @add_chain_feeding_dotproduct_i32_v8_1(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i32> %d) { ; CHECK-LABEL: @add_chain_feeding_dotproduct_i32_v8_1( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[SPLIT:%.*]] = shufflevector <8 x i32> [[A:%.*]], <8 x i32> poison, <1 x i32> zeroinitializer -; CHECK-NEXT: [[SPLIT1:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> poison, <1 x i32> -; CHECK-NEXT: [[SPLIT2:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> poison, <1 x i32> -; CHECK-NEXT: [[SPLIT3:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> poison, <1 x i32> -; CHECK-NEXT: [[SPLIT4:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> poison, <1 x i32> -; CHECK-NEXT: [[SPLIT5:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> poison, <1 x i32> -; CHECK-NEXT: [[SPLIT6:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> poison, <1 x i32> -; CHECK-NEXT: [[SPLIT7:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> poison, <1 x i32> -; CHECK-NEXT: [[SPLIT8:%.*]] = shufflevector <8 x i32> [[B:%.*]], <8 x i32> poison, <1 x i32> zeroinitializer -; CHECK-NEXT: [[SPLIT9:%.*]] = shufflevector <8 x i32> [[B]], <8 x i32> poison, <1 x i32> -; CHECK-NEXT: [[SPLIT10:%.*]] = shufflevector <8 x i32> [[B]], <8 x i32> poison, <1 x i32> -; CHECK-NEXT: [[SPLIT11:%.*]] = shufflevector <8 x i32> [[B]], <8 x i32> poison, <1 x i32> -; CHECK-NEXT: [[SPLIT12:%.*]] = shufflevector <8 x i32> [[B]], <8 x i32> poison, <1 x i32> -; CHECK-NEXT: [[SPLIT13:%.*]] = shufflevector <8 x i32> [[B]], <8 x i32> poison, <1 x i32> -; CHECK-NEXT: [[SPLIT14:%.*]] = shufflevector <8 x i32> [[B]], <8 x i32> poison, <1 x i32> -; CHECK-NEXT: [[SPLIT15:%.*]] = shufflevector <8 x i32> [[B]], <8 x i32> poison, <1 x i32> -; CHECK-NEXT: [[TMP0:%.*]] = add <1 x i32> [[SPLIT]], [[SPLIT8]] -; CHECK-NEXT: [[TMP1:%.*]] = add <1 x i32> [[SPLIT1]], [[SPLIT9]] -; CHECK-NEXT: [[TMP2:%.*]] = add <1 x i32> [[SPLIT2]], [[SPLIT10]] -; CHECK-NEXT: [[TMP3:%.*]] = add <1 x i32> [[SPLIT3]], [[SPLIT11]] -; CHECK-NEXT: [[TMP4:%.*]] = add <1 x i32> [[SPLIT4]], [[SPLIT12]] -; CHECK-NEXT: [[TMP5:%.*]] = add <1 x i32> [[SPLIT5]], [[SPLIT13]] -; CHECK-NEXT: [[TMP6:%.*]] = add <1 x i32> [[SPLIT6]], [[SPLIT14]] -; CHECK-NEXT: [[TMP7:%.*]] = add <1 x i32> [[SPLIT7]], [[SPLIT15]] -; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <1 x i32> [[TMP0]], <1 x i32> [[TMP1]], <2 x i32> -; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <1 x i32> [[TMP2]], <1 x i32> [[TMP3]], <2 x i32> -; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <1 x i32> [[TMP4]], <1 x i32> [[TMP5]], <2 x i32> -; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <1 x i32> [[TMP6]], <1 x i32> [[TMP7]], <2 x i32> -; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <2 x i32> [[TMP8]], <2 x i32> [[TMP9]], <4 x i32> -; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <2 x i32> [[TMP10]], <2 x i32> [[TMP11]], <4 x i32> -; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x i32> [[TMP12]], <4 x i32> [[TMP13]], <8 x i32> -; CHECK-NEXT: [[SPLIT16:%.*]] = shufflevector <8 x i32> [[TMP14]], <8 x i32> poison, <8 x i32> -; CHECK-NEXT: [[SPLIT17:%.*]] = shufflevector <8 x i32> [[C:%.*]], <8 x i32> poison, <8 x i32> -; CHECK-NEXT: [[TMP15:%.*]] = add <8 x i32> [[SPLIT16]], [[SPLIT17]] -; CHECK-NEXT: [[TMP16:%.*]] = mul <8 x i32> [[TMP15]], [[D:%.*]] -; CHECK-NEXT: [[TMP17:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[TMP16]]) -; CHECK-NEXT: [[TMP18:%.*]] = insertelement <1 x i32> poison, i32 [[TMP17]], i64 0 -; CHECK-NEXT: ret <1 x i32> [[TMP18]] +; CHECK-NEXT: [[SPLIT:%.*]] = shufflevector <8 x i32> [[A:%.*]], <8 x i32> poison, <8 x i32> +; CHECK-NEXT: [[SPLIT1:%.*]] = shufflevector <8 x i32> [[B:%.*]], <8 x i32> poison, <8 x i32> +; CHECK-NEXT: [[TMP0:%.*]] = add <8 x i32> [[SPLIT]], [[SPLIT1]] +; CHECK-NEXT: [[SPLIT2:%.*]] = shufflevector <8 x i32> [[C:%.*]], <8 x i32> poison, <8 x i32> +; CHECK-NEXT: [[TMP1:%.*]] = add <8 x i32> [[TMP0]], [[SPLIT2]] +; CHECK-NEXT: [[TMP2:%.*]] = mul <8 x i32> [[TMP1]], [[D:%.*]] +; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[TMP2]]) +; CHECK-NEXT: [[TMP4:%.*]] = insertelement <1 x i32> poison, i32 [[TMP3]], i64 0 +; CHECK-NEXT: ret <1 x i32> [[TMP4]] ; entry: %add.1 = add <8 x i32> %a, %b -- GitLab From ffd79b3312cea51c0787aad479ce285771470397 Mon Sep 17 00:00:00 2001 From: Sergey Kachkov <109674256+skachkov-sc@users.noreply.github.com> Date: Tue, 6 Feb 2024 17:01:38 +0300 Subject: [PATCH 074/266] [LoopUnroll] Consider simplified operands while retrieving TTI instruction cost (#70929) Get more precise cost of instruction after LoopUnroll considering that some operands of it can be simplified, e.g. induction variable will be replaced by constant after full unrolling. --- llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp | 10 +++++- .../AMDGPU/unroll-cost-addrspacecast.ll | 22 ++++++++---- .../Transforms/LoopUnroll/RISCV/unroll-Os.ll | 35 +++++++++++++++++++ 3 files changed, 59 insertions(+), 8 deletions(-) create mode 100644 llvm/test/Transforms/LoopUnroll/RISCV/unroll-Os.ll diff --git a/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp b/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp index 7dfe4aca6fe4..75fb8765061e 100644 --- a/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp +++ b/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp @@ -450,7 +450,15 @@ static std::optional analyzeLoopUnrollCost( // First accumulate the cost of this instruction. if (!Cost.IsFree) { - UnrolledCost += TTI.getInstructionCost(I, CostKind); + // Consider simplified operands in instruction cost. + SmallVector Operands; + transform(I->operands(), std::back_inserter(Operands), + [&](Value *Op) { + if (auto Res = SimplifiedValues.lookup(Op)) + return Res; + return Op; + }); + UnrolledCost += TTI.getInstructionCost(I, Operands, CostKind); LLVM_DEBUG(dbgs() << "Adding cost of instruction (iteration " << Iteration << "): "); LLVM_DEBUG(I->dump()); diff --git a/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-cost-addrspacecast.ll b/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-cost-addrspacecast.ll index 6ec64bfba895..d189f9170485 100644 --- a/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-cost-addrspacecast.ll +++ b/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-cost-addrspacecast.ll @@ -1,4 +1,6 @@ -; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=hawaii -passes=loop-unroll -unroll-threshold=49 -unroll-peel-count=0 -unroll-allow-partial=false -unroll-max-iteration-count-to-analyze=16 < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=hawaii -passes=loop-unroll -unroll-threshold=57 -unroll-peel-count=0 -unroll-allow-partial=false -unroll-max-iteration-count-to-analyze=16 < %s | FileCheck %s + +@indices = external global [16 x i32] ; CHECK-LABEL: @test_func_addrspacecast_cost_noop( ; CHECK-NOT: br i1 @@ -9,8 +11,10 @@ entry: for.body: %indvars.iv = phi i32 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %sum.02 = phi float [ %fmul, %for.body ], [ 0.0, %entry ] - %arrayidx.in = getelementptr inbounds float, ptr addrspace(1) %in, i32 %indvars.iv - %arrayidx.out = getelementptr inbounds float, ptr addrspace(1) %out, i32 %indvars.iv + %idx.ptr = getelementptr inbounds [16 x i32], ptr @indices, i32 0, i32 %indvars.iv + %index = load i32, ptr %idx.ptr + %arrayidx.in = getelementptr inbounds float, ptr addrspace(1) %in, i32 %index + %arrayidx.out = getelementptr inbounds float, ptr addrspace(1) %out, i32 %index %cast.in = addrspacecast ptr addrspace(1) %arrayidx.in to ptr %cast.out = addrspacecast ptr addrspace(1) %arrayidx.out to ptr %load = load float, ptr %cast.in @@ -34,8 +38,10 @@ entry: for.body: %indvars.iv = phi i32 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %sum.02 = phi float [ %fmul, %for.body ], [ 0.0, %entry ] - %arrayidx.in = getelementptr inbounds float, ptr %in, i32 %indvars.iv - %arrayidx.out = getelementptr inbounds float, ptr %out, i32 %indvars.iv + %idx.ptr = getelementptr inbounds [16 x i32], ptr @indices, i32 0, i32 %indvars.iv + %index = load i32, ptr %idx.ptr + %arrayidx.in = getelementptr inbounds float, ptr %in, i32 %index + %arrayidx.out = getelementptr inbounds float, ptr %out, i32 %index %cast.in = addrspacecast ptr %arrayidx.in to ptr addrspace(3) %cast.out = addrspacecast ptr %arrayidx.out to ptr addrspace(3) %load = load float, ptr addrspace(3) %cast.in @@ -58,8 +64,10 @@ entry: for.body: %indvars.iv = phi i32 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %sum.02 = phi float [ %fmul, %for.body ], [ 0.0, %entry ] - %arrayidx.in = getelementptr inbounds float, ptr addrspace(3) %in, i32 %indvars.iv - %arrayidx.out = getelementptr inbounds float, ptr addrspace(3) %out, i32 %indvars.iv + %idx.ptr = getelementptr inbounds [16 x i32], ptr @indices, i32 0, i32 %indvars.iv + %index = load i32, ptr %idx.ptr + %arrayidx.in = getelementptr inbounds float, ptr addrspace(3) %in, i32 %index + %arrayidx.out = getelementptr inbounds float, ptr addrspace(3) %out, i32 %index %cast.in = addrspacecast ptr addrspace(3) %arrayidx.in to ptr %cast.out = addrspacecast ptr addrspace(3) %arrayidx.out to ptr %load = load float, ptr %cast.in diff --git a/llvm/test/Transforms/LoopUnroll/RISCV/unroll-Os.ll b/llvm/test/Transforms/LoopUnroll/RISCV/unroll-Os.ll new file mode 100644 index 000000000000..26de40bf1dc1 --- /dev/null +++ b/llvm/test/Transforms/LoopUnroll/RISCV/unroll-Os.ll @@ -0,0 +1,35 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 +; RUN: opt < %s -S -mtriple=riscv64 -passes=loop-unroll | FileCheck %s + +; Function Attrs: optsize +define void @foo(ptr %array, i32 %x) #0 { +; CHECK-LABEL: define void @foo +; CHECK-SAME: (ptr [[ARRAY:%.*]], i32 [[X:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[FOR_BODY:%.*]] +; CHECK: for.body: +; CHECK-NEXT: store i32 [[X]], ptr [[ARRAY]], align 4 +; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[ARRAY]], i64 1 +; CHECK-NEXT: store i32 [[X]], ptr [[ARRAYIDX_1]], align 4 +; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[ARRAY]], i64 2 +; CHECK-NEXT: store i32 [[X]], ptr [[ARRAYIDX_2]], align 4 +; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[ARRAY]], i64 3 +; CHECK-NEXT: store i32 [[X]], ptr [[ARRAYIDX_3]], align 4 +; CHECK-NEXT: ret void +; +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %arrayidx = getelementptr inbounds i32, ptr %array, i64 %indvars.iv + store i32 %x, ptr %arrayidx, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond.not = icmp eq i64 %indvars.iv.next, 4 + br i1 %exitcond.not, label %for.cond.cleanup, label %for.body + +for.cond.cleanup: + ret void +} + +attributes #0 = { optsize } -- GitLab From 62c352e13c145b5606ace88ecbe9164ff011b5cf Mon Sep 17 00:00:00 2001 From: Zahira Ammarguellat Date: Tue, 6 Feb 2024 06:23:22 -0800 Subject: [PATCH 075/266] [CLANG] Fix INF/NAN warning. (#80290) In https://github.com/llvm/llvm-project/pull/76873 a warning was added when the macros INFINITY and NAN are used in binary expressions when -menable-no-nans or -menable-no-infs are used. If the user uses an option that nullifies these two options, the warning will still be generated. This patch adds an additional information to the warning comment to let the user know about this. It also suppresses the warning when #ifdef INFINITY, #ifdef NAN, #ifdef NAN or #ifndef NAN are used in the code. --- .../clang/Basic/DiagnosticCommonKinds.td | 2 +- clang/include/clang/Basic/DiagnosticDocs.td | 9 +++ clang/include/clang/Lex/Preprocessor.h | 11 ++-- clang/lib/Lex/PPDirectives.cpp | 2 +- clang/lib/Lex/PPExpressions.cpp | 4 +- .../Sema/warn-infinity-nan-disabled-lnx.cpp | 60 ++++++++++++++++--- .../Sema/warn-infinity-nan-disabled-win.cpp | 60 ++++++++++++++++--- 7 files changed, 126 insertions(+), 22 deletions(-) diff --git a/clang/include/clang/Basic/DiagnosticCommonKinds.td b/clang/include/clang/Basic/DiagnosticCommonKinds.td index b1bada65cb6b..08bb1d81ba29 100644 --- a/clang/include/clang/Basic/DiagnosticCommonKinds.td +++ b/clang/include/clang/Basic/DiagnosticCommonKinds.td @@ -73,7 +73,7 @@ def warn_pragma_debug_unexpected_argument : Warning< def warn_fp_nan_inf_when_disabled : Warning< "use of %select{infinity|NaN}0%select{| via a macro}1 is undefined behavior " "due to the currently enabled floating-point options">, - InGroup>; + InGroup>; } // Parse && Sema diff --git a/clang/include/clang/Basic/DiagnosticDocs.td b/clang/include/clang/Basic/DiagnosticDocs.td index e9862422b499..8c024b5cad74 100644 --- a/clang/include/clang/Basic/DiagnosticDocs.td +++ b/clang/include/clang/Basic/DiagnosticDocs.td @@ -87,3 +87,12 @@ program by treating all string literals as having type ``const char *`` instead of ``char *``. This can cause unexpected behaviors with type-sensitive constructs like ``_Generic``. }]; + +defvar NanInfDisabledDocs = [{ +This warning is enabled when source code using the macros ``INFINITY`` or ``NAN`` +is compiled with floating-point options preventing these two values. This can +lead to undefined behavior. Check the order of command line arguments that modify +this behavior, such as ``-ffast-math``, ``-fhonor-infinities``, and +``-fhonor-nans`` (etc), as well as ``#pragma`` directives if this diagnostic is +generated unexpectedly. +}]; diff --git a/clang/include/clang/Lex/Preprocessor.h b/clang/include/clang/Lex/Preprocessor.h index 9d0d53129a12..0836b7d439bb 100644 --- a/clang/include/clang/Lex/Preprocessor.h +++ b/clang/include/clang/Lex/Preprocessor.h @@ -2838,7 +2838,8 @@ public: return AnnotationInfos.find(II)->second; } - void emitMacroExpansionWarnings(const Token &Identifier) const { + void emitMacroExpansionWarnings(const Token &Identifier, + bool IsIfnDef = false) const { IdentifierInfo *Info = Identifier.getIdentifierInfo(); if (Info->isDeprecatedMacro()) emitMacroDeprecationWarning(Identifier); @@ -2847,12 +2848,12 @@ public: !SourceMgr.isInMainFile(Identifier.getLocation())) emitRestrictExpansionWarning(Identifier); - if (Info->getName() == "INFINITY") - if (getLangOpts().NoHonorInfs) + if (!IsIfnDef) { + if (Info->getName() == "INFINITY" && getLangOpts().NoHonorInfs) emitRestrictInfNaNWarning(Identifier, 0); - if (Info->getName() == "NAN") - if (getLangOpts().NoHonorNaNs) + if (Info->getName() == "NAN" && getLangOpts().NoHonorNaNs) emitRestrictInfNaNWarning(Identifier, 1); + } } static void processPathForFileMacro(SmallVectorImpl &Path, diff --git a/clang/lib/Lex/PPDirectives.cpp b/clang/lib/Lex/PPDirectives.cpp index 9f82a6d073e3..a980f4bcbae1 100644 --- a/clang/lib/Lex/PPDirectives.cpp +++ b/clang/lib/Lex/PPDirectives.cpp @@ -3288,7 +3288,7 @@ void Preprocessor::HandleIfdefDirective(Token &Result, return; } - emitMacroExpansionWarnings(MacroNameTok); + emitMacroExpansionWarnings(MacroNameTok, /*IsIfnDef=*/true); // Check to see if this is the last token on the #if[n]def line. CheckEndOfDirective(isIfndef ? "ifndef" : "ifdef"); diff --git a/clang/lib/Lex/PPExpressions.cpp b/clang/lib/Lex/PPExpressions.cpp index 1feb0eb18d71..8f25c67ec9df 100644 --- a/clang/lib/Lex/PPExpressions.cpp +++ b/clang/lib/Lex/PPExpressions.cpp @@ -133,7 +133,9 @@ static bool EvaluateDefined(PPValue &Result, Token &PeekTok, DefinedTracker &DT, Result.Val.setIsUnsigned(false); // Result is signed intmax_t. DT.IncludedUndefinedIds = !Macro; - PP.emitMacroExpansionWarnings(PeekTok); + PP.emitMacroExpansionWarnings( + PeekTok, + (II->getName() == "INFINITY" || II->getName() == "NAN") ? true : false); // If there is a macro, mark it used. if (Result.Val != 0 && ValueLive) diff --git a/clang/test/Sema/warn-infinity-nan-disabled-lnx.cpp b/clang/test/Sema/warn-infinity-nan-disabled-lnx.cpp index 8a610fa0e737..03a432e05851 100644 --- a/clang/test/Sema/warn-infinity-nan-disabled-lnx.cpp +++ b/clang/test/Sema/warn-infinity-nan-disabled-lnx.cpp @@ -1,13 +1,31 @@ -// RUN: %clang_cc1 -x c++ -verify=no-inf-no-nan -triple powerpc64le-unknown-unknown %s \ -// RUN: -menable-no-infs -menable-no-nans +// RUN: %clang_cc1 -x c++ -verify=no-inf-no-nan \ +// RUN: -triple powerpc64le-unknown-unknown %s -menable-no-infs \ +// RUN: -menable-no-nans -std=c++23 -// RUN: %clang_cc1 -x c++ -verify=no-fast -triple powerpc64le-unknown-unknown %s +// RUN: %clang_cc1 -x c++ -verify=no-inf-no-nan \ +// RUN: -triple powerpc64le-unknown-unknown %s -menable-no-infs \ +// RUN: -menable-no-nans -funsafe-math-optimizations -std=c++23 + +// RUN: %clang_cc1 -x c++ -verify=no-fast -triple powerpc64le-unknown-unknown \ +// RUN: %s -std=c++23 + +// RUN: %clang_cc1 -x c++ -verify=no-inf -triple powerpc64le-unknown-unknown %s \ +// RUN: -menable-no-infs -std=c++23 // RUN: %clang_cc1 -x c++ -verify=no-inf -triple powerpc64le-unknown-unknown %s \ -// RUN: -menable-no-infs +// RUN: -menable-no-infs -funsafe-math-optimizations -std=c++23 + +// RUN: %clang_cc1 -x c++ -verify=no-nan -triple powerpc64le-unknown-unknown %s \ +// RUN: -menable-no-nans -std=c++23 // RUN: %clang_cc1 -x c++ -verify=no-nan -triple powerpc64le-unknown-unknown %s \ -// RUN: -menable-no-nans +// RUN: -funsafe-math-optimizations -menable-no-nans -std=c++23 + +// RUN: %clang_cc1 -x c++ -verify=no-fast -triple powerpc64le-unknown-unknown \ +// RUN: %s -Wno-nan-infinity-disabled -menable-no-infs -std=c++23 + +// RUN: %clang_cc1 -x c++ -verify=no-fast -triple powerpc64le-unknown-unknown \ +// RUN: %s -Wno-nan-infinity-disabled -menable-no-nans -std=c++23 // no-fast-no-diagnostics @@ -133,13 +151,41 @@ int compareit(float a, float b) { // no-inf-warning@+1 {{use of infinity is undefined behavior due to the currently enabled floating-point options}} p = __builtin_isfinite(a); - // These should NOT warn, since they are not using NaN or infinity. +// These should NOT warn, since they are not using NaN or infinity. j = a > 1.1; j = b < 1.1; j = a >= 1.1; j = b <= 1.1; j = isunorderedf(a, b); +#ifndef INFINITY + j = a; +#endif +#ifndef NAN + j = b; +#endif +#ifdef INFINITY + j = a; +#endif +#ifdef NAN + j = b; +#endif +#if defined(INFINITY) + j = a; +#elifndef(INFINITY) + j = b; +#endif +#if defined(INFINITY) + j = a; +#elifndef(NAN) + j = b; +#endif +#if defined(NAN) + j = a; +#elifndef(INFINITY) + j = b; +#endif + // no-inf-no-nan-warning@+4 {{use of NaN via a macro is undefined behavior due to the currently enabled floating-point options}} // no-inf-no-nan-warning@+3 {{use of NaN is undefined behavior due to the currently enabled floating-point options}} // no-nan-warning@+2 {{use of NaN via a macro is undefined behavior due to the currently enabled floating-point options}} @@ -173,4 +219,4 @@ int compareit(float a, float b) { j = numeric_limits::infinity(); return 0; -} +} diff --git a/clang/test/Sema/warn-infinity-nan-disabled-win.cpp b/clang/test/Sema/warn-infinity-nan-disabled-win.cpp index 19a575386e32..51f9d325619b 100644 --- a/clang/test/Sema/warn-infinity-nan-disabled-win.cpp +++ b/clang/test/Sema/warn-infinity-nan-disabled-win.cpp @@ -1,16 +1,34 @@ // Use of NAN macro will trigger a warning "infinity defined in macro" because // on Windows the NAN macro is defined using INFINITY. See below. -// RUN: %clang_cc1 -x c++ -verify=no-inf-no-nan -triple powerpc64le-unknown-unknown %s \ -// RUN: -menable-no-infs -menable-no-nans +// RUN: %clang_cc1 -x c++ -verify=no-inf-no-nan \ +// RUN: -triple powerpc64le-unknown-unknown %s -menable-no-infs \ +// RUN: -menable-no-nans -std=c++23 -// RUN: %clang_cc1 -x c++ -verify=no-fast -triple powerpc64le-unknown-unknown %s +// RUN: %clang_cc1 -x c++ -verify=no-inf-no-nan \ +// RUN: -triple powerpc64le-unknown-unknown %s -menable-no-infs \ +// RUN: -menable-no-nans -funsafe-math-optimizations -std=c++23 + +// RUN: %clang_cc1 -x c++ -verify=no-fast -triple powerpc64le-unknown-unknown \ +// RUN: %s -std=c++23 + +// RUN: %clang_cc1 -x c++ -verify=no-inf -triple powerpc64le-unknown-unknown %s \ +// RUN: -menable-no-infs -std=c++23 // RUN: %clang_cc1 -x c++ -verify=no-inf -triple powerpc64le-unknown-unknown %s \ -// RUN: -menable-no-infs +// RUN: -menable-no-infs -funsafe-math-optimizations -std=c++23 + +// RUN: %clang_cc1 -x c++ -verify=no-nan -triple powerpc64le-unknown-unknown %s \ +// RUN: -menable-no-nans -std=c++23 // RUN: %clang_cc1 -x c++ -verify=no-nan -triple powerpc64le-unknown-unknown %s \ -// RUN: -menable-no-nans +// RUN: -funsafe-math-optimizations -menable-no-nans -std=c++23 + +// RUN: %clang_cc1 -x c++ -verify=no-fast -triple powerpc64le-unknown-unknown \ +// RUN: %s -Wno-nan-infinity-disabled -menable-no-infs -std=c++23 + +// RUN: %clang_cc1 -x c++ -verify=no-fast -triple powerpc64le-unknown-unknown \ +// RUN: %s -Wno-nan-infinity-disabled -menable-no-nans -std=c++23 // no-fast-no-diagnostics @@ -136,13 +154,41 @@ int compareit(float a, float b) { // no-inf-warning@+1 {{use of infinity is undefined behavior due to the currently enabled floating-point options}} p = __builtin_isfinite(a); - // These should NOT warn, since they are not using NaN or infinity. +// These should NOT warn, since they are not using NaN or infinity. j = a > 1.1; j = b < 1.1; j = a >= 1.1; j = b <= 1.1; j = isunorderedf(a, b); +#ifndef INFINITY + j = a; +#endif +#ifndef NAN + j = b; +#endif +#ifdef INFINITY + j = a; +#endif +#ifdef NAN + j = b; +#endif +#if defined(INFINITY) + j = a; +#elifndef(INFINITY) + j = b; +#endif +#if defined(INFINITY) + j = a; +#elifndef(NAN) + j = b; +#endif +#if defined(NAN) + j = a; +#elifndef(INFINITY) + j = b; +#endif + // no-inf-no-nan-warning@+4 {{use of infinity via a macro is undefined behavior due to the currently enabled floating-point option}} // no-inf-no-nan-warning@+3 {{use of NaN via a macro is undefined behavior due to the currently enabled floating-point options}} // no-inf-warning@+2 {{use of infinity via a macro is undefined behavior due to the currently enabled floating-point options}} @@ -176,4 +222,4 @@ int compareit(float a, float b) { j = numeric_limits::infinity(); return 0; -} +} -- GitLab From d5a3de4aeef4f4f1c52692533ddb9fdf45aef9d3 Mon Sep 17 00:00:00 2001 From: Nick Desaulniers Date: Tue, 6 Feb 2024 06:27:03 -0800 Subject: [PATCH 076/266] [libc][stdbit] implement stdc_trailing_zeros (C23) (#80344) --- libc/config/linux/x86_64/entrypoints.txt | 5 + libc/include/llvm-libc-macros/stdbit-macros.h | 22 +++ libc/spec/stdc.td | 11 +- libc/src/stdbit/CMakeLists.txt | 118 +++------------- libc/src/stdbit/stdc_trailing_zeros_uc.cpp | 20 +++ libc/src/stdbit/stdc_trailing_zeros_uc.h | 18 +++ libc/src/stdbit/stdc_trailing_zeros_ui.cpp | 20 +++ libc/src/stdbit/stdc_trailing_zeros_ui.h | 18 +++ libc/src/stdbit/stdc_trailing_zeros_ul.cpp | 20 +++ libc/src/stdbit/stdc_trailing_zeros_ul.h | 18 +++ libc/src/stdbit/stdc_trailing_zeros_ull.cpp | 21 +++ libc/src/stdbit/stdc_trailing_zeros_ull.h | 18 +++ libc/src/stdbit/stdc_trailing_zeros_us.cpp | 20 +++ libc/src/stdbit/stdc_trailing_zeros_us.h | 18 +++ libc/test/include/stdbit_test.cpp | 13 ++ libc/test/src/stdbit/CMakeLists.txt | 130 +++--------------- .../stdbit/stdc_trailing_zeros_uc_test.cpp | 21 +++ .../stdbit/stdc_trailing_zeros_ui_test.cpp | 21 +++ .../stdbit/stdc_trailing_zeros_ul_test.cpp | 21 +++ .../stdbit/stdc_trailing_zeros_ull_test.cpp | 21 +++ .../stdbit/stdc_trailing_zeros_us_test.cpp | 21 +++ 21 files changed, 384 insertions(+), 211 deletions(-) create mode 100644 libc/src/stdbit/stdc_trailing_zeros_uc.cpp create mode 100644 libc/src/stdbit/stdc_trailing_zeros_uc.h create mode 100644 libc/src/stdbit/stdc_trailing_zeros_ui.cpp create mode 100644 libc/src/stdbit/stdc_trailing_zeros_ui.h create mode 100644 libc/src/stdbit/stdc_trailing_zeros_ul.cpp create mode 100644 libc/src/stdbit/stdc_trailing_zeros_ul.h create mode 100644 libc/src/stdbit/stdc_trailing_zeros_ull.cpp create mode 100644 libc/src/stdbit/stdc_trailing_zeros_ull.h create mode 100644 libc/src/stdbit/stdc_trailing_zeros_us.cpp create mode 100644 libc/src/stdbit/stdc_trailing_zeros_us.h create mode 100644 libc/test/src/stdbit/stdc_trailing_zeros_uc_test.cpp create mode 100644 libc/test/src/stdbit/stdc_trailing_zeros_ui_test.cpp create mode 100644 libc/test/src/stdbit/stdc_trailing_zeros_ul_test.cpp create mode 100644 libc/test/src/stdbit/stdc_trailing_zeros_ull_test.cpp create mode 100644 libc/test/src/stdbit/stdc_trailing_zeros_us_test.cpp diff --git a/libc/config/linux/x86_64/entrypoints.txt b/libc/config/linux/x86_64/entrypoints.txt index a1236817d2d1..2ac9a7444a1e 100644 --- a/libc/config/linux/x86_64/entrypoints.txt +++ b/libc/config/linux/x86_64/entrypoints.txt @@ -102,6 +102,11 @@ set(TARGET_LIBC_ENTRYPOINTS libc.src.stdbit.stdc_leading_ones_ui libc.src.stdbit.stdc_leading_ones_ul libc.src.stdbit.stdc_leading_ones_ull + libc.src.stdbit.stdc_trailing_zeros_uc + libc.src.stdbit.stdc_trailing_zeros_us + libc.src.stdbit.stdc_trailing_zeros_ui + libc.src.stdbit.stdc_trailing_zeros_ul + libc.src.stdbit.stdc_trailing_zeros_ull # stdlib.h entrypoints libc.src.stdlib.abs diff --git a/libc/include/llvm-libc-macros/stdbit-macros.h b/libc/include/llvm-libc-macros/stdbit-macros.h index cc964a5268b0..15e391288357 100644 --- a/libc/include/llvm-libc-macros/stdbit-macros.h +++ b/libc/include/llvm-libc-macros/stdbit-macros.h @@ -40,6 +40,21 @@ inline unsigned stdc_leading_ones(unsigned long x) { inline unsigned stdc_leading_ones(unsigned long long x) { return stdc_leading_ones_ull(x); } +inline unsigned stdc_trailing_zeros(unsigned char x) { + return stdc_trailing_zeros_uc(x); +} +inline unsigned stdc_trailing_zeros(unsigned short x) { + return stdc_trailing_zeros_us(x); +} +inline unsigned stdc_trailing_zeros(unsigned x) { + return stdc_trailing_zeros_ui(x); +} +inline unsigned stdc_trailing_zeros(unsigned long x) { + return stdc_trailing_zeros_ul(x); +} +inline unsigned stdc_trailing_zeros(unsigned long long x) { + return stdc_trailing_zeros_ull(x); +} #else #define stdc_leading_zeros(x) \ _Generic((x), \ @@ -55,6 +70,13 @@ inline unsigned stdc_leading_ones(unsigned long long x) { unsigned: stdc_leading_ones_ui, \ unsigned long: stdc_leading_ones_ul, \ unsigned long long: stdc_leading_ones_ull)(x) +#define stdc_trailing_zeros(x) \ + _Generic((x), \ + unsigned char: stdc_trailing_zeros_uc, \ + unsigned short: stdc_trailing_zeros_us, \ + unsigned: stdc_trailing_zeros_ui, \ + unsigned long: stdc_trailing_zeros_ul, \ + unsigned long long: stdc_trailing_zeros_ull)(x) #endif // __cplusplus #endif // __LLVM_LIBC_MACROS_STDBIT_MACROS_H diff --git a/libc/spec/stdc.td b/libc/spec/stdc.td index 607dda7c9041..3a162b0bc76f 100644 --- a/libc/spec/stdc.td +++ b/libc/spec/stdc.td @@ -775,7 +775,9 @@ def StdC : StandardSpec<"stdc"> { HeaderSpec StdBit = HeaderSpec< "stdbit.h", [ - Macro<"stdc_leading_zeros"> + Macro<"stdc_leading_zeros">, + Macro<"stdc_leading_ones">, + Macro<"stdc_trailing_zeros"> ], // Macros [], // Types [], // Enumerations @@ -789,7 +791,12 @@ def StdC : StandardSpec<"stdc"> { FunctionSpec<"stdc_leading_ones_us", RetValSpec, [ArgSpec]>, FunctionSpec<"stdc_leading_ones_ui", RetValSpec, [ArgSpec]>, FunctionSpec<"stdc_leading_ones_ul", RetValSpec, [ArgSpec]>, - FunctionSpec<"stdc_leading_ones_ull", RetValSpec, [ArgSpec]> + FunctionSpec<"stdc_leading_ones_ull", RetValSpec, [ArgSpec]>, + FunctionSpec<"stdc_trailing_zeros_uc", RetValSpec, [ArgSpec]>, + FunctionSpec<"stdc_trailing_zeros_us", RetValSpec, [ArgSpec]>, + FunctionSpec<"stdc_trailing_zeros_ui", RetValSpec, [ArgSpec]>, + FunctionSpec<"stdc_trailing_zeros_ul", RetValSpec, [ArgSpec]>, + FunctionSpec<"stdc_trailing_zeros_ull", RetValSpec, [ArgSpec]> ] // Functions >; diff --git a/libc/src/stdbit/CMakeLists.txt b/libc/src/stdbit/CMakeLists.txt index d7daff44dfda..35df7f9c41ec 100644 --- a/libc/src/stdbit/CMakeLists.txt +++ b/libc/src/stdbit/CMakeLists.txt @@ -1,99 +1,19 @@ -add_entrypoint_object( - stdc_leading_zeros_uc - SRCS - stdc_leading_zeros_uc.cpp - HDRS - stdc_leading_zeros_uc.h - DEPENDS - libc.src.__support.CPP.bit -) - -add_entrypoint_object( - stdc_leading_zeros_us - SRCS - stdc_leading_zeros_us.cpp - HDRS - stdc_leading_zeros_us.h - DEPENDS - libc.src.__support.CPP.bit -) - -add_entrypoint_object( - stdc_leading_zeros_ui - SRCS - stdc_leading_zeros_ui.cpp - HDRS - stdc_leading_zeros_ui.h - DEPENDS - libc.src.__support.CPP.bit -) - -add_entrypoint_object( - stdc_leading_zeros_ul - SRCS - stdc_leading_zeros_ul.cpp - HDRS - stdc_leading_zeros_ul.h - DEPENDS - libc.src.__support.CPP.bit -) - -add_entrypoint_object( - stdc_leading_zeros_ull - SRCS - stdc_leading_zeros_ull.cpp - HDRS - stdc_leading_zeros_ull.h - DEPENDS - libc.src.__support.CPP.bit -) - -add_entrypoint_object( - stdc_leading_ones_uc - SRCS - stdc_leading_ones_uc.cpp - HDRS - stdc_leading_ones_uc.h - DEPENDS - libc.src.__support.CPP.bit -) - -add_entrypoint_object( - stdc_leading_ones_us - SRCS - stdc_leading_ones_us.cpp - HDRS - stdc_leading_ones_us.h - DEPENDS - libc.src.__support.CPP.bit -) - -add_entrypoint_object( - stdc_leading_ones_ui - SRCS - stdc_leading_ones_ui.cpp - HDRS - stdc_leading_ones_ui.h - DEPENDS - libc.src.__support.CPP.bit -) - -add_entrypoint_object( - stdc_leading_ones_ul - SRCS - stdc_leading_ones_ul.cpp - HDRS - stdc_leading_ones_ul.h - DEPENDS - libc.src.__support.CPP.bit -) - -add_entrypoint_object( - stdc_leading_ones_ull - SRCS - stdc_leading_ones_ull.cpp - HDRS - stdc_leading_ones_ull.h - DEPENDS - libc.src.__support.CPP.bit -) +set(prefixes + leading_zeros + leading_ones + trailing_zeros +) +set(suffixes c s i l ll) +foreach(prefix IN LISTS prefixes) + foreach(suffix IN LISTS suffixes) + add_entrypoint_object( + stdc_${prefix}_u${suffix} + SRCS + stdc_${prefix}_u${suffix}.cpp + HDRS + stdc_${prefix}_u${suffix}.h + DEPENDS + libc.src.__support.CPP.bit + ) + endforeach() +endforeach() diff --git a/libc/src/stdbit/stdc_trailing_zeros_uc.cpp b/libc/src/stdbit/stdc_trailing_zeros_uc.cpp new file mode 100644 index 000000000000..36924c5a053a --- /dev/null +++ b/libc/src/stdbit/stdc_trailing_zeros_uc.cpp @@ -0,0 +1,20 @@ +//===-- Implementation of stdc_trailing_zeros_uc --------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/stdbit/stdc_trailing_zeros_uc.h" + +#include "src/__support/CPP/bit.h" +#include "src/__support/common.h" + +namespace LIBC_NAMESPACE { + +LLVM_LIBC_FUNCTION(unsigned, stdc_trailing_zeros_uc, (unsigned char value)) { + return static_cast(cpp::countr_zero(value)); +} + +} // namespace LIBC_NAMESPACE diff --git a/libc/src/stdbit/stdc_trailing_zeros_uc.h b/libc/src/stdbit/stdc_trailing_zeros_uc.h new file mode 100644 index 000000000000..866201e5acea --- /dev/null +++ b/libc/src/stdbit/stdc_trailing_zeros_uc.h @@ -0,0 +1,18 @@ +//===-- Implementation header for stdc_trailing_zeros_uc --------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ZEROS_UC_H +#define LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ZEROS_UC_H + +namespace LIBC_NAMESPACE { + +unsigned stdc_trailing_zeros_uc(unsigned char value); + +} // namespace LIBC_NAMESPACE + +#endif // LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ZEROS_UC_H diff --git a/libc/src/stdbit/stdc_trailing_zeros_ui.cpp b/libc/src/stdbit/stdc_trailing_zeros_ui.cpp new file mode 100644 index 000000000000..a264fd97f251 --- /dev/null +++ b/libc/src/stdbit/stdc_trailing_zeros_ui.cpp @@ -0,0 +1,20 @@ +//===-- Implementation of stdc_trailing_zeros_ui --------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/stdbit/stdc_trailing_zeros_ui.h" + +#include "src/__support/CPP/bit.h" +#include "src/__support/common.h" + +namespace LIBC_NAMESPACE { + +LLVM_LIBC_FUNCTION(unsigned, stdc_trailing_zeros_ui, (unsigned value)) { + return static_cast(cpp::countr_zero(value)); +} + +} // namespace LIBC_NAMESPACE diff --git a/libc/src/stdbit/stdc_trailing_zeros_ui.h b/libc/src/stdbit/stdc_trailing_zeros_ui.h new file mode 100644 index 000000000000..0642e312f4fe --- /dev/null +++ b/libc/src/stdbit/stdc_trailing_zeros_ui.h @@ -0,0 +1,18 @@ +//===-- Implementation header for stdc_trailing_zeros_ui --------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ZEROS_UI_H +#define LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ZEROS_UI_H + +namespace LIBC_NAMESPACE { + +unsigned stdc_trailing_zeros_ui(unsigned value); + +} // namespace LIBC_NAMESPACE + +#endif // LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ZEROS_UI_H diff --git a/libc/src/stdbit/stdc_trailing_zeros_ul.cpp b/libc/src/stdbit/stdc_trailing_zeros_ul.cpp new file mode 100644 index 000000000000..8e0c36cb0996 --- /dev/null +++ b/libc/src/stdbit/stdc_trailing_zeros_ul.cpp @@ -0,0 +1,20 @@ +//===-- Implementation of stdc_trailing_zeros_ul --------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/stdbit/stdc_trailing_zeros_ul.h" + +#include "src/__support/CPP/bit.h" +#include "src/__support/common.h" + +namespace LIBC_NAMESPACE { + +LLVM_LIBC_FUNCTION(unsigned, stdc_trailing_zeros_ul, (unsigned long value)) { + return static_cast(cpp::countr_zero(value)); +} + +} // namespace LIBC_NAMESPACE diff --git a/libc/src/stdbit/stdc_trailing_zeros_ul.h b/libc/src/stdbit/stdc_trailing_zeros_ul.h new file mode 100644 index 000000000000..e10b4474753a --- /dev/null +++ b/libc/src/stdbit/stdc_trailing_zeros_ul.h @@ -0,0 +1,18 @@ +//===-- Implementation header for stdc_trailing_zeros_ul --------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ZEROS_UL_H +#define LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ZEROS_UL_H + +namespace LIBC_NAMESPACE { + +unsigned stdc_trailing_zeros_ul(unsigned long value); + +} // namespace LIBC_NAMESPACE + +#endif // LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ZEROS_UL_H diff --git a/libc/src/stdbit/stdc_trailing_zeros_ull.cpp b/libc/src/stdbit/stdc_trailing_zeros_ull.cpp new file mode 100644 index 000000000000..77cb20cb1ba4 --- /dev/null +++ b/libc/src/stdbit/stdc_trailing_zeros_ull.cpp @@ -0,0 +1,21 @@ +//===-- Implementation of stdc_trailing_zeros_ull -------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/stdbit/stdc_trailing_zeros_ull.h" + +#include "src/__support/CPP/bit.h" +#include "src/__support/common.h" + +namespace LIBC_NAMESPACE { + +LLVM_LIBC_FUNCTION(unsigned, stdc_trailing_zeros_ull, + (unsigned long long value)) { + return static_cast(cpp::countr_zero(value)); +} + +} // namespace LIBC_NAMESPACE diff --git a/libc/src/stdbit/stdc_trailing_zeros_ull.h b/libc/src/stdbit/stdc_trailing_zeros_ull.h new file mode 100644 index 000000000000..f95169d29f45 --- /dev/null +++ b/libc/src/stdbit/stdc_trailing_zeros_ull.h @@ -0,0 +1,18 @@ +//===-- Implementation header for stdc_trailing_zeros_ull -------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ZEROS_ULL_H +#define LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ZEROS_ULL_H + +namespace LIBC_NAMESPACE { + +unsigned stdc_trailing_zeros_ull(unsigned long long value); + +} // namespace LIBC_NAMESPACE + +#endif // LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ZEROS_ULL_H diff --git a/libc/src/stdbit/stdc_trailing_zeros_us.cpp b/libc/src/stdbit/stdc_trailing_zeros_us.cpp new file mode 100644 index 000000000000..a5b9f4a7d849 --- /dev/null +++ b/libc/src/stdbit/stdc_trailing_zeros_us.cpp @@ -0,0 +1,20 @@ +//===-- Implementation of stdc_trailing_zeros_us --------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/stdbit/stdc_trailing_zeros_us.h" + +#include "src/__support/CPP/bit.h" +#include "src/__support/common.h" + +namespace LIBC_NAMESPACE { + +LLVM_LIBC_FUNCTION(unsigned, stdc_trailing_zeros_us, (unsigned short value)) { + return static_cast(cpp::countr_zero(value)); +} + +} // namespace LIBC_NAMESPACE diff --git a/libc/src/stdbit/stdc_trailing_zeros_us.h b/libc/src/stdbit/stdc_trailing_zeros_us.h new file mode 100644 index 000000000000..ddbdf0d647ab --- /dev/null +++ b/libc/src/stdbit/stdc_trailing_zeros_us.h @@ -0,0 +1,18 @@ +//===-- Implementation header for stdc_trailing_zeros_us --------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ZEROS_US_H +#define LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ZEROS_US_H + +namespace LIBC_NAMESPACE { + +unsigned stdc_trailing_zeros_us(unsigned short value); + +} // namespace LIBC_NAMESPACE + +#endif // LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ZEROS_US_H diff --git a/libc/test/include/stdbit_test.cpp b/libc/test/include/stdbit_test.cpp index 6e48b0f2f759..858dc08bfd70 100644 --- a/libc/test/include/stdbit_test.cpp +++ b/libc/test/include/stdbit_test.cpp @@ -33,6 +33,11 @@ unsigned stdc_leading_ones_us(unsigned short) noexcept { return 0xBBU; } unsigned stdc_leading_ones_ui(unsigned) noexcept { return 0xBCU; } unsigned stdc_leading_ones_ul(unsigned long) noexcept { return 0xBDU; } unsigned stdc_leading_ones_ull(unsigned long long) noexcept { return 0xBFU; } +unsigned stdc_trailing_zeros_uc(unsigned char) noexcept { return 0xCAU; } +unsigned stdc_trailing_zeros_us(unsigned short) noexcept { return 0xCBU; } +unsigned stdc_trailing_zeros_ui(unsigned) noexcept { return 0xCCU; } +unsigned stdc_trailing_zeros_ul(unsigned long) noexcept { return 0xCDU; } +unsigned stdc_trailing_zeros_ull(unsigned long long) noexcept { return 0xCFU; } } #include "include/llvm-libc-macros/stdbit-macros.h" @@ -52,3 +57,11 @@ TEST(LlvmLibcStdbitTest, TypeGenericMacroLeadingOnes) { EXPECT_EQ(stdc_leading_ones(0UL), 0xBDU); EXPECT_EQ(stdc_leading_ones(0ULL), 0xBFU); } + +TEST(LlvmLibcStdbitTest, TypeGenericMacroTrailingZeros) { + EXPECT_EQ(stdc_trailing_zeros(static_cast(0U)), 0xCAU); + EXPECT_EQ(stdc_trailing_zeros(static_cast(0U)), 0xCBU); + EXPECT_EQ(stdc_trailing_zeros(0U), 0xCCU); + EXPECT_EQ(stdc_trailing_zeros(0UL), 0xCDU); + EXPECT_EQ(stdc_trailing_zeros(0ULL), 0xCFU); +} diff --git a/libc/test/src/stdbit/CMakeLists.txt b/libc/test/src/stdbit/CMakeLists.txt index a8c3c9f88353..64d66037d0f6 100644 --- a/libc/test/src/stdbit/CMakeLists.txt +++ b/libc/test/src/stdbit/CMakeLists.txt @@ -1,112 +1,22 @@ add_custom_target(libc-stdbit-tests) -add_libc_test( - stdc_leading_zeros_uc_test - SUITE - libc-stdbit-tests - SRCS - stdc_leading_zeros_uc_test.cpp - DEPENDS - libc.src.__support.CPP.limits - libc.src.stdbit.stdc_leading_zeros_uc -) - -add_libc_test( - stdc_leading_zeros_us_test - SUITE - libc-stdbit-tests - SRCS - stdc_leading_zeros_us_test.cpp - DEPENDS - libc.src.__support.CPP.limits - libc.src.stdbit.stdc_leading_zeros_us -) - -add_libc_test( - stdc_leading_zeros_ui_test - SUITE - libc-stdbit-tests - SRCS - stdc_leading_zeros_ui_test.cpp - DEPENDS - libc.src.__support.CPP.limits - libc.src.stdbit.stdc_leading_zeros_ui -) - -add_libc_test( - stdc_leading_zeros_ul_test - SUITE - libc-stdbit-tests - SRCS - stdc_leading_zeros_ul_test.cpp - DEPENDS - libc.src.__support.CPP.limits - libc.src.stdbit.stdc_leading_zeros_ul -) - -add_libc_test( - stdc_leading_zeros_ull_test - SUITE - libc-stdbit-tests - SRCS - stdc_leading_zeros_ull_test.cpp - DEPENDS - libc.src.__support.CPP.limits - libc.src.stdbit.stdc_leading_zeros_ull -) - -add_libc_test( - stdc_leading_ones_uc_test - SUITE - libc-stdbit-tests - SRCS - stdc_leading_ones_uc_test.cpp - DEPENDS - libc.src.__support.CPP.limits - libc.src.stdbit.stdc_leading_ones_uc -) - -add_libc_test( - stdc_leading_ones_us_test - SUITE - libc-stdbit-tests - SRCS - stdc_leading_ones_us_test.cpp - DEPENDS - libc.src.__support.CPP.limits - libc.src.stdbit.stdc_leading_ones_us -) - -add_libc_test( - stdc_leading_ones_ui_test - SUITE - libc-stdbit-tests - SRCS - stdc_leading_ones_ui_test.cpp - DEPENDS - libc.src.__support.CPP.limits - libc.src.stdbit.stdc_leading_ones_ui -) - -add_libc_test( - stdc_leading_ones_ul_test - SUITE - libc-stdbit-tests - SRCS - stdc_leading_ones_ul_test.cpp - DEPENDS - libc.src.__support.CPP.limits - libc.src.stdbit.stdc_leading_ones_ul -) - -add_libc_test( - stdc_leading_ones_ull_test - SUITE - libc-stdbit-tests - SRCS - stdc_leading_ones_ull_test.cpp - DEPENDS - libc.src.__support.CPP.limits - libc.src.stdbit.stdc_leading_ones_ull -) - +set(prefixes + leading_zeros + leading_ones + trailing_zeros +) +set(suffixes c s i l ll) +foreach(prefix IN LISTS prefixes) + foreach(suffix IN LISTS suffixes) + add_libc_test( + stdc_${prefix}_u${suffix}_test + SUITE + libc-stdbit-tests + SRCS + stdc_${prefix}_u${suffix}_test.cpp + DEPENDS + libc.src.__support.CPP.limits + libc.src.stdbit.stdc_${prefix}_u${suffix} + ) + endforeach() +endforeach() diff --git a/libc/test/src/stdbit/stdc_trailing_zeros_uc_test.cpp b/libc/test/src/stdbit/stdc_trailing_zeros_uc_test.cpp new file mode 100644 index 000000000000..c02b518865d9 --- /dev/null +++ b/libc/test/src/stdbit/stdc_trailing_zeros_uc_test.cpp @@ -0,0 +1,21 @@ +//===-- Unittests for stdc_trailing_zeros_uc ------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/__support/CPP/limits.h" +#include "src/stdbit/stdc_trailing_zeros_uc.h" +#include "test/UnitTest/Test.h" + +TEST(LlvmLibcStdcTrailingZerosUcTest, Zero) { + EXPECT_EQ(LIBC_NAMESPACE::stdc_trailing_zeros_uc(0U), + static_cast(UCHAR_WIDTH)); +} + +TEST(LlvmLibcStdcTrailingZerosUcTest, OneHot) { + for (unsigned i = 0U; i != UCHAR_WIDTH; ++i) + EXPECT_EQ(LIBC_NAMESPACE::stdc_trailing_zeros_uc(1U << i), i); +} diff --git a/libc/test/src/stdbit/stdc_trailing_zeros_ui_test.cpp b/libc/test/src/stdbit/stdc_trailing_zeros_ui_test.cpp new file mode 100644 index 000000000000..ad9b12633517 --- /dev/null +++ b/libc/test/src/stdbit/stdc_trailing_zeros_ui_test.cpp @@ -0,0 +1,21 @@ +//===-- Unittests for stdc_trailing_zeros_ui ------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/__support/CPP/limits.h" +#include "src/stdbit/stdc_trailing_zeros_ui.h" +#include "test/UnitTest/Test.h" + +TEST(LlvmLibcStdcTrailingZerosUiTest, Zero) { + EXPECT_EQ(LIBC_NAMESPACE::stdc_trailing_zeros_ui(0U), + static_cast(UINT_WIDTH)); +} + +TEST(LlvmLibcStdcTrailingZerosUiTest, OneHot) { + for (unsigned i = 0U; i != UINT_WIDTH; ++i) + EXPECT_EQ(LIBC_NAMESPACE::stdc_trailing_zeros_ui(1U << i), i); +} diff --git a/libc/test/src/stdbit/stdc_trailing_zeros_ul_test.cpp b/libc/test/src/stdbit/stdc_trailing_zeros_ul_test.cpp new file mode 100644 index 000000000000..6d7f4b3cb093 --- /dev/null +++ b/libc/test/src/stdbit/stdc_trailing_zeros_ul_test.cpp @@ -0,0 +1,21 @@ +//===-- Unittests for stdc_trailing_zeros_ul ------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/__support/CPP/limits.h" +#include "src/stdbit/stdc_trailing_zeros_ul.h" +#include "test/UnitTest/Test.h" + +TEST(LlvmLibcStdcTrailingZerosUlTest, Zero) { + EXPECT_EQ(LIBC_NAMESPACE::stdc_trailing_zeros_ul(0U), + static_cast(ULONG_WIDTH)); +} + +TEST(LlvmLibcStdcTrailingZerosUlTest, OneHot) { + for (unsigned i = 0U; i != ULONG_WIDTH; ++i) + EXPECT_EQ(LIBC_NAMESPACE::stdc_trailing_zeros_ul(1UL << i), i); +} diff --git a/libc/test/src/stdbit/stdc_trailing_zeros_ull_test.cpp b/libc/test/src/stdbit/stdc_trailing_zeros_ull_test.cpp new file mode 100644 index 000000000000..64b93b12e605 --- /dev/null +++ b/libc/test/src/stdbit/stdc_trailing_zeros_ull_test.cpp @@ -0,0 +1,21 @@ +//===-- Unittests for stdc_trailing_zeros_ull -----------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/__support/CPP/limits.h" +#include "src/stdbit/stdc_trailing_zeros_ull.h" +#include "test/UnitTest/Test.h" + +TEST(LlvmLibcStdcTrailingZerosUllTest, Zero) { + EXPECT_EQ(LIBC_NAMESPACE::stdc_trailing_zeros_ull(0U), + static_cast(ULLONG_WIDTH)); +} + +TEST(LlvmLibcStdcTrailingZerosUllTest, OneHot) { + for (unsigned i = 0U; i != ULLONG_WIDTH; ++i) + EXPECT_EQ(LIBC_NAMESPACE::stdc_trailing_zeros_ull(1ULL << i), i); +} diff --git a/libc/test/src/stdbit/stdc_trailing_zeros_us_test.cpp b/libc/test/src/stdbit/stdc_trailing_zeros_us_test.cpp new file mode 100644 index 000000000000..a9f8327dfd91 --- /dev/null +++ b/libc/test/src/stdbit/stdc_trailing_zeros_us_test.cpp @@ -0,0 +1,21 @@ +//===-- Unittests for stdc_trailing_zeros_us ------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/__support/CPP/limits.h" +#include "src/stdbit/stdc_trailing_zeros_us.h" +#include "test/UnitTest/Test.h" + +TEST(LlvmLibcStdcTrailingZerosUsTest, Zero) { + EXPECT_EQ(LIBC_NAMESPACE::stdc_trailing_zeros_us(0U), + static_cast(USHRT_WIDTH)); +} + +TEST(LlvmLibcStdcTrailingZerosUsTest, OneHot) { + for (unsigned i = 0U; i != USHRT_WIDTH; ++i) + EXPECT_EQ(LIBC_NAMESPACE::stdc_trailing_zeros_us(1U << i), i); +} -- GitLab From ca1da36aec963c5504ae7ae2e834b37856c476db Mon Sep 17 00:00:00 2001 From: Schrodinger ZHU Yifan Date: Tue, 6 Feb 2024 09:35:56 -0500 Subject: [PATCH 077/266] [libc] add inttypes macros (#80726) Standard file: https://pubs.opengroup.org/onlinepubs/9699919799.2018edition/ Notice that we are not quite the same as other implementations: 1. MUSL: https://github.com/bminor/musl/blob/master/include/inttypes.h 2. GLIBC: https://github.com/bminor/glibc/blob/bbd248ac0d75efdef8fe61ea69b1fb25fb95b6e7/stdlib/inttypes.h#L57 3. CheriBSD: https://github.com/CTSRD-CHERI/cheribsd/blob/698d1636dd1fe2322e5bc7029e415928c80b76b1/sys/arm64/include/_inttypes.h fixes #80186 --- libc/include/CMakeLists.txt | 1 + libc/include/inttypes.h.def | 1 + libc/include/llvm-libc-macros/CMakeLists.txt | 6 + .../llvm-libc-macros/inttypes-macros.h | 289 ++++++++++++++++++ libc/test/src/stdio/CMakeLists.txt | 1 + libc/test/src/stdio/sprintf_test.cpp | 20 ++ 6 files changed, 318 insertions(+) create mode 100644 libc/include/llvm-libc-macros/inttypes-macros.h diff --git a/libc/include/CMakeLists.txt b/libc/include/CMakeLists.txt index 4f4d8434757d..332410453b54 100644 --- a/libc/include/CMakeLists.txt +++ b/libc/include/CMakeLists.txt @@ -73,6 +73,7 @@ add_gen_header( DEPENDS .llvm_libc_common_h .llvm-libc-types.imaxdiv_t + .llvm-libc-macros.inttypes_macros ) add_gen_header( diff --git a/libc/include/inttypes.h.def b/libc/include/inttypes.h.def index 94cdc2f21eaf..a99d4e931f51 100644 --- a/libc/include/inttypes.h.def +++ b/libc/include/inttypes.h.def @@ -10,6 +10,7 @@ #define LLVM_LIBC_INTTYPES_H #include <__llvm-libc-common.h> +#include #include %%public_api() diff --git a/libc/include/llvm-libc-macros/CMakeLists.txt b/libc/include/llvm-libc-macros/CMakeLists.txt index c5a7e742cadd..562769a5e84c 100644 --- a/libc/include/llvm-libc-macros/CMakeLists.txt +++ b/libc/include/llvm-libc-macros/CMakeLists.txt @@ -221,3 +221,9 @@ add_macro_header( HDR wchar-macros.h ) + +add_macro_header( + inttypes_macros + HDR + inttypes-macros.h +) diff --git a/libc/include/llvm-libc-macros/inttypes-macros.h b/libc/include/llvm-libc-macros/inttypes-macros.h new file mode 100644 index 000000000000..fc3e2517f194 --- /dev/null +++ b/libc/include/llvm-libc-macros/inttypes-macros.h @@ -0,0 +1,289 @@ +//===-- Definition of macros from inttypes.h ------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +#ifndef __LLVM_LIBC_MACROS_INTTYPES_MACROS_H +#define __LLVM_LIBC_MACROS_INTTYPES_MACROS_H + +// fprintf/scanf format macros. +// POSIX.1-2008, Technical Corrigendum 1, XBD/TC1-2008/0050 [211] is applied. + +// clang provides these macros, so we don't need to define them. +// TODO: ISO C23 will provide binary notations. + +#ifndef __clang__ +#if __UINTPTR_MAX__ == __UINT64_MAX__ +#define __PRI64 "l" +#define __PRIPTR "l" +#elif __UINTPTR_MAX__ == __UINT32_MAX__ +#define __PRI64 "ll" +#define __PRIPTR "" +#else +// CHERI achitecture for example, has 128-bit pointers that use special "P" +// format. +#error "Unsupported pointer format" +#endif +#define __INT8_FMTd__ "hhd" +#define __INT16_FMTd__ "hd" +#define __INT32_FMTd__ "d" +#define __INT64_FMTd__ __PRI64 "d" +#define __INT_LEAST8_FMTd__ "hhd" +#define __INT_LEAST16_FMTd__ "hd" +#define __INT_LEAST32_FMTd__ "d" +#define __INT_LEAST64_FMTd__ __PRI64 "d" +#define __INT_FAST8_FMTd__ "hhd" +#define __INT_FAST16_FMTd__ "hd" +#define __INT_FAST32_FMTd__ "d" +#define __INT_FAST64_FMTd__ __PRI64 "d" +#define __INTMAX_FMTd__ __PRI64 "d" +#define __INTPTR_FMTd__ __PRIPTR "d" + +#define __INT8_FMTi__ "hhi" +#define __INT16_FMTi__ "hi" +#define __INT32_FMTi__ "i" +#define __INT64_FMTi__ __PRI64 "i" +#define __INT_LEAST8_FMTi__ "hhi" +#define __INT_LEAST16_FMTi__ "hi" +#define __INT_LEAST32_FMTi__ "i" +#define __INT_LEAST64_FMTi__ __PRI64 "i" +#define __INT_FAST8_FMTi__ "hhi" +#define __INT_FAST16_FMTi__ "hi" +#define __INT_FAST32_FMTi__ "i" +#define __INT_FAST64_FMTi__ __PRI64 "i" +#define __INTMAX_FMTi__ __PRI64 "i" +#define __INTPTR_FMTi__ __PRIPTR "i" + +#define __UINT8_FMTo__ "hho" +#define __UINT16_FMTo__ "ho" +#define __UINT32_FMTo__ "o" +#define __UINT64_FMTo__ __PRI64 "o" +#define __UINT_LEAST8_FMTo__ "hho" +#define __UINT_LEAST16_FMTo__ "ho" +#define __UINT_LEAST32_FMTo__ "o" +#define __UINT_LEAST64_FMTo__ __PRI64 "o" +#define __UINT_FAST8_FMTo__ "hho" +#define __UINT_FAST16_FMTo__ "ho" +#define __UINT_FAST32_FMTo__ "o" +#define __UINT_FAST64_FMTo__ __PRI64 "o" +#define __UINTMAX_FMTo__ __PRI64 "o" +#define __UINTPTR_FMTo__ __PRIPTR "o" + +#define __UINT8_FMTu__ "hhu" +#define __UINT16_FMTu__ "hu" +#define __UINT32_FMTu__ "u" +#define __UINT64_FMTu__ __PRI64 "u" +#define __UINT_LEAST8_FMTu__ "hhu" +#define __UINT_LEAST16_FMTu__ "hu" +#define __UINT_LEAST32_FMTu__ "u" +#define __UINT_LEAST64_FMTu__ __PRI64 "u" +#define __UINT_FAST8_FMTu__ "hhu" +#define __UINT_FAST16_FMTu__ "hu" +#define __UINT_FAST32_FMTu__ "u" +#define __UINT_FAST64_FMTu__ __PRI64 "u" +#define __UINTMAX_FMTu__ __PRI64 "u" +#define __UINTPTR_FMTu__ __PRIPTR "u" + +#define __UINT8_FMTx__ "hhx" +#define __UINT16_FMTx__ "hx" +#define __UINT32_FMTx__ "x" +#define __UINT64_FMTx__ __PRI64 "x" +#define __UINT_LEAST8_FMTx__ "hhx" +#define __UINT_LEAST16_FMTx__ "hx" +#define __UINT_LEAST32_FMTx__ "x" +#define __UINT_LEAST64_FMTx__ __PRI64 "x" +#define __UINT_FAST8_FMTx__ "hhx" +#define __UINT_FAST16_FMTx__ "hx" +#define __UINT_FAST32_FMTx__ "x" +#define __UINT_FAST64_FMTx__ __PRI64 "x" +#define __UINTMAX_FMTx__ __PRI64 "x" +#define __UINTPTR_FMTx__ __PRIPTR "x" + +#define __UINT8_FMTX__ "hhX" +#define __UINT16_FMTX__ "hX" +#define __UINT32_FMTX__ "X" +#define __UINT64_FMTX__ __PRI64 "X" +#define __UINT_LEAST8_FMTX__ "hhX" +#define __UINT_LEAST16_FMTX__ "hX" +#define __UINT_LEAST32_FMTX__ "X" +#define __UINT_LEAST64_FMTX__ __PRI64 "X" +#define __UINT_FAST8_FMTX__ "hhX" +#define __UINT_FAST16_FMTX__ "hX" +#define __UINT_FAST32_FMTX__ "X" +#define __UINT_FAST64_FMTX__ __PRI64 "X" +#define __UINTMAX_FMTX__ __PRI64 "X" +#define __UINTPTR_FMTX__ __PRIPTR "X" +#endif + +// The fprintf() macros for signed integers. +#define PRId8 __INT8_FMTd__ +#define PRId16 __INT16_FMTd__ +#define PRId32 __INT32_FMTd__ +#define PRId64 __INT64_FMTd__ +#define PRIdLEAST8 __INT_LEAST8_FMTd__ +#define PRIdLEAST16 __INT_LEAST16_FMTd__ +#define PRIdLEAST32 __INT_LEAST32_FMTd__ +#define PRIdLEAST64 __INT_LEAST64_FMTd__ +#define PRIdFAST8 __INT_FAST8_FMTd__ +#define PRIdFAST16 __INT_FAST16_FMTd__ +#define PRIdFAST32 __INT_FAST32_FMTd__ +#define PRIdFAST64 __INT_FAST64_FMTd__ +#define PRIdMAX __INTMAX_FMTd__ +#define PRIdPTR __INTPTR_FMTd__ + +#define PRIi8 __INT8_FMTi__ +#define PRIi16 __INT16_FMTi__ +#define PRIi32 __INT32_FMTi__ +#define PRIi64 __INT64_FMTi__ +#define PRIiLEAST8 __INT_LEAST8_FMTi__ +#define PRIiLEAST16 __INT_LEAST16_FMTi__ +#define PRIiLEAST32 __INT_LEAST32_FMTi__ +#define PRIiLEAST64 __INT_LEAST64_FMTi__ +#define PRIiFAST8 __INT_FAST8_FMTi__ +#define PRIiFAST16 __INT_FAST16_FMTi__ +#define PRIiFAST32 __INT_FAST32_FMTi__ +#define PRIiFAST64 __INT_FAST64_FMTi__ +#define PRIiMAX __INTMAX_FMTi__ +#define PRIiPTR __INTPTR_FMTi__ + +// The fprintf() macros for unsigned integers. +#define PRIo8 __UINT8_FMTo__ +#define PRIo16 __UINT16_FMTo__ +#define PRIo32 __UINT32_FMTo__ +#define PRIo64 __UINT64_FMTo__ +#define PRIoLEAST8 __UINT_LEAST8_FMTo__ +#define PRIoLEAST16 __UINT_LEAST16_FMTo__ +#define PRIoLEAST32 __UINT_LEAST32_FMTo__ +#define PRIoLEAST64 __UINT_LEAST64_FMTo__ +#define PRIoFAST8 __UINT_FAST8_FMTo__ +#define PRIoFAST16 __UINT_FAST16_FMTo__ +#define PRIoFAST32 __UINT_FAST32_FMTo__ +#define PRIoFAST64 __UINT_FAST64_FMTo__ +#define PRIoMAX __UINTMAX_FMTo__ +#define PRIoPTR __UINTPTR_FMTo__ + +#define PRIu8 __UINT8_FMTu__ +#define PRIu16 __UINT16_FMTu__ +#define PRIu32 __UINT32_FMTu__ +#define PRIu64 __UINT64_FMTu__ +#define PRIuLEAST8 __UINT_LEAST8_FMTu__ +#define PRIuLEAST16 __UINT_LEAST16_FMTu__ +#define PRIuLEAST32 __UINT_LEAST32_FMTu__ +#define PRIuLEAST64 __UINT_LEAST64_FMTu__ +#define PRIuFAST8 __UINT_FAST8_FMTu__ +#define PRIuFAST16 __UINT_FAST16_FMTu__ +#define PRIuFAST32 __UINT_FAST32_FMTu__ +#define PRIuFAST64 __UINT_FAST64_FMTu__ +#define PRIuMAX __UINTMAX_FMTu__ +#define PRIuPTR __UINTPTR_FMTu__ + +#define PRIx8 __UINT8_FMTx__ +#define PRIx16 __UINT16_FMTx__ +#define PRIx32 __UINT32_FMTx__ +#define PRIx64 __UINT64_FMTx__ +#define PRIxLEAST8 __UINT_LEAST8_FMTx__ +#define PRIxLEAST16 __UINT_LEAST16_FMTx__ +#define PRIxLEAST32 __UINT_LEAST32_FMTx__ +#define PRIxLEAST64 __UINT_LEAST64_FMTx__ +#define PRIxFAST8 __UINT_FAST8_FMTx__ +#define PRIxFAST16 __UINT_FAST16_FMTx__ +#define PRIxFAST32 __UINT_FAST32_FMTx__ +#define PRIxFAST64 __UINT_FAST64_FMTx__ +#define PRIxMAX __UINTMAX_FMTx__ +#define PRIxPTR __UINTPTR_FMTx__ + +#define PRIX8 __UINT8_FMTX__ +#define PRIX16 __UINT16_FMTX__ +#define PRIX32 __UINT32_FMTX__ +#define PRIX64 __UINT64_FMTX__ +#define PRIXLEAST8 __UINT_LEAST8_FMTX__ +#define PRIXLEAST16 __UINT_LEAST16_FMTX__ +#define PRIXLEAST32 __UINT_LEAST32_FMTX__ +#define PRIXLEAST64 __UINT_LEAST64_FMTX__ +#define PRIXFAST8 __UINT_FAST8_FMTX__ +#define PRIXFAST16 __UINT_FAST16_FMTX__ +#define PRIXFAST32 __UINT_FAST32_FMTX__ +#define PRIXFAST64 __UINT_FAST64_FMTX__ +#define PRIXMAX __UINTMAX_FMTX__ +#define PRIXPTR __UINTPTR_FMTX__ + +// The fscanf() macros for signed integers. +#define SCNd8 __INT8_FMTd__ +#define SCNd16 __INT16_FMTd__ +#define SCNd32 __INT32_FMTd__ +#define SCNd64 __INT64_FMTd__ +#define SCNdLEAST8 __INT_LEAST8_FMTd__ +#define SCNdLEAST16 __INT_LEAST16_FMTd__ +#define SCNdLEAST32 __INT_LEAST32_FMTd__ +#define SCNdLEAST64 __INT_LEAST64_FMTd__ +#define SCNdFAST8 __INT_FAST8_FMTd__ +#define SCNdFAST16 __INT_FAST16_FMTd__ +#define SCNdFAST32 __INT_FAST32_FMTd__ +#define SCNdFAST64 __INT_FAST64_FMTd__ +#define SCNdMAX __INTMAX_FMTd__ +#define SCNdPTR __INTPTR_FMTd__ + +#define SCNi8 __INT8_FMTi__ +#define SCNi16 __INT16_FMTi__ +#define SCNi32 __INT32_FMTi__ +#define SCNi64 __INT64_FMTi__ +#define SCNiLEAST8 __INT_LEAST8_FMTi__ +#define SCNiLEAST16 __INT_LEAST16_FMTi__ +#define SCNiLEAST32 __INT_LEAST32_FMTi__ +#define SCNiLEAST64 __INT_LEAST64_FMTi__ +#define SCNiFAST8 __INT_FAST8_FMTi__ +#define SCNiFAST16 __INT_FAST16_FMTi__ +#define SCNiFAST32 __INT_FAST32_FMTi__ +#define SCNiFAST64 __INT_FAST64_FMTi__ +#define SCNiMAX __INTMAX_FMTi__ +#define SCNiPTR __INTPTR_FMTi__ + +// The fscanf() macros for unsigned integers. +#define SCNo8 __UINT8_FMTo__ +#define SCNo16 __UINT16_FMTo__ +#define SCNo32 __UINT32_FMTo__ +#define SCNo64 __UINT64_FMTo__ +#define SCNoLEAST8 __UINT_LEAST8_FMTo__ +#define SCNoLEAST16 __UINT_LEAST16_FMTo__ +#define SCNoLEAST32 __UINT_LEAST32_FMTo__ +#define SCNoLEAST64 __UINT_LEAST64_FMTo__ +#define SCNoFAST8 __UINT_FAST8_FMTo__ +#define SCNoFAST16 __UINT_FAST16_FMTo__ +#define SCNoFAST32 __UINT_FAST32_FMTo__ +#define SCNoFAST64 __UINT_FAST64_FMTo__ +#define SCNoMAX __UINTMAX_FMTo__ +#define SCNoPTR __UINTPTR_FMTo__ + +#define SCNu8 __UINT8_FMTu__ +#define SCNu16 __UINT16_FMTu__ +#define SCNu32 __UINT32_FMTu__ +#define SCNu64 __UINT64_FMTu__ +#define SCNuLEAST8 __UINT_LEAST8_FMTu__ +#define SCNuLEAST16 __UINT_LEAST16_FMTu__ +#define SCNuLEAST32 __UINT_LEAST32_FMTu__ +#define SCNuLEAST64 __UINT_LEAST64_FMTu__ +#define SCNuFAST8 __UINT_FAST8_FMTu__ +#define SCNuFAST16 __UINT_FAST16_FMTu__ +#define SCNuFAST32 __UINT_FAST32_FMTu__ +#define SCNuFAST64 __UINT_FAST64_FMTu__ +#define SCNuMAX __UINTMAX_FMTu__ +#define SCNuPTR __UINTPTR_FMTu__ + +#define SCNx8 __UINT8_FMTx__ +#define SCNx16 __UINT16_FMTx__ +#define SCNx32 __UINT32_FMTx__ +#define SCNx64 __UINT64_FMTx__ +#define SCNxLEAST8 __UINT_LEAST8_FMTx__ +#define SCNxLEAST16 __UINT_LEAST16_FMTx__ +#define SCNxLEAST32 __UINT_LEAST32_FMTx__ +#define SCNxLEAST64 __UINT_LEAST64_FMTx__ +#define SCNxFAST8 __UINT_FAST8_FMTx__ +#define SCNxFAST16 __UINT_FAST16_FMTx__ +#define SCNxFAST32 __UINT_FAST32_FMTx__ +#define SCNxFAST64 __UINT_FAST64_FMTx__ +#define SCNxMAX __UINTMAX_FMTx__ +#define SCNxPTR __UINTPTR_FMTx__ + +#endif // __LLVM_LIBC_MACROS_INTTYPES_MACROS_H diff --git a/libc/test/src/stdio/CMakeLists.txt b/libc/test/src/stdio/CMakeLists.txt index ffc238443863..8db2293ab74a 100644 --- a/libc/test/src/stdio/CMakeLists.txt +++ b/libc/test/src/stdio/CMakeLists.txt @@ -132,6 +132,7 @@ add_fp_unittest( DEPENDS libc.src.stdio.sprintf libc.src.__support.FPUtil.fp_bits + libc.include.inttypes COMPILE_OPTIONS ${sprintf_test_copts} ) diff --git a/libc/test/src/stdio/sprintf_test.cpp b/libc/test/src/stdio/sprintf_test.cpp index 1468bffe2a03..f3614b05a0c3 100644 --- a/libc/test/src/stdio/sprintf_test.cpp +++ b/libc/test/src/stdio/sprintf_test.cpp @@ -11,6 +11,7 @@ #include "src/__support/FPUtil/FPBits.h" #include "test/UnitTest/RoundingModeUtils.h" #include "test/UnitTest/Test.h" +#include // TODO: Add a comment here explaining the printf format string. @@ -33,6 +34,25 @@ using LIBC_NAMESPACE::fputil::testing::RoundingMode; EXPECT_EQ(actual_written, static_cast(sizeof(expected_str) - 1)); \ EXPECT_STREQ(actual_str, expected_str); +#define macro_test(FMT, X, expected) \ + do { \ + for (char &c : buff) { \ + c = 0; \ + } \ + LIBC_NAMESPACE::sprintf(buff, "%" FMT, X); \ + ASSERT_STREQ(buff, expected); \ + } while (0) + +TEST(LlvmLibcSPrintfTest, Macros) { + char buff[128]; + macro_test(PRIu8, 1, "1"); + macro_test(PRIX16, 0xAA, "AA"); + macro_test(PRId32, -123, "-123"); + macro_test(PRIX32, 0xFFFFFF85, "FFFFFF85"); + macro_test(PRIo8, 0xFF, "377"); + macro_test(PRIo64, 0123, "123"); +} + TEST(LlvmLibcSPrintfTest, SimpleNoConv) { char buff[64]; int written; -- GitLab From 364f781344e11d6a781ebdd0a4d9689bc9c51cfb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?= Date: Tue, 6 Feb 2024 15:58:02 +0100 Subject: [PATCH 078/266] [GlobalIsel] Combine logic of icmps (#77855) Inspired by InstCombinerImpl::foldAndOrOfICmpsUsingRanges with some adaptations to MIR. --- .../llvm/CodeGen/GlobalISel/CombinerHelper.h | 12 + .../CodeGen/GlobalISel/GenericMachineInstrs.h | 128 +++++++++ .../include/llvm/Target/GlobalISel/Combine.td | 14 +- .../lib/CodeGen/GlobalISel/CombinerHelper.cpp | 180 ++++++++++++ .../GlobalISel/combine-logic-of-compare.mir | 262 ++++++++++++++++++ llvm/test/CodeGen/AArch64/arm64-ccmp.ll | 46 +-- .../CodeGen/AMDGPU/llvm.is.fpclass.f16.ll | 104 +++---- 7 files changed, 647 insertions(+), 99 deletions(-) create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/combine-logic-of-compare.mir diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h index 90428a622b41..10eeafdd09a8 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h @@ -814,6 +814,12 @@ public: /// Combine selects. bool matchSelect(MachineInstr &MI, BuildFnTy &MatchInfo); + /// Combine ands, + bool matchAnd(MachineInstr &MI, BuildFnTy &MatchInfo); + + /// Combine ors, + bool matchOr(MachineInstr &MI, BuildFnTy &MatchInfo); + private: /// Checks for legality of an indexed variant of \p LdSt. bool isIndexedLoadStoreLegal(GLoadStore &LdSt) const; @@ -919,6 +925,12 @@ private: bool AllowUndefs); std::optional getConstantOrConstantSplatVector(Register Src); + + /// Fold (icmp Pred1 V1, C1) && (icmp Pred2 V2, C2) + /// or (icmp Pred1 V1, C1) || (icmp Pred2 V2, C2) + /// into a single comparison using range-based reasoning. + bool tryFoldAndOrOrICmpsUsingRanges(GLogicalBinOp *Logic, + BuildFnTy &MatchInfo); }; } // namespace llvm diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h index eabbe688a1c7..f5a6528d10a9 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h @@ -592,6 +592,134 @@ public: } }; +/// Represents a binary operation, i.e, x = y op z. +class GBinOp : public GenericMachineInstr { +public: + Register getLHSReg() const { return getReg(1); } + Register getRHSReg() const { return getReg(2); } + + static bool classof(const MachineInstr *MI) { + switch (MI->getOpcode()) { + // Integer. + case TargetOpcode::G_ADD: + case TargetOpcode::G_SUB: + case TargetOpcode::G_MUL: + case TargetOpcode::G_SDIV: + case TargetOpcode::G_UDIV: + case TargetOpcode::G_SREM: + case TargetOpcode::G_UREM: + case TargetOpcode::G_SMIN: + case TargetOpcode::G_SMAX: + case TargetOpcode::G_UMIN: + case TargetOpcode::G_UMAX: + // Floating point. + case TargetOpcode::G_FMINNUM: + case TargetOpcode::G_FMAXNUM: + case TargetOpcode::G_FMINNUM_IEEE: + case TargetOpcode::G_FMAXNUM_IEEE: + case TargetOpcode::G_FMINIMUM: + case TargetOpcode::G_FMAXIMUM: + case TargetOpcode::G_FADD: + case TargetOpcode::G_FSUB: + case TargetOpcode::G_FMUL: + case TargetOpcode::G_FDIV: + case TargetOpcode::G_FPOW: + // Logical. + case TargetOpcode::G_AND: + case TargetOpcode::G_OR: + case TargetOpcode::G_XOR: + return true; + default: + return false; + } + }; +}; + +/// Represents an integer binary operation. +class GIntBinOp : public GBinOp { +public: + static bool classof(const MachineInstr *MI) { + switch (MI->getOpcode()) { + case TargetOpcode::G_ADD: + case TargetOpcode::G_SUB: + case TargetOpcode::G_MUL: + case TargetOpcode::G_SDIV: + case TargetOpcode::G_UDIV: + case TargetOpcode::G_SREM: + case TargetOpcode::G_UREM: + case TargetOpcode::G_SMIN: + case TargetOpcode::G_SMAX: + case TargetOpcode::G_UMIN: + case TargetOpcode::G_UMAX: + return true; + default: + return false; + } + }; +}; + +/// Represents a floating point binary operation. +class GFBinOp : public GBinOp { +public: + static bool classof(const MachineInstr *MI) { + switch (MI->getOpcode()) { + case TargetOpcode::G_FMINNUM: + case TargetOpcode::G_FMAXNUM: + case TargetOpcode::G_FMINNUM_IEEE: + case TargetOpcode::G_FMAXNUM_IEEE: + case TargetOpcode::G_FMINIMUM: + case TargetOpcode::G_FMAXIMUM: + case TargetOpcode::G_FADD: + case TargetOpcode::G_FSUB: + case TargetOpcode::G_FMUL: + case TargetOpcode::G_FDIV: + case TargetOpcode::G_FPOW: + return true; + default: + return false; + } + }; +}; + +/// Represents a logical binary operation. +class GLogicalBinOp : public GBinOp { +public: + static bool classof(const MachineInstr *MI) { + switch (MI->getOpcode()) { + case TargetOpcode::G_AND: + case TargetOpcode::G_OR: + case TargetOpcode::G_XOR: + return true; + default: + return false; + } + }; +}; + +/// Represents an integer addition. +class GAdd : public GIntBinOp { +public: + static bool classof(const MachineInstr *MI) { + return MI->getOpcode() == TargetOpcode::G_ADD; + }; +}; + +/// Represents a logical and. +class GAnd : public GLogicalBinOp { +public: + static bool classof(const MachineInstr *MI) { + return MI->getOpcode() == TargetOpcode::G_AND; + }; +}; + +/// Represents a logical or. +class GOr : public GLogicalBinOp { +public: + static bool classof(const MachineInstr *MI) { + return MI->getOpcode() == TargetOpcode::G_OR; + }; +}; + } // namespace llvm #endif // LLVM_CODEGEN_GLOBALISEL_GENERICMACHINEINSTRS_H diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td index 6bda80681432..9b0e1b0d7c4f 100644 --- a/llvm/include/llvm/Target/GlobalISel/Combine.td +++ b/llvm/include/llvm/Target/GlobalISel/Combine.td @@ -1241,6 +1241,18 @@ def match_selects : GICombineRule< [{ return Helper.matchSelect(*${root}, ${matchinfo}); }]), (apply [{ Helper.applyBuildFn(*${root}, ${matchinfo}); }])>; +def match_ands : GICombineRule< + (defs root:$root, build_fn_matchinfo:$matchinfo), + (match (wip_match_opcode G_AND):$root, + [{ return Helper.matchAnd(*${root}, ${matchinfo}); }]), + (apply [{ Helper.applyBuildFn(*${root}, ${matchinfo}); }])>; + +def match_ors : GICombineRule< + (defs root:$root, build_fn_matchinfo:$matchinfo), + (match (wip_match_opcode G_OR):$root, + [{ return Helper.matchOr(*${root}, ${matchinfo}); }]), + (apply [{ Helper.applyBuildFn(*${root}, ${matchinfo}); }])>; + // FIXME: These should use the custom predicate feature once it lands. def undef_combines : GICombineGroup<[undef_to_fp_zero, undef_to_int_zero, undef_to_negative_one, @@ -1314,7 +1326,7 @@ def all_combines : GICombineGroup<[trivial_combines, insert_vec_elt_combines, intdiv_combines, mulh_combines, redundant_neg_operands, and_or_disjoint_mask, fma_combines, fold_binop_into_select, sub_add_reg, select_to_minmax, redundant_binop_in_equality, - fsub_to_fneg, commute_constant_to_rhs]>; + fsub_to_fneg, commute_constant_to_rhs, match_ands, match_ors]>; // A combine group used to for prelegalizer combiners at -O0. The combines in // this group have been selected based on experiments to balance code size and diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp index 772229215e79..1b199cfd41d2 100644 --- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp @@ -28,10 +28,12 @@ #include "llvm/CodeGen/TargetInstrInfo.h" #include "llvm/CodeGen/TargetLowering.h" #include "llvm/CodeGen/TargetOpcodes.h" +#include "llvm/IR/ConstantRange.h" #include "llvm/IR/DataLayout.h" #include "llvm/IR/InstrTypes.h" #include "llvm/Support/Casting.h" #include "llvm/Support/DivisionByConstantInfo.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" #include "llvm/Target/TargetMachine.h" #include @@ -6651,3 +6653,181 @@ bool CombinerHelper::matchSelect(MachineInstr &MI, BuildFnTy &MatchInfo) { return false; } + +/// Fold (icmp Pred1 V1, C1) && (icmp Pred2 V2, C2) +/// or (icmp Pred1 V1, C1) || (icmp Pred2 V2, C2) +/// into a single comparison using range-based reasoning. +/// see InstCombinerImpl::foldAndOrOfICmpsUsingRanges. +bool CombinerHelper::tryFoldAndOrOrICmpsUsingRanges(GLogicalBinOp *Logic, + BuildFnTy &MatchInfo) { + assert(Logic->getOpcode() != TargetOpcode::G_XOR && "unexpected xor"); + bool IsAnd = Logic->getOpcode() == TargetOpcode::G_AND; + Register DstReg = Logic->getReg(0); + Register LHS = Logic->getLHSReg(); + Register RHS = Logic->getRHSReg(); + unsigned Flags = Logic->getFlags(); + + // We need an G_ICMP on the LHS register. + GICmp *Cmp1 = getOpcodeDef(LHS, MRI); + if (!Cmp1) + return false; + + // We need an G_ICMP on the RHS register. + GICmp *Cmp2 = getOpcodeDef(RHS, MRI); + if (!Cmp2) + return false; + + // We want to fold the icmps. + if (!MRI.hasOneNonDBGUse(Cmp1->getReg(0)) || + !MRI.hasOneNonDBGUse(Cmp2->getReg(0))) + return false; + + APInt C1; + APInt C2; + std::optional MaybeC1 = + getIConstantVRegValWithLookThrough(Cmp1->getRHSReg(), MRI); + if (!MaybeC1) + return false; + C1 = MaybeC1->Value; + + std::optional MaybeC2 = + getIConstantVRegValWithLookThrough(Cmp2->getRHSReg(), MRI); + if (!MaybeC2) + return false; + C2 = MaybeC2->Value; + + Register R1 = Cmp1->getLHSReg(); + Register R2 = Cmp2->getLHSReg(); + CmpInst::Predicate Pred1 = Cmp1->getCond(); + CmpInst::Predicate Pred2 = Cmp2->getCond(); + LLT CmpTy = MRI.getType(Cmp1->getReg(0)); + LLT CmpOperandTy = MRI.getType(R1); + + // We build ands, adds, and constants of type CmpOperandTy. + // They must be legal to build. + if (!isLegalOrBeforeLegalizer({TargetOpcode::G_AND, CmpOperandTy}) || + !isLegalOrBeforeLegalizer({TargetOpcode::G_ADD, CmpOperandTy}) || + !isConstantLegalOrBeforeLegalizer(CmpOperandTy)) + return false; + + // Look through add of a constant offset on R1, R2, or both operands. This + // allows us to interpret the R + C' < C'' range idiom into a proper range. + std::optional Offset1; + std::optional Offset2; + if (R1 != R2) { + if (GAdd *Add = getOpcodeDef(R1, MRI)) { + std::optional MaybeOffset1 = + getIConstantVRegValWithLookThrough(Add->getRHSReg(), MRI); + if (MaybeOffset1) { + R1 = Add->getLHSReg(); + Offset1 = MaybeOffset1->Value; + } + } + if (GAdd *Add = getOpcodeDef(R2, MRI)) { + std::optional MaybeOffset2 = + getIConstantVRegValWithLookThrough(Add->getRHSReg(), MRI); + if (MaybeOffset2) { + R2 = Add->getLHSReg(); + Offset2 = MaybeOffset2->Value; + } + } + } + + if (R1 != R2) + return false; + + // We calculate the icmp ranges including maybe offsets. + ConstantRange CR1 = ConstantRange::makeExactICmpRegion( + IsAnd ? ICmpInst::getInversePredicate(Pred1) : Pred1, C1); + if (Offset1) + CR1 = CR1.subtract(*Offset1); + + ConstantRange CR2 = ConstantRange::makeExactICmpRegion( + IsAnd ? ICmpInst::getInversePredicate(Pred2) : Pred2, C2); + if (Offset2) + CR2 = CR2.subtract(*Offset2); + + bool CreateMask = false; + APInt LowerDiff; + std::optional CR = CR1.exactUnionWith(CR2); + if (!CR) { + // We need non-wrapping ranges. + if (CR1.isWrappedSet() || CR2.isWrappedSet()) + return false; + + // Check whether we have equal-size ranges that only differ by one bit. + // In that case we can apply a mask to map one range onto the other. + LowerDiff = CR1.getLower() ^ CR2.getLower(); + APInt UpperDiff = (CR1.getUpper() - 1) ^ (CR2.getUpper() - 1); + APInt CR1Size = CR1.getUpper() - CR1.getLower(); + if (!LowerDiff.isPowerOf2() || LowerDiff != UpperDiff || + CR1Size != CR2.getUpper() - CR2.getLower()) + return false; + + CR = CR1.getLower().ult(CR2.getLower()) ? CR1 : CR2; + CreateMask = true; + } + + if (IsAnd) + CR = CR->inverse(); + + CmpInst::Predicate NewPred; + APInt NewC, Offset; + CR->getEquivalentICmp(NewPred, NewC, Offset); + + // We take the result type of one of the original icmps, CmpTy, for + // the to be build icmp. The operand type, CmpOperandTy, is used for + // the other instructions and constants to be build. The types of + // the parameters and output are the same for add and and. CmpTy + // and the type of DstReg might differ. That is why we zext or trunc + // the icmp into the destination register. + + MatchInfo = [=](MachineIRBuilder &B) { + if (CreateMask && Offset != 0) { + auto TildeLowerDiff = B.buildConstant(CmpOperandTy, ~LowerDiff); + auto And = B.buildAnd(CmpOperandTy, R1, TildeLowerDiff); // the mask. + auto OffsetC = B.buildConstant(CmpOperandTy, Offset); + auto Add = B.buildAdd(CmpOperandTy, And, OffsetC, Flags); + auto NewCon = B.buildConstant(CmpOperandTy, NewC); + auto ICmp = B.buildICmp(NewPred, CmpTy, Add, NewCon); + B.buildZExtOrTrunc(DstReg, ICmp); + } else if (CreateMask && Offset == 0) { + auto TildeLowerDiff = B.buildConstant(CmpOperandTy, ~LowerDiff); + auto And = B.buildAnd(CmpOperandTy, R1, TildeLowerDiff); // the mask. + auto NewCon = B.buildConstant(CmpOperandTy, NewC); + auto ICmp = B.buildICmp(NewPred, CmpTy, And, NewCon); + B.buildZExtOrTrunc(DstReg, ICmp); + } else if (!CreateMask && Offset != 0) { + auto OffsetC = B.buildConstant(CmpOperandTy, Offset); + auto Add = B.buildAdd(CmpOperandTy, R1, OffsetC, Flags); + auto NewCon = B.buildConstant(CmpOperandTy, NewC); + auto ICmp = B.buildICmp(NewPred, CmpTy, Add, NewCon); + B.buildZExtOrTrunc(DstReg, ICmp); + } else if (!CreateMask && Offset == 0) { + auto NewCon = B.buildConstant(CmpOperandTy, NewC); + auto ICmp = B.buildICmp(NewPred, CmpTy, R1, NewCon); + B.buildZExtOrTrunc(DstReg, ICmp); + } else { + llvm_unreachable("unexpected configuration of CreateMask and Offset"); + } + }; + return true; +} + +bool CombinerHelper::matchAnd(MachineInstr &MI, BuildFnTy &MatchInfo) { + GAnd *And = cast(&MI); + + if (tryFoldAndOrOrICmpsUsingRanges(And, MatchInfo)) + return true; + + return false; +} + +bool CombinerHelper::matchOr(MachineInstr &MI, BuildFnTy &MatchInfo) { + GOr *Or = cast(&MI); + + if (tryFoldAndOrOrICmpsUsingRanges(Or, MatchInfo)) + return true; + + return false; +} diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-logic-of-compare.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-logic-of-compare.mir new file mode 100644 index 000000000000..f667a83bf21a --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-logic-of-compare.mir @@ -0,0 +1,262 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -debugify-and-strip-all-safe -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s +--- +# icmp (x, 1) && icmp (x, 2) -> x +name: test_icmp_and_icmp +body: | + bb.1: + liveins: $x0, $x1 + ; CHECK-LABEL: name: test_icmp_and_icmp + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: %one:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s64), %one + ; CHECK-NEXT: %zext:_(s64) = G_ZEXT [[ICMP]](s1) + ; CHECK-NEXT: $x0 = COPY %zext(s64) + %0:_(s64) = COPY $x0 + %1:_(s64) = COPY $x1 + %2:_(s64) = COPY $x2 + %one:_(s64) = G_CONSTANT i64 1 + %two:_(s64) = G_CONSTANT i64 2 + %cmp1:_(s1) = G_ICMP intpred(eq), %0(s64), %one + %cmp2:_(s1) = G_ICMP intpred(ne), %0(s64), %two + %and:_(s1) = G_AND %cmp1, %cmp2 + %zext:_(s64) = G_ZEXT %and(s1) + $x0 = COPY %zext +... +--- +# multi use icmp (x, 1) && icmp (x, 2) -> x +name: multi_use_test_icmp_and_icmp +body: | + bb.1: + liveins: $x0, $x1 + ; CHECK-LABEL: name: multi_use_test_icmp_and_icmp + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: %one:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: %two:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: %cmp1:_(s1) = G_ICMP intpred(eq), [[COPY]](s64), %one + ; CHECK-NEXT: %cmp2:_(s1) = G_ICMP intpred(ne), [[COPY]](s64), %two + ; CHECK-NEXT: %and:_(s1) = G_AND %cmp1, %cmp2 + ; CHECK-NEXT: %zext:_(s64) = G_ZEXT %and(s1) + ; CHECK-NEXT: %cmp1zext:_(s64) = G_ZEXT %cmp1(s1) + ; CHECK-NEXT: $x0 = COPY %zext(s64) + ; CHECK-NEXT: $x0 = COPY %cmp1zext(s64) + %0:_(s64) = COPY $x0 + %1:_(s64) = COPY $x1 + %2:_(s64) = COPY $x2 + %one:_(s64) = G_CONSTANT i64 1 + %two:_(s64) = G_CONSTANT i64 2 + %cmp1:_(s1) = G_ICMP intpred(eq), %0(s64), %one + %cmp2:_(s1) = G_ICMP intpred(ne), %0(s64), %two + %and:_(s1) = G_AND %cmp1, %cmp2 + %zext:_(s64) = G_ZEXT %and(s1) + %cmp1zext:_(s64) = G_ZEXT %cmp1(s1) + $x0 = COPY %zext + $x0 = COPY %cmp1zext +... +--- +# icmp (x, 1) && icmp (x, add(x, 2)) -> x +name: test_icmp_and_icmp_with_add +body: | + bb.1: + liveins: $x0, $x1 + ; CHECK-LABEL: name: test_icmp_and_icmp_with_add + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: %one:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: %cmp1:_(s1) = G_ICMP intpred(eq), [[COPY]](s64), %one + ; CHECK-NEXT: %zext:_(s64) = G_ZEXT %cmp1(s1) + ; CHECK-NEXT: $x0 = COPY %zext(s64) + %0:_(s64) = COPY $x0 + %1:_(s64) = COPY $x1 + %2:_(s64) = COPY $x2 + %one:_(s64) = G_CONSTANT i64 1 + %two:_(s64) = G_CONSTANT i64 2 + %add:_(s64) = G_ADD %0(s64), %two + %cmp1:_(s1) = G_ICMP intpred(eq), %0(s64), %one + %cmp2:_(s1) = G_ICMP intpred(ne), %0(s64), %add + %and:_(s1) = G_AND %cmp1, %cmp2 + %zext:_(s64) = G_ZEXT %and(s1) + $x0 = COPY %zext +... +--- +# icmp (x, 1) && icmp (x, add(x, 2000)) -> x +name: test_icmp_or_icmp_with_add_2000 +body: | + bb.1: + liveins: $x0, $x1 + ; CHECK-LABEL: name: test_icmp_or_icmp_with_add_2000 + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: %one:_(s64) = G_CONSTANT i64 -100 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s64), %one + ; CHECK-NEXT: %zext:_(s64) = G_ZEXT [[ICMP]](s1) + ; CHECK-NEXT: $x0 = COPY %zext(s64) + %0:_(s64) = COPY $x0 + %1:_(s64) = COPY $x1 + %2:_(s64) = COPY $x2 + %one:_(s64) = G_CONSTANT i64 -100 + %two:_(s64) = G_CONSTANT i64 2000 + %cmp1:_(s1) = G_ICMP intpred(eq), %0(s64), %one + %cmp2:_(s1) = G_ICMP intpred(ne), %0(s64), %two + %or:_(s1) = G_AND %cmp1, %cmp2 + %zext:_(s64) = G_ZEXT %or(s1) + $x0 = COPY %zext +... +--- +# icmp (x, -100) || icmp (x, 2000) -> x +name: test_icmp_or_icmp +body: | + bb.1: + liveins: $x0, $x1 + ; CHECK-LABEL: name: test_icmp_or_icmp + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: %two:_(s64) = G_CONSTANT i64 2000 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s64), %two + ; CHECK-NEXT: %zext:_(s64) = G_ZEXT [[ICMP]](s1) + ; CHECK-NEXT: $x0 = COPY %zext(s64) + %0:_(s64) = COPY $x0 + %1:_(s64) = COPY $x1 + %2:_(s64) = COPY $x2 + %one:_(s64) = G_CONSTANT i64 -100 + %two:_(s64) = G_CONSTANT i64 2000 + %cmp1:_(s1) = G_ICMP intpred(eq), %0(s64), %one + %cmp2:_(s1) = G_ICMP intpred(ne), %0(s64), %two + %or:_(s1) = G_OR %cmp1, %cmp2 + %zext:_(s64) = G_ZEXT %or(s1) + $x0 = COPY %zext +... +--- +# offset icmp (x, -100) || icmp (x, 2000) -> x +name: test_icmp_or_icmp_offset +body: | + bb.1: + liveins: $x0, $x1 + ; CHECK-LABEL: name: test_icmp_or_icmp_offset + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -2001 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -2101 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[ADD]](s64), [[C1]] + ; CHECK-NEXT: %zext:_(s64) = G_ZEXT [[ICMP]](s1) + ; CHECK-NEXT: $x0 = COPY %zext(s64) + %0:_(s64) = COPY $x0 + %1:_(s64) = COPY $x1 + %2:_(s64) = COPY $x2 + %one:_(s64) = G_CONSTANT i64 -100 + %two:_(s64) = G_CONSTANT i64 2000 + %cmp1:_(s1) = G_ICMP intpred(slt), %0(s64), %one + %cmp2:_(s1) = G_ICMP intpred(sgt), %0(s64), %two + %or:_(s1) = G_OR %cmp1, %cmp2 + %zext:_(s64) = G_ZEXT %or(s1) + $x0 = COPY %zext +... +--- +# icmp (x, add(x, 9) || icmp (x, add(x, 2)) -> x +name: test_icmp_or_icmp_with_add_and_add +body: | + bb.1: + liveins: $x0, $x1 + ; CHECK-LABEL: name: test_icmp_or_icmp_with_add_and_add + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1 + ; CHECK-NEXT: %two:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: %add2:_(s64) = G_ADD [[COPY]], %two + ; CHECK-NEXT: %cmp2:_(s1) = G_ICMP intpred(ne), [[COPY1]](s64), %add2 + ; CHECK-NEXT: %zext:_(s64) = G_ZEXT %cmp2(s1) + ; CHECK-NEXT: $x0 = COPY %zext(s64) + %0:_(s64) = COPY $x0 + %1:_(s64) = COPY $x1 + %2:_(s64) = COPY $x2 + %nine:_(s64) = G_CONSTANT i64 9 + %two:_(s64) = G_CONSTANT i64 2 + %add1:_(s64) = G_ADD %0(s64), %nine + %add2:_(s64) = G_ADD %0(s64), %two + %cmp1:_(s1) = G_ICMP intpred(eq), %0(s64), %add1 + %cmp2:_(s1) = G_ICMP intpred(ne), %1(s64), %add2 + %and:_(s1) = G_OR %cmp1, %cmp2 + %zext:_(s64) = G_ZEXT %and(s1) + $x0 = COPY %zext +... +--- +# icmp (x, 9) && icmp (x, 2)) -> x +# buildConstant 0 +# buildICmp ult, R1, NewC +# buildZExtOrTrunc -> COPY +# erase G_AND +# x > 9 && x < 2 => false +name: test_icmp_and_icmp_9_2 +body: | + bb.1: + liveins: $x0, $x1 + ; CHECK-LABEL: name: test_icmp_and_icmp_9_2 + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: $x0 = COPY [[C]](s64) + %0:_(s64) = COPY $x0 + %nine:_(s64) = G_CONSTANT i64 9 + %two:_(s64) = G_CONSTANT i64 2 + %cmp1:_(s1) = G_ICMP intpred(sgt), %0(s64), %nine + %cmp2:_(s1) = G_ICMP intpred(slt), %0(s64), %two + %and:_(s1) = G_AND %cmp1, %cmp2 + %zext:_(s64) = G_ZEXT %and(s1) + $x0 = COPY %zext +... +--- +# icmp (x, v1) && icmp (x, v2)) -> x +name: test_icmp_and_icmp_with_vectors +body: | + bb.1: + liveins: $x0, $x1 + ; CHECK-LABEL: name: test_icmp_and_icmp_with_vectors + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5 + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6 + ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7 + ; CHECK-NEXT: %v1:_(<2 x s64>) = G_BUILD_VECTOR [[COPY]](s64), [[COPY1]](s64) + ; CHECK-NEXT: %v2:_(<2 x s64>) = G_BUILD_VECTOR [[COPY2]](s64), [[COPY3]](s64) + ; CHECK-NEXT: %v3:_(<2 x s64>) = G_BUILD_VECTOR [[COPY4]](s64), [[COPY5]](s64) + ; CHECK-NEXT: %v4:_(<2 x s64>) = G_BUILD_VECTOR [[COPY6]](s64), [[COPY7]](s64) + ; CHECK-NEXT: %cmp1:_(<2 x s1>) = G_ICMP intpred(ne), %v1(<2 x s64>), %v2 + ; CHECK-NEXT: %cmp2:_(<2 x s1>) = G_ICMP intpred(eq), %v3(<2 x s64>), %v4 + ; CHECK-NEXT: %and:_(<2 x s1>) = G_AND %cmp1, %cmp2 + ; CHECK-NEXT: %zext:_(<2 x s64>) = G_ZEXT %and(<2 x s1>) + ; CHECK-NEXT: $q0 = COPY %zext(<2 x s64>) + %0:_(s64) = COPY $x0 + %1:_(s64) = COPY $x1 + %2:_(s64) = COPY $x2 + %3:_(s64) = COPY $x3 + %4:_(s64) = COPY $x4 + %5:_(s64) = COPY $x5 + %6:_(s64) = COPY $x6 + %7:_(s64) = COPY $x7 + %nine:_(s64) = G_CONSTANT i64 9 + %two:_(s64) = G_CONSTANT i64 2 + %v1:_(<2 x s64>) = G_BUILD_VECTOR %0(s64), %1(s64) + %v2:_(<2 x s64>) = G_BUILD_VECTOR %2(s64), %3(s64) + %v3:_(<2 x s64>) = G_BUILD_VECTOR %4(s64), %5(s64) + %v4:_(<2 x s64>) = G_BUILD_VECTOR %6(s64), %7(s64) + %cmp1:_(<2 x s1>) = G_ICMP intpred(ne), %v1(<2 x s64>), %v2 + %cmp2:_(<2 x s1>) = G_ICMP intpred(eq), %v3(<2 x s64>), %v4 + %and:_(<2 x s1>) = G_AND %cmp1, %cmp2 + %zext:_(<2 x s64>) = G_ZEXT %and(<2 x s1>) + $q0 = COPY %zext +... diff --git a/llvm/test/CodeGen/AArch64/arm64-ccmp.ll b/llvm/test/CodeGen/AArch64/arm64-ccmp.ll index 446526986b88..5d3b2d3649e1 100644 --- a/llvm/test/CodeGen/AArch64/arm64-ccmp.ll +++ b/llvm/test/CodeGen/AArch64/arm64-ccmp.ll @@ -635,19 +635,7 @@ define i64 @select_noccmp1(i64 %v1, i64 %v2, i64 %v3, i64 %r) { ; ; GISEL-LABEL: select_noccmp1: ; GISEL: ; %bb.0: -; GISEL-NEXT: cmp x0, #0 -; GISEL-NEXT: cset w8, lt -; GISEL-NEXT: cmp x0, #13 -; GISEL-NEXT: cset w9, gt -; GISEL-NEXT: cmp x2, #2 -; GISEL-NEXT: cset w10, lt -; GISEL-NEXT: cmp x2, #4 -; GISEL-NEXT: cset w11, gt -; GISEL-NEXT: and w8, w8, w9 -; GISEL-NEXT: and w9, w10, w11 -; GISEL-NEXT: orr w8, w8, w9 -; GISEL-NEXT: tst w8, #0x1 -; GISEL-NEXT: csel x0, xzr, x3, ne +; GISEL-NEXT: mov x0, x3 ; GISEL-NEXT: ret %c0 = icmp slt i64 %v1, 0 %c1 = icmp sgt i64 %v1, 13 @@ -677,11 +665,8 @@ define i64 @select_noccmp2(i64 %v1, i64 %v2, i64 %v3, i64 %r) { ; ; GISEL-LABEL: select_noccmp2: ; GISEL: ; %bb.0: -; GISEL-NEXT: cmp x0, #0 -; GISEL-NEXT: cset w8, lt -; GISEL-NEXT: cmp x0, #13 -; GISEL-NEXT: cset w9, gt -; GISEL-NEXT: orr w8, w8, w9 +; GISEL-NEXT: cmp x0, #14 +; GISEL-NEXT: cset w8, hs ; GISEL-NEXT: tst w8, #0x1 ; GISEL-NEXT: csel x0, xzr, x3, ne ; GISEL-NEXT: sbfx w8, w8, #0, #1 @@ -719,25 +704,14 @@ define i32 @select_noccmp3(i32 %v0, i32 %v1, i32 %v2) { ; ; GISEL-LABEL: select_noccmp3: ; GISEL: ; %bb.0: -; GISEL-NEXT: cmp w0, #0 -; GISEL-NEXT: cset w8, lt -; GISEL-NEXT: cmp w0, #13 -; GISEL-NEXT: cset w9, gt -; GISEL-NEXT: cmp w0, #22 -; GISEL-NEXT: cset w10, lt -; GISEL-NEXT: cmp w0, #44 -; GISEL-NEXT: cset w11, gt -; GISEL-NEXT: cmp w0, #99 -; GISEL-NEXT: cset w12, eq +; GISEL-NEXT: mov w8, #99 ; =0x63 +; GISEL-NEXT: sub w9, w0, #45 +; GISEL-NEXT: mov w10, #-23 ; =0xffffffe9 ; GISEL-NEXT: cmp w0, #77 -; GISEL-NEXT: cset w13, eq -; GISEL-NEXT: orr w8, w8, w9 -; GISEL-NEXT: orr w9, w10, w11 -; GISEL-NEXT: and w8, w8, w9 -; GISEL-NEXT: orr w9, w12, w13 -; GISEL-NEXT: and w8, w8, w9 -; GISEL-NEXT: tst w8, #0x1 -; GISEL-NEXT: csel w0, w1, w2, ne +; GISEL-NEXT: ccmp w0, w8, #4, ne +; GISEL-NEXT: ccmp w9, w10, #2, eq +; GISEL-NEXT: ccmp w0, #14, #0, lo +; GISEL-NEXT: csel w0, w1, w2, hs ; GISEL-NEXT: ret %c0 = icmp slt i32 %v0, 0 %c1 = icmp sgt i32 %v0, 13 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll index b4a8193d2377..ec3c08ec7952 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll @@ -183,12 +183,10 @@ define i1 @snan_f16(half %x) nounwind { ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00 -; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v0, v1 -; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7e00 -; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], v0, v1 -; GFX7GLISEL-NEXT: s_and_b64 s[4:5], vcc, s[4:5] -; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] +; GFX7GLISEL-NEXT: v_add_i32_e32 v0, vcc, 0xffff83ff, v0 +; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x1ff +; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1 +; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX8CHECK-LABEL: snan_f16: @@ -894,11 +892,9 @@ define i1 @not_isnan_f16(half %x) { ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00 +; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c01 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1 -; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v0, v1 -; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] -; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] +; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX8CHECK-LABEL: not_isnan_f16: @@ -1542,10 +1538,8 @@ define i1 @not_issubnormal_or_zero_f16(half %x) { ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00 -; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], v1, v2 -; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0 +; GFX7GLISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v2 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1 @@ -2103,11 +2097,9 @@ define i1 @ispositive_f16(half %x) { ; GFX7GLISEL: ; %bb.0: ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00 +; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c01 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1 -; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v0, v1 -; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] -; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] +; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX8CHECK-LABEL: ispositive_f16: @@ -2294,13 +2286,12 @@ define i1 @not_isnegative_f16(half %x) { ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00 +; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c01 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v2 -; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v0, v2 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v1 +; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00 +; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], v0, v1 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] -; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v0, v2 -; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31] ; @@ -2355,11 +2346,10 @@ define i1 @iszero_or_nan_f16(half %x) { ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00 -; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], v0, v1 -; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] -; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] +; GFX7GLISEL-NEXT: v_add_i32_e32 v0, vcc, 0xffff83ff, v0 +; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0xffff8400 +; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1 +; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX8CHECK-LABEL: iszero_or_nan_f16: @@ -2414,11 +2404,10 @@ define i1 @iszero_or_nan_f_daz(half %x) #0 { ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00 -; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], v0, v1 -; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] -; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] +; GFX7GLISEL-NEXT: v_add_i32_e32 v0, vcc, 0xffff83ff, v0 +; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0xffff8400 +; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1 +; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX8CHECK-LABEL: iszero_or_nan_f_daz: @@ -2473,11 +2462,10 @@ define i1 @iszero_or_nan_f_maybe_daz(half %x) #1 { ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00 -; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], v0, v1 -; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] -; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] +; GFX7GLISEL-NEXT: v_add_i32_e32 v0, vcc, 0xffff83ff, v0 +; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0xffff8400 +; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1 +; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX8CHECK-LABEL: iszero_or_nan_f_maybe_daz: @@ -2733,11 +2721,10 @@ define i1 @iszero_or_qnan_f16(half %x) { ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7e00 -; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX7GLISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v1 -; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] -; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] +; GFX7GLISEL-NEXT: v_add_i32_e32 v0, vcc, 0xffff8200, v0 +; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0xffff8201 +; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1 +; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX8CHECK-LABEL: iszero_or_qnan_f16: @@ -2795,13 +2782,11 @@ define i1 @iszero_or_snan_f16(half %x) { ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00 -; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], v0, v1 -; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7e00 -; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[6:7], v0, v1 -; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX7GLISEL-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7] -; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] +; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0 +; GFX7GLISEL-NEXT: v_add_i32_e32 v0, vcc, 0xffff83ff, v0 +; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x1ff +; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1 +; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31] ; @@ -2875,15 +2860,14 @@ define i1 @not_iszero_or_qnan_f16(half %x) { ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v2 -; GFX7GLISEL-NEXT: s_or_b64 s[6:7], vcc, s[4:5] -; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v1, v2 -; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7e00 -; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], v1, v2 -; GFX7GLISEL-NEXT: s_and_b64 s[4:5], vcc, s[4:5] +; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] +; GFX7GLISEL-NEXT: v_add_i32_e32 v1, vcc, 0xffff83ff, v1 +; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x1ff +; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v1, v2 +; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc ; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800 -; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[6:7], s[4:5] ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] @@ -3020,10 +3004,8 @@ define i1 @isinf_or_nan_f16(half %x) { ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00 -; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1 -; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], v0, v1 -; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] -; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] +; GFX7GLISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1 +; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX8CHECK-LABEL: isinf_or_nan_f16: @@ -3132,10 +3114,8 @@ define i1 @isfinite_or_nan_f(half %x) { ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00 -; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1 -; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], v0, v1 -; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] -; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] +; GFX7GLISEL-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1 +; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX8CHECK-LABEL: isfinite_or_nan_f: -- GitLab From b1acb7a315e903ee340a33dbc9b2b61b0450bb67 Mon Sep 17 00:00:00 2001 From: stephenpeckham <118857872+stephenpeckham@users.noreply.github.com> Date: Tue, 6 Feb 2024 09:08:18 -0600 Subject: [PATCH 079/266] [XCOFF] Add compiler version to an auxiliary symbol table entry (#80162) C_FILE symbols. To match the behavior of the assembler and the legacy compiler, this includes using the generic ".file" name for the C_FILE symbol and generating the actual file name in an auxiliary entry. --- llvm/include/llvm/BinaryFormat/XCOFF.h | 1 + llvm/include/llvm/MC/MCAssembler.h | 8 + llvm/lib/MC/MCAsmStreamer.cpp | 25 ++- llvm/lib/MC/MCObjectStreamer.cpp | 4 +- llvm/lib/MC/XCOFFObjectWriter.cpp | 75 ++++++- .../CodeGen/PowerPC/aix-alias-alignment-2.ll | 2 +- .../CodeGen/PowerPC/aix-alias-alignment.ll | 2 +- .../aix-available-externally-linkage-fun.ll | 8 +- llvm/test/CodeGen/PowerPC/aix-extern-weak.ll | 7 +- llvm/test/CodeGen/PowerPC/aix-extern.ll | 7 +- llvm/test/CodeGen/PowerPC/aix-filename-c.ll | 3 +- llvm/test/CodeGen/PowerPC/aix-filename-cpp.ll | 3 +- llvm/test/CodeGen/PowerPC/aix-filename-f.ll | 3 +- llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll | 14 +- .../CodeGen/PowerPC/aix-llvm-intrinsic.ll | 28 +-- llvm/test/CodeGen/PowerPC/aix-overflow-toc.py | 16 +- .../test/CodeGen/PowerPC/aix-relro-section.ll | 24 +-- .../aix-small-local-exec-tls-largeaccess.ll | 60 +++--- .../CodeGen/PowerPC/aix-tls-ie-xcoff-reloc.ll | 190 +++++++++-------- .../PowerPC/aix-tls-le-xcoff-reloc-large.ll | 122 +++++------ .../PowerPC/aix-tls-le-xcoff-reloc-large32.ll | 136 ++++++------ .../CodeGen/PowerPC/aix-tls-le-xcoff-reloc.ll | 108 +++++----- .../PowerPC/aix-tls-le-xcoff-reloc32.ll | 122 +++++------ .../PowerPC/aix-tls-xcoff-reloc-large.ll | 198 +++++++++--------- .../CodeGen/PowerPC/aix-tls-xcoff-reloc.ll | 193 +++++++++-------- .../PowerPC/aix-tls-xcoff-variables.ll | 67 +++--- .../PowerPC/aix-user-defined-memcpy.ll | 22 +- llvm/test/CodeGen/PowerPC/aix-weak.ll | 7 +- llvm/test/CodeGen/PowerPC/aix-xcoff-cold.ll | 2 +- .../PowerPC/aix-xcoff-data-sections.ll | 30 +-- llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll | 22 +- .../aix-xcoff-exception-section-debug.ll | 8 +- .../PowerPC/aix-xcoff-exception-section.ll | 16 +- .../PowerPC/aix-xcoff-explicit-section.ll | 14 +- .../CodeGen/PowerPC/aix-xcoff-funcsect.ll | 156 +++++++------- llvm/test/CodeGen/PowerPC/aix-xcoff-lcomm.ll | 2 +- .../CodeGen/PowerPC/aix-xcoff-reloc-large.ll | 2 +- llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll | 46 ++-- llvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll | 2 +- .../PowerPC/aix-xcoff-symbol-rename.ll | 46 ++-- .../CodeGen/PowerPC/basic-toc-data-def.ll | 22 +- .../CodeGen/PowerPC/basic-toc-data-extern.ll | 32 +-- ...iltins-ppc-xlcompat-trap-annotations-td.ll | 2 +- ...iltins-ppc-xlcompat-trap-annotations-tw.ll | 2 +- .../test/CodeGen/PowerPC/pgo-ref-directive.ll | 2 +- llvm/test/CodeGen/PowerPC/toc-data-const.ll | 56 ++--- llvm/test/MC/PowerPC/aix-file-symbols.s | 16 +- .../llvm-objdump/XCOFF/symbol-table.test | 46 ++-- 48 files changed, 1043 insertions(+), 936 deletions(-) diff --git a/llvm/include/llvm/BinaryFormat/XCOFF.h b/llvm/include/llvm/BinaryFormat/XCOFF.h index 19d44a5ac57f..bbcd8a4f29ae 100644 --- a/llvm/include/llvm/BinaryFormat/XCOFF.h +++ b/llvm/include/llvm/BinaryFormat/XCOFF.h @@ -27,6 +27,7 @@ namespace XCOFF { constexpr size_t FileNamePadSize = 6; constexpr size_t NameSize = 8; +constexpr size_t AuxFileEntNameSize = 14; constexpr size_t FileHeaderSize32 = 20; constexpr size_t FileHeaderSize64 = 24; constexpr size_t AuxFileHeaderSize32 = 72; diff --git a/llvm/include/llvm/MC/MCAssembler.h b/llvm/include/llvm/MC/MCAssembler.h index 5ae5f6d70938..3fa5f2fe655e 100644 --- a/llvm/include/llvm/MC/MCAssembler.h +++ b/llvm/include/llvm/MC/MCAssembler.h @@ -133,6 +133,8 @@ private: /// List of declared file names std::vector> FileNames; + // Optional compiler version. + std::string CompilerVersion; MCDwarfLineTableParams LTParams; @@ -486,6 +488,12 @@ public: FileNames.emplace_back(std::string(FileName), Symbols.size()); } + void setCompilerVersion(std::string CompilerVers) { + if (CompilerVersion.empty()) + CompilerVersion = std::move(CompilerVers); + } + StringRef getCompilerVersion() { return CompilerVersion; } + /// Write the necessary bundle padding to \p OS. /// Expects a fragment \p F containing instructions and its size \p FSize. void writeFragmentPadding(raw_ostream &OS, const MCEncodedFragment &F, diff --git a/llvm/lib/MC/MCAsmStreamer.cpp b/llvm/lib/MC/MCAsmStreamer.cpp index a4dbd8cc1544..3dc70a401589 100644 --- a/llvm/lib/MC/MCAsmStreamer.cpp +++ b/llvm/lib/MC/MCAsmStreamer.cpp @@ -1590,17 +1590,22 @@ void MCAsmStreamer::emitFileDirective(StringRef Filename, assert(MAI->hasFourStringsDotFile()); OS << "\t.file\t"; PrintQuotedString(Filename, OS); - OS << ","; - if (!CompilerVersion.empty()) { - PrintQuotedString(CompilerVersion, OS); - } - if (!TimeStamp.empty()) { - OS << ","; - PrintQuotedString(TimeStamp, OS); - } - if (!Description.empty()) { + bool useTimeStamp = !TimeStamp.empty(); + bool useCompilerVersion = !CompilerVersion.empty(); + bool useDescription = !Description.empty(); + if (useTimeStamp || useCompilerVersion || useDescription) { OS << ","; - PrintQuotedString(Description, OS); + if (useTimeStamp) + PrintQuotedString(TimeStamp, OS); + if (useCompilerVersion || useDescription) { + OS << ","; + if (useCompilerVersion) + PrintQuotedString(CompilerVersion, OS); + if (useDescription) { + OS << ","; + PrintQuotedString(Description, OS); + } + } } EmitEOL(); } diff --git a/llvm/lib/MC/MCObjectStreamer.cpp b/llvm/lib/MC/MCObjectStreamer.cpp index bb4a92434a14..8948f3f16457 100644 --- a/llvm/lib/MC/MCObjectStreamer.cpp +++ b/llvm/lib/MC/MCObjectStreamer.cpp @@ -902,7 +902,9 @@ void MCObjectStreamer::emitFileDirective(StringRef Filename, StringRef TimeStamp, StringRef Description) { getAssembler().addFileName(Filename); - // TODO: add additional info to integrated assembler. + getAssembler().setCompilerVersion(CompilerVerion.str()); + // TODO: add TimeStamp and Description to .file symbol table entry + // with the integrated assembler. } void MCObjectStreamer::emitAddrsig() { diff --git a/llvm/lib/MC/XCOFFObjectWriter.cpp b/llvm/lib/MC/XCOFFObjectWriter.cpp index 11f8a72edead..8809af2e5e0c 100644 --- a/llvm/lib/MC/XCOFFObjectWriter.cpp +++ b/llvm/lib/MC/XCOFFObjectWriter.cpp @@ -361,6 +361,8 @@ class XCOFFObjectWriter : public MCObjectWriter { bool is64Bit() const { return TargetObjectWriter->is64Bit(); } bool nameShouldBeInStringTable(const StringRef &); void writeSymbolName(const StringRef &); + bool auxFileSymNameShouldBeInStringTable(const StringRef &); + void writeAuxFileSymName(const StringRef &); void writeSymbolEntryForCsectMemberLabel(const Symbol &SymbolRef, const XCOFFSection &CSectionRef, @@ -391,7 +393,8 @@ class XCOFFObjectWriter : public MCObjectWriter { const MCAsmLayout &Layout, CInfoSymSectionEntry &CInfoSymEntry, uint64_t &CurrentAddressLocation); - void writeSymbolTable(const MCAsmLayout &Layout); + void writeSymbolTable(MCAssembler &Asm, const MCAsmLayout &Layout); + void writeSymbolAuxFileEntry(StringRef &Name, uint8_t ftype); void writeSymbolAuxDwarfEntry(uint64_t LengthOfSectionPortion, uint64_t NumberOfRelocEnt = 0); void writeSymbolAuxCsectEntry(uint64_t SectionOrLength, @@ -416,7 +419,7 @@ class XCOFFObjectWriter : public MCObjectWriter { // *) Assigns symbol table indices. // *) Builds up the section header table by adding any non-empty sections to // `Sections`. - void assignAddressesAndIndices(const MCAsmLayout &); + void assignAddressesAndIndices(MCAssembler &Asm, const MCAsmLayout &); // Called after relocations are recorded. void finalizeSectionInfo(); void finalizeRelocationInfo(SectionEntry *Sec, uint64_t RelCount); @@ -640,12 +643,20 @@ void XCOFFObjectWriter::executePostLayoutBinding(MCAssembler &Asm, if (FileNames.empty()) FileNames.emplace_back(".file", 0); for (const std::pair &F : FileNames) { - if (nameShouldBeInStringTable(F.first)) + if (auxFileSymNameShouldBeInStringTable(F.first)) Strings.add(F.first); } + // Always add ".file" to the symbol table. The actual file name will be in + // the AUX_FILE auxiliary entry. + if (nameShouldBeInStringTable(".file")) + Strings.add(".file"); + StringRef Vers = Asm.getCompilerVersion(); + if (auxFileSymNameShouldBeInStringTable(Vers)) + Strings.add(Vers); + Strings.finalize(); - assignAddressesAndIndices(Layout); + assignAddressesAndIndices(Asm, Layout); } void XCOFFObjectWriter::recordRelocation(MCAssembler &Asm, @@ -818,7 +829,7 @@ uint64_t XCOFFObjectWriter::writeObject(MCAssembler &Asm, writeSectionHeaderTable(); writeSections(Asm, Layout); writeRelocations(); - writeSymbolTable(Layout); + writeSymbolTable(Asm, Layout); // Write the string table. Strings.write(W.OS); @@ -878,6 +889,36 @@ void XCOFFObjectWriter::writeSymbolAuxCsectEntry(uint64_t SectionOrLength, } } +bool XCOFFObjectWriter::auxFileSymNameShouldBeInStringTable( + const StringRef &SymbolName) { + return SymbolName.size() > XCOFF::AuxFileEntNameSize; +} + +void XCOFFObjectWriter::writeAuxFileSymName(const StringRef &SymbolName) { + // Magic, Offset or SymbolName. + if (auxFileSymNameShouldBeInStringTable(SymbolName)) { + W.write(0); + W.write(Strings.getOffset(SymbolName)); + W.OS.write_zeros(XCOFF::FileNamePadSize); + } else { + char Name[XCOFF::AuxFileEntNameSize + 1]; + std::strncpy(Name, SymbolName.data(), XCOFF::AuxFileEntNameSize); + ArrayRef NameRef(Name, XCOFF::AuxFileEntNameSize); + W.write(NameRef); + } +} + +void XCOFFObjectWriter::writeSymbolAuxFileEntry(StringRef &Name, + uint8_t ftype) { + writeAuxFileSymName(Name); + W.write(ftype); + W.OS.write_zeros(2); + if (is64Bit()) + W.write(XCOFF::AUX_FILE); + else + W.OS.write_zeros(1); +} + void XCOFFObjectWriter::writeSymbolAuxDwarfEntry( uint64_t LengthOfSectionPortion, uint64_t NumberOfRelocEnt) { writeWord(LengthOfSectionPortion); @@ -1109,8 +1150,11 @@ void XCOFFObjectWriter::writeRelocations() { writeRelocation(Reloc, *DwarfSection.DwarfSect); } -void XCOFFObjectWriter::writeSymbolTable(const MCAsmLayout &Layout) { +void XCOFFObjectWriter::writeSymbolTable(MCAssembler &Asm, + const MCAsmLayout &Layout) { // Write C_FILE symbols. + StringRef Vers = Asm.getCompilerVersion(); + for (const std::pair &F : FileNames) { // The n_name of a C_FILE symbol is the source file's name when no auxiliary // entries are present. @@ -1139,9 +1183,15 @@ void XCOFFObjectWriter::writeSymbolTable(const MCAsmLayout &Layout) { else CpuID = XCOFF::TCPU_COM; - writeSymbolEntry(FileName, /*Value=*/0, XCOFF::ReservedSectionNum::N_DEBUG, + int NumberOfFileAuxEntries = 1; + if (!Vers.empty()) + ++NumberOfFileAuxEntries; + writeSymbolEntry(".file", /*Value=*/0, XCOFF::ReservedSectionNum::N_DEBUG, /*SymbolType=*/(LangID << 8) | CpuID, XCOFF::C_FILE, - /*NumberOfAuxEntries=*/0); + NumberOfFileAuxEntries); + writeSymbolAuxFileEntry(FileName, XCOFF::XFT_FN); + if (!Vers.empty()) + writeSymbolAuxFileEntry(Vers, XCOFF::XFT_CV); } if (CInfoSymSection.Entry) @@ -1357,9 +1407,12 @@ void XCOFFObjectWriter::addCInfoSymEntry(StringRef Name, StringRef Metadata) { std::make_unique(Name.str(), Metadata.str())); } -void XCOFFObjectWriter::assignAddressesAndIndices(const MCAsmLayout &Layout) { - // The symbol table starts with all the C_FILE symbols. - uint32_t SymbolTableIndex = FileNames.size(); +void XCOFFObjectWriter::assignAddressesAndIndices(MCAssembler &Asm, + const MCAsmLayout &Layout) { + // The symbol table starts with all the C_FILE symbols. Each C_FILE symbol + // requires 1 or 2 auxiliary entries. + uint32_t SymbolTableIndex = + (2 + (Asm.getCompilerVersion().empty() ? 0 : 1)) * FileNames.size(); if (CInfoSymSection.Entry) SymbolTableIndex++; diff --git a/llvm/test/CodeGen/PowerPC/aix-alias-alignment-2.ll b/llvm/test/CodeGen/PowerPC/aix-alias-alignment-2.ll index b8299148cd8d..0993a243f73b 100644 --- a/llvm/test/CodeGen/PowerPC/aix-alias-alignment-2.ll +++ b/llvm/test/CodeGen/PowerPC/aix-alias-alignment-2.ll @@ -58,7 +58,7 @@ define void @foo3(%struct.B %a1) { ; ASM-NEXT: .vbyte 4, 34 ; SYM: SYMBOL TABLE: -; SYM-NEXT: 00000000 df *DEBUG* 00000000 +; SYM-NEXT: 00000000 df *DEBUG* 00000000 .file ; SYM-NEXT: 00000000 l .text 0000008a ; SYM-NEXT: 00000000 g F .text (csect: ) 00000000 .foo1 ; SYM-NEXT: 00000030 g F .text (csect: ) 00000000 .foo2 diff --git a/llvm/test/CodeGen/PowerPC/aix-alias-alignment.ll b/llvm/test/CodeGen/PowerPC/aix-alias-alignment.ll index 8bfc5139aa74..7e51f4173aa8 100644 --- a/llvm/test/CodeGen/PowerPC/aix-alias-alignment.ll +++ b/llvm/test/CodeGen/PowerPC/aix-alias-alignment.ll @@ -61,7 +61,7 @@ define void @foo(i32 %a1, i32 %a2, i32 %a3) { ; OBJ-NEXT: c: 4e 80 00 20 blr ; SYM: SYMBOL TABLE: -; SYM-NEXT: 00000000 df *DEBUG* 00000000 +; SYM-NEXT: 00000000 df *DEBUG* 00000000 .file ; SYM-NEXT: 00000000 l .text 00000029 ; SYM-NEXT: 00000000 g F .text (csect: ) 00000000 .foo ; SYM-NEXT: 0000002c l .data 00000008 .data diff --git a/llvm/test/CodeGen/PowerPC/aix-available-externally-linkage-fun.ll b/llvm/test/CodeGen/PowerPC/aix-available-externally-linkage-fun.ll index f87184f7b4bf..0ad229004b8a 100644 --- a/llvm/test/CodeGen/PowerPC/aix-available-externally-linkage-fun.ll +++ b/llvm/test/CodeGen/PowerPC/aix-available-externally-linkage-fun.ll @@ -6,11 +6,11 @@ ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \ ; RUN: -mattr=-altivec -filetype=obj -o %t.o < %s -; RUN: llvm-readobj --symbols %t.o | FileCheck --check-prefix=OBJ %s +; RUN: llvm-readobj --symbols %t.o | FileCheck -D#NFA=2 --check-prefix=OBJ %s ; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 \ ; RUN: -mattr=-altivec -filetype=obj -o %t64.o < %s -; RUN: llvm-readobj --symbols %t64.o | FileCheck --check-prefix=OBJ %s +; RUN: llvm-readobj --symbols %t64.o | FileCheck -D#NFA=2 --check-prefix=OBJ %s define available_externally i32 @foo(i32 %a) { entry: @@ -27,7 +27,7 @@ entry: ; OBJ-NEXT: StorageClass: C_EXT (0x2) ; OBJ-NEXT: NumberOfAuxEntries: 1 ; OBJ-NEXT: CSECT Auxiliary Entry { -; OBJ-NEXT: Index: 2 +; OBJ-NEXT: Index: [[#NFA+2]] ; OBJ-NEXT: SectionLen: 0 ; OBJ-NEXT: ParameterHashIndex: 0x0 ; OBJ-NEXT: TypeChkSectNum: 0x0 @@ -42,7 +42,7 @@ entry: ; OBJ-NEXT: StorageClass: C_EXT (0x2) ; OBJ-NEXT: NumberOfAuxEntries: 1 ; OBJ-NEXT: CSECT Auxiliary Entry { -; OBJ-NEXT: Index: 4 +; OBJ-NEXT: Index: [[#NFA+4]] ; OBJ-NEXT: SectionLen: 0 ; OBJ-NEXT: ParameterHashIndex: 0x0 ; OBJ-NEXT: TypeChkSectNum: 0x0 diff --git a/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll b/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll index 11b6827c33b1..ea61fdb022b5 100644 --- a/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll +++ b/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll @@ -65,16 +65,15 @@ declare extern_weak void @foo_ext_weak(ptr) ; CHECKSYM: Symbols [ ; CHECKSYM-NEXT: Symbol { ; CHECKSYM-NEXT: Index: 0 -; CHECKSYM-NEXT: Name: +; CHECKSYM-NEXT: Name: .file ; CHECKSYM-NEXT: Value (SymbolTableIndex): 0x0 ; CHECKSYM-NEXT: Section: N_DEBUG ; CHECKSYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9) ; CHECKSYM32-NEXT: CPU Version ID: TCPU_COM (0x3) ; CHECKSYM64-NEXT: CPU Version ID: TCPU_PPC64 (0x2) ; CHECKSYM-NEXT: StorageClass: C_FILE (0x67) -; CHECKSYM-NEXT: NumberOfAuxEntries: 0 -; CHECKSYM-NEXT: } -; CHECKSYM-NEXT: Symbol { +; CHECKSYM-NEXT: NumberOfAuxEntries: 2 +; CHECKSYM: Symbol { ; CHECKSYM-NEXT: Index: [[#Index:]] ; CHECKSYM-NEXT: Name: .foo_ext_weak ; CHECKSYM-NEXT: Value (RelocatableAddress): 0x0 diff --git a/llvm/test/CodeGen/PowerPC/aix-extern.ll b/llvm/test/CodeGen/PowerPC/aix-extern.ll index 905e45847390..b4366dddedb2 100644 --- a/llvm/test/CodeGen/PowerPC/aix-extern.ll +++ b/llvm/test/CodeGen/PowerPC/aix-extern.ll @@ -88,16 +88,15 @@ declare i32 @bar_extern(ptr) ; CHECKSYM: Symbols [ ; CHECKSYM-NEXT: Symbol { ; CHECKSYM-NEXT: Index: 0 -; CHECKSYM-NEXT: Name: +; CHECKSYM-NEXT: Name: .file ; CHECKSYM-NEXT: Value (SymbolTableIndex): 0x0 ; CHECKSYM-NEXT: Section: N_DEBUG ; CHECKSYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9) ; CHECKSYM32-NEXT: CPU Version ID: TCPU_COM (0x3) ; CHECKSYM64-NEXT: CPU Version ID: TCPU_PPC64 (0x2) ; CHECKSYM-NEXT: StorageClass: C_FILE (0x67) -; CHECKSYM-NEXT: NumberOfAuxEntries: 0 -; CHECKSYM-NEXT: } -; CHECKSYM-NEXT: Symbol { +; CHECKSYM-NEXT: NumberOfAuxEntries: 2 +; CHECKSYM: Symbol { ; CHECKSYM-NEXT: Index: [[#Index:]] ; CHECKSYM-NEXT: Name: .bar_extern ; CHECKSYM-NEXT: Value (RelocatableAddress): 0x0 diff --git a/llvm/test/CodeGen/PowerPC/aix-filename-c.ll b/llvm/test/CodeGen/PowerPC/aix-filename-c.ll index 2adc51cc2aec..c4202a0c58ce 100644 --- a/llvm/test/CodeGen/PowerPC/aix-filename-c.ll +++ b/llvm/test/CodeGen/PowerPC/aix-filename-c.ll @@ -5,7 +5,8 @@ source_filename = "1.c" -; OBJ: Name: 1.c +; OBJ: Name: .file ; OBJ: Source Language ID: TB_C (0x0) ; OBJ32: CPU Version ID: TCPU_COM (0x3) ; OBJ64: CPU Version ID: TCPU_PPC64 (0x2) +; OBJ: Name: 1.c diff --git a/llvm/test/CodeGen/PowerPC/aix-filename-cpp.ll b/llvm/test/CodeGen/PowerPC/aix-filename-cpp.ll index 22496be1dfc8..802281b6c1ea 100644 --- a/llvm/test/CodeGen/PowerPC/aix-filename-cpp.ll +++ b/llvm/test/CodeGen/PowerPC/aix-filename-cpp.ll @@ -5,7 +5,8 @@ source_filename = "1.cpp" -; OBJ: Name: 1.cpp +; OBJ: Name: .file ; OBJ: Source Language ID: TB_CPLUSPLUS (0x9) ; OBJ32: CPU Version ID: TCPU_COM (0x3) ; OBJ64: CPU Version ID: TCPU_PPC64 (0x2) +; OBJ: Name: 1.cpp diff --git a/llvm/test/CodeGen/PowerPC/aix-filename-f.ll b/llvm/test/CodeGen/PowerPC/aix-filename-f.ll index 914c4facc3cf..99036bde702d 100644 --- a/llvm/test/CodeGen/PowerPC/aix-filename-f.ll +++ b/llvm/test/CodeGen/PowerPC/aix-filename-f.ll @@ -5,7 +5,8 @@ source_filename = "1.f95" -; OBJ: Name: 1.f95 +; OBJ: Name: .file ; OBJ: Source Language ID: TB_Fortran (0x1) ; OBJ32: CPU Version ID: TCPU_COM (0x3) ; OBJ64: CPU Version ID: TCPU_PPC64 (0x2) +; OBJ: Name: 1.f95 diff --git a/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll b/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll index 23fb51e94442..4cca1b4d6f7b 100644 --- a/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll +++ b/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll @@ -13,13 +13,23 @@ entry: ; CHECK-NEXT: AddressSize: 32bit ; CHECK: Symbol { ; CHECK-NEXT: Index: 0 -; CHECK-NEXT: Name: +; CHECK-NEXT: Name: .file ; CHECK-NEXT: Value (SymbolTableIndex): 0x0 ; CHECK-NEXT: Section: N_DEBUG ; CHECK-NEXT: Source Language ID: TB_CPLUSPLUS (0x9) ; CHECK-NEXT: CPU Version ID: TCPU_COM (0x3) ; CHECK-NEXT: StorageClass: C_FILE (0x67) -; CHECK-NEXT: NumberOfAuxEntries: 0 +; CHECK-NEXT: NumberOfAuxEntries: 2 +; CHECK-NEXT: File Auxiliary Entry { +; CHECK-NEXT: Index: 1 +; CHECK-NEXT: Name: +; CHECK-NEXT: Type: XFT_FN (0x0) +; CHECK-NEXT: } +; CHECK-NEXT: File Auxiliary Entry { +; CHECK-NEXT: Index: 2 +; CHECK-NEXT: Name: LLVM +; CHECK-NEXT: Type: XFT_CV (0x2) +; CHECK-NEXT: } ; CHECK-NEXT: } ; CHECK-NEXT: Symbol { ; CHECK-NEXT: Index: [[#Index:]] diff --git a/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll b/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll index 09aec55a5b3d..50677f36e3f7 100644 --- a/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll +++ b/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll @@ -7,12 +7,12 @@ ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \ ; RUN: -mattr=-altivec -filetype=obj -o %t.o < %s ; RUN: llvm-readobj --symbols %t.o | FileCheck --check-prefixes=CHECKSYM,CHECKSYM32 %s -; RUN: llvm-objdump -r -d --symbol-description %t.o | FileCheck --check-prefixes=CHECKRELOC,CHECKRELOC32 %s +; RUN: llvm-objdump -r -d --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefixes=CHECKRELOC,CHECKRELOC32 %s ; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 \ ; RUN: -mattr=-altivec -filetype=obj -o %t64.o < %s ; RUN: llvm-readobj --symbols %t64.o | FileCheck --check-prefixes=CHECKSYM,CHECKSYM64 %s -; RUN: llvm-objdump -r -d --symbol-description %t64.o | FileCheck --check-prefixes=CHECKRELOC,CHECKRELOC64 %s +; RUN: llvm-objdump -r -d --symbol-description %t64.o | FileCheck -D#NFA=2 --check-prefixes=CHECKRELOC,CHECKRELOC64 %s %struct.S = type { i32, i32 } @@ -40,17 +40,17 @@ declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1 immarg) ; CHECKSYM: Symbol { ; CHECKSYM-NEXT: Index: 0 -; CHECKSYM-NEXT: Name: +; CHECKSYM-NEXT: Name: .file ; CHECKSYM-NEXT: Value (SymbolTableIndex): 0x0 ; CHECKSYM-NEXT: Section: N_DEBUG ; CHECKSYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9) ; CHECKSYM32-NEXT: CPU Version ID: TCPU_COM (0x3) ; CHECKSYM64-NEXT: CPU Version ID: TCPU_PPC64 (0x2) ; CHECKSYM-NEXT: StorageClass: C_FILE (0x67) -; CHECKSYM-NEXT: NumberOfAuxEntries: 0 -; CHECKSYM-NEXT: } -; CHECKSYM-NEXT: Symbol { -; CHECKSYM-NEXT: Index: 1 +; CHECKSYM-NEXT: NumberOfAuxEntries: 2 +; CHECKSYM: } +; CHECKSYM: Symbol { +; CHECKSYM: Index: 3 ; CHECKSYM32-NEXT: Name: .___memset ; CHECKSYM64-NEXT: Name: .___memset64 ; CHECKSYM-NEXT: Value (RelocatableAddress): 0x0 @@ -59,7 +59,7 @@ declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1 immarg) ; CHECKSYM-NEXT: StorageClass: C_EXT (0x2) ; CHECKSYM-NEXT: NumberOfAuxEntries: 1 ; CHECKSYM-NEXT: CSECT Auxiliary Entry { -; CHECKSYM-NEXT: Index: 2 +; CHECKSYM-NEXT: Index: 4 ; CHECKSYM-NEXT: SectionLen: 0 ; CHECKSYM-NEXT: ParameterHashIndex: 0x0 ; CHECKSYM-NEXT: TypeChkSectNum: 0x0 @@ -72,19 +72,19 @@ declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1 immarg) ; CHECKSYM-NEXT: } ; CHECKSYM-NEXT: } -; CHECKRELOC32: 00000000 (idx: 7) .bar: -; CHECKRELOC64: 0000000000000000 (idx: 7) .bar: +; CHECKRELOC32: 00000000 (idx: [[#NFA+7]]) .bar: +; CHECKRELOC64: 0000000000000000 (idx: [[#NFA+7]]) .bar: ; CHECKRELOC-NEXT: 0: 7c 08 02 a6 mflr 0 ; CHECKRELOC32-NEXT: 4: 94 21 ff c0 stwu 1, -64(1) ; CHECKRELOC32-NEXT: 8: 80 62 00 00 lwz 3, 0(2) -; CHECKRELOC32-NEXT: 0000000a: R_TOC (idx: 13) s[TC] +; CHECKRELOC32-NEXT: 0000000a: R_TOC (idx: [[#NFA+13]]) s[TC] ; CHECKRELOC32-NEXT: c: 90 01 00 48 stw 0, 72(1) ; CHECKRELOC64-NEXT: 4: f8 21 ff 91 stdu 1, -112(1) ; CHECKRELOC64-NEXT: 8: e8 62 00 00 ld 3, 0(2) -; CHECKRELOC64-NEXT: 000000000000000a: R_TOC (idx: 13) s[TC] +; CHECKRELOC64-NEXT: 000000000000000a: R_TOC (idx: [[#NFA+13]]) s[TC] ; CHECKRELOC64-NEXT: c: f8 01 00 80 std 0, 128(1) ; CHECKRELOC-NEXT: 10: 80 83 00 04 lwz 4, 4(3) ; CHECKRELOC-NEXT: 14: 7c 85 23 78 mr 5, 4 ; CHECKRELOC-NEXT: 18: 4b ff ff e9 bl 0x0 -; CHECKRELOC32-NEXT: 00000018: R_RBR (idx: 1) .___memset[PR] -; CHECKRELOC64-NEXT: 0000000000000018: R_RBR (idx: 1) .___memset64[PR] +; CHECKRELOC32-NEXT: 00000018: R_RBR (idx: [[#NFA+1]]) .___memset[PR] +; CHECKRELOC64-NEXT: 0000000000000018: R_RBR (idx: [[#NFA+1]]) .___memset64[PR] diff --git a/llvm/test/CodeGen/PowerPC/aix-overflow-toc.py b/llvm/test/CodeGen/PowerPC/aix-overflow-toc.py index a5fbb81b8d9e..84438c3552e5 100644 --- a/llvm/test/CodeGen/PowerPC/aix-overflow-toc.py +++ b/llvm/test/CodeGen/PowerPC/aix-overflow-toc.py @@ -9,7 +9,7 @@ # RUN: llc -mtriple powerpc-ibm-aix-xcoff -code-model=small -data-sections=false -mcpu=pwr4 -mattr=-altivec -O0 \ # RUN: -filetype=obj -o %t.o < %t.ll -# RUN: llvm-objdump --no-print-imm-hex -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS32 %s +# RUN: llvm-objdump --no-print-imm-hex -D -r --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=DIS32 %s ## FIXME: currently only fileHeader and sectionHeaders are supported in XCOFF64. @@ -48,18 +48,18 @@ print("}") # ASM64: ld 4, L..C12289-131072(2) # @a12289 # DIS32: 0: 80 82 00 00 lwz 4, 0(2) -# DIS32: 00000002: R_TOC (idx: 24591) a0[TC] +# DIS32: 00000002: R_TOC (idx: [[#NFA+24591]]) a0[TC] # DIS32: c: 80 82 00 04 lwz 4, 4(2) -# DIS32: 0000000e: R_TOC (idx: 24593) a1[TC] +# DIS32: 0000000e: R_TOC (idx: [[#NFA+24593]]) a1[TC] # DIS32: fffc: 80 82 7f fc lwz 4, 32764(2) -# DIS32: 0000fffe: R_TOC (idx: 40973) a8191[TC] +# DIS32: 0000fffe: R_TOC (idx: [[#NFA+40973]]) a8191[TC] # DIS32: 10004: 80 82 80 00 lwz 4, -32768(2) -# DIS32: 00010006: R_TOC (idx: 40975) a8192[TC] +# DIS32: 00010006: R_TOC (idx: [[#NFA+40975]]) a8192[TC] # DIS32: 1000c: 80 82 80 04 lwz 4, -32764(2) -# DIS32: 0001000e: R_TOC (idx: 40977) a8193[TC] +# DIS32: 0001000e: R_TOC (idx: [[#NFA+40977]]) a8193[TC] # DIS32: 18004: 80 82 c0 00 lwz 4, -16384(2) -# DIS32: 00018006: R_TOC (idx: 49167) a12288[TC] +# DIS32: 00018006: R_TOC (idx: [[#NFA+49167]]) a12288[TC] # DIS32: 1800c: 80 82 c0 04 lwz 4, -16380(2) -# DIS32: 0001800e: R_TOC (idx: 49169) a12289[TC] +# DIS32: 0001800e: R_TOC (idx: [[#NFA+49169]]) a12289[TC] diff --git a/llvm/test/CodeGen/PowerPC/aix-relro-section.ll b/llvm/test/CodeGen/PowerPC/aix-relro-section.ll index 25be1f0e16f3..5da99191f3d0 100644 --- a/llvm/test/CodeGen/PowerPC/aix-relro-section.ll +++ b/llvm/test/CodeGen/PowerPC/aix-relro-section.ll @@ -4,10 +4,10 @@ ; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mxcoff-roptr < %s | FileCheck %s --check-prefix CHECK-RO ; RUN: llc -filetype=obj -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s -o %t32.o -; RUN: llvm-readobj %t32.o --syms --relocs | FileCheck %s --check-prefix=OBJ32 +; RUN: llvm-readobj %t32.o --syms --relocs | FileCheck %s -D#NFA=2 --check-prefix=OBJ32 ; RUN: llc -filetype=obj -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s -o %t64.o -; RUN: llvm-readobj %t64.o --syms --relocs | FileCheck %s --check-prefix=OBJ64 +; RUN: llvm-readobj %t64.o --syms --relocs | FileCheck %s -D#NFA=2 --check-prefix=OBJ64 @var = external constant i32 @ptr = private constant ptr @var, section "relro-section" @@ -20,11 +20,11 @@ ; OBJ32: Relocations [ ; OBJ32-NEXT: Section (index: 2) .data { -; OBJ32-NEXT: 0x0 R_POS var(1) 0x1F +; OBJ32-NEXT: 0x0 R_POS var([[#NFA+1]]) 0x1F ; OBJ32-NEXT: } ; OBJ32-NEXT: ] ; OBJ32-NEXT: Symbols [ -; OBJ32: Index: 1 +; OBJ32: Index: [[#NFA+1]] ; OBJ32-NEXT: Name: var ; OBJ32-NEXT: Value (RelocatableAddress): 0x0 ; OBJ32-NEXT: Section: N_UNDEF @@ -32,7 +32,7 @@ ; OBJ32-NEXT: StorageClass: C_EXT (0x2) ; OBJ32-NEXT: NumberOfAuxEntries: 1 ; OBJ32-NEXT: CSECT Auxiliary Entry { -; OBJ32-NEXT: Index: 2 +; OBJ32-NEXT: Index: [[#NFA+2]] ; OBJ32-NEXT: SectionLen: 0 ; OBJ32-NEXT: ParameterHashIndex: 0x0 ; OBJ32-NEXT: TypeChkSectNum: 0x0 @@ -42,7 +42,7 @@ ; OBJ32-NEXT: StabInfoIndex: 0x0 ; OBJ32-NEXT: StabSectNum: 0x0 ; OBJ32-NEXT: } -; OBJ32: Index: 5 +; OBJ32: Index: [[#NFA+5]] ; OBJ32-NEXT: Name: relro-section ; OBJ32-NEXT: Value (RelocatableAddress): 0x0 ; OBJ32-NEXT: Section: .data @@ -50,7 +50,7 @@ ; OBJ32-NEXT: StorageClass: C_HIDEXT (0x6B) ; OBJ32-NEXT: NumberOfAuxEntries: 1 ; OBJ32-NEXT: CSECT Auxiliary Entry { -; OBJ32-NEXT: Index: 6 +; OBJ32-NEXT: Index: [[#NFA+6]] ; OBJ32-NEXT: SectionLen: 4 ; OBJ32-NEXT: ParameterHashIndex: 0x0 ; OBJ32-NEXT: TypeChkSectNum: 0x0 @@ -64,11 +64,11 @@ ; OBJ64: Relocations [ ; OBJ64-NEXT: Section (index: 2) .data { -; OBJ64-NEXT: 0x0 R_POS var(1) 0x3F +; OBJ64-NEXT: 0x0 R_POS var([[#NFA+1]]) 0x3F ; OBJ64-NEXT: } ; OBJ64-NEXT: ] ; OBJ64-NEXT: Symbols [ -; OBJ64: Index: 1 +; OBJ64: Index: [[#NFA+1]] ; OBJ64-NEXT: Name: var ; OBJ64-NEXT: Value (RelocatableAddress): 0x0 ; OBJ64-NEXT: Section: N_UNDEF @@ -76,7 +76,7 @@ ; OBJ64-NEXT: StorageClass: C_EXT (0x2) ; OBJ64-NEXT: NumberOfAuxEntries: 1 ; OBJ64-NEXT: CSECT Auxiliary Entry { -; OBJ64-NEXT: Index: 2 +; OBJ64-NEXT: Index: [[#NFA+2]] ; OBJ64-NEXT: SectionLen: 0 ; OBJ64-NEXT: ParameterHashIndex: 0x0 ; OBJ64-NEXT: TypeChkSectNum: 0x0 @@ -85,7 +85,7 @@ ; OBJ64-NEXT: StorageMappingClass: XMC_UA (0x4) ; OBJ64-NEXT: Auxiliary Type: AUX_CSECT (0xFB) ; OBJ64-NEXT: } -; OBJ64: Index: 5 +; OBJ64: Index: [[#NFA+5]] ; OBJ64-NEXT: Name: relro-section ; OBJ64-NEXT: Value (RelocatableAddress): 0x0 ; OBJ64-NEXT: Section: .data @@ -93,7 +93,7 @@ ; OBJ64-NEXT: StorageClass: C_HIDEXT (0x6B) ; OBJ64-NEXT: NumberOfAuxEntries: 1 ; OBJ64-NEXT: CSECT Auxiliary Entry { -; OBJ64-NEXT: Index: 6 +; OBJ64-NEXT: Index: [[#NFA+6]] ; OBJ64-NEXT: SectionLen: 8 ; OBJ64-NEXT: ParameterHashIndex: 0x0 ; OBJ64-NEXT: TypeChkSectNum: 0x0 diff --git a/llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-largeaccess.ll b/llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-largeaccess.ll index 22b8503ef403..67d82c6908d7 100644 --- a/llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-largeaccess.ll +++ b/llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-largeaccess.ll @@ -11,7 +11,7 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+aix-small-local-exec-tls \ ; RUN: -mtriple powerpc64-ibm-aix-xcoff -xcoff-traceback-table=false \ ; RUN: --code-model=large -filetype=obj -o %t.o < %s -; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s +; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=DIS %s @mySmallLocalExecTLSv1 = thread_local(localexec) global [8187 x i32] zeroinitializer, align 4 @mySmallLocalExecTLS2 = thread_local(localexec) global [4000 x i32] zeroinitializer, align 4 @@ -152,79 +152,79 @@ entry: ret i32 %add15 } -; DIS: {{.*}}aix-small-local-exec-tls-largeaccess.ll.tmp.o: file format aix5coff64-rs6000 +; DIS: file format aix5coff64-rs6000 ; DIS: Disassembly of section .text: -; DIS: 0000000000000000 (idx: 3) .StoreArrays1: +; DIS: 0000000000000000 (idx: [[#NFA+3]]) .StoreArrays1: ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 3, 1 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 4, 4 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stw 3, 0(13) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: 15) mySmallLocalExecTLSv1[TL] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: [[#NFA+15]]) mySmallLocalExecTLSv1[TL] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 3, 2 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stw 4, 24(13) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: 15) mySmallLocalExecTLSv1[TL] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: [[#NFA+15]]) mySmallLocalExecTLSv1[TL] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stw 3, -32468(13) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: 17) mySmallLocalExecTLS2[TL] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: [[#NFA+17]]) mySmallLocalExecTLS2[TL] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 3, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stw 3, -16464(13) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: 19) mySmallLocalExecTLS3[TL] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: [[#NFA+19]]) mySmallLocalExecTLS3[TL] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 3, 88 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stw 4, -460(13) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: 21) mySmallLocalExecTLS4[TL] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: [[#NFA+21]]) mySmallLocalExecTLS4[TL] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stw 3, 15544(13) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: 23) mySmallLocalExecTLS5[TL] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: [[#NFA+23]]) mySmallLocalExecTLS5[TL] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 3, 102 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} blr -; DIS: 0000000000000040 (idx: 5) .StoreArrays2: +; DIS: 0000000000000040 (idx: [[#NFA+5]]) .StoreArrays2: ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 13) mySmallLocalExecTLSv2[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+13]]) mySmallLocalExecTLSv2[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 4, 1 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 3, 0(3) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 13) mySmallLocalExecTLSv2[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+13]]) mySmallLocalExecTLSv2[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} add 3, 13, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stw 4, 0(3) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 4, 4 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stw 4, 24(3) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 3, 2 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stw 3, -32468(13) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: 17) mySmallLocalExecTLS2[TL] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: [[#NFA+17]]) mySmallLocalExecTLS2[TL] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 3, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stw 3, -16464(13) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: 19) mySmallLocalExecTLS3[TL] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: [[#NFA+19]]) mySmallLocalExecTLS3[TL] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 3, 88 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stw 4, -460(13) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: 21) mySmallLocalExecTLS4[TL] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: [[#NFA+21]]) mySmallLocalExecTLS4[TL] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stw 3, 15544(13) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: 23) mySmallLocalExecTLS5[TL] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: [[#NFA+23]]) mySmallLocalExecTLS5[TL] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 3, 102 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} blr ; DIS: Disassembly of section .data: -; DIS: 0000000000000080 (idx: 7) StoreArrays1[DS]: +; DIS: 0000000000000080 (idx: [[#NFA+7]]) StoreArrays1[DS]: ; DIS-NEXT: 80: 00 00 00 00 -; DIS-NEXT: 0000000000000080: R_POS (idx: 3) .StoreArrays1 +; DIS-NEXT: 0000000000000080: R_POS (idx: [[#NFA+3]]) .StoreArrays1 ; DIS-NEXT: 84: 00 00 00 00 ; DIS-NEXT: 88: 00 00 00 00 -; DIS-NEXT: 0000000000000088: R_POS (idx: 11) TOC[TC0] +; DIS-NEXT: 0000000000000088: R_POS (idx: [[#NFA+11]]) TOC[TC0] ; DIS-NEXT: 8c: 00 00 00 b0 -; DIS: 0000000000000098 (idx: 9) StoreArrays2[DS]: +; DIS: 0000000000000098 (idx: [[#NFA+9]]) StoreArrays2[DS]: ; DIS-NEXT: 98: 00 00 00 00 -; DIS-NEXT: 0000000000000098: R_POS (idx: 5) .StoreArrays2 +; DIS-NEXT: 0000000000000098: R_POS (idx: [[#NFA+5]]) .StoreArrays2 ; DIS-NEXT: 9c: 00 00 00 40 ; DIS-NEXT: a0: 00 00 00 00 -; DIS-NEXT: 00000000000000a0: R_POS (idx: 11) TOC[TC0] +; DIS-NEXT: 00000000000000a0: R_POS (idx: [[#NFA+11]]) TOC[TC0] ; DIS-NEXT: a4: 00 00 00 b0 -; DIS: 00000000000000b0 (idx: 13) mySmallLocalExecTLSv2[TE]: +; DIS: 00000000000000b0 (idx: [[#NFA+13]]) mySmallLocalExecTLSv2[TE]: ; DIS-NEXT: b0: 00 00 00 00 -; DIS-NEXT: 00000000000000b0: R_TLS_LE (idx: 25) mySmallLocalExecTLSv2[TL] +; DIS-NEXT: 00000000000000b0: R_TLS_LE (idx: [[#NFA+25]]) mySmallLocalExecTLSv2[TL] ; DIS-NEXT: b4: 00 01 79 ec ; DIS: Disassembly of section .tdata: -; DIS: 0000000000000000 (idx: 15) mySmallLocalExecTLSv1[TL]: -; DIS: 0000000000007fec (idx: 17) mySmallLocalExecTLS2[TL]: -; DIS: 000000000000be6c (idx: 19) mySmallLocalExecTLS3[TL]: -; DIS: 000000000000fcec (idx: 21) mySmallLocalExecTLS4[TL]: -; DIS: 0000000000013b6c (idx: 23) mySmallLocalExecTLS5[TL]: -; DIS: 00000000000179ec (idx: 25) mySmallLocalExecTLSv2[TL]: +; DIS: 0000000000000000 (idx: [[#NFA+15]]) mySmallLocalExecTLSv1[TL]: +; DIS: 0000000000007fec (idx: [[#NFA+17]]) mySmallLocalExecTLS2[TL]: +; DIS: 000000000000be6c (idx: [[#NFA+19]]) mySmallLocalExecTLS3[TL]: +; DIS: 000000000000fcec (idx: [[#NFA+21]]) mySmallLocalExecTLS4[TL]: +; DIS: 0000000000013b6c (idx: [[#NFA+23]]) mySmallLocalExecTLS5[TL]: +; DIS: 00000000000179ec (idx: [[#NFA+25]]) mySmallLocalExecTLSv2[TL]: \ No newline at end of file diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-ie-xcoff-reloc.ll b/llvm/test/CodeGen/PowerPC/aix-tls-ie-xcoff-reloc.ll index e34bb130d5ed..46fa52815e96 100644 --- a/llvm/test/CodeGen/PowerPC/aix-tls-ie-xcoff-reloc.ll +++ b/llvm/test/CodeGen/PowerPC/aix-tls-ie-xcoff-reloc.ll @@ -1,26 +1,26 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-ibm-aix-xcoff \ ; RUN: -xcoff-traceback-table=false -data-sections=false -filetype=obj -o %t.o < %s -; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefix=REL64 %s -; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM64 %s -; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS64 %s +; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck -D#NFA=2 --check-prefix=REL64 %s +; RUN: llvm-readobj --syms %t.o | FileCheck -D#NFA=2 --check-prefix=SYM64 %s +; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=DIS64 %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-ibm-aix-xcoff -code-model=small \ ; RUN: -xcoff-traceback-table=false -data-sections=false -filetype=obj -o %t.o < %s -; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefix=REL64 %s -; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM64 %s -; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS64 %s +; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck -D#NFA=2 --check-prefix=REL64 %s +; RUN: llvm-readobj --syms %t.o | FileCheck -D#NFA=2 --check-prefix=SYM64 %s +; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=DIS64 %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc-ibm-aix-xcoff \ ; RUN: -xcoff-traceback-table=false -data-sections=false -filetype=obj -o %t.o < %s -; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefix=REL32 %s -; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM32 %s -; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS32 %s +; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck -D#NFA=2 --check-prefix=REL32 %s +; RUN: llvm-readobj --syms %t.o | FileCheck -D#NFA=2 --check-prefix=SYM32 %s +; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=DIS32 %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc-ibm-aix-xcoff -code-model=small \ ; RUN: -xcoff-traceback-table=false -data-sections=false -filetype=obj -o %t.o < %s -; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefix=REL32 %s -; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM32 %s -; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS32 %s +; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck -D#NFA=2 --check-prefix=REL32 %s +; RUN: llvm-readobj --syms %t.o | FileCheck -D#NFA=2 --check-prefix=SYM32 %s +; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=DIS32 %s @global_int_nonzero = thread_local(initialexec) global i32 1, align 4 @intern_int_zero = internal thread_local(initialexec) global i32 0, align 4 @@ -48,61 +48,60 @@ entry: declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) -; REL64: File: {{.*}}aix-tls-ie-xcoff-reloc.ll.tmp.o +; REL64: File: ; REL64-NEXT: Format: aix5coff64-rs6000 ; REL64-NEXT: Arch: powerpc64 ; REL64-NEXT: AddressSize: 64bit ; REL64-NEXT: Relocations [ ; REL64: Virtual Address: 0x2 -; REL64-NEXT: Symbol: intern_int_zero (17) +; REL64-NEXT: Symbol: intern_int_zero ([[#NFA+17]]) ; REL64-NEXT: IsSigned: No ; REL64-NEXT: FixupBitValue: 0 ; REL64-NEXT: Length: 16 ; REL64-NEXT: Type: R_TOC (0x3) ; REL64-NEXT: } ; REL64: Virtual Address: 0x12 -; REL64-NEXT: Symbol: global_int_nonzero (19) +; REL64-NEXT: Symbol: global_int_nonzero ([[#NFA+19]]) ; REL64-NEXT: IsSigned: No ; REL64-NEXT: FixupBitValue: 0 ; REL64-NEXT: Length: 16 ; REL64-NEXT: Type: R_TOC (0x3) ; REL64-NEXT: } ; REL64: Virtual Address: 0x22 -; REL64-NEXT: Symbol: intern_int_zero (17) +; REL64-NEXT: Symbol: intern_int_zero ([[#NFA+17]]) ; REL64-NEXT: IsSigned: No ; REL64-NEXT: FixupBitValue: 0 ; REL64-NEXT: Length: 16 ; REL64-NEXT: Type: R_TOC (0x3) ; REL64-NEXT: } ; REL64: Virtual Address: 0x78 -; REL64-NEXT: Symbol: intern_int_zero (25) +; REL64-NEXT: Symbol: intern_int_zero ([[#NFA+25]]) ; REL64-NEXT: IsSigned: No ; REL64-NEXT: FixupBitValue: 0 ; REL64-NEXT: Length: 64 ; REL64-NEXT: Type: R_TLS_IE (0x21) ; REL64-NEXT: } ; REL64: Virtual Address: 0x80 -; REL64-NEXT: Symbol: global_int_nonzero (23) +; REL64-NEXT: Symbol: global_int_nonzero ([[#NFA+23]]) ; REL64-NEXT: IsSigned: No ; REL64-NEXT: FixupBitValue: 0 ; REL64-NEXT: Length: 64 ; REL64-NEXT: Type: R_TLS_IE (0x21) ; REL64-NEXT: } -; SYM64: File: {{.*}}aix-tls-ie-xcoff-reloc.ll.tmp.o +; SYM64: File: ; SYM64-NEXT: Format: aix5coff64-rs6000 ; SYM64-NEXT: Arch: powerpc64 ; SYM64-NEXT: AddressSize: 64bit ; SYM64-NEXT: Symbols [ -; SYM64: Index: 17 -; SYM64-NEXT: Name: intern_int_zero +; SYM64: Name: intern_int_zero ; SYM64-NEXT: Value (RelocatableAddress): 0x78 ; SYM64-NEXT: Section: .data ; SYM64-NEXT: Type: 0x0 ; SYM64-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM64-NEXT: NumberOfAuxEntries: 1 ; SYM64-NEXT: CSECT Auxiliary Entry { -; SYM64-NEXT: Index: 18 +; SYM64-NEXT: Index: [[#INDX:]] ; SYM64-NEXT: SectionLen: 8 ; SYM64-NEXT: ParameterHashIndex: 0x0 ; SYM64-NEXT: TypeChkSectNum: 0x0 @@ -112,7 +111,7 @@ declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) ; SYM64-NEXT: Auxiliary Type: AUX_CSECT (0xFB) ; SYM64-NEXT: } ; SYM64-NEXT: } -; SYM64: Index: 19 +; SYM64: Index: [[#INDX+1]] ; SYM64-NEXT: Name: global_int_nonzero ; SYM64-NEXT: Value (RelocatableAddress): 0x80 ; SYM64-NEXT: Section: .data @@ -120,7 +119,7 @@ declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) ; SYM64-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM64-NEXT: NumberOfAuxEntries: 1 ; SYM64-NEXT: CSECT Auxiliary Entry { -; SYM64-NEXT: Index: 20 +; SYM64-NEXT: Index: [[#INDX+2]] ; SYM64-NEXT: SectionLen: 8 ; SYM64-NEXT: ParameterHashIndex: 0x0 ; SYM64-NEXT: TypeChkSectNum: 0x0 @@ -130,7 +129,7 @@ declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) ; SYM64-NEXT: Auxiliary Type: AUX_CSECT (0xFB) ; SYM64-NEXT: } ; SYM64-NEXT: } -; SYM64: Index: 23 +; SYM64: Index: [[#INDX+5]] ; SYM64-NEXT: Name: global_int_nonzero ; SYM64-NEXT: Value (RelocatableAddress): 0x0 ; SYM64-NEXT: Section: .tdata @@ -138,8 +137,8 @@ declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) ; SYM64-NEXT: StorageClass: C_EXT (0x2) ; SYM64-NEXT: NumberOfAuxEntries: 1 ; SYM64-NEXT: CSECT Auxiliary Entry { -; SYM64-NEXT: Index: 24 -; SYM64-NEXT: ContainingCsectSymbolIndex: 21 +; SYM64-NEXT: Index: [[#INDX+6]] +; SYM64-NEXT: ContainingCsectSymbolIndex: [[#INDX+3]] ; SYM64-NEXT: ParameterHashIndex: 0x0 ; SYM64-NEXT: TypeChkSectNum: 0x0 ; SYM64-NEXT: SymbolAlignmentLog2: 0 @@ -148,7 +147,7 @@ declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) ; SYM64-NEXT: Auxiliary Type: AUX_CSECT (0xFB) ; SYM64-NEXT: } ; SYM64-NEXT: } -; SYM64: Index: 25 +; SYM64: Index: [[#INDX+7]] ; SYM64-NEXT: Name: intern_int_zero ; SYM64-NEXT: Value (RelocatableAddress): 0x4 ; SYM64-NEXT: Section: .tbss @@ -156,7 +155,7 @@ declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) ; SYM64-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM64-NEXT: NumberOfAuxEntries: 1 ; SYM64-NEXT: CSECT Auxiliary Entry { -; SYM64-NEXT: Index: 26 +; SYM64-NEXT: Index: [[#INDX+8]] ; SYM64-NEXT: SectionLen: 4 ; SYM64-NEXT: ParameterHashIndex: 0x0 ; SYM64-NEXT: TypeChkSectNum: 0x0 @@ -167,121 +166,120 @@ declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) ; SYM64-NEXT: } ; SYM64-NEXT: } -; DIS64: {{.*}}aix-tls-ie-xcoff-reloc.ll.tmp.o: file format aix5coff64-rs6000 +; DIS64: {{.*}}: file format aix5coff64-rs6000 ; DIS64: Disassembly of section .text: -; DIS64: (idx: 3) .store_intern_int_zero: +; DIS64: (idx: [[#NFA+3]]) .store_intern_int_zero: ; DIS64-NEXT: ld 4, 0(2) -; DIS64-NEXT: (idx: 17) intern_int_zero[TC] +; DIS64-NEXT: (idx: [[#NFA+17]]) intern_int_zero[TC] ; DIS64-NEXT: stwx 3, 13, 4 ; DIS64-NEXT: blr -; DIS64: (idx: 5) .load_global_int_nonzero: +; DIS64: (idx: [[#NFA+5]]) .load_global_int_nonzero: ; DIS64-NEXT: ld 3, 8(2) -; DIS64-NEXT: (idx: 19) global_int_nonzero[TC] +; DIS64-NEXT: (idx: [[#NFA+19]]) global_int_nonzero[TC] ; DIS64-NEXT: lwax 3, 13, 3 ; DIS64-NEXT: blr -; DIS64: (idx: 7) .load_intern_int_zero: +; DIS64: (idx: [[#NFA+7]]) .load_intern_int_zero: ; DIS64-NEXT: ld 3, 0(2) -; DIS64-NEXT: (idx: 17) intern_int_zero[TC] +; DIS64-NEXT: (idx: [[#NFA+17]]) intern_int_zero[TC] ; DIS64-NEXT: lwax 3, 13, 3 ; DIS64-NEXT: blr ; DIS64: Disassembly of section .data: -; DIS64: (idx: 9) store_intern_int_zero[DS]: -; DIS64: R_POS (idx: 3) .store_intern_int_zero -; DIS64: R_POS (idx: 15) TOC[TC0] -; DIS64: (idx: 11) load_global_int_nonzero[DS]: -; DIS64: R_POS (idx: 5) .load_global_int_nonzero -; DIS64: R_POS (idx: 15) TOC[TC0] -; DIS64: (idx: 13) load_intern_int_zero[DS]: -; DIS64: R_POS (idx: 7) .load_intern_int_zero -; DIS64: R_POS (idx: 15) TOC[TC0] -; DIS64: (idx: 17) intern_int_zero[TC]: -; DIS64: R_TLS_IE (idx: 25) intern_int_zero[UL] -; DIS64: (idx: 19) global_int_nonzero[TC]: -; DIS64: R_TLS_IE (idx: 23) global_int_nonzero +; DIS64: (idx: [[#NFA+9]]) store_intern_int_zero[DS]: +; DIS64: R_POS (idx: [[#NFA+3]]) .store_intern_int_zero +; DIS64: R_POS (idx: [[#NFA+15]]) TOC[TC0] +; DIS64: (idx: [[#NFA+11]]) load_global_int_nonzero[DS]: +; DIS64: R_POS (idx: [[#NFA+5]]) .load_global_int_nonzero +; DIS64: R_POS (idx: [[#NFA+15]]) TOC[TC0] +; DIS64: (idx: [[#NFA+13]]) load_intern_int_zero[DS]: +; DIS64: R_POS (idx: [[#NFA+7]]) .load_intern_int_zero +; DIS64: R_POS (idx: [[#NFA+15]]) TOC[TC0] +; DIS64: (idx: [[#NFA+17]]) intern_int_zero[TC]: +; DIS64: R_TLS_IE (idx: [[#NFA+25]]) intern_int_zero[UL] +; DIS64: (idx: [[#NFA+19]]) global_int_nonzero[TC]: +; DIS64: R_TLS_IE (idx: [[#NFA+23]]) global_int_nonzero ; DIS64: Disassembly of section .tdata: -; DIS64: (idx: 23) global_int_nonzero: +; DIS64: (idx: [[#NFA+23]]) global_int_nonzero: ; DIS64: Disassembly of section .tbss: -; DIS64: (idx: 25) intern_int_zero[UL]: +; DIS64: (idx: [[#NFA+25]]) intern_int_zero[UL]: -; REL32: File: {{.*}}aix-tls-ie-xcoff-reloc.ll.tmp.o +; REL32: File: ; REL32-NEXT: Format: aixcoff-rs6000 ; REL32-NEXT: Arch: powerpc ; REL32-NEXT: AddressSize: 32bit ; REL32-NEXT: Relocations [ ; REL32: Virtual Address: 0xA -; REL32-NEXT: Symbol: intern_int_zero (19) +; REL32-NEXT: Symbol: intern_int_zero ([[#NFA+19]]) ; REL32-NEXT: IsSigned: No ; REL32-NEXT: FixupBitValue: 0 ; REL32-NEXT: Length: 16 ; REL32-NEXT: Type: R_TOC (0x3) ; REL32-NEXT: } ; REL32: Virtual Address: 0x10 -; REL32-NEXT: Symbol: .__get_tpointer (1) +; REL32-NEXT: Symbol: .__get_tpointer ([[#NFA+1]]) ; REL32-NEXT: IsSigned: No ; REL32-NEXT: FixupBitValue: 0 ; REL32-NEXT: Length: 26 ; REL32-NEXT: Type: R_RBA (0x18) ; REL32-NEXT: } ; REL32: Virtual Address: 0x3A -; REL32-NEXT: Symbol: global_int_nonzero (21) +; REL32-NEXT: Symbol: global_int_nonzero ([[#NFA+21]]) ; REL32-NEXT: IsSigned: No ; REL32-NEXT: FixupBitValue: 0 ; REL32-NEXT: Length: 16 ; REL32-NEXT: Type: R_TOC (0x3) ; REL32-NEXT: } ; REL32: Virtual Address: 0x40 -; REL32-NEXT: Symbol: .__get_tpointer (1) +; REL32-NEXT: Symbol: .__get_tpointer ([[#NFA+1]]) ; REL32-NEXT: IsSigned: No ; REL32-NEXT: FixupBitValue: 0 ; REL32-NEXT: Length: 26 ; REL32-NEXT: Type: R_RBA (0x18) ; REL32-NEXT: } ; REL32: Virtual Address: 0x6A -; REL32-NEXT: Symbol: intern_int_zero (19) +; REL32-NEXT: Symbol: intern_int_zero ([[#NFA+19]]) ; REL32-NEXT: IsSigned: No ; REL32-NEXT: FixupBitValue: 0 ; REL32-NEXT: Length: 16 ; REL32-NEXT: Type: R_TOC (0x3) ; REL32-NEXT: } ; REL32: Virtual Address: 0x70 -; REL32-NEXT: Symbol: .__get_tpointer (1) +; REL32-NEXT: Symbol: .__get_tpointer ([[#NFA+1]]) ; REL32-NEXT: IsSigned: No ; REL32-NEXT: FixupBitValue: 0 ; REL32-NEXT: Length: 26 ; REL32-NEXT: Type: R_RBA (0x18) ; REL32-NEXT: } ; REL32: Virtual Address: 0xAC -; REL32-NEXT: Symbol: intern_int_zero (27) +; REL32-NEXT: Symbol: intern_int_zero ([[#NFA+27]]) ; REL32-NEXT: IsSigned: No ; REL32-NEXT: FixupBitValue: 0 ; REL32-NEXT: Length: 32 ; REL32-NEXT: Type: R_TLS_IE (0x21) ; REL32-NEXT: } ; REL32: Virtual Address: 0xB0 -; REL32-NEXT: Symbol: global_int_nonzero (25) +; REL32-NEXT: Symbol: global_int_nonzero ([[#NFA+25]]) ; REL32-NEXT: IsSigned: No ; REL32-NEXT: FixupBitValue: 0 ; REL32-NEXT: Length: 32 ; REL32-NEXT: Type: R_TLS_IE (0x21) ; REL32-NEXT: } -; SYM32: File: {{.*}}aix-tls-ie-xcoff-reloc.ll.tmp.o +; SYM32: File: ; SYM32-NEXT: Format: aixcoff-rs6000 ; SYM32-NEXT: Arch: powerpc ; SYM32-NEXT: AddressSize: 32bit ; SYM32-NEXT: Symbols [ -; SYM32: Index: 19 -; SYM32-NEXT: Name: intern_int_zero +; SYM32: Name: intern_int_zero ; SYM32-NEXT: Value (RelocatableAddress): 0xAC ; SYM32-NEXT: Section: .data ; SYM32-NEXT: Type: 0x0 ; SYM32-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM32-NEXT: NumberOfAuxEntries: 1 ; SYM32-NEXT: CSECT Auxiliary Entry { -; SYM32-NEXT: Index: 20 +; SYM32-NEXT: Index: [[#INDX:]] ; SYM32-NEXT: SectionLen: 4 ; SYM32-NEXT: ParameterHashIndex: 0x0 ; SYM32-NEXT: TypeChkSectNum: 0x0 @@ -292,7 +290,7 @@ declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) ; SYM32-NEXT: StabSectNum: 0x0 ; SYM32-NEXT: } ; SYM32-NEXT: } -; SYM32: Index: 21 +; SYM32: Index: [[#INDX+1]] ; SYM32-NEXT: Name: global_int_nonzero ; SYM32-NEXT: Value (RelocatableAddress): 0xB0 ; SYM32-NEXT: Section: .data @@ -300,7 +298,7 @@ declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) ; SYM32-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM32-NEXT: NumberOfAuxEntries: 1 ; SYM32-NEXT: CSECT Auxiliary Entry { -; SYM32-NEXT: Index: 22 +; SYM32-NEXT: Index: [[#INDX+2]] ; SYM32-NEXT: SectionLen: 4 ; SYM32-NEXT: ParameterHashIndex: 0x0 ; SYM32-NEXT: TypeChkSectNum: 0x0 @@ -311,7 +309,7 @@ declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) ; SYM32-NEXT: StabSectNum: 0x0 ; SYM32-NEXT: } ; SYM32-NEXT: } -; SYM32: Index: 25 +; SYM32: Index: [[#INDX+5]] ; SYM32-NEXT: Name: global_int_nonzero ; SYM32-NEXT: Value (RelocatableAddress): 0x0 ; SYM32-NEXT: Section: .tdata @@ -319,8 +317,8 @@ declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) ; SYM32-NEXT: StorageClass: C_EXT (0x2) ; SYM32-NEXT: NumberOfAuxEntries: 1 ; SYM32-NEXT: CSECT Auxiliary Entry { -; SYM32-NEXT: Index: 26 -; SYM32-NEXT: ContainingCsectSymbolIndex: 23 +; SYM32-NEXT: Index: [[#INDX+6]] +; SYM32-NEXT: ContainingCsectSymbolIndex: [[#INDX+3]] ; SYM32-NEXT: ParameterHashIndex: 0x0 ; SYM32-NEXT: TypeChkSectNum: 0x0 ; SYM32-NEXT: SymbolAlignmentLog2: 0 @@ -330,7 +328,7 @@ declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) ; SYM32-NEXT: StabSectNum: 0x0 ; SYM32-NEXT: } ; SYM32-NEXT: } -; SYM32: Index: 27 +; SYM32: Index: [[#INDX+7]] ; SYM32-NEXT: Name: intern_int_zero ; SYM32-NEXT: Value (RelocatableAddress): 0x4 ; SYM32-NEXT: Section: .tbss @@ -338,7 +336,7 @@ declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) ; SYM32-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM32-NEXT: NumberOfAuxEntries: 1 ; SYM32-NEXT: CSECT Auxiliary Entry { -; SYM32-NEXT: Index: 28 +; SYM32-NEXT: Index: [[#INDX+8]] ; SYM32-NEXT: SectionLen: 4 ; SYM32-NEXT: ParameterHashIndex: 0x0 ; SYM32-NEXT: TypeChkSectNum: 0x0 @@ -350,38 +348,38 @@ declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) ; SYM32-NEXT: } ; SYM32-NEXT: } -; DIS32: {{.*}}aix-tls-ie-xcoff-reloc.ll.tmp.o: file format aixcoff-rs6000 +; DIS32: file format aixcoff-rs6000 ; DIS32: Disassembly of section .text: -; DIS32: (idx: 5) .store_intern_int_zero: -; DIS32: R_TOC (idx: 19) intern_int_zero[TC] -; DIS32: R_RBA (idx: 1) .__get_tpointer[PR] +; DIS32: (idx: [[#NFA+5]]) .store_intern_int_zero: +; DIS32: R_TOC (idx: [[#NFA+19]]) intern_int_zero[TC] +; DIS32: R_RBA (idx: [[#NFA+1]]) .__get_tpointer[PR] ; DIS32: blr -; DIS32: (idx: 7) .load_global_int_nonzero: -; DIS32: R_TOC (idx: 21) global_int_nonzero[TC] -; DIS32: R_RBA (idx: 1) .__get_tpointer[PR] +; DIS32: (idx: [[#NFA+7]]) .load_global_int_nonzero: +; DIS32: R_TOC (idx: [[#NFA+21]]) global_int_nonzero[TC] +; DIS32: R_RBA (idx: [[#NFA+1]]) .__get_tpointer[PR] ; DIS32: blr -; DIS32: (idx: 9) .load_intern_int_zero: -; DIS32: R_TOC (idx: 19) intern_int_zero[TC] -; DIS32: R_RBA (idx: 1) .__get_tpointer[PR] +; DIS32: (idx: [[#NFA+9]]) .load_intern_int_zero: +; DIS32: R_TOC (idx: [[#NFA+19]]) intern_int_zero[TC] +; DIS32: R_RBA (idx: [[#NFA+1]]) .__get_tpointer[PR] ; DIS32: blr ; DIS32: Disassembly of section .data: -; DIS32: (idx: 11) store_intern_int_zero[DS]: -; DIS32: R_POS (idx: 5) .store_intern_int_zero -; DIS32: R_POS (idx: 17) TOC[TC0] -; DIS32: (idx: 13) load_global_int_nonzero[DS]: -; DIS32: R_POS (idx: 7) .load_global_int_nonzero -; DIS32: R_POS (idx: 17) TOC[TC0] -; DIS32: (idx: 15) load_intern_int_zero[DS]: -; DIS32: R_POS (idx: 9) .load_intern_int_zero -; DIS32: R_POS (idx: 17) TOC[TC0] -; DIS32: (idx: 19) intern_int_zero[TC]: -; DIS32: R_TLS_IE (idx: 27) intern_int_zero[UL] -; DIS32: (idx: 21) global_int_nonzero[TC]: -; DIS32: R_TLS_IE (idx: 25) global_int_nonzero +; DIS32: (idx: [[#NFA+11]]) store_intern_int_zero[DS]: +; DIS32: R_POS (idx: [[#NFA+5]]) .store_intern_int_zero +; DIS32: R_POS (idx: [[#NFA+17]]) TOC[TC0] +; DIS32: (idx: [[#NFA+13]]) load_global_int_nonzero[DS]: +; DIS32: R_POS (idx: [[#NFA+7]]) .load_global_int_nonzero +; DIS32: R_POS (idx: [[#NFA+17]]) TOC[TC0] +; DIS32: (idx: [[#NFA+15]]) load_intern_int_zero[DS]: +; DIS32: R_POS (idx: [[#NFA+9]]) .load_intern_int_zero +; DIS32: R_POS (idx: [[#NFA+17]]) TOC[TC0] +; DIS32: (idx: [[#NFA+19]]) intern_int_zero[TC]: +; DIS32: R_TLS_IE (idx: [[#NFA+27]]) intern_int_zero[UL] +; DIS32: (idx: [[#NFA+21]]) global_int_nonzero[TC]: +; DIS32: R_TLS_IE (idx: [[#NFA+25]]) global_int_nonzero ; DIS32: Disassembly of section .tdata: -; DIS32: (idx: 25) global_int_nonzero: +; DIS32: (idx: [[#NFA+25]]) global_int_nonzero: ; DIS32: Disassembly of section .tbss: -; DIS32: (idx: 27) intern_int_zero[UL]: +; DIS32: (idx: [[#NFA+27]]) intern_int_zero[UL]: diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large.ll b/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large.ll index 5283e24c060c..83296de036d0 100644 --- a/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large.ll +++ b/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large.ll @@ -1,8 +1,8 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ ; RUN: -xcoff-traceback-table=false --code-model=large -filetype=obj -o %t.o < %s -; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefix=RELOC %s -; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM %s -; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s +; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck -D#NFA=2 --check-prefix=RELOC %s +; RUN: llvm-readobj --syms %t.o | FileCheck -D#NFA=2 --check-prefix=SYM %s +; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=DIS %s @ThreadLocalVarInit = thread_local(localexec) global i64 1, align 8 @VarInit = global i64 87, align 8 @@ -36,81 +36,81 @@ entry: ret i64 %add } -; RELOC: File: {{.*}}aix-tls-le-xcoff-reloc-large.ll.tmp.o +; RELOC: File: ; RELOC-NEXT: Format: aix5coff64-rs6000 ; RELOC-NEXT: Arch: powerpc64 ; RELOC-NEXT: AddressSize: 64bit ; RELOC-NEXT: Relocations [ ; RELOC: Virtual Address: 0x2 -; RELOC-NEXT: Symbol: IThreadLocalVarUninit (19) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit ([[#NFA+19]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOCU (0x30) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x6 -; RELOC-NEXT: Symbol: IThreadLocalVarUninit (19) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit ([[#NFA+19]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOCL (0x31) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x12 -; RELOC-NEXT: Symbol: ThreadLocalVarInit (21) +; RELOC-NEXT: Symbol: ThreadLocalVarInit ([[#NFA+21]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOCU (0x30) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x1A -; RELOC-NEXT: Symbol: ThreadLocalVarInit (21) +; RELOC-NEXT: Symbol: ThreadLocalVarInit ([[#NFA+21]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOCL (0x31) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x42 -; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 (25) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 ([[#NFA+25]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOCU (0x30) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x46 -; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 (25) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 ([[#NFA+25]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOCL (0x31) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0xA8 -; RELOC-NEXT: Symbol: IThreadLocalVarUninit (29) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit ([[#NFA+29]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 64 ; RELOC-NEXT: Type: R_TLS_LE (0x23) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0xB0 -; RELOC-NEXT: Symbol: ThreadLocalVarInit (27) +; RELOC-NEXT: Symbol: ThreadLocalVarInit ([[#NFA+27]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 64 ; RELOC-NEXT: Type: R_TLS_LE (0x23) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0xC0 -; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 (31) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 ([[#NFA+31]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 64 ; RELOC-NEXT: Type: R_TLS_LE (0x23) ; RELOC-NEXT: } -; SYM: File: {{.*}}aix-tls-le-xcoff-reloc-large.ll.tmp.o +; SYM: File: ; SYM-NEXT: Format: aix5coff64-rs6000 ; SYM-NEXT: Arch: powerpc64 ; SYM-NEXT: AddressSize: 64bit ; SYM-NEXT: Symbols [ -; SYM: Index: 19 +; SYM: Index: [[#NFA+19]] ; SYM-NEXT: Name: IThreadLocalVarUninit ; SYM-NEXT: Value (RelocatableAddress): 0xA8 ; SYM-NEXT: Section: .data @@ -118,7 +118,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 20 +; SYM-NEXT: Index: [[#NFA+20]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -128,7 +128,7 @@ entry: ; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB) ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 21 +; SYM: Index: [[#NFA+21]] ; SYM-NEXT: Name: ThreadLocalVarInit ; SYM-NEXT: Value (RelocatableAddress): 0xB0 ; SYM-NEXT: Section: .data @@ -136,7 +136,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 22 +; SYM-NEXT: Index: [[#NFA+22]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -145,7 +145,7 @@ entry: ; SYM-NEXT: StorageMappingClass: XMC_TE (0x16) ; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB) ; SYM-NEXT: } -; SYM: Index: 25 +; SYM: Index: [[#NFA+25]] ; SYM-NEXT: Name: IThreadLocalVarUninit2 ; SYM-NEXT: Value (RelocatableAddress): 0xC0 ; SYM-NEXT: Section: .data @@ -153,7 +153,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 26 +; SYM-NEXT: Index: [[#NFA+26]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -163,7 +163,7 @@ entry: ; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB) ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 27 +; SYM: Index: [[#NFA+27]] ; SYM-NEXT: Name: ThreadLocalVarInit ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: .tdata @@ -171,7 +171,7 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 28 +; SYM-NEXT: Index: [[#NFA+28]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -181,7 +181,7 @@ entry: ; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB) ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 29 +; SYM: Index: [[#NFA+29]] ; SYM-NEXT: Name: IThreadLocalVarUninit ; SYM-NEXT: Value (RelocatableAddress): 0x8 ; SYM-NEXT: Section: .tbss @@ -189,7 +189,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 30 +; SYM-NEXT: Index: [[#NFA+30]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -199,7 +199,7 @@ entry: ; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB) ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 31 +; SYM: Index: [[#NFA+31]] ; SYM-NEXT: Name: IThreadLocalVarUninit2 ; SYM-NEXT: Value (RelocatableAddress): 0x10 ; SYM-NEXT: Section: .tbss @@ -207,7 +207,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 32 +; SYM-NEXT: Index: [[#NFA+32]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -218,93 +218,93 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } -; DIS: {{.*}}aix-tls-le-xcoff-reloc-large.ll.tmp.o: file format aix5coff64-rs6000 +; DIS: file format aix5coff64-rs6000 ; DIS: Disassembly of section .text: -; DIS: 0000000000000000 (idx: 3) .storeITLUninit: +; DIS: 0000000000000000 (idx: [[#NFA+3]]) .storeITLUninit: ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 4, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 19) IThreadLocalVarUninit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+19]]) IThreadLocalVarUninit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 4, 0(4) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 19) IThreadLocalVarUninit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+19]]) IThreadLocalVarUninit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stdx 3, 13, 4 ; DIS-NEXT: blr -; DIS: 0000000000000010 (idx: 5) .loadTLInit: +; DIS: 0000000000000010 (idx: [[#NFA+5]]) .loadTLInit: ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 21) ThreadLocalVarInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+21]]) ThreadLocalVarInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 4, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 23) VarInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+23]]) VarInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 3, 8(3) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 21) ThreadLocalVarInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+21]]) ThreadLocalVarInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 4, 16(4) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 23) VarInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+23]]) VarInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ldx 3, 13, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 4, 0(4) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} add 3, 4, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} blr -; DIS: 0000000000000030 (idx: 7) .loadTLUninit: +; DIS: 0000000000000030 (idx: [[#NFA+7]]) .loadTLUninit: ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 19) IThreadLocalVarUninit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+19]]) IThreadLocalVarUninit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 4, 1 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 3, 0(3) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 19) IThreadLocalVarUninit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+19]]) IThreadLocalVarUninit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stdx 4, 13, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 25) IThreadLocalVarUninit2[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+25]]) IThreadLocalVarUninit2[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 3, 24(3) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 25) IThreadLocalVarUninit2[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+25]]) IThreadLocalVarUninit2[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ldx 3, 13, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addi 3, 3, 1 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} blr ; DIS: Disassembly of section .data: -; DIS: 0000000000000058 (idx: 9) VarInit[RW]: +; DIS: 0000000000000058 (idx: [[#NFA+9]]) VarInit[RW]: ; DIS-NEXT: 58: 00 00 00 00 ; DIS-NEXT: 5c: 00 00 00 57 -; DIS: 0000000000000060 (idx: 11) storeITLUninit[DS]: +; DIS: 0000000000000060 (idx: [[#NFA+11]]) storeITLUninit[DS]: ; DIS-NEXT: 60: 00 00 00 00 -; DIS-NEXT: 0000000000000060: R_POS (idx: 3) .storeITLUninit +; DIS-NEXT: 0000000000000060: R_POS (idx: [[#NFA+3]]) .storeITLUninit ; DIS-NEXT: 64: 00 00 00 00 ; DIS-NEXT: 68: 00 00 00 00 -; DIS-NEXT: 0000000000000068: R_POS (idx: 17) TOC[TC0] +; DIS-NEXT: 0000000000000068: R_POS (idx: [[#NFA+17]]) TOC[TC0] ; DIS-NEXT: 6c: 00 00 00 a8 -; DIS: 0000000000000078 (idx: 13) loadTLInit[DS]: +; DIS: 0000000000000078 (idx: [[#NFA+13]]) loadTLInit[DS]: ; DIS-NEXT: 78: 00 00 00 00 -; DIS-NEXT: 0000000000000078: R_POS (idx: 5) .loadTLInit +; DIS-NEXT: 0000000000000078: R_POS (idx: [[#NFA+5]]) .loadTLInit ; DIS-NEXT: 7c: 00 00 00 10 ; DIS-NEXT: 80: 00 00 00 00 -; DIS-NEXT: 0000000000000080: R_POS (idx: 17) TOC[TC0] +; DIS-NEXT: 0000000000000080: R_POS (idx: [[#NFA+17]]) TOC[TC0] ; DIS-NEXT: 84: 00 00 00 a8 -; DIS: 0000000000000090 (idx: 15) loadTLUninit[DS]: +; DIS: 0000000000000090 (idx: [[#NFA+15]]) loadTLUninit[DS]: ; DIS-NEXT: 90: 00 00 00 00 -; DIS-NEXT: 0000000000000090: R_POS (idx: 7) .loadTLUninit +; DIS-NEXT: 0000000000000090: R_POS (idx: [[#NFA+7]]) .loadTLUninit ; DIS-NEXT: 94: 00 00 00 30 ; DIS-NEXT: 98: 00 00 00 00 -; DIS-NEXT: 0000000000000098: R_POS (idx: 17) TOC[TC0] +; DIS-NEXT: 0000000000000098: R_POS (idx: [[#NFA+17]]) TOC[TC0] ; DIS-NEXT: 9c: 00 00 00 a8 -; DIS: 00000000000000a8 (idx: 19) IThreadLocalVarUninit[TE]: +; DIS: 00000000000000a8 (idx: [[#NFA+19]]) IThreadLocalVarUninit[TE]: ; DIS-NEXT: a8: 00 00 00 00 -; DIS-NEXT: 00000000000000a8: R_TLS_LE (idx: 29) IThreadLocalVarUninit[UL] +; DIS-NEXT: 00000000000000a8: R_TLS_LE (idx: [[#NFA+29]]) IThreadLocalVarUninit[UL] ; DIS-NEXT: ac: 00 00 00 08 -; DIS: 00000000000000b0 (idx: 21) ThreadLocalVarInit[TE]: +; DIS: 00000000000000b0 (idx: [[#NFA+21]]) ThreadLocalVarInit[TE]: ; DIS-NEXT: b0: 00 00 00 00 -; DIS-NEXT: 00000000000000b0: R_TLS_LE (idx: 27) ThreadLocalVarInit[TL] +; DIS-NEXT: 00000000000000b0: R_TLS_LE (idx: [[#NFA+27]]) ThreadLocalVarInit[TL] ; DIS-NEXT: b4: 00 00 00 00 -; DIS: 00000000000000b8 (idx: 23) VarInit[TE]: +; DIS: 00000000000000b8 (idx: [[#NFA+23]]) VarInit[TE]: ; DIS-NEXT: b8: 00 00 00 00 -; DIS-NEXT: 00000000000000b8: R_POS (idx: 9) VarInit[RW] +; DIS-NEXT: 00000000000000b8: R_POS (idx: [[#NFA+9]]) VarInit[RW] ; DIS-NEXT: bc: 00 00 00 58 -; DIS: 00000000000000c0 (idx: 25) IThreadLocalVarUninit2[TE]: +; DIS: 00000000000000c0 (idx: [[#NFA+25]]) IThreadLocalVarUninit2[TE]: ; DIS-NEXT: c0: 00 00 00 00 -; DIS-NEXT: 00000000000000c0: R_TLS_LE (idx: 31) IThreadLocalVarUninit2[UL] +; DIS-NEXT: 00000000000000c0: R_TLS_LE (idx: [[#NFA+31]]) IThreadLocalVarUninit2[UL] ; DIS-NEXT: c4: 00 00 00 10 ; DIS: Disassembly of section .tdata: -; DIS: 0000000000000000 (idx: 27) ThreadLocalVarInit[TL]: +; DIS: 0000000000000000 (idx: [[#NFA+27]]) ThreadLocalVarInit[TL]: ; DIS-NEXT: 0: 00 00 00 00 ; DIS-NEXT: 4: 00 00 00 01 ; DIS: Disassembly of section .tbss: -; DIS: 0000000000000008 (idx: 29) IThreadLocalVarUninit[UL]: +; DIS: 0000000000000008 (idx: [[#NFA+29]]) IThreadLocalVarUninit[UL]: ; DIS-NEXT: ... -; DIS: 0000000000000010 (idx: 31) IThreadLocalVarUninit2[UL]: +; DIS: 0000000000000010 (idx: [[#NFA+31]]) IThreadLocalVarUninit2[UL]: ; DIS-NEXT: ... diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large32.ll b/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large32.ll index 9897fc89b423..3b754e362f12 100644 --- a/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large32.ll +++ b/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large32.ll @@ -1,8 +1,8 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -xcoff-traceback-table=false --code-model=large -filetype=obj -o %t.o < %s -; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefix=RELOC %s -; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM %s -; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s +; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck -D#NFA=2 --check-prefix=RELOC %s +; RUN: llvm-readobj --syms %t.o | FileCheck -D#NFA=2 --check-prefix=SYM %s +; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=DIS %s @ThreadLocalVarInit = thread_local(localexec) global i64 1, align 8 @VarInit = global i64 87, align 8 @@ -36,69 +36,69 @@ entry: ret i64 %add } -; RELOC: File: {{.*}}aix-tls-le-xcoff-reloc-large32.ll.tmp.o +; RELOC: File: ; RELOC-NEXT: Format: aixcoff-rs6000 ; RELOC-NEXT: Arch: powerpc ; RELOC-NEXT: AddressSize: 32bit ; RELOC-NEXT: Relocations [ ; RELOC: Virtual Address: 0x12 -; RELOC-NEXT: Symbol: IThreadLocalVarUninit (21) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit ([[#NFA+21]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOCU (0x30) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x16 -; RELOC-NEXT: Symbol: IThreadLocalVarUninit (21) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit ([[#NFA+21]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOCL (0x31) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x18 -; RELOC-NEXT: Symbol: .__get_tpointer (1) +; RELOC-NEXT: Symbol: .__get_tpointer ([[#NFA+1]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 26 ; RELOC-NEXT: Type: R_RBA (0x18) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x4E -; RELOC-NEXT: Symbol: ThreadLocalVarInit (23) +; RELOC-NEXT: Symbol: ThreadLocalVarInit ([[#NFA+23]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOCU (0x30) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x52 -; RELOC-NEXT: Symbol: ThreadLocalVarInit (23) +; RELOC-NEXT: Symbol: ThreadLocalVarInit ([[#NFA+23]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOCL (0x31) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x54 -; RELOC-NEXT: Symbol: .__get_tpointer (1) +; RELOC-NEXT: Symbol: .__get_tpointer ([[#NFA+1]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 26 ; RELOC-NEXT: Type: R_RBA (0x18) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0xBE -; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 (27) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 ([[#NFA+27]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOCU (0x30) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0xC2 -; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 (27) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 ([[#NFA+27]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOCL (0x31) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x114 -; RELOC-NEXT: Symbol: IThreadLocalVarUninit (31) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit ([[#NFA+31]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -106,26 +106,26 @@ entry: ; RELOC-NEXT: } ; RELOC: Relocation { ; RELOC-NEXT: Virtual Address: 0x118 -; RELOC-NEXT: Symbol: ThreadLocalVarInit (29) +; RELOC-NEXT: Symbol: ThreadLocalVarInit ([[#NFA+29]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 ; RELOC-NEXT: Type: R_TLS_LE (0x23) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x120 -; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 (33) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 ([[#NFA+33]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 ; RELOC-NEXT: Type: R_TLS_LE (0x23) ; RELOC-NEXT: } -; SYM: File: {{.*}}aix-tls-le-xcoff-reloc-large32.ll.tmp.o +; SYM: File: ; SYM-NEXT: Format: aixcoff-rs6000 ; SYM-NEXT: Arch: powerpc ; SYM-NEXT: AddressSize: 32bit ; SYM-NEXT: Symbols [ -; SYM: Index: 1 +; SYM: Index: [[#NFA+1]] ; SYM-NEXT: Name: .__get_tpointer ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: N_UNDEF @@ -133,7 +133,7 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 2 +; SYM-NEXT: Index: [[#NFA+2]] ; SYM-NEXT: SectionLen: 0 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -144,7 +144,7 @@ entry: ; SYM-NEXT: StabSectNum: 0x0 ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 21 +; SYM: Index: [[#NFA+21]] ; SYM-NEXT: Name: IThreadLocalVarUninit ; SYM-NEXT: Value (RelocatableAddress): 0x114 ; SYM-NEXT: Section: .data @@ -152,7 +152,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 22 +; SYM-NEXT: Index: [[#NFA+22]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -163,7 +163,7 @@ entry: ; SYM-NEXT: StabSectNum: 0x0 ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 23 +; SYM: Index: [[#NFA+23]] ; SYM-NEXT: Name: ThreadLocalVarInit ; SYM-NEXT: Value (RelocatableAddress): 0x118 ; SYM-NEXT: Section: .data @@ -171,7 +171,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 24 +; SYM-NEXT: Index: [[#NFA+24]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -182,7 +182,7 @@ entry: ; SYM-NEXT: StabSectNum: 0x0 ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 27 +; SYM: Index: [[#NFA+27]] ; SYM-NEXT: Name: IThreadLocalVarUninit2 ; SYM-NEXT: Value (RelocatableAddress): 0x120 ; SYM-NEXT: Section: .data @@ -190,7 +190,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 28 +; SYM-NEXT: Index: [[#NFA+28]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -201,7 +201,7 @@ entry: ; SYM-NEXT: StabSectNum: 0x0 ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 29 +; SYM: Index: [[#NFA+29]] ; SYM-NEXT: Name: ThreadLocalVarInit ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: .tdata @@ -209,7 +209,7 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 30 +; SYM-NEXT: Index: [[#NFA+30]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -220,7 +220,7 @@ entry: ; SYM-NEXT: StabSectNum: 0x0 ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 31 +; SYM: Index: [[#NFA+31]] ; SYM-NEXT: Name: IThreadLocalVarUninit ; SYM-NEXT: Value (RelocatableAddress): 0x8 ; SYM-NEXT: Section: .tbss @@ -228,7 +228,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 32 +; SYM-NEXT: Index: [[#NFA+32]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -239,7 +239,7 @@ entry: ; SYM-NEXT: StabSectNum: 0x0 ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 33 +; SYM: Index: [[#NFA+33]] ; SYM-NEXT: Name: IThreadLocalVarUninit2 ; SYM-NEXT: Value (RelocatableAddress): 0x10 ; SYM-NEXT: Section: .tbss @@ -247,7 +247,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 34 +; SYM-NEXT: Index: [[#NFA+34]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -259,19 +259,19 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } -; DIS: {{.*}}aix-tls-le-xcoff-reloc-large32.ll.tmp.o: file format aixcoff-rs6000 +; DIS: file format aixcoff-rs6000 ; DIS: Disassembly of section .text: -; DIS: 00000000 (idx: 5) .storeITLUninit: +; DIS: 00000000 (idx: [[#NFA+5]]) .storeITLUninit: ; DIS-NEXT: mflr 0 ; DIS-NEXT: stwu 1, -32(1) ; DIS-NEXT: stw 0, 40(1) ; DIS-NEXT: mr 5, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 21) IThreadLocalVarUninit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+21]]) IThreadLocalVarUninit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 6, 0(3) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 21) IThreadLocalVarUninit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+21]]) IThreadLocalVarUninit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0 -; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: 1) .__get_tpointer[PR] +; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: [[#NFA+1]]) .__get_tpointer[PR] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} add 3, 3, 6 ; DIS-NEXT: stw 4, 4(3) ; DIS-NEXT: stw 5, 0(3) @@ -279,23 +279,23 @@ entry: ; DIS-NEXT: lwz 0, 8(1) ; DIS-NEXT: mtlr 0 ; DIS-NEXT: blr -; DIS: 00000040 (idx: 7) .loadTLInit: +; DIS: 00000040 (idx: [[#NFA+7]]) .loadTLInit: ; DIS-NEXT: mflr 0 ; DIS-NEXT: stwu 1, -32(1) ; DIS-NEXT: stw 0, 40(1) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 23) ThreadLocalVarInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+23]]) ThreadLocalVarInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 4(3) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 23) ThreadLocalVarInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+23]]) ThreadLocalVarInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0 -; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: 1) .__get_tpointer[PR] +; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: [[#NFA+1]]) .__get_tpointer[PR] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} add 3, 3, 4 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 4(3) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 3, 0(3) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 5, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 25) VarInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+25]]) VarInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 5, 8(5) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 25) VarInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+25]]) VarInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 6, 4(5) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 5, 0(5) ; DIS-NEXT: addc 4, 6, 4 @@ -304,25 +304,25 @@ entry: ; DIS-NEXT: lwz 0, 8(1) ; DIS-NEXT: mtlr 0 ; DIS-NEXT: blr -; DIS: 00000090 (idx: 9) .loadTLUninit: +; DIS: 00000090 (idx: [[#NFA+9]]) .loadTLUninit: ; DIS-NEXT: mflr 0 ; DIS-NEXT: stwu 1, -32(1) ; DIS-NEXT: stw 0, 40(1) ; DIS-NEXT: li 5, 1 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 21) IThreadLocalVarUninit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+21]]) IThreadLocalVarUninit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 0(3) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 21) IThreadLocalVarUninit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+21]]) IThreadLocalVarUninit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0 -; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: 1) .__get_tpointer[PR] +; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: [[#NFA+1]]) .__get_tpointer[PR] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} add 4, 3, 4 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stw 5, 4(4) ; DIS-NEXT: li 5, 0 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stw 5, 0(4) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 4, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 27) IThreadLocalVarUninit2[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+27]]) IThreadLocalVarUninit2[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 12(4) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 27) IThreadLocalVarUninit2[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+27]]) IThreadLocalVarUninit2[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} add 3, 3, 4 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 4(3) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 3, 0(3) @@ -334,48 +334,48 @@ entry: ; DIS-NEXT: blr ; DIS: Disassembly of section .data: -; DIS: 000000e8 (idx: 11) VarInit[RW]: +; DIS: 000000e8 (idx: [[#NFA+11]]) VarInit[RW]: ; DIS-NEXT: e8: 00 00 00 00 ; DIS-NEXT: ec: 00 00 00 57 -; DIS: 000000f0 (idx: 13) storeITLUninit[DS]: +; DIS: 000000f0 (idx: [[#NFA+13]]) storeITLUninit[DS]: ; DIS-NEXT: f0: 00 00 00 00 -; DIS-NEXT: 000000f0: R_POS (idx: 5) .storeITLUninit +; DIS-NEXT: 000000f0: R_POS (idx: [[#NFA+5]]) .storeITLUninit ; DIS-NEXT: f4: 00 00 01 14 -; DIS-NEXT: 000000f4: R_POS (idx: 19) TOC[TC0] +; DIS-NEXT: 000000f4: R_POS (idx: [[#NFA+19]]) TOC[TC0] ; DIS-NEXT: f8: 00 00 00 00 -; DIS: 000000fc (idx: 15) loadTLInit[DS]: +; DIS: 000000fc (idx: [[#NFA+15]]) loadTLInit[DS]: ; DIS-NEXT: fc: 00 00 00 40 -; DIS-NEXT: 000000fc: R_POS (idx: 7) .loadTLInit +; DIS-NEXT: 000000fc: R_POS (idx: [[#NFA+7]]) .loadTLInit ; DIS-NEXT: 100: 00 00 01 14 -; DIS-NEXT: 00000100: R_POS (idx: 19) TOC[TC0] +; DIS-NEXT: 00000100: R_POS (idx: [[#NFA+19]]) TOC[TC0] ; DIS-NEXT: 104: 00 00 00 00 -; DIS: 00000108 (idx: 17) loadTLUninit[DS]: +; DIS: 00000108 (idx: [[#NFA+17]]) loadTLUninit[DS]: ; DIS-NEXT: 108: 00 00 00 90 -; DIS-NEXT: 00000108: R_POS (idx: 9) .loadTLUninit +; DIS-NEXT: 00000108: R_POS (idx: [[#NFA+9]]) .loadTLUninit ; DIS-NEXT: 10c: 00 00 01 14 -; DIS-NEXT: 0000010c: R_POS (idx: 19) TOC[TC0] +; DIS-NEXT: 0000010c: R_POS (idx: [[#NFA+19]]) TOC[TC0] ; DIS-NEXT: 110: 00 00 00 00 -; DIS: 00000114 (idx: 21) IThreadLocalVarUninit[TE]: +; DIS: 00000114 (idx: [[#NFA+21]]) IThreadLocalVarUninit[TE]: ; DIS-NEXT: 114: 00 00 00 08 -; DIS-NEXT: 00000114: R_TLS_LE (idx: 31) IThreadLocalVarUninit[UL] -; DIS: 00000118 (idx: 23) ThreadLocalVarInit[TE]: +; DIS-NEXT: 00000114: R_TLS_LE (idx: [[#NFA+31]]) IThreadLocalVarUninit[UL] +; DIS: 00000118 (idx: [[#NFA+23]]) ThreadLocalVarInit[TE]: ; DIS-NEXT: 118: 00 00 00 00 -; DIS-NEXT: 00000118: R_TLS_LE (idx: 29) ThreadLocalVarInit[TL] -; DIS: 0000011c (idx: 25) VarInit[TE]: +; DIS-NEXT: 00000118: R_TLS_LE (idx: [[#NFA+29]]) ThreadLocalVarInit[TL] +; DIS: 0000011c (idx: [[#NFA+25]]) VarInit[TE]: ; DIS-NEXT: 11c: 00 00 00 e8 -; DIS-NEXT: 0000011c: R_POS (idx: 11) VarInit[RW] -; DIS: 00000120 (idx: 27) IThreadLocalVarUninit2[TE]: +; DIS-NEXT: 0000011c: R_POS (idx: [[#NFA+11]]) VarInit[RW] +; DIS: 00000120 (idx: [[#NFA+27]]) IThreadLocalVarUninit2[TE]: ; DIS-NEXT: 120: 00 00 00 10 -; DIS-NEXT: 00000120: R_TLS_LE (idx: 33) IThreadLocalVarUninit2[UL] +; DIS-NEXT: 00000120: R_TLS_LE (idx: [[#NFA+33]]) IThreadLocalVarUninit2[UL] ; DIS: Disassembly of section .tdata: -; DIS: 00000000 (idx: 29) ThreadLocalVarInit[TL]: +; DIS: 00000000 (idx: [[#NFA+29]]) ThreadLocalVarInit[TL]: ; DIS-NEXT: 0: 00 00 00 00 ; DIS-NEXT: 4: 00 00 00 01 ; DIS: Disassembly of section .tbss: -; DIS: 00000008 (idx: 31) IThreadLocalVarUninit[UL]: +; DIS: 00000008 (idx: [[#NFA+31]]) IThreadLocalVarUninit[UL]: ; DIS-NEXT: ... -; DIS: 00000010 (idx: 33) IThreadLocalVarUninit2[UL]: +; DIS: 00000010 (idx: [[#NFA+33]]) IThreadLocalVarUninit2[UL]: ; DIS-NEXT: ... diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc.ll b/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc.ll index d469a8690110..c67c79e3ab7b 100644 --- a/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc.ll +++ b/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc.ll @@ -1,8 +1,8 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ ; RUN: -xcoff-traceback-table=false -data-sections=false -filetype=obj -o %t.o < %s -; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefix=RELOC %s -; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM %s -; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s +; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck -D#NFA=2 --check-prefix=RELOC %s +; RUN: llvm-readobj --syms %t.o | FileCheck -D#NFA=2 --check-prefix=SYM %s +; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=DIS %s @ThreadLocalVarInit = thread_local(localexec) global i32 1, align 4 @VarInit = global i32 87, align 4 @@ -36,60 +36,60 @@ entry: ret i32 %add } -; RELOC: File: {{.*}}aix-tls-le-xcoff-reloc.ll.tmp.o +; RELOC: File: ; RELOC-NEXT: Format: aix5coff64-rs6000 ; RELOC-NEXT: Arch: powerpc64 ; RELOC-NEXT: AddressSize: 64bit ; RELOC-NEXT: Relocations [ ; RELOC: Virtual Address: 0x2 -; RELOC-NEXT: Symbol: IThreadLocalVarUninit (21) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit ([[#NFA+21]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOC (0x3) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x12 -; RELOC-NEXT: Symbol: ThreadLocalVarInit (23) +; RELOC-NEXT: Symbol: ThreadLocalVarInit ([[#NFA+23]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOC (0x3) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x3E -; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 (27) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 ([[#NFA+27]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOC (0x3) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0xA0 -; RELOC-NEXT: Symbol: IThreadLocalVarUninit (33) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit ([[#NFA+33]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 64 ; RELOC-NEXT: Type: R_TLS_LE (0x23) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0xA8 -; RELOC-NEXT: Symbol: ThreadLocalVarInit (31) +; RELOC-NEXT: Symbol: ThreadLocalVarInit ([[#NFA+31]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 64 ; RELOC-NEXT: Type: R_TLS_LE (0x23) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0xB8 -; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 (35) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 ([[#NFA+35]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 64 ; RELOC-NEXT: Type: R_TLS_LE (0x23) ; RELOC-NEXT: } -; SYM: File: {{.*}}aix-tls-le-xcoff-reloc.ll.tmp.o +; SYM: File: ; SYM-NEXT: Format: aix5coff64-rs6000 ; SYM-NEXT: Arch: powerpc64 ; SYM-NEXT: AddressSize: 64bit ; SYM-NEXT: Symbols [ -; SYM: Index: 21 +; SYM: Index: [[#NFA+21]] ; SYM-NEXT: Name: IThreadLocalVarUninit ; SYM-NEXT: Value (RelocatableAddress): 0xA0 ; SYM-NEXT: Section: .data @@ -97,7 +97,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 22 +; SYM-NEXT: Index: [[#NFA+22]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -107,7 +107,7 @@ entry: ; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB) ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 23 +; SYM: Index: [[#NFA+23]] ; SYM-NEXT: Name: ThreadLocalVarInit ; SYM-NEXT: Value (RelocatableAddress): 0xA8 ; SYM-NEXT: Section: .data @@ -115,7 +115,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 24 +; SYM-NEXT: Index: [[#NFA+24]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -125,7 +125,7 @@ entry: ; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB) ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 27 +; SYM: Index: [[#NFA+27]] ; SYM-NEXT: Name: IThreadLocalVarUninit2 ; SYM-NEXT: Value (RelocatableAddress): 0xB8 ; SYM-NEXT: Section: .data @@ -133,7 +133,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 28 +; SYM-NEXT: Index: [[#NFA+28]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -143,7 +143,7 @@ entry: ; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB) ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 31 +; SYM: Index: [[#NFA+31]] ; SYM-NEXT: Name: ThreadLocalVarInit ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: .tdata @@ -151,8 +151,8 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 32 -; SYM-NEXT: ContainingCsectSymbolIndex: 29 +; SYM-NEXT: Index: [[#NFA+32]] +; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+29]] ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 ; SYM-NEXT: SymbolAlignmentLog2: 0 @@ -161,7 +161,7 @@ entry: ; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB) ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 33 +; SYM: Index: [[#NFA+33]] ; SYM-NEXT: Name: IThreadLocalVarUninit ; SYM-NEXT: Value (RelocatableAddress): 0x4 ; SYM-NEXT: Section: .tbss @@ -169,7 +169,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 34 +; SYM-NEXT: Index: [[#NFA+34]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -179,7 +179,7 @@ entry: ; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB) ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 35 +; SYM: Index: [[#NFA+35]] ; SYM-NEXT: Name: IThreadLocalVarUninit2 ; SYM-NEXT: Value (RelocatableAddress): 0x8 ; SYM-NEXT: Section: .tbss @@ -187,7 +187,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 36 +; SYM-NEXT: Index: [[#NFA+36]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -198,83 +198,83 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } -; DIS: {{.*}}aix-tls-le-xcoff-reloc.ll.tmp.o: file format aix5coff64-rs6000 +; DIS: file format aix5coff64-rs6000 ; DIS: Disassembly of section .text: -; DIS: 0000000000000000 (idx: 3) .storeITLUninit: +; DIS: 0000000000000000 (idx: [[#NFA+3]]) .storeITLUninit: ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 4, 0(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 21) IThreadLocalVarUninit[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+21]]) IThreadLocalVarUninit[TC] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stwx 3, 13, 4 ; DIS-NEXT: blr -; DIS: 0000000000000010 (idx: 5) .loadTLInit: +; DIS: 0000000000000010 (idx: [[#NFA+5]]) .loadTLInit: ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 3, 8(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 23) ThreadLocalVarInit[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+23]]) ThreadLocalVarInit[TC] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 4, 16(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 25) VarInit[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+25]]) VarInit[TC] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwzx 3, 13, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 0(4) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} add 3, 4, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} extsw 3, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} blr -; DIS: 0000000000000030 (idx: 7) .loadTLUninit: +; DIS: 0000000000000030 (idx: [[#NFA+7]]) .loadTLUninit: ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 3, 0(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 21) IThreadLocalVarUninit[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+21]]) IThreadLocalVarUninit[TC] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 4, 1 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stwx 4, 13, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 3, 24(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 27) IThreadLocalVarUninit2[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+27]]) IThreadLocalVarUninit2[TC] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwzx 3, 13, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addi 3, 3, 1 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} extsw 3, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} blr ; DIS: Disassembly of section .data: -; DIS: 0000000000000050 (idx: 11) VarInit: +; DIS: 0000000000000050 (idx: [[#NFA+11]]) VarInit: ; DIS-NEXT: 50: 00 00 00 57 -; DIS: 0000000000000058 (idx: 13) storeITLUninit[DS]: +; DIS: 0000000000000058 (idx: [[#NFA+13]]) storeITLUninit[DS]: ; DIS-NEXT: 58: 00 00 00 00 -; DIS-NEXT: 0000000000000058: R_POS (idx: 3) .storeITLUninit +; DIS-NEXT: 0000000000000058: R_POS (idx: [[#NFA+3]]) .storeITLUninit ; DIS-NEXT: 5c: 00 00 00 00 ; DIS-NEXT: 60: 00 00 00 00 -; DIS-NEXT: 0000000000000060: R_POS (idx: 19) TOC[TC0] +; DIS-NEXT: 0000000000000060: R_POS (idx: [[#NFA+19]]) TOC[TC0] ; DIS-NEXT: 64: 00 00 00 a0 -; DIS: 0000000000000070 (idx: 15) loadTLInit[DS]: +; DIS: 0000000000000070 (idx: [[#NFA+15]]) loadTLInit[DS]: ; DIS-NEXT: 70: 00 00 00 00 -; DIS-NEXT: 0000000000000070: R_POS (idx: 5) .loadTLInit +; DIS-NEXT: 0000000000000070: R_POS (idx: [[#NFA+5]]) .loadTLInit ; DIS-NEXT: 74: 00 00 00 10 ; DIS-NEXT: 78: 00 00 00 00 -; DIS-NEXT: 0000000000000078: R_POS (idx: 19) TOC[TC0] +; DIS-NEXT: 0000000000000078: R_POS (idx: [[#NFA+19]]) TOC[TC0] ; DIS-NEXT: 7c: 00 00 00 a0 -; DIS: 0000000000000088 (idx: 17) loadTLUninit[DS]: +; DIS: 0000000000000088 (idx: [[#NFA+17]]) loadTLUninit[DS]: ; DIS-NEXT: 88: 00 00 00 00 -; DIS-NEXT: 0000000000000088: R_POS (idx: 7) .loadTLUninit +; DIS-NEXT: 0000000000000088: R_POS (idx: [[#NFA+7]]) .loadTLUninit ; DIS-NEXT: 8c: 00 00 00 30 ; DIS-NEXT: 90: 00 00 00 00 -; DIS-NEXT: 0000000000000090: R_POS (idx: 19) TOC[TC0] +; DIS-NEXT: 0000000000000090: R_POS (idx: [[#NFA+19]]) TOC[TC0] ; DIS-NEXT: 94: 00 00 00 a0 -; DIS: 00000000000000a0 (idx: 21) IThreadLocalVarUninit[TC]: +; DIS: 00000000000000a0 (idx: [[#NFA+21]]) IThreadLocalVarUninit[TC]: ; DIS-NEXT: a0: 00 00 00 00 -; DIS-NEXT: 00000000000000a0: R_TLS_LE (idx: 33) IThreadLocalVarUninit[UL] +; DIS-NEXT: 00000000000000a0: R_TLS_LE (idx: [[#NFA+33]]) IThreadLocalVarUninit[UL] ; DIS-NEXT: a4: 00 00 00 04 -; DIS: 00000000000000a8 (idx: 23) ThreadLocalVarInit[TC]: +; DIS: 00000000000000a8 (idx: [[#NFA+23]]) ThreadLocalVarInit[TC]: ; DIS-NEXT: a8: 00 00 00 00 -; DIS-NEXT: 00000000000000a8: R_TLS_LE (idx: 31) ThreadLocalVarInit +; DIS-NEXT: 00000000000000a8: R_TLS_LE (idx: [[#NFA+31]]) ThreadLocalVarInit ; DIS-NEXT: ac: 00 00 00 00 -; DIS: 00000000000000b0 (idx: 25) VarInit[TC]: +; DIS: 00000000000000b0 (idx: [[#NFA+25]]) VarInit[TC]: ; DIS-NEXT: b0: 00 00 00 00 -; DIS-NEXT: 00000000000000b0: R_POS (idx: 11) VarInit +; DIS-NEXT: 00000000000000b0: R_POS (idx: [[#NFA+11]]) VarInit ; DIS-NEXT: b4: 00 00 00 50 -; DIS: 00000000000000b8 (idx: 27) IThreadLocalVarUninit2[TC]: +; DIS: 00000000000000b8 (idx: [[#NFA+27]]) IThreadLocalVarUninit2[TC]: ; DIS-NEXT: b8: 00 00 00 00 -; DIS-NEXT: 00000000000000b8: R_TLS_LE (idx: 35) IThreadLocalVarUninit2[UL] +; DIS-NEXT: 00000000000000b8: R_TLS_LE (idx: [[#NFA+35]]) IThreadLocalVarUninit2[UL] ; DIS-NEXT: bc: 00 00 00 08 ; DIS: Disassembly of section .tdata: -; DIS: 0000000000000000 (idx: 31) ThreadLocalVarInit: +; DIS: 0000000000000000 (idx: [[#NFA+31]]) ThreadLocalVarInit: ; DIS-NEXT: 0: 00 00 00 01 ; DIS: Disassembly of section .tbss: -; DIS: 0000000000000004 (idx: 33) IThreadLocalVarUninit[UL]: +; DIS: 0000000000000004 (idx: [[#NFA+33]]) IThreadLocalVarUninit[UL]: ; DIS-NEXT: ... -; DIS: 0000000000000008 (idx: 35) IThreadLocalVarUninit2[UL]: +; DIS: 0000000000000008 (idx: [[#NFA+35]]) IThreadLocalVarUninit2[UL]: ; DIS-NEXT: ... diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc32.ll b/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc32.ll index a681cd815d43..4be292b3030f 100644 --- a/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc32.ll +++ b/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc32.ll @@ -1,8 +1,8 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -xcoff-traceback-table=false -data-sections=false -filetype=obj -o %t.o < %s -; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefix=RELOC %s -; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM %s -; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s +; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck -D#NFA=2 --check-prefix=RELOC %s +; RUN: llvm-readobj --syms %t.o | FileCheck -D#NFA=2 --check-prefix=SYM %s +; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=DIS %s @ThreadLocalVarInit = thread_local(localexec) global i32 1, align 4 @VarInit = global i32 87, align 4 @@ -36,74 +36,74 @@ entry: ret i32 %add } -; RELOC: File: {{.*}}aix-tls-le-xcoff-reloc32.ll.tmp.o +; RELOC: File: ; RELOC-NEXT: Format: aixcoff-rs6000 ; RELOC-NEXT: Arch: powerpc ; RELOC-NEXT: AddressSize: 32bit ; RELOC-NEXT: Relocations [ ; RELOC: Virtual Address: 0xA -; RELOC-NEXT: Symbol: IThreadLocalVarUninit (23) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit ([[#NFA+23]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOC (0x3) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x10 -; RELOC-NEXT: Symbol: .__get_tpointer (1) +; RELOC-NEXT: Symbol: .__get_tpointer ([[#NFA+1]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 26 ; RELOC-NEXT: Type: R_RBA (0x18) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x3A -; RELOC-NEXT: Symbol: ThreadLocalVarInit (25) +; RELOC-NEXT: Symbol: ThreadLocalVarInit ([[#NFA+25]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOC (0x3) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x40 -; RELOC-NEXT: Symbol: .__get_tpointer (1) +; RELOC-NEXT: Symbol: .__get_tpointer ([[#NFA+1]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 26 ; RELOC-NEXT: Type: R_RBA (0x18) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x8E -; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 (29) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 ([[#NFA+29]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOC (0x3) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0xD0 -; RELOC-NEXT: Symbol: IThreadLocalVarUninit (35) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit ([[#NFA+35]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 ; RELOC-NEXT: Type: R_TLS_LE (0x23) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0xD4 -; RELOC-NEXT: Symbol: ThreadLocalVarInit (33) +; RELOC-NEXT: Symbol: ThreadLocalVarInit ([[#NFA+33]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 ; RELOC-NEXT: Type: R_TLS_LE (0x23) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0xDC -; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 (37) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 ([[#NFA+37]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 ; RELOC-NEXT: Type: R_TLS_LE (0x23) ; RELOC-NEXT: } -; SYM: File: {{.*}}aix-tls-le-xcoff-reloc32.ll.tmp.o +; SYM: File: ; SYM-NEXT: Format: aixcoff-rs6000 ; SYM-NEXT: Arch: powerpc ; SYM-NEXT: AddressSize: 32bit ; SYM-NEXT: Symbols [ -; SYM: Index: 1 +; SYM: Index: [[#NFA+1]] ; SYM-NEXT: Name: .__get_tpointer ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: N_UNDEF @@ -111,7 +111,7 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 2 +; SYM-NEXT: Index: [[#NFA+2]] ; SYM-NEXT: SectionLen: 0 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -122,7 +122,7 @@ entry: ; SYM-NEXT: StabSectNum: 0x0 ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 23 +; SYM: Index: [[#NFA+23]] ; SYM-NEXT: Name: IThreadLocalVarUninit ; SYM-NEXT: Value (RelocatableAddress): 0xD0 ; SYM-NEXT: Section: .data @@ -130,7 +130,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 24 +; SYM-NEXT: Index: [[#NFA+24]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -141,7 +141,7 @@ entry: ; SYM-NEXT: StabSectNum: 0x0 ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 25 +; SYM: Index: [[#NFA+25]] ; SYM-NEXT: Name: ThreadLocalVarInit ; SYM-NEXT: Value (RelocatableAddress): 0xD4 ; SYM-NEXT: Section: .data @@ -149,7 +149,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 26 +; SYM-NEXT: Index: [[#NFA+26]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -160,7 +160,7 @@ entry: ; SYM-NEXT: StabSectNum: 0x0 ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 29 +; SYM: Index: [[#NFA+29]] ; SYM-NEXT: Name: IThreadLocalVarUninit2 ; SYM-NEXT: Value (RelocatableAddress): 0xDC ; SYM-NEXT: Section: .data @@ -168,7 +168,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 30 +; SYM-NEXT: Index: [[#NFA+30]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -179,7 +179,7 @@ entry: ; SYM-NEXT: StabSectNum: 0x0 ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 33 +; SYM: Index: [[#NFA+33]] ; SYM-NEXT: Name: ThreadLocalVarInit ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: .tdata @@ -187,8 +187,8 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 34 -; SYM-NEXT: ContainingCsectSymbolIndex: 31 +; SYM-NEXT: Index: [[#NFA+34]] +; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+31]] ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 ; SYM-NEXT: SymbolAlignmentLog2: 0 @@ -198,7 +198,7 @@ entry: ; SYM-NEXT: StabSectNum: 0x0 ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 35 +; SYM: Index: [[#NFA+35]] ; SYM-NEXT: Name: IThreadLocalVarUninit ; SYM-NEXT: Value (RelocatableAddress): 0x4 ; SYM-NEXT: Section: .tbss @@ -206,7 +206,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 36 +; SYM-NEXT: Index: [[#NFA+36]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -217,7 +217,7 @@ entry: ; SYM-NEXT: StabSectNum: 0x0 ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 37 +; SYM: Index: [[#NFA+37]] ; SYM-NEXT: Name: IThreadLocalVarUninit2 ; SYM-NEXT: Value (RelocatableAddress): 0x8 ; SYM-NEXT: Section: .tbss @@ -225,7 +225,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 38 +; SYM-NEXT: Index: [[#NFA+38]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -237,51 +237,51 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } -; DIS: {{.*}}aix-tls-le-xcoff-reloc32.ll.tmp.o: file format aixcoff-rs6000 +; DIS: file format aixcoff-rs6000 ; DIS: Disassembly of section .text: -; DIS: 00000000 (idx: 5) .storeITLUninit: +; DIS: 00000000 (idx: [[#NFA+5]]) .storeITLUninit: ; DIS-NEXT: mflr 0 ; DIS-NEXT: stwu 1, -32(1) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 5, 0(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 23) IThreadLocalVarUninit[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+23]]) IThreadLocalVarUninit[TC] ; DIS-NEXT: mr 4, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0 -; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: 1) .__get_tpointer[PR] +; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: [[#NFA+1]]) .__get_tpointer[PR] ; DIS-NEXT: stw 0, 40(1) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stwx 4, 3, 5 ; DIS-NEXT: addi 1, 1, 32 ; DIS-NEXT: lwz 0, 8(1) ; DIS-NEXT: mtlr 0 ; DIS-NEXT: blr -; DIS: 00000030 (idx: 7) .loadTLInit: +; DIS: 00000030 (idx: [[#NFA+7]]) .loadTLInit: ; DIS-NEXT: mflr 0 ; DIS-NEXT: stwu 1, -32(1) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 4(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 25) ThreadLocalVarInit[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+25]]) ThreadLocalVarInit[TC] ; DIS-NEXT: stw 0, 40(1) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0 -; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: 1) .__get_tpointer[PR] +; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: [[#NFA+1]]) .__get_tpointer[PR] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwzx 3, 3, 4 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 8(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 27) VarInit[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+27]]) VarInit[TC] ; DIS-NEXT: lwz 4, 0(4) ; DIS-NEXT: add 3, 4, 3 ; DIS-NEXT: addi 1, 1, 32 ; DIS-NEXT: lwz 0, 8(1) ; DIS-NEXT: mtlr 0 ; DIS-NEXT: blr -; DIS: 00000070 (idx: 9) .loadTLUninit: +; DIS: 00000070 (idx: [[#NFA+9]]) .loadTLUninit: ; DIS-NEXT: mflr 0 ; DIS-NEXT: stwu 1, -32(1) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 0(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 23) IThreadLocalVarUninit[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+23]]) IThreadLocalVarUninit[TC] ; DIS-NEXT: li 5, 1 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0 -; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: 1) .__get_tpointer[PR] +; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: [[#NFA+1]]) .__get_tpointer[PR] ; DIS-NEXT: stw 0, 40(1) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stwx 5, 3, 4 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 12(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 29) IThreadLocalVarUninit2[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+29]]) IThreadLocalVarUninit2[TC] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwzx 3, 3, 4 ; DIS-NEXT: addi 3, 3, 1 ; DIS-NEXT: addi 1, 1, 32 @@ -290,46 +290,46 @@ entry: ; DIS-NEXT: blr ; DIS: Disassembly of section .data: -; DIS: 000000a8 (idx: 13) VarInit: +; DIS: 000000a8 (idx: [[#NFA+13]]) VarInit: ; DIS-NEXT: a8: 00 00 00 57 -; DIS: 000000ac (idx: 15) storeITLUninit[DS]: +; DIS: 000000ac (idx: [[#NFA+15]]) storeITLUninit[DS]: ; DIS-NEXT: ac: 00 00 00 00 -; DIS-NEXT: 000000ac: R_POS (idx: 5) .storeITLUninit +; DIS-NEXT: 000000ac: R_POS (idx: [[#NFA+5]]) .storeITLUninit ; DIS-NEXT: b0: 00 00 00 d0 -; DIS-NEXT: 000000b0: R_POS (idx: 21) TOC[TC0] +; DIS-NEXT: 000000b0: R_POS (idx: [[#NFA+21]]) TOC[TC0] ; DIS-NEXT: b4: 00 00 00 00 -; DIS: 000000b8 (idx: 17) loadTLInit[DS]: +; DIS: 000000b8 (idx: [[#NFA+17]]) loadTLInit[DS]: ; DIS-NEXT: b8: 00 00 00 30 -; DIS-NEXT: 000000b8: R_POS (idx: 7) .loadTLInit +; DIS-NEXT: 000000b8: R_POS (idx: [[#NFA+7]]) .loadTLInit ; DIS-NEXT: bc: 00 00 00 d0 -; DIS-NEXT: 000000bc: R_POS (idx: 21) TOC[TC0] +; DIS-NEXT: 000000bc: R_POS (idx: [[#NFA+21]]) TOC[TC0] ; DIS-NEXT: c0: 00 00 00 00 -; DIS: 000000c4 (idx: 19) loadTLUninit[DS]: +; DIS: 000000c4 (idx: [[#NFA+19]]) loadTLUninit[DS]: ; DIS-NEXT: c4: 00 00 00 70 -; DIS-NEXT: 000000c4: R_POS (idx: 9) .loadTLUninit +; DIS-NEXT: 000000c4: R_POS (idx: [[#NFA+9]]) .loadTLUninit ; DIS-NEXT: c8: 00 00 00 d0 -; DIS-NEXT: 000000c8: R_POS (idx: 21) TOC[TC0] +; DIS-NEXT: 000000c8: R_POS (idx: [[#NFA+21]]) TOC[TC0] ; DIS-NEXT: cc: 00 00 00 00 -; DIS: 000000d0 (idx: 23) IThreadLocalVarUninit[TC]: +; DIS: 000000d0 (idx: [[#NFA+23]]) IThreadLocalVarUninit[TC]: ; DIS-NEXT: d0: 00 00 00 04 -; DIS-NEXT: 000000d0: R_TLS_LE (idx: 35) IThreadLocalVarUninit[UL] -; DIS: 000000d4 (idx: 25) ThreadLocalVarInit[TC]: +; DIS-NEXT: 000000d0: R_TLS_LE (idx: [[#NFA+35]]) IThreadLocalVarUninit[UL] +; DIS: 000000d4 (idx: [[#NFA+25]]) ThreadLocalVarInit[TC]: ; DIS-NEXT: d4: 00 00 00 00 -; DIS-NEXT: 000000d4: R_TLS_LE (idx: 33) ThreadLocalVarInit -; DIS: 000000d8 (idx: 27) VarInit[TC]: +; DIS-NEXT: 000000d4: R_TLS_LE (idx: [[#NFA+33]]) ThreadLocalVarInit +; DIS: 000000d8 (idx: [[#NFA+27]]) VarInit[TC]: ; DIS-NEXT: d8: 00 00 00 a8 -; DIS-NEXT: 000000d8: R_POS (idx: 13) VarInit -; DIS: 000000dc (idx: 29) IThreadLocalVarUninit2[TC]: +; DIS-NEXT: 000000d8: R_POS (idx: [[#NFA+13]]) VarInit +; DIS: 000000dc (idx: [[#NFA+29]]) IThreadLocalVarUninit2[TC]: ; DIS-NEXT: dc: 00 00 00 08 -; DIS-NEXT: 000000dc: R_TLS_LE (idx: 37) IThreadLocalVarUninit2[UL] +; DIS-NEXT: 000000dc: R_TLS_LE (idx: [[#NFA+37]]) IThreadLocalVarUninit2[UL] ; DIS: Disassembly of section .tdata: -; DIS: 00000000 (idx: 33) ThreadLocalVarInit: +; DIS: 00000000 (idx: [[#NFA+33]]) ThreadLocalVarInit: ; DIS-NEXT: 0: 00 00 00 01 ; DIS: Disassembly of section .tbss: -; DIS: 00000004 (idx: 35) IThreadLocalVarUninit[UL]: +; DIS: 00000004 (idx: [[#NFA+35]]) IThreadLocalVarUninit[UL]: ; DIS-NEXT: ... -; DIS: 00000008 (idx: 37) IThreadLocalVarUninit2[UL]: +; DIS: 00000008 (idx: [[#NFA+37]]) IThreadLocalVarUninit2[UL]: ; DIS-NEXT: ... diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll index 2dae8ee96e20..059924f392f6 100644 --- a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll +++ b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll @@ -1,8 +1,8 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -xcoff-traceback-table=false --code-model=large -filetype=obj -o %t.o < %s -; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefix=RELOC %s -; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM %s -; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s +; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck -D#NFA=2 --check-prefix=RELOC %s +; RUN: llvm-readobj --syms %t.o | FileCheck -D#NFA=2 --check-prefix=SYM %s +; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=DIS %s @GInit = global double 1.000000e+00, align 8 @TIInit = internal thread_local global i64 1, align 8 @@ -24,7 +24,7 @@ entry: ret double %add } -; RELOC: File: {{.*}}aix-tls-xcoff-reloc-large.ll.tmp.o +; RELOC: File: ; RELOC-NEXT: Format: aixcoff-rs6000 ; RELOC-NEXT: Arch: powerpc ; RELOC-NEXT: AddressSize: 32bit @@ -32,7 +32,7 @@ entry: ; RELOC-NEXT: Section (index: 1) .text { ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x16 -; RELOC-NEXT: Symbol: .TIInit (17) +; RELOC-NEXT: Symbol: .TIInit ([[#NFA+17]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -40,7 +40,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x1A -; RELOC-NEXT: Symbol: TIInit (19) +; RELOC-NEXT: Symbol: TIInit ([[#NFA+19]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -48,7 +48,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x1E -; RELOC-NEXT: Symbol: .TIInit (17) +; RELOC-NEXT: Symbol: .TIInit ([[#NFA+17]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -56,7 +56,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x22 -; RELOC-NEXT: Symbol: TIInit (19) +; RELOC-NEXT: Symbol: TIInit ([[#NFA+19]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -64,7 +64,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x24 -; RELOC-NEXT: Symbol: .__tls_get_addr (1) +; RELOC-NEXT: Symbol: .__tls_get_addr ([[#NFA+1]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 26 @@ -72,7 +72,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x4E -; RELOC-NEXT: Symbol: .TWInit (21) +; RELOC-NEXT: Symbol: .TWInit ([[#NFA+21]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -80,7 +80,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x52 -; RELOC-NEXT: Symbol: TWInit (23) +; RELOC-NEXT: Symbol: TWInit ([[#NFA+23]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -88,7 +88,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x56 -; RELOC-NEXT: Symbol: .TWInit (21) +; RELOC-NEXT: Symbol: .TWInit ([[#NFA+21]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -96,7 +96,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x5A -; RELOC-NEXT: Symbol: TWInit (23) +; RELOC-NEXT: Symbol: TWInit ([[#NFA+23]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -104,7 +104,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x5C -; RELOC-NEXT: Symbol: .__tls_get_addr (1) +; RELOC-NEXT: Symbol: .__tls_get_addr ([[#NFA+1]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 26 @@ -112,7 +112,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x66 -; RELOC-NEXT: Symbol: GInit (25) +; RELOC-NEXT: Symbol: GInit ([[#NFA+25]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -120,7 +120,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x6A -; RELOC-NEXT: Symbol: GInit (25) +; RELOC-NEXT: Symbol: GInit ([[#NFA+25]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -130,7 +130,7 @@ entry: ; RELOC-NEXT: Section (index: 2) .data { ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x90 -; RELOC-NEXT: Symbol: .storesTIInit (5) +; RELOC-NEXT: Symbol: .storesTIInit ([[#NFA+5]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -138,7 +138,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x94 -; RELOC-NEXT: Symbol: TOC (15) +; RELOC-NEXT: Symbol: TOC ([[#NFA+15]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -146,7 +146,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x9C -; RELOC-NEXT: Symbol: .loadsTWInit (7) +; RELOC-NEXT: Symbol: .loadsTWInit ([[#NFA+7]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -154,7 +154,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0xA0 -; RELOC-NEXT: Symbol: TOC (15) +; RELOC-NEXT: Symbol: TOC ([[#NFA+15]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -162,7 +162,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0xA8 -; RELOC-NEXT: Symbol: TIInit (27) +; RELOC-NEXT: Symbol: TIInit ([[#NFA+27]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -170,7 +170,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0xAC -; RELOC-NEXT: Symbol: TIInit (27) +; RELOC-NEXT: Symbol: TIInit ([[#NFA+27]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -178,7 +178,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0xB0 -; RELOC-NEXT: Symbol: TWInit (29) +; RELOC-NEXT: Symbol: TWInit ([[#NFA+29]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -186,7 +186,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0xB4 -; RELOC-NEXT: Symbol: TWInit (29) +; RELOC-NEXT: Symbol: TWInit ([[#NFA+29]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -194,7 +194,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0xB8 -; RELOC-NEXT: Symbol: GInit (9) +; RELOC-NEXT: Symbol: GInit ([[#NFA+9]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -203,23 +203,33 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: ] -; SYM: File: {{.*}}aix-tls-xcoff-reloc-large.ll.tmp.o +; SYM: File: ; SYM-NEXT: Format: aixcoff-rs6000 ; SYM-NEXT: Arch: powerpc ; SYM-NEXT: AddressSize: 32bit ; SYM-NEXT: Symbols [ ; SYM-NEXT: Symbol { ; SYM-NEXT: Index: 0 -; SYM-NEXT: Name: +; SYM-NEXT: Name: .file ; SYM-NEXT: Value (SymbolTableIndex): 0x0 ; SYM-NEXT: Section: N_DEBUG ; SYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9) ; SYM-NEXT: CPU Version ID: TCPU_COM (0x3) ; SYM-NEXT: StorageClass: C_FILE (0x67) -; SYM-NEXT: NumberOfAuxEntries: 0 +; SYM-NEXT: NumberOfAuxEntries: 2 +; SYM-NEXT: File Auxiliary Entry { +; SYM-NEXT: Index: 1 +; SYM-NEXT: Name: +; SYM-NEXT: Type: XFT_FN (0x0) +; SYM-NEXT: } +; SYM-NEXT: File Auxiliary Entry { +; SYM-NEXT: Index: 2 +; SYM-NEXT: Name: LLVM +; SYM-NEXT: Type: XFT_CV (0x2) +; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 1 +; SYM-NEXT: Index: [[#NFA+1]] ; SYM-NEXT: Name: .__tls_get_addr ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: N_UNDEF @@ -227,7 +237,7 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 2 +; SYM-NEXT: Index: [[#NFA+2]] ; SYM-NEXT: SectionLen: 0 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -239,7 +249,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 3 +; SYM-NEXT: Index: [[#NFA+3]] ; SYM-NEXT: Name: ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: .text @@ -247,7 +257,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 4 +; SYM-NEXT: Index: [[#NFA+4]] ; SYM-NEXT: SectionLen: 132 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -259,7 +269,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 5 +; SYM-NEXT: Index: [[#NFA+5]] ; SYM-NEXT: Name: .storesTIInit ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: .text @@ -267,8 +277,8 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 6 -; SYM-NEXT: ContainingCsectSymbolIndex: 3 +; SYM-NEXT: Index: [[#NFA+6]] +; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+3]] ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 ; SYM-NEXT: SymbolAlignmentLog2: 0 @@ -279,7 +289,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 7 +; SYM-NEXT: Index: [[#NFA+7]] ; SYM-NEXT: Name: .loadsTWInit ; SYM-NEXT: Value (RelocatableAddress): 0x40 ; SYM-NEXT: Section: .text @@ -287,8 +297,8 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 8 -; SYM-NEXT: ContainingCsectSymbolIndex: 3 +; SYM-NEXT: Index: [[#NFA+8]] +; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+3]] ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 ; SYM-NEXT: SymbolAlignmentLog2: 0 @@ -299,7 +309,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 9 +; SYM-NEXT: Index: [[#NFA+9]] ; SYM-NEXT: Name: GInit ; SYM-NEXT: Value (RelocatableAddress): 0x88 ; SYM-NEXT: Section: .data @@ -307,7 +317,7 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 10 +; SYM-NEXT: Index: [[#NFA+10]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -319,7 +329,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 11 +; SYM-NEXT: Index: [[#NFA+11]] ; SYM-NEXT: Name: storesTIInit ; SYM-NEXT: Value (RelocatableAddress): 0x90 ; SYM-NEXT: Section: .data @@ -327,7 +337,7 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 12 +; SYM-NEXT: Index: [[#NFA+12]] ; SYM-NEXT: SectionLen: 12 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -339,7 +349,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 13 +; SYM-NEXT: Index: [[#NFA+13]] ; SYM-NEXT: Name: loadsTWInit ; SYM-NEXT: Value (RelocatableAddress): 0x9C ; SYM-NEXT: Section: .data @@ -347,7 +357,7 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 14 +; SYM-NEXT: Index: [[#NFA+14]] ; SYM-NEXT: SectionLen: 12 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -359,7 +369,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 15 +; SYM-NEXT: Index: [[#NFA+15]] ; SYM-NEXT: Name: TOC ; SYM-NEXT: Value (RelocatableAddress): 0xA8 ; SYM-NEXT: Section: .data @@ -367,7 +377,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 16 +; SYM-NEXT: Index: [[#NFA+16]] ; SYM-NEXT: SectionLen: 0 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -379,7 +389,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 17 +; SYM-NEXT: Index: [[#NFA+17]] ; SYM-NEXT: Name: .TIInit ; SYM-NEXT: Value (RelocatableAddress): 0xA8 ; SYM-NEXT: Section: .data @@ -387,7 +397,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 18 +; SYM-NEXT: Index: [[#NFA+18]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -399,7 +409,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 19 +; SYM-NEXT: Index: [[#NFA+19]] ; SYM-NEXT: Name: TIInit ; SYM-NEXT: Value (RelocatableAddress): 0xAC ; SYM-NEXT: Section: .data @@ -407,7 +417,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 20 +; SYM-NEXT: Index: [[#NFA+20]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -419,7 +429,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 21 +; SYM-NEXT: Index: [[#NFA+21]] ; SYM-NEXT: Name: .TWInit ; SYM-NEXT: Value (RelocatableAddress): 0xB0 ; SYM-NEXT: Section: .data @@ -427,7 +437,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 22 +; SYM-NEXT: Index: [[#NFA+22]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -439,7 +449,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 23 +; SYM-NEXT: Index: [[#NFA+23]] ; SYM-NEXT: Name: TWInit ; SYM-NEXT: Value (RelocatableAddress): 0xB4 ; SYM-NEXT: Section: .data @@ -447,7 +457,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 24 +; SYM-NEXT: Index: [[#NFA+24]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -459,7 +469,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 25 +; SYM-NEXT: Index: [[#NFA+25]] ; SYM-NEXT: Name: GInit ; SYM-NEXT: Value (RelocatableAddress): 0xB8 ; SYM-NEXT: Section: .data @@ -467,7 +477,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 26 +; SYM-NEXT: Index: [[#NFA+26]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -479,7 +489,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 27 +; SYM-NEXT: Index: [[#NFA+27]] ; SYM-NEXT: Name: TIInit ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: .tdata @@ -487,7 +497,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 28 +; SYM-NEXT: Index: [[#NFA+28]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -499,7 +509,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 29 +; SYM-NEXT: Index: [[#NFA+29]] ; SYM-NEXT: Name: TWInit ; SYM-NEXT: Value (RelocatableAddress): 0x8 ; SYM-NEXT: Section: .tdata @@ -507,7 +517,7 @@ entry: ; SYM-NEXT: StorageClass: C_WEAKEXT (0x6F) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 30 +; SYM-NEXT: Index: [[#NFA+30]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -520,49 +530,49 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: ] -; DIS: {{.*}}aix-tls-xcoff-reloc-large.ll.tmp.o: file format aixcoff-rs6000 +; DIS: file format aixcoff-rs6000 ; DIS: Disassembly of section .text: -; DIS: 00000000 (idx: 5) .storesTIInit: +; DIS: 00000000 (idx: [[#INDX:]]) .storesTIInit: ; DIS-NEXT: mflr 0 ; DIS-NEXT: stwu 1, -32(1) ; DIS-NEXT: stw 0, 40(1) ; DIS-NEXT: mr 6, 4 ; DIS-NEXT: mr 7, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 17) .TIInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+17]]) .TIInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 4, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 19) TIInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+19]]) TIInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 3, 0(3) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 17) .TIInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+17]]) .TIInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 4(4) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 19) TIInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+19]]) TIInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0 -; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: 1) .__tls_get_addr[PR] +; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: [[#NFA+1]]) .__tls_get_addr[PR] ; DIS-NEXT: stw 6, 4(3) ; DIS-NEXT: stw 7, 0(3) ; DIS-NEXT: addi 1, 1, 32 ; DIS-NEXT: lwz 0, 8(1) ; DIS-NEXT: mtlr 0 ; DIS-NEXT: blr -; DIS: 00000040 (idx: 7) .loadsTWInit: +; DIS: 00000040 (idx: [[#INDX+2]]) .loadsTWInit: ; DIS-NEXT: mflr 0 ; DIS-NEXT: stwu 1, -32(1) ; DIS-NEXT: stw 0, 40(1) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 21) .TWInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+21]]) .TWInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 4, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 23) TWInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+23]]) TWInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 3, 8(3) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 21) .TWInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+21]]) .TWInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 12(4) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 23) TWInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+23]]) TWInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0 -; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: 1) .__tls_get_addr[PR] +; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: [[#NFA+1]]) .__tls_get_addr[PR] ; DIS-NEXT: lfd 0, 0(3) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 25) GInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+25]]) GInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 3, 16(3) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 25) GInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+25]]) GInit[TE] ; DIS-NEXT: lfd 1, 0(3) ; DIS-NEXT: fadd 1, 0, 1 ; DIS-NEXT: addi 1, 1, 32 @@ -571,42 +581,42 @@ entry: ; DIS-NEXT: blr ; DIS: Disassembly of section .data: -; DIS: 00000088 (idx: 9) GInit[RW]: +; DIS: 00000088 (idx: [[#NFA+9]]) GInit[RW]: ; DIS-NEXT: 88: 3f f0 00 00 ; DIS-NEXT: 8c: 00 00 00 00 -; DIS: 00000090 (idx: 11) storesTIInit[DS]: +; DIS: 00000090 (idx: [[#NFA+11]]) storesTIInit[DS]: ; DIS-NEXT: 90: 00 00 00 00 -; DIS-NEXT: 00000090: R_POS (idx: 5) .storesTIInit +; DIS-NEXT: 00000090: R_POS (idx: [[#NFA+5]]) .storesTIInit ; DIS-NEXT: 94: 00 00 00 a8 -; DIS-NEXT: 00000094: R_POS (idx: 15) TOC[TC0] +; DIS-NEXT: 00000094: R_POS (idx: [[#NFA+15]]) TOC[TC0] ; DIS-NEXT: 98: 00 00 00 00 -; DIS: 0000009c (idx: 13) loadsTWInit[DS]: +; DIS: 0000009c (idx: [[#NFA+13]]) loadsTWInit[DS]: ; DIS-NEXT: 9c: 00 00 00 40 -; DIS-NEXT: 0000009c: R_POS (idx: 7) .loadsTWInit +; DIS-NEXT: 0000009c: R_POS (idx: [[#NFA+7]]) .loadsTWInit ; DIS-NEXT: a0: 00 00 00 a8 -; DIS-NEXT: 000000a0: R_POS (idx: 15) TOC[TC0] +; DIS-NEXT: 000000a0: R_POS (idx: [[#NFA+15]]) TOC[TC0] ; DIS-NEXT: a4: 00 00 00 00 -; DIS: 000000a8 (idx: 17) .TIInit[TE]: +; DIS: 000000a8 (idx: [[#NFA+17]]) .TIInit[TE]: ; DIS-NEXT: a8: 00 00 00 00 -; DIS-NEXT: 000000a8: R_TLSM (idx: 27) TIInit[TL] -; DIS: 000000ac (idx: 19) TIInit[TE]: +; DIS-NEXT: 000000a8: R_TLSM (idx: [[#NFA+27]]) TIInit[TL] +; DIS: 000000ac (idx: [[#NFA+19]]) TIInit[TE]: ; DIS-NEXT: ac: 00 00 00 00 -; DIS-NEXT: 000000ac: R_TLS (idx: 27) TIInit[TL] -; DIS: 000000b0 (idx: 21) .TWInit[TE]: +; DIS-NEXT: 000000ac: R_TLS (idx: [[#NFA+27]]) TIInit[TL] +; DIS: 000000b0 (idx: [[#NFA+21]]) .TWInit[TE]: ; DIS-NEXT: b0: 00 00 00 00 -; DIS-NEXT: 000000b0: R_TLSM (idx: 29) TWInit[TL] -; DIS: 000000b4 (idx: 23) TWInit[TE]: +; DIS-NEXT: 000000b0: R_TLSM (idx: [[#NFA+29]]) TWInit[TL] +; DIS: 000000b4 (idx: [[#NFA+23]]) TWInit[TE]: ; DIS-NEXT: b4: 00 00 00 08 -; DIS-NEXT: 000000b4: R_TLS (idx: 29) TWInit[TL] -; DIS: 000000b8 (idx: 25) GInit[TE]: +; DIS-NEXT: 000000b4: R_TLS (idx: [[#NFA+29]]) TWInit[TL] +; DIS: 000000b8 (idx: [[#NFA+25]]) GInit[TE]: ; DIS-NEXT: b8: 00 00 00 88 -; DIS-NEXT: 000000b8: R_POS (idx: 9) GInit[RW] +; DIS-NEXT: 000000b8: R_POS (idx: [[#NFA+9]]) GInit[RW] ; DIS: Disassembly of section .tdata: -; DIS: 00000000 (idx: 27) TIInit[TL]: +; DIS: 00000000 (idx: [[#NFA+27]]) TIInit[TL]: ; DIS-NEXT: 0: 00 00 00 00 ; DIS-NEXT: 4: 00 00 00 01 -; DIS: 00000008 (idx: 29) TWInit[TL]: +; DIS: 00000008 (idx: [[#NFA+29]]) TWInit[TL]: ; DIS-NEXT: 8: 3f f0 00 00 ; DIS-NEXT: c: 00 00 00 00 diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll index 0779686b54f3..eb7a0e277a56 100644 --- a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll +++ b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll @@ -1,8 +1,8 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -xcoff-traceback-table=false -data-sections=false -filetype=obj -o %t.o < %s -; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefix=RELOC %s -; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM %s -; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s +; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck -D#NFA=2 --check-prefix=RELOC %s +; RUN: llvm-readobj --syms %t.o | FileCheck -D#NFA=2 --check-prefix=SYM %s +; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=DIS %s @const_ivar = constant i32 6, align 4 @GInit = global i32 1, align 4 @@ -25,7 +25,7 @@ entry: ret i32 %add } -; RELOC: File: {{.*}}aix-tls-xcoff-reloc.ll.tmp.o +; RELOC: File: ; RELOC-NEXT: Format: aixcoff-rs6000 ; RELOC-NEXT: Arch: powerpc ; RELOC-NEXT: AddressSize: 32bit @@ -33,7 +33,7 @@ entry: ; RELOC-NEXT: Section (index: 1) .text { ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0xE -; RELOC-NEXT: Symbol: .TIUninit (23) +; RELOC-NEXT: Symbol: .TIUninit ([[#NFA+23]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -41,7 +41,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x12 -; RELOC-NEXT: Symbol: TIUninit (25) +; RELOC-NEXT: Symbol: TIUninit ([[#NFA+25]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -49,7 +49,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x18 -; RELOC-NEXT: Symbol: .__tls_get_addr (1) +; RELOC-NEXT: Symbol: .__tls_get_addr ([[#NFA+1]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 26 @@ -57,7 +57,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x3A -; RELOC-NEXT: Symbol: .TGInit (27) +; RELOC-NEXT: Symbol: .TGInit ([[#NFA+27]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -65,7 +65,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x3E -; RELOC-NEXT: Symbol: TGInit (29) +; RELOC-NEXT: Symbol: TGInit ([[#NFA+29]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -73,7 +73,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x44 -; RELOC-NEXT: Symbol: .__tls_get_addr (1) +; RELOC-NEXT: Symbol: .__tls_get_addr ([[#NFA+1]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 26 @@ -81,7 +81,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x4A -; RELOC-NEXT: Symbol: GInit (31) +; RELOC-NEXT: Symbol: GInit ([[#NFA+31]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -91,7 +91,7 @@ entry: ; RELOC-NEXT: Section (index: 2) .data { ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x70 -; RELOC-NEXT: Symbol: .storesTIUninit (5) +; RELOC-NEXT: Symbol: .storesTIUninit ([[#NFA+5]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -99,7 +99,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x74 -; RELOC-NEXT: Symbol: TOC (21) +; RELOC-NEXT: Symbol: TOC ([[#NFA+21]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -107,7 +107,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x7C -; RELOC-NEXT: Symbol: .loadsTGInit (7) +; RELOC-NEXT: Symbol: .loadsTGInit ([[#NFA+7]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -115,7 +115,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x80 -; RELOC-NEXT: Symbol: TOC (21) +; RELOC-NEXT: Symbol: TOC ([[#NFA+21]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -123,7 +123,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x88 -; RELOC-NEXT: Symbol: TIUninit (37) +; RELOC-NEXT: Symbol: TIUninit ([[#NFA+37]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -131,7 +131,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x8C -; RELOC-NEXT: Symbol: TIUninit (37) +; RELOC-NEXT: Symbol: TIUninit ([[#NFA+37]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -139,7 +139,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x90 -; RELOC-NEXT: Symbol: TGInit (35) +; RELOC-NEXT: Symbol: TGInit ([[#NFA+35]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -147,7 +147,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x94 -; RELOC-NEXT: Symbol: TGInit (35) +; RELOC-NEXT: Symbol: TGInit ([[#NFA+35]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -155,7 +155,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x98 -; RELOC-NEXT: Symbol: GInit (15) +; RELOC-NEXT: Symbol: GInit ([[#NFA+15]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -164,23 +164,22 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: ] -; SYM: File: {{.*}}aix-tls-xcoff-reloc.ll.tmp.o +; SYM: File: ; SYM-NEXT: Format: aixcoff-rs6000 ; SYM-NEXT: Arch: powerpc ; SYM-NEXT: AddressSize: 32bit ; SYM-NEXT: Symbols [ ; SYM-NEXT: Symbol { ; SYM-NEXT: Index: 0 -; SYM-NEXT: Name: +; SYM-NEXT: Name: .file ; SYM-NEXT: Value (SymbolTableIndex): 0x0 ; SYM-NEXT: Section: N_DEBUG ; SYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9) ; SYM-NEXT: CPU Version ID: TCPU_COM (0x3) ; SYM-NEXT: StorageClass: C_FILE (0x67) -; SYM-NEXT: NumberOfAuxEntries: 0 -; SYM-NEXT: } -; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 1 +; SYM-NEXT: NumberOfAuxEntries: 2 +; SYM: Symbol { +; SYM-NEXT: Index: [[#NFA+1]] ; SYM-NEXT: Name: .__tls_get_addr ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: N_UNDEF @@ -188,7 +187,7 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 2 +; SYM-NEXT: Index: [[#NFA+2]] ; SYM-NEXT: SectionLen: 0 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -200,7 +199,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 3 +; SYM-NEXT: Index: [[#NFA+3]] ; SYM-NEXT: Name: ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: .text @@ -208,7 +207,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 4 +; SYM-NEXT: Index: [[#NFA+4]] ; SYM-NEXT: SectionLen: 104 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -220,7 +219,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 5 +; SYM-NEXT: Index: [[#NFA+5]] ; SYM-NEXT: Name: .storesTIUninit ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: .text @@ -228,8 +227,8 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 6 -; SYM-NEXT: ContainingCsectSymbolIndex: 3 +; SYM-NEXT: Index: [[#NFA+6]] +; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+3]] ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 ; SYM-NEXT: SymbolAlignmentLog2: 0 @@ -240,7 +239,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 7 +; SYM-NEXT: Index: [[#NFA+7]] ; SYM-NEXT: Name: .loadsTGInit ; SYM-NEXT: Value (RelocatableAddress): 0x30 ; SYM-NEXT: Section: .text @@ -248,8 +247,8 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 8 -; SYM-NEXT: ContainingCsectSymbolIndex: 3 +; SYM-NEXT: Index: [[#NFA+8]] +; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+3]] ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 ; SYM-NEXT: SymbolAlignmentLog2: 0 @@ -260,7 +259,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 9 +; SYM-NEXT: Index: [[#NFA+9]] ; SYM-NEXT: Name: .rodata ; SYM-NEXT: Value (RelocatableAddress): 0x68 ; SYM-NEXT: Section: .text @@ -268,7 +267,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 10 +; SYM-NEXT: Index: [[#NFA+10]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -280,7 +279,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 11 +; SYM-NEXT: Index: [[#NFA+11]] ; SYM-NEXT: Name: const_ivar ; SYM-NEXT: Value (RelocatableAddress): 0x68 ; SYM-NEXT: Section: .text @@ -288,8 +287,8 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 12 -; SYM-NEXT: ContainingCsectSymbolIndex: 9 +; SYM-NEXT: Index: [[#NFA+12]] +; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+9]] ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 ; SYM-NEXT: SymbolAlignmentLog2: 0 @@ -300,7 +299,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 13 +; SYM-NEXT: Index: [[#NFA+13]] ; SYM-NEXT: Name: .data ; SYM-NEXT: Value (RelocatableAddress): 0x6C ; SYM-NEXT: Section: .data @@ -308,7 +307,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 14 +; SYM-NEXT: Index: [[#NFA+14]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -320,7 +319,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 15 +; SYM-NEXT: Index: [[#NFA+15]] ; SYM-NEXT: Name: GInit ; SYM-NEXT: Value (RelocatableAddress): 0x6C ; SYM-NEXT: Section: .data @@ -328,8 +327,8 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 16 -; SYM-NEXT: ContainingCsectSymbolIndex: 13 +; SYM-NEXT: Index: [[#NFA+16]] +; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+13]] ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 ; SYM-NEXT: SymbolAlignmentLog2: 0 @@ -340,7 +339,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 17 +; SYM-NEXT: Index: [[#NFA+17]] ; SYM-NEXT: Name: storesTIUninit ; SYM-NEXT: Value (RelocatableAddress): 0x70 ; SYM-NEXT: Section: .data @@ -348,7 +347,7 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 18 +; SYM-NEXT: Index: [[#NFA+18]] ; SYM-NEXT: SectionLen: 12 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -360,7 +359,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 19 +; SYM-NEXT: Index: [[#NFA+19]] ; SYM-NEXT: Name: loadsTGInit ; SYM-NEXT: Value (RelocatableAddress): 0x7C ; SYM-NEXT: Section: .data @@ -368,7 +367,7 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 20 +; SYM-NEXT: Index: [[#NFA+20]] ; SYM-NEXT: SectionLen: 12 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -380,7 +379,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 21 +; SYM-NEXT: Index: [[#NFA+21]] ; SYM-NEXT: Name: TOC ; SYM-NEXT: Value (RelocatableAddress): 0x88 ; SYM-NEXT: Section: .data @@ -388,7 +387,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 22 +; SYM-NEXT: Index: [[#NFA+22]] ; SYM-NEXT: SectionLen: 0 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -400,7 +399,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 23 +; SYM-NEXT: Index: [[#NFA+23]] ; SYM-NEXT: Name: .TIUninit ; SYM-NEXT: Value (RelocatableAddress): 0x88 ; SYM-NEXT: Section: .data @@ -408,7 +407,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 24 +; SYM-NEXT: Index: [[#NFA+24]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -420,7 +419,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 25 +; SYM-NEXT: Index: [[#NFA+25]] ; SYM-NEXT: Name: TIUninit ; SYM-NEXT: Value (RelocatableAddress): 0x8C ; SYM-NEXT: Section: .data @@ -428,7 +427,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 26 +; SYM-NEXT: Index: [[#NFA+26]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -440,7 +439,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 27 +; SYM-NEXT: Index: [[#NFA+27]] ; SYM-NEXT: Name: .TGInit ; SYM-NEXT: Value (RelocatableAddress): 0x90 ; SYM-NEXT: Section: .data @@ -448,7 +447,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 28 +; SYM-NEXT: Index: [[#NFA+28]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -460,7 +459,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 29 +; SYM-NEXT: Index: [[#NFA+29]] ; SYM-NEXT: Name: TGInit ; SYM-NEXT: Value (RelocatableAddress): 0x94 ; SYM-NEXT: Section: .data @@ -468,7 +467,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 30 +; SYM-NEXT: Index: [[#NFA+30]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -480,7 +479,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 31 +; SYM-NEXT: Index: [[#NFA+31]] ; SYM-NEXT: Name: GInit ; SYM-NEXT: Value (RelocatableAddress): 0x98 ; SYM-NEXT: Section: .data @@ -488,7 +487,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 32 +; SYM-NEXT: Index: [[#NFA+32]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -500,7 +499,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 33 +; SYM-NEXT: Index: [[#NFA+33]] ; SYM-NEXT: Name: .tdata ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: .tdata @@ -508,7 +507,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 34 +; SYM-NEXT: Index: [[#NFA+34]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -520,7 +519,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 35 +; SYM-NEXT: Index: [[#NFA+35]] ; SYM-NEXT: Name: TGInit ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: .tdata @@ -528,8 +527,8 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 36 -; SYM-NEXT: ContainingCsectSymbolIndex: 33 +; SYM-NEXT: Index: [[#NFA+36]] +; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+33]] ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 ; SYM-NEXT: SymbolAlignmentLog2: 0 @@ -540,7 +539,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 37 +; SYM-NEXT: Index: [[#NFA+37]] ; SYM-NEXT: Name: TIUninit ; SYM-NEXT: Value (RelocatableAddress): 0x4 ; SYM-NEXT: Section: .tbss @@ -548,7 +547,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 38 +; SYM-NEXT: Index: [[#NFA+38]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -563,34 +562,34 @@ entry: ; DIS: {{.*}}aix-tls-xcoff-reloc.ll.tmp.o: file format aixcoff-rs6000 ; DIS: Disassembly of section .text: -; DIS: 00000000 (idx: 5) .storesTIUninit: +; DIS: 00000000 (idx: [[#NFA+5]]) .storesTIUninit: ; DIS-NEXT: mflr 0 ; DIS-NEXT: stwu 1, -32(1) ; DIS-NEXT: mr 6, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 3, 0(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 23) .TIUninit[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+23]]) .TIUninit[TC] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 4(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 25) TIUninit[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+25]]) TIUninit[TC] ; DIS-NEXT: stw 0, 40(1) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0 -; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: 1) .__tls_get_addr[PR] +; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: [[#NFA+1]]) .__tls_get_addr[PR] ; DIS-NEXT: stw 6, 0(3) ; DIS-NEXT: addi 1, 1, 32 ; DIS-NEXT: lwz 0, 8(1) ; DIS-NEXT: mtlr 0 ; DIS-NEXT: blr -; DIS: 00000030 (idx: 7) .loadsTGInit: +; DIS: 00000030 (idx: [[#NFA+7]]) .loadsTGInit: ; DIS-NEXT: mflr 0 ; DIS-NEXT: stwu 1, -32(1) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 3, 8(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 27) .TGInit[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+27]]) .TGInit[TC] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 12(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 29) TGInit[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+29]]) TGInit[TC] ; DIS-NEXT: stw 0, 40(1) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0 -; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: 1) .__tls_get_addr[PR] +; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: [[#NFA+1]]) .__tls_get_addr[PR] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 16(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 31) GInit[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+31]]) GInit[TC] ; DIS-NEXT: lwz 3, 0(3) ; DIS-NEXT: lwz 4, 0(4) ; DIS-NEXT: add 3, 4, 3 @@ -598,46 +597,46 @@ entry: ; DIS-NEXT: lwz 0, 8(1) ; DIS-NEXT: mtlr 0 ; DIS-NEXT: blr -; DIS: 00000068 (idx: 11) const_ivar: +; DIS: 00000068 (idx: [[#NFA+11]]) const_ivar: ; DIS-NEXT: 68: 00 00 00 06 ; DIS: Disassembly of section .data: -; DIS: 0000006c (idx: 15) GInit: +; DIS: 0000006c (idx: [[#NFA+15]]) GInit: ; DIS-NEXT: 6c: 00 00 00 01 -; DIS: 00000070 (idx: 17) storesTIUninit[DS]: +; DIS: 00000070 (idx: [[#NFA+17]]) storesTIUninit[DS]: ; DIS-NEXT: 70: 00 00 00 00 -; DIS-NEXT: 00000070: R_POS (idx: 5) .storesTIUninit +; DIS-NEXT: 00000070: R_POS (idx: [[#NFA+5]]) .storesTIUninit ; DIS-NEXT: 74: 00 00 00 88 -; DIS-NEXT: 00000074: R_POS (idx: 21) TOC[TC0] +; DIS-NEXT: 00000074: R_POS (idx: [[#NFA+21]]) TOC[TC0] ; DIS-NEXT: 78: 00 00 00 00 -; DIS: 0000007c (idx: 19) loadsTGInit[DS]: +; DIS: 0000007c (idx: [[#NFA+19]]) loadsTGInit[DS]: ; DIS-NEXT: 7c: 00 00 00 30 -; DIS-NEXT: 0000007c: R_POS (idx: 7) .loadsTGInit +; DIS-NEXT: 0000007c: R_POS (idx: [[#NFA+7]]) .loadsTGInit ; DIS-NEXT: 80: 00 00 00 88 -; DIS-NEXT: 00000080: R_POS (idx: 21) TOC[TC0] +; DIS-NEXT: 00000080: R_POS (idx: [[#NFA+21]]) TOC[TC0] ; DIS-NEXT: 84: 00 00 00 00 -; DIS: 00000088 (idx: 23) .TIUninit[TC]: +; DIS: 00000088 (idx: [[#NFA+23]]) .TIUninit[TC]: ; DIS-NEXT: 88: 00 00 00 00 -; DIS-NEXT: 00000088: R_TLSM (idx: 37) TIUninit[UL] -; DIS: 0000008c (idx: 25) TIUninit[TC]: +; DIS-NEXT: 00000088: R_TLSM (idx: [[#NFA+37]]) TIUninit[UL] +; DIS: 0000008c (idx: [[#NFA+25]]) TIUninit[TC]: ; DIS-NEXT: 8c: 00 00 00 04 -; DIS-NEXT: 0000008c: R_TLS (idx: 37) TIUninit[UL] -; DIS: 00000090 (idx: 27) .TGInit[TC]: +; DIS-NEXT: 0000008c: R_TLS (idx: [[#NFA+37]]) TIUninit[UL] +; DIS: 00000090 (idx: [[#NFA+27]]) .TGInit[TC]: ; DIS-NEXT: 90: 00 00 00 00 -; DIS-NEXT: 00000090: R_TLSM (idx: 35) TGInit -; DIS: 00000094 (idx: 29) TGInit[TC]: +; DIS-NEXT: 00000090: R_TLSM (idx: [[#NFA+35]]) TGInit +; DIS: 00000094 (idx: [[#NFA+29]]) TGInit[TC]: ; DIS-NEXT: 94: 00 00 00 00 -; DIS-NEXT: 00000094: R_TLS (idx: 35) TGInit -; DIS: 00000098 (idx: 31) GInit[TC]: +; DIS-NEXT: 00000094: R_TLS (idx: [[#NFA+35]]) TGInit +; DIS: 00000098 (idx: [[#NFA+31]]) GInit[TC]: ; DIS-NEXT: 98: 00 00 00 6c -; DIS-NEXT: 00000098: R_POS (idx: 15) GInit +; DIS-NEXT: 00000098: R_POS (idx: [[#NFA+15]]) GInit ; DIS: Disassembly of section .tdata: -; DIS: 00000000 (idx: 35) TGInit: +; DIS: 00000000 (idx: [[#NFA+35]]) TGInit: ; DIS-NEXT: 0: 00 00 00 01 ; DIS: Disassembly of section .tbss: -; DIS: 00000004 (idx: 37) TIUninit[UL]: +; DIS: 00000004 (idx: [[#NFA+37]]) TIUninit[UL]: ; DIS-NEXT: ... attributes #0 = { nofree norecurse nounwind willreturn writeonly "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-spe,-vsx" } diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-variables.ll b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-variables.ll index 3bbdadcdb7ba..f9a1a6161776 100644 --- a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-variables.ll +++ b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-variables.ll @@ -3,16 +3,16 @@ ; RUN: llc -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s ; RUN: llvm-readobj --section-headers %t.o | FileCheck --check-prefix=SECTION %s ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefixes=SYMS,SYMS-DATASECT %s -; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefixes=OBJDUMP-DATASECT %s +; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefixes=OBJDUMP-DATASECT %s ; RUN: llc -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s ; RUN: llvm-readobj --section-headers %t.o | FileCheck --check-prefix=SECTION %s ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefixes=SYMS,SYMS-NODATASECT %s -; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefixes=OBJDUMP-NODATASECT %s +; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefixes=OBJDUMP-NODATASECT %s ;; FIXME: currently only fileHeader and sectionHeaders are supported in XCOFF64. -; SECTION: File: {{.*}}aix-tls-xcoff-variables.ll.tmp.o +; SECTION: File: ; SECTION-NEXT: Format: aixcoff-rs6000 ; SECTION-NEXT: Arch: powerpc ; SECTION-NEXT: AddressSize: 32bit @@ -59,22 +59,21 @@ ; SECTION-NEXT: ] -; SYMS: File: {{.*}}aix-tls-xcoff-variables.ll.tmp.o +; SYMS: File: ; SYMS-NEXT: Format: aixcoff-rs6000 ; SYMS-NEXT: Arch: powerpc ; SYMS-NEXT: AddressSize: 32bit ; SYMS-NEXT: Symbols [ ; SYMS-NEXT: Symbol { ; SYMS-NEXT: Index: 0 -; SYMS-NEXT: Name: +; SYMS-NEXT: Name: .file ; SYMS-NEXT: Value (SymbolTableIndex): 0x0 ; SYMS-NEXT: Section: N_DEBUG ; SYMS-NEXT: Source Language ID: TB_CPLUSPLUS (0x9) ; SYMS-NEXT: CPU Version ID: TCPU_COM (0x3) ; SYMS-NEXT: StorageClass: C_FILE (0x67) -; SYMS-NEXT: NumberOfAuxEntries: 0 -; SYMS-NEXT: } -; SYMS-NEXT: Symbol { +; SYMS-NEXT: NumberOfAuxEntries: 2 +; SYMS: Symbol { ; SYMS-NEXT: Index: [[#INDX:]] ; SYMS-NEXT: Name: tls_global_int_external_uninitialized ; SYMS-NEXT: Value (RelocatableAddress): 0x0 @@ -531,100 +530,100 @@ ; OBJDUMP-DATASECT: Disassembly of section .text: ; OBJDUMP-DATASECT-EMPTY: -; OBJDUMP-DATASECT-NEXT: 00000000 (idx: 7) const_ivar[RO]: +; OBJDUMP-DATASECT-NEXT: 00000000 (idx: [[#NFA+7]]) const_ivar[RO]: ; OBJDUMP-DATASECT-NEXT: 0: 00 00 00 06 ; OBJDUMP-DATASECT-EMPTY: ; OBJDUMP-DATASECT-NEXT: Disassembly of section .tdata: ; OBJDUMP-DATASECT-EMPTY: -; OBJDUMP-DATASECT-NEXT: 00000000 (idx: 11) tls_global_alias_int_external_val_initialized: +; OBJDUMP-DATASECT-NEXT: 00000000 (idx: [[#NFA+11]]) tls_global_alias_int_external_val_initialized: ; OBJDUMP-DATASECT-NEXT: 0: 00 00 00 01 ; OBJDUMP-DATASECT-EMPTY: -; OBJDUMP-DATASECT-NEXT: 00000004 (idx: 13) tls_global_int_external_zero_initialized[TL]: +; OBJDUMP-DATASECT-NEXT: 00000004 (idx: [[#NFA+13]]) tls_global_int_external_zero_initialized[TL]: ; OBJDUMP-DATASECT-NEXT: 4: 00 00 00 00 ; OBJDUMP-DATASECT-EMPTY: -; OBJDUMP-DATASECT-NEXT: 00000008 (idx: 15) tls_global_int_local_val_initialized[TL]: +; OBJDUMP-DATASECT-NEXT: 00000008 (idx: [[#NFA+15]]) tls_global_int_local_val_initialized[TL]: ; OBJDUMP-DATASECT-NEXT: 8: 00 00 00 02 ; OBJDUMP-DATASECT-EMPTY: -; OBJDUMP-DATASECT-NEXT: 0000000c (idx: 17) tls_global_int_weak_zero_initialized[TL]: +; OBJDUMP-DATASECT-NEXT: 0000000c (idx: [[#NFA+17]]) tls_global_int_weak_zero_initialized[TL]: ; OBJDUMP-DATASECT-NEXT: c: 00 00 00 00 ; OBJDUMP-DATASECT-EMPTY: -; OBJDUMP-DATASECT-NEXT: 00000010 (idx: 19) tls_global_int_weak_val_initialized[TL]: +; OBJDUMP-DATASECT-NEXT: 00000010 (idx: [[#NFA+19]]) tls_global_int_weak_val_initialized[TL]: ; OBJDUMP-DATASECT-NEXT: 10: 00 00 00 01 ; OBJDUMP-DATASECT-NEXT: 14: 00 00 00 00 ; OBJDUMP-DATASECT-EMPTY: -; OBJDUMP-DATASECT-NEXT: 00000018 (idx: 21) tls_global_long_long_internal_val_initialized[TL]: +; OBJDUMP-DATASECT-NEXT: 00000018 (idx: [[#NFA+21]]) tls_global_long_long_internal_val_initialized[TL]: ; OBJDUMP-DATASECT-NEXT: 18: 00 00 00 00 ; OBJDUMP-DATASECT-NEXT: 1c: 00 00 00 01 ; OBJDUMP-DATASECT-EMPTY: -; OBJDUMP-DATASECT-NEXT: 00000020 (idx: 23) tls_global_long_long_weak_val_initialized[TL]: +; OBJDUMP-DATASECT-NEXT: 00000020 (idx: [[#NFA+23]]) tls_global_long_long_weak_val_initialized[TL]: ; OBJDUMP-DATASECT-NEXT: 20: 00 00 00 00 ; OBJDUMP-DATASECT-NEXT: 24: 00 00 00 01 ; OBJDUMP-DATASECT-EMPTY: -; OBJDUMP-DATASECT-NEXT: 00000028 (idx: 25) tls_global_long_long_weak_zero_initialized[TL]: +; OBJDUMP-DATASECT-NEXT: 00000028 (idx: [[#NFA+25]]) tls_global_long_long_weak_zero_initialized[TL]: ; OBJDUMP-DATASECT-NEXT: ... ; OBJDUMP-DATASECT-EMPTY: ; OBJDUMP-DATASECT-NEXT: Disassembly of section .tbss: ; OBJDUMP-DATASECT-EMPTY: -; OBJDUMP-DATASECT-NEXT: 00000030 (idx: 27) tls_global_int_local_zero_initialized[UL]: +; OBJDUMP-DATASECT-NEXT: 00000030 (idx: [[#NFA+27]]) tls_global_int_local_zero_initialized[UL]: ; OBJDUMP-DATASECT-NEXT: ... ; OBJDUMP-DATASECT-EMPTY: -; OBJDUMP-DATASECT-NEXT: 00000034 (idx: 29) tls_global_int_common_zero_initialized[UL]: +; OBJDUMP-DATASECT-NEXT: 00000034 (idx: [[#NFA+29]]) tls_global_int_common_zero_initialized[UL]: ; OBJDUMP-DATASECT-NEXT: ... ; OBJDUMP-DATASECT-EMPTY: -; OBJDUMP-DATASECT-NEXT: 00000038 (idx: 31) tls_global_double_common_zero_initialized[UL] +; OBJDUMP-DATASECT-NEXT: 00000038 (idx: [[#NFA+31]]) tls_global_double_common_zero_initialized[UL] ; OBJDUMP-DATASECT-NEXT: ... ; OBJDUMP-DATASECT-EMPTY: -; OBJDUMP-DATASECT-NEXT: 00000040 (idx: 33) tls_global_long_long_internal_zero_initialized[UL]: +; OBJDUMP-DATASECT-NEXT: 00000040 (idx: [[#NFA+33]]) tls_global_long_long_internal_zero_initialized[UL]: ; OBJDUMP-DATASECT-NEXT: ... ; OBJDUMP-NODATASECT: Disassembly of section .text: ; OBJDUMP-NODATASECT-EMPTY: -; OBJDUMP-NODATASECT-NEXT: 00000000 (idx: 9) const_ivar: +; OBJDUMP-NODATASECT-NEXT: 00000000 (idx: [[#NFA+9]]) const_ivar: ; OBJDUMP-NODATASECT-NEXT: 0: 00 00 00 06 ; OBJDUMP-NODATASECT-EMPTY: ; OBJDUMP-NODATASECT-NEXT: Disassembly of section .tdata: ; OBJDUMP-NODATASECT-EMPTY: -; OBJDUMP-NODATASECT: 00000000 (idx: 13) tls_global_int_external_val_initialized: +; OBJDUMP-NODATASECT: 00000000 (idx: [[#NFA+13]]) tls_global_int_external_val_initialized: ; OBJDUMP-NODATASECT-NEXT: 0: 00 00 00 01 ; OBJDUMP-NODATASECT-EMPTY: -; OBJDUMP-NODATASECT-NEXT: 00000004 (idx: 17) tls_global_int_external_zero_initialized: +; OBJDUMP-NODATASECT-NEXT: 00000004 (idx: [[#NFA+17]]) tls_global_int_external_zero_initialized: ; OBJDUMP-NODATASECT-NEXT: 4: 00 00 00 00 ; OBJDUMP-NODATASECT-EMPTY: -; OBJDUMP-NODATASECT-NEXT: 00000008 (idx: 19) tls_global_int_local_val_initialized: +; OBJDUMP-NODATASECT-NEXT: 00000008 (idx: [[#NFA+19]]) tls_global_int_local_val_initialized: ; OBJDUMP-NODATASECT-NEXT: 8: 00 00 00 02 ; OBJDUMP-NODATASECT-EMPTY: -; OBJDUMP-NODATASECT-NEXT: 0000000c (idx: 21) tls_global_int_weak_zero_initialized: +; OBJDUMP-NODATASECT-NEXT: 0000000c (idx: [[#NFA+21]]) tls_global_int_weak_zero_initialized: ; OBJDUMP-NODATASECT-NEXT: c: 00 00 00 00 ; OBJDUMP-NODATASECT-EMPTY: -; OBJDUMP-NODATASECT-NEXT: 00000010 (idx: 23) tls_global_int_weak_val_initialized: +; OBJDUMP-NODATASECT-NEXT: 00000010 (idx: [[#NFA+23]]) tls_global_int_weak_val_initialized: ; OBJDUMP-NODATASECT-NEXT: 10: 00 00 00 01 ; OBJDUMP-NODATASECT-NEXT: 14: 00 00 00 00 ; OBJDUMP-NODATASECT-EMPTY: -; OBJDUMP-NODATASECT-NEXT: 00000018 (idx: 25) tls_global_long_long_internal_val_initialized: +; OBJDUMP-NODATASECT-NEXT: 00000018 (idx: [[#NFA+25]]) tls_global_long_long_internal_val_initialized: ; OBJDUMP-NODATASECT-NEXT: 18: 00 00 00 00 ; OBJDUMP-NODATASECT-NEXT: 1c: 00 00 00 01 ; OBJDUMP-NODATASECT-EMPTY: -; OBJDUMP-NODATASECT-NEXT: 00000020 (idx: 27) tls_global_long_long_weak_val_initialized: +; OBJDUMP-NODATASECT-NEXT: 00000020 (idx: [[#NFA+27]]) tls_global_long_long_weak_val_initialized: ; OBJDUMP-NODATASECT-NEXT: 20: 00 00 00 00 ; OBJDUMP-NODATASECT-NEXT: 24: 00 00 00 01 ; OBJDUMP-NODATASECT-EMPTY: -; OBJDUMP-NODATASECT-NEXT: 00000028 (idx: 29) tls_global_long_long_weak_zero_initialized: +; OBJDUMP-NODATASECT-NEXT: 00000028 (idx: [[#NFA+29]]) tls_global_long_long_weak_zero_initialized: ; OBJDUMP-NODATASECT-NEXT: ... ; OBJDUMP-NODATASECT-EMPTY: ; OBJDUMP-NODATASECT-NEXT: Disassembly of section .tbss: ; OBJDUMP-NODATASECT-EMPTY: -; OBJDUMP-NODATASECT-NEXT: 00000030 (idx: 31) tls_global_int_local_zero_initialized[UL]: +; OBJDUMP-NODATASECT-NEXT: 00000030 (idx: [[#NFA+31]]) tls_global_int_local_zero_initialized[UL]: ; OBJDUMP-NODATASECT-NEXT: ... ; OBJDUMP-NODATASECT-EMPTY: -; OBJDUMP-NODATASECT-NEXT: 00000034 (idx: 33) tls_global_int_common_zero_initialized[UL]: +; OBJDUMP-NODATASECT-NEXT: 00000034 (idx: [[#NFA+33]]) tls_global_int_common_zero_initialized[UL]: ; OBJDUMP-NODATASECT-NEXT: ... ; OBJDUMP-NODATASECT-EMPTY: -; OBJDUMP-NODATASECT-NEXT: 00000038 (idx: 35) tls_global_double_common_zero_initialized[UL]: +; OBJDUMP-NODATASECT-NEXT: 00000038 (idx: [[#NFA+35]]) tls_global_double_common_zero_initialized[UL]: ; OBJDUMP-NODATASECT-NEXT: ... ; OBJDUMP-NODATASECT-EMPTY: -; OBJDUMP-NODATASECT-NEXT: 00000040 (idx: 37) tls_global_long_long_internal_zero_initialized[UL]: +; OBJDUMP-NODATASECT-NEXT: 00000040 (idx: [[#NFA+37]]) tls_global_long_long_internal_zero_initialized[UL]: ; OBJDUMP-NODATASECT-NEXT: ... @tls_global_int_external_val_initialized = thread_local global i32 1, align 4 diff --git a/llvm/test/CodeGen/PowerPC/aix-user-defined-memcpy.ll b/llvm/test/CodeGen/PowerPC/aix-user-defined-memcpy.ll index 6891637b8fcb..4f1735a74355 100644 --- a/llvm/test/CodeGen/PowerPC/aix-user-defined-memcpy.ll +++ b/llvm/test/CodeGen/PowerPC/aix-user-defined-memcpy.ll @@ -1,12 +1,12 @@ ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \ ; RUN: -mattr=-altivec -filetype=obj -xcoff-traceback-table=false -o %t.o < %s -; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=32-SYM %s +; RUN: llvm-readobj --syms %t.o | FileCheck -D#NFA=2 --check-prefix=32-SYM %s -; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck \ +; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck -D#NFA=2 \ ; RUN: --check-prefix=32-REL %s -; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=32-DIS %s +; RUN: llvm-objdump -D %t.o | FileCheck -D#NFA=2 --check-prefix=32-DIS %s ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -mcpu=pwr4 -mattr=-altivec < %s | FileCheck %s @@ -45,7 +45,7 @@ declare void @llvm.memcpy.p0.p0.i32(ptr nocapture writeonly, ptr nocapture reado ; 32-SYM-NEXT: StorageClass: C_EXT (0x2) ; 32-SYM-NEXT: NumberOfAuxEntries: 1 ; 32-SYM-NEXT: CSECT Auxiliary Entry { -; 32-SYM-NEXT: Index: 2 +; 32-SYM-NEXT: Index: [[#NFA+2]] ; 32-SYM-NEXT: SectionLen: 0 ; 32-SYM-NEXT: ParameterHashIndex: 0x0 ; 32-SYM-NEXT: TypeChkSectNum: 0x0 @@ -64,8 +64,8 @@ declare void @llvm.memcpy.p0.p0.i32(ptr nocapture writeonly, ptr nocapture reado ; 32-SYM-NEXT: StorageClass: C_EXT (0x2) ; 32-SYM-NEXT: NumberOfAuxEntries: 1 ; 32-SYM-NEXT: CSECT Auxiliary Entry { -; 32-SYM-NEXT: Index: 6 -; 32-SYM-NEXT: ContainingCsectSymbolIndex: 3 +; 32-SYM-NEXT: Index: [[#NFA+6]] +; 32-SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+3]] ; 32-SYM-NEXT: ParameterHashIndex: 0x0 ; 32-SYM-NEXT: TypeChkSectNum: 0x0 ; 32-SYM-NEXT: SymbolAlignmentLog2: 0 @@ -82,7 +82,7 @@ declare void @llvm.memcpy.p0.p0.i32(ptr nocapture writeonly, ptr nocapture reado ; 32-REL-NEXT: Section (index: 1) .text { ; 32-REL-NEXT: Relocation { ; 32-REL-NEXT: Virtual Address: 0x1C -; 32-REL-NEXT: Symbol: .___memmove (1) +; 32-REL-NEXT: Symbol: .___memmove ([[#NFA+1]]) ; 32-REL-NEXT: IsSigned: Yes ; 32-REL-NEXT: FixupBitValue: 0 ; 32-REL-NEXT: Length: 26 @@ -92,7 +92,7 @@ declare void @llvm.memcpy.p0.p0.i32(ptr nocapture writeonly, ptr nocapture reado ; 32-REL-NEXT: Section (index: 2) .data { ; 32-REL-NEXT: Relocation { ; 32-REL-NEXT: Virtual Address: 0x34 -; 32-REL-NEXT: Symbol: .memcpy (5) +; 32-REL-NEXT: Symbol: .memcpy ([[#NFA+5]]) ; 32-REL-NEXT: IsSigned: No ; 32-REL-NEXT: FixupBitValue: 0 ; 32-REL-NEXT: Length: 32 @@ -100,7 +100,7 @@ declare void @llvm.memcpy.p0.p0.i32(ptr nocapture writeonly, ptr nocapture reado ; 32-REL-NEXT: } ; 32-REL-NEXT: Relocation { ; 32-REL-NEXT: Virtual Address: 0x38 -; 32-REL-NEXT: Symbol: TOC (13) +; 32-REL-NEXT: Symbol: TOC ([[#NFA+13]]) ; 32-REL-NEXT: IsSigned: No ; 32-REL-NEXT: FixupBitValue: 0 ; 32-REL-NEXT: Length: 32 @@ -108,7 +108,7 @@ declare void @llvm.memcpy.p0.p0.i32(ptr nocapture writeonly, ptr nocapture reado ; 32-REL-NEXT: } ; 32-REL-NEXT: Relocation { ; 32-REL-NEXT: Virtual Address: 0x40 -; 32-REL-NEXT: Symbol: .call_memcpy (7) +; 32-REL-NEXT: Symbol: .call_memcpy ([[#NFA+7]]) ; 32-REL-NEXT: IsSigned: No ; 32-REL-NEXT: FixupBitValue: 0 ; 32-REL-NEXT: Length: 32 @@ -116,7 +116,7 @@ declare void @llvm.memcpy.p0.p0.i32(ptr nocapture writeonly, ptr nocapture reado ; 32-REL-NEXT: } ; 32-REL-NEXT: Relocation { ; 32-REL-NEXT: Virtual Address: 0x44 -; 32-REL-NEXT: Symbol: TOC (13) +; 32-REL-NEXT: Symbol: TOC ([[#NFA+13]]) ; 32-REL-NEXT: IsSigned: No ; 32-REL-NEXT: FixupBitValue: 0 ; 32-REL-NEXT: Length: 32 diff --git a/llvm/test/CodeGen/PowerPC/aix-weak.ll b/llvm/test/CodeGen/PowerPC/aix-weak.ll index 84ef83a9b966..7bf80ad19e9e 100644 --- a/llvm/test/CodeGen/PowerPC/aix-weak.ll +++ b/llvm/test/CodeGen/PowerPC/aix-weak.ll @@ -100,16 +100,15 @@ entry: ; CHECKSYM: Symbols [ ; CHECKSYM-NEXT: Symbol { ; CHECKSYM-NEXT: Index: 0 -; CHECKSYM-NEXT: Name: +; CHECKSYM-NEXT: Name: .file ; CHECKSYM-NEXT: Value (SymbolTableIndex): 0x0 ; CHECKSYM-NEXT: Section: N_DEBUG ; CHECKSYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9) ; CHECKSYM32-NEXT: CPU Version ID: TCPU_COM (0x3) ; CHECKSYM64-NEXT: CPU Version ID: TCPU_PPC64 (0x2) ; CHECKSYM-NEXT: StorageClass: C_FILE (0x67) -; CHECKSYM-NEXT: NumberOfAuxEntries: 0 -; CHECKSYM-NEXT: } -; CHECKSYM-NEXT: Symbol { +; CHECKSYM-NEXT: NumberOfAuxEntries: 2 +; CHECKSYM: Symbol { ; CHECKSYM-NEXT: Index: [[#Index:]] ; CHECKSYM-NEXT: Name: ; CHECKSYM-NEXT: Value (RelocatableAddress): 0x0 diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-cold.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-cold.ll index db6071653b6b..6464257c6f26 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-cold.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-cold.ll @@ -2,7 +2,7 @@ ; RUN: llvm-objdump --syms %t.o | FileCheck %s ; CHECK: SYMBOL TABLE: -; CHECK-NEXT: 0000000000000000 df *DEBUG* 0000000000000000 +; CHECK-NEXT: 0000000000000000 df *DEBUG* 0000000000000000 .file ; CHECK-NEXT: 0000000000000000 l .text 000000000000001e ; CHECK-NEXT: 0000000000000000 g F .text (csect: ) 0000000000000000 .cold_fun ; CHECK-NEXT: 0000000000000020 g O .data 0000000000000018 cold_fun diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll index 9072e98aecb2..19c623c50213 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll @@ -5,7 +5,7 @@ ; RUN: FileCheck --check-prefixes=CHECK,CHECK64 %s ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -filetype=obj -data-sections -xcoff-traceback-table=false -o %t.o < %s -; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s +; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=CHECKOBJ %s ; RUN: llvm-readobj -s %t.o | FileCheck --check-prefix=CHECKSYM %s ;; Test to see if the default is correct for -data-sections on AIX. @@ -16,7 +16,7 @@ ; RUN: FileCheck --check-prefixes=CHECK,CHECK64 %s ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -xcoff-traceback-table=false -filetype=obj -o %t.o < %s -; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s +; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=CHECKOBJ %s ; RUN: llvm-readobj -s %t.o | FileCheck --check-prefix=CHECKSYM %s ;; Test to see if the default is correct for -data-sections on AIX. @@ -28,7 +28,7 @@ ; RUN: FileCheck --check-prefixes=CHECK,CHECK64 %s ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -xcoff-traceback-table=false -filetype=obj -o %t.o < %s -; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s +; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=CHECKOBJ %s ; RUN: llvm-readobj -s %t.o | FileCheck --check-prefix=CHECKSYM %s @ivar = local_unnamed_addr global i32 35, align 4 @@ -90,50 +90,50 @@ entry: ; CHECK-NEXT: L..C3: ; CHECK-NEXT: .tc f[TC],f[RW] -; CHECKOBJ: 00000038 (idx: 7) const_ivar[RO]: +; CHECKOBJ: 00000038 (idx: [[#NFA+7]]) const_ivar[RO]: ; CHECKOBJ-NEXT: 38: 00 00 00 23 ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 0000003c (idx: 9) L...str[RO]: +; CHECKOBJ-NEXT: 0000003c (idx: [[#NFA+9]]) L...str[RO]: ; CHECKOBJ-NEXT: 3c: 61 62 63 64 ; CHECKOBJ-NEXT: 40: 65 66 67 68 ; CHECKOBJ-NEXT: 44: 00 00 00 00 ; CHECKOBJ-EMPTY: ; CHECKOBJ-NEXT: Disassembly of section .data: ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 00000048 (idx: 11) ivar[RW]: +; CHECKOBJ-NEXT: 00000048 (idx: [[#NFA+11]]) ivar[RW]: ; CHECKOBJ-NEXT: 48: 00 00 00 23 ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 0000004c (idx: 13) p[RW]: +; CHECKOBJ-NEXT: 0000004c (idx: [[#NFA+13]]) p[RW]: ; CHECKOBJ-NEXT: 4c: 00 00 00 3c ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 00000050 (idx: 15) foo[DS]: +; CHECKOBJ-NEXT: 00000050 (idx: [[#NFA+15]]) foo[DS]: ; CHECKOBJ-NEXT: 50: 00 00 00 00 ; CHECKOBJ-NEXT: 54: 00 00 00 68 ; CHECKOBJ-NEXT: 58: 00 00 00 00 ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 0000005c (idx: 17) bar[DS]: +; CHECKOBJ-NEXT: 0000005c (idx: [[#NFA+17]]) bar[DS]: ; CHECKOBJ-NEXT: 5c: 00 00 00 10 ; CHECKOBJ-NEXT: 60: 00 00 00 68 ; CHECKOBJ-NEXT: 64: 00 00 00 00 ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 00000068 (idx: 21) p[TC]: +; CHECKOBJ-NEXT: 00000068 (idx: [[#NFA+21]]) p[TC]: ; CHECKOBJ-NEXT: 68: 00 00 00 4c ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 0000006c (idx: 23) ivar[TC]: +; CHECKOBJ-NEXT: 0000006c (idx: [[#NFA+23]]) ivar[TC]: ; CHECKOBJ-NEXT: 6c: 00 00 00 48 ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 00000070 (idx: 25) a[TC]: +; CHECKOBJ-NEXT: 00000070 (idx: [[#NFA+25]]) a[TC]: ; CHECKOBJ-NEXT: 70: 00 00 00 78 ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 00000074 (idx: 27) f[TC]: +; CHECKOBJ-NEXT: 00000074 (idx: [[#NFA+27]]) f[TC]: ; CHECKOBJ-NEXT: 74: 00 00 00 7c ; CHECKOBJ-EMPTY: ; CHECKOBJ-NEXT: Disassembly of section .bss: ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 00000078 (idx: 29) a[RW]: +; CHECKOBJ-NEXT: 00000078 (idx: [[#NFA+29]]) a[RW]: ; CHECKOBJ-NEXT: ... ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 0000007c (idx: 31) f[RW]: +; CHECKOBJ-NEXT: 0000007c (idx: [[#NFA+31]]) f[RW]: ; CHECKOBJ-NEXT: ... diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll index 58958e399cb0..de937386b8b7 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll @@ -147,7 +147,7 @@ ; CHECK-NEXT: .comm over_aligned_comm[RW],8,5 ; CHECK-NEXT: .comm array[RW],33,0 -; OBJ: File: {{.*}}aix-xcoff-data.ll.tmp.o +; OBJ: File: ; OBJ-NEXT: Format: aixcoff-rs6000 ; OBJ-NEXT: Arch: powerpc ; OBJ-NEXT: AddressSize: 32bit @@ -156,7 +156,7 @@ ; OBJ-NEXT: NumberOfSections: 3 ; OBJ-NEXT: TimeStamp: ; OBJ-NEXT: SymbolTableOffset: 0x10C -; OBJ-NEXT: SymbolTableEntries: 45 +; OBJ-NEXT: SymbolTableEntries: 47 ; OBJ-NEXT: OptionalHeaderSize: 0x0 ; OBJ-NEXT: Flags: 0x0 ; OBJ-NEXT: } @@ -208,14 +208,26 @@ ; SYMS: Symbols [ ; SYMS-NEXT: Symbol { ; SYMS-NEXT: Index: 0 -; SYMS-NEXT: Name: +; SYMS-NEXT: Name: .file ; SYMS-NEXT: Value (SymbolTableIndex): 0x0 ; SYMS-NEXT: Section: N_DEBUG ; SYMS-NEXT: Source Language ID: TB_CPLUSPLUS (0x9) ; SYMS32-NEXT: CPU Version ID: TCPU_COM (0x3) ; SYMS64-NEXT: CPU Version ID: TCPU_PPC64 (0x2) ; SYMS-NEXT: StorageClass: C_FILE (0x67) -; SYMS-NEXT: NumberOfAuxEntries: 0 +; SYMS-NEXT: NumberOfAuxEntries: 2 +; SYMS-NEXT: File Auxiliary Entry { +; SYMS-NEXT: Index: 1 +; SYMS-NEXT: Name: +; SYMS-NEXT: Type: XFT_FN (0x0) +; SYMS64-NEXT: Auxiliary Type: AUX_FILE (0xFC) +; SYMS-NEXT: } +; SYMS-NEXT: File Auxiliary Entry { +; SYMS-NEXT: Index: 2 +; SYMS-NEXT: Name: LLVM +; SYMS-NEXT: Type: XFT_CV (0x2) +; SYMS64-NEXT: Auxiliary Type: AUX_FILE (0xFC) +; SYMS-NEXT: } ; SYMS-NEXT: } ; SYMS-NEXT: Symbol { ; SYMS-NEXT: Index: [[#INDX:]] @@ -710,7 +722,7 @@ ; OBJ64-NEXT: NumberOfSections: 3 ; OBJ64-NEXT: TimeStamp: None (0x0) ; OBJ64-NEXT: SymbolTableOffset: 0x170 -; OBJ64-NEXT: SymbolTableEntries: 45 +; OBJ64-NEXT: SymbolTableEntries: 47 ; OBJ64-NEXT: OptionalHeaderSize: 0x0 ; OBJ64-NEXT: Flags: 0x0 ; OBJ64-NEXT: } diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section-debug.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section-debug.ll index 01d0aa9e173f..bc6e9f350198 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section-debug.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section-debug.ll @@ -47,7 +47,7 @@ define dso_local void @test__trap_annotation_debug(i32 %a) !dbg !4 { ; SYMS32-NEXT: } ; SYMS32-NEXT: CSECT Auxiliary Entry { ; SYMS32-NEXT: Index: [[#IND+2]] -; SYMS32-NEXT: ContainingCsectSymbolIndex: 1 +; SYMS32-NEXT: ContainingCsectSymbolIndex: [[#IND-2]] ; SYMS32-NEXT: ParameterHashIndex: 0x0 ; SYMS32-NEXT: TypeChkSectNum: 0x0 ; SYMS32-NEXT: SymbolAlignmentLog2: 0 @@ -74,7 +74,7 @@ define dso_local void @test__trap_annotation_debug(i32 %a) !dbg !4 { ; SYMS32-NEXT: } ; SYMS32-NEXT: CSECT Auxiliary Entry { ; SYMS32-NEXT: Index: [[#IND+5]] -; SYMS32-NEXT: ContainingCsectSymbolIndex: 1 +; SYMS32-NEXT: ContainingCsectSymbolIndex: [[#IND-2]] ; SYMS32-NEXT: ParameterHashIndex: 0x0 ; SYMS32-NEXT: TypeChkSectNum: 0x0 ; SYMS32-NEXT: SymbolAlignmentLog2: 0 @@ -107,7 +107,7 @@ define dso_local void @test__trap_annotation_debug(i32 %a) !dbg !4 { ; SYMS64-NEXT: } ; SYMS64-NEXT: CSECT Auxiliary Entry { ; SYMS64-NEXT: Index: [[#IND+3]] -; SYMS64-NEXT: ContainingCsectSymbolIndex: 1 +; SYMS64-NEXT: ContainingCsectSymbolIndex: [[#IND-2]] ; SYMS64-NEXT: ParameterHashIndex: 0x0 ; SYMS64-NEXT: TypeChkSectNum: 0x0 ; SYMS64-NEXT: SymbolAlignmentLog2: 0 @@ -140,7 +140,7 @@ define dso_local void @test__trap_annotation_debug(i32 %a) !dbg !4 { ; SYMS64-NEXT: } ; SYMS64-NEXT: CSECT Auxiliary Entry { ; SYMS64-NEXT: Index: [[#IND+7]] -; SYMS64-NEXT: ContainingCsectSymbolIndex: 1 +; SYMS64-NEXT: ContainingCsectSymbolIndex: [[#IND-2]] ; SYMS64-NEXT: ParameterHashIndex: 0x0 ; SYMS64-NEXT: TypeChkSectNum: 0x0 ; SYMS64-NEXT: SymbolAlignmentLog2: 0 diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section.ll index 17047460f7ca..8ee58755919b 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section.ll @@ -24,13 +24,13 @@ define dso_local void @test__trap_annotation(i32 %a) { } ; EXCEPT: Exception section { -; EXCEPT-NEXT: Symbol: .sub_test (3) +; EXCEPT-NEXT: Symbol: .sub_test ; EXCEPT-NEXT: LangID: 0 ; EXCEPT-NEXT: Reason: 0 ; EXCEPT-NEXT: Trap Instr Addr: 0x4 ; EXCEPT-NEXT: LangID: 1 ; EXCEPT-NEXT: Reason: 2 -; EXCEPT-NEXT: Symbol: .test__trap_annotation (6) +; EXCEPT-NEXT: Symbol: .test__trap_annotation ; EXCEPT-NEXT: LangID: 0 ; EXCEPT-NEXT: Reason: 0 ; EXCEPT-NEXT: Trap Instr Addr: 0x3C @@ -75,7 +75,7 @@ define dso_local void @test__trap_annotation(i32 %a) { ; SYMS-NEXT: } ; SYMS-NEXT: CSECT Auxiliary Entry { ; SYMS-NEXT: Index: [[#IND+2]] -; SYMS-NEXT: ContainingCsectSymbolIndex: 1 +; SYMS-NEXT: ContainingCsectSymbolIndex: [[#IND-2]] ; SYMS-NEXT: ParameterHashIndex: 0x0 ; SYMS-NEXT: TypeChkSectNum: 0x0 ; SYMS-NEXT: SymbolAlignmentLog2: 0 @@ -102,7 +102,7 @@ define dso_local void @test__trap_annotation(i32 %a) { ; SYMS-NEXT: } ; SYMS-NEXT: CSECT Auxiliary Entry { ; SYMS-NEXT: Index: [[#IND+5]] -; SYMS-NEXT: ContainingCsectSymbolIndex: 1 +; SYMS-NEXT: ContainingCsectSymbolIndex: [[#IND-2]] ; SYMS-NEXT: ParameterHashIndex: 0x0 ; SYMS-NEXT: TypeChkSectNum: 0x0 ; SYMS-NEXT: SymbolAlignmentLog2: 0 @@ -114,13 +114,13 @@ define dso_local void @test__trap_annotation(i32 %a) { ; SYMS-NEXT: } ; EXCEPT64: Exception section { -; EXCEPT64-NEXT: Symbol: .sub_test (3) +; EXCEPT64-NEXT: Symbol: .sub_test ; EXCEPT64-NEXT: LangID: 0 ; EXCEPT64-NEXT: Reason: 0 ; EXCEPT64-NEXT: Trap Instr Addr: 0x4 ; EXCEPT64-NEXT: LangID: 1 ; EXCEPT64-NEXT: Reason: 2 -; EXCEPT64-NEXT: Symbol: .test__trap_annotation (6) +; EXCEPT64-NEXT: Symbol: .test__trap_annotation ; EXCEPT64-NEXT: LangID: 0 ; EXCEPT64-NEXT: Reason: 0 ; EXCEPT64-NEXT: Trap Instr Addr: 0x3C @@ -163,7 +163,7 @@ define dso_local void @test__trap_annotation(i32 %a) { ; SYMS64-NEXT: } ; SYMS64-NEXT: CSECT Auxiliary Entry { ; SYMS64-NEXT: Index: [[#IND+2]] -; SYMS64-NEXT: ContainingCsectSymbolIndex: 1 +; SYMS64-NEXT: ContainingCsectSymbolIndex: [[#IND-2]] ; SYMS64-NEXT: ParameterHashIndex: 0x0 ; SYMS64-NEXT: TypeChkSectNum: 0x0 ; SYMS64-NEXT: SymbolAlignmentLog2: 0 @@ -189,7 +189,7 @@ define dso_local void @test__trap_annotation(i32 %a) { ; SYMS64-NEXT: } ; SYMS64-NEXT: CSECT Auxiliary Entry { ; SYMS64-NEXT: Index: [[#IND+5]] -; SYMS64-NEXT: ContainingCsectSymbolIndex: 1 +; SYMS64-NEXT: ContainingCsectSymbolIndex: [[#IND-2]] ; SYMS64-NEXT: ParameterHashIndex: 0x0 ; SYMS64-NEXT: TypeChkSectNum: 0x0 ; SYMS64-NEXT: SymbolAlignmentLog2: 0 diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll index a38da2229a7e..a28c2f2eefea 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll @@ -48,7 +48,7 @@ entry: ; CHECK-NEXT: L..C1: ; CHECK-NEXT: .tc ext_zvar[TC],ext_zvar -; CHECKOBJ: 00000000 (idx: 5) .ext_fun: +; CHECKOBJ: 00000000 (idx: [[#INDX:]]) .ext_fun: ; CHECKOBJ-NEXT: 0: 80 62 00 00 lwz 3, 0(2) ; CHECKOBJ-NEXT: 4: 80 82 00 04 lwz 4, 4(2) ; CHECKOBJ-NEXT: 8: 80 63 00 00 lwz 3, 0(3) @@ -57,26 +57,26 @@ entry: ; CHECKOBJ-NEXT: 14: 38 63 00 01 addi 3, 3, 1 ; CHECKOBJ-NEXT: 18: 4e 80 00 20 blr ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 0000001c (idx: 9) ext_const: +; CHECKOBJ-NEXT: 0000001c (idx: [[#INDX+4]]) ext_const: ; CHECKOBJ-NEXT: 1c: 00 00 00 01 ; CHECKOBJ-EMPTY: ; CHECKOBJ-NEXT: Disassembly of section .data: ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 00000020 (idx: 13) ext_var: +; CHECKOBJ-NEXT: 00000020 (idx: [[#INDX+8]]) ext_var: ; CHECKOBJ-NEXT: 20: 00 00 00 01 ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 00000024 (idx: 17) ext_zvar: +; CHECKOBJ-NEXT: 00000024 (idx: [[#INDX+12]]) ext_zvar: ; CHECKOBJ-NEXT: 24: 00 00 00 00 ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 00000028 (idx: 19) ext_fun[DS]: +; CHECKOBJ-NEXT: 00000028 (idx: [[#INDX+14]]) ext_fun[DS]: ; CHECKOBJ-NEXT: 28: 00 00 00 00 ; CHECKOBJ-NEXT: 2c: 00 00 00 34 ; CHECKOBJ-NEXT: 30: 00 00 00 00 ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 00000034 (idx: 23) ext_var[TC]: +; CHECKOBJ-NEXT: 00000034 (idx: [[#INDX+18]]) ext_var[TC]: ; CHECKOBJ-NEXT: 34: 00 00 00 20 ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 00000038 (idx: 25) ext_zvar[TC]: +; CHECKOBJ-NEXT: 00000038 (idx: [[#INDX+20]]) ext_zvar[TC]: ; CHECKOBJ-NEXT: 38: 00 00 00 24 ; CHECKSYM: Symbol {{[{][[:space:]] *}}Index: [[#INDX:]]{{[[:space:]] *}}Name: .ext_fun_sec diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-funcsect.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-funcsect.ll index a557b6f4f171..dbfbd0de08b9 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-funcsect.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-funcsect.ll @@ -9,17 +9,17 @@ ; RUN: -mattr=-altivec -function-sections -xcoff-traceback-table=true \ ; RUN: -filetype=obj -o %t32.o < %s ; RUN: llvm-objdump --syms --reloc --symbol-description %t32.o | \ -; RUN: FileCheck --check-prefix=XCOFF32 %s +; RUN: FileCheck -D#NFA=2 --check-prefix=XCOFF32 %s ; RUN: llvm-objdump -dr --symbol-description %t32.o | \ -; RUN: FileCheck --check-prefix=DIS32 %s +; RUN: FileCheck -D#NFA=2 --check-prefix=DIS32 %s ; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 \ ; RUN: -mattr=-altivec -function-sections -xcoff-traceback-table=true \ ; RUN: -filetype=obj -o %t64.o < %s ; RUN: llvm-objdump --syms --reloc --symbol-description %t64.o | \ -; RUN: FileCheck --check-prefix=XCOFF64 %s +; RUN: FileCheck -D#NFA=2 --check-prefix=XCOFF64 %s ; RUN: llvm-objdump -dr --symbol-description %t64.o | \ -; RUN: FileCheck --check-prefix=DIS64 %s +; RUN: FileCheck -D#NFA=2 --check-prefix=DIS64 %s @alias_foo = alias void (...), ptr @foo @@ -113,117 +113,117 @@ entry: ; ASM-NEXT: .globl .alias_foo ; XCOFF32: SYMBOL TABLE: -; XCOFF32-NEXT: 00000000 df *DEBUG* 00000000 (idx: 0) -; XCOFF32-NEXT: 00000000 *UND* 00000000 (idx: 1) .extern_foo[PR] -; XCOFF32-NEXT: 00000000 *UND* 00000000 (idx: 3) extern_foo[DS] -; XCOFF32-NEXT: 00000000 l .text 00000000 (idx: 5) [PR] -; XCOFF32-NEXT: 00000000 g .text 00000019 (idx: 7) .foo[PR] -; XCOFF32-NEXT: 00000000 g F .text (csect: (idx: 7) .foo[PR]) 00000000 (idx: 9) .alias_foo -; XCOFF32-NEXT: 00000020 g F .text 00000020 .hidden (idx: 11) .hidden_foo[PR] -; XCOFF32-NEXT: 00000040 g F .text 00000059 (idx: 13) .bar[PR] -; XCOFF32-NEXT: 000000c0 l F .text 0000002a (idx: 15) .static_overalign_foo[PR] -; XCOFF32-NEXT: 000000ec g O .data 0000000c (idx: 17) foo[DS] -; XCOFF32-NEXT: 000000ec g O .data (csect: (idx: 17) foo[DS]) 00000000 (idx: 19) alias_foo -; XCOFF32-NEXT: 000000f8 g O .data 0000000c .hidden (idx: 21) hidden_foo[DS] -; XCOFF32-NEXT: 00000104 g O .data 0000000c (idx: 23) bar[DS] -; XCOFF32-NEXT: 00000110 l O .data 0000000c (idx: 25) static_overalign_foo[DS] -; XCOFF32-NEXT: 0000011c l .data 00000000 (idx: 27) TOC[TC0] +; XCOFF32-NEXT: 00000000 df *DEBUG* 00000000 (idx: 0) .file +; XCOFF32-NEXT: 00000000 *UND* 00000000 (idx: [[#NFA+1]]) .extern_foo[PR] +; XCOFF32-NEXT: 00000000 *UND* 00000000 (idx: [[#NFA+3]]) extern_foo[DS] +; XCOFF32-NEXT: 00000000 l .text 00000000 (idx: [[#NFA+5]]) [PR] +; XCOFF32-NEXT: 00000000 g .text 00000019 (idx: [[#NFA+7]]) .foo[PR] +; XCOFF32-NEXT: 00000000 g F .text (csect: (idx: [[#NFA+7]]) .foo[PR]) 00000000 (idx: [[#NFA+9]]) .alias_foo +; XCOFF32-NEXT: 00000020 g F .text 00000020 .hidden (idx: [[#NFA+11]]) .hidden_foo[PR] +; XCOFF32-NEXT: 00000040 g F .text 00000059 (idx: [[#NFA+13]]) .bar[PR] +; XCOFF32-NEXT: 000000c0 l F .text 0000002a (idx: [[#NFA+15]]) .static_overalign_foo[PR] +; XCOFF32-NEXT: 000000ec g O .data 0000000c (idx: [[#NFA+17]]) foo[DS] +; XCOFF32-NEXT: 000000ec g O .data (csect: (idx: [[#NFA+17]]) foo[DS]) 00000000 (idx: [[#NFA+19]]) alias_foo +; XCOFF32-NEXT: 000000f8 g O .data 0000000c .hidden (idx: [[#NFA+21]]) hidden_foo[DS] +; XCOFF32-NEXT: 00000104 g O .data 0000000c (idx: [[#NFA+23]]) bar[DS] +; XCOFF32-NEXT: 00000110 l O .data 0000000c (idx: [[#NFA+25]]) static_overalign_foo[DS] +; XCOFF32-NEXT: 0000011c l .data 00000000 (idx: [[#NFA+27]]) TOC[TC0] ; XCOFF32: RELOCATION RECORDS FOR [.text]: ; XCOFF32-NEXT: OFFSET TYPE VALUE -; XCOFF32-NEXT: 0000004c R_RBR (idx: 7) .foo[PR] -; XCOFF32-NEXT: 00000054 R_RBR (idx: 15) .static_overalign_foo[PR] -; XCOFF32-NEXT: 0000005c R_RBR (idx: 9) .alias_foo -; XCOFF32-NEXT: 00000064 R_RBR (idx: 1) .extern_foo[PR] -; XCOFF32-NEXT: 0000006c R_RBR (idx: 11) .hidden_foo[PR] +; XCOFF32-NEXT: 0000004c R_RBR (idx: [[#NFA+7]]) .foo[PR] +; XCOFF32-NEXT: 00000054 R_RBR (idx: [[#NFA+15]]) .static_overalign_foo[PR] +; XCOFF32-NEXT: 0000005c R_RBR (idx: [[#NFA+9]]) .alias_foo +; XCOFF32-NEXT: 00000064 R_RBR (idx: [[#NFA+1]]) .extern_foo[PR] +; XCOFF32-NEXT: 0000006c R_RBR (idx: [[#NFA+11]]) .hidden_foo[PR] ; XCOFF32: RELOCATION RECORDS FOR [.data]: ; XCOFF32-NEXT: OFFSET TYPE VALUE -; XCOFF32-NEXT: 00000000 R_POS (idx: 7) .foo[PR] -; XCOFF32-NEXT: 00000004 R_POS (idx: 27) TOC[TC0] -; XCOFF32-NEXT: 0000000c R_POS (idx: 11) .hidden_foo[PR] -; XCOFF32-NEXT: 00000010 R_POS (idx: 27) TOC[TC0] -; XCOFF32-NEXT: 00000018 R_POS (idx: 13) .bar[PR] -; XCOFF32-NEXT: 0000001c R_POS (idx: 27) TOC[TC0] -; XCOFF32-NEXT: 00000024 R_POS (idx: 15) .static_overalign_foo[PR] -; XCOFF32-NEXT: 00000028 R_POS (idx: 27) TOC[TC0] +; XCOFF32-NEXT: 00000000 R_POS (idx: [[#NFA+7]]) .foo[PR] +; XCOFF32-NEXT: 00000004 R_POS (idx: [[#NFA+27]]) TOC[TC0] +; XCOFF32-NEXT: 0000000c R_POS (idx: [[#NFA+11]]) .hidden_foo[PR] +; XCOFF32-NEXT: 00000010 R_POS (idx: [[#NFA+27]]) TOC[TC0] +; XCOFF32-NEXT: 00000018 R_POS (idx: [[#NFA+13]]) .bar[PR] +; XCOFF32-NEXT: 0000001c R_POS (idx: [[#NFA+27]]) TOC[TC0] +; XCOFF32-NEXT: 00000024 R_POS (idx: [[#NFA+15]]) .static_overalign_foo[PR] +; XCOFF32-NEXT: 00000028 R_POS (idx: [[#NFA+27]]) TOC[TC0] ; XCOFF64: SYMBOL TABLE: -; XCOFF64-NEXT: 0000000000000000 df *DEBUG* 0000000000000000 (idx: 0) -; XCOFF64-NEXT: 0000000000000000 *UND* 0000000000000000 (idx: 1) .extern_foo[PR] -; XCOFF64-NEXT: 0000000000000000 *UND* 0000000000000000 (idx: 3) extern_foo[DS] -; XCOFF64-NEXT: 0000000000000000 l .text 0000000000000000 (idx: 5) [PR] -; XCOFF64-NEXT: 0000000000000000 g .text 0000000000000019 (idx: 7) .foo[PR] -; XCOFF64-NEXT: 0000000000000000 g F .text (csect: (idx: 7) .foo[PR]) 0000000000000000 (idx: 9) .alias_foo -; XCOFF64-NEXT: 0000000000000020 g F .text 0000000000000020 .hidden (idx: 11) .hidden_foo[PR] -; XCOFF64-NEXT: 0000000000000040 g F .text 0000000000000059 (idx: 13) .bar[PR] -; XCOFF64-NEXT: 00000000000000c0 l F .text 000000000000002a (idx: 15) .static_overalign_foo[PR] -; XCOFF64-NEXT: 00000000000000f0 g O .data 0000000000000018 (idx: 17) foo[DS] -; XCOFF64-NEXT: 00000000000000f0 g O .data (csect: (idx: 17) foo[DS]) 0000000000000000 (idx: 19) alias_foo -; XCOFF64-NEXT: 0000000000000108 g O .data 0000000000000018 .hidden (idx: 21) hidden_foo[DS] -; XCOFF64-NEXT: 0000000000000120 g O .data 0000000000000018 (idx: 23) bar[DS] -; XCOFF64-NEXT: 0000000000000138 l O .data 0000000000000018 (idx: 25) static_overalign_foo[DS] -; XCOFF64-NEXT: 0000000000000150 l .data 0000000000000000 (idx: 27) TOC[TC0] +; XCOFF64-NEXT: 0000000000000000 df *DEBUG* 0000000000000000 (idx: 0) .file +; XCOFF64-NEXT: 0000000000000000 *UND* 0000000000000000 (idx: [[#NFA+1]]) .extern_foo[PR] +; XCOFF64-NEXT: 0000000000000000 *UND* 0000000000000000 (idx: [[#NFA+3]]) extern_foo[DS] +; XCOFF64-NEXT: 0000000000000000 l .text 0000000000000000 (idx: [[#NFA+5]]) [PR] +; XCOFF64-NEXT: 0000000000000000 g .text 0000000000000019 (idx: [[#NFA+7]]) .foo[PR] +; XCOFF64-NEXT: 0000000000000000 g F .text (csect: (idx: [[#NFA+7]]) .foo[PR]) 0000000000000000 (idx: [[#NFA+9]]) .alias_foo +; XCOFF64-NEXT: 0000000000000020 g F .text 0000000000000020 .hidden (idx: [[#NFA+11]]) .hidden_foo[PR] +; XCOFF64-NEXT: 0000000000000040 g F .text 0000000000000059 (idx: [[#NFA+13]]) .bar[PR] +; XCOFF64-NEXT: 00000000000000c0 l F .text 000000000000002a (idx: [[#NFA+15]]) .static_overalign_foo[PR] +; XCOFF64-NEXT: 00000000000000f0 g O .data 0000000000000018 (idx: [[#NFA+17]]) foo[DS] +; XCOFF64-NEXT: 00000000000000f0 g O .data (csect: (idx: [[#NFA+17]]) foo[DS]) 0000000000000000 (idx: [[#NFA+19]]) alias_foo +; XCOFF64-NEXT: 0000000000000108 g O .data 0000000000000018 .hidden (idx: [[#NFA+21]]) hidden_foo[DS] +; XCOFF64-NEXT: 0000000000000120 g O .data 0000000000000018 (idx: [[#NFA+23]]) bar[DS] +; XCOFF64-NEXT: 0000000000000138 l O .data 0000000000000018 (idx: [[#NFA+25]]) static_overalign_foo[DS] +; XCOFF64-NEXT: 0000000000000150 l .data 0000000000000000 (idx: [[#NFA+27]]) TOC[TC0] ; XCOFF64: RELOCATION RECORDS FOR [.text]: ; XCOFF64-NEXT: OFFSET TYPE VALUE -; XCOFF64-NEXT: 000000000000004c R_RBR (idx: 7) .foo[PR] -; XCOFF64-NEXT: 0000000000000054 R_RBR (idx: 15) .static_overalign_foo[PR] -; XCOFF64-NEXT: 000000000000005c R_RBR (idx: 9) .alias_foo -; XCOFF64-NEXT: 0000000000000064 R_RBR (idx: 1) .extern_foo[PR] -; XCOFF64-NEXT: 000000000000006c R_RBR (idx: 11) .hidden_foo[PR] +; XCOFF64-NEXT: 000000000000004c R_RBR (idx: [[#NFA+7]]) .foo[PR] +; XCOFF64-NEXT: 0000000000000054 R_RBR (idx: [[#NFA+15]]) .static_overalign_foo[PR] +; XCOFF64-NEXT: 000000000000005c R_RBR (idx: [[#NFA+9]]) .alias_foo +; XCOFF64-NEXT: 0000000000000064 R_RBR (idx: [[#NFA+1]]) .extern_foo[PR] +; XCOFF64-NEXT: 000000000000006c R_RBR (idx: [[#NFA+11]]) .hidden_foo[PR] ; XCOFF64: RELOCATION RECORDS FOR [.data]: ; XCOFF64-NEXT: OFFSET TYPE VALUE -; XCOFF64-NEXT: 0000000000000000 R_POS (idx: 7) .foo[PR] -; XCOFF64-NEXT: 0000000000000008 R_POS (idx: 27) TOC[TC0] -; XCOFF64-NEXT: 0000000000000018 R_POS (idx: 11) .hidden_foo[PR] -; XCOFF64-NEXT: 0000000000000020 R_POS (idx: 27) TOC[TC0] -; XCOFF64-NEXT: 0000000000000030 R_POS (idx: 13) .bar[PR] -; XCOFF64-NEXT: 0000000000000038 R_POS (idx: 27) TOC[TC0] -; XCOFF64-NEXT: 0000000000000048 R_POS (idx: 15) .static_overalign_foo[PR] -; XCOFF64-NEXT: 0000000000000050 R_POS (idx: 27) TOC[TC0] +; XCOFF64-NEXT: 0000000000000000 R_POS (idx: [[#NFA+7]]) .foo[PR] +; XCOFF64-NEXT: 0000000000000008 R_POS (idx: [[#NFA+27]]) TOC[TC0] +; XCOFF64-NEXT: 0000000000000018 R_POS (idx: [[#NFA+11]]) .hidden_foo[PR] +; XCOFF64-NEXT: 0000000000000020 R_POS (idx: [[#NFA+27]]) TOC[TC0] +; XCOFF64-NEXT: 0000000000000030 R_POS (idx: [[#NFA+13]]) .bar[PR] +; XCOFF64-NEXT: 0000000000000038 R_POS (idx: [[#NFA+27]]) TOC[TC0] +; XCOFF64-NEXT: 0000000000000048 R_POS (idx: [[#NFA+15]]) .static_overalign_foo[PR] +; XCOFF64-NEXT: 0000000000000050 R_POS (idx: [[#NFA+27]]) TOC[TC0] ; DIS32: Disassembly of section .text: -; DIS32: 00000000 (idx: 9) .alias_foo: -; DIS32: 00000020 (idx: 11) .hidden_foo[PR]: -; DIS32: 00000040 (idx: 13) .bar[PR]: +; DIS32: 00000000 (idx: [[#NFA+9]]) .alias_foo: +; DIS32: 00000020 (idx: [[#NFA+11]]) .hidden_foo[PR]: +; DIS32: 00000040 (idx: [[#NFA+13]]) .bar[PR]: ; DIS32-NEXT: 40: 7c 08 02 a6 mflr 0 ; DIS32-NEXT: 44: 94 21 ff c0 stwu 1, -64(1) ; DIS32-NEXT: 48: 90 01 00 48 stw 0, 72(1) ; DIS32-NEXT: 4c: 4b ff ff b5 bl 0x0 <.foo> -; DIS32-NEXT: 0000004c: R_RBR (idx: 7) .foo[PR] +; DIS32-NEXT: 0000004c: R_RBR (idx: [[#NFA+7]]) .foo[PR] ; DIS32-NEXT: 50: 60 00 00 00 nop ; DIS32-NEXT: 54: 48 00 00 6d bl 0xc0 <.static_overalign_foo> -; DIS32-NEXT: 00000054: R_RBR (idx: 15) .static_overalign_foo[PR] +; DIS32-NEXT: 00000054: R_RBR (idx: [[#NFA+15]]) .static_overalign_foo[PR] ; DIS32-NEXT: 58: 60 00 00 00 nop ; DIS32-NEXT: 5c: 4b ff ff a5 bl 0x0 <.alias_foo> -; DIS32-NEXT: 0000005c: R_RBR (idx: 9) .alias_foo +; DIS32-NEXT: 0000005c: R_RBR (idx: [[#NFA+9]]) .alias_foo ; DIS32-NEXT: 60: 60 00 00 00 nop ; DIS32-NEXT: 64: 4b ff ff 9d bl 0x0 <.extern_foo> -; DIS32-NEXT: 00000064: R_RBR (idx: 1) .extern_foo[PR] +; DIS32-NEXT: 00000064: R_RBR (idx: [[#NFA+1]]) .extern_foo[PR] ; DIS32-NEXT: 68: 60 00 00 00 nop ; DIS32-NEXT: 6c: 4b ff ff b5 bl 0x20 <.hidden_foo> -; DIS32-NEXT: 0000006c: R_RBR (idx: 11) .hidden_foo[PR] -; DIS32: 000000c0 (idx: 15) .static_overalign_foo[PR]: +; DIS32-NEXT: 0000006c: R_RBR (idx: [[#NFA+11]]) .hidden_foo[PR] +; DIS32: 000000c0 (idx: [[#NFA+15]]) .static_overalign_foo[PR]: ; DIS64: Disassembly of section .text: -; DIS64: 0000000000000000 (idx: 9) .alias_foo: -; DIS64: 0000000000000020 (idx: 11) .hidden_foo[PR]: -; DIS64: 0000000000000040 (idx: 13) .bar[PR]: +; DIS64: 0000000000000000 (idx: [[#NFA+9]]) .alias_foo: +; DIS64: 0000000000000020 (idx: [[#NFA+11]]) .hidden_foo[PR]: +; DIS64: 0000000000000040 (idx: [[#NFA+13]]) .bar[PR]: ; DIS64-NEXT: 40: 7c 08 02 a6 mflr 0 ; DIS64-NEXT: 44: f8 21 ff 91 stdu 1, -112(1) ; DIS64-NEXT: 48: f8 01 00 80 std 0, 128(1) ; DIS64-NEXT: 4c: 4b ff ff b5 bl 0x0 <.foo> -; DIS64-NEXT: 000000000000004c: R_RBR (idx: 7) .foo[PR] +; DIS64-NEXT: 000000000000004c: R_RBR (idx: [[#NFA+7]]) .foo[PR] ; DIS64-NEXT: 50: 60 00 00 00 nop ; DIS64-NEXT: 54: 48 00 00 6d bl 0xc0 <.static_overalign_foo> -; DIS64-NEXT: 0000000000000054: R_RBR (idx: 15) .static_overalign_foo[PR] +; DIS64-NEXT: 0000000000000054: R_RBR (idx: [[#NFA+15]]) .static_overalign_foo[PR] ; DIS64-NEXT: 58: 60 00 00 00 nop ; DIS64-NEXT: 5c: 4b ff ff a5 bl 0x0 <.alias_foo> -; DIS64-NEXT: 000000000000005c: R_RBR (idx: 9) .alias_foo +; DIS64-NEXT: 000000000000005c: R_RBR (idx: [[#NFA+9]]) .alias_foo ; DIS64-NEXT: 60: 60 00 00 00 nop ; DIS64-NEXT: 64: 4b ff ff 9d bl 0x0 <.extern_foo> -; DIS64-NEXT: 0000000000000064: R_RBR (idx: 1) .extern_foo[PR] +; DIS64-NEXT: 0000000000000064: R_RBR (idx: [[#NFA+1]]) .extern_foo[PR] ; DIS64-NEXT: 68: 60 00 00 00 nop ; DIS64-NEXT: 6c: 4b ff ff b5 bl 0x20 <.hidden_foo> -; DIS64-NEXT: 000000000000006c: R_RBR (idx: 11) .hidden_foo[PR] -; DIS64: 00000000000000c0 (idx: 15) .static_overalign_foo[PR]: +; DIS64-NEXT: 000000000000006c: R_RBR (idx: [[#NFA+11]]) .hidden_foo[PR] +; DIS64: 00000000000000c0 (idx: [[#NFA+15]]) .static_overalign_foo[PR]: diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-lcomm.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-lcomm.ll index 31fdea9ad13d..8240306686ab 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-lcomm.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-lcomm.ll @@ -29,7 +29,7 @@ ; OBJ-NEXT: TimeStamp: ; OBJ32-NEXT: SymbolTableOffset: 0x64 ; OBJ64-NEXT: SymbolTableOffset: 0xA8 -; OBJ-NEXT: SymbolTableEntries: 9 +; OBJ-NEXT: SymbolTableEntries: 11 ; OBJ-NEXT: OptionalHeaderSize: 0x0 ; OBJ-NEXT: Flags: 0x0 ; OBJ-NEXT: } diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll index ca13edd08513..91e0f5da6e1b 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll @@ -147,7 +147,7 @@ entry: ; DIS64: Disassembly of section .text: ; DIS64-EMPTY: -; DIS64-NEXT: 0000000000000000 (idx: 3) .foo: +; DIS64-NEXT: 0000000000000000 (idx: {{[0-9]+}}) .foo: ; DIS64-NEXT: 0: 3c 62 00 00 addis 3, 2, 0 ; DIS64-NEXT: 0000000000000002: R_TOCU (idx: [[#INDX:]]) a[TE] ; DIS64-NEXT: 4: 3c 82 00 00 addis 4, 2, 0 diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll index 5ac6a7af0db2..82ff008ad16d 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll @@ -1,16 +1,16 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -mattr=-altivec \ ; RUN: -xcoff-traceback-table=false -data-sections=false -filetype=obj -o %t.o < %s -; RUN: llvm-readobj --section-headers --file-header %t.o | FileCheck --check-prefixes=OBJ,OBJ32 %s -; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefixes=RELOC,RELOC32 %s -; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefixes=SYM,SYM32 %s +; RUN: llvm-readobj --section-headers --file-header %t.o | FileCheck -D#NFA=2 --check-prefixes=OBJ,OBJ32 %s +; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck -D#NFA=2 --check-prefixes=RELOC,RELOC32 %s +; RUN: llvm-readobj --syms %t.o | FileCheck -D#NFA=2 --check-prefixes=SYM,SYM32 %s ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=DIS %s ; RUN: llvm-objdump -r %t.o | FileCheck --check-prefix=DIS_REL %s ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -mattr=-altivec \ ; RUN: -xcoff-traceback-table=false -data-sections=false -filetype=obj -o %t64.o < %s -; RUN: llvm-readobj --section-headers --file-header %t64.o | FileCheck --check-prefixes=OBJ,OBJ64 %s -; RUN: llvm-readobj --relocs --expand-relocs %t64.o | FileCheck --check-prefixes=RELOC,RELOC64 %s -; RUN: llvm-readobj --syms %t64.o | FileCheck --check-prefixes=SYM,SYM64 %s +; RUN: llvm-readobj --section-headers --file-header %t64.o | FileCheck -D#NFA=2 --check-prefixes=OBJ,OBJ64 %s +; RUN: llvm-readobj --relocs --expand-relocs %t64.o | FileCheck -D#NFA=2 --check-prefixes=RELOC,RELOC64 %s +; RUN: llvm-readobj --syms %t64.o | FileCheck -D#NFA=2 --check-prefixes=SYM,SYM64 %s ; RUN: llvm-objdump -D %t64.o | FileCheck --check-prefix=DIS64 %s ; RUN: llvm-objdump -r %t64.o | FileCheck --check-prefix=DIS_REL64 %s @@ -38,7 +38,7 @@ declare i32 @bar(i32) ; OBJ-NEXT: TimeStamp: None (0x0) ; OBJ32-NEXT: SymbolTableOffset: 0x13C ; OBJ64-NEXT: SymbolTableOffset: 0x1B8 -; OBJ-NEXT: SymbolTableEntries: 27 +; OBJ-NEXT: SymbolTableEntries: [[#NFA+27]] ; OBJ-NEXT: OptionalHeaderSize: 0x0 ; OBJ-NEXT: Flags: 0x0 ; OBJ-NEXT: } @@ -80,7 +80,7 @@ declare i32 @bar(i32) ; RELOC-NEXT: Section (index: 1) .text { ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x10 -; RELOC-NEXT: Symbol: .bar (1) +; RELOC-NEXT: Symbol: .bar ([[#NFA+1]]) ; RELOC-NEXT: IsSigned: Yes ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 26 @@ -88,7 +88,7 @@ declare i32 @bar(i32) ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x1A -; RELOC-NEXT: Symbol: globalA (23) +; RELOC-NEXT: Symbol: globalA ([[#NFA+23]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -96,7 +96,7 @@ declare i32 @bar(i32) ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x1E -; RELOC-NEXT: Symbol: globalB (25) +; RELOC-NEXT: Symbol: globalB ([[#NFA+25]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -106,7 +106,7 @@ declare i32 @bar(i32) ; RELOC-NEXT: Section (index: 2) .data { ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x70 -; RELOC-NEXT: Symbol: arr (15) +; RELOC-NEXT: Symbol: arr ([[#NFA+15]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC32-NEXT: Length: 32 @@ -116,7 +116,7 @@ declare i32 @bar(i32) ; RELOC-NEXT: Relocation { ; RELOC32-NEXT: Virtual Address: 0x74 ; RELOC64-NEXT: Virtual Address: 0x78 -; RELOC-NEXT: Symbol: .foo (7) +; RELOC-NEXT: Symbol: .foo ([[#NFA+7]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC32-NEXT: Length: 32 @@ -126,7 +126,7 @@ declare i32 @bar(i32) ; RELOC-NEXT: Relocation { ; RELOC32-NEXT: Virtual Address: 0x78 ; RELOC64-NEXT: Virtual Address: 0x80 -; RELOC-NEXT: Symbol: TOC (21) +; RELOC-NEXT: Symbol: TOC ([[#NFA+21]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC32-NEXT: Length: 32 @@ -136,7 +136,7 @@ declare i32 @bar(i32) ; RELOC-NEXT: Relocation { ; RELOC32-NEXT: Virtual Address: 0x80 ; RELOC64-NEXT: Virtual Address: 0x90 -; RELOC-NEXT: Symbol: globalA (11) +; RELOC-NEXT: Symbol: globalA ([[#NFA+11]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC32-NEXT: Length: 32 @@ -146,7 +146,7 @@ declare i32 @bar(i32) ; RELOC-NEXT: Relocation { ; RELOC32-NEXT: Virtual Address: 0x84 ; RELOC64-NEXT: Virtual Address: 0x98 -; RELOC-NEXT: Symbol: globalB (13) +; RELOC-NEXT: Symbol: globalB ([[#NFA+13]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC32-NEXT: Length: 32 @@ -159,14 +159,26 @@ declare i32 @bar(i32) ; SYM: Symbols [ ; SYM-NEXT: Symbol { ; SYM-NEXT: Index: 0 -; SYM-NEXT: Name: +; SYM-NEXT: Name: .file ; SYM-NEXT: Value (SymbolTableIndex): 0x0 ; SYM-NEXT: Section: N_DEBUG ; SYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9) ; SYM32-NEXT: CPU Version ID: TCPU_COM (0x3) ; SYM64-NEXT: CPU Version ID: TCPU_PPC64 (0x2) ; SYM-NEXT: StorageClass: C_FILE (0x67) -; SYM-NEXT: NumberOfAuxEntries: 0 +; SYM-NEXT: NumberOfAuxEntries: 2 +; SYM-NEXT: File Auxiliary Entry { +; SYM-NEXT: Index: 1 +; SYM-NEXT: Name: +; SYM-NEXT: Type: XFT_FN (0x0) +; SYM64-NEXT: Auxiliary Type: AUX_FILE (0xFC) +; SYM-NEXT: } +; SYM-NEXT: File Auxiliary Entry { +; SYM-NEXT: Index: 2 +; SYM-NEXT: Name: LLVM version 18.0.0git +; SYM-NEXT: Type: XFT_CV (0x2) +; SYM64-NEXT: Auxiliary Type: AUX_FILE (0xFC) +; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { ; SYM-NEXT: Index: [[#INDX:]] diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll index cafb91aafe23..0fa47373964a 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll @@ -82,7 +82,7 @@ ; OBJ-NEXT: TimeStamp: None (0x0) ; OBJ32-NEXT: SymbolTableOffset: 0x8C ; OBJ64-NEXT: SymbolTableOffset: 0xB0 -; OBJ-NEXT: SymbolTableEntries: 21 +; OBJ-NEXT: SymbolTableEntries: 23 ; OBJ-NEXT: OptionalHeaderSize: 0x0 ; OBJ-NEXT: Flags: 0x0 ; OBJ-NEXT: } diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-symbol-rename.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-symbol-rename.ll index 494078010fd0..296bef6919de 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-symbol-rename.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-symbol-rename.ll @@ -10,7 +10,7 @@ ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \ ; RUN: -mattr=-altivec -data-sections=false -xcoff-traceback-table=false -filetype=obj -o %t.o < %s ; RUN: llvm-objdump -D -r --symbol-description %t.o | \ -; RUN: FileCheck --check-prefix=OBJ %s +; RUN: FileCheck --check-prefix=OBJ -D#NFA=2 %s ; This is f`o @"f\60o" = global i32 10, align 4 @@ -105,12 +105,12 @@ declare i32 @"f\40o"(...) ; OBJ: Disassembly of section .text: ; OBJ-EMPTY: -; OBJ-NEXT: 00000000 (idx: 7) .f$o: +; OBJ-NEXT: 00000000 (idx: [[#NFA+7]]) .f$o: ; OBJ-NEXT: 0: 7c 08 02 a6 mflr 0 ; OBJ-NEXT: 4: 94 21 ff c0 stwu 1, -64(1) ; OBJ-NEXT: 8: 90 01 00 48 stw 0, 72(1) ; OBJ-NEXT: c: 4b ff ff f5 bl 0x0 -; OBJ-NEXT: 0000000c: R_RBR (idx: 1) .f@o[PR] +; OBJ-NEXT: 0000000c: R_RBR (idx: [[#NFA+1]]) .f@o[PR] ; OBJ-NEXT: 10: 60 00 00 00 nop ; OBJ-NEXT: 14: 38 21 00 40 addi 1, 1, 64 ; OBJ-NEXT: 18: 80 01 00 08 lwz 0, 8(1) @@ -120,13 +120,13 @@ declare i32 @"f\40o"(...) ; OBJ-NEXT: 28: 60 00 00 00 nop ; OBJ-NEXT: 2c: 60 00 00 00 nop ; OBJ-EMPTY: -; OBJ-NEXT: 00000030 (idx: 9) .f&o: +; OBJ-NEXT: 00000030 (idx: [[#NFA+9]]) .f&o: ; OBJ-NEXT: 30: 7c 08 02 a6 mflr 0 ; OBJ-NEXT: 34: 94 21 ff c0 stwu 1, -64(1) ; OBJ-NEXT: 38: 90 01 00 48 stw 0, 72(1) ; OBJ-NEXT: 3c: 4b ff ff c5 bl 0x0 ; OBJ-NEXT: 40: 80 82 00 00 lwz 4, 0(2) -; OBJ-NEXT: 00000042: R_TOC (idx: 25) f=o[TC] +; OBJ-NEXT: 00000042: R_TOC (idx: [[#NFA+25]]) f=o[TC] ; OBJ-NEXT: 44: 80 84 00 00 lwz 4, 0(4) ; OBJ-NEXT: 48: 7c 63 22 14 add 3, 3, 4 ; OBJ-NEXT: 4c: 38 21 00 40 addi 1, 1, 64 @@ -135,49 +135,49 @@ declare i32 @"f\40o"(...) ; OBJ-NEXT: 58: 4e 80 00 20 blr ; OBJ-NEXT: 5c: 60 00 00 00 nop ; OBJ-EMPTY: -; OBJ-NEXT: 00000060 (idx: 11) .f&_o: +; OBJ-NEXT: 00000060 (idx: [[#NFA+11]]) .f&_o: ; OBJ-NEXT: 60: 80 62 00 04 lwz 3, 4(2) -; OBJ-NEXT: 00000062: R_TOC (idx: 27) f@o[TC] +; OBJ-NEXT: 00000062: R_TOC (idx: [[#NFA+27]]) f@o[TC] ; OBJ-NEXT: 64: 4e 80 00 20 blr ; OBJ-EMPTY: ; OBJ-NEXT: Disassembly of section .data: ; OBJ-EMPTY: -; OBJ-NEXT: 00000068 (idx: 15) f`o: +; OBJ-NEXT: 00000068 (idx: [[#NFA+15]]) f`o: ; OBJ-NEXT: 68: 00 00 00 0a ; OBJ-EMPTY: -; OBJ-NEXT: 0000006c (idx: 17) f$o[DS]: +; OBJ-NEXT: 0000006c (idx: [[#NFA+17]]) f$o[DS]: ; OBJ-NEXT: 6c: 00 00 00 00 -; OBJ-NEXT: 0000006c: R_POS (idx: 7) .f$o +; OBJ-NEXT: 0000006c: R_POS (idx: [[#NFA+7]]) .f$o ; OBJ-NEXT: 70: 00 00 00 90 -; OBJ-NEXT: 00000070: R_POS (idx: 23) TOC[TC0] +; OBJ-NEXT: 00000070: R_POS (idx: [[#NFA+23]]) TOC[TC0] ; OBJ-NEXT: 74: 00 00 00 00 ; OBJ-EMPTY: -; OBJ-NEXT: 00000078 (idx: 19) f&o[DS]: +; OBJ-NEXT: 00000078 (idx: [[#NFA+19]]) f&o[DS]: ; OBJ-NEXT: 78: 00 00 00 30 -; OBJ-NEXT: 00000078: R_POS (idx: 9) .f&o +; OBJ-NEXT: 00000078: R_POS (idx: [[#NFA+9]]) .f&o ; OBJ-NEXT: 7c: 00 00 00 90 -; OBJ-NEXT: 0000007c: R_POS (idx: 23) TOC[TC0] +; OBJ-NEXT: 0000007c: R_POS (idx: [[#NFA+23]]) TOC[TC0] ; OBJ-NEXT: 80: 00 00 00 00 ; OBJ-EMPTY: -; OBJ-NEXT: 00000084 (idx: 21) f&_o[DS]: +; OBJ-NEXT: 00000084 (idx: [[#NFA+21]]) f&_o[DS]: ; OBJ-NEXT: 84: 00 00 00 60 -; OBJ-NEXT: 00000084: R_POS (idx: 11) .f&_o +; OBJ-NEXT: 00000084: R_POS (idx: [[#NFA+11]]) .f&_o ; OBJ-NEXT: 88: 00 00 00 90 -; OBJ-NEXT: 00000088: R_POS (idx: 23) TOC[TC0] +; OBJ-NEXT: 00000088: R_POS (idx: [[#NFA+23]]) TOC[TC0] ; OBJ-NEXT: 8c: 00 00 00 00 ; OBJ-EMPTY: -; OBJ-NEXT: 00000090 (idx: 25) f=o[TC]: +; OBJ-NEXT: 00000090 (idx: [[#NFA+25]]) f=o[TC]: ; OBJ-NEXT: 90: 00 00 00 9c -; OBJ-NEXT: 00000090: R_POS (idx: 31) f=o[BS] +; OBJ-NEXT: 00000090: R_POS (idx: [[#NFA+31]]) f=o[BS] ; OBJ-EMPTY: -; OBJ-NEXT: 00000094 (idx: 27) f@o[TC]: +; OBJ-NEXT: 00000094 (idx: [[#NFA+27]]) f@o[TC]: ; OBJ-NEXT: 94: 00 00 00 00 -; OBJ-NEXT: 00000094: R_POS (idx: 3) f@o[DS] +; OBJ-NEXT: 00000094: R_POS (idx: [[#NFA+3]]) f@o[DS] ; OBJ-EMPTY: ; OBJ-NEXT: Disassembly of section .bss: ; OBJ-EMPTY: -; OBJ-NEXT: 00000098 (idx: 29) f"o"[RW]: +; OBJ-NEXT: 00000098 (idx: [[#NFA+29]]) f"o"[RW]: ; OBJ-NEXT: ... ; OBJ-EMPTY: -; OBJ-NEXT: 0000009c (idx: 31) f=o[BS]: +; OBJ-NEXT: 0000009c (idx: [[#NFA+31]]) f=o[BS]: ; OBJ-NEXT: ... diff --git a/llvm/test/CodeGen/PowerPC/basic-toc-data-def.ll b/llvm/test/CodeGen/PowerPC/basic-toc-data-def.ll index 2d2c09cc17ab..5fbd3b17d4f8 100644 --- a/llvm/test/CodeGen/PowerPC/basic-toc-data-def.ll +++ b/llvm/test/CodeGen/PowerPC/basic-toc-data-def.ll @@ -2,9 +2,9 @@ ; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -filetype=obj -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s -o %t32.o -; RUN: llvm-readobj %t32.o --syms | FileCheck %s --check-prefix=OBJ32 +; RUN: llvm-readobj %t32.o --syms | FileCheck %s -D#INDX=5 --check-prefix=OBJ32 ; RUN: llc -filetype=obj -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s -o %t64.o -; RUN: llvm-readobj %t64.o --syms | FileCheck %s --check-prefix=OBJ64 +; RUN: llvm-readobj %t64.o --syms | FileCheck %s -D#INDX=5 --check-prefix=OBJ64 @i = global i32 55, align 4 #0 @@ -16,8 +16,7 @@ attributes #0 = { "toc-data" } ; CHECK-NEXT: .align 2 ; CHECK-NEXT: .vbyte 4, 55 -; OBJ32: Symbol { -; OBJ32: Index: 3 +; OBJ32: Index: [[#INDX]] ; OBJ32-NEXT: Name: TOC ; OBJ32-NEXT: Value (RelocatableAddress): 0x0 ; OBJ32-NEXT: Section: .data @@ -25,7 +24,7 @@ attributes #0 = { "toc-data" } ; OBJ32-NEXT: StorageClass: C_HIDEXT (0x6B) ; OBJ32-NEXT: NumberOfAuxEntries: 1 ; OBJ32-NEXT: CSECT Auxiliary Entry { -; OBJ32-NEXT: Index: 4 +; OBJ32-NEXT: Index: [[#INDX+1]] ; OBJ32-NEXT: SectionLen: 0 ; OBJ32-NEXT: ParameterHashIndex: 0x0 ; OBJ32-NEXT: TypeChkSectNum: 0x0 @@ -37,7 +36,7 @@ attributes #0 = { "toc-data" } ; OBJ32-NEXT: } ; OBJ32-NEXT: } ; OBJ32-NEXT: Symbol { -; OBJ32-NEXT: Index: 5 +; OBJ32-NEXT: Index: [[#INDX+2]] ; OBJ32-NEXT: Name: i ; OBJ32-NEXT: Value (RelocatableAddress): 0x0 ; OBJ32-NEXT: Section: .data @@ -45,7 +44,7 @@ attributes #0 = { "toc-data" } ; OBJ32-NEXT: StorageClass: C_EXT (0x2) ; OBJ32-NEXT: NumberOfAuxEntries: 1 ; OBJ32-NEXT: CSECT Auxiliary Entry { -; OBJ32-NEXT: Index: 6 +; OBJ32-NEXT: Index: [[#INDX+3]] ; OBJ32-NEXT: SectionLen: 4 ; OBJ32-NEXT: ParameterHashIndex: 0x0 ; OBJ32-NEXT: TypeChkSectNum: 0x0 @@ -57,8 +56,7 @@ attributes #0 = { "toc-data" } ; OBJ32-NEXT: } ; OBJ32-NEXT: } -; OBJ64: Symbol { -; OBJ64: Index: 3 +; OBJ64: Index: [[#INDX]] ; OBJ64-NEXT: Name: TOC ; OBJ64-NEXT: Value (RelocatableAddress): 0x0 ; OBJ64-NEXT: Section: .data @@ -66,7 +64,7 @@ attributes #0 = { "toc-data" } ; OBJ64-NEXT: StorageClass: C_HIDEXT (0x6B) ; OBJ64-NEXT: NumberOfAuxEntries: 1 ; OBJ64-NEXT: CSECT Auxiliary Entry { -; OBJ64-NEXT: Index: 4 +; OBJ64-NEXT: Index: [[#INDX+1]] ; OBJ64-NEXT: SectionLen: 0 ; OBJ64-NEXT: ParameterHashIndex: 0x0 ; OBJ64-NEXT: TypeChkSectNum: 0x0 @@ -77,7 +75,7 @@ attributes #0 = { "toc-data" } ; OBJ64-NEXT: } ; OBJ64-NEXT: } ; OBJ64-NEXT: Symbol { -; OBJ64-NEXT: Index: 5 +; OBJ64-NEXT: Index: [[#INDX+2]] ; OBJ64-NEXT: Name: i ; OBJ64-NEXT: Value (RelocatableAddress): 0x0 ; OBJ64-NEXT: Section: .data @@ -85,7 +83,7 @@ attributes #0 = { "toc-data" } ; OBJ64-NEXT: StorageClass: C_EXT (0x2) ; OBJ64-NEXT: NumberOfAuxEntries: 1 ; OBJ64-NEXT: CSECT Auxiliary Entry { -; OBJ64-NEXT: Index: 6 +; OBJ64-NEXT: Index: [[#INDX+3]] ; OBJ64-NEXT: SectionLen: 4 ; OBJ64-NEXT: ParameterHashIndex: 0x0 ; OBJ64-NEXT: TypeChkSectNum: 0x0 diff --git a/llvm/test/CodeGen/PowerPC/basic-toc-data-extern.ll b/llvm/test/CodeGen/PowerPC/basic-toc-data-extern.ll index 04a2bfbf2dd4..0a649f683fea 100644 --- a/llvm/test/CodeGen/PowerPC/basic-toc-data-extern.ll +++ b/llvm/test/CodeGen/PowerPC/basic-toc-data-extern.ll @@ -2,9 +2,9 @@ ; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -filetype=obj -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s -o %t32.o -; RUN: llvm-readobj %t32.o --syms --relocs | FileCheck %s --check-prefix=OBJ32 +; RUN: llvm-readobj %t32.o --syms --relocs | FileCheck %s -D#NFA=2 --check-prefix=OBJ32 ; RUN: llc -filetype=obj -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s -o %t64.o -; RUN: llvm-readobj %t64.o --syms --relocs | FileCheck %s --check-prefix=OBJ64 +; RUN: llvm-readobj %t64.o --syms --relocs | FileCheck %s -D#NFA=2 --check-prefix=OBJ64 @i = external global i32, align 4 #0 @@ -22,16 +22,16 @@ attributes #0 = { "toc-data" } ; OBJ32: Relocations [ ; OBJ32-NEXT: Section (index: 1) .text { -; OBJ32-NEXT: 0x2 R_TOC i(1) 0xF +; OBJ32-NEXT: 0x2 R_TOC i([[#NFA+1]]) 0xF ; OBJ32-NEXT: } ; OBJ32-NEXT: Section (index: 2) .data { -; OBJ32-NEXT: 0x20 R_POS .get(5) 0x1F -; OBJ32-NEXT: 0x24 R_POS TOC(9) 0x1F +; OBJ32-NEXT: 0x20 R_POS .get([[#NFA+5]]) 0x1F +; OBJ32-NEXT: 0x24 R_POS TOC([[#NFA+9]]) 0x1F ; OBJ32-NEXT: } ; OBJ32-NEXT: ] ; OBJ32: Symbol { -; OBJ32: Index: 1 +; OBJ32: Index: [[#NFA+1]] ; OBJ32-NEXT: Name: i ; OBJ32-NEXT: Value (RelocatableAddress): 0x0 ; OBJ32-NEXT: Section: N_UNDEF @@ -39,7 +39,7 @@ attributes #0 = { "toc-data" } ; OBJ32-NEXT: StorageClass: C_EXT (0x2) ; OBJ32-NEXT: NumberOfAuxEntries: 1 ; OBJ32-NEXT: CSECT Auxiliary Entry { -; OBJ32-NEXT: Index: 2 +; OBJ32-NEXT: Index: [[#NFA+2]] ; OBJ32-NEXT: SectionLen: 0 ; OBJ32-NEXT: ParameterHashIndex: 0x0 ; OBJ32-NEXT: TypeChkSectNum: 0x0 @@ -51,7 +51,7 @@ attributes #0 = { "toc-data" } ; OBJ32-NEXT: } ; OBJ32-NEXT: } ; OBJ32: Symbol { -; OBJ32: Index: 9 +; OBJ32: Index: [[#NFA+9]] ; OBJ32-NEXT: Name: TOC ; OBJ32-NEXT: Value (RelocatableAddress): 0x2C ; OBJ32-NEXT: Section: .data @@ -59,7 +59,7 @@ attributes #0 = { "toc-data" } ; OBJ32-NEXT: StorageClass: C_HIDEXT (0x6B) ; OBJ32-NEXT: NumberOfAuxEntries: 1 ; OBJ32-NEXT: CSECT Auxiliary Entry { -; OBJ32-NEXT: Index: 10 +; OBJ32-NEXT: Index: [[#NFA+10]] ; OBJ32-NEXT: SectionLen: 0 ; OBJ32-NEXT: ParameterHashIndex: 0x0 ; OBJ32-NEXT: TypeChkSectNum: 0x0 @@ -73,16 +73,16 @@ attributes #0 = { "toc-data" } ; OBJ64: Relocations [ ; OBJ64-NEXT: Section (index: 1) .text { -; OBJ64-NEXT: 0x2 R_TOC i(1) 0xF +; OBJ64-NEXT: 0x2 R_TOC i([[#NFA+1]]) 0xF ; OBJ64-NEXT: } ; OBJ64-NEXT: Section (index: 2) .data { -; OBJ64-NEXT: 0x20 R_POS .get(5) 0x3F -; OBJ64-NEXT: 0x28 R_POS TOC(9) 0x3F +; OBJ64-NEXT: 0x20 R_POS .get([[#NFA+5]]) 0x3F +; OBJ64-NEXT: 0x28 R_POS TOC([[#NFA+9]]) 0x3F ; OBJ64-NEXT: } ; OBJ64-NEXT: ] ; OBJ64: Symbol { -; OBJ64: Index: 1 +; OBJ64: Index: [[#NFA+1]] ; OBJ64-NEXT: Name: i ; OBJ64-NEXT: Value (RelocatableAddress): 0x0 ; OBJ64-NEXT: Section: N_UNDEF @@ -90,7 +90,7 @@ attributes #0 = { "toc-data" } ; OBJ64-NEXT: StorageClass: C_EXT (0x2) ; OBJ64-NEXT: NumberOfAuxEntries: 1 ; OBJ64-NEXT: CSECT Auxiliary Entry { -; OBJ64-NEXT: Index: 2 +; OBJ64-NEXT: Index: [[#NFA+2]] ; OBJ64-NEXT: SectionLen: 0 ; OBJ64-NEXT: ParameterHashIndex: 0x0 ; OBJ64-NEXT: TypeChkSectNum: 0x0 @@ -101,7 +101,7 @@ attributes #0 = { "toc-data" } ; OBJ64-NEXT: } ; OBJ64-NEXT: } ; OBJ64: Symbol { -; OBJ64: Index: 9 +; OBJ64: Index: [[#NFA+9]] ; OBJ64-NEXT: Name: TOC ; OBJ64-NEXT: Value (RelocatableAddress): 0x38 ; OBJ64-NEXT: Section: .data @@ -109,7 +109,7 @@ attributes #0 = { "toc-data" } ; OBJ64-NEXT: StorageClass: C_HIDEXT (0x6B) ; OBJ64-NEXT: NumberOfAuxEntries: 1 ; OBJ64-NEXT: CSECT Auxiliary Entry { -; OBJ64-NEXT: Index: 10 +; OBJ64-NEXT: Index: [[#NFA+10]] ; OBJ64-NEXT: SectionLen: 0 ; OBJ64-NEXT: ParameterHashIndex: 0x0 ; OBJ64-NEXT: TypeChkSectNum: 0x0 diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-annotations-td.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-annotations-td.ll index 17c2b438a94a..1e48b1242f85 100644 --- a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-annotations-td.ll +++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-annotations-td.ll @@ -9,7 +9,7 @@ ; Check that we do not crash in object mode ; OBJ64: Exception section { -; OBJ64-NEXT: Symbol: .test__tdw_annotation (6) +; OBJ64-NEXT: Symbol: .test__tdw_annotation !1 = !{!"ppc-trap-reason", !"1", !"2"} declare void @llvm.ppc.trapd(i64 %a) diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-annotations-tw.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-annotations-tw.ll index 24a0723bf39c..d18d075590d2 100644 --- a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-annotations-tw.ll +++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-annotations-tw.ll @@ -13,7 +13,7 @@ ; Check that we do not crash in object mode ; OBJ: Exception section { -; OBJ-NEXT: Symbol: .test__trap_annotation (3) +; OBJ-NEXT: Symbol: .test__trap_annotation !1 = !{!"ppc-trap-reason", !"1", !"2"} declare void @llvm.ppc.trap(i32 %a) diff --git a/llvm/test/CodeGen/PowerPC/pgo-ref-directive.ll b/llvm/test/CodeGen/PowerPC/pgo-ref-directive.ll index 480b44caaded..02b0a9ba4397 100644 --- a/llvm/test/CodeGen/PowerPC/pgo-ref-directive.ll +++ b/llvm/test/CodeGen/PowerPC/pgo-ref-directive.ll @@ -121,7 +121,7 @@ entry: ; WITHVNDS-NEXT: .ref __llvm_prf_vnds[RW] ; WITHVNDS-OBJ: SYMBOL TABLE: -; WITHVNDS-OBJ-NEXT: 00000000 df *DEBUG* 00000000 +; WITHVNDS-OBJ-NEXT: 00000000 df *DEBUG* 00000000 .file ; WITHVNDS-OBJ-NEXT: 00000000 l .text 00000008 ; WITHVNDS-OBJ-NEXT: 00000000 g F .text (csect: ) 00000000 .main ; WITHVNDS-OBJ-NEXT: 00000008 l .text 00000006 __llvm_prf_names diff --git a/llvm/test/CodeGen/PowerPC/toc-data-const.ll b/llvm/test/CodeGen/PowerPC/toc-data-const.ll index 740032e26a43..6972079d826e 100644 --- a/llvm/test/CodeGen/PowerPC/toc-data-const.ll +++ b/llvm/test/CodeGen/PowerPC/toc-data-const.ll @@ -2,11 +2,11 @@ ; RUN: llc -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s --check-prefix CHECK ; RUN: llc -filetype=obj -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s -o %t32.o -; RUN: llvm-readobj %t32.o --syms --relocs | FileCheck %s --check-prefix=OBJ32 +; RUN: llvm-readobj %t32.o --syms --relocs | FileCheck %s -D#NFA=2 --check-prefix=OBJ32 ; RUN: llvm-objdump %t32.o -dr | FileCheck %s --check-prefix=DIS32 ; RUN: llc -filetype=obj -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s -o %t64.o -; RUN: llvm-readobj %t64.o --syms --relocs | FileCheck %s --check-prefix=OBJ64 +; RUN: llvm-readobj %t64.o --syms --relocs | FileCheck %s -D#NFA=2 --check-prefix=OBJ64 ; RUN: llvm-objdump %t64.o -dr | FileCheck %s --check-prefix=DIS64 @i1 = external constant i32 #0 @@ -35,20 +35,20 @@ attributes #0 = { "toc-data" } ; OBJ32: Relocations [ ; OBJ32-NEXT: Section (index: 1) .text { -; OBJ32-NEXT: 0x2 R_TOC i1(1) 0xF -; OBJ32-NEXT: 0x26 R_TOC i2(15) 0xF +; OBJ32-NEXT: 0x2 R_TOC i1([[#NFA+1]]) 0xF +; OBJ32-NEXT: 0x26 R_TOC i2([[#NFA+15]]) 0xF ; OBJ32-NEXT: } ; OBJ32-NEXT: Section (index: 2) .data { -; OBJ32-NEXT: 0x44 R_POS .read(5) 0x1F -; OBJ32-NEXT: 0x48 R_POS TOC(13) 0x1F -; OBJ32-NEXT: 0x50 R_POS .retptr(7) 0x1F -; OBJ32-NEXT: 0x54 R_POS TOC(13) 0x1F -; OBJ32-NEXT: 0x5C R_POS i1(1) 0x1F +; OBJ32-NEXT: 0x44 R_POS .read([[#NFA+5]]) 0x1F +; OBJ32-NEXT: 0x48 R_POS TOC([[#NFA+13]]) 0x1F +; OBJ32-NEXT: 0x50 R_POS .retptr([[#NFA+7]]) 0x1F +; OBJ32-NEXT: 0x54 R_POS TOC([[#NFA+13]]) 0x1F +; OBJ32-NEXT: 0x5C R_POS i1([[#NFA+1]]) 0x1F ; OBJ32-NEXT: } ; OBJ32-NEXT: ] ; OBJ32: Symbol { -; OBJ32: Index: 1 +; OBJ32: Index: [[#NFA+1]] ; OBJ32-NEXT: Name: i1 ; OBJ32-NEXT: Value (RelocatableAddress): 0x0 ; OBJ32-NEXT: Section: N_UNDEF @@ -56,7 +56,7 @@ attributes #0 = { "toc-data" } ; OBJ32-NEXT: StorageClass: C_EXT (0x2) ; OBJ32-NEXT: NumberOfAuxEntries: 1 ; OBJ32-NEXT: CSECT Auxiliary Entry { -; OBJ32-NEXT: Index: 2 +; OBJ32-NEXT: Index: [[#NFA+2]] ; OBJ32-NEXT: SectionLen: 0 ; OBJ32-NEXT: ParameterHashIndex: 0x0 ; OBJ32-NEXT: TypeChkSectNum: 0x0 @@ -68,7 +68,7 @@ attributes #0 = { "toc-data" } ; OBJ32-NEXT: } ; OBJ32-NEXT: } ; OBJ32: Symbol { -; OBJ32: Index: 13 +; OBJ32: Index: [[#NFA+13]] ; OBJ32-NEXT: Name: TOC ; OBJ32-NEXT: Value (RelocatableAddress): 0x5C ; OBJ32-NEXT: Section: .data @@ -76,7 +76,7 @@ attributes #0 = { "toc-data" } ; OBJ32-NEXT: StorageClass: C_HIDEXT (0x6B) ; OBJ32-NEXT: NumberOfAuxEntries: 1 ; OBJ32-NEXT: CSECT Auxiliary Entry { -; OBJ32-NEXT: Index: 14 +; OBJ32-NEXT: Index: [[#NFA+14]] ; OBJ32-NEXT: SectionLen: 0 ; OBJ32-NEXT: ParameterHashIndex: 0x0 ; OBJ32-NEXT: TypeChkSectNum: 0x0 @@ -88,7 +88,7 @@ attributes #0 = { "toc-data" } ; OBJ32-NEXT: } ; OBJ32-NEXT: } ; OBJ32: Symbol { -; OBJ32: Index: 15 +; OBJ32: Index: [[#NFA+15]] ; OBJ32-NEXT: Name: i2 ; OBJ32-NEXT: Value (RelocatableAddress): 0x5C ; OBJ32-NEXT: Section: .data @@ -96,7 +96,7 @@ attributes #0 = { "toc-data" } ; OBJ32-NEXT: StorageClass: C_EXT (0x2) ; OBJ32-NEXT: NumberOfAuxEntries: 1 ; OBJ32-NEXT: CSECT Auxiliary Entry { -; OBJ32-NEXT: Index: 16 +; OBJ32-NEXT: Index: [[#NFA+16]] ; OBJ32-NEXT: SectionLen: 4 ; OBJ32-NEXT: ParameterHashIndex: 0x0 ; OBJ32-NEXT: TypeChkSectNum: 0x0 @@ -110,20 +110,20 @@ attributes #0 = { "toc-data" } ; OBJ64: Relocations [ ; OBJ64-NEXT: Section (index: 1) .text { -; OBJ64-NEXT: 0x2 R_TOC i1(1) 0xF -; OBJ64-NEXT: 0x26 R_TOC i2(15) 0xF +; OBJ64-NEXT: 0x2 R_TOC i1([[#NFA+1]]) 0xF +; OBJ64-NEXT: 0x26 R_TOC i2([[#NFA+15]]) 0xF ; OBJ64-NEXT: } ; OBJ64-NEXT: Section (index: 2) .data { -; OBJ64-NEXT: 0x48 R_POS .read(5) 0x3F -; OBJ64-NEXT: 0x50 R_POS TOC(13) 0x3F -; OBJ64-NEXT: 0x60 R_POS .retptr(7) 0x3F -; OBJ64-NEXT: 0x68 R_POS TOC(13) 0x3F -; OBJ64-NEXT: 0x78 R_POS i1(1) 0x3F +; OBJ64-NEXT: 0x48 R_POS .read([[#NFA+5]]) 0x3F +; OBJ64-NEXT: 0x50 R_POS TOC([[#NFA+13]]) 0x3F +; OBJ64-NEXT: 0x60 R_POS .retptr([[#NFA+7]]) 0x3F +; OBJ64-NEXT: 0x68 R_POS TOC([[#NFA+13]]) 0x3F +; OBJ64-NEXT: 0x78 R_POS i1([[#NFA+1]]) 0x3F ; OBJ64-NEXT: } ; OBJ64-NEXT: ] ; OBJ64: Symbol { -; OBJ64: Index: 1 +; OBJ64: Index: [[#NFA+1]] ; OBJ64-NEXT: Name: i1 ; OBJ64-NEXT: Value (RelocatableAddress): 0x0 ; OBJ64-NEXT: Section: N_UNDEF @@ -131,7 +131,7 @@ attributes #0 = { "toc-data" } ; OBJ64-NEXT: StorageClass: C_EXT (0x2) ; OBJ64-NEXT: NumberOfAuxEntries: 1 ; OBJ64-NEXT: CSECT Auxiliary Entry { -; OBJ64-NEXT: Index: 2 +; OBJ64-NEXT: Index: [[#NFA+2]] ; OBJ64-NEXT: SectionLen: 0 ; OBJ64-NEXT: ParameterHashIndex: 0x0 ; OBJ64-NEXT: TypeChkSectNum: 0x0 @@ -142,7 +142,7 @@ attributes #0 = { "toc-data" } ; OBJ64-NEXT: } ; OBJ64-NEXT: } ; OBJ64: Symbol { -; OBJ64: Index: 13 +; OBJ64: Index: [[#NFA+13]] ; OBJ64-NEXT: Name: TOC ; OBJ64-NEXT: Value (RelocatableAddress): 0x78 ; OBJ64-NEXT: Section: .data @@ -150,7 +150,7 @@ attributes #0 = { "toc-data" } ; OBJ64-NEXT: StorageClass: C_HIDEXT (0x6B) ; OBJ64-NEXT: NumberOfAuxEntries: 1 ; OBJ64-NEXT: CSECT Auxiliary Entry { -; OBJ64-NEXT: Index: 14 +; OBJ64-NEXT: Index: [[#NFA+14]] ; OBJ64-NEXT: SectionLen: 0 ; OBJ64-NEXT: ParameterHashIndex: 0x0 ; OBJ64-NEXT: TypeChkSectNum: 0x0 @@ -161,7 +161,7 @@ attributes #0 = { "toc-data" } ; OBJ64-NEXT: } ; OBJ64-NEXT: } ; OBJ64: Symbol { -; OBJ64: Index: 15 +; OBJ64: Index: [[#NFA+15]] ; OBJ64-NEXT: Name: i2 ; OBJ64-NEXT: Value (RelocatableAddress): 0x78 ; OBJ64-NEXT: Section: .data @@ -169,7 +169,7 @@ attributes #0 = { "toc-data" } ; OBJ64-NEXT: StorageClass: C_EXT (0x2) ; OBJ64-NEXT: NumberOfAuxEntries: 1 ; OBJ64-NEXT: CSECT Auxiliary Entry { -; OBJ64-NEXT: Index: 16 +; OBJ64-NEXT: Index: [[#NFA+16]] ; OBJ64-NEXT: SectionLen: 8 ; OBJ64-NEXT: ParameterHashIndex: 0x0 ; OBJ64-NEXT: TypeChkSectNum: 0x0 diff --git a/llvm/test/MC/PowerPC/aix-file-symbols.s b/llvm/test/MC/PowerPC/aix-file-symbols.s index 7ab0244f3c71..42aecb74a851 100644 --- a/llvm/test/MC/PowerPC/aix-file-symbols.s +++ b/llvm/test/MC/PowerPC/aix-file-symbols.s @@ -1,6 +1,6 @@ ## Check mutiple C_FILE symbols are emitted. # RUN: llvm-mc -triple powerpc-ibm-aix-xcoff %s -filetype=obj -o - | \ -# RUN: llvm-objdump --syms - | FileCheck %s +# RUN: llvm-readobj --syms - | FileCheck %s .file "1.c" .globl .var1 @@ -10,10 +10,10 @@ .var2: .file "3.c" -# CHECK: SYMBOL TABLE: -# CHECK-NEXT: 00000000 df *DEBUG* 00000000 1.c -# CHECK-NEXT: 00000000 df *DEBUG* 00000000 2.c -# CHECK-NEXT: 00000000 df *DEBUG* 00000000 3.c -# CHECK-NEXT: 00000000 l .text 00000000 -# CHECK-NEXT: 00000000 g F .text (csect: ) 00000000 .var1 -# CHECK-NEXT: 00000000 g F .text (csect: ) 00000000 .var2 +# CHECK: Symbols [ +# CHECK: Name: 1.c +# CHECK-NEXT: Type: XFT_FN (0x0) +# CHECK: Name: 2.c +# CHECK-NEXT: Type: XFT_FN (0x0) +# CHECK: Name: 3.c +# CHECK-NEXT: Type: XFT_FN (0x0) diff --git a/llvm/test/tools/llvm-objdump/XCOFF/symbol-table.test b/llvm/test/tools/llvm-objdump/XCOFF/symbol-table.test index f8fc114f05a6..94b04c5e89c6 100644 --- a/llvm/test/tools/llvm-objdump/XCOFF/symbol-table.test +++ b/llvm/test/tools/llvm-objdump/XCOFF/symbol-table.test @@ -1,8 +1,8 @@ ; Test the --syms option for xcoff object files. ; Also test the --symbol-description option for xcoff object files, when specified with --syms. ; RUN: llc -mtriple powerpc-ibm-aix -mcpu=pwr4 -filetype=obj -o %t.o < %s -; RUN: llvm-objdump --syms %t.o | FileCheck --check-prefix=SYM %s -; RUN: llvm-objdump --syms --symbol-description %t.o | FileCheck --check-prefix=SYM-DES %s +; RUN: llvm-objdump --syms %t.o | FileCheck -D#NFA=2 --check-prefix=SYM %s +; RUN: llvm-objdump --syms --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=SYM-DES %s ;; The IR below is generated by the following source code. ;; bash> cat test.c @@ -66,7 +66,7 @@ entry: } ; SYM: SYMBOL TABLE: -; SYM-NEXT: 00000000 df *DEBUG* 00000000 +; SYM-NEXT: 00000000 df *DEBUG* 00000000 .file ; SYM-NEXT: 00000000 *UND* 00000000 ei ; SYM-NEXT: 00000000 l .text 00000091 ; SYM-NEXT: 00000000 g F .text (csect: ) 00000000 .bar @@ -88,23 +88,23 @@ entry: ; SYM-NEXT: 000000ec l O *COM* 00000004 si ; SYM-DES: SYMBOL TABLE: -; SYM-DES-NEXT: 00000000 df *DEBUG* 00000000 (idx: 0) -; SYM-DES-NEXT: 00000000 *UND* 00000000 (idx: 1) ei[UA] -; SYM-DES-NEXT: 00000000 l .text 00000091 (idx: 3) [PR] -; SYM-DES-NEXT: 00000000 g F .text (csect: (idx: 3) [PR]) 00000000 (idx: 5) .bar -; SYM-DES-NEXT: 00000050 g F .text (csect: (idx: 3) [PR]) 00000000 (idx: 7) .foo -; SYM-DES-NEXT: 00000094 l .text 00000013 (idx: 9) L...str[RO] -; SYM-DES-NEXT: 000000a8 g O .data 00000004 (idx: 11) con[RW] -; SYM-DES-NEXT: 000000ac w O .data 00000004 (idx: 13) wi[RW] -; SYM-DES-NEXT: 000000b0 g O .data 00000004 (idx: 15) i[RW] -; SYM-DES-NEXT: 000000b4 g O .data 00000001 (idx: 17) c[RW] -; SYM-DES-NEXT: 000000b8 g O .data 00000004 (idx: 19) ap[RW] -; SYM-DES-NEXT: 000000bc g O .data 00000004 (idx: 21) f[RW] -; SYM-DES-NEXT: 000000c0 g O .data 00000008 (idx: 23) ll[RW] -; SYM-DES-NEXT: 000000c8 g O .data 0000000c (idx: 25) bar[DS] -; SYM-DES-NEXT: 000000d4 g O .data 0000000c (idx: 27) foo[DS] -; SYM-DES-NEXT: 000000e0 l .data 00000000 (idx: 29) TOC[TC0] -; SYM-DES-NEXT: 000000e0 l O .data 00000004 (idx: 31) si[TC] -; SYM-DES-NEXT: 000000e4 l O .data 00000004 (idx: 33) ei[TC] -; SYM-DES-NEXT: 000000e8 l O .data 00000004 (idx: 35) con[TC] -; SYM-DES-NEXT: 000000ec l O *COM* 00000004 (idx: 37) si[BS] +; SYM-DES-NEXT: 00000000 df *DEBUG* 00000000 (idx: 0) .file +; SYM-DES-NEXT: 00000000 *UND* 00000000 (idx: [[#NFA+1]]) ei[UA] +; SYM-DES-NEXT: 00000000 l .text 00000091 (idx: [[#NFA+3]]) [PR] +; SYM-DES-NEXT: 00000000 g F .text (csect: (idx: [[#NFA+3]]) [PR]) 00000000 (idx: [[#NFA+5]]) .bar +; SYM-DES-NEXT: 00000050 g F .text (csect: (idx: [[#NFA+3]]) [PR]) 00000000 (idx: [[#NFA+7]]) .foo +; SYM-DES-NEXT: 00000094 l .text 00000013 (idx: [[#NFA+9]]) L...str[RO] +; SYM-DES-NEXT: 000000a8 g O .data 00000004 (idx: [[#NFA+11]]) con[RW] +; SYM-DES-NEXT: 000000ac w O .data 00000004 (idx: [[#NFA+13]]) wi[RW] +; SYM-DES-NEXT: 000000b0 g O .data 00000004 (idx: [[#NFA+15]]) i[RW] +; SYM-DES-NEXT: 000000b4 g O .data 00000001 (idx: [[#NFA+17]]) c[RW] +; SYM-DES-NEXT: 000000b8 g O .data 00000004 (idx: [[#NFA+19]]) ap[RW] +; SYM-DES-NEXT: 000000bc g O .data 00000004 (idx: [[#NFA+21]]) f[RW] +; SYM-DES-NEXT: 000000c0 g O .data 00000008 (idx: [[#NFA+23]]) ll[RW] +; SYM-DES-NEXT: 000000c8 g O .data 0000000c (idx: [[#NFA+25]]) bar[DS] +; SYM-DES-NEXT: 000000d4 g O .data 0000000c (idx: [[#NFA+27]]) foo[DS] +; SYM-DES-NEXT: 000000e0 l .data 00000000 (idx: [[#NFA+29]]) TOC[TC0] +; SYM-DES-NEXT: 000000e0 l O .data 00000004 (idx: [[#NFA+31]]) si[TC] +; SYM-DES-NEXT: 000000e4 l O .data 00000004 (idx: [[#NFA+33]]) ei[TC] +; SYM-DES-NEXT: 000000e8 l O .data 00000004 (idx: [[#NFA+35]]) con[TC] +; SYM-DES-NEXT: 000000ec l O *COM* 00000004 (idx: [[#NFA+37]]) si[BS] -- GitLab From d4c5acac99e83ffa12d2d720c9e502a181cbd7ea Mon Sep 17 00:00:00 2001 From: Fraser Cormack Date: Tue, 6 Feb 2024 15:23:24 +0000 Subject: [PATCH 080/266] [ExecutionEngine] Fix a couple of typos (NFC) --- llvm/lib/ExecutionEngine/GDBRegistrationListener.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/ExecutionEngine/GDBRegistrationListener.cpp b/llvm/lib/ExecutionEngine/GDBRegistrationListener.cpp index b5b76130c55e..1250c0defd31 100644 --- a/llvm/lib/ExecutionEngine/GDBRegistrationListener.cpp +++ b/llvm/lib/ExecutionEngine/GDBRegistrationListener.cpp @@ -56,9 +56,9 @@ extern "C" { namespace { // FIXME: lli aims to provide both, RuntimeDyld and JITLink, as the dynamic -// loaders for it's JIT implementations. And they both offer debugging via the +// loaders for its JIT implementations. And they both offer debugging via the // GDB JIT interface, which builds on the two well-known symbol names below. -// As these symbols must be unique accross the linked executable, we can only +// As these symbols must be unique across the linked executable, we can only // define them in one of the libraries and make the other depend on it. // OrcTargetProcess is a minimal stub for embedding a JIT client in remote // executors. For the moment it seems reasonable to have the definition there -- GitLab From d6c7253d32e4bdff619c39708170f1c1fa01ff95 Mon Sep 17 00:00:00 2001 From: David Stuttard Date: Tue, 6 Feb 2024 15:34:36 +0000 Subject: [PATCH 081/266] [AMDGPU] Add pal metadata 3.0 support to callable pal funcs (#67104) PAL Metadata 3.0 introduces an explicit structure in metadata for the programmable registers written out by the compiler backend. The previous approach used opaque registers which can change between different architectures and required encoding the bitfield information in the backend, which may change between versions. This change is an extension the previously added support - which only handled entry functions. This adds support for all functions. The change also includes some re-factoring to separate common code. --- llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 54 ++-- .../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 5 + llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 5 + .../AMDGPU/pal-metadata-3.0-callable.ll | 305 ++++++++++++++++++ 4 files changed, 347 insertions(+), 22 deletions(-) create mode 100644 llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable.ll diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp index db81e1ee9e38..059df7879dd5 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp @@ -1025,6 +1025,27 @@ void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF, OutStreamer->emitInt32(MFI->getNumSpilledVGPRs()); } +// Helper function to add common PAL Metadata 3.0+ +static void EmitPALMetadataCommon(AMDGPUPALMetadata *MD, + const SIProgramInfo &CurrentProgramInfo, + CallingConv::ID CC, const GCNSubtarget &ST) { + if (ST.hasIEEEMode()) + MD->setHwStage(CC, ".ieee_mode", (bool)CurrentProgramInfo.IEEEMode); + + MD->setHwStage(CC, ".wgp_mode", (bool)CurrentProgramInfo.WgpMode); + MD->setHwStage(CC, ".mem_ordered", (bool)CurrentProgramInfo.MemOrdered); + + if (AMDGPU::isCompute(CC)) { + MD->setHwStage(CC, ".trap_present", + (bool)CurrentProgramInfo.TrapHandlerEnable); + MD->setHwStage(CC, ".excp_en", CurrentProgramInfo.EXCPEnable); + + MD->setHwStage(CC, ".lds_size", + (unsigned)(CurrentProgramInfo.LdsSize * + getLdsDwGranularity(ST) * sizeof(uint32_t))); + } +} + // This is the equivalent of EmitProgramInfoSI above, but for when the OS type // is AMDPAL. It stores each compute/SPI register setting and other PAL // metadata items into the PALMD::Metadata, combining with any provided by the @@ -1056,24 +1077,8 @@ void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF, } } else { MD->setHwStage(CC, ".debug_mode", (bool)CurrentProgramInfo.DebugMode); - MD->setHwStage(CC, ".ieee_mode", (bool)CurrentProgramInfo.IEEEMode); - MD->setHwStage(CC, ".wgp_mode", (bool)CurrentProgramInfo.WgpMode); - MD->setHwStage(CC, ".mem_ordered", (bool)CurrentProgramInfo.MemOrdered); - - if (AMDGPU::isCompute(CC)) { - MD->setHwStage(CC, ".scratch_en", (bool)CurrentProgramInfo.ScratchEnable); - MD->setHwStage(CC, ".trap_present", - (bool)CurrentProgramInfo.TrapHandlerEnable); - - // EXCPEnMSB? - const unsigned LdsDwGranularity = 128; - MD->setHwStage(CC, ".lds_size", - (unsigned)(CurrentProgramInfo.LdsSize * LdsDwGranularity * - sizeof(uint32_t))); - MD->setHwStage(CC, ".excp_en", CurrentProgramInfo.EXCPEnable); - } else { - MD->setHwStage(CC, ".scratch_en", (bool)CurrentProgramInfo.ScratchEnable); - } + MD->setHwStage(CC, ".scratch_en", (bool)CurrentProgramInfo.ScratchEnable); + EmitPALMetadataCommon(MD, CurrentProgramInfo, CC, STM); } // ScratchSize is in bytes, 16 aligned. @@ -1127,10 +1132,15 @@ void AMDGPUAsmPrinter::emitPALFunctionMetadata(const MachineFunction &MF) { MD->setFunctionScratchSize(FnName, MFI.getStackSize()); const GCNSubtarget &ST = MF.getSubtarget(); - // Set compute registers - MD->setRsrc1(CallingConv::AMDGPU_CS, - CurrentProgramInfo.getPGMRSrc1(CallingConv::AMDGPU_CS, ST)); - MD->setRsrc2(CallingConv::AMDGPU_CS, CurrentProgramInfo.getComputePGMRSrc2()); + if (MD->getPALMajorVersion() < 3) { + // Set compute registers + MD->setRsrc1(CallingConv::AMDGPU_CS, + CurrentProgramInfo.getPGMRSrc1(CallingConv::AMDGPU_CS, ST)); + MD->setRsrc2(CallingConv::AMDGPU_CS, + CurrentProgramInfo.getComputePGMRSrc2()); + } else { + EmitPALMetadataCommon(MD, CurrentProgramInfo, CallingConv::AMDGPU_CS, ST); + } // Set optional info MD->setFunctionLdsSize(FnName, CurrentProgramInfo.LDSSize); diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp index 33335ac75df7..71b315a94300 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp @@ -2958,6 +2958,11 @@ bool isDPALU_DPP(const MCInstrDesc &OpDesc) { return hasAny64BitVGPROperands(OpDesc); } +unsigned getLdsDwGranularity(const MCSubtargetInfo &ST) { + // Currently this is 128 for all subtargets + return 128; +} + } // namespace AMDGPU raw_ostream &operator<<(raw_ostream &OS, diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h index f24b9f0e3615..ae3afb334127 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h @@ -1439,6 +1439,11 @@ bool isIntrinsicSourceOfDivergence(unsigned IntrID); /// \returns true if the intrinsic is uniform bool isIntrinsicAlwaysUniform(unsigned IntrID); +/// \returns lds block size in terms of dwords. \p +/// This is used to calculate the lds size encoded for PAL metadata 3.0+ which +/// must be defined in terms of bytes. +unsigned getLdsDwGranularity(const MCSubtargetInfo &ST); + } // end namespace AMDGPU raw_ostream &operator<<(raw_ostream &OS, diff --git a/llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable.ll b/llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable.ll new file mode 100644 index 000000000000..538ce15979de --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable.ll @@ -0,0 +1,305 @@ +; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s + +; CHECK: .amdgpu_pal_metadata +; CHECK-NEXT: --- +; CHECK-NEXT: amdpal.pipelines: +; CHECK-NEXT: - .api: Vulkan +; CHECK-NEXT: .compute_registers: +; CHECK-NEXT: .tg_size_en: true +; CHECK-NEXT: .tgid_x_en: false +; CHECK-NEXT: .tgid_y_en: false +; CHECK-NEXT: .tgid_z_en: false +; CHECK-NEXT: .tidig_comp_cnt: 0x1 +; CHECK-NEXT: .hardware_stages: +; CHECK-NEXT: .cs: +; CHECK-NEXT: .checksum_value: 0x9444d7d0 +; CHECK-NEXT: .debug_mode: 0 +; CHECK-NEXT: .excp_en: 0 +; CHECK-NEXT: .float_mode: 0xc0 +; CHECK-NEXT: .ieee_mode: true +; CHECK-NEXT: .image_op: false +; CHECK-NEXT: .lds_size: 0x200 +; CHECK-NEXT: .mem_ordered: true +; CHECK-NEXT: .sgpr_limit: 0x6a +; CHECK-NEXT: .threadgroup_dimensions: +; CHECK-NEXT: - 0x1 +; CHECK-NEXT: - 0x400 +; CHECK-NEXT: - 0x1 +; CHECK-NEXT: .trap_present: false +; CHECK-NEXT: .user_data_reg_map: +; CHECK-NEXT: - 0x10000000 +; CHECK-NEXT: - 0xffffffff +; CHECK-NEXT: - 0 +; CHECK-NEXT: - 0xffffffff +; CHECK-NEXT: - 0xffffffff +; CHECK-NEXT: - 0xffffffff +; CHECK-NEXT: - 0xffffffff +; CHECK-NEXT: - 0xffffffff +; CHECK-NEXT: - 0xffffffff +; CHECK-NEXT: - 0xffffffff +; CHECK-NEXT: - 0xffffffff +; CHECK-NEXT: - 0xffffffff +; CHECK-NEXT: - 0xffffffff +; CHECK-NEXT: - 0xffffffff +; CHECK-NEXT: - 0xffffffff +; CHECK-NEXT: - 0xffffffff +; CHECK-NEXT: - 0xffffffff +; CHECK-NEXT: - 0xffffffff +; CHECK-NEXT: - 0xffffffff +; CHECK-NEXT: - 0xffffffff +; CHECK-NEXT: - 0xffffffff +; CHECK-NEXT: - 0xffffffff +; CHECK-NEXT: - 0xffffffff +; CHECK-NEXT: - 0xffffffff +; CHECK-NEXT: - 0xffffffff +; CHECK-NEXT: - 0xffffffff +; CHECK-NEXT: - 0xffffffff +; CHECK-NEXT: - 0xffffffff +; CHECK-NEXT: - 0xffffffff +; CHECK-NEXT: - 0xffffffff +; CHECK-NEXT: - 0xffffffff +; CHECK-NEXT: - 0xffffffff +; CHECK-NEXT: .user_sgprs: 0x3 +; CHECK-NEXT: .vgpr_limit: 0x100 +; CHECK-NEXT: .wavefront_size: 0x40 +; CHECK-NEXT: .wgp_mode: true +; CHECK: .registers: {} +; CHECK-NEXT: .shader_functions: +; CHECK-NEXT: dynamic_stack: +; CHECK-NEXT: .backend_stack_size: 0x10 +; CHECK-NEXT: .lds_size: 0 +; CHECK-NEXT: .sgpr_count: 0x22 +; CHECK-NEXT: .stack_frame_size_in_bytes: 0x10 +; CHECK-NEXT: .vgpr_count: 0x2 +; CHECK-NEXT: dynamic_stack_loop: +; CHECK-NEXT: .backend_stack_size: 0x10 +; CHECK-NEXT: .lds_size: 0 +; CHECK-NEXT: .sgpr_count: 0x22 +; CHECK-NEXT: .stack_frame_size_in_bytes: 0x10 +; CHECK-NEXT: .vgpr_count: 0x3 +; CHECK-NEXT: multiple_stack: +; CHECK-NEXT: .backend_stack_size: 0x24 +; CHECK-NEXT: .lds_size: 0 +; CHECK-NEXT: .sgpr_count: 0x21 +; CHECK-NEXT: .stack_frame_size_in_bytes: 0x24 +; CHECK-NEXT: .vgpr_count: 0x3 +; CHECK-NEXT: no_stack: +; CHECK-NEXT: .backend_stack_size: 0 +; CHECK-NEXT: .lds_size: 0 +; CHECK-NEXT: .sgpr_count: 0x20 +; CHECK-NEXT: .stack_frame_size_in_bytes: 0 +; CHECK-NEXT: .vgpr_count: 0x1 +; CHECK-NEXT: no_stack_call: +; CHECK-NEXT: .backend_stack_size: 0x10 +; CHECK-NEXT: .lds_size: 0 +; CHECK-NEXT: .sgpr_count: 0x22 +; CHECK-NEXT: .stack_frame_size_in_bytes: 0x10 +; CHECK-NEXT: .vgpr_count: 0x3 +; CHECK-NEXT: no_stack_extern_call: +; CHECK-NEXT: .backend_stack_size: 0x10 +; CHECK-NEXT: .lds_size: 0 +; CHECK-NEXT: .sgpr_count: 0x29 +; CHECK-NEXT: .stack_frame_size_in_bytes: 0x10 +; CHECK-NEXT: .vgpr_count: 0x58 +; CHECK-NEXT: no_stack_extern_call_many_args: +; CHECK-NEXT: .backend_stack_size: 0x90 +; CHECK-NEXT: .lds_size: 0 +; CHECK-NEXT: .sgpr_count: 0x29 +; CHECK-NEXT: .stack_frame_size_in_bytes: 0x90 +; CHECK-NEXT: .vgpr_count: 0x58 +; CHECK-NEXT: no_stack_indirect_call: +; CHECK-NEXT: .backend_stack_size: 0x10 +; CHECK-NEXT: .lds_size: 0 +; CHECK-NEXT: .sgpr_count: 0x29 +; CHECK-NEXT: .stack_frame_size_in_bytes: 0x10 +; CHECK-NEXT: .vgpr_count: 0x58 +; CHECK-NEXT: simple_lds: +; CHECK-NEXT: .backend_stack_size: 0 +; CHECK-NEXT: .lds_size: 0x100 +; CHECK-NEXT: .sgpr_count: 0x20 +; CHECK-NEXT: .stack_frame_size_in_bytes: 0 +; CHECK-NEXT: .vgpr_count: 0x1 +; CHECK-NEXT: simple_lds_recurse: +; CHECK-NEXT: .backend_stack_size: 0x10 +; CHECK-NEXT: .lds_size: 0x100 +; CHECK-NEXT: .sgpr_count: 0x24 +; CHECK-NEXT: .stack_frame_size_in_bytes: 0x10 +; CHECK-NEXT: .vgpr_count: 0x29 +; CHECK-NEXT: simple_stack: +; CHECK-NEXT: .backend_stack_size: 0x14 +; CHECK-NEXT: .lds_size: 0 +; CHECK-NEXT: .sgpr_count: 0x21 +; CHECK-NEXT: .stack_frame_size_in_bytes: 0x14 +; CHECK-NEXT: .vgpr_count: 0x2 +; CHECK-NEXT: simple_stack_call: +; CHECK-NEXT: .backend_stack_size: 0x20 +; CHECK-NEXT: .lds_size: 0 +; CHECK-NEXT: .sgpr_count: 0x22 +; CHECK-NEXT: .stack_frame_size_in_bytes: 0x20 +; CHECK-NEXT: .vgpr_count: 0x4 +; CHECK-NEXT: simple_stack_extern_call: +; CHECK-NEXT: .backend_stack_size: 0x20 +; CHECK-NEXT: .lds_size: 0 +; CHECK-NEXT: .sgpr_count: 0x29 +; CHECK-NEXT: .stack_frame_size_in_bytes: 0x20 +; CHECK-NEXT: .vgpr_count: 0x58 +; CHECK-NEXT: simple_stack_indirect_call: +; CHECK-NEXT: .backend_stack_size: 0x20 +; CHECK-NEXT: .lds_size: 0 +; CHECK-NEXT: .sgpr_count: 0x29 +; CHECK-NEXT: .stack_frame_size_in_bytes: 0x20 +; CHECK-NEXT: .vgpr_count: 0x58 +; CHECK-NEXT: simple_stack_recurse: +; CHECK-NEXT: .backend_stack_size: 0x20 +; CHECK-NEXT: .lds_size: 0 +; CHECK-NEXT: .sgpr_count: 0x24 +; CHECK-NEXT: .stack_frame_size_in_bytes: 0x20 +; CHECK-NEXT: .vgpr_count: 0x2a +; CHECK:amdpal.version: +; CHECK-NEXT: - 0x3 +; CHECK-NEXT: - 0 +; CHECK-NEXT:... +; CHECK-NEXT: .end_amdgpu_pal_metadata + +declare amdgpu_gfx float @extern_func(float) #0 +declare amdgpu_gfx float @extern_func_many_args(<64 x float>) #0 + +@funcptr = external hidden unnamed_addr addrspace(4) constant ptr, align 4 + +define amdgpu_gfx float @no_stack(float %arg0) #0 { + %add = fadd float %arg0, 1.0 + ret float %add +} + +define amdgpu_gfx float @simple_stack(float %arg0) #0 { + %stack = alloca float, i32 4, align 4, addrspace(5) + store volatile float 2.0, ptr addrspace(5) %stack + %val = load volatile float, ptr addrspace(5) %stack + %add = fadd float %arg0, %val + ret float %add +} + +define amdgpu_gfx float @multiple_stack(float %arg0) #0 { + %stack = alloca float, i32 4, align 4, addrspace(5) + store volatile float 2.0, ptr addrspace(5) %stack + %val = load volatile float, ptr addrspace(5) %stack + %add = fadd float %arg0, %val + %stack2 = alloca float, i32 4, align 4, addrspace(5) + store volatile float 2.0, ptr addrspace(5) %stack2 + %val2 = load volatile float, ptr addrspace(5) %stack2 + %add2 = fadd float %add, %val2 + ret float %add2 +} + +define amdgpu_gfx float @dynamic_stack(float %arg0) #0 { +bb0: + %cmp = fcmp ogt float %arg0, 0.0 + br i1 %cmp, label %bb1, label %bb2 + +bb1: + %stack = alloca float, i32 4, align 4, addrspace(5) + store volatile float 2.0, ptr addrspace(5) %stack + %val = load volatile float, ptr addrspace(5) %stack + %add = fadd float %arg0, %val + br label %bb2 + +bb2: + %res = phi float [ 0.0, %bb0 ], [ %add, %bb1 ] + ret float %res +} + +define amdgpu_gfx float @dynamic_stack_loop(float %arg0) #0 { +bb0: + br label %bb1 + +bb1: + %ctr = phi i32 [ 0, %bb0 ], [ %newctr, %bb1 ] + %stack = alloca float, i32 4, align 4, addrspace(5) + store volatile float 2.0, ptr addrspace(5) %stack + %val = load volatile float, ptr addrspace(5) %stack + %add = fadd float %arg0, %val + %cmp = icmp sgt i32 %ctr, 0 + %newctr = sub i32 %ctr, 1 + br i1 %cmp, label %bb1, label %bb2 + +bb2: + ret float %add +} + +define amdgpu_gfx float @no_stack_call(float %arg0) #0 { + %res = call amdgpu_gfx float @simple_stack(float %arg0) + ret float %res +} + +define amdgpu_gfx float @simple_stack_call(float %arg0) #0 { + %stack = alloca float, i32 4, align 4, addrspace(5) + store volatile float 2.0, ptr addrspace(5) %stack + %val = load volatile float, ptr addrspace(5) %stack + %res = call amdgpu_gfx float @simple_stack(float %arg0) + %add = fadd float %res, %val + ret float %add +} + +define amdgpu_gfx float @no_stack_extern_call(float %arg0) #0 { + %res = call amdgpu_gfx float @extern_func(float %arg0) + ret float %res +} + +define amdgpu_gfx float @simple_stack_extern_call(float %arg0) #0 { + %stack = alloca float, i32 4, align 4, addrspace(5) + store volatile float 2.0, ptr addrspace(5) %stack + %val = load volatile float, ptr addrspace(5) %stack + %res = call amdgpu_gfx float @extern_func(float %arg0) + %add = fadd float %res, %val + ret float %add +} + +define amdgpu_gfx float @no_stack_extern_call_many_args(<64 x float> %arg0) #0 { + %res = call amdgpu_gfx float @extern_func_many_args(<64 x float> %arg0) + ret float %res +} + +define amdgpu_gfx float @no_stack_indirect_call(float %arg0) #0 { + %fptr = load ptr, ptr addrspace(4) @funcptr + call amdgpu_gfx void %fptr() + ret float %arg0 +} + +define amdgpu_gfx float @simple_stack_indirect_call(float %arg0) #0 { + %stack = alloca float, i32 4, align 4, addrspace(5) + store volatile float 2.0, ptr addrspace(5) %stack + %val = load volatile float, ptr addrspace(5) %stack + %fptr = load ptr, ptr addrspace(4) @funcptr + call amdgpu_gfx void %fptr() + %add = fadd float %arg0, %val + ret float %add +} + +define amdgpu_gfx float @simple_stack_recurse(float %arg0) #0 { + %stack = alloca float, i32 4, align 4, addrspace(5) + store volatile float 2.0, ptr addrspace(5) %stack + %val = load volatile float, ptr addrspace(5) %stack + %res = call amdgpu_gfx float @simple_stack_recurse(float %arg0) + %add = fadd float %res, %val + ret float %add +} + +@lds = internal addrspace(3) global [64 x float] undef + +define amdgpu_gfx float @simple_lds(float %arg0) #0 { + %val = load float, ptr addrspace(3) @lds + ret float %val +} + +define amdgpu_gfx float @simple_lds_recurse(float %arg0) #0 { + %val = load float, ptr addrspace(3) @lds + %res = call amdgpu_gfx float @simple_lds_recurse(float %val) + ret float %res +} + +attributes #0 = { nounwind } + +!amdgpu.pal.metadata.msgpack = !{!0} + +!0 = !{!"\82\B0amdpal.pipelines\91\8A\A4.api\A6Vulkan\B2.compute_registers\85\AB.tg_size_en\C3\AA.tgid_x_en\C2\AA.tgid_y_en\C2\AA.tgid_z_en\C2\AF.tidig_comp_cnt\01\B0.hardware_stages\81\A3.cs\8C\AF.checksum_value\CE\94D\D7\D0\AB.debug_mode\00\AB.float_mode\CC\C0\A9.image_op\C2\AC.mem_ordered\C3\AB.sgpr_limitj\B7.threadgroup_dimensions\93\01\CD\04\00\01\AD.trap_present\00\B2.user_data_reg_map\DC\00 \CE\10\00\00\00\CE\FF\FF\FF\FF\00\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\AB.user_sgprs\03\AB.vgpr_limit\CD\01\00\AF.wavefront_size@\B7.internal_pipeline_hash\92\CF\E7\10k\A6:\A6%\F7\CF\B2\1F\1A\D4{\DA\E1T\AA.registers\80\A8.shaders\81\A8.compute\82\B0.api_shader_hash\92\CF\E9Zn7}\1E\B9\E7\00\B1.hardware_mapping\91\A3.cs\B0.spill_threshold\CE\FF\FF\FF\FF\A5.type\A2Cs\B0.user_data_limit\01\AF.xgl_cache_info\82\B3.128_bit_cache_hash\92\CF\B4X\B8\11[\A4\88P\CF\A0;\B0\AF\FF\B4\BE\C0\AD.llpc_version\A461.1\AEamdpal.version\92\03\00"} +!1 = !{i32 7} -- GitLab From 40fd17a90d4dcfb4bada663d73111a43c4c6ccb1 Mon Sep 17 00:00:00 2001 From: hlivin01 <110549819+hlivin01@users.noreply.github.com> Date: Tue, 6 Feb 2024 15:46:57 +0000 Subject: [PATCH 082/266] [ARM][AARCH64][NEON]: Wrong return type of NEON intrinsic vqrshrunh_n_s16, vqrshruns_n_s32, and vqrshrund_n_s64 in arm_neon.h (#80819) * fixes https://github.com/llvm/llvm-project/issues/71751 * changed return types in the table gen file responsible for generation of the problematic intrinsics * this is to ensure that the return type for the functions is the same as specified in the Arm Developer Documentation and avoid casting bugs (https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrunh_n_s16) * updated lit tests to reflect the change in return type, worth noting that LLVM does not seems to differentiate signed and unsigned ints in the IR, hence the change in type cannot be checked in IR as far as I am aware --- clang/include/clang/Basic/arm_neon.td | 4 ++-- clang/test/CodeGen/aarch64-neon-intrinsics.c | 12 ++++++------ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/clang/include/clang/Basic/arm_neon.td b/clang/include/clang/Basic/arm_neon.td index 9cb7e0981384..f16de97f4e6b 100644 --- a/clang/include/clang/Basic/arm_neon.td +++ b/clang/include/clang/Basic/arm_neon.td @@ -1354,9 +1354,9 @@ let isScalarNarrowShift = 1 in { // Signed/Unsigned Saturating Rounded Shift Right Narrow (Immediate) def SCALAR_SQRSHRN_N: SInst<"vqrshrn_n", "(1<)1I", "SsSiSlSUsSUiSUl">; // Signed Saturating Shift Right Unsigned Narrow (Immediate) - def SCALAR_SQSHRUN_N: SInst<"vqshrun_n", "(1<)1I", "SsSiSl">; + def SCALAR_SQSHRUN_N: SInst<"vqshrun_n", "(1; // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate) - def SCALAR_SQRSHRUN_N: SInst<"vqrshrun_n", "(1<)1I", "SsSiSl">; + def SCALAR_SQRSHRUN_N: SInst<"vqrshrun_n", "(1; } //////////////////////////////////////////////////////////////////////////////// diff --git a/clang/test/CodeGen/aarch64-neon-intrinsics.c b/clang/test/CodeGen/aarch64-neon-intrinsics.c index 7c53b9b0af6b..eeb50d095a5c 100644 --- a/clang/test/CodeGen/aarch64-neon-intrinsics.c +++ b/clang/test/CodeGen/aarch64-neon-intrinsics.c @@ -14132,8 +14132,8 @@ int32_t test_vqshrund_n_s64(int64_t a) { // CHECK: [[VQRSHRUNH_N_S16:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> [[TMP0]], i32 8) // CHECK: [[TMP1:%.*]] = extractelement <8 x i8> [[VQRSHRUNH_N_S16]], i64 0 // CHECK: ret i8 [[TMP1]] -int8_t test_vqrshrunh_n_s16(int16_t a) { - return (int8_t)vqrshrunh_n_s16(a, 8); +uint8_t test_vqrshrunh_n_s16(int16_t a) { + return (uint8_t)vqrshrunh_n_s16(a, 8); } // CHECK-LABEL: @test_vqrshruns_n_s32( @@ -14141,15 +14141,15 @@ int8_t test_vqrshrunh_n_s16(int16_t a) { // CHECK: [[VQRSHRUNS_N_S32:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> [[TMP0]], i32 16) // CHECK: [[TMP1:%.*]] = extractelement <4 x i16> [[VQRSHRUNS_N_S32]], i64 0 // CHECK: ret i16 [[TMP1]] -int16_t test_vqrshruns_n_s32(int32_t a) { - return (int16_t)vqrshruns_n_s32(a, 16); +uint16_t test_vqrshruns_n_s32(int32_t a) { + return (uint16_t)vqrshruns_n_s32(a, 16); } // CHECK-LABEL: @test_vqrshrund_n_s64( // CHECK: [[VQRSHRUND_N_S64:%.*]] = call i32 @llvm.aarch64.neon.sqrshrun.i32(i64 %a, i32 32) // CHECK: ret i32 [[VQRSHRUND_N_S64]] -int32_t test_vqrshrund_n_s64(int64_t a) { - return (int32_t)vqrshrund_n_s64(a, 32); +uint32_t test_vqrshrund_n_s64(int64_t a) { + return (uint32_t)vqrshrund_n_s64(a, 32); } // CHECK-LABEL: @test_vcvts_n_f32_s32( -- GitLab From 9ea34be3e4c9deeabfc21cced1acb7f9593ffe93 Mon Sep 17 00:00:00 2001 From: Vinayak Dev <104419489+vinayakdsci@users.noreply.github.com> Date: Tue, 6 Feb 2024 21:24:17 +0530 Subject: [PATCH 083/266] [MC]: Fix typo in MCObjectStreamer.cpp (#80856) Fixes a typo in llvm/lib/MC/MCObjectStreamer.cpp introduced in #80162 --- llvm/lib/MC/MCObjectStreamer.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/MC/MCObjectStreamer.cpp b/llvm/lib/MC/MCObjectStreamer.cpp index 8948f3f16457..490e0a4dd404 100644 --- a/llvm/lib/MC/MCObjectStreamer.cpp +++ b/llvm/lib/MC/MCObjectStreamer.cpp @@ -902,7 +902,7 @@ void MCObjectStreamer::emitFileDirective(StringRef Filename, StringRef TimeStamp, StringRef Description) { getAssembler().addFileName(Filename); - getAssembler().setCompilerVersion(CompilerVerion.str()); + getAssembler().setCompilerVersion(CompilerVersion.str()); // TODO: add TimeStamp and Description to .file symbol table entry // with the integrated assembler. } -- GitLab From e5638c5a00682243b1ee012d7dd8292aa221dff8 Mon Sep 17 00:00:00 2001 From: choikwa <5455710+choikwa@users.noreply.github.com> Date: Tue, 6 Feb 2024 11:02:28 -0500 Subject: [PATCH 084/266] [AMDGPU] Use correct number of bits needed for div/rem shrinking (#80622) There was an error where dividend of type i64 and actual used number of bits of 32 fell into path that assumes only 24 bits being used. Check that AtLeast field is used correctly when using computeNumSignBits and add necessary extend/trunc for 32 bits path. Regolden and update testcases. @jrbyrnes @bcahoon @arsenm @rampitec --- .../Target/AMDGPU/AMDGPUCodeGenPrepare.cpp | 21 +- .../CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll | 104 +++-- .../CodeGen/AMDGPU/GlobalISel/srem.i64.ll | 104 +++-- .../CodeGen/AMDGPU/GlobalISel/udiv.i32.ll | 86 ++-- .../CodeGen/AMDGPU/GlobalISel/urem.i32.ll | 90 ++-- llvm/test/CodeGen/AMDGPU/bypass-div.ll | 53 ++- llvm/test/CodeGen/AMDGPU/sdiv64.ll | 434 +++++++++++------- llvm/test/CodeGen/AMDGPU/srem64.ll | 378 ++++++++------- llvm/test/CodeGen/AMDGPU/udiv.ll | 208 ++++----- llvm/test/CodeGen/AMDGPU/udiv64.ll | 150 ++++-- llvm/test/CodeGen/AMDGPU/urem64.ll | 388 +++++++++------- 11 files changed, 1158 insertions(+), 858 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp index c4293f59204d..1c75c5a47c9d 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp @@ -1213,7 +1213,10 @@ Value *AMDGPUCodeGenPrepareImpl::expandDivRem24(IRBuilder<> &Builder, BinaryOperator &I, Value *Num, Value *Den, bool IsDiv, bool IsSigned) const { - int DivBits = getDivNumBits(I, Num, Den, 9, IsSigned); + unsigned SSBits = Num->getType()->getScalarSizeInBits(); + // If Num bits <= 24, assume 0 signbits. + unsigned AtLeast = (SSBits <= 24) ? 0 : (SSBits - 24 + IsSigned); + int DivBits = getDivNumBits(I, Num, Den, AtLeast, IsSigned); if (DivBits == -1) return nullptr; return expandDivRem24Impl(Builder, I, Num, Den, DivBits, IsDiv, IsSigned); @@ -1385,13 +1388,13 @@ Value *AMDGPUCodeGenPrepareImpl::expandDivRem32(IRBuilder<> &Builder, Type *I32Ty = Builder.getInt32Ty(); Type *F32Ty = Builder.getFloatTy(); - if (Ty->getScalarSizeInBits() < 32) { + if (Ty->getScalarSizeInBits() != 32) { if (IsSigned) { - X = Builder.CreateSExt(X, I32Ty); - Y = Builder.CreateSExt(Y, I32Ty); + X = Builder.CreateSExtOrTrunc(X, I32Ty); + Y = Builder.CreateSExtOrTrunc(Y, I32Ty); } else { - X = Builder.CreateZExt(X, I32Ty); - Y = Builder.CreateZExt(Y, I32Ty); + X = Builder.CreateZExtOrTrunc(X, I32Ty); + Y = Builder.CreateZExtOrTrunc(Y, I32Ty); } } @@ -1482,10 +1485,10 @@ Value *AMDGPUCodeGenPrepareImpl::expandDivRem32(IRBuilder<> &Builder, if (IsSigned) { Res = Builder.CreateXor(Res, Sign); Res = Builder.CreateSub(Res, Sign); + Res = Builder.CreateSExtOrTrunc(Res, Ty); + } else { + Res = Builder.CreateZExtOrTrunc(Res, Ty); } - - Res = Builder.CreateTrunc(Res, Ty); - return Res; } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll index 3eb6f1eced09..0a6b7af2f78d 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll @@ -3055,19 +3055,29 @@ define i64 @v_sdiv_i64_24bit(i64 %num, i64 %den) { ; CGP-LABEL: v_sdiv_i64_24bit: ; CGP: ; %bb.0: ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v2 -; CGP-NEXT: v_cvt_f32_i32_e32 v1, v1 -; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0 -; CGP-NEXT: v_cvt_f32_i32_e32 v0, v0 -; CGP-NEXT: v_rcp_f32_e32 v2, v1 -; CGP-NEXT: v_mul_f32_e32 v2, v0, v2 -; CGP-NEXT: v_trunc_f32_e32 v2, v2 -; CGP-NEXT: v_mad_f32 v0, -v2, v1, v0 -; CGP-NEXT: v_cvt_i32_f32_e32 v2, v2 -; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v0|, |v1| -; CGP-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] -; CGP-NEXT: v_add_i32_e32 v0, vcc, v2, v0 -; CGP-NEXT: v_bfe_i32 v0, v0, 0, 25 +; CGP-NEXT: v_and_b32_e32 v3, 0xffffff, v2 +; CGP-NEXT: v_cvt_f32_u32_e32 v1, v3 +; CGP-NEXT: v_and_b32_e32 v5, 0xffffff, v0 +; CGP-NEXT: v_rcp_f32_e32 v1, v1 +; CGP-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 +; CGP-NEXT: v_cvt_u32_f32_e32 v4, v1 +; CGP-NEXT: v_sub_i32_e32 v1, vcc, 0, v3 +; CGP-NEXT: v_mul_lo_u32 v1, v1, v4 +; CGP-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v4, v1, 0 +; CGP-NEXT: v_mov_b32_e32 v0, v2 +; CGP-NEXT: v_add_i32_e32 v0, vcc, v4, v0 +; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v5, v0, 0 +; CGP-NEXT: v_mov_b32_e32 v0, v1 +; CGP-NEXT: v_mul_lo_u32 v1, v0, v3 +; CGP-NEXT: v_add_i32_e32 v2, vcc, 1, v0 +; CGP-NEXT: v_sub_i32_e32 v1, vcc, v5, v1 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 +; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; CGP-NEXT: v_sub_i32_e64 v2, s[4:5], v1, v3 +; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; CGP-NEXT: v_add_i32_e32 v2, vcc, 1, v0 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 +; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; CGP-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; CGP-NEXT: s_setpc_b64 s[30:31] %num.mask = and i64 %num, 16777215 @@ -3335,32 +3345,52 @@ define <2 x i64> @v_sdiv_v2i64_24bit(<2 x i64> %num, <2 x i64> %den) { ; CGP-LABEL: v_sdiv_v2i64_24bit: ; CGP: ; %bb.0: ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v4 -; CGP-NEXT: v_cvt_f32_i32_e32 v1, v1 -; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0 -; CGP-NEXT: v_cvt_f32_i32_e32 v0, v0 +; CGP-NEXT: v_and_b32_e32 v3, 0xffffff, v4 +; CGP-NEXT: v_cvt_f32_u32_e32 v1, v3 ; CGP-NEXT: v_and_b32_e32 v4, 0xffffff, v6 -; CGP-NEXT: v_rcp_f32_e32 v3, v1 -; CGP-NEXT: v_cvt_f32_i32_e32 v4, v4 +; CGP-NEXT: v_sub_i32_e32 v6, vcc, 0, v3 +; CGP-NEXT: v_rcp_f32_e32 v1, v1 +; CGP-NEXT: v_and_b32_e32 v7, 0xffffff, v0 ; CGP-NEXT: v_and_b32_e32 v2, 0xffffff, v2 -; CGP-NEXT: v_cvt_f32_i32_e32 v2, v2 -; CGP-NEXT: v_mul_f32_e32 v3, v0, v3 -; CGP-NEXT: v_trunc_f32_e32 v3, v3 -; CGP-NEXT: v_mad_f32 v0, -v3, v1, v0 -; CGP-NEXT: v_cvt_i32_f32_e32 v3, v3 -; CGP-NEXT: v_rcp_f32_e32 v5, v4 -; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v0|, |v1| -; CGP-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] -; CGP-NEXT: v_add_i32_e32 v0, vcc, v3, v0 -; CGP-NEXT: v_mul_f32_e32 v3, v2, v5 -; CGP-NEXT: v_trunc_f32_e32 v3, v3 -; CGP-NEXT: v_mad_f32 v2, -v3, v4, v2 -; CGP-NEXT: v_cvt_i32_f32_e32 v3, v3 -; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, |v4| -; CGP-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5] -; CGP-NEXT: v_bfe_i32 v0, v0, 0, 25 -; CGP-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; CGP-NEXT: v_bfe_i32 v2, v2, 0, 25 +; CGP-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 +; CGP-NEXT: v_cvt_u32_f32_e32 v5, v1 +; CGP-NEXT: v_cvt_f32_u32_e32 v1, v4 +; CGP-NEXT: v_mul_lo_u32 v6, v6, v5 +; CGP-NEXT: v_rcp_f32_e32 v8, v1 +; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v5, v6, 0 +; CGP-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v8 +; CGP-NEXT: v_cvt_u32_f32_e32 v6, v0 +; CGP-NEXT: v_mov_b32_e32 v0, v1 +; CGP-NEXT: v_add_i32_e32 v0, vcc, v5, v0 +; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v7, v0, 0 +; CGP-NEXT: v_sub_i32_e32 v0, vcc, 0, v4 +; CGP-NEXT: v_mov_b32_e32 v5, v1 +; CGP-NEXT: v_mul_lo_u32 v0, v0, v6 +; CGP-NEXT: v_mul_lo_u32 v1, v5, v3 +; CGP-NEXT: v_add_i32_e32 v8, vcc, 1, v5 +; CGP-NEXT: v_sub_i32_e32 v7, vcc, v7, v1 +; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v0, 0 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v7, v3 +; CGP-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc +; CGP-NEXT: v_mov_b32_e32 v0, v1 +; CGP-NEXT: v_add_i32_e64 v0, s[4:5], v6, v0 +; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, v0, 0 +; CGP-NEXT: v_sub_i32_e64 v8, s[4:5], v7, v3 +; CGP-NEXT: v_cndmask_b32_e32 v0, v7, v8, vcc +; CGP-NEXT: v_mov_b32_e32 v7, v1 +; CGP-NEXT: v_mul_lo_u32 v8, v7, v4 +; CGP-NEXT: v_add_i32_e32 v6, vcc, 1, v5 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3 +; CGP-NEXT: v_cndmask_b32_e32 v0, v5, v6, vcc +; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v8 +; CGP-NEXT: v_add_i32_e32 v3, vcc, 1, v7 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v4 +; CGP-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc +; CGP-NEXT: v_sub_i32_e64 v5, s[4:5], v2, v4 +; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc +; CGP-NEXT: v_add_i32_e32 v5, vcc, 1, v3 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v4 +; CGP-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc ; CGP-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; CGP-NEXT: v_ashrrev_i32_e32 v3, 31, v2 ; CGP-NEXT: s_setpc_b64 s[30:31] diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll index 0b22b3b3a4ba..c455b24313dd 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll @@ -3000,21 +3000,27 @@ define i64 @v_srem_i64_24bit(i64 %num, i64 %den) { ; CGP-LABEL: v_srem_i64_24bit: ; CGP: ; %bb.0: ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v2 -; CGP-NEXT: v_cvt_f32_i32_e32 v2, v1 -; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0 -; CGP-NEXT: v_cvt_f32_i32_e32 v3, v0 -; CGP-NEXT: v_rcp_f32_e32 v4, v2 -; CGP-NEXT: v_mul_f32_e32 v4, v3, v4 -; CGP-NEXT: v_trunc_f32_e32 v4, v4 -; CGP-NEXT: v_mad_f32 v3, -v4, v2, v3 -; CGP-NEXT: v_cvt_i32_f32_e32 v4, v4 -; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v3|, |v2| -; CGP-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5] -; CGP-NEXT: v_add_i32_e32 v2, vcc, v4, v2 -; CGP-NEXT: v_mul_lo_u32 v1, v2, v1 -; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v1 -; CGP-NEXT: v_bfe_i32 v0, v0, 0, 25 +; CGP-NEXT: v_and_b32_e32 v3, 0xffffff, v2 +; CGP-NEXT: v_cvt_f32_u32_e32 v1, v3 +; CGP-NEXT: v_and_b32_e32 v5, 0xffffff, v0 +; CGP-NEXT: v_rcp_f32_e32 v1, v1 +; CGP-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 +; CGP-NEXT: v_cvt_u32_f32_e32 v4, v1 +; CGP-NEXT: v_sub_i32_e32 v1, vcc, 0, v3 +; CGP-NEXT: v_mul_lo_u32 v1, v1, v4 +; CGP-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v4, v1, 0 +; CGP-NEXT: v_mov_b32_e32 v0, v2 +; CGP-NEXT: v_add_i32_e32 v0, vcc, v4, v0 +; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v5, v0, 0 +; CGP-NEXT: v_mov_b32_e32 v0, v1 +; CGP-NEXT: v_mul_lo_u32 v0, v0, v3 +; CGP-NEXT: v_sub_i32_e32 v0, vcc, v5, v0 +; CGP-NEXT: v_sub_i32_e32 v1, vcc, v0, v3 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3 +; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; CGP-NEXT: v_sub_i32_e32 v1, vcc, v0, v3 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3 +; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; CGP-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; CGP-NEXT: s_setpc_b64 s[30:31] %num.mask = and i64 %num, 16777215 @@ -3282,37 +3288,47 @@ define <2 x i64> @v_srem_v2i64_24bit(<2 x i64> %num, <2 x i64> %den) { ; CGP-LABEL: v_srem_v2i64_24bit: ; CGP: ; %bb.0: ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v4 -; CGP-NEXT: v_cvt_f32_i32_e32 v3, v1 -; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0 -; CGP-NEXT: v_cvt_f32_i32_e32 v4, v0 -; CGP-NEXT: v_and_b32_e32 v6, 0xffffff, v6 -; CGP-NEXT: v_rcp_f32_e32 v5, v3 +; CGP-NEXT: v_and_b32_e32 v3, 0xffffff, v4 +; CGP-NEXT: v_cvt_f32_u32_e32 v1, v3 +; CGP-NEXT: v_and_b32_e32 v4, 0xffffff, v6 +; CGP-NEXT: v_sub_i32_e32 v6, vcc, 0, v3 +; CGP-NEXT: v_rcp_f32_e32 v1, v1 +; CGP-NEXT: v_and_b32_e32 v7, 0xffffff, v0 ; CGP-NEXT: v_and_b32_e32 v2, 0xffffff, v2 -; CGP-NEXT: v_mul_f32_e32 v5, v4, v5 -; CGP-NEXT: v_trunc_f32_e32 v5, v5 -; CGP-NEXT: v_mad_f32 v4, -v5, v3, v4 -; CGP-NEXT: v_cvt_i32_f32_e32 v5, v5 -; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v4|, |v3| -; CGP-NEXT: v_cvt_f32_i32_e32 v4, v6 -; CGP-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[4:5] -; CGP-NEXT: v_add_i32_e32 v3, vcc, v5, v3 -; CGP-NEXT: v_mul_lo_u32 v1, v3, v1 -; CGP-NEXT: v_cvt_f32_i32_e32 v3, v2 -; CGP-NEXT: v_rcp_f32_e32 v5, v4 -; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v1 -; CGP-NEXT: v_mul_f32_e32 v1, v3, v5 -; CGP-NEXT: v_trunc_f32_e32 v1, v1 -; CGP-NEXT: v_mad_f32 v3, -v1, v4, v3 -; CGP-NEXT: v_cvt_i32_f32_e32 v1, v1 -; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v3|, |v4| -; CGP-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[4:5] -; CGP-NEXT: v_bfe_i32 v0, v0, 0, 25 -; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v3 -; CGP-NEXT: v_mul_lo_u32 v3, v1, v6 +; CGP-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 +; CGP-NEXT: v_cvt_u32_f32_e32 v5, v1 +; CGP-NEXT: v_cvt_f32_u32_e32 v1, v4 +; CGP-NEXT: v_mul_lo_u32 v6, v6, v5 +; CGP-NEXT: v_rcp_f32_e32 v8, v1 +; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v5, v6, 0 +; CGP-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v8 +; CGP-NEXT: v_cvt_u32_f32_e32 v6, v0 +; CGP-NEXT: v_mov_b32_e32 v0, v1 +; CGP-NEXT: v_add_i32_e32 v0, vcc, v5, v0 +; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v7, v0, 0 +; CGP-NEXT: v_sub_i32_e32 v0, vcc, 0, v4 +; CGP-NEXT: v_mul_lo_u32 v0, v0, v6 +; CGP-NEXT: v_mul_lo_u32 v5, v1, v3 +; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v0, 0 +; CGP-NEXT: v_sub_i32_e32 v5, vcc, v7, v5 +; CGP-NEXT: v_mov_b32_e32 v0, v1 +; CGP-NEXT: v_add_i32_e32 v0, vcc, v6, v0 +; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, v0, 0 +; CGP-NEXT: v_sub_i32_e32 v7, vcc, v5, v3 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v5, v3 +; CGP-NEXT: v_mul_lo_u32 v6, v1, v4 +; CGP-NEXT: v_cndmask_b32_e32 v0, v5, v7, vcc +; CGP-NEXT: v_sub_i32_e32 v5, vcc, v0, v3 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3 +; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc +; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v6 +; CGP-NEXT: v_sub_i32_e32 v3, vcc, v2, v4 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v4 +; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc +; CGP-NEXT: v_sub_i32_e32 v3, vcc, v2, v4 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v4 +; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc ; CGP-NEXT: v_ashrrev_i32_e32 v1, 31, v0 -; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v3 -; CGP-NEXT: v_bfe_i32 v2, v2, 0, 25 ; CGP-NEXT: v_ashrrev_i32_e32 v3, 31, v2 ; CGP-NEXT: s_setpc_b64 s[30:31] %num.mask = and <2 x i64> %num, diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll index 6588112973f4..cd01148fa7dd 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll @@ -415,25 +415,17 @@ define i32 @v_udiv_i32_24bit(i32 %num, i32 %den) { ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0 ; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1 -; CGP-NEXT: v_cvt_f32_u32_e32 v2, v1 -; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v1 -; CGP-NEXT: v_rcp_f32_e32 v2, v2 -; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2 +; CGP-NEXT: v_cvt_f32_u32_e32 v0, v0 +; CGP-NEXT: v_cvt_f32_u32_e32 v1, v1 +; CGP-NEXT: v_rcp_f32_e32 v2, v1 +; CGP-NEXT: v_mul_f32_e32 v2, v0, v2 +; CGP-NEXT: v_trunc_f32_e32 v2, v2 +; CGP-NEXT: v_fma_f32 v0, -v2, v1, v0 ; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2 -; CGP-NEXT: v_mul_lo_u32 v3, v3, v2 -; CGP-NEXT: v_mul_hi_u32 v3, v2, v3 -; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; CGP-NEXT: v_mul_hi_u32 v2, v0, v2 -; CGP-NEXT: v_mul_lo_u32 v3, v2, v1 -; CGP-NEXT: v_add_i32_e32 v4, vcc, 1, v2 -; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v3 -; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1 -; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc -; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v0, v1 -; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc -; CGP-NEXT: v_add_i32_e32 v3, vcc, 1, v2 -; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1 -; CGP-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc +; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v0|, v1 +; CGP-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] +; CGP-NEXT: v_add_i32_e32 v0, vcc, v2, v0 +; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0 ; CGP-NEXT: s_setpc_b64 s[30:31] %num.mask = and i32 %num, 16777215 %den.mask = and i32 %den, 16777215 @@ -496,44 +488,28 @@ define <2 x i32> @v_udiv_v2i32_24bit(<2 x i32> %num, <2 x i32> %den) { ; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1 ; CGP-NEXT: v_and_b32_e32 v2, 0xffffff, v2 ; CGP-NEXT: v_and_b32_e32 v3, 0xffffff, v3 -; CGP-NEXT: v_cvt_f32_u32_e32 v4, v2 -; CGP-NEXT: v_sub_i32_e32 v5, vcc, 0, v2 -; CGP-NEXT: v_cvt_f32_u32_e32 v6, v3 -; CGP-NEXT: v_sub_i32_e32 v7, vcc, 0, v3 -; CGP-NEXT: v_rcp_f32_e32 v4, v4 -; CGP-NEXT: v_rcp_f32_e32 v6, v6 -; CGP-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4 -; CGP-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6 +; CGP-NEXT: v_cvt_f32_u32_e32 v0, v0 +; CGP-NEXT: v_cvt_f32_u32_e32 v2, v2 +; CGP-NEXT: v_cvt_f32_u32_e32 v1, v1 +; CGP-NEXT: v_cvt_f32_u32_e32 v3, v3 +; CGP-NEXT: v_rcp_f32_e32 v4, v2 +; CGP-NEXT: v_rcp_f32_e32 v5, v3 +; CGP-NEXT: v_mul_f32_e32 v4, v0, v4 +; CGP-NEXT: v_mul_f32_e32 v5, v1, v5 +; CGP-NEXT: v_trunc_f32_e32 v4, v4 +; CGP-NEXT: v_trunc_f32_e32 v5, v5 +; CGP-NEXT: v_fma_f32 v0, -v4, v2, v0 ; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4 -; CGP-NEXT: v_cvt_u32_f32_e32 v6, v6 -; CGP-NEXT: v_mul_lo_u32 v5, v5, v4 -; CGP-NEXT: v_mul_lo_u32 v7, v7, v6 -; CGP-NEXT: v_mul_hi_u32 v5, v4, v5 -; CGP-NEXT: v_mul_hi_u32 v7, v6, v7 -; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v5 -; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v7 -; CGP-NEXT: v_mul_hi_u32 v4, v0, v4 -; CGP-NEXT: v_mul_hi_u32 v5, v1, v5 -; CGP-NEXT: v_mul_lo_u32 v6, v4, v2 -; CGP-NEXT: v_add_i32_e32 v7, vcc, 1, v4 -; CGP-NEXT: v_mul_lo_u32 v8, v5, v3 -; CGP-NEXT: v_add_i32_e32 v9, vcc, 1, v5 -; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v6 -; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v8 -; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 -; CGP-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc -; CGP-NEXT: v_sub_i32_e64 v6, s[4:5], v0, v2 -; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v3 -; CGP-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[4:5] -; CGP-NEXT: v_sub_i32_e64 v7, s[6:7], v1, v3 -; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc -; CGP-NEXT: v_add_i32_e32 v6, vcc, 1, v4 -; CGP-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[4:5] -; CGP-NEXT: v_add_i32_e32 v7, vcc, 1, v5 -; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 -; CGP-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc -; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 -; CGP-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc +; CGP-NEXT: v_fma_f32 v1, -v5, v3, v1 +; CGP-NEXT: v_cvt_u32_f32_e32 v5, v5 +; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v0|, v2 +; CGP-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] +; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, v3 +; CGP-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5] +; CGP-NEXT: v_add_i32_e32 v0, vcc, v4, v0 +; CGP-NEXT: v_add_i32_e32 v1, vcc, v5, v1 +; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0 +; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1 ; CGP-NEXT: s_setpc_b64 s[30:31] %num.mask = and <2 x i32> %num, %den.mask = and <2 x i32> %den, diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll index 158403644607..31f61b9968b8 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll @@ -445,23 +445,19 @@ define i32 @v_urem_i32_24bit(i32 %num, i32 %den) { ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0 ; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1 -; CGP-NEXT: v_cvt_f32_u32_e32 v2, v1 -; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v1 -; CGP-NEXT: v_rcp_f32_e32 v2, v2 -; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2 -; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2 -; CGP-NEXT: v_mul_lo_u32 v3, v3, v2 -; CGP-NEXT: v_mul_hi_u32 v3, v2, v3 -; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; CGP-NEXT: v_mul_hi_u32 v2, v0, v2 -; CGP-NEXT: v_mul_lo_u32 v2, v2, v1 -; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 -; CGP-NEXT: v_sub_i32_e32 v2, vcc, v0, v1 -; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1 -; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; CGP-NEXT: v_sub_i32_e32 v2, vcc, v0, v1 -; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1 -; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; CGP-NEXT: v_cvt_f32_u32_e32 v2, v0 +; CGP-NEXT: v_cvt_f32_u32_e32 v3, v1 +; CGP-NEXT: v_rcp_f32_e32 v4, v3 +; CGP-NEXT: v_mul_f32_e32 v4, v2, v4 +; CGP-NEXT: v_trunc_f32_e32 v4, v4 +; CGP-NEXT: v_fma_f32 v2, -v4, v3, v2 +; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4 +; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, v3 +; CGP-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5] +; CGP-NEXT: v_add_i32_e32 v2, vcc, v4, v2 +; CGP-NEXT: v_mul_lo_u32 v1, v2, v1 +; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v1 +; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0 ; CGP-NEXT: s_setpc_b64 s[30:31] %num.mask = and i32 %num, 16777215 %den.mask = and i32 %den, 16777215 @@ -520,40 +516,32 @@ define <2 x i32> @v_urem_v2i32_24bit(<2 x i32> %num, <2 x i32> %den) { ; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1 ; CGP-NEXT: v_and_b32_e32 v2, 0xffffff, v2 ; CGP-NEXT: v_and_b32_e32 v3, 0xffffff, v3 -; CGP-NEXT: v_cvt_f32_u32_e32 v4, v2 -; CGP-NEXT: v_sub_i32_e32 v5, vcc, 0, v2 -; CGP-NEXT: v_cvt_f32_u32_e32 v6, v3 -; CGP-NEXT: v_sub_i32_e32 v7, vcc, 0, v3 -; CGP-NEXT: v_rcp_f32_e32 v4, v4 -; CGP-NEXT: v_rcp_f32_e32 v6, v6 -; CGP-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4 -; CGP-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6 -; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4 -; CGP-NEXT: v_cvt_u32_f32_e32 v6, v6 -; CGP-NEXT: v_mul_lo_u32 v5, v5, v4 -; CGP-NEXT: v_mul_lo_u32 v7, v7, v6 -; CGP-NEXT: v_mul_hi_u32 v5, v4, v5 -; CGP-NEXT: v_mul_hi_u32 v7, v6, v7 -; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v5 -; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v7 -; CGP-NEXT: v_mul_hi_u32 v4, v0, v4 -; CGP-NEXT: v_mul_hi_u32 v5, v1, v5 -; CGP-NEXT: v_mul_lo_u32 v4, v4, v2 -; CGP-NEXT: v_mul_lo_u32 v5, v5, v3 -; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v4 -; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v5 -; CGP-NEXT: v_sub_i32_e32 v4, vcc, v0, v2 -; CGP-NEXT: v_sub_i32_e32 v5, vcc, v1, v3 -; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 -; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc -; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 -; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc -; CGP-NEXT: v_sub_i32_e32 v4, vcc, v0, v2 -; CGP-NEXT: v_sub_i32_e32 v5, vcc, v1, v3 -; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 -; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc -; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 -; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; CGP-NEXT: v_cvt_f32_u32_e32 v4, v0 +; CGP-NEXT: v_cvt_f32_u32_e32 v5, v2 +; CGP-NEXT: v_cvt_f32_u32_e32 v6, v1 +; CGP-NEXT: v_cvt_f32_u32_e32 v7, v3 +; CGP-NEXT: v_rcp_f32_e32 v8, v5 +; CGP-NEXT: v_rcp_f32_e32 v9, v7 +; CGP-NEXT: v_mul_f32_e32 v8, v4, v8 +; CGP-NEXT: v_mul_f32_e32 v9, v6, v9 +; CGP-NEXT: v_trunc_f32_e32 v8, v8 +; CGP-NEXT: v_trunc_f32_e32 v9, v9 +; CGP-NEXT: v_fma_f32 v4, -v8, v5, v4 +; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8 +; CGP-NEXT: v_fma_f32 v6, -v9, v7, v6 +; CGP-NEXT: v_cvt_u32_f32_e32 v9, v9 +; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v4|, v5 +; CGP-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5] +; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v6|, v7 +; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[4:5] +; CGP-NEXT: v_add_i32_e32 v4, vcc, v8, v4 +; CGP-NEXT: v_add_i32_e32 v5, vcc, v9, v5 +; CGP-NEXT: v_mul_lo_u32 v2, v4, v2 +; CGP-NEXT: v_mul_lo_u32 v3, v5, v3 +; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 +; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v3 +; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0 +; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1 ; CGP-NEXT: s_setpc_b64 s[30:31] %num.mask = and <2 x i32> %num, %den.mask = and <2 x i32> %den, diff --git a/llvm/test/CodeGen/AMDGPU/bypass-div.ll b/llvm/test/CodeGen/AMDGPU/bypass-div.ll index cb1b664549c9..4d8687b141a7 100644 --- a/llvm/test/CodeGen/AMDGPU/bypass-div.ll +++ b/llvm/test/CodeGen/AMDGPU/bypass-div.ll @@ -1024,16 +1024,25 @@ define i64 @sdiv64_known32(i64 %a, i64 %b) { ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, v3 -; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v1 -; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GFX9-NEXT: v_mul_f32_e32 v2, v1, v2 -; GFX9-NEXT: v_trunc_f32_e32 v2, v2 -; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v2 -; GFX9-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 +; GFX9-NEXT: v_sub_u32_e32 v2, 0, v3 +; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GFX9-NEXT: v_mul_lo_u32 v2, v2, v0 +; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2 +; GFX9-NEXT: v_add_u32_e32 v0, v0, v2 +; GFX9-NEXT: v_mul_hi_u32 v0, v1, v0 +; GFX9-NEXT: v_mul_lo_u32 v2, v0, v3 +; GFX9-NEXT: v_add_u32_e32 v4, 1, v0 +; GFX9-NEXT: v_sub_u32_e32 v1, v1, v2 +; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 +; GFX9-NEXT: v_sub_u32_e32 v2, v1, v3 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; GFX9-NEXT: v_add_u32_e32 v2, 1, v0 +; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX9-NEXT: v_mov_b32_e32 v1, 0 -; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v3, vcc -; GFX9-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] %a.ext = ashr i64 %a, 32 %b.ext = ashr i64 %b, 32 @@ -1046,15 +1055,25 @@ define i64 @udiv64_known32(i64 %a, i64 %b) { ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v2 -; GFX9-NEXT: v_cvt_f32_u32_e32 v0, v0 -; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v1 -; GFX9-NEXT: v_mul_f32_e32 v2, v0, v2 -; GFX9-NEXT: v_trunc_f32_e32 v2, v2 -; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v2 -; GFX9-NEXT: v_mad_f32 v0, -v2, v1, v0 -; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v1 +; GFX9-NEXT: v_sub_u32_e32 v3, 0, v2 +; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1 +; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 +; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GFX9-NEXT: v_mul_lo_u32 v3, v3, v1 +; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3 +; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 +; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1 +; GFX9-NEXT: v_mul_lo_u32 v3, v1, v2 +; GFX9-NEXT: v_add_u32_e32 v4, 1, v1 +; GFX9-NEXT: v_sub_u32_e32 v0, v0, v3 +; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 +; GFX9-NEXT: v_sub_u32_e32 v3, v0, v2 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc +; GFX9-NEXT: v_add_u32_e32 v3, 1, v1 +; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc ; GFX9-NEXT: v_mov_b32_e32 v1, 0 -; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v3, vcc ; GFX9-NEXT: s_setpc_b64 s[30:31] %a.mask = and i64 %a, 4294967295 %b.mask = and i64 %b, 4294967295 diff --git a/llvm/test/CodeGen/AMDGPU/sdiv64.ll b/llvm/test/CodeGen/AMDGPU/sdiv64.ll index f37d681ab965..b086640c72f8 100644 --- a/llvm/test/CodeGen/AMDGPU/sdiv64.ll +++ b/llvm/test/CodeGen/AMDGPU/sdiv64.ll @@ -529,17 +529,26 @@ define i64 @v_test_sdiv24_64(i64 %x, i64 %y) { ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v3 -; GCN-NEXT: v_cvt_f32_i32_e32 v0, v0 +; GCN-NEXT: v_cvt_f32_u32_e32 v2, v0 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v0 ; GCN-NEXT: v_lshrrev_b32_e32 v1, 8, v1 -; GCN-NEXT: v_cvt_f32_i32_e32 v1, v1 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_cvt_i32_f32_e32 v3, v2 -; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc -; GCN-NEXT: v_bfe_i32 v0, v0, 0, 25 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2 +; GCN-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 +; GCN-NEXT: v_mul_lo_u32 v3, v3, v2 +; GCN-NEXT: v_mul_hi_u32 v3, v2, v3 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 +; GCN-NEXT: v_mul_hi_u32 v2, v1, v2 +; GCN-NEXT: v_mul_u32_u24_e32 v3, v2, v0 +; GCN-NEXT: v_add_i32_e32 v4, vcc, 1, v2 +; GCN-NEXT: v_sub_i32_e32 v1, vcc, v1, v3 +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v0 +; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc +; GCN-NEXT: v_sub_i32_e64 v3, s[4:5], v1, v0 +; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, 1, v2 +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v0 +; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-NEXT: s_setpc_b64 s[30:31] ; @@ -547,17 +556,26 @@ define i64 @v_test_sdiv24_64(i64 %x, i64 %y) { ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v3 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, v0 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v2, v0 +; GCN-IR-NEXT: v_sub_i32_e32 v3, vcc, 0, v0 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v1, 8, v1 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, v1 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cvt_i32_f32_e32 v3, v2 -; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| -; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc -; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 25 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v2 +; GCN-IR-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v2 +; GCN-IR-NEXT: v_mul_lo_u32 v3, v3, v2 +; GCN-IR-NEXT: v_mul_hi_u32 v3, v2, v3 +; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v2, v3 +; GCN-IR-NEXT: v_mul_hi_u32 v2, v1, v2 +; GCN-IR-NEXT: v_mul_u32_u24_e32 v3, v2, v0 +; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v2 +; GCN-IR-NEXT: v_sub_i32_e32 v1, vcc, v1, v3 +; GCN-IR-NEXT: v_cmp_ge_u32_e32 vcc, v1, v0 +; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc +; GCN-IR-NEXT: v_sub_i32_e64 v3, s[4:5], v1, v0 +; GCN-IR-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, 1, v2 +; GCN-IR-NEXT: v_cmp_ge_u32_e32 vcc, v1, v0 +; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-IR-NEXT: s_setpc_b64 s[30:31] %1 = lshr i64 %x, 40 @@ -569,55 +587,91 @@ define i64 @v_test_sdiv24_64(i64 %x, i64 %y) { define amdgpu_kernel void @s_test_sdiv32_64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-LABEL: s_test_sdiv32_64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dword s8, s[0:1], 0xe -; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-NEXT: s_load_dword s2, s[0:1], 0xe ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8 -; GCN-NEXT: v_cvt_f32_i32_e32 v1, s3 -; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: s_xor_b32 s0, s3, s8 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-NEXT: s_ashr_i32 s0, s0, 30 +; GCN-NEXT: s_ashr_i32 s8, s2, 31 +; GCN-NEXT: s_add_i32 s2, s2, s8 +; GCN-NEXT: s_xor_b32 s9, s2, s8 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s9 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_sub_i32 s2, 0, s9 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: s_or_b32 s2, s0, 1 -; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, |v0| -; GCN-NEXT: s_and_b64 s[0:1], s[0:1], exec -; GCN-NEXT: s_cselect_b32 s0, s2, 0 -; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v2 -; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; GCN-NEXT: s_mov_b32 s4, s0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-NEXT: s_ashr_i32 s2, s3, 31 +; GCN-NEXT: s_add_i32 s3, s3, s2 +; GCN-NEXT: s_xor_b32 s3, s3, s2 +; GCN-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-NEXT: s_xor_b32 s0, s2, s8 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_mul_hi_u32 v0, s3, v0 +; GCN-NEXT: v_readfirstlane_b32 s1, v0 +; GCN-NEXT: s_mul_i32 s2, s1, s9 +; GCN-NEXT: s_sub_i32 s2, s3, s2 +; GCN-NEXT: s_add_i32 s8, s1, 1 +; GCN-NEXT: s_sub_i32 s3, s2, s9 +; GCN-NEXT: s_cmp_ge_u32 s2, s9 +; GCN-NEXT: s_cselect_b32 s1, s8, s1 +; GCN-NEXT: s_cselect_b32 s2, s3, s2 +; GCN-NEXT: s_add_i32 s3, s1, 1 +; GCN-NEXT: s_cmp_ge_u32 s2, s9 +; GCN-NEXT: s_cselect_b32 s1, s3, s1 +; GCN-NEXT: s_xor_b32 s1, s1, s0 +; GCN-NEXT: s_sub_i32 s0, s1, s0 +; GCN-NEXT: s_ashr_i32 s1, s0, 31 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s1 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_sdiv32_64: ; GCN-IR: ; %bb.0: -; GCN-IR-NEXT: s_load_dword s8, s[0:1], 0xe -; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-IR-NEXT: s_load_dword s2, s[0:1], 0xe ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s8 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s3 -; GCN-IR-NEXT: s_mov_b32 s4, s0 -; GCN-IR-NEXT: s_xor_b32 s0, s3, s8 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-IR-NEXT: s_ashr_i32 s0, s0, 30 +; GCN-IR-NEXT: s_ashr_i32 s8, s2, 31 +; GCN-IR-NEXT: s_add_i32 s2, s2, s8 +; GCN-IR-NEXT: s_xor_b32 s9, s2, s8 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s9 +; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) +; GCN-IR-NEXT: s_sub_i32 s2, 0, s9 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GCN-IR-NEXT: s_mov_b32 s5, s1 -; GCN-IR-NEXT: s_or_b32 s2, s0, 1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, |v0| -; GCN-IR-NEXT: s_and_b64 s[0:1], s[0:1], exec -; GCN-IR-NEXT: s_cselect_b32 s0, s2, 0 -; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s0, v2 -; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; GCN-IR-NEXT: s_mov_b32 s4, s0 +; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-IR-NEXT: s_ashr_i32 s2, s3, 31 +; GCN-IR-NEXT: s_add_i32 s3, s3, s2 +; GCN-IR-NEXT: s_xor_b32 s3, s3, s2 +; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-IR-NEXT: s_xor_b32 s0, s2, s8 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-IR-NEXT: v_mul_hi_u32 v0, s3, v0 +; GCN-IR-NEXT: v_readfirstlane_b32 s1, v0 +; GCN-IR-NEXT: s_mul_i32 s2, s1, s9 +; GCN-IR-NEXT: s_sub_i32 s2, s3, s2 +; GCN-IR-NEXT: s_add_i32 s8, s1, 1 +; GCN-IR-NEXT: s_sub_i32 s3, s2, s9 +; GCN-IR-NEXT: s_cmp_ge_u32 s2, s9 +; GCN-IR-NEXT: s_cselect_b32 s1, s8, s1 +; GCN-IR-NEXT: s_cselect_b32 s2, s3, s2 +; GCN-IR-NEXT: s_add_i32 s3, s1, 1 +; GCN-IR-NEXT: s_cmp_ge_u32 s2, s9 +; GCN-IR-NEXT: s_cselect_b32 s1, s3, s1 +; GCN-IR-NEXT: s_xor_b32 s1, s1, s0 +; GCN-IR-NEXT: s_sub_i32 s0, s1, s0 +; GCN-IR-NEXT: s_ashr_i32 s1, s0, 31 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s0 +; GCN-IR-NEXT: v_mov_b32_e32 v1, s1 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-IR-NEXT: s_endpgm %1 = ashr i64 %x, 32 @@ -630,62 +684,96 @@ define amdgpu_kernel void @s_test_sdiv32_64(ptr addrspace(1) %out, i64 %x, i64 % define amdgpu_kernel void @s_test_sdiv31_64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-LABEL: s_test_sdiv31_64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-NEXT: s_load_dword s1, s[0:1], 0xe -; GCN-NEXT: s_mov_b32 s3, 0xf000 -; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_load_dword s3, s[0:1], 0xe +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s0, s4 -; GCN-NEXT: s_ashr_i64 s[8:9], s[0:1], 33 -; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8 -; GCN-NEXT: s_mov_b32 s1, s5 -; GCN-NEXT: s_ashr_i64 s[4:5], s[6:7], 33 -; GCN-NEXT: v_cvt_f32_i32_e32 v1, s4 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-NEXT: s_xor_b32 s4, s4, s8 -; GCN-NEXT: s_ashr_i32 s4, s4, 30 -; GCN-NEXT: s_or_b32 s6, s4, 1 -; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| -; GCN-NEXT: s_and_b64 s[4:5], s[4:5], exec -; GCN-NEXT: s_cselect_b32 s4, s6, 0 -; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v2 -; GCN-NEXT: v_bfe_i32 v0, v0, 0, 31 -; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 -; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 33 +; GCN-NEXT: s_ashr_i32 s8, s2, 31 +; GCN-NEXT: s_add_i32 s2, s2, s8 +; GCN-NEXT: s_xor_b32 s9, s2, s8 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s9 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_sub_i32 s2, 0, s9 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: s_mov_b32 s5, s1 +; GCN-NEXT: s_mov_b32 s4, s0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 33 +; GCN-NEXT: s_ashr_i32 s3, s2, 31 +; GCN-NEXT: s_add_i32 s2, s2, s3 +; GCN-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-NEXT: s_xor_b32 s2, s2, s3 +; GCN-NEXT: s_xor_b32 s0, s3, s8 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_mul_hi_u32 v0, s2, v0 +; GCN-NEXT: v_readfirstlane_b32 s1, v0 +; GCN-NEXT: s_mul_i32 s3, s1, s9 +; GCN-NEXT: s_sub_i32 s2, s2, s3 +; GCN-NEXT: s_add_i32 s8, s1, 1 +; GCN-NEXT: s_sub_i32 s3, s2, s9 +; GCN-NEXT: s_cmp_ge_u32 s2, s9 +; GCN-NEXT: s_cselect_b32 s1, s8, s1 +; GCN-NEXT: s_cselect_b32 s2, s3, s2 +; GCN-NEXT: s_add_i32 s3, s1, 1 +; GCN-NEXT: s_cmp_ge_u32 s2, s9 +; GCN-NEXT: s_cselect_b32 s1, s3, s1 +; GCN-NEXT: s_xor_b32 s1, s1, s0 +; GCN-NEXT: s_sub_i32 s0, s1, s0 +; GCN-NEXT: s_ashr_i32 s1, s0, 31 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s1 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_sdiv31_64: ; GCN-IR: ; %bb.0: -; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-IR-NEXT: s_load_dword s1, s[0:1], 0xe -; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 -; GCN-IR-NEXT: s_mov_b32 s2, -1 +; GCN-IR-NEXT: s_load_dword s3, s[0:1], 0xe +; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 +; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_mov_b32 s0, s4 -; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[0:1], 33 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s8 -; GCN-IR-NEXT: s_mov_b32 s1, s5 -; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[6:7], 33 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s4 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-IR-NEXT: s_xor_b32 s4, s4, s8 -; GCN-IR-NEXT: s_ashr_i32 s4, s4, 30 -; GCN-IR-NEXT: s_or_b32 s6, s4, 1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| -; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], exec -; GCN-IR-NEXT: s_cselect_b32 s4, s6, 0 -; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s4, v2 -; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 31 -; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 -; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 33 +; GCN-IR-NEXT: s_ashr_i32 s8, s2, 31 +; GCN-IR-NEXT: s_add_i32 s2, s2, s8 +; GCN-IR-NEXT: s_xor_b32 s9, s2, s8 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s9 +; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) +; GCN-IR-NEXT: s_sub_i32 s2, 0, s9 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-IR-NEXT: s_mov_b32 s5, s1 +; GCN-IR-NEXT: s_mov_b32 s4, s0 +; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 33 +; GCN-IR-NEXT: s_ashr_i32 s3, s2, 31 +; GCN-IR-NEXT: s_add_i32 s2, s2, s3 +; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-IR-NEXT: s_xor_b32 s2, s2, s3 +; GCN-IR-NEXT: s_xor_b32 s0, s3, s8 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-IR-NEXT: v_mul_hi_u32 v0, s2, v0 +; GCN-IR-NEXT: v_readfirstlane_b32 s1, v0 +; GCN-IR-NEXT: s_mul_i32 s3, s1, s9 +; GCN-IR-NEXT: s_sub_i32 s2, s2, s3 +; GCN-IR-NEXT: s_add_i32 s8, s1, 1 +; GCN-IR-NEXT: s_sub_i32 s3, s2, s9 +; GCN-IR-NEXT: s_cmp_ge_u32 s2, s9 +; GCN-IR-NEXT: s_cselect_b32 s1, s8, s1 +; GCN-IR-NEXT: s_cselect_b32 s2, s3, s2 +; GCN-IR-NEXT: s_add_i32 s3, s1, 1 +; GCN-IR-NEXT: s_cmp_ge_u32 s2, s9 +; GCN-IR-NEXT: s_cselect_b32 s1, s3, s1 +; GCN-IR-NEXT: s_xor_b32 s1, s1, s0 +; GCN-IR-NEXT: s_sub_i32 s0, s1, s0 +; GCN-IR-NEXT: s_ashr_i32 s1, s0, 31 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s0 +; GCN-IR-NEXT: v_mov_b32_e32 v1, s1 +; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-IR-NEXT: s_endpgm %1 = ashr i64 %x, 33 %2 = ashr i64 %y, 33 @@ -764,62 +852,96 @@ define amdgpu_kernel void @s_test_sdiv23_64(ptr addrspace(1) %out, i64 %x, i64 % define amdgpu_kernel void @s_test_sdiv25_64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-LABEL: s_test_sdiv25_64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-NEXT: s_load_dword s1, s[0:1], 0xe -; GCN-NEXT: s_mov_b32 s3, 0xf000 -; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_load_dword s3, s[0:1], 0xe +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s0, s4 -; GCN-NEXT: s_ashr_i64 s[8:9], s[0:1], 39 -; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8 -; GCN-NEXT: s_mov_b32 s1, s5 -; GCN-NEXT: s_ashr_i64 s[4:5], s[6:7], 39 -; GCN-NEXT: v_cvt_f32_i32_e32 v1, s4 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-NEXT: s_xor_b32 s4, s4, s8 -; GCN-NEXT: s_ashr_i32 s4, s4, 30 -; GCN-NEXT: s_or_b32 s6, s4, 1 -; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| -; GCN-NEXT: s_and_b64 s[4:5], s[4:5], exec -; GCN-NEXT: s_cselect_b32 s4, s6, 0 -; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v2 -; GCN-NEXT: v_bfe_i32 v0, v0, 0, 25 -; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 -; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 39 +; GCN-NEXT: s_ashr_i32 s8, s2, 31 +; GCN-NEXT: s_add_i32 s2, s2, s8 +; GCN-NEXT: s_xor_b32 s9, s2, s8 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s9 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_sub_i32 s2, 0, s9 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: s_mov_b32 s5, s1 +; GCN-NEXT: s_mov_b32 s4, s0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 39 +; GCN-NEXT: s_ashr_i32 s3, s2, 31 +; GCN-NEXT: s_add_i32 s2, s2, s3 +; GCN-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-NEXT: s_xor_b32 s2, s2, s3 +; GCN-NEXT: s_xor_b32 s0, s3, s8 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_mul_hi_u32 v0, s2, v0 +; GCN-NEXT: v_readfirstlane_b32 s1, v0 +; GCN-NEXT: s_mul_i32 s3, s1, s9 +; GCN-NEXT: s_sub_i32 s2, s2, s3 +; GCN-NEXT: s_add_i32 s8, s1, 1 +; GCN-NEXT: s_sub_i32 s3, s2, s9 +; GCN-NEXT: s_cmp_ge_u32 s2, s9 +; GCN-NEXT: s_cselect_b32 s1, s8, s1 +; GCN-NEXT: s_cselect_b32 s2, s3, s2 +; GCN-NEXT: s_add_i32 s3, s1, 1 +; GCN-NEXT: s_cmp_ge_u32 s2, s9 +; GCN-NEXT: s_cselect_b32 s1, s3, s1 +; GCN-NEXT: s_xor_b32 s1, s1, s0 +; GCN-NEXT: s_sub_i32 s0, s1, s0 +; GCN-NEXT: s_ashr_i32 s1, s0, 31 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s1 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_sdiv25_64: ; GCN-IR: ; %bb.0: -; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-IR-NEXT: s_load_dword s1, s[0:1], 0xe -; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 -; GCN-IR-NEXT: s_mov_b32 s2, -1 +; GCN-IR-NEXT: s_load_dword s3, s[0:1], 0xe +; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 +; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_mov_b32 s0, s4 -; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[0:1], 39 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s8 -; GCN-IR-NEXT: s_mov_b32 s1, s5 -; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[6:7], 39 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s4 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-IR-NEXT: s_xor_b32 s4, s4, s8 -; GCN-IR-NEXT: s_ashr_i32 s4, s4, 30 -; GCN-IR-NEXT: s_or_b32 s6, s4, 1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| -; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], exec -; GCN-IR-NEXT: s_cselect_b32 s4, s6, 0 -; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s4, v2 -; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 25 -; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 -; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 39 +; GCN-IR-NEXT: s_ashr_i32 s8, s2, 31 +; GCN-IR-NEXT: s_add_i32 s2, s2, s8 +; GCN-IR-NEXT: s_xor_b32 s9, s2, s8 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s9 +; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) +; GCN-IR-NEXT: s_sub_i32 s2, 0, s9 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-IR-NEXT: s_mov_b32 s5, s1 +; GCN-IR-NEXT: s_mov_b32 s4, s0 +; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 39 +; GCN-IR-NEXT: s_ashr_i32 s3, s2, 31 +; GCN-IR-NEXT: s_add_i32 s2, s2, s3 +; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-IR-NEXT: s_xor_b32 s2, s2, s3 +; GCN-IR-NEXT: s_xor_b32 s0, s3, s8 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-IR-NEXT: v_mul_hi_u32 v0, s2, v0 +; GCN-IR-NEXT: v_readfirstlane_b32 s1, v0 +; GCN-IR-NEXT: s_mul_i32 s3, s1, s9 +; GCN-IR-NEXT: s_sub_i32 s2, s2, s3 +; GCN-IR-NEXT: s_add_i32 s8, s1, 1 +; GCN-IR-NEXT: s_sub_i32 s3, s2, s9 +; GCN-IR-NEXT: s_cmp_ge_u32 s2, s9 +; GCN-IR-NEXT: s_cselect_b32 s1, s8, s1 +; GCN-IR-NEXT: s_cselect_b32 s2, s3, s2 +; GCN-IR-NEXT: s_add_i32 s3, s1, 1 +; GCN-IR-NEXT: s_cmp_ge_u32 s2, s9 +; GCN-IR-NEXT: s_cselect_b32 s1, s3, s1 +; GCN-IR-NEXT: s_xor_b32 s1, s1, s0 +; GCN-IR-NEXT: s_sub_i32 s0, s1, s0 +; GCN-IR-NEXT: s_ashr_i32 s1, s0, 31 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s0 +; GCN-IR-NEXT: v_mov_b32_e32 v1, s1 +; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-IR-NEXT: s_endpgm %1 = ashr i64 %x, 39 %2 = ashr i64 %y, 39 diff --git a/llvm/test/CodeGen/AMDGPU/srem64.ll b/llvm/test/CodeGen/AMDGPU/srem64.ll index e10be23a7177..ed7f27b367fd 100644 --- a/llvm/test/CodeGen/AMDGPU/srem64.ll +++ b/llvm/test/CodeGen/AMDGPU/srem64.ll @@ -650,72 +650,90 @@ define i64 @v_test_srem24_64(i64 %x, i64 %y) { define amdgpu_kernel void @s_test_srem25_64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-LABEL: s_test_srem25_64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-NEXT: s_load_dword s1, s[0:1], 0xe -; GCN-NEXT: s_mov_b32 s3, 0xf000 -; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_load_dword s3, s[0:1], 0xe +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s0, s4 -; GCN-NEXT: s_ashr_i64 s[8:9], s[0:1], 39 -; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8 -; GCN-NEXT: s_mov_b32 s1, s5 -; GCN-NEXT: s_ashr_i64 s[4:5], s[6:7], 39 -; GCN-NEXT: v_cvt_f32_i32_e32 v1, s4 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-NEXT: s_xor_b32 s5, s4, s8 -; GCN-NEXT: s_ashr_i32 s5, s5, 30 -; GCN-NEXT: s_or_b32 s5, s5, 1 -; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 s[6:7], |v1|, |v0| -; GCN-NEXT: s_and_b64 s[6:7], s[6:7], exec -; GCN-NEXT: s_cselect_b32 s5, s5, 0 -; GCN-NEXT: v_readfirstlane_b32 s6, v2 -; GCN-NEXT: s_add_i32 s5, s6, s5 -; GCN-NEXT: s_mul_i32 s5, s5, s8 -; GCN-NEXT: s_sub_i32 s4, s4, s5 -; GCN-NEXT: s_bfe_i32 s4, s4, 0x190000 -; GCN-NEXT: s_ashr_i32 s5, s4, 31 -; GCN-NEXT: v_mov_b32_e32 v0, s4 -; GCN-NEXT: v_mov_b32_e32 v1, s5 -; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 39 +; GCN-NEXT: s_ashr_i32 s3, s2, 31 +; GCN-NEXT: s_add_i32 s2, s2, s3 +; GCN-NEXT: s_xor_b32 s8, s2, s3 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_sub_i32 s2, 0, s8 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: s_mov_b32 s4, s0 +; GCN-NEXT: s_mov_b32 s5, s1 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 39 +; GCN-NEXT: s_ashr_i32 s3, s2, 31 +; GCN-NEXT: s_add_i32 s2, s2, s3 +; GCN-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-NEXT: s_xor_b32 s2, s2, s3 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_mul_hi_u32 v0, s2, v0 +; GCN-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-NEXT: s_mul_i32 s0, s0, s8 +; GCN-NEXT: s_sub_i32 s0, s2, s0 +; GCN-NEXT: s_sub_i32 s1, s0, s8 +; GCN-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-NEXT: s_sub_i32 s1, s0, s8 +; GCN-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-NEXT: s_xor_b32 s0, s0, s3 +; GCN-NEXT: s_sub_i32 s0, s0, s3 +; GCN-NEXT: s_ashr_i32 s1, s0, 31 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s1 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_srem25_64: ; GCN-IR: ; %bb.0: -; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-IR-NEXT: s_load_dword s1, s[0:1], 0xe -; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 -; GCN-IR-NEXT: s_mov_b32 s2, -1 +; GCN-IR-NEXT: s_load_dword s3, s[0:1], 0xe +; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 +; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_mov_b32 s0, s4 -; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[0:1], 39 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s8 -; GCN-IR-NEXT: s_mov_b32 s1, s5 -; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[6:7], 39 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s4 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-IR-NEXT: s_xor_b32 s5, s4, s8 -; GCN-IR-NEXT: s_ashr_i32 s5, s5, 30 -; GCN-IR-NEXT: s_or_b32 s5, s5, 1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[6:7], |v1|, |v0| -; GCN-IR-NEXT: s_and_b64 s[6:7], s[6:7], exec -; GCN-IR-NEXT: s_cselect_b32 s5, s5, 0 -; GCN-IR-NEXT: v_readfirstlane_b32 s6, v2 -; GCN-IR-NEXT: s_add_i32 s5, s6, s5 -; GCN-IR-NEXT: s_mul_i32 s5, s5, s8 -; GCN-IR-NEXT: s_sub_i32 s4, s4, s5 -; GCN-IR-NEXT: s_bfe_i32 s4, s4, 0x190000 -; GCN-IR-NEXT: s_ashr_i32 s5, s4, 31 -; GCN-IR-NEXT: v_mov_b32_e32 v0, s4 -; GCN-IR-NEXT: v_mov_b32_e32 v1, s5 -; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 39 +; GCN-IR-NEXT: s_ashr_i32 s3, s2, 31 +; GCN-IR-NEXT: s_add_i32 s2, s2, s3 +; GCN-IR-NEXT: s_xor_b32 s8, s2, s3 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) +; GCN-IR-NEXT: s_sub_i32 s2, 0, s8 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-IR-NEXT: s_mov_b32 s4, s0 +; GCN-IR-NEXT: s_mov_b32 s5, s1 +; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 39 +; GCN-IR-NEXT: s_ashr_i32 s3, s2, 31 +; GCN-IR-NEXT: s_add_i32 s2, s2, s3 +; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-IR-NEXT: s_xor_b32 s2, s2, s3 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-IR-NEXT: v_mul_hi_u32 v0, s2, v0 +; GCN-IR-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-IR-NEXT: s_mul_i32 s0, s0, s8 +; GCN-IR-NEXT: s_sub_i32 s0, s2, s0 +; GCN-IR-NEXT: s_sub_i32 s1, s0, s8 +; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-IR-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-IR-NEXT: s_sub_i32 s1, s0, s8 +; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-IR-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-IR-NEXT: s_xor_b32 s0, s0, s3 +; GCN-IR-NEXT: s_sub_i32 s0, s0, s3 +; GCN-IR-NEXT: s_ashr_i32 s1, s0, 31 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s0 +; GCN-IR-NEXT: v_mov_b32_e32 v1, s1 +; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-IR-NEXT: s_endpgm %1 = ashr i64 %x, 39 %2 = ashr i64 %y, 39 @@ -727,72 +745,90 @@ define amdgpu_kernel void @s_test_srem25_64(ptr addrspace(1) %out, i64 %x, i64 % define amdgpu_kernel void @s_test_srem31_64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-LABEL: s_test_srem31_64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-NEXT: s_load_dword s1, s[0:1], 0xe -; GCN-NEXT: s_mov_b32 s3, 0xf000 -; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_load_dword s3, s[0:1], 0xe +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s0, s4 -; GCN-NEXT: s_ashr_i64 s[8:9], s[0:1], 33 -; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8 -; GCN-NEXT: s_mov_b32 s1, s5 -; GCN-NEXT: s_ashr_i64 s[4:5], s[6:7], 33 -; GCN-NEXT: v_cvt_f32_i32_e32 v1, s4 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-NEXT: s_xor_b32 s5, s4, s8 -; GCN-NEXT: s_ashr_i32 s5, s5, 30 -; GCN-NEXT: s_or_b32 s5, s5, 1 -; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 s[6:7], |v1|, |v0| -; GCN-NEXT: s_and_b64 s[6:7], s[6:7], exec -; GCN-NEXT: s_cselect_b32 s5, s5, 0 -; GCN-NEXT: v_readfirstlane_b32 s6, v2 -; GCN-NEXT: s_add_i32 s5, s6, s5 -; GCN-NEXT: s_mul_i32 s5, s5, s8 -; GCN-NEXT: s_sub_i32 s4, s4, s5 -; GCN-NEXT: s_bfe_i32 s4, s4, 0x1f0000 -; GCN-NEXT: s_ashr_i32 s5, s4, 31 -; GCN-NEXT: v_mov_b32_e32 v0, s4 -; GCN-NEXT: v_mov_b32_e32 v1, s5 -; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 33 +; GCN-NEXT: s_ashr_i32 s3, s2, 31 +; GCN-NEXT: s_add_i32 s2, s2, s3 +; GCN-NEXT: s_xor_b32 s8, s2, s3 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_sub_i32 s2, 0, s8 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: s_mov_b32 s4, s0 +; GCN-NEXT: s_mov_b32 s5, s1 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 33 +; GCN-NEXT: s_ashr_i32 s3, s2, 31 +; GCN-NEXT: s_add_i32 s2, s2, s3 +; GCN-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-NEXT: s_xor_b32 s2, s2, s3 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_mul_hi_u32 v0, s2, v0 +; GCN-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-NEXT: s_mul_i32 s0, s0, s8 +; GCN-NEXT: s_sub_i32 s0, s2, s0 +; GCN-NEXT: s_sub_i32 s1, s0, s8 +; GCN-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-NEXT: s_sub_i32 s1, s0, s8 +; GCN-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-NEXT: s_xor_b32 s0, s0, s3 +; GCN-NEXT: s_sub_i32 s0, s0, s3 +; GCN-NEXT: s_ashr_i32 s1, s0, 31 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s1 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_srem31_64: ; GCN-IR: ; %bb.0: -; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-IR-NEXT: s_load_dword s1, s[0:1], 0xe -; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 -; GCN-IR-NEXT: s_mov_b32 s2, -1 +; GCN-IR-NEXT: s_load_dword s3, s[0:1], 0xe +; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 +; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_mov_b32 s0, s4 -; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[0:1], 33 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s8 -; GCN-IR-NEXT: s_mov_b32 s1, s5 -; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[6:7], 33 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s4 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-IR-NEXT: s_xor_b32 s5, s4, s8 -; GCN-IR-NEXT: s_ashr_i32 s5, s5, 30 -; GCN-IR-NEXT: s_or_b32 s5, s5, 1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[6:7], |v1|, |v0| -; GCN-IR-NEXT: s_and_b64 s[6:7], s[6:7], exec -; GCN-IR-NEXT: s_cselect_b32 s5, s5, 0 -; GCN-IR-NEXT: v_readfirstlane_b32 s6, v2 -; GCN-IR-NEXT: s_add_i32 s5, s6, s5 -; GCN-IR-NEXT: s_mul_i32 s5, s5, s8 -; GCN-IR-NEXT: s_sub_i32 s4, s4, s5 -; GCN-IR-NEXT: s_bfe_i32 s4, s4, 0x1f0000 -; GCN-IR-NEXT: s_ashr_i32 s5, s4, 31 -; GCN-IR-NEXT: v_mov_b32_e32 v0, s4 -; GCN-IR-NEXT: v_mov_b32_e32 v1, s5 -; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 33 +; GCN-IR-NEXT: s_ashr_i32 s3, s2, 31 +; GCN-IR-NEXT: s_add_i32 s2, s2, s3 +; GCN-IR-NEXT: s_xor_b32 s8, s2, s3 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) +; GCN-IR-NEXT: s_sub_i32 s2, 0, s8 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-IR-NEXT: s_mov_b32 s4, s0 +; GCN-IR-NEXT: s_mov_b32 s5, s1 +; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 33 +; GCN-IR-NEXT: s_ashr_i32 s3, s2, 31 +; GCN-IR-NEXT: s_add_i32 s2, s2, s3 +; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-IR-NEXT: s_xor_b32 s2, s2, s3 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-IR-NEXT: v_mul_hi_u32 v0, s2, v0 +; GCN-IR-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-IR-NEXT: s_mul_i32 s0, s0, s8 +; GCN-IR-NEXT: s_sub_i32 s0, s2, s0 +; GCN-IR-NEXT: s_sub_i32 s1, s0, s8 +; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-IR-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-IR-NEXT: s_sub_i32 s1, s0, s8 +; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-IR-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-IR-NEXT: s_xor_b32 s0, s0, s3 +; GCN-IR-NEXT: s_sub_i32 s0, s0, s3 +; GCN-IR-NEXT: s_ashr_i32 s1, s0, 31 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s0 +; GCN-IR-NEXT: v_mov_b32_e32 v1, s1 +; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-IR-NEXT: s_endpgm %1 = ashr i64 %x, 33 %2 = ashr i64 %y, 33 @@ -805,59 +841,85 @@ define amdgpu_kernel void @s_test_srem31_64(ptr addrspace(1) %out, i64 %x, i64 % define amdgpu_kernel void @s_test_srem32_64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-LABEL: s_test_srem32_64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dword s8, s[0:1], 0xe -; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-NEXT: s_load_dword s2, s[0:1], 0xe ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8 -; GCN-NEXT: v_cvt_f32_i32_e32 v1, s3 -; GCN-NEXT: s_xor_b32 s2, s3, s8 -; GCN-NEXT: s_ashr_i32 s2, s2, 30 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-NEXT: s_or_b32 s2, s2, 1 -; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| -; GCN-NEXT: s_and_b64 s[4:5], s[4:5], exec -; GCN-NEXT: s_cselect_b32 s2, s2, 0 -; GCN-NEXT: v_add_i32_e32 v0, vcc, s2, v2 -; GCN-NEXT: v_mul_lo_u32 v0, v0, s8 +; GCN-NEXT: s_ashr_i32 s3, s2, 31 +; GCN-NEXT: s_add_i32 s2, s2, s3 +; GCN-NEXT: s_xor_b32 s8, s2, s3 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_sub_i32 s2, 0, s8 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GCN-NEXT: s_mov_b32 s4, s0 ; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: v_sub_i32_e32 v0, vcc, s3, v0 -; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-NEXT: s_ashr_i32 s2, s3, 31 +; GCN-NEXT: s_add_i32 s3, s3, s2 +; GCN-NEXT: s_xor_b32 s3, s3, s2 +; GCN-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_mul_hi_u32 v0, s3, v0 +; GCN-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-NEXT: s_mul_i32 s0, s0, s8 +; GCN-NEXT: s_sub_i32 s0, s3, s0 +; GCN-NEXT: s_sub_i32 s1, s0, s8 +; GCN-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-NEXT: s_sub_i32 s1, s0, s8 +; GCN-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-NEXT: s_xor_b32 s0, s0, s2 +; GCN-NEXT: s_sub_i32 s0, s0, s2 +; GCN-NEXT: s_ashr_i32 s1, s0, 31 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s1 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_srem32_64: ; GCN-IR: ; %bb.0: -; GCN-IR-NEXT: s_load_dword s8, s[0:1], 0xe -; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-IR-NEXT: s_load_dword s2, s[0:1], 0xe ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s8 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s3 -; GCN-IR-NEXT: s_xor_b32 s2, s3, s8 -; GCN-IR-NEXT: s_ashr_i32 s2, s2, 30 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-IR-NEXT: s_or_b32 s2, s2, 1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| -; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], exec -; GCN-IR-NEXT: s_cselect_b32 s2, s2, 0 -; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s2, v2 -; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s8 +; GCN-IR-NEXT: s_ashr_i32 s3, s2, 31 +; GCN-IR-NEXT: s_add_i32 s2, s2, s3 +; GCN-IR-NEXT: s_xor_b32 s8, s2, s3 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) +; GCN-IR-NEXT: s_sub_i32 s2, 0, s8 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GCN-IR-NEXT: s_mov_b32 s4, s0 ; GCN-IR-NEXT: s_mov_b32 s5, s1 -; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s3, v0 -; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-IR-NEXT: s_ashr_i32 s2, s3, 31 +; GCN-IR-NEXT: s_add_i32 s3, s3, s2 +; GCN-IR-NEXT: s_xor_b32 s3, s3, s2 +; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-IR-NEXT: v_mul_hi_u32 v0, s3, v0 +; GCN-IR-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-IR-NEXT: s_mul_i32 s0, s0, s8 +; GCN-IR-NEXT: s_sub_i32 s0, s3, s0 +; GCN-IR-NEXT: s_sub_i32 s1, s0, s8 +; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-IR-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-IR-NEXT: s_sub_i32 s1, s0, s8 +; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-IR-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-IR-NEXT: s_xor_b32 s0, s0, s2 +; GCN-IR-NEXT: s_sub_i32 s0, s0, s2 +; GCN-IR-NEXT: s_ashr_i32 s1, s0, 31 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s0 +; GCN-IR-NEXT: v_mov_b32_e32 v1, s1 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-IR-NEXT: s_endpgm %1 = ashr i64 %x, 32 diff --git a/llvm/test/CodeGen/AMDGPU/udiv.ll b/llvm/test/CodeGen/AMDGPU/udiv.ll index fbfaf3cff080..f686aad0cefc 100644 --- a/llvm/test/CodeGen/AMDGPU/udiv.ll +++ b/llvm/test/CodeGen/AMDGPU/udiv.ll @@ -1848,96 +1848,76 @@ define amdgpu_kernel void @v_udiv_i23(ptr addrspace(1) %out, ptr addrspace(1) %i define amdgpu_kernel void @v_udiv_i24(ptr addrspace(1) %out, ptr addrspace(1) %in) { ; SI-LABEL: v_udiv_i24: ; SI: ; %bb.0: -; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; SI-NEXT: s_mov_b32 s3, 0xf000 -; SI-NEXT: s_mov_b32 s2, -1 -; SI-NEXT: s_mov_b32 s10, s2 -; SI-NEXT: s_mov_b32 s11, s3 +; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NEXT: s_mov_b32 s7, 0xf000 +; SI-NEXT: s_mov_b32 s6, -1 +; SI-NEXT: s_mov_b32 s10, s6 +; SI-NEXT: s_mov_b32 s11, s7 ; SI-NEXT: s_waitcnt lgkmcnt(0) -; SI-NEXT: s_mov_b32 s8, s6 -; SI-NEXT: s_mov_b32 s9, s7 +; SI-NEXT: s_mov_b32 s8, s2 +; SI-NEXT: s_mov_b32 s9, s3 ; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0 offset:6 ; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 offset:4 ; SI-NEXT: buffer_load_ubyte v2, off, s[8:11], 0 offset:2 ; SI-NEXT: buffer_load_ushort v3, off, s[8:11], 0 -; SI-NEXT: s_mov_b32 s0, s4 -; SI-NEXT: s_mov_b32 s1, s5 +; SI-NEXT: s_mov_b32 s4, s0 +; SI-NEXT: s_mov_b32 s5, s1 ; SI-NEXT: s_waitcnt vmcnt(3) ; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: v_or_b32_e32 v0, v1, v0 -; SI-NEXT: v_cvt_f32_u32_e32 v1, v0 -; SI-NEXT: v_sub_i32_e32 v4, vcc, 0, v0 +; SI-NEXT: v_cvt_f32_u32_e32 v0, v0 ; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; SI-NEXT: v_rcp_iflag_f32_e32 v1, v1 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_or_b32_e32 v2, v3, v2 -; SI-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 -; SI-NEXT: v_cvt_u32_f32_e32 v1, v1 -; SI-NEXT: v_mul_lo_u32 v4, v4, v1 -; SI-NEXT: v_mul_hi_u32 v4, v1, v4 -; SI-NEXT: v_add_i32_e32 v1, vcc, v1, v4 -; SI-NEXT: v_mul_hi_u32 v1, v2, v1 -; SI-NEXT: v_mul_lo_u32 v3, v1, v0 -; SI-NEXT: v_add_i32_e32 v4, vcc, 1, v1 -; SI-NEXT: v_sub_i32_e32 v2, vcc, v2, v3 -; SI-NEXT: v_sub_i32_e32 v3, vcc, v2, v0 -; SI-NEXT: v_cmp_ge_u32_e32 vcc, v2, v0 -; SI-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc -; SI-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc -; SI-NEXT: v_add_i32_e32 v3, vcc, 1, v1 -; SI-NEXT: v_cmp_ge_u32_e32 vcc, v2, v0 -; SI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc +; SI-NEXT: v_or_b32_e32 v1, v3, v1 +; SI-NEXT: v_cvt_f32_u32_e32 v1, v1 +; SI-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; SI-NEXT: v_mul_f32_e32 v2, v1, v2 +; SI-NEXT: v_trunc_f32_e32 v2, v2 +; SI-NEXT: v_cvt_u32_f32_e32 v3, v2 +; SI-NEXT: v_mad_f32 v1, -v2, v0, v1 +; SI-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 +; SI-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc ; SI-NEXT: v_and_b32_e32 v0, 0xffffff, v0 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; SI-NEXT: s_endpgm ; ; VI-LABEL: v_udiv_i24: ; VI: ; %bb.0: -; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; VI-NEXT: s_mov_b32 s3, 0xf000 -; VI-NEXT: s_mov_b32 s2, -1 -; VI-NEXT: s_mov_b32 s10, s2 -; VI-NEXT: s_mov_b32 s11, s3 +; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; VI-NEXT: s_mov_b32 s7, 0xf000 +; VI-NEXT: s_mov_b32 s6, -1 +; VI-NEXT: s_mov_b32 s10, s6 +; VI-NEXT: s_mov_b32 s11, s7 ; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: s_mov_b32 s8, s6 -; VI-NEXT: s_mov_b32 s9, s7 +; VI-NEXT: s_mov_b32 s8, s2 +; VI-NEXT: s_mov_b32 s9, s3 ; VI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0 offset:6 ; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 offset:4 ; VI-NEXT: buffer_load_ubyte v2, off, s[8:11], 0 offset:2 ; VI-NEXT: buffer_load_ushort v3, off, s[8:11], 0 -; VI-NEXT: s_mov_b32 s0, s4 -; VI-NEXT: s_mov_b32 s1, s5 +; VI-NEXT: s_mov_b32 s4, s0 +; VI-NEXT: s_mov_b32 s5, s1 ; VI-NEXT: s_waitcnt vmcnt(3) ; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; VI-NEXT: s_waitcnt vmcnt(2) ; VI-NEXT: v_or_b32_e32 v0, v1, v0 -; VI-NEXT: v_cvt_f32_u32_e32 v1, v0 -; VI-NEXT: v_sub_u32_e32 v4, vcc, 0, v0 +; VI-NEXT: v_cvt_f32_u32_e32 v0, v0 ; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; VI-NEXT: v_rcp_iflag_f32_e32 v1, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v2 ; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_e32 v2, v3, v2 -; VI-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 -; VI-NEXT: v_cvt_u32_f32_e32 v1, v1 -; VI-NEXT: v_mul_lo_u32 v4, v4, v1 -; VI-NEXT: v_mul_hi_u32 v4, v1, v4 -; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v4 -; VI-NEXT: v_mul_hi_u32 v1, v2, v1 -; VI-NEXT: v_mul_lo_u32 v3, v1, v0 -; VI-NEXT: v_add_u32_e32 v4, vcc, 1, v1 -; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v3 -; VI-NEXT: v_sub_u32_e32 v3, vcc, v2, v0 -; VI-NEXT: v_cmp_ge_u32_e32 vcc, v2, v0 -; VI-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc -; VI-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc -; VI-NEXT: v_add_u32_e32 v3, vcc, 1, v1 -; VI-NEXT: v_cmp_ge_u32_e32 vcc, v2, v0 -; VI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc +; VI-NEXT: v_or_b32_e32 v1, v3, v1 +; VI-NEXT: v_cvt_f32_u32_e32 v1, v1 +; VI-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; VI-NEXT: v_mul_f32_e32 v2, v1, v2 +; VI-NEXT: v_trunc_f32_e32 v2, v2 +; VI-NEXT: v_cvt_u32_f32_e32 v3, v2 +; VI-NEXT: v_mad_f32 v1, -v2, v0, v1 +; VI-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 +; VI-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc ; VI-NEXT: v_and_b32_e32 v0, 0xffffff, v0 -; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; VI-NEXT: s_endpgm ; ; GCN-LABEL: v_udiv_i24: @@ -1947,50 +1927,40 @@ define amdgpu_kernel void @v_udiv_i24(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_add_u32 s4, s2, 4 ; GCN-NEXT: s_addc_u32 s5, s3, 0 ; GCN-NEXT: s_add_u32 s6, s2, 2 -; GCN-NEXT: v_mov_b32_e32 v0, s4 ; GCN-NEXT: s_addc_u32 s7, s3, 0 -; GCN-NEXT: v_mov_b32_e32 v1, s5 -; GCN-NEXT: s_add_u32 s4, s2, 6 -; GCN-NEXT: s_addc_u32 s5, s3, 0 -; GCN-NEXT: v_mov_b32_e32 v2, s4 -; GCN-NEXT: v_mov_b32_e32 v3, s5 -; GCN-NEXT: flat_load_ubyte v4, v[2:3] -; GCN-NEXT: flat_load_ushort v5, v[0:1] +; GCN-NEXT: v_mov_b32_e32 v0, s6 +; GCN-NEXT: v_mov_b32_e32 v1, s7 +; GCN-NEXT: s_add_u32 s6, s2, 6 +; GCN-NEXT: s_addc_u32 s7, s3, 0 ; GCN-NEXT: v_mov_b32_e32 v2, s6 -; GCN-NEXT: v_mov_b32_e32 v0, s2 ; GCN-NEXT: v_mov_b32_e32 v3, s7 -; GCN-NEXT: v_mov_b32_e32 v1, s3 -; GCN-NEXT: flat_load_ubyte v2, v[2:3] -; GCN-NEXT: flat_load_ushort v0, v[0:1] +; GCN-NEXT: v_mov_b32_e32 v4, s4 +; GCN-NEXT: v_mov_b32_e32 v5, s5 +; GCN-NEXT: flat_load_ubyte v6, v[2:3] +; GCN-NEXT: flat_load_ushort v4, v[4:5] +; GCN-NEXT: v_mov_b32_e32 v2, s2 +; GCN-NEXT: v_mov_b32_e32 v3, s3 +; GCN-NEXT: flat_load_ubyte v0, v[0:1] +; GCN-NEXT: flat_load_ushort v1, v[2:3] ; GCN-NEXT: s_waitcnt vmcnt(3) -; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v6 ; GCN-NEXT: s_waitcnt vmcnt(2) -; GCN-NEXT: v_or_b32_e32 v3, v5, v1 -; GCN-NEXT: v_cvt_f32_u32_e32 v1, v3 -; GCN-NEXT: v_sub_u32_e32 v4, vcc, 0, v3 +; GCN-NEXT: v_or_b32_e32 v2, v4, v2 +; GCN-NEXT: v_cvt_f32_u32_e32 v2, v2 ; GCN-NEXT: s_waitcnt vmcnt(1) -; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v1 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_or_b32_e32 v2, v0, v2 -; GCN-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 -; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 -; GCN-NEXT: v_mul_lo_u32 v4, v4, v1 -; GCN-NEXT: v_mul_hi_u32 v4, v1, v4 -; GCN-NEXT: v_add_u32_e32 v0, vcc, v1, v4 -; GCN-NEXT: v_mul_hi_u32 v4, v2, v0 +; GCN-NEXT: v_or_b32_e32 v0, v1, v0 +; GCN-NEXT: v_cvt_f32_u32_e32 v3, v0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v2 ; GCN-NEXT: v_mov_b32_e32 v0, s0 ; GCN-NEXT: v_mov_b32_e32 v1, s1 -; GCN-NEXT: v_mul_lo_u32 v5, v4, v3 -; GCN-NEXT: v_add_u32_e32 v6, vcc, 1, v4 -; GCN-NEXT: v_sub_u32_e32 v2, vcc, v2, v5 -; GCN-NEXT: v_sub_u32_e32 v5, vcc, v2, v3 -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v2, v3 -; GCN-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc -; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc -; GCN-NEXT: v_add_u32_e32 v5, vcc, 1, v4 -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v2, v3 -; GCN-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc +; GCN-NEXT: v_mul_f32_e32 v4, v3, v4 +; GCN-NEXT: v_trunc_f32_e32 v4, v4 +; GCN-NEXT: v_cvt_u32_f32_e32 v5, v4 +; GCN-NEXT: v_mad_f32 v3, -v4, v2, v3 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v2 +; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc ; GCN-NEXT: v_and_b32_e32 v2, 0xffffff, v2 ; GCN-NEXT: flat_store_dword v[0:1], v2 ; GCN-NEXT: s_endpgm @@ -2006,39 +1976,23 @@ define amdgpu_kernel void @v_udiv_i24(ptr addrspace(1) %out, ptr addrspace(1) %i ; GFX1030-NEXT: global_load_ubyte v3, v0, s[2:3] offset:2 ; GFX1030-NEXT: global_load_ushort v4, v0, s[2:3] ; GFX1030-NEXT: s_waitcnt vmcnt(3) -; GFX1030-NEXT: v_readfirstlane_b32 s2, v1 +; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX1030-NEXT: s_waitcnt vmcnt(2) -; GFX1030-NEXT: v_readfirstlane_b32 s3, v2 +; GFX1030-NEXT: v_or_b32_e32 v1, v2, v1 ; GFX1030-NEXT: s_waitcnt vmcnt(1) -; GFX1030-NEXT: v_readfirstlane_b32 s4, v3 +; GFX1030-NEXT: v_lshlrev_b32_e32 v2, 16, v3 +; GFX1030-NEXT: v_cvt_f32_u32_e32 v1, v1 ; GFX1030-NEXT: s_waitcnt vmcnt(0) -; GFX1030-NEXT: v_readfirstlane_b32 s5, v4 -; GFX1030-NEXT: s_lshl_b32 s2, s2, 16 -; GFX1030-NEXT: s_or_b32 s2, s3, s2 -; GFX1030-NEXT: s_lshl_b32 s4, s4, 16 -; GFX1030-NEXT: v_cvt_f32_u32_e32 v1, s2 -; GFX1030-NEXT: s_sub_i32 s6, 0, s2 -; GFX1030-NEXT: s_or_b32 s4, s5, s4 -; GFX1030-NEXT: v_rcp_iflag_f32_e32 v1, v1 -; GFX1030-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 -; GFX1030-NEXT: v_cvt_u32_f32_e32 v1, v1 -; GFX1030-NEXT: v_readfirstlane_b32 s3, v1 -; GFX1030-NEXT: s_mul_i32 s6, s6, s3 -; GFX1030-NEXT: s_mul_hi_u32 s6, s3, s6 -; GFX1030-NEXT: s_add_i32 s3, s3, s6 -; GFX1030-NEXT: s_mul_hi_u32 s3, s4, s3 -; GFX1030-NEXT: s_mul_i32 s5, s3, s2 -; GFX1030-NEXT: s_sub_i32 s4, s4, s5 -; GFX1030-NEXT: s_add_i32 s5, s3, 1 -; GFX1030-NEXT: s_sub_i32 s6, s4, s2 -; GFX1030-NEXT: s_cmp_ge_u32 s4, s2 -; GFX1030-NEXT: s_cselect_b32 s3, s5, s3 -; GFX1030-NEXT: s_cselect_b32 s4, s6, s4 -; GFX1030-NEXT: s_add_i32 s5, s3, 1 -; GFX1030-NEXT: s_cmp_ge_u32 s4, s2 -; GFX1030-NEXT: s_cselect_b32 s2, s5, s3 -; GFX1030-NEXT: s_and_b32 s2, s2, 0xffffff -; GFX1030-NEXT: v_mov_b32_e32 v1, s2 +; GFX1030-NEXT: v_or_b32_e32 v2, v4, v2 +; GFX1030-NEXT: v_rcp_iflag_f32_e32 v3, v1 +; GFX1030-NEXT: v_cvt_f32_u32_e32 v2, v2 +; GFX1030-NEXT: v_mul_f32_e32 v3, v2, v3 +; GFX1030-NEXT: v_trunc_f32_e32 v3, v3 +; GFX1030-NEXT: v_fma_f32 v2, -v3, v1, v2 +; GFX1030-NEXT: v_cvt_u32_f32_e32 v3, v3 +; GFX1030-NEXT: v_cmp_ge_f32_e64 vcc_lo, |v2|, v1 +; GFX1030-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v3, vcc_lo +; GFX1030-NEXT: v_and_b32_e32 v1, 0xffffff, v1 ; GFX1030-NEXT: global_store_dword v0, v1, s[0:1] ; GFX1030-NEXT: s_endpgm ; diff --git a/llvm/test/CodeGen/AMDGPU/udiv64.ll b/llvm/test/CodeGen/AMDGPU/udiv64.ll index bde3415c9d10..48b9c72ea689 100644 --- a/llvm/test/CodeGen/AMDGPU/udiv64.ll +++ b/llvm/test/CodeGen/AMDGPU/udiv64.ll @@ -497,45 +497,73 @@ define i64 @v_test_udiv24_i64(i64 %x, i64 %y) { define amdgpu_kernel void @s_test_udiv32_i64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-LABEL: s_test_udiv32_i64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dword s4, s[0:1], 0xe -; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-NEXT: s_load_dword s8, s[0:1], 0xe ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4 -; GCN-NEXT: v_cvt_f32_u32_e32 v1, s3 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GCN-NEXT: s_sub_i32 s2, 0, s8 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_mov_b32 s4, s0 ; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2 -; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_mul_hi_u32 v0, s3, v0 +; GCN-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-NEXT: s_mul_i32 s0, s0, s8 +; GCN-NEXT: s_sub_i32 s0, s3, s0 +; GCN-NEXT: s_sub_i32 s1, s0, s8 +; GCN-NEXT: v_add_i32_e32 v1, vcc, 1, v0 +; GCN-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-NEXT: s_cselect_b64 vcc, -1, 0 +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; GCN-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-NEXT: v_add_i32_e32 v1, vcc, 1, v0 +; GCN-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-NEXT: s_cselect_b64 vcc, -1, 0 +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; GCN-NEXT: v_mov_b32_e32 v1, 0 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_udiv32_i64: ; GCN-IR: ; %bb.0: -; GCN-IR-NEXT: s_load_dword s4, s[0:1], 0xe -; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-IR-NEXT: s_load_dword s8, s[0:1], 0xe ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s4 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s3 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GCN-IR-NEXT: s_sub_i32 s2, 0, s8 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_mov_b32 s4, s0 ; GCN-IR-NEXT: s_mov_b32 s5, s1 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2 -; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-IR-NEXT: v_mul_hi_u32 v0, s3, v0 +; GCN-IR-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-IR-NEXT: s_mul_i32 s0, s0, s8 +; GCN-IR-NEXT: s_sub_i32 s0, s3, s0 +; GCN-IR-NEXT: s_sub_i32 s1, s0, s8 +; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, 1, v0 +; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0 +; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; GCN-IR-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, 1, v0 +; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0 +; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 -; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-IR-NEXT: s_endpgm %1 = lshr i64 %x, 32 @@ -548,51 +576,77 @@ define amdgpu_kernel void @s_test_udiv32_i64(ptr addrspace(1) %out, i64 %x, i64 define amdgpu_kernel void @s_test_udiv31_i64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-LABEL: s_test_udiv31_i64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dword s4, s[0:1], 0xe -; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-NEXT: s_load_dword s2, s[0:1], 0xe ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_lshr_b32 s2, s4, 1 -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2 +; GCN-NEXT: s_lshr_b32 s8, s2, 1 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GCN-NEXT: s_sub_i32 s2, 0, s8 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_lshr_b32 s2, s3, 1 -; GCN-NEXT: v_cvt_f32_u32_e32 v1, s2 ; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_mul_hi_u32 v0, s2, v0 ; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2 -; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 +; GCN-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-NEXT: s_mul_i32 s0, s0, s8 +; GCN-NEXT: s_sub_i32 s0, s2, s0 +; GCN-NEXT: s_sub_i32 s1, s0, s8 +; GCN-NEXT: v_add_i32_e32 v1, vcc, 1, v0 +; GCN-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-NEXT: s_cselect_b64 vcc, -1, 0 +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; GCN-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-NEXT: v_add_i32_e32 v1, vcc, 1, v0 +; GCN-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-NEXT: s_cselect_b64 vcc, -1, 0 +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; GCN-NEXT: v_mov_b32_e32 v1, 0 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc -; GCN-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_udiv31_i64: ; GCN-IR: ; %bb.0: -; GCN-IR-NEXT: s_load_dword s4, s[0:1], 0xe -; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-IR-NEXT: s_load_dword s2, s[0:1], 0xe ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_lshr_b32 s2, s4, 1 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s2 +; GCN-IR-NEXT: s_lshr_b32 s8, s2, 1 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GCN-IR-NEXT: s_sub_i32 s2, 0, s8 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_lshr_b32 s2, s3, 1 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s2 ; GCN-IR-NEXT: s_mov_b32 s4, s0 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-IR-NEXT: v_mul_hi_u32 v0, s2, v0 ; GCN-IR-NEXT: s_mov_b32 s5, s1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2 -; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 +; GCN-IR-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-IR-NEXT: s_mul_i32 s0, s0, s8 +; GCN-IR-NEXT: s_sub_i32 s0, s2, s0 +; GCN-IR-NEXT: s_sub_i32 s1, s0, s8 +; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, 1, v0 +; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0 +; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; GCN-IR-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, 1, v0 +; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0 +; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 -; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc -; GCN-IR-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-IR-NEXT: s_endpgm %1 = lshr i64 %x, 33 diff --git a/llvm/test/CodeGen/AMDGPU/urem64.ll b/llvm/test/CodeGen/AMDGPU/urem64.ll index 56cd594fced7..f35589853393 100644 --- a/llvm/test/CodeGen/AMDGPU/urem64.ll +++ b/llvm/test/CodeGen/AMDGPU/urem64.ll @@ -413,52 +413,72 @@ define i64 @v_test_urem_i64(i64 %x, i64 %y) { define amdgpu_kernel void @s_test_urem31_i64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-LABEL: s_test_urem31_i64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dword s4, s[0:1], 0xe +; GCN-NEXT: s_load_dword s2, s[0:1], 0xe +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshr_b32 s8, s2, 1 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GCN-NEXT: s_sub_i32 s2, 0, s8 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, s2, v0 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-NEXT: v_mul_hi_u32 v1, v0, v1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s2, -1 -; GCN-NEXT: s_lshr_b32 s4, s4, 1 -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4 -; GCN-NEXT: s_lshr_b32 s5, s3, 1 -; GCN-NEXT: v_cvt_f32_u32_e32 v1, s5 -; GCN-NEXT: s_mov_b32 s3, 0xf000 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2 -; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 +; GCN-NEXT: s_lshr_b32 s2, s3, 1 +; GCN-NEXT: s_mov_b32 s4, s0 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_mul_hi_u32 v0, s2, v0 +; GCN-NEXT: s_mov_b32 s5, s1 ; GCN-NEXT: v_mov_b32_e32 v1, 0 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc -; GCN-NEXT: v_mul_lo_u32 v0, v0, s4 -; GCN-NEXT: v_sub_i32_e32 v0, vcc, s5, v0 -; GCN-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 -; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-NEXT: s_mul_i32 s0, s0, s8 +; GCN-NEXT: s_sub_i32 s0, s2, s0 +; GCN-NEXT: s_sub_i32 s1, s0, s8 +; GCN-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-NEXT: s_sub_i32 s1, s0, s8 +; GCN-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_urem31_i64: ; GCN-IR: ; %bb.0: -; GCN-IR-NEXT: s_load_dword s4, s[0:1], 0xe +; GCN-IR-NEXT: s_load_dword s2, s[0:1], 0xe +; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 +; GCN-IR-NEXT: s_mov_b32 s6, -1 +; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) +; GCN-IR-NEXT: s_lshr_b32 s8, s2, 1 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GCN-IR-NEXT: s_sub_i32 s2, 0, s8 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v0 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_mov_b32 s2, -1 -; GCN-IR-NEXT: s_lshr_b32 s4, s4, 1 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s4 -; GCN-IR-NEXT: s_lshr_b32 s5, s3, 1 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s5 -; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2 -; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 +; GCN-IR-NEXT: s_lshr_b32 s2, s3, 1 +; GCN-IR-NEXT: s_mov_b32 s4, s0 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-IR-NEXT: v_mul_hi_u32 v0, s2, v0 +; GCN-IR-NEXT: s_mov_b32 s5, s1 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 -; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc -; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s4 -; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s5, v0 -; GCN-IR-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 -; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-IR-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-IR-NEXT: s_mul_i32 s0, s0, s8 +; GCN-IR-NEXT: s_sub_i32 s0, s2, s0 +; GCN-IR-NEXT: s_sub_i32 s1, s0, s8 +; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-IR-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-IR-NEXT: s_sub_i32 s1, s0, s8 +; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-IR-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s0 +; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-IR-NEXT: s_endpgm %1 = lshr i64 %x, 33 %2 = lshr i64 %y, 33 @@ -472,39 +492,53 @@ define amdgpu_kernel void @s_test_urem31_v2i64(ptr addrspace(1) %out, <2 x i64> ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd ; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 -; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshr_b32 s2, s9, 1 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2 +; GCN-NEXT: s_sub_i32 s3, 0, s2 +; GCN-NEXT: s_lshr_b32 s4, s11, 1 +; GCN-NEXT: v_cvt_f32_u32_e32 v2, s4 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, s3, v0 +; GCN-NEXT: s_lshr_b32 s3, s5, 1 +; GCN-NEXT: s_lshr_b32 s5, s7, 1 +; GCN-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_mul_hi_u32 v0, s3, v0 +; GCN-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_readfirstlane_b32 s6, v0 +; GCN-NEXT: s_mul_i32 s6, s6, s2 +; GCN-NEXT: s_sub_i32 s3, s3, s6 +; GCN-NEXT: s_sub_i32 s6, s3, s2 +; GCN-NEXT: s_cmp_ge_u32 s3, s2 +; GCN-NEXT: s_cselect_b32 s3, s6, s3 +; GCN-NEXT: s_sub_i32 s6, s3, s2 +; GCN-NEXT: s_cmp_ge_u32 s3, s2 +; GCN-NEXT: s_cselect_b32 s6, s6, s3 +; GCN-NEXT: s_sub_i32 s2, 0, s4 +; GCN-NEXT: v_mul_lo_u32 v0, s2, v1 ; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s2, -1 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_lshr_b32 s4, s9, 1 -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4 -; GCN-NEXT: s_lshr_b32 s5, s5, 1 -; GCN-NEXT: s_lshr_b32 s6, s7, 1 -; GCN-NEXT: s_lshr_b32 s7, s11, 1 -; GCN-NEXT: v_cvt_f32_u32_e32 v2, s5 -; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v0 -; GCN-NEXT: v_cvt_f32_u32_e32 v4, s7 -; GCN-NEXT: v_cvt_f32_u32_e32 v5, s6 -; GCN-NEXT: v_mul_f32_e32 v3, v2, v3 -; GCN-NEXT: v_rcp_iflag_f32_e32 v6, v4 -; GCN-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-NEXT: v_mad_f32 v2, -v3, v0, v2 -; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0 -; GCN-NEXT: v_mul_f32_e32 v2, v5, v6 -; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc -; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2 -; GCN-NEXT: v_mad_f32 v2, -v2, v4, v5 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4 -; GCN-NEXT: v_mul_lo_u32 v0, v0, s4 -; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc -; GCN-NEXT: v_mul_lo_u32 v2, v2, s7 -; GCN-NEXT: v_sub_i32_e32 v0, vcc, s5, v0 -; GCN-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 -; GCN-NEXT: v_sub_i32_e32 v2, vcc, s6, v2 -; GCN-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2 +; GCN-NEXT: v_mul_hi_u32 v0, v1, v0 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0 +; GCN-NEXT: v_mul_hi_u32 v2, s5, v0 +; GCN-NEXT: v_mov_b32_e32 v0, s6 +; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mov_b32_e32 v3, v1 +; GCN-NEXT: v_readfirstlane_b32 s6, v2 +; GCN-NEXT: s_mul_i32 s6, s6, s4 +; GCN-NEXT: s_sub_i32 s5, s5, s6 +; GCN-NEXT: s_sub_i32 s6, s5, s4 +; GCN-NEXT: s_cmp_ge_u32 s5, s4 +; GCN-NEXT: s_cselect_b32 s5, s6, s5 +; GCN-NEXT: s_sub_i32 s6, s5, s4 +; GCN-NEXT: s_cmp_ge_u32 s5, s4 +; GCN-NEXT: s_cselect_b32 s4, s6, s5 +; GCN-NEXT: v_mov_b32_e32 v2, s4 ; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; GCN-NEXT: s_endpgm ; @@ -512,39 +546,53 @@ define amdgpu_kernel void @s_test_urem31_v2i64(ptr addrspace(1) %out, <2 x i64> ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd ; GCN-IR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) +; GCN-IR-NEXT: s_lshr_b32 s2, s9, 1 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s2 +; GCN-IR-NEXT: s_sub_i32 s3, 0, s2 +; GCN-IR-NEXT: s_lshr_b32 s4, s11, 1 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v2, s4 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v2 +; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-IR-NEXT: v_mul_lo_u32 v1, s3, v0 +; GCN-IR-NEXT: s_lshr_b32 s3, s5, 1 +; GCN-IR-NEXT: s_lshr_b32 s5, s7, 1 +; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-IR-NEXT: v_mul_hi_u32 v0, s3, v0 +; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-IR-NEXT: v_readfirstlane_b32 s6, v0 +; GCN-IR-NEXT: s_mul_i32 s6, s6, s2 +; GCN-IR-NEXT: s_sub_i32 s3, s3, s6 +; GCN-IR-NEXT: s_sub_i32 s6, s3, s2 +; GCN-IR-NEXT: s_cmp_ge_u32 s3, s2 +; GCN-IR-NEXT: s_cselect_b32 s3, s6, s3 +; GCN-IR-NEXT: s_sub_i32 s6, s3, s2 +; GCN-IR-NEXT: s_cmp_ge_u32 s3, s2 +; GCN-IR-NEXT: s_cselect_b32 s6, s6, s3 +; GCN-IR-NEXT: s_sub_i32 s2, 0, s4 +; GCN-IR-NEXT: v_mul_lo_u32 v0, s2, v1 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s2, -1 -; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_lshr_b32 s4, s9, 1 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s4 -; GCN-IR-NEXT: s_lshr_b32 s5, s5, 1 -; GCN-IR-NEXT: s_lshr_b32 s6, s7, 1 -; GCN-IR-NEXT: s_lshr_b32 s7, s11, 1 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v2, s5 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v3, v0 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v4, s7 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v5, s6 -; GCN-IR-NEXT: v_mul_f32_e32 v3, v2, v3 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v6, v4 -; GCN-IR-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-IR-NEXT: v_mad_f32 v2, -v3, v0, v2 -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v3 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v5, v6 -; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2 -; GCN-IR-NEXT: v_mad_f32 v2, -v2, v4, v5 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4 -; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s4 -; GCN-IR-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc -; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, s7 -; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s5, v0 -; GCN-IR-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 -; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s6, v2 -; GCN-IR-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2 +; GCN-IR-NEXT: v_mul_hi_u32 v0, v1, v0 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v1, v0 +; GCN-IR-NEXT: v_mul_hi_u32 v2, s5, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 +; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, v1 +; GCN-IR-NEXT: v_readfirstlane_b32 s6, v2 +; GCN-IR-NEXT: s_mul_i32 s6, s6, s4 +; GCN-IR-NEXT: s_sub_i32 s5, s5, s6 +; GCN-IR-NEXT: s_sub_i32 s6, s5, s4 +; GCN-IR-NEXT: s_cmp_ge_u32 s5, s4 +; GCN-IR-NEXT: s_cselect_b32 s5, s6, s5 +; GCN-IR-NEXT: s_sub_i32 s6, s5, s4 +; GCN-IR-NEXT: s_cmp_ge_u32 s5, s4 +; GCN-IR-NEXT: s_cselect_b32 s4, s6, s5 +; GCN-IR-NEXT: v_mov_b32_e32 v2, s4 ; GCN-IR-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; GCN-IR-NEXT: s_endpgm %1 = lshr <2 x i64> %x, @@ -616,39 +664,53 @@ define amdgpu_kernel void @s_test_urem23_64_v2i64(ptr addrspace(1) %out, <2 x i6 ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd ; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 -; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshr_b32 s2, s9, 1 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2 +; GCN-NEXT: s_sub_i32 s3, 0, s2 +; GCN-NEXT: s_lshr_b32 s4, s11, 9 +; GCN-NEXT: v_cvt_f32_u32_e32 v2, s4 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, s3, v0 +; GCN-NEXT: s_lshr_b32 s3, s5, 1 +; GCN-NEXT: s_lshr_b32 s5, s7, 9 +; GCN-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_mul_hi_u32 v0, s3, v0 +; GCN-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_readfirstlane_b32 s6, v0 +; GCN-NEXT: s_mul_i32 s6, s6, s2 +; GCN-NEXT: s_sub_i32 s3, s3, s6 +; GCN-NEXT: s_sub_i32 s6, s3, s2 +; GCN-NEXT: s_cmp_ge_u32 s3, s2 +; GCN-NEXT: s_cselect_b32 s3, s6, s3 +; GCN-NEXT: s_sub_i32 s6, s3, s2 +; GCN-NEXT: s_cmp_ge_u32 s3, s2 +; GCN-NEXT: s_cselect_b32 s6, s6, s3 +; GCN-NEXT: s_sub_i32 s2, 0, s4 +; GCN-NEXT: v_mul_lo_u32 v0, s2, v1 ; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s2, -1 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_lshr_b32 s4, s9, 1 -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4 -; GCN-NEXT: s_lshr_b32 s5, s5, 1 -; GCN-NEXT: s_lshr_b32 s6, s7, 9 -; GCN-NEXT: s_lshr_b32 s7, s11, 9 -; GCN-NEXT: v_cvt_f32_u32_e32 v2, s5 -; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v0 -; GCN-NEXT: v_cvt_f32_u32_e32 v4, s7 -; GCN-NEXT: v_cvt_f32_u32_e32 v5, s6 -; GCN-NEXT: v_mul_f32_e32 v3, v2, v3 -; GCN-NEXT: v_rcp_iflag_f32_e32 v6, v4 -; GCN-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-NEXT: v_mad_f32 v2, -v3, v0, v2 -; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0 -; GCN-NEXT: v_mul_f32_e32 v2, v5, v6 -; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc -; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2 -; GCN-NEXT: v_mad_f32 v2, -v2, v4, v5 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4 -; GCN-NEXT: v_mul_lo_u32 v0, v0, s4 -; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc -; GCN-NEXT: v_mul_lo_u32 v2, v2, s7 -; GCN-NEXT: v_sub_i32_e32 v0, vcc, s5, v0 -; GCN-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 -; GCN-NEXT: v_sub_i32_e32 v2, vcc, s6, v2 -; GCN-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2 +; GCN-NEXT: v_mul_hi_u32 v0, v1, v0 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0 +; GCN-NEXT: v_mul_hi_u32 v2, s5, v0 +; GCN-NEXT: v_mov_b32_e32 v0, s6 +; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mov_b32_e32 v3, v1 +; GCN-NEXT: v_readfirstlane_b32 s6, v2 +; GCN-NEXT: s_mul_i32 s6, s6, s4 +; GCN-NEXT: s_sub_i32 s5, s5, s6 +; GCN-NEXT: s_sub_i32 s6, s5, s4 +; GCN-NEXT: s_cmp_ge_u32 s5, s4 +; GCN-NEXT: s_cselect_b32 s5, s6, s5 +; GCN-NEXT: s_sub_i32 s6, s5, s4 +; GCN-NEXT: s_cmp_ge_u32 s5, s4 +; GCN-NEXT: s_cselect_b32 s4, s6, s5 +; GCN-NEXT: v_mov_b32_e32 v2, s4 ; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; GCN-NEXT: s_endpgm ; @@ -656,39 +718,53 @@ define amdgpu_kernel void @s_test_urem23_64_v2i64(ptr addrspace(1) %out, <2 x i6 ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd ; GCN-IR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) +; GCN-IR-NEXT: s_lshr_b32 s2, s9, 1 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s2 +; GCN-IR-NEXT: s_sub_i32 s3, 0, s2 +; GCN-IR-NEXT: s_lshr_b32 s4, s11, 9 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v2, s4 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v2 +; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-IR-NEXT: v_mul_lo_u32 v1, s3, v0 +; GCN-IR-NEXT: s_lshr_b32 s3, s5, 1 +; GCN-IR-NEXT: s_lshr_b32 s5, s7, 9 +; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-IR-NEXT: v_mul_hi_u32 v0, s3, v0 +; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-IR-NEXT: v_readfirstlane_b32 s6, v0 +; GCN-IR-NEXT: s_mul_i32 s6, s6, s2 +; GCN-IR-NEXT: s_sub_i32 s3, s3, s6 +; GCN-IR-NEXT: s_sub_i32 s6, s3, s2 +; GCN-IR-NEXT: s_cmp_ge_u32 s3, s2 +; GCN-IR-NEXT: s_cselect_b32 s3, s6, s3 +; GCN-IR-NEXT: s_sub_i32 s6, s3, s2 +; GCN-IR-NEXT: s_cmp_ge_u32 s3, s2 +; GCN-IR-NEXT: s_cselect_b32 s6, s6, s3 +; GCN-IR-NEXT: s_sub_i32 s2, 0, s4 +; GCN-IR-NEXT: v_mul_lo_u32 v0, s2, v1 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s2, -1 -; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_lshr_b32 s4, s9, 1 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s4 -; GCN-IR-NEXT: s_lshr_b32 s5, s5, 1 -; GCN-IR-NEXT: s_lshr_b32 s6, s7, 9 -; GCN-IR-NEXT: s_lshr_b32 s7, s11, 9 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v2, s5 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v3, v0 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v4, s7 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v5, s6 -; GCN-IR-NEXT: v_mul_f32_e32 v3, v2, v3 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v6, v4 -; GCN-IR-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-IR-NEXT: v_mad_f32 v2, -v3, v0, v2 -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v3 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v5, v6 -; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2 -; GCN-IR-NEXT: v_mad_f32 v2, -v2, v4, v5 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4 -; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s4 -; GCN-IR-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc -; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, s7 -; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s5, v0 -; GCN-IR-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 -; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s6, v2 -; GCN-IR-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2 +; GCN-IR-NEXT: v_mul_hi_u32 v0, v1, v0 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v1, v0 +; GCN-IR-NEXT: v_mul_hi_u32 v2, s5, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 +; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, v1 +; GCN-IR-NEXT: v_readfirstlane_b32 s6, v2 +; GCN-IR-NEXT: s_mul_i32 s6, s6, s4 +; GCN-IR-NEXT: s_sub_i32 s5, s5, s6 +; GCN-IR-NEXT: s_sub_i32 s6, s5, s4 +; GCN-IR-NEXT: s_cmp_ge_u32 s5, s4 +; GCN-IR-NEXT: s_cselect_b32 s5, s6, s5 +; GCN-IR-NEXT: s_sub_i32 s6, s5, s4 +; GCN-IR-NEXT: s_cmp_ge_u32 s5, s4 +; GCN-IR-NEXT: s_cselect_b32 s4, s6, s5 +; GCN-IR-NEXT: v_mov_b32_e32 v2, s4 ; GCN-IR-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; GCN-IR-NEXT: s_endpgm %1 = lshr <2 x i64> %x, -- GitLab From 36e8db7d8c9183c66363e76517772b074b4f53be Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Tue, 6 Feb 2024 07:49:34 -0800 Subject: [PATCH 085/266] [SLP][NFC]Extract main part of GetGEPCostDiff to a function, NFC. --- .../Transforms/Vectorize/SLPVectorizer.cpp | 150 ++++++++++-------- 1 file changed, 80 insertions(+), 70 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index b8d04322de29..c35d39f0a921 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -6954,6 +6954,82 @@ getShuffleCost(const TargetTransformInfo &TTI, TTI::ShuffleKind Kind, return TTI.getShuffleCost(Kind, Tp, Mask, CostKind, Index, SubTp, Args); } +/// Calculate the scalar and the vector costs from vectorizing set of GEPs. +static std::pair +getGEPCosts(const TargetTransformInfo &TTI, ArrayRef Ptrs, + Value *BasePtr, unsigned Opcode, TTI::TargetCostKind CostKind, + Type *ScalarTy, VectorType *VecTy) { + InstructionCost ScalarCost = 0; + InstructionCost VecCost = 0; + // Here we differentiate two cases: (1) when Ptrs represent a regular + // vectorization tree node (as they are pointer arguments of scattered + // loads) or (2) when Ptrs are the arguments of loads or stores being + // vectorized as plane wide unit-stride load/store since all the + // loads/stores are known to be from/to adjacent locations. + if (Opcode == Instruction::Load || Opcode == Instruction::Store) { + // Case 2: estimate costs for pointer related costs when vectorizing to + // a wide load/store. + // Scalar cost is estimated as a set of pointers with known relationship + // between them. + // For vector code we will use BasePtr as argument for the wide load/store + // but we also need to account all the instructions which are going to + // stay in vectorized code due to uses outside of these scalar + // loads/stores. + ScalarCost = TTI.getPointersChainCost( + Ptrs, BasePtr, TTI::PointersChainInfo::getUnitStride(), ScalarTy, + CostKind); + + SmallVector PtrsRetainedInVecCode; + for (Value *V : Ptrs) { + if (V == BasePtr) { + PtrsRetainedInVecCode.push_back(V); + continue; + } + auto *Ptr = dyn_cast(V); + // For simplicity assume Ptr to stay in vectorized code if it's not a + // GEP instruction. We don't care since it's cost considered free. + // TODO: We should check for any uses outside of vectorizable tree + // rather than just single use. + if (!Ptr || !Ptr->hasOneUse()) + PtrsRetainedInVecCode.push_back(V); + } + + if (PtrsRetainedInVecCode.size() == Ptrs.size()) { + // If all pointers stay in vectorized code then we don't have + // any savings on that. + return std::make_pair(TTI::TCC_Free, TTI::TCC_Free); + } + VecCost = TTI.getPointersChainCost(PtrsRetainedInVecCode, BasePtr, + TTI::PointersChainInfo::getKnownStride(), + VecTy, CostKind); + } else { + // Case 1: Ptrs are the arguments of loads that we are going to transform + // into masked gather load intrinsic. + // All the scalar GEPs will be removed as a result of vectorization. + // For any external uses of some lanes extract element instructions will + // be generated (which cost is estimated separately). + TTI::PointersChainInfo PtrsInfo = + all_of(Ptrs, + [](const Value *V) { + auto *Ptr = dyn_cast(V); + return Ptr && !Ptr->hasAllConstantIndices(); + }) + ? TTI::PointersChainInfo::getUnknownStride() + : TTI::PointersChainInfo::getKnownStride(); + + ScalarCost = + TTI.getPointersChainCost(Ptrs, BasePtr, PtrsInfo, ScalarTy, CostKind); + if (auto *BaseGEP = dyn_cast(BasePtr)) { + SmallVector Indices(BaseGEP->indices()); + VecCost = TTI.getGEPCost(BaseGEP->getSourceElementType(), + BaseGEP->getPointerOperand(), Indices, VecTy, + CostKind); + } + } + + return std::make_pair(ScalarCost, VecCost); +} + /// Merges shuffle masks and emits final shuffle instruction, if required. It /// supports shuffling of 2 input vectors. It implements lazy shuffles emission, /// when the actual shuffle instruction is generated only if this is actually @@ -7917,78 +7993,12 @@ BoUpSLP::getEntryCost(const TreeEntry *E, ArrayRef VectorizedVals, // Calculate cost difference from vectorizing set of GEPs. // Negative value means vectorizing is profitable. auto GetGEPCostDiff = [=](ArrayRef Ptrs, Value *BasePtr) { - InstructionCost ScalarCost = 0; - InstructionCost VecCost = 0; - // Here we differentiate two cases: (1) when Ptrs represent a regular - // vectorization tree node (as they are pointer arguments of scattered - // loads) or (2) when Ptrs are the arguments of loads or stores being - // vectorized as plane wide unit-stride load/store since all the - // loads/stores are known to be from/to adjacent locations. assert(E->State == TreeEntry::Vectorize && "Entry state expected to be Vectorize here."); - if (isa(VL0)) { - // Case 2: estimate costs for pointer related costs when vectorizing to - // a wide load/store. - // Scalar cost is estimated as a set of pointers with known relationship - // between them. - // For vector code we will use BasePtr as argument for the wide load/store - // but we also need to account all the instructions which are going to - // stay in vectorized code due to uses outside of these scalar - // loads/stores. - ScalarCost = TTI->getPointersChainCost( - Ptrs, BasePtr, TTI::PointersChainInfo::getUnitStride(), ScalarTy, - CostKind); - - SmallVector PtrsRetainedInVecCode; - for (Value *V : Ptrs) { - if (V == BasePtr) { - PtrsRetainedInVecCode.push_back(V); - continue; - } - auto *Ptr = dyn_cast(V); - // For simplicity assume Ptr to stay in vectorized code if it's not a - // GEP instruction. We don't care since it's cost considered free. - // TODO: We should check for any uses outside of vectorizable tree - // rather than just single use. - if (!Ptr || !Ptr->hasOneUse()) - PtrsRetainedInVecCode.push_back(V); - } - - if (PtrsRetainedInVecCode.size() == Ptrs.size()) { - // If all pointers stay in vectorized code then we don't have - // any savings on that. - LLVM_DEBUG(dumpTreeCosts(E, 0, ScalarCost, ScalarCost, - "Calculated GEPs cost for Tree")); - return InstructionCost{TTI::TCC_Free}; - } - VecCost = TTI->getPointersChainCost( - PtrsRetainedInVecCode, BasePtr, - TTI::PointersChainInfo::getKnownStride(), VecTy, CostKind); - } else { - // Case 1: Ptrs are the arguments of loads that we are going to transform - // into masked gather load intrinsic. - // All the scalar GEPs will be removed as a result of vectorization. - // For any external uses of some lanes extract element instructions will - // be generated (which cost is estimated separately). - TTI::PointersChainInfo PtrsInfo = - all_of(Ptrs, - [](const Value *V) { - auto *Ptr = dyn_cast(V); - return Ptr && !Ptr->hasAllConstantIndices(); - }) - ? TTI::PointersChainInfo::getUnknownStride() - : TTI::PointersChainInfo::getKnownStride(); - - ScalarCost = TTI->getPointersChainCost(Ptrs, BasePtr, PtrsInfo, ScalarTy, - CostKind); - if (auto *BaseGEP = dyn_cast(BasePtr)) { - SmallVector Indices(BaseGEP->indices()); - VecCost = TTI->getGEPCost(BaseGEP->getSourceElementType(), - BaseGEP->getPointerOperand(), Indices, VecTy, - CostKind); - } - } - + InstructionCost ScalarCost = 0; + InstructionCost VecCost = 0; + std::tie(ScalarCost, VecCost) = getGEPCosts( + *TTI, Ptrs, BasePtr, E->getOpcode(), CostKind, ScalarTy, VecTy); LLVM_DEBUG(dumpTreeCosts(E, 0, VecCost, ScalarCost, "Calculated GEPs cost for Tree")); -- GitLab From 388548359f5049b88a9738d8a9e67691503fbdef Mon Sep 17 00:00:00 2001 From: Chelsea Cassanova Date: Tue, 6 Feb 2024 08:17:23 -0800 Subject: [PATCH 086/266] [lldb][unittest] Add call_once flag to initialize debugger (#80786) I tried adding a new unit test to the core test suite (https://github.com/llvm/llvm-project/pull/79533) but it broke the test suite on AArch64 Linux due to hitting an assertion for calling `Debugger::Initialize` more than once. When the unit test suite is invoked as a standalone binary the test suite state is shared, and `Debugger::Initialize` gets called in `DiagnosticEventTest.cpp` before being called in `ProgressReportTest.cpp`. `DiagnosticEventTest.cpp` uses a call_once flag to initialize the debugger but it's local to that test. This commit adds a once_flag to `TestUtilities` so that `Debugger::Initialize` can be called once by the tests that use it. --- lldb/unittests/TestingSupport/TestUtilities.cpp | 1 + lldb/unittests/TestingSupport/TestUtilities.h | 7 ++++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/lldb/unittests/TestingSupport/TestUtilities.cpp b/lldb/unittests/TestingSupport/TestUtilities.cpp index 9e5523e48754..efdc6c5eb234 100644 --- a/lldb/unittests/TestingSupport/TestUtilities.cpp +++ b/lldb/unittests/TestingSupport/TestUtilities.cpp @@ -19,6 +19,7 @@ using namespace lldb_private; extern const char *TestMainArgv0; +std::once_flag TestUtilities::g_debugger_initialize_flag; std::string lldb_private::GetInputFilePath(const llvm::Twine &name) { llvm::SmallString<128> result = llvm::sys::path::parent_path(TestMainArgv0); llvm::sys::fs::make_absolute(result); diff --git a/lldb/unittests/TestingSupport/TestUtilities.h b/lldb/unittests/TestingSupport/TestUtilities.h index 811c4c152126..7d040d64db8d 100644 --- a/lldb/unittests/TestingSupport/TestUtilities.h +++ b/lldb/unittests/TestingSupport/TestUtilities.h @@ -31,6 +31,11 @@ namespace lldb_private { std::string GetInputFilePath(const llvm::Twine &name); +class TestUtilities { +public: + static std::once_flag g_debugger_initialize_flag; +}; + class TestFile { public: static llvm::Expected fromYaml(llvm::StringRef Yaml); @@ -51,6 +56,6 @@ private: std::string Buffer; }; -} +} // namespace lldb_private #endif -- GitLab From 299e5fef9dee3f2d3af8f9162075b8f1cfa34446 Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Tue, 6 Feb 2024 08:16:55 -0800 Subject: [PATCH 087/266] [SLP][NFC]Simplify/unify vectors for scattered/vectorized loads from gathers, NFC. --- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index c35d39f0a921..1fe39ca1a485 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -7090,8 +7090,8 @@ class BoUpSLP::ShuffleCostEstimator : public BaseShuffleAnalysis { !all_of(Gathers, [&](Value *V) { return R.getTreeEntry(V); }) && !isSplat(Gathers)) { SetVector VectorizedLoads; - SmallVector VectorizedStarts; - SmallVector> ScatterVectorized; + SmallVector VectorizedStarts; + SmallVector ScatterVectorized; unsigned StartIdx = 0; unsigned VF = VL.size() / 2; for (; VF >= MinVF; VF /= 2) { @@ -7119,9 +7119,9 @@ class BoUpSLP::ShuffleCostEstimator : public BaseShuffleAnalysis { // again. // TODO: better handling of loads with reorders. if (LS == LoadsState::Vectorize && CurrentOrder.empty()) - VectorizedStarts.push_back(cast(Slice.front())); + VectorizedStarts.push_back(Cnt); else - ScatterVectorized.emplace_back(Cnt, VF); + ScatterVectorized.push_back(Cnt); VectorizedLoads.insert(Slice.begin(), Slice.end()); // If we vectorized initial block, no need to try to vectorize // it again. @@ -7163,17 +7163,18 @@ class BoUpSLP::ShuffleCostEstimator : public BaseShuffleAnalysis { CostKind, TTI::OperandValueInfo(), LI); } auto *LoadTy = FixedVectorType::get(VL.front()->getType(), VF); - for (LoadInst *LI : VectorizedStarts) { + for (unsigned P : VectorizedStarts) { + auto *LI = cast(VL[P]); Align Alignment = LI->getAlign(); GatherCost += TTI.getMemoryOpCost(Instruction::Load, LoadTy, Alignment, LI->getPointerAddressSpace(), CostKind, TTI::OperandValueInfo(), LI); } - for (std::pair P : ScatterVectorized) { - auto *LI0 = cast(VL[P.first]); + for (unsigned P : ScatterVectorized) { + auto *LI0 = cast(VL[P]); Align CommonAlignment = - computeCommonAlignment(VL.slice(P.first + 1, VF - 1)); + computeCommonAlignment(VL.slice(P, VF)); GatherCost += TTI.getGatherScatterOpCost( Instruction::Load, LoadTy, LI0->getPointerOperand(), /*VariableMask=*/false, CommonAlignment, CostKind, LI0); -- GitLab From 6ce418113746c1d8a85012d1f8e22270eb5fdaf1 Mon Sep 17 00:00:00 2001 From: Jan Patrick Lehr Date: Tue, 6 Feb 2024 17:22:09 +0100 Subject: [PATCH 088/266] [OpenMP] HSA_ENABLE_SDMA visible in libomptarget tests (#80860) Enable the environment variable inside the test environment. This allows to disable SDMA engine transfers as a potential mitigation of flaky OpenMP offloading tests on AMDGPU. Motivated by the open ticket https://github.com/ROCm/ROCm/issues/2616 about a missed synchronization signal. --- openmp/libomptarget/test/lit.cfg | 3 +++ 1 file changed, 3 insertions(+) diff --git a/openmp/libomptarget/test/lit.cfg b/openmp/libomptarget/test/lit.cfg index d912b622c05b..fc1d436e51b7 100644 --- a/openmp/libomptarget/test/lit.cfg +++ b/openmp/libomptarget/test/lit.cfg @@ -31,6 +31,9 @@ if 'LIBOMPTARGET_LOCK_MAPPED_HOST_BUFFERS' in os.environ: if 'OMP_TARGET_OFFLOAD' in os.environ: config.environment['OMP_TARGET_OFFLOAD'] = os.environ['OMP_TARGET_OFFLOAD'] +if 'HSA_ENABLE_SDMA' in os.environ: + config.environment['HSA_ENABLE_SDMA'] = os.environ['HSA_ENABLE_SDMA'] + # set default environment variables for test if 'CHECK_OPENMP_ENV' in os.environ: test_env = os.environ['CHECK_OPENMP_ENV'].split() -- GitLab From 93a2a8cb7f6ab815849e8320bff54c965edd09e7 Mon Sep 17 00:00:00 2001 From: Ryosuke Niwa Date: Tue, 6 Feb 2024 08:28:15 -0800 Subject: [PATCH 089/266] Fix a crash in clang::isGetterOfRefCounted by checking nullptr in tryToFindPtrOrigin (#80768) --- .../Checkers/WebKit/ASTUtils.cpp | 15 ++++++----- .../WebKit/member-function-pointer-crash.cpp | 26 +++++++++++++++++++ 2 files changed, 35 insertions(+), 6 deletions(-) create mode 100644 clang/test/Analysis/Checkers/WebKit/member-function-pointer-crash.cpp diff --git a/clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp b/clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp index 64028b277021..4526fac64735 100644 --- a/clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp @@ -34,13 +34,16 @@ tryToFindPtrOrigin(const Expr *E, bool StopAtFirstRefCountedObj) { } if (auto *call = dyn_cast(E)) { if (auto *memberCall = dyn_cast(call)) { - std::optional IsGetterOfRefCt = isGetterOfRefCounted(memberCall->getMethodDecl()); - if (IsGetterOfRefCt && *IsGetterOfRefCt) { - E = memberCall->getImplicitObjectArgument(); - if (StopAtFirstRefCountedObj) { - return {E, true}; + if (auto *decl = memberCall->getMethodDecl()) { + std::optional IsGetterOfRefCt = + isGetterOfRefCounted(memberCall->getMethodDecl()); + if (IsGetterOfRefCt && *IsGetterOfRefCt) { + E = memberCall->getImplicitObjectArgument(); + if (StopAtFirstRefCountedObj) { + return {E, true}; + } + continue; } - continue; } } diff --git a/clang/test/Analysis/Checkers/WebKit/member-function-pointer-crash.cpp b/clang/test/Analysis/Checkers/WebKit/member-function-pointer-crash.cpp new file mode 100644 index 000000000000..16d3b89b3ac4 --- /dev/null +++ b/clang/test/Analysis/Checkers/WebKit/member-function-pointer-crash.cpp @@ -0,0 +1,26 @@ +// RUN: %clang_analyze_cc1 -analyzer-checker=alpha.webkit.UncountedLocalVarsChecker -verify %s + +#include "mock-types.h" + +class RenderStyle; + +class FillLayer { +public: + void ref() const; + void deref() const; +}; + +class FillLayersPropertyWrapper { +public: + typedef const FillLayer& (RenderStyle::*LayersGetter)() const; + +private: + bool canInterpolate(const RenderStyle& from) const + { + auto* fromLayer = &(from.*m_layersGetter)(); + // expected-warning@-1{{Local variable 'fromLayer' is uncounted and unsafe}} + return true; + } + + LayersGetter m_layersGetter; +}; -- GitLab From 56900278b578b4f7beedb8ac1e52c541d347f401 Mon Sep 17 00:00:00 2001 From: Chelsea Cassanova Date: Tue, 6 Feb 2024 08:36:00 -0800 Subject: [PATCH 090/266] [lldb][unittest] Use shared once_flag in DiagnosticEventTest (#80788) Incorporates the changes from https://github.com/llvm/llvm-project/pull/80786 to use a once_flag from `TestUtilities` instead of a local flag in order to prevent hitting an assertion that the debugger was initialized again in another test. --- lldb/unittests/Core/DiagnosticEventTest.cpp | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/lldb/unittests/Core/DiagnosticEventTest.cpp b/lldb/unittests/Core/DiagnosticEventTest.cpp index bca8f3789955..d06f164e87e7 100644 --- a/lldb/unittests/Core/DiagnosticEventTest.cpp +++ b/lldb/unittests/Core/DiagnosticEventTest.cpp @@ -11,6 +11,7 @@ #include "Plugins/Platform/MacOSX/PlatformMacOSX.h" #include "Plugins/Platform/MacOSX/PlatformRemoteMacOSX.h" #include "TestingSupport/SubsystemRAII.h" +#include "TestingSupport/TestUtilities.h" #include "lldb/Core/Debugger.h" #include "lldb/Core/DebuggerEvents.h" #include "lldb/Host/FileSystem.h" @@ -26,8 +27,6 @@ using namespace lldb_private::repro; static const constexpr std::chrono::seconds TIMEOUT(0); static const constexpr size_t DEBUGGERS = 3; -static std::once_flag debugger_initialize_flag; - namespace { class DiagnosticEventTest : public ::testing::Test { public: @@ -35,7 +34,7 @@ public: FileSystem::Initialize(); HostInfo::Initialize(); PlatformMacOSX::Initialize(); - std::call_once(debugger_initialize_flag, + std::call_once(TestUtilities::g_debugger_initialize_flag, []() { Debugger::Initialize(nullptr); }); ArchSpec arch("x86_64-apple-macosx-"); Platform::SetHostPlatform( -- GitLab From a628f68a9c4ce6f3dcd0c8bb3650db45671ed15a Mon Sep 17 00:00:00 2001 From: Owen Pan Date: Tue, 6 Feb 2024 09:00:15 -0800 Subject: [PATCH 091/266] Revert "[clang] Mark clang-format-ignore.cpp as unsupported on Windows" This reverts commit dc61ebb44c11d2f5d03b7dd9cb80a0644a30775e. See https://github.com/llvm/llvm-project/pull/76733#issuecomment-1890311152. --- clang/test/Format/clang-format-ignore.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/clang/test/Format/clang-format-ignore.cpp b/clang/test/Format/clang-format-ignore.cpp index b4e526463000..fb49fa9dd52c 100644 --- a/clang/test/Format/clang-format-ignore.cpp +++ b/clang/test/Format/clang-format-ignore.cpp @@ -1,4 +1,3 @@ -// UNSUPPORTED: system-windows // RUN: rm -rf %t.dir // RUN: mkdir -p %t.dir/level1/level2 -- GitLab From 8ea858b96787578e814723a009f443808f446378 Mon Sep 17 00:00:00 2001 From: Mingming Liu Date: Tue, 6 Feb 2024 09:22:34 -0800 Subject: [PATCH 092/266] [CallPromotionUtil] See through function alias when devirtualizing a virtual call on an alloca. (#80736) - Extract utility function from `DevirtModule::tryFindVirtualCallTargets` [1], which sees through an alias to a function. Call this utility function in the WPD callsite. - For type profiling work, this helper function will be used by indirect-call-promotion pass to find the function pointer at a specified vtable offset (an example in [2]) [1] https://github.com/llvm/llvm-project/blob/b99163fe8feeacba7797d5479bbcd5d8f327dd2d/llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp#L1069-L1082 [2] https://github.com/minglotus-6/llvm-project/blob/77a0ef12de82d11f448f7f9de6f2dcf87d9b74af/llvm/lib/Transforms/Instrumentation/IndirectCallPromotion.cpp#L347 --- .../include/llvm/Analysis/TypeMetadataUtils.h | 9 +++++++++ llvm/lib/Analysis/TypeMetadataUtils.cpp | 20 +++++++++++++++++++ .../lib/Transforms/IPO/WholeProgramDevirt.cpp | 15 ++++---------- .../Transforms/Utils/CallPromotionUtils.cpp | 11 ++++------ 4 files changed, 37 insertions(+), 18 deletions(-) diff --git a/llvm/include/llvm/Analysis/TypeMetadataUtils.h b/llvm/include/llvm/Analysis/TypeMetadataUtils.h index dab67aad1ab0..8894945c28d9 100644 --- a/llvm/include/llvm/Analysis/TypeMetadataUtils.h +++ b/llvm/include/llvm/Analysis/TypeMetadataUtils.h @@ -15,6 +15,7 @@ #define LLVM_ANALYSIS_TYPEMETADATAUTILS_H #include +#include namespace llvm { @@ -24,6 +25,7 @@ class CallInst; class Constant; class Function; class DominatorTree; +class GlobalVariable; class Instruction; class Module; @@ -77,6 +79,13 @@ void findDevirtualizableCallsForTypeCheckedLoad( Constant *getPointerAtOffset(Constant *I, uint64_t Offset, Module &M, Constant *TopLevelGlobal = nullptr); +/// Given a vtable and a specified offset, returns the function and the trivial +/// pointer at the specified offset in pair iff the pointer at the specified +/// offset is a function or an alias to a function. Returns a pair of nullptr +/// otherwise. +std::pair +getFunctionAtVTableOffset(GlobalVariable *GV, uint64_t Offset, Module &M); + /// Finds the same "relative pointer" pattern as described above, where the /// target is `F`, and replaces the entire pattern with a constant zero. void replaceRelativePointerUsersWithZero(Function *F); diff --git a/llvm/lib/Analysis/TypeMetadataUtils.cpp b/llvm/lib/Analysis/TypeMetadataUtils.cpp index bbaee06ed8a5..b8dcc39e9223 100644 --- a/llvm/lib/Analysis/TypeMetadataUtils.cpp +++ b/llvm/lib/Analysis/TypeMetadataUtils.cpp @@ -201,6 +201,26 @@ Constant *llvm::getPointerAtOffset(Constant *I, uint64_t Offset, Module &M, return nullptr; } +std::pair +llvm::getFunctionAtVTableOffset(GlobalVariable *GV, uint64_t Offset, + Module &M) { + Constant *Ptr = getPointerAtOffset(GV->getInitializer(), Offset, M, GV); + if (!Ptr) + return std::pair(nullptr, nullptr); + + auto C = Ptr->stripPointerCasts(); + // Make sure this is a function or alias to a function. + auto Fn = dyn_cast(C); + auto A = dyn_cast(C); + if (!Fn && A) + Fn = dyn_cast(A->getAliasee()); + + if (!Fn) + return std::pair(nullptr, nullptr); + + return std::pair(Fn, C); +} + void llvm::replaceRelativePointerUsersWithZero(Function *F) { for (auto *U : F->users()) { auto *PtrExpr = dyn_cast(U); diff --git a/llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp b/llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp index 01aba47cdbff..75f7de4290a7 100644 --- a/llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp +++ b/llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp @@ -1066,17 +1066,10 @@ bool DevirtModule::tryFindVirtualCallTargets( GlobalObject::VCallVisibilityPublic) return false; - Constant *Ptr = getPointerAtOffset(TM.Bits->GV->getInitializer(), - TM.Offset + ByteOffset, M, TM.Bits->GV); - if (!Ptr) - return false; - - auto C = Ptr->stripPointerCasts(); - // Make sure this is a function or alias to a function. - auto Fn = dyn_cast(C); - auto A = dyn_cast(C); - if (!Fn && A) - Fn = dyn_cast(A->getAliasee()); + Function *Fn = nullptr; + Constant *C = nullptr; + std::tie(Fn, C) = + getFunctionAtVTableOffset(TM.Bits->GV, TM.Offset + ByteOffset, M); if (!Fn) return false; diff --git a/llvm/lib/Transforms/Utils/CallPromotionUtils.cpp b/llvm/lib/Transforms/Utils/CallPromotionUtils.cpp index e42cdab64446..4e84927f1cfc 100644 --- a/llvm/lib/Transforms/Utils/CallPromotionUtils.cpp +++ b/llvm/lib/Transforms/Utils/CallPromotionUtils.cpp @@ -597,16 +597,13 @@ bool llvm::tryPromoteCall(CallBase &CB) { // Not in the form of a global constant variable with an initializer. return false; - Constant *VTableGVInitializer = GV->getInitializer(); APInt VTableGVOffset = VTableOffsetGVBase + VTableOffset; if (!(VTableGVOffset.getActiveBits() <= 64)) return false; // Out of range. - Constant *Ptr = getPointerAtOffset(VTableGVInitializer, - VTableGVOffset.getZExtValue(), - *M); - if (!Ptr) - return false; // No constant (function) pointer found. - Function *DirectCallee = dyn_cast(Ptr->stripPointerCasts()); + + Function *DirectCallee = nullptr; + std::tie(DirectCallee, std::ignore) = + getFunctionAtVTableOffset(GV, VTableGVOffset.getZExtValue(), *M); if (!DirectCallee) return false; // No function pointer found. -- GitLab From 6b2fd7aed66d592738f26c76caa8fff95e168598 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Tue, 6 Feb 2024 09:23:33 -0800 Subject: [PATCH 093/266] [MIPS] Use generic isBlockOnlyReachableByFallthrough (#80799) FastISel may create a redundant BGTZ terminal which fallthroughes. ``` BGTZ %2:gpr32, %bb.1, implicit-def $at bb.1.bb1: ; predecessors: %bb.0 ``` The `!I->isBarrier()` check in MipsAsmPrinter::isBlockOnlyReachableByFallthrough will incorrectly not print a label, leading to a `Undefined temporary symbol ` error when we try assembling the output assembly file. See the updated `Fast-ISel/pr40325.ll` and https://github.com/rust-lang/rust/issues/108835 In addition, the `SwitchInst` condition is too conservative and prints many unneeded labels (see the updated tests). Just use the generic isBlockOnlyReachableByFallthrough, updated by commit 1995b9fead62f2f6c0ad217bd00ce3184f741fdb for SPARC, which also handles MIPS. --- llvm/lib/Target/Mips/MipsAsmPrinter.cpp | 39 ------------------- llvm/lib/Target/Mips/MipsAsmPrinter.h | 2 - llvm/test/CodeGen/Mips/Fast-ISel/pr40325.ll | 2 +- .../GlobalISel/llvm-ir/jump_table_and_brjt.ll | 8 ++-- .../unsafe-in-forbidden-slot.ll | 4 +- .../Mips/indirect-jump-hazard/jumptables.ll | 16 ++++---- llvm/test/CodeGen/Mips/jump-table-mul.ll | 2 +- llvm/test/CodeGen/Mips/pseudo-jump-fill.ll | 2 +- 8 files changed, 17 insertions(+), 58 deletions(-) diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp index 718844bc36ff..66b2b0de8d52 100644 --- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp +++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp @@ -471,45 +471,6 @@ void MipsAsmPrinter::emitBasicBlockEnd(const MachineBasicBlock &MBB) { TS.emitDirectiveInsn(); } -/// isBlockOnlyReachableByFallthough - Return true if the basic block has -/// exactly one predecessor and the control transfer mechanism between -/// the predecessor and this block is a fall-through. -bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock* - MBB) const { - // The predecessor has to be immediately before this block. - const MachineBasicBlock *Pred = *MBB->pred_begin(); - - // If the predecessor is a switch statement, assume a jump table - // implementation, so it is not a fall through. - if (const BasicBlock *bb = Pred->getBasicBlock()) - if (isa(bb->getTerminator())) - return false; - - // If this is a landing pad, it isn't a fall through. If it has no preds, - // then nothing falls through to it. - if (MBB->isEHPad() || MBB->pred_empty()) - return false; - - // If there isn't exactly one predecessor, it can't be a fall through. - if (MBB->pred_size() != 1) - return false; - - // The predecessor has to be immediately before this block. - if (!Pred->isLayoutSuccessor(MBB)) - return false; - - // If the block is completely empty, then it definitely does fall through. - if (Pred->empty()) - return true; - - // Otherwise, check the last instruction. - // Check if the last terminator is an unconditional branch. - MachineBasicBlock::const_iterator I = Pred->end(); - while (I != Pred->begin() && !(--I)->isTerminator()) ; - - return !I->isBarrier(); -} - // Print out an operand for an inline asm expression. bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, const char *ExtraCode, raw_ostream &O) { diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.h b/llvm/lib/Target/Mips/MipsAsmPrinter.h index 64424b181504..0b55089385d7 100644 --- a/llvm/lib/Target/Mips/MipsAsmPrinter.h +++ b/llvm/lib/Target/Mips/MipsAsmPrinter.h @@ -142,8 +142,6 @@ public: void emitFunctionBodyStart() override; void emitFunctionBodyEnd() override; void emitBasicBlockEnd(const MachineBasicBlock &MBB) override; - bool isBlockOnlyReachableByFallthrough( - const MachineBasicBlock* MBB) const override; bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &O) override; bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/pr40325.ll b/llvm/test/CodeGen/Mips/Fast-ISel/pr40325.ll index 9e64d7b2fa03..c276515920d5 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/pr40325.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/pr40325.ll @@ -11,7 +11,7 @@ define void @test(i32 %x, ptr %p) nounwind { ; CHECK-NEXT: andi $1, $4, 1 ; CHECK-NEXT: bgtz $1, $BB0_1 ; CHECK-NEXT: nop -; CHECK-NEXT: # %bb.1: # %foo +; CHECK-NEXT: $BB0_1: # %foo ; CHECK-NEXT: jr $ra ; CHECK-NEXT: nop %y = and i32 %x, 1 diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll index 4c10fedaa4a8..74765ff0e8f1 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll @@ -25,7 +25,7 @@ define i32 @mod4_0_to_11(i32 %a) { ; MIPS32-NEXT: sltu $1, $1, $2 ; MIPS32-NEXT: bnez $1, $BB0_6 ; MIPS32-NEXT: nop -; MIPS32-NEXT: $BB0_1: # %entry +; MIPS32-NEXT: # %bb.1: # %entry ; MIPS32-NEXT: lw $2, 28($sp) # 4-byte Folded Reload ; MIPS32-NEXT: lui $1, %hi($JTI0_0) ; MIPS32-NEXT: sll $2, $2, 2 @@ -65,7 +65,7 @@ define i32 @mod4_0_to_11(i32 %a) { ; MIPS32-NEXT: sltu $1, $1, $2 ; MIPS32-NEXT: bnez $1, $BB0_13 ; MIPS32-NEXT: nop -; MIPS32-NEXT: $BB0_8: # %sw.epilog +; MIPS32-NEXT: # %bb.8: # %sw.epilog ; MIPS32-NEXT: lw $2, 0($sp) # 4-byte Folded Reload ; MIPS32-NEXT: lui $1, %hi($JTI0_1) ; MIPS32-NEXT: sll $2, $2, 2 @@ -125,7 +125,7 @@ define i32 @mod4_0_to_11(i32 %a) { ; MIPS32_PIC-NEXT: sltu $1, $1, $2 ; MIPS32_PIC-NEXT: bnez $1, $BB0_6 ; MIPS32_PIC-NEXT: nop -; MIPS32_PIC-NEXT: $BB0_1: # %entry +; MIPS32_PIC-NEXT: # %bb.1: # %entry ; MIPS32_PIC-NEXT: lw $2, 8($sp) # 4-byte Folded Reload ; MIPS32_PIC-NEXT: lw $3, 36($sp) # 4-byte Folded Reload ; MIPS32_PIC-NEXT: lw $1, %got($JTI0_0)($2) @@ -167,7 +167,7 @@ define i32 @mod4_0_to_11(i32 %a) { ; MIPS32_PIC-NEXT: sltu $1, $1, $2 ; MIPS32_PIC-NEXT: bnez $1, $BB0_13 ; MIPS32_PIC-NEXT: nop -; MIPS32_PIC-NEXT: $BB0_8: # %sw.epilog +; MIPS32_PIC-NEXT: # %bb.8: # %sw.epilog ; MIPS32_PIC-NEXT: lw $2, 8($sp) # 4-byte Folded Reload ; MIPS32_PIC-NEXT: lw $3, 4($sp) # 4-byte Folded Reload ; MIPS32_PIC-NEXT: lw $1, %got($JTI0_1)($2) diff --git a/llvm/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll b/llvm/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll index cbd8b2370ac9..de61515cff9b 100644 --- a/llvm/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll +++ b/llvm/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll @@ -18,7 +18,7 @@ sw.bb: ; preds = %entry br label %sw.epilog ; CHECK: beqzc ; CHECK-NEXT: nop -; CHECK-NEXT: .LBB +; CHECK-NEXT: # %bb.1 ; CHECK-NEXT: j sw.bb1: ; preds = %entry, %entry @@ -26,7 +26,7 @@ sw.bb1: ; preds = %entry, %entry br label %sw.epilog ; CHECK: bnezc ; CHECK-NEXT: nop -; CHECK-NEXT: .LBB +; CHECK-NEXT: # %bb.3 ; CHECK-NEXT: j sw.epilog: ; preds = %entry, %sw.bb1, %sw.bb diff --git a/llvm/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll b/llvm/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll index 1ce46cfa07cf..634216027ef6 100644 --- a/llvm/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll +++ b/llvm/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll @@ -42,7 +42,7 @@ define ptr @_Z3fooi(i32 signext %Letter) { ; MIPS32R2-NEXT: sltiu $1, $4, 7 ; MIPS32R2-NEXT: beqz $1, $BB0_6 ; MIPS32R2-NEXT: sw $4, 4($sp) -; MIPS32R2-NEXT: $BB0_1: # %entry +; MIPS32R2-NEXT: # %bb.1: # %entry ; MIPS32R2-NEXT: sll $1, $4, 2 ; MIPS32R2-NEXT: lui $2, %hi($JTI0_0) ; MIPS32R2-NEXT: addu $1, $1, $2 @@ -100,7 +100,7 @@ define ptr @_Z3fooi(i32 signext %Letter) { ; MIPS32R6-NEXT: sltiu $1, $4, 7 ; MIPS32R6-NEXT: beqz $1, $BB0_6 ; MIPS32R6-NEXT: sw $4, 4($sp) -; MIPS32R6-NEXT: $BB0_1: # %entry +; MIPS32R6-NEXT: # %bb.1: # %entry ; MIPS32R6-NEXT: sll $1, $4, 2 ; MIPS32R6-NEXT: lui $2, %hi($JTI0_0) ; MIPS32R6-NEXT: addu $1, $1, $2 @@ -159,7 +159,7 @@ define ptr @_Z3fooi(i32 signext %Letter) { ; MIPS64R2-NEXT: sltiu $1, $2, 7 ; MIPS64R2-NEXT: beqz $1, .LBB0_6 ; MIPS64R2-NEXT: sw $4, 4($sp) -; MIPS64R2-NEXT: .LBB0_1: # %entry +; MIPS64R2-NEXT: # %bb.1: # %entry ; MIPS64R2-NEXT: dsll $1, $2, 3 ; MIPS64R2-NEXT: lui $2, %highest(.LJTI0_0) ; MIPS64R2-NEXT: daddiu $2, $2, %higher(.LJTI0_0) @@ -254,7 +254,7 @@ define ptr @_Z3fooi(i32 signext %Letter) { ; MIPS64R6-NEXT: sltiu $1, $2, 7 ; MIPS64R6-NEXT: beqz $1, .LBB0_6 ; MIPS64R6-NEXT: sw $4, 4($sp) -; MIPS64R6-NEXT: .LBB0_1: # %entry +; MIPS64R6-NEXT: # %bb.1: # %entry ; MIPS64R6-NEXT: dsll $1, $2, 3 ; MIPS64R6-NEXT: lui $2, %highest(.LJTI0_0) ; MIPS64R6-NEXT: daddiu $2, $2, %higher(.LJTI0_0) @@ -351,7 +351,7 @@ define ptr @_Z3fooi(i32 signext %Letter) { ; PIC-MIPS32R2-NEXT: sltiu $1, $4, 7 ; PIC-MIPS32R2-NEXT: beqz $1, $BB0_6 ; PIC-MIPS32R2-NEXT: sw $4, 4($sp) -; PIC-MIPS32R2-NEXT: $BB0_1: # %entry +; PIC-MIPS32R2-NEXT: # %bb.1: # %entry ; PIC-MIPS32R2-NEXT: sll $1, $4, 2 ; PIC-MIPS32R2-NEXT: lw $3, %got($JTI0_0)($2) ; PIC-MIPS32R2-NEXT: addu $1, $1, $3 @@ -413,7 +413,7 @@ define ptr @_Z3fooi(i32 signext %Letter) { ; PIC-MIPS32R6-NEXT: sltiu $1, $4, 7 ; PIC-MIPS32R6-NEXT: beqz $1, $BB0_6 ; PIC-MIPS32R6-NEXT: sw $4, 4($sp) -; PIC-MIPS32R6-NEXT: $BB0_1: # %entry +; PIC-MIPS32R6-NEXT: # %bb.1: # %entry ; PIC-MIPS32R6-NEXT: sll $1, $4, 2 ; PIC-MIPS32R6-NEXT: lw $3, %got($JTI0_0)($2) ; PIC-MIPS32R6-NEXT: addu $1, $1, $3 @@ -476,7 +476,7 @@ define ptr @_Z3fooi(i32 signext %Letter) { ; PIC-MIPS64R2-NEXT: sltiu $1, $3, 7 ; PIC-MIPS64R2-NEXT: beqz $1, .LBB0_6 ; PIC-MIPS64R2-NEXT: sw $4, 4($sp) -; PIC-MIPS64R2-NEXT: .LBB0_1: # %entry +; PIC-MIPS64R2-NEXT: # %bb.1: # %entry ; PIC-MIPS64R2-NEXT: dsll $1, $3, 3 ; PIC-MIPS64R2-NEXT: ld $3, %got_page(.LJTI0_0)($2) ; PIC-MIPS64R2-NEXT: daddu $1, $1, $3 @@ -539,7 +539,7 @@ define ptr @_Z3fooi(i32 signext %Letter) { ; PIC-MIPS64R6-NEXT: sltiu $1, $3, 7 ; PIC-MIPS64R6-NEXT: beqz $1, .LBB0_6 ; PIC-MIPS64R6-NEXT: sw $4, 4($sp) -; PIC-MIPS64R6-NEXT: .LBB0_1: # %entry +; PIC-MIPS64R6-NEXT: # %bb.1: # %entry ; PIC-MIPS64R6-NEXT: dsll $1, $3, 3 ; PIC-MIPS64R6-NEXT: ld $3, %got_page(.LJTI0_0)($2) ; PIC-MIPS64R6-NEXT: daddu $1, $1, $3 diff --git a/llvm/test/CodeGen/Mips/jump-table-mul.ll b/llvm/test/CodeGen/Mips/jump-table-mul.ll index 22f41f53d154..cca6080a0754 100644 --- a/llvm/test/CodeGen/Mips/jump-table-mul.ll +++ b/llvm/test/CodeGen/Mips/jump-table-mul.ll @@ -10,7 +10,7 @@ define i64 @test(i64 %arg) { ; CHECK-NEXT: sltiu $1, $4, 11 ; CHECK-NEXT: beqz $1, .LBB0_4 ; CHECK-NEXT: nop -; CHECK-NEXT: .LBB0_1: # %entry +; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: daddiu $1, $2, %lo(%neg(%gp_rel(test))) ; CHECK-NEXT: dsll $2, $4, 3 ; CHECK-NEXT: ld $3, %got_page(.LJTI0_0)($1) diff --git a/llvm/test/CodeGen/Mips/pseudo-jump-fill.ll b/llvm/test/CodeGen/Mips/pseudo-jump-fill.ll index afb79e55f4f9..5d7cdbc0b69e 100644 --- a/llvm/test/CodeGen/Mips/pseudo-jump-fill.ll +++ b/llvm/test/CodeGen/Mips/pseudo-jump-fill.ll @@ -14,7 +14,7 @@ define i32 @test(i32 signext %x, i32 signext %c) { ; CHECK-NEXT: sltiu $1, $5, 4 ; CHECK-NEXT: beqz $1, $BB0_6 ; CHECK-NEXT: addu $3, $2, $25 -; CHECK-NEXT: $BB0_1: # %entry +; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: li16 $2, 0 ; CHECK-NEXT: sll16 $5, $5, 2 ; CHECK-NEXT: lw $6, %got($JTI0_0)($3) -- GitLab From cca49663a56d90f6773f140269940d606aa61430 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 6 Feb 2024 09:38:25 -0800 Subject: [PATCH 094/266] [FastISel][X86] Use getTypeForExtReturn in GetReturnInfo. (#80803) The comment and code here seems to match getTypeForExtReturn. The history shows that at the time this code was added, similar code existed in SelectionDAGBuilder. SelectionDAGBuiler code has since been refactored into getTypeForExtReturn. This patch makes FastISel match SelectionDAGBuilder. The test changes are because X86 has customization of getTypeForExtReturn. So now we only extend returns to i8. Stumbled onto this difference by accident. --- llvm/lib/CodeGen/TargetLoweringBase.cpp | 11 +- llvm/lib/Target/X86/X86FastISel.cpp | 13 +- .../X86/avx512-intrinsics-fast-isel.ll | 24 +-- .../X86/avx512bwvl-intrinsics-fast-isel.ll | 36 ++-- .../X86/avx512vl-intrinsics-fast-isel.ll | 48 +++--- llvm/test/CodeGen/X86/fast-isel-fcmp.ll | 155 ++++-------------- llvm/test/CodeGen/X86/fast-isel-ret-ext.ll | 2 +- .../X86/keylocker-intrinsics-fast-isel.ll | 16 -- llvm/test/CodeGen/X86/xaluo.ll | 67 ++------ llvm/test/CodeGen/X86/xmulo.ll | 63 +++---- llvm/test/DebugInfo/X86/convert-debugloc.ll | 2 +- 11 files changed, 140 insertions(+), 297 deletions(-) diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp index fe7bed760572..16cd14ba3de9 100644 --- a/llvm/lib/CodeGen/TargetLoweringBase.cpp +++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp @@ -1738,15 +1738,8 @@ void llvm::GetReturnInfo(CallingConv::ID CC, Type *ReturnType, else if (attr.hasRetAttr(Attribute::ZExt)) ExtendKind = ISD::ZERO_EXTEND; - // FIXME: C calling convention requires the return type to be promoted to - // at least 32-bit. But this is not necessary for non-C calling - // conventions. The frontend should mark functions whose return values - // require promoting with signext or zeroext attributes. - if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { - MVT MinVT = TLI.getRegisterType(MVT::i32); - if (VT.bitsLT(MinVT)) - VT = MinVT; - } + if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) + VT = TLI.getTypeForExtReturn(ReturnType->getContext(), VT, ExtendKind); unsigned NumParts = TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT); diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp index 1ce1e6f6a563..9368de62817b 100644 --- a/llvm/lib/Target/X86/X86FastISel.cpp +++ b/llvm/lib/Target/X86/X86FastISel.cpp @@ -1250,19 +1250,18 @@ bool X86FastISel::X86SelectRet(const Instruction *I) { if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) return false; - assert(DstVT == MVT::i32 && "X86 should always ext to i32"); - if (SrcVT == MVT::i1) { if (Outs[0].Flags.isSExt()) return false; - // TODO SrcReg = fastEmitZExtFromI1(MVT::i8, SrcReg); SrcVT = MVT::i8; } - unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND : - ISD::SIGN_EXTEND; - // TODO - SrcReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, SrcReg); + if (SrcVT != DstVT) { + unsigned Op = + Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND; + SrcReg = + fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, SrcReg); + } } // Make the copy. diff --git a/llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll index 780abc9f9dc4..1ca870add95b 100644 --- a/llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll +++ b/llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll @@ -21,7 +21,7 @@ define zeroext i16 @test_mm512_kunpackb(<8 x i64> %__A, <8 x i64> %__B, <8 x i64 ; X86-NEXT: kunpckbw %k0, %k1, %k1 ; X86-NEXT: vpcmpneqd 72(%ebp), %zmm3, %k0 {%k1} ; X86-NEXT: kmovw %k0, %eax -; X86-NEXT: movzwl %ax, %eax +; X86-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NEXT: movl %ebp, %esp ; X86-NEXT: popl %ebp ; X86-NEXT: .cfi_def_cfa %esp, 4 @@ -35,7 +35,7 @@ define zeroext i16 @test_mm512_kunpackb(<8 x i64> %__A, <8 x i64> %__B, <8 x i64 ; X64-NEXT: kunpckbw %k0, %k1, %k1 ; X64-NEXT: vpcmpneqd %zmm5, %zmm4, %k0 {%k1} ; X64-NEXT: kmovw %k0, %eax -; X64-NEXT: movzwl %ax, %eax +; X64-NEXT: # kill: def $ax killed $ax killed $eax ; X64-NEXT: vzeroupper ; X64-NEXT: retq entry: @@ -367,7 +367,7 @@ define zeroext i16 @test_mm512_testn_epi32_mask(<8 x i64> %__A, <8 x i64> %__B) ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestnmd %zmm0, %zmm1, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: movzwl %ax, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: ret{{[l|q]}} entry: @@ -385,7 +385,7 @@ define zeroext i16 @test_mm512_mask_testn_epi32_mask(i16 zeroext %__U, <8 x i64> ; X86-NEXT: kmovw %eax, %k1 ; X86-NEXT: vptestnmd %zmm0, %zmm1, %k0 {%k1} ; X86-NEXT: kmovw %k0, %eax -; X86-NEXT: movzwl %ax, %eax +; X86-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NEXT: vzeroupper ; X86-NEXT: retl ; @@ -394,7 +394,7 @@ define zeroext i16 @test_mm512_mask_testn_epi32_mask(i16 zeroext %__U, <8 x i64> ; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: vptestnmd %zmm0, %zmm1, %k0 {%k1} ; X64-NEXT: kmovw %k0, %eax -; X64-NEXT: movzwl %ax, %eax +; X64-NEXT: # kill: def $ax killed $ax killed $eax ; X64-NEXT: vzeroupper ; X64-NEXT: retq entry: @@ -412,7 +412,7 @@ define zeroext i8 @test_mm512_testn_epi64_mask(<8 x i64> %__A, <8 x i64> %__B) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestnmq %zmm0, %zmm1, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: movzbl %al, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: ret{{[l|q]}} entry: @@ -429,7 +429,7 @@ define zeroext i8 @test_mm512_mask_testn_epi64_mask(i8 zeroext %__U, <8 x i64> % ; X86-NEXT: kmovw %eax, %k1 ; X86-NEXT: vptestnmq %zmm0, %zmm1, %k0 {%k1} ; X86-NEXT: kmovw %k0, %eax -; X86-NEXT: movzbl %al, %eax +; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: vzeroupper ; X86-NEXT: retl ; @@ -438,7 +438,7 @@ define zeroext i8 @test_mm512_mask_testn_epi64_mask(i8 zeroext %__U, <8 x i64> % ; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: vptestnmq %zmm0, %zmm1, %k0 {%k1} ; X64-NEXT: kmovw %k0, %eax -; X64-NEXT: movzbl %al, %eax +; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: vzeroupper ; X64-NEXT: retq entry: @@ -457,7 +457,7 @@ define zeroext i16 @test_mm512_mask_test_epi32_mask(i16 zeroext %__U, <8 x i64> ; X86-NEXT: kmovw %eax, %k1 ; X86-NEXT: vptestmd %zmm0, %zmm1, %k0 {%k1} ; X86-NEXT: kmovw %k0, %eax -; X86-NEXT: movzwl %ax, %eax +; X86-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NEXT: vzeroupper ; X86-NEXT: retl ; @@ -466,7 +466,7 @@ define zeroext i16 @test_mm512_mask_test_epi32_mask(i16 zeroext %__U, <8 x i64> ; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: vptestmd %zmm0, %zmm1, %k0 {%k1} ; X64-NEXT: kmovw %k0, %eax -; X64-NEXT: movzwl %ax, %eax +; X64-NEXT: # kill: def $ax killed $ax killed $eax ; X64-NEXT: vzeroupper ; X64-NEXT: retq entry: @@ -486,7 +486,7 @@ define zeroext i8 @test_mm512_mask_test_epi64_mask(i8 zeroext %__U, <8 x i64> %_ ; X86-NEXT: kmovw %eax, %k1 ; X86-NEXT: vptestmq %zmm0, %zmm1, %k0 {%k1} ; X86-NEXT: kmovw %k0, %eax -; X86-NEXT: movzbl %al, %eax +; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: vzeroupper ; X86-NEXT: retl ; @@ -495,7 +495,7 @@ define zeroext i8 @test_mm512_mask_test_epi64_mask(i8 zeroext %__U, <8 x i64> %_ ; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: vptestmq %zmm0, %zmm1, %k0 {%k1} ; X64-NEXT: kmovw %k0, %eax -; X64-NEXT: movzbl %al, %eax +; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: vzeroupper ; X64-NEXT: retq entry: diff --git a/llvm/test/CodeGen/X86/avx512bwvl-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/avx512bwvl-intrinsics-fast-isel.ll index a32b84986e89..00729262473d 100644 --- a/llvm/test/CodeGen/X86/avx512bwvl-intrinsics-fast-isel.ll +++ b/llvm/test/CodeGen/X86/avx512bwvl-intrinsics-fast-isel.ll @@ -9,7 +9,7 @@ define zeroext i16 @test_mm_test_epi8_mask(<2 x i64> %__A, <2 x i64> %__B) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestmb %xmm0, %xmm1, %k0 ; CHECK-NEXT: kmovd %k0, %eax -; CHECK-NEXT: movzwl %ax, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax ; CHECK-NEXT: ret{{[l|q]}} entry: %and.i.i = and <2 x i64> %__B, %__A @@ -25,7 +25,7 @@ define zeroext i16 @test_mm_mask_test_epi8_mask(i16 zeroext %__U, <2 x i64> %__A ; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 ; X86-NEXT: vptestmb %xmm0, %xmm1, %k0 {%k1} ; X86-NEXT: kmovd %k0, %eax -; X86-NEXT: movzwl %ax, %eax +; X86-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NEXT: retl ; ; X64-LABEL: test_mm_mask_test_epi8_mask: @@ -33,7 +33,7 @@ define zeroext i16 @test_mm_mask_test_epi8_mask(i16 zeroext %__U, <2 x i64> %__A ; X64-NEXT: kmovd %edi, %k1 ; X64-NEXT: vptestmb %xmm0, %xmm1, %k0 {%k1} ; X64-NEXT: kmovd %k0, %eax -; X64-NEXT: movzwl %ax, %eax +; X64-NEXT: # kill: def $ax killed $ax killed $eax ; X64-NEXT: retq entry: %and.i.i = and <2 x i64> %__B, %__A @@ -91,7 +91,7 @@ define zeroext i8 @test_mm_test_epi16_mask(<2 x i64> %__A, <2 x i64> %__B) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestmw %xmm0, %xmm1, %k0 ; CHECK-NEXT: kmovd %k0, %eax -; CHECK-NEXT: movzbl %al, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: ret{{[l|q]}} entry: %and.i.i = and <2 x i64> %__B, %__A @@ -108,7 +108,7 @@ define zeroext i8 @test_mm_mask_test_epi16_mask(i8 zeroext %__U, <2 x i64> %__A, ; X86-NEXT: kmovd %eax, %k1 ; X86-NEXT: vptestmw %xmm0, %xmm1, %k0 {%k1} ; X86-NEXT: kmovd %k0, %eax -; X86-NEXT: movzbl %al, %eax +; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: retl ; ; X64-LABEL: test_mm_mask_test_epi16_mask: @@ -116,7 +116,7 @@ define zeroext i8 @test_mm_mask_test_epi16_mask(i8 zeroext %__U, <2 x i64> %__A, ; X64-NEXT: kmovd %edi, %k1 ; X64-NEXT: vptestmw %xmm0, %xmm1, %k0 {%k1} ; X64-NEXT: kmovd %k0, %eax -; X64-NEXT: movzbl %al, %eax +; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq entry: %and.i.i = and <2 x i64> %__B, %__A @@ -133,7 +133,7 @@ define zeroext i16 @test_mm256_test_epi16_mask(<4 x i64> %__A, <4 x i64> %__B) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestmw %ymm0, %ymm1, %k0 ; CHECK-NEXT: kmovd %k0, %eax -; CHECK-NEXT: movzwl %ax, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: ret{{[l|q]}} entry: @@ -150,7 +150,7 @@ define zeroext i16 @test_mm256_mask_test_epi16_mask(i16 zeroext %__U, <4 x i64> ; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 ; X86-NEXT: vptestmw %ymm0, %ymm1, %k0 {%k1} ; X86-NEXT: kmovd %k0, %eax -; X86-NEXT: movzwl %ax, %eax +; X86-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NEXT: vzeroupper ; X86-NEXT: retl ; @@ -159,7 +159,7 @@ define zeroext i16 @test_mm256_mask_test_epi16_mask(i16 zeroext %__U, <4 x i64> ; X64-NEXT: kmovd %edi, %k1 ; X64-NEXT: vptestmw %ymm0, %ymm1, %k0 {%k1} ; X64-NEXT: kmovd %k0, %eax -; X64-NEXT: movzwl %ax, %eax +; X64-NEXT: # kill: def $ax killed $ax killed $eax ; X64-NEXT: vzeroupper ; X64-NEXT: retq entry: @@ -177,7 +177,7 @@ define zeroext i16 @test_mm_testn_epi8_mask(<2 x i64> %__A, <2 x i64> %__B) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestnmb %xmm0, %xmm1, %k0 ; CHECK-NEXT: kmovd %k0, %eax -; CHECK-NEXT: movzwl %ax, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax ; CHECK-NEXT: ret{{[l|q]}} entry: %and.i.i = and <2 x i64> %__B, %__A @@ -193,7 +193,7 @@ define zeroext i16 @test_mm_mask_testn_epi8_mask(i16 zeroext %__U, <2 x i64> %__ ; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 ; X86-NEXT: vptestnmb %xmm0, %xmm1, %k0 {%k1} ; X86-NEXT: kmovd %k0, %eax -; X86-NEXT: movzwl %ax, %eax +; X86-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NEXT: retl ; ; X64-LABEL: test_mm_mask_testn_epi8_mask: @@ -201,7 +201,7 @@ define zeroext i16 @test_mm_mask_testn_epi8_mask(i16 zeroext %__U, <2 x i64> %__ ; X64-NEXT: kmovd %edi, %k1 ; X64-NEXT: vptestnmb %xmm0, %xmm1, %k0 {%k1} ; X64-NEXT: kmovd %k0, %eax -; X64-NEXT: movzwl %ax, %eax +; X64-NEXT: # kill: def $ax killed $ax killed $eax ; X64-NEXT: retq entry: %and.i.i = and <2 x i64> %__B, %__A @@ -259,7 +259,7 @@ define zeroext i8 @test_mm_testn_epi16_mask(<2 x i64> %__A, <2 x i64> %__B) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestnmw %xmm0, %xmm1, %k0 ; CHECK-NEXT: kmovd %k0, %eax -; CHECK-NEXT: movzbl %al, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: ret{{[l|q]}} entry: %and.i.i = and <2 x i64> %__B, %__A @@ -276,7 +276,7 @@ define zeroext i8 @test_mm_mask_testn_epi16_mask(i8 zeroext %__U, <2 x i64> %__A ; X86-NEXT: kmovd %eax, %k1 ; X86-NEXT: vptestnmw %xmm0, %xmm1, %k0 {%k1} ; X86-NEXT: kmovd %k0, %eax -; X86-NEXT: movzbl %al, %eax +; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: retl ; ; X64-LABEL: test_mm_mask_testn_epi16_mask: @@ -284,7 +284,7 @@ define zeroext i8 @test_mm_mask_testn_epi16_mask(i8 zeroext %__U, <2 x i64> %__A ; X64-NEXT: kmovd %edi, %k1 ; X64-NEXT: vptestnmw %xmm0, %xmm1, %k0 {%k1} ; X64-NEXT: kmovd %k0, %eax -; X64-NEXT: movzbl %al, %eax +; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq entry: %and.i.i = and <2 x i64> %__B, %__A @@ -301,7 +301,7 @@ define zeroext i16 @test_mm256_testn_epi16_mask(<4 x i64> %__A, <4 x i64> %__B) ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestnmw %ymm0, %ymm1, %k0 ; CHECK-NEXT: kmovd %k0, %eax -; CHECK-NEXT: movzwl %ax, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: ret{{[l|q]}} entry: @@ -318,7 +318,7 @@ define zeroext i16 @test_mm256_mask_testn_epi16_mask(i16 zeroext %__U, <4 x i64> ; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 ; X86-NEXT: vptestnmw %ymm0, %ymm1, %k0 {%k1} ; X86-NEXT: kmovd %k0, %eax -; X86-NEXT: movzwl %ax, %eax +; X86-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NEXT: vzeroupper ; X86-NEXT: retl ; @@ -327,7 +327,7 @@ define zeroext i16 @test_mm256_mask_testn_epi16_mask(i16 zeroext %__U, <4 x i64> ; X64-NEXT: kmovd %edi, %k1 ; X64-NEXT: vptestnmw %ymm0, %ymm1, %k0 {%k1} ; X64-NEXT: kmovd %k0, %eax -; X64-NEXT: movzwl %ax, %eax +; X64-NEXT: # kill: def $ax killed $ax killed $eax ; X64-NEXT: vzeroupper ; X64-NEXT: retq entry: diff --git a/llvm/test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll index 173e2bad8ace..06e7096e430b 100644 --- a/llvm/test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll +++ b/llvm/test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll @@ -1547,7 +1547,7 @@ define zeroext i8 @test_mm_test_epi32_mask(<2 x i64> %__A, <2 x i64> %__B) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestmd %xmm0, %xmm1, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: movzbl %al, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: ret{{[l|q]}} entry: %and.i.i = and <2 x i64> %__B, %__A @@ -1565,7 +1565,7 @@ define zeroext i8 @test_mm_mask_test_epi32_mask(i8 zeroext %__U, <2 x i64> %__A, ; X86-NEXT: kmovw %eax, %k1 ; X86-NEXT: vptestmd %xmm0, %xmm1, %k0 {%k1} ; X86-NEXT: kmovw %k0, %eax -; X86-NEXT: movzbl %al, %eax +; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: retl ; ; X64-LABEL: test_mm_mask_test_epi32_mask: @@ -1573,7 +1573,7 @@ define zeroext i8 @test_mm_mask_test_epi32_mask(i8 zeroext %__U, <2 x i64> %__A, ; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: vptestmd %xmm0, %xmm1, %k0 {%k1} ; X64-NEXT: kmovw %k0, %eax -; X64-NEXT: movzbl %al, %eax +; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq entry: %and.i.i = and <2 x i64> %__B, %__A @@ -1592,7 +1592,7 @@ define zeroext i8 @test_mm256_test_epi32_mask(<4 x i64> %__A, <4 x i64> %__B) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestmd %ymm0, %ymm1, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: movzbl %al, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: ret{{[l|q]}} entry: @@ -1610,7 +1610,7 @@ define zeroext i8 @test_mm256_mask_test_epi32_mask(i8 zeroext %__U, <4 x i64> %_ ; X86-NEXT: kmovw %eax, %k1 ; X86-NEXT: vptestmd %ymm0, %ymm1, %k0 {%k1} ; X86-NEXT: kmovw %k0, %eax -; X86-NEXT: movzbl %al, %eax +; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: vzeroupper ; X86-NEXT: retl ; @@ -1619,7 +1619,7 @@ define zeroext i8 @test_mm256_mask_test_epi32_mask(i8 zeroext %__U, <4 x i64> %_ ; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: vptestmd %ymm0, %ymm1, %k0 {%k1} ; X64-NEXT: kmovw %k0, %eax -; X64-NEXT: movzbl %al, %eax +; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: vzeroupper ; X64-NEXT: retq entry: @@ -1637,7 +1637,7 @@ define zeroext i8 @test_mm_test_epi64_mask(<2 x i64> %__A, <2 x i64> %__B) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestmq %xmm0, %xmm1, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: movzbl %al, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: ret{{[l|q]}} entry: %and.i.i = and <2 x i64> %__B, %__A @@ -1654,7 +1654,7 @@ define zeroext i8 @test_mm_mask_test_epi64_mask(i8 zeroext %__U, <2 x i64> %__A, ; X86-NEXT: kmovw %eax, %k1 ; X86-NEXT: vptestmq %xmm0, %xmm1, %k0 {%k1} ; X86-NEXT: kmovw %k0, %eax -; X86-NEXT: movzbl %al, %eax +; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: retl ; ; X64-LABEL: test_mm_mask_test_epi64_mask: @@ -1662,7 +1662,7 @@ define zeroext i8 @test_mm_mask_test_epi64_mask(i8 zeroext %__U, <2 x i64> %__A, ; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: vptestmq %xmm0, %xmm1, %k0 {%k1} ; X64-NEXT: kmovw %k0, %eax -; X64-NEXT: movzbl %al, %eax +; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq entry: %and.i.i = and <2 x i64> %__B, %__A @@ -1680,7 +1680,7 @@ define zeroext i8 @test_mm256_test_epi64_mask(<4 x i64> %__A, <4 x i64> %__B) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestmq %ymm0, %ymm1, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: movzbl %al, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: ret{{[l|q]}} entry: @@ -1698,7 +1698,7 @@ define zeroext i8 @test_mm256_mask_test_epi64_mask(i8 zeroext %__U, <4 x i64> %_ ; X86-NEXT: kmovw %eax, %k1 ; X86-NEXT: vptestmq %ymm0, %ymm1, %k0 {%k1} ; X86-NEXT: kmovw %k0, %eax -; X86-NEXT: movzbl %al, %eax +; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: vzeroupper ; X86-NEXT: retl ; @@ -1707,7 +1707,7 @@ define zeroext i8 @test_mm256_mask_test_epi64_mask(i8 zeroext %__U, <4 x i64> %_ ; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: vptestmq %ymm0, %ymm1, %k0 {%k1} ; X64-NEXT: kmovw %k0, %eax -; X64-NEXT: movzbl %al, %eax +; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: vzeroupper ; X64-NEXT: retq entry: @@ -1726,7 +1726,7 @@ define zeroext i8 @test_mm_testn_epi32_mask(<2 x i64> %__A, <2 x i64> %__B) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestnmd %xmm0, %xmm1, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: movzbl %al, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: ret{{[l|q]}} entry: %and.i.i = and <2 x i64> %__B, %__A @@ -1744,7 +1744,7 @@ define zeroext i8 @test_mm_mask_testn_epi32_mask(i8 zeroext %__U, <2 x i64> %__A ; X86-NEXT: kmovw %eax, %k1 ; X86-NEXT: vptestnmd %xmm0, %xmm1, %k0 {%k1} ; X86-NEXT: kmovw %k0, %eax -; X86-NEXT: movzbl %al, %eax +; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: retl ; ; X64-LABEL: test_mm_mask_testn_epi32_mask: @@ -1752,7 +1752,7 @@ define zeroext i8 @test_mm_mask_testn_epi32_mask(i8 zeroext %__U, <2 x i64> %__A ; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: vptestnmd %xmm0, %xmm1, %k0 {%k1} ; X64-NEXT: kmovw %k0, %eax -; X64-NEXT: movzbl %al, %eax +; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq entry: %and.i.i = and <2 x i64> %__B, %__A @@ -1771,7 +1771,7 @@ define zeroext i8 @test_mm256_testn_epi32_mask(<4 x i64> %__A, <4 x i64> %__B) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestnmd %ymm0, %ymm1, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: movzbl %al, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: ret{{[l|q]}} entry: @@ -1789,7 +1789,7 @@ define zeroext i8 @test_mm256_mask_testn_epi32_mask(i8 zeroext %__U, <4 x i64> % ; X86-NEXT: kmovw %eax, %k1 ; X86-NEXT: vptestnmd %ymm0, %ymm1, %k0 {%k1} ; X86-NEXT: kmovw %k0, %eax -; X86-NEXT: movzbl %al, %eax +; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: vzeroupper ; X86-NEXT: retl ; @@ -1798,7 +1798,7 @@ define zeroext i8 @test_mm256_mask_testn_epi32_mask(i8 zeroext %__U, <4 x i64> % ; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: vptestnmd %ymm0, %ymm1, %k0 {%k1} ; X64-NEXT: kmovw %k0, %eax -; X64-NEXT: movzbl %al, %eax +; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: vzeroupper ; X64-NEXT: retq entry: @@ -1816,7 +1816,7 @@ define zeroext i8 @test_mm_testn_epi64_mask(<2 x i64> %__A, <2 x i64> %__B) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestnmq %xmm0, %xmm1, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: movzbl %al, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: ret{{[l|q]}} entry: %and.i.i = and <2 x i64> %__B, %__A @@ -1833,7 +1833,7 @@ define zeroext i8 @test_mm_mask_testn_epi64_mask(i8 zeroext %__U, <2 x i64> %__A ; X86-NEXT: kmovw %eax, %k1 ; X86-NEXT: vptestnmq %xmm0, %xmm1, %k0 {%k1} ; X86-NEXT: kmovw %k0, %eax -; X86-NEXT: movzbl %al, %eax +; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: retl ; ; X64-LABEL: test_mm_mask_testn_epi64_mask: @@ -1841,7 +1841,7 @@ define zeroext i8 @test_mm_mask_testn_epi64_mask(i8 zeroext %__U, <2 x i64> %__A ; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: vptestnmq %xmm0, %xmm1, %k0 {%k1} ; X64-NEXT: kmovw %k0, %eax -; X64-NEXT: movzbl %al, %eax +; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq entry: %and.i.i = and <2 x i64> %__B, %__A @@ -1859,7 +1859,7 @@ define zeroext i8 @test_mm256_testn_epi64_mask(<4 x i64> %__A, <4 x i64> %__B) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestnmq %ymm0, %ymm1, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: movzbl %al, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: ret{{[l|q]}} entry: @@ -1877,7 +1877,7 @@ define zeroext i8 @test_mm256_mask_testn_epi64_mask(i8 zeroext %__U, <4 x i64> % ; X86-NEXT: kmovw %eax, %k1 ; X86-NEXT: vptestnmq %ymm0, %ymm1, %k0 {%k1} ; X86-NEXT: kmovw %k0, %eax -; X86-NEXT: movzbl %al, %eax +; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: vzeroupper ; X86-NEXT: retl ; @@ -1886,7 +1886,7 @@ define zeroext i8 @test_mm256_mask_testn_epi64_mask(i8 zeroext %__U, <4 x i64> % ; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: vptestnmq %ymm0, %ymm1, %k0 {%k1} ; X64-NEXT: kmovw %k0, %eax -; X64-NEXT: movzbl %al, %eax +; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: vzeroupper ; X64-NEXT: retq entry: diff --git a/llvm/test/CodeGen/X86/fast-isel-fcmp.ll b/llvm/test/CodeGen/X86/fast-isel-fcmp.ll index c6ad2171aa89..b9ef3154cd1c 100644 --- a/llvm/test/CodeGen/X86/fast-isel-fcmp.ll +++ b/llvm/test/CodeGen/X86/fast-isel-fcmp.ll @@ -16,21 +16,19 @@ define zeroext i1 @fcmp_oeq(float %x, float %y) { ; FAST_NOAVX-LABEL: fcmp_oeq: ; FAST_NOAVX: ## %bb.0: ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 -; FAST_NOAVX-NEXT: sete %al -; FAST_NOAVX-NEXT: setnp %cl -; FAST_NOAVX-NEXT: andb %al, %cl -; FAST_NOAVX-NEXT: andb $1, %cl -; FAST_NOAVX-NEXT: movzbl %cl, %eax +; FAST_NOAVX-NEXT: sete %cl +; FAST_NOAVX-NEXT: setnp %al +; FAST_NOAVX-NEXT: andb %cl, %al +; FAST_NOAVX-NEXT: andb $1, %al ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_oeq: ; FAST_AVX: ## %bb.0: ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 -; FAST_AVX-NEXT: sete %al -; FAST_AVX-NEXT: setnp %cl -; FAST_AVX-NEXT: andb %al, %cl -; FAST_AVX-NEXT: andb $1, %cl -; FAST_AVX-NEXT: movzbl %cl, %eax +; FAST_AVX-NEXT: sete %cl +; FAST_AVX-NEXT: setnp %al +; FAST_AVX-NEXT: andb %cl, %al +; FAST_AVX-NEXT: andb $1, %al ; FAST_AVX-NEXT: retq %1 = fcmp oeq float %x, %y ret i1 %1 @@ -48,7 +46,6 @@ define zeroext i1 @fcmp_ogt(float %x, float %y) { ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 ; FAST_NOAVX-NEXT: seta %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ogt: @@ -56,7 +53,6 @@ define zeroext i1 @fcmp_ogt(float %x, float %y) { ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 ; FAST_AVX-NEXT: seta %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ogt float %x, %y ret i1 %1 @@ -74,7 +70,6 @@ define zeroext i1 @fcmp_oge(float %x, float %y) { ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 ; FAST_NOAVX-NEXT: setae %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_oge: @@ -82,7 +77,6 @@ define zeroext i1 @fcmp_oge(float %x, float %y) { ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 ; FAST_AVX-NEXT: setae %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp oge float %x, %y ret i1 %1 @@ -100,7 +94,6 @@ define zeroext i1 @fcmp_olt(float %x, float %y) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm1 ; FAST_NOAVX-NEXT: seta %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_olt: @@ -108,7 +101,6 @@ define zeroext i1 @fcmp_olt(float %x, float %y) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm1 ; FAST_AVX-NEXT: seta %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp olt float %x, %y ret i1 %1 @@ -126,7 +118,6 @@ define zeroext i1 @fcmp_ole(float %x, float %y) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm1 ; FAST_NOAVX-NEXT: setae %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ole: @@ -134,7 +125,6 @@ define zeroext i1 @fcmp_ole(float %x, float %y) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm1 ; FAST_AVX-NEXT: setae %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ole float %x, %y ret i1 %1 @@ -152,7 +142,6 @@ define zeroext i1 @fcmp_one(float %x, float %y) { ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 ; FAST_NOAVX-NEXT: setne %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_one: @@ -160,7 +149,6 @@ define zeroext i1 @fcmp_one(float %x, float %y) { ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 ; FAST_AVX-NEXT: setne %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp one float %x, %y ret i1 %1 @@ -178,7 +166,6 @@ define zeroext i1 @fcmp_ord(float %x, float %y) { ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 ; FAST_NOAVX-NEXT: setnp %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ord: @@ -186,7 +173,6 @@ define zeroext i1 @fcmp_ord(float %x, float %y) { ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 ; FAST_AVX-NEXT: setnp %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ord float %x, %y ret i1 %1 @@ -204,7 +190,6 @@ define zeroext i1 @fcmp_uno(float %x, float %y) { ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 ; FAST_NOAVX-NEXT: setp %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_uno: @@ -212,7 +197,6 @@ define zeroext i1 @fcmp_uno(float %x, float %y) { ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 ; FAST_AVX-NEXT: setp %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp uno float %x, %y ret i1 %1 @@ -230,7 +214,6 @@ define zeroext i1 @fcmp_ueq(float %x, float %y) { ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 ; FAST_NOAVX-NEXT: sete %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ueq: @@ -238,7 +221,6 @@ define zeroext i1 @fcmp_ueq(float %x, float %y) { ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 ; FAST_AVX-NEXT: sete %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ueq float %x, %y ret i1 %1 @@ -256,7 +238,6 @@ define zeroext i1 @fcmp_ugt(float %x, float %y) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm1 ; FAST_NOAVX-NEXT: setb %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ugt: @@ -264,7 +245,6 @@ define zeroext i1 @fcmp_ugt(float %x, float %y) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm1 ; FAST_AVX-NEXT: setb %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ugt float %x, %y ret i1 %1 @@ -282,7 +262,6 @@ define zeroext i1 @fcmp_uge(float %x, float %y) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm1 ; FAST_NOAVX-NEXT: setbe %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_uge: @@ -290,7 +269,6 @@ define zeroext i1 @fcmp_uge(float %x, float %y) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm1 ; FAST_AVX-NEXT: setbe %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp uge float %x, %y ret i1 %1 @@ -308,7 +286,6 @@ define zeroext i1 @fcmp_ult(float %x, float %y) { ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 ; FAST_NOAVX-NEXT: setb %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ult: @@ -316,7 +293,6 @@ define zeroext i1 @fcmp_ult(float %x, float %y) { ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 ; FAST_AVX-NEXT: setb %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ult float %x, %y ret i1 %1 @@ -334,7 +310,6 @@ define zeroext i1 @fcmp_ule(float %x, float %y) { ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 ; FAST_NOAVX-NEXT: setbe %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ule: @@ -342,7 +317,6 @@ define zeroext i1 @fcmp_ule(float %x, float %y) { ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 ; FAST_AVX-NEXT: setbe %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ule float %x, %y ret i1 %1 @@ -360,21 +334,19 @@ define zeroext i1 @fcmp_une(float %x, float %y) { ; FAST_NOAVX-LABEL: fcmp_une: ; FAST_NOAVX: ## %bb.0: ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 -; FAST_NOAVX-NEXT: setne %al -; FAST_NOAVX-NEXT: setp %cl -; FAST_NOAVX-NEXT: orb %al, %cl -; FAST_NOAVX-NEXT: andb $1, %cl -; FAST_NOAVX-NEXT: movzbl %cl, %eax +; FAST_NOAVX-NEXT: setne %cl +; FAST_NOAVX-NEXT: setp %al +; FAST_NOAVX-NEXT: orb %cl, %al +; FAST_NOAVX-NEXT: andb $1, %al ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_une: ; FAST_AVX: ## %bb.0: ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 -; FAST_AVX-NEXT: setne %al -; FAST_AVX-NEXT: setp %cl -; FAST_AVX-NEXT: orb %al, %cl -; FAST_AVX-NEXT: andb $1, %cl -; FAST_AVX-NEXT: movzbl %cl, %eax +; FAST_AVX-NEXT: setne %cl +; FAST_AVX-NEXT: setp %al +; FAST_AVX-NEXT: orb %cl, %al +; FAST_AVX-NEXT: andb $1, %al ; FAST_AVX-NEXT: retq %1 = fcmp une float %x, %y ret i1 %1 @@ -392,7 +364,6 @@ define zeroext i1 @icmp_eq(i32 %x, i32 %y) { ; FAST-NEXT: cmpl %esi, %edi ; FAST-NEXT: sete %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %1 = icmp eq i32 %x, %y ret i1 %1 @@ -410,7 +381,6 @@ define zeroext i1 @icmp_ne(i32 %x, i32 %y) { ; FAST-NEXT: cmpl %esi, %edi ; FAST-NEXT: setne %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %1 = icmp ne i32 %x, %y ret i1 %1 @@ -428,7 +398,6 @@ define zeroext i1 @icmp_ugt(i32 %x, i32 %y) { ; FAST-NEXT: cmpl %esi, %edi ; FAST-NEXT: seta %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %1 = icmp ugt i32 %x, %y ret i1 %1 @@ -446,7 +415,6 @@ define zeroext i1 @icmp_uge(i32 %x, i32 %y) { ; FAST-NEXT: cmpl %esi, %edi ; FAST-NEXT: setae %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %1 = icmp uge i32 %x, %y ret i1 %1 @@ -464,7 +432,6 @@ define zeroext i1 @icmp_ult(i32 %x, i32 %y) { ; FAST-NEXT: cmpl %esi, %edi ; FAST-NEXT: setb %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %1 = icmp ult i32 %x, %y ret i1 %1 @@ -482,7 +449,6 @@ define zeroext i1 @icmp_ule(i32 %x, i32 %y) { ; FAST-NEXT: cmpl %esi, %edi ; FAST-NEXT: setbe %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %1 = icmp ule i32 %x, %y ret i1 %1 @@ -500,7 +466,6 @@ define zeroext i1 @icmp_sgt(i32 %x, i32 %y) { ; FAST-NEXT: cmpl %esi, %edi ; FAST-NEXT: setg %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %1 = icmp sgt i32 %x, %y ret i1 %1 @@ -518,7 +483,6 @@ define zeroext i1 @icmp_sge(i32 %x, i32 %y) { ; FAST-NEXT: cmpl %esi, %edi ; FAST-NEXT: setge %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %1 = icmp sge i32 %x, %y ret i1 %1 @@ -536,7 +500,6 @@ define zeroext i1 @icmp_slt(i32 %x, i32 %y) { ; FAST-NEXT: cmpl %esi, %edi ; FAST-NEXT: setl %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %1 = icmp slt i32 %x, %y ret i1 %1 @@ -554,7 +517,6 @@ define zeroext i1 @icmp_sle(i32 %x, i32 %y) { ; FAST-NEXT: cmpl %esi, %edi ; FAST-NEXT: setle %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %1 = icmp sle i32 %x, %y ret i1 %1 @@ -573,7 +535,6 @@ define zeroext i1 @fcmp_oeq2(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm0 ; FAST_NOAVX-NEXT: setnp %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_oeq2: @@ -581,7 +542,6 @@ define zeroext i1 @fcmp_oeq2(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm0 ; FAST_AVX-NEXT: setnp %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp oeq float %x, %x ret i1 %1 @@ -601,22 +561,20 @@ define zeroext i1 @fcmp_oeq3(float %x) { ; FAST_NOAVX: ## %bb.0: ; FAST_NOAVX-NEXT: xorps %xmm1, %xmm1 ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 -; FAST_NOAVX-NEXT: sete %al -; FAST_NOAVX-NEXT: setnp %cl -; FAST_NOAVX-NEXT: andb %al, %cl -; FAST_NOAVX-NEXT: andb $1, %cl -; FAST_NOAVX-NEXT: movzbl %cl, %eax +; FAST_NOAVX-NEXT: sete %cl +; FAST_NOAVX-NEXT: setnp %al +; FAST_NOAVX-NEXT: andb %cl, %al +; FAST_NOAVX-NEXT: andb $1, %al ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_oeq3: ; FAST_AVX: ## %bb.0: ; FAST_AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 -; FAST_AVX-NEXT: sete %al -; FAST_AVX-NEXT: setnp %cl -; FAST_AVX-NEXT: andb %al, %cl -; FAST_AVX-NEXT: andb $1, %cl -; FAST_AVX-NEXT: movzbl %cl, %eax +; FAST_AVX-NEXT: sete %cl +; FAST_AVX-NEXT: setnp %al +; FAST_AVX-NEXT: andb %cl, %al +; FAST_AVX-NEXT: andb $1, %al ; FAST_AVX-NEXT: retq %1 = fcmp oeq float %x, 0.000000e+00 ret i1 %1 @@ -632,7 +590,7 @@ define zeroext i1 @fcmp_ogt2(float %x) { ; FAST: ## %bb.0: ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: ## kill: def $al killed $al killed $eax ; FAST-NEXT: retq %1 = fcmp ogt float %x, %x ret i1 %1 @@ -652,7 +610,6 @@ define zeroext i1 @fcmp_ogt3(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 ; FAST_NOAVX-NEXT: seta %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ogt3: @@ -661,7 +618,6 @@ define zeroext i1 @fcmp_ogt3(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 ; FAST_AVX-NEXT: seta %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ogt float %x, 0.000000e+00 ret i1 %1 @@ -679,7 +635,6 @@ define zeroext i1 @fcmp_oge2(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm0 ; FAST_NOAVX-NEXT: setnp %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_oge2: @@ -687,7 +642,6 @@ define zeroext i1 @fcmp_oge2(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm0 ; FAST_AVX-NEXT: setnp %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp oge float %x, %x ret i1 %1 @@ -707,7 +661,6 @@ define zeroext i1 @fcmp_oge3(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 ; FAST_NOAVX-NEXT: setae %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_oge3: @@ -716,7 +669,6 @@ define zeroext i1 @fcmp_oge3(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 ; FAST_AVX-NEXT: setae %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp oge float %x, 0.000000e+00 ret i1 %1 @@ -732,7 +684,7 @@ define zeroext i1 @fcmp_olt2(float %x) { ; FAST: ## %bb.0: ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: ## kill: def $al killed $al killed $eax ; FAST-NEXT: retq %1 = fcmp olt float %x, %x ret i1 %1 @@ -752,7 +704,6 @@ define zeroext i1 @fcmp_olt3(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm1 ; FAST_NOAVX-NEXT: seta %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_olt3: @@ -761,7 +712,6 @@ define zeroext i1 @fcmp_olt3(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm1 ; FAST_AVX-NEXT: seta %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp olt float %x, 0.000000e+00 ret i1 %1 @@ -779,7 +729,6 @@ define zeroext i1 @fcmp_ole2(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm0 ; FAST_NOAVX-NEXT: setnp %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ole2: @@ -787,7 +736,6 @@ define zeroext i1 @fcmp_ole2(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm0 ; FAST_AVX-NEXT: setnp %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ole float %x, %x ret i1 %1 @@ -807,7 +755,6 @@ define zeroext i1 @fcmp_ole3(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm1 ; FAST_NOAVX-NEXT: setae %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ole3: @@ -816,7 +763,6 @@ define zeroext i1 @fcmp_ole3(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm1 ; FAST_AVX-NEXT: setae %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ole float %x, 0.000000e+00 ret i1 %1 @@ -832,7 +778,7 @@ define zeroext i1 @fcmp_one2(float %x) { ; FAST: ## %bb.0: ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: ## kill: def $al killed $al killed $eax ; FAST-NEXT: retq %1 = fcmp one float %x, %x ret i1 %1 @@ -852,7 +798,6 @@ define zeroext i1 @fcmp_one3(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 ; FAST_NOAVX-NEXT: setne %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_one3: @@ -861,7 +806,6 @@ define zeroext i1 @fcmp_one3(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 ; FAST_AVX-NEXT: setne %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp one float %x, 0.000000e+00 ret i1 %1 @@ -879,7 +823,6 @@ define zeroext i1 @fcmp_ord2(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm0 ; FAST_NOAVX-NEXT: setnp %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ord2: @@ -887,7 +830,6 @@ define zeroext i1 @fcmp_ord2(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm0 ; FAST_AVX-NEXT: setnp %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ord float %x, %x ret i1 %1 @@ -905,7 +847,6 @@ define zeroext i1 @fcmp_ord3(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm0 ; FAST_NOAVX-NEXT: setnp %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ord3: @@ -913,7 +854,6 @@ define zeroext i1 @fcmp_ord3(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm0 ; FAST_AVX-NEXT: setnp %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ord float %x, 0.000000e+00 ret i1 %1 @@ -931,7 +871,6 @@ define zeroext i1 @fcmp_uno2(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm0 ; FAST_NOAVX-NEXT: setp %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_uno2: @@ -939,7 +878,6 @@ define zeroext i1 @fcmp_uno2(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm0 ; FAST_AVX-NEXT: setp %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp uno float %x, %x ret i1 %1 @@ -957,7 +895,6 @@ define zeroext i1 @fcmp_uno3(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm0 ; FAST_NOAVX-NEXT: setp %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_uno3: @@ -965,7 +902,6 @@ define zeroext i1 @fcmp_uno3(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm0 ; FAST_AVX-NEXT: setp %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp uno float %x, 0.000000e+00 ret i1 %1 @@ -981,7 +917,6 @@ define zeroext i1 @fcmp_ueq2(float %x) { ; FAST: ## %bb.0: ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %1 = fcmp ueq float %x, %x ret i1 %1 @@ -1001,7 +936,6 @@ define zeroext i1 @fcmp_ueq3(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 ; FAST_NOAVX-NEXT: sete %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ueq3: @@ -1010,7 +944,6 @@ define zeroext i1 @fcmp_ueq3(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 ; FAST_AVX-NEXT: sete %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ueq float %x, 0.000000e+00 ret i1 %1 @@ -1028,7 +961,6 @@ define zeroext i1 @fcmp_ugt2(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm0 ; FAST_NOAVX-NEXT: setp %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ugt2: @@ -1036,7 +968,6 @@ define zeroext i1 @fcmp_ugt2(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm0 ; FAST_AVX-NEXT: setp %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ugt float %x, %x ret i1 %1 @@ -1056,7 +987,6 @@ define zeroext i1 @fcmp_ugt3(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm1 ; FAST_NOAVX-NEXT: setb %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ugt3: @@ -1065,7 +995,6 @@ define zeroext i1 @fcmp_ugt3(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm1 ; FAST_AVX-NEXT: setb %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ugt float %x, 0.000000e+00 ret i1 %1 @@ -1081,7 +1010,6 @@ define zeroext i1 @fcmp_uge2(float %x) { ; FAST: ## %bb.0: ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %1 = fcmp uge float %x, %x ret i1 %1 @@ -1101,7 +1029,6 @@ define zeroext i1 @fcmp_uge3(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm1 ; FAST_NOAVX-NEXT: setbe %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_uge3: @@ -1110,7 +1037,6 @@ define zeroext i1 @fcmp_uge3(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm1 ; FAST_AVX-NEXT: setbe %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp uge float %x, 0.000000e+00 ret i1 %1 @@ -1128,7 +1054,6 @@ define zeroext i1 @fcmp_ult2(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm0 ; FAST_NOAVX-NEXT: setp %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ult2: @@ -1136,7 +1061,6 @@ define zeroext i1 @fcmp_ult2(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm0 ; FAST_AVX-NEXT: setp %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ult float %x, %x ret i1 %1 @@ -1156,7 +1080,6 @@ define zeroext i1 @fcmp_ult3(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 ; FAST_NOAVX-NEXT: setb %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ult3: @@ -1165,7 +1088,6 @@ define zeroext i1 @fcmp_ult3(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 ; FAST_AVX-NEXT: setb %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ult float %x, 0.000000e+00 ret i1 %1 @@ -1181,7 +1103,6 @@ define zeroext i1 @fcmp_ule2(float %x) { ; FAST: ## %bb.0: ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %1 = fcmp ule float %x, %x ret i1 %1 @@ -1201,7 +1122,6 @@ define zeroext i1 @fcmp_ule3(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 ; FAST_NOAVX-NEXT: setbe %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ule3: @@ -1210,7 +1130,6 @@ define zeroext i1 @fcmp_ule3(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 ; FAST_AVX-NEXT: setbe %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ule float %x, 0.000000e+00 ret i1 %1 @@ -1228,7 +1147,6 @@ define zeroext i1 @fcmp_une2(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm0 ; FAST_NOAVX-NEXT: setp %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_une2: @@ -1236,7 +1154,6 @@ define zeroext i1 @fcmp_une2(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm0 ; FAST_AVX-NEXT: setp %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp une float %x, %x ret i1 %1 @@ -1256,22 +1173,20 @@ define zeroext i1 @fcmp_une3(float %x) { ; FAST_NOAVX: ## %bb.0: ; FAST_NOAVX-NEXT: xorps %xmm1, %xmm1 ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 -; FAST_NOAVX-NEXT: setne %al -; FAST_NOAVX-NEXT: setp %cl -; FAST_NOAVX-NEXT: orb %al, %cl -; FAST_NOAVX-NEXT: andb $1, %cl -; FAST_NOAVX-NEXT: movzbl %cl, %eax +; FAST_NOAVX-NEXT: setne %cl +; FAST_NOAVX-NEXT: setp %al +; FAST_NOAVX-NEXT: orb %cl, %al +; FAST_NOAVX-NEXT: andb $1, %al ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_une3: ; FAST_AVX: ## %bb.0: ; FAST_AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 -; FAST_AVX-NEXT: setne %al -; FAST_AVX-NEXT: setp %cl -; FAST_AVX-NEXT: orb %al, %cl -; FAST_AVX-NEXT: andb $1, %cl -; FAST_AVX-NEXT: movzbl %cl, %eax +; FAST_AVX-NEXT: setne %cl +; FAST_AVX-NEXT: setp %al +; FAST_AVX-NEXT: orb %cl, %al +; FAST_AVX-NEXT: andb $1, %al ; FAST_AVX-NEXT: retq %1 = fcmp une float %x, 0.000000e+00 ret i1 %1 diff --git a/llvm/test/CodeGen/X86/fast-isel-ret-ext.ll b/llvm/test/CodeGen/X86/fast-isel-ret-ext.ll index cd3439fcddc5..0341694fe826 100644 --- a/llvm/test/CodeGen/X86/fast-isel-ret-ext.ll +++ b/llvm/test/CodeGen/X86/fast-isel-ret-ext.ll @@ -34,5 +34,5 @@ define zeroext i1 @test5(i32 %y) nounwind { ret i1 %conv ; CHECK-LABEL: test5: ; CHECK: andb $1 - ; CHECK: movzbl {{.*}}, %eax + ; CHECK-NEXT: ret } diff --git a/llvm/test/CodeGen/X86/keylocker-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/keylocker-intrinsics-fast-isel.ll index ae046be9a508..f91c4ad0e8e3 100644 --- a/llvm/test/CodeGen/X86/keylocker-intrinsics-fast-isel.ll +++ b/llvm/test/CodeGen/X86/keylocker-intrinsics-fast-isel.ll @@ -119,7 +119,6 @@ entry: define zeroext i8 @test_mm_aesenc256kl_u8(ptr %odata, <2 x i64> %idata, ptr %h) { ; CHECK-LABEL: test_mm_aesenc256kl_u8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: aesenc256kl (%rsi), %xmm0 ; CHECK-NEXT: sete %al ; CHECK-NEXT: movaps %xmm0, (%rdi) @@ -127,7 +126,6 @@ define zeroext i8 @test_mm_aesenc256kl_u8(ptr %odata, <2 x i64> %idata, ptr %h) ; ; EGPR-LABEL: test_mm_aesenc256kl_u8: ; EGPR: # %bb.0: # %entry -; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; EGPR-NEXT: aesenc256kl (%rsi), %xmm0 # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xde,0x06] ; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] ; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07] @@ -143,7 +141,6 @@ entry: define zeroext i8 @test_mm_aesdec256kl_u8(ptr %odata, <2 x i64> %idata, ptr %h) { ; CHECK-LABEL: test_mm_aesdec256kl_u8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: aesdec256kl (%rsi), %xmm0 ; CHECK-NEXT: sete %al ; CHECK-NEXT: movaps %xmm0, (%rdi) @@ -151,7 +148,6 @@ define zeroext i8 @test_mm_aesdec256kl_u8(ptr %odata, <2 x i64> %idata, ptr %h) ; ; EGPR-LABEL: test_mm_aesdec256kl_u8: ; EGPR: # %bb.0: # %entry -; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; EGPR-NEXT: aesdec256kl (%rsi), %xmm0 # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xdf,0x06] ; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] ; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07] @@ -167,7 +163,6 @@ entry: define zeroext i8 @test_mm_aesenc128kl_u8(ptr %odata, <2 x i64> %idata, ptr %h) { ; CHECK-LABEL: test_mm_aesenc128kl_u8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: aesenc128kl (%rsi), %xmm0 ; CHECK-NEXT: sete %al ; CHECK-NEXT: movaps %xmm0, (%rdi) @@ -175,7 +170,6 @@ define zeroext i8 @test_mm_aesenc128kl_u8(ptr %odata, <2 x i64> %idata, ptr %h) ; ; EGPR-LABEL: test_mm_aesenc128kl_u8: ; EGPR: # %bb.0: # %entry -; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; EGPR-NEXT: aesenc128kl (%rsi), %xmm0 # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xdc,0x06] ; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] ; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07] @@ -191,7 +185,6 @@ entry: define zeroext i8 @test_mm_aesdec128kl_u8(ptr %odata, <2 x i64> %idata, ptr %h) { ; CHECK-LABEL: test_mm_aesdec128kl_u8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: aesdec128kl (%rsi), %xmm0 ; CHECK-NEXT: sete %al ; CHECK-NEXT: movaps %xmm0, (%rdi) @@ -199,7 +192,6 @@ define zeroext i8 @test_mm_aesdec128kl_u8(ptr %odata, <2 x i64> %idata, ptr %h) ; ; EGPR-LABEL: test_mm_aesdec128kl_u8: ; EGPR: # %bb.0: # %entry -; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; EGPR-NEXT: aesdec128kl (%rsi), %xmm0 # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xdd,0x06] ; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] ; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07] @@ -223,7 +215,6 @@ define zeroext i8 @test__mm_aesencwide128kl_u8(ptr %odata, ptr %idata, ptr %h) { ; CHECK-NEXT: movaps 80(%rsi), %xmm5 ; CHECK-NEXT: movaps 96(%rsi), %xmm6 ; CHECK-NEXT: movaps 112(%rsi), %xmm7 -; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: aesencwide128kl (%rdx) ; CHECK-NEXT: sete %al ; CHECK-NEXT: movaps %xmm0, (%rdi) @@ -246,7 +237,6 @@ define zeroext i8 @test__mm_aesencwide128kl_u8(ptr %odata, ptr %idata, ptr %h) { ; EGPR-NEXT: movaps 80(%rsi), %xmm5 # encoding: [0x0f,0x28,0x6e,0x50] ; EGPR-NEXT: movaps 96(%rsi), %xmm6 # encoding: [0x0f,0x28,0x76,0x60] ; EGPR-NEXT: movaps 112(%rsi), %xmm7 # encoding: [0x0f,0x28,0x7e,0x70] -; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; EGPR-NEXT: aesencwide128kl (%rdx) # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xd8,0x02] ; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] ; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07] @@ -313,7 +303,6 @@ define zeroext i8 @test__mm_aesdecwide128kl_u8(ptr %odata, ptr %idata, ptr %h) { ; CHECK-NEXT: movaps 80(%rsi), %xmm5 ; CHECK-NEXT: movaps 96(%rsi), %xmm6 ; CHECK-NEXT: movaps 112(%rsi), %xmm7 -; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: aesdecwide128kl (%rdx) ; CHECK-NEXT: sete %al ; CHECK-NEXT: movaps %xmm0, (%rdi) @@ -336,7 +325,6 @@ define zeroext i8 @test__mm_aesdecwide128kl_u8(ptr %odata, ptr %idata, ptr %h) { ; EGPR-NEXT: movaps 80(%rsi), %xmm5 # encoding: [0x0f,0x28,0x6e,0x50] ; EGPR-NEXT: movaps 96(%rsi), %xmm6 # encoding: [0x0f,0x28,0x76,0x60] ; EGPR-NEXT: movaps 112(%rsi), %xmm7 # encoding: [0x0f,0x28,0x7e,0x70] -; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; EGPR-NEXT: aesdecwide128kl (%rdx) # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xd8,0x0a] ; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] ; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07] @@ -403,7 +391,6 @@ define zeroext i8 @test__mm_aesencwide256kl_u8(ptr %odata, ptr %idata, ptr %h) { ; CHECK-NEXT: movaps 80(%rsi), %xmm5 ; CHECK-NEXT: movaps 96(%rsi), %xmm6 ; CHECK-NEXT: movaps 112(%rsi), %xmm7 -; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: aesencwide256kl (%rdx) ; CHECK-NEXT: sete %al ; CHECK-NEXT: movaps %xmm0, (%rdi) @@ -426,7 +413,6 @@ define zeroext i8 @test__mm_aesencwide256kl_u8(ptr %odata, ptr %idata, ptr %h) { ; EGPR-NEXT: movaps 80(%rsi), %xmm5 # encoding: [0x0f,0x28,0x6e,0x50] ; EGPR-NEXT: movaps 96(%rsi), %xmm6 # encoding: [0x0f,0x28,0x76,0x60] ; EGPR-NEXT: movaps 112(%rsi), %xmm7 # encoding: [0x0f,0x28,0x7e,0x70] -; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; EGPR-NEXT: aesencwide256kl (%rdx) # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xd8,0x12] ; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] ; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07] @@ -493,7 +479,6 @@ define zeroext i8 @test__mm_aesdecwide256kl_u8(ptr %odata, ptr %idata, ptr %h) { ; CHECK-NEXT: movaps 80(%rsi), %xmm5 ; CHECK-NEXT: movaps 96(%rsi), %xmm6 ; CHECK-NEXT: movaps 112(%rsi), %xmm7 -; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: aesdecwide256kl (%rdx) ; CHECK-NEXT: sete %al ; CHECK-NEXT: movaps %xmm0, (%rdi) @@ -516,7 +501,6 @@ define zeroext i8 @test__mm_aesdecwide256kl_u8(ptr %odata, ptr %idata, ptr %h) { ; EGPR-NEXT: movaps 80(%rsi), %xmm5 # encoding: [0x0f,0x28,0x6e,0x50] ; EGPR-NEXT: movaps 96(%rsi), %xmm6 # encoding: [0x0f,0x28,0x76,0x60] ; EGPR-NEXT: movaps 112(%rsi), %xmm7 # encoding: [0x0f,0x28,0x7e,0x70] -; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; EGPR-NEXT: aesdecwide256kl (%rdx) # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xd8,0x1a] ; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] ; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07] diff --git a/llvm/test/CodeGen/X86/xaluo.ll b/llvm/test/CodeGen/X86/xaluo.ll index 5796e485f631..c2a8002c949c 100644 --- a/llvm/test/CodeGen/X86/xaluo.ll +++ b/llvm/test/CodeGen/X86/xaluo.ll @@ -21,7 +21,6 @@ define zeroext i1 @saddoi8(i8 signext %v1, i8 signext %v2, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movb %dil, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i8, i1} @llvm.sadd.with.overflow.i8(i8 %v1, i8 %v2) %val = extractvalue {i8, i1} %t, 0 @@ -44,7 +43,6 @@ define zeroext i1 @saddoi16(i16 %v1, i16 %v2, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movw %di, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i16, i1} @llvm.sadd.with.overflow.i16(i16 %v1, i16 %v2) %val = extractvalue {i16, i1} %t, 0 @@ -67,7 +65,6 @@ define zeroext i1 @saddoi32(i32 %v1, i32 %v2, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movl %edi, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2) %val = extractvalue {i32, i1} %t, 0 @@ -90,7 +87,6 @@ define zeroext i1 @saddoi64(i64 %v1, i64 %v2, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movq %rdi, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2) %val = extractvalue {i64, i1} %t, 0 @@ -114,7 +110,6 @@ define zeroext i1 @saddoinci8(i8 %v1, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movb %dil, (%rsi) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i8, i1} @llvm.sadd.with.overflow.i8(i8 %v1, i8 1) %val = extractvalue {i8, i1} %t, 0 @@ -137,7 +132,6 @@ define zeroext i1 @saddoinci16(i16 %v1, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movw %di, (%rsi) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i16, i1} @llvm.sadd.with.overflow.i16(i16 %v1, i16 1) %val = extractvalue {i16, i1} %t, 0 @@ -160,7 +154,6 @@ define zeroext i1 @saddoinci32(i32 %v1, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movl %edi, (%rsi) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 1) %val = extractvalue {i32, i1} %t, 0 @@ -183,7 +176,6 @@ define zeroext i1 @saddoinci64(i64 %v1, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movq %rdi, (%rsi) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 1) %val = extractvalue {i64, i1} %t, 0 @@ -207,7 +199,6 @@ define zeroext i1 @saddoi64imm1(i64 %v1, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movq %rdi, (%rsi) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 2, i64 %v1) %val = extractvalue {i64, i1} %t, 0 @@ -231,7 +222,6 @@ define zeroext i1 @saddoi64imm2(i64 %v1, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movq %rdi, (%rsi) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 -2147483648) %val = extractvalue {i64, i1} %t, 0 @@ -251,12 +241,11 @@ define zeroext i1 @saddoi64imm3(i64 %v1, ptr %res) { ; ; FAST-LABEL: saddoi64imm3: ; FAST: ## %bb.0: -; FAST-NEXT: movabsq $-21474836489, %rax ## imm = 0xFFFFFFFAFFFFFFF7 -; FAST-NEXT: addq %rdi, %rax -; FAST-NEXT: seto %cl -; FAST-NEXT: movq %rax, (%rsi) -; FAST-NEXT: andb $1, %cl -; FAST-NEXT: movzbl %cl, %eax +; FAST-NEXT: movabsq $-21474836489, %rcx ## imm = 0xFFFFFFFAFFFFFFF7 +; FAST-NEXT: addq %rdi, %rcx +; FAST-NEXT: seto %al +; FAST-NEXT: movq %rcx, (%rsi) +; FAST-NEXT: andb $1, %al ; FAST-NEXT: retq %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 -21474836489) %val = extractvalue {i64, i1} %t, 0 @@ -279,7 +268,6 @@ define zeroext i1 @saddoi64imm4(i64 %v1, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movq %rdi, (%rsi) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 2147483647) %val = extractvalue {i64, i1} %t, 0 @@ -298,12 +286,11 @@ define zeroext i1 @saddoi64imm5(i64 %v1, ptr %res) { ; ; FAST-LABEL: saddoi64imm5: ; FAST: ## %bb.0: -; FAST-NEXT: movl $2147483648, %eax ## imm = 0x80000000 -; FAST-NEXT: addq %rdi, %rax -; FAST-NEXT: seto %cl -; FAST-NEXT: movq %rax, (%rsi) -; FAST-NEXT: andb $1, %cl -; FAST-NEXT: movzbl %cl, %eax +; FAST-NEXT: movl $2147483648, %ecx ## imm = 0x80000000 +; FAST-NEXT: addq %rdi, %rcx +; FAST-NEXT: seto %al +; FAST-NEXT: movq %rcx, (%rsi) +; FAST-NEXT: andb $1, %al ; FAST-NEXT: retq %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 2147483648) %val = extractvalue {i64, i1} %t, 0 @@ -327,7 +314,6 @@ define zeroext i1 @uaddoi32(i32 %v1, i32 %v2, ptr %res) { ; FAST-NEXT: setb %al ; FAST-NEXT: movl %edi, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2) %val = extractvalue {i32, i1} %t, 0 @@ -350,7 +336,6 @@ define zeroext i1 @uaddoi64(i64 %v1, i64 %v2, ptr %res) { ; FAST-NEXT: setb %al ; FAST-NEXT: movq %rdi, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2) %val = extractvalue {i64, i1} %t, 0 @@ -374,7 +359,6 @@ define zeroext i1 @uaddoinci8(i8 %v1, ptr %res) { ; FAST-NEXT: setb %al ; FAST-NEXT: movb %dil, (%rsi) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i8, i1} @llvm.uadd.with.overflow.i8(i8 %v1, i8 1) %val = extractvalue {i8, i1} %t, 0 @@ -397,7 +381,6 @@ define zeroext i1 @uaddoinci16(i16 %v1, ptr %res) { ; FAST-NEXT: setb %al ; FAST-NEXT: movw %di, (%rsi) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i16, i1} @llvm.uadd.with.overflow.i16(i16 %v1, i16 1) %val = extractvalue {i16, i1} %t, 0 @@ -420,7 +403,6 @@ define zeroext i1 @uaddoinci32(i32 %v1, ptr %res) { ; FAST-NEXT: setb %al ; FAST-NEXT: movl %edi, (%rsi) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 1) %val = extractvalue {i32, i1} %t, 0 @@ -443,7 +425,6 @@ define zeroext i1 @uaddoinci64(i64 %v1, ptr %res) { ; FAST-NEXT: setb %al ; FAST-NEXT: movq %rdi, (%rsi) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 1) %val = extractvalue {i64, i1} %t, 0 @@ -467,7 +448,6 @@ define zeroext i1 @ssuboi32(i32 %v1, i32 %v2, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movl %edi, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2) %val = extractvalue {i32, i1} %t, 0 @@ -490,7 +470,6 @@ define zeroext i1 @ssuboi64(i64 %v1, i64 %v2, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movq %rdi, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2) %val = extractvalue {i64, i1} %t, 0 @@ -514,7 +493,6 @@ define zeroext i1 @usuboi32(i32 %v1, i32 %v2, ptr %res) { ; FAST-NEXT: setb %al ; FAST-NEXT: movl %edi, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2) %val = extractvalue {i32, i1} %t, 0 @@ -537,7 +515,6 @@ define zeroext i1 @usuboi64(i64 %v1, i64 %v2, ptr %res) { ; FAST-NEXT: setb %al ; FAST-NEXT: movq %rdi, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2) %val = extractvalue {i64, i1} %t, 0 @@ -679,12 +656,11 @@ define zeroext i1 @saddobri32(i32 %v1, i32 %v2) { ; FAST-NEXT: ## %bb.2: ## %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: LBB31_1: ## %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: ## kill: def $al killed $al killed $eax ; FAST-NEXT: retq %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2) %val = extractvalue {i32, i1} %t, 0 @@ -717,12 +693,11 @@ define zeroext i1 @saddobri64(i64 %v1, i64 %v2) { ; FAST-NEXT: ## %bb.2: ## %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: LBB32_1: ## %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: ## kill: def $al killed $al killed $eax ; FAST-NEXT: retq %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2) %val = extractvalue {i64, i1} %t, 0 @@ -755,12 +730,11 @@ define zeroext i1 @uaddobri32(i32 %v1, i32 %v2) { ; FAST-NEXT: ## %bb.2: ## %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: LBB33_1: ## %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: ## kill: def $al killed $al killed $eax ; FAST-NEXT: retq %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2) %val = extractvalue {i32, i1} %t, 0 @@ -793,12 +767,11 @@ define zeroext i1 @uaddobri64(i64 %v1, i64 %v2) { ; FAST-NEXT: ## %bb.2: ## %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: LBB34_1: ## %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: ## kill: def $al killed $al killed $eax ; FAST-NEXT: retq %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2) %val = extractvalue {i64, i1} %t, 0 @@ -831,12 +804,11 @@ define zeroext i1 @ssubobri32(i32 %v1, i32 %v2) { ; FAST-NEXT: ## %bb.2: ## %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: LBB35_1: ## %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: ## kill: def $al killed $al killed $eax ; FAST-NEXT: retq %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2) %val = extractvalue {i32, i1} %t, 0 @@ -869,12 +841,11 @@ define zeroext i1 @ssubobri64(i64 %v1, i64 %v2) { ; FAST-NEXT: ## %bb.2: ## %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: LBB36_1: ## %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: ## kill: def $al killed $al killed $eax ; FAST-NEXT: retq %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2) %val = extractvalue {i64, i1} %t, 0 @@ -907,12 +878,11 @@ define zeroext i1 @usubobri32(i32 %v1, i32 %v2) { ; FAST-NEXT: ## %bb.2: ## %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: LBB37_1: ## %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: ## kill: def $al killed $al killed $eax ; FAST-NEXT: retq %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2) %val = extractvalue {i32, i1} %t, 0 @@ -945,12 +915,11 @@ define zeroext i1 @usubobri64(i64 %v1, i64 %v2) { ; FAST-NEXT: ## %bb.2: ## %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: LBB38_1: ## %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: ## kill: def $al killed $al killed $eax ; FAST-NEXT: retq %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2) %val = extractvalue {i64, i1} %t, 0 diff --git a/llvm/test/CodeGen/X86/xmulo.ll b/llvm/test/CodeGen/X86/xmulo.ll index 6eb34b4e773e..2169b39b9dfa 100644 --- a/llvm/test/CodeGen/X86/xmulo.ll +++ b/llvm/test/CodeGen/X86/xmulo.ll @@ -76,7 +76,7 @@ define zeroext i1 @smuloi8(i8 %v1, i8 %v2, ptr %res) { ; FAST-NEXT: seto %cl ; FAST-NEXT: movb %al, (%rdx) ; FAST-NEXT: andb $1, %cl -; FAST-NEXT: movzbl %cl, %eax +; FAST-NEXT: movl %ecx, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smuloi8: @@ -118,7 +118,6 @@ define zeroext i1 @smuloi16(i16 %v1, i16 %v2, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movw %di, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smuloi16: @@ -157,7 +156,6 @@ define zeroext i1 @smuloi32(i32 %v1, i32 %v2, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movl %edi, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smuloi32: @@ -196,7 +194,6 @@ define zeroext i1 @smuloi64(i64 %v1, i64 %v2, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movq %rdi, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smuloi64: @@ -306,7 +303,7 @@ define zeroext i1 @umuloi8(i8 %v1, i8 %v2, ptr %res) { ; FAST-NEXT: seto %cl ; FAST-NEXT: movb %al, (%rdx) ; FAST-NEXT: andb $1, %cl -; FAST-NEXT: movzbl %cl, %eax +; FAST-NEXT: movl %ecx, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umuloi8: @@ -355,7 +352,7 @@ define zeroext i1 @umuloi16(i16 %v1, i16 %v2, ptr %res) { ; FAST-NEXT: seto %dl ; FAST-NEXT: movw %ax, (%rcx) ; FAST-NEXT: andb $1, %dl -; FAST-NEXT: movzbl %dl, %eax +; FAST-NEXT: movl %edx, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umuloi16: @@ -404,7 +401,7 @@ define zeroext i1 @umuloi32(i32 %v1, i32 %v2, ptr %res) { ; FAST-NEXT: seto %dl ; FAST-NEXT: movl %eax, (%rcx) ; FAST-NEXT: andb $1, %dl -; FAST-NEXT: movzbl %dl, %eax +; FAST-NEXT: movl %edx, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umuloi32: @@ -453,7 +450,7 @@ define zeroext i1 @umuloi64(i64 %v1, i64 %v2, ptr %res) { ; FAST-NEXT: seto %dl ; FAST-NEXT: movq %rax, (%rcx) ; FAST-NEXT: andb $1, %dl -; FAST-NEXT: movzbl %dl, %eax +; FAST-NEXT: movl %edx, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umuloi64: @@ -779,12 +776,11 @@ define zeroext i1 @smulobri8(i8 %v1, i8 %v2) { ; FAST-NEXT: # %bb.2: # %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: .LBB15_1: # %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: # kill: def $al killed $al killed $eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smulobri8: @@ -843,12 +839,11 @@ define zeroext i1 @smulobri16(i16 %v1, i16 %v2) { ; FAST-NEXT: # %bb.2: # %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: .LBB16_1: # %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: # kill: def $al killed $al killed $eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smulobri16: @@ -904,12 +899,11 @@ define zeroext i1 @smulobri32(i32 %v1, i32 %v2) { ; FAST-NEXT: # %bb.2: # %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: .LBB17_1: # %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: # kill: def $al killed $al killed $eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smulobri32: @@ -965,12 +959,11 @@ define zeroext i1 @smulobri64(i64 %v1, i64 %v2) { ; FAST-NEXT: # %bb.2: # %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: .LBB18_1: # %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: # kill: def $al killed $al killed $eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smulobri64: @@ -1094,12 +1087,11 @@ define zeroext i1 @umulobri8(i8 %v1, i8 %v2) { ; FAST-NEXT: # %bb.2: # %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: .LBB19_1: # %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: # kill: def $al killed $al killed $eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umulobri8: @@ -1162,12 +1154,11 @@ define zeroext i1 @umulobri16(i16 %v1, i16 %v2) { ; FAST-NEXT: # %bb.2: # %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: .LBB20_1: # %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: # kill: def $al killed $al killed $eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umulobri16: @@ -1226,12 +1217,11 @@ define zeroext i1 @umulobri32(i32 %v1, i32 %v2) { ; FAST-NEXT: # %bb.2: # %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: .LBB21_1: # %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: # kill: def $al killed $al killed $eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umulobri32: @@ -1290,12 +1280,11 @@ define zeroext i1 @umulobri64(i64 %v1, i64 %v2) { ; FAST-NEXT: # %bb.2: # %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: .LBB22_1: # %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: # kill: def $al killed $al killed $eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umulobri64: @@ -1422,7 +1411,7 @@ define zeroext i1 @smuloi8_load(ptr %ptr1, i8 %v2, ptr %res) { ; FAST-NEXT: seto %cl ; FAST-NEXT: movb %al, (%rdx) ; FAST-NEXT: andb $1, %cl -; FAST-NEXT: movzbl %cl, %eax +; FAST-NEXT: movl %ecx, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smuloi8_load: @@ -1471,7 +1460,7 @@ define zeroext i1 @smuloi8_load2(i8 %v1, ptr %ptr2, ptr %res) { ; FAST-NEXT: seto %cl ; FAST-NEXT: movb %al, (%rdx) ; FAST-NEXT: andb $1, %cl -; FAST-NEXT: movzbl %cl, %eax +; FAST-NEXT: movl %ecx, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smuloi8_load2: @@ -1515,7 +1504,6 @@ define zeroext i1 @smuloi16_load(ptr %ptr1, i16 %v2, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movw %si, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smuloi16_load: @@ -1556,7 +1544,6 @@ define zeroext i1 @smuloi16_load2(i16 %v1, ptr %ptr2, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movw %di, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smuloi16_load2: @@ -1597,7 +1584,6 @@ define zeroext i1 @smuloi32_load(ptr %ptr1, i32 %v2, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movl %esi, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smuloi32_load: @@ -1638,7 +1624,6 @@ define zeroext i1 @smuloi32_load2(i32 %v1, ptr %ptr2, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movl %edi, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smuloi32_load2: @@ -1679,7 +1664,6 @@ define zeroext i1 @smuloi64_load(ptr %ptr1, i64 %v2, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movq %rsi, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smuloi64_load: @@ -1789,7 +1773,6 @@ define zeroext i1 @smuloi64_load2(i64 %v1, ptr %ptr2, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movq %rdi, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smuloi64_load2: @@ -1898,7 +1881,7 @@ define zeroext i1 @umuloi8_load(ptr %ptr1, i8 %v2, ptr %res) { ; FAST-NEXT: seto %cl ; FAST-NEXT: movb %al, (%rdx) ; FAST-NEXT: andb $1, %cl -; FAST-NEXT: movzbl %cl, %eax +; FAST-NEXT: movl %ecx, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umuloi8_load: @@ -1947,7 +1930,7 @@ define zeroext i1 @umuloi8_load2(i8 %v1, ptr %ptr2, ptr %res) { ; FAST-NEXT: seto %cl ; FAST-NEXT: movb %al, (%rdx) ; FAST-NEXT: andb $1, %cl -; FAST-NEXT: movzbl %cl, %eax +; FAST-NEXT: movl %ecx, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umuloi8_load2: @@ -1997,7 +1980,7 @@ define zeroext i1 @umuloi16_load(ptr %ptr1, i16 %v2, ptr %res) { ; FAST-NEXT: seto %dl ; FAST-NEXT: movw %ax, (%rcx) ; FAST-NEXT: andb $1, %dl -; FAST-NEXT: movzbl %dl, %eax +; FAST-NEXT: movl %edx, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umuloi16_load: @@ -2050,7 +2033,7 @@ define zeroext i1 @umuloi16_load2(i16 %v1, ptr %ptr2, ptr %res) { ; FAST-NEXT: seto %dl ; FAST-NEXT: movw %ax, (%rcx) ; FAST-NEXT: andb $1, %dl -; FAST-NEXT: movzbl %dl, %eax +; FAST-NEXT: movl %edx, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umuloi16_load2: @@ -2101,7 +2084,7 @@ define zeroext i1 @umuloi32_load(ptr %ptr1, i32 %v2, ptr %res) { ; FAST-NEXT: seto %dl ; FAST-NEXT: movl %eax, (%rcx) ; FAST-NEXT: andb $1, %dl -; FAST-NEXT: movzbl %dl, %eax +; FAST-NEXT: movl %edx, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umuloi32_load: @@ -2152,7 +2135,7 @@ define zeroext i1 @umuloi32_load2(i32 %v1, ptr %ptr2, ptr %res) { ; FAST-NEXT: seto %dl ; FAST-NEXT: movl %eax, (%rcx) ; FAST-NEXT: andb $1, %dl -; FAST-NEXT: movzbl %dl, %eax +; FAST-NEXT: movl %edx, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umuloi32_load2: @@ -2203,7 +2186,7 @@ define zeroext i1 @umuloi64_load(ptr %ptr1, i64 %v2, ptr %res) { ; FAST-NEXT: seto %dl ; FAST-NEXT: movq %rax, (%rcx) ; FAST-NEXT: andb $1, %dl -; FAST-NEXT: movzbl %dl, %eax +; FAST-NEXT: movl %edx, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umuloi64_load: @@ -2280,7 +2263,7 @@ define zeroext i1 @umuloi64_load2(i64 %v1, ptr %ptr2, ptr %res) { ; FAST-NEXT: seto %dl ; FAST-NEXT: movq %rax, (%rcx) ; FAST-NEXT: andb $1, %dl -; FAST-NEXT: movzbl %dl, %eax +; FAST-NEXT: movl %edx, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umuloi64_load2: diff --git a/llvm/test/DebugInfo/X86/convert-debugloc.ll b/llvm/test/DebugInfo/X86/convert-debugloc.ll index de0857d53832..ad3f48c05de9 100644 --- a/llvm/test/DebugInfo/X86/convert-debugloc.ll +++ b/llvm/test/DebugInfo/X86/convert-debugloc.ll @@ -27,7 +27,7 @@ ; RUN: | FileCheck %s --check-prefix=VERBOSE --check-prefix=CONV "--implicit-check-not={{DW_TAG|NULL}}" -; SPLITCONV: Compile Unit:{{.*}} DWO_id = 0x24191746f389535f +; SPLITCONV: Compile Unit:{{.*}} DWO_id = 0x06580df9fdd5b54b ; SPLIT: DW_TAG_skeleton_unit ; CONV: DW_TAG_compile_unit -- GitLab From 2a4f715b0797f235b58f6dfefbc369c2374c44c1 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 6 Feb 2024 09:38:50 -0800 Subject: [PATCH 095/266] [RISCV] Adjust a few vector scheduler class names. NFC (#80795) Shortening Iota to Iot seemed strange to me. I also remove the M from VMIota and VMIdx. The instruction for viota does have an m at the end of it, but vid.v does not. The M didn't seem very important for viota. --- llvm/lib/Target/RISCV/RISCVInstrInfoV.td | 8 ++++---- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 12 ++++++------ llvm/lib/Target/RISCV/RISCVSchedSiFive7.td | 6 +++--- llvm/lib/Target/RISCV/RISCVScheduleV.td | 12 ++++++------ 4 files changed, 19 insertions(+), 19 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td index 9fc9a29c210d..d2d824da9c78 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -861,9 +861,9 @@ multiclass VMSFS_MV_V funct6, bits<5> vs1> { SchedUnaryMC<"WriteVMSFSV", "ReadVMSFSV">; } -multiclass VMIOT_MV_V funct6, bits<5> vs1> { +multiclass VIOTA_MV_V funct6, bits<5> vs1> { def "" : VALUVs2, - SchedUnaryMC<"WriteVMIotV", "ReadVMIotV">; + SchedUnaryMC<"WriteVIotaV", "ReadVIotaV">; } multiclass VSHT_IV_V_X_I funct6> { @@ -1621,7 +1621,7 @@ defm VMSIF_M : VMSFS_MV_V<"vmsif.m", 0b010100, 0b00011>; // vmsof.m set-only-first mask bit defm VMSOF_M : VMSFS_MV_V<"vmsof.m", 0b010100, 0b00010>; // Vector Iota Instruction -defm VIOTA_M : VMIOT_MV_V<"viota.m", 0b010100, 0b10000>; +defm VIOTA_M : VIOTA_MV_V<"viota.m", 0b010100, 0b10000>; } // Constraints = "@earlyclobber $vd", RVVConstraint = Iota @@ -1631,7 +1631,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { let vs2 = 0 in def VID_V : RVInstV<0b010100, 0b10001, OPMVV, (outs VR:$vd), (ins VMaskOp:$vm), "vid.v", "$vd$vm">, - SchedNullaryMC<"WriteVMIdxV">; + SchedNullaryMC<"WriteVIdxV">; // Integer Scalar Move Instructions let vm = 1, RVVConstraint = NoConstraint in { diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index d3973f9b2edc..48cf48e8af58 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -2066,10 +2066,10 @@ multiclass VPseudoVID_V { defvar mx = m.MX; let VLMul = m.value in { def "_V_" # mx : VPseudoNullaryNoMask, - SchedNullary<"WriteVMIdxV", mx, forceMergeOpRead=true>; + SchedNullary<"WriteVIdxV", mx, forceMergeOpRead=true>; def "_V_" # mx # "_MASK" : VPseudoNullaryMask, RISCVMaskedPseudo, - SchedNullary<"WriteVMIdxV", mx, + SchedNullary<"WriteVIdxV", mx, forceMergeOpRead=true>; } } @@ -2084,17 +2084,17 @@ multiclass VPseudoNullaryPseudoM { } } -multiclass VPseudoVIOT_M { +multiclass VPseudoVIOTA_M { defvar constraint = "@earlyclobber $rd"; foreach m = MxList in { defvar mx = m.MX; let VLMul = m.value in { def "_" # mx : VPseudoUnaryNoMask, - SchedUnary<"WriteVMIotV", "ReadVMIotV", mx, + SchedUnary<"WriteVIotaV", "ReadVIotaV", mx, forceMergeOpRead=true>; def "_" # mx # "_MASK" : VPseudoUnaryMask, RISCVMaskedPseudo, - SchedUnary<"WriteVMIotV", "ReadVMIotV", mx, + SchedUnary<"WriteVIotaV", "ReadVIotaV", mx, forceMergeOpRead=true>; } } @@ -6747,7 +6747,7 @@ defm PseudoVMSOF: VPseudoVSFS_M; //===----------------------------------------------------------------------===// // 15.8. Vector Iota Instruction //===----------------------------------------------------------------------===// -defm PseudoVIOTA_M: VPseudoVIOT_M; +defm PseudoVIOTA_M: VPseudoVIOTA_M; //===----------------------------------------------------------------------===// // 15.9. Vector Element Index Instruction diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td index 976b88250e45..040cec426740 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td @@ -868,8 +868,8 @@ foreach mx = SchedMxList in { defvar Cycles = SiFive7GetCyclesDefault.c; defvar IsWorstCase = SiFive7IsWorstCaseMX.c; let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { - defm "" : LMULWriteResMX<"WriteVMIotV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVMIdxV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIotaV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIdxV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; } } @@ -1173,7 +1173,7 @@ defm "" : LMULReadAdvance<"ReadVMALUV", 0>; defm "" : LMULReadAdvance<"ReadVMPopV", 0>; defm "" : LMULReadAdvance<"ReadVMFFSV", 0>; defm "" : LMULReadAdvance<"ReadVMSFSV", 0>; -defm "" : LMULReadAdvance<"ReadVMIotV", 0>; +defm "" : LMULReadAdvance<"ReadVIotaV", 0>; // 17. Vector Permutation Instructions def : ReadAdvance; diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td index 29f2ceec25fa..d15cb611ae66 100644 --- a/llvm/lib/Target/RISCV/RISCVScheduleV.td +++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td @@ -473,9 +473,9 @@ defm "" : LMULSchedWrites<"WriteVMFFSV">; // 15.6. Vector Set-only-First Mask Bit defm "" : LMULSchedWrites<"WriteVMSFSV">; // 15.8. Vector Iota Instruction -defm "" : LMULSchedWrites<"WriteVMIotV">; +defm "" : LMULSchedWrites<"WriteVIotaV">; // 15.9. Vector Element Index Instruction -defm "" : LMULSchedWrites<"WriteVMIdxV">; +defm "" : LMULSchedWrites<"WriteVIdxV">; // 16. Vector Permutation Instructions // 16.1. Integer Scalar Move Instructions @@ -700,7 +700,7 @@ defm "" : LMULSchedReads<"ReadVMFFSV">; // 15.6. Vector Set-only-First Mask Bit defm "" : LMULSchedReads<"ReadVMSFSV">; // 15.8. Vector Iota Instruction -defm "" : LMULSchedReads<"ReadVMIotV">; +defm "" : LMULSchedReads<"ReadVIotaV">; // 16. Vector Permutation Instructions // 16.1. Integer Scalar Move Instructions @@ -912,8 +912,8 @@ defm "" : LMULWriteRes<"WriteVMALUV", []>; defm "" : LMULWriteRes<"WriteVMPopV", []>; defm "" : LMULWriteRes<"WriteVMFFSV", []>; defm "" : LMULWriteRes<"WriteVMSFSV", []>; -defm "" : LMULWriteRes<"WriteVMIotV", []>; -defm "" : LMULWriteRes<"WriteVMIdxV", []>; +defm "" : LMULWriteRes<"WriteVIotaV", []>; +defm "" : LMULWriteRes<"WriteVIdxV", []>; // 16. Vector Permutation Instructions def : WriteRes; @@ -1074,7 +1074,7 @@ defm "" : LMULReadAdvance<"ReadVMALUV", 0>; defm "" : LMULReadAdvance<"ReadVMPopV", 0>; defm "" : LMULReadAdvance<"ReadVMFFSV", 0>; defm "" : LMULReadAdvance<"ReadVMSFSV", 0>; -defm "" : LMULReadAdvance<"ReadVMIotV", 0>; +defm "" : LMULReadAdvance<"ReadVIotaV", 0>; // 16. Vector Permutation Instructions def : ReadAdvance; -- GitLab From 0fb9f68bae4743dbabbccf3bbc575ac569730840 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 6 Feb 2024 09:39:19 -0800 Subject: [PATCH 096/266] [SelectionDAG] Use getRegisterType instead of getTypeToTransformTo in ComputePHILiveOutRegInfo. (#80773) Since we used getNumRegisters right before this, I think this is the correct interface we should be using here. I'm experimenting with making i32 legal on RISC-V 64, but using i64 for the register type between basic blocks. This was one of the first issues I found trying to do that. --- llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp index 5926a6058111..6cf540859152 100644 --- a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp @@ -431,7 +431,7 @@ void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) { if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1) return; - IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT); + IntVT = TLI->getRegisterType(PN->getContext(), IntVT); unsigned BitWidth = IntVT.getSizeInBits(); auto It = ValueMap.find(PN); -- GitLab From 1833de3ee364a996d03bb23b19fe472e3e2ddf3b Mon Sep 17 00:00:00 2001 From: Jeremy Morse Date: Tue, 6 Feb 2024 17:40:32 +0000 Subject: [PATCH 097/266] [Extractor][DebugInfo] Don't pick DebugLocs from dbg intrinsics (#80863) When picking the source location for a branch instruction in the CodeExtractor, we can end up picking the source location of a debugging intrinsic. This never makes sense because any variable assignment information (or labels) might originate from completely different lexical scopes that have been inlined, and also makes the line tables change between -g and -gmlt. Fix this by skipping debug intrinsics when looking for branch source locations. Detected because of test differences with RemoveDIs, the non-intrinsinc form of debug-info -- fixing in intrinsic form to avoid there being spurious test differences when we turn it on. --- llvm/lib/Transforms/Utils/CodeExtractor.cpp | 4 ++++ llvm/test/Transforms/HotColdSplit/split-out-dbg-label.ll | 2 +- llvm/test/Transforms/IROutliner/gvn-phi-debug.ll | 5 ++--- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Transforms/Utils/CodeExtractor.cpp b/llvm/lib/Transforms/Utils/CodeExtractor.cpp index 278111883459..57d392651599 100644 --- a/llvm/lib/Transforms/Utils/CodeExtractor.cpp +++ b/llvm/lib/Transforms/Utils/CodeExtractor.cpp @@ -1769,6 +1769,10 @@ CodeExtractor::extractCodeRegion(const CodeExtractorAnalysisCache &CEAC, return any_of(*BB, [&BranchI](const Instruction &I) { if (!I.getDebugLoc()) return false; + // Don't use source locations attached to debug-intrinsics: they could + // be from completely unrelated scopes. + if (isa(I)) + return false; BranchI->setDebugLoc(I.getDebugLoc()); return true; }); diff --git a/llvm/test/Transforms/HotColdSplit/split-out-dbg-label.ll b/llvm/test/Transforms/HotColdSplit/split-out-dbg-label.ll index 8209f93915e9..97bb13d4bdcf 100644 --- a/llvm/test/Transforms/HotColdSplit/split-out-dbg-label.ll +++ b/llvm/test/Transforms/HotColdSplit/split-out-dbg-label.ll @@ -18,8 +18,8 @@ target triple = "x86_64-apple-macosx10.14.0" ; CHECK: [[FILE:![0-9]+]] = !DIFile ; CHECK: [[INLINE_ME_SCOPE:![0-9]+]] = distinct !DISubprogram(name: "inline_me" ; CHECK: [[SCOPE:![0-9]+]] = distinct !DISubprogram(name: "foo.cold.1" -; CHECK: [[LINE]] = !DILocation(line: 1, column: 1, scope: [[SCOPE]] ; CHECK: [[LABEL]] = !DILabel(scope: [[SCOPE]], name: "bye", file: [[FILE]], line: 28 +; CHECK: [[LINE]] = !DILocation(line: 1, column: 1, scope: [[SCOPE]] ; CHECK: [[LABEL_IN_INLINE_ME]] = !DILabel(scope: [[INLINE_ME_SCOPE]], name: "label_in_@inline_me", file: [[FILE]], line: 29 ; CHECK: [[LINE2]] = !DILocation(line: 2, column: 2, scope: [[INLINE_ME_SCOPE]], inlinedAt: [[LINE]] ; CHECK: [[SCOPED_LABEL]] = !DILabel(scope: [[SCOPE_IN_FOO:![0-9]+]], name: "scoped_label_in_foo", file: [[FILE]], line: 30 diff --git a/llvm/test/Transforms/IROutliner/gvn-phi-debug.ll b/llvm/test/Transforms/IROutliner/gvn-phi-debug.ll index 934bda1fc7c2..217a8498ffbb 100644 --- a/llvm/test/Transforms/IROutliner/gvn-phi-debug.ll +++ b/llvm/test/Transforms/IROutliner/gvn-phi-debug.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 ; RUN: opt -S -passes=verify,iroutliner -ir-outlining-no-cost < %s | FileCheck %s +; RUN: opt -S -passes=verify,iroutliner -ir-outlining-no-cost < %s --try-experimental-debuginfo-iterators | FileCheck %s target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "thumbv7-none-linux-android19" @@ -171,7 +172,5 @@ attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memo ; CHECK: [[DBG8]] = distinct !DISubprogram(name: "w", scope: [[META5]], file: [[META5]], line: 54, type: [[META9:![0-9]+]], scopeLine: 54, flags: DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: [[META0]], retainedNodes: [[META10:![0-9]+]]) ; CHECK: [[META9]] = !DISubroutineType(types: [[META10]]) ; CHECK: [[META10]] = !{} -; CHECK: [[DBG11]] = !DILocation(line: 0, scope: [[META12:![0-9]+]]) -; CHECK: [[META12]] = distinct !DILexicalBlock(scope: [[META13:![0-9]+]], file: [[META5]], line: 56, column: 17) -; CHECK: [[META13]] = distinct !DILexicalBlock(scope: [[DBG8]], file: [[META5]], line: 56, column: 11) +; CHECK: [[DBG11]] = !DILocation(line: 0, scope: [[DBG8]]) ;. -- GitLab From 6eb7273b11e6a3ec7c5ddb2d55bc585a25c0a923 Mon Sep 17 00:00:00 2001 From: Cyndy Ishida Date: Tue, 6 Feb 2024 10:01:45 -0800 Subject: [PATCH 098/266] [readtapi] Ensure universal dylibs record the same input path location across slices (#80875) resolves: https://github.com/llvm/llvm-project/issues/80868 --- llvm/lib/TextAPI/BinaryReader/DylibReader.cpp | 1 + llvm/tools/llvm-readtapi/llvm-readtapi.cpp | 1 + 2 files changed, 2 insertions(+) diff --git a/llvm/lib/TextAPI/BinaryReader/DylibReader.cpp b/llvm/lib/TextAPI/BinaryReader/DylibReader.cpp index 40b57b5e40ea..25b9499d1895 100644 --- a/llvm/lib/TextAPI/BinaryReader/DylibReader.cpp +++ b/llvm/lib/TextAPI/BinaryReader/DylibReader.cpp @@ -408,6 +408,7 @@ Expected DylibReader::readFile(MemoryBufferRef Buffer, Results.emplace_back(std::make_shared(RecordsSlice({T}))); if (auto Err = load(&Obj, *Results.back(), Opt, Arch)) return std::move(Err); + Results.back()->getBinaryAttrs().Path = Buffer.getBufferIdentifier(); } break; } diff --git a/llvm/tools/llvm-readtapi/llvm-readtapi.cpp b/llvm/tools/llvm-readtapi/llvm-readtapi.cpp index 5944b1cd1f59..80064ed98485 100644 --- a/llvm/tools/llvm-readtapi/llvm-readtapi.cpp +++ b/llvm/tools/llvm-readtapi/llvm-readtapi.cpp @@ -199,6 +199,7 @@ static void stubifyImpl(std::unique_ptr IF, Context &Ctx) { // TODO: Add inlining and magic merge support. if (Ctx.OutStream == nullptr) { std::error_code EC; + assert(!IF->getPath().empty() && "Unknown output location"); SmallString OutputLoc = IF->getPath(); replace_extension(OutputLoc, ".tbd"); Ctx.OutStream = std::make_unique(OutputLoc, EC); -- GitLab From 2faeea313fef284fa933e7adb1d4c44a33e943e5 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 6 Feb 2024 10:06:01 -0800 Subject: [PATCH 099/266] [RISCV] Add Ssqosid support to -march. (#80747) --- clang/test/Preprocessor/riscv-target-features.c | 17 +++++++++++++---- llvm/docs/RISCVUsage.rst | 3 +++ llvm/docs/ReleaseNotes.rst | 1 + llvm/lib/Support/RISCVISAInfo.cpp | 1 + llvm/lib/Target/RISCV/RISCVFeatures.td | 4 ++++ llvm/test/CodeGen/RISCV/attributes.ll | 4 ++++ llvm/test/MC/RISCV/attribute-arch.s | 3 +++ llvm/unittests/Support/RISCVISAInfoTest.cpp | 1 + 8 files changed, 30 insertions(+), 4 deletions(-) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index add96c0046cc..ea81c6620443 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -163,6 +163,7 @@ // CHECK-NOT: __riscv_smnpm{{.*$}} // CHECK-NOT: __riscv_ssnpm{{.*$}} // CHECK-NOT: __riscv_sspm{{.*$}} +// CHECK-NOT: __riscv_ssqosid{{.*$}} // CHECK-NOT: __riscv_supm{{.*$}} // CHECK-NOT: __riscv_zaamo {{.*$}} // CHECK-NOT: __riscv_zacas {{.*$}} @@ -1599,19 +1600,27 @@ // RUN: %clang --target=riscv32 -menable-experimental-extensions \ // RUN: -march=rv32i_sspm0p8 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-SSPM-EXT %s -// RUN: %clang --target=riscv64 \ -// RUN: -march=rv64i_sspm0p8 -E -dM %s -menable-experimental-extensions \ +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_sspm0p8 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-SSPM-EXT %s // CHECK-SSPM-EXT: __riscv_sspm 8000{{$}} // RUN: %clang --target=riscv32 -menable-experimental-extensions \ // RUN: -march=rv32i_supm0p8 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s -// RUN: %clang --target=riscv64 \ -// RUN: -march=rv64i_supm0p8 -E -dM %s -menable-experimental-extensions \ +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_supm0p8 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s // CHECK-SUPM-EXT: __riscv_supm 8000{{$}} +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_ssqosid1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSQOSID-EXT %s +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_ssqosid1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSQOSID-EXT %s +// CHECK-SSQOSID-EXT: __riscv_ssqosid 1000000{{$}} + // Misaligned // RUN: %clang --target=riscv32-unknown-linux-gnu -march=rv32i -E -dM %s \ diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index c9e99c9b98e3..43c6c3f116c5 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -246,6 +246,9 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-ssnpm``, ``experimental-smnpm``, ``experimental-smmpm``, ``experimental-sspm``, ``experimental-supm`` LLVM implements the `v0.8.1 draft specification ` +``experimental-ssqosid`` + LLVM implements assembler support for the `v1.0-rc1 draft specification `_. + ``experimental-zabha`` LLVM implements assembler support for the `v1.0-rc1 draft specification `_. diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 6ac83961d7cf..05d8eea3add4 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -102,6 +102,7 @@ Changes to the RISC-V Backend names in the RISC-V profiles specification are now recognised. * Codegen support was added for the Zimop (May-Be-Operations) extension. * The experimental Ssnpm, Smnpm, Smmpm, Sspm, and Supm 0.8.1 Pointer Masking extensions are supported. +* The experimental Ssqosid extension is supported. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index 6fe8eb62e280..d028302b8c4d 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -215,6 +215,7 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { {"smnpm", {0, 8}}, {"ssnpm", {0, 8}}, {"sspm", {0, 8}}, + {"ssqosid", {1, 0}}, {"supm", {0, 8}}, {"zaamo", {0, 2}}, diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 03ccda4561ed..03e098040210 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -828,6 +828,10 @@ def FeatureStdExtSstc : SubtargetFeature<"sstc", "HasStdExtSstc", "true", "'Sstc' (Supervisor-mode timer interrupts)", []>; +def FeaturesSsqosid + : SubtargetFeature<"experimental-ssqosid", "HasStdExtSsqosid", "true", + "'Ssqosid' (Quality-of-Service (QoS) Identifiers)", []>; + def FeatureStdExtShtvala : SubtargetFeature<"shtvala", "HasStdExtShtvala", "true", "'Shtvala' (htval provides all needed values)", []>; diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 088cc0b90a05..13635a94d641 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -121,6 +121,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-smmpm %s -o - | FileCheck --check-prefix=RV32SMMPM %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-sspm %s -o - | FileCheck --check-prefix=RV32SSPM %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-supm %s -o - | FileCheck --check-prefix=RV32SUPM %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssqosid %s -o - | FileCheck --check-prefix=RV32SSQOSID %s ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s @@ -249,6 +250,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-smmpm %s -o - | FileCheck --check-prefix=RV64SMMPM %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-sspm %s -o - | FileCheck --check-prefix=RV64SSPM %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-supm %s -o - | FileCheck --check-prefix=RV64SUPM %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s ; CHECK: .attribute 4, 16 @@ -372,6 +374,7 @@ ; RV32SMMPM: .attribute 5, "rv32i2p1_smmpm0p8" ; RV32SSPM: .attribute 5, "rv32i2p1_sspm0p8" ; RV32SUPM: .attribute 5, "rv32i2p1_supm0p8" +; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0" ; RV64M: .attribute 5, "rv64i2p1_m2p0" ; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0" @@ -499,6 +502,7 @@ ; RV64SMMPM: .attribute 5, "rv64i2p1_smmpm0p8" ; RV64SSPM: .attribute 5, "rv64i2p1_sspm0p8" ; RV64SUPM: .attribute 5, "rv64i2p1_supm0p8" +; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0" define i32 @addi(i32 %a) { %1 = add i32 %a, 1 diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 342e6327cde3..368d8daf72b3 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -321,6 +321,9 @@ .attribute arch, "rv32i_sscounterenw1p0" # CHECK: attribute 5, "rv32i2p1_sscounterenw1p0" +.attribute arch, "rv32i_ssqosid1p0" +# CHECK: attribute 5, "rv32i2p1_ssqosid1p0" + .attribute arch, "rv32i_ssstateen1p0" # CHECK: attribute 5, "rv32i2p1_ssstateen1p0" diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp index ac6066ebdfb9..df4c7f7de8a3 100644 --- a/llvm/unittests/Support/RISCVISAInfoTest.cpp +++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp @@ -885,6 +885,7 @@ Experimental extensions smnpm 0.8 ssnpm 0.8 sspm 0.8 + ssqosid 1.0 supm 0.8 Use -march to specify the target's extension. -- GitLab From c7d181cc67a7af122835bc51159baa0eb6c5ac7c Mon Sep 17 00:00:00 2001 From: Jon Roelofs Date: Tue, 6 Feb 2024 10:27:16 -0800 Subject: [PATCH 100/266] [llvm][unittests] Put human-readable names on TargetParserTests. NFC (#80749) Before: ``` [----------] 65 tests from AArch64CPUTests/AArch64CPUTestFixture [ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/0 [ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/0 (0 ms) [ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/1 [ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/1 (0 ms) [ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/2 [ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/2 (0 ms) [ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/3 [ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/3 (0 ms) [ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/4 [ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/4 (0 ms) [ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/5 [ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/5 (0 ms) [ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/6 [ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/6 (0 ms) [ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/7 [ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/7 (0 ms) [ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/8 ... ``` After: ``` [----------] 65 tests from AArch64CPUTests/AArch64CPUTestFixture [ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a34 [ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a34 (0 ms) [ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a35 [ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a35 (0 ms) [ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a53 [ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a53 (0 ms) [ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a55 [ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a55 (0 ms) [ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a510 [ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a510 (0 ms) [ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a520 [ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a520 (0 ms) [ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a57 [ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a57 (0 ms) [ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a65 [ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a65 (0 ms) ... ``` Which improves the experience of finding and running this: ``` $ ./unittests/TargetParser/TargetParserTests --gtest_filter=AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a65 Note: Google Test filter = AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a65 [==========] Running 1 test from 1 test suite. [----------] Global test environment set-up. [----------] 1 test from AArch64CPUTests/AArch64CPUTestFixture [ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a65 [ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a65 (0 ms) [----------] 1 test from AArch64CPUTests/AArch64CPUTestFixture (0 ms total) [----------] Global test environment tear-down [==========] 1 test from 1 test suite ran. (0 ms total) [ PASSED ] 1 test. ``` --- .../TargetParser/TargetParserTest.cpp | 22 ++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index cbd8fe18cd18..e7f997304eb4 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -163,6 +163,19 @@ template struct ARMCPUTestParams { return os; } + /// Print a gtest-compatible facsimile of the CPUName, to make the test's name + /// human-readable. + /// + /// https://github.com/google/googletest/blob/main/docs/advanced.md#specifying-names-for-value-parameterized-test-parameters + static std::string + PrintToStringParamName(const testing::TestParamInfo>& Info) { + std::string Name = Info.param.CPUName.str(); + for (char &C : Name) + if (!std::isalnum(C)) + C = '_'; + return Name; + } + StringRef CPUName; StringRef ExpectedArch; StringRef ExpectedFPU; @@ -263,7 +276,8 @@ INSTANTIATE_TEST_SUITE_P( ARM::AEK_SEC | ARM::AEK_VIRT | ARM::AEK_DSP, "7-A"), ARMCPUTestParams("cortex-a8", "armv7-a", "neon", - ARM::AEK_SEC | ARM::AEK_DSP, "7-A"))); + ARM::AEK_SEC | ARM::AEK_DSP, "7-A")), + ARMCPUTestParams::PrintToStringParamName); // gtest in llvm has a limit of 50 test cases when using ::Values so we split // them into 2 blocks @@ -483,7 +497,8 @@ INSTANTIATE_TEST_SUITE_P( ARMCPUTestParams("xscale", "xscale", "none", ARM::AEK_NONE, "xscale"), ARMCPUTestParams("swift", "armv7s", "neon-vfpv4", ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP, - "7-S"))); + "7-S")), + ARMCPUTestParams::PrintToStringParamName); static constexpr unsigned NumARMCPUArchs = 90; @@ -1660,7 +1675,8 @@ INSTANTIATE_TEST_SUITE_P( {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_FP16, AArch64::AEK_RAS, AArch64::AEK_LSE, AArch64::AEK_RDM})), - "8.2-A"))); + "8.2-A")), + ARMCPUTestParams::PrintToStringParamName); // Note: number of CPUs includes aliases. static constexpr unsigned NumAArch64CPUArchs = 68; -- GitLab From a4531108da358500939af95b53794591432aaf74 Mon Sep 17 00:00:00 2001 From: Jeremy Morse Date: Tue, 6 Feb 2024 18:30:20 +0000 Subject: [PATCH 101/266] [DebugInfo][RemoveDIs] Extend intrinsic-conversion in debugify (#80861) A while back the entry/exit points of debugify were instrumented with conversion functions to/from non-intrinsic-form debug-info. This is the path of least resistance to incrementally converting parts of LLVM to use the new format. However, it turns out that debugify registers callbacks with the pass manager and can be fed non-intrinsic form debug-info. Thus: this patch wraps each of the four major debugify functions with the convertion utilities, and extends test coverage to a test that exposes this problem. (An alternative would be to put this code in the callback lambdas, but then it would be fighting pass manager abstractions of what type the IR has). Handily debugify has been designed to record the /meaning/ of debug-info rather than take pointers to intrinsics and the like, so the storage mechanism for debug-info is transparent to it! --- llvm/lib/Transforms/Utils/Debugify.cpp | 73 +++++++++---------- .../Util/Debugify/loc-only-original-mode.ll | 17 +++-- 2 files changed, 46 insertions(+), 44 deletions(-) diff --git a/llvm/lib/Transforms/Utils/Debugify.cpp b/llvm/lib/Transforms/Utils/Debugify.cpp index d0cc603426d2..200bad22148f 100644 --- a/llvm/lib/Transforms/Utils/Debugify.cpp +++ b/llvm/lib/Transforms/Utils/Debugify.cpp @@ -87,6 +87,10 @@ bool llvm::applyDebugifyMetadata( return false; } + bool NewDebugMode = M.IsNewDbgInfoFormat; + if (NewDebugMode) + M.convertFromNewDbgValues(); + DIBuilder DIB(M); LLVMContext &Ctx = M.getContext(); auto *Int32Ty = Type::getInt32Ty(Ctx); @@ -210,6 +214,9 @@ bool llvm::applyDebugifyMetadata( if (!M.getModuleFlag(DIVersionKey)) M.addModuleFlag(Module::Warning, DIVersionKey, DEBUG_METADATA_VERSION); + if (NewDebugMode) + M.convertToNewDbgValues(); + return true; } @@ -304,6 +311,10 @@ bool llvm::collectDebugInfoMetadata(Module &M, return false; } + bool NewDebugMode = M.IsNewDbgInfoFormat; + if (NewDebugMode) + M.convertFromNewDbgValues(); + uint64_t FunctionsCnt = DebugInfoBeforePass.DIFunctions.size(); // Visit each instruction. for (Function &F : Functions) { @@ -368,6 +379,9 @@ bool llvm::collectDebugInfoMetadata(Module &M, } } + if (NewDebugMode) + M.convertToNewDbgValues(); + return true; } @@ -547,6 +561,10 @@ bool llvm::checkDebugInfoMetadata(Module &M, return false; } + bool NewDebugMode = M.IsNewDbgInfoFormat; + if (NewDebugMode) + M.convertFromNewDbgValues(); + // Map the debug info holding DIs after a pass. DebugInfoPerPass DebugInfoAfterPass; @@ -657,6 +675,9 @@ bool llvm::checkDebugInfoMetadata(Module &M, // the debugging information from the previous pass. DebugInfoBeforePass = DebugInfoAfterPass; + if (NewDebugMode) + M.convertToNewDbgValues(); + LLVM_DEBUG(dbgs() << "\n\n"); return Result; } @@ -714,6 +735,10 @@ bool checkDebugifyMetadata(Module &M, return false; } + bool NewDebugMode = M.IsNewDbgInfoFormat; + if (NewDebugMode) + M.convertFromNewDbgValues(); + auto getDebugifyOperand = [&](unsigned Idx) -> unsigned { return mdconst::extract(NMD->getOperand(Idx)->getOperand(0)) ->getZExtValue(); @@ -791,24 +816,22 @@ bool checkDebugifyMetadata(Module &M, dbg() << ": " << (HasErrors ? "FAIL" : "PASS") << '\n'; // Strip debugify metadata if required. + bool Ret = false; if (Strip) - return stripDebugifyMetadata(M); + Ret = stripDebugifyMetadata(M); + + if (NewDebugMode) + M.convertToNewDbgValues(); - return false; + return Ret; } /// ModulePass for attaching synthetic debug info to everything, used with the /// legacy module pass manager. struct DebugifyModulePass : public ModulePass { bool runOnModule(Module &M) override { - bool NewDebugMode = M.IsNewDbgInfoFormat; - if (NewDebugMode) - M.convertFromNewDbgValues(); - - bool Result = applyDebugify(M, Mode, DebugInfoBeforePass, NameOfWrappedPass); - - if (NewDebugMode) - M.convertToNewDbgValues(); + bool Result = + applyDebugify(M, Mode, DebugInfoBeforePass, NameOfWrappedPass); return Result; } @@ -834,14 +857,8 @@ private: /// single function, used with the legacy module pass manager. struct DebugifyFunctionPass : public FunctionPass { bool runOnFunction(Function &F) override { - bool NewDebugMode = F.IsNewDbgInfoFormat; - if (NewDebugMode) - F.convertFromNewDbgValues(); - - bool Result = applyDebugify(F, Mode, DebugInfoBeforePass, NameOfWrappedPass); - - if (NewDebugMode) - F.convertToNewDbgValues(); + bool Result = + applyDebugify(F, Mode, DebugInfoBeforePass, NameOfWrappedPass); return Result; } @@ -868,10 +885,6 @@ private: /// legacy module pass manager. struct CheckDebugifyModulePass : public ModulePass { bool runOnModule(Module &M) override { - bool NewDebugMode = M.IsNewDbgInfoFormat; - if (NewDebugMode) - M.convertFromNewDbgValues(); - bool Result; if (Mode == DebugifyMode::SyntheticDebugInfo) Result = checkDebugifyMetadata(M, M.functions(), NameOfWrappedPass, @@ -882,9 +895,6 @@ struct CheckDebugifyModulePass : public ModulePass { "CheckModuleDebugify (original debuginfo)", NameOfWrappedPass, OrigDIVerifyBugsReportFilePath); - if (NewDebugMode) - M.convertToNewDbgValues(); - return Result; } @@ -918,10 +928,6 @@ private: /// with the legacy module pass manager. struct CheckDebugifyFunctionPass : public FunctionPass { bool runOnFunction(Function &F) override { - bool NewDebugMode = F.IsNewDbgInfoFormat; - if (NewDebugMode) - F.convertFromNewDbgValues(); - Module &M = *F.getParent(); auto FuncIt = F.getIterator(); bool Result; @@ -935,8 +941,6 @@ struct CheckDebugifyFunctionPass : public FunctionPass { "CheckFunctionDebugify (original debuginfo)", NameOfWrappedPass, OrigDIVerifyBugsReportFilePath); - if (NewDebugMode) - F.convertToNewDbgValues(); return Result; } @@ -1009,10 +1013,6 @@ createDebugifyFunctionPass(enum DebugifyMode Mode, } PreservedAnalyses NewPMDebugifyPass::run(Module &M, ModuleAnalysisManager &) { - bool NewDebugMode = M.IsNewDbgInfoFormat; - if (NewDebugMode) - M.convertFromNewDbgValues(); - if (Mode == DebugifyMode::SyntheticDebugInfo) applyDebugifyMetadata(M, M.functions(), "ModuleDebugify: ", /*ApplyToMF*/ nullptr); @@ -1021,9 +1021,6 @@ PreservedAnalyses NewPMDebugifyPass::run(Module &M, ModuleAnalysisManager &) { "ModuleDebugify (original debuginfo)", NameOfWrappedPass); - if (NewDebugMode) - M.convertToNewDbgValues(); - PreservedAnalyses PA; PA.preserveSet(); return PA; diff --git a/llvm/test/Transforms/Util/Debugify/loc-only-original-mode.ll b/llvm/test/Transforms/Util/Debugify/loc-only-original-mode.ll index 65f24831bc89..b1ba4e15d49f 100644 --- a/llvm/test/Transforms/Util/Debugify/loc-only-original-mode.ll +++ b/llvm/test/Transforms/Util/Debugify/loc-only-original-mode.ll @@ -14,6 +14,11 @@ ; RUN: -verify-each-debuginfo-preserve \ ; RUN: -debugify-func-limit=2 -S 2>&1 | FileCheck %s --check-prefix=CHECK-DROP +;; Add some runlines that use RemoveDIs non-intrinsic debug-info, to check that +;; variable preservation checking works. +; RUN: opt < %s -passes=deadargelim --try-experimental-debuginfo-iterators \ +; RUN: -verify-each-debuginfo-preserve \ +; RUN: -debugify-level=location+variables -S 2>&1 | FileCheck %s --check-prefix=CHECK-DROP ; CHECK-NOT: drops dbg.value()/dbg.declare() ; CHECK-DROP: drops dbg.value()/dbg.declare() @@ -22,10 +27,10 @@ target triple = "x86_64-unknown-linux-gnu" define dso_local i32 @fn2(i32 %l, i32 %k) !dbg !7 { entry: - call void @llvm.dbg.value(metadata i32 %l, metadata !12, metadata !DIExpression()), !dbg !15 - call void @llvm.dbg.value(metadata i32 %k, metadata !13, metadata !DIExpression()), !dbg !15 + tail call void @llvm.dbg.value(metadata i32 %l, metadata !12, metadata !DIExpression()), !dbg !15 + tail call void @llvm.dbg.value(metadata i32 %k, metadata !13, metadata !DIExpression()), !dbg !15 %call = call i32 (...) @fn3(), !dbg !16 - call void @llvm.dbg.value(metadata i32 %call, metadata !14, metadata !DIExpression()), !dbg !15 + tail call void @llvm.dbg.value(metadata i32 %call, metadata !14, metadata !DIExpression()), !dbg !15 ret i32 %call, !dbg !17 } @@ -33,10 +38,10 @@ declare !dbg !18 dso_local i32 @fn3(...) define dso_local i32 @fn(i32 %x, i32 %y) !dbg !22 { entry: - call void @llvm.dbg.value(metadata i32 %x, metadata !24, metadata !DIExpression()), !dbg !27 - call void @llvm.dbg.value(metadata i32 %y, metadata !25, metadata !DIExpression()), !dbg !27 + tail call void @llvm.dbg.value(metadata i32 %x, metadata !24, metadata !DIExpression()), !dbg !27 + tail call void @llvm.dbg.value(metadata i32 %y, metadata !25, metadata !DIExpression()), !dbg !27 %call = call i32 @fn2(i32 %x, i32 %y), !dbg !27 - call void @llvm.dbg.value(metadata i32 %call, metadata !26, metadata !DIExpression()), !dbg !27 + tail call void @llvm.dbg.value(metadata i32 %call, metadata !26, metadata !DIExpression()), !dbg !27 %add = add nsw i32 %call, %x, !dbg !27 %add1 = add nsw i32 %add, %y, !dbg !27 ret i32 %add1, !dbg !27 -- GitLab From 33cfc1341fab1af8d0f2a8270332fcc91895f473 Mon Sep 17 00:00:00 2001 From: Davide Italiano Date: Tue, 6 Feb 2024 10:32:28 -0800 Subject: [PATCH 102/266] [github][CODEOWNERS] Add BOLT. --- .github/CODEOWNERS | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS index 3c67a45bbcf7..767f58e01a39 100644 --- a/.github/CODEOWNERS +++ b/.github/CODEOWNERS @@ -101,3 +101,6 @@ # MLIR Sparsifier. /mlir/**/*SparseTensor*/ @aartbik @PeimingLiu @yinying-lisa-li @matthias-springer + +# BOLT +/bolt/ @aaupov @maksfb @rafaelauler @dcci -- GitLab From f2508d0a406c8978636eafeb9a23e15984e68836 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 6 Feb 2024 10:38:06 -0800 Subject: [PATCH 103/266] [RISCV][Docs] Use double underscore for external links in RISCVUsage.rst. Using a single underscore creates a reference target. If the target name has the same name as another link, we get a "Duplicate target name" warning. This is currently happening for Ssqosid. Using __ prevents this. I've converted all links so no one trips over this in the future. One link was missing any underscores so wasn't a link at all in the generated html. --- llvm/docs/RISCVUsage.rst | 60 ++++++++++++++++++++-------------------- 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 43c6c3f116c5..5ae10a8681f2 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -21,10 +21,10 @@ and ISA extensions with pragmatic variances. The most recent specification can be found at: https://github.com/riscv/riscv-isa-manual/releases/. `The official RISC-V International specification page -`_. is also worth checking, but +`__. is also worth checking, but tends to significantly lag the specifications linked above. Make sure to check the `wiki for not yet integrated extensions -`_ and note +`__ and note that in addition, we sometimes carry support for extensions that have not yet been ratified (these will be marked as experimental - see below) and support various vendor-specific extensions (see below). @@ -234,7 +234,7 @@ Supported .. _riscv-profiles-extensions-note: ``Za128rs``, ``Za64rs``, ``Zic64b``, ``Ziccamoa``, ``Ziccif``, ``Zicclsm``, ``Ziccrse``, ``Shcounterenvw``, ``Shgatpa``, ``Shtvala``, ``Shvsatpa``, ``Shvstvala``, ``Shvstvecd``, ``Ssccptr``, ``Sscounterenw``, ``Ssstateen``, ``Ssstrict``, ``Sstvala``, ``Sstvecd``, ``Ssu64xl``, ``Svade``, ``Svbare`` - These extensions are defined as part of the `RISC-V Profiles specification `_. They do not introduce any new features themselves, but instead describe existing hardware features. + These extensions are defined as part of the `RISC-V Profiles specification `__. They do not introduce any new features themselves, but instead describe existing hardware features. Experimental Extensions ======================= @@ -244,22 +244,22 @@ LLVM supports (to various degrees) a number of experimental extensions. All exp The primary goal of experimental support is to assist in the process of ratification by providing an existence proof of an implementation, and simplifying efforts to validate the value of a proposed extension against large code bases. Experimental extensions are expected to either transition to ratified status, or be eventually removed. The decision on whether to accept an experimental extension is currently done on an entirely case by case basis; if you want to propose one, attending the bi-weekly RISC-V sync-up call is strongly advised. ``experimental-ssnpm``, ``experimental-smnpm``, ``experimental-smmpm``, ``experimental-sspm``, ``experimental-supm`` - LLVM implements the `v0.8.1 draft specification ` + LLVM implements the `v0.8.1 draft specification __` ``experimental-ssqosid`` LLVM implements assembler support for the `v1.0-rc1 draft specification `_. ``experimental-zabha`` - LLVM implements assembler support for the `v1.0-rc1 draft specification `_. + LLVM implements assembler support for the `v1.0-rc1 draft specification `__. ``experimental-zacas`` - LLVM implements the `1.0-rc1 draft specification `_. + LLVM implements the `1.0-rc1 draft specification `__. ``experimental-zalasr`` - LLVM implements the `0.0.5 draft specification `_. + LLVM implements the `0.0.5 draft specification `__. ``experimental-zfbfmin``, ``experimental-zvfbfmin``, ``experimental-zvfbfwma`` - LLVM implements assembler support for the `1.0.0-rc2 specification `_. + LLVM implements assembler support for the `1.0.0-rc2 specification `__. ``experimental-zicfilp``, ``experimental-zicfiss`` LLVM implements the `0.4 draft specification `__. @@ -283,71 +283,71 @@ Vendor Extensions Vendor extensions are extensions which are not standardized by RISC-V International, and are instead defined by a hardware vendor. The term vendor extension roughly parallels the definition of a `non-standard` extension from Section 1.3 of the Volume I: RISC-V Unprivileged ISA specification. In particular, we expect to eventually accept both `custom` extensions and `non-conforming` extensions. -Inclusion of a vendor extension will be considered on a case by case basis. All proposals should be brought to the bi-weekly RISCV sync calls for discussion. For a general idea of the factors likely to be considered, please see the `Clang documentation `_. +Inclusion of a vendor extension will be considered on a case by case basis. All proposals should be brought to the bi-weekly RISCV sync calls for discussion. For a general idea of the factors likely to be considered, please see the `Clang documentation `__. -It is our intention to follow the naming conventions described in `riscv-non-isa/riscv-toolchain-conventions `_. Exceptions to this naming will need to be strongly motivated. +It is our intention to follow the naming conventions described in `riscv-non-isa/riscv-toolchain-conventions `__. Exceptions to this naming will need to be strongly motivated. The current vendor extensions supported are: ``XTHeadBa`` - LLVM implements `the THeadBa (address-generation) vendor-defined instructions specified in `_ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. + LLVM implements `the THeadBa (address-generation) vendor-defined instructions specified in `__ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. ``XTHeadBb`` - LLVM implements `the THeadBb (basic bit-manipulation) vendor-defined instructions specified in `_ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. + LLVM implements `the THeadBb (basic bit-manipulation) vendor-defined instructions specified in `__ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. ``XTHeadBs`` - LLVM implements `the THeadBs (single-bit operations) vendor-defined instructions specified in `_ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. + LLVM implements `the THeadBs (single-bit operations) vendor-defined instructions specified in `__ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. ``XTHeadCondMov`` - LLVM implements `the THeadCondMov (conditional move) vendor-defined instructions specified in `_ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. + LLVM implements `the THeadCondMov (conditional move) vendor-defined instructions specified in `__ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. ``XTHeadCmo`` - LLVM implements `the THeadCmo (cache management operations) vendor-defined instructions specified in `_ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. + LLVM implements `the THeadCmo (cache management operations) vendor-defined instructions specified in `__ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. ``XTHeadFMemIdx`` - LLVM implements `the THeadFMemIdx (indexed memory operations for floating point) vendor-defined instructions specified in `_ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. + LLVM implements `the THeadFMemIdx (indexed memory operations for floating point) vendor-defined instructions specified in `__ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. ``XTheadMac`` - LLVM implements `the XTheadMac (multiply-accumulate instructions) vendor-defined instructions specified in `_ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. + LLVM implements `the XTheadMac (multiply-accumulate instructions) vendor-defined instructions specified in `__ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. ``XTHeadMemIdx`` - LLVM implements `the THeadMemIdx (indexed memory operations) vendor-defined instructions specified in `_ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. + LLVM implements `the THeadMemIdx (indexed memory operations) vendor-defined instructions specified in `__ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. ``XTHeadMemPair`` - LLVM implements `the THeadMemPair (two-GPR memory operations) vendor-defined instructions specified in `_ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. + LLVM implements `the THeadMemPair (two-GPR memory operations) vendor-defined instructions specified in `__ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. ``XTHeadSync`` - LLVM implements `the THeadSync (multi-core synchronization instructions) vendor-defined instructions specified in `_ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. + LLVM implements `the THeadSync (multi-core synchronization instructions) vendor-defined instructions specified in `__ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. ``XTHeadVdot`` - LLVM implements `version 1.0.0 of the THeadV-family custom instructions specification `_ by T-HEAD of Alibaba. All instructions are prefixed with `th.` as described in the specification, and the riscv-toolchain-convention document linked above. + LLVM implements `version 1.0.0 of the THeadV-family custom instructions specification `__ by T-HEAD of Alibaba. All instructions are prefixed with `th.` as described in the specification, and the riscv-toolchain-convention document linked above. ``XVentanaCondOps`` - LLVM implements `version 1.0.0 of the VTx-family custom instructions specification `_ by Ventana Micro Systems. All instructions are prefixed with `vt.` as described in the specification, and the riscv-toolchain-convention document linked above. These instructions are only available for riscv64 at this time. + LLVM implements `version 1.0.0 of the VTx-family custom instructions specification `__ by Ventana Micro Systems. All instructions are prefixed with `vt.` as described in the specification, and the riscv-toolchain-convention document linked above. These instructions are only available for riscv64 at this time. ``XSfvcp`` - LLVM implements `version 1.0.0 of the SiFive Vector Coprocessor Interface (VCIX) Software Specification `_ by SiFive. All instructions are prefixed with `sf.vc.` as described in the specification, and the riscv-toolchain-convention document linked above. + LLVM implements `version 1.0.0 of the SiFive Vector Coprocessor Interface (VCIX) Software Specification `__ by SiFive. All instructions are prefixed with `sf.vc.` as described in the specification, and the riscv-toolchain-convention document linked above. ``XCVbitmanip`` - LLVM implements `version 1.0.0 of the CORE-V Bit Manipulation custom instructions specification `_ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. + LLVM implements `version 1.0.0 of the CORE-V Bit Manipulation custom instructions specification `__ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. ``XCVelw`` - LLVM implements `version 1.0.0 of the CORE-V Event load custom instructions specification `_ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time. + LLVM implements `version 1.0.0 of the CORE-V Event load custom instructions specification `__ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time. ``XCVmac`` - LLVM implements `version 1.0.0 of the CORE-V Multiply-Accumulate (MAC) custom instructions specification `_ by OpenHW Group. All instructions are prefixed with `cv.mac` as described in the specification. These instructions are only available for riscv32 at this time. + LLVM implements `version 1.0.0 of the CORE-V Multiply-Accumulate (MAC) custom instructions specification `__ by OpenHW Group. All instructions are prefixed with `cv.mac` as described in the specification. These instructions are only available for riscv32 at this time. ``XCVmem`` - LLVM implements `version 1.0.0 of the CORE-V Post-Increment load and stores custom instructions specification `_ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time. + LLVM implements `version 1.0.0 of the CORE-V Post-Increment load and stores custom instructions specification `__ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time. ``XCValu`` - LLVM implements `version 1.0.0 of the Core-V ALU custom instructions specification `_ by Core-V. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time. + LLVM implements `version 1.0.0 of the Core-V ALU custom instructions specification `__ by Core-V. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time. ``XCVsimd`` - LLVM implements `version 1.0.0 of the CORE-V SIMD custom instructions specification `_ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. + LLVM implements `version 1.0.0 of the CORE-V SIMD custom instructions specification `__ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. ``XCVbi`` - LLVM implements `version 1.0.0 of the CORE-V immediate branching custom instructions specification `_ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time. + LLVM implements `version 1.0.0 of the CORE-V immediate branching custom instructions specification `__ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time. Experimental C Intrinsics ========================= -- GitLab From 5ac2320824fd545a0d746a1d989543ec4bbd03fa Mon Sep 17 00:00:00 2001 From: michaelrj-google <71531609+michaelrj-google@users.noreply.github.com> Date: Tue, 6 Feb 2024 10:48:25 -0800 Subject: [PATCH 104/266] [libc][NFC] Fix extraneous namespace on Errno (#80894) The Errno type doesn't need to be explicitly namespaced now that it's enclosed in a namespace. --- libc/src/errno/libc_errno.cpp | 2 +- libc/src/errno/libc_errno.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/libc/src/errno/libc_errno.cpp b/libc/src/errno/libc_errno.cpp index 4af21dccc156..30b0a67a3241 100644 --- a/libc/src/errno/libc_errno.cpp +++ b/libc/src/errno/libc_errno.cpp @@ -46,5 +46,5 @@ LIBC_NAMESPACE::Errno::operator int() { return errno; } namespace LIBC_NAMESPACE { // Define the global `libc_errno` instance. -LIBC_NAMESPACE::Errno libc_errno; +Errno libc_errno; } // namespace LIBC_NAMESPACE diff --git a/libc/src/errno/libc_errno.h b/libc/src/errno/libc_errno.h index 6a6ddbc3a9c0..5afc0a41d348 100644 --- a/libc/src/errno/libc_errno.h +++ b/libc/src/errno/libc_errno.h @@ -40,7 +40,7 @@ struct Errno { operator int(); }; -extern LIBC_NAMESPACE::Errno libc_errno; +extern Errno libc_errno; } // namespace LIBC_NAMESPACE -- GitLab From a8ab8306069e8e53b5148ceec7624d7d36ffb459 Mon Sep 17 00:00:00 2001 From: Chelsea Cassanova Date: Tue, 6 Feb 2024 10:56:41 -0800 Subject: [PATCH 105/266] Reland "[lldb][progress][NFC] Add unit test for progress reports" (#80791) This file was previously approved and merged from this PR: https://github.com/llvm/llvm-project/pull/79533 but caused a test failure on the Linux AArch64 bots due to hitting an assertion that `Debugger::Initialize` was already called. To fix this, this commit uses the changes made here: https://github.com/llvm/llvm-project/pull/80786 to use a shared call_once flag to initialize the debugger. --- lldb/unittests/Core/CMakeLists.txt | 1 + lldb/unittests/Core/ProgressReportTest.cpp | 128 +++++++++++++++++++++ 2 files changed, 129 insertions(+) create mode 100644 lldb/unittests/Core/ProgressReportTest.cpp diff --git a/lldb/unittests/Core/CMakeLists.txt b/lldb/unittests/Core/CMakeLists.txt index b3cddd150635..d40c357e3f46 100644 --- a/lldb/unittests/Core/CMakeLists.txt +++ b/lldb/unittests/Core/CMakeLists.txt @@ -7,6 +7,7 @@ add_lldb_unittest(LLDBCoreTests FormatEntityTest.cpp MangledTest.cpp ModuleSpecTest.cpp + ProgressReportTest.cpp RichManglingContextTest.cpp SourceLocationSpecTest.cpp SourceManagerTest.cpp diff --git a/lldb/unittests/Core/ProgressReportTest.cpp b/lldb/unittests/Core/ProgressReportTest.cpp new file mode 100644 index 000000000000..559f3ef1ae46 --- /dev/null +++ b/lldb/unittests/Core/ProgressReportTest.cpp @@ -0,0 +1,128 @@ +//===-- ProgressReportTest.cpp --------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "Plugins/Platform/MacOSX/PlatformMacOSX.h" +#include "Plugins/Platform/MacOSX/PlatformRemoteMacOSX.h" +#include "TestingSupport/SubsystemRAII.h" +#include "TestingSupport/TestUtilities.h" +#include "lldb/Core/Debugger.h" +#include "lldb/Core/Progress.h" +#include "lldb/Host/FileSystem.h" +#include "lldb/Host/HostInfo.h" +#include "lldb/Utility/Listener.h" +#include "gtest/gtest.h" +#include +#include + +using namespace lldb; +using namespace lldb_private; + +class ProgressReportTest : public ::testing::Test { + SubsystemRAII subsystems; + + // The debugger's initialization function can't be called with no arguments + // so calling it using SubsystemRAII will cause the test build to fail as + // SubsystemRAII will call Initialize with no arguments. As such we set it up + // here the usual way. + void SetUp() override { + std::call_once(TestUtilities::g_debugger_initialize_flag, + []() { Debugger::Initialize(nullptr); }); + }; +}; + +TEST_F(ProgressReportTest, TestReportCreation) { + std::chrono::milliseconds timeout(100); + + // Set up the debugger, make sure that was done properly. + ArchSpec arch("x86_64-apple-macosx-"); + Platform::SetHostPlatform(PlatformRemoteMacOSX::CreateInstance(true, &arch)); + + DebuggerSP debugger_sp = Debugger::CreateInstance(); + ASSERT_TRUE(debugger_sp); + + // Get the debugger's broadcaster. + Broadcaster &broadcaster = debugger_sp->GetBroadcaster(); + + // Create a listener, make sure it can receive events and that it's + // listening to the correct broadcast bit. + ListenerSP listener_sp = Listener::MakeListener("progress-listener"); + + listener_sp->StartListeningForEvents(&broadcaster, + Debugger::eBroadcastBitProgress); + EXPECT_TRUE( + broadcaster.EventTypeHasListeners(Debugger::eBroadcastBitProgress)); + + EventSP event_sp; + const ProgressEventData *data; + + // Scope this for RAII on the progress objects. + // Create progress reports and check that their respective events for having + // started and ended are broadcasted. + { + Progress progress1("Progress report 1", "Starting report 1"); + Progress progress2("Progress report 2", "Starting report 2"); + Progress progress3("Progress report 3", "Starting report 3"); + } + + // Start popping events from the queue, they should have been recevied + // in this order: + // Starting progress: 1, 2, 3 + // Ending progress: 3, 2, 1 + EXPECT_TRUE(listener_sp->GetEvent(event_sp, timeout)); + data = ProgressEventData::GetEventDataFromEvent(event_sp.get()); + + ASSERT_EQ(data->GetDetails(), "Starting report 1"); + ASSERT_FALSE(data->IsFinite()); + ASSERT_FALSE(data->GetCompleted()); + ASSERT_EQ(data->GetTotal(), Progress::kNonDeterministicTotal); + ASSERT_EQ(data->GetMessage(), "Progress report 1: Starting report 1"); + + EXPECT_TRUE(listener_sp->GetEvent(event_sp, timeout)); + data = ProgressEventData::GetEventDataFromEvent(event_sp.get()); + + ASSERT_EQ(data->GetDetails(), "Starting report 2"); + ASSERT_FALSE(data->IsFinite()); + ASSERT_FALSE(data->GetCompleted()); + ASSERT_EQ(data->GetTotal(), Progress::kNonDeterministicTotal); + ASSERT_EQ(data->GetMessage(), "Progress report 2: Starting report 2"); + + EXPECT_TRUE(listener_sp->GetEvent(event_sp, timeout)); + data = ProgressEventData::GetEventDataFromEvent(event_sp.get()); + ASSERT_EQ(data->GetDetails(), "Starting report 3"); + ASSERT_FALSE(data->IsFinite()); + ASSERT_FALSE(data->GetCompleted()); + ASSERT_EQ(data->GetTotal(), Progress::kNonDeterministicTotal); + ASSERT_EQ(data->GetMessage(), "Progress report 3: Starting report 3"); + + // Progress report objects should be destroyed at this point so + // get each report from the queue and check that they've been + // destroyed in reverse order. + EXPECT_TRUE(listener_sp->GetEvent(event_sp, timeout)); + data = ProgressEventData::GetEventDataFromEvent(event_sp.get()); + + ASSERT_EQ(data->GetTitle(), "Progress report 3"); + ASSERT_TRUE(data->GetCompleted()); + ASSERT_FALSE(data->IsFinite()); + ASSERT_EQ(data->GetMessage(), "Progress report 3: Starting report 3"); + + EXPECT_TRUE(listener_sp->GetEvent(event_sp, timeout)); + data = ProgressEventData::GetEventDataFromEvent(event_sp.get()); + + ASSERT_EQ(data->GetTitle(), "Progress report 2"); + ASSERT_TRUE(data->GetCompleted()); + ASSERT_FALSE(data->IsFinite()); + ASSERT_EQ(data->GetMessage(), "Progress report 2: Starting report 2"); + + EXPECT_TRUE(listener_sp->GetEvent(event_sp, timeout)); + data = ProgressEventData::GetEventDataFromEvent(event_sp.get()); + + ASSERT_EQ(data->GetTitle(), "Progress report 1"); + ASSERT_TRUE(data->GetCompleted()); + ASSERT_FALSE(data->IsFinite()); + ASSERT_EQ(data->GetMessage(), "Progress report 1: Starting report 1"); +} -- GitLab From cdd9221489ec4ed6afc0e5146c2fae4daa8ab260 Mon Sep 17 00:00:00 2001 From: Yingwei Zheng Date: Wed, 7 Feb 2024 03:10:41 +0800 Subject: [PATCH 106/266] [InstCombine] Simplify the overflow result of `umulov X, X` (#80796) This patch does the following folds if only the overflow result is used: ``` extractvalue (umul.with.overflow iN X, X), 1 -> icmp ugt X, 2^(N/2)-1 ``` Alive2: https://alive2.llvm.org/ce/z/a8yPC6 --- .../InstCombine/InstructionCombining.cpp | 11 +++ .../Transforms/InstCombine/umulo-square.ll | 72 +++++++++++++++++++ 2 files changed, 83 insertions(+) create mode 100644 llvm/test/Transforms/InstCombine/umulo-square.ll diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp index dd168917f4dc..4e88a5cc535b 100644 --- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp +++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp @@ -3459,6 +3459,17 @@ InstCombinerImpl::foldExtractOfOverflowIntrinsic(ExtractValueInst &EV) { WO->getLHS()->getType()->isIntOrIntVectorTy(1)) return BinaryOperator::CreateAnd(WO->getLHS(), WO->getRHS()); + // extractvalue (umul_with_overflow X, X), 1 -> X u> 2^(N/2)-1 + if (OvID == Intrinsic::umul_with_overflow && WO->getLHS() == WO->getRHS()) { + unsigned BitWidth = WO->getLHS()->getType()->getScalarSizeInBits(); + // Only handle even bitwidths for performance reasons. + if (BitWidth % 2 == 0) + return new ICmpInst( + ICmpInst::ICMP_UGT, WO->getLHS(), + ConstantInt::get(WO->getLHS()->getType(), + APInt::getLowBitsSet(BitWidth, BitWidth / 2))); + } + // If only the overflow result is used, and the right hand side is a // constant (or constant splat), we can remove the intrinsic by directly // checking for overflow. diff --git a/llvm/test/Transforms/InstCombine/umulo-square.ll b/llvm/test/Transforms/InstCombine/umulo-square.ll new file mode 100644 index 000000000000..838ebc35875b --- /dev/null +++ b/llvm/test/Transforms/InstCombine/umulo-square.ll @@ -0,0 +1,72 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -passes=instcombine -S %s | FileCheck %s + +define i1 @umulov_square_i32(i32 %x) { +; CHECK-LABEL: define i1 @umulov_square_i32( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[RES:%.*]] = icmp ugt i32 [[X]], 65535 +; CHECK-NEXT: ret i1 [[RES]] +; + %ret = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %x, i32 %x) + %res = extractvalue {i32, i1} %ret, 1 + ret i1 %res +} + +define i1 @umulov_square_i16(i16 %x) { +; CHECK-LABEL: define i1 @umulov_square_i16( +; CHECK-SAME: i16 [[X:%.*]]) { +; CHECK-NEXT: [[RES:%.*]] = icmp ugt i16 [[X]], 255 +; CHECK-NEXT: ret i1 [[RES]] +; + %ret = call {i16, i1} @llvm.umul.with.overflow.i16(i16 %x, i16 %x) + %res = extractvalue {i16, i1} %ret, 1 + ret i1 %res +} + +; Negative tests + +define i1 @umulov_square_i13(i13 %x) { +; CHECK-LABEL: define i1 @umulov_square_i13( +; CHECK-SAME: i13 [[X:%.*]]) { +; CHECK-NEXT: [[RET:%.*]] = call { i13, i1 } @llvm.umul.with.overflow.i13(i13 [[X]], i13 [[X]]) +; CHECK-NEXT: [[RES:%.*]] = extractvalue { i13, i1 } [[RET]], 1 +; CHECK-NEXT: ret i1 [[RES]] +; + %ret = call {i13, i1} @llvm.umul.with.overflow.i13(i13 %x, i13 %x) + %res = extractvalue {i13, i1} %ret, 1 + ret i1 %res +} + +define i1 @umulov_square_i32_multiuse(i32 %x) { +; CHECK-LABEL: define i1 @umulov_square_i32_multiuse( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[RET:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[X]], i32 [[X]]) +; CHECK-NEXT: [[RES:%.*]] = extractvalue { i32, i1 } [[RET]], 1 +; CHECK-NEXT: [[VAL:%.*]] = extractvalue { i32, i1 } [[RET]], 0 +; CHECK-NEXT: call void @use(i32 [[VAL]]) +; CHECK-NEXT: ret i1 [[RES]] +; + %ret = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %x, i32 %x) + %res = extractvalue {i32, i1} %ret, 1 + %val = extractvalue {i32, i1} %ret, 0 + call void @use(i32 %val) + ret i1 %res +} + +define i1 @smulov_square_i32(i32 %x) { +; CHECK-LABEL: define i1 @smulov_square_i32( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[RET:%.*]] = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 [[X]], i32 [[X]]) +; CHECK-NEXT: [[RES:%.*]] = extractvalue { i32, i1 } [[RET]], 1 +; CHECK-NEXT: ret i1 [[RES]] +; + %ret = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %x, i32 %x) + %res = extractvalue {i32, i1} %ret, 1 + ret i1 %res +} + +declare {i32, i1} @llvm.umul.with.overflow.i32(i32, i32) +declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32) +declare {i16, i1} @llvm.umul.with.overflow.i16(i16, i16) +declare {i13, i1} @llvm.umul.with.overflow.i13(i13, i13) +declare void @use(i32) -- GitLab From 6812bc40bd6c70f7cae10d1e0a2aeac31cfaef03 Mon Sep 17 00:00:00 2001 From: michaelrj-google <71531609+michaelrj-google@users.noreply.github.com> Date: Tue, 6 Feb 2024 11:16:12 -0800 Subject: [PATCH 107/266] [libc] Fix off by one in long double buffer size (#80889) The size for the long double BLOCK_BUFFER_LEN is calculated based on the properties of the long double type. Somewhere in the calculation, the result was mis-rounded so that the buffer was one element too small. This patch fixes the issue and adds asserts to catch it sooner in the future. --- libc/src/__support/float_to_string.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/libc/src/__support/float_to_string.h b/libc/src/__support/float_to_string.h index 1431aeffa5b2..f30110d47b21 100644 --- a/libc/src/__support/float_to_string.h +++ b/libc/src/__support/float_to_string.h @@ -651,7 +651,8 @@ template <> class FloatToString { int int_block_index = 0; static constexpr size_t BLOCK_BUFFER_LEN = - internal::div_ceil(internal::log10_pow2(FLOAT_AS_INT_WIDTH), BLOCK_SIZE); + internal::div_ceil(internal::log10_pow2(FLOAT_AS_INT_WIDTH), BLOCK_SIZE) + + 1; BlockInt block_buffer[BLOCK_BUFFER_LEN] = {0}; size_t block_buffer_valid = 0; @@ -693,6 +694,7 @@ template <> class FloatToString { int_block_index = 0; while (float_as_int > 0) { + LIBC_ASSERT(int_block_index < static_cast(BLOCK_BUFFER_LEN)); block_buffer[int_block_index] = grab_digits(float_as_int); ++int_block_index; } @@ -785,6 +787,8 @@ public: if (block_index > static_cast(block_buffer_valid) || block_index < 0) return 0; + LIBC_ASSERT(block_index < static_cast(BLOCK_BUFFER_LEN)); + return block_buffer[block_index]; } -- GitLab From 5f87957fefb21d454f2fd7e6b4891350170d8690 Mon Sep 17 00:00:00 2001 From: Adam Magier <83226568+AdamMagierFOSS@users.noreply.github.com> Date: Tue, 6 Feb 2024 13:16:55 -0600 Subject: [PATCH 108/266] [clang][CodeGen][UBSan] Fixing shift-exponent generation for _BitInt (#80515) Testing the shift-exponent check with small width _BitInt values exposed a bug in ScalarExprEmitter::GetWidthMinusOneValue when using the result to determine valid exponent sizes. False positives were reported for some left shifts when width(LHS)-1 > range(RHS) and false negatives were reported for right shifts when value(RHS) > range(LHS). This patch caps the maximum value of GetWidthMinusOneValue to fit within range(RHS) to fix the issue with left shifts and fixes a code generation in EmitShr to fix the issue with right shifts and renames the function to GetMaximumShiftAmount to better reflect the new behaviour. Fixes #80135. Co-authored-by: Adam Magier --- clang/lib/CodeGen/CGExprScalar.cpp | 22 ++++++++++----- clang/test/CodeGen/ubsan-shift-bitint.c | 36 +++++++++++++++++++++++++ 2 files changed, 51 insertions(+), 7 deletions(-) create mode 100644 clang/test/CodeGen/ubsan-shift-bitint.c diff --git a/clang/lib/CodeGen/CGExprScalar.cpp b/clang/lib/CodeGen/CGExprScalar.cpp index 5502f685f647..df8f71cf1d90 100644 --- a/clang/lib/CodeGen/CGExprScalar.cpp +++ b/clang/lib/CodeGen/CGExprScalar.cpp @@ -774,7 +774,7 @@ public: void EmitUndefinedBehaviorIntegerDivAndRemCheck(const BinOpInfo &Ops, llvm::Value *Zero,bool isDiv); // Common helper for getting how wide LHS of shift is. - static Value *GetWidthMinusOneValue(Value* LHS,Value* RHS); + static Value *GetMaximumShiftAmount(Value *LHS, Value *RHS); // Used for shifting constraints for OpenCL, do mask for powers of 2, URem for // non powers of two. @@ -4115,13 +4115,21 @@ Value *ScalarExprEmitter::EmitSub(const BinOpInfo &op) { return Builder.CreateExactSDiv(diffInChars, divisor, "sub.ptr.div"); } -Value *ScalarExprEmitter::GetWidthMinusOneValue(Value* LHS,Value* RHS) { +Value *ScalarExprEmitter::GetMaximumShiftAmount(Value *LHS, Value *RHS) { llvm::IntegerType *Ty; if (llvm::VectorType *VT = dyn_cast(LHS->getType())) Ty = cast(VT->getElementType()); else Ty = cast(LHS->getType()); - return llvm::ConstantInt::get(RHS->getType(), Ty->getBitWidth() - 1); + // For a given type of LHS the maximum shift amount is width(LHS)-1, however + // it can occur that width(LHS)-1 > range(RHS). Since there is no check for + // this in ConstantInt::get, this results in the value getting truncated. + // Constrain the return value to be max(RHS) in this case. + llvm::Type *RHSTy = RHS->getType(); + llvm::APInt RHSMax = llvm::APInt::getMaxValue(RHSTy->getScalarSizeInBits()); + if (RHSMax.ult(Ty->getBitWidth())) + return llvm::ConstantInt::get(RHSTy, RHSMax); + return llvm::ConstantInt::get(RHSTy, Ty->getBitWidth() - 1); } Value *ScalarExprEmitter::ConstrainShiftValue(Value *LHS, Value *RHS, @@ -4133,7 +4141,7 @@ Value *ScalarExprEmitter::ConstrainShiftValue(Value *LHS, Value *RHS, Ty = cast(LHS->getType()); if (llvm::isPowerOf2_64(Ty->getBitWidth())) - return Builder.CreateAnd(RHS, GetWidthMinusOneValue(LHS, RHS), Name); + return Builder.CreateAnd(RHS, GetMaximumShiftAmount(LHS, RHS), Name); return Builder.CreateURem( RHS, llvm::ConstantInt::get(RHS->getType(), Ty->getBitWidth()), Name); @@ -4166,7 +4174,7 @@ Value *ScalarExprEmitter::EmitShl(const BinOpInfo &Ops) { isa(Ops.LHS->getType())) { CodeGenFunction::SanitizerScope SanScope(&CGF); SmallVector, 2> Checks; - llvm::Value *WidthMinusOne = GetWidthMinusOneValue(Ops.LHS, Ops.RHS); + llvm::Value *WidthMinusOne = GetMaximumShiftAmount(Ops.LHS, Ops.RHS); llvm::Value *ValidExponent = Builder.CreateICmpULE(Ops.RHS, WidthMinusOne); if (SanitizeExponent) { @@ -4184,7 +4192,7 @@ Value *ScalarExprEmitter::EmitShl(const BinOpInfo &Ops) { Builder.CreateCondBr(ValidExponent, CheckShiftBase, Cont); llvm::Value *PromotedWidthMinusOne = (RHS == Ops.RHS) ? WidthMinusOne - : GetWidthMinusOneValue(Ops.LHS, RHS); + : GetMaximumShiftAmount(Ops.LHS, RHS); CGF.EmitBlock(CheckShiftBase); llvm::Value *BitsShiftedOff = Builder.CreateLShr( Ops.LHS, Builder.CreateSub(PromotedWidthMinusOne, RHS, "shl.zeros", @@ -4235,7 +4243,7 @@ Value *ScalarExprEmitter::EmitShr(const BinOpInfo &Ops) { isa(Ops.LHS->getType())) { CodeGenFunction::SanitizerScope SanScope(&CGF); llvm::Value *Valid = - Builder.CreateICmpULE(RHS, GetWidthMinusOneValue(Ops.LHS, RHS)); + Builder.CreateICmpULE(Ops.RHS, GetMaximumShiftAmount(Ops.LHS, Ops.RHS)); EmitBinOpCheck(std::make_pair(Valid, SanitizerKind::ShiftExponent), Ops); } diff --git a/clang/test/CodeGen/ubsan-shift-bitint.c b/clang/test/CodeGen/ubsan-shift-bitint.c new file mode 100644 index 000000000000..844d5c4ad846 --- /dev/null +++ b/clang/test/CodeGen/ubsan-shift-bitint.c @@ -0,0 +1,36 @@ +// RUN: %clang_cc1 %s -O0 -fsanitize=shift-exponent -emit-llvm -std=c2x -triple=x86_64-unknown-linux -o - | FileCheck %s + +// Checking that the code generation is using the unextended/untruncated +// exponent values and capping the values accordingly + +// CHECK-LABEL: define{{.*}} i32 @test_left_variable +int test_left_variable(unsigned _BitInt(5) b, unsigned _BitInt(2) e) { + // CHECK: [[E_REG:%.+]] = load [[E_SIZE:i2]] + // CHECK: icmp ule [[E_SIZE]] [[E_REG]], -1 + return b << e; +} + +// CHECK-LABEL: define{{.*}} i32 @test_right_variable +int test_right_variable(unsigned _BitInt(2) b, unsigned _BitInt(3) e) { + // CHECK: [[E_REG:%.+]] = load [[E_SIZE:i3]] + // CHECK: icmp ule [[E_SIZE]] [[E_REG]], 1 + return b >> e; +} + +// Old code generation would give false positives on left shifts when: +// value(e) > (width(b) - 1 % 2 ** width(e)) +// CHECK-LABEL: define{{.*}} i32 @test_left_literal +int test_left_literal(unsigned _BitInt(5) b) { + // CHECK-NOT: br i1 false, label %cont, label %handler.shift_out_of_bounds + // CHECK: br i1 true, label %cont, label %handler.shift_out_of_bounds + return b << 3uwb; +} + +// Old code generation would give false positives on right shifts when: +// (value(e) % 2 ** width(b)) < width(b) +// CHECK-LABEL: define{{.*}} i32 @test_right_literal +int test_right_literal(unsigned _BitInt(2) b) { + // CHECK-NOT: br i1 true, label %cont, label %handler.shift_out_of_bounds + // CHECK: br i1 false, label %cont, label %handler.shift_out_of_bounds + return b >> 4uwb; +} -- GitLab From c6691f689e9aa787b809fd3493bae8a5ca845cea Mon Sep 17 00:00:00 2001 From: michaelrj-google <71531609+michaelrj-google@users.noreply.github.com> Date: Tue, 6 Feb 2024 11:16:59 -0800 Subject: [PATCH 109/266] [libc] Fix pread under msan (#80893) The pread function wasn't properly unpoisoning its result under msan, causing test failures downstream when I tried to roll it out. This patch adds the msan unpoison call that fixes the issue. --- libc/src/unistd/linux/CMakeLists.txt | 2 ++ libc/src/unistd/linux/pread.cpp | 5 ++++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/libc/src/unistd/linux/CMakeLists.txt b/libc/src/unistd/linux/CMakeLists.txt index 42190079141b..df85d44e9e9e 100644 --- a/libc/src/unistd/linux/CMakeLists.txt +++ b/libc/src/unistd/linux/CMakeLists.txt @@ -283,6 +283,7 @@ add_entrypoint_object( libc.include.unistd libc.include.sys_syscall libc.src.__support.OSUtil.osutil + libc.src.__support.macros.sanitizer libc.src.errno.errno ) @@ -309,6 +310,7 @@ add_entrypoint_object( libc.include.unistd libc.include.sys_syscall libc.src.__support.OSUtil.osutil + libc.src.__support.macros.sanitizer libc.src.errno.errno ) diff --git a/libc/src/unistd/linux/pread.cpp b/libc/src/unistd/linux/pread.cpp index 614de9732c62..11cefc5c2f3a 100644 --- a/libc/src/unistd/linux/pread.cpp +++ b/libc/src/unistd/linux/pread.cpp @@ -10,7 +10,7 @@ #include "src/__support/OSUtil/syscall.h" // For internal syscall function. #include "src/__support/common.h" - +#include "src/__support/macros/sanitizer.h" // for MSAN_UNPOISON #include "src/errno/libc_errno.h" #include // For uint64_t. #include // For syscall numbers. @@ -28,6 +28,9 @@ LLVM_LIBC_FUNCTION(ssize_t, pread, ssize_t ret = LIBC_NAMESPACE::syscall_impl(SYS_pread64, fd, buf, count, offset); #endif + // The cast is important since there is a check that dereferences the pointer + // which fails on void*. + MSAN_UNPOISON(reinterpret_cast(buf), count); if (ret < 0) { libc_errno = static_cast(-ret); return -1; -- GitLab From ce00fdc91cb7a466054c3ffd8788ae2f9f5100f3 Mon Sep 17 00:00:00 2001 From: Heejin Ahn Date: Tue, 6 Feb 2024 11:19:46 -0800 Subject: [PATCH 110/266] [WebAssembly] Cleanup feature tests (#80780) This adds missing features to the tests and removes a stale feature (unimplemented_simd128) from them. --- clang/test/Driver/wasm-features.c | 80 +++++++++++++++++++ .../test/Preprocessor/wasm-target-features.c | 3 +- 2 files changed, 82 insertions(+), 1 deletion(-) diff --git a/clang/test/Driver/wasm-features.c b/clang/test/Driver/wasm-features.c index 1a43361a4a10..4fba3da7bea2 100644 --- a/clang/test/Driver/wasm-features.c +++ b/clang/test/Driver/wasm-features.c @@ -42,6 +42,16 @@ // MVP-NOT: "-target-feature" "+nontrapping-fptoint" // BLEEDING-EDGE-NOT: "-target-feature" "-nontrapping-fptoint" +// RUN: %clang --target=wasm32-unknown-unknown -### %s -mmultivalue 2>&1 | FileCheck %s -check-prefix=MULTIVALUE +// RUN: %clang --target=wasm32-unknown-unknown -### %s -mno-multivalue 2>&1 | FileCheck %s -check-prefix=NO-MULTIVALUE + +// MULTIVALUE: "-target-feature" "+multivalue" +// NO-MULTIVALUE: "-target-feature" "-multivalue" +// DEFAULT-NOT: "-target-feature" "-multivalue" +// MVP-NOT: "-target-feature" "+multivalue" +// GENERIC-NOT: "-target-feature" "+multivalue" +// BLEEDING-EDGE-NOT: "-target-feature" "-multivalue" + // RUN: %clang --target=wasm32-unknown-unknown -### %s -mmultimemory 2>&1 | FileCheck %s -check-prefix=MULTIMEMORY // RUN: %clang --target=wasm32-unknown-unknown -### %s -mno-multimemory 2>&1 | FileCheck %s -check-prefix=NO-MULTIMEMORY @@ -50,3 +60,73 @@ // DEFAULT-NOT: "-target-feature" "-multimemory" // MVP-NOT: "-target-feature" "+multimemory" // BLEEDING-EDGE-NOT: "-target-feature" "-multimemory" + +// RUN: %clang --target=wasm32-unknown-unknown -### %s -matomics 2>&1 | FileCheck %s -check-prefix=ATOMICS +// RUN: %clang --target=wasm32-unknown-unknown -### %s -mno-atomics 2>&1 | FileCheck %s -check-prefix=NO-ATOMICS + +// ATOMICS: "-target-feature" "+atomics" +// NO-ATOMICS: "-target-feature" "-atomics" +// DEFAULT-NOT: "-target-feature" "-atomics" +// MVP-NOT: "-target-feature" "+atomics" +// GENERIC-NOT: "-target-feature" "+atomics" +// BLEEDING-EDGE-NOT: "-target-feature" "-atomics" + +// RUN: %clang --target=wasm32-unknown-unknown -### %s -mtail-call 2>&1 | FileCheck %s -check-prefix=TAIL-CALL +// RUN: %clang --target=wasm32-unknown-unknown -### %s -mno-tail-call 2>&1 | FileCheck %s -check-prefix=NO-TAIL-CALL + +// TAIL-CALL: "-target-feature" "+tail-call" +// NO-TAIL-CALL: "-target-feature" "-tail-call" +// DEFAULT-NOT: "-target-feature" "-tail-call" +// MVP-NOT: "-target-feature" "+tail-call" +// GENERIC-NOT: "-target-feature" "+tail-call" +// BLEEDING-EDGE-NOT: "-target-feature" "-tail-call" + +// RUN: %clang --target=wasm32-unknown-unknown -### %s -mreference-types 2>&1 | FileCheck %s -check-prefix=REFERENCE-TYPES +// RUN: %clang --target=wasm32-unknown-unknown -### %s -mno-reference-types 2>&1 | FileCheck %s -check-prefix=NO-REFERENCE-TYPES + +// REFERENCE-TYPES: "-target-feature" "+reference-types" +// NO-REFERENCE-TYPES: "-target-feature" "-reference-types" +// DEFAULT-NOT: "-target-feature" "-reference-types" +// MVP-NOT: "-target-feature" "+reference-types" +// GENERIC-NOT: "-target-feature" "+reference-types" +// BLEEDING-EDGE-NOT: "-target-feature" "-reference-types" + +// RUN: %clang --target=wasm32-unknown-unknown -### %s -msimd128 2>&1 | FileCheck %s -check-prefix=SIMD128 +// RUN: %clang --target=wasm32-unknown-unknown -### %s -mno-simd128 2>&1 | FileCheck %s -check-prefix=NO-SIMD128 + +// SIMD128: "-target-feature" "+simd128" +// NO-SIMD128: "-target-feature" "-simd128" +// DEFAULT-NOT: "-target-feature" "-simd128" +// MVP-NOT: "-target-feature" "+simd128" +// GENERIC-NOT: "-target-feature" "+simd128" +// BLEEDING-EDGE-NOT: "-target-feature" "+simd128" + +// RUN: %clang --target=wasm32-unknown-unknown -### %s -mrelaxed-simd 2>&1 | FileCheck %s -check-prefix=RELAXED-SIMD +// RUN: %clang --target=wasm32-unknown-unknown -### %s -mno-relaxed-simd 2>&1 | FileCheck %s -check-prefix=NO-RELAXED-SIMD + +// RELAXED-SIMD: "-target-feature" "+relaxed-simd" +// NO-RELAXED-SIMD: "-target-feature" "-relaxed-simd" +// DEFAULT-NOT: "-target-feature" "-relaxed-simd" +// MVP-NOT: "-target-feature" "+relaxed-simd" +// GENERIC-NOT: "-target-feature" "+relaxed-simd" +// BLEEDING-EDGE-NOT: "-target-feature" "+relaxed-simd" + +// RUN: %clang --target=wasm32-unknown-unknown -### %s -mexception-handling 2>&1 | FileCheck %s -check-prefix=EXCEPTION-HANDLING +// RUN: %clang --target=wasm32-unknown-unknown -### %s -mno-exception-handling 2>&1 | FileCheck %s -check-prefix=NO-EXCEPTION-HANDLING + +// EXCEPTION-HANDLING: "-target-feature" "+exception-handling" +// NO-EXCEPTION-HANDLING: "-target-feature" "-exception-handling" +// DEFAULT-NOT: "-target-feature" "-exception-handling" +// MVP-NOT: "-target-feature" "+exception-handling" +// GENERIC-NOT: "-target-feature" "+exception-handling" +// BLEEDING-EDGE-NOT: "-target-feature" "+exception-handling" + +// RUN: %clang --target=wasm32-unknown-unknown -### %s -mextended-const 2>&1 | FileCheck %s -check-prefix=EXTENDED-CONST +// RUN: %clang --target=wasm32-unknown-unknown -### %s -mno-extended-const 2>&1 | FileCheck %s -check-prefix=NO-EXTENDED-CONST + +// EXTENDED-CONST: "-target-feature" "+extended-const" +// NO-EXTENDED-CONST: "-target-feature" "-extended-const" +// DEFAULT-NOT: "-target-feature" "-extended-const" +// MVP-NOT: "-target-feature" "+extended-const" +// GENERIC-NOT: "-target-feature" "+extended-const" +// BLEEDING-EDGE-NOT: "-target-feature" "+extended-const" diff --git a/clang/test/Preprocessor/wasm-target-features.c b/clang/test/Preprocessor/wasm-target-features.c index c225e226b69b..e50c5a4afe79 100644 --- a/clang/test/Preprocessor/wasm-target-features.c +++ b/clang/test/Preprocessor/wasm-target-features.c @@ -144,6 +144,7 @@ // MVP-NOT:#define __wasm_reference_types__ // MVP-NOT:#define __wasm_extended_const__ // MVP-NOT:#define __wasm_multimemory__ +// MVP-NOT:#define __wasm_relaxed_simd__ // RUN: %clang -E -dM %s -o - 2>&1 \ // RUN: -target wasm32-unknown-unknown -mcpu=bleeding-edge \ @@ -160,11 +161,11 @@ // BLEEDING-EDGE-DAG:#define __wasm_mutable_globals__ 1{{$}} // BLEEDING-EDGE-DAG:#define __wasm_tail_call__ 1{{$}} // BLEEDING-EDGE-DAG:#define __wasm_multimemory__ 1{{$}} -// BLEEDING-EDGE-NOT:#define __wasm_unimplemented_simd128__ 1{{$}} // BLEEDING-EDGE-NOT:#define __wasm_exception_handling__ 1{{$}} // BLEEDING-EDGE-NOT:#define __wasm_multivalue__ 1{{$}} // BLEEDING-EDGE-NOT:#define __wasm_reference_types__ 1{{$}} // BLEEDING-EDGE-NOT:#define __wasm_extended_const__ 1{{$}} +// BLEEDING-EDGE-NOT:#define __wasm_relaxed_simd__ 1{{$}} // RUN: %clang -E -dM %s -o - 2>&1 \ // RUN: -target wasm32-unknown-unknown -mcpu=bleeding-edge -mno-simd128 \ -- GitLab From 5b780c8c6c558ec283a9eec485a4f172df0f9fe1 Mon Sep 17 00:00:00 2001 From: PiJoules <6019989+PiJoules@users.noreply.github.com> Date: Tue, 6 Feb 2024 11:29:30 -0800 Subject: [PATCH 111/266] Diagnose invalid fixed point conversion (#80763) --- clang/include/clang/AST/Type.h | 7 +++++++ clang/lib/Sema/SemaOverload.cpp | 5 ++++- clang/test/Frontend/fixed_point_errors.cpp | 4 ++++ 3 files changed, 15 insertions(+), 1 deletion(-) diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h index d6a55f39a4be..1942b0e67f65 100644 --- a/clang/include/clang/AST/Type.h +++ b/clang/include/clang/AST/Type.h @@ -2613,6 +2613,9 @@ public: /// Return true if this is a fixed point or integer type. bool isFixedPointOrIntegerType() const; + /// Return true if this can be converted to (or from) a fixed point type. + bool isConvertibleToFixedPointType() const; + /// Return true if this is a saturated fixed point type according to /// ISO/IEC JTC1 SC22 WG14 N1169. This type can be signed or unsigned. bool isSaturatedFixedPointType() const; @@ -7493,6 +7496,10 @@ inline bool Type::isFixedPointOrIntegerType() const { return isFixedPointType() || isIntegerType(); } +inline bool Type::isConvertibleToFixedPointType() const { + return isRealFloatingType() || isFixedPointOrIntegerType(); +} + inline bool Type::isSaturatedFixedPointType() const { if (const auto *BT = dyn_cast(CanonicalType)) { return BT->getKind() >= BuiltinType::SatShortAccum && diff --git a/clang/lib/Sema/SemaOverload.cpp b/clang/lib/Sema/SemaOverload.cpp index 6a04d68b4f04..c46f6338a5a1 100644 --- a/clang/lib/Sema/SemaOverload.cpp +++ b/clang/lib/Sema/SemaOverload.cpp @@ -2177,7 +2177,10 @@ static bool IsStandardConversion(Sema &S, Expr* From, QualType ToType, From->isIntegerConstantExpr(S.getASTContext())) { SCS.Second = ICK_Compatible_Conversion; FromType = ToType; - } else if (ToType->isFixedPointType() || FromType->isFixedPointType()) { + } else if ((ToType->isFixedPointType() && + FromType->isConvertibleToFixedPointType()) || + (FromType->isFixedPointType() && + ToType->isConvertibleToFixedPointType())) { SCS.Second = ICK_Fixed_Point_Conversion; FromType = ToType; } else { diff --git a/clang/test/Frontend/fixed_point_errors.cpp b/clang/test/Frontend/fixed_point_errors.cpp index 4097cd73c845..ef064bc38873 100644 --- a/clang/test/Frontend/fixed_point_errors.cpp +++ b/clang/test/Frontend/fixed_point_errors.cpp @@ -14,3 +14,7 @@ int fract_int = 10r; // expected-error{{invalid suffix 'r' on integer consta float accum_flt = 0.0k; // expected-error{{invalid suffix 'k' on floating constant}} float fract_flt = 0.0r; // expected-error{{invalid suffix 'r' on floating constant}} #endif + +#ifndef WITHOUT_FIXED_POINT +const char *c = 10.0k; // expected-error{{cannot initialize a variable of type 'const char *' with an rvalue of type '_Accum'}} +#endif -- GitLab From 5ce2f73b2e5e6664d74b49ee45f11505f8306577 Mon Sep 17 00:00:00 2001 From: Jeremy Morse Date: Tue, 6 Feb 2024 19:23:11 +0000 Subject: [PATCH 112/266] [DebugInfo][RemoveDIs] Add some missing test coverage In github PR #78731 it looks like I added test coverage for RemoveDIs to either the wrong test, or not enough. Adding --try-experimental-debuginfo-iterators to this particular test is enough to restore some coverage it seems. --- llvm/test/CodeGen/AArch64/stack-tagging-dbg.ll | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/test/CodeGen/AArch64/stack-tagging-dbg.ll b/llvm/test/CodeGen/AArch64/stack-tagging-dbg.ll index 8b6c0c86bb4e..ba8c76348b9b 100644 --- a/llvm/test/CodeGen/AArch64/stack-tagging-dbg.ll +++ b/llvm/test/CodeGen/AArch64/stack-tagging-dbg.ll @@ -1,4 +1,5 @@ ; RUN: opt < %s -aarch64-stack-tagging -S -o - | FileCheck %s +; RUN: opt < %s -aarch64-stack-tagging -S -o - --try-experimental-debuginfo-iterators | FileCheck %s target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64--linux-android" -- GitLab From c13e271a38363d354294e2af1651470bed8facb3 Mon Sep 17 00:00:00 2001 From: Bhuminjay Soni Date: Wed, 7 Feb 2024 01:27:34 +0530 Subject: [PATCH 113/266] Add clang-tidy check to suggest replacement of conditional statement with std::min/std::max (#77816) This pull request fixes #64914 where author suggests adding a readability check to propose the replacement of conditional statements with std::min/std::max for improved code readability. Additionally, reference is made to PyLint's similar checks: [consider-using-min-builtin](https://pylint.pycqa.org/en/latest/user_guide/messages/refactor/consider-using-min-builtin.html) and [consider-using-max-builtin](https://pylint.pycqa.org/en/latest/user_guide/messages/refactor/consider-using-max-builtin.html) --- .../clang-tidy/readability/CMakeLists.txt | 1 + .../readability/ReadabilityTidyModule.cpp | 3 + .../readability/UseStdMinMaxCheck.cpp | 188 +++++++++++++ .../readability/UseStdMinMaxCheck.h | 42 +++ clang-tools-extra/docs/ReleaseNotes.rst | 6 + .../docs/clang-tidy/checks/list.rst | 1 + .../checks/readability/use-std-min-max.rst | 29 ++ .../checkers/readability/use-std-min-max.cpp | 254 ++++++++++++++++++ 8 files changed, 524 insertions(+) create mode 100644 clang-tools-extra/clang-tidy/readability/UseStdMinMaxCheck.cpp create mode 100644 clang-tools-extra/clang-tidy/readability/UseStdMinMaxCheck.h create mode 100644 clang-tools-extra/docs/clang-tidy/checks/readability/use-std-min-max.rst create mode 100644 clang-tools-extra/test/clang-tidy/checkers/readability/use-std-min-max.cpp diff --git a/clang-tools-extra/clang-tidy/readability/CMakeLists.txt b/clang-tools-extra/clang-tidy/readability/CMakeLists.txt index a6c8cbd8eb44..5728c9970fb6 100644 --- a/clang-tools-extra/clang-tidy/readability/CMakeLists.txt +++ b/clang-tools-extra/clang-tidy/readability/CMakeLists.txt @@ -55,6 +55,7 @@ add_clang_library(clangTidyReadabilityModule UniqueptrDeleteReleaseCheck.cpp UppercaseLiteralSuffixCheck.cpp UseAnyOfAllOfCheck.cpp + UseStdMinMaxCheck.cpp LINK_LIBS clangTidy diff --git a/clang-tools-extra/clang-tidy/readability/ReadabilityTidyModule.cpp b/clang-tools-extra/clang-tidy/readability/ReadabilityTidyModule.cpp index 87b299bf1ef1..bca2c425111f 100644 --- a/clang-tools-extra/clang-tidy/readability/ReadabilityTidyModule.cpp +++ b/clang-tools-extra/clang-tidy/readability/ReadabilityTidyModule.cpp @@ -58,6 +58,7 @@ #include "UniqueptrDeleteReleaseCheck.h" #include "UppercaseLiteralSuffixCheck.h" #include "UseAnyOfAllOfCheck.h" +#include "UseStdMinMaxCheck.h" namespace clang::tidy { namespace readability { @@ -163,6 +164,8 @@ public: "readability-uppercase-literal-suffix"); CheckFactories.registerCheck( "readability-use-anyofallof"); + CheckFactories.registerCheck( + "readability-use-std-min-max"); } }; diff --git a/clang-tools-extra/clang-tidy/readability/UseStdMinMaxCheck.cpp b/clang-tools-extra/clang-tidy/readability/UseStdMinMaxCheck.cpp new file mode 100644 index 000000000000..9c5c2f3939c9 --- /dev/null +++ b/clang-tools-extra/clang-tidy/readability/UseStdMinMaxCheck.cpp @@ -0,0 +1,188 @@ +//===--- UseStdMinMaxCheck.cpp - clang-tidy -------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "UseStdMinMaxCheck.h" +#include "../utils/ASTUtils.h" +#include "clang/AST/ASTContext.h" +#include "clang/ASTMatchers/ASTMatchFinder.h" +#include "clang/Lex/Preprocessor.h" + +using namespace clang::ast_matchers; + +namespace clang::tidy::readability { + +namespace { + +// Ignore if statements that are inside macros. +AST_MATCHER(IfStmt, isIfInMacro) { + return Node.getIfLoc().isMacroID() || Node.getEndLoc().isMacroID(); +} + +} // namespace + +static const llvm::StringRef AlgorithmHeader(""); + +static bool minCondition(const BinaryOperator::Opcode Op, const Expr *CondLhs, + const Expr *CondRhs, const Expr *AssignLhs, + const Expr *AssignRhs, const ASTContext &Context) { + if ((Op == BO_LT || Op == BO_LE) && + (tidy::utils::areStatementsIdentical(CondLhs, AssignRhs, Context) && + tidy::utils::areStatementsIdentical(CondRhs, AssignLhs, Context))) + return true; + + if ((Op == BO_GT || Op == BO_GE) && + (tidy::utils::areStatementsIdentical(CondLhs, AssignLhs, Context) && + tidy::utils::areStatementsIdentical(CondRhs, AssignRhs, Context))) + return true; + + return false; +} + +static bool maxCondition(const BinaryOperator::Opcode Op, const Expr *CondLhs, + const Expr *CondRhs, const Expr *AssignLhs, + const Expr *AssignRhs, const ASTContext &Context) { + if ((Op == BO_LT || Op == BO_LE) && + (tidy::utils::areStatementsIdentical(CondLhs, AssignLhs, Context) && + tidy::utils::areStatementsIdentical(CondRhs, AssignRhs, Context))) + return true; + + if ((Op == BO_GT || Op == BO_GE) && + (tidy::utils::areStatementsIdentical(CondLhs, AssignRhs, Context) && + tidy::utils::areStatementsIdentical(CondRhs, AssignLhs, Context))) + return true; + + return false; +} + +QualType getNonTemplateAlias(QualType QT) { + while (true) { + // cast to a TypedefType + if (const TypedefType *TT = dyn_cast(QT)) { + // check if the typedef is a template and if it is dependent + if (!TT->getDecl()->getDescribedTemplate() && + !TT->getDecl()->getDeclContext()->isDependentContext()) + return QT; + QT = TT->getDecl()->getUnderlyingType(); + } + // cast to elaborated type + else if (const ElaboratedType *ET = dyn_cast(QT)) { + QT = ET->getNamedType(); + } else { + break; + } + } + return QT; +} + +static std::string createReplacement(const Expr *CondLhs, const Expr *CondRhs, + const Expr *AssignLhs, + const SourceManager &Source, + const LangOptions &LO, + StringRef FunctionName, + const BinaryOperator *BO) { + const llvm::StringRef CondLhsStr = Lexer::getSourceText( + Source.getExpansionRange(CondLhs->getSourceRange()), Source, LO); + const llvm::StringRef CondRhsStr = Lexer::getSourceText( + Source.getExpansionRange(CondRhs->getSourceRange()), Source, LO); + const llvm::StringRef AssignLhsStr = Lexer::getSourceText( + Source.getExpansionRange(AssignLhs->getSourceRange()), Source, LO); + + clang::QualType GlobalImplicitCastType; + clang::QualType LhsType = CondLhs->getType() + .getCanonicalType() + .getNonReferenceType() + .getUnqualifiedType(); + clang::QualType RhsType = CondRhs->getType() + .getCanonicalType() + .getNonReferenceType() + .getUnqualifiedType(); + if (LhsType != RhsType) { + GlobalImplicitCastType = getNonTemplateAlias(BO->getLHS()->getType()); + } + + return (AssignLhsStr + " = " + FunctionName + + (!GlobalImplicitCastType.isNull() + ? "<" + GlobalImplicitCastType.getAsString() + ">(" + : "(") + + CondLhsStr + ", " + CondRhsStr + ");") + .str(); +} + +UseStdMinMaxCheck::UseStdMinMaxCheck(StringRef Name, ClangTidyContext *Context) + : ClangTidyCheck(Name, Context), + IncludeInserter(Options.getLocalOrGlobal("IncludeStyle", + utils::IncludeSorter::IS_LLVM), + areDiagsSelfContained()) {} + +void UseStdMinMaxCheck::storeOptions(ClangTidyOptions::OptionMap &Opts) { + Options.store(Opts, "IncludeStyle", IncludeInserter.getStyle()); +} + +void UseStdMinMaxCheck::registerMatchers(MatchFinder *Finder) { + auto AssignOperator = + binaryOperator(hasOperatorName("="), + hasLHS(expr(unless(isTypeDependent())).bind("AssignLhs")), + hasRHS(expr(unless(isTypeDependent())).bind("AssignRhs"))); + auto BinaryOperator = + binaryOperator(hasAnyOperatorName("<", ">", "<=", ">="), + hasLHS(expr(unless(isTypeDependent())).bind("CondLhs")), + hasRHS(expr(unless(isTypeDependent())).bind("CondRhs"))) + .bind("binaryOp"); + Finder->addMatcher( + ifStmt(stmt().bind("if"), unless(isIfInMacro()), + unless(hasElse(stmt())), // Ensure `if` has no `else` + hasCondition(BinaryOperator), + hasThen( + anyOf(stmt(AssignOperator), + compoundStmt(statementCountIs(1), has(AssignOperator)))), + hasParent(stmt(unless(ifStmt(hasElse( + equalsBoundNode("if"))))))), // Ensure `if` has no `else if` + this); +} + +void UseStdMinMaxCheck::registerPPCallbacks(const SourceManager &SM, + Preprocessor *PP, + Preprocessor *ModuleExpanderPP) { + IncludeInserter.registerPreprocessor(PP); +} + +void UseStdMinMaxCheck::check(const MatchFinder::MatchResult &Result) { + const auto *If = Result.Nodes.getNodeAs("if"); + const clang::LangOptions &LO = Result.Context->getLangOpts(); + const auto *CondLhs = Result.Nodes.getNodeAs("CondLhs"); + const auto *CondRhs = Result.Nodes.getNodeAs("CondRhs"); + const auto *AssignLhs = Result.Nodes.getNodeAs("AssignLhs"); + const auto *AssignRhs = Result.Nodes.getNodeAs("AssignRhs"); + const auto *BinaryOp = Result.Nodes.getNodeAs("binaryOp"); + const clang::BinaryOperatorKind BinaryOpcode = BinaryOp->getOpcode(); + const SourceLocation IfLocation = If->getIfLoc(); + const SourceLocation ThenLocation = If->getEndLoc(); + + auto ReplaceAndDiagnose = [&](const llvm::StringRef FunctionName) { + const SourceManager &Source = *Result.SourceManager; + diag(IfLocation, "use `%0` instead of `%1`") + << FunctionName << BinaryOp->getOpcodeStr() + << FixItHint::CreateReplacement( + SourceRange(IfLocation, Lexer::getLocForEndOfToken( + ThenLocation, 0, Source, LO)), + createReplacement(CondLhs, CondRhs, AssignLhs, Source, LO, + FunctionName, BinaryOp)) + << IncludeInserter.createIncludeInsertion( + Source.getFileID(If->getBeginLoc()), AlgorithmHeader); + }; + + if (minCondition(BinaryOpcode, CondLhs, CondRhs, AssignLhs, AssignRhs, + (*Result.Context))) { + ReplaceAndDiagnose("std::min"); + } else if (maxCondition(BinaryOpcode, CondLhs, CondRhs, AssignLhs, AssignRhs, + (*Result.Context))) { + ReplaceAndDiagnose("std::max"); + } +} + +} // namespace clang::tidy::readability diff --git a/clang-tools-extra/clang-tidy/readability/UseStdMinMaxCheck.h b/clang-tools-extra/clang-tidy/readability/UseStdMinMaxCheck.h new file mode 100644 index 000000000000..b8d8b8c4fe89 --- /dev/null +++ b/clang-tools-extra/clang-tidy/readability/UseStdMinMaxCheck.h @@ -0,0 +1,42 @@ +//===--- UseStdMinMaxCheck.h - clang-tidy -----------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_READABILITY_USESTDMINMAXCHECK_H +#define LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_READABILITY_USESTDMINMAXCHECK_H + +#include "../ClangTidyCheck.h" +#include "../utils/IncludeInserter.h" + +namespace clang::tidy::readability { + +/// Replaces certain conditional statements with equivalent calls to +/// ``std::min`` or ``std::max``. +/// For the user-facing documentation see: +/// http://clang.llvm.org/extra/clang-tidy/checks/readability/UseStdMinMax.html +class UseStdMinMaxCheck : public ClangTidyCheck { +public: + UseStdMinMaxCheck(StringRef Name, ClangTidyContext *Context); + bool isLanguageVersionSupported(const LangOptions &LangOpts) const override { + return LangOpts.CPlusPlus; + } + void registerPPCallbacks(const SourceManager &SM, Preprocessor *PP, + Preprocessor *ModuleExpanderPP) override; + void storeOptions(ClangTidyOptions::OptionMap &Opts) override; + void registerMatchers(ast_matchers::MatchFinder *Finder) override; + void check(const ast_matchers::MatchFinder::MatchResult &Result) override; + std::optional getCheckTraversalKind() const override { + return TK_IgnoreUnlessSpelledInSource; + } + +private: + utils::IncludeInserter IncludeInserter; +}; + +} // namespace clang::tidy::readability + +#endif // LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_READABILITY_USESTDMINMAXCHECK_H diff --git a/clang-tools-extra/docs/ReleaseNotes.rst b/clang-tools-extra/docs/ReleaseNotes.rst index 16309bd89bda..e50914aed5f0 100644 --- a/clang-tools-extra/docs/ReleaseNotes.rst +++ b/clang-tools-extra/docs/ReleaseNotes.rst @@ -100,6 +100,12 @@ Improvements to clang-tidy New checks ^^^^^^^^^^ +- New :doc:`readability-use-std-min-max + ` check. + + Replaces certain conditional statements with equivalent calls to + ``std::min`` or ``std::max``. + New check aliases ^^^^^^^^^^^^^^^^^ diff --git a/clang-tools-extra/docs/clang-tidy/checks/list.rst b/clang-tools-extra/docs/clang-tidy/checks/list.rst index f40192ed9dea..59ef69f390ee 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/list.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/list.rst @@ -385,6 +385,7 @@ Clang-Tidy Checks :doc:`readability-uniqueptr-delete-release `, "Yes" :doc:`readability-uppercase-literal-suffix `, "Yes" :doc:`readability-use-anyofallof `, + :doc:`readability-use-std-min-max `, "Yes" :doc:`zircon-temporary-objects `, diff --git a/clang-tools-extra/docs/clang-tidy/checks/readability/use-std-min-max.rst b/clang-tools-extra/docs/clang-tidy/checks/readability/use-std-min-max.rst new file mode 100644 index 000000000000..73712bdba83b --- /dev/null +++ b/clang-tools-extra/docs/clang-tidy/checks/readability/use-std-min-max.rst @@ -0,0 +1,29 @@ +.. title:: clang-tidy - readability-use-std-min-max + +readability-use-std-min-max +=========================== + +Replaces certain conditional statements with equivalent calls to +``std::min`` or ``std::max``. +Note: This may impact performance in critical code due to potential +additional stores compared to the original if statement. + +Before: + +.. code-block:: c++ + + void foo() { + int a = 2, b = 3; + if (a < b) + a = b; + } + + +After: + +.. code-block:: c++ + + void foo() { + int a = 2, b = 3; + a = std::max(a, b); + } diff --git a/clang-tools-extra/test/clang-tidy/checkers/readability/use-std-min-max.cpp b/clang-tools-extra/test/clang-tidy/checkers/readability/use-std-min-max.cpp new file mode 100644 index 000000000000..9c0e2eabda34 --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/checkers/readability/use-std-min-max.cpp @@ -0,0 +1,254 @@ +// RUN: %check_clang_tidy -std=c++11-or-later %s readability-use-std-min-max %t -- -- -fno-delayed-template-parsing +#define MY_MACRO_MIN(a, b) ((a) < (b) ? (a) : (b)) + +constexpr int myConstexprMin(int a, int b) { + return a < b ? a : b; +} + +constexpr int myConstexprMax(int a, int b) { + return a > b ? a : b; +} + +#define MY_IF_MACRO(condition, statement) \ + if (condition) { \ + statement \ + } + +class MyClass { +public: + int member1; + int member2; +}; + +template + +void foo(T value7) { + int value1,value2,value3; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::max` instead of `<` [readability-use-std-min-max] + // CHECK-FIXES: value1 = std::max(value1, value2); + if (value1 < value2) + value1 = value2; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::min` instead of `<` [readability-use-std-min-max] + // CHECK-FIXES: value2 = std::min(value1, value2); + if (value1 < value2) + value2 = value1; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::min` instead of `>` [readability-use-std-min-max] + // CHECK-FIXES: value2 = std::min(value2, value1); + if (value2 > value1) + value2 = value1; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::max` instead of `>` [readability-use-std-min-max] + // CHECK-FIXES: value1 = std::max(value2, value1); + if (value2 > value1) + value1 = value2; + + // No suggestion needed here + if (value1 == value2) + value1 = value2; + + // CHECK-MESSAGES: :[[@LINE+3]]:3: warning: use `std::max` instead of `<` [readability-use-std-min-max] + // CHECK-FIXES: value1 = std::max(value1, value4); + short value4; + if(value1` [readability-use-std-min-max] + // CHECK-FIXES: value1 = std::min(value1, myConstexprMax(value2, value3)); + if (value1 > myConstexprMax(value2, value3)) + value1 = myConstexprMax(value2, value3); + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::min` instead of `<=` [readability-use-std-min-max] + // CHECK-FIXES: value2 = std::min(value1, value2); + if (value1 <= value2) + value2 = value1; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::max` instead of `<=` [readability-use-std-min-max] + // CHECK-FIXES: value1 = std::max(value1, value2); + if (value1 <= value2) + value1 = value2; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::max` instead of `>=` [readability-use-std-min-max] + // CHECK-FIXES: value1 = std::max(value2, value1); + if (value2 >= value1) + value1 = value2; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::min` instead of `>=` [readability-use-std-min-max] + // CHECK-FIXES: value2 = std::min(value2, value1); + if (value2 >= value1) + value2 = value1; + + // CHECK-MESSAGES: :[[@LINE+3]]:3: warning: use `std::max` instead of `<` [readability-use-std-min-max] + // CHECK-FIXES: obj.member1 = std::max(obj.member1, obj.member2); + MyClass obj; + if (obj.member1 < obj.member2) + obj.member1 = obj.member2; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::min` instead of `<` [readability-use-std-min-max] + // CHECK-FIXES: obj.member2 = std::min(obj.member1, obj.member2); + if (obj.member1 < obj.member2) + obj.member2 = obj.member1; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::min` instead of `>` [readability-use-std-min-max] + // CHECK-FIXES: obj.member2 = std::min(obj.member2, obj.member1); + if (obj.member2 > obj.member1) + obj.member2 = obj.member1; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::max` instead of `>` [readability-use-std-min-max] + // CHECK-FIXES: obj.member1 = std::max(obj.member2, obj.member1); + if (obj.member2 > obj.member1) + obj.member1 = obj.member2; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::max` instead of `<` [readability-use-std-min-max] + // CHECK-FIXES: obj.member1 = std::max(obj.member1, value4); + if (obj.member1 < value4) + obj.member1 = value4; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::min` instead of `<` [readability-use-std-min-max] + // CHECK-FIXES: value3 = std::min(obj.member1 + value2, value3); + if (obj.member1 + value2 < value3) + value3 = obj.member1 + value2; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::min` instead of `<=` [readability-use-std-min-max] + // CHECK-FIXES: obj.member2 = std::min(value1, obj.member2); + if (value1 <= obj.member2) + obj.member2 = value1; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::max` instead of `<=` [readability-use-std-min-max] + // CHECK-FIXES: value1 = std::max(value1, obj.member2); + if (value1 <= obj.member2) + value1 = obj.member2; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::max` instead of `>=` [readability-use-std-min-max] + // CHECK-FIXES: value1 = std::max(obj.member2, value1); + if (obj.member2 >= value1) + value1 = obj.member2; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::min` instead of `>=` [readability-use-std-min-max] + // CHECK-FIXES: obj.member2 = std::min(obj.member2, value1); + if (obj.member2 >= value1) + obj.member2 = value1; + + // No suggestion needed here + if (MY_MACRO_MIN(value1, value2) < value3) + value3 = MY_MACRO_MIN(value1, value2); + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::max` instead of `<` [readability-use-std-min-max] + // CHECK-FIXES: value4 = std::max(value4, value2); + if (value4 < value2){ + value4 = value2; + } + + // No suggestion needed here + if(value1 < value2) + value2 = value1; + else + value2 = value3; + + // No suggestion needed here + if(value1value2){ + value2 = value1; + } + + // CHECK-MESSAGES: :[[@LINE+3]]:5: warning: use `std::max` instead of `<` [readability-use-std-min-max] + // CHECK-FIXES: value1 = std::max(value1, value3); + if(value1 == value2){ + if(value1(value1, value4); + if(value1 == value2){ + if(value2 == value3){ + value3+=1; + if(value1value2){ + value2 = value3; + } + } + + // CHECK-MESSAGES: :[[@LINE+4]]:3: warning: use `std::min` instead of `<` [readability-use-std-min-max] + // CHECK-FIXES: value6 = std::min(value5, value6); + unsigned int value5; + unsigned char value6; + if(value5 +struct MyVector +{ + using size_type = my_size; + size_type size() const; +}; + +void testVectorSizeType() { + MyVector v; + unsigned int value; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::max` instead of `>` [readability-use-std-min-max] + // CHECK-FIXES: value = std::max(v.size(), value); + if (v.size() > value) + value = v.size(); + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::max` instead of `<` [readability-use-std-min-max] + // CHECK-FIXES: value = std::max(value, v.size()); + if (value < v.size()) + value = v.size(); +} -- GitLab From e197b957ce1061cb1bfbd586b703065367cce5dc Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 6 Feb 2024 12:17:45 -0800 Subject: [PATCH 114/266] [RISCV] Fix typo in call to clearFeatureBits. We had "+zca" instead of "zca". The previous line used "c", not "+c". This may not be a functional change. I think the function we pass this to strips any '+' or '-'. --- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 4063719582bb..d83979a873f2 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -2893,7 +2893,7 @@ bool RISCVAsmParser::parseDirectiveOption() { getTargetStreamer().emitDirectiveOptionNoRVC(); clearFeatureBits(RISCV::FeatureStdExtC, "c"); - clearFeatureBits(RISCV::FeatureStdExtZca, "+zca"); + clearFeatureBits(RISCV::FeatureStdExtZca, "zca"); return false; } -- GitLab From 8bb827c0e67e51adba1252d23edc58197e025cf7 Mon Sep 17 00:00:00 2001 From: Shubham Sandeep Rastogi Date: Tue, 6 Feb 2024 12:27:21 -0800 Subject: [PATCH 115/266] Add test for iterating over MDNode operands when they are empty (#80737) With e8512786fedbfa6ddba70ceddc29d7122173ba5e the for loop that iterates over MDNode operands was changed to a range-based for loop. This change surfaces a bug where if the result of MD->operands() is an ArrayRef that has a size of 0, then iterating over that ArrayRef leads to a segmentation fault, due to accessing invalid addresses. This was reverted with 6ce03ff3fef8fb6fa9afe8eb22c6d98bced26d48 but this test should be added to test that codepath in the future. --- .../test/Verifier/verify-dwarf-no-operands.ll | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 llvm/test/Verifier/verify-dwarf-no-operands.ll diff --git a/llvm/test/Verifier/verify-dwarf-no-operands.ll b/llvm/test/Verifier/verify-dwarf-no-operands.ll new file mode 100644 index 000000000000..aaa5c4b6af04 --- /dev/null +++ b/llvm/test/Verifier/verify-dwarf-no-operands.ll @@ -0,0 +1,25 @@ +; RUN: llvm-as -disable-output %s +%"class.llvm::StringRef" = type { ptr, i64 } +define internal void @_ZL30tokenizeWindowsCommandLineImplN4llvm9StringRefERNS_11StringSaverENS_12function_refIFvS0_EEEbNS3_IFvvEEEb() !dbg !12 { + %7 = alloca %"class.llvm::StringRef", align 8 + %21 = call noundef i64 @_ZNK4llvm9StringRef4sizeEv(ptr noundef nonnull align 8 dereferenceable(16) %7) + br label %22 + br label %22, !llvm.loop !284 ; This instruction has loop metadata but no operands and should not result in a segmentation fault in the verifier. +} +define linkonce_odr noundef i64 @_ZNK4llvm9StringRef4sizeEv() align 2 !dbg !340 { + %2 = alloca ptr, align 8 + %3 = load ptr, ptr %2, align 8 + %4 = getelementptr inbounds %"class.llvm::StringRef", ptr %3 + %5 = load i64, ptr %4 + ret i64 %5 +} +!llvm.module.flags = !{!2, !6} +!llvm.dbg.cu = !{!7} +!2 = !{i32 2, !"Debug Info Version", i32 3} +!6 = !{i32 7, !"frame-pointer", i32 1} +!7 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !8, sdk: "MacOSX14.0.sdk") +!8 = !DIFile(filename: "file.cpp", directory: "/Users/Dev", checksumkind: CSK_MD5, checksum: "ed7ae158f20f7914bc5fb843291e80da") +!12 = distinct !DISubprogram(unit: !7, retainedNodes: !36) +!36 = !{} +!284 = distinct !{} +!340 = distinct !DISubprogram(unit: !7, retainedNodes: !36) -- GitLab From 4858e9c9feb94d65acdb284fc2eaa5fe131c6584 Mon Sep 17 00:00:00 2001 From: Yingwei Zheng Date: Wed, 7 Feb 2024 04:33:26 +0800 Subject: [PATCH 116/266] [InstCombine] Canonicalize the fcmp range check idiom into `fabs + fcmp` (#76367) This patch canonicalizes the fcmp range check idiom into `fabs + fcmp` since the canonicalized form is better than the original form for the backends. Godbolt: https://godbolt.org/z/x3eqPb1fz ``` and (fcmp olt/ole/ult/ule x, C), (fcmp ogt/oge/ugt/uge x, -C) --> fabs(x) olt/ole/ult/ule C or (fcmp ogt/oge/ugt/uge x, C), (fcmp olt/ole/ult/ule x, -C) --> fabs(x) ogt/oge/ugt/uge C ``` Alive2: https://alive2.llvm.org/ce/z/MRtoYq --- .../InstCombine/InstCombineAndOrXor.cpp | 38 ++ .../InstCombine/fcmp-range-check-idiom.ll | 361 ++++++++++++++++++ 2 files changed, 399 insertions(+) create mode 100644 llvm/test/Transforms/InstCombine/fcmp-range-check-idiom.ll diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp index 6ca4d6d67306..6a827e2f3a96 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp @@ -1419,6 +1419,44 @@ Value *InstCombinerImpl::foldLogicOfFCmps(FCmpInst *LHS, FCmpInst *RHS, } } + // Canonicalize the range check idiom: + // and (fcmp olt/ole/ult/ule x, C), (fcmp ogt/oge/ugt/uge x, -C) + // --> fabs(x) olt/ole/ult/ule C + // or (fcmp ogt/oge/ugt/uge x, C), (fcmp olt/ole/ult/ule x, -C) + // --> fabs(x) ogt/oge/ugt/uge C + // TODO: Generalize to handle a negated variable operand? + const APFloat *LHSC, *RHSC; + if (LHS0 == RHS0 && LHS->hasOneUse() && RHS->hasOneUse() && + FCmpInst::getSwappedPredicate(PredL) == PredR && + match(LHS1, m_APFloatAllowUndef(LHSC)) && + match(RHS1, m_APFloatAllowUndef(RHSC)) && + LHSC->bitwiseIsEqual(neg(*RHSC))) { + auto IsLessThanOrLessEqual = [](FCmpInst::Predicate Pred) { + switch (Pred) { + case FCmpInst::FCMP_OLT: + case FCmpInst::FCMP_OLE: + case FCmpInst::FCMP_ULT: + case FCmpInst::FCMP_ULE: + return true; + default: + return false; + } + }; + if (IsLessThanOrLessEqual(IsAnd ? PredR : PredL)) { + std::swap(LHSC, RHSC); + std::swap(PredL, PredR); + } + if (IsLessThanOrLessEqual(IsAnd ? PredL : PredR)) { + BuilderTy::FastMathFlagGuard Guard(Builder); + Builder.setFastMathFlags(LHS->getFastMathFlags() | + RHS->getFastMathFlags()); + + Value *FAbs = Builder.CreateUnaryIntrinsic(Intrinsic::fabs, LHS0); + return Builder.CreateFCmp(PredL, FAbs, + ConstantFP::get(LHS0->getType(), *LHSC)); + } + } + return nullptr; } diff --git a/llvm/test/Transforms/InstCombine/fcmp-range-check-idiom.ll b/llvm/test/Transforms/InstCombine/fcmp-range-check-idiom.ll new file mode 100644 index 000000000000..0893b27f5cf4 --- /dev/null +++ b/llvm/test/Transforms/InstCombine/fcmp-range-check-idiom.ll @@ -0,0 +1,361 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -S -passes=instcombine %s | FileCheck %s + +declare void @use(i1) + +define i1 @test_and_olt(float %x) { +; CHECK-LABEL: define i1 @test_and_olt( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X]]) +; CHECK-NEXT: [[COND:%.*]] = fcmp olt float [[TMP1]], 0x3C00000000000000 +; CHECK-NEXT: ret i1 [[COND]] +; + %cmp1 = fcmp olt float %x, 0x3C00000000000000 + %cmp2 = fcmp ogt float %x, 0xBC00000000000000 + %cond = and i1 %cmp1, %cmp2 + ret i1 %cond +} + +define i1 @test_and_ole(float %x) { +; CHECK-LABEL: define i1 @test_and_ole( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X]]) +; CHECK-NEXT: [[COND:%.*]] = fcmp ole float [[TMP1]], 0x3C00000000000000 +; CHECK-NEXT: ret i1 [[COND]] +; + %cmp1 = fcmp ole float %x, 0x3C00000000000000 + %cmp2 = fcmp oge float %x, 0xBC00000000000000 + %cond = and i1 %cmp1, %cmp2 + ret i1 %cond +} + +define i1 @test_or_ogt(float %x) { +; CHECK-LABEL: define i1 @test_or_ogt( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X]]) +; CHECK-NEXT: [[COND:%.*]] = fcmp ogt float [[TMP1]], 0x3C00000000000000 +; CHECK-NEXT: ret i1 [[COND]] +; + %cmp1 = fcmp ogt float %x, 0x3C00000000000000 + %cmp2 = fcmp olt float %x, 0xBC00000000000000 + %cond = or i1 %cmp1, %cmp2 + ret i1 %cond +} + +define i1 @test_or_oge(float %x) { +; CHECK-LABEL: define i1 @test_or_oge( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X]]) +; CHECK-NEXT: [[COND:%.*]] = fcmp oge float [[TMP1]], 0x3C00000000000000 +; CHECK-NEXT: ret i1 [[COND]] +; + %cmp1 = fcmp oge float %x, 0x3C00000000000000 + %cmp2 = fcmp ole float %x, 0xBC00000000000000 + %cond = or i1 %cmp1, %cmp2 + ret i1 %cond +} + +define i1 @test_and_ult(float %x) { +; CHECK-LABEL: define i1 @test_and_ult( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X]]) +; CHECK-NEXT: [[COND:%.*]] = fcmp ult float [[TMP1]], 0x3C00000000000000 +; CHECK-NEXT: ret i1 [[COND]] +; + %cmp1 = fcmp ult float %x, 0x3C00000000000000 + %cmp2 = fcmp ugt float %x, 0xBC00000000000000 + %cond = and i1 %cmp1, %cmp2 + ret i1 %cond +} + +define i1 @test_and_ule(float %x) { +; CHECK-LABEL: define i1 @test_and_ule( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X]]) +; CHECK-NEXT: [[COND:%.*]] = fcmp ule float [[TMP1]], 0x3C00000000000000 +; CHECK-NEXT: ret i1 [[COND]] +; + %cmp1 = fcmp ule float %x, 0x3C00000000000000 + %cmp2 = fcmp uge float %x, 0xBC00000000000000 + %cond = and i1 %cmp1, %cmp2 + ret i1 %cond +} + +define i1 @test_or_ugt(float %x) { +; CHECK-LABEL: define i1 @test_or_ugt( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X]]) +; CHECK-NEXT: [[COND:%.*]] = fcmp ugt float [[TMP1]], 0x3C00000000000000 +; CHECK-NEXT: ret i1 [[COND]] +; + %cmp1 = fcmp ugt float %x, 0x3C00000000000000 + %cmp2 = fcmp ult float %x, 0xBC00000000000000 + %cond = or i1 %cmp1, %cmp2 + ret i1 %cond +} + +define i1 @test_or_uge(float %x) { +; CHECK-LABEL: define i1 @test_or_uge( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X]]) +; CHECK-NEXT: [[COND:%.*]] = fcmp uge float [[TMP1]], 0x3C00000000000000 +; CHECK-NEXT: ret i1 [[COND]] +; + %cmp1 = fcmp uge float %x, 0x3C00000000000000 + %cmp2 = fcmp ule float %x, 0xBC00000000000000 + %cond = or i1 %cmp1, %cmp2 + ret i1 %cond +} + +define i1 @test_and_olt_commuted(float %x) { +; CHECK-LABEL: define i1 @test_and_olt_commuted( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X]]) +; CHECK-NEXT: [[COND:%.*]] = fcmp olt float [[TMP1]], 0x3C00000000000000 +; CHECK-NEXT: ret i1 [[COND]] +; + %cmp1 = fcmp olt float %x, 0x3C00000000000000 + %cmp2 = fcmp ogt float %x, 0xBC00000000000000 + %cond = and i1 %cmp2, %cmp1 + ret i1 %cond +} + +define i1 @test_and_olt_subnormal(float %x) { +; CHECK-LABEL: define i1 @test_and_olt_subnormal( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X]]) +; CHECK-NEXT: [[COND:%.*]] = fcmp olt float [[TMP1]], 0x36A0000000000000 +; CHECK-NEXT: ret i1 [[COND]] +; + %cmp1 = fcmp olt float %x, 0x36A0000000000000 + %cmp2 = fcmp ogt float %x, 0xB6A0000000000000 + %cond = and i1 %cmp1, %cmp2 + ret i1 %cond +} + +define i1 @test_and_olt_infinity(float %x) { +; CHECK-LABEL: define i1 @test_and_olt_infinity( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X]]) +; CHECK-NEXT: [[COND:%.*]] = fcmp one float [[TMP1]], 0x7FF0000000000000 +; CHECK-NEXT: ret i1 [[COND]] +; + %cmp1 = fcmp olt float %x, 0x7FF0000000000000 + %cmp2 = fcmp ogt float %x, 0xFFF0000000000000 + %cond = and i1 %cmp1, %cmp2 + ret i1 %cond +} + +define i1 @test_and_olt_zero(float %x) { +; CHECK-LABEL: define i1 @test_and_olt_zero( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: ret i1 false +; + %cmp1 = fcmp olt float %x, 0x0000000000000000 + %cmp2 = fcmp ogt float %x, 0x8000000000000000 + %cond = and i1 %cmp1, %cmp2 + ret i1 %cond +} + +define i1 @test_and_ole_zero(float %x) { +; CHECK-LABEL: define i1 @test_and_ole_zero( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[COND:%.*]] = fcmp oeq float [[X]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[COND]] +; + %cmp1 = fcmp ole float %x, 0x0000000000000000 + %cmp2 = fcmp oge float %x, 0x8000000000000000 + %cond = and i1 %cmp1, %cmp2 + ret i1 %cond +} + +define i1 @test_and_olt_logical(float %x) { +; CHECK-LABEL: define i1 @test_and_olt_logical( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X]]) +; CHECK-NEXT: [[COND:%.*]] = fcmp olt float [[TMP1]], 0x3C00000000000000 +; CHECK-NEXT: ret i1 [[COND]] +; + %cmp1 = fcmp olt float %x, 0x3C00000000000000 + %cmp2 = fcmp ogt float %x, 0xBC00000000000000 + %cond = select i1 %cmp1, i1 %cmp2, i1 false + ret i1 %cond +} + +define <2 x i1> @test_and_olt_undef(<2 x float> %x) { +; CHECK-LABEL: define <2 x i1> @test_and_olt_undef( +; CHECK-SAME: <2 x float> [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = call <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]]) +; CHECK-NEXT: [[COND:%.*]] = fcmp olt <2 x float> [[TMP1]], +; CHECK-NEXT: ret <2 x i1> [[COND]] +; + %cmp1 = fcmp olt <2 x float> %x, + %cmp2 = fcmp ogt <2 x float> %x, + %cond = and <2 x i1> %cmp1, %cmp2 + ret <2 x i1> %cond +} + +define i1 @test_and_olt_nan(float %x) { +; CHECK-LABEL: define i1 @test_and_olt_nan( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: ret i1 false +; + %cmp1 = fcmp olt float %x, 0x7FF8000000000000 + %cmp2 = fcmp ogt float %x, 0xFFF8000000000000 + %cond = and i1 %cmp1, %cmp2 + ret i1 %cond +} + +define i1 @test_and_ult_nan(float %x) { +; CHECK-LABEL: define i1 @test_and_ult_nan( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: ret i1 true +; + %cmp1 = fcmp ult float %x, 0x7FF0000020000000 + %cmp2 = fcmp ugt float %x, 0xFFF0000020000000 + %cond = and i1 %cmp1, %cmp2 + ret i1 %cond +} + +define i1 @test_or_ogt_nan(float %x) { +; CHECK-LABEL: define i1 @test_or_ogt_nan( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: ret i1 false +; + %cmp1 = fcmp ogt float %x, 0x7FF0000020000000 + %cmp2 = fcmp olt float %x, 0xFFF0000020000000 + %cond = or i1 %cmp1, %cmp2 + ret i1 %cond +} + +define i1 @test_or_ugt_nan(float %x) { +; CHECK-LABEL: define i1 @test_or_ugt_nan( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: ret i1 true +; + %cmp1 = fcmp ugt float %x, 0x7FF0000020000000 + %cmp2 = fcmp ult float %x, 0xFFF0000020000000 + %cond = or i1 %cmp1, %cmp2 + ret i1 %cond +} + +define i1 @test_and_ogt(float %x) { +; CHECK-LABEL: define i1 @test_and_ogt( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: ret i1 false +; + %cmp1 = fcmp ogt float %x, 0x3C00000000000000 + %cmp2 = fcmp olt float %x, 0xBC00000000000000 + %cond = and i1 %cmp1, %cmp2 + ret i1 %cond +} + +define i1 @test_or_olt(float %x) { +; CHECK-LABEL: define i1 @test_or_olt( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X]]) +; CHECK-NEXT: [[COND:%.*]] = fcmp ogt float [[TMP1]], 0xBC00000000000000 +; CHECK-NEXT: ret i1 [[COND]] +; + %cmp1 = fcmp olt float %x, 0x3C00000000000000 + %cmp2 = fcmp ogt float %x, 0xBC00000000000000 + %cond = or i1 %cmp1, %cmp2 + ret i1 %cond +} + +; Negative tests + +define i1 @test_and_olt_multiuse(float %x) { +; CHECK-LABEL: define i1 @test_and_olt_multiuse( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[CMP1:%.*]] = fcmp olt float [[X]], 0x3C00000000000000 +; CHECK-NEXT: call void @use(i1 [[CMP1]]) +; CHECK-NEXT: [[CMP2:%.*]] = fcmp ogt float [[X]], 0xBC00000000000000 +; CHECK-NEXT: [[COND:%.*]] = and i1 [[CMP1]], [[CMP2]] +; CHECK-NEXT: ret i1 [[COND]] +; + %cmp1 = fcmp olt float %x, 0x3C00000000000000 + call void @use(i1 %cmp1) + %cmp2 = fcmp ogt float %x, 0xBC00000000000000 + %cond = and i1 %cmp1, %cmp2 + ret i1 %cond +} + +define i1 @test_and_olt_mismatched_lhs(float %x, float %y) { +; CHECK-LABEL: define i1 @test_and_olt_mismatched_lhs( +; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) { +; CHECK-NEXT: [[CMP1:%.*]] = fcmp olt float [[X]], 0x3C00000000000000 +; CHECK-NEXT: [[CMP2:%.*]] = fcmp ogt float [[Y]], 0xBC00000000000000 +; CHECK-NEXT: [[COND:%.*]] = and i1 [[CMP1]], [[CMP2]] +; CHECK-NEXT: ret i1 [[COND]] +; + %cmp1 = fcmp olt float %x, 0x3C00000000000000 + %cmp2 = fcmp ogt float %y, 0xBC00000000000000 + %cond = and i1 %cmp1, %cmp2 + ret i1 %cond +} + +define i1 @test_and_olt_same_sign(float %x) { +; CHECK-LABEL: define i1 @test_and_olt_same_sign( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: ret i1 false +; + %cmp1 = fcmp olt float %x, 0x3C00000000000000 + %cmp2 = fcmp ogt float %x, 0x3C00000000000000 + %cond = and i1 %cmp1, %cmp2 + ret i1 %cond +} + +define i1 @test_and_olt_mismatched_mag(float %x) { +; CHECK-LABEL: define i1 @test_and_olt_mismatched_mag( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[CMP1:%.*]] = fcmp olt float [[X]], 0x3C80000000000000 +; CHECK-NEXT: [[CMP2:%.*]] = fcmp ogt float [[X]], 0xBC00000000000000 +; CHECK-NEXT: [[COND:%.*]] = and i1 [[CMP1]], [[CMP2]] +; CHECK-NEXT: ret i1 [[COND]] +; + %cmp1 = fcmp olt float %x, 0x3C80000000000000 + %cmp2 = fcmp ogt float %x, 0xBC00000000000000 + %cond = and i1 %cmp1, %cmp2 + ret i1 %cond +} + +define i1 @test_and_olt_wrong_pred2(float %x) { +; CHECK-LABEL: define i1 @test_and_olt_wrong_pred2( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[CMP1:%.*]] = fcmp olt float [[X]], 0x3C00000000000000 +; CHECK-NEXT: [[CMP2:%.*]] = fcmp oge float [[X]], 0xBC00000000000000 +; CHECK-NEXT: [[COND:%.*]] = and i1 [[CMP1]], [[CMP2]] +; CHECK-NEXT: ret i1 [[COND]] +; + %cmp1 = fcmp olt float %x, 0x3C00000000000000 + %cmp2 = fcmp oge float %x, 0xBC00000000000000 + %cond = and i1 %cmp1, %cmp2 + ret i1 %cond +} + +define i1 @test_and_olt_fmf_propagation(float %x) { +; CHECK-LABEL: define i1 @test_and_olt_fmf_propagation( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf nsz float @llvm.fabs.f32(float [[X]]) +; CHECK-NEXT: [[COND:%.*]] = fcmp nnan ninf nsz olt float [[TMP1]], 0x3C00000000000000 +; CHECK-NEXT: ret i1 [[COND]] +; + %cmp1 = fcmp nsz nnan ninf olt float %x, 0x3C00000000000000 + %cmp2 = fcmp nsz nnan ninf ogt float %x, 0xBC00000000000000 + %cond = and i1 %cmp1, %cmp2 + ret i1 %cond +} + +define i1 @test_and_olt_fmf_propagation_union(float %x) { +; CHECK-LABEL: define i1 @test_and_olt_fmf_propagation_union( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf nsz float @llvm.fabs.f32(float [[X]]) +; CHECK-NEXT: [[COND:%.*]] = fcmp nnan ninf nsz olt float [[TMP1]], 0x3C00000000000000 +; CHECK-NEXT: ret i1 [[COND]] +; + %cmp1 = fcmp nnan ninf olt float %x, 0x3C00000000000000 + %cmp2 = fcmp nsz nnan ogt float %x, 0xBC00000000000000 + %cond = and i1 %cmp1, %cmp2 + ret i1 %cond +} -- GitLab From 90e8dc0f7cbd09cc653b497eb2dfc68edd800f48 Mon Sep 17 00:00:00 2001 From: stephenpeckham <118857872+stephenpeckham@users.noreply.github.com> Date: Tue, 6 Feb 2024 14:35:21 -0600 Subject: [PATCH 117/266] Fix failing testcases (#80902) --- .../aix-small-local-exec-tls-largeaccess2.ll | 42 +++++++++---------- llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll | 2 +- 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-largeaccess2.ll b/llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-largeaccess2.ll index 725b68005492..f7b99461be5f 100644 --- a/llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-largeaccess2.ll +++ b/llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-largeaccess2.ll @@ -11,7 +11,7 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+aix-small-local-exec-tls \ ; RUN: -mtriple powerpc64-ibm-aix-xcoff -xcoff-traceback-table=false \ ; RUN: --code-model=large -filetype=obj -o %t.o < %s -; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s +; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=DIS %s @mySmallLocalExecTLS6 = external thread_local(localexec) global [60 x i64], align 8 @mySmallLocalExecTLS2 = thread_local(localexec) global [3000 x i64] zeroinitializer, align 8 @@ -105,37 +105,37 @@ entry: ret i64 %add11 } -; DIS: 0000000000000000 (idx: 7) .StoreLargeAccess1: +; DIS: 0000000000000000 (idx: [[#NFA+7]]) .StoreLargeAccess1: ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} mflr 0 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stdu 1, -48(1) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 3, 212 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} std 0, 64(1) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 4, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 13) MyTLSGDVar[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+13]]) MyTLSGDVar[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 4, 0(4) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 13) MyTLSGDVar[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+13]]) MyTLSGDVar[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} std 3, 424(13) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: 1) mySmallLocalExecTLS6[UL] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: [[#NFA+1]]) mySmallLocalExecTLS6[UL] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 3, 203 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} std 3, 1200(13) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: 17) mySmallLocalExecTLS2[TL] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: [[#NFA+17]]) mySmallLocalExecTLS2[TL] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 15) .MyTLSGDVar[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+15]]) .MyTLSGDVar[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 3, 8(3) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 15) .MyTLSGDVar[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+15]]) .MyTLSGDVar[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0 -; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: 3) .__tls_get_addr[PR] +; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: [[#NFA+3]]) .__tls_get_addr[PR] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 4, 44 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} std 4, 440(3) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 3, 6 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 4, 100 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} std 3, 32400(13) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: 21) mySmallLocalExecTLS3[TL] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: [[#NFA+21]]) mySmallLocalExecTLS3[TL] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 3, 882 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} std 4, -4336(13) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: 23) mySmallLocalExecTLS4[TL] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: [[#NFA+23]]) mySmallLocalExecTLS4[TL] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} std 3, 21264(13) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: 25) mySmallLocalExecTLS5[TL] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: [[#NFA+25]]) mySmallLocalExecTLS5[TL] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 3, 1191 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addi 1, 1, 48 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 0, 16(1) @@ -143,18 +143,18 @@ entry: ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} blr ; DIS: Disassembly of section .data: -; DIS: 0000000000000068 (idx: 9) StoreLargeAccess1[DS]: +; DIS: 0000000000000068 (idx: [[#NFA+9]]) StoreLargeAccess1[DS]: ; DIS-NEXT: 68: 00 00 00 00 -; DIS-NEXT: 0000000000000068: R_POS (idx: 7) .StoreLargeAccess1 +; DIS-NEXT: 0000000000000068: R_POS (idx: [[#NFA+7]]) .StoreLargeAccess1 ; DIS-NEXT: 6c: 00 00 00 00 ; DIS-NEXT: 70: 00 00 00 00 -; DIS-NEXT: 0000000000000070: R_POS (idx: 11) TOC[TC0] +; DIS-NEXT: 0000000000000070: R_POS (idx: [[#NFA+11]]) TOC[TC0] ; DIS-NEXT: 74: 00 00 00 80 ; DIS: Disassembly of section .tdata: -; DIS: 0000000000000000 (idx: 17) mySmallLocalExecTLS2[TL]: -; DIS: 0000000000005dc0 (idx: 19) MyTLSGDVar[TL]: -; DIS: 00000000000076c0 (idx: 21) mySmallLocalExecTLS3[TL]: -; DIS: 000000000000d480 (idx: 23) mySmallLocalExecTLS4[TL]: -; DIS: 0000000000013240 (idx: 25) mySmallLocalExecTLS5[TL]: -; DIS: 0000000000019000 (idx: 27) mySmallLocalExecTLS[TL]: +; DIS: 0000000000000000 (idx: [[#NFA+17]]) mySmallLocalExecTLS2[TL]: +; DIS: 0000000000005dc0 (idx: [[#NFA+19]]) MyTLSGDVar[TL]: +; DIS: 00000000000076c0 (idx: [[#NFA+21]]) mySmallLocalExecTLS3[TL]: +; DIS: 000000000000d480 (idx: [[#NFA+23]]) mySmallLocalExecTLS4[TL]: +; DIS: 0000000000013240 (idx: [[#NFA+25]]) mySmallLocalExecTLS5[TL]: +; DIS: 0000000000019000 (idx: [[#NFA+27]]) mySmallLocalExecTLS[TL]: diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll index 82ff008ad16d..6599debbd41b 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll @@ -175,7 +175,7 @@ declare i32 @bar(i32) ; SYM-NEXT: } ; SYM-NEXT: File Auxiliary Entry { ; SYM-NEXT: Index: 2 -; SYM-NEXT: Name: LLVM version 18.0.0git +; SYM-NEXT: Name: LLVM ; SYM-NEXT: Type: XFT_CV (0x2) ; SYM64-NEXT: Auxiliary Type: AUX_FILE (0xFC) ; SYM-NEXT: } -- GitLab From 672fb27b267edc5dec4939b0295c8eebcdc57467 Mon Sep 17 00:00:00 2001 From: Yitzhak Mandelbaum Date: Tue, 6 Feb 2024 15:38:56 -0500 Subject: [PATCH 118/266] [clang][dataflow] Add new `join` API and replace existing `merge` implementations. (#80361) This patch adds a new interface for the join operation, now properly called `join`. Originally, the framework offered a single `merge` operation, which could serve either as a join or a widening. In practice, though we found this conflation didn't work for non-trivial anlyses, and split of the widening operation (`widen`). This change completes the transition by introducing a proper `join` with strict join semantics. In the process, it drops an odd (and often misused) aspect of `merge` wherein callees could implictly instruct the framework to drop the current entry by returning `false`. This features was never used correctly in analyses and doesn't belong in a join operation, so it is omitted. --------- Co-authored-by: Dmitri Gribenko Co-authored-by: martinboehme --- .../FlowSensitive/DataflowEnvironment.h | 26 +++++++- .../FlowSensitive/DataflowEnvironment.cpp | 59 +++++++++---------- .../FlowSensitive/SignAnalysisTest.cpp | 58 +++++++++--------- .../TypeErasedDataflowAnalysisTest.cpp | 29 ++++----- 4 files changed, 93 insertions(+), 79 deletions(-) diff --git a/clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h b/clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h index 1543f900e401..5c737a561a7c 100644 --- a/clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h +++ b/clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h @@ -19,7 +19,6 @@ #include "clang/AST/DeclBase.h" #include "clang/AST/Expr.h" #include "clang/AST/Type.h" -#include "clang/Analysis/FlowSensitive/ControlFlowContext.h" #include "clang/Analysis/FlowSensitive/DataflowAnalysisContext.h" #include "clang/Analysis/FlowSensitive/DataflowLattice.h" #include "clang/Analysis/FlowSensitive/Formula.h" @@ -31,7 +30,6 @@ #include "llvm/ADT/MapVector.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/ErrorHandling.h" -#include #include #include @@ -81,6 +79,8 @@ public: return ComparisonResult::Unknown; } + /// DEPRECATED. Override `join` and/or `widen`, instead. + /// /// Modifies `MergedVal` to approximate both `Val1` and `Val2`. This could /// be a strict lattice join or a more general widening operation. /// @@ -105,6 +105,28 @@ public: return true; } + /// Modifies `JoinedVal` to approximate both `Val1` and `Val2`. This should + /// obey the properties of a lattice join. + /// + /// `Env1` and `Env2` can be used to query child values and path condition + /// implications of `Val1` and `Val2` respectively. + /// + /// Requirements: + /// + /// `Val1` and `Val2` must be distinct. + /// + /// `Val1`, `Val2`, and `JoinedVal` must model values of type `Type`. + /// + /// `Val1` and `Val2` must be assigned to the same storage location in + /// `Env1` and `Env2` respectively. + virtual void join(QualType Type, const Value &Val1, const Environment &Env1, + const Value &Val2, const Environment &Env2, + Value &JoinedVal, Environment &JoinedEnv) { + [[maybe_unused]] bool ShouldKeep = + merge(Type, Val1, Env1, Val2, Env2, JoinedVal, JoinedEnv); + assert(ShouldKeep && "dropping merged value is unsupported"); + } + /// This function may widen the current value -- replace it with an /// approximation that can reach a fixed point more quickly than iterated /// application of the transfer function alone. The previous value is diff --git a/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp b/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp index 01db65866d13..24811ded970e 100644 --- a/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp +++ b/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp @@ -86,15 +86,15 @@ static bool compareDistinctValues(QualType Type, Value &Val1, llvm_unreachable("All cases covered in switch"); } -/// Attempts to merge distinct values `Val1` and `Val2` in `Env1` and `Env2`, -/// respectively, of the same type `Type`. Merging generally produces a single +/// Attempts to join distinct values `Val1` and `Val2` in `Env1` and `Env2`, +/// respectively, of the same type `Type`. Joining generally produces a single /// value that (soundly) approximates the two inputs, although the actual /// meaning depends on `Model`. -static Value *mergeDistinctValues(QualType Type, Value &Val1, - const Environment &Env1, Value &Val2, - const Environment &Env2, - Environment &MergedEnv, - Environment::ValueModel &Model) { +static Value *joinDistinctValues(QualType Type, Value &Val1, + const Environment &Env1, Value &Val2, + const Environment &Env2, + Environment &JoinedEnv, + Environment::ValueModel &Model) { // Join distinct boolean values preserving information about the constraints // in the respective path conditions. if (isa(&Val1) && isa(&Val2)) { @@ -113,17 +113,17 @@ static Value *mergeDistinctValues(QualType Type, Value &Val1, // ``` auto &Expr1 = cast(Val1).formula(); auto &Expr2 = cast(Val2).formula(); - auto &A = MergedEnv.arena(); - auto &MergedVal = A.makeAtomRef(A.makeAtom()); - MergedEnv.assume( + auto &A = JoinedEnv.arena(); + auto &JoinedVal = A.makeAtomRef(A.makeAtom()); + JoinedEnv.assume( A.makeOr(A.makeAnd(A.makeAtomRef(Env1.getFlowConditionToken()), - A.makeEquals(MergedVal, Expr1)), + A.makeEquals(JoinedVal, Expr1)), A.makeAnd(A.makeAtomRef(Env2.getFlowConditionToken()), - A.makeEquals(MergedVal, Expr2)))); - return &A.makeBoolValue(MergedVal); + A.makeEquals(JoinedVal, Expr2)))); + return &A.makeBoolValue(JoinedVal); } - Value *MergedVal = nullptr; + Value *JoinedVal = nullptr; if (auto *RecordVal1 = dyn_cast(&Val1)) { auto *RecordVal2 = cast(&Val2); @@ -131,24 +131,21 @@ static Value *mergeDistinctValues(QualType Type, Value &Val1, // `RecordVal1` and `RecordVal2` may have different properties associated // with them. Create a new `RecordValue` with the same location but // without any properties so that we soundly approximate both values. If a - // particular analysis needs to merge properties, it should do so in - // `DataflowAnalysis::merge()`. - MergedVal = &MergedEnv.create(RecordVal1->getLoc()); + // particular analysis needs to join properties, it should do so in + // `DataflowAnalysis::join()`. + JoinedVal = &JoinedEnv.create(RecordVal1->getLoc()); else // If the locations for the two records are different, need to create a // completely new value. - MergedVal = MergedEnv.createValue(Type); + JoinedVal = JoinedEnv.createValue(Type); } else { - MergedVal = MergedEnv.createValue(Type); + JoinedVal = JoinedEnv.createValue(Type); } - // FIXME: Consider destroying `MergedValue` immediately if `ValueModel::merge` - // returns false to avoid storing unneeded values in `DACtx`. - if (MergedVal) - if (Model.merge(Type, Val1, Env1, Val2, Env2, *MergedVal, MergedEnv)) - return MergedVal; + if (JoinedVal) + Model.join(Type, Val1, Env1, Val2, Env2, *JoinedVal, JoinedEnv); - return nullptr; + return JoinedVal; } // When widening does not change `Current`, return value will equal `&Prev`. @@ -240,9 +237,9 @@ joinLocToVal(const llvm::MapVector &LocToVal, continue; } - if (Value *MergedVal = mergeDistinctValues( + if (Value *JoinedVal = joinDistinctValues( Loc->getType(), *Val, Env1, *It->second, Env2, JoinedEnv, Model)) { - Result.insert({Loc, MergedVal}); + Result.insert({Loc, JoinedVal}); } } @@ -657,10 +654,10 @@ Environment Environment::join(const Environment &EnvA, const Environment &EnvB, // cast. auto *Func = dyn_cast(EnvA.CallStack.back()); assert(Func != nullptr); - if (Value *MergedVal = - mergeDistinctValues(Func->getReturnType(), *EnvA.ReturnVal, EnvA, - *EnvB.ReturnVal, EnvB, JoinedEnv, Model)) - JoinedEnv.ReturnVal = MergedVal; + if (Value *JoinedVal = + joinDistinctValues(Func->getReturnType(), *EnvA.ReturnVal, EnvA, + *EnvB.ReturnVal, EnvB, JoinedEnv, Model)) + JoinedEnv.ReturnVal = JoinedVal; } if (EnvA.ReturnLoc == EnvB.ReturnLoc) diff --git a/clang/unittests/Analysis/FlowSensitive/SignAnalysisTest.cpp b/clang/unittests/Analysis/FlowSensitive/SignAnalysisTest.cpp index a6f4c45504fa..b8fc528dbdce 100644 --- a/clang/unittests/Analysis/FlowSensitive/SignAnalysisTest.cpp +++ b/clang/unittests/Analysis/FlowSensitive/SignAnalysisTest.cpp @@ -364,18 +364,17 @@ public: LatticeTransferState State(L, Env); TransferMatchSwitch(Elt, getASTContext(), State); } - bool merge(QualType Type, const Value &Val1, const Environment &Env1, - const Value &Val2, const Environment &Env2, Value &MergedVal, - Environment &MergedEnv) override; + void join(QualType Type, const Value &Val1, const Environment &Env1, + const Value &Val2, const Environment &Env2, Value &MergedVal, + Environment &MergedEnv) override; private: CFGMatchSwitch> TransferMatchSwitch; }; -// Copied from crubit. -BoolValue &mergeBoolValues(BoolValue &Bool1, const Environment &Env1, - BoolValue &Bool2, const Environment &Env2, - Environment &MergedEnv) { +BoolValue &joinBoolValues(BoolValue &Bool1, const Environment &Env1, + BoolValue &Bool2, const Environment &Env2, + Environment &JoinedEnv) { if (&Bool1 == &Bool2) { return Bool1; } @@ -383,41 +382,40 @@ BoolValue &mergeBoolValues(BoolValue &Bool1, const Environment &Env1, auto &B1 = Bool1.formula(); auto &B2 = Bool2.formula(); - auto &A = MergedEnv.arena(); - auto &MergedBool = MergedEnv.makeAtomicBoolValue(); + auto &A = JoinedEnv.arena(); + auto &JoinedBool = JoinedEnv.makeAtomicBoolValue(); // If `Bool1` and `Bool2` is constrained to the same true / false value, - // `MergedBool` can be constrained similarly without needing to consider the - // path taken - this simplifies the flow condition tracked in `MergedEnv`. + // `JoinedBool` can be constrained similarly without needing to consider the + // path taken - this simplifies the flow condition tracked in `JoinedEnv`. // Otherwise, information about which path was taken is used to associate - // `MergedBool` with `Bool1` and `Bool2`. + // `JoinedBool` with `Bool1` and `Bool2`. if (Env1.proves(B1) && Env2.proves(B2)) { - MergedEnv.assume(MergedBool.formula()); + JoinedEnv.assume(JoinedBool.formula()); } else if (Env1.proves(A.makeNot(B1)) && Env2.proves(A.makeNot(B2))) { - MergedEnv.assume(A.makeNot(MergedBool.formula())); + JoinedEnv.assume(A.makeNot(JoinedBool.formula())); } - return MergedBool; + return JoinedBool; } -bool SignPropagationAnalysis::merge(QualType Type, const Value &Val1, - const Environment &Env1, const Value &Val2, - const Environment &Env2, Value &MergedVal, - Environment &MergedEnv) { +void SignPropagationAnalysis::join(QualType Type, const Value &Val1, + const Environment &Env1, const Value &Val2, + const Environment &Env2, Value &JoinedVal, + Environment &JoinedEnv) { if (!Type->isIntegerType()) - return false; + return; SignProperties Ps1 = getSignProperties(Val1, Env1); SignProperties Ps2 = getSignProperties(Val2, Env2); if (!Ps1.Neg || !Ps2.Neg) - return false; - BoolValue &MergedNeg = - mergeBoolValues(*Ps1.Neg, Env1, *Ps2.Neg, Env2, MergedEnv); - BoolValue &MergedZero = - mergeBoolValues(*Ps1.Zero, Env1, *Ps2.Zero, Env2, MergedEnv); - BoolValue &MergedPos = - mergeBoolValues(*Ps1.Pos, Env1, *Ps2.Pos, Env2, MergedEnv); - setSignProperties(MergedVal, - SignProperties{&MergedNeg, &MergedZero, &MergedPos}); - return true; + return; + BoolValue &JoinedNeg = + joinBoolValues(*Ps1.Neg, Env1, *Ps2.Neg, Env2, JoinedEnv); + BoolValue &JoinedZero = + joinBoolValues(*Ps1.Zero, Env1, *Ps2.Zero, Env2, JoinedEnv); + BoolValue &JoinedPos = + joinBoolValues(*Ps1.Pos, Env1, *Ps2.Pos, Env2, JoinedEnv); + setSignProperties(JoinedVal, + SignProperties{&JoinedNeg, &JoinedZero, &JoinedPos}); } template diff --git a/clang/unittests/Analysis/FlowSensitive/TypeErasedDataflowAnalysisTest.cpp b/clang/unittests/Analysis/FlowSensitive/TypeErasedDataflowAnalysisTest.cpp index 466d33358fd3..3bca9cced8d6 100644 --- a/clang/unittests/Analysis/FlowSensitive/TypeErasedDataflowAnalysisTest.cpp +++ b/clang/unittests/Analysis/FlowSensitive/TypeErasedDataflowAnalysisTest.cpp @@ -672,26 +672,23 @@ public: : ComparisonResult::Different; } - bool merge(QualType Type, const Value &Val1, const Environment &Env1, - const Value &Val2, const Environment &Env2, Value &MergedVal, - Environment &MergedEnv) override { - // Nothing to say about a value that is not a pointer. + void join(QualType Type, const Value &Val1, const Environment &Env1, + const Value &Val2, const Environment &Env2, Value &JoinedVal, + Environment &JoinedEnv) override { + // Nothing to say about a value that is not a pointer... if (!Type->isPointerType()) - return false; + return; + // ... or, a pointer without the `is_null` property. auto *IsNull1 = cast_or_null(Val1.getProperty("is_null")); - if (IsNull1 == nullptr) - return false; - auto *IsNull2 = cast_or_null(Val2.getProperty("is_null")); - if (IsNull2 == nullptr) - return false; + if (IsNull1 == nullptr || IsNull2 == nullptr) + return; if (IsNull1 == IsNull2) - MergedVal.setProperty("is_null", *IsNull1); + JoinedVal.setProperty("is_null", *IsNull1); else - MergedVal.setProperty("is_null", MergedEnv.makeTopBoolValue()); - return true; + JoinedVal.setProperty("is_null", JoinedEnv.makeTopBoolValue()); } }; @@ -1176,7 +1173,7 @@ TEST_F(FlowConditionTest, Join) { // Note: currently, arbitrary function calls are uninterpreted, so the test // exercises this case. If and when we change that, this test will not add to // coverage (although it may still test a valuable case). -TEST_F(FlowConditionTest, OpaqueFlowConditionMergesToOpaqueBool) { +TEST_F(FlowConditionTest, OpaqueFlowConditionJoinsToOpaqueBool) { std::string Code = R"( bool foo(); @@ -1211,7 +1208,7 @@ TEST_F(FlowConditionTest, OpaqueFlowConditionMergesToOpaqueBool) { // the first instance), so the test exercises this case. If and when we change // that, this test will not add to coverage (although it may still test a // valuable case). -TEST_F(FlowConditionTest, OpaqueFieldFlowConditionMergesToOpaqueBool) { +TEST_F(FlowConditionTest, OpaqueFieldFlowConditionJoinsToOpaqueBool) { std::string Code = R"( struct Rec { Rec* Next; @@ -1249,7 +1246,7 @@ TEST_F(FlowConditionTest, OpaqueFieldFlowConditionMergesToOpaqueBool) { // condition is not meaningfully interpreted. Adds to above by nesting the // interestnig case inside a normal branch. This protects against degenerate // solutions which only test for empty flow conditions, for example. -TEST_F(FlowConditionTest, OpaqueFlowConditionInsideBranchMergesToOpaqueBool) { +TEST_F(FlowConditionTest, OpaqueFlowConditionInsideBranchJoinsToOpaqueBool) { std::string Code = R"( bool foo(); -- GitLab From 4607f385e005b3792b5669683d2c9b50d83e4e61 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 6 Feb 2024 12:38:22 -0800 Subject: [PATCH 119/266] [RISCV] Use hasStdExtCOrZca instead of FeatureStdExtC to determine NOP size in RISCVAsmPrinter.cpp. Found while auditing places where we only check C and not Zca. --- llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp index b2e9cd87373b..cb82e74b1efa 100644 --- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp +++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp @@ -110,7 +110,7 @@ private: void RISCVAsmPrinter::LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM, const MachineInstr &MI) { - unsigned NOPBytes = STI->getFeatureBits()[RISCV::FeatureStdExtC] ? 2 : 4; + unsigned NOPBytes = STI->hasStdExtCOrZca() ? 2 : 4; unsigned NumNOPBytes = StackMapOpers(&MI).getNumPatchBytes(); auto &Ctx = OutStreamer.getContext(); @@ -143,7 +143,7 @@ void RISCVAsmPrinter::LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM, // [], , , , void RISCVAsmPrinter::LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM, const MachineInstr &MI) { - unsigned NOPBytes = STI->getFeatureBits()[RISCV::FeatureStdExtC] ? 2 : 4; + unsigned NOPBytes = STI->hasStdExtCOrZca() ? 2 : 4; auto &Ctx = OutStreamer.getContext(); MCSymbol *MILabel = Ctx.createTempSymbol(); @@ -165,7 +165,7 @@ void RISCVAsmPrinter::LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM, void RISCVAsmPrinter::LowerSTATEPOINT(MCStreamer &OutStreamer, StackMaps &SM, const MachineInstr &MI) { - unsigned NOPBytes = STI->getFeatureBits()[RISCV::FeatureStdExtC] ? 2 : 4; + unsigned NOPBytes = STI->hasStdExtCOrZca() ? 2 : 4; StatepointOpers SOpers(&MI); if (unsigned PatchBytes = SOpers.getNumPatchBytes()) { -- GitLab From 3f1e95a9d4cc1fdb933390247d0bd4391cf93f60 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Tue, 6 Feb 2024 20:15:56 +0100 Subject: [PATCH 120/266] [clang][Interp] consider "MS constexpr" functions as well This implements the minimum amout of support for this feature to get the test/AST/ms-constexpr.cpp test working. More has to be added to get SemaCXX tests to work. --- clang/lib/AST/Interp/ByteCodeEmitter.cpp | 4 +++- clang/test/AST/ms-constexpr.cpp | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/clang/lib/AST/Interp/ByteCodeEmitter.cpp b/clang/lib/AST/Interp/ByteCodeEmitter.cpp index 409ce21506ca..8bbfa928bd64 100644 --- a/clang/lib/AST/Interp/ByteCodeEmitter.cpp +++ b/clang/lib/AST/Interp/ByteCodeEmitter.cpp @@ -14,6 +14,7 @@ #include "Opcode.h" #include "Program.h" #include "clang/AST/ASTLambda.h" +#include "clang/AST/Attr.h" #include "clang/AST/DeclCXX.h" #include "clang/Basic/Builtins.h" #include @@ -116,7 +117,8 @@ Function *ByteCodeEmitter::compileFunc(const FunctionDecl *FuncDecl) { if (const auto *MD = dyn_cast(FuncDecl)) IsEligibleForCompilation = MD->isLambdaStaticInvoker(); if (!IsEligibleForCompilation) - IsEligibleForCompilation = FuncDecl->isConstexpr(); + IsEligibleForCompilation = + FuncDecl->isConstexpr() || FuncDecl->hasAttr(); // Compile the function body. if (!IsEligibleForCompilation || !visitFunc(FuncDecl)) { diff --git a/clang/test/AST/ms-constexpr.cpp b/clang/test/AST/ms-constexpr.cpp index e85af8494f33..673af1234f44 100644 --- a/clang/test/AST/ms-constexpr.cpp +++ b/clang/test/AST/ms-constexpr.cpp @@ -1,4 +1,5 @@ // RUN: %clang_cc1 -fms-compatibility -fms-compatibility-version=19.33 -std=c++20 -ast-dump -verify %s | FileCheck %s +// RUN: %clang_cc1 -fms-compatibility -fms-compatibility-version=19.33 -std=c++20 -ast-dump -verify %s -fexperimental-new-constant-interpreter | FileCheck %s // expected-no-diagnostics // CHECK: used f1 'bool ()' -- GitLab From cd0d11be7a6de335dcfcf2788a97d915f017e25e Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Tue, 6 Feb 2024 12:53:16 -0800 Subject: [PATCH 121/266] [M68k] Convert tests to opaque pointers (NFC) --- .../CodeGen/M68k/Alloc/dyn_alloca_aligned.ll | 2 +- .../CodeGen/M68k/Arith/add-with-overflow.ll | 8 +- llvm/test/CodeGen/M68k/Arith/add.ll | 24 ++-- llvm/test/CodeGen/M68k/Arith/bitwise.ll | 36 ++--- .../CodeGen/M68k/Arith/smul-with-overflow.ll | 10 +- .../CodeGen/M68k/Arith/sub-with-overflow.ll | 10 +- llvm/test/CodeGen/M68k/Atomics/load-store.ll | 128 +++++++++--------- llvm/test/CodeGen/M68k/CConv/c-args-inreg.ll | 10 +- llvm/test/CodeGen/M68k/CConv/c-args.ll | 18 +-- llvm/test/CodeGen/M68k/CConv/fastcc-args.ll | 10 +- llvm/test/CodeGen/M68k/CConv/fastcc-call.ll | 4 +- .../test/CodeGen/M68k/CodeModel/medium-pic.ll | 38 +++--- .../CodeModel/medium-pie-global-access.ll | 16 +-- .../CodeGen/M68k/CodeModel/medium-static.ll | 38 +++--- llvm/test/CodeGen/M68k/CodeModel/small-pic.ll | 38 +++--- .../M68k/CodeModel/small-pie-global-access.ll | 16 +-- .../CodeGen/M68k/CodeModel/small-static.ll | 38 +++--- llvm/test/CodeGen/M68k/Control/cmp.ll | 22 +-- .../M68k/GlobalISel/irtranslator-call.ll | 40 +++--- .../M68k/GlobalISel/irtranslator-ret.ll | 4 +- llvm/test/CodeGen/M68k/inline-asm.ll | 6 +- llvm/test/CodeGen/M68k/link-unlnk.ll | 24 ++-- llvm/test/CodeGen/M68k/reserved-regs.ll | 40 +++--- llvm/test/CodeGen/M68k/varargs.ll | 24 ++-- 24 files changed, 302 insertions(+), 302 deletions(-) diff --git a/llvm/test/CodeGen/M68k/Alloc/dyn_alloca_aligned.ll b/llvm/test/CodeGen/M68k/Alloc/dyn_alloca_aligned.ll index ff361b626822..c8cf34dbe7f2 100644 --- a/llvm/test/CodeGen/M68k/Alloc/dyn_alloca_aligned.ll +++ b/llvm/test/CodeGen/M68k/Alloc/dyn_alloca_aligned.ll @@ -24,6 +24,6 @@ define i32 @A(i32 %Size) { ; CHECK-NEXT: unlk %a6 ; CHECK-NEXT: rts %A = alloca i8, i32 %Size, align 128 - %A_addr = ptrtoint i8* %A to i32 + %A_addr = ptrtoint ptr %A to i32 ret i32 %A_addr } diff --git a/llvm/test/CodeGen/M68k/Arith/add-with-overflow.ll b/llvm/test/CodeGen/M68k/Arith/add-with-overflow.ll index 0fd32b6c12ad..bd5e593edb33 100644 --- a/llvm/test/CodeGen/M68k/Arith/add-with-overflow.ll +++ b/llvm/test/CodeGen/M68k/Arith/add-with-overflow.ll @@ -4,7 +4,7 @@ declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32) declare {i32, i1} @llvm.uadd.with.overflow.i32(i32, i32) -define fastcc i32 @test5(i32 %v1, i32 %v2, i32* %X) nounwind { +define fastcc i32 @test5(i32 %v1, i32 %v2, ptr %X) nounwind { ; CHECK-LABEL: test5: ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: add.l %d1, %d0 @@ -20,14 +20,14 @@ entry: br i1 %obit, label %overflow, label %normal normal: - store i32 0, i32* %X + store i32 0, ptr %X br label %overflow overflow: ret i32 %sum } -define fastcc i1 @test6(i32 %v1, i32 %v2, i32* %X) nounwind { +define fastcc i1 @test6(i32 %v1, i32 %v2, ptr %X) nounwind { ; CHECK-LABEL: test6: ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: add.l %d1, %d0 @@ -44,7 +44,7 @@ entry: br i1 %obit, label %carry, label %normal normal: - store i32 0, i32* %X + store i32 0, ptr %X br label %carry carry: diff --git a/llvm/test/CodeGen/M68k/Arith/add.ll b/llvm/test/CodeGen/M68k/Arith/add.ll index 19d8d619083c..281751e3e183 100644 --- a/llvm/test/CodeGen/M68k/Arith/add.ll +++ b/llvm/test/CodeGen/M68k/Arith/add.ll @@ -14,30 +14,30 @@ define i64 @test1(i64 %A, i32 %B) nounwind { ret i64 %tmp5 } -define void @test2(i32* inreg %a) nounwind { +define void @test2(ptr inreg %a) nounwind { ; CHECK-LABEL: test2: ; CHECK: ; %bb.0: ; CHECK-NEXT: move.l %d0, %a0 ; CHECK-NEXT: add.l #128, (%a0) ; CHECK-NEXT: rts - %aa = load i32, i32* %a + %aa = load i32, ptr %a %b = add i32 %aa, 128 - store i32 %b, i32* %a + store i32 %b, ptr %a ret void } -define fastcc void @test2_fast(i32* inreg %a) nounwind { +define fastcc void @test2_fast(ptr inreg %a) nounwind { ; CHECK-LABEL: test2_fast: ; CHECK: ; %bb.0: ; CHECK-NEXT: add.l #128, (%a0) ; CHECK-NEXT: rts - %aa = load i32, i32* %a + %aa = load i32, ptr %a %b = add i32 %aa, 128 - store i32 %b, i32* %a + store i32 %b, ptr %a ret void } -define fastcc void @test3(i64* inreg %a) nounwind { +define fastcc void @test3(ptr inreg %a) nounwind { ; CHECK-LABEL: test3: ; CHECK: ; %bb.0: ; CHECK-NEXT: suba.l #4, %sp @@ -52,13 +52,13 @@ define fastcc void @test3(i64* inreg %a) nounwind { ; CHECK-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload ; CHECK-NEXT: adda.l #4, %sp ; CHECK-NEXT: rts - %aa = load i64, i64* %a + %aa = load i64, ptr %a %b = add i64 %aa, 2147483648 - store i64 %b, i64* %a + store i64 %b, ptr %a ret void } -define fastcc void @test4(i64* inreg %a) nounwind { +define fastcc void @test4(ptr inreg %a) nounwind { ; CHECK-LABEL: test4: ; CHECK: ; %bb.0: ; CHECK-NEXT: suba.l #4, %sp @@ -73,9 +73,9 @@ define fastcc void @test4(i64* inreg %a) nounwind { ; CHECK-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload ; CHECK-NEXT: adda.l #4, %sp ; CHECK-NEXT: rts - %aa = load i64, i64* %a + %aa = load i64, ptr %a %b = add i64 %aa, 128 - store i64 %b, i64* %a + store i64 %b, ptr %a ret void } diff --git a/llvm/test/CodeGen/M68k/Arith/bitwise.ll b/llvm/test/CodeGen/M68k/Arith/bitwise.ll index fa8ea1370f86..70e4dd42bfb6 100644 --- a/llvm/test/CodeGen/M68k/Arith/bitwise.ll +++ b/llvm/test/CodeGen/M68k/Arith/bitwise.ll @@ -117,7 +117,7 @@ define i32 @eorl(i32 %a, i32 %b) nounwind { ; op reg, imm ; For type i8 and i16, value is loaded from memory to avoid optimizing it to *.l -define void @andib(i8* %a) nounwind { +define void @andib(ptr %a) nounwind { ; CHECK-LABEL: andib: ; CHECK: ; %bb.0: ; CHECK-NEXT: move.l (4,%sp), %a0 @@ -125,13 +125,13 @@ define void @andib(i8* %a) nounwind { ; CHECK-NEXT: and.b #18, %d0 ; CHECK-NEXT: move.b %d0, (%a0) ; CHECK-NEXT: rts - %1 = load i8, i8* %a + %1 = load i8, ptr %a %2 = and i8 %1, 18 - store i8 %2, i8* %a + store i8 %2, ptr %a ret void } -define void @andiw(i16* %a) nounwind { +define void @andiw(ptr %a) nounwind { ; CHECK-LABEL: andiw: ; CHECK: ; %bb.0: ; CHECK-NEXT: move.l (4,%sp), %a0 @@ -139,9 +139,9 @@ define void @andiw(i16* %a) nounwind { ; CHECK-NEXT: and.w #4660, %d0 ; CHECK-NEXT: move.w %d0, (%a0) ; CHECK-NEXT: rts - %1 = load i16, i16* %a + %1 = load i16, ptr %a %2 = and i16 %1, 4660 - store i16 %2, i16* %a + store i16 %2, ptr %a ret void } @@ -155,7 +155,7 @@ define i32 @andil(i32 %a) nounwind { ret i32 %1 } -define void @orib(i8* %a) nounwind { +define void @orib(ptr %a) nounwind { ; CHECK-LABEL: orib: ; CHECK: ; %bb.0: ; CHECK-NEXT: move.l (4,%sp), %a0 @@ -163,13 +163,13 @@ define void @orib(i8* %a) nounwind { ; CHECK-NEXT: or.b #18, %d0 ; CHECK-NEXT: move.b %d0, (%a0) ; CHECK-NEXT: rts - %1 = load i8, i8* %a + %1 = load i8, ptr %a %2 = or i8 %1, 18 - store i8 %2, i8* %a + store i8 %2, ptr %a ret void } -define void @oriw(i16* %a) nounwind { +define void @oriw(ptr %a) nounwind { ; CHECK-LABEL: oriw: ; CHECK: ; %bb.0: ; CHECK-NEXT: move.l (4,%sp), %a0 @@ -177,9 +177,9 @@ define void @oriw(i16* %a) nounwind { ; CHECK-NEXT: or.w #4660, %d0 ; CHECK-NEXT: move.w %d0, (%a0) ; CHECK-NEXT: rts - %1 = load i16, i16* %a + %1 = load i16, ptr %a %2 = or i16 %1, 4660 - store i16 %2, i16* %a + store i16 %2, ptr %a ret void } @@ -193,7 +193,7 @@ define i32 @oril(i32 %a) nounwind { ret i32 %1 } -define void @eorib(i8* %a) nounwind { +define void @eorib(ptr %a) nounwind { ; CHECK-LABEL: eorib: ; CHECK: ; %bb.0: ; CHECK-NEXT: move.l (4,%sp), %a0 @@ -201,13 +201,13 @@ define void @eorib(i8* %a) nounwind { ; CHECK-NEXT: eori.b #18, %d0 ; CHECK-NEXT: move.b %d0, (%a0) ; CHECK-NEXT: rts - %1 = load i8, i8* %a + %1 = load i8, ptr %a %2 = xor i8 %1, 18 - store i8 %2, i8* %a + store i8 %2, ptr %a ret void } -define void @eoriw(i16* %a) nounwind { +define void @eoriw(ptr %a) nounwind { ; CHECK-LABEL: eoriw: ; CHECK: ; %bb.0: ; CHECK-NEXT: move.l (4,%sp), %a0 @@ -215,9 +215,9 @@ define void @eoriw(i16* %a) nounwind { ; CHECK-NEXT: eori.w #4660, %d0 ; CHECK-NEXT: move.w %d0, (%a0) ; CHECK-NEXT: rts - %1 = load i16, i16* %a + %1 = load i16, ptr %a %2 = xor i16 %1, 4660 - store i16 %2, i16* %a + store i16 %2, ptr %a ret void } diff --git a/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll b/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll index b649b2ba1614..5bd4d5d48bc8 100644 --- a/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll +++ b/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll @@ -54,7 +54,7 @@ entry: declare { i16, i1 } @llvm.smul.with.overflow.i16(i16, i16) nounwind readnone -declare i32 @printf(i8*, ...) nounwind +declare i32 @printf(ptr, ...) nounwind declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32) @ok = internal constant [4 x i8] c"%d\0A\00" @@ -88,11 +88,11 @@ entry: br i1 %obit, label %overflow, label %normal normal: - %t1 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind + %t1 = tail call i32 (ptr, ...) @printf( ptr @ok, i32 %sum ) nounwind ret i1 true overflow: - %t2 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @no, i32 0, i32 0) ) nounwind + %t2 = tail call i32 (ptr, ...) @printf( ptr @no ) nounwind ret i1 false } @@ -126,11 +126,11 @@ entry: br i1 %obit, label %overflow, label %normal overflow: - %t2 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @no, i32 0, i32 0) ) nounwind + %t2 = tail call i32 (ptr, ...) @printf( ptr @no ) nounwind ret i1 false normal: - %t1 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind + %t1 = tail call i32 (ptr, ...) @printf( ptr @ok, i32 %sum ) nounwind ret i1 true } diff --git a/llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll b/llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll index da6d78a49288..8d47c7ebf7e5 100644 --- a/llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll +++ b/llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=m68k-linux -verify-machineinstrs | FileCheck %s -declare i32 @printf(i8*, ...) nounwind +declare i32 @printf(ptr, ...) nounwind declare {i32, i1} @llvm.ssub.with.overflow.i32(i32, i32) declare {i32, i1} @llvm.usub.with.overflow.i32(i32, i32) @@ -37,11 +37,11 @@ entry: br i1 %obit, label %overflow, label %normal normal: - %t1 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind + %t1 = tail call i32 (ptr, ...) @printf( ptr @ok, i32 %sum ) nounwind ret i1 true overflow: - %t2 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @no, i32 0, i32 0) ) nounwind + %t2 = tail call i32 (ptr, ...) @printf( ptr @no ) nounwind ret i1 false } @@ -74,11 +74,11 @@ entry: br i1 %obit, label %carry, label %normal normal: - %t1 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind + %t1 = tail call i32 (ptr, ...) @printf( ptr @ok, i32 %sum ) nounwind ret i1 true carry: - %t2 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @no, i32 0, i32 0) ) nounwind + %t2 = tail call i32 (ptr, ...) @printf( ptr @no ) nounwind ret i1 false } diff --git a/llvm/test/CodeGen/M68k/Atomics/load-store.ll b/llvm/test/CodeGen/M68k/Atomics/load-store.ll index 7608edb220d3..b238172c2f12 100644 --- a/llvm/test/CodeGen/M68k/Atomics/load-store.ll +++ b/llvm/test/CodeGen/M68k/Atomics/load-store.ll @@ -5,7 +5,7 @@ ; RUN: llc %s -o - -mtriple=m68k -mcpu=M68030 | FileCheck %s --check-prefix=ATOMIC ; RUN: llc %s -o - -mtriple=m68k -mcpu=M68040 | FileCheck %s --check-prefix=ATOMIC -define i8 @atomic_load_i8_unordered(i8 *%a) nounwind { +define i8 @atomic_load_i8_unordered(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i8_unordered: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (4,%sp), %a0 @@ -17,11 +17,11 @@ define i8 @atomic_load_i8_unordered(i8 *%a) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.b (%a0), %d0 ; ATOMIC-NEXT: rts - %1 = load atomic i8, i8* %a unordered, align 1 + %1 = load atomic i8, ptr %a unordered, align 1 ret i8 %1 } -define i8 @atomic_load_i8_monotonic(i8 *%a) nounwind { +define i8 @atomic_load_i8_monotonic(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i8_monotonic: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (4,%sp), %a0 @@ -33,11 +33,11 @@ define i8 @atomic_load_i8_monotonic(i8 *%a) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.b (%a0), %d0 ; ATOMIC-NEXT: rts - %1 = load atomic i8, i8* %a monotonic, align 1 + %1 = load atomic i8, ptr %a monotonic, align 1 ret i8 %1 } -define i8 @atomic_load_i8_acquire(i8 *%a) nounwind { +define i8 @atomic_load_i8_acquire(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i8_acquire: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (4,%sp), %a0 @@ -49,11 +49,11 @@ define i8 @atomic_load_i8_acquire(i8 *%a) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.b (%a0), %d0 ; ATOMIC-NEXT: rts - %1 = load atomic i8, i8* %a acquire, align 1 + %1 = load atomic i8, ptr %a acquire, align 1 ret i8 %1 } -define i8 @atomic_load_i8_seq_cst(i8 *%a) nounwind { +define i8 @atomic_load_i8_seq_cst(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i8_seq_cst: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (4,%sp), %a0 @@ -65,11 +65,11 @@ define i8 @atomic_load_i8_seq_cst(i8 *%a) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.b (%a0), %d0 ; ATOMIC-NEXT: rts - %1 = load atomic i8, i8* %a seq_cst, align 1 + %1 = load atomic i8, ptr %a seq_cst, align 1 ret i8 %1 } -define i16 @atomic_load_i16_unordered(i16 *%a) nounwind { +define i16 @atomic_load_i16_unordered(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i16_unordered: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (4,%sp), %a0 @@ -81,11 +81,11 @@ define i16 @atomic_load_i16_unordered(i16 *%a) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.w (%a0), %d0 ; ATOMIC-NEXT: rts - %1 = load atomic i16, i16* %a unordered, align 2 + %1 = load atomic i16, ptr %a unordered, align 2 ret i16 %1 } -define i16 @atomic_load_i16_monotonic(i16 *%a) nounwind { +define i16 @atomic_load_i16_monotonic(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i16_monotonic: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (4,%sp), %a0 @@ -97,11 +97,11 @@ define i16 @atomic_load_i16_monotonic(i16 *%a) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.w (%a0), %d0 ; ATOMIC-NEXT: rts - %1 = load atomic i16, i16* %a monotonic, align 2 + %1 = load atomic i16, ptr %a monotonic, align 2 ret i16 %1 } -define i16 @atomic_load_i16_acquire(i16 *%a) nounwind { +define i16 @atomic_load_i16_acquire(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i16_acquire: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (4,%sp), %a0 @@ -113,11 +113,11 @@ define i16 @atomic_load_i16_acquire(i16 *%a) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.w (%a0), %d0 ; ATOMIC-NEXT: rts - %1 = load atomic i16, i16* %a acquire, align 2 + %1 = load atomic i16, ptr %a acquire, align 2 ret i16 %1 } -define i16 @atomic_load_i16_seq_cst(i16 *%a) nounwind { +define i16 @atomic_load_i16_seq_cst(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i16_seq_cst: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (4,%sp), %a0 @@ -129,11 +129,11 @@ define i16 @atomic_load_i16_seq_cst(i16 *%a) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.w (%a0), %d0 ; ATOMIC-NEXT: rts - %1 = load atomic i16, i16* %a seq_cst, align 2 + %1 = load atomic i16, ptr %a seq_cst, align 2 ret i16 %1 } -define i32 @atomic_load_i32_unordered(i32 *%a) nounwind { +define i32 @atomic_load_i32_unordered(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i32_unordered: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (4,%sp), %a0 @@ -145,11 +145,11 @@ define i32 @atomic_load_i32_unordered(i32 *%a) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.l (%a0), %d0 ; ATOMIC-NEXT: rts - %1 = load atomic i32, i32* %a unordered, align 4 + %1 = load atomic i32, ptr %a unordered, align 4 ret i32 %1 } -define i32 @atomic_load_i32_monotonic(i32 *%a) nounwind { +define i32 @atomic_load_i32_monotonic(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i32_monotonic: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (4,%sp), %a0 @@ -161,11 +161,11 @@ define i32 @atomic_load_i32_monotonic(i32 *%a) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.l (%a0), %d0 ; ATOMIC-NEXT: rts - %1 = load atomic i32, i32* %a monotonic, align 4 + %1 = load atomic i32, ptr %a monotonic, align 4 ret i32 %1 } -define i32 @atomic_load_i32_acquire(i32 *%a) nounwind { +define i32 @atomic_load_i32_acquire(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i32_acquire: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (4,%sp), %a0 @@ -177,11 +177,11 @@ define i32 @atomic_load_i32_acquire(i32 *%a) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.l (%a0), %d0 ; ATOMIC-NEXT: rts - %1 = load atomic i32, i32* %a acquire, align 4 + %1 = load atomic i32, ptr %a acquire, align 4 ret i32 %1 } -define i32 @atomic_load_i32_seq_cst(i32 *%a) nounwind { +define i32 @atomic_load_i32_seq_cst(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i32_seq_cst: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (4,%sp), %a0 @@ -193,11 +193,11 @@ define i32 @atomic_load_i32_seq_cst(i32 *%a) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.l (%a0), %d0 ; ATOMIC-NEXT: rts - %1 = load atomic i32, i32* %a seq_cst, align 4 + %1 = load atomic i32, ptr %a seq_cst, align 4 ret i32 %1 } -define i64 @atomic_load_i64_unordered(i64 *%a) nounwind { +define i64 @atomic_load_i64_unordered(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i64_unordered: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: suba.l #12, %sp @@ -215,11 +215,11 @@ define i64 @atomic_load_i64_unordered(i64 *%a) nounwind { ; ATOMIC-NEXT: jsr __atomic_load_8@PLT ; ATOMIC-NEXT: adda.l #12, %sp ; ATOMIC-NEXT: rts - %1 = load atomic i64, i64* %a unordered, align 8 + %1 = load atomic i64, ptr %a unordered, align 8 ret i64 %1 } -define i64 @atomic_load_i64_monotonic(i64 *%a) nounwind { +define i64 @atomic_load_i64_monotonic(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i64_monotonic: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: suba.l #12, %sp @@ -237,11 +237,11 @@ define i64 @atomic_load_i64_monotonic(i64 *%a) nounwind { ; ATOMIC-NEXT: jsr __atomic_load_8@PLT ; ATOMIC-NEXT: adda.l #12, %sp ; ATOMIC-NEXT: rts - %1 = load atomic i64, i64* %a monotonic, align 8 + %1 = load atomic i64, ptr %a monotonic, align 8 ret i64 %1 } -define i64 @atomic_load_i64_acquire(i64 *%a) nounwind { +define i64 @atomic_load_i64_acquire(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i64_acquire: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: suba.l #12, %sp @@ -259,11 +259,11 @@ define i64 @atomic_load_i64_acquire(i64 *%a) nounwind { ; ATOMIC-NEXT: jsr __atomic_load_8@PLT ; ATOMIC-NEXT: adda.l #12, %sp ; ATOMIC-NEXT: rts - %1 = load atomic i64, i64* %a acquire, align 8 + %1 = load atomic i64, ptr %a acquire, align 8 ret i64 %1 } -define i64 @atomic_load_i64_seq_cst(i64 *%a) nounwind { +define i64 @atomic_load_i64_seq_cst(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i64_seq_cst: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: suba.l #12, %sp @@ -281,11 +281,11 @@ define i64 @atomic_load_i64_seq_cst(i64 *%a) nounwind { ; ATOMIC-NEXT: jsr __atomic_load_8@PLT ; ATOMIC-NEXT: adda.l #12, %sp ; ATOMIC-NEXT: rts - %1 = load atomic i64, i64* %a seq_cst, align 8 + %1 = load atomic i64, ptr %a seq_cst, align 8 ret i64 %1 } -define void @atomic_store_i8_unordered(i8 *%a, i8 %val) nounwind { +define void @atomic_store_i8_unordered(ptr %a, i8 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i8_unordered: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.b (11,%sp), %d0 @@ -299,11 +299,11 @@ define void @atomic_store_i8_unordered(i8 *%a, i8 %val) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.b %d0, (%a0) ; ATOMIC-NEXT: rts - store atomic i8 %val, i8* %a unordered, align 1 + store atomic i8 %val, ptr %a unordered, align 1 ret void } -define void @atomic_store_i8_monotonic(i8 *%a, i8 %val) nounwind { +define void @atomic_store_i8_monotonic(ptr %a, i8 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i8_monotonic: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.b (11,%sp), %d0 @@ -317,11 +317,11 @@ define void @atomic_store_i8_monotonic(i8 *%a, i8 %val) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.b %d0, (%a0) ; ATOMIC-NEXT: rts - store atomic i8 %val, i8* %a monotonic, align 1 + store atomic i8 %val, ptr %a monotonic, align 1 ret void } -define void @atomic_store_i8_release(i8 *%a, i8 %val) nounwind { +define void @atomic_store_i8_release(ptr %a, i8 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i8_release: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.b (11,%sp), %d0 @@ -335,11 +335,11 @@ define void @atomic_store_i8_release(i8 *%a, i8 %val) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.b %d0, (%a0) ; ATOMIC-NEXT: rts - store atomic i8 %val, i8* %a release, align 1 + store atomic i8 %val, ptr %a release, align 1 ret void } -define void @atomic_store_i8_seq_cst(i8 *%a, i8 %val) nounwind { +define void @atomic_store_i8_seq_cst(ptr %a, i8 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i8_seq_cst: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.b (11,%sp), %d0 @@ -353,11 +353,11 @@ define void @atomic_store_i8_seq_cst(i8 *%a, i8 %val) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.b %d0, (%a0) ; ATOMIC-NEXT: rts - store atomic i8 %val, i8* %a seq_cst, align 1 + store atomic i8 %val, ptr %a seq_cst, align 1 ret void } -define void @atomic_store_i16_unordered(i16 *%a, i16 %val) nounwind { +define void @atomic_store_i16_unordered(ptr %a, i16 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i16_unordered: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.w (10,%sp), %d0 @@ -371,11 +371,11 @@ define void @atomic_store_i16_unordered(i16 *%a, i16 %val) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.w %d0, (%a0) ; ATOMIC-NEXT: rts - store atomic i16 %val, i16* %a unordered, align 2 + store atomic i16 %val, ptr %a unordered, align 2 ret void } -define void @atomic_store_i16_monotonic(i16 *%a, i16 %val) nounwind { +define void @atomic_store_i16_monotonic(ptr %a, i16 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i16_monotonic: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.w (10,%sp), %d0 @@ -389,11 +389,11 @@ define void @atomic_store_i16_monotonic(i16 *%a, i16 %val) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.w %d0, (%a0) ; ATOMIC-NEXT: rts - store atomic i16 %val, i16* %a monotonic, align 2 + store atomic i16 %val, ptr %a monotonic, align 2 ret void } -define void @atomic_store_i16_release(i16 *%a, i16 %val) nounwind { +define void @atomic_store_i16_release(ptr %a, i16 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i16_release: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.w (10,%sp), %d0 @@ -407,11 +407,11 @@ define void @atomic_store_i16_release(i16 *%a, i16 %val) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.w %d0, (%a0) ; ATOMIC-NEXT: rts - store atomic i16 %val, i16* %a release, align 2 + store atomic i16 %val, ptr %a release, align 2 ret void } -define void @atomic_store_i16_seq_cst(i16 *%a, i16 %val) nounwind { +define void @atomic_store_i16_seq_cst(ptr %a, i16 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i16_seq_cst: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.w (10,%sp), %d0 @@ -425,11 +425,11 @@ define void @atomic_store_i16_seq_cst(i16 *%a, i16 %val) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.w %d0, (%a0) ; ATOMIC-NEXT: rts - store atomic i16 %val, i16* %a seq_cst, align 2 + store atomic i16 %val, ptr %a seq_cst, align 2 ret void } -define void @atomic_store_i32_unordered(i32 *%a, i32 %val) nounwind { +define void @atomic_store_i32_unordered(ptr %a, i32 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i32_unordered: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (8,%sp), %d0 @@ -443,11 +443,11 @@ define void @atomic_store_i32_unordered(i32 *%a, i32 %val) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.l %d0, (%a0) ; ATOMIC-NEXT: rts - store atomic i32 %val, i32* %a unordered, align 4 + store atomic i32 %val, ptr %a unordered, align 4 ret void } -define void @atomic_store_i32_monotonic(i32 *%a, i32 %val) nounwind { +define void @atomic_store_i32_monotonic(ptr %a, i32 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i32_monotonic: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (8,%sp), %d0 @@ -461,11 +461,11 @@ define void @atomic_store_i32_monotonic(i32 *%a, i32 %val) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.l %d0, (%a0) ; ATOMIC-NEXT: rts - store atomic i32 %val, i32* %a monotonic, align 4 + store atomic i32 %val, ptr %a monotonic, align 4 ret void } -define void @atomic_store_i32_release(i32 *%a, i32 %val) nounwind { +define void @atomic_store_i32_release(ptr %a, i32 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i32_release: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (8,%sp), %d0 @@ -479,11 +479,11 @@ define void @atomic_store_i32_release(i32 *%a, i32 %val) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.l %d0, (%a0) ; ATOMIC-NEXT: rts - store atomic i32 %val, i32* %a release, align 4 + store atomic i32 %val, ptr %a release, align 4 ret void } -define void @atomic_store_i32_seq_cst(i32 *%a, i32 %val) nounwind { +define void @atomic_store_i32_seq_cst(ptr %a, i32 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i32_seq_cst: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (8,%sp), %d0 @@ -497,11 +497,11 @@ define void @atomic_store_i32_seq_cst(i32 *%a, i32 %val) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.l %d0, (%a0) ; ATOMIC-NEXT: rts - store atomic i32 %val, i32* %a seq_cst, align 4 + store atomic i32 %val, ptr %a seq_cst, align 4 ret void } -define void @atomic_store_i64_unordered(i64 *%a, i64 %val) nounwind { +define void @atomic_store_i64_unordered(ptr %a, i64 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i64_unordered: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: suba.l #20, %sp @@ -523,11 +523,11 @@ define void @atomic_store_i64_unordered(i64 *%a, i64 %val) nounwind { ; ATOMIC-NEXT: jsr __atomic_store_8@PLT ; ATOMIC-NEXT: adda.l #20, %sp ; ATOMIC-NEXT: rts - store atomic i64 %val, i64* %a unordered, align 8 + store atomic i64 %val, ptr %a unordered, align 8 ret void } -define void @atomic_store_i64_monotonic(i64 *%a, i64 %val) nounwind { +define void @atomic_store_i64_monotonic(ptr %a, i64 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i64_monotonic: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: suba.l #20, %sp @@ -549,11 +549,11 @@ define void @atomic_store_i64_monotonic(i64 *%a, i64 %val) nounwind { ; ATOMIC-NEXT: jsr __atomic_store_8@PLT ; ATOMIC-NEXT: adda.l #20, %sp ; ATOMIC-NEXT: rts - store atomic i64 %val, i64* %a monotonic, align 8 + store atomic i64 %val, ptr %a monotonic, align 8 ret void } -define void @atomic_store_i64_release(i64 *%a, i64 %val) nounwind { +define void @atomic_store_i64_release(ptr %a, i64 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i64_release: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: suba.l #20, %sp @@ -575,11 +575,11 @@ define void @atomic_store_i64_release(i64 *%a, i64 %val) nounwind { ; ATOMIC-NEXT: jsr __atomic_store_8@PLT ; ATOMIC-NEXT: adda.l #20, %sp ; ATOMIC-NEXT: rts - store atomic i64 %val, i64* %a release, align 8 + store atomic i64 %val, ptr %a release, align 8 ret void } -define void @atomic_store_i64_seq_cst(i64 *%a, i64 %val) nounwind { +define void @atomic_store_i64_seq_cst(ptr %a, i64 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i64_seq_cst: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: suba.l #20, %sp @@ -601,6 +601,6 @@ define void @atomic_store_i64_seq_cst(i64 *%a, i64 %val) nounwind { ; ATOMIC-NEXT: jsr __atomic_store_8@PLT ; ATOMIC-NEXT: adda.l #20, %sp ; ATOMIC-NEXT: rts - store atomic i64 %val, i64* %a seq_cst, align 8 + store atomic i64 %val, ptr %a seq_cst, align 8 ret void } diff --git a/llvm/test/CodeGen/M68k/CConv/c-args-inreg.ll b/llvm/test/CodeGen/M68k/CConv/c-args-inreg.ll index 5eee426462cf..f0ccd8c09e53 100644 --- a/llvm/test/CodeGen/M68k/CConv/c-args-inreg.ll +++ b/llvm/test/CodeGen/M68k/CConv/c-args-inreg.ll @@ -4,18 +4,18 @@ ; ; Pass first two arguments in registers %d0 and %d1 -define void @foo_inreg(i32* nocapture inreg %out, i32 inreg %in) nounwind { +define void @foo_inreg(ptr nocapture inreg %out, i32 inreg %in) nounwind { ; CHECK-LABEL: foo_inreg: ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: move.l %d0, %a0 ; CHECK-NEXT: move.l %d1, (%a0) ; CHECK-NEXT: rts entry: - store i32 %in, i32* %out, align 4 + store i32 %in, ptr %out, align 4 ret void } -define void @bar_inreg(i32* nocapture inreg %pOut, i32* nocapture inreg %pIn) nounwind { +define void @bar_inreg(ptr nocapture inreg %pOut, ptr nocapture inreg %pIn) nounwind { ; CHECK-LABEL: bar_inreg: ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: move.l %d1, %a0 @@ -23,7 +23,7 @@ define void @bar_inreg(i32* nocapture inreg %pOut, i32* nocapture inreg %pIn) no ; CHECK-NEXT: move.l (%a0), (%a1) ; CHECK-NEXT: rts entry: - %0 = load i32, i32* %pIn, align 4 - store i32 %0, i32* %pOut, align 4 + %0 = load i32, ptr %pIn, align 4 + store i32 %0, ptr %pOut, align 4 ret void } diff --git a/llvm/test/CodeGen/M68k/CConv/c-args.ll b/llvm/test/CodeGen/M68k/CConv/c-args.ll index c5477e2812ca..c7e356ef349b 100644 --- a/llvm/test/CodeGen/M68k/CConv/c-args.ll +++ b/llvm/test/CodeGen/M68k/CConv/c-args.ll @@ -4,18 +4,18 @@ ; ; C Call passes all arguments on stack ... -define void @test1(i32* nocapture %out, i32 %in) nounwind { +define void @test1(ptr nocapture %out, i32 %in) nounwind { ; CHECK-LABEL: test1: ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: move.l (4,%sp), %a0 ; CHECK-NEXT: move.l (8,%sp), (%a0) ; CHECK-NEXT: rts entry: - store i32 %in, i32* %out, align 4 + store i32 %in, ptr %out, align 4 ret void } -define void @test2(i32* nocapture %pOut, i32* nocapture %pIn) nounwind { +define void @test2(ptr nocapture %pOut, ptr nocapture %pIn) nounwind { ; CHECK-LABEL: test2: ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: move.l (8,%sp), %a0 @@ -23,30 +23,30 @@ define void @test2(i32* nocapture %pOut, i32* nocapture %pIn) nounwind { ; CHECK-NEXT: move.l (%a0), (%a1) ; CHECK-NEXT: rts entry: - %0 = load i32, i32* %pIn, align 4 - store i32 %0, i32* %pOut, align 4 + %0 = load i32, ptr %pIn, align 4 + store i32 %0, ptr %pOut, align 4 ret void } -define void @test3(i8* nocapture %out, i8 %in) nounwind { +define void @test3(ptr nocapture %out, i8 %in) nounwind { ; CHECK-LABEL: test3: ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: move.l (4,%sp), %a0 ; CHECK-NEXT: move.b (11,%sp), (%a0) ; CHECK-NEXT: rts entry: - store i8 %in, i8* %out, align 1 + store i8 %in, ptr %out, align 1 ret void } -define void @test4(i16* nocapture %out, i16 %in) nounwind { +define void @test4(ptr nocapture %out, i16 %in) nounwind { ; CHECK-LABEL: test4: ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: move.l (4,%sp), %a0 ; CHECK-NEXT: move.w (10,%sp), (%a0) ; CHECK-NEXT: rts entry: - store i16 %in, i16* %out, align 2 + store i16 %in, ptr %out, align 2 ret void } diff --git a/llvm/test/CodeGen/M68k/CConv/fastcc-args.ll b/llvm/test/CodeGen/M68k/CConv/fastcc-args.ll index 55c0b9f449e7..12ba97e26178 100644 --- a/llvm/test/CodeGen/M68k/CConv/fastcc-args.ll +++ b/llvm/test/CodeGen/M68k/CConv/fastcc-args.ll @@ -3,24 +3,24 @@ ; ; C Call passes all arguments on stack ... -define fastcc void @test1(i32* nocapture %out, i32 %in) nounwind { +define fastcc void @test1(ptr nocapture %out, i32 %in) nounwind { ; CHECK-LABEL: test1: ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: move.l %d0, (%a0) ; CHECK-NEXT: rts entry: - store i32 %in, i32* %out, align 4 + store i32 %in, ptr %out, align 4 ret void } -define fastcc void @test2(i32* nocapture %pOut, i32* nocapture %pIn) nounwind { +define fastcc void @test2(ptr nocapture %pOut, ptr nocapture %pIn) nounwind { ; CHECK-LABEL: test2: ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: move.l (%a1), (%a0) ; CHECK-NEXT: rts entry: - %0 = load i32, i32* %pIn, align 4 - store i32 %0, i32* %pOut, align 4 + %0 = load i32, ptr %pIn, align 4 + store i32 %0, ptr %pOut, align 4 ret void } diff --git a/llvm/test/CodeGen/M68k/CConv/fastcc-call.ll b/llvm/test/CodeGen/M68k/CConv/fastcc-call.ll index 5931f76d70b1..4b0f8ed254a5 100644 --- a/llvm/test/CodeGen/M68k/CConv/fastcc-call.ll +++ b/llvm/test/CodeGen/M68k/CConv/fastcc-call.ll @@ -44,8 +44,8 @@ define i32 @foo2() nounwind uwtable { entry: %a = alloca i32, align 4 %b = alloca i32, align 4 - call fastcc void @bar2(i32* %a, i32 2, i32* %b, i32 4) nounwind + call fastcc void @bar2(ptr %a, i32 2, ptr %b, i32 4) nounwind ret i32 0 } -declare fastcc void @bar2(i32* %a, i32 %b, i32* %c, i32 %d); +declare fastcc void @bar2(ptr %a, i32 %b, ptr %c, i32 %d); diff --git a/llvm/test/CodeGen/M68k/CodeModel/medium-pic.ll b/llvm/test/CodeGen/M68k/CodeModel/medium-pic.ll index 2ab3115f87f5..407bbd48bc7f 100644 --- a/llvm/test/CodeGen/M68k/CodeModel/medium-pic.ll +++ b/llvm/test/CodeGen/M68k/CodeModel/medium-pic.ll @@ -3,7 +3,7 @@ ; RUN: -code-model=medium -relocation-model=pic \ ; RUN: | FileCheck %s -@ptr = external global i32* +@ptr = external global ptr @dst = external global i32 @src = external global i32 @@ -17,13 +17,13 @@ define void @test0() nounwind { ; CHECK-NEXT: move.l (%a1), (%a0) ; CHECK-NEXT: rts entry: - store i32* @dst, i32** @ptr - %tmp.s = load i32, i32* @src - store i32 %tmp.s, i32* @dst + store ptr @dst, ptr @ptr + %tmp.s = load i32, ptr @src + store i32 %tmp.s, ptr @dst ret void } -@ptr2 = global i32* null +@ptr2 = global ptr null @dst2 = global i32 0 @src2 = global i32 0 @@ -37,13 +37,13 @@ define void @test1() nounwind { ; CHECK-NEXT: move.l (%a1), (%a0) ; CHECK-NEXT: rts entry: - store i32* @dst2, i32** @ptr2 - %tmp.s = load i32, i32* @src2 - store i32 %tmp.s, i32* @dst2 + store ptr @dst2, ptr @ptr2 + %tmp.s = load i32, ptr @src2 + store i32 %tmp.s, ptr @dst2 ret void } -declare i8* @malloc(i32) +declare ptr @malloc(i32) define void @test2() nounwind { ; CHECK-LABEL: test2: @@ -54,12 +54,12 @@ define void @test2() nounwind { ; CHECK-NEXT: adda.l #4, %sp ; CHECK-NEXT: rts entry: - %ptr = call i8* @malloc(i32 40) + %ptr = call ptr @malloc(i32 40) ret void } -@pfoo = external global void(...)* -declare void(...)* @afoo(...) +@pfoo = external global ptr +declare ptr @afoo(...) define void @test3() nounwind { ; CHECK-LABEL: test3: @@ -72,9 +72,9 @@ define void @test3() nounwind { ; CHECK-NEXT: adda.l #4, %sp ; CHECK-NEXT: rts entry: - %tmp = call void(...)*(...) @afoo() - store void(...)* %tmp, void(...)** @pfoo - %tmp1 = load void(...)*, void(...)** @pfoo + %tmp = call ptr(...) @afoo() + store ptr %tmp, ptr @pfoo + %tmp1 = load ptr, ptr @pfoo call void(...) %tmp1() ret void } @@ -93,7 +93,7 @@ entry: ret void } -@ptr6 = internal global i32* null +@ptr6 = internal global ptr null @dst6 = internal global i32 0 @src6 = internal global i32 0 @@ -110,9 +110,9 @@ define void @test5() nounwind { ; CHECK-NEXT: move.l (0,%a0,%d0), (0,%a0,%d1) ; CHECK-NEXT: rts entry: - store i32* @dst6, i32** @ptr6 - %tmp.s = load i32, i32* @src6 - store i32 %tmp.s, i32* @dst6 + store ptr @dst6, ptr @ptr6 + %tmp.s = load i32, ptr @src6 + store i32 %tmp.s, ptr @dst6 ret void } diff --git a/llvm/test/CodeGen/M68k/CodeModel/medium-pie-global-access.ll b/llvm/test/CodeGen/M68k/CodeModel/medium-pie-global-access.ll index aca79f001737..ce8f2d0a6ba7 100644 --- a/llvm/test/CodeGen/M68k/CodeModel/medium-pie-global-access.ll +++ b/llvm/test/CodeGen/M68k/CodeModel/medium-pie-global-access.ll @@ -14,7 +14,7 @@ define i32 @my_access_global_a() #0 { ; CHECK-NEXT: move.l (%a0), %d0 ; CHECK-NEXT: rts entry: - %0 = load i32, i32* @a, align 4 + %0 = load i32, ptr @a, align 4 ret i32 %0 } @@ -29,7 +29,7 @@ define i32 @my_access_global_b() #0 { ; CHECK-NEXT: move.l (%a0), %d0 ; CHECK-NEXT: rts entry: - %0 = load i32, i32* @b, align 4 + %0 = load i32, ptr @b, align 4 ret i32 %0 } @@ -45,7 +45,7 @@ define i32 @my_access_global_c() #0 { ; CHECK-NEXT: move.l (0,%a0,%d0), %d0 ; CHECK-NEXT: rts entry: - %0 = load i32, i32* @c, align 4 + %0 = load i32, ptr @c, align 4 ret i32 %0 } @@ -60,7 +60,7 @@ define i32 @my_access_global_load_d() #0 { ; CHECK-NEXT: move.l (%a0), %d0 ; CHECK-NEXT: rts entry: - %0 = load i32, i32* @d, align 4 + %0 = load i32, ptr @d, align 4 ret i32 %0 } @@ -74,12 +74,12 @@ define i32 @my_access_global_store_d() #0 { ; CHECK-NEXT: move.l #0, %d0 ; CHECK-NEXT: rts entry: - store i32 2, i32* @d, align 4 + store i32 2, ptr @d, align 4 ret i32 0 } ; External Linkage, function pointer access. -declare i32 @access_fp(i32 ()*) +declare i32 @access_fp(ptr) declare i32 @foo() define i32 @my_access_fp_foo() #0 { @@ -93,7 +93,7 @@ define i32 @my_access_fp_foo() #0 { ; CHECK-NEXT: adda.l #4, %sp ; CHECK-NEXT: rts entry: - %call = call i32 @access_fp(i32 ()* @foo) + %call = call i32 @access_fp(ptr @foo) ret i32 %call } @@ -122,7 +122,7 @@ define i32 @my_access_fp_bar() #0 { ; CHECK-NEXT: adda.l #4, %sp ; CHECK-NEXT: rts entry: - %call = call i32 @access_fp(i32 ()* @bar) + %call = call i32 @access_fp(ptr @bar) ret i32 %call } diff --git a/llvm/test/CodeGen/M68k/CodeModel/medium-static.ll b/llvm/test/CodeGen/M68k/CodeModel/medium-static.ll index 1a544a971d26..87d8380d6cc9 100644 --- a/llvm/test/CodeGen/M68k/CodeModel/medium-static.ll +++ b/llvm/test/CodeGen/M68k/CodeModel/medium-static.ll @@ -3,7 +3,7 @@ ; RUN: -code-model=medium -relocation-model=static \ ; RUN: | FileCheck %s -@ptr = external global i32* +@ptr = external global ptr @dst = external global i32 @src = external global i32 @@ -14,13 +14,13 @@ define void @test0() nounwind { ; CHECK-NEXT: move.l src, dst ; CHECK-NEXT: rts entry: - store i32* @dst, i32** @ptr - %tmp.s = load i32, i32* @src - store i32 %tmp.s, i32* @dst + store ptr @dst, ptr @ptr + %tmp.s = load i32, ptr @src + store i32 %tmp.s, ptr @dst ret void } -@ptr2 = global i32* null +@ptr2 = global ptr null @dst2 = global i32 0 @src2 = global i32 0 @@ -31,13 +31,13 @@ define void @test1() nounwind { ; CHECK-NEXT: move.l src2, dst2 ; CHECK-NEXT: rts entry: - store i32* @dst2, i32** @ptr2 - %tmp.s = load i32, i32* @src2 - store i32 %tmp.s, i32* @dst2 + store ptr @dst2, ptr @ptr2 + %tmp.s = load i32, ptr @src2 + store i32 %tmp.s, ptr @dst2 ret void } -declare i8* @malloc(i32) +declare ptr @malloc(i32) define void @test2() nounwind { ; CHECK-LABEL: test2: @@ -48,12 +48,12 @@ define void @test2() nounwind { ; CHECK-NEXT: adda.l #4, %sp ; CHECK-NEXT: rts entry: - %ptr = call i8* @malloc(i32 40) + %ptr = call ptr @malloc(i32 40) ret void } -@pfoo = external global void(...)* -declare void(...)* @afoo(...) +@pfoo = external global ptr +declare ptr @afoo(...) define void @test3() nounwind { @@ -66,9 +66,9 @@ define void @test3() nounwind { ; CHECK-NEXT: adda.l #4, %sp ; CHECK-NEXT: rts entry: - %tmp = call void(...)*(...) @afoo() - store void(...)* %tmp, void(...)** @pfoo - %tmp1 = load void(...)*, void(...)** @pfoo + %tmp = call ptr(...) @afoo() + store ptr %tmp, ptr @pfoo + %tmp1 = load ptr, ptr @pfoo call void(...) %tmp1() ret void } @@ -87,7 +87,7 @@ entry: ret void } -@ptr6 = internal global i32* null +@ptr6 = internal global ptr null @dst6 = internal global i32 0 @src6 = internal global i32 0 @@ -98,9 +98,9 @@ define void @test5() nounwind { ; CHECK-NEXT: move.l src6, dst6 ; CHECK-NEXT: rts entry: - store i32* @dst6, i32** @ptr6 - %tmp.s = load i32, i32* @src6 - store i32 %tmp.s, i32* @dst6 + store ptr @dst6, ptr @ptr6 + %tmp.s = load i32, ptr @src6 + store i32 %tmp.s, ptr @dst6 ret void } diff --git a/llvm/test/CodeGen/M68k/CodeModel/small-pic.ll b/llvm/test/CodeGen/M68k/CodeModel/small-pic.ll index 1f39ec82db32..37115953e5be 100644 --- a/llvm/test/CodeGen/M68k/CodeModel/small-pic.ll +++ b/llvm/test/CodeGen/M68k/CodeModel/small-pic.ll @@ -3,7 +3,7 @@ ; RUN: -code-model=small -relocation-model=pic \ ; RUN: | FileCheck %s -@ptr = external global i32* +@ptr = external global ptr @dst = external global i32 @src = external global i32 @@ -17,13 +17,13 @@ define void @test0() nounwind { ; CHECK-NEXT: move.l (%a1), (%a0) ; CHECK-NEXT: rts entry: - store i32* @dst, i32** @ptr - %tmp.s = load i32, i32* @src - store i32 %tmp.s, i32* @dst + store ptr @dst, ptr @ptr + %tmp.s = load i32, ptr @src + store i32 %tmp.s, ptr @dst ret void } -@ptr2 = global i32* null +@ptr2 = global ptr null @dst2 = global i32 0 @src2 = global i32 0 @@ -37,13 +37,13 @@ define void @test1() nounwind { ; CHECK-NEXT: move.l (%a1), (%a0) ; CHECK-NEXT: rts entry: - store i32* @dst2, i32** @ptr2 - %tmp.s = load i32, i32* @src2 - store i32 %tmp.s, i32* @dst2 + store ptr @dst2, ptr @ptr2 + %tmp.s = load i32, ptr @src2 + store i32 %tmp.s, ptr @dst2 ret void } -declare i8* @malloc(i32) +declare ptr @malloc(i32) define void @test2() nounwind { ; CHECK-LABEL: test2: @@ -54,12 +54,12 @@ define void @test2() nounwind { ; CHECK-NEXT: adda.l #4, %sp ; CHECK-NEXT: rts entry: - %ptr = call i8* @malloc(i32 40) + %ptr = call ptr @malloc(i32 40) ret void } -@pfoo = external global void(...)* -declare void(...)* @afoo(...) +@pfoo = external global ptr +declare ptr @afoo(...) define void @test3() nounwind { ; CHECK-LABEL: test3: @@ -72,9 +72,9 @@ define void @test3() nounwind { ; CHECK-NEXT: adda.l #4, %sp ; CHECK-NEXT: rts entry: - %tmp = call void(...)*(...) @afoo() - store void(...)* %tmp, void(...)** @pfoo - %tmp1 = load void(...)*, void(...)** @pfoo + %tmp = call ptr(...) @afoo() + store ptr %tmp, ptr @pfoo + %tmp1 = load ptr, ptr @pfoo call void(...) %tmp1() ret void } @@ -93,7 +93,7 @@ entry: ret void } -@ptr6 = internal global i32* null +@ptr6 = internal global ptr null @dst6 = internal global i32 0 @src6 = internal global i32 0 @@ -105,9 +105,9 @@ define void @test5() nounwind { ; CHECK-NEXT: move.l (src6,%pc), (dst6,%pc) ; CHECK-NEXT: rts entry: - store i32* @dst6, i32** @ptr6 - %tmp.s = load i32, i32* @src6 - store i32 %tmp.s, i32* @dst6 + store ptr @dst6, ptr @ptr6 + %tmp.s = load i32, ptr @src6 + store i32 %tmp.s, ptr @dst6 ret void } diff --git a/llvm/test/CodeGen/M68k/CodeModel/small-pie-global-access.ll b/llvm/test/CodeGen/M68k/CodeModel/small-pie-global-access.ll index de6e1227e72a..668f8a96ac6f 100644 --- a/llvm/test/CodeGen/M68k/CodeModel/small-pie-global-access.ll +++ b/llvm/test/CodeGen/M68k/CodeModel/small-pie-global-access.ll @@ -14,7 +14,7 @@ define i32 @my_access_global_a() #0 { ; CHECK-NEXT: move.l (%a0), %d0 ; CHECK-NEXT: rts entry: - %0 = load i32, i32* @a, align 4 + %0 = load i32, ptr @a, align 4 ret i32 %0 } @@ -29,7 +29,7 @@ define i32 @my_access_global_b() #0 { ; CHECK-NEXT: move.l (%a0), %d0 ; CHECK-NEXT: rts entry: - %0 = load i32, i32* @b, align 4 + %0 = load i32, ptr @b, align 4 ret i32 %0 } @@ -43,7 +43,7 @@ define i32 @my_access_global_c() #0 { ; CHECK-NEXT: move.l (c,%pc), %d0 ; CHECK-NEXT: rts entry: - %0 = load i32, i32* @c, align 4 + %0 = load i32, ptr @c, align 4 ret i32 %0 } @@ -58,7 +58,7 @@ define i32 @my_access_global_load_d() #0 { ; CHECK-NEXT: move.l (%a0), %d0 ; CHECK-NEXT: rts entry: - %0 = load i32, i32* @d, align 4 + %0 = load i32, ptr @d, align 4 ret i32 %0 } @@ -72,12 +72,12 @@ define i32 @my_access_global_store_d() #0 { ; CHECK-NEXT: move.l #0, %d0 ; CHECK-NEXT: rts entry: - store i32 2, i32* @d, align 4 + store i32 2, ptr @d, align 4 ret i32 0 } ; External Linkage, function pointer access. -declare i32 @access_fp(i32 ()*) +declare i32 @access_fp(ptr) declare i32 @foo() define i32 @my_access_fp_foo() #0 { @@ -91,7 +91,7 @@ define i32 @my_access_fp_foo() #0 { ; CHECK-NEXT: adda.l #4, %sp ; CHECK-NEXT: rts entry: - %call = call i32 @access_fp(i32 ()* @foo) + %call = call i32 @access_fp(ptr @foo) ret i32 %call } @@ -120,7 +120,7 @@ define i32 @my_access_fp_bar() #0 { ; CHECK-NEXT: adda.l #4, %sp ; CHECK-NEXT: rts entry: - %call = call i32 @access_fp(i32 ()* @bar) + %call = call i32 @access_fp(ptr @bar) ret i32 %call } diff --git a/llvm/test/CodeGen/M68k/CodeModel/small-static.ll b/llvm/test/CodeGen/M68k/CodeModel/small-static.ll index 6ab9a7b61e44..d7fa5b0ea4e5 100644 --- a/llvm/test/CodeGen/M68k/CodeModel/small-static.ll +++ b/llvm/test/CodeGen/M68k/CodeModel/small-static.ll @@ -3,7 +3,7 @@ ; RUN: -code-model=small -relocation-model=static \ ; RUN: | FileCheck %s -@ptr = external global i32* +@ptr = external global ptr @dst = external global i32 @src = external global i32 @@ -15,13 +15,13 @@ define void @test0() nounwind { ; CHECK-NEXT: move.l (src,%pc), (dst,%pc) ; CHECK-NEXT: rts entry: - store i32* @dst, i32** @ptr - %tmp.s = load i32, i32* @src - store i32 %tmp.s, i32* @dst + store ptr @dst, ptr @ptr + %tmp.s = load i32, ptr @src + store i32 %tmp.s, ptr @dst ret void } -@ptr2 = global i32* null +@ptr2 = global ptr null @dst2 = global i32 0 @src2 = global i32 0 @@ -33,13 +33,13 @@ define void @test1() nounwind { ; CHECK-NEXT: move.l (src2,%pc), (dst2,%pc) ; CHECK-NEXT: rts entry: - store i32* @dst2, i32** @ptr2 - %tmp.s = load i32, i32* @src2 - store i32 %tmp.s, i32* @dst2 + store ptr @dst2, ptr @ptr2 + %tmp.s = load i32, ptr @src2 + store i32 %tmp.s, ptr @dst2 ret void } -declare i8* @malloc(i32) +declare ptr @malloc(i32) define void @test2() nounwind { ; CHECK-LABEL: test2: @@ -50,12 +50,12 @@ define void @test2() nounwind { ; CHECK-NEXT: adda.l #4, %sp ; CHECK-NEXT: rts entry: - %ptr = call i8* @malloc(i32 40) + %ptr = call ptr @malloc(i32 40) ret void } -@pfoo = external global void(...)* -declare void(...)* @afoo(...) +@pfoo = external global ptr +declare ptr @afoo(...) define void @test3() nounwind { ; CHECK-LABEL: test3: @@ -67,9 +67,9 @@ define void @test3() nounwind { ; CHECK-NEXT: adda.l #4, %sp ; CHECK-NEXT: rts entry: - %tmp = call void(...)*(...) @afoo() - store void(...)* %tmp, void(...)** @pfoo - %tmp1 = load void(...)*, void(...)** @pfoo + %tmp = call ptr(...) @afoo() + store ptr %tmp, ptr @pfoo + %tmp1 = load ptr, ptr @pfoo call void(...) %tmp1() ret void } @@ -88,7 +88,7 @@ entry: ret void } -@ptr6 = internal global i32* null +@ptr6 = internal global ptr null @dst6 = internal global i32 0 @src6 = internal global i32 0 @@ -100,9 +100,9 @@ define void @test5() nounwind { ; CHECK-NEXT: move.l (src6,%pc), (dst6,%pc) ; CHECK-NEXT: rts entry: - store i32* @dst6, i32** @ptr6 - %tmp.s = load i32, i32* @src6 - store i32 %tmp.s, i32* @dst6 + store ptr @dst6, ptr @ptr6 + %tmp.s = load i32, ptr @src6 + store i32 %tmp.s, ptr @dst6 ret void } diff --git a/llvm/test/CodeGen/M68k/Control/cmp.ll b/llvm/test/CodeGen/M68k/Control/cmp.ll index aa20461a8d65..634c08760a4e 100644 --- a/llvm/test/CodeGen/M68k/Control/cmp.ll +++ b/llvm/test/CodeGen/M68k/Control/cmp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=m68k -verify-machineinstrs | FileCheck %s -define i32 @test1(i32* %y) nounwind { +define i32 @test1(ptr %y) nounwind { ; CHECK-LABEL: test1: ; CHECK: ; %bb.0: ; CHECK-NEXT: move.l (4,%sp), %a0 @@ -13,7 +13,7 @@ define i32 @test1(i32* %y) nounwind { ; CHECK-NEXT: .LBB0_2: ; %cond_true ; CHECK-NEXT: move.l #1, %d0 ; CHECK-NEXT: rts - %tmp = load i32, i32* %y ; [#uses=1] + %tmp = load i32, ptr %y ; [#uses=1] %tmp.upgrd.1 = icmp eq i32 %tmp, 0 ; [#uses=1] br i1 %tmp.upgrd.1, label %cond_true, label %cond_false @@ -24,7 +24,7 @@ cond_true: ; preds = %0 ret i32 1 } -define i32 @test2(i32* %y) nounwind { +define i32 @test2(ptr %y) nounwind { ; CHECK-LABEL: test2: ; CHECK: ; %bb.0: ; CHECK-NEXT: move.l (4,%sp), %a0 @@ -38,7 +38,7 @@ define i32 @test2(i32* %y) nounwind { ; CHECK-NEXT: .LBB1_2: ; %cond_true ; CHECK-NEXT: move.l #1, %d0 ; CHECK-NEXT: rts - %tmp = load i32, i32* %y ; [#uses=1] + %tmp = load i32, ptr %y ; [#uses=1] %tmp1 = shl i32 %tmp, 3 ; [#uses=1] %tmp1.upgrd.2 = icmp eq i32 %tmp1, 0 ; [#uses=1] br i1 %tmp1.upgrd.2, label %cond_true, label %cond_false @@ -50,7 +50,7 @@ cond_true: ; preds = %0 ret i32 1 } -define i8 @test2b(i8* %y) nounwind { +define i8 @test2b(ptr %y) nounwind { ; CHECK-LABEL: test2b: ; CHECK: ; %bb.0: ; CHECK-NEXT: move.l (4,%sp), %a0 @@ -64,7 +64,7 @@ define i8 @test2b(i8* %y) nounwind { ; CHECK-NEXT: .LBB2_2: ; %cond_true ; CHECK-NEXT: move.b #1, %d0 ; CHECK-NEXT: rts - %tmp = load i8, i8* %y ; [#uses=1] + %tmp = load i8, ptr %y ; [#uses=1] %tmp1 = shl i8 %tmp, 3 ; [#uses=1] %tmp1.upgrd.2 = icmp eq i8 %tmp1, 0 ; [#uses=1] br i1 %tmp1.upgrd.2, label %cond_true, label %cond_false @@ -127,8 +127,8 @@ define i32 @test6() nounwind align 2 { ; CHECK-NEXT: adda.l #20, %sp ; CHECK-NEXT: rts %A = alloca {i64, i64}, align 8 - %B = getelementptr inbounds {i64, i64}, {i64, i64}* %A, i64 0, i32 1 - %C = load i64, i64* %B + %B = getelementptr inbounds {i64, i64}, ptr %A, i64 0, i32 1 + %C = load i64, ptr %B %D = icmp eq i64 %C, 0 br i1 %D, label %T, label %F T: @@ -282,7 +282,7 @@ define i8 @test18(i64 %L) { @d = global i8 0, align 1 -define void @test20(i32 %bf.load, i8 %x1, i8* %b_addr) { +define void @test20(i32 %bf.load, i8 %x1, ptr %b_addr) { ; CHECK-LABEL: test20: ; CHECK: .cfi_startproc ; CHECK-NEXT: ; %bb.0: @@ -312,9 +312,9 @@ define void @test20(i32 %bf.load, i8 %x1, i8* %b_addr) { %add = add nuw nsw i32 %conv, %conv6 %tobool7 = icmp ne i32 %add, 0 %frombool = zext i1 %tobool7 to i8 - store i8 %frombool, i8* %b_addr, align 1 + store i8 %frombool, ptr %b_addr, align 1 %tobool14 = icmp ne i32 %bf.shl, 0 %frombool15 = zext i1 %tobool14 to i8 - store i8 %frombool15, i8* @d, align 1 + store i8 %frombool15, ptr @d, align 1 ret void } diff --git a/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-call.ll b/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-call.ll index f4ff2582fbb1..b4ecbd5c6282 100644 --- a/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-call.ll +++ b/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-call.ll @@ -57,8 +57,8 @@ define i8 @test_ret_i8() nounwind { ret i8 %1 } -declare void @sret_callee(%struct.A* sret(%struct.A)) -define void @test_sret(%struct.A* sret(%struct.A) %0) nounwind { +declare void @sret_callee(ptr sret(%struct.A)) +define void @test_sret(ptr sret(%struct.A) %0) nounwind { ; CHECK-LABEL: name: test_sret ; CHECK: bb.1 (%ir-block.1): ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 @@ -71,7 +71,7 @@ define void @test_sret(%struct.A* sret(%struct.A) %0) nounwind { ; CHECK-NEXT: CALLb @sret_callee, csr_std, implicit $sp ; CHECK-NEXT: ADJCALLSTACKUP 4, 0, implicit-def $sp, implicit-def $ccr, implicit $sp ; CHECK-NEXT: RTS - call void @sret_callee(%struct.A* sret(%struct.A) %0) + call void @sret_callee(ptr sret(%struct.A) %0) ret void } @@ -105,7 +105,7 @@ define void @test_arg_i32_i16_i8() nounwind { } declare void @arg_struct_callee(%struct.A) -define void @test_arg_struct(%struct.A *%0) nounwind { +define void @test_arg_struct(ptr %0) nounwind { ; CHECK-LABEL: name: test_arg_struct ; CHECK: bb.1 (%ir-block.1): ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 @@ -135,13 +135,13 @@ define void @test_arg_struct(%struct.A *%0) nounwind { ; CHECK-NEXT: CALLb @arg_struct_callee, csr_std, implicit $sp ; CHECK-NEXT: ADJCALLSTACKUP 12, 0, implicit-def $sp, implicit-def $ccr, implicit $sp ; CHECK-NEXT: RTS - %2 = load %struct.A, %struct.A* %0 + %2 = load %struct.A, ptr %0 call void @arg_struct_callee(%struct.A %2) ret void } declare void @arg_array_callee([8 x i8]) -define void @test_arg_array([8 x i8] *%0) nounwind { +define void @test_arg_array(ptr %0) nounwind { ; CHECK-LABEL: name: test_arg_array ; CHECK: bb.1 (%ir-block.1): ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 @@ -212,13 +212,13 @@ define void @test_arg_array([8 x i8] *%0) nounwind { ; CHECK-NEXT: CALLb @arg_array_callee, csr_std, implicit $sp ; CHECK-NEXT: ADJCALLSTACKUP 32, 0, implicit-def $sp, implicit-def $ccr, implicit $sp ; CHECK-NEXT: RTS - %2 = load [8 x i8], [8 x i8]* %0 + %2 = load [8 x i8], ptr %0 call void @arg_array_callee([8 x i8] %2) ret void } -declare void @arg_pass_struct_by_ptr_callee(%struct.A*) -define void @test_arg_pass_struct_by_ptr(%struct.A *%0) nounwind { +declare void @arg_pass_struct_by_ptr_callee(ptr) +define void @test_arg_pass_struct_by_ptr(ptr %0) nounwind { ; CHECK-LABEL: name: test_arg_pass_struct_by_ptr ; CHECK: bb.1 (%ir-block.1): ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 @@ -231,12 +231,12 @@ define void @test_arg_pass_struct_by_ptr(%struct.A *%0) nounwind { ; CHECK-NEXT: CALLb @arg_pass_struct_by_ptr_callee, csr_std, implicit $sp ; CHECK-NEXT: ADJCALLSTACKUP 4, 0, implicit-def $sp, implicit-def $ccr, implicit $sp ; CHECK-NEXT: RTS - call void @arg_pass_struct_by_ptr_callee(%struct.A *%0) + call void @arg_pass_struct_by_ptr_callee(ptr %0) ret void } -declare void @arg_pass_integer_byval_callee(i32* byval(i32), i16* byval(i16), i8* byval(i8)) -define void @test_arg_pass_integer_byval(i32 *%0, i16 *%1, i8 *%2) nounwind { +declare void @arg_pass_integer_byval_callee(ptr byval(i32), ptr byval(i16), ptr byval(i8)) +define void @test_arg_pass_integer_byval(ptr %0, ptr %1, ptr %2) nounwind { ; CHECK-LABEL: name: test_arg_pass_integer_byval ; CHECK: bb.1 (%ir-block.3): ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 @@ -264,12 +264,12 @@ define void @test_arg_pass_integer_byval(i32 *%0, i16 *%1, i8 *%2) nounwind { ; CHECK-NEXT: CALLb @arg_pass_integer_byval_callee, csr_std, implicit $sp ; CHECK-NEXT: ADJCALLSTACKUP 12, 0, implicit-def $sp, implicit-def $ccr, implicit $sp ; CHECK-NEXT: RTS - call void @arg_pass_integer_byval_callee(i32* byval(i32) %0, i16* byval(i16) %1, i8* byval(i8) %2) + call void @arg_pass_integer_byval_callee(ptr byval(i32) %0, ptr byval(i16) %1, ptr byval(i8) %2) ret void } -declare void @arg_pass_struct_byval_callee(%struct.A* byval(%struct.A)) -define void @test_arg_pass_struct_byval(%struct.A *%0) nounwind { +declare void @arg_pass_struct_byval_callee(ptr byval(%struct.A)) +define void @test_arg_pass_struct_byval(ptr %0) nounwind { ; CHECK-LABEL: name: test_arg_pass_struct_byval ; CHECK: bb.1 (%ir-block.1): ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 @@ -283,12 +283,12 @@ define void @test_arg_pass_struct_byval(%struct.A *%0) nounwind { ; CHECK-NEXT: CALLb @arg_pass_struct_byval_callee, csr_std, implicit $sp ; CHECK-NEXT: ADJCALLSTACKUP 8, 0, implicit-def $sp, implicit-def $ccr, implicit $sp ; CHECK-NEXT: RTS - call void @arg_pass_struct_byval_callee(%struct.A* byval(%struct.A) %0) + call void @arg_pass_struct_byval_callee(ptr byval(%struct.A) %0) ret void } -declare void @arg_pass_array_byval_callee([32 x i8]* byval([32 x i8])) -define void @test_arg_pass_array_byval([32 x i8] *%0) nounwind { +declare void @arg_pass_array_byval_callee(ptr byval([32 x i8])) +define void @test_arg_pass_array_byval(ptr %0) nounwind { ; CHECK-LABEL: name: test_arg_pass_array_byval ; CHECK: bb.1 (%ir-block.1): ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 @@ -302,11 +302,11 @@ define void @test_arg_pass_array_byval([32 x i8] *%0) nounwind { ; CHECK-NEXT: CALLb @arg_pass_array_byval_callee, csr_std, implicit $sp ; CHECK-NEXT: ADJCALLSTACKUP 32, 0, implicit-def $sp, implicit-def $ccr, implicit $sp ; CHECK-NEXT: RTS - call void @arg_pass_array_byval_callee([32 x i8]* byval([32 x i8]) %0) + call void @arg_pass_array_byval_callee(ptr byval([32 x i8]) %0) ret void } -define void @test_indirect_call(void() *%fptr) nounwind { +define void @test_indirect_call(ptr %fptr) nounwind { ; CHECK-LABEL: name: test_indirect_call ; CHECK: bb.1 (%ir-block.0): ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 diff --git a/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll b/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll index 1dd258599135..0504792c3fce 100644 --- a/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll +++ b/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll @@ -140,7 +140,7 @@ define void @test_arg_lowering_multiple(i1 %a, i8 %b, i16 %c, i32 %d, i64 %e, i1 ret void } -define void @test_arg_lowering_ptr(i32* %x) { +define void @test_arg_lowering_ptr(ptr %x) { ; CHECK-LABEL: name: test_arg_lowering_ptr ; CHECK: bb.1 (%ir-block.0): ; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX @@ -149,7 +149,7 @@ define void @test_arg_lowering_ptr(i32* %x) { ret void } -define void @test_arg_lowering_float_ptr(float* %x) { +define void @test_arg_lowering_float_ptr(ptr %x) { ; CHECK-LABEL: name: test_arg_lowering_float_ptr ; CHECK: bb.1 (%ir-block.0): ; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX diff --git a/llvm/test/CodeGen/M68k/inline-asm.ll b/llvm/test/CodeGen/M68k/inline-asm.ll index 72cdfb78e82d..dda943920788 100644 --- a/llvm/test/CodeGen/M68k/inline-asm.ll +++ b/llvm/test/CodeGen/M68k/inline-asm.ll @@ -114,11 +114,11 @@ define void @register_constraints() { entry: %out = alloca i32, align 4 %0 = call i32 asm sideeffect "move.l #94, $0", "=r"() - store i32 %0, i32* %out, align 4 + store i32 %0, ptr %out, align 4 %1 = call i32 asm sideeffect "move.l #87, $0", "=d"() - store i32 %1, i32* %out, align 4 + store i32 %1, ptr %out, align 4 %2 = call i32 asm sideeffect "move.l #66, $0", "=a"() - store i32 %2, i32* %out, align 4 + store i32 %2, ptr %out, align 4 ret void } diff --git a/llvm/test/CodeGen/M68k/link-unlnk.ll b/llvm/test/CodeGen/M68k/link-unlnk.ll index 530f01b56998..dfdd80e66ade 100644 --- a/llvm/test/CodeGen/M68k/link-unlnk.ll +++ b/llvm/test/CodeGen/M68k/link-unlnk.ll @@ -59,8 +59,8 @@ entry: %arr = alloca [8 x i32], align 4 %s0 = getelementptr i32, ptr %arr, i32 0 %s1 = getelementptr i32, ptr %arr, i32 1 - store i32 %a, i32* %s0 - store i32 %b, i32* %s1 + store i32 %a, ptr %s0 + store i32 %b, ptr %s1 %ptr0 = getelementptr i32, ptr %arr, i32 0 %ptr1 = getelementptr i32, ptr %arr, i32 1 @@ -71,26 +71,26 @@ entry: %ptr6 = getelementptr i32, ptr %arr, i32 6 %ptr7 = getelementptr i32, ptr %arr, i32 7 - %res0 = load i32, i32 * %ptr0 - %res1 = load i32, i32 * %ptr1 + %res0 = load i32, ptr %ptr0 + %res1 = load i32, ptr %ptr1 %res2 = add i32 %res0, %res1 - store i32 %res2, i32 * %ptr2 + store i32 %res2, ptr %ptr2 %res3 = add i32 %res1, %res2 - store i32 %res3, i32 * %ptr3 + store i32 %res3, ptr %ptr3 %res4 = add i32 %res2, %res3 - store i32 %res4, i32 * %ptr4 + store i32 %res4, ptr %ptr4 %res5 = add i32 %res3, %res4 - store i32 %res5, i32 * %ptr5 + store i32 %res5, ptr %ptr5 %res6 = add i32 %res4, %res5 - store i32 %res6, i32 * %ptr6 + store i32 %res6, ptr %ptr6 %res7 = add i32 %res5, %res6 - store i32 %res7, i32 * %ptr7 + store i32 %res7, ptr %ptr7 ret i32 %res7 } @@ -122,8 +122,8 @@ define i32 @test_gep() { entry: %arr = alloca [8 x [8 x i32]] %ptr1 = getelementptr [8 x i32], ptr %arr, i64 0, i64 0 - store i32 12, i32 * %ptr1 + store i32 12, ptr %ptr1 %ptr2 = getelementptr [8 x i32], ptr %arr, i64 7, i64 7 - store i32 21, i32 * %ptr2 + store i32 21, ptr %ptr2 ret i32 0 } diff --git a/llvm/test/CodeGen/M68k/reserved-regs.ll b/llvm/test/CodeGen/M68k/reserved-regs.ll index 04acaf679792..553e6c8faaed 100644 --- a/llvm/test/CodeGen/M68k/reserved-regs.ll +++ b/llvm/test/CodeGen/M68k/reserved-regs.ll @@ -26,27 +26,27 @@ ; Which is copied from `test/CodeGen/RISCV/reserved-regs.ll`. ; But currently we have problem doing codegen for the above snippet ; (https://bugs.llvm.org/show_bug.cgi?id=50377). -define void @foo(i32* nocapture readonly %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32* nocapture readonly %d, - i32* nocapture readonly %a1, i32* nocapture readonly %b1, i32* nocapture readonly %c1, i32* nocapture readonly %d1, - i32* nocapture readonly %a2, i32* nocapture readonly %b2, i32* nocapture readonly %c2, i32* nocapture readonly %d2, - i32* nocapture readonly %a3, i32* nocapture readonly %b3, i32* nocapture readonly %c3, i32* nocapture readonly %d3) { +define void @foo(ptr nocapture readonly %a, ptr nocapture readonly %b, ptr nocapture readonly %c, ptr nocapture readonly %d, + ptr nocapture readonly %a1, ptr nocapture readonly %b1, ptr nocapture readonly %c1, ptr nocapture readonly %d1, + ptr nocapture readonly %a2, ptr nocapture readonly %b2, ptr nocapture readonly %c2, ptr nocapture readonly %d2, + ptr nocapture readonly %a3, ptr nocapture readonly %b3, ptr nocapture readonly %c3, ptr nocapture readonly %d3) { entry: - %0 = load i32, i32* %a, align 4 - %1 = load i32, i32* %b, align 4 - %2 = load i32, i32* %c, align 4 - %3 = load i32, i32* %d, align 4 - %4 = load i32, i32* %a1, align 4 - %5 = load i32, i32* %b1, align 4 - %6 = load i32, i32* %c1, align 4 - %7 = load i32, i32* %d1, align 4 - %8 = load i32, i32* %a2, align 4 - %9 = load i32, i32* %b2, align 4 - %10 = load i32, i32* %c2, align 4 - %11 = load i32, i32* %d2, align 4 - %12 = load i32, i32* %a3, align 4 - %13 = load i32, i32* %b3, align 4 - %14 = load i32, i32* %c3, align 4 - %15 = load i32, i32* %d3, align 4 + %0 = load i32, ptr %a, align 4 + %1 = load i32, ptr %b, align 4 + %2 = load i32, ptr %c, align 4 + %3 = load i32, ptr %d, align 4 + %4 = load i32, ptr %a1, align 4 + %5 = load i32, ptr %b1, align 4 + %6 = load i32, ptr %c1, align 4 + %7 = load i32, ptr %d1, align 4 + %8 = load i32, ptr %a2, align 4 + %9 = load i32, ptr %b2, align 4 + %10 = load i32, ptr %c2, align 4 + %11 = load i32, ptr %d2, align 4 + %12 = load i32, ptr %a3, align 4 + %13 = load i32, ptr %b3, align 4 + %14 = load i32, ptr %c3, align 4 + %15 = load i32, ptr %d3, align 4 ; A0-NOT: %a0 ; A1-NOT: %a1 ; A2-NOT: %a2 diff --git a/llvm/test/CodeGen/M68k/varargs.ll b/llvm/test/CodeGen/M68k/varargs.ll index c04bfdd40477..dae72edc6a34 100644 --- a/llvm/test/CodeGen/M68k/varargs.ll +++ b/llvm/test/CodeGen/M68k/varargs.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=m68k-linux -verify-machineinstrs | FileCheck %s -%struct.va_list = type { i8* } +%struct.va_list = type { ptr } define i32 @test(i32 %X, ...) { ; Initialize variable argument processing @@ -19,23 +19,23 @@ define i32 @test(i32 %X, ...) { ; CHECK-NEXT: adda.l #8, %sp ; CHECK-NEXT: rts %ap = alloca %struct.va_list - %ap2 = bitcast %struct.va_list* %ap to i8* - call void @llvm.va_start(i8* %ap2) + %ap2 = bitcast ptr %ap to ptr + call void @llvm.va_start(ptr %ap2) ; Read a single integer argument - %tmp = va_arg i8* %ap2, i32 + %tmp = va_arg ptr %ap2, i32 ; Demonstrate usage of llvm.va_copy and llvm.va_end - %aq = alloca i8* - %aq2 = bitcast i8** %aq to i8* - call void @llvm.va_copy(i8* %aq2, i8* %ap2) - call void @llvm.va_end(i8* %aq2) + %aq = alloca ptr + %aq2 = bitcast ptr %aq to ptr + call void @llvm.va_copy(ptr %aq2, ptr %ap2) + call void @llvm.va_end(ptr %aq2) ; Stop processing of arguments. - call void @llvm.va_end(i8* %ap2) + call void @llvm.va_end(ptr %ap2) ret i32 %tmp } -declare void @llvm.va_start(i8*) -declare void @llvm.va_copy(i8*, i8*) -declare void @llvm.va_end(i8*) +declare void @llvm.va_start(ptr) +declare void @llvm.va_copy(ptr, ptr) +declare void @llvm.va_end(ptr) -- GitLab From 423ac3d9ee82ff48da91b35ec80497089bc55b9e Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Tue, 6 Feb 2024 12:54:20 -0800 Subject: [PATCH 122/266] [CSKY] Convert tests to opaque pointers (NFC) --- llvm/test/CodeGen/CSKY/atomic-cmpxchg-flag.ll | 4 +- llvm/test/CodeGen/CSKY/atomic-cmpxchg.ll | 160 ++-- llvm/test/CodeGen/CSKY/atomic-load-store.ll | 128 +-- llvm/test/CodeGen/CSKY/atomic-rmw.ll | 880 +++++++++--------- llvm/test/CodeGen/CSKY/call-16bit.ll | 12 +- llvm/test/CodeGen/CSKY/call.ll | 12 +- llvm/test/CodeGen/CSKY/constantpool.ll | 4 +- llvm/test/CodeGen/CSKY/dwarf-eh.ll | 12 +- llvm/test/CodeGen/CSKY/fpu/ldst-d.ll | 24 +- llvm/test/CodeGen/CSKY/fpu/ldst-f.ll | 24 +- .../test/CodeGen/CSKY/frameaddr-returnaddr.ll | 40 +- llvm/test/CodeGen/CSKY/indirectbr.ll | 8 +- .../CodeGen/CSKY/inline-asm-d-constraint-f.ll | 4 +- .../CodeGen/CSKY/inline-asm-f-constraint-f.ll | 4 +- llvm/test/CodeGen/CSKY/inline-asm.ll | 26 +- llvm/test/CodeGen/CSKY/ldst-i.ll | 212 ++--- llvm/test/CodeGen/CSKY/tls-models.ll | 16 +- 17 files changed, 785 insertions(+), 785 deletions(-) diff --git a/llvm/test/CodeGen/CSKY/atomic-cmpxchg-flag.ll b/llvm/test/CodeGen/CSKY/atomic-cmpxchg-flag.ll index 8b2c28701adb..bd74e4608645 100644 --- a/llvm/test/CodeGen/CSKY/atomic-cmpxchg-flag.ll +++ b/llvm/test/CodeGen/CSKY/atomic-cmpxchg-flag.ll @@ -2,7 +2,7 @@ ; RUN: llc -mtriple=csky -verify-machineinstrs -csky-no-aliases -mattr=+2e3 < %s \ ; RUN: | FileCheck -check-prefix=CSKY %s -define i1 @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 signext %cmp, +define i1 @cmpxchg_i32_seq_cst_seq_cst(ptr %ptr, i32 signext %cmp, i32 signext %val) nounwind { ; CSKY-LABEL: cmpxchg_i32_seq_cst_seq_cst: ; CSKY: # %bb.0: # %entry @@ -26,7 +26,7 @@ define i1 @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 signext %cmp, ; CSKY-NEXT: .long __atomic_compare_exchange_4 ; entry: - %0 = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst seq_cst + %0 = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst seq_cst %1 = extractvalue { i32, i1 } %0, 1 ret i1 %1 } diff --git a/llvm/test/CodeGen/CSKY/atomic-cmpxchg.ll b/llvm/test/CodeGen/CSKY/atomic-cmpxchg.ll index fc0c08b27234..a257a0444d8b 100644 --- a/llvm/test/CodeGen/CSKY/atomic-cmpxchg.ll +++ b/llvm/test/CodeGen/CSKY/atomic-cmpxchg.ll @@ -2,7 +2,7 @@ ; RUN: llc -mtriple=csky -verify-machineinstrs -csky-no-aliases -mattr=+2e3 < %s \ ; RUN: | FileCheck -check-prefix=CSKY %s -define void @cmpxchg_i8_monotonic_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { +define void @cmpxchg_i8_monotonic_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-LABEL: cmpxchg_i8_monotonic_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -24,11 +24,11 @@ define void @cmpxchg_i8_monotonic_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind ; CSKY-NEXT: .LCPI0_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 ; - %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val monotonic monotonic + %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val monotonic monotonic ret void } -define void @cmpxchg_i8_acquire_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { +define void @cmpxchg_i8_acquire_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-LABEL: cmpxchg_i8_acquire_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -50,11 +50,11 @@ define void @cmpxchg_i8_acquire_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-NEXT: .LCPI1_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 ; - %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire monotonic + %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val acquire monotonic ret void } -define void @cmpxchg_i8_acquire_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { +define void @cmpxchg_i8_acquire_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-LABEL: cmpxchg_i8_acquire_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -76,11 +76,11 @@ define void @cmpxchg_i8_acquire_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-NEXT: .LCPI2_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 ; - %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire acquire + %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val acquire acquire ret void } -define void @cmpxchg_i8_release_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { +define void @cmpxchg_i8_release_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-LABEL: cmpxchg_i8_release_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -102,11 +102,11 @@ define void @cmpxchg_i8_release_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-NEXT: .LCPI3_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 ; - %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release monotonic + %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val release monotonic ret void } -define void @cmpxchg_i8_release_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { +define void @cmpxchg_i8_release_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-LABEL: cmpxchg_i8_release_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -128,11 +128,11 @@ define void @cmpxchg_i8_release_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-NEXT: .LCPI4_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 ; - %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release acquire + %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val release acquire ret void } -define void @cmpxchg_i8_acq_rel_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { +define void @cmpxchg_i8_acq_rel_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-LABEL: cmpxchg_i8_acq_rel_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -154,11 +154,11 @@ define void @cmpxchg_i8_acq_rel_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-NEXT: .LCPI5_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 ; - %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel monotonic + %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val acq_rel monotonic ret void } -define void @cmpxchg_i8_acq_rel_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { +define void @cmpxchg_i8_acq_rel_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-LABEL: cmpxchg_i8_acq_rel_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -180,11 +180,11 @@ define void @cmpxchg_i8_acq_rel_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-NEXT: .LCPI6_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 ; - %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel acquire + %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val acq_rel acquire ret void } -define void @cmpxchg_i8_seq_cst_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { +define void @cmpxchg_i8_seq_cst_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-LABEL: cmpxchg_i8_seq_cst_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -206,11 +206,11 @@ define void @cmpxchg_i8_seq_cst_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-NEXT: .LCPI7_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 ; - %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst monotonic + %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val seq_cst monotonic ret void } -define void @cmpxchg_i8_seq_cst_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { +define void @cmpxchg_i8_seq_cst_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-LABEL: cmpxchg_i8_seq_cst_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -232,11 +232,11 @@ define void @cmpxchg_i8_seq_cst_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-NEXT: .LCPI8_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 ; - %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst acquire + %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val seq_cst acquire ret void } -define void @cmpxchg_i8_seq_cst_seq_cst(i8* %ptr, i8 %cmp, i8 %val) nounwind { +define void @cmpxchg_i8_seq_cst_seq_cst(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-LABEL: cmpxchg_i8_seq_cst_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -258,11 +258,11 @@ define void @cmpxchg_i8_seq_cst_seq_cst(i8* %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-NEXT: .LCPI9_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 ; - %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst seq_cst + %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val seq_cst seq_cst ret void } -define void @cmpxchg_i16_monotonic_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind { +define void @cmpxchg_i16_monotonic_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwind { ; CSKY-LABEL: cmpxchg_i16_monotonic_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -284,11 +284,11 @@ define void @cmpxchg_i16_monotonic_monotonic(i16* %ptr, i16 %cmp, i16 %val) noun ; CSKY-NEXT: .LCPI10_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 ; - %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val monotonic monotonic + %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val monotonic monotonic ret void } -define void @cmpxchg_i16_acquire_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind { +define void @cmpxchg_i16_acquire_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwind { ; CSKY-LABEL: cmpxchg_i16_acquire_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -310,11 +310,11 @@ define void @cmpxchg_i16_acquire_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwi ; CSKY-NEXT: .LCPI11_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 ; - %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire monotonic + %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val acquire monotonic ret void } -define void @cmpxchg_i16_acquire_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind { +define void @cmpxchg_i16_acquire_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind { ; CSKY-LABEL: cmpxchg_i16_acquire_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -336,11 +336,11 @@ define void @cmpxchg_i16_acquire_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind ; CSKY-NEXT: .LCPI12_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 ; - %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire acquire + %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val acquire acquire ret void } -define void @cmpxchg_i16_release_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind { +define void @cmpxchg_i16_release_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwind { ; CSKY-LABEL: cmpxchg_i16_release_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -362,11 +362,11 @@ define void @cmpxchg_i16_release_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwi ; CSKY-NEXT: .LCPI13_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 ; - %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release monotonic + %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val release monotonic ret void } -define void @cmpxchg_i16_release_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind { +define void @cmpxchg_i16_release_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind { ; CSKY-LABEL: cmpxchg_i16_release_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -388,11 +388,11 @@ define void @cmpxchg_i16_release_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind ; CSKY-NEXT: .LCPI14_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 ; - %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release acquire + %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val release acquire ret void } -define void @cmpxchg_i16_acq_rel_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind { +define void @cmpxchg_i16_acq_rel_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwind { ; CSKY-LABEL: cmpxchg_i16_acq_rel_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -414,11 +414,11 @@ define void @cmpxchg_i16_acq_rel_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwi ; CSKY-NEXT: .LCPI15_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 ; - %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel monotonic + %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val acq_rel monotonic ret void } -define void @cmpxchg_i16_acq_rel_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind { +define void @cmpxchg_i16_acq_rel_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind { ; CSKY-LABEL: cmpxchg_i16_acq_rel_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -440,11 +440,11 @@ define void @cmpxchg_i16_acq_rel_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind ; CSKY-NEXT: .LCPI16_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 ; - %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel acquire + %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val acq_rel acquire ret void } -define void @cmpxchg_i16_seq_cst_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind { +define void @cmpxchg_i16_seq_cst_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwind { ; CSKY-LABEL: cmpxchg_i16_seq_cst_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -466,11 +466,11 @@ define void @cmpxchg_i16_seq_cst_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwi ; CSKY-NEXT: .LCPI17_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 ; - %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst monotonic + %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val seq_cst monotonic ret void } -define void @cmpxchg_i16_seq_cst_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind { +define void @cmpxchg_i16_seq_cst_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind { ; CSKY-LABEL: cmpxchg_i16_seq_cst_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -492,11 +492,11 @@ define void @cmpxchg_i16_seq_cst_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind ; CSKY-NEXT: .LCPI18_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 ; - %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst acquire + %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val seq_cst acquire ret void } -define void @cmpxchg_i16_seq_cst_seq_cst(i16* %ptr, i16 %cmp, i16 %val) nounwind { +define void @cmpxchg_i16_seq_cst_seq_cst(ptr %ptr, i16 %cmp, i16 %val) nounwind { ; CSKY-LABEL: cmpxchg_i16_seq_cst_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -518,11 +518,11 @@ define void @cmpxchg_i16_seq_cst_seq_cst(i16* %ptr, i16 %cmp, i16 %val) nounwind ; CSKY-NEXT: .LCPI19_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 ; - %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst seq_cst + %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val seq_cst seq_cst ret void } -define void @cmpxchg_i32_monotonic_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind { +define void @cmpxchg_i32_monotonic_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwind { ; CSKY-LABEL: cmpxchg_i32_monotonic_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -544,11 +544,11 @@ define void @cmpxchg_i32_monotonic_monotonic(i32* %ptr, i32 %cmp, i32 %val) noun ; CSKY-NEXT: .LCPI20_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 ; - %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val monotonic monotonic + %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val monotonic monotonic ret void } -define void @cmpxchg_i32_acquire_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind { +define void @cmpxchg_i32_acquire_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwind { ; CSKY-LABEL: cmpxchg_i32_acquire_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -570,11 +570,11 @@ define void @cmpxchg_i32_acquire_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwi ; CSKY-NEXT: .LCPI21_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 ; - %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acquire monotonic + %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val acquire monotonic ret void } -define void @cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind { +define void @cmpxchg_i32_acquire_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind { ; CSKY-LABEL: cmpxchg_i32_acquire_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -596,11 +596,11 @@ define void @cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind ; CSKY-NEXT: .LCPI22_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 ; - %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acquire acquire + %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val acquire acquire ret void } -define void @cmpxchg_i32_release_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind { +define void @cmpxchg_i32_release_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwind { ; CSKY-LABEL: cmpxchg_i32_release_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -622,11 +622,11 @@ define void @cmpxchg_i32_release_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwi ; CSKY-NEXT: .LCPI23_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 ; - %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release monotonic + %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val release monotonic ret void } -define void @cmpxchg_i32_release_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind { +define void @cmpxchg_i32_release_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind { ; CSKY-LABEL: cmpxchg_i32_release_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -648,11 +648,11 @@ define void @cmpxchg_i32_release_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind ; CSKY-NEXT: .LCPI24_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 ; - %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release acquire + %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val release acquire ret void } -define void @cmpxchg_i32_acq_rel_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind { +define void @cmpxchg_i32_acq_rel_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwind { ; CSKY-LABEL: cmpxchg_i32_acq_rel_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -674,11 +674,11 @@ define void @cmpxchg_i32_acq_rel_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwi ; CSKY-NEXT: .LCPI25_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 ; - %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acq_rel monotonic + %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val acq_rel monotonic ret void } -define void @cmpxchg_i32_acq_rel_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind { +define void @cmpxchg_i32_acq_rel_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind { ; CSKY-LABEL: cmpxchg_i32_acq_rel_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -700,11 +700,11 @@ define void @cmpxchg_i32_acq_rel_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind ; CSKY-NEXT: .LCPI26_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 ; - %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acq_rel acquire + %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val acq_rel acquire ret void } -define void @cmpxchg_i32_seq_cst_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind { +define void @cmpxchg_i32_seq_cst_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwind { ; CSKY-LABEL: cmpxchg_i32_seq_cst_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -726,11 +726,11 @@ define void @cmpxchg_i32_seq_cst_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwi ; CSKY-NEXT: .LCPI27_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 ; - %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst monotonic + %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst monotonic ret void } -define void @cmpxchg_i32_seq_cst_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind { +define void @cmpxchg_i32_seq_cst_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind { ; CSKY-LABEL: cmpxchg_i32_seq_cst_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -752,11 +752,11 @@ define void @cmpxchg_i32_seq_cst_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind ; CSKY-NEXT: .LCPI28_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 ; - %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst acquire + %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst acquire ret void } -define void @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 %cmp, i32 %val) nounwind { +define void @cmpxchg_i32_seq_cst_seq_cst(ptr %ptr, i32 %cmp, i32 %val) nounwind { ; CSKY-LABEL: cmpxchg_i32_seq_cst_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -778,11 +778,11 @@ define void @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 %cmp, i32 %val) nounwind ; CSKY-NEXT: .LCPI29_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 ; - %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst seq_cst + %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst seq_cst ret void } -define void @cmpxchg_i64_monotonic_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind { +define void @cmpxchg_i64_monotonic_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwind { ; CSKY-LABEL: cmpxchg_i64_monotonic_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -808,11 +808,11 @@ define void @cmpxchg_i64_monotonic_monotonic(i64* %ptr, i64 %cmp, i64 %val) noun ; CSKY-NEXT: .LCPI30_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 ; - %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val monotonic monotonic + %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val monotonic monotonic ret void } -define void @cmpxchg_i64_acquire_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind { +define void @cmpxchg_i64_acquire_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwind { ; CSKY-LABEL: cmpxchg_i64_acquire_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -839,11 +839,11 @@ define void @cmpxchg_i64_acquire_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwi ; CSKY-NEXT: .LCPI31_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 ; - %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acquire monotonic + %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val acquire monotonic ret void } -define void @cmpxchg_i64_acquire_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind { +define void @cmpxchg_i64_acquire_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind { ; CSKY-LABEL: cmpxchg_i64_acquire_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -869,11 +869,11 @@ define void @cmpxchg_i64_acquire_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind ; CSKY-NEXT: .LCPI32_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 ; - %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acquire acquire + %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val acquire acquire ret void } -define void @cmpxchg_i64_release_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind { +define void @cmpxchg_i64_release_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwind { ; CSKY-LABEL: cmpxchg_i64_release_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -900,11 +900,11 @@ define void @cmpxchg_i64_release_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwi ; CSKY-NEXT: .LCPI33_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 ; - %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release monotonic + %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val release monotonic ret void } -define void @cmpxchg_i64_release_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind { +define void @cmpxchg_i64_release_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind { ; CSKY-LABEL: cmpxchg_i64_release_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -931,11 +931,11 @@ define void @cmpxchg_i64_release_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind ; CSKY-NEXT: .LCPI34_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 ; - %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release acquire + %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val release acquire ret void } -define void @cmpxchg_i64_acq_rel_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind { +define void @cmpxchg_i64_acq_rel_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwind { ; CSKY-LABEL: cmpxchg_i64_acq_rel_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -962,11 +962,11 @@ define void @cmpxchg_i64_acq_rel_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwi ; CSKY-NEXT: .LCPI35_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 ; - %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acq_rel monotonic + %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val acq_rel monotonic ret void } -define void @cmpxchg_i64_acq_rel_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind { +define void @cmpxchg_i64_acq_rel_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind { ; CSKY-LABEL: cmpxchg_i64_acq_rel_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -993,11 +993,11 @@ define void @cmpxchg_i64_acq_rel_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind ; CSKY-NEXT: .LCPI36_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 ; - %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acq_rel acquire + %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val acq_rel acquire ret void } -define void @cmpxchg_i64_seq_cst_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind { +define void @cmpxchg_i64_seq_cst_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwind { ; CSKY-LABEL: cmpxchg_i64_seq_cst_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1024,11 +1024,11 @@ define void @cmpxchg_i64_seq_cst_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwi ; CSKY-NEXT: .LCPI37_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 ; - %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst monotonic + %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val seq_cst monotonic ret void } -define void @cmpxchg_i64_seq_cst_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind { +define void @cmpxchg_i64_seq_cst_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind { ; CSKY-LABEL: cmpxchg_i64_seq_cst_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1055,11 +1055,11 @@ define void @cmpxchg_i64_seq_cst_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind ; CSKY-NEXT: .LCPI38_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 ; - %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst acquire + %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val seq_cst acquire ret void } -define void @cmpxchg_i64_seq_cst_seq_cst(i64* %ptr, i64 %cmp, i64 %val) nounwind { +define void @cmpxchg_i64_seq_cst_seq_cst(ptr %ptr, i64 %cmp, i64 %val) nounwind { ; CSKY-LABEL: cmpxchg_i64_seq_cst_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1085,6 +1085,6 @@ define void @cmpxchg_i64_seq_cst_seq_cst(i64* %ptr, i64 %cmp, i64 %val) nounwind ; CSKY-NEXT: .LCPI39_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 ; - %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst seq_cst + %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val seq_cst seq_cst ret void } diff --git a/llvm/test/CodeGen/CSKY/atomic-load-store.ll b/llvm/test/CodeGen/CSKY/atomic-load-store.ll index 064f05b32693..553e8ffb1ff2 100644 --- a/llvm/test/CodeGen/CSKY/atomic-load-store.ll +++ b/llvm/test/CodeGen/CSKY/atomic-load-store.ll @@ -2,7 +2,7 @@ ; RUN: llc -mtriple=csky -verify-machineinstrs -csky-no-aliases -mattr=+2e3 < %s \ ; RUN: | FileCheck -check-prefix=CSKY %s -define i8 @atomic_load_i8_unordered(i8 *%a) nounwind { +define i8 @atomic_load_i8_unordered(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i8_unordered: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -18,11 +18,11 @@ define i8 @atomic_load_i8_unordered(i8 *%a) nounwind { ; CSKY-NEXT: .LCPI0_0: ; CSKY-NEXT: .long __atomic_load_1 ; - %1 = load atomic i8, i8* %a unordered, align 1 + %1 = load atomic i8, ptr %a unordered, align 1 ret i8 %1 } -define i8 @atomic_load_i8_monotonic(i8 *%a) nounwind { +define i8 @atomic_load_i8_monotonic(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i8_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -38,11 +38,11 @@ define i8 @atomic_load_i8_monotonic(i8 *%a) nounwind { ; CSKY-NEXT: .LCPI1_0: ; CSKY-NEXT: .long __atomic_load_1 ; - %1 = load atomic i8, i8* %a monotonic, align 1 + %1 = load atomic i8, ptr %a monotonic, align 1 ret i8 %1 } -define i8 @atomic_load_i8_acquire(i8 *%a) nounwind { +define i8 @atomic_load_i8_acquire(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i8_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -58,11 +58,11 @@ define i8 @atomic_load_i8_acquire(i8 *%a) nounwind { ; CSKY-NEXT: .LCPI2_0: ; CSKY-NEXT: .long __atomic_load_1 ; - %1 = load atomic i8, i8* %a acquire, align 1 + %1 = load atomic i8, ptr %a acquire, align 1 ret i8 %1 } -define i8 @atomic_load_i8_seq_cst(i8 *%a) nounwind { +define i8 @atomic_load_i8_seq_cst(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i8_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -78,11 +78,11 @@ define i8 @atomic_load_i8_seq_cst(i8 *%a) nounwind { ; CSKY-NEXT: .LCPI3_0: ; CSKY-NEXT: .long __atomic_load_1 ; - %1 = load atomic i8, i8* %a seq_cst, align 1 + %1 = load atomic i8, ptr %a seq_cst, align 1 ret i8 %1 } -define i16 @atomic_load_i16_unordered(i16 *%a) nounwind { +define i16 @atomic_load_i16_unordered(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i16_unordered: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -98,11 +98,11 @@ define i16 @atomic_load_i16_unordered(i16 *%a) nounwind { ; CSKY-NEXT: .LCPI4_0: ; CSKY-NEXT: .long __atomic_load_2 ; - %1 = load atomic i16, i16* %a unordered, align 2 + %1 = load atomic i16, ptr %a unordered, align 2 ret i16 %1 } -define i16 @atomic_load_i16_monotonic(i16 *%a) nounwind { +define i16 @atomic_load_i16_monotonic(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i16_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -118,11 +118,11 @@ define i16 @atomic_load_i16_monotonic(i16 *%a) nounwind { ; CSKY-NEXT: .LCPI5_0: ; CSKY-NEXT: .long __atomic_load_2 ; - %1 = load atomic i16, i16* %a monotonic, align 2 + %1 = load atomic i16, ptr %a monotonic, align 2 ret i16 %1 } -define i16 @atomic_load_i16_acquire(i16 *%a) nounwind { +define i16 @atomic_load_i16_acquire(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i16_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -138,11 +138,11 @@ define i16 @atomic_load_i16_acquire(i16 *%a) nounwind { ; CSKY-NEXT: .LCPI6_0: ; CSKY-NEXT: .long __atomic_load_2 ; - %1 = load atomic i16, i16* %a acquire, align 2 + %1 = load atomic i16, ptr %a acquire, align 2 ret i16 %1 } -define i16 @atomic_load_i16_seq_cst(i16 *%a) nounwind { +define i16 @atomic_load_i16_seq_cst(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i16_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -158,11 +158,11 @@ define i16 @atomic_load_i16_seq_cst(i16 *%a) nounwind { ; CSKY-NEXT: .LCPI7_0: ; CSKY-NEXT: .long __atomic_load_2 ; - %1 = load atomic i16, i16* %a seq_cst, align 2 + %1 = load atomic i16, ptr %a seq_cst, align 2 ret i16 %1 } -define i32 @atomic_load_i32_unordered(i32 *%a) nounwind { +define i32 @atomic_load_i32_unordered(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i32_unordered: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -178,11 +178,11 @@ define i32 @atomic_load_i32_unordered(i32 *%a) nounwind { ; CSKY-NEXT: .LCPI8_0: ; CSKY-NEXT: .long __atomic_load_4 ; - %1 = load atomic i32, i32* %a unordered, align 4 + %1 = load atomic i32, ptr %a unordered, align 4 ret i32 %1 } -define i32 @atomic_load_i32_monotonic(i32 *%a) nounwind { +define i32 @atomic_load_i32_monotonic(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i32_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -198,11 +198,11 @@ define i32 @atomic_load_i32_monotonic(i32 *%a) nounwind { ; CSKY-NEXT: .LCPI9_0: ; CSKY-NEXT: .long __atomic_load_4 ; - %1 = load atomic i32, i32* %a monotonic, align 4 + %1 = load atomic i32, ptr %a monotonic, align 4 ret i32 %1 } -define i32 @atomic_load_i32_acquire(i32 *%a) nounwind { +define i32 @atomic_load_i32_acquire(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i32_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -218,11 +218,11 @@ define i32 @atomic_load_i32_acquire(i32 *%a) nounwind { ; CSKY-NEXT: .LCPI10_0: ; CSKY-NEXT: .long __atomic_load_4 ; - %1 = load atomic i32, i32* %a acquire, align 4 + %1 = load atomic i32, ptr %a acquire, align 4 ret i32 %1 } -define i32 @atomic_load_i32_seq_cst(i32 *%a) nounwind { +define i32 @atomic_load_i32_seq_cst(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i32_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -238,11 +238,11 @@ define i32 @atomic_load_i32_seq_cst(i32 *%a) nounwind { ; CSKY-NEXT: .LCPI11_0: ; CSKY-NEXT: .long __atomic_load_4 ; - %1 = load atomic i32, i32* %a seq_cst, align 4 + %1 = load atomic i32, ptr %a seq_cst, align 4 ret i32 %1 } -define i64 @atomic_load_i64_unordered(i64 *%a) nounwind { +define i64 @atomic_load_i64_unordered(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i64_unordered: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -258,11 +258,11 @@ define i64 @atomic_load_i64_unordered(i64 *%a) nounwind { ; CSKY-NEXT: .LCPI12_0: ; CSKY-NEXT: .long __atomic_load_8 ; - %1 = load atomic i64, i64* %a unordered, align 8 + %1 = load atomic i64, ptr %a unordered, align 8 ret i64 %1 } -define i64 @atomic_load_i64_monotonic(i64 *%a) nounwind { +define i64 @atomic_load_i64_monotonic(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i64_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -278,11 +278,11 @@ define i64 @atomic_load_i64_monotonic(i64 *%a) nounwind { ; CSKY-NEXT: .LCPI13_0: ; CSKY-NEXT: .long __atomic_load_8 ; - %1 = load atomic i64, i64* %a monotonic, align 8 + %1 = load atomic i64, ptr %a monotonic, align 8 ret i64 %1 } -define i64 @atomic_load_i64_acquire(i64 *%a) nounwind { +define i64 @atomic_load_i64_acquire(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i64_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -298,11 +298,11 @@ define i64 @atomic_load_i64_acquire(i64 *%a) nounwind { ; CSKY-NEXT: .LCPI14_0: ; CSKY-NEXT: .long __atomic_load_8 ; - %1 = load atomic i64, i64* %a acquire, align 8 + %1 = load atomic i64, ptr %a acquire, align 8 ret i64 %1 } -define i64 @atomic_load_i64_seq_cst(i64 *%a) nounwind { +define i64 @atomic_load_i64_seq_cst(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i64_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -318,11 +318,11 @@ define i64 @atomic_load_i64_seq_cst(i64 *%a) nounwind { ; CSKY-NEXT: .LCPI15_0: ; CSKY-NEXT: .long __atomic_load_8 ; - %1 = load atomic i64, i64* %a seq_cst, align 8 + %1 = load atomic i64, ptr %a seq_cst, align 8 ret i64 %1 } -define void @atomic_store_i8_unordered(i8 *%a, i8 %b) nounwind { +define void @atomic_store_i8_unordered(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomic_store_i8_unordered: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -338,11 +338,11 @@ define void @atomic_store_i8_unordered(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .LCPI16_0: ; CSKY-NEXT: .long __atomic_store_1 ; - store atomic i8 %b, i8* %a unordered, align 1 + store atomic i8 %b, ptr %a unordered, align 1 ret void } -define void @atomic_store_i8_monotonic(i8 *%a, i8 %b) nounwind { +define void @atomic_store_i8_monotonic(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomic_store_i8_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -358,11 +358,11 @@ define void @atomic_store_i8_monotonic(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .LCPI17_0: ; CSKY-NEXT: .long __atomic_store_1 ; - store atomic i8 %b, i8* %a monotonic, align 1 + store atomic i8 %b, ptr %a monotonic, align 1 ret void } -define void @atomic_store_i8_release(i8 *%a, i8 %b) nounwind { +define void @atomic_store_i8_release(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomic_store_i8_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -378,11 +378,11 @@ define void @atomic_store_i8_release(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .LCPI18_0: ; CSKY-NEXT: .long __atomic_store_1 ; - store atomic i8 %b, i8* %a release, align 1 + store atomic i8 %b, ptr %a release, align 1 ret void } -define void @atomic_store_i8_seq_cst(i8 *%a, i8 %b) nounwind { +define void @atomic_store_i8_seq_cst(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomic_store_i8_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -398,11 +398,11 @@ define void @atomic_store_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .LCPI19_0: ; CSKY-NEXT: .long __atomic_store_1 ; - store atomic i8 %b, i8* %a seq_cst, align 1 + store atomic i8 %b, ptr %a seq_cst, align 1 ret void } -define void @atomic_store_i16_unordered(i16 *%a, i16 %b) nounwind { +define void @atomic_store_i16_unordered(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomic_store_i16_unordered: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -418,11 +418,11 @@ define void @atomic_store_i16_unordered(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .LCPI20_0: ; CSKY-NEXT: .long __atomic_store_2 ; - store atomic i16 %b, i16* %a unordered, align 2 + store atomic i16 %b, ptr %a unordered, align 2 ret void } -define void @atomic_store_i16_monotonic(i16 *%a, i16 %b) nounwind { +define void @atomic_store_i16_monotonic(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomic_store_i16_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -438,11 +438,11 @@ define void @atomic_store_i16_monotonic(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .LCPI21_0: ; CSKY-NEXT: .long __atomic_store_2 ; - store atomic i16 %b, i16* %a monotonic, align 2 + store atomic i16 %b, ptr %a monotonic, align 2 ret void } -define void @atomic_store_i16_release(i16 *%a, i16 %b) nounwind { +define void @atomic_store_i16_release(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomic_store_i16_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -458,11 +458,11 @@ define void @atomic_store_i16_release(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .LCPI22_0: ; CSKY-NEXT: .long __atomic_store_2 ; - store atomic i16 %b, i16* %a release, align 2 + store atomic i16 %b, ptr %a release, align 2 ret void } -define void @atomic_store_i16_seq_cst(i16 *%a, i16 %b) nounwind { +define void @atomic_store_i16_seq_cst(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomic_store_i16_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -478,11 +478,11 @@ define void @atomic_store_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .LCPI23_0: ; CSKY-NEXT: .long __atomic_store_2 ; - store atomic i16 %b, i16* %a seq_cst, align 2 + store atomic i16 %b, ptr %a seq_cst, align 2 ret void } -define void @atomic_store_i32_unordered(i32 *%a, i32 %b) nounwind { +define void @atomic_store_i32_unordered(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomic_store_i32_unordered: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -498,11 +498,11 @@ define void @atomic_store_i32_unordered(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .LCPI24_0: ; CSKY-NEXT: .long __atomic_store_4 ; - store atomic i32 %b, i32* %a unordered, align 4 + store atomic i32 %b, ptr %a unordered, align 4 ret void } -define void @atomic_store_i32_monotonic(i32 *%a, i32 %b) nounwind { +define void @atomic_store_i32_monotonic(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomic_store_i32_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -518,11 +518,11 @@ define void @atomic_store_i32_monotonic(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .LCPI25_0: ; CSKY-NEXT: .long __atomic_store_4 ; - store atomic i32 %b, i32* %a monotonic, align 4 + store atomic i32 %b, ptr %a monotonic, align 4 ret void } -define void @atomic_store_i32_release(i32 *%a, i32 %b) nounwind { +define void @atomic_store_i32_release(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomic_store_i32_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -538,11 +538,11 @@ define void @atomic_store_i32_release(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .LCPI26_0: ; CSKY-NEXT: .long __atomic_store_4 ; - store atomic i32 %b, i32* %a release, align 4 + store atomic i32 %b, ptr %a release, align 4 ret void } -define void @atomic_store_i32_seq_cst(i32 *%a, i32 %b) nounwind { +define void @atomic_store_i32_seq_cst(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomic_store_i32_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -558,11 +558,11 @@ define void @atomic_store_i32_seq_cst(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .LCPI27_0: ; CSKY-NEXT: .long __atomic_store_4 ; - store atomic i32 %b, i32* %a seq_cst, align 4 + store atomic i32 %b, ptr %a seq_cst, align 4 ret void } -define void @atomic_store_i64_unordered(i64 *%a, i64 %b) nounwind { +define void @atomic_store_i64_unordered(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomic_store_i64_unordered: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -578,11 +578,11 @@ define void @atomic_store_i64_unordered(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .LCPI28_0: ; CSKY-NEXT: .long __atomic_store_8 ; - store atomic i64 %b, i64* %a unordered, align 8 + store atomic i64 %b, ptr %a unordered, align 8 ret void } -define void @atomic_store_i64_monotonic(i64 *%a, i64 %b) nounwind { +define void @atomic_store_i64_monotonic(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomic_store_i64_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -598,11 +598,11 @@ define void @atomic_store_i64_monotonic(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .LCPI29_0: ; CSKY-NEXT: .long __atomic_store_8 ; - store atomic i64 %b, i64* %a monotonic, align 8 + store atomic i64 %b, ptr %a monotonic, align 8 ret void } -define void @atomic_store_i64_release(i64 *%a, i64 %b) nounwind { +define void @atomic_store_i64_release(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomic_store_i64_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -618,11 +618,11 @@ define void @atomic_store_i64_release(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .LCPI30_0: ; CSKY-NEXT: .long __atomic_store_8 ; - store atomic i64 %b, i64* %a release, align 8 + store atomic i64 %b, ptr %a release, align 8 ret void } -define void @atomic_store_i64_seq_cst(i64 *%a, i64 %b) nounwind { +define void @atomic_store_i64_seq_cst(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomic_store_i64_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -638,6 +638,6 @@ define void @atomic_store_i64_seq_cst(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .LCPI31_0: ; CSKY-NEXT: .long __atomic_store_8 ; - store atomic i64 %b, i64* %a seq_cst, align 8 + store atomic i64 %b, ptr %a seq_cst, align 8 ret void } diff --git a/llvm/test/CodeGen/CSKY/atomic-rmw.ll b/llvm/test/CodeGen/CSKY/atomic-rmw.ll index c9fd90bb8c34..ee1c8194cd35 100644 --- a/llvm/test/CodeGen/CSKY/atomic-rmw.ll +++ b/llvm/test/CodeGen/CSKY/atomic-rmw.ll @@ -2,7 +2,7 @@ ; RUN: llc -mtriple=csky -verify-machineinstrs -csky-no-aliases -mattr=+2e3 < %s \ ; RUN: | FileCheck -check-prefix=CSKY %s -define i8 @atomicrmw_xchg_i8_monotonic(i8* %a, i8 %b) nounwind { +define i8 @atomicrmw_xchg_i8_monotonic(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i8_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -17,11 +17,11 @@ define i8 @atomicrmw_xchg_i8_monotonic(i8* %a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI0_0: ; CSKY-NEXT: .long __atomic_exchange_1 - %1 = atomicrmw xchg i8* %a, i8 %b monotonic + %1 = atomicrmw xchg ptr %a, i8 %b monotonic ret i8 %1 } -define i8 @atomicrmw_xchg_i8_acquire(i8* %a, i8 %b) nounwind { +define i8 @atomicrmw_xchg_i8_acquire(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i8_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -36,11 +36,11 @@ define i8 @atomicrmw_xchg_i8_acquire(i8* %a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI1_0: ; CSKY-NEXT: .long __atomic_exchange_1 - %1 = atomicrmw xchg i8* %a, i8 %b acquire + %1 = atomicrmw xchg ptr %a, i8 %b acquire ret i8 %1 } -define i8 @atomicrmw_xchg_i8_release(i8* %a, i8 %b) nounwind { +define i8 @atomicrmw_xchg_i8_release(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i8_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -55,11 +55,11 @@ define i8 @atomicrmw_xchg_i8_release(i8* %a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI2_0: ; CSKY-NEXT: .long __atomic_exchange_1 - %1 = atomicrmw xchg i8* %a, i8 %b release + %1 = atomicrmw xchg ptr %a, i8 %b release ret i8 %1 } -define i8 @atomicrmw_xchg_i8_acq_rel(i8* %a, i8 %b) nounwind { +define i8 @atomicrmw_xchg_i8_acq_rel(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i8_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -74,11 +74,11 @@ define i8 @atomicrmw_xchg_i8_acq_rel(i8* %a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI3_0: ; CSKY-NEXT: .long __atomic_exchange_1 - %1 = atomicrmw xchg i8* %a, i8 %b acq_rel + %1 = atomicrmw xchg ptr %a, i8 %b acq_rel ret i8 %1 } -define i8 @atomicrmw_xchg_i8_seq_cst(i8* %a, i8 %b) nounwind { +define i8 @atomicrmw_xchg_i8_seq_cst(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i8_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -93,11 +93,11 @@ define i8 @atomicrmw_xchg_i8_seq_cst(i8* %a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI4_0: ; CSKY-NEXT: .long __atomic_exchange_1 - %1 = atomicrmw xchg i8* %a, i8 %b seq_cst + %1 = atomicrmw xchg ptr %a, i8 %b seq_cst ret i8 %1 } -define i8 @atomicrmw_add_i8_monotonic(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_add_i8_monotonic(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i8_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -112,11 +112,11 @@ define i8 @atomicrmw_add_i8_monotonic(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI5_0: ; CSKY-NEXT: .long __atomic_fetch_add_1 - %1 = atomicrmw add i8* %a, i8 %b monotonic + %1 = atomicrmw add ptr %a, i8 %b monotonic ret i8 %1 } -define i8 @atomicrmw_add_i8_acquire(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_add_i8_acquire(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i8_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -131,11 +131,11 @@ define i8 @atomicrmw_add_i8_acquire(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI6_0: ; CSKY-NEXT: .long __atomic_fetch_add_1 - %1 = atomicrmw add i8* %a, i8 %b acquire + %1 = atomicrmw add ptr %a, i8 %b acquire ret i8 %1 } -define i8 @atomicrmw_add_i8_release(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_add_i8_release(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i8_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -150,11 +150,11 @@ define i8 @atomicrmw_add_i8_release(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI7_0: ; CSKY-NEXT: .long __atomic_fetch_add_1 - %1 = atomicrmw add i8* %a, i8 %b release + %1 = atomicrmw add ptr %a, i8 %b release ret i8 %1 } -define i8 @atomicrmw_add_i8_acq_rel(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_add_i8_acq_rel(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i8_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -169,11 +169,11 @@ define i8 @atomicrmw_add_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI8_0: ; CSKY-NEXT: .long __atomic_fetch_add_1 - %1 = atomicrmw add i8* %a, i8 %b acq_rel + %1 = atomicrmw add ptr %a, i8 %b acq_rel ret i8 %1 } -define i8 @atomicrmw_add_i8_seq_cst(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_add_i8_seq_cst(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i8_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -188,11 +188,11 @@ define i8 @atomicrmw_add_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI9_0: ; CSKY-NEXT: .long __atomic_fetch_add_1 - %1 = atomicrmw add i8* %a, i8 %b seq_cst + %1 = atomicrmw add ptr %a, i8 %b seq_cst ret i8 %1 } -define i8 @atomicrmw_sub_i8_monotonic(i8* %a, i8 %b) nounwind { +define i8 @atomicrmw_sub_i8_monotonic(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i8_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -207,11 +207,11 @@ define i8 @atomicrmw_sub_i8_monotonic(i8* %a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI10_0: ; CSKY-NEXT: .long __atomic_fetch_sub_1 - %1 = atomicrmw sub i8* %a, i8 %b monotonic + %1 = atomicrmw sub ptr %a, i8 %b monotonic ret i8 %1 } -define i8 @atomicrmw_sub_i8_acquire(i8* %a, i8 %b) nounwind { +define i8 @atomicrmw_sub_i8_acquire(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i8_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -226,11 +226,11 @@ define i8 @atomicrmw_sub_i8_acquire(i8* %a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI11_0: ; CSKY-NEXT: .long __atomic_fetch_sub_1 - %1 = atomicrmw sub i8* %a, i8 %b acquire + %1 = atomicrmw sub ptr %a, i8 %b acquire ret i8 %1 } -define i8 @atomicrmw_sub_i8_release(i8* %a, i8 %b) nounwind { +define i8 @atomicrmw_sub_i8_release(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i8_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -245,11 +245,11 @@ define i8 @atomicrmw_sub_i8_release(i8* %a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI12_0: ; CSKY-NEXT: .long __atomic_fetch_sub_1 - %1 = atomicrmw sub i8* %a, i8 %b release + %1 = atomicrmw sub ptr %a, i8 %b release ret i8 %1 } -define i8 @atomicrmw_sub_i8_acq_rel(i8* %a, i8 %b) nounwind { +define i8 @atomicrmw_sub_i8_acq_rel(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i8_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -264,11 +264,11 @@ define i8 @atomicrmw_sub_i8_acq_rel(i8* %a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI13_0: ; CSKY-NEXT: .long __atomic_fetch_sub_1 - %1 = atomicrmw sub i8* %a, i8 %b acq_rel + %1 = atomicrmw sub ptr %a, i8 %b acq_rel ret i8 %1 } -define i8 @atomicrmw_sub_i8_seq_cst(i8* %a, i8 %b) nounwind { +define i8 @atomicrmw_sub_i8_seq_cst(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i8_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -283,11 +283,11 @@ define i8 @atomicrmw_sub_i8_seq_cst(i8* %a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI14_0: ; CSKY-NEXT: .long __atomic_fetch_sub_1 - %1 = atomicrmw sub i8* %a, i8 %b seq_cst + %1 = atomicrmw sub ptr %a, i8 %b seq_cst ret i8 %1 } -define i8 @atomicrmw_and_i8_monotonic(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i8_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -302,11 +302,11 @@ define i8 @atomicrmw_and_i8_monotonic(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI15_0: ; CSKY-NEXT: .long __atomic_fetch_and_1 - %1 = atomicrmw and i8* %a, i8 %b monotonic + %1 = atomicrmw and ptr %a, i8 %b monotonic ret i8 %1 } -define i8 @atomicrmw_and_i8_acquire(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_and_i8_acquire(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i8_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -321,11 +321,11 @@ define i8 @atomicrmw_and_i8_acquire(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI16_0: ; CSKY-NEXT: .long __atomic_fetch_and_1 - %1 = atomicrmw and i8* %a, i8 %b acquire + %1 = atomicrmw and ptr %a, i8 %b acquire ret i8 %1 } -define i8 @atomicrmw_and_i8_release(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_and_i8_release(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i8_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -340,11 +340,11 @@ define i8 @atomicrmw_and_i8_release(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI17_0: ; CSKY-NEXT: .long __atomic_fetch_and_1 - %1 = atomicrmw and i8* %a, i8 %b release + %1 = atomicrmw and ptr %a, i8 %b release ret i8 %1 } -define i8 @atomicrmw_and_i8_acq_rel(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_and_i8_acq_rel(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i8_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -359,11 +359,11 @@ define i8 @atomicrmw_and_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI18_0: ; CSKY-NEXT: .long __atomic_fetch_and_1 - %1 = atomicrmw and i8* %a, i8 %b acq_rel + %1 = atomicrmw and ptr %a, i8 %b acq_rel ret i8 %1 } -define i8 @atomicrmw_and_i8_seq_cst(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_and_i8_seq_cst(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i8_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -378,11 +378,11 @@ define i8 @atomicrmw_and_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI19_0: ; CSKY-NEXT: .long __atomic_fetch_and_1 - %1 = atomicrmw and i8* %a, i8 %b seq_cst + %1 = atomicrmw and ptr %a, i8 %b seq_cst ret i8 %1 } -define i8 @atomicrmw_nand_i8_monotonic(i8* %a, i8 %b) nounwind { +define i8 @atomicrmw_nand_i8_monotonic(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i8_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -397,11 +397,11 @@ define i8 @atomicrmw_nand_i8_monotonic(i8* %a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI20_0: ; CSKY-NEXT: .long __atomic_fetch_nand_1 - %1 = atomicrmw nand i8* %a, i8 %b monotonic + %1 = atomicrmw nand ptr %a, i8 %b monotonic ret i8 %1 } -define i8 @atomicrmw_nand_i8_acquire(i8* %a, i8 %b) nounwind { +define i8 @atomicrmw_nand_i8_acquire(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i8_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -416,11 +416,11 @@ define i8 @atomicrmw_nand_i8_acquire(i8* %a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI21_0: ; CSKY-NEXT: .long __atomic_fetch_nand_1 - %1 = atomicrmw nand i8* %a, i8 %b acquire + %1 = atomicrmw nand ptr %a, i8 %b acquire ret i8 %1 } -define i8 @atomicrmw_nand_i8_release(i8* %a, i8 %b) nounwind { +define i8 @atomicrmw_nand_i8_release(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i8_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -435,11 +435,11 @@ define i8 @atomicrmw_nand_i8_release(i8* %a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI22_0: ; CSKY-NEXT: .long __atomic_fetch_nand_1 - %1 = atomicrmw nand i8* %a, i8 %b release + %1 = atomicrmw nand ptr %a, i8 %b release ret i8 %1 } -define i8 @atomicrmw_nand_i8_acq_rel(i8* %a, i8 %b) nounwind { +define i8 @atomicrmw_nand_i8_acq_rel(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i8_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -454,11 +454,11 @@ define i8 @atomicrmw_nand_i8_acq_rel(i8* %a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI23_0: ; CSKY-NEXT: .long __atomic_fetch_nand_1 - %1 = atomicrmw nand i8* %a, i8 %b acq_rel + %1 = atomicrmw nand ptr %a, i8 %b acq_rel ret i8 %1 } -define i8 @atomicrmw_nand_i8_seq_cst(i8* %a, i8 %b) nounwind { +define i8 @atomicrmw_nand_i8_seq_cst(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i8_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -473,11 +473,11 @@ define i8 @atomicrmw_nand_i8_seq_cst(i8* %a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI24_0: ; CSKY-NEXT: .long __atomic_fetch_nand_1 - %1 = atomicrmw nand i8* %a, i8 %b seq_cst + %1 = atomicrmw nand ptr %a, i8 %b seq_cst ret i8 %1 } -define i8 @atomicrmw_or_i8_monotonic(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_or_i8_monotonic(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i8_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -492,11 +492,11 @@ define i8 @atomicrmw_or_i8_monotonic(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI25_0: ; CSKY-NEXT: .long __atomic_fetch_or_1 - %1 = atomicrmw or i8* %a, i8 %b monotonic + %1 = atomicrmw or ptr %a, i8 %b monotonic ret i8 %1 } -define i8 @atomicrmw_or_i8_acquire(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_or_i8_acquire(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i8_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -511,11 +511,11 @@ define i8 @atomicrmw_or_i8_acquire(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI26_0: ; CSKY-NEXT: .long __atomic_fetch_or_1 - %1 = atomicrmw or i8* %a, i8 %b acquire + %1 = atomicrmw or ptr %a, i8 %b acquire ret i8 %1 } -define i8 @atomicrmw_or_i8_release(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_or_i8_release(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i8_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -530,11 +530,11 @@ define i8 @atomicrmw_or_i8_release(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI27_0: ; CSKY-NEXT: .long __atomic_fetch_or_1 - %1 = atomicrmw or i8* %a, i8 %b release + %1 = atomicrmw or ptr %a, i8 %b release ret i8 %1 } -define i8 @atomicrmw_or_i8_acq_rel(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_or_i8_acq_rel(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i8_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -549,11 +549,11 @@ define i8 @atomicrmw_or_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI28_0: ; CSKY-NEXT: .long __atomic_fetch_or_1 - %1 = atomicrmw or i8* %a, i8 %b acq_rel + %1 = atomicrmw or ptr %a, i8 %b acq_rel ret i8 %1 } -define i8 @atomicrmw_or_i8_seq_cst(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_or_i8_seq_cst(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i8_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -568,11 +568,11 @@ define i8 @atomicrmw_or_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI29_0: ; CSKY-NEXT: .long __atomic_fetch_or_1 - %1 = atomicrmw or i8* %a, i8 %b seq_cst + %1 = atomicrmw or ptr %a, i8 %b seq_cst ret i8 %1 } -define i8 @atomicrmw_xor_i8_monotonic(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_xor_i8_monotonic(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i8_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -587,11 +587,11 @@ define i8 @atomicrmw_xor_i8_monotonic(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI30_0: ; CSKY-NEXT: .long __atomic_fetch_xor_1 - %1 = atomicrmw xor i8* %a, i8 %b monotonic + %1 = atomicrmw xor ptr %a, i8 %b monotonic ret i8 %1 } -define i8 @atomicrmw_xor_i8_acquire(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_xor_i8_acquire(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i8_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -606,11 +606,11 @@ define i8 @atomicrmw_xor_i8_acquire(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI31_0: ; CSKY-NEXT: .long __atomic_fetch_xor_1 - %1 = atomicrmw xor i8* %a, i8 %b acquire + %1 = atomicrmw xor ptr %a, i8 %b acquire ret i8 %1 } -define i8 @atomicrmw_xor_i8_release(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_xor_i8_release(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i8_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -625,11 +625,11 @@ define i8 @atomicrmw_xor_i8_release(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI32_0: ; CSKY-NEXT: .long __atomic_fetch_xor_1 - %1 = atomicrmw xor i8* %a, i8 %b release + %1 = atomicrmw xor ptr %a, i8 %b release ret i8 %1 } -define i8 @atomicrmw_xor_i8_acq_rel(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_xor_i8_acq_rel(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i8_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -644,11 +644,11 @@ define i8 @atomicrmw_xor_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI33_0: ; CSKY-NEXT: .long __atomic_fetch_xor_1 - %1 = atomicrmw xor i8* %a, i8 %b acq_rel + %1 = atomicrmw xor ptr %a, i8 %b acq_rel ret i8 %1 } -define i8 @atomicrmw_xor_i8_seq_cst(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_xor_i8_seq_cst(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i8_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -663,11 +663,11 @@ define i8 @atomicrmw_xor_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI34_0: ; CSKY-NEXT: .long __atomic_fetch_xor_1 - %1 = atomicrmw xor i8* %a, i8 %b seq_cst + %1 = atomicrmw xor ptr %a, i8 %b seq_cst ret i8 %1 } -define i8 @atomicrmw_max_i8_monotonic(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i8_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -711,11 +711,11 @@ define i8 @atomicrmw_max_i8_monotonic(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI35_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw max i8* %a, i8 %b monotonic + %1 = atomicrmw max ptr %a, i8 %b monotonic ret i8 %1 } -define i8 @atomicrmw_max_i8_acquire(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_max_i8_acquire(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i8_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -759,11 +759,11 @@ define i8 @atomicrmw_max_i8_acquire(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI36_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw max i8* %a, i8 %b acquire + %1 = atomicrmw max ptr %a, i8 %b acquire ret i8 %1 } -define i8 @atomicrmw_max_i8_release(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_max_i8_release(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i8_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -807,11 +807,11 @@ define i8 @atomicrmw_max_i8_release(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI37_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw max i8* %a, i8 %b release + %1 = atomicrmw max ptr %a, i8 %b release ret i8 %1 } -define i8 @atomicrmw_max_i8_acq_rel(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_max_i8_acq_rel(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i8_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -855,11 +855,11 @@ define i8 @atomicrmw_max_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI38_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw max i8* %a, i8 %b acq_rel + %1 = atomicrmw max ptr %a, i8 %b acq_rel ret i8 %1 } -define i8 @atomicrmw_max_i8_seq_cst(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_max_i8_seq_cst(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i8_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -903,11 +903,11 @@ define i8 @atomicrmw_max_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI39_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw max i8* %a, i8 %b seq_cst + %1 = atomicrmw max ptr %a, i8 %b seq_cst ret i8 %1 } -define i8 @atomicrmw_min_i8_monotonic(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i8_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -951,11 +951,11 @@ define i8 @atomicrmw_min_i8_monotonic(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI40_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw min i8* %a, i8 %b monotonic + %1 = atomicrmw min ptr %a, i8 %b monotonic ret i8 %1 } -define i8 @atomicrmw_min_i8_acquire(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_min_i8_acquire(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i8_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -999,11 +999,11 @@ define i8 @atomicrmw_min_i8_acquire(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI41_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw min i8* %a, i8 %b acquire + %1 = atomicrmw min ptr %a, i8 %b acquire ret i8 %1 } -define i8 @atomicrmw_min_i8_release(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_min_i8_release(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i8_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -1047,11 +1047,11 @@ define i8 @atomicrmw_min_i8_release(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI42_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw min i8* %a, i8 %b release + %1 = atomicrmw min ptr %a, i8 %b release ret i8 %1 } -define i8 @atomicrmw_min_i8_acq_rel(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_min_i8_acq_rel(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i8_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -1095,11 +1095,11 @@ define i8 @atomicrmw_min_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI43_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw min i8* %a, i8 %b acq_rel + %1 = atomicrmw min ptr %a, i8 %b acq_rel ret i8 %1 } -define i8 @atomicrmw_min_i8_seq_cst(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_min_i8_seq_cst(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i8_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -1143,11 +1143,11 @@ define i8 @atomicrmw_min_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI44_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw min i8* %a, i8 %b seq_cst + %1 = atomicrmw min ptr %a, i8 %b seq_cst ret i8 %1 } -define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i8_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -1191,11 +1191,11 @@ define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI45_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw umax i8* %a, i8 %b monotonic + %1 = atomicrmw umax ptr %a, i8 %b monotonic ret i8 %1 } -define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_umax_i8_acquire(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i8_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -1239,11 +1239,11 @@ define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI46_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw umax i8* %a, i8 %b acquire + %1 = atomicrmw umax ptr %a, i8 %b acquire ret i8 %1 } -define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_umax_i8_release(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i8_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -1287,11 +1287,11 @@ define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI47_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw umax i8* %a, i8 %b release + %1 = atomicrmw umax ptr %a, i8 %b release ret i8 %1 } -define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_umax_i8_acq_rel(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i8_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -1335,11 +1335,11 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI48_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw umax i8* %a, i8 %b acq_rel + %1 = atomicrmw umax ptr %a, i8 %b acq_rel ret i8 %1 } -define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_umax_i8_seq_cst(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i8_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -1383,11 +1383,11 @@ define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI49_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw umax i8* %a, i8 %b seq_cst + %1 = atomicrmw umax ptr %a, i8 %b seq_cst ret i8 %1 } -define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_umin_i8_monotonic(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i8_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -1431,11 +1431,11 @@ define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI50_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw umin i8* %a, i8 %b monotonic + %1 = atomicrmw umin ptr %a, i8 %b monotonic ret i8 %1 } -define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_umin_i8_acquire(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i8_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -1479,11 +1479,11 @@ define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI51_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw umin i8* %a, i8 %b acquire + %1 = atomicrmw umin ptr %a, i8 %b acquire ret i8 %1 } -define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_umin_i8_release(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i8_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -1527,11 +1527,11 @@ define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI52_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw umin i8* %a, i8 %b release + %1 = atomicrmw umin ptr %a, i8 %b release ret i8 %1 } -define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_umin_i8_acq_rel(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i8_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -1575,11 +1575,11 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI53_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw umin i8* %a, i8 %b acq_rel + %1 = atomicrmw umin ptr %a, i8 %b acq_rel ret i8 %1 } -define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_umin_i8_seq_cst(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i8_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -1623,11 +1623,11 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI54_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw umin i8* %a, i8 %b seq_cst + %1 = atomicrmw umin ptr %a, i8 %b seq_cst ret i8 %1 } -define i16 @atomicrmw_xchg_i16_monotonic(i16* %a, i16 %b) nounwind { +define i16 @atomicrmw_xchg_i16_monotonic(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i16_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1642,11 +1642,11 @@ define i16 @atomicrmw_xchg_i16_monotonic(i16* %a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI55_0: ; CSKY-NEXT: .long __atomic_exchange_2 - %1 = atomicrmw xchg i16* %a, i16 %b monotonic + %1 = atomicrmw xchg ptr %a, i16 %b monotonic ret i16 %1 } -define i16 @atomicrmw_xchg_i16_acquire(i16* %a, i16 %b) nounwind { +define i16 @atomicrmw_xchg_i16_acquire(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i16_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1661,11 +1661,11 @@ define i16 @atomicrmw_xchg_i16_acquire(i16* %a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI56_0: ; CSKY-NEXT: .long __atomic_exchange_2 - %1 = atomicrmw xchg i16* %a, i16 %b acquire + %1 = atomicrmw xchg ptr %a, i16 %b acquire ret i16 %1 } -define i16 @atomicrmw_xchg_i16_release(i16* %a, i16 %b) nounwind { +define i16 @atomicrmw_xchg_i16_release(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i16_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1680,11 +1680,11 @@ define i16 @atomicrmw_xchg_i16_release(i16* %a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI57_0: ; CSKY-NEXT: .long __atomic_exchange_2 - %1 = atomicrmw xchg i16* %a, i16 %b release + %1 = atomicrmw xchg ptr %a, i16 %b release ret i16 %1 } -define i16 @atomicrmw_xchg_i16_acq_rel(i16* %a, i16 %b) nounwind { +define i16 @atomicrmw_xchg_i16_acq_rel(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i16_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1699,11 +1699,11 @@ define i16 @atomicrmw_xchg_i16_acq_rel(i16* %a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI58_0: ; CSKY-NEXT: .long __atomic_exchange_2 - %1 = atomicrmw xchg i16* %a, i16 %b acq_rel + %1 = atomicrmw xchg ptr %a, i16 %b acq_rel ret i16 %1 } -define i16 @atomicrmw_xchg_i16_seq_cst(i16* %a, i16 %b) nounwind { +define i16 @atomicrmw_xchg_i16_seq_cst(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i16_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1718,11 +1718,11 @@ define i16 @atomicrmw_xchg_i16_seq_cst(i16* %a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI59_0: ; CSKY-NEXT: .long __atomic_exchange_2 - %1 = atomicrmw xchg i16* %a, i16 %b seq_cst + %1 = atomicrmw xchg ptr %a, i16 %b seq_cst ret i16 %1 } -define i16 @atomicrmw_add_i16_monotonic(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_add_i16_monotonic(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i16_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1737,11 +1737,11 @@ define i16 @atomicrmw_add_i16_monotonic(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI60_0: ; CSKY-NEXT: .long __atomic_fetch_add_2 - %1 = atomicrmw add i16* %a, i16 %b monotonic + %1 = atomicrmw add ptr %a, i16 %b monotonic ret i16 %1 } -define i16 @atomicrmw_add_i16_acquire(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_add_i16_acquire(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i16_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1756,11 +1756,11 @@ define i16 @atomicrmw_add_i16_acquire(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI61_0: ; CSKY-NEXT: .long __atomic_fetch_add_2 - %1 = atomicrmw add i16* %a, i16 %b acquire + %1 = atomicrmw add ptr %a, i16 %b acquire ret i16 %1 } -define i16 @atomicrmw_add_i16_release(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_add_i16_release(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i16_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1775,11 +1775,11 @@ define i16 @atomicrmw_add_i16_release(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI62_0: ; CSKY-NEXT: .long __atomic_fetch_add_2 - %1 = atomicrmw add i16* %a, i16 %b release + %1 = atomicrmw add ptr %a, i16 %b release ret i16 %1 } -define i16 @atomicrmw_add_i16_acq_rel(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_add_i16_acq_rel(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i16_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1794,11 +1794,11 @@ define i16 @atomicrmw_add_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI63_0: ; CSKY-NEXT: .long __atomic_fetch_add_2 - %1 = atomicrmw add i16* %a, i16 %b acq_rel + %1 = atomicrmw add ptr %a, i16 %b acq_rel ret i16 %1 } -define i16 @atomicrmw_add_i16_seq_cst(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_add_i16_seq_cst(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i16_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1813,11 +1813,11 @@ define i16 @atomicrmw_add_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI64_0: ; CSKY-NEXT: .long __atomic_fetch_add_2 - %1 = atomicrmw add i16* %a, i16 %b seq_cst + %1 = atomicrmw add ptr %a, i16 %b seq_cst ret i16 %1 } -define i16 @atomicrmw_sub_i16_monotonic(i16* %a, i16 %b) nounwind { +define i16 @atomicrmw_sub_i16_monotonic(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i16_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1832,11 +1832,11 @@ define i16 @atomicrmw_sub_i16_monotonic(i16* %a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI65_0: ; CSKY-NEXT: .long __atomic_fetch_sub_2 - %1 = atomicrmw sub i16* %a, i16 %b monotonic + %1 = atomicrmw sub ptr %a, i16 %b monotonic ret i16 %1 } -define i16 @atomicrmw_sub_i16_acquire(i16* %a, i16 %b) nounwind { +define i16 @atomicrmw_sub_i16_acquire(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i16_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1851,11 +1851,11 @@ define i16 @atomicrmw_sub_i16_acquire(i16* %a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI66_0: ; CSKY-NEXT: .long __atomic_fetch_sub_2 - %1 = atomicrmw sub i16* %a, i16 %b acquire + %1 = atomicrmw sub ptr %a, i16 %b acquire ret i16 %1 } -define i16 @atomicrmw_sub_i16_release(i16* %a, i16 %b) nounwind { +define i16 @atomicrmw_sub_i16_release(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i16_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1870,11 +1870,11 @@ define i16 @atomicrmw_sub_i16_release(i16* %a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI67_0: ; CSKY-NEXT: .long __atomic_fetch_sub_2 - %1 = atomicrmw sub i16* %a, i16 %b release + %1 = atomicrmw sub ptr %a, i16 %b release ret i16 %1 } -define i16 @atomicrmw_sub_i16_acq_rel(i16* %a, i16 %b) nounwind { +define i16 @atomicrmw_sub_i16_acq_rel(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i16_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1889,11 +1889,11 @@ define i16 @atomicrmw_sub_i16_acq_rel(i16* %a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI68_0: ; CSKY-NEXT: .long __atomic_fetch_sub_2 - %1 = atomicrmw sub i16* %a, i16 %b acq_rel + %1 = atomicrmw sub ptr %a, i16 %b acq_rel ret i16 %1 } -define i16 @atomicrmw_sub_i16_seq_cst(i16* %a, i16 %b) nounwind { +define i16 @atomicrmw_sub_i16_seq_cst(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i16_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1908,11 +1908,11 @@ define i16 @atomicrmw_sub_i16_seq_cst(i16* %a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI69_0: ; CSKY-NEXT: .long __atomic_fetch_sub_2 - %1 = atomicrmw sub i16* %a, i16 %b seq_cst + %1 = atomicrmw sub ptr %a, i16 %b seq_cst ret i16 %1 } -define i16 @atomicrmw_and_i16_monotonic(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i16_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1927,11 +1927,11 @@ define i16 @atomicrmw_and_i16_monotonic(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI70_0: ; CSKY-NEXT: .long __atomic_fetch_and_2 - %1 = atomicrmw and i16* %a, i16 %b monotonic + %1 = atomicrmw and ptr %a, i16 %b monotonic ret i16 %1 } -define i16 @atomicrmw_and_i16_acquire(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_and_i16_acquire(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i16_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1946,11 +1946,11 @@ define i16 @atomicrmw_and_i16_acquire(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI71_0: ; CSKY-NEXT: .long __atomic_fetch_and_2 - %1 = atomicrmw and i16* %a, i16 %b acquire + %1 = atomicrmw and ptr %a, i16 %b acquire ret i16 %1 } -define i16 @atomicrmw_and_i16_release(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_and_i16_release(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i16_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1965,11 +1965,11 @@ define i16 @atomicrmw_and_i16_release(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI72_0: ; CSKY-NEXT: .long __atomic_fetch_and_2 - %1 = atomicrmw and i16* %a, i16 %b release + %1 = atomicrmw and ptr %a, i16 %b release ret i16 %1 } -define i16 @atomicrmw_and_i16_acq_rel(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_and_i16_acq_rel(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i16_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1984,11 +1984,11 @@ define i16 @atomicrmw_and_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI73_0: ; CSKY-NEXT: .long __atomic_fetch_and_2 - %1 = atomicrmw and i16* %a, i16 %b acq_rel + %1 = atomicrmw and ptr %a, i16 %b acq_rel ret i16 %1 } -define i16 @atomicrmw_and_i16_seq_cst(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_and_i16_seq_cst(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i16_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2003,11 +2003,11 @@ define i16 @atomicrmw_and_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI74_0: ; CSKY-NEXT: .long __atomic_fetch_and_2 - %1 = atomicrmw and i16* %a, i16 %b seq_cst + %1 = atomicrmw and ptr %a, i16 %b seq_cst ret i16 %1 } -define i16 @atomicrmw_nand_i16_monotonic(i16* %a, i16 %b) nounwind { +define i16 @atomicrmw_nand_i16_monotonic(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i16_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2022,11 +2022,11 @@ define i16 @atomicrmw_nand_i16_monotonic(i16* %a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI75_0: ; CSKY-NEXT: .long __atomic_fetch_nand_2 - %1 = atomicrmw nand i16* %a, i16 %b monotonic + %1 = atomicrmw nand ptr %a, i16 %b monotonic ret i16 %1 } -define i16 @atomicrmw_nand_i16_acquire(i16* %a, i16 %b) nounwind { +define i16 @atomicrmw_nand_i16_acquire(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i16_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2041,11 +2041,11 @@ define i16 @atomicrmw_nand_i16_acquire(i16* %a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI76_0: ; CSKY-NEXT: .long __atomic_fetch_nand_2 - %1 = atomicrmw nand i16* %a, i16 %b acquire + %1 = atomicrmw nand ptr %a, i16 %b acquire ret i16 %1 } -define i16 @atomicrmw_nand_i16_release(i16* %a, i16 %b) nounwind { +define i16 @atomicrmw_nand_i16_release(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i16_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2060,11 +2060,11 @@ define i16 @atomicrmw_nand_i16_release(i16* %a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI77_0: ; CSKY-NEXT: .long __atomic_fetch_nand_2 - %1 = atomicrmw nand i16* %a, i16 %b release + %1 = atomicrmw nand ptr %a, i16 %b release ret i16 %1 } -define i16 @atomicrmw_nand_i16_acq_rel(i16* %a, i16 %b) nounwind { +define i16 @atomicrmw_nand_i16_acq_rel(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i16_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2079,11 +2079,11 @@ define i16 @atomicrmw_nand_i16_acq_rel(i16* %a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI78_0: ; CSKY-NEXT: .long __atomic_fetch_nand_2 - %1 = atomicrmw nand i16* %a, i16 %b acq_rel + %1 = atomicrmw nand ptr %a, i16 %b acq_rel ret i16 %1 } -define i16 @atomicrmw_nand_i16_seq_cst(i16* %a, i16 %b) nounwind { +define i16 @atomicrmw_nand_i16_seq_cst(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i16_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2098,11 +2098,11 @@ define i16 @atomicrmw_nand_i16_seq_cst(i16* %a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI79_0: ; CSKY-NEXT: .long __atomic_fetch_nand_2 - %1 = atomicrmw nand i16* %a, i16 %b seq_cst + %1 = atomicrmw nand ptr %a, i16 %b seq_cst ret i16 %1 } -define i16 @atomicrmw_or_i16_monotonic(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_or_i16_monotonic(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i16_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2117,11 +2117,11 @@ define i16 @atomicrmw_or_i16_monotonic(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI80_0: ; CSKY-NEXT: .long __atomic_fetch_or_2 - %1 = atomicrmw or i16* %a, i16 %b monotonic + %1 = atomicrmw or ptr %a, i16 %b monotonic ret i16 %1 } -define i16 @atomicrmw_or_i16_acquire(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_or_i16_acquire(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i16_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2136,11 +2136,11 @@ define i16 @atomicrmw_or_i16_acquire(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI81_0: ; CSKY-NEXT: .long __atomic_fetch_or_2 - %1 = atomicrmw or i16* %a, i16 %b acquire + %1 = atomicrmw or ptr %a, i16 %b acquire ret i16 %1 } -define i16 @atomicrmw_or_i16_release(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_or_i16_release(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i16_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2155,11 +2155,11 @@ define i16 @atomicrmw_or_i16_release(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI82_0: ; CSKY-NEXT: .long __atomic_fetch_or_2 - %1 = atomicrmw or i16* %a, i16 %b release + %1 = atomicrmw or ptr %a, i16 %b release ret i16 %1 } -define i16 @atomicrmw_or_i16_acq_rel(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_or_i16_acq_rel(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i16_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2174,11 +2174,11 @@ define i16 @atomicrmw_or_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI83_0: ; CSKY-NEXT: .long __atomic_fetch_or_2 - %1 = atomicrmw or i16* %a, i16 %b acq_rel + %1 = atomicrmw or ptr %a, i16 %b acq_rel ret i16 %1 } -define i16 @atomicrmw_or_i16_seq_cst(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_or_i16_seq_cst(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i16_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2193,11 +2193,11 @@ define i16 @atomicrmw_or_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI84_0: ; CSKY-NEXT: .long __atomic_fetch_or_2 - %1 = atomicrmw or i16* %a, i16 %b seq_cst + %1 = atomicrmw or ptr %a, i16 %b seq_cst ret i16 %1 } -define i16 @atomicrmw_xor_i16_monotonic(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_xor_i16_monotonic(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i16_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2212,11 +2212,11 @@ define i16 @atomicrmw_xor_i16_monotonic(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI85_0: ; CSKY-NEXT: .long __atomic_fetch_xor_2 - %1 = atomicrmw xor i16* %a, i16 %b monotonic + %1 = atomicrmw xor ptr %a, i16 %b monotonic ret i16 %1 } -define i16 @atomicrmw_xor_i16_acquire(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_xor_i16_acquire(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i16_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2231,11 +2231,11 @@ define i16 @atomicrmw_xor_i16_acquire(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI86_0: ; CSKY-NEXT: .long __atomic_fetch_xor_2 - %1 = atomicrmw xor i16* %a, i16 %b acquire + %1 = atomicrmw xor ptr %a, i16 %b acquire ret i16 %1 } -define i16 @atomicrmw_xor_i16_release(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_xor_i16_release(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i16_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2250,11 +2250,11 @@ define i16 @atomicrmw_xor_i16_release(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI87_0: ; CSKY-NEXT: .long __atomic_fetch_xor_2 - %1 = atomicrmw xor i16* %a, i16 %b release + %1 = atomicrmw xor ptr %a, i16 %b release ret i16 %1 } -define i16 @atomicrmw_xor_i16_acq_rel(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_xor_i16_acq_rel(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i16_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2269,11 +2269,11 @@ define i16 @atomicrmw_xor_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI88_0: ; CSKY-NEXT: .long __atomic_fetch_xor_2 - %1 = atomicrmw xor i16* %a, i16 %b acq_rel + %1 = atomicrmw xor ptr %a, i16 %b acq_rel ret i16 %1 } -define i16 @atomicrmw_xor_i16_seq_cst(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_xor_i16_seq_cst(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i16_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2288,11 +2288,11 @@ define i16 @atomicrmw_xor_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI89_0: ; CSKY-NEXT: .long __atomic_fetch_xor_2 - %1 = atomicrmw xor i16* %a, i16 %b seq_cst + %1 = atomicrmw xor ptr %a, i16 %b seq_cst ret i16 %1 } -define i16 @atomicrmw_max_i16_monotonic(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i16_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -2336,11 +2336,11 @@ define i16 @atomicrmw_max_i16_monotonic(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI90_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw max i16* %a, i16 %b monotonic + %1 = atomicrmw max ptr %a, i16 %b monotonic ret i16 %1 } -define i16 @atomicrmw_max_i16_acquire(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_max_i16_acquire(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i16_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -2384,11 +2384,11 @@ define i16 @atomicrmw_max_i16_acquire(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI91_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw max i16* %a, i16 %b acquire + %1 = atomicrmw max ptr %a, i16 %b acquire ret i16 %1 } -define i16 @atomicrmw_max_i16_release(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_max_i16_release(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i16_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -2432,11 +2432,11 @@ define i16 @atomicrmw_max_i16_release(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI92_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw max i16* %a, i16 %b release + %1 = atomicrmw max ptr %a, i16 %b release ret i16 %1 } -define i16 @atomicrmw_max_i16_acq_rel(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_max_i16_acq_rel(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i16_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -2480,11 +2480,11 @@ define i16 @atomicrmw_max_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI93_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw max i16* %a, i16 %b acq_rel + %1 = atomicrmw max ptr %a, i16 %b acq_rel ret i16 %1 } -define i16 @atomicrmw_max_i16_seq_cst(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_max_i16_seq_cst(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i16_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -2528,11 +2528,11 @@ define i16 @atomicrmw_max_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI94_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw max i16* %a, i16 %b seq_cst + %1 = atomicrmw max ptr %a, i16 %b seq_cst ret i16 %1 } -define i16 @atomicrmw_min_i16_monotonic(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i16_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -2576,11 +2576,11 @@ define i16 @atomicrmw_min_i16_monotonic(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI95_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw min i16* %a, i16 %b monotonic + %1 = atomicrmw min ptr %a, i16 %b monotonic ret i16 %1 } -define i16 @atomicrmw_min_i16_acquire(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_min_i16_acquire(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i16_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -2624,11 +2624,11 @@ define i16 @atomicrmw_min_i16_acquire(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI96_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw min i16* %a, i16 %b acquire + %1 = atomicrmw min ptr %a, i16 %b acquire ret i16 %1 } -define i16 @atomicrmw_min_i16_release(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_min_i16_release(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i16_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -2672,11 +2672,11 @@ define i16 @atomicrmw_min_i16_release(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI97_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw min i16* %a, i16 %b release + %1 = atomicrmw min ptr %a, i16 %b release ret i16 %1 } -define i16 @atomicrmw_min_i16_acq_rel(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_min_i16_acq_rel(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i16_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -2720,11 +2720,11 @@ define i16 @atomicrmw_min_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI98_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw min i16* %a, i16 %b acq_rel + %1 = atomicrmw min ptr %a, i16 %b acq_rel ret i16 %1 } -define i16 @atomicrmw_min_i16_seq_cst(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_min_i16_seq_cst(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i16_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -2768,11 +2768,11 @@ define i16 @atomicrmw_min_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI99_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw min i16* %a, i16 %b seq_cst + %1 = atomicrmw min ptr %a, i16 %b seq_cst ret i16 %1 } -define i16 @atomicrmw_umax_i16_monotonic(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i16_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -2816,11 +2816,11 @@ define i16 @atomicrmw_umax_i16_monotonic(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI100_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw umax i16* %a, i16 %b monotonic + %1 = atomicrmw umax ptr %a, i16 %b monotonic ret i16 %1 } -define i16 @atomicrmw_umax_i16_acquire(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_umax_i16_acquire(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i16_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -2864,11 +2864,11 @@ define i16 @atomicrmw_umax_i16_acquire(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI101_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw umax i16* %a, i16 %b acquire + %1 = atomicrmw umax ptr %a, i16 %b acquire ret i16 %1 } -define i16 @atomicrmw_umax_i16_release(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_umax_i16_release(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i16_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -2912,11 +2912,11 @@ define i16 @atomicrmw_umax_i16_release(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI102_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw umax i16* %a, i16 %b release + %1 = atomicrmw umax ptr %a, i16 %b release ret i16 %1 } -define i16 @atomicrmw_umax_i16_acq_rel(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_umax_i16_acq_rel(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i16_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -2960,11 +2960,11 @@ define i16 @atomicrmw_umax_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI103_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw umax i16* %a, i16 %b acq_rel + %1 = atomicrmw umax ptr %a, i16 %b acq_rel ret i16 %1 } -define i16 @atomicrmw_umax_i16_seq_cst(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_umax_i16_seq_cst(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i16_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -3008,11 +3008,11 @@ define i16 @atomicrmw_umax_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI104_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw umax i16* %a, i16 %b seq_cst + %1 = atomicrmw umax ptr %a, i16 %b seq_cst ret i16 %1 } -define i16 @atomicrmw_umin_i16_monotonic(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i16_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -3056,11 +3056,11 @@ define i16 @atomicrmw_umin_i16_monotonic(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI105_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw umin i16* %a, i16 %b monotonic + %1 = atomicrmw umin ptr %a, i16 %b monotonic ret i16 %1 } -define i16 @atomicrmw_umin_i16_acquire(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_umin_i16_acquire(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i16_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -3104,11 +3104,11 @@ define i16 @atomicrmw_umin_i16_acquire(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI106_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw umin i16* %a, i16 %b acquire + %1 = atomicrmw umin ptr %a, i16 %b acquire ret i16 %1 } -define i16 @atomicrmw_umin_i16_release(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_umin_i16_release(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i16_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -3152,11 +3152,11 @@ define i16 @atomicrmw_umin_i16_release(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI107_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw umin i16* %a, i16 %b release + %1 = atomicrmw umin ptr %a, i16 %b release ret i16 %1 } -define i16 @atomicrmw_umin_i16_acq_rel(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_umin_i16_acq_rel(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i16_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -3200,11 +3200,11 @@ define i16 @atomicrmw_umin_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI108_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw umin i16* %a, i16 %b acq_rel + %1 = atomicrmw umin ptr %a, i16 %b acq_rel ret i16 %1 } -define i16 @atomicrmw_umin_i16_seq_cst(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_umin_i16_seq_cst(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i16_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -3248,11 +3248,11 @@ define i16 @atomicrmw_umin_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI109_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw umin i16* %a, i16 %b seq_cst + %1 = atomicrmw umin ptr %a, i16 %b seq_cst ret i16 %1 } -define i32 @atomicrmw_xchg_i32_monotonic(i32* %a, i32 %b) nounwind { +define i32 @atomicrmw_xchg_i32_monotonic(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i32_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3267,11 +3267,11 @@ define i32 @atomicrmw_xchg_i32_monotonic(i32* %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI110_0: ; CSKY-NEXT: .long __atomic_exchange_4 - %1 = atomicrmw xchg i32* %a, i32 %b monotonic + %1 = atomicrmw xchg ptr %a, i32 %b monotonic ret i32 %1 } -define i32 @atomicrmw_xchg_i32_acquire(i32* %a, i32 %b) nounwind { +define i32 @atomicrmw_xchg_i32_acquire(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i32_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3286,11 +3286,11 @@ define i32 @atomicrmw_xchg_i32_acquire(i32* %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI111_0: ; CSKY-NEXT: .long __atomic_exchange_4 - %1 = atomicrmw xchg i32* %a, i32 %b acquire + %1 = atomicrmw xchg ptr %a, i32 %b acquire ret i32 %1 } -define i32 @atomicrmw_xchg_i32_release(i32* %a, i32 %b) nounwind { +define i32 @atomicrmw_xchg_i32_release(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i32_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3305,11 +3305,11 @@ define i32 @atomicrmw_xchg_i32_release(i32* %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI112_0: ; CSKY-NEXT: .long __atomic_exchange_4 - %1 = atomicrmw xchg i32* %a, i32 %b release + %1 = atomicrmw xchg ptr %a, i32 %b release ret i32 %1 } -define i32 @atomicrmw_xchg_i32_acq_rel(i32* %a, i32 %b) nounwind { +define i32 @atomicrmw_xchg_i32_acq_rel(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i32_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3324,11 +3324,11 @@ define i32 @atomicrmw_xchg_i32_acq_rel(i32* %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI113_0: ; CSKY-NEXT: .long __atomic_exchange_4 - %1 = atomicrmw xchg i32* %a, i32 %b acq_rel + %1 = atomicrmw xchg ptr %a, i32 %b acq_rel ret i32 %1 } -define i32 @atomicrmw_xchg_i32_seq_cst(i32* %a, i32 %b) nounwind { +define i32 @atomicrmw_xchg_i32_seq_cst(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i32_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3343,11 +3343,11 @@ define i32 @atomicrmw_xchg_i32_seq_cst(i32* %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI114_0: ; CSKY-NEXT: .long __atomic_exchange_4 - %1 = atomicrmw xchg i32* %a, i32 %b seq_cst + %1 = atomicrmw xchg ptr %a, i32 %b seq_cst ret i32 %1 } -define i32 @atomicrmw_add_i32_monotonic(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_add_i32_monotonic(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i32_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3362,11 +3362,11 @@ define i32 @atomicrmw_add_i32_monotonic(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI115_0: ; CSKY-NEXT: .long __atomic_fetch_add_4 - %1 = atomicrmw add i32* %a, i32 %b monotonic + %1 = atomicrmw add ptr %a, i32 %b monotonic ret i32 %1 } -define i32 @atomicrmw_add_i32_acquire(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_add_i32_acquire(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i32_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3381,11 +3381,11 @@ define i32 @atomicrmw_add_i32_acquire(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI116_0: ; CSKY-NEXT: .long __atomic_fetch_add_4 - %1 = atomicrmw add i32* %a, i32 %b acquire + %1 = atomicrmw add ptr %a, i32 %b acquire ret i32 %1 } -define i32 @atomicrmw_add_i32_release(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_add_i32_release(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i32_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3400,11 +3400,11 @@ define i32 @atomicrmw_add_i32_release(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI117_0: ; CSKY-NEXT: .long __atomic_fetch_add_4 - %1 = atomicrmw add i32* %a, i32 %b release + %1 = atomicrmw add ptr %a, i32 %b release ret i32 %1 } -define i32 @atomicrmw_add_i32_acq_rel(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_add_i32_acq_rel(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i32_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3419,11 +3419,11 @@ define i32 @atomicrmw_add_i32_acq_rel(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI118_0: ; CSKY-NEXT: .long __atomic_fetch_add_4 - %1 = atomicrmw add i32* %a, i32 %b acq_rel + %1 = atomicrmw add ptr %a, i32 %b acq_rel ret i32 %1 } -define i32 @atomicrmw_add_i32_seq_cst(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_add_i32_seq_cst(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i32_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3438,11 +3438,11 @@ define i32 @atomicrmw_add_i32_seq_cst(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI119_0: ; CSKY-NEXT: .long __atomic_fetch_add_4 - %1 = atomicrmw add i32* %a, i32 %b seq_cst + %1 = atomicrmw add ptr %a, i32 %b seq_cst ret i32 %1 } -define i32 @atomicrmw_sub_i32_monotonic(i32* %a, i32 %b) nounwind { +define i32 @atomicrmw_sub_i32_monotonic(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i32_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3457,11 +3457,11 @@ define i32 @atomicrmw_sub_i32_monotonic(i32* %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI120_0: ; CSKY-NEXT: .long __atomic_fetch_sub_4 - %1 = atomicrmw sub i32* %a, i32 %b monotonic + %1 = atomicrmw sub ptr %a, i32 %b monotonic ret i32 %1 } -define i32 @atomicrmw_sub_i32_acquire(i32* %a, i32 %b) nounwind { +define i32 @atomicrmw_sub_i32_acquire(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i32_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3476,11 +3476,11 @@ define i32 @atomicrmw_sub_i32_acquire(i32* %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI121_0: ; CSKY-NEXT: .long __atomic_fetch_sub_4 - %1 = atomicrmw sub i32* %a, i32 %b acquire + %1 = atomicrmw sub ptr %a, i32 %b acquire ret i32 %1 } -define i32 @atomicrmw_sub_i32_release(i32* %a, i32 %b) nounwind { +define i32 @atomicrmw_sub_i32_release(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i32_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3495,11 +3495,11 @@ define i32 @atomicrmw_sub_i32_release(i32* %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI122_0: ; CSKY-NEXT: .long __atomic_fetch_sub_4 - %1 = atomicrmw sub i32* %a, i32 %b release + %1 = atomicrmw sub ptr %a, i32 %b release ret i32 %1 } -define i32 @atomicrmw_sub_i32_acq_rel(i32* %a, i32 %b) nounwind { +define i32 @atomicrmw_sub_i32_acq_rel(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i32_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3514,11 +3514,11 @@ define i32 @atomicrmw_sub_i32_acq_rel(i32* %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI123_0: ; CSKY-NEXT: .long __atomic_fetch_sub_4 - %1 = atomicrmw sub i32* %a, i32 %b acq_rel + %1 = atomicrmw sub ptr %a, i32 %b acq_rel ret i32 %1 } -define i32 @atomicrmw_sub_i32_seq_cst(i32* %a, i32 %b) nounwind { +define i32 @atomicrmw_sub_i32_seq_cst(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i32_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3533,11 +3533,11 @@ define i32 @atomicrmw_sub_i32_seq_cst(i32* %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI124_0: ; CSKY-NEXT: .long __atomic_fetch_sub_4 - %1 = atomicrmw sub i32* %a, i32 %b seq_cst + %1 = atomicrmw sub ptr %a, i32 %b seq_cst ret i32 %1 } -define i32 @atomicrmw_and_i32_monotonic(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_and_i32_monotonic(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i32_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3552,11 +3552,11 @@ define i32 @atomicrmw_and_i32_monotonic(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI125_0: ; CSKY-NEXT: .long __atomic_fetch_and_4 - %1 = atomicrmw and i32* %a, i32 %b monotonic + %1 = atomicrmw and ptr %a, i32 %b monotonic ret i32 %1 } -define i32 @atomicrmw_and_i32_acquire(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_and_i32_acquire(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i32_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3571,11 +3571,11 @@ define i32 @atomicrmw_and_i32_acquire(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI126_0: ; CSKY-NEXT: .long __atomic_fetch_and_4 - %1 = atomicrmw and i32* %a, i32 %b acquire + %1 = atomicrmw and ptr %a, i32 %b acquire ret i32 %1 } -define i32 @atomicrmw_and_i32_release(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_and_i32_release(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i32_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3590,11 +3590,11 @@ define i32 @atomicrmw_and_i32_release(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI127_0: ; CSKY-NEXT: .long __atomic_fetch_and_4 - %1 = atomicrmw and i32* %a, i32 %b release + %1 = atomicrmw and ptr %a, i32 %b release ret i32 %1 } -define i32 @atomicrmw_and_i32_acq_rel(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_and_i32_acq_rel(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i32_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3609,11 +3609,11 @@ define i32 @atomicrmw_and_i32_acq_rel(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI128_0: ; CSKY-NEXT: .long __atomic_fetch_and_4 - %1 = atomicrmw and i32* %a, i32 %b acq_rel + %1 = atomicrmw and ptr %a, i32 %b acq_rel ret i32 %1 } -define i32 @atomicrmw_and_i32_seq_cst(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_and_i32_seq_cst(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i32_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3628,11 +3628,11 @@ define i32 @atomicrmw_and_i32_seq_cst(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI129_0: ; CSKY-NEXT: .long __atomic_fetch_and_4 - %1 = atomicrmw and i32* %a, i32 %b seq_cst + %1 = atomicrmw and ptr %a, i32 %b seq_cst ret i32 %1 } -define i32 @atomicrmw_nand_i32_monotonic(i32* %a, i32 %b) nounwind { +define i32 @atomicrmw_nand_i32_monotonic(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i32_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3647,11 +3647,11 @@ define i32 @atomicrmw_nand_i32_monotonic(i32* %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI130_0: ; CSKY-NEXT: .long __atomic_fetch_nand_4 - %1 = atomicrmw nand i32* %a, i32 %b monotonic + %1 = atomicrmw nand ptr %a, i32 %b monotonic ret i32 %1 } -define i32 @atomicrmw_nand_i32_acquire(i32* %a, i32 %b) nounwind { +define i32 @atomicrmw_nand_i32_acquire(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i32_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3666,11 +3666,11 @@ define i32 @atomicrmw_nand_i32_acquire(i32* %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI131_0: ; CSKY-NEXT: .long __atomic_fetch_nand_4 - %1 = atomicrmw nand i32* %a, i32 %b acquire + %1 = atomicrmw nand ptr %a, i32 %b acquire ret i32 %1 } -define i32 @atomicrmw_nand_i32_release(i32* %a, i32 %b) nounwind { +define i32 @atomicrmw_nand_i32_release(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i32_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3685,11 +3685,11 @@ define i32 @atomicrmw_nand_i32_release(i32* %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI132_0: ; CSKY-NEXT: .long __atomic_fetch_nand_4 - %1 = atomicrmw nand i32* %a, i32 %b release + %1 = atomicrmw nand ptr %a, i32 %b release ret i32 %1 } -define i32 @atomicrmw_nand_i32_acq_rel(i32* %a, i32 %b) nounwind { +define i32 @atomicrmw_nand_i32_acq_rel(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i32_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3704,11 +3704,11 @@ define i32 @atomicrmw_nand_i32_acq_rel(i32* %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI133_0: ; CSKY-NEXT: .long __atomic_fetch_nand_4 - %1 = atomicrmw nand i32* %a, i32 %b acq_rel + %1 = atomicrmw nand ptr %a, i32 %b acq_rel ret i32 %1 } -define i32 @atomicrmw_nand_i32_seq_cst(i32* %a, i32 %b) nounwind { +define i32 @atomicrmw_nand_i32_seq_cst(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i32_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3723,11 +3723,11 @@ define i32 @atomicrmw_nand_i32_seq_cst(i32* %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI134_0: ; CSKY-NEXT: .long __atomic_fetch_nand_4 - %1 = atomicrmw nand i32* %a, i32 %b seq_cst + %1 = atomicrmw nand ptr %a, i32 %b seq_cst ret i32 %1 } -define i32 @atomicrmw_or_i32_monotonic(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_or_i32_monotonic(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i32_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3742,11 +3742,11 @@ define i32 @atomicrmw_or_i32_monotonic(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI135_0: ; CSKY-NEXT: .long __atomic_fetch_or_4 - %1 = atomicrmw or i32* %a, i32 %b monotonic + %1 = atomicrmw or ptr %a, i32 %b monotonic ret i32 %1 } -define i32 @atomicrmw_or_i32_acquire(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_or_i32_acquire(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i32_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3761,11 +3761,11 @@ define i32 @atomicrmw_or_i32_acquire(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI136_0: ; CSKY-NEXT: .long __atomic_fetch_or_4 - %1 = atomicrmw or i32* %a, i32 %b acquire + %1 = atomicrmw or ptr %a, i32 %b acquire ret i32 %1 } -define i32 @atomicrmw_or_i32_release(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_or_i32_release(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i32_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3780,11 +3780,11 @@ define i32 @atomicrmw_or_i32_release(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI137_0: ; CSKY-NEXT: .long __atomic_fetch_or_4 - %1 = atomicrmw or i32* %a, i32 %b release + %1 = atomicrmw or ptr %a, i32 %b release ret i32 %1 } -define i32 @atomicrmw_or_i32_acq_rel(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_or_i32_acq_rel(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i32_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3799,11 +3799,11 @@ define i32 @atomicrmw_or_i32_acq_rel(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI138_0: ; CSKY-NEXT: .long __atomic_fetch_or_4 - %1 = atomicrmw or i32* %a, i32 %b acq_rel + %1 = atomicrmw or ptr %a, i32 %b acq_rel ret i32 %1 } -define i32 @atomicrmw_or_i32_seq_cst(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_or_i32_seq_cst(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i32_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3818,11 +3818,11 @@ define i32 @atomicrmw_or_i32_seq_cst(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI139_0: ; CSKY-NEXT: .long __atomic_fetch_or_4 - %1 = atomicrmw or i32* %a, i32 %b seq_cst + %1 = atomicrmw or ptr %a, i32 %b seq_cst ret i32 %1 } -define i32 @atomicrmw_xor_i32_monotonic(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_xor_i32_monotonic(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i32_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3837,11 +3837,11 @@ define i32 @atomicrmw_xor_i32_monotonic(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI140_0: ; CSKY-NEXT: .long __atomic_fetch_xor_4 - %1 = atomicrmw xor i32* %a, i32 %b monotonic + %1 = atomicrmw xor ptr %a, i32 %b monotonic ret i32 %1 } -define i32 @atomicrmw_xor_i32_acquire(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_xor_i32_acquire(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i32_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3856,11 +3856,11 @@ define i32 @atomicrmw_xor_i32_acquire(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI141_0: ; CSKY-NEXT: .long __atomic_fetch_xor_4 - %1 = atomicrmw xor i32* %a, i32 %b acquire + %1 = atomicrmw xor ptr %a, i32 %b acquire ret i32 %1 } -define i32 @atomicrmw_xor_i32_release(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_xor_i32_release(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i32_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3875,11 +3875,11 @@ define i32 @atomicrmw_xor_i32_release(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI142_0: ; CSKY-NEXT: .long __atomic_fetch_xor_4 - %1 = atomicrmw xor i32* %a, i32 %b release + %1 = atomicrmw xor ptr %a, i32 %b release ret i32 %1 } -define i32 @atomicrmw_xor_i32_acq_rel(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_xor_i32_acq_rel(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i32_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3894,11 +3894,11 @@ define i32 @atomicrmw_xor_i32_acq_rel(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI143_0: ; CSKY-NEXT: .long __atomic_fetch_xor_4 - %1 = atomicrmw xor i32* %a, i32 %b acq_rel + %1 = atomicrmw xor ptr %a, i32 %b acq_rel ret i32 %1 } -define i32 @atomicrmw_xor_i32_seq_cst(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_xor_i32_seq_cst(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i32_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3913,11 +3913,11 @@ define i32 @atomicrmw_xor_i32_seq_cst(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI144_0: ; CSKY-NEXT: .long __atomic_fetch_xor_4 - %1 = atomicrmw xor i32* %a, i32 %b seq_cst + %1 = atomicrmw xor ptr %a, i32 %b seq_cst ret i32 %1 } -define i32 @atomicrmw_max_i32_monotonic(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_max_i32_monotonic(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i32_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -3957,11 +3957,11 @@ define i32 @atomicrmw_max_i32_monotonic(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI145_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw max i32* %a, i32 %b monotonic + %1 = atomicrmw max ptr %a, i32 %b monotonic ret i32 %1 } -define i32 @atomicrmw_max_i32_acquire(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_max_i32_acquire(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i32_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4001,11 +4001,11 @@ define i32 @atomicrmw_max_i32_acquire(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI146_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw max i32* %a, i32 %b acquire + %1 = atomicrmw max ptr %a, i32 %b acquire ret i32 %1 } -define i32 @atomicrmw_max_i32_release(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_max_i32_release(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i32_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4045,11 +4045,11 @@ define i32 @atomicrmw_max_i32_release(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI147_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw max i32* %a, i32 %b release + %1 = atomicrmw max ptr %a, i32 %b release ret i32 %1 } -define i32 @atomicrmw_max_i32_acq_rel(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_max_i32_acq_rel(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i32_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4089,11 +4089,11 @@ define i32 @atomicrmw_max_i32_acq_rel(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI148_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw max i32* %a, i32 %b acq_rel + %1 = atomicrmw max ptr %a, i32 %b acq_rel ret i32 %1 } -define i32 @atomicrmw_max_i32_seq_cst(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_max_i32_seq_cst(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i32_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4133,11 +4133,11 @@ define i32 @atomicrmw_max_i32_seq_cst(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI149_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw max i32* %a, i32 %b seq_cst + %1 = atomicrmw max ptr %a, i32 %b seq_cst ret i32 %1 } -define i32 @atomicrmw_min_i32_monotonic(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_min_i32_monotonic(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i32_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4177,11 +4177,11 @@ define i32 @atomicrmw_min_i32_monotonic(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI150_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw min i32* %a, i32 %b monotonic + %1 = atomicrmw min ptr %a, i32 %b monotonic ret i32 %1 } -define i32 @atomicrmw_min_i32_acquire(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_min_i32_acquire(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i32_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4221,11 +4221,11 @@ define i32 @atomicrmw_min_i32_acquire(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI151_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw min i32* %a, i32 %b acquire + %1 = atomicrmw min ptr %a, i32 %b acquire ret i32 %1 } -define i32 @atomicrmw_min_i32_release(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_min_i32_release(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i32_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4265,11 +4265,11 @@ define i32 @atomicrmw_min_i32_release(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI152_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw min i32* %a, i32 %b release + %1 = atomicrmw min ptr %a, i32 %b release ret i32 %1 } -define i32 @atomicrmw_min_i32_acq_rel(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_min_i32_acq_rel(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i32_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4309,11 +4309,11 @@ define i32 @atomicrmw_min_i32_acq_rel(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI153_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw min i32* %a, i32 %b acq_rel + %1 = atomicrmw min ptr %a, i32 %b acq_rel ret i32 %1 } -define i32 @atomicrmw_min_i32_seq_cst(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_min_i32_seq_cst(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i32_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4353,11 +4353,11 @@ define i32 @atomicrmw_min_i32_seq_cst(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI154_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw min i32* %a, i32 %b seq_cst + %1 = atomicrmw min ptr %a, i32 %b seq_cst ret i32 %1 } -define i32 @atomicrmw_umax_i32_monotonic(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_umax_i32_monotonic(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i32_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4397,11 +4397,11 @@ define i32 @atomicrmw_umax_i32_monotonic(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI155_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw umax i32* %a, i32 %b monotonic + %1 = atomicrmw umax ptr %a, i32 %b monotonic ret i32 %1 } -define i32 @atomicrmw_umax_i32_acquire(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_umax_i32_acquire(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i32_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4441,11 +4441,11 @@ define i32 @atomicrmw_umax_i32_acquire(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI156_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw umax i32* %a, i32 %b acquire + %1 = atomicrmw umax ptr %a, i32 %b acquire ret i32 %1 } -define i32 @atomicrmw_umax_i32_release(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_umax_i32_release(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i32_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4485,11 +4485,11 @@ define i32 @atomicrmw_umax_i32_release(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI157_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw umax i32* %a, i32 %b release + %1 = atomicrmw umax ptr %a, i32 %b release ret i32 %1 } -define i32 @atomicrmw_umax_i32_acq_rel(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_umax_i32_acq_rel(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i32_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4529,11 +4529,11 @@ define i32 @atomicrmw_umax_i32_acq_rel(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI158_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw umax i32* %a, i32 %b acq_rel + %1 = atomicrmw umax ptr %a, i32 %b acq_rel ret i32 %1 } -define i32 @atomicrmw_umax_i32_seq_cst(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_umax_i32_seq_cst(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i32_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4573,11 +4573,11 @@ define i32 @atomicrmw_umax_i32_seq_cst(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI159_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw umax i32* %a, i32 %b seq_cst + %1 = atomicrmw umax ptr %a, i32 %b seq_cst ret i32 %1 } -define i32 @atomicrmw_umin_i32_monotonic(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_umin_i32_monotonic(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i32_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4617,11 +4617,11 @@ define i32 @atomicrmw_umin_i32_monotonic(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI160_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw umin i32* %a, i32 %b monotonic + %1 = atomicrmw umin ptr %a, i32 %b monotonic ret i32 %1 } -define i32 @atomicrmw_umin_i32_acquire(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_umin_i32_acquire(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i32_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4661,11 +4661,11 @@ define i32 @atomicrmw_umin_i32_acquire(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI161_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw umin i32* %a, i32 %b acquire + %1 = atomicrmw umin ptr %a, i32 %b acquire ret i32 %1 } -define i32 @atomicrmw_umin_i32_release(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_umin_i32_release(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i32_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4705,11 +4705,11 @@ define i32 @atomicrmw_umin_i32_release(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI162_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw umin i32* %a, i32 %b release + %1 = atomicrmw umin ptr %a, i32 %b release ret i32 %1 } -define i32 @atomicrmw_umin_i32_acq_rel(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_umin_i32_acq_rel(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i32_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4749,11 +4749,11 @@ define i32 @atomicrmw_umin_i32_acq_rel(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI163_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw umin i32* %a, i32 %b acq_rel + %1 = atomicrmw umin ptr %a, i32 %b acq_rel ret i32 %1 } -define i32 @atomicrmw_umin_i32_seq_cst(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_umin_i32_seq_cst(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i32_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4793,11 +4793,11 @@ define i32 @atomicrmw_umin_i32_seq_cst(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI164_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw umin i32* %a, i32 %b seq_cst + %1 = atomicrmw umin ptr %a, i32 %b seq_cst ret i32 %1 } -define i64 @atomicrmw_xchg_i64_monotonic(i64* %a, i64 %b) nounwind { +define i64 @atomicrmw_xchg_i64_monotonic(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i64_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -4812,11 +4812,11 @@ define i64 @atomicrmw_xchg_i64_monotonic(i64* %a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI165_0: ; CSKY-NEXT: .long __atomic_exchange_8 - %1 = atomicrmw xchg i64* %a, i64 %b monotonic + %1 = atomicrmw xchg ptr %a, i64 %b monotonic ret i64 %1 } -define i64 @atomicrmw_xchg_i64_acquire(i64* %a, i64 %b) nounwind { +define i64 @atomicrmw_xchg_i64_acquire(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i64_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -4831,11 +4831,11 @@ define i64 @atomicrmw_xchg_i64_acquire(i64* %a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI166_0: ; CSKY-NEXT: .long __atomic_exchange_8 - %1 = atomicrmw xchg i64* %a, i64 %b acquire + %1 = atomicrmw xchg ptr %a, i64 %b acquire ret i64 %1 } -define i64 @atomicrmw_xchg_i64_release(i64* %a, i64 %b) nounwind { +define i64 @atomicrmw_xchg_i64_release(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i64_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -4850,11 +4850,11 @@ define i64 @atomicrmw_xchg_i64_release(i64* %a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI167_0: ; CSKY-NEXT: .long __atomic_exchange_8 - %1 = atomicrmw xchg i64* %a, i64 %b release + %1 = atomicrmw xchg ptr %a, i64 %b release ret i64 %1 } -define i64 @atomicrmw_xchg_i64_acq_rel(i64* %a, i64 %b) nounwind { +define i64 @atomicrmw_xchg_i64_acq_rel(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i64_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -4869,11 +4869,11 @@ define i64 @atomicrmw_xchg_i64_acq_rel(i64* %a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI168_0: ; CSKY-NEXT: .long __atomic_exchange_8 - %1 = atomicrmw xchg i64* %a, i64 %b acq_rel + %1 = atomicrmw xchg ptr %a, i64 %b acq_rel ret i64 %1 } -define i64 @atomicrmw_xchg_i64_seq_cst(i64* %a, i64 %b) nounwind { +define i64 @atomicrmw_xchg_i64_seq_cst(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i64_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -4888,11 +4888,11 @@ define i64 @atomicrmw_xchg_i64_seq_cst(i64* %a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI169_0: ; CSKY-NEXT: .long __atomic_exchange_8 - %1 = atomicrmw xchg i64* %a, i64 %b seq_cst + %1 = atomicrmw xchg ptr %a, i64 %b seq_cst ret i64 %1 } -define i64 @atomicrmw_add_i64_monotonic(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_add_i64_monotonic(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i64_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -4907,11 +4907,11 @@ define i64 @atomicrmw_add_i64_monotonic(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI170_0: ; CSKY-NEXT: .long __atomic_fetch_add_8 - %1 = atomicrmw add i64* %a, i64 %b monotonic + %1 = atomicrmw add ptr %a, i64 %b monotonic ret i64 %1 } -define i64 @atomicrmw_add_i64_acquire(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_add_i64_acquire(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i64_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -4926,11 +4926,11 @@ define i64 @atomicrmw_add_i64_acquire(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI171_0: ; CSKY-NEXT: .long __atomic_fetch_add_8 - %1 = atomicrmw add i64* %a, i64 %b acquire + %1 = atomicrmw add ptr %a, i64 %b acquire ret i64 %1 } -define i64 @atomicrmw_add_i64_release(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_add_i64_release(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i64_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -4945,11 +4945,11 @@ define i64 @atomicrmw_add_i64_release(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI172_0: ; CSKY-NEXT: .long __atomic_fetch_add_8 - %1 = atomicrmw add i64* %a, i64 %b release + %1 = atomicrmw add ptr %a, i64 %b release ret i64 %1 } -define i64 @atomicrmw_add_i64_acq_rel(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_add_i64_acq_rel(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i64_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -4964,11 +4964,11 @@ define i64 @atomicrmw_add_i64_acq_rel(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI173_0: ; CSKY-NEXT: .long __atomic_fetch_add_8 - %1 = atomicrmw add i64* %a, i64 %b acq_rel + %1 = atomicrmw add ptr %a, i64 %b acq_rel ret i64 %1 } -define i64 @atomicrmw_add_i64_seq_cst(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_add_i64_seq_cst(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i64_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -4983,11 +4983,11 @@ define i64 @atomicrmw_add_i64_seq_cst(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI174_0: ; CSKY-NEXT: .long __atomic_fetch_add_8 - %1 = atomicrmw add i64* %a, i64 %b seq_cst + %1 = atomicrmw add ptr %a, i64 %b seq_cst ret i64 %1 } -define i64 @atomicrmw_sub_i64_monotonic(i64* %a, i64 %b) nounwind { +define i64 @atomicrmw_sub_i64_monotonic(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i64_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5002,11 +5002,11 @@ define i64 @atomicrmw_sub_i64_monotonic(i64* %a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI175_0: ; CSKY-NEXT: .long __atomic_fetch_sub_8 - %1 = atomicrmw sub i64* %a, i64 %b monotonic + %1 = atomicrmw sub ptr %a, i64 %b monotonic ret i64 %1 } -define i64 @atomicrmw_sub_i64_acquire(i64* %a, i64 %b) nounwind { +define i64 @atomicrmw_sub_i64_acquire(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i64_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5021,11 +5021,11 @@ define i64 @atomicrmw_sub_i64_acquire(i64* %a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI176_0: ; CSKY-NEXT: .long __atomic_fetch_sub_8 - %1 = atomicrmw sub i64* %a, i64 %b acquire + %1 = atomicrmw sub ptr %a, i64 %b acquire ret i64 %1 } -define i64 @atomicrmw_sub_i64_release(i64* %a, i64 %b) nounwind { +define i64 @atomicrmw_sub_i64_release(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i64_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5040,11 +5040,11 @@ define i64 @atomicrmw_sub_i64_release(i64* %a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI177_0: ; CSKY-NEXT: .long __atomic_fetch_sub_8 - %1 = atomicrmw sub i64* %a, i64 %b release + %1 = atomicrmw sub ptr %a, i64 %b release ret i64 %1 } -define i64 @atomicrmw_sub_i64_acq_rel(i64* %a, i64 %b) nounwind { +define i64 @atomicrmw_sub_i64_acq_rel(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i64_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5059,11 +5059,11 @@ define i64 @atomicrmw_sub_i64_acq_rel(i64* %a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI178_0: ; CSKY-NEXT: .long __atomic_fetch_sub_8 - %1 = atomicrmw sub i64* %a, i64 %b acq_rel + %1 = atomicrmw sub ptr %a, i64 %b acq_rel ret i64 %1 } -define i64 @atomicrmw_sub_i64_seq_cst(i64* %a, i64 %b) nounwind { +define i64 @atomicrmw_sub_i64_seq_cst(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i64_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5078,11 +5078,11 @@ define i64 @atomicrmw_sub_i64_seq_cst(i64* %a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI179_0: ; CSKY-NEXT: .long __atomic_fetch_sub_8 - %1 = atomicrmw sub i64* %a, i64 %b seq_cst + %1 = atomicrmw sub ptr %a, i64 %b seq_cst ret i64 %1 } -define i64 @atomicrmw_and_i64_monotonic(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_and_i64_monotonic(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i64_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5097,11 +5097,11 @@ define i64 @atomicrmw_and_i64_monotonic(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI180_0: ; CSKY-NEXT: .long __atomic_fetch_and_8 - %1 = atomicrmw and i64* %a, i64 %b monotonic + %1 = atomicrmw and ptr %a, i64 %b monotonic ret i64 %1 } -define i64 @atomicrmw_and_i64_acquire(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_and_i64_acquire(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i64_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5116,11 +5116,11 @@ define i64 @atomicrmw_and_i64_acquire(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI181_0: ; CSKY-NEXT: .long __atomic_fetch_and_8 - %1 = atomicrmw and i64* %a, i64 %b acquire + %1 = atomicrmw and ptr %a, i64 %b acquire ret i64 %1 } -define i64 @atomicrmw_and_i64_release(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_and_i64_release(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i64_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5135,11 +5135,11 @@ define i64 @atomicrmw_and_i64_release(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI182_0: ; CSKY-NEXT: .long __atomic_fetch_and_8 - %1 = atomicrmw and i64* %a, i64 %b release + %1 = atomicrmw and ptr %a, i64 %b release ret i64 %1 } -define i64 @atomicrmw_and_i64_acq_rel(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_and_i64_acq_rel(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i64_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5154,11 +5154,11 @@ define i64 @atomicrmw_and_i64_acq_rel(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI183_0: ; CSKY-NEXT: .long __atomic_fetch_and_8 - %1 = atomicrmw and i64* %a, i64 %b acq_rel + %1 = atomicrmw and ptr %a, i64 %b acq_rel ret i64 %1 } -define i64 @atomicrmw_and_i64_seq_cst(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_and_i64_seq_cst(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i64_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5173,11 +5173,11 @@ define i64 @atomicrmw_and_i64_seq_cst(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI184_0: ; CSKY-NEXT: .long __atomic_fetch_and_8 - %1 = atomicrmw and i64* %a, i64 %b seq_cst + %1 = atomicrmw and ptr %a, i64 %b seq_cst ret i64 %1 } -define i64 @atomicrmw_nand_i64_monotonic(i64* %a, i64 %b) nounwind { +define i64 @atomicrmw_nand_i64_monotonic(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i64_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5192,11 +5192,11 @@ define i64 @atomicrmw_nand_i64_monotonic(i64* %a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI185_0: ; CSKY-NEXT: .long __atomic_fetch_nand_8 - %1 = atomicrmw nand i64* %a, i64 %b monotonic + %1 = atomicrmw nand ptr %a, i64 %b monotonic ret i64 %1 } -define i64 @atomicrmw_nand_i64_acquire(i64* %a, i64 %b) nounwind { +define i64 @atomicrmw_nand_i64_acquire(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i64_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5211,11 +5211,11 @@ define i64 @atomicrmw_nand_i64_acquire(i64* %a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI186_0: ; CSKY-NEXT: .long __atomic_fetch_nand_8 - %1 = atomicrmw nand i64* %a, i64 %b acquire + %1 = atomicrmw nand ptr %a, i64 %b acquire ret i64 %1 } -define i64 @atomicrmw_nand_i64_release(i64* %a, i64 %b) nounwind { +define i64 @atomicrmw_nand_i64_release(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i64_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5230,11 +5230,11 @@ define i64 @atomicrmw_nand_i64_release(i64* %a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI187_0: ; CSKY-NEXT: .long __atomic_fetch_nand_8 - %1 = atomicrmw nand i64* %a, i64 %b release + %1 = atomicrmw nand ptr %a, i64 %b release ret i64 %1 } -define i64 @atomicrmw_nand_i64_acq_rel(i64* %a, i64 %b) nounwind { +define i64 @atomicrmw_nand_i64_acq_rel(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i64_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5249,11 +5249,11 @@ define i64 @atomicrmw_nand_i64_acq_rel(i64* %a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI188_0: ; CSKY-NEXT: .long __atomic_fetch_nand_8 - %1 = atomicrmw nand i64* %a, i64 %b acq_rel + %1 = atomicrmw nand ptr %a, i64 %b acq_rel ret i64 %1 } -define i64 @atomicrmw_nand_i64_seq_cst(i64* %a, i64 %b) nounwind { +define i64 @atomicrmw_nand_i64_seq_cst(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i64_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5268,11 +5268,11 @@ define i64 @atomicrmw_nand_i64_seq_cst(i64* %a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI189_0: ; CSKY-NEXT: .long __atomic_fetch_nand_8 - %1 = atomicrmw nand i64* %a, i64 %b seq_cst + %1 = atomicrmw nand ptr %a, i64 %b seq_cst ret i64 %1 } -define i64 @atomicrmw_or_i64_monotonic(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_or_i64_monotonic(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i64_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5287,11 +5287,11 @@ define i64 @atomicrmw_or_i64_monotonic(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI190_0: ; CSKY-NEXT: .long __atomic_fetch_or_8 - %1 = atomicrmw or i64* %a, i64 %b monotonic + %1 = atomicrmw or ptr %a, i64 %b monotonic ret i64 %1 } -define i64 @atomicrmw_or_i64_acquire(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_or_i64_acquire(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i64_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5306,11 +5306,11 @@ define i64 @atomicrmw_or_i64_acquire(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI191_0: ; CSKY-NEXT: .long __atomic_fetch_or_8 - %1 = atomicrmw or i64* %a, i64 %b acquire + %1 = atomicrmw or ptr %a, i64 %b acquire ret i64 %1 } -define i64 @atomicrmw_or_i64_release(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_or_i64_release(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i64_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5325,11 +5325,11 @@ define i64 @atomicrmw_or_i64_release(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI192_0: ; CSKY-NEXT: .long __atomic_fetch_or_8 - %1 = atomicrmw or i64* %a, i64 %b release + %1 = atomicrmw or ptr %a, i64 %b release ret i64 %1 } -define i64 @atomicrmw_or_i64_acq_rel(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_or_i64_acq_rel(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i64_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5344,11 +5344,11 @@ define i64 @atomicrmw_or_i64_acq_rel(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI193_0: ; CSKY-NEXT: .long __atomic_fetch_or_8 - %1 = atomicrmw or i64* %a, i64 %b acq_rel + %1 = atomicrmw or ptr %a, i64 %b acq_rel ret i64 %1 } -define i64 @atomicrmw_or_i64_seq_cst(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_or_i64_seq_cst(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i64_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5363,11 +5363,11 @@ define i64 @atomicrmw_or_i64_seq_cst(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI194_0: ; CSKY-NEXT: .long __atomic_fetch_or_8 - %1 = atomicrmw or i64* %a, i64 %b seq_cst + %1 = atomicrmw or ptr %a, i64 %b seq_cst ret i64 %1 } -define i64 @atomicrmw_xor_i64_monotonic(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_xor_i64_monotonic(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i64_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5382,11 +5382,11 @@ define i64 @atomicrmw_xor_i64_monotonic(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI195_0: ; CSKY-NEXT: .long __atomic_fetch_xor_8 - %1 = atomicrmw xor i64* %a, i64 %b monotonic + %1 = atomicrmw xor ptr %a, i64 %b monotonic ret i64 %1 } -define i64 @atomicrmw_xor_i64_acquire(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_xor_i64_acquire(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i64_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5401,11 +5401,11 @@ define i64 @atomicrmw_xor_i64_acquire(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI196_0: ; CSKY-NEXT: .long __atomic_fetch_xor_8 - %1 = atomicrmw xor i64* %a, i64 %b acquire + %1 = atomicrmw xor ptr %a, i64 %b acquire ret i64 %1 } -define i64 @atomicrmw_xor_i64_release(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_xor_i64_release(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i64_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5420,11 +5420,11 @@ define i64 @atomicrmw_xor_i64_release(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI197_0: ; CSKY-NEXT: .long __atomic_fetch_xor_8 - %1 = atomicrmw xor i64* %a, i64 %b release + %1 = atomicrmw xor ptr %a, i64 %b release ret i64 %1 } -define i64 @atomicrmw_xor_i64_acq_rel(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_xor_i64_acq_rel(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i64_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5439,11 +5439,11 @@ define i64 @atomicrmw_xor_i64_acq_rel(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI198_0: ; CSKY-NEXT: .long __atomic_fetch_xor_8 - %1 = atomicrmw xor i64* %a, i64 %b acq_rel + %1 = atomicrmw xor ptr %a, i64 %b acq_rel ret i64 %1 } -define i64 @atomicrmw_xor_i64_seq_cst(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_xor_i64_seq_cst(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i64_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5458,11 +5458,11 @@ define i64 @atomicrmw_xor_i64_seq_cst(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI199_0: ; CSKY-NEXT: .long __atomic_fetch_xor_8 - %1 = atomicrmw xor i64* %a, i64 %b seq_cst + %1 = atomicrmw xor ptr %a, i64 %b seq_cst ret i64 %1 } -define i64 @atomicrmw_max_i64_monotonic(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_max_i64_monotonic(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i64_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -5524,11 +5524,11 @@ define i64 @atomicrmw_max_i64_monotonic(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI200_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw max i64* %a, i64 %b monotonic + %1 = atomicrmw max ptr %a, i64 %b monotonic ret i64 %1 } -define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_max_i64_acquire(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i64_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -5590,11 +5590,11 @@ define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI201_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw max i64* %a, i64 %b acquire + %1 = atomicrmw max ptr %a, i64 %b acquire ret i64 %1 } -define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_max_i64_release(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i64_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 24 @@ -5659,11 +5659,11 @@ define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI202_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw max i64* %a, i64 %b release + %1 = atomicrmw max ptr %a, i64 %b release ret i64 %1 } -define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_max_i64_acq_rel(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i64_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 24 @@ -5728,11 +5728,11 @@ define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI203_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw max i64* %a, i64 %b acq_rel + %1 = atomicrmw max ptr %a, i64 %b acq_rel ret i64 %1 } -define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_max_i64_seq_cst(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i64_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -5794,11 +5794,11 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI204_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw max i64* %a, i64 %b seq_cst + %1 = atomicrmw max ptr %a, i64 %b seq_cst ret i64 %1 } -define i64 @atomicrmw_min_i64_monotonic(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_min_i64_monotonic(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i64_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -5860,11 +5860,11 @@ define i64 @atomicrmw_min_i64_monotonic(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI205_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw min i64* %a, i64 %b monotonic + %1 = atomicrmw min ptr %a, i64 %b monotonic ret i64 %1 } -define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_min_i64_acquire(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i64_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -5926,11 +5926,11 @@ define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI206_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw min i64* %a, i64 %b acquire + %1 = atomicrmw min ptr %a, i64 %b acquire ret i64 %1 } -define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_min_i64_release(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i64_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 24 @@ -5995,11 +5995,11 @@ define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI207_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw min i64* %a, i64 %b release + %1 = atomicrmw min ptr %a, i64 %b release ret i64 %1 } -define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_min_i64_acq_rel(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i64_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 24 @@ -6064,11 +6064,11 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI208_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw min i64* %a, i64 %b acq_rel + %1 = atomicrmw min ptr %a, i64 %b acq_rel ret i64 %1 } -define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_min_i64_seq_cst(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i64_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -6130,11 +6130,11 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI209_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw min i64* %a, i64 %b seq_cst + %1 = atomicrmw min ptr %a, i64 %b seq_cst ret i64 %1 } -define i64 @atomicrmw_umax_i64_monotonic(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_umax_i64_monotonic(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i64_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -6192,11 +6192,11 @@ define i64 @atomicrmw_umax_i64_monotonic(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI210_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw umax i64* %a, i64 %b monotonic + %1 = atomicrmw umax ptr %a, i64 %b monotonic ret i64 %1 } -define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_umax_i64_acquire(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i64_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -6254,11 +6254,11 @@ define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI211_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw umax i64* %a, i64 %b acquire + %1 = atomicrmw umax ptr %a, i64 %b acquire ret i64 %1 } -define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_umax_i64_release(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i64_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 24 @@ -6319,11 +6319,11 @@ define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI212_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw umax i64* %a, i64 %b release + %1 = atomicrmw umax ptr %a, i64 %b release ret i64 %1 } -define i64 @atomicrmw_umax_i64_acq_rel(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_umax_i64_acq_rel(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i64_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 24 @@ -6384,11 +6384,11 @@ define i64 @atomicrmw_umax_i64_acq_rel(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI213_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw umax i64* %a, i64 %b acq_rel + %1 = atomicrmw umax ptr %a, i64 %b acq_rel ret i64 %1 } -define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_umax_i64_seq_cst(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i64_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -6446,11 +6446,11 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI214_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw umax i64* %a, i64 %b seq_cst + %1 = atomicrmw umax ptr %a, i64 %b seq_cst ret i64 %1 } -define i64 @atomicrmw_umin_i64_monotonic(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_umin_i64_monotonic(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i64_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -6516,11 +6516,11 @@ define i64 @atomicrmw_umin_i64_monotonic(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI215_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw umin i64* %a, i64 %b monotonic + %1 = atomicrmw umin ptr %a, i64 %b monotonic ret i64 %1 } -define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_umin_i64_acquire(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i64_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -6586,11 +6586,11 @@ define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI216_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw umin i64* %a, i64 %b acquire + %1 = atomicrmw umin ptr %a, i64 %b acquire ret i64 %1 } -define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_umin_i64_release(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i64_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 24 @@ -6659,11 +6659,11 @@ define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI217_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw umin i64* %a, i64 %b release + %1 = atomicrmw umin ptr %a, i64 %b release ret i64 %1 } -define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_umin_i64_acq_rel(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i64_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 24 @@ -6732,11 +6732,11 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI218_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw umin i64* %a, i64 %b acq_rel + %1 = atomicrmw umin ptr %a, i64 %b acq_rel ret i64 %1 } -define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_umin_i64_seq_cst(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i64_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -6802,6 +6802,6 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI219_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw umin i64* %a, i64 %b seq_cst + %1 = atomicrmw umin ptr %a, i64 %b seq_cst ret i64 %1 } diff --git a/llvm/test/CodeGen/CSKY/call-16bit.ll b/llvm/test/CodeGen/CSKY/call-16bit.ll index e7f169a9df12..f30c0285985c 100644 --- a/llvm/test/CodeGen/CSKY/call-16bit.ll +++ b/llvm/test/CodeGen/CSKY/call-16bit.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky | FileCheck %s -@p_fun = global void (i32, i32)* @bar, align 8 +@p_fun = global ptr @bar, align 8 declare void @bar(i32, i32) -define void @foo(i32 %a, i32* %ptr){ +define void @foo(i32 %a, ptr %ptr){ ; CHECK-LABEL: foo: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: subi16 sp, sp, 4 @@ -28,12 +28,12 @@ define void @foo(i32 %a, i32* %ptr){ ; CHECK-NEXT: .long bar ; entry: - %0 = load i32, i32* %ptr + %0 = load i32, ptr %ptr tail call void (i32, i32) @bar(i32 %a, i32 %0) ret void } -define void @foo_indirect(i32 %a, i32* %ptr) { +define void @foo_indirect(i32 %a, ptr %ptr) { ; CHECK-LABEL: foo_indirect: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: subi16 sp, sp, 4 @@ -57,8 +57,8 @@ define void @foo_indirect(i32 %a, i32* %ptr) { ; CHECK-NEXT: .long p_fun ; entry: - %0 = load void (i32, i32)*, void (i32, i32)** @p_fun, align 8 - %1 = load i32, i32* %ptr + %0 = load ptr, ptr @p_fun, align 8 + %1 = load i32, ptr %ptr tail call void (i32, i32) %0(i32 %a, i32 %1) ret void } diff --git a/llvm/test/CodeGen/CSKY/call.ll b/llvm/test/CodeGen/CSKY/call.ll index 8804756802fc..c6621c9da964 100644 --- a/llvm/test/CodeGen/CSKY/call.ll +++ b/llvm/test/CodeGen/CSKY/call.ll @@ -3,11 +3,11 @@ ; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -relocation-model=pic -code-model=small -mattr=+2e3 | FileCheck %s --check-prefix=CHECK-PIC-SMALL ; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -relocation-model=pic -code-model=large -mattr=+2e3 | FileCheck %s --check-prefix=CHECK-PIC-LARGE -@p_fun = global void (i32, i32)* @bar, align 8 +@p_fun = global ptr @bar, align 8 declare void @bar(i32, i32) -define void @foo(i32 %a, i32* %ptr){ +define void @foo(i32 %a, ptr %ptr){ ; CHECK-LABEL: foo: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: subi16 sp, sp, 4 @@ -63,12 +63,12 @@ define void @foo(i32 %a, i32* %ptr){ ; CHECK-PIC-NEXT: ld32.w a1, a1, 0 ; CHECK-PIC-NEXT: br32 bar entry: - %0 = load i32, i32* %ptr + %0 = load i32, ptr %ptr tail call void (i32, i32) @bar(i32 %a, i32 %0) ret void } -define void @foo_indirect(i32 %a, i32* %ptr) { +define void @foo_indirect(i32 %a, ptr %ptr) { ; CHECK-LABEL: foo_indirect: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: subi16 sp, sp, 4 @@ -132,8 +132,8 @@ define void @foo_indirect(i32 %a, i32* %ptr) { ; CHECK-PIC-NEXT: ld32.w a1, a1, 0 ; CHECK-PIC-NEXT: jmp32 a2 entry: - %0 = load void (i32, i32)*, void (i32, i32)** @p_fun, align 8 - %1 = load i32, i32* %ptr + %0 = load ptr, ptr @p_fun, align 8 + %1 = load i32, ptr %ptr tail call void (i32, i32) %0(i32 %a, i32 %1) ret void } diff --git a/llvm/test/CodeGen/CSKY/constantpool.ll b/llvm/test/CodeGen/CSKY/constantpool.ll index d7741f2e1a1b..b333968e9a43 100644 --- a/llvm/test/CodeGen/CSKY/constantpool.ll +++ b/llvm/test/CodeGen/CSKY/constantpool.ll @@ -4,7 +4,7 @@ declare i32 @llvm.cttz.i32(i32, i1) -define void @cttztest(i32 %C, i32* %CP) { +define void @cttztest(i32 %C, ptr %CP) { ; GENERIC-LABEL: cttztest: ; GENERIC: # %bb.0: ; GENERIC-NEXT: .cfi_def_cfa_offset 0 @@ -39,6 +39,6 @@ define void @cttztest(i32 %C, i32* %CP) { ; GENERIC-NEXT: .LCPI0_0: ; GENERIC-NEXT: .ascii "\000\001\034\002\035\016\030\003\036\026\024\017\031\021\004\b\037\033\r\027\025\023\020\007\032\f\022\006\013\005\n\t" %c = call i32 @llvm.cttz.i32( i32 %C, i1 true ) - store i32 %c, i32* %CP + store i32 %c, ptr %CP ret void } diff --git a/llvm/test/CodeGen/CSKY/dwarf-eh.ll b/llvm/test/CodeGen/CSKY/dwarf-eh.ll index 706db07c3036..c38b894d53a1 100644 --- a/llvm/test/CodeGen/CSKY/dwarf-eh.ll +++ b/llvm/test/CodeGen/CSKY/dwarf-eh.ll @@ -12,7 +12,7 @@ declare void @throw_exception() declare i32 @__gxx_personality_v0(...) -declare i8* @__cxa_begin_catch(i8*) +declare ptr @__cxa_begin_catch(ptr) declare void @__cxa_end_catch() @@ -22,7 +22,7 @@ declare void @__cxa_end_catch() ; LSDAEncoding = DW_EH_PE_pcrel | DW_EH_PE_sdata4 ; CHECK-NEXT: .cfi_lsda 27, .Lexception0 -define void @test1() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +define void @test1() personality ptr @__gxx_personality_v0 { ; SMALL: # %bb.0: # %entry ; SMALL-NEXT: subi16 sp, sp, 4 ; SMALL-NEXT: .cfi_def_cfa_offset 4 @@ -162,10 +162,10 @@ entry: invoke void @throw_exception() to label %try.cont unwind label %lpad lpad: - %0 = landingpad { i8*, i32 } - catch i8* null - %1 = extractvalue { i8*, i32 } %0, 0 - %2 = tail call i8* @__cxa_begin_catch(i8* %1) + %0 = landingpad { ptr, i32 } + catch ptr null + %1 = extractvalue { ptr, i32 } %0, 0 + %2 = tail call ptr @__cxa_begin_catch(ptr %1) tail call void @__cxa_end_catch() br label %try.cont diff --git a/llvm/test/CodeGen/CSKY/fpu/ldst-d.ll b/llvm/test/CodeGen/CSKY/fpu/ldst-d.ll index e31fd409d277..612cecb2b4d7 100644 --- a/llvm/test/CodeGen/CSKY/fpu/ldst-d.ll +++ b/llvm/test/CodeGen/CSKY/fpu/ldst-d.ll @@ -3,7 +3,7 @@ ; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv2_sf -mattr=+fpuv2_df | FileCheck %s --check-prefix=CHECK-DF ; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv3_sf -mattr=+fpuv3_df | FileCheck %s --check-prefix=CHECK-DF2 -define double @load_I_d(double* nocapture readonly %a) local_unnamed_addr #0 { +define double @load_I_d(ptr nocapture readonly %a) local_unnamed_addr #0 { ; ; ; CHECK-DF-LABEL: load_I_d: @@ -16,14 +16,14 @@ define double @load_I_d(double* nocapture readonly %a) local_unnamed_addr #0 { ; CHECK-DF2-NEXT: fld.64 vr0, (a0, 24) ; CHECK-DF2-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds double, double* %a, i64 3 - %0 = load double, double* %arrayidx, align 4 + %arrayidx = getelementptr inbounds double, ptr %a, i64 3 + %0 = load double, ptr %arrayidx, align 4 ret double %0 } -define double @load_R_d(double* nocapture readonly %a, i32 %b) local_unnamed_addr #0 { +define double @load_R_d(ptr nocapture readonly %a, i32 %b) local_unnamed_addr #0 { ; ; ; CHECK-DF-LABEL: load_R_d: @@ -37,12 +37,12 @@ define double @load_R_d(double* nocapture readonly %a, i32 %b) local_unnamed_add ; CHECK-DF2-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds double, double* %a, i64 %idxprom - %0 = load double, double* %arrayidx, align 4 + %arrayidx = getelementptr inbounds double, ptr %a, i64 %idxprom + %0 = load double, ptr %arrayidx, align 4 ret double %0 } -define double @store_I_d(double* %a, double %b) local_unnamed_addr #0 { +define double @store_I_d(ptr %a, double %b) local_unnamed_addr #0 { ; ; ; CHECK-DF-LABEL: store_I_d: @@ -68,12 +68,12 @@ define double @store_I_d(double* %a, double %b) local_unnamed_addr #0 { ; CHECK-DF2-NEXT: .LCPI2_0: ; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0 entry: - %arrayidx = getelementptr inbounds double, double* %a, i64 3 - store double %b, double* %arrayidx, align 4 + %arrayidx = getelementptr inbounds double, ptr %a, i64 3 + store double %b, ptr %arrayidx, align 4 ret double 0.0 } -define double @store_R_d(double* %a, i32 %b, double %c) local_unnamed_addr #0 { +define double @store_R_d(ptr %a, i32 %b, double %c) local_unnamed_addr #0 { ; ; ; CHECK-DF-LABEL: store_R_d: @@ -100,7 +100,7 @@ define double @store_R_d(double* %a, i32 %b, double %c) local_unnamed_addr #0 { ; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds double, double* %a, i64 %idxprom - store double %c, double* %arrayidx, align 4 + %arrayidx = getelementptr inbounds double, ptr %a, i64 %idxprom + store double %c, ptr %arrayidx, align 4 ret double 0.0 } diff --git a/llvm/test/CodeGen/CSKY/fpu/ldst-f.ll b/llvm/test/CodeGen/CSKY/fpu/ldst-f.ll index bbcde8e6430a..e22541fb3798 100644 --- a/llvm/test/CodeGen/CSKY/fpu/ldst-f.ll +++ b/llvm/test/CodeGen/CSKY/fpu/ldst-f.ll @@ -3,7 +3,7 @@ ; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv2_sf | FileCheck %s --check-prefix=CHECK-SF ; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv3_sf | FileCheck %s --check-prefix=CHECK-SF2 -define float @load_I_w(float* nocapture readonly %a) local_unnamed_addr #0 { +define float @load_I_w(ptr nocapture readonly %a) local_unnamed_addr #0 { ; ; CHECK-SF-LABEL: load_I_w: ; CHECK-SF: # %bb.0: # %entry @@ -15,12 +15,12 @@ define float @load_I_w(float* nocapture readonly %a) local_unnamed_addr #0 { ; CHECK-SF2-NEXT: fld.32 vr0, (a0, 12) ; CHECK-SF2-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds float, float* %a, i64 3 - %0 = load float, float* %arrayidx, align 4 + %arrayidx = getelementptr inbounds float, ptr %a, i64 3 + %0 = load float, ptr %arrayidx, align 4 ret float %0 } -define float @load_R_w(float* nocapture readonly %a, i32 %b) local_unnamed_addr #0 { +define float @load_R_w(ptr nocapture readonly %a, i32 %b) local_unnamed_addr #0 { ; ; CHECK-SF-LABEL: load_R_w: ; CHECK-SF: # %bb.0: # %entry @@ -33,13 +33,13 @@ define float @load_R_w(float* nocapture readonly %a, i32 %b) local_unnamed_addr ; CHECK-SF2-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds float, float* %a, i64 %idxprom - %0 = load float, float* %arrayidx, align 4 + %arrayidx = getelementptr inbounds float, ptr %a, i64 %idxprom + %0 = load float, ptr %arrayidx, align 4 ret float %0 } -define float @store_I_w(float* %a, float %b) local_unnamed_addr #0 { +define float @store_I_w(ptr %a, float %b) local_unnamed_addr #0 { ; ; CHECK-SF-LABEL: store_I_w: ; CHECK-SF: # %bb.0: # %entry @@ -55,12 +55,12 @@ define float @store_I_w(float* %a, float %b) local_unnamed_addr #0 { ; CHECK-SF2-NEXT: fmtvr.32.1 vr0, a0 ; CHECK-SF2-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds float, float* %a, i64 3 - store float %b, float* %arrayidx, align 4 + %arrayidx = getelementptr inbounds float, ptr %a, i64 3 + store float %b, ptr %arrayidx, align 4 ret float 0.0 } -define float @store_R_w(float* %a, i32 %b, float %c) local_unnamed_addr #0 { +define float @store_R_w(ptr %a, i32 %b, float %c) local_unnamed_addr #0 { ; ; CHECK-SF-LABEL: store_R_w: ; CHECK-SF: # %bb.0: # %entry @@ -77,7 +77,7 @@ define float @store_R_w(float* %a, i32 %b, float %c) local_unnamed_addr #0 { ; CHECK-SF2-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds float, float* %a, i64 %idxprom - store float %c, float* %arrayidx, align 4 + %arrayidx = getelementptr inbounds float, ptr %a, i64 %idxprom + store float %c, ptr %arrayidx, align 4 ret float 0.0 } diff --git a/llvm/test/CodeGen/CSKY/frameaddr-returnaddr.ll b/llvm/test/CodeGen/CSKY/frameaddr-returnaddr.ll index e8878cfa3254..1718bbb3a68b 100644 --- a/llvm/test/CodeGen/CSKY/frameaddr-returnaddr.ll +++ b/llvm/test/CodeGen/CSKY/frameaddr-returnaddr.ll @@ -2,11 +2,11 @@ ; RUN: llc -mtriple=csky -verify-machineinstrs -csky-no-aliases -mattr=+2e3 < %s \ ; RUN: | FileCheck %s -declare void @notdead(i8*) -declare i8* @llvm.frameaddress(i32) -declare i8* @llvm.returnaddress(i32) +declare void @notdead(ptr) +declare ptr @llvm.frameaddress(i32) +declare ptr @llvm.returnaddress(i32) -define i8* @test_frameaddress_0() nounwind { +define ptr @test_frameaddress_0() nounwind { ; CHECK-LABEL: test_frameaddress_0: ; CHECK: # %bb.0: ; CHECK-NEXT: subi16 sp, sp, 4 @@ -17,11 +17,11 @@ define i8* @test_frameaddress_0() nounwind { ; CHECK-NEXT: ld32.w l4, (sp, 0) # 4-byte Folded Reload ; CHECK-NEXT: addi16 sp, sp, 4 ; CHECK-NEXT: rts16 - %1 = call i8* @llvm.frameaddress(i32 0) - ret i8* %1 + %1 = call ptr @llvm.frameaddress(i32 0) + ret ptr %1 } -define i8* @test_frameaddress_2() nounwind { +define ptr @test_frameaddress_2() nounwind { ; CHECK-LABEL: test_frameaddress_2: ; CHECK: # %bb.0: ; CHECK-NEXT: subi16 sp, sp, 4 @@ -33,11 +33,11 @@ define i8* @test_frameaddress_2() nounwind { ; CHECK-NEXT: ld32.w l4, (sp, 0) # 4-byte Folded Reload ; CHECK-NEXT: addi16 sp, sp, 4 ; CHECK-NEXT: rts16 - %1 = call i8* @llvm.frameaddress(i32 2) - ret i8* %1 + %1 = call ptr @llvm.frameaddress(i32 2) + ret ptr %1 } -define i8* @test_frameaddress_3_alloca() nounwind { +define ptr @test_frameaddress_3_alloca() nounwind { ; CHECK-LABEL: test_frameaddress_3_alloca: ; CHECK: # %bb.0: ; CHECK-NEXT: subi16 sp, sp, 8 @@ -57,22 +57,22 @@ define i8* @test_frameaddress_3_alloca() nounwind { ; CHECK-NEXT: addi16 sp, sp, 8 ; CHECK-NEXT: rts16 %1 = alloca [100 x i8] - %2 = bitcast [100 x i8]* %1 to i8* - call void @notdead(i8* %2) - %3 = call i8* @llvm.frameaddress(i32 3) - ret i8* %3 + %2 = bitcast ptr %1 to ptr + call void @notdead(ptr %2) + %3 = call ptr @llvm.frameaddress(i32 3) + ret ptr %3 } -define i8* @test_returnaddress_0() nounwind { +define ptr @test_returnaddress_0() nounwind { ; CHECK-LABEL: test_returnaddress_0: ; CHECK: # %bb.0: ; CHECK-NEXT: mov16 a0, lr ; CHECK-NEXT: rts16 - %1 = call i8* @llvm.returnaddress(i32 0) - ret i8* %1 + %1 = call ptr @llvm.returnaddress(i32 0) + ret ptr %1 } -define i8* @test_returnaddress_2() nounwind { +define ptr @test_returnaddress_2() nounwind { ; CHECK-LABEL: test_returnaddress_2: ; CHECK: # %bb.0: ; CHECK-NEXT: subi16 sp, sp, 4 @@ -85,6 +85,6 @@ define i8* @test_returnaddress_2() nounwind { ; CHECK-NEXT: ld32.w l4, (sp, 0) # 4-byte Folded Reload ; CHECK-NEXT: addi16 sp, sp, 4 ; CHECK-NEXT: rts16 - %1 = call i8* @llvm.returnaddress(i32 2) - ret i8* %1 + %1 = call ptr @llvm.returnaddress(i32 2) + ret ptr %1 } diff --git a/llvm/test/CodeGen/CSKY/indirectbr.ll b/llvm/test/CodeGen/CSKY/indirectbr.ll index 431d3201dc89..71a30fb597c3 100644 --- a/llvm/test/CodeGen/CSKY/indirectbr.ll +++ b/llvm/test/CodeGen/CSKY/indirectbr.ll @@ -3,7 +3,7 @@ ; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -relocation-model=pic -code-model=small -mattr=+2e3 | FileCheck %s --check-prefix=CHECK-PIC-SMALL ; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -relocation-model=pic -code-model=large -mattr=+2e3 | FileCheck %s --check-prefix=CHECK-PIC-LARGE -@f.a = private unnamed_addr constant [2 x i8*] [i8* blockaddress(@f, %return), i8* blockaddress(@f, %l2)], align 16 +@f.a = private unnamed_addr constant [2 x ptr] [ptr blockaddress(@f, %return), ptr blockaddress(@f, %l2)], align 16 define i32 @f(i32 %x) #0 { ; CHECK-LABEL: f: @@ -88,9 +88,9 @@ define i32 @f(i32 %x) #0 { ; CHECK-PIC-LARGE-NEXT: .long .Lf.a@GOTOFF entry: %idxprom = sext i32 %x to i64 - %arrayidx = getelementptr inbounds [2 x i8*], [2 x i8*]* @f.a, i64 0, i64 %idxprom - %0 = load i8*, i8** %arrayidx, align 8 - indirectbr i8* %0, [label %return, label %l2] + %arrayidx = getelementptr inbounds [2 x ptr], ptr @f.a, i64 0, i64 %idxprom + %0 = load ptr, ptr %arrayidx, align 8 + indirectbr ptr %0, [label %return, label %l2] l2: ; preds = %entry br label %return diff --git a/llvm/test/CodeGen/CSKY/inline-asm-d-constraint-f.ll b/llvm/test/CodeGen/CSKY/inline-asm-d-constraint-f.ll index 09efc7cf804c..313c8db61092 100644 --- a/llvm/test/CodeGen/CSKY/inline-asm-d-constraint-f.ll +++ b/llvm/test/CodeGen/CSKY/inline-asm-d-constraint-f.ll @@ -21,7 +21,7 @@ define double @constraint_f_double(double %a) nounwind { ; CSKYF-NEXT: .LCPI0_0: ; CSKYF-NEXT: .long gd - %1 = load double, double* @gd + %1 = load double, ptr @gd %2 = tail call double asm "faddd $0, $1, $2", "=v,v,v"(double %a, double %1) ret double %2 } @@ -45,7 +45,7 @@ define double @constraint_f_double_abi_name(double %a) nounwind { ; CSKYF-NEXT: .LCPI1_0: ; CSKYF-NEXT: .long gd - %1 = load double, double* @gd + %1 = load double, ptr @gd %2 = tail call double asm "faddd $0, $1, $2", "={fr1},{fr2},{fr3}"(double %a, double %1) ret double %2 } diff --git a/llvm/test/CodeGen/CSKY/inline-asm-f-constraint-f.ll b/llvm/test/CodeGen/CSKY/inline-asm-f-constraint-f.ll index cf97a8477bd4..d6d5b9b2489c 100644 --- a/llvm/test/CodeGen/CSKY/inline-asm-f-constraint-f.ll +++ b/llvm/test/CodeGen/CSKY/inline-asm-f-constraint-f.ll @@ -20,7 +20,7 @@ define float @constraint_f_float(float %a) nounwind { ; CSKYF-NEXT: .p2align 2 ; CSKYF-NEXT: .LCPI0_0: ; CSKYF-NEXT: .long gf - %1 = load float, float* @gf + %1 = load float, ptr @gf %2 = tail call float asm "fadds $0, $1, $2", "=v,v,v"(float %a, float %1) ret float %2 } @@ -43,7 +43,7 @@ define float @constraint_f_float_abi_name(float %a) nounwind { ; CSKYF-NEXT: .LCPI1_0: ; CSKYF-NEXT: .long gf - %1 = load float, float* @gf + %1 = load float, ptr @gf %2 = tail call float asm "fadds $0, $1, $2", "={fr0},{fr1},{fr2}"(float %a, float %1) ret float %2 } diff --git a/llvm/test/CodeGen/CSKY/inline-asm.ll b/llvm/test/CodeGen/CSKY/inline-asm.ll index 4e7cb8e98e74..b955e43ce30d 100644 --- a/llvm/test/CodeGen/CSKY/inline-asm.ll +++ b/llvm/test/CodeGen/CSKY/inline-asm.ll @@ -21,7 +21,7 @@ define i32 @constraint_r(i32 %a) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI0_0: ; CSKY-NEXT: .long gi - %1 = load i32, i32* @gi + %1 = load i32, ptr @gi %2 = tail call i32 asm "add $0, $1, $2", "=r,r,r"(i32 %a, i32 %1) ret i32 %2 } @@ -45,7 +45,7 @@ define i64 @constraint_r_i64(i32 %a) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI1_0: ; CSKY-NEXT: .long mi - %1 = load i64, i64* @mi + %1 = load i64, ptr @mi %2 = call i64 asm "mula.s32 $0, $1, $2", "=r,r,r,0"(i32 %a, i32 %a, i64 %1) ret i64 %2 } @@ -66,7 +66,7 @@ define i32 @constraint_a(i32 %a) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI2_0: ; CSKY-NEXT: .long gi - %1 = load i32, i32* @gi + %1 = load i32, ptr @gi %2 = tail call i32 asm "add $0, $1, $2", "=a,a,a"(i32 %a, i32 %1) ret i32 %2 } @@ -87,7 +87,7 @@ define i32 @constraint_b(i32 %a) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI3_0: ; CSKY-NEXT: .long gi - %1 = load i32, i32* @gi + %1 = load i32, ptr @gi %2 = tail call i32 asm "add $0, $1, $2", "=b,b,b"(i32 %a, i32 %1) ret i32 %2 } @@ -109,7 +109,7 @@ define i32 @constraint_z(i32 %a) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI4_0: ; CSKY-NEXT: .long gi - %1 = load i32, i32* @gi + %1 = load i32, ptr @gi %2 = tail call i32 asm "add $0, $1, $2", "=r,z,r"(i32 %a, i32 %1) ret i32 %2 } @@ -130,7 +130,7 @@ define i32 @constraint_c(i32 %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI5_0: ; CSKY-NEXT: .long gi - %1 = load i32, i32* @gi + %1 = load i32, ptr @gi %2 = tail call i32 asm "addc $0, $1, $2", "=r,r,r,~{c}"(i32 %a, i32 %1) ret i32 %2 } @@ -145,12 +145,12 @@ define i32 @constraint_i(i32 %a) nounwind { ; CSKY-NEXT: addi16 sp, sp, 4 ; CSKY-NEXT: rts16 - %1 = load i32, i32* @gi + %1 = load i32, ptr @gi %2 = tail call i32 asm "addi $0, $1, $2", "=r,r,i"(i32 %a, i32 113) ret i32 %2 } -define void @constraint_m(i32* %a) nounwind { +define void @constraint_m(ptr %a) nounwind { ; CSKY-LABEL: constraint_m: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -159,11 +159,11 @@ define void @constraint_m(i32* %a) nounwind { ; CSKY-NEXT: addi16 sp, sp, 4 ; CSKY-NEXT: rts16 - call void asm sideeffect "", "=*m"(i32* elementtype(i32) %a) + call void asm sideeffect "", "=*m"(ptr elementtype(i32) %a) ret void } -define i32 @constraint_m2(i32* %a) nounwind { +define i32 @constraint_m2(ptr %a) nounwind { ; CSKY-LABEL: constraint_m2: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -173,7 +173,7 @@ define i32 @constraint_m2(i32* %a) nounwind { ; CSKY-NEXT: addi16 sp, sp, 4 ; CSKY-NEXT: rts16 - %1 = tail call i32 asm "ld.w $0, $1", "=r,*m"(i32* elementtype(i32) %a) + %1 = tail call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %a) ret i32 %1 } @@ -200,7 +200,7 @@ define void @operand_global() nounwind { ; CSKY-NEXT: addi16 sp, sp, 4 ; CSKY-NEXT: rts16 - tail call void asm sideeffect ".4byte $0", "i"(i32* @gi) + tail call void asm sideeffect ".4byte $0", "i"(ptr @gi) ret void } @@ -216,7 +216,7 @@ define void @operand_block_address() nounwind { ; CSKY-NEXT: addi16 sp, sp, 4 ; CSKY-NEXT: rts16 - call void asm sideeffect "br32 $0", "i"(i8* blockaddress(@operand_block_address, %bb)) + call void asm sideeffect "br32 $0", "i"(ptr blockaddress(@operand_block_address, %bb)) br label %bb bb: ret void diff --git a/llvm/test/CodeGen/CSKY/ldst-i.ll b/llvm/test/CodeGen/CSKY/ldst-i.ll index 06cfc9bde655..c8f2683f0c33 100644 --- a/llvm/test/CodeGen/CSKY/ldst-i.ll +++ b/llvm/test/CodeGen/CSKY/ldst-i.ll @@ -2,7 +2,7 @@ ; RUN: llc -verify-machineinstrs -csky-no-aliases -mattr=+2e3 < %s -mtriple=csky | FileCheck %s ; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky | FileCheck %s --check-prefix=GENERIC -define signext i1 @load_I_bits(i1* nocapture readonly %a) local_unnamed_addr #0 { +define signext i1 @load_I_bits(ptr nocapture readonly %a) local_unnamed_addr #0 { ; CHECK-LABEL: load_I_bits: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ld16.b a0, (a0, 3) @@ -20,12 +20,12 @@ define signext i1 @load_I_bits(i1* nocapture readonly %a) local_unnamed_addr #0 ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i1, i1* %a, i64 3 - %0 = load i1, i1* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i1, ptr %a, i64 3 + %0 = load i1, ptr %arrayidx, align 1 ret i1 %0 } -define zeroext i1 @load_I_bit_(i1* nocapture readonly %a) local_unnamed_addr #0 { +define zeroext i1 @load_I_bit_(ptr nocapture readonly %a) local_unnamed_addr #0 { ; CHECK-LABEL: load_I_bit_: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ld16.b a0, (a0, 3) @@ -40,12 +40,12 @@ define zeroext i1 @load_I_bit_(i1* nocapture readonly %a) local_unnamed_addr #0 ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i1, i1* %a, i64 3 - %0 = load i1, i1* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i1, ptr %a, i64 3 + %0 = load i1, ptr %arrayidx, align 1 ret i1 %0 } -define signext i8 @load_I_bs(i8* nocapture readonly %a) local_unnamed_addr #0 { +define signext i8 @load_I_bs(ptr nocapture readonly %a) local_unnamed_addr #0 { ; CHECK-LABEL: load_I_bs: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ld32.bs a0, (a0, 3) @@ -61,12 +61,12 @@ define signext i8 @load_I_bs(i8* nocapture readonly %a) local_unnamed_addr #0 { ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i8, i8* %a, i64 3 - %0 = load i8, i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, ptr %a, i64 3 + %0 = load i8, ptr %arrayidx, align 1 ret i8 %0 } -define zeroext i8 @load_I_b_(i8* nocapture readonly %a) local_unnamed_addr #0 { +define zeroext i8 @load_I_b_(ptr nocapture readonly %a) local_unnamed_addr #0 { ; CHECK-LABEL: load_I_b_: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ld16.b a0, (a0, 3) @@ -81,12 +81,12 @@ define zeroext i8 @load_I_b_(i8* nocapture readonly %a) local_unnamed_addr #0 { ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i8, i8* %a, i64 3 - %0 = load i8, i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, ptr %a, i64 3 + %0 = load i8, ptr %arrayidx, align 1 ret i8 %0 } -define signext i16 @load_I_hs(i16* nocapture readonly %a) local_unnamed_addr #0 { +define signext i16 @load_I_hs(ptr nocapture readonly %a) local_unnamed_addr #0 { ; CHECK-LABEL: load_I_hs: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ld32.hs a0, (a0, 6) @@ -102,12 +102,12 @@ define signext i16 @load_I_hs(i16* nocapture readonly %a) local_unnamed_addr #0 ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i16, i16* %a, i64 3 - %0 = load i16, i16* %arrayidx, align 2 + %arrayidx = getelementptr inbounds i16, ptr %a, i64 3 + %0 = load i16, ptr %arrayidx, align 2 ret i16 %0 } -define zeroext i16 @load_I_h_(i16* nocapture readonly %a) local_unnamed_addr #0 { +define zeroext i16 @load_I_h_(ptr nocapture readonly %a) local_unnamed_addr #0 { ; CHECK-LABEL: load_I_h_: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ld16.h a0, (a0, 6) @@ -122,12 +122,12 @@ define zeroext i16 @load_I_h_(i16* nocapture readonly %a) local_unnamed_addr #0 ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i16, i16* %a, i64 3 - %0 = load i16, i16* %arrayidx, align 2 + %arrayidx = getelementptr inbounds i16, ptr %a, i64 3 + %0 = load i16, ptr %arrayidx, align 2 ret i16 %0 } -define i32 @load_I_w(i32* nocapture readonly %a) local_unnamed_addr #0 { +define i32 @load_I_w(ptr nocapture readonly %a) local_unnamed_addr #0 { ; CHECK-LABEL: load_I_w: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ld16.w a0, (a0, 12) @@ -142,12 +142,12 @@ define i32 @load_I_w(i32* nocapture readonly %a) local_unnamed_addr #0 { ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i32, i32* %a, i64 3 - %0 = load i32, i32* %arrayidx, align 4 + %arrayidx = getelementptr inbounds i32, ptr %a, i64 3 + %0 = load i32, ptr %arrayidx, align 4 ret i32 %0 } -define i64 @load_I_d(i64* nocapture readonly %a) local_unnamed_addr #0 { +define i64 @load_I_d(ptr nocapture readonly %a) local_unnamed_addr #0 { ; CHECK-LABEL: load_I_d: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ld16.w a2, (a0, 24) @@ -166,12 +166,12 @@ define i64 @load_I_d(i64* nocapture readonly %a) local_unnamed_addr #0 { ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i64, i64* %a, i64 3 - %0 = load i64, i64* %arrayidx, align 4 + %arrayidx = getelementptr inbounds i64, ptr %a, i64 3 + %0 = load i64, ptr %arrayidx, align 4 ret i64 %0 } -define i8 @load_I_i8_anyext(i8* %p) { +define i8 @load_I_i8_anyext(ptr %p) { ; CHECK-LABEL: load_I_i8_anyext: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ld16.b a0, (a0, 0) @@ -186,11 +186,11 @@ define i8 @load_I_i8_anyext(i8* %p) { ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %ret = load i8, i8* %p, align 1 + %ret = load i8, ptr %p, align 1 ret i8 %ret } -define signext i1 @load_R_bits(i1* nocapture readonly %a, i32 %b) local_unnamed_addr #0 { +define signext i1 @load_R_bits(ptr nocapture readonly %a, i32 %b) local_unnamed_addr #0 { ; CHECK-LABEL: load_R_bits: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ldr32.bs a0, (a0, a1 << 0) @@ -210,12 +210,12 @@ define signext i1 @load_R_bits(i1* nocapture readonly %a, i32 %b) local_unnamed_ ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i1, i1* %a, i64 %idxprom - %0 = load i1, i1* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i1, ptr %a, i64 %idxprom + %0 = load i1, ptr %arrayidx, align 1 ret i1 %0 } -define zeroext i1 @load_R_bit_(i1* nocapture readonly %a, i32 %b) local_unnamed_addr #0 { +define zeroext i1 @load_R_bit_(ptr nocapture readonly %a, i32 %b) local_unnamed_addr #0 { ; CHECK-LABEL: load_R_bit_: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ldr32.b a0, (a0, a1 << 0) @@ -232,13 +232,13 @@ define zeroext i1 @load_R_bit_(i1* nocapture readonly %a, i32 %b) local_unnamed_ ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i1, i1* %a, i64 %idxprom - %0 = load i1, i1* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i1, ptr %a, i64 %idxprom + %0 = load i1, ptr %arrayidx, align 1 ret i1 %0 } -define signext i8 @load_R_bs(i8* nocapture readonly %a, i32 %b) local_unnamed_addr #0 { +define signext i8 @load_R_bs(ptr nocapture readonly %a, i32 %b) local_unnamed_addr #0 { ; CHECK-LABEL: load_R_bs: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ldr32.bs a0, (a0, a1 << 0) @@ -256,12 +256,12 @@ define signext i8 @load_R_bs(i8* nocapture readonly %a, i32 %b) local_unnamed_ad ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i8, i8* %a, i64 %idxprom - %0 = load i8, i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, ptr %a, i64 %idxprom + %0 = load i8, ptr %arrayidx, align 1 ret i8 %0 } -define zeroext i8 @load_R_b_(i8* nocapture readonly %a, i32 %b) local_unnamed_addr #0 { +define zeroext i8 @load_R_b_(ptr nocapture readonly %a, i32 %b) local_unnamed_addr #0 { ; CHECK-LABEL: load_R_b_: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ldr32.b a0, (a0, a1 << 0) @@ -278,12 +278,12 @@ define zeroext i8 @load_R_b_(i8* nocapture readonly %a, i32 %b) local_unnamed_ad ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i8, i8* %a, i64 %idxprom - %0 = load i8, i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, ptr %a, i64 %idxprom + %0 = load i8, ptr %arrayidx, align 1 ret i8 %0 } -define signext i16 @load_R_hs(i16* nocapture readonly %a, i32 %b) local_unnamed_addr #0 { +define signext i16 @load_R_hs(ptr nocapture readonly %a, i32 %b) local_unnamed_addr #0 { ; CHECK-LABEL: load_R_hs: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ldr32.hs a0, (a0, a1 << 1) @@ -302,12 +302,12 @@ define signext i16 @load_R_hs(i16* nocapture readonly %a, i32 %b) local_unnamed_ ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i16, i16* %a, i64 %idxprom - %0 = load i16, i16* %arrayidx, align 2 + %arrayidx = getelementptr inbounds i16, ptr %a, i64 %idxprom + %0 = load i16, ptr %arrayidx, align 2 ret i16 %0 } -define zeroext i16 @load_R_h_(i16* nocapture readonly %a, i32 %b) local_unnamed_addr #0 { +define zeroext i16 @load_R_h_(ptr nocapture readonly %a, i32 %b) local_unnamed_addr #0 { ; CHECK-LABEL: load_R_h_: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ldr32.h a0, (a0, a1 << 1) @@ -325,12 +325,12 @@ define zeroext i16 @load_R_h_(i16* nocapture readonly %a, i32 %b) local_unnamed_ ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i16, i16* %a, i64 %idxprom - %0 = load i16, i16* %arrayidx, align 2 + %arrayidx = getelementptr inbounds i16, ptr %a, i64 %idxprom + %0 = load i16, ptr %arrayidx, align 2 ret i16 %0 } -define i32 @load_R_w(i32* nocapture readonly %a, i32 %b) local_unnamed_addr #0 { +define i32 @load_R_w(ptr nocapture readonly %a, i32 %b) local_unnamed_addr #0 { ; CHECK-LABEL: load_R_w: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ldr32.w a0, (a0, a1 << 2) @@ -348,12 +348,12 @@ define i32 @load_R_w(i32* nocapture readonly %a, i32 %b) local_unnamed_addr #0 { ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i32, i32* %a, i64 %idxprom - %0 = load i32, i32* %arrayidx, align 4 + %arrayidx = getelementptr inbounds i32, ptr %a, i64 %idxprom + %0 = load i32, ptr %arrayidx, align 4 ret i32 %0 } -define i64 @load_R_d(i64* nocapture readonly %a, i32 %b) local_unnamed_addr #0 { +define i64 @load_R_d(ptr nocapture readonly %a, i32 %b) local_unnamed_addr #0 { ; CHECK-LABEL: load_R_d: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ixd32 a2, a0, a1 @@ -374,12 +374,12 @@ define i64 @load_R_d(i64* nocapture readonly %a, i32 %b) local_unnamed_addr #0 { ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i64, i64* %a, i64 %idxprom - %0 = load i64, i64* %arrayidx, align 4 + %arrayidx = getelementptr inbounds i64, ptr %a, i64 %idxprom + %0 = load i64, ptr %arrayidx, align 4 ret i64 %0 } -define i8 @loadR_i8_anyext(i8* %c, i32 %a) { +define i8 @loadR_i8_anyext(ptr %c, i32 %a) { ; CHECK-LABEL: loadR_i8_anyext: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ldr32.bs a0, (a0, a1 << 0) @@ -396,12 +396,12 @@ define i8 @loadR_i8_anyext(i8* %c, i32 %a) { ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %a to i64 - %arrayidx = getelementptr inbounds i8, i8* %c, i64 %idxprom - %0 = load i8, i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, ptr %c, i64 %idxprom + %0 = load i8, ptr %arrayidx, align 1 ret i8 %0 } -define signext i1 @store_I_bits(i1* %a, i1 %b) local_unnamed_addr #0 { +define signext i1 @store_I_bits(ptr %a, i1 %b) local_unnamed_addr #0 { ; CHECK-LABEL: store_I_bits: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: andi32 a1, a1, 1 @@ -421,12 +421,12 @@ define signext i1 @store_I_bits(i1* %a, i1 %b) local_unnamed_addr #0 { ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i1, i1* %a, i64 3 - store i1 %b, i1* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i1, ptr %a, i64 3 + store i1 %b, ptr %arrayidx, align 1 ret i1 0 } -define zeroext i1 @store_I_bit_(i1* %a, i1 %b) local_unnamed_addr #0 { +define zeroext i1 @store_I_bit_(ptr %a, i1 %b) local_unnamed_addr #0 { ; CHECK-LABEL: store_I_bit_: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: andi32 a1, a1, 1 @@ -446,12 +446,12 @@ define zeroext i1 @store_I_bit_(i1* %a, i1 %b) local_unnamed_addr #0 { ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i1, i1* %a, i64 3 - store i1 %b, i1* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i1, ptr %a, i64 3 + store i1 %b, ptr %arrayidx, align 1 ret i1 0 } -define signext i8 @store_I_bs(i8* %a, i8 %b) local_unnamed_addr #0 { +define signext i8 @store_I_bs(ptr %a, i8 %b) local_unnamed_addr #0 { ; CHECK-LABEL: store_I_bs: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: st16.b a1, (a0, 3) @@ -468,12 +468,12 @@ define signext i8 @store_I_bs(i8* %a, i8 %b) local_unnamed_addr #0 { ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i8, i8* %a, i64 3 - store i8 %b, i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, ptr %a, i64 3 + store i8 %b, ptr %arrayidx, align 1 ret i8 0 } -define zeroext i8 @store_I_b_(i8* %a, i8 %b) local_unnamed_addr #0 { +define zeroext i8 @store_I_b_(ptr %a, i8 %b) local_unnamed_addr #0 { ; CHECK-LABEL: store_I_b_: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: st16.b a1, (a0, 3) @@ -490,12 +490,12 @@ define zeroext i8 @store_I_b_(i8* %a, i8 %b) local_unnamed_addr #0 { ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i8, i8* %a, i64 3 - store i8 %b, i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, ptr %a, i64 3 + store i8 %b, ptr %arrayidx, align 1 ret i8 0 } -define signext i16 @store_I_hs(i16* %a, i16 %b) local_unnamed_addr #0 { +define signext i16 @store_I_hs(ptr %a, i16 %b) local_unnamed_addr #0 { ; CHECK-LABEL: store_I_hs: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: st16.h a1, (a0, 6) @@ -512,12 +512,12 @@ define signext i16 @store_I_hs(i16* %a, i16 %b) local_unnamed_addr #0 { ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i16, i16* %a, i64 3 - store i16 %b, i16* %arrayidx, align 2 + %arrayidx = getelementptr inbounds i16, ptr %a, i64 3 + store i16 %b, ptr %arrayidx, align 2 ret i16 0 } -define zeroext i16 @store_I_h_(i16* %a, i16 %b) local_unnamed_addr #0 { +define zeroext i16 @store_I_h_(ptr %a, i16 %b) local_unnamed_addr #0 { ; CHECK-LABEL: store_I_h_: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: st16.h a1, (a0, 6) @@ -534,12 +534,12 @@ define zeroext i16 @store_I_h_(i16* %a, i16 %b) local_unnamed_addr #0 { ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i16, i16* %a, i64 3 - store i16 %b, i16* %arrayidx, align 2 + %arrayidx = getelementptr inbounds i16, ptr %a, i64 3 + store i16 %b, ptr %arrayidx, align 2 ret i16 0 } -define i32 @store_I_w(i32* %a, i32 %b) local_unnamed_addr #0 { +define i32 @store_I_w(ptr %a, i32 %b) local_unnamed_addr #0 { ; CHECK-LABEL: store_I_w: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: st16.w a1, (a0, 12) @@ -556,12 +556,12 @@ define i32 @store_I_w(i32* %a, i32 %b) local_unnamed_addr #0 { ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i32, i32* %a, i64 3 - store i32 %b, i32* %arrayidx, align 4 + %arrayidx = getelementptr inbounds i32, ptr %a, i64 3 + store i32 %b, ptr %arrayidx, align 4 ret i32 0 } -define i64 @store_I_d(i64* %a, i64 %b) local_unnamed_addr #0 { +define i64 @store_I_d(ptr %a, i64 %b) local_unnamed_addr #0 { ; CHECK-LABEL: store_I_d: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: st16.w a2, (a0, 28) @@ -582,12 +582,12 @@ define i64 @store_I_d(i64* %a, i64 %b) local_unnamed_addr #0 { ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i64, i64* %a, i64 3 - store i64 %b, i64* %arrayidx, align 4 + %arrayidx = getelementptr inbounds i64, ptr %a, i64 3 + store i64 %b, ptr %arrayidx, align 4 ret i64 0 } -define i8 @store_I_i8_anyext(i8* %p, i8 %b) { +define i8 @store_I_i8_anyext(ptr %p, i8 %b) { ; CHECK-LABEL: store_I_i8_anyext: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: st16.b a1, (a0, 0) @@ -604,11 +604,11 @@ define i8 @store_I_i8_anyext(i8* %p, i8 %b) { ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - store i8 %b, i8* %p, align 1 + store i8 %b, ptr %p, align 1 ret i8 0 } -define signext i1 @store_R_bits(i1* %a, i32 %b, i1 %c) local_unnamed_addr #0 { +define signext i1 @store_R_bits(ptr %a, i32 %b, i1 %c) local_unnamed_addr #0 { ; CHECK-LABEL: store_R_bits: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: andi32 a2, a2, 1 @@ -630,12 +630,12 @@ define signext i1 @store_R_bits(i1* %a, i32 %b, i1 %c) local_unnamed_addr #0 { ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i1, i1* %a, i64 %idxprom - store i1 %c, i1* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i1, ptr %a, i64 %idxprom + store i1 %c, ptr %arrayidx, align 1 ret i1 0 } -define zeroext i1 @store_R_bit_(i1* %a, i32 %b, i1 %c) local_unnamed_addr #0 { +define zeroext i1 @store_R_bit_(ptr %a, i32 %b, i1 %c) local_unnamed_addr #0 { ; CHECK-LABEL: store_R_bit_: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: andi32 a2, a2, 1 @@ -657,13 +657,13 @@ define zeroext i1 @store_R_bit_(i1* %a, i32 %b, i1 %c) local_unnamed_addr #0 { ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i1, i1* %a, i64 %idxprom - store i1 %c, i1* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i1, ptr %a, i64 %idxprom + store i1 %c, ptr %arrayidx, align 1 ret i1 0 } -define signext i8 @store_R_bs(i8* %a, i32 %b, i8 %c) local_unnamed_addr #0 { +define signext i8 @store_R_bs(ptr %a, i32 %b, i8 %c) local_unnamed_addr #0 { ; CHECK-LABEL: store_R_bs: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: str32.b a2, (a0, a1 << 0) @@ -682,12 +682,12 @@ define signext i8 @store_R_bs(i8* %a, i32 %b, i8 %c) local_unnamed_addr #0 { ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i8, i8* %a, i64 %idxprom - store i8 %c, i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, ptr %a, i64 %idxprom + store i8 %c, ptr %arrayidx, align 1 ret i8 0 } -define zeroext i8 @store_R_b_(i8* %a, i32 %b, i8 %c) local_unnamed_addr #0 { +define zeroext i8 @store_R_b_(ptr %a, i32 %b, i8 %c) local_unnamed_addr #0 { ; CHECK-LABEL: store_R_b_: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: str32.b a2, (a0, a1 << 0) @@ -706,12 +706,12 @@ define zeroext i8 @store_R_b_(i8* %a, i32 %b, i8 %c) local_unnamed_addr #0 { ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i8, i8* %a, i64 %idxprom - store i8 %c, i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, ptr %a, i64 %idxprom + store i8 %c, ptr %arrayidx, align 1 ret i8 0 } -define signext i16 @store_R_hs(i16* %a, i32 %b, i16 %c) local_unnamed_addr #0 { +define signext i16 @store_R_hs(ptr %a, i32 %b, i16 %c) local_unnamed_addr #0 { ; CHECK-LABEL: store_R_hs: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: str32.h a2, (a0, a1 << 1) @@ -731,12 +731,12 @@ define signext i16 @store_R_hs(i16* %a, i32 %b, i16 %c) local_unnamed_addr #0 { ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i16, i16* %a, i64 %idxprom - store i16 %c, i16* %arrayidx, align 2 + %arrayidx = getelementptr inbounds i16, ptr %a, i64 %idxprom + store i16 %c, ptr %arrayidx, align 2 ret i16 0 } -define zeroext i16 @store_R_h_(i16* %a, i32 %b, i16 %c) local_unnamed_addr #0 { +define zeroext i16 @store_R_h_(ptr %a, i32 %b, i16 %c) local_unnamed_addr #0 { ; CHECK-LABEL: store_R_h_: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: str32.h a2, (a0, a1 << 1) @@ -756,12 +756,12 @@ define zeroext i16 @store_R_h_(i16* %a, i32 %b, i16 %c) local_unnamed_addr #0 { ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i16, i16* %a, i64 %idxprom - store i16 %c, i16* %arrayidx, align 2 + %arrayidx = getelementptr inbounds i16, ptr %a, i64 %idxprom + store i16 %c, ptr %arrayidx, align 2 ret i16 0 } -define i32 @store_R_w(i32* %a, i32 %b, i32 %c) local_unnamed_addr #0 { +define i32 @store_R_w(ptr %a, i32 %b, i32 %c) local_unnamed_addr #0 { ; CHECK-LABEL: store_R_w: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: str32.w a2, (a0, a1 << 2) @@ -781,12 +781,12 @@ define i32 @store_R_w(i32* %a, i32 %b, i32 %c) local_unnamed_addr #0 { ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i32, i32* %a, i64 %idxprom - store i32 %c, i32* %arrayidx, align 4 + %arrayidx = getelementptr inbounds i32, ptr %a, i64 %idxprom + store i32 %c, ptr %arrayidx, align 4 ret i32 0 } -define i64 @store_R_d(i64* %a, i32 %b, i64 %c) local_unnamed_addr #0 { +define i64 @store_R_d(ptr %a, i32 %b, i64 %c) local_unnamed_addr #0 { ; CHECK-LABEL: store_R_d: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ixd32 t0, a0, a1 @@ -811,12 +811,12 @@ define i64 @store_R_d(i64* %a, i32 %b, i64 %c) local_unnamed_addr #0 { ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i64, i64* %a, i64 %idxprom - store i64 %c, i64* %arrayidx, align 4 + %arrayidx = getelementptr inbounds i64, ptr %a, i64 %idxprom + store i64 %c, ptr %arrayidx, align 4 ret i64 0 } -define i8 @storeR_i8_anyext(i8* %c, i32 %a, i8 %d) { +define i8 @storeR_i8_anyext(ptr %c, i32 %a, i8 %d) { ; CHECK-LABEL: storeR_i8_anyext: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: str32.b a2, (a0, a1 << 0) @@ -835,7 +835,7 @@ define i8 @storeR_i8_anyext(i8* %c, i32 %a, i8 %d) { ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %a to i64 - %arrayidx = getelementptr inbounds i8, i8* %c, i64 %idxprom - store i8 %d, i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, ptr %c, i64 %idxprom + store i8 %d, ptr %arrayidx, align 1 ret i8 0 } diff --git a/llvm/test/CodeGen/CSKY/tls-models.ll b/llvm/test/CodeGen/CSKY/tls-models.ll index 35dca36f515b..d520e247c9a3 100644 --- a/llvm/test/CodeGen/CSKY/tls-models.ll +++ b/llvm/test/CodeGen/CSKY/tls-models.ll @@ -15,7 +15,7 @@ ; No model specified -define i32* @f1() nounwind { +define ptr @f1() nounwind { ; CSKY-PIC-LABEL: f1: ; CSKY-PIC: # %bb.0: # %entry ; CSKY-PIC-NEXT: subi16 sp, sp, 8 @@ -59,13 +59,13 @@ define i32* @f1() nounwind { ; CSKY-NOPIC-NEXT: .Ltmp0: ; CSKY-NOPIC-NEXT: .long unspecified-(.LPC0_1-.Ltmp0)@GOTTPOFF entry: - ret i32* @unspecified + ret ptr @unspecified } ; localdynamic specified -define i32* @f2() nounwind { +define ptr @f2() nounwind { ; CSKY-PIC-LABEL: f2: ; CSKY-PIC: # %bb.0: # %entry ; CSKY-PIC-NEXT: subi16 sp, sp, 8 @@ -109,13 +109,13 @@ define i32* @f2() nounwind { ; CSKY-NOPIC-NEXT: .Ltmp1: ; CSKY-NOPIC-NEXT: .long ld-(.LPC1_1-.Ltmp1)@GOTTPOFF entry: - ret i32* @ld + ret ptr @ld } ; initialexec specified -define i32* @f3() nounwind { +define ptr @f3() nounwind { ; CSKY-PIC-LABEL: f3: ; CSKY-PIC: # %bb.0: # %entry ; CSKY-PIC-NEXT: .LPC2_1: @@ -146,13 +146,13 @@ define i32* @f3() nounwind { ; CSKY-NOPIC-NEXT: .Ltmp2: ; CSKY-NOPIC-NEXT: .long ie-(.LPC2_1-.Ltmp2)@GOTTPOFF entry: - ret i32* @ie + ret ptr @ie } ; localexec specified -define i32* @f4() nounwind { +define ptr @f4() nounwind { ; CSKY-PIC-LABEL: f4: ; CSKY-PIC: # %bb.0: # %entry ; CSKY-PIC-NEXT: lrw32 a0, [.LCPI3_0] @@ -175,5 +175,5 @@ define i32* @f4() nounwind { ; CSKY-NOPIC-NEXT: .LCPI3_0: ; CSKY-NOPIC-NEXT: .long le@TPOFF entry: - ret i32* @le + ret ptr @le } -- GitLab From 1c22d3f55df852985c155742bbe96ab5e86aa6f0 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Tue, 6 Feb 2024 12:55:15 -0800 Subject: [PATCH 123/266] [ARC] Convert tests to opaque pointers (NFC) --- llvm/test/CodeGen/ARC/addrmode.ll | 38 ++++----- llvm/test/CodeGen/ARC/call.ll | 4 +- llvm/test/CodeGen/ARC/ldst.ll | 132 +++++++++++++++--------------- 3 files changed, 87 insertions(+), 87 deletions(-) diff --git a/llvm/test/CodeGen/ARC/addrmode.ll b/llvm/test/CodeGen/ARC/addrmode.ll index 8ca3749025e9..248ec7d4238f 100644 --- a/llvm/test/CodeGen/ARC/addrmode.ll +++ b/llvm/test/CodeGen/ARC/addrmode.ll @@ -2,17 +2,17 @@ ; CHECK-LABEL: copy ; CHECK-NOT: add -define void @copy(i8* inreg nocapture %p, i8* inreg nocapture readonly %q) { +define void @copy(ptr inreg nocapture %p, ptr inreg nocapture readonly %q) { entry: br label %while.cond while.cond: ; preds = %while.cond, %entry - %p.addr.0 = phi i8* [ %p, %entry ], [ %incdec.ptr1, %while.cond ] - %q.addr.0 = phi i8* [ %q, %entry ], [ %incdec.ptr, %while.cond ] - %incdec.ptr = getelementptr inbounds i8, i8* %q.addr.0, i32 1 - %0 = load i8, i8* %q.addr.0, align 1 - %incdec.ptr1 = getelementptr inbounds i8, i8* %p.addr.0, i32 1 - store i8 %0, i8* %p.addr.0, align 1 + %p.addr.0 = phi ptr [ %p, %entry ], [ %incdec.ptr1, %while.cond ] + %q.addr.0 = phi ptr [ %q, %entry ], [ %incdec.ptr, %while.cond ] + %incdec.ptr = getelementptr inbounds i8, ptr %q.addr.0, i32 1 + %0 = load i8, ptr %q.addr.0, align 1 + %incdec.ptr1 = getelementptr inbounds i8, ptr %p.addr.0, i32 1 + store i8 %0, ptr %p.addr.0, align 1 %tobool = icmp eq i8 %0, 0 br i1 %tobool, label %while.end, label %while.cond @@ -21,11 +21,11 @@ while.end: ; preds = %while.cond } -%struct._llist = type { %struct._llist*, %struct._llist*, i32 } +%struct._llist = type { ptr, ptr, i32 } ; CHECK-LABEL: neg1 ; CHECK-NOT: std.ab -define void @neg1(i8* inreg nocapture %a, i8* inreg nocapture readonly %b, i32 inreg %n) { +define void @neg1(ptr inreg nocapture %a, ptr inreg nocapture readonly %b, i32 inreg %n) { entry: %cmp6 = icmp sgt i32 %n, 0 br i1 %cmp6, label %for.body, label %for.cond.cleanup @@ -35,11 +35,11 @@ for.cond.cleanup: for.body: %i.07 = phi i32 [ %inc, %for.body ], [ 0, %entry ] - %arrayidx = getelementptr inbounds i8, i8* %b, i32 %i.07 - %0 = load i8, i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, ptr %b, i32 %i.07 + %0 = load i8, ptr %arrayidx, align 1 %mul = mul nuw nsw i32 %i.07, 257 - %arrayidx1 = getelementptr inbounds i8, i8* %a, i32 %mul - store i8 %0, i8* %arrayidx1, align 1 + %arrayidx1 = getelementptr inbounds i8, ptr %a, i32 %mul + store i8 %0, ptr %arrayidx1, align 1 %inc = add nuw nsw i32 %i.07, 1 %exitcond = icmp eq i32 %inc, %n br i1 %exitcond, label %for.cond.cleanup, label %for.body @@ -47,7 +47,7 @@ for.body: ; CHECK-LABEL: neg2 ; CHECK-NOT: st.ab -define void @neg2(%struct._llist* inreg %a, i32 inreg %n) { +define void @neg2(ptr inreg %a, i32 inreg %n) { entry: %cmp13 = icmp sgt i32 %n, 0 br i1 %cmp13, label %for.body, label %for.cond.cleanup @@ -57,11 +57,11 @@ for.cond.cleanup: for.body: %i.014 = phi i32 [ %inc, %for.body ], [ 0, %entry ] - %arrayidx = getelementptr inbounds %struct._llist, %struct._llist* %a, i32 %i.014 - %next = getelementptr inbounds %struct._llist, %struct._llist* %arrayidx, i32 0, i32 0 - store %struct._llist* %arrayidx, %struct._llist** %next, align 4 - %prev = getelementptr inbounds %struct._llist, %struct._llist* %a, i32 %i.014, i32 1 - store %struct._llist* %arrayidx, %struct._llist** %prev, align 4 + %arrayidx = getelementptr inbounds %struct._llist, ptr %a, i32 %i.014 + %next = getelementptr inbounds %struct._llist, ptr %arrayidx, i32 0, i32 0 + store ptr %arrayidx, ptr %next, align 4 + %prev = getelementptr inbounds %struct._llist, ptr %a, i32 %i.014, i32 1 + store ptr %arrayidx, ptr %prev, align 4 %inc = add nuw nsw i32 %i.014, 1 %exitcond = icmp eq i32 %inc, %n br i1 %exitcond, label %for.cond.cleanup, label %for.body diff --git a/llvm/test/CodeGen/ARC/call.ll b/llvm/test/CodeGen/ARC/call.ll index 2985439b5f10..d74b35a35f65 100644 --- a/llvm/test/CodeGen/ARC/call.ll +++ b/llvm/test/CodeGen/ARC/call.ll @@ -73,14 +73,14 @@ define i64 @ret1() nounwind { ret i64 281470698455295 } -@funcptr = external global i32 (i32)*, align 4 +@funcptr = external global ptr, align 4 ; Indirect calls use JL ; CHECK-LABEL: call_indirect ; CHECK-DAG: ld %r[[REG:[0-9]+]], [@funcptr] ; CHECK-DAG: mov %r0, 12 ; CHECK: jl [%r[[REG]]] define i32 @call_indirect(i32 %x) nounwind { - %f = load i32 (i32)*, i32 (i32)** @funcptr, align 4 + %f = load ptr, ptr @funcptr, align 4 %call = call i32 %f(i32 12) %add = add nsw i32 %call, %x ret i32 %add diff --git a/llvm/test/CodeGen/ARC/ldst.ll b/llvm/test/CodeGen/ARC/ldst.ll index dd1529875a66..99b43de71cb4 100644 --- a/llvm/test/CodeGen/ARC/ldst.ll +++ b/llvm/test/CodeGen/ARC/ldst.ll @@ -3,40 +3,40 @@ ; CHECK-LABEL: load32 ; CHECK: ld %r0, [%r0,16000] -define i32 @load32(i32* %bp) nounwind { +define i32 @load32(ptr %bp) nounwind { entry: - %gep = getelementptr i32, i32* %bp, i32 4000 - %v = load i32, i32* %gep, align 4 + %gep = getelementptr i32, ptr %bp, i32 4000 + %v = load i32, ptr %gep, align 4 ret i32 %v } ; CHECK-LABEL: load16 ; CHECK: ldh %r0, [%r0,8000] -define i16 @load16(i16* %bp) nounwind { +define i16 @load16(ptr %bp) nounwind { entry: - %gep = getelementptr i16, i16* %bp, i32 4000 - %v = load i16, i16* %gep, align 2 + %gep = getelementptr i16, ptr %bp, i32 4000 + %v = load i16, ptr %gep, align 2 ret i16 %v } ; CHECK-LABEL: load8 ; CHECK: ldb %r0, [%r0,4000] -define i8 @load8(i8* %bp) nounwind { +define i8 @load8(ptr %bp) nounwind { entry: - %gep = getelementptr i8, i8* %bp, i32 4000 - %v = load i8, i8* %gep, align 1 + %gep = getelementptr i8, ptr %bp, i32 4000 + %v = load i8, ptr %gep, align 1 ret i8 %v } ; CHECK-LABEL: sextload16 ; CHECK: ldh.x %r0, [%r0,8000] -define i32 @sextload16(i16* %bp) nounwind { +define i32 @sextload16(ptr %bp) nounwind { entry: - %gep = getelementptr i16, i16* %bp, i32 4000 - %vl = load i16, i16* %gep, align 2 + %gep = getelementptr i16, ptr %bp, i32 4000 + %vl = load i16, ptr %gep, align 2 %v = sext i16 %vl to i32 ret i32 %v } @@ -44,10 +44,10 @@ entry: ; CHECK-LABEL: sextload8 ; CHECK: ldb.x %r0, [%r0,4000] -define i32 @sextload8(i8* %bp) nounwind { +define i32 @sextload8(ptr %bp) nounwind { entry: - %gep = getelementptr i8, i8* %bp, i32 4000 - %vl = load i8, i8* %gep, align 1 + %gep = getelementptr i8, ptr %bp, i32 4000 + %vl = load i8, ptr %gep, align 1 %v = sext i8 %vl to i32 ret i32 %v } @@ -55,10 +55,10 @@ entry: ; CHECK-LABEL: s_sextload16 ; CHECK: ldh.x %r0, [%r0,32] -define i32 @s_sextload16(i16* %bp) nounwind { +define i32 @s_sextload16(ptr %bp) nounwind { entry: - %gep = getelementptr i16, i16* %bp, i32 16 - %vl = load i16, i16* %gep, align 2 + %gep = getelementptr i16, ptr %bp, i32 16 + %vl = load i16, ptr %gep, align 2 %v = sext i16 %vl to i32 ret i32 %v } @@ -66,10 +66,10 @@ entry: ; CHECK-LABEL: s_sextload8 ; CHECK: ldb.x %r0, [%r0,16] -define i32 @s_sextload8(i8* %bp) nounwind { +define i32 @s_sextload8(ptr %bp) nounwind { entry: - %gep = getelementptr i8, i8* %bp, i32 16 - %vl = load i8, i8* %gep, align 1 + %gep = getelementptr i8, ptr %bp, i32 16 + %vl = load i8, ptr %gep, align 1 %v = sext i8 %vl to i32 ret i32 %v } @@ -79,10 +79,10 @@ entry: ; CHECK: st %r0, [%r[[REG]],0] ; Long range stores (offset does not fit in s9) must be add followed by st. -define void @store32(i32 %val, i32* %bp) nounwind { +define void @store32(i32 %val, ptr %bp) nounwind { entry: - %gep = getelementptr i32, i32* %bp, i32 4000 - store i32 %val, i32* %gep, align 4 + %gep = getelementptr i32, ptr %bp, i32 4000 + store i32 %val, ptr %gep, align 4 ret void } @@ -90,10 +90,10 @@ entry: ; CHECK: add %r[[REG:[0-9]+]], %r1, 8000 ; CHECK: sth %r0, [%r[[REG]],0] -define void @store16(i16 zeroext %val, i16* %bp) nounwind { +define void @store16(i16 zeroext %val, ptr %bp) nounwind { entry: - %gep = getelementptr i16, i16* %bp, i32 4000 - store i16 %val, i16* %gep, align 2 + %gep = getelementptr i16, ptr %bp, i32 4000 + store i16 %val, ptr %gep, align 2 ret void } @@ -101,10 +101,10 @@ entry: ; CHECK: add %r[[REG:[0-9]+]], %r1, 4000 ; CHECK: stb %r0, [%r[[REG]],0] -define void @store8(i8 zeroext %val, i8* %bp) nounwind { +define void @store8(i8 zeroext %val, ptr %bp) nounwind { entry: - %gep = getelementptr i8, i8* %bp, i32 4000 - store i8 %val, i8* %gep, align 1 + %gep = getelementptr i8, ptr %bp, i32 4000 + store i8 %val, ptr %gep, align 1 ret void } @@ -112,30 +112,30 @@ entry: ; CHECK-LABEL: s_store32 ; CHECK-NOT: add ; CHECK: st %r0, [%r1,64] -define void @s_store32(i32 %val, i32* %bp) nounwind { +define void @s_store32(i32 %val, ptr %bp) nounwind { entry: - %gep = getelementptr i32, i32* %bp, i32 16 - store i32 %val, i32* %gep, align 4 + %gep = getelementptr i32, ptr %bp, i32 16 + store i32 %val, ptr %gep, align 4 ret void } ; CHECK-LABEL: s_store16 ; CHECK-NOT: add ; CHECK: sth %r0, [%r1,32] -define void @s_store16(i16 zeroext %val, i16* %bp) nounwind { +define void @s_store16(i16 zeroext %val, ptr %bp) nounwind { entry: - %gep = getelementptr i16, i16* %bp, i32 16 - store i16 %val, i16* %gep, align 2 + %gep = getelementptr i16, ptr %bp, i32 16 + store i16 %val, ptr %gep, align 2 ret void } ; CHECK-LABEL: s_store8 ; CHECK-NOT: add ; CHECK: stb %r0, [%r1,16] -define void @s_store8(i8 zeroext %val, i8* %bp) nounwind { +define void @s_store8(i8 zeroext %val, ptr %bp) nounwind { entry: - %gep = getelementptr i8, i8* %bp, i32 16 - store i8 %val, i8* %gep, align 1 + %gep = getelementptr i8, ptr %bp, i32 16 + store i8 %val, ptr %gep, align 1 ret void } @@ -149,7 +149,7 @@ entry: ; CHECK: st %r0, [@aaaa+64] define void @g_store32(i32 %val) nounwind { entry: - store i32 %val, i32* getelementptr inbounds ([128 x i32], [128 x i32]* @aaaa, i32 0, i32 16), align 4 + store i32 %val, ptr getelementptr inbounds ([128 x i32], ptr @aaaa, i32 0, i32 16), align 4 ret void } @@ -157,8 +157,8 @@ entry: ; CHECK-NOT: add ; CHECK: ld %r0, [@aaaa+64] define i32 @g_load32() nounwind { - %gep = getelementptr inbounds [128 x i32], [128 x i32]* @aaaa, i32 0, i32 16 - %v = load i32, i32* %gep, align 4 + %gep = getelementptr inbounds [128 x i32], ptr @aaaa, i32 0, i32 16 + %v = load i32, ptr %gep, align 4 ret i32 %v } @@ -167,7 +167,7 @@ define i32 @g_load32() nounwind { ; CHECK: sth %r0, [@bbbb+32] define void @g_store16(i16 %val) nounwind { entry: - store i16 %val, i16* getelementptr inbounds ([128 x i16], [128 x i16]* @bbbb, i16 0, i16 16), align 2 + store i16 %val, ptr getelementptr inbounds ([128 x i16], ptr @bbbb, i16 0, i16 16), align 2 ret void } @@ -175,8 +175,8 @@ entry: ; CHECK-NOT: add ; CHECK: ldh %r0, [@bbbb+32] define i16 @g_load16() nounwind { - %gep = getelementptr inbounds [128 x i16], [128 x i16]* @bbbb, i16 0, i16 16 - %v = load i16, i16* %gep, align 2 + %gep = getelementptr inbounds [128 x i16], ptr @bbbb, i16 0, i16 16 + %v = load i16, ptr %gep, align 2 ret i16 %v } @@ -185,7 +185,7 @@ define i16 @g_load16() nounwind { ; CHECK: stb %r0, [@cccc+16] define void @g_store8(i8 %val) nounwind { entry: - store i8 %val, i8* getelementptr inbounds ([128 x i8], [128 x i8]* @cccc, i8 0, i8 16), align 1 + store i8 %val, ptr getelementptr inbounds ([128 x i8], ptr @cccc, i8 0, i8 16), align 1 ret void } @@ -193,8 +193,8 @@ entry: ; CHECK-NOT: add ; CHECK: ldb %r0, [@cccc+16] define i8 @g_load8() nounwind { - %gep = getelementptr inbounds [128 x i8], [128 x i8]* @cccc, i8 0, i8 16 - %v = load i8, i8* %gep, align 1 + %gep = getelementptr inbounds [128 x i8], ptr @cccc, i8 0, i8 16 + %v = load i8, ptr %gep, align 1 ret i8 %v } @@ -202,10 +202,10 @@ define i8 @g_load8() nounwind { ; CHECK-DAG: ldh %r[[REG0:[0-9]+]], [%r0,0] ; CHECK-DAG: ldh %r[[REG1:[0-9]+]], [%r0,2] ; CHECK-DAG: asl %r[[REG2:[0-9]+]], %r[[REG1]], 16 -define i32 @align2_load32(i8* %p) nounwind { +define i32 @align2_load32(ptr %p) nounwind { entry: - %bp = bitcast i8* %p to i32* - %v = load i32, i32* %bp, align 2 + %bp = bitcast ptr %p to ptr + %v = load i32, ptr %bp, align 2 ret i32 %v } @@ -220,10 +220,10 @@ entry: ; CHECK-DAG: or %r[[AREG01:[0-9]+]], %r[[AREG1]], %r[[REG0]] ; CHECK-DAG: or %r[[AREG23:[0-9]+]], %r[[AREG3]], %r[[AREG2]] ; CHECK-DAG: or %r0, %r[[AREG23]], %r[[AREG01]] -define i32 @align1_load32(i8* %p) nounwind { +define i32 @align1_load32(ptr %p) nounwind { entry: - %bp = bitcast i8* %p to i32* - %v = load i32, i32* %bp, align 1 + %bp = bitcast ptr %p to ptr + %v = load i32, ptr %bp, align 1 ret i32 %v } @@ -231,10 +231,10 @@ entry: ; CHECK-DAG: ldb %r[[REG0:[0-9]+]], [%r0,0] ; CHECK-DAG: ldb %r[[REG1:[0-9]+]], [%r0,1] ; CHECK-DAG: asl %r[[REG2:[0-9]+]], %r[[REG1]], 8 -define i16 @align1_load16(i8* %p) nounwind { +define i16 @align1_load16(ptr %p) nounwind { entry: - %bp = bitcast i8* %p to i16* - %v = load i16, i16* %bp, align 1 + %bp = bitcast ptr %p to ptr + %v = load i16, ptr %bp, align 1 ret i16 %v } @@ -242,10 +242,10 @@ entry: ; CHECK-DAG: lsr %r[[REG:[0-9]+]], %r1, 16 ; CHECK-DAG: sth %r1, [%r0,0] ; CHECK-DAG: sth %r[[REG:[0-9]+]], [%r0,2] -define void @align2_store32(i8* %p, i32 %v) nounwind { +define void @align2_store32(ptr %p, i32 %v) nounwind { entry: - %bp = bitcast i8* %p to i32* - store i32 %v, i32* %bp, align 2 + %bp = bitcast ptr %p to ptr + store i32 %v, ptr %bp, align 2 ret void } @@ -253,10 +253,10 @@ entry: ; CHECK-DAG: lsr %r[[REG:[0-9]+]], %r1, 8 ; CHECK-DAG: stb %r1, [%r0,0] ; CHECK-DAG: stb %r[[REG:[0-9]+]], [%r0,1] -define void @align1_store16(i8* %p, i16 %v) nounwind { +define void @align1_store16(ptr %p, i16 %v) nounwind { entry: - %bp = bitcast i8* %p to i16* - store i16 %v, i16* %bp, align 1 + %bp = bitcast ptr %p to ptr + store i16 %v, ptr %bp, align 1 ret void } @@ -268,9 +268,9 @@ entry: ; CHECK-DAG: stb %r[[REG0]], [%r0,1] ; CHECK-DAG: stb %r[[REG1]], [%r0,2] ; CHECK-DAG: stb %r[[REG2]], [%r0,3] -define void @align1_store32(i8* %p, i32 %v) nounwind { +define void @align1_store32(ptr %p, i32 %v) nounwind { entry: - %bp = bitcast i8* %p to i32* - store i32 %v, i32* %bp, align 1 + %bp = bitcast ptr %p to ptr + store i32 %v, ptr %bp, align 1 ret void } -- GitLab From 92b33822e989884d29465d34769b07d78aeb1a84 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Tue, 6 Feb 2024 12:59:49 -0800 Subject: [PATCH 124/266] [DebugInfo/MIR] Convert tests to opaque pointers (NFC) Link: https://discourse.llvm.org/t/enabling-opaque-pointers-by-default/61322 --- .../test/DebugInfo/MIR/AArch64/clobber-sp.mir | 12 +- .../MIR/AArch64/dbgcall-site-expr-chain.mir | 2 +- ...bgcall-site-indirect-param-with-offset.mir | 12 +- .../AArch64/dbgcall-site-indirect-param.mir | 12 +- .../AArch64/dbgcall-site-interpretation.mir | 30 ++-- .../MIR/AArch64/dbgcall-site-orr-moves.mir | 2 +- .../MIR/AArch64/implicit-def-dead-scope.mir | 48 +++---- .../MIR/ARM/call-site-info-vmovd.mir | 4 +- .../MIR/ARM/call-site-info-vmovs.mir | 4 +- .../MIR/ARM/dbgcall-site-interpretation.mir | 30 ++-- .../MIR/ARM/dbgcall-site-propagated-value.mir | 8 +- .../MIR/ARM/if-coverter-call-site-info.mir | 18 +-- .../MIR/ARM/live-debug-values-reg-copy.mir | 2 +- .../DebugInfo/MIR/ARM/param-reg-const-mix.mir | 2 +- .../MIR/ARM/split-superreg-complex.mir | 2 +- .../MIR/ARM/split-superreg-piece.mir | 2 +- .../test/DebugInfo/MIR/ARM/split-superreg.mir | 2 +- ...dbgcall-site-instr-before-bundled-call.mir | 6 +- .../InstrRef/follow-spill-of-indir-value.mir | 8 +- .../InstrRef/follow-spill-of-live-value.mir | 136 +++++++++--------- .../memory-operand-folding-tieddef.mir | 24 ++-- .../MIR/InstrRef/out-of-scope-blocks.mir | 22 +-- .../restore-clobber-with-indirectness.mir | 2 +- .../MIR/InstrRef/stack-coloring-dbg-phi.mir | 4 +- .../InstrRef/win32-chkctk-modifies-esp.mir | 28 ++-- .../MIR/InstrRef/x86-drop-compare-inst.mir | 16 +-- .../x86-fp-stackifier-drop-locations.mir | 8 +- .../DebugInfo/MIR/InstrRef/x86-lea-fixup.mir | 2 +- .../MIR/Mips/dbg-call-site-copy-sub-reg.mir | 8 +- ...l-site-delay-slot-interpretation-64bit.mir | 6 +- ...bg-call-site-delay-slot-interpretation.mir | 6 +- .../Mips/dbg-call-site-param-addiu-64bit.mir | 2 +- .../MIR/Mips/dbg-call-site-param-addiu.mir | 2 +- .../DebugInfo/MIR/Mips/last-inst-bundled.mir | 26 ++-- .../MIR/Mips/live-debug-values-reg-copy.mir | 2 +- .../X86/avoid-single-entry-value-location.mir | 6 +- .../MIR/X86/backup-entry-values-usage.mir | 4 +- .../MIR/X86/call-site-gnu-vs-dwarf5-attrs.mir | 4 +- .../DebugInfo/MIR/X86/clobbered-fragments.mir | 8 +- ...bg-call-site-spilled-arg-multiple-defs.mir | 2 +- .../MIR/X86/dbg-call-site-spilled-arg.mir | 2 +- .../MIR/X86/dbg-stack-value-range.mir | 26 ++-- .../MIR/X86/dbgcall-site-interpretation.mir | 18 +-- .../X86/dbgcall-site-lea-interpretation.mir | 22 +-- .../MIR/X86/dbgcall-site-reference.mir | 14 +- .../MIR/X86/dbgcall-site-two-fwd-reg-defs.mir | 8 +- .../MIR/X86/debug-call-site-param.mir | 10 +- .../MIR/X86/debug-entry-value-operation.mir | 2 +- llvm/test/DebugInfo/MIR/X86/debug-loc-0.mir | 14 +- .../MIR/X86/dvl-livedebugvars-movements.mir | 6 +- .../MIR/X86/dvl-livedebugvars-stackptr.mir | 6 +- llvm/test/DebugInfo/MIR/X86/empty-inline.mir | 22 +-- .../DebugInfo/MIR/X86/kill-after-spill.mir | 90 ++++++------ .../MIR/X86/ldv_unreachable_blocks.mir | 2 +- .../MIR/X86/ldv_unreachable_blocks2.mir | 2 +- .../X86/live-debug-values-entry-transfer.mir | 4 +- .../MIR/X86/live-debug-values-fragments.mir | 6 +- .../MIR/X86/live-debug-values-reg-copy.mir | 24 ++-- .../MIR/X86/live-debug-values-restore.mir | 60 ++++---- .../MIR/X86/live-debug-values-spill.mir | 58 ++++---- .../DebugInfo/MIR/X86/live-debug-values.mir | 16 +-- .../MIR/X86/livedebugvalues-limit.mir | 2 +- .../X86/livedebugvars-crossbb-interval.mir | 8 +- llvm/test/DebugInfo/MIR/X86/machine-cse.mir | 26 ++-- .../DebugInfo/MIR/X86/machinesink-subreg.mir | 2 +- llvm/test/DebugInfo/MIR/X86/machinesink.mir | 6 +- .../MIR/X86/mlicm-hoist-post-regalloc.mir | 16 +-- .../MIR/X86/mlicm-hoist-pre-regalloc.mir | 16 +-- .../X86/multiple-param-dbg-value-entry.mir | 2 +- llvm/test/DebugInfo/MIR/X86/no-cfi-loc.mir | 2 +- .../DebugInfo/MIR/X86/postra-subreg-sink.mir | 2 +- .../MIR/X86/prolog-epilog-indirection.mir | 20 +-- .../X86/regcoalescing-clears-dead-dbgvals.mir | 8 +- .../MIR/X86/remove-redundant-dbg-vals.mir | 24 ++-- .../DebugInfo/MIR/X86/sink-leaves-undef.mir | 8 +- 75 files changed, 539 insertions(+), 539 deletions(-) diff --git a/llvm/test/DebugInfo/MIR/AArch64/clobber-sp.mir b/llvm/test/DebugInfo/MIR/AArch64/clobber-sp.mir index 618e979aa564..c245684f1fca 100644 --- a/llvm/test/DebugInfo/MIR/AArch64/clobber-sp.mir +++ b/llvm/test/DebugInfo/MIR/AArch64/clobber-sp.mir @@ -32,16 +32,16 @@ entry: %x.addr = alloca i32, align 4 tail call void @llvm.dbg.value(metadata i32 %x, i64 0, metadata !19, metadata !22), !dbg !23 - store i32 %x, i32* %x.addr, align 4, !tbaa !24 + store i32 %x, ptr %x.addr, align 4, !tbaa !24 tail call void @llvm.dbg.value(metadata i32 %y, i64 0, metadata !20, metadata !22), !dbg !28 - tail call void @llvm.dbg.declare(metadata %struct.Rect* undef, metadata !21, metadata !22), !dbg !29 + tail call void @llvm.dbg.declare(metadata ptr undef, metadata !21, metadata !22), !dbg !29 tail call void @g([4 x double] %s.coerce) #4, !dbg !30 %tobool = icmp eq i32 %y, 0, !dbg !31 br i1 %tobool, label %if.end, label %if.then, !dbg !33 if.then: ; preds = %entry - tail call void @llvm.dbg.value(metadata i32* %x.addr, i64 0, metadata !19, metadata !22), !dbg !23 - call void @h(i32* nonnull %x.addr) #4, !dbg !34 + tail call void @llvm.dbg.value(metadata ptr %x.addr, i64 0, metadata !19, metadata !22), !dbg !23 + call void @h(ptr nonnull %x.addr) #4, !dbg !34 br label %if.end, !dbg !34 if.end: ; preds = %if.then, %entry @@ -50,9 +50,9 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 declare void @g([4 x double]) local_unnamed_addr #2 - declare void @h(i32*) local_unnamed_addr #2 + declare void @h(ptr) local_unnamed_addr #2 declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1 - declare void @llvm.stackprotector(i8*, i8**) #3 + declare void @llvm.stackprotector(ptr, ptr) #3 attributes #0 = { nounwind optsize ssp } attributes #1 = { nounwind readnone speculatable } diff --git a/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-expr-chain.mir b/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-expr-chain.mir index 3e2244f76c90..cb3e78066440 100644 --- a/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-expr-chain.mir +++ b/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-expr-chain.mir @@ -20,7 +20,7 @@ define dso_local i64 @foo() local_unnamed_addr !dbg !12 { entry: - %0 = load i64, i64* @global, align 8, !dbg !17 + %0 = load i64, ptr @global, align 8, !dbg !17 call void @llvm.dbg.value(metadata i64 %0, metadata !16, metadata !DIExpression()), !dbg !17 %add = add nsw i64 %0, 123, !dbg !17 %sub = add nsw i64 %0, -456, !dbg !17 diff --git a/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-indirect-param-with-offset.mir b/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-indirect-param-with-offset.mir index 59d886cf3211..8363b145e42e 100644 --- a/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-indirect-param-with-offset.mir +++ b/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-indirect-param-with-offset.mir @@ -16,14 +16,14 @@ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" target triple = "arm64-apple-ios10.0.0" - %struct.fat_ptr = type { i32*, i32*, i32* } + %struct.fat_ptr = type { ptr, ptr, ptr } - define i32 @bar(%struct.fat_ptr* nocapture readonly %f) local_unnamed_addr !dbg !13 { + define i32 @bar(ptr nocapture readonly %f) local_unnamed_addr !dbg !13 { entry: - call void @llvm.dbg.declare(metadata %struct.fat_ptr* %f, metadata !23, metadata !DIExpression()), !dbg !24 - %ptr2 = bitcast %struct.fat_ptr* %f to i32**, !dbg !25 - %0 = load i32*, i32** %ptr2, align 8, !dbg !25 - %1 = load i32, i32* %0, align 4, !dbg !31 + call void @llvm.dbg.declare(metadata ptr %f, metadata !23, metadata !DIExpression()), !dbg !24 + %ptr2 = bitcast ptr %f to ptr, !dbg !25 + %0 = load ptr, ptr %ptr2, align 8, !dbg !25 + %1 = load i32, ptr %0, align 4, !dbg !31 %call = tail call i32 @baz(i32 %1), !dbg !34 %call1 = tail call i32 @baz(i32 %call), !dbg !35 ret i32 %call1, !dbg !36 diff --git a/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-indirect-param.mir b/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-indirect-param.mir index c5157f0a0d3b..44aa53c04a9d 100644 --- a/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-indirect-param.mir +++ b/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-indirect-param.mir @@ -35,14 +35,14 @@ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" target triple = "arm64-apple-ios10.0.0" - %struct.fat_ptr = type { i32*, i32*, i32* } + %struct.fat_ptr = type { ptr, ptr, ptr } - define i32 @bar(%struct.fat_ptr* nocapture readonly %f) local_unnamed_addr !dbg !13 { + define i32 @bar(ptr nocapture readonly %f) local_unnamed_addr !dbg !13 { entry: - call void @llvm.dbg.declare(metadata %struct.fat_ptr* %f, metadata !23, metadata !DIExpression()), !dbg !24 - %ptr2 = bitcast %struct.fat_ptr* %f to i32**, !dbg !25 - %0 = load i32*, i32** %ptr2, align 8, !dbg !25 - %1 = load i32, i32* %0, align 4, !dbg !31 + call void @llvm.dbg.declare(metadata ptr %f, metadata !23, metadata !DIExpression()), !dbg !24 + %ptr2 = bitcast ptr %f to ptr, !dbg !25 + %0 = load ptr, ptr %ptr2, align 8, !dbg !25 + %1 = load i32, ptr %0, align 4, !dbg !31 %call = tail call i32 @baz(i32 %1), !dbg !34 %call1 = tail call i32 @baz(i32 %call), !dbg !35 ret i32 %call1, !dbg !36 diff --git a/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpretation.mir b/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpretation.mir index 41665ff71d10..9df0044d3971 100644 --- a/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpretation.mir +++ b/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpretation.mir @@ -47,42 +47,42 @@ call void @llvm.dbg.value(metadata i32 %arg1, metadata !17, metadata !DIExpression()), !dbg !21 call void @llvm.dbg.value(metadata i32 %arg2, metadata !18, metadata !DIExpression()), !dbg !21 call void @llvm.dbg.value(metadata i32 %arg3, metadata !19, metadata !DIExpression()), !dbg !21 - store i32 %arg3, i32* %arg3.addr, align 4 - %0 = bitcast i32* %a to i8*, !dbg !21 - call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %0), !dbg !21 + store i32 %arg3, ptr %arg3.addr, align 4 + %0 = bitcast ptr %a to ptr, !dbg !21 + call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %0), !dbg !21 %add = add nsw i32 %arg1, 2, !dbg !21 %sub = add nsw i32 %arg2, -4, !dbg !21 - call void @llvm.dbg.value(metadata i32* %arg3.addr, metadata !19, metadata !DIExpression(DW_OP_deref)), !dbg !21 - %call = call i32 @func2(i32 %add, i32 %sub, i32* nonnull %arg3.addr), !dbg !21 + call void @llvm.dbg.value(metadata ptr %arg3.addr, metadata !19, metadata !DIExpression(DW_OP_deref)), !dbg !21 + %call = call i32 @func2(i32 %add, i32 %sub, ptr nonnull %arg3.addr), !dbg !21 call void @llvm.dbg.value(metadata i32 %call, metadata !20, metadata !DIExpression()), !dbg !21 - store i32 %call, i32* %a, align 4, !dbg !21 - %1 = load i32, i32* %arg3.addr, align 4, !dbg !21 + store i32 %call, ptr %a, align 4, !dbg !21 + %1 = load i32, ptr %arg3.addr, align 4, !dbg !21 call void @llvm.dbg.value(metadata i32 %1, metadata !19, metadata !DIExpression()), !dbg !21 %sub1 = add nsw i32 %1, -16, !dbg !21 %add2 = add nsw i32 %arg1, 8, !dbg !21 - call void @llvm.dbg.value(metadata i32* %a, metadata !20, metadata !DIExpression(DW_OP_deref)), !dbg !21 - %call3 = call i32 @func2(i32 %sub1, i32 %add2, i32* nonnull %a), !dbg !21 - %2 = load i32, i32* %a, align 4, !dbg !21 + call void @llvm.dbg.value(metadata ptr %a, metadata !20, metadata !DIExpression(DW_OP_deref)), !dbg !21 + %call3 = call i32 @func2(i32 %sub1, i32 %add2, ptr nonnull %a), !dbg !21 + %2 = load i32, ptr %a, align 4, !dbg !21 call void @llvm.dbg.value(metadata i32 %2, metadata !20, metadata !DIExpression()), !dbg !21 %add4 = add nsw i32 %2, %call3, !dbg !21 call void @llvm.dbg.value(metadata i32 %add4, metadata !20, metadata !DIExpression(DW_OP_plus_uconst, 1, DW_OP_stack_value)), !dbg !21 - call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %0), !dbg !21 + call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %0), !dbg !21 ret i32 %add4, !dbg !21 } ; Function Attrs: argmemonly nounwind willreturn - declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) + declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) - declare !dbg !4 dso_local i32 @func2(i32, i32, i32*) local_unnamed_addr + declare !dbg !4 dso_local i32 @func2(i32, i32, ptr) local_unnamed_addr ; Function Attrs: argmemonly nounwind willreturn - declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) + declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) ; Function Attrs: nounwind readnone speculatable willreturn declare void @llvm.dbg.value(metadata, metadata, metadata) ; Function Attrs: nounwind - declare void @llvm.stackprotector(i8*, i8**) + declare void @llvm.stackprotector(ptr, ptr) attributes #0 = { "frame-pointer"="all" } diff --git a/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-orr-moves.mir b/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-orr-moves.mir index adf2d2ec791f..389121914ba8 100644 --- a/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-orr-moves.mir +++ b/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-orr-moves.mir @@ -55,7 +55,7 @@ call void @llvm.dbg.value(metadata i32 %p, metadata !40, metadata !DIExpression()), !dbg !42 call void @llvm.dbg.value(metadata i64 %q, metadata !41, metadata !DIExpression()), !dbg !42 %conv = trunc i64 %q to i32, !dbg !43 - %0 = load i32, i32* @global, align 4, !dbg !43 + %0 = load i32, ptr @global, align 4, !dbg !43 tail call void @call_int_int(i32 %conv, i32 %0), !dbg !43 ret i32 %p, !dbg !44 } diff --git a/llvm/test/DebugInfo/MIR/AArch64/implicit-def-dead-scope.mir b/llvm/test/DebugInfo/MIR/AArch64/implicit-def-dead-scope.mir index 98ec9dc8fa41..1479b3728ad0 100644 --- a/llvm/test/DebugInfo/MIR/AArch64/implicit-def-dead-scope.mir +++ b/llvm/test/DebugInfo/MIR/AArch64/implicit-def-dead-scope.mir @@ -21,12 +21,12 @@ @bt = global i32 0, align 4 - define void @_ZN1v2bvEv(%class.v* nocapture readonly %this) local_unnamed_addr align 2 !dbg !14 { + define void @_ZN1v2bvEv(ptr nocapture readonly %this) local_unnamed_addr align 2 !dbg !14 { entry: %bz = alloca %class.j, align 8 %att = alloca %class.j, align 8 - %ap = getelementptr inbounds %class.v, %class.v* %this, i64 0, i32 1 - %0 = load i8, i8* %ap, align 4 + %ap = getelementptr inbounds %class.v, ptr %this, i64 0, i32 1 + %0 = load i8, ptr %ap, align 4 %conv = sext i8 %0 to i32 switch i32 %conv, label %sw.epilog [ i32 1, label %_ZN1jILi6EN1a1fEE1mEj.exit @@ -34,24 +34,24 @@ ] _ZN1jILi6EN1a1fEE1mEj.exit: ; preds = %entry - %1 = bitcast %class.j* %att to i64* - %2 = bitcast %class.j* %bz to i64* - store i64 1, i64* %2, align 8 + %1 = bitcast ptr %att to ptr + %2 = bitcast ptr %bz to ptr + store i64 1, ptr %2, align 8 call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !18, metadata !23), !dbg !24 - store i64 1, i64* %1, align 8, !dbg !27 + store i64 1, ptr %1, align 8, !dbg !27 br label %sw.epilog sw.bb2: ; preds = %entry - %3 = bitcast %class.j* %att to i64* - %4 = bitcast %class.j* %bz to i64* - %.pre = load i64, i64* %3, align 8 - %agg.tmp.sroa.2.0..sroa_idx1.i.i.i.i.i.i13.phi.trans.insert = getelementptr inbounds %class.j, %class.j* %bz, i64 0, i32 1 - %.phi.trans.insert = bitcast i32* %agg.tmp.sroa.2.0..sroa_idx1.i.i.i.i.i.i13.phi.trans.insert to i64* - %agg.tmp.sroa.2.0.copyload2.i.i6.i.i.i.i14.pre = load i64, i64* %.phi.trans.insert, align 8 - %.pre25 = load i64, i64* %4, align 8 - %agg.tmp.sroa.2.0..sroa_idx1.i.i.i.i.i.i.phi.trans.insert = getelementptr inbounds %class.j, %class.j* %att, i64 0, i32 1 - %.phi.trans.insert26 = bitcast i32* %agg.tmp.sroa.2.0..sroa_idx1.i.i.i.i.i.i.phi.trans.insert to i64* - %agg.tmp.sroa.2.0.copyload2.i.i6.i.i.i.i.pre = load i64, i64* %.phi.trans.insert26, align 8 + %3 = bitcast ptr %att to ptr + %4 = bitcast ptr %bz to ptr + %.pre = load i64, ptr %3, align 8 + %agg.tmp.sroa.2.0..sroa_idx1.i.i.i.i.i.i13.phi.trans.insert = getelementptr inbounds %class.j, ptr %bz, i64 0, i32 1 + %.phi.trans.insert = bitcast ptr %agg.tmp.sroa.2.0..sroa_idx1.i.i.i.i.i.i13.phi.trans.insert to ptr + %agg.tmp.sroa.2.0.copyload2.i.i6.i.i.i.i14.pre = load i64, ptr %.phi.trans.insert, align 8 + %.pre25 = load i64, ptr %4, align 8 + %agg.tmp.sroa.2.0..sroa_idx1.i.i.i.i.i.i.phi.trans.insert = getelementptr inbounds %class.j, ptr %att, i64 0, i32 1 + %.phi.trans.insert26 = bitcast ptr %agg.tmp.sroa.2.0..sroa_idx1.i.i.i.i.i.i.phi.trans.insert to ptr + %agg.tmp.sroa.2.0.copyload2.i.i6.i.i.i.i.pre = load i64, ptr %.phi.trans.insert26, align 8 br label %sw.epilog sw.epilog: ; preds = %sw.bb2, %_ZN1jILi6EN1a1fEE1mEj.exit, %entry @@ -59,26 +59,26 @@ %5 = phi i64 [ %.pre25, %sw.bb2 ], [ 0, %entry ], [ 1, %_ZN1jILi6EN1a1fEE1mEj.exit ] %agg.tmp.sroa.2.0.copyload2.i.i6.i.i.i.i14 = phi i64 [ %agg.tmp.sroa.2.0.copyload2.i.i6.i.i.i.i14.pre, %sw.bb2 ], [ undef, %entry ], [ undef, %_ZN1jILi6EN1a1fEE1mEj.exit ] %6 = phi i64 [ %.pre, %sw.bb2 ], [ 0, %entry ], [ 1, %_ZN1jILi6EN1a1fEE1mEj.exit ] - %bw1 = bitcast %class.v* %this to i32* - %7 = load i32, i32* %bw1, align 4 - %bx = getelementptr inbounds %class.v, %class.v* %this, i64 0, i32 2 - %8 = load i8, i8* %bx, align 1 + %bw1 = bitcast ptr %this to ptr + %7 = load i32, ptr %bw1, align 4 + %bx = getelementptr inbounds %class.v, ptr %this, i64 0, i32 2 + %8 = load i8, ptr %bx, align 1 %tobool = icmp ne i8 %8, 0 %.fca.0.insert9 = insertvalue [2 x i64] undef, i64 %agg.tmp.sroa.2.0.copyload2.i.i6.i.i.i.i14, 0 %.fca.1.insert12 = insertvalue [2 x i64] %.fca.0.insert9, i64 %5, 1 %.fca.0.insert = insertvalue [2 x i64] undef, i64 %agg.tmp.sroa.2.0.copyload2.i.i6.i.i.i.i, 0 %.fca.1.insert = insertvalue [2 x i64] %.fca.0.insert, i64 %6, 1 - call void @_Z2byi1LS_bbPi(i32 %7, [2 x i64] %.fca.1.insert12, [2 x i64] %.fca.1.insert, i1 %tobool, i1 false, i32* nonnull @bt) + call void @_Z2byi1LS_bbPi(i32 %7, [2 x i64] %.fca.1.insert12, [2 x i64] %.fca.1.insert, i1 %tobool, i1 false, ptr nonnull @bt) ret void } - declare void @_Z2byi1LS_bbPi(i32, [2 x i64], [2 x i64], i1, i1, i32*) local_unnamed_addr + declare void @_Z2byi1LS_bbPi(i32, [2 x i64], [2 x i64], i1, i1, ptr) local_unnamed_addr ; Function Attrs: nounwind readnone speculatable declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #0 ; Function Attrs: nounwind - declare void @llvm.stackprotector(i8*, i8**) #1 + declare void @llvm.stackprotector(ptr, ptr) #1 attributes #0 = { nounwind readnone speculatable } attributes #1 = { nounwind } diff --git a/llvm/test/DebugInfo/MIR/ARM/call-site-info-vmovd.mir b/llvm/test/DebugInfo/MIR/ARM/call-site-info-vmovd.mir index e6a1e267ecba..ee4baf7e567c 100644 --- a/llvm/test/DebugInfo/MIR/ARM/call-site-info-vmovd.mir +++ b/llvm/test/DebugInfo/MIR/ARM/call-site-info-vmovd.mir @@ -27,7 +27,7 @@ define arm_aapcs_vfpcc i32 @b(double %c) local_unnamed_addr #0 !dbg !16 { entry: call void @llvm.dbg.value(metadata double %c, metadata !21, metadata !DIExpression()), !dbg !22 - %call = tail call arm_aapcs_vfpcc i32 bitcast (i32 (...)* @d to i32 ()*)(), !dbg !23 + %call = tail call arm_aapcs_vfpcc i32 @d(), !dbg !23 %conv = fptrunc double %c to float, !dbg !24 %call1 = tail call arm_aapcs_vfpcc i32 @a(float %conv), !dbg !25 ret i32 undef, !dbg !26 @@ -35,7 +35,7 @@ declare arm_aapcs_vfpcc i32 @d(...) local_unnamed_addr #0 declare !dbg !4 arm_aapcs_vfpcc i32 @a(float) local_unnamed_addr #0 declare void @llvm.dbg.value(metadata, metadata, metadata) - declare void @llvm.stackprotector(i8*, i8**) + declare void @llvm.stackprotector(ptr, ptr) attributes #0 = { "disable-tail-calls"="false" "frame-pointer"="all" "target-features"="+thumb-mode,+vfp2" } diff --git a/llvm/test/DebugInfo/MIR/ARM/call-site-info-vmovs.mir b/llvm/test/DebugInfo/MIR/ARM/call-site-info-vmovs.mir index 8bfb0cdc1a00..730d0f47cb55 100644 --- a/llvm/test/DebugInfo/MIR/ARM/call-site-info-vmovs.mir +++ b/llvm/test/DebugInfo/MIR/ARM/call-site-info-vmovs.mir @@ -22,14 +22,14 @@ define arm_aapcs_vfpcc i32 @b(double %c) local_unnamed_addr #0 !dbg !16 { entry: call void @llvm.dbg.value(metadata double %c, metadata !18, metadata !DIExpression()), !dbg !19 - %call = tail call arm_aapcs_vfpcc i32 bitcast (i32 (...)* @d to i32 ()*)(), !dbg !20 + %call = tail call arm_aapcs_vfpcc i32 @d(), !dbg !20 %call1 = tail call arm_aapcs_vfpcc i32 @a(double %c), !dbg !21 ret i32 undef, !dbg !22 } declare arm_aapcs_vfpcc i32 @d(...) local_unnamed_addr #0 declare !dbg !4 arm_aapcs_vfpcc i32 @a(double) local_unnamed_addr #0 declare void @llvm.dbg.value(metadata, metadata, metadata) - declare void @llvm.stackprotector(i8*, i8**) + declare void @llvm.stackprotector(ptr, ptr) attributes #0 = { "disable-tail-calls"="false" "frame-pointer"="all" "target-features"="+thumb-mode,+vfp2" } diff --git a/llvm/test/DebugInfo/MIR/ARM/dbgcall-site-interpretation.mir b/llvm/test/DebugInfo/MIR/ARM/dbgcall-site-interpretation.mir index 0ba0b78203ef..ce9fc094fa29 100644 --- a/llvm/test/DebugInfo/MIR/ARM/dbgcall-site-interpretation.mir +++ b/llvm/test/DebugInfo/MIR/ARM/dbgcall-site-interpretation.mir @@ -43,42 +43,42 @@ call void @llvm.dbg.value(metadata i32 %arg1, metadata !18, metadata !DIExpression()), !dbg !22 call void @llvm.dbg.value(metadata i32 %arg2, metadata !19, metadata !DIExpression()), !dbg !22 call void @llvm.dbg.value(metadata i32 %arg3, metadata !20, metadata !DIExpression()), !dbg !22 - store i32 %arg3, i32* %arg3.addr, align 4 - %0 = bitcast i32* %a to i8*, !dbg !22 - call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %0), !dbg !22 + store i32 %arg3, ptr %arg3.addr, align 4 + %0 = bitcast ptr %a to ptr, !dbg !22 + call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %0), !dbg !22 %add = add nsw i32 %arg1, 2, !dbg !22 %sub = add nsw i32 %arg2, -4, !dbg !22 - call void @llvm.dbg.value(metadata i32* %arg3.addr, metadata !20, metadata !DIExpression(DW_OP_deref)), !dbg !22 - %call = call arm_aapcscc i32 @func2(i32 %add, i32 %sub, i32* nonnull %arg3.addr), !dbg !22 + call void @llvm.dbg.value(metadata ptr %arg3.addr, metadata !20, metadata !DIExpression(DW_OP_deref)), !dbg !22 + %call = call arm_aapcscc i32 @func2(i32 %add, i32 %sub, ptr nonnull %arg3.addr), !dbg !22 call void @llvm.dbg.value(metadata i32 %call, metadata !21, metadata !DIExpression()), !dbg !22 - store i32 %call, i32* %a, align 4, !dbg !22 - %1 = load i32, i32* %arg3.addr, align 4, !dbg !22 + store i32 %call, ptr %a, align 4, !dbg !22 + %1 = load i32, ptr %arg3.addr, align 4, !dbg !22 call void @llvm.dbg.value(metadata i32 %1, metadata !20, metadata !DIExpression()), !dbg !22 %sub1 = add nsw i32 %1, -16, !dbg !22 %add2 = add nsw i32 %arg1, 8, !dbg !22 - call void @llvm.dbg.value(metadata i32* %a, metadata !21, metadata !DIExpression(DW_OP_deref)), !dbg !22 - %call3 = call arm_aapcscc i32 @func2(i32 %sub1, i32 %add2, i32* nonnull %a), !dbg !22 - %2 = load i32, i32* %a, align 4, !dbg !22 + call void @llvm.dbg.value(metadata ptr %a, metadata !21, metadata !DIExpression(DW_OP_deref)), !dbg !22 + %call3 = call arm_aapcscc i32 @func2(i32 %sub1, i32 %add2, ptr nonnull %a), !dbg !22 + %2 = load i32, ptr %a, align 4, !dbg !22 call void @llvm.dbg.value(metadata i32 %2, metadata !21, metadata !DIExpression()), !dbg !22 %add4 = add nsw i32 %2, %call3, !dbg !22 call void @llvm.dbg.value(metadata i32 %add4, metadata !21, metadata !DIExpression(DW_OP_plus_uconst, 1, DW_OP_stack_value)), !dbg !22 - call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %0), !dbg !22 + call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %0), !dbg !22 ret i32 %add4, !dbg !22 } ; Function Attrs: argmemonly nounwind willreturn - declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) + declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) - declare !dbg !4 dso_local arm_aapcscc i32 @func2(i32, i32, i32*) local_unnamed_addr + declare !dbg !4 dso_local arm_aapcscc i32 @func2(i32, i32, ptr) local_unnamed_addr ; Function Attrs: argmemonly nounwind willreturn - declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) + declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) ; Function Attrs: nounwind readnone speculatable willreturn declare void @llvm.dbg.value(metadata, metadata, metadata) ; Function Attrs: nounwind - declare void @llvm.stackprotector(i8*, i8**) + declare void @llvm.stackprotector(ptr, ptr) attributes #0 = { "frame-pointer"="all" "target-features"="+armv7-a" } diff --git a/llvm/test/DebugInfo/MIR/ARM/dbgcall-site-propagated-value.mir b/llvm/test/DebugInfo/MIR/ARM/dbgcall-site-propagated-value.mir index b25b1c90d634..a2242acafebb 100644 --- a/llvm/test/DebugInfo/MIR/ARM/dbgcall-site-propagated-value.mir +++ b/llvm/test/DebugInfo/MIR/ARM/dbgcall-site-propagated-value.mir @@ -33,14 +33,14 @@ } ; Function Attrs: noinline nounwind optsize - define internal arm_aapcs_vfpcc void @callee(i32* %p1) unnamed_addr #0 !dbg !29 { + define internal arm_aapcs_vfpcc void @callee(ptr %p1) unnamed_addr #0 !dbg !29 { entry: unreachable } - declare !dbg !4 arm_aapcs_vfpcc i32* @value() - declare !dbg !9 arm_aapcs_vfpcc i32 @interesting(i32*) - declare !dbg !12 arm_aapcs_vfpcc void @ext(i32*) + declare !dbg !4 arm_aapcs_vfpcc ptr @value() + declare !dbg !9 arm_aapcs_vfpcc i32 @interesting(ptr) + declare !dbg !12 arm_aapcs_vfpcc void @ext(ptr) ; Function Attrs: nounwind readnone speculatable willreturn declare void @llvm.dbg.value(metadata, metadata, metadata) #1 diff --git a/llvm/test/DebugInfo/MIR/ARM/if-coverter-call-site-info.mir b/llvm/test/DebugInfo/MIR/ARM/if-coverter-call-site-info.mir index e79f905148a1..e0c89647bbe2 100644 --- a/llvm/test/DebugInfo/MIR/ARM/if-coverter-call-site-info.mir +++ b/llvm/test/DebugInfo/MIR/ARM/if-coverter-call-site-info.mir @@ -33,34 +33,34 @@ target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "armv6kz-unknown-linux-gnueabihf" - @mri_common_symbol = external dso_local local_unnamed_addr global i32*, align 4 + @mri_common_symbol = external dso_local local_unnamed_addr global ptr, align 4 ; Function Attrs: nounwind - define dso_local void @baa(i32* %secptr, i32 %subseg) local_unnamed_addr #0 !dbg !14 { + define dso_local void @baa(ptr %secptr, i32 %subseg) local_unnamed_addr #0 !dbg !14 { entry: - call void @llvm.dbg.value(metadata i32* %secptr, metadata !16, metadata !DIExpression()), !dbg !18 + call void @llvm.dbg.value(metadata ptr %secptr, metadata !16, metadata !DIExpression()), !dbg !18 call void @llvm.dbg.value(metadata i32 %subseg, metadata !17, metadata !DIExpression()), !dbg !18 - %cmp = icmp eq i32* %secptr, null, !dbg !19 + %cmp = icmp eq ptr %secptr, null, !dbg !19 %cmp1 = icmp eq i32 %subseg, 0, !dbg !21 %or.cond = and i1 %cmp, %cmp1, !dbg !22 br i1 %or.cond, label %if.end, label %if.then, !dbg !22 if.then: ; preds = %entry - tail call void @foo(i32* %secptr, i32 %subseg), !dbg !23 + tail call void @foo(ptr %secptr, i32 %subseg), !dbg !23 br label %if.end, !dbg !23 if.end: ; preds = %entry, %if.then - store i32* null, i32** @mri_common_symbol, align 4, !dbg !24, !tbaa !25 + store ptr null, ptr @mri_common_symbol, align 4, !dbg !24, !tbaa !25 ret void, !dbg !29 } - declare !dbg !4 dso_local void @foo(i32*, i32) local_unnamed_addr + declare !dbg !4 dso_local void @foo(ptr, i32) local_unnamed_addr ; Function Attrs: nounwind readnone speculatable willreturn declare void @llvm.dbg.value(metadata, metadata, metadata) ; Function Attrs: nounwind - declare void @llvm.stackprotector(i8*, i8**) + declare void @llvm.stackprotector(ptr, ptr) attributes #0 = { "frame-pointer"="all" } @@ -123,7 +123,7 @@ callSites: - { arg: 1, reg: '$r1' } } constants: - id: 0 - value: 'i32** null' + value: 'ptr null' alignment: 4 machineFunctionInfo: {} body: | diff --git a/llvm/test/DebugInfo/MIR/ARM/live-debug-values-reg-copy.mir b/llvm/test/DebugInfo/MIR/ARM/live-debug-values-reg-copy.mir index bb9cd5ef5c3b..c7e19abaa630 100644 --- a/llvm/test/DebugInfo/MIR/ARM/live-debug-values-reg-copy.mir +++ b/llvm/test/DebugInfo/MIR/ARM/live-debug-values-reg-copy.mir @@ -40,7 +40,7 @@ declare void @llvm.dbg.value(metadata, metadata, metadata) #0 ; Function Attrs: nounwind - declare void @llvm.stackprotector(i8*, i8**) #1 + declare void @llvm.stackprotector(ptr, ptr) #1 attributes #0 = { nounwind readnone speculatable } attributes #1 = { nounwind } diff --git a/llvm/test/DebugInfo/MIR/ARM/param-reg-const-mix.mir b/llvm/test/DebugInfo/MIR/ARM/param-reg-const-mix.mir index 83b5a6f394dc..71505e3504ae 100644 --- a/llvm/test/DebugInfo/MIR/ARM/param-reg-const-mix.mir +++ b/llvm/test/DebugInfo/MIR/ARM/param-reg-const-mix.mir @@ -26,7 +26,7 @@ %p1.coerce.fca.1.extract = extractvalue [3 x i32] %p1.coerce, 1 call void @llvm.dbg.value(metadata i32 %p1.coerce.fca.1.extract, metadata !17, metadata !DIExpression(DW_OP_LLVM_fragment, 32, 32)), !dbg !18 call void @llvm.dbg.value(metadata i32 undef, metadata !17, metadata !DIExpression(DW_OP_LLVM_fragment, 64, 32)), !dbg !18 - %call = tail call arm_aapcscc i32 bitcast (i32 (...)* @fn2 to i32 (i32)*)(i32 %p1.coerce.fca.1.extract), !dbg !19 + %call = tail call arm_aapcscc i32 @fn2(i32 %p1.coerce.fca.1.extract), !dbg !19 %cmp = icmp sge i32 %p1.coerce.fca.0.extract, %call, !dbg !19 %conv = zext i1 %cmp to i32, !dbg !19 ret i32 %conv, !dbg !19 diff --git a/llvm/test/DebugInfo/MIR/ARM/split-superreg-complex.mir b/llvm/test/DebugInfo/MIR/ARM/split-superreg-complex.mir index 9bb255a65257..c119334b0cf5 100644 --- a/llvm/test/DebugInfo/MIR/ARM/split-superreg-complex.mir +++ b/llvm/test/DebugInfo/MIR/ARM/split-superreg-complex.mir @@ -24,7 +24,7 @@ define float @f() local_unnamed_addr #0 !dbg !9 { entry: - %call = tail call <4 x float> bitcast (<4 x float> (...)* @v to <4 x float> ()*)() #0, !dbg !19 + %call = tail call <4 x float> @v() #0, !dbg !19 tail call void @llvm.dbg.value(metadata <4 x float> %call, i64 0, metadata !14, metadata !20), !dbg !21 %vecext = extractelement <4 x float> %call, i32 0, !dbg !22 %vecext1 = extractelement <4 x float> %call, i32 1, !dbg !23 diff --git a/llvm/test/DebugInfo/MIR/ARM/split-superreg-piece.mir b/llvm/test/DebugInfo/MIR/ARM/split-superreg-piece.mir index c741c4022382..70cecd2e57b3 100644 --- a/llvm/test/DebugInfo/MIR/ARM/split-superreg-piece.mir +++ b/llvm/test/DebugInfo/MIR/ARM/split-superreg-piece.mir @@ -20,7 +20,7 @@ define float @f() local_unnamed_addr #0 !dbg !9 { entry: - %call = tail call <4 x float> bitcast (<4 x float> (...)* @v to <4 x float> ()*)() #0, !dbg !19 + %call = tail call <4 x float> @v() #0, !dbg !19 tail call void @llvm.dbg.value(metadata <4 x float> %call, i64 0, metadata !14, metadata !20), !dbg !21 %vecext = extractelement <4 x float> %call, i32 0, !dbg !22 %vecext1 = extractelement <4 x float> %call, i32 1, !dbg !23 diff --git a/llvm/test/DebugInfo/MIR/ARM/split-superreg.mir b/llvm/test/DebugInfo/MIR/ARM/split-superreg.mir index b7d51a13b7ec..93dca334a6a4 100644 --- a/llvm/test/DebugInfo/MIR/ARM/split-superreg.mir +++ b/llvm/test/DebugInfo/MIR/ARM/split-superreg.mir @@ -20,7 +20,7 @@ define float @f() local_unnamed_addr #0 !dbg !9 { entry: - %call = tail call <4 x float> bitcast (<4 x float> (...)* @v to <4 x float> ()*)() #0, !dbg !19 + %call = tail call <4 x float> @v() #0, !dbg !19 tail call void @llvm.dbg.value(metadata <4 x float> %call, i64 0, metadata !14, metadata !20), !dbg !21 %vecext = extractelement <4 x float> %call, i32 0, !dbg !22 %vecext1 = extractelement <4 x float> %call, i32 1, !dbg !23 diff --git a/llvm/test/DebugInfo/MIR/Hexagon/dbgcall-site-instr-before-bundled-call.mir b/llvm/test/DebugInfo/MIR/Hexagon/dbgcall-site-instr-before-bundled-call.mir index e96f13c53555..22101d514613 100644 --- a/llvm/test/DebugInfo/MIR/Hexagon/dbgcall-site-instr-before-bundled-call.mir +++ b/llvm/test/DebugInfo/MIR/Hexagon/dbgcall-site-instr-before-bundled-call.mir @@ -33,9 +33,9 @@ ; Function Attrs: nounwind define void @caller() #0 !dbg !12 { entry: - %0 = load i32, i32* @ga, align 4, !dbg !15 - %1 = load i32, i32* @gb, align 4, !dbg !16 - %2 = load i32, i32* @gc, align 4, !dbg !17 + %0 = load i32, ptr @ga, align 4, !dbg !15 + %1 = load i32, ptr @gb, align 4, !dbg !16 + %2 = load i32, ptr @gc, align 4, !dbg !17 call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28}"(), !dbg !18, !srcloc !19 call void @callee(i32 %0, i32 %1, i32 %2), !dbg !20 ret void, !dbg !21 diff --git a/llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-indir-value.mir b/llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-indir-value.mir index 512a10d512a4..e3b8df277854 100644 --- a/llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-indir-value.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-indir-value.mir @@ -42,12 +42,12 @@ %struct.NonTrivial = type { i32 } ; Function Attrs: nounwind uwtable - define i32 @_Z3foo10NonTrivial(%struct.NonTrivial* nocapture readonly %nt) local_unnamed_addr #0 !dbg !7 { + define i32 @_Z3foo10NonTrivial(ptr nocapture readonly %nt) local_unnamed_addr #0 !dbg !7 { entry: - tail call void @llvm.dbg.declare(metadata %struct.NonTrivial* %nt, metadata !20, metadata !DIExpression()), !dbg !21 + tail call void @llvm.dbg.declare(metadata ptr %nt, metadata !20, metadata !DIExpression()), !dbg !21 tail call void asm sideeffect "", "~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{dirflag},~{fpsr},~{flags}"() #2, !dbg !22, !srcloc !23 - %i1 = bitcast %struct.NonTrivial* %nt to i32*, !dbg !24 - %0 = load i32, i32* %i1, align 4, !dbg !24, !tbaa !25 + %i1 = bitcast ptr %nt to ptr, !dbg !24 + %0 = load i32, ptr %i1, align 4, !dbg !24, !tbaa !25 ret i32 %0, !dbg !30 } diff --git a/llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-live-value.mir b/llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-live-value.mir index 59d8e735c678..a3332785e50f 100644 --- a/llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-live-value.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-live-value.mir @@ -32,70 +32,70 @@ %"class.std::deque" = type { %"class.std::_Deque_base" } %"class.std::_Deque_base" = type { %"struct.std::_Deque_base>::_Deque_impl" } - %"struct.std::_Deque_base>::_Deque_impl" = type { %"class.llvm::Loop"***, i64, %"struct.std::_Deque_iterator", %"struct.std::_Deque_iterator" } + %"struct.std::_Deque_base>::_Deque_impl" = type { ptr, i64, %"struct.std::_Deque_iterator", %"struct.std::_Deque_iterator" } %"class.llvm::Loop" = type opaque - %"struct.std::_Deque_iterator" = type { %"class.llvm::Loop"**, %"class.llvm::Loop"**, %"class.llvm::Loop"**, %"class.llvm::Loop"*** } + %"struct.std::_Deque_iterator" = type { ptr, ptr, ptr, ptr } - define linkonce_odr void @_ZNSt5dequeIPN4llvm4LoopESaIS2_EE13_M_insert_auxESt15_Deque_iteratorIS2_RS2_PS2_EmRKS2_(%"class.std::deque"* %this, %"struct.std::_Deque_iterator"* %__pos, i64 %__n) local_unnamed_addr align 2 !dbg !3 { + define linkonce_odr void @_ZNSt5dequeIPN4llvm4LoopESaIS2_EE13_M_insert_auxESt15_Deque_iteratorIS2_RS2_PS2_EmRKS2_(ptr %this, ptr %__pos, i64 %__n) local_unnamed_addr align 2 !dbg !3 { entry: - %0 = load %"class.llvm::Loop"**, %"class.llvm::Loop"*** undef, align 8, !dbg !7 - %_M_cur6.i = getelementptr inbounds %"class.std::deque", %"class.std::deque"* %this, i64 0, i32 0, i32 0, i32 2, i32 0, !dbg !7 - %1 = load %"class.llvm::Loop"**, %"class.llvm::Loop"*** %_M_cur6.i, align 8, !dbg !7 - %2 = load %"class.llvm::Loop"**, %"class.llvm::Loop"*** undef, align 8, !dbg !7 + %0 = load ptr, ptr undef, align 8, !dbg !7 + %_M_cur6.i = getelementptr inbounds %"class.std::deque", ptr %this, i64 0, i32 0, i32 0, i32 2, i32 0, !dbg !7 + %1 = load ptr, ptr %_M_cur6.i, align 8, !dbg !7 + %2 = load ptr, ptr undef, align 8, !dbg !7 br i1 undef, label %if.then.i851, label %if.end.i856, !dbg !7 if.then.i851: ; preds = %entry - %.pre1038 = load %"class.llvm::Loop"**, %"class.llvm::Loop"*** undef, align 8, !dbg !7 - %3 = bitcast %"class.std::deque"* %this to i8*, !dbg !7 - %sunkaddr = getelementptr inbounds i8, i8* %3, i64 40, !dbg !7 - %4 = bitcast i8* %sunkaddr to %"class.llvm::Loop"****, !dbg !7 - %.pre1039 = load %"class.llvm::Loop"***, %"class.llvm::Loop"**** %4, align 8, !dbg !7 + %.pre1038 = load ptr, ptr undef, align 8, !dbg !7 + %3 = bitcast ptr %this to ptr, !dbg !7 + %sunkaddr = getelementptr inbounds i8, ptr %3, i64 40, !dbg !7 + %4 = bitcast ptr %sunkaddr to ptr, !dbg !7 + %.pre1039 = load ptr, ptr %4, align 8, !dbg !7 br label %if.end.i856, !dbg !7 if.end.i856: ; preds = %if.then.i851, %entry - %5 = phi %"class.llvm::Loop"*** [ %.pre1039, %if.then.i851 ], [ undef, %entry ], !dbg !7 - %6 = phi %"class.llvm::Loop"** [ %.pre1038, %if.then.i851 ], [ %0, %entry ], !dbg !7 + %5 = phi ptr [ %.pre1039, %if.then.i851 ], [ undef, %entry ], !dbg !7 + %6 = phi ptr [ %.pre1038, %if.then.i851 ], [ %0, %entry ], !dbg !7 %sub.i.i.i853 = sub nsw i64 0, %__n, !dbg !7 - %add.ptr.i.i.i.i859 = getelementptr inbounds %"class.llvm::Loop"*, %"class.llvm::Loop"** %1, i64 %sub.i.i.i853, !dbg !7 - store %"class.llvm::Loop"** %6, %"class.llvm::Loop"*** undef, align 8, !dbg !7 - %7 = bitcast %"struct.std::_Deque_iterator"* %__pos to i8*, !dbg !7 - %sunkaddr1 = getelementptr inbounds i8, i8* %7, i64 24, !dbg !7 - %8 = bitcast i8* %sunkaddr1 to %"class.llvm::Loop"****, !dbg !7 - store %"class.llvm::Loop"*** %5, %"class.llvm::Loop"**** %8, align 8, !dbg !7 - %9 = bitcast %"class.std::deque"* %this to i8*, !dbg !7 - %sunkaddr2 = getelementptr inbounds i8, i8* %9, i64 16, !dbg !7 - %10 = bitcast i8* %sunkaddr2 to %"class.llvm::Loop"***, !dbg !7 - %11 = load %"class.llvm::Loop"**, %"class.llvm::Loop"*** %10, align 8, !dbg !7 - %12 = load %"class.llvm::Loop"**, %"class.llvm::Loop"*** undef, align 8, !dbg !7 - %13 = bitcast %"class.std::deque"* %this to i8*, !dbg !7 - %sunkaddr3 = getelementptr inbounds i8, i8* %13, i64 40, !dbg !7 - %14 = bitcast i8* %sunkaddr3 to %"class.llvm::Loop"****, !dbg !7 - %15 = load %"class.llvm::Loop"***, %"class.llvm::Loop"**** %14, align 8, !dbg !7 + %add.ptr.i.i.i.i859 = getelementptr inbounds ptr, ptr %1, i64 %sub.i.i.i853, !dbg !7 + store ptr %6, ptr undef, align 8, !dbg !7 + %7 = bitcast ptr %__pos to ptr, !dbg !7 + %sunkaddr1 = getelementptr inbounds i8, ptr %7, i64 24, !dbg !7 + %8 = bitcast ptr %sunkaddr1 to ptr, !dbg !7 + store ptr %5, ptr %8, align 8, !dbg !7 + %9 = bitcast ptr %this to ptr, !dbg !7 + %sunkaddr2 = getelementptr inbounds i8, ptr %9, i64 16, !dbg !7 + %10 = bitcast ptr %sunkaddr2 to ptr, !dbg !7 + %11 = load ptr, ptr %10, align 8, !dbg !7 + %12 = load ptr, ptr undef, align 8, !dbg !7 + %13 = bitcast ptr %this to ptr, !dbg !7 + %sunkaddr3 = getelementptr inbounds i8, ptr %13, i64 40, !dbg !7 + %14 = bitcast ptr %sunkaddr3 to ptr, !dbg !7 + %15 = load ptr, ptr %14, align 8, !dbg !7 br i1 undef, label %if.then.i.i775, label %cond.true.i.i777, !dbg !7 if.then.i.i775: ; preds = %if.end.i856 - %add.ptr.i.i774 = getelementptr inbounds %"class.llvm::Loop"*, %"class.llvm::Loop"** %11, i64 %__n, !dbg !7 + %add.ptr.i.i774 = getelementptr inbounds ptr, ptr %11, i64 %__n, !dbg !7 br label %_ZNKSt15_Deque_iteratorIPN4llvm4LoopERS2_PS2_EplEl.exit796, !dbg !7 cond.true.i.i777: ; preds = %if.end.i856 - %16 = load %"class.llvm::Loop"**, %"class.llvm::Loop"*** undef, align 8, !dbg !7 - %.pre1043 = ptrtoint %"class.llvm::Loop"** %16 to i64, !dbg !7 + %16 = load ptr, ptr undef, align 8, !dbg !7 + %.pre1043 = ptrtoint ptr %16 to i64, !dbg !7 br label %_ZNKSt15_Deque_iteratorIPN4llvm4LoopERS2_PS2_EplEl.exit796 _ZNKSt15_Deque_iteratorIPN4llvm4LoopERS2_PS2_EplEl.exit796: ; preds = %cond.true.i.i777, %if.then.i.i775 %sub.ptr.rhs.cast3.i.i.i.i.i.i.i.i.i690.pre-phi = phi i64 [ undef, %if.then.i.i775 ], [ %.pre1043, %cond.true.i.i777 ], !dbg !7 - %__tmp.sroa.13.0.i788 = phi %"class.llvm::Loop"*** [ %15, %if.then.i.i775 ], [ undef, %cond.true.i.i777 ], !dbg !7 - %__tmp.sroa.10.0.i789 = phi %"class.llvm::Loop"** [ %12, %if.then.i.i775 ], [ undef, %cond.true.i.i777 ], !dbg !7 - %storemerge.i.i791 = phi %"class.llvm::Loop"** [ %add.ptr.i.i774, %if.then.i.i775 ], [ undef, %cond.true.i.i777 ], !dbg !7 - %17 = ptrtoint %"class.llvm::Loop"** %11 to i64, !dbg !7 - %sub.ptr.lhs.cast.i.i.i.i.i.i.i.i.i685 = ptrtoint %"class.llvm::Loop"*** %__tmp.sroa.13.0.i788 to i64, !dbg !7 - %sub.ptr.rhs.cast.i.i.i.i.i.i.i.i.i686 = ptrtoint %"class.llvm::Loop"*** %15 to i64, !dbg !7 + %__tmp.sroa.13.0.i788 = phi ptr [ %15, %if.then.i.i775 ], [ undef, %cond.true.i.i777 ], !dbg !7 + %__tmp.sroa.10.0.i789 = phi ptr [ %12, %if.then.i.i775 ], [ undef, %cond.true.i.i777 ], !dbg !7 + %storemerge.i.i791 = phi ptr [ %add.ptr.i.i774, %if.then.i.i775 ], [ undef, %cond.true.i.i777 ], !dbg !7 + %17 = ptrtoint ptr %11 to i64, !dbg !7 + %sub.ptr.lhs.cast.i.i.i.i.i.i.i.i.i685 = ptrtoint ptr %__tmp.sroa.13.0.i788 to i64, !dbg !7 + %sub.ptr.rhs.cast.i.i.i.i.i.i.i.i.i686 = ptrtoint ptr %15 to i64, !dbg !7 %sub.ptr.sub.i.i.i.i.i.i.i.i.i687 = sub i64 %sub.ptr.lhs.cast.i.i.i.i.i.i.i.i.i685, %sub.ptr.rhs.cast.i.i.i.i.i.i.i.i.i686, !dbg !7 %sub.i.i.i.i.i.i.i.i.i688 = shl i64 %sub.ptr.sub.i.i.i.i.i.i.i.i.i687, 3, !dbg !7 - %sub.ptr.lhs.cast2.i.i.i.i.i.i.i.i.i689 = ptrtoint %"class.llvm::Loop"** %storemerge.i.i791 to i64, !dbg !7 + %sub.ptr.lhs.cast2.i.i.i.i.i.i.i.i.i689 = ptrtoint ptr %storemerge.i.i791 to i64, !dbg !7 %sub.ptr.sub4.i.i.i.i.i.i.i.i.i691 = sub i64 %sub.ptr.lhs.cast2.i.i.i.i.i.i.i.i.i689, %sub.ptr.rhs.cast3.i.i.i.i.i.i.i.i.i690.pre-phi, !dbg !7 %sub.ptr.div5.i.i.i.i.i.i.i.i.i692 = ashr exact i64 %sub.ptr.sub4.i.i.i.i.i.i.i.i.i691, 3, !dbg !7 - %sub.ptr.lhs.cast7.i.i.i.i.i.i.i.i.i693 = ptrtoint %"class.llvm::Loop"** %12 to i64, !dbg !7 + %sub.ptr.lhs.cast7.i.i.i.i.i.i.i.i.i693 = ptrtoint ptr %12 to i64, !dbg !7 %sub.ptr.sub9.i.i.i.i.i.i.i.i.i695 = sub i64 %sub.ptr.lhs.cast7.i.i.i.i.i.i.i.i.i693, %17, !dbg !7 %sub.ptr.div10.i.i.i.i.i.i.i.i.i696 = ashr exact i64 %sub.ptr.sub9.i.i.i.i.i.i.i.i.i695, 3, !dbg !7 %mul.i.i.i.i.i.i.i.i.i697 = add nsw i64 %sub.ptr.div10.i.i.i.i.i.i.i.i.i696, -64, !dbg !7 @@ -105,33 +105,33 @@ br i1 %cmp27.i.i.i.i.i.i.i.i700, label %for.body.i.i.i.i.i.i.i.i711.preheader, label %_ZSt22__uninitialized_move_aISt15_Deque_iteratorIPN4llvm4LoopERS3_PS3_ES6_SaIS3_EET0_T_S9_S8_RT1_.exit737, !dbg !7 for.body.i.i.i.i.i.i.i.i711.preheader: ; preds = %_ZNKSt15_Deque_iteratorIPN4llvm4LoopERS2_PS2_EplEl.exit796 - %18 = load %"class.llvm::Loop"*, %"class.llvm::Loop"** %11, align 8, !dbg !7 - store %"class.llvm::Loop"* %18, %"class.llvm::Loop"** %add.ptr.i.i.i.i859, align 8, !dbg !7 + %18 = load ptr, ptr %11, align 8, !dbg !7 + store ptr %18, ptr %add.ptr.i.i.i.i859, align 8, !dbg !7 ret void _ZSt22__uninitialized_move_aISt15_Deque_iteratorIPN4llvm4LoopERS3_PS3_ES6_SaIS3_EET0_T_S9_S8_RT1_.exit737: ; preds = %_ZNKSt15_Deque_iteratorIPN4llvm4LoopERS2_PS2_EplEl.exit796 - %19 = ptrtoint %"class.llvm::Loop"** %storemerge.i.i791 to i64, !dbg !7 - %20 = ptrtoint %"class.llvm::Loop"*** %__tmp.sroa.13.0.i788 to i64, !dbg !7 - %21 = bitcast %"class.std::deque"* %this to i8*, !dbg !7 - %sunkaddr4 = getelementptr inbounds i8, i8* %21, i64 16, !dbg !7 - %22 = bitcast i8* %sunkaddr4 to %"class.llvm::Loop"***, !dbg !7 - store %"class.llvm::Loop"** %add.ptr.i.i.i.i859, %"class.llvm::Loop"*** %22, align 8, !dbg !7 - store %"class.llvm::Loop"** %2, %"class.llvm::Loop"*** undef, align 8, !dbg !7 - store %"class.llvm::Loop"** %6, %"class.llvm::Loop"*** undef, align 8, !dbg !7 - %23 = bitcast %"class.std::deque"* %this to i8*, !dbg !7 - %sunkaddr5 = getelementptr inbounds i8, i8* %23, i64 40, !dbg !7 - %24 = bitcast i8* %sunkaddr5 to %"class.llvm::Loop"****, !dbg !7 - store %"class.llvm::Loop"*** %5, %"class.llvm::Loop"**** %24, align 8, !dbg !7 - %25 = bitcast %"struct.std::_Deque_iterator"* %__pos to i8*, !dbg !7 - %sunkaddr6 = getelementptr inbounds i8, i8* %25, i64 24, !dbg !7 - %26 = bitcast i8* %sunkaddr6 to %"class.llvm::Loop"****, !dbg !7 - %27 = load %"class.llvm::Loop"***, %"class.llvm::Loop"**** %26, align 8, !dbg !7 - call void @llvm.dbg.value(metadata %"class.llvm::Loop"** %2, metadata !8, metadata !DIExpression(DW_OP_LLVM_fragment, 64, 64)), !dbg !7 - %sub.ptr.lhs.cast.i.i.i597 = ptrtoint %"class.llvm::Loop"*** %27 to i64, !dbg !7 + %19 = ptrtoint ptr %storemerge.i.i791 to i64, !dbg !7 + %20 = ptrtoint ptr %__tmp.sroa.13.0.i788 to i64, !dbg !7 + %21 = bitcast ptr %this to ptr, !dbg !7 + %sunkaddr4 = getelementptr inbounds i8, ptr %21, i64 16, !dbg !7 + %22 = bitcast ptr %sunkaddr4 to ptr, !dbg !7 + store ptr %add.ptr.i.i.i.i859, ptr %22, align 8, !dbg !7 + store ptr %2, ptr undef, align 8, !dbg !7 + store ptr %6, ptr undef, align 8, !dbg !7 + %23 = bitcast ptr %this to ptr, !dbg !7 + %sunkaddr5 = getelementptr inbounds i8, ptr %23, i64 40, !dbg !7 + %24 = bitcast ptr %sunkaddr5 to ptr, !dbg !7 + store ptr %5, ptr %24, align 8, !dbg !7 + %25 = bitcast ptr %__pos to ptr, !dbg !7 + %sunkaddr6 = getelementptr inbounds i8, ptr %25, i64 24, !dbg !7 + %26 = bitcast ptr %sunkaddr6 to ptr, !dbg !7 + %27 = load ptr, ptr %26, align 8, !dbg !7 + call void @llvm.dbg.value(metadata ptr %2, metadata !8, metadata !DIExpression(DW_OP_LLVM_fragment, 64, 64)), !dbg !7 + %sub.ptr.lhs.cast.i.i.i597 = ptrtoint ptr %27 to i64, !dbg !7 %sub.ptr.sub.i.i.i599 = sub i64 %sub.ptr.lhs.cast.i.i.i597, %20, !dbg !7 %sub.i.i.i600 = shl i64 %sub.ptr.sub.i.i.i599, 3, !dbg !7 %sub.ptr.div5.i.i.i604 = ashr exact i64 undef, 3, !dbg !7 - %sub.ptr.lhs.cast7.i.i.i605 = ptrtoint %"class.llvm::Loop"** %__tmp.sroa.10.0.i789 to i64, !dbg !7 + %sub.ptr.lhs.cast7.i.i.i605 = ptrtoint ptr %__tmp.sroa.10.0.i789 to i64, !dbg !7 %sub.ptr.sub9.i.i.i607 = sub i64 %sub.ptr.lhs.cast7.i.i.i605, %19, !dbg !7 %sub.ptr.div10.i.i.i608 = ashr exact i64 %sub.ptr.sub9.i.i.i607, 3, !dbg !7 %mul.i.i.i609 = add nsw i64 %sub.ptr.div10.i.i.i608, -64, !dbg !7 @@ -222,7 +222,7 @@ body: | CFI_INSTRUCTION offset $r14, -32 CFI_INSTRUCTION offset $r15, -24 CFI_INSTRUCTION offset $rbp, -16 - renamable $r10 = MOV64rm undef renamable $rax, 1, $noreg, 0, $noreg, debug-instr-number 1, debug-location !7 :: (load 8 from `%"class.llvm::Loop"*** undef`) + renamable $r10 = MOV64rm undef renamable $rax, 1, $noreg, 0, $noreg, debug-instr-number 1, debug-location !7 :: (load 8 from `ptr undef`) renamable $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags TEST8rr renamable $al, renamable $al, implicit-def $eflags, implicit killed $eax, debug-location !7 MOV64mr $rsp, 1, $noreg, -8, $noreg, renamable $r10 :: (store 8 into %stack.0) @@ -231,7 +231,7 @@ body: | bb.2.if.then.i851: liveins: $rdi, $rdx, $rsi - renamable $r10 = MOV64rm undef renamable $rax, 1, $noreg, 0, $noreg, debug-location !7 :: (load 8 from `%"class.llvm::Loop"*** undef`) + renamable $r10 = MOV64rm undef renamable $rax, 1, $noreg, 0, $noreg, debug-location !7 :: (load 8 from `ptr undef`) renamable $r9 = MOV64rm renamable $rdi, 1, $noreg, 40, $noreg, debug-location !7 :: (load 8 from %ir.4) JMP_1 %bb.3 @@ -246,11 +246,11 @@ body: | renamable $rax = MOV64rm renamable $rdi, 1, $noreg, 16, $noreg, debug-location !7 :: (load 8 from %ir._M_cur6.i) renamable $r15 = LEA64r $noreg, 8, renamable $rdx, 0, $noreg, debug-location !7 - MOV64mr undef renamable $rax, 1, $noreg, 0, $noreg, renamable $r10, debug-location !7 :: (store 8 into `%"class.llvm::Loop"*** undef`) + MOV64mr undef renamable $rax, 1, $noreg, 0, $noreg, renamable $r10, debug-location !7 :: (store 8 into `ptr undef`) MOV64mr renamable $rsi, 1, $noreg, 24, $noreg, renamable $r9, debug-location !7 :: (store 8 into %ir.8) renamable $r13 = MOV64rm renamable $rdi, 1, $noreg, 16, $noreg, debug-location !7 :: (load 8 from %ir.10) renamable $r11 = MOV64rm renamable $rdi, 1, $noreg, 40, $noreg, debug-location !7 :: (load 8 from %ir.14) - renamable $r8 = MOV64rm undef renamable $rax, 1, $noreg, 0, $noreg, debug-location !7 :: (load 8 from `%"class.llvm::Loop"*** undef`) + renamable $r8 = MOV64rm undef renamable $rax, 1, $noreg, 0, $noreg, debug-location !7 :: (load 8 from `ptr undef`) renamable $ebp = XOR32rr undef $ebp, undef $ebp, implicit-def dead $eflags TEST8rr renamable $bpl, renamable $bpl, implicit-def $eflags, implicit killed $ebp, debug-location !7 JCC_1 %bb.5, 5, implicit killed $eflags, debug-location !7 @@ -265,7 +265,7 @@ body: | bb.5.cond.true.i.i777: liveins: $rax, $rdi, $rdx, $rsi, $r8, $r9, $r10, $r11, $r13, $r15 - renamable $r12 = MOV64rm undef renamable $rax, 1, $noreg, 0, $noreg, debug-location !7 :: (load 8 from `%"class.llvm::Loop"*** undef`) + renamable $r12 = MOV64rm undef renamable $rax, 1, $noreg, 0, $noreg, debug-location !7 :: (load 8 from `ptr undef`) renamable $r14 = IMPLICIT_DEF debug-location !7 bb.6._ZNKSt15_Deque_iteratorIPN4llvm4LoopERS2_PS2_EplEl.exit796: @@ -299,8 +299,8 @@ body: | MOV64mr renamable $rdi, 1, $noreg, 16, $noreg, killed renamable $rax, debug-location !7 :: (store 8 into %ir.22) renamable $rax = MOV64rm $rsp, 1, $noreg, -8, $noreg :: (load 8 from %stack.0) - MOV64mr undef renamable $rax, 1, $noreg, 0, $noreg, killed renamable $rax, debug-location !7 :: (store 8 into `%"class.llvm::Loop"*** undef`) - MOV64mr undef renamable $rax, 1, $noreg, 0, $noreg, killed renamable $r10, debug-location !7 :: (store 8 into `%"class.llvm::Loop"*** undef`) + MOV64mr undef renamable $rax, 1, $noreg, 0, $noreg, killed renamable $rax, debug-location !7 :: (store 8 into `ptr undef`) + MOV64mr undef renamable $rax, 1, $noreg, 0, $noreg, killed renamable $r10, debug-location !7 :: (store 8 into `ptr undef`) MOV64mr killed renamable $rdi, 1, $noreg, 40, $noreg, killed renamable $r9, debug-location !7 :: (store 8 into %ir.24) renamable $rax = MOV64rm killed renamable $rsi, 1, $noreg, 24, $noreg, debug-location !7 :: (load 8 from %ir.26) DBG_INSTR_REF !8, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 64, 64), dbg-instr-ref(1, 0), debug-location !7 diff --git a/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir b/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir index 7d074b3faefc..cece656d0897 100644 --- a/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir @@ -133,8 +133,8 @@ body: | %5:gr32 = PHI %15, %bb.0, %7, %bb.5, debug-location !13 %6:gr32 = PHI %15, %bb.0, %13, %bb.5, debug-location !13 %16:gr64 = ADD64rr %4, %4, implicit-def dead $eflags, debug-location !13 - MOV32mr %17, 1, $noreg, 0, $noreg, %5, debug-location !13 :: (store (s32) into `i32* undef`, align 8) - MOV64mr %18, 1, $noreg, 0, $noreg, killed %16, debug-location !13 :: (store (s64) into `i64* undef`) + MOV32mr %17, 1, $noreg, 0, $noreg, %5, debug-location !13 :: (store (s32) into `ptr undef`, align 8) + MOV64mr %18, 1, $noreg, 0, $noreg, killed %16, debug-location !13 :: (store (s64) into `ptr undef`) %20:gr8 = COPY %19.sub_8bit TEST8rr %20, %20, implicit-def $eflags, debug-location !13 JCC_1 %bb.3, 5, implicit $eflags, debug-location !13 @@ -146,10 +146,10 @@ body: | successors: %bb.4, %bb.5 %7:gr32 = PHI %5, %bb.1, %21, %bb.2, debug-location !13 - MOV32mr %22, 1, $noreg, 0, $noreg, %7, debug-location !13 :: (store (s32) into `i32* undef`, align 8) - %8:gr64 = MOV64rm %23, 1, $noreg, 0, $noreg, debug-location !13 :: (load (s64) from `i64* undef`) - MOV32mr %24, 1, $noreg, 0, $noreg, %3, debug-location !13 :: (store (s32) into `i32* undef`, align 8) - MOV64mi32 %25, 1, $noreg, 0, $noreg, 0, debug-location !13 :: (store (s64) into `i64* undef`) + MOV32mr %22, 1, $noreg, 0, $noreg, %7, debug-location !13 :: (store (s32) into `ptr undef`, align 8) + %8:gr64 = MOV64rm %23, 1, $noreg, 0, $noreg, debug-location !13 :: (load (s64) from `ptr undef`) + MOV32mr %24, 1, $noreg, 0, $noreg, %3, debug-location !13 :: (store (s32) into `ptr undef`, align 8) + MOV64mi32 %25, 1, $noreg, 0, $noreg, 0, debug-location !13 :: (store (s64) into `ptr undef`) %28:gr8 = COPY %19.sub_8bit TEST8rr %28, %28, implicit-def $eflags, debug-location !13 JCC_1 %bb.5, 5, implicit $eflags, debug-location !13 @@ -157,15 +157,15 @@ body: | bb.4: %29:gr64 = ADD64rr %2, %2, implicit-def dead $eflags, debug-location !13 - MOV64mr %30, 1, $noreg, 0, $noreg, killed %29, debug-location !13 :: (store (s64) into `i64* undef`) + MOV64mr %30, 1, $noreg, 0, $noreg, killed %29, debug-location !13 :: (store (s64) into `ptr undef`) bb.5: - %9:gr32 = MOV32rm %26, 1, $noreg, 0, $noreg, debug-location !13 :: (load (s32) from `i32* undef`, align 8) - %10:gr64 = MOV64rm %31, 1, $noreg, 0, $noreg, debug-location !13 :: (load (s64) from `i64* undef`) + %9:gr32 = MOV32rm %26, 1, $noreg, 0, $noreg, debug-location !13 :: (load (s32) from `ptr undef`, align 8) + %10:gr64 = MOV64rm %31, 1, $noreg, 0, $noreg, debug-location !13 :: (load (s64) from `ptr undef`) %12:gr64 = ADD64rr %0, %0, implicit-def dead $eflags, debug-location !13 - MOV32mr %32, 1, $noreg, 0, $noreg, %1, debug-location !13 :: (store (s32) into `i32* undef`, align 8) - MOV64mr %33, 1, $noreg, 0, $noreg, %12, debug-location !13 :: (store (s64) into `i64* undef`) - %11:gr32 = MOV32rm %34, 1, $noreg, 0, $noreg, debug-location !13 :: (load (s32) from `i32* undef`, align 8) + MOV32mr %32, 1, $noreg, 0, $noreg, %1, debug-location !13 :: (store (s32) into `ptr undef`, align 8) + MOV64mr %33, 1, $noreg, 0, $noreg, %12, debug-location !13 :: (store (s64) into `ptr undef`) + %11:gr32 = MOV32rm %34, 1, $noreg, 0, $noreg, debug-location !13 :: (load (s32) from `ptr undef`, align 8) ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !13 $rdi = COPY %35, debug-location !13 $rsi = COPY %36, debug-location !13 diff --git a/llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir b/llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir index 9d11eb77eec2..e6bb87b9e2a4 100644 --- a/llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir @@ -34,27 +34,27 @@ %class._Tree = type { i8 } %class._Tree_const_iterator = type { %class._Tree_unchecked_const_iterator } - %class._Tree_unchecked_const_iterator = type { %struct._Iterator_base0, i32* } + %class._Tree_unchecked_const_iterator = type { %struct._Iterator_base0, ptr } %struct._Iterator_base0 = type { i32 } - define i32 @main({ i32, i32* } %call.i) !dbg !6 { + define i32 @main({ i32, ptr } %call.i) !dbg !6 { entry: call void @llvm.dbg.value(metadata i32 2, metadata !10, metadata !DIExpression()), !dbg !12 - %call.i1 = call { i32, i32* } undef(%class._Tree* null) - %0 = extractvalue { i32, i32* } %call.i, 1 - call void @llvm.dbg.value(metadata i32* %0, metadata !13, metadata !DIExpression(DW_OP_LLVM_fragment, 64, 64)), !dbg !15 - %call.i.i.i.i.i = call i8 undef(i32* null), !dbg !15 + %call.i1 = call { i32, ptr } undef(ptr null) + %0 = extractvalue { i32, ptr } %call.i, 1 + call void @llvm.dbg.value(metadata ptr %0, metadata !13, metadata !DIExpression(DW_OP_LLVM_fragment, 64, 64)), !dbg !15 + %call.i.i.i.i.i = call i8 undef(ptr null), !dbg !15 br i1 undef, label %_Z17do_insert_cv_testI5_TreeEvv.exit, label %if.then.i.i.i.i.i if.then.i.i.i.i.i: - %call3.i.i.i.i.i = call i32* undef(i32* null) - call void @llvm.dbg.value(metadata i32* %call3.i.i.i.i.i, metadata !13, metadata !DIExpression(DW_OP_LLVM_fragment, 64, 64)), !dbg !15 + %call3.i.i.i.i.i = call ptr undef(ptr null) + call void @llvm.dbg.value(metadata ptr %call3.i.i.i.i.i, metadata !13, metadata !DIExpression(DW_OP_LLVM_fragment, 64, 64)), !dbg !15 br label %_Z17do_insert_cv_testI5_TreeEvv.exit _Z17do_insert_cv_testI5_TreeEvv.exit: - %_First.sroa.2.0.i.i = phi i32* [ %0, %entry ], [ %call3.i.i.i.i.i, %if.then.i.i.i.i.i ] - call void @llvm.dbg.value(metadata i32* %_First.sroa.2.0.i.i, metadata !13, metadata !DIExpression(DW_OP_LLVM_fragment, 64, 64)), !dbg !15 - call void undef(%class._Tree_const_iterator* null, i32 0, i32* %_First.sroa.2.0.i.i), !dbg !16 + %_First.sroa.2.0.i.i = phi ptr [ %0, %entry ], [ %call3.i.i.i.i.i, %if.then.i.i.i.i.i ] + call void @llvm.dbg.value(metadata ptr %_First.sroa.2.0.i.i, metadata !13, metadata !DIExpression(DW_OP_LLVM_fragment, 64, 64)), !dbg !15 + call void undef(ptr null, i32 0, ptr %_First.sroa.2.0.i.i), !dbg !16 ret i32 0 } diff --git a/llvm/test/DebugInfo/MIR/InstrRef/restore-clobber-with-indirectness.mir b/llvm/test/DebugInfo/MIR/InstrRef/restore-clobber-with-indirectness.mir index aadfd3c7448b..1a2012d36f1a 100644 --- a/llvm/test/DebugInfo/MIR/InstrRef/restore-clobber-with-indirectness.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/restore-clobber-with-indirectness.mir @@ -71,7 +71,7 @@ body: | bb.0.entry: liveins: $rdi, $rdx, $rsi, $rbp, $r15, $r14, $r13, $r12, $rbx - renamable $r10 = MOV64rm undef renamable $rax, 1, $noreg, 0, $noreg, debug-instr-number 1, debug-location !7 :: (load 8 from `%"class.llvm::Loop"*** undef`) + renamable $r10 = MOV64rm undef renamable $rax, 1, $noreg, 0, $noreg, debug-instr-number 1, debug-location !7 :: (load 8 from `ptr undef`) renamable $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags DBG_VALUE $r10, 0, !8, !DIExpression(DW_OP_LLVM_fragment, 64, 64), debug-location !7 TEST8rr renamable $al, renamable $al, implicit-def $eflags, implicit killed $eax, debug-location !7 diff --git a/llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir b/llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir index 56958efcefb8..47a7b460e43e 100644 --- a/llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir @@ -17,7 +17,7 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" - define hidden fastcc i64 @amd64_push_arguments(i32 *%regcache, i32 *%args) unnamed_addr !dbg !4 { + define hidden fastcc i64 @amd64_push_arguments(ptr %regcache, ptr %args) unnamed_addr !dbg !4 { ret i64 0 } @@ -259,7 +259,7 @@ body: | %10:gr32 = PHI %4, %bb.20, %4, %bb.17, %6, %bb.16, debug-location !9 %11:gr64 = PHI %8, %bb.20, undef %45:gr64, %bb.17, undef %47:gr64, %bb.16 %12:gr32 = PHI %42, %bb.20, %46, %bb.17, %48, %bb.16, debug-location !9 - %49:gr32 = MOV32rm killed %11, 1, $noreg, 0, $noreg, debug-location !9 :: (load (s32) from `i32 *undef`) + %49:gr32 = MOV32rm killed %11, 1, $noreg, 0, $noreg, debug-location !9 :: (load (s32) from `ptr undef`) ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !9 $rdi = COPY %50, debug-location !9 CALL64pcrel32 target-flags(x86-plt) &memcpy, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit undef $rsi, implicit undef $rdx, implicit-def $rsp, implicit-def $ssp, implicit-def dead $rax, debug-location !9 diff --git a/llvm/test/DebugInfo/MIR/InstrRef/win32-chkctk-modifies-esp.mir b/llvm/test/DebugInfo/MIR/InstrRef/win32-chkctk-modifies-esp.mir index 238556f7fe00..ed1ba590d746 100644 --- a/llvm/test/DebugInfo/MIR/InstrRef/win32-chkctk-modifies-esp.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/win32-chkctk-modifies-esp.mir @@ -18,25 +18,25 @@ %struct.incomplete_struct = type { i32 } @"\01?multi_dim_arr@@3PAY146DA" = global [2 x [5 x [7 x i8]]] zeroinitializer, align 1, !dbg !0 - @"\01?p_incomplete_struct_arr@@3PAY02Uincomplete_struct@@A" = global [3 x i8]* null, align 4, !dbg !6 + @"\01?p_incomplete_struct_arr@@3PAY02Uincomplete_struct@@A" = global ptr null, align 4, !dbg !6 @"\01?incomplete_struct_arr@@3PAUincomplete_struct@@A" = global [3 x %struct.incomplete_struct] zeroinitializer, align 4, !dbg !16 @"\01?typedef_arr@@3SDHD" = constant [4 x i32] zeroinitializer, align 4, !dbg !18 define void @"\01?foo@@YAXH@Z"(i32 %x) !dbg !35 { entry: %x.addr = alloca i32, align 4 - %saved_stack = alloca i8*, align 4 - store i32 %x, i32* %x.addr, align 4 - call void @llvm.dbg.declare(metadata i32* %x.addr, metadata !38, metadata !DIExpression()), !dbg !39 - %0 = load i32, i32* %x.addr, align 4, !dbg !40 - %1 = call i8* @llvm.stacksave(), !dbg !41 - store i8* %1, i8** %saved_stack, align 4, !dbg !41 + %saved_stack = alloca ptr, align 4 + store i32 %x, ptr %x.addr, align 4 + call void @llvm.dbg.declare(metadata ptr %x.addr, metadata !38, metadata !DIExpression()), !dbg !39 + %0 = load i32, ptr %x.addr, align 4, !dbg !40 + %1 = call ptr @llvm.stacksave(), !dbg !41 + store ptr %1, ptr %saved_stack, align 4, !dbg !41 %vla = alloca i32, i32 %0, align 4, !dbg !41 - call void @llvm.dbg.declare(metadata i32* %vla, metadata !42, metadata !DIExpression(DW_OP_deref)), !dbg !46 - %arrayidx1 = bitcast i32* %vla to i32*, !dbg !47 - store i32 0, i32* %arrayidx1, align 4, !dbg !48 - %2 = load i8*, i8** %saved_stack, align 4, !dbg !49 - call void @llvm.stackrestore(i8* %2), !dbg !49 + call void @llvm.dbg.declare(metadata ptr %vla, metadata !42, metadata !DIExpression(DW_OP_deref)), !dbg !46 + %arrayidx1 = bitcast ptr %vla to ptr, !dbg !47 + store i32 0, ptr %arrayidx1, align 4, !dbg !48 + %2 = load ptr, ptr %saved_stack, align 4, !dbg !49 + call void @llvm.stackrestore(ptr %2), !dbg !49 ret void, !dbg !49 } @@ -44,10 +44,10 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) ; Function Attrs: nofree nosync nounwind willreturn - declare i8* @llvm.stacksave() + declare ptr @llvm.stacksave() ; Function Attrs: nofree nosync nounwind willreturn - declare void @llvm.stackrestore(i8*) + declare void @llvm.stackrestore(ptr) !llvm.dbg.cu = !{!2} !llvm.module.flags = !{!32, !33} diff --git a/llvm/test/DebugInfo/MIR/InstrRef/x86-drop-compare-inst.mir b/llvm/test/DebugInfo/MIR/InstrRef/x86-drop-compare-inst.mir index 415b336fc480..7a782625188d 100644 --- a/llvm/test/DebugInfo/MIR/InstrRef/x86-drop-compare-inst.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/x86-drop-compare-inst.mir @@ -17,19 +17,19 @@ %"class.std::vector.534" = type { %"struct.std::_Vector_base.535" } %"struct.std::_Vector_base.535" = type { %"struct.std::_Vector_base>::_Vector_impl" } - %"struct.std::_Vector_base>::_Vector_impl" = type { i8*, i8*, i8* } + %"struct.std::_Vector_base>::_Vector_impl" = type { ptr, ptr, ptr } ; Function Attrs: nofree nosync nounwind readnone speculatable willreturn declare void @llvm.dbg.declare(metadata, metadata, metadata) #0 define hidden fastcc void @soup() unnamed_addr !dbg !3 { _ZN4llvm11raw_ostreamlsEPKc.exit2752: - %0 = load %"class.std::vector.534"*, %"class.std::vector.534"** undef, align 8, !dbg !7 - %1 = load i8*, i8** undef, align 8, !dbg !7 - %_M_start.i2756 = getelementptr inbounds %"class.std::vector.534", %"class.std::vector.534"* %0, i64 undef, i32 0, i32 0, i32 0, !dbg !7 - %2 = load i8*, i8** %_M_start.i2756, align 8, !dbg !7 - %sub.ptr.lhs.cast.i2757 = ptrtoint i8* %1 to i64, !dbg !7 - %sub.ptr.rhs.cast.i2758 = ptrtoint i8* %2 to i64, !dbg !7 + %0 = load ptr, ptr undef, align 8, !dbg !7 + %1 = load ptr, ptr undef, align 8, !dbg !7 + %_M_start.i2756 = getelementptr inbounds %"class.std::vector.534", ptr %0, i64 undef, i32 0, i32 0, i32 0, !dbg !7 + %2 = load ptr, ptr %_M_start.i2756, align 8, !dbg !7 + %sub.ptr.lhs.cast.i2757 = ptrtoint ptr %1 to i64, !dbg !7 + %sub.ptr.rhs.cast.i2758 = ptrtoint ptr %2 to i64, !dbg !7 %sub.ptr.sub.i2759 = sub i64 %sub.ptr.lhs.cast.i2757, %sub.ptr.rhs.cast.i2758, !dbg !7 %conv373 = trunc i64 %sub.ptr.sub.i2759 to i32, !dbg !7 call void @llvm.dbg.value(metadata i32 %conv373, metadata !8, metadata !DIExpression()), !dbg !7 @@ -80,7 +80,7 @@ body: | successors: %bb.1(0x30000000), %bb.2(0x50000000) %1:gr64 = IMPLICIT_DEF - %0:gr64 = MOV64rm killed %1, 1, $noreg, 0, $noreg, debug-location !7 :: (load (s64) from `i8** undef`) + %0:gr64 = MOV64rm killed %1, 1, $noreg, 0, $noreg, debug-location !7 :: (load (s64) from `ptr undef`) %2:gr32 = COPY %0.sub_32bit, debug-location !7 %3:gr32 = SUB32rm %2, %0, 1, $noreg, 0, $noreg, implicit-def $eflags, debug-instr-number 1, debug-location !7 :: (load (s32) from %ir._M_start.i2756, align 8) DBG_INSTR_REF !8, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !7 diff --git a/llvm/test/DebugInfo/MIR/InstrRef/x86-fp-stackifier-drop-locations.mir b/llvm/test/DebugInfo/MIR/InstrRef/x86-fp-stackifier-drop-locations.mir index 404ca0c8a42c..be12082c45b9 100644 --- a/llvm/test/DebugInfo/MIR/InstrRef/x86-fp-stackifier-drop-locations.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/x86-fp-stackifier-drop-locations.mir @@ -41,13 +41,13 @@ %add = fadd x86_fp80 %a, %b, !dbg !21 call void @llvm.dbg.value(metadata x86_fp80 %add, metadata !17, metadata !DIExpression()), !dbg !20 call void @llvm.dbg.value(metadata x86_fp80 undef, metadata !18, metadata !DIExpression()), !dbg !20 - %call = tail call x86_fp80 bitcast (x86_fp80 (...)* @ext to x86_fp80 ()*)() #3, !dbg !22 + %call = tail call x86_fp80 @ext() #3, !dbg !22 %mul = fmul x86_fp80 %add, %call, !dbg !23 call void @llvm.dbg.value(metadata x86_fp80 %mul, metadata !17, metadata !DIExpression()), !dbg !20 - %call2 = tail call x86_fp80 bitcast (x86_fp80 (...)* @ext to x86_fp80 ()*)() #3, !dbg !24 + %call2 = tail call x86_fp80 @ext() #3, !dbg !24 call void @llvm.dbg.value(metadata x86_fp80 undef, metadata !18, metadata !DIExpression()), !dbg !20 %cmp = fcmp olt x86_fp80 %mul, 0xK4001A000000000000000, !dbg !25 - %0 = load x86_fp80, x86_fp80* @glob, align 4, !dbg !27 + %0 = load x86_fp80, ptr @glob, align 4, !dbg !27 %add3 = fadd x86_fp80 %mul, %0, !dbg !27 %a.addr.0 = select i1 %cmp, x86_fp80 %add3, x86_fp80 %mul, !dbg !27 %add1 = fadd x86_fp80 %b, %c, !dbg !28 @@ -177,7 +177,7 @@ body: | renamable $fp0 = nofpexcept DIV_Fp80 killed renamable $fp1, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw, debug-instr-number 19, debug-location !29 renamable $fp0 = nofpexcept SUB_Fp80 killed renamable $fp3, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw, debug-instr-number 20, debug-location !30 ;; Edited in: - renamable $fp0 = ADD_Fp64m killed renamable $fp0, killed $esp, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw, debug-instr-number 21, :: (load (s64) from `i32 *undef`) + renamable $fp0 = ADD_Fp64m killed renamable $fp0, killed $esp, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw, debug-instr-number 21, :: (load (s64) from `ptr undef`) RET 0, killed renamable $fp0, debug-location !31 ... diff --git a/llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup.mir b/llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup.mir index b84f86c032cc..2e28804682ba 100644 --- a/llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup.mir @@ -74,7 +74,7 @@ body: | renamable $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags renamable $ecx = nsw ADD32rr renamable $ecx, renamable $eax, implicit-def dead $eflags, implicit killed $rax, implicit killed $rcx, implicit-def $rcx, debug-instr-number 1 ; ATOM: LEA64_32r {{.*}} debug-instr-number 2 - renamable $eax = MOV32rm killed renamable $rcx, 1, $noreg, 0, $noreg :: (load (s32) from `i32 *undef`) + renamable $eax = MOV32rm killed renamable $rcx, 1, $noreg, 0, $noreg :: (load (s32) from `ptr undef`) RET64 $eax ... diff --git a/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-copy-sub-reg.mir b/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-copy-sub-reg.mir index 82ce923141e5..013c7086eb56 100644 --- a/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-copy-sub-reg.mir +++ b/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-copy-sub-reg.mir @@ -30,15 +30,15 @@ target triple = "mips64-unknown-linux" ; Function Attrs: nounwind - define signext i32 @f1(i32 signext %a, i8* %str) local_unnamed_addr !dbg !8 { + define signext i32 @f1(i32 signext %a, ptr %str) local_unnamed_addr !dbg !8 { entry: call void @llvm.dbg.value(metadata i32 %a, metadata !16, metadata !DIExpression()), !dbg !18 - call void @llvm.dbg.value(metadata i8* %str, metadata !17, metadata !DIExpression()), !dbg !18 - %call = tail call fastcc signext i32 @foo(i8* %str, i32 signext %a, i32 signext 0), !dbg !18 + call void @llvm.dbg.value(metadata ptr %str, metadata !17, metadata !DIExpression()), !dbg !18 + %call = tail call fastcc signext i32 @foo(ptr %str, i32 signext %a, i32 signext 0), !dbg !18 ret i32 %call, !dbg !18 } - declare !dbg !21 fastcc signext i32 @foo(i8*, i32 signext, i32 signext) local_unnamed_addr + declare !dbg !21 fastcc signext i32 @foo(ptr, i32 signext, i32 signext) local_unnamed_addr ; Function Attrs: nounwind readnone speculatable willreturn declare void @llvm.dbg.value(metadata, metadata, metadata) diff --git a/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-delay-slot-interpretation-64bit.mir b/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-delay-slot-interpretation-64bit.mir index a7acf6f69ed3..b35c3dea8246 100644 --- a/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-delay-slot-interpretation-64bit.mir +++ b/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-delay-slot-interpretation-64bit.mir @@ -34,15 +34,15 @@ target datalayout = "E-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128" target triple = "mips64-unknown-linux-gnu" ; Function Attrs: noinline nounwind - define void @set(i32* nocapture %adr, i32 signext %val) local_unnamed_addr !dbg !13 { + define void @set(ptr nocapture %adr, i32 signext %val) local_unnamed_addr !dbg !13 { entry: - call void @llvm.dbg.value(metadata i32* %adr, metadata !18, metadata !DIExpression()), !dbg !20 + call void @llvm.dbg.value(metadata ptr %adr, metadata !18, metadata !DIExpression()), !dbg !20 call void @llvm.dbg.value(metadata i32 %val, metadata !19, metadata !DIExpression()), !dbg !20 %inc = add nsw i32 %val, 1, !dbg !20 call void @llvm.dbg.value(metadata i32 %inc, metadata !19, metadata !DIExpression()), !dbg !20 %call = tail call signext i32 @sum(i32 signext %inc, i32 signext %inc), !dbg !20 %add = add nsw i32 %call, %inc, !dbg !20 - store i32 %add, i32* %adr, align 4, !dbg !20 + store i32 %add, ptr %adr, align 4, !dbg !20 ret void } diff --git a/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-delay-slot-interpretation.mir b/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-delay-slot-interpretation.mir index 0755b86757b5..b6eddff967b5 100644 --- a/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-delay-slot-interpretation.mir +++ b/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-delay-slot-interpretation.mir @@ -34,15 +34,15 @@ target datalayout = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64" target triple = "mips-unknown-linux-gnu" ; Function Attrs: noinline nounwind - define dso_local void @set(i32* nocapture %adr, i32 signext %val) local_unnamed_addr !dbg !12 { + define dso_local void @set(ptr nocapture %adr, i32 signext %val) local_unnamed_addr !dbg !12 { entry: - call void @llvm.dbg.value(metadata i32* %adr, metadata !17, metadata !DIExpression()), !dbg !19 + call void @llvm.dbg.value(metadata ptr %adr, metadata !17, metadata !DIExpression()), !dbg !19 call void @llvm.dbg.value(metadata i32 %val, metadata !18, metadata !DIExpression()), !dbg !19 %inc = add nsw i32 %val, 1, !dbg !19 call void @llvm.dbg.value(metadata i32 %inc, metadata !18, metadata !DIExpression()), !dbg !19 %call = tail call i32 @sum(i32 signext %inc, i32 signext %inc), !dbg !19 %add = add nsw i32 %call, %inc, !dbg !19 - store i32 %add, i32* %adr, align 4, !dbg !19 + store i32 %add, ptr %adr, align 4, !dbg !19 ret void } declare !dbg !4 dso_local i32 @sum(i32 signext, i32 signext) local_unnamed_addr diff --git a/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-param-addiu-64bit.mir b/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-param-addiu-64bit.mir index a0da42d25d11..66fa095650fa 100644 --- a/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-param-addiu-64bit.mir +++ b/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-param-addiu-64bit.mir @@ -41,7 +41,7 @@ define signext i32 @fn2(i64 signext %a) local_unnamed_addr !dbg !14 { entry: call void @llvm.dbg.value(metadata i64 %a, metadata !18, metadata !DIExpression()), !dbg !20 - tail call void bitcast (void (...)* @clobber to void ()*)(), !dbg !20 + tail call void @clobber(), !dbg !20 %add = add nsw i64 %a, 10, !dbg !20 %call = tail call signext i32 @fn1(i64 signext 44, i64 signext %a, i64 signext %add), !dbg !20 call void @llvm.dbg.value(metadata i32 %call, metadata !19, metadata !DIExpression()), !dbg !20 diff --git a/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-param-addiu.mir b/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-param-addiu.mir index 526f7928b56a..216ae0b98ed7 100644 --- a/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-param-addiu.mir +++ b/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-param-addiu.mir @@ -41,7 +41,7 @@ define dso_local i32 @fn2(i32 signext %a) local_unnamed_addr !dbg !12 { entry: call void @llvm.dbg.value(metadata i32 %a, metadata !16, metadata !DIExpression()), !dbg !18 - tail call void bitcast (void (...)* @clobber to void ()*)(), !dbg !18 + tail call void @clobber(), !dbg !18 %add = add nsw i32 %a, 10, !dbg !18 %call = tail call i32 @fn1(i32 signext 44, i32 signext %a, i32 signext %add), !dbg !18 call void @llvm.dbg.value(metadata i32 %call, metadata !17, metadata !DIExpression()), !dbg !18 diff --git a/llvm/test/DebugInfo/MIR/Mips/last-inst-bundled.mir b/llvm/test/DebugInfo/MIR/Mips/last-inst-bundled.mir index 7825bff2d410..97ff7c4589b4 100644 --- a/llvm/test/DebugInfo/MIR/Mips/last-inst-bundled.mir +++ b/llvm/test/DebugInfo/MIR/Mips/last-inst-bundled.mir @@ -33,40 +33,40 @@ entry: %condition = alloca i32, align 4 call void @llvm.dbg.value(metadata i32 %argument, metadata !12, metadata !DIExpression()), !dbg !17 - %0 = bitcast i32* %condition to i8*, !dbg !18 - call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %0), !dbg !18 - call void @llvm.dbg.value(metadata i32* %condition, metadata !13, metadata !DIExpression()), !dbg !19 - call void @set_cond(i32 signext %argument, i32* nonnull %condition), !dbg !20 - %1 = load i32, i32* %condition, align 4, !dbg !21, !tbaa !23 + %0 = bitcast ptr %condition to ptr, !dbg !18 + call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %0), !dbg !18 + call void @llvm.dbg.value(metadata ptr %condition, metadata !13, metadata !DIExpression()), !dbg !19 + call void @set_cond(i32 signext %argument, ptr nonnull %condition), !dbg !20 + %1 = load i32, ptr %condition, align 4, !dbg !21, !tbaa !23 call void @llvm.dbg.value(metadata i32 %1, metadata !13, metadata !DIExpression()), !dbg !19 %tobool = icmp eq i32 %1, 0, !dbg !21 br i1 %tobool, label %if.end, label %if.then, !dbg !27 if.then: ; preds = %entry - call void @do_something(i8* undef, i32 signext %argument), !dbg !28 + call void @do_something(ptr undef, i32 signext %argument), !dbg !28 br label %if.end, !dbg !28 if.end: ; preds = %if.then, %entry - %2 = bitcast i32* %condition to i8* - call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %2), !dbg !29 + %2 = bitcast ptr %condition to ptr + call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %2), !dbg !29 ret void, !dbg !29 } ; Function Attrs: argmemonly nounwind - declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #0 + declare void @llvm.lifetime.start.p0(i64, ptr nocapture) #0 - declare void @set_cond(i32 signext, i32*) local_unnamed_addr + declare void @set_cond(i32 signext, ptr) local_unnamed_addr - declare void @do_something(i8*, i32 signext) local_unnamed_addr + declare void @do_something(ptr, i32 signext) local_unnamed_addr ; Function Attrs: argmemonly nounwind - declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #0 + declare void @llvm.lifetime.end.p0(i64, ptr nocapture) #0 ; Function Attrs: nounwind readnone speculatable declare void @llvm.dbg.value(metadata, metadata, metadata) #1 ; Function Attrs: nounwind - declare void @llvm.stackprotector(i8*, i8**) #2 + declare void @llvm.stackprotector(ptr, ptr) #2 attributes #0 = { argmemonly nounwind } attributes #1 = { nounwind readnone speculatable } diff --git a/llvm/test/DebugInfo/MIR/Mips/live-debug-values-reg-copy.mir b/llvm/test/DebugInfo/MIR/Mips/live-debug-values-reg-copy.mir index a295e12e645f..1e848f74512d 100644 --- a/llvm/test/DebugInfo/MIR/Mips/live-debug-values-reg-copy.mir +++ b/llvm/test/DebugInfo/MIR/Mips/live-debug-values-reg-copy.mir @@ -61,7 +61,7 @@ declare void @llvm.dbg.value(metadata, metadata, metadata) #0 ; Function Attrs: nounwind - declare void @llvm.stackprotector(i8*, i8**) #1 + declare void @llvm.stackprotector(ptr, ptr) #1 attributes #0 = { nounwind readnone speculatable } attributes #1 = { nounwind } diff --git a/llvm/test/DebugInfo/MIR/X86/avoid-single-entry-value-location.mir b/llvm/test/DebugInfo/MIR/X86/avoid-single-entry-value-location.mir index 8dba058da740..8dafeb3d7e1c 100644 --- a/llvm/test/DebugInfo/MIR/X86/avoid-single-entry-value-location.mir +++ b/llvm/test/DebugInfo/MIR/X86/avoid-single-entry-value-location.mir @@ -10,10 +10,10 @@ target triple = "x86_64-unknown-linux-gnu" ; Function Attrs: noinline nounwind uwtable - define dso_local void @fn1(i8* %x) local_unnamed_addr !dbg !12 { + define dso_local void @fn1(ptr %x) local_unnamed_addr !dbg !12 { entry: - call void @llvm.dbg.value(metadata i8* %x, metadata !16, metadata !DIExpression()), !dbg !18 - %0 = ptrtoint i8* %x to i64, !dbg !18 + call void @llvm.dbg.value(metadata ptr %x, metadata !16, metadata !DIExpression()), !dbg !18 + %0 = ptrtoint ptr %x to i64, !dbg !18 %y = trunc i64 %0 to i32, !dbg !18 call void @llvm.dbg.value(metadata i32 %y, metadata !17, metadata !DIExpression()), !dbg !18 tail call void @fn2(i32 7), !dbg !18 diff --git a/llvm/test/DebugInfo/MIR/X86/backup-entry-values-usage.mir b/llvm/test/DebugInfo/MIR/X86/backup-entry-values-usage.mir index b7617e5b0a9a..8d7378c04887 100644 --- a/llvm/test/DebugInfo/MIR/X86/backup-entry-values-usage.mir +++ b/llvm/test/DebugInfo/MIR/X86/backup-entry-values-usage.mir @@ -36,8 +36,8 @@ define dso_local i32 @foo(i32 %param) local_unnamed_addr !dbg !8 { entry: call void @llvm.dbg.value(metadata i32 %param, metadata !13, metadata !DIExpression()), !dbg !14 - store i32 %param, i32* @side_effect, align 4, !dbg !15, !tbaa !16 - %0 = load i32, i32* @value, align 4, !dbg !20, !tbaa !16 + store i32 %param, ptr @side_effect, align 4, !dbg !15, !tbaa !16 + %0 = load i32, ptr @value, align 4, !dbg !20, !tbaa !16 call void @llvm.dbg.value(metadata i32 %0, metadata !13, metadata !DIExpression()), !dbg !14 call void @bar(i32 %0), !dbg !21 ret i32 0, !dbg !22 diff --git a/llvm/test/DebugInfo/MIR/X86/call-site-gnu-vs-dwarf5-attrs.mir b/llvm/test/DebugInfo/MIR/X86/call-site-gnu-vs-dwarf5-attrs.mir index 789968397199..1790f761585c 100644 --- a/llvm/test/DebugInfo/MIR/X86/call-site-gnu-vs-dwarf5-attrs.mir +++ b/llvm/test/DebugInfo/MIR/X86/call-site-gnu-vs-dwarf5-attrs.mir @@ -92,9 +92,9 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" ; Function Attrs: nounwind uwtable - define dso_local i32 @fn1(i32 (...)* nocapture %fn4) local_unnamed_addr !dbg !18 { + define dso_local i32 @fn1(ptr nocapture %fn4) local_unnamed_addr !dbg !18 { entry: - call void @llvm.dbg.value(metadata i32 (...)* %fn4, metadata !23, metadata !DIExpression()), !dbg !25 + call void @llvm.dbg.value(metadata ptr %fn4, metadata !23, metadata !DIExpression()), !dbg !25 tail call void (...) @fn(), !dbg !26 tail call void @fn2(i32 5), !dbg !27 %call = tail call i32 (...) %fn4(), !dbg !28 diff --git a/llvm/test/DebugInfo/MIR/X86/clobbered-fragments.mir b/llvm/test/DebugInfo/MIR/X86/clobbered-fragments.mir index c8ea384ce727..a334e99b9cad 100644 --- a/llvm/test/DebugInfo/MIR/X86/clobbered-fragments.mir +++ b/llvm/test/DebugInfo/MIR/X86/clobbered-fragments.mir @@ -33,7 +33,7 @@ ; Function Attrs: nounwind uwtable define i32 @test1() #0 !dbg !8 { entry: - %0 = load i32, i32* @global1, align 4, !dbg !16 + %0 = load i32, ptr @global1, align 4, !dbg !16 call void @llvm.dbg.value(metadata i32 %0, metadata !12, metadata !DIExpression(DW_OP_LLVM_fragment, 0, 32)), !dbg !16 call void @llvm.dbg.value(metadata i32 123, metadata !12, metadata !DIExpression(DW_OP_LLVM_fragment, 32, 32)), !dbg !16 call void @llvm.dbg.value(metadata i32 456, metadata !12, metadata !DIExpression(DW_OP_LLVM_fragment, 64, 32)), !dbg !16 @@ -46,11 +46,11 @@ ; Function Attrs: nounwind uwtable define i32 @test2() #0 !dbg !18 { entry: - %0 = load i32, i32* @global1, align 4, !dbg !20 + %0 = load i32, ptr @global1, align 4, !dbg !20 call void @llvm.dbg.value(metadata i32 %0, metadata !19, metadata !DIExpression(DW_OP_LLVM_fragment, 0, 32)), !dbg !20 - %1 = load i32, i32* @global2, align 4, !dbg !20 + %1 = load i32, ptr @global2, align 4, !dbg !20 call void @llvm.dbg.value(metadata i32 %1, metadata !19, metadata !DIExpression(DW_OP_LLVM_fragment, 32, 32)), !dbg !20 - %2 = load i32, i32* @global3, align 4, !dbg !20 + %2 = load i32, ptr @global3, align 4, !dbg !20 call void @llvm.dbg.value(metadata i32 %2, metadata !19, metadata !DIExpression(DW_OP_LLVM_fragment, 64, 32)), !dbg !20 tail call void @ext3(i32 %0, i32 %1, i32 %2) #3, !dbg !20 ret i32 %0, !dbg !21 diff --git a/llvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg-multiple-defs.mir b/llvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg-multiple-defs.mir index 4d3c466f3eb3..5c926cb50dff 100644 --- a/llvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg-multiple-defs.mir +++ b/llvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg-multiple-defs.mir @@ -36,7 +36,7 @@ entry: call void @llvm.dbg.value(metadata i32 %x, metadata !14, metadata !DIExpression()), !dbg !15 call void asm sideeffect "", "~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{dirflag},~{fpsr},~{flags}"(), !dbg !16, !srcloc !17 - %0 = load i32, i32* @y, align 4, !dbg !18 + %0 = load i32, ptr @y, align 4, !dbg !18 %rem = srem i32 %x, %0, !dbg !18 call void @llvm.dbg.value(metadata i32 %rem, metadata !14, metadata !DIExpression()), !dbg !15 call void @callee(i32 %rem), !dbg !18 diff --git a/llvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg.mir b/llvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg.mir index 62d091bbce53..8ede60c33359 100644 --- a/llvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg.mir +++ b/llvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg.mir @@ -45,7 +45,7 @@ declare void @llvm.dbg.value(metadata, metadata, metadata) ; Function Attrs: nounwind - declare void @llvm.stackprotector(i8*, i8**) + declare void @llvm.stackprotector(ptr, ptr) attributes #0 = { "disable-tail-calls"="true" "frame-pointer"="all" } diff --git a/llvm/test/DebugInfo/MIR/X86/dbg-stack-value-range.mir b/llvm/test/DebugInfo/MIR/X86/dbg-stack-value-range.mir index 8254b81c2204..876393557cc9 100644 --- a/llvm/test/DebugInfo/MIR/X86/dbg-stack-value-range.mir +++ b/llvm/test/DebugInfo/MIR/X86/dbg-stack-value-range.mir @@ -45,8 +45,8 @@ entry: %local1 = alloca i32, align 4 call void @llvm.dbg.value(metadata i32 %X, metadata !12, metadata !DIExpression()), !dbg !15 - %0 = bitcast i32* %local1 to i8*, !dbg !15 - call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %0), !dbg !15 + %0 = bitcast ptr %local1 to ptr, !dbg !15 + call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %0), !dbg !15 call void @llvm.dbg.value(metadata i32 5, metadata !14, metadata !DIExpression()), !dbg !15 %call = tail call i32 (...) @check(), !dbg !15 %tobool = icmp eq i32 %call, 0, !dbg !15 @@ -54,45 +54,45 @@ if.then: ; preds = %entry call void @llvm.dbg.value(metadata i32 4, metadata !13, metadata !DIExpression()), !dbg !15 - store i32 4, i32* %local1, align 4, !dbg !15, !tbaa !16 - call void @llvm.dbg.value(metadata i32* %local1, metadata !13, metadata !DIExpression(DW_OP_deref)), !dbg !15 - %call1 = call i32 @init(i32* nonnull %local1), !dbg !15 + store i32 4, ptr %local1, align 4, !dbg !15, !tbaa !16 + call void @llvm.dbg.value(metadata ptr %local1, metadata !13, metadata !DIExpression(DW_OP_deref)), !dbg !15 + %call1 = call i32 @init(ptr nonnull %local1), !dbg !15 call void @llvm.dbg.value(metadata i32 undef, metadata !14, metadata !DIExpression()), !dbg !15 br label %if.end, !dbg !15 if.else: ; preds = %entry call void @llvm.dbg.value(metadata i32 5, metadata !13, metadata !DIExpression()), !dbg !15 - store i32 5, i32* %local1, align 4, !dbg !15, !tbaa !16 + store i32 5, ptr %local1, align 4, !dbg !15, !tbaa !16 br label %if.end if.end: ; preds = %if.else, %if.then - %1 = bitcast i32* %local1 to i8*, !dbg !15 + %1 = bitcast ptr %local1 to ptr, !dbg !15 call void @llvm.dbg.value(metadata i32 undef, metadata !14, metadata !DIExpression()), !dbg !15 %call2 = call i32 (...) @init2(), !dbg !15 call void @llvm.dbg.value(metadata i32 undef, metadata !14, metadata !DIExpression()), !dbg !15 - %2 = load i32, i32* %local1, align 4, !dbg !15, !tbaa !16 + %2 = load i32, ptr %local1, align 4, !dbg !15, !tbaa !16 call void @llvm.dbg.value(metadata i32 %2, metadata !13, metadata !DIExpression()), !dbg !15 - call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %1), !dbg !15 + call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %1), !dbg !15 ret i32 %2, !dbg !15 } ; Function Attrs: argmemonly nounwind - declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) + declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) declare dso_local i32 @check(...) local_unnamed_addr - declare dso_local i32 @init(i32*) local_unnamed_addr + declare dso_local i32 @init(ptr) local_unnamed_addr declare dso_local i32 @init2(...) local_unnamed_addr ; Function Attrs: argmemonly nounwind - declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) + declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) ; Function Attrs: nounwind readnone speculatable declare void @llvm.dbg.value(metadata, metadata, metadata) ; Function Attrs: nounwind - declare void @llvm.stackprotector(i8*, i8**) + declare void @llvm.stackprotector(ptr, ptr) attributes #0 = { nounwind uwtable "frame-pointer"="non-leaf" } diff --git a/llvm/test/DebugInfo/MIR/X86/dbgcall-site-interpretation.mir b/llvm/test/DebugInfo/MIR/X86/dbgcall-site-interpretation.mir index a6f64f6f3b24..9f18dd04c467 100644 --- a/llvm/test/DebugInfo/MIR/X86/dbgcall-site-interpretation.mir +++ b/llvm/test/DebugInfo/MIR/X86/dbgcall-site-interpretation.mir @@ -51,14 +51,14 @@ call void @llvm.dbg.value(metadata i32 %arg1, metadata !14, metadata !DIExpression()), !dbg !21 call void @llvm.dbg.value(metadata i32 %arg2, metadata !15, metadata !DIExpression()), !dbg !21 call void @llvm.dbg.value(metadata i32 %arg3, metadata !16, metadata !DIExpression()), !dbg !21 - store i32 %arg3, i32* %arg3.addr, align 4 + store i32 %arg3, ptr %arg3.addr, align 4 call void @llvm.dbg.value(metadata i32 %arg4, metadata !17, metadata !DIExpression()), !dbg !21 - %0 = bitcast i32* %local2 to i8*, !dbg !21 - call void @llvm.dbg.value(metadata i32* %arg3.addr, metadata !16, metadata !DIExpression(DW_OP_deref)), !dbg !21 - %call = call i32 @foo(i32 %arg1, i32 %arg2, i32* nonnull %arg3.addr, i32 %arg4), !dbg !21 + %0 = bitcast ptr %local2 to ptr, !dbg !21 + call void @llvm.dbg.value(metadata ptr %arg3.addr, metadata !16, metadata !DIExpression(DW_OP_deref)), !dbg !21 + %call = call i32 @foo(i32 %arg1, i32 %arg2, ptr nonnull %arg3.addr, i32 %arg4), !dbg !21 call void @llvm.dbg.value(metadata i32 %call, metadata !18, metadata !DIExpression()), !dbg !21 %cmp = icmp sgt i32 %arg1, %arg2, !dbg !21 - %1 = load i32, i32* %arg3.addr, align 4, !dbg !21 + %1 = load i32, ptr %arg3.addr, align 4, !dbg !21 call void @llvm.dbg.value(metadata i32 %1, metadata !16, metadata !DIExpression()), !dbg !21 %add = add nsw i32 %1, %arg1, !dbg !21 %add1 = add nsw i32 %arg4, %arg2, !dbg !21 @@ -70,19 +70,19 @@ %add3 = add nsw i32 %1, %arg4, !dbg !21 %storemerge = select i1 %tobool, i32 %mul, i32 %add3, !dbg !21 call void @llvm.dbg.value(metadata i32 %storemerge, metadata !19, metadata !DIExpression()), !dbg !21 - store i32 %storemerge, i32* %local2, align 4, !dbg !21 + store i32 %storemerge, ptr %local2, align 4, !dbg !21 %cmp6 = icmp slt i32 %storemerge, %arg4, !dbg !21 %local3.0.v = select i1 %cmp6, i32 %local1.0, i32 %arg1, !dbg !21 %local3.0 = mul nsw i32 %local3.0.v, %storemerge, !dbg !21 call void @llvm.dbg.value(metadata i32 %local3.0, metadata !20, metadata !DIExpression()), !dbg !21 - call void @llvm.dbg.value(metadata i32* %local2, metadata !19, metadata !DIExpression(DW_OP_deref)), !dbg !21 - %call12 = call i32 @foo(i32 %local1.0, i32 4, i32* nonnull %local2, i32 %local3.0), !dbg !21 + call void @llvm.dbg.value(metadata ptr %local2, metadata !19, metadata !DIExpression(DW_OP_deref)), !dbg !21 + %call12 = call i32 @foo(i32 %local1.0, i32 4, ptr nonnull %local2, i32 %local3.0), !dbg !21 call void @llvm.dbg.value(metadata i32 %call12, metadata !14, metadata !DIExpression()), !dbg !21 %add13 = add nsw i32 %call12, 4, !dbg !21 ret i32 %add13, !dbg !21 } - declare !dbg !4 dso_local i32 @foo(i32, i32, i32*, i32) local_unnamed_addr + declare !dbg !4 dso_local i32 @foo(i32, i32, ptr, i32) local_unnamed_addr ; Function Attrs: nounwind readnone speculatable declare void @llvm.dbg.value(metadata, metadata, metadata) diff --git a/llvm/test/DebugInfo/MIR/X86/dbgcall-site-lea-interpretation.mir b/llvm/test/DebugInfo/MIR/X86/dbgcall-site-lea-interpretation.mir index f6f746e47005..44b45e67a8f4 100644 --- a/llvm/test/DebugInfo/MIR/X86/dbgcall-site-lea-interpretation.mir +++ b/llvm/test/DebugInfo/MIR/X86/dbgcall-site-lea-interpretation.mir @@ -44,25 +44,25 @@ %arg1.addr = alloca i32, align 4 %arg3.addr = alloca i32, align 4 %local1 = alloca i32, align 4 - store i32 %arg1, i32* %arg1.addr, align 4 - store i32 %arg3, i32* %arg3.addr, align 4 - %0 = bitcast i32* %local1 to i8*, !dbg !14 + store i32 %arg1, ptr %arg1.addr, align 4 + store i32 %arg3, ptr %arg3.addr, align 4 + %0 = bitcast ptr %local1 to ptr, !dbg !14 %mul = mul nsw i32 %arg3, %arg1, !dbg !14 - store i32 %mul, i32* %local1, align 4, !dbg !14 + store i32 %mul, ptr %local1, align 4, !dbg !14 %add = add nsw i32 %arg2, %arg1, !dbg !14 %sub = sub nsw i32 %add, %arg3, !dbg !14 - %call = call i32 @foo(i32 %mul, i32 %sub, i32* nonnull %local1, i32* nonnull %arg1.addr, i32* nonnull %arg3.addr, i32 %add), !dbg !14 - %1 = load i32, i32* %local1, align 4, !dbg !14 + %call = call i32 @foo(i32 %mul, i32 %sub, ptr nonnull %local1, ptr nonnull %arg1.addr, ptr nonnull %arg3.addr, i32 %add), !dbg !14 + %1 = load i32, ptr %local1, align 4, !dbg !14 %add2 = add nsw i32 %1, %call, !dbg !14 - store i32 %add2, i32* %local1, align 4, !dbg !14 - %call3 = call i32 @foo2(i32* nonnull %local1), !dbg !14 - %2 = load i32, i32* %local1, align 4, !dbg !14 + store i32 %add2, ptr %local1, align 4, !dbg !14 + %call3 = call i32 @foo2(ptr nonnull %local1), !dbg !14 + %2 = load i32, ptr %local1, align 4, !dbg !14 ret i32 %2, !dbg !14 } - declare !dbg !4 dso_local i32 @foo(i32, i32, i32*, i32*, i32*, i32) local_unnamed_addr + declare !dbg !4 dso_local i32 @foo(i32, i32, ptr, ptr, ptr, i32) local_unnamed_addr - declare !dbg !5 dso_local i32 @foo2(i32*) local_unnamed_addr + declare !dbg !5 dso_local i32 @foo2(ptr) local_unnamed_addr !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!6, !7, !8} diff --git a/llvm/test/DebugInfo/MIR/X86/dbgcall-site-reference.mir b/llvm/test/DebugInfo/MIR/X86/dbgcall-site-reference.mir index 6b753bf11f16..31f607d9db23 100644 --- a/llvm/test/DebugInfo/MIR/X86/dbgcall-site-reference.mir +++ b/llvm/test/DebugInfo/MIR/X86/dbgcall-site-reference.mir @@ -29,22 +29,22 @@ %struct.A = type { i8 } %struct.C = type { i8 } - @_ZN1DC1E1B = dso_local unnamed_addr alias void (%struct.D*, %struct.B*), void (%struct.D*, %struct.B*)* @_ZN1DC2E1B + @_ZN1DC1E1B = dso_local unnamed_addr alias void (ptr, ptr), ptr @_ZN1DC2E1B ; Function Attrs: uwtable - define dso_local void @_ZN1DC2E1B(%struct.D* %this, %struct.B* nocapture readnone %b) unnamed_addr #0 align 2 !dbg !7 { + define dso_local void @_ZN1DC2E1B(ptr %this, ptr nocapture readnone %b) unnamed_addr #0 align 2 !dbg !7 { entry: %agg.tmp = alloca %struct.B, align 1 - call void @llvm.dbg.value(metadata %struct.D* %this, metadata !32, metadata !DIExpression()), !dbg !35 - call void @llvm.dbg.declare(metadata %struct.B* %b, metadata !34, metadata !DIExpression()), !dbg !36 - %0 = bitcast %struct.D* %this to %struct.C*, !dbg !36 - call void @_ZN1CC2E1B(%struct.C* %0, %struct.B* nonnull %agg.tmp), !dbg !36 + call void @llvm.dbg.value(metadata ptr %this, metadata !32, metadata !DIExpression()), !dbg !35 + call void @llvm.dbg.declare(metadata ptr %b, metadata !34, metadata !DIExpression()), !dbg !36 + %0 = bitcast ptr %this to ptr, !dbg !36 + call void @_ZN1CC2E1B(ptr %0, ptr nonnull %agg.tmp), !dbg !36 ret void, !dbg !36 } ; Function Attrs: nounwind readnone speculatable willreturn declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 - declare dso_local void @_ZN1CC2E1B(%struct.C*, %struct.B*) unnamed_addr + declare dso_local void @_ZN1CC2E1B(ptr, ptr) unnamed_addr ; Function Attrs: nounwind readnone speculatable willreturn declare void @llvm.dbg.value(metadata, metadata, metadata) #1 diff --git a/llvm/test/DebugInfo/MIR/X86/dbgcall-site-two-fwd-reg-defs.mir b/llvm/test/DebugInfo/MIR/X86/dbgcall-site-two-fwd-reg-defs.mir index 01b61913fd65..b2e4d96cf440 100644 --- a/llvm/test/DebugInfo/MIR/X86/dbgcall-site-two-fwd-reg-defs.mir +++ b/llvm/test/DebugInfo/MIR/X86/dbgcall-site-two-fwd-reg-defs.mir @@ -26,17 +26,17 @@ ; Function Attrs: noinline norecurse nounwind readonly define i32 @e() #0 !dbg !13 { entry: - %0 = load i32, i32* @a, align 4, !dbg !16 + %0 = load i32, ptr @a, align 4, !dbg !16 ret i32 %0, !dbg !16 } ; Function Attrs: noinline nounwind define i32 @main() #1 !dbg !17 { entry: - %0 = load i32, i32* @c, align 4, !dbg !19 - store i32 %0, i32* @d, align 4, !dbg !19 + %0 = load i32, ptr @c, align 4, !dbg !19 + store i32 %0, ptr @d, align 4, !dbg !19 %call = tail call i32 @e(), !dbg !20 - store i32 %call, i32* @b, align 4, !dbg !20 + store i32 %call, ptr @b, align 4, !dbg !20 %conv = sext i32 %0 to i64, !dbg !21 tail call void @call(i64 %conv, i32 %0), !dbg !21 ret i32 0, !dbg !22 diff --git a/llvm/test/DebugInfo/MIR/X86/debug-call-site-param.mir b/llvm/test/DebugInfo/MIR/X86/debug-call-site-param.mir index 0b2110b12a9d..26e66ae13ce5 100644 --- a/llvm/test/DebugInfo/MIR/X86/debug-call-site-param.mir +++ b/llvm/test/DebugInfo/MIR/X86/debug-call-site-param.mir @@ -83,20 +83,20 @@ call void @llvm.dbg.value(metadata i32 %arg1, metadata !15, metadata !DIExpression()), !dbg !19 call void @llvm.dbg.value(metadata i32 %arg2, metadata !16, metadata !DIExpression()), !dbg !20 call void @llvm.dbg.value(metadata i32 %arg3, metadata !17, metadata !DIExpression()), !dbg !21 - %0 = bitcast i32* %local1 to i8*, !dbg !22 + %0 = bitcast ptr %local1 to ptr, !dbg !22 %call = tail call i32 (...) @getVal(), !dbg !23 call void @llvm.dbg.value(metadata i32 %call, metadata !18, metadata !DIExpression()), !dbg !24 - store i32 %call, i32* %local1, align 4, !dbg !24 + store i32 %call, ptr %local1, align 4, !dbg !24 %add = add nsw i32 %arg3, 3, !dbg !24 %add1 = add nsw i32 %arg2, %arg1, !dbg !24 - call void @llvm.dbg.value(metadata i32* %local1, metadata !18, metadata !DIExpression(DW_OP_deref)), !dbg !24 - call void @foo(i32* nonnull %local1, i32 %arg2, i32 10, i32 15, i32 %add, i32 %add1), !dbg !24 + call void @llvm.dbg.value(metadata ptr %local1, metadata !18, metadata !DIExpression(DW_OP_deref)), !dbg !24 + call void @foo(ptr nonnull %local1, i32 %arg2, i32 10, i32 15, i32 %add, i32 %add1), !dbg !24 ret void, !dbg !24 } declare !dbg !4 dso_local i32 @getVal(...) local_unnamed_addr - declare !dbg !5 dso_local void @foo(i32*, i32, i32, i32, i32, i32) local_unnamed_addr + declare !dbg !5 dso_local void @foo(ptr, i32, i32, i32, i32, i32) local_unnamed_addr ; Function Attrs: nounwind readnone speculatable declare void @llvm.dbg.value(metadata, metadata, metadata) diff --git a/llvm/test/DebugInfo/MIR/X86/debug-entry-value-operation.mir b/llvm/test/DebugInfo/MIR/X86/debug-entry-value-operation.mir index a051aaa5f7ad..ae0160e75b4a 100644 --- a/llvm/test/DebugInfo/MIR/X86/debug-entry-value-operation.mir +++ b/llvm/test/DebugInfo/MIR/X86/debug-entry-value-operation.mir @@ -36,7 +36,7 @@ call void @llvm.dbg.value(metadata i32 %q, metadata !16, metadata !DIExpression()), !dbg !18 call void @llvm.dbg.value(metadata i32 %r, metadata !17, metadata !DIExpression()), !dbg !18 %add = add nsw i32 %p, 1, !dbg !18 - store i32 %add, i32* @global, align 4, !dbg !18 + store i32 %add, ptr @global, align 4, !dbg !18 tail call void asm sideeffect "", "~{edi},~{esi},~{edx},~{dirflag},~{fpsr},~{flags}"(), !dbg !18, !srcloc !19 ret i32 123, !dbg !18 } diff --git a/llvm/test/DebugInfo/MIR/X86/debug-loc-0.mir b/llvm/test/DebugInfo/MIR/X86/debug-loc-0.mir index edde1b36c423..56a4d835aaa5 100644 --- a/llvm/test/DebugInfo/MIR/X86/debug-loc-0.mir +++ b/llvm/test/DebugInfo/MIR/X86/debug-loc-0.mir @@ -14,25 +14,25 @@ target triple = "x86_64-apple-macosx10.9.0" %swift.opaque = type opaque - %swift.metadata_response = type { %swift.type*, i64 } + %swift.metadata_response = type { ptr, i64 } %swift.type = type { i64 } define hidden swiftcc void @"$S4main1fyyF"() !dbg !5 { entry: - %s1.addr = alloca i8*, align 8 - %0 = bitcast i8** %s1.addr to %swift.opaque** - store %swift.opaque* null, %swift.opaque** %0, align 8 + %s1.addr = alloca ptr, align 8 + %0 = bitcast ptr %s1.addr to ptr + store ptr null, ptr %0, align 8 %1 = call swiftcc %swift.metadata_response @"$S16resilient_struct4SizeVMa"(i64 0) #1, !dbg !10 %2 = extractvalue %swift.metadata_response %1, 0, !dbg !10 - %3 = bitcast %swift.type* %2 to i8***, !dbg !10 - %4 = getelementptr inbounds i8**, i8*** %3, i64 -1, !dbg !10 + %3 = bitcast ptr %2 to ptr, !dbg !10 + %4 = getelementptr inbounds ptr, ptr %3, i64 -1, !dbg !10 ret void, !dbg !12 } declare swiftcc %swift.metadata_response @"$S16resilient_struct4SizeVMa"(i64) ; Function Attrs: nounwind - declare void @llvm.stackprotector(i8*, i8**) #0 + declare void @llvm.stackprotector(ptr, ptr) #0 attributes #0 = { nounwind } attributes #1 = { nounwind readnone } diff --git a/llvm/test/DebugInfo/MIR/X86/dvl-livedebugvars-movements.mir b/llvm/test/DebugInfo/MIR/X86/dvl-livedebugvars-movements.mir index 42f8bc256428..20536b674390 100644 --- a/llvm/test/DebugInfo/MIR/X86/dvl-livedebugvars-movements.mir +++ b/llvm/test/DebugInfo/MIR/X86/dvl-livedebugvars-movements.mir @@ -27,10 +27,10 @@ %struct.a = type { i32 } ; Function Attrs: nounwind ssp - define i32 @bar(%struct.a* nocapture %b, i32 %shoes) !dbg !4 { + define i32 @bar(ptr nocapture %b, i32 %shoes) !dbg !4 { entry: tail call void @llvm.dbg.value(metadata i32 %shoes, metadata !9, metadata !DIExpression()), !dbg !16 - %tmp1 = getelementptr inbounds %struct.a, %struct.a* %b, i64 0, i32 0, !dbg !17 + %tmp1 = getelementptr inbounds %struct.a, ptr %b, i64 0, i32 0, !dbg !17 br label %bb3 bb1: ; preds = %bb2 @@ -44,7 +44,7 @@ br label %bb1 bb3: ; preds = %entry - %tmp2 = load i32, i32* %tmp1, align 4, !dbg !17 + %tmp2 = load i32, ptr %tmp1, align 4, !dbg !17 br label %bb2 exit: ; preds = %bb1 diff --git a/llvm/test/DebugInfo/MIR/X86/dvl-livedebugvars-stackptr.mir b/llvm/test/DebugInfo/MIR/X86/dvl-livedebugvars-stackptr.mir index aeadd5bd2b4f..363ef4395eaf 100644 --- a/llvm/test/DebugInfo/MIR/X86/dvl-livedebugvars-stackptr.mir +++ b/llvm/test/DebugInfo/MIR/X86/dvl-livedebugvars-stackptr.mir @@ -26,11 +26,11 @@ %struct.a = type { i32 } ; Function Attrs: nounwind ssp - define i32 @bar(%struct.a* nocapture %b, i32 %shoes) !dbg !4 { + define i32 @bar(ptr nocapture %b, i32 %shoes) !dbg !4 { entry: %local1 = alloca i64 tail call void @llvm.dbg.value(metadata i32 %shoes, metadata !9, metadata !DIExpression()), !dbg !16 - %tmp1 = getelementptr inbounds %struct.a, %struct.a* %b, i64 0, i32 0, !dbg !17 + %tmp1 = getelementptr inbounds %struct.a, ptr %b, i64 0, i32 0, !dbg !17 br label %bb3 bb1: ; preds = %bb2 @@ -44,7 +44,7 @@ br label %bb1 bb3: ; preds = %entry - %tmp2 = load i32, i32* %tmp1, align 4, !dbg !17 + %tmp2 = load i32, ptr %tmp1, align 4, !dbg !17 br label %bb2 exit: ; preds = %bb1 diff --git a/llvm/test/DebugInfo/MIR/X86/empty-inline.mir b/llvm/test/DebugInfo/MIR/X86/empty-inline.mir index ae843ac3bd33..695b7c60365b 100644 --- a/llvm/test/DebugInfo/MIR/X86/empty-inline.mir +++ b/llvm/test/DebugInfo/MIR/X86/empty-inline.mir @@ -25,27 +25,27 @@ %class.D = type { %class.B } %class.B = type { %class.A, %class.A } %class.A = type { i8 } - %class.C = type <{ %class.E*, %class.B, [2 x i8] }> + %class.C = type <{ ptr, %class.B, [2 x i8] }> - @a = local_unnamed_addr global %class.E* null, align 4 + @a = local_unnamed_addr global ptr null, align 4 - define i32 @_ZN1C5m_fn3Ev(%class.C* nocapture) local_unnamed_addr align 2 !dbg !6 { + define i32 @_ZN1C5m_fn3Ev(ptr nocapture) local_unnamed_addr align 2 !dbg !6 { %2 = alloca %class.B, align 1 - %3 = load %class.E*, %class.E** @a, align 4 - %4 = icmp eq %class.E* %3, null + %3 = load ptr, ptr @a, align 4 + %4 = icmp eq ptr %3, null br i1 %4, label %10, label %5 ;